[PATCH v4] riscv: probes: simulate c.jal instruction

[PATCH v4] riscv: probes: simulate c.jal instruction

[Xiaofeng Yuan]

The c.jal instruction is currently marked REJECTED in kprobes
instruction decoding, but it should be SIMULATED like other
compressed jump instructions.

Add simulate_c_jal() which saves the return address to RA and
sets the program counter to the target offset, reusing
simulate_c_j for the common jump logic.

Signed-off-by: Xiaofeng Yuan <xiaofengmian@163.com>
---
v3: fixed diff (v2 had wrong diff)
v4: use regs->ra directly; move SET_SIMULATE to group with others (per Nam Cao's review)

 arch/riscv/kernel/probes/decode-insn.c   | 2 +-
 arch/riscv/kernel/probes/simulate-insn.c | 7 +++++++
 arch/riscv/kernel/probes/simulate-insn.h | 1 +
 3 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/arch/riscv/kernel/probes/decode-insn.c b/arch/riscv/kernel/probes/decode-insn.c
index 65d9590bf..433d9035b 100644
--- a/arch/riscv/kernel/probes/decode-insn.c
+++ b/arch/riscv/kernel/probes/decode-insn.c
@@ -29,12 +29,12 @@ riscv_probe_decode_insn(probe_opcode_t *addr, struct arch_probe_insn *api)
 	 * TODO: the REJECTED ones below need to be implemented
 	 */
 #ifdef CONFIG_RISCV_ISA_C
-	RISCV_INSN_REJECTED(c_jal,		insn);
 	RISCV_INSN_REJECTED(c_ebreak,		insn);
 
 	RISCV_INSN_SET_SIMULATE(c_j,		insn);
 	RISCV_INSN_SET_SIMULATE(c_jr,		insn);
 	RISCV_INSN_SET_SIMULATE(c_jalr,		insn);
+	RISCV_INSN_SET_SIMULATE(c_jal,		insn);
 	RISCV_INSN_SET_SIMULATE(c_beqz,		insn);
 	RISCV_INSN_SET_SIMULATE(c_bnez,		insn);
 #endif
diff --git a/arch/riscv/kernel/probes/simulate-insn.c b/arch/riscv/kernel/probes/simulate-insn.c
index fa581590c..f8a2f6857 100644
--- a/arch/riscv/kernel/probes/simulate-insn.c
+++ b/arch/riscv/kernel/probes/simulate-insn.c
@@ -163,6 +163,13 @@ bool __kprobes simulate_c_j(u32 opcode, unsigned long addr, struct pt_regs *regs
 	return true;
 }
 
+bool __kprobes simulate_c_jal(u32 opcode, unsigned long addr, struct pt_regs *regs)
+{
+	regs->ra = addr + 2;
+
+	return simulate_c_j(opcode, addr, regs);
+}
+
 static bool __kprobes simulate_c_jr_jalr(u32 opcode, unsigned long addr, struct pt_regs *regs,
 					 bool is_jalr)
 {
diff --git a/arch/riscv/kernel/probes/simulate-insn.h b/arch/riscv/kernel/probes/simulate-insn.h
index 44ebbc444..b89e1bb01 100644
--- a/arch/riscv/kernel/probes/simulate-insn.h
+++ b/arch/riscv/kernel/probes/simulate-insn.h
@@ -25,6 +25,7 @@ bool simulate_branch(u32 opcode, unsigned long addr, struct pt_regs *regs);
 bool simulate_jal(u32 opcode, unsigned long addr, struct pt_regs *regs);
 bool simulate_jalr(u32 opcode, unsigned long addr, struct pt_regs *regs);
 bool simulate_c_j(u32 opcode, unsigned long addr, struct pt_regs *regs);
+bool simulate_c_jal(u32 opcode, unsigned long addr, struct pt_regs *regs);
 bool simulate_c_jr(u32 opcode, unsigned long addr, struct pt_regs *regs);
 bool simulate_c_jalr(u32 opcode, unsigned long addr, struct pt_regs *regs);
 bool simulate_c_bnez(u32 opcode, unsigned long addr, struct pt_regs *regs);
-- 
2.43.0

Re: [PATCH v4] riscv: probes: simulate c.jal instruction

[Charlie Jenkins]

On Sat, 27 Jun 2026 00:19:39 +0000, Xiaofeng Yuan <xiaofengmian@163.com> wrote:
> The c.jal instruction is currently marked REJECTED in kprobes
> instruction decoding, but it should be SIMULATED like other
> compressed jump instructions.
> 
> Add simulate_c_jal() which saves the return address to RA and
> sets the program counter to the target offset, reusing
> simulate_c_j for the common jump logic.

I was looking at this recently trying to figure out why this hadn't been
implemented and couldn't determine why this one was special, it might be
because it is 32-bit only. Since it is 32-bit only, can you put ifdefs
around it for riscv32 (#if __riscv_xlen == 32) ?

Can you also add a test case to:
arch/riscv/kernel/tests/kprobes/test-kprobes-asm.S?

- Charlie

-- 
- Charlie

Re: [PATCH v4] riscv: probes: simulate c.jal instruction

[Nam Cao]

Charlie Jenkins <thecharlesjenkins@gmail.com> writes:
> I was looking at this recently trying to figure out why this hadn't been
> implemented and couldn't determine why this one was special, it might be
> because it is 32-bit only.

Yes. When I looked into this, I had no idea how to test rv32, so I skipped it.

> Since it is 32-bit only, can you put ifdefs
> around it for riscv32 (#if __riscv_xlen == 32) ?

Except for slightly bigger kernel size, it does not hurt to keep. And
#if stuff is quite ugly. But I'm fine with it either way.

> Can you also add a test case to:
> arch/riscv/kernel/tests/kprobes/test-kprobes-asm.S?

I already have a patch adding test case. Let me send it.

Nam

Re: [PATCH v4] riscv: probes: simulate c.jal instruction

[Nam Cao]

Xiaofeng Yuan <xiaofengmian@163.com> writes:
> The c.jal instruction is currently marked REJECTED in kprobes
> instruction decoding, but it should be SIMULATED like other
> compressed jump instructions.
>
> Add simulate_c_jal() which saves the return address to RA and
> sets the program counter to the target offset, reusing
> simulate_c_j for the common jump logic.
>
> Signed-off-by: Xiaofeng Yuan <xiaofengmian@163.com>

Reviewed-by: Nam Cao <namcao@linutronix.de>
Tested-by: Nam Cao <namcao@linutronix.de>

Re: [PATCH v4] riscv: probes: simulate c.jal instruction

[Nam Cao]

Nam Cao <namcao@linutronix.de> writes:
> Charlie Jenkins <thecharlesjenkins@gmail.com> writes:
>> Can you also add a test case to:
>> arch/riscv/kernel/tests/kprobes/test-kprobes-asm.S?
>
> I already have a patch adding test case. Let me send it.

I screwed up and didn't cc you two. But here it is:
https://lore.kernel.org/lkml/20260627115051.3235783-1-namcao@linutronix.de/

Nam