* [PATCH 0/6] ISA based RISC-V tune implementation
@ 2025-06-16 2:29 Mark Hatle
2025-06-16 2:29 ` [PATCH 1/6] riscv tunes: ISA Implementation of RISC-V tune features Mark Hatle
` (6 more replies)
0 siblings, 7 replies; 15+ messages in thread
From: Mark Hatle @ 2025-06-16 2:29 UTC (permalink / raw)
To: openembedded-core
From: Mark Hatle <mark.hatle@amd.com>
The following implements the risc-v processor tune based on the ISA approach
as documented in the oe-architecture post:
https://lists.openembedded.org/g/openembedded-architecture/message/2155
This set also attempts to make u-boot and kernel configurations dynamic
based on the TUNE_FEATURES.
For the linux-yocto, I suspect that the config fragments should be
sent to the kmeta (kernel-cache), but I'd like a review from Bruce and
others before I do this.
Additionally, this enables a new (optional) features_check for TUNE_FEATURES.
I've found numerous items in the system have certain RISC-V ISA expectations
that may need to be addressed over time, however the obvious one is the
Linux kernel requires ima_zicsr_zifencei. Since it has it's own -march=
setting this will ensure the processor defintion will be compatible.
Also dynamically configure the QEMU cpu based on the tune_features. This
is nice to ensure that what we're actually building should be able to run
on real hardware. However, it does highlight some of the (extension)
limitations in the current design. (limitations as in extension not yet
enabled.)
Note: OpenSBI _requires_ the 'c' extension or it will not execute. I
suspect this can be fixed, but it's beyond my capabilities at this time.
Mark Hatle (6):
riscv tunes: ISA Implementation of RISC-V tune features
linux-yocto: Enable risc-v TUNE_FEATURES ISA selections
u-boot: Dynamic RISC-V ISA configuration
qemuriscv: Dynamically configure qemu CPU
features_check.bbclass: Add support for required TUNE_FEATURES
linux-yocto.inc: State riscv required tune_features
meta/classes-recipe/features_check.bbclass | 2 +-
meta/conf/machine/include/riscv/README | 122 ++++++++++++++++
.../conf/machine/include/riscv/arch-riscv.inc | 138 +++++++++++++++++-
meta/conf/machine/include/riscv/qemuriscv.inc | 31 +++-
.../conf/machine/include/riscv/tune-riscv.inc | 40 ++---
meta/conf/machine/qemuriscv32.conf | 4 +-
meta/lib/oe/__init__.py | 2 +-
meta/lib/oe/tune.py | 81 ++++++++++
.../u-boot/files/u-boot-riscv-isa_a.cfg | 1 +
.../u-boot/files/u-boot-riscv-isa_c.cfg | 1 +
.../u-boot/files/u-boot-riscv-isa_clear.cfg | 6 +
.../u-boot/files/u-boot-riscv-isa_d.cfg | 1 +
.../u-boot/files/u-boot-riscv-isa_f.cfg | 1 +
.../u-boot/files/u-boot-riscv-isa_zbb.cfg | 1 +
.../u-boot/files/u-boot-riscv-isa_zicbom.cfg | 1 +
meta/recipes-bsp/u-boot/u-boot-common.inc | 12 ++
.../linux/files/risc-v-isa-c.cfg | 1 +
.../linux/files/risc-v-isa-clear.cfg | 9 ++
.../linux/files/risc-v-isa-fpu.cfg | 1 +
.../linux/files/risc-v-isa-rv32i.cfg | 2 +
.../linux/files/risc-v-isa-rv64i.cfg | 2 +
.../linux/files/risc-v-isa-v.cfg | 1 +
.../linux/files/risc-v-isa-zbb.cfg | 1 +
.../linux/files/risc-v-isa-zicbom.cfg | 1 +
meta/recipes-kernel/linux/linux-yocto.inc | 19 +++
25 files changed, 439 insertions(+), 42 deletions(-)
create mode 100644 meta/conf/machine/include/riscv/README
create mode 100644 meta/lib/oe/tune.py
create mode 100644 meta/recipes-bsp/u-boot/files/u-boot-riscv-isa_a.cfg
create mode 100644 meta/recipes-bsp/u-boot/files/u-boot-riscv-isa_c.cfg
create mode 100644 meta/recipes-bsp/u-boot/files/u-boot-riscv-isa_clear.cfg
create mode 100644 meta/recipes-bsp/u-boot/files/u-boot-riscv-isa_d.cfg
create mode 100644 meta/recipes-bsp/u-boot/files/u-boot-riscv-isa_f.cfg
create mode 100644 meta/recipes-bsp/u-boot/files/u-boot-riscv-isa_zbb.cfg
create mode 100644 meta/recipes-bsp/u-boot/files/u-boot-riscv-isa_zicbom.cfg
create mode 100644 meta/recipes-kernel/linux/files/risc-v-isa-c.cfg
create mode 100644 meta/recipes-kernel/linux/files/risc-v-isa-clear.cfg
create mode 100644 meta/recipes-kernel/linux/files/risc-v-isa-fpu.cfg
create mode 100644 meta/recipes-kernel/linux/files/risc-v-isa-rv32i.cfg
create mode 100644 meta/recipes-kernel/linux/files/risc-v-isa-rv64i.cfg
create mode 100644 meta/recipes-kernel/linux/files/risc-v-isa-v.cfg
create mode 100644 meta/recipes-kernel/linux/files/risc-v-isa-zbb.cfg
create mode 100644 meta/recipes-kernel/linux/files/risc-v-isa-zicbom.cfg
--
2.34.1
^ permalink raw reply [flat|nested] 15+ messages in thread* [PATCH 1/6] riscv tunes: ISA Implementation of RISC-V tune features 2025-06-16 2:29 [PATCH 0/6] ISA based RISC-V tune implementation Mark Hatle @ 2025-06-16 2:29 ` Mark Hatle 2025-06-16 10:11 ` [OE-core] " Richard Purdie 2025-06-16 2:29 ` [PATCH 2/6] linux-yocto: Enable risc-v TUNE_FEATURES ISA selections Mark Hatle ` (5 subsequent siblings) 6 siblings, 1 reply; 15+ messages in thread From: Mark Hatle @ 2025-06-16 2:29 UTC (permalink / raw) To: openembedded-core From: Mark Hatle <mark.hatle@amd.com> This implements the following base ISAs: * rv32i, rv64i * rv32e, rv64i The following ABIs: * ilp32, ilp32e, ilp32f, ilp32d * lp64, lp64e, lp64f, lp64d The following ISA extension are also implemented: * M - Integer Multiplication and Division Extension * A - Atomic Memory Extension * F - Single-Precision Floating-Point Extension * D - Double-Precision Floating-Point Extension * C - Compressed Extension * B - Bit Manipulation Extension (implies Zba, Zbb, Zbs) * V - Vector Operations Extension * Zicsr - Control and Status Register Access Extension * Zifencei - Instruction-Fetch Fence Extension * Zba - Address bit manipulation extension * Zbb - Basic bit manipulation extension * Zbc - Carry-less multiplication extension * Zbs - Single-bit manipulation extension * Zicbom - Cache-block management extension The existing processors tunes are preserved: * riscv64 (rv64gc) * riscv32 (rv32gc) * riscv64nf (rv64imac_zicsr_zifencei) * riscv32nf (rv32imac_zicsr_zifencei) * riscv64nc (rv64imafd_zicsr_zifencei) Previously defined feature 'big-endian' has been removed as it was not used. Signed-off-by: Mark Hatle <mark.hatle@amd.com> --- meta/conf/machine/include/riscv/README | 122 ++++++++++++++++ .../conf/machine/include/riscv/arch-riscv.inc | 138 +++++++++++++++++- .../conf/machine/include/riscv/tune-riscv.inc | 40 ++--- meta/conf/machine/qemuriscv32.conf | 4 +- meta/lib/oe/__init__.py | 2 +- meta/lib/oe/tune.py | 81 ++++++++++ 6 files changed, 349 insertions(+), 38 deletions(-) create mode 100644 meta/conf/machine/include/riscv/README create mode 100644 meta/lib/oe/tune.py diff --git a/meta/conf/machine/include/riscv/README b/meta/conf/machine/include/riscv/README new file mode 100644 index 0000000000..beef68f523 --- /dev/null +++ b/meta/conf/machine/include/riscv/README @@ -0,0 +1,122 @@ +2025/06/08 - Mark Hatle <mark.hatle@amd.com> + - Initial Revision + +The RISC-V ISA is broken into two parts, a base ISA and extensions. As +of the writing of this document these are documented at: + +https://lf-riscv.atlassian.net/wiki/spaces/HOME/pages/16154769/RISC-V+Technical+Specifications + +Specifically "The RISC-V Instruction Set Manual Volume I: Unprivileged ISA" +was used to create this implementation. + +Requirements +------------ +As RISC-V is a “variable” ISA (a base isa plus numerous extensions), a +mechanism is required to specify a series of ISA features that a user or +tune can use to specify a specific CPU instantiation. + +Not all ratified or draft features should or can be implemented with the +available resources. + +The implementation should work for Linux, baremetal (newlib), zephyr and +other operating systems. Supported extensions should be based on +real-world examples. + +Linux +----- +Linux required base and support extensions should be available. Linux +requires: +* Base: rv32ima & rv64ima +* Optional FPU: fd +* Optional RISCV_ISA_C: c +* Optiona RISCV_ISA_V: v +* Required additional: _zicsr_zifencei +* Optional RISCV_ISA_ZBA: _zba +* Optional RISCV_ISA_ZBB: _zbb +* Optional RISCV_ISA_ZBC: _zbc (not supported by current QEMU design) + +See: https://git.yoctoproject.org/linux-yocto/tree/arch/riscv/Makefile?h=v6.12/base + +Baremetal +--------- +AMD Microblaze-V FPGA support uses the following static configurations: +Base: rv32e, rv32i, rv64i +Extensions: m, a, f, d, c, b, zicsr, zifencei + +Zephyr +------ +AMD Microblaze-V development for Zephyr is the same as Baremetal, with a +few additional extensions: zbc, zicbom + +ABI +--- +The following ABIs are supported GNU tools and some combination of systems. +* ilp32 - Integer, long and pointer are 32-bit +* lp64 - Long and pointer are 64-bit (integer is 32-bit) + +The ABI is dependent upon the core system implementation, as ilp32 can +only used on an ‘rv32’ system, while lp64 can only be used on an ‘rv64’ +system. + +There are additional variations of each ABI: +* e - used with the Reduced register extension +* f - used when single precision floating point (but not double precision) is + enabled +* d - used when both single and double precision floating point is enabled + +Based on the above, the ABI should be automatically determined based on +the selected Base ISA and Extensions. + +Implementation +-------------- +To make it easier to generate the RISC-V canonical arch, ISA based -march, +and the ABI string, a few new variables are added for specific RISC-V items. + +TUNE_RISCV_ARCH - This contains the canonical GNU style arch, generally this + will evaluate to "riscv32" or "riscv64". + +TUNE_RISCV_MARCH - This will contain an ISA based -march string compatible + with gcc and similar toolchains. For example: + rv32imacfd_zicsr_zifencei + +TUNE_RISCV_ABI - This is the generated ABI that corresponds to the ARCH and + MARCH/ISA values. For riscv32, the value will be ilp32 + (int, long and pointer is 32-bit) with the ISA + variation. For riscv64, the value will be lp64 (long + and pointer are 64-bit bit, while int is 32-bit) with the + ISA variation. The ISA affects the ABI when the 'e', 'f' + and 'd' extension are used. + +TUNE_RISCV_PKGARCH - This is the generated PKGARCH value. + +The standard variables are defined as: + +TUNE_CCARGS = "${@ '-march=${TUNE_RISCV_MARCH} -mabi=${TUNE_RISCV_ABI}' if not d.getVar('TUNE_CCARGS:tune-${DEFAULTTUNE}') else 'TUNE_CCARGS:tune-${DEFAULTTUNE}'}" + +The above will allow the user to specify an implementation specific +TUNE_CCARGS for a given processor tune if the default implementtion is +not adequate for some reason. It is expected that most, if not all, +implementations will use the default behavior. + +TUNE_ARCH = "${TUNE_RISCV_ARCH}" +TUNE_PKGARCH = "${TUNE_RISCV_PKGARCH}" + +The above two will always base their setting off the standard TUNE_FEATURES. + +Ratified and draft extensions should be implemented as TUNE_FEATURES in +the arch-riscv.inc file. + +Vendor specific extensions and processor specific settings should go +into a 'tune-<vendor>.inc' file, with tune-riscv.inc being reserved for +general purpose tunes. + +TUNE_FEATURE Helper +------------------- +A special helper function has been written that will convert RISC-V ISA +notation into TUNE_FEATURE notion, for example: + +rv32g -> rv 32 i m a f d zicsr zifencei + +The helper can be called using oe.tune.riscv_isa_to_tune("<ISA>") such as +oe.tune.riscv_isa_to_tune("rv64gc") which would return: + rv 64 i m a f d c zicsr zifencei diff --git a/meta/conf/machine/include/riscv/arch-riscv.inc b/meta/conf/machine/include/riscv/arch-riscv.inc index b34064e78f..99bed8fde5 100644 --- a/meta/conf/machine/include/riscv/arch-riscv.inc +++ b/meta/conf/machine/include/riscv/arch-riscv.inc @@ -1,14 +1,140 @@ # RISCV Architecture definition -DEFAULTTUNE ?= "riscv64" +# Based on the RISC-V Instruction Set Manual Volume I: Unprivileged ISA from May 2025 +# As well as the RISC-V options for using GCC (as of June 2025) -TUNE_ARCH = "${TUNE_ARCH:tune-${DEFAULTTUNE}}" -TUNE_PKGARCH = "${TUNE_PKGARCH:tune-${DEFAULTTUNE}}" -TUNE_CCARGS:append = "${@bb.utils.contains('TUNE_FEATURES', 'riscv64nf', ' -mabi=lp64', ' ', d)}" -TUNE_CCARGS:append = "${@bb.utils.contains('TUNE_FEATURES', 'riscv32nf', ' -mabi=ilp32', ' ', d)}" +# Note: the following should be implemented in the order that GCC expects +# -march= values to be defined in. -TUNE_CCARGS:append = "${@bb.utils.contains('TUNE_FEATURES', 'riscv64nc', ' -march=rv64imafd', ' ', d)}" +# Base ISA +# All supported march strings must start with rv32 or rv64 +TUNEVALID[rv] = "RISC-V" +TUNE_RISCV_ARCH = "${@bb.utils.contains("TUNE_FEATURES", "rv", "riscv", "", d)}" +TUNE_RISCV_MARCH = "${@bb.utils.contains("TUNE_FEATURES", "rv", "rv", "", d)}" +TUNE_RISCV_ABI = "" +# There are two primary ABIs, ilp32 and lp64 +# There are variants of both, that appears to be based on extensions above +# For example: +# rv32i uses ilp32, rv32e uses ilp32e, rv32f uses ilp32f +# rv64i uses lp64, rv64if uses lp64f, rv64id uses lp64d +TUNEVALID[32] = "ISA XLEN - 32-bit" +TUNECONFLICTS[32] = "64" +TUNE_RISCV_ARCH .= "${@bb.utils.contains("TUNE_FEATURES", "32", "32", "", d)}" +TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "32", "32", "", d)}" +TUNE_RISCV_ABI .= "${@bb.utils.contains("TUNE_FEATURES", "32", "ilp32", "", d)}" + +TUNEVALID[64] = "ISA XLEN - 64-bit" +TUNECONFLICTS[64] = "32" +TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "64", "64", "", d)}" +TUNE_RISCV_ARCH .= "${@bb.utils.contains("TUNE_FEATURES", "64", "64", "", d)}" +TUNE_RISCV_ABI .= "${@bb.utils.contains("TUNE_FEATURES", "64", "lp64", "", d)}" + +# The package arch starts with the canonical arch, but adds some extensions to make +# package compatibility clear +TUNE_RISCV_PKGARCH = "${TUNE_RISCV_ARCH}" + +# i, e, or g are defined by gcc, but 'g' refers to 'i' + extensions 'MAFD Zicsr Zifencei' +# So 'g' will not be defined here as it is an abbreviation of the expanded version +TUNEVALID[e] = "Reduced register base integer extension" +TUNECONFLICTS[e] = "i" +TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "e", "e", "", d)}" +TUNE_RISCV_ABI .= "${@bb.utils.contains("TUNE_FEATURES", "e", "e", "", d)}" +TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "e", "e", "", d)}" + +TUNEVALID[i] = "Base integer extension" +TUNECONFLICTS[i] = "e" +TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "i", "i", "", d)}" +TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "i", "i", "", d)}" + +# Extensions +TUNEVALID[m] = "Integer multiplication and division extension" +TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "m", "m", "", d)}" +TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "m", "m", "", d)}" + +TUNEVALID[a] = "Atomic extension" +TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "a", "a", "", d)}" +TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "a", "a", "", d)}" + +TUNEVALID[f] = "Single-precision floating-point extension" +TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "f d", "f", "", d)}" +TUNE_RISCV_PKGARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "f d", "f", "", d)}" + +TUNEVALID[d] = "Double-precision floating-point extension" +TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "d", "d", "", d)}" +TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "d", "d", "", d)}" + +# Only f OR d, but just one +TUNE_RISCV_ABI .= "${@bb.utils.contains("TUNE_FEATURES", "d", "d", bb.utils.contains("TUNE_FEATURES", "f", "f", "", d), d)}" + +TUNEVALID[c] = "Compressed extension" +TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "c", "c", "", d)}" +TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "c", "c", "", d)}" + +TUNEVALID[b] = "Bit Manipulation extension" +# Handled below via zba, zbb, zbs +# This matches current Linux kernel behavior +#TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "b", "b", "", d)}" +#TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "b", "b", "", d)}" + +TUNEVALID[v] = "Vector operations extension" +TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "v", "v", "", d)}" +TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "v", "v", "", d)}" + +# Now the special Z extensions +TUNEVALID[zicbom] = "Cache-block management extension" +TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zicbom", "_zicbom", "", d)}" +TUNE_RISCV_PKGARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zicbom", "_zicbom", "", d)}" + +TUNEVALID[zicsr] = "Control and status register access extension" +TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zicsr f d", "_zicsr", "", d)}" +# If zicsr (or zifencei) is in the path, OpenSBI fails to use the extensions, do to (Makefile): +# # Check whether the assembler and the compiler support the Zicsr and Zifencei extensions +# CC_SUPPORT_ZICSR_ZIFENCEI := $(shell $(CC) $(CLANG_TARGET) $(RELAX_FLAG) -nostdlib -march=rv$(OPENSBI_CC_XLEN)imafd_zicsr_zifencei -x c /dev/null -o /dev/null 2>&1 | grep -e "zicsr" -e "zifencei" > /dev/null && echo n || echo y) +# this will match on the path containing zicsr or zifencei when an error is reported, which +# will always happens in this check. +# +# Yocto Project Bugzilla 15897 +# +#TUNE_RISCV_PKGARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zicsr f d", "_zicsr", "", d)}" + +TUNEVALID[zifencei] = "Instruction-fetch fence extension" +TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zifencei", "_zifencei", "", d)}" +# See above Bug 15897 +#TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zifencei", "_zifencei", "", d)}" + +TUNEVALID[zba] = "Address bit manipulation extension" +TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "b zba", "_zba", "", d)}" +TUNE_RISCV_PKGARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "b zba", "_zba", "", d)}" + +TUNEVALID[zbb] = "Basic bit manipulation extension" +TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "b zbb", "_zbb", "", d)}" +TUNE_RISCV_PKGARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "b zbb", "_zbb", "", d)}" + +TUNEVALID[zbc] = "Carry-less multiplication extension" +TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zbc", "_zbc", "", d)}" +TUNE_RISCV_PKGARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zbc", "_zbc", "", d)}" + +TUNEVALID[zbs] = "Single-bit manipulation extension" +TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "b zbs", "_zbs", "", d)}" +TUNE_RISCV_PKGARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "b zbs", "_zbs", "", d)}" + +# Construct TUNE_CCARGS +# This should result in a CCARG similar to: +# -march=rv32imac -mabi=ilp32 +TUNE_CCARGS = "${@ '-march=${TUNE_RISCV_MARCH} -mabi=${TUNE_RISCV_ABI}' if not d.getVar('TUNE_CCARGS:tune-${DEFAULTTUNE}') else 'TUNE_CCARGS:tune-${DEFAULTTUNE}'}" + +# Construct TUNE_ARCH +# This should result in an arch string similar to: +# riscv32 +TUNE_ARCH = "${TUNE_RISCV_ARCH}" + +# Construct TUNE_PKGARCH +# This should result in a package are like: +# riscv32imac +TUNE_PKGARCH = "${TUNE_RISCV_PKGARCH}" + +# Misc settings # Fix: ld: unrecognized option '--hash-style=sysv' LINKER_HASH_STYLE:libc-newlib = "" LINKER_HASH_STYLE:libc-picolibc = "" diff --git a/meta/conf/machine/include/riscv/tune-riscv.inc b/meta/conf/machine/include/riscv/tune-riscv.inc index 804712077e..12c1125c8b 100644 --- a/meta/conf/machine/include/riscv/tune-riscv.inc +++ b/meta/conf/machine/include/riscv/tune-riscv.inc @@ -1,41 +1,23 @@ require conf/machine/include/riscv/arch-riscv.inc -TUNEVALID[riscv64] = "Enable 64-bit RISC-V optimizations" -TUNEVALID[riscv32] = "Enable 32-bit RISC-V optimizations" - -TUNEVALID[riscv64nf] = "Enable 64-bit RISC-V optimizations no floating point" -TUNEVALID[riscv32nf] = "Enable 32-bit RISC-V optimizations no floating point" - -TUNEVALID[riscv64nc] = "Enable 64-bit RISC-V optimizations without compressed instructions" - -TUNEVALID[bigendian] = "Big endian mode" +DEFAULTTUNE ?= "riscv64" AVAILTUNES += "riscv64 riscv32 riscv64nc riscv64nf riscv32nf" # Default -TUNE_FEATURES:tune-riscv64 = "riscv64" -TUNE_ARCH:tune-riscv64 = "riscv64" -TUNE_PKGARCH:tune-riscv64 = "riscv64" -PACKAGE_EXTRA_ARCHS:tune-riscv64 = "riscv64" +TUNE_FEATURES:tune-riscv64 := "${@oe.tune.riscv_isa_to_tune("rv64gc")}" +PACKAGE_EXTRA_ARCHS:tune-riscv64 = "${TUNE_RISCV_PKGARCH}" -TUNE_FEATURES:tune-riscv32 = "riscv32" -TUNE_ARCH:tune-riscv32 = "riscv32" -TUNE_PKGARCH:tune-riscv32 = "riscv32" -PACKAGE_EXTRA_ARCHS:tune-riscv32 = "riscv32" +TUNE_FEATURES:tune-riscv32 := "${@oe.tune.riscv_isa_to_tune("rv32gc")}" +PACKAGE_EXTRA_ARCHS:tune-riscv32 = "${TUNE_RISCV_PKGARCH}" # No float -TUNE_FEATURES:tune-riscv64nf = "${TUNE_FEATURES:tune-riscv64} riscv64nf" -TUNE_ARCH:tune-riscv64nf = "riscv64" -TUNE_PKGARCH:tune-riscv64nf = "riscv64nf" -PACKAGE_EXTRA_ARCHS:tune-riscv64nf = "riscv64nf" +TUNE_FEATURES:tune-riscv64nf := "${@oe.tune.riscv_isa_to_tune("rv64imac_zicsr_zifencei")}" +PACKAGE_EXTRA_ARCHS:tune-riscv64nf = "${TUNE_RISCV_PKGARCH}" -TUNE_FEATURES:tune-riscv32nf = "${TUNE_FEATURES:tune-riscv32} riscv32nf" -TUNE_ARCH:tune-riscv32nf = "riscv32" -TUNE_PKGARCH:tune-riscv32nf = "riscv32nf" -PACKAGE_EXTRA_ARCHS:tune-riscv32nf = "riscv32nf" +TUNE_FEATURES:tune-riscv32nf := "${@oe.tune.riscv_isa_to_tune("rv32imac_zicsr_zifencei")}" +PACKAGE_EXTRA_ARCHS:tune-riscv32nf = "${TUNE_RISCV_PKGARCH}" # no compressed -TUNE_FEATURES:tune-riscv64nc = "${TUNE_FEATURES:tune-riscv64} riscv64nc" -TUNE_ARCH:tune-riscv64nc = "riscv64" -TUNE_PKGARCH:tune-riscv64nc = "riscv64nc" -PACKAGE_EXTRA_ARCHS:tune-riscv64nc = "riscv64nc" +TUNE_FEATURES:tune-riscv64nc := "${@oe.tune.riscv_isa_to_tune("rv64imafd_zicsr_zifencei")}" +PACKAGE_EXTRA_ARCHS:tune-riscv64nc = "${TUNE_RISCV_PKGARCH}" diff --git a/meta/conf/machine/qemuriscv32.conf b/meta/conf/machine/qemuriscv32.conf index d3858dc051..aff36c28a5 100644 --- a/meta/conf/machine/qemuriscv32.conf +++ b/meta/conf/machine/qemuriscv32.conf @@ -2,9 +2,9 @@ #@NAME: generic riscv32 machine #@DESCRIPTION: Machine configuration for running a generic riscv32 -require conf/machine/include/riscv/qemuriscv.inc +DEFAULTTUNE ?= "riscv32" -DEFAULTTUNE = "riscv32" +require conf/machine/include/riscv/qemuriscv.inc PREFERRED_VERSION_openocd-native = "riscv" PREFERRED_VERSION_openocd = "riscv" diff --git a/meta/lib/oe/__init__.py b/meta/lib/oe/__init__.py index dd094a874a..73de774266 100644 --- a/meta/lib/oe/__init__.py +++ b/meta/lib/oe/__init__.py @@ -12,4 +12,4 @@ __path__ = extend_path(__path__, __name__) BBIMPORTS = ["qa", "data", "path", "utils", "types", "package", "packagedata", \ "packagegroup", "sstatesig", "lsb", "cachedpath", "license", "qemu", \ "reproducible", "rust", "buildcfg", "go", "spdx30_tasks", "spdx_common", \ - "cve_check"] + "cve_check", "tune"] diff --git a/meta/lib/oe/tune.py b/meta/lib/oe/tune.py new file mode 100644 index 0000000000..7fda19430d --- /dev/null +++ b/meta/lib/oe/tune.py @@ -0,0 +1,81 @@ +# +# Copyright OpenEmbedded Contributors +# +# SPDX-License-Identifier: GPL-2.0-only +# + +# riscv_isa_to_tune(isa) +# +# Automatically translate a RISC-V ISA string to TUNE_FEATURES +# +# Abbreviations, such as rv32g -> rv32imaffd_zicsr_zifencei are supported. +# +# Profiles, such as rva22u64, are NOT supported, you must use ISA strings. +# +def riscv_isa_to_tune(isa): + _isa = isa.lower() + + feature = [] + iter = 0 + + # rv or riscv + if _isa[iter:].startswith('rv'): + feature.append('rv') + iter = iter + 2 + elif _isa[iter:].startswith('riscv'): + feature.append('rv') + iter = iter + 5 + else: + # Not a risc-v ISA! + return _isa + + while (_isa[iter:]): + # Skip _ and whitespace + if _isa[iter] == '_' or _isa[iter].isspace(): + iter = iter + 1 + continue + + # Length, just capture numbers here + if _isa[iter].isdigit(): + iter_end = iter + while iter_end < len(_isa) and _isa[iter_end].isdigit(): + iter_end = iter_end + 1 + + feature.append(_isa[iter:iter_end]) + iter = iter_end + continue + + # Typically i, e or g is next, followed by extensions. + # Extensions are single character, except for Z, Ss, Sh, Sm, Sv, and X + + # If the extension starts with 'Z', 'S' or 'X' use the name until the next _, whitespace or end + if _isa[iter] in ['z', 's', 'x']: + ext_type = _isa[iter] + iter_end = iter + 1 + + # Multicharacter extension, these are supposed to have a _ before the next multicharacter extension + # See 37.4 and 37.5: + # 37.4: Underscores "_" may be used to separate ISA extensions... + # 37.5: All multi-letter extensions ... must be separated from other multi-letter extensions by an underscore... + # Some extensions permit only alphabetic characters, while others allow alphanumeric chartacters + while iter_end < len(_isa) and _isa[iter_end] != "_" and not _isa[iter_end].isspace(): + iter_end = iter_end + 1 + + feature.append(_isa[iter:iter_end]) + iter = iter_end + continue + + # 'g' is special, it's an abbreviation for imafd_zicsr_zifencei + # When expanding the abbreviation, any additional letters must appear before the _z* extensions + if _isa[iter] == 'g': + _isa = 'imafd' + _isa[iter+1:] + '_zicsr_zifencei' + iter = 0 + continue + + feature.append(_isa[iter]) + iter = iter + 1 + continue + + # Eliminate duplicates, but preserve the order + feature = list(dict.fromkeys(feature)) + return ' '.join(feature) -- 2.34.1 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [OE-core] [PATCH 1/6] riscv tunes: ISA Implementation of RISC-V tune features 2025-06-16 2:29 ` [PATCH 1/6] riscv tunes: ISA Implementation of RISC-V tune features Mark Hatle @ 2025-06-16 10:11 ` Richard Purdie 2025-06-16 14:21 ` Mark Hatle 0 siblings, 1 reply; 15+ messages in thread From: Richard Purdie @ 2025-06-16 10:11 UTC (permalink / raw) To: mark.hatle, openembedded-core On Sun, 2025-06-15 at 21:29 -0500, Mark Hatle via lists.openembedded.org wrote: > From: Mark Hatle <mark.hatle@amd.com> > > This implements the following base ISAs: > > * rv32i, rv64i > * rv32e, rv64i > > The following ABIs: > * ilp32, ilp32e, ilp32f, ilp32d > * lp64, lp64e, lp64f, lp64d > > The following ISA extension are also implemented: > * M - Integer Multiplication and Division Extension > * A - Atomic Memory Extension > * F - Single-Precision Floating-Point Extension > * D - Double-Precision Floating-Point Extension > * C - Compressed Extension > * B - Bit Manipulation Extension (implies Zba, Zbb, Zbs) > * V - Vector Operations Extension > * Zicsr - Control and Status Register Access Extension > * Zifencei - Instruction-Fetch Fence Extension > * Zba - Address bit manipulation extension > * Zbb - Basic bit manipulation extension > * Zbc - Carry-less multiplication extension > * Zbs - Single-bit manipulation extension > * Zicbom - Cache-block management extension > > The existing processors tunes are preserved: > * riscv64 (rv64gc) > * riscv32 (rv32gc) > * riscv64nf (rv64imac_zicsr_zifencei) > * riscv32nf (rv32imac_zicsr_zifencei) > * riscv64nc (rv64imafd_zicsr_zifencei) > > Previously defined feature 'big-endian' has been removed as it was not used. I tried this (just 1/6) and it caused: https://autobuilder.yoctoproject.org/valkyrie/#/builders/58/builds/142 https://autobuilder.yoctoproject.org/valkyrie/#/builders/45/builds/135 https://autobuilder.yoctoproject.org/valkyrie/#/builders/56/builds/114 Cheers, Richard ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [OE-core] [PATCH 1/6] riscv tunes: ISA Implementation of RISC-V tune features 2025-06-16 10:11 ` [OE-core] " Richard Purdie @ 2025-06-16 14:21 ` Mark Hatle 0 siblings, 0 replies; 15+ messages in thread From: Mark Hatle @ 2025-06-16 14:21 UTC (permalink / raw) To: Richard Purdie, openembedded-core These all seem to be related to the same issue reported by Gyorgy Sarvari. atomic_4 and atomic_8 functions are not working. --Mark On 6/16/25 5:11 AM, Richard Purdie wrote: > On Sun, 2025-06-15 at 21:29 -0500, Mark Hatle via lists.openembedded.org wrote: >> From: Mark Hatle <mark.hatle@amd.com> >> >> This implements the following base ISAs: >> >> * rv32i, rv64i >> * rv32e, rv64i >> >> The following ABIs: >> * ilp32, ilp32e, ilp32f, ilp32d >> * lp64, lp64e, lp64f, lp64d >> >> The following ISA extension are also implemented: >> * M - Integer Multiplication and Division Extension >> * A - Atomic Memory Extension >> * F - Single-Precision Floating-Point Extension >> * D - Double-Precision Floating-Point Extension >> * C - Compressed Extension >> * B - Bit Manipulation Extension (implies Zba, Zbb, Zbs) >> * V - Vector Operations Extension >> * Zicsr - Control and Status Register Access Extension >> * Zifencei - Instruction-Fetch Fence Extension >> * Zba - Address bit manipulation extension >> * Zbb - Basic bit manipulation extension >> * Zbc - Carry-less multiplication extension >> * Zbs - Single-bit manipulation extension >> * Zicbom - Cache-block management extension >> >> The existing processors tunes are preserved: >> * riscv64 (rv64gc) >> * riscv32 (rv32gc) >> * riscv64nf (rv64imac_zicsr_zifencei) >> * riscv32nf (rv32imac_zicsr_zifencei) >> * riscv64nc (rv64imafd_zicsr_zifencei) >> >> Previously defined feature 'big-endian' has been removed as it was not used. > > I tried this (just 1/6) and it caused: > > https://autobuilder.yoctoproject.org/valkyrie/#/builders/58/builds/142 > https://autobuilder.yoctoproject.org/valkyrie/#/builders/45/builds/135 > https://autobuilder.yoctoproject.org/valkyrie/#/builders/56/builds/114 > > Cheers, > > Richard ^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 2/6] linux-yocto: Enable risc-v TUNE_FEATURES ISA selections 2025-06-16 2:29 [PATCH 0/6] ISA based RISC-V tune implementation Mark Hatle 2025-06-16 2:29 ` [PATCH 1/6] riscv tunes: ISA Implementation of RISC-V tune features Mark Hatle @ 2025-06-16 2:29 ` Mark Hatle 2025-06-16 10:50 ` Bruce Ashfield 2025-06-16 2:29 ` [PATCH 3/6] u-boot: Dynamic RISC-V ISA configuration Mark Hatle ` (4 subsequent siblings) 6 siblings, 1 reply; 15+ messages in thread From: Mark Hatle @ 2025-06-16 2:29 UTC (permalink / raw) To: openembedded-core, Bruce Ashfield From: Mark Hatle <mark.hatle@amd.com> Allow the risc-v TUNE_FEATURES to select specific ISA (kconfig) selections in the kernel config via config fragments. This allows the following items to be selected dynamically: CONFIG_ARCH_RV32I CONFIG_ARCH_RV64I CONFIG_FPU CONFIG_RISCV_ISA_C CONFIG_RISCV_ISA_V CONFIG_RISCV_ISA_ZBB CONFIG_RISCV_ISA_ZICBOM CONFIG_RISCV_ISA_ZICBOZ CONFIG_TOOLCHAIN_NEEDS_EXPLICIT_ZICSR_ZIFENCEI Signed-off-by: Mark Hatle <mark.hatle@amd.com> --- meta/recipes-kernel/linux/files/risc-v-isa-c.cfg | 1 + .../linux/files/risc-v-isa-clear.cfg | 9 +++++++++ meta/recipes-kernel/linux/files/risc-v-isa-fpu.cfg | 1 + .../linux/files/risc-v-isa-rv32i.cfg | 2 ++ .../linux/files/risc-v-isa-rv64i.cfg | 2 ++ meta/recipes-kernel/linux/files/risc-v-isa-v.cfg | 1 + meta/recipes-kernel/linux/files/risc-v-isa-zbb.cfg | 1 + .../linux/files/risc-v-isa-zicbom.cfg | 1 + meta/recipes-kernel/linux/linux-yocto.inc | 14 ++++++++++++++ 9 files changed, 32 insertions(+) create mode 100644 meta/recipes-kernel/linux/files/risc-v-isa-c.cfg create mode 100644 meta/recipes-kernel/linux/files/risc-v-isa-clear.cfg create mode 100644 meta/recipes-kernel/linux/files/risc-v-isa-fpu.cfg create mode 100644 meta/recipes-kernel/linux/files/risc-v-isa-rv32i.cfg create mode 100644 meta/recipes-kernel/linux/files/risc-v-isa-rv64i.cfg create mode 100644 meta/recipes-kernel/linux/files/risc-v-isa-v.cfg create mode 100644 meta/recipes-kernel/linux/files/risc-v-isa-zbb.cfg create mode 100644 meta/recipes-kernel/linux/files/risc-v-isa-zicbom.cfg diff --git a/meta/recipes-kernel/linux/files/risc-v-isa-c.cfg b/meta/recipes-kernel/linux/files/risc-v-isa-c.cfg new file mode 100644 index 0000000000..1cb459f636 --- /dev/null +++ b/meta/recipes-kernel/linux/files/risc-v-isa-c.cfg @@ -0,0 +1 @@ +CONFIG_RISCV_ISA_C=y diff --git a/meta/recipes-kernel/linux/files/risc-v-isa-clear.cfg b/meta/recipes-kernel/linux/files/risc-v-isa-clear.cfg new file mode 100644 index 0000000000..ba18d7b9b5 --- /dev/null +++ b/meta/recipes-kernel/linux/files/risc-v-isa-clear.cfg @@ -0,0 +1,9 @@ +# CONFIG_ARCH_RV32I is not set +# CONFIG_ARCH_RV64I is not set +# CONFIG_FPU is not set +# CONFIG_RISCV_ISA_C is not set +# CONFIG_RISCV_ISA_V is not set +# CONFIG_RISCV_ISA_ZBB is not set +# CONFIG_RISCV_ISA_ZICBOM is not set +# CONFIG_RISCV_ISA_ZICBOZ is not set +# CONFIG_TOOLCHAIN_NEEDS_EXPLICIT_ZICSR_ZIFENCEI is not set diff --git a/meta/recipes-kernel/linux/files/risc-v-isa-fpu.cfg b/meta/recipes-kernel/linux/files/risc-v-isa-fpu.cfg new file mode 100644 index 0000000000..c099c8e81d --- /dev/null +++ b/meta/recipes-kernel/linux/files/risc-v-isa-fpu.cfg @@ -0,0 +1 @@ +CONFIG_FPU=y diff --git a/meta/recipes-kernel/linux/files/risc-v-isa-rv32i.cfg b/meta/recipes-kernel/linux/files/risc-v-isa-rv32i.cfg new file mode 100644 index 0000000000..4c6bac5138 --- /dev/null +++ b/meta/recipes-kernel/linux/files/risc-v-isa-rv32i.cfg @@ -0,0 +1,2 @@ +CONFIG_ARCH_RV32I=y +CONFIG_TOOLCHAIN_NEEDS_EXPLICIT_ZICSR_ZIFENCEI=y diff --git a/meta/recipes-kernel/linux/files/risc-v-isa-rv64i.cfg b/meta/recipes-kernel/linux/files/risc-v-isa-rv64i.cfg new file mode 100644 index 0000000000..002b492e4c --- /dev/null +++ b/meta/recipes-kernel/linux/files/risc-v-isa-rv64i.cfg @@ -0,0 +1,2 @@ +CONFIG_ARCH_RV64I=y +CONFIG_TOOLCHAIN_NEEDS_EXPLICIT_ZICSR_ZIFENCEI=y diff --git a/meta/recipes-kernel/linux/files/risc-v-isa-v.cfg b/meta/recipes-kernel/linux/files/risc-v-isa-v.cfg new file mode 100644 index 0000000000..c29c97fc4a --- /dev/null +++ b/meta/recipes-kernel/linux/files/risc-v-isa-v.cfg @@ -0,0 +1 @@ +CONFIG_RISCV_ISA_V=y diff --git a/meta/recipes-kernel/linux/files/risc-v-isa-zbb.cfg b/meta/recipes-kernel/linux/files/risc-v-isa-zbb.cfg new file mode 100644 index 0000000000..2b71b016f8 --- /dev/null +++ b/meta/recipes-kernel/linux/files/risc-v-isa-zbb.cfg @@ -0,0 +1 @@ +CONFIG_RISCV_ISA_ZBB=y diff --git a/meta/recipes-kernel/linux/files/risc-v-isa-zicbom.cfg b/meta/recipes-kernel/linux/files/risc-v-isa-zicbom.cfg new file mode 100644 index 0000000000..96daf04b20 --- /dev/null +++ b/meta/recipes-kernel/linux/files/risc-v-isa-zicbom.cfg @@ -0,0 +1 @@ +CONFIG_RISCV_ISA_ZICBOM=y diff --git a/meta/recipes-kernel/linux/linux-yocto.inc b/meta/recipes-kernel/linux/linux-yocto.inc index 389329030d..cdf2583698 100644 --- a/meta/recipes-kernel/linux/linux-yocto.inc +++ b/meta/recipes-kernel/linux/linux-yocto.inc @@ -37,6 +37,20 @@ KERNEL_FEATURES:append = " ${@bb.utils.contains('MACHINE_FEATURES', 'efi', 'cfg/ KERNEL_FEATURES:append = " ${@bb.utils.contains('MACHINE_FEATURES', 'numa', 'features/numa/numa.scc', '', d)}" KERNEL_FEATURES:append = " ${@bb.utils.contains('MACHINE_FEATURES', 'vfat', 'cfg/fs/vfat.scc', '', d)}" +SRC_URI_RISCV = "\ + file://risc-v-isa-clear.cfg \ + ${@bb.utils.contains( "TUNE_FEATURES", "rv 32 i m a", "file://risc-v-isa-rv32i.cfg", "", d)} \ + ${@bb.utils.contains( "TUNE_FEATURES", "rv 64 i m a", "file://risc-v-isa-rv64i.cfg", "", d)} \ + ${@bb.utils.contains( "TUNE_FEATURES", "f d", "file://risc-v-isa-fpu.cfg", "", d)} \ + ${@bb.utils.contains( "TUNE_FEATURES", "c", "file://risc-v-isa-c.cfg", "", d)} \ + ${@bb.utils.contains( "TUNE_FEATURES", "v", "file://risc-v-isa-v.cfg", "", d)} \ + ${@bb.utils.contains_any("TUNE_FEATURES", "b zbb", "file://risc-v-isa-zbb.cfg", "", d)} \ + ${@bb.utils.contains( "TUNE_FEATURES", "zicbom", "file://risc-v-isa-zicbom.cfg", "", d)} \ + " + +SRC_URI:append:riscv32 = "${SRC_URI_RISCV}" +SRC_URI:append:riscv64 = "${SRC_URI_RISCV}" + # A KMACHINE is the mapping of a yocto $MACHINE to what is built # by the kernel. This is typically the branch that should be built, # and it can be specific to the machine or shared -- 2.34.1 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [PATCH 2/6] linux-yocto: Enable risc-v TUNE_FEATURES ISA selections 2025-06-16 2:29 ` [PATCH 2/6] linux-yocto: Enable risc-v TUNE_FEATURES ISA selections Mark Hatle @ 2025-06-16 10:50 ` Bruce Ashfield 0 siblings, 0 replies; 15+ messages in thread From: Bruce Ashfield @ 2025-06-16 10:50 UTC (permalink / raw) To: Mark Hatle; +Cc: openembedded-core [-- Attachment #1: Type: text/plain, Size: 6741 bytes --] On Sun, Jun 15, 2025 at 10:30 PM Mark Hatle <mark.hatle@kernel.crashing.org> wrote: > From: Mark Hatle <mark.hatle@amd.com> > > Allow the risc-v TUNE_FEATURES to select specific ISA (kconfig) selections > in the kernel config via config fragments. > > This allows the following items to be selected dynamically: > > CONFIG_ARCH_RV32I > CONFIG_ARCH_RV64I > CONFIG_FPU > CONFIG_RISCV_ISA_C > CONFIG_RISCV_ISA_V > CONFIG_RISCV_ISA_ZBB > CONFIG_RISCV_ISA_ZICBOM > CONFIG_RISCV_ISA_ZICBOZ > CONFIG_TOOLCHAIN_NEEDS_EXPLICIT_ZICSR_ZIFENCEI > As you probably suspected, These need to be submitted to the kernel-cache and enabled via KERNEL_FEATURES additions, not just added to the SRC_URI. Cheers, Bruce > > Signed-off-by: Mark Hatle <mark.hatle@amd.com> > --- > meta/recipes-kernel/linux/files/risc-v-isa-c.cfg | 1 + > .../linux/files/risc-v-isa-clear.cfg | 9 +++++++++ > meta/recipes-kernel/linux/files/risc-v-isa-fpu.cfg | 1 + > .../linux/files/risc-v-isa-rv32i.cfg | 2 ++ > .../linux/files/risc-v-isa-rv64i.cfg | 2 ++ > meta/recipes-kernel/linux/files/risc-v-isa-v.cfg | 1 + > meta/recipes-kernel/linux/files/risc-v-isa-zbb.cfg | 1 + > .../linux/files/risc-v-isa-zicbom.cfg | 1 + > meta/recipes-kernel/linux/linux-yocto.inc | 14 ++++++++++++++ > 9 files changed, 32 insertions(+) > create mode 100644 meta/recipes-kernel/linux/files/risc-v-isa-c.cfg > create mode 100644 meta/recipes-kernel/linux/files/risc-v-isa-clear.cfg > create mode 100644 meta/recipes-kernel/linux/files/risc-v-isa-fpu.cfg > create mode 100644 meta/recipes-kernel/linux/files/risc-v-isa-rv32i.cfg > create mode 100644 meta/recipes-kernel/linux/files/risc-v-isa-rv64i.cfg > create mode 100644 meta/recipes-kernel/linux/files/risc-v-isa-v.cfg > create mode 100644 meta/recipes-kernel/linux/files/risc-v-isa-zbb.cfg > create mode 100644 meta/recipes-kernel/linux/files/risc-v-isa-zicbom.cfg > > diff --git a/meta/recipes-kernel/linux/files/risc-v-isa-c.cfg > b/meta/recipes-kernel/linux/files/risc-v-isa-c.cfg > new file mode 100644 > index 0000000000..1cb459f636 > --- /dev/null > +++ b/meta/recipes-kernel/linux/files/risc-v-isa-c.cfg > @@ -0,0 +1 @@ > +CONFIG_RISCV_ISA_C=y > diff --git a/meta/recipes-kernel/linux/files/risc-v-isa-clear.cfg > b/meta/recipes-kernel/linux/files/risc-v-isa-clear.cfg > new file mode 100644 > index 0000000000..ba18d7b9b5 > --- /dev/null > +++ b/meta/recipes-kernel/linux/files/risc-v-isa-clear.cfg > @@ -0,0 +1,9 @@ > +# CONFIG_ARCH_RV32I is not set > +# CONFIG_ARCH_RV64I is not set > +# CONFIG_FPU is not set > +# CONFIG_RISCV_ISA_C is not set > +# CONFIG_RISCV_ISA_V is not set > +# CONFIG_RISCV_ISA_ZBB is not set > +# CONFIG_RISCV_ISA_ZICBOM is not set > +# CONFIG_RISCV_ISA_ZICBOZ is not set > +# CONFIG_TOOLCHAIN_NEEDS_EXPLICIT_ZICSR_ZIFENCEI is not set > diff --git a/meta/recipes-kernel/linux/files/risc-v-isa-fpu.cfg > b/meta/recipes-kernel/linux/files/risc-v-isa-fpu.cfg > new file mode 100644 > index 0000000000..c099c8e81d > --- /dev/null > +++ b/meta/recipes-kernel/linux/files/risc-v-isa-fpu.cfg > @@ -0,0 +1 @@ > +CONFIG_FPU=y > diff --git a/meta/recipes-kernel/linux/files/risc-v-isa-rv32i.cfg > b/meta/recipes-kernel/linux/files/risc-v-isa-rv32i.cfg > new file mode 100644 > index 0000000000..4c6bac5138 > --- /dev/null > +++ b/meta/recipes-kernel/linux/files/risc-v-isa-rv32i.cfg > @@ -0,0 +1,2 @@ > +CONFIG_ARCH_RV32I=y > +CONFIG_TOOLCHAIN_NEEDS_EXPLICIT_ZICSR_ZIFENCEI=y > diff --git a/meta/recipes-kernel/linux/files/risc-v-isa-rv64i.cfg > b/meta/recipes-kernel/linux/files/risc-v-isa-rv64i.cfg > new file mode 100644 > index 0000000000..002b492e4c > --- /dev/null > +++ b/meta/recipes-kernel/linux/files/risc-v-isa-rv64i.cfg > @@ -0,0 +1,2 @@ > +CONFIG_ARCH_RV64I=y > +CONFIG_TOOLCHAIN_NEEDS_EXPLICIT_ZICSR_ZIFENCEI=y > diff --git a/meta/recipes-kernel/linux/files/risc-v-isa-v.cfg > b/meta/recipes-kernel/linux/files/risc-v-isa-v.cfg > new file mode 100644 > index 0000000000..c29c97fc4a > --- /dev/null > +++ b/meta/recipes-kernel/linux/files/risc-v-isa-v.cfg > @@ -0,0 +1 @@ > +CONFIG_RISCV_ISA_V=y > diff --git a/meta/recipes-kernel/linux/files/risc-v-isa-zbb.cfg > b/meta/recipes-kernel/linux/files/risc-v-isa-zbb.cfg > new file mode 100644 > index 0000000000..2b71b016f8 > --- /dev/null > +++ b/meta/recipes-kernel/linux/files/risc-v-isa-zbb.cfg > @@ -0,0 +1 @@ > +CONFIG_RISCV_ISA_ZBB=y > diff --git a/meta/recipes-kernel/linux/files/risc-v-isa-zicbom.cfg > b/meta/recipes-kernel/linux/files/risc-v-isa-zicbom.cfg > new file mode 100644 > index 0000000000..96daf04b20 > --- /dev/null > +++ b/meta/recipes-kernel/linux/files/risc-v-isa-zicbom.cfg > @@ -0,0 +1 @@ > +CONFIG_RISCV_ISA_ZICBOM=y > diff --git a/meta/recipes-kernel/linux/linux-yocto.inc > b/meta/recipes-kernel/linux/linux-yocto.inc > index 389329030d..cdf2583698 100644 > --- a/meta/recipes-kernel/linux/linux-yocto.inc > +++ b/meta/recipes-kernel/linux/linux-yocto.inc > @@ -37,6 +37,20 @@ KERNEL_FEATURES:append = " > ${@bb.utils.contains('MACHINE_FEATURES', 'efi', 'cfg/ > KERNEL_FEATURES:append = " ${@bb.utils.contains('MACHINE_FEATURES', > 'numa', 'features/numa/numa.scc', '', d)}" > KERNEL_FEATURES:append = " ${@bb.utils.contains('MACHINE_FEATURES', > 'vfat', 'cfg/fs/vfat.scc', '', d)}" > > +SRC_URI_RISCV = "\ > + file://risc-v-isa-clear.cfg \ > + ${@bb.utils.contains( "TUNE_FEATURES", "rv 32 i m a", > "file://risc-v-isa-rv32i.cfg", "", d)} \ > + ${@bb.utils.contains( "TUNE_FEATURES", "rv 64 i m a", > "file://risc-v-isa-rv64i.cfg", "", d)} \ > + ${@bb.utils.contains( "TUNE_FEATURES", "f d", > "file://risc-v-isa-fpu.cfg", "", d)} \ > + ${@bb.utils.contains( "TUNE_FEATURES", "c", > "file://risc-v-isa-c.cfg", "", d)} \ > + ${@bb.utils.contains( "TUNE_FEATURES", "v", > "file://risc-v-isa-v.cfg", "", d)} \ > + ${@bb.utils.contains_any("TUNE_FEATURES", "b zbb", > "file://risc-v-isa-zbb.cfg", "", d)} \ > + ${@bb.utils.contains( "TUNE_FEATURES", "zicbom", > "file://risc-v-isa-zicbom.cfg", "", d)} \ > + " > + > +SRC_URI:append:riscv32 = "${SRC_URI_RISCV}" > +SRC_URI:append:riscv64 = "${SRC_URI_RISCV}" > + > # A KMACHINE is the mapping of a yocto $MACHINE to what is built > # by the kernel. This is typically the branch that should be built, > # and it can be specific to the machine or shared > -- > 2.34.1 > > -- - Thou shalt not follow the NULL pointer, for chaos and madness await thee at its end - "Use the force Harry" - Gandalf, Star Trek II [-- Attachment #2: Type: text/html, Size: 8731 bytes --] ^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 3/6] u-boot: Dynamic RISC-V ISA configuration 2025-06-16 2:29 [PATCH 0/6] ISA based RISC-V tune implementation Mark Hatle 2025-06-16 2:29 ` [PATCH 1/6] riscv tunes: ISA Implementation of RISC-V tune features Mark Hatle 2025-06-16 2:29 ` [PATCH 2/6] linux-yocto: Enable risc-v TUNE_FEATURES ISA selections Mark Hatle @ 2025-06-16 2:29 ` Mark Hatle 2025-06-16 2:29 ` [PATCH 4/6] qemuriscv: Dynamically configure qemu CPU Mark Hatle ` (3 subsequent siblings) 6 siblings, 0 replies; 15+ messages in thread From: Mark Hatle @ 2025-06-16 2:29 UTC (permalink / raw) To: openembedded-core From: Mark Hatle <mark.hatle@amd.com> Allow the risc-v TUNE_FEATURES to select specific ISA (kconfig) selections via config fragments. This allows the following items to be selected dynamically: CONFIG_RISCV_ISA_C CONFIG_RISCV_ISA_F CONFIG_RISCV_ISA_D CONFIG_RISCV_ISA_ZBB CONFIG_RISCV_ISA_A CONFIG_RISCV_ISA_ZICBOM Signed-off-by: Mark Hatle <mark.hatle@amd.com> --- meta/recipes-bsp/u-boot/files/u-boot-riscv-isa_a.cfg | 1 + meta/recipes-bsp/u-boot/files/u-boot-riscv-isa_c.cfg | 1 + .../u-boot/files/u-boot-riscv-isa_clear.cfg | 6 ++++++ meta/recipes-bsp/u-boot/files/u-boot-riscv-isa_d.cfg | 1 + meta/recipes-bsp/u-boot/files/u-boot-riscv-isa_f.cfg | 1 + .../u-boot/files/u-boot-riscv-isa_zbb.cfg | 1 + .../u-boot/files/u-boot-riscv-isa_zicbom.cfg | 1 + meta/recipes-bsp/u-boot/u-boot-common.inc | 12 ++++++++++++ 8 files changed, 24 insertions(+) create mode 100644 meta/recipes-bsp/u-boot/files/u-boot-riscv-isa_a.cfg create mode 100644 meta/recipes-bsp/u-boot/files/u-boot-riscv-isa_c.cfg create mode 100644 meta/recipes-bsp/u-boot/files/u-boot-riscv-isa_clear.cfg create mode 100644 meta/recipes-bsp/u-boot/files/u-boot-riscv-isa_d.cfg create mode 100644 meta/recipes-bsp/u-boot/files/u-boot-riscv-isa_f.cfg create mode 100644 meta/recipes-bsp/u-boot/files/u-boot-riscv-isa_zbb.cfg create mode 100644 meta/recipes-bsp/u-boot/files/u-boot-riscv-isa_zicbom.cfg diff --git a/meta/recipes-bsp/u-boot/files/u-boot-riscv-isa_a.cfg b/meta/recipes-bsp/u-boot/files/u-boot-riscv-isa_a.cfg new file mode 100644 index 0000000000..fc45b64480 --- /dev/null +++ b/meta/recipes-bsp/u-boot/files/u-boot-riscv-isa_a.cfg @@ -0,0 +1 @@ +CONFIG_RISCV_ISA_A=y diff --git a/meta/recipes-bsp/u-boot/files/u-boot-riscv-isa_c.cfg b/meta/recipes-bsp/u-boot/files/u-boot-riscv-isa_c.cfg new file mode 100644 index 0000000000..1cb459f636 --- /dev/null +++ b/meta/recipes-bsp/u-boot/files/u-boot-riscv-isa_c.cfg @@ -0,0 +1 @@ +CONFIG_RISCV_ISA_C=y diff --git a/meta/recipes-bsp/u-boot/files/u-boot-riscv-isa_clear.cfg b/meta/recipes-bsp/u-boot/files/u-boot-riscv-isa_clear.cfg new file mode 100644 index 0000000000..ce90da23ce --- /dev/null +++ b/meta/recipes-bsp/u-boot/files/u-boot-riscv-isa_clear.cfg @@ -0,0 +1,6 @@ +# CONFIG_RISCV_ISA_C is not set +# CONFIG_RISCV_ISA_F is not set +# CONFIG_RISCV_ISA_D is not set +# CONFIG_RISCV_ISA_ZBB is not set +# CONFIG_RISCV_ISA_A is not set +# CONFIG_RISCV_ISA_ZICBOM is not set diff --git a/meta/recipes-bsp/u-boot/files/u-boot-riscv-isa_d.cfg b/meta/recipes-bsp/u-boot/files/u-boot-riscv-isa_d.cfg new file mode 100644 index 0000000000..fd25fa4e89 --- /dev/null +++ b/meta/recipes-bsp/u-boot/files/u-boot-riscv-isa_d.cfg @@ -0,0 +1 @@ +CONFIG_RISCV_ISA_D=y diff --git a/meta/recipes-bsp/u-boot/files/u-boot-riscv-isa_f.cfg b/meta/recipes-bsp/u-boot/files/u-boot-riscv-isa_f.cfg new file mode 100644 index 0000000000..dfa9876f82 --- /dev/null +++ b/meta/recipes-bsp/u-boot/files/u-boot-riscv-isa_f.cfg @@ -0,0 +1 @@ +CONFIG_RISCV_ISA_F=y diff --git a/meta/recipes-bsp/u-boot/files/u-boot-riscv-isa_zbb.cfg b/meta/recipes-bsp/u-boot/files/u-boot-riscv-isa_zbb.cfg new file mode 100644 index 0000000000..2b71b016f8 --- /dev/null +++ b/meta/recipes-bsp/u-boot/files/u-boot-riscv-isa_zbb.cfg @@ -0,0 +1 @@ +CONFIG_RISCV_ISA_ZBB=y diff --git a/meta/recipes-bsp/u-boot/files/u-boot-riscv-isa_zicbom.cfg b/meta/recipes-bsp/u-boot/files/u-boot-riscv-isa_zicbom.cfg new file mode 100644 index 0000000000..96daf04b20 --- /dev/null +++ b/meta/recipes-bsp/u-boot/files/u-boot-riscv-isa_zicbom.cfg @@ -0,0 +1 @@ +CONFIG_RISCV_ISA_ZICBOM=y diff --git a/meta/recipes-bsp/u-boot/u-boot-common.inc b/meta/recipes-bsp/u-boot/u-boot-common.inc index fd1eab5cdd..515f18ba9c 100644 --- a/meta/recipes-bsp/u-boot/u-boot-common.inc +++ b/meta/recipes-bsp/u-boot/u-boot-common.inc @@ -16,6 +16,18 @@ SRCREV = "34820924edbc4ec7803eb89d9852f4b870fa760a" SRC_URI = "git://source.denx.de/u-boot/u-boot.git;protocol=https;branch=master;tag=v${PV}" +SRC_URI_RISCV = "\ + file://u-boot-riscv-isa_clear.cfg \ + ${@bb.utils.contains ("TUNE_FEATURES", "a", "file://u-boot-riscv-isa_a.cfg", "", d)} \ + ${@bb.utils.contains ("TUNE_FEATURES", "f", "file://u-boot-riscv-isa_f.cfg", "", d)} \ + ${@bb.utils.contains ("TUNE_FEATURES", "d", "file://u-boot-riscv-isa_d.cfg", "", d)} \ + ${@bb.utils.contains_any("TUNE_FEATURES", "b zbb", "file://u-boot-riscv-isa_zbb.cfg", "", d)} \ + ${@bb.utils.contains ("TUNE_FEATURES", "zicbom", "file://u-boot-riscv-isa_zicbom.cfg", "", d)} \ + " + +SRC_URI:append:riscv32 = "${SRC_URI_RISCV}" +SRC_URI:append:riscv64 = "${SRC_URI_RISCV}" + S = "${WORKDIR}/git" B = "${WORKDIR}/build" -- 2.34.1 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH 4/6] qemuriscv: Dynamically configure qemu CPU 2025-06-16 2:29 [PATCH 0/6] ISA based RISC-V tune implementation Mark Hatle ` (2 preceding siblings ...) 2025-06-16 2:29 ` [PATCH 3/6] u-boot: Dynamic RISC-V ISA configuration Mark Hatle @ 2025-06-16 2:29 ` Mark Hatle 2025-06-16 2:29 ` [PATCH 5/6] features_check.bbclass: Add support for required TUNE_FEATURES Mark Hatle ` (2 subsequent siblings) 6 siblings, 0 replies; 15+ messages in thread From: Mark Hatle @ 2025-06-16 2:29 UTC (permalink / raw) To: openembedded-core From: Mark Hatle <mark.hatle@amd.com> Use TUNE_FEATURES to dynamically configure the QEMU emulated CPU for the options selected by the DEFAULTTUNE. Note: OpenSBI currently requires 'c' (compressed instructions) or it will not work. Change the base device configuration to use a different variable to select the emulate devices. This will allow a user to override or append the QB_OPT_APPEND without the riscv32 override getting in the way. Signed-off-by: Mark Hatle <mark.hatle@amd.com> --- meta/conf/machine/include/riscv/qemuriscv.inc | 31 +++++++++++++++++-- 1 file changed, 28 insertions(+), 3 deletions(-) diff --git a/meta/conf/machine/include/riscv/qemuriscv.inc b/meta/conf/machine/include/riscv/qemuriscv.inc index 65cbfd66ee..91a84cdd39 100644 --- a/meta/conf/machine/include/riscv/qemuriscv.inc +++ b/meta/conf/machine/include/riscv/qemuriscv.inc @@ -27,7 +27,6 @@ UBOOT_ENTRYPOINT:riscv64 = "0x80200000" # qemuboot options QB_SMP ?= "-smp 4" QB_KERNEL_CMDLINE_APPEND = "earlycon=sbi" -QB_CPU:riscv64 ?= "-cpu rva22s64" QB_MACHINE = "-machine virt" QB_DEFAULT_BIOS = "fw_jump.elf" QB_TAP_OPT = "-netdev tap,id=net0,ifname=@TAP@,script=no,downscript=no" @@ -36,5 +35,31 @@ QB_ROOTFS_OPT = "-drive id=disk0,file=@ROOTFS@,if=none,format=raw -device virtio QB_SERIAL_OPT = "-device virtio-serial-device -chardev null,id=virtcon -device virtconsole,chardev=virtcon" QB_TCPSERIAL_OPT = " -device virtio-serial-device -chardev socket,id=virtcon,port=@PORT@,host=127.0.0.1,nodelay=on -device virtconsole,chardev=virtcon" QB_GRAPHICS = "-device bochs-display" -QB_OPT_APPEND = "-device qemu-xhci -device usb-tablet -device usb-kbd" -QB_OPT_APPEND:riscv32 = "-device virtio-tablet-pci -device virtio-keyboard-pci" +QB_OPT_APPEND = "${RV_QEMU_ISA} ${RV_QEMU_DEVICES}" + +RV_QEMU_DEVICES = "-device qemu-xhci -device usb-tablet -device usb-kbd" +RV_QEMU_DEVICES:riscv32 = "-device virtio-tablet-pci -device virtio-keyboard-pci" + +RV_QEMU_ISA = "-cpu " +# Choose rv32 or rv64 +RV_QEMU_ISA .= "${@bb.utils.contains("TUNE_FEATURES", "rv 32", "rv32", "", d)}" +RV_QEMU_ISA .= "${@bb.utils.contains("TUNE_FEATURES", "rv 64", "rv64", "", d)}" +# Disable all of the default extensions we don't support +RV_QEMU_ISA .= ",zihintntl=false,zihintpause=false,zawrs=false,zfa=false,svadu=false,zicntr=false,zihpm=false" +RV_QEMU_ISA .= ",zicboz=false,zicbop=false,zmmul=false,sstc=false,h=false" +# Dynamically enable the extensions based on TUNE_FEATURES +RV_QEMU_ISA .= "${@bb.utils.contains ("TUNE_FEATURES", "m", ",m=true", ",m=false", d)}" +RV_QEMU_ISA .= "${@bb.utils.contains ("TUNE_FEATURES", "a", ",a=true", ",a=false", d)}" +RV_QEMU_ISA .= "${@bb.utils.contains_any("TUNE_FEATURES", "f d", ",f=true", ",f=false", d)}" +RV_QEMU_ISA .= "${@bb.utils.contains ("TUNE_FEATURES", "d", ",d=true", ",d=false", d)}" +# OpenSBI fails to boot without 'c' +#RV_QEMU_ISA .= "${@bb.utils.contains ("TUNE_FEATURES", "c", ",c=true", ",c=false", d)}" +RV_QEMU_ISA .= "${@bb.utils.contains ("TUNE_FEATURES", "v", ",v=true", ",v=false", d)}" +RV_QEMU_ISA .= "${@bb.utils.contains ("TUNE_FEATURES", "zicbom", ",zicbom=true", ",zicbom=false", d)}" +RV_QEMU_ISA .= "${@bb.utils.contains_any("TUNE_FEATURES", "zicsr f d", ",zicsr=true", ",zicsr=false", d)}" +RV_QEMU_ISA .= "${@bb.utils.contains ("TUNE_FEATURES", "zifencei", ",zifencei=true", ",zifencei=false", d)}" +RV_QEMU_ISA .= "${@bb.utils.contains_any("TUNE_FEATURES", "b zba", ",zba=true", ",zba=false", d)}" +RV_QEMU_ISA .= "${@bb.utils.contains_any("TUNE_FEATURES", "b zbb", ",zbb=true", ",zbb=false", d)}" +RV_QEMU_ISA .= "${@bb.utils.contains ("TUNE_FEATURES", "zbc", ",zbc=true", ",zbc=false", d)}" +RV_QEMU_ISA .= "${@bb.utils.contains_any("TUNE_FEATURES", "b zbs", ",zbs=true", ",zbs=false", d)}" + -- 2.34.1 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH 5/6] features_check.bbclass: Add support for required TUNE_FEATURES 2025-06-16 2:29 [PATCH 0/6] ISA based RISC-V tune implementation Mark Hatle ` (3 preceding siblings ...) 2025-06-16 2:29 ` [PATCH 4/6] qemuriscv: Dynamically configure qemu CPU Mark Hatle @ 2025-06-16 2:29 ` Mark Hatle 2025-06-16 2:29 ` [PATCH 6/6] linux-yocto.inc: State riscv required tune_features Mark Hatle 2025-06-16 10:11 ` [OE-core] [PATCH 0/6] ISA based RISC-V tune implementation Gyorgy Sarvari 6 siblings, 0 replies; 15+ messages in thread From: Mark Hatle @ 2025-06-16 2:29 UTC (permalink / raw) To: openembedded-core From: Mark Hatle <mark.hatle@amd.com> Signed-off-by: Mark Hatle <mark.hatle@amd.com> --- meta/classes-recipe/features_check.bbclass | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta/classes-recipe/features_check.bbclass b/meta/classes-recipe/features_check.bbclass index 4e122ecaef..1e0eaa4eed 100644 --- a/meta/classes-recipe/features_check.bbclass +++ b/meta/classes-recipe/features_check.bbclass @@ -21,7 +21,7 @@ python () { unused = True - for kind in ['DISTRO', 'MACHINE', 'COMBINED', 'IMAGE']: + for kind in ['DISTRO', 'MACHINE', 'COMBINED', 'IMAGE', 'TUNE']: if d.getVar('ANY_OF_' + kind + '_FEATURES') is None and not d.hasOverrides('ANY_OF_' + kind + '_FEATURES') and \ d.getVar('REQUIRED_' + kind + '_FEATURES') is None and not d.hasOverrides('REQUIRED_' + kind + '_FEATURES') and \ d.getVar('CONFLICT_' + kind + '_FEATURES') is None and not d.hasOverrides('CONFLICT_' + kind + '_FEATURES'): -- 2.34.1 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH 6/6] linux-yocto.inc: State riscv required tune_features 2025-06-16 2:29 [PATCH 0/6] ISA based RISC-V tune implementation Mark Hatle ` (4 preceding siblings ...) 2025-06-16 2:29 ` [PATCH 5/6] features_check.bbclass: Add support for required TUNE_FEATURES Mark Hatle @ 2025-06-16 2:29 ` Mark Hatle 2025-06-16 11:05 ` [OE-core] " Bruce Ashfield 2025-06-16 10:11 ` [OE-core] [PATCH 0/6] ISA based RISC-V tune implementation Gyorgy Sarvari 6 siblings, 1 reply; 15+ messages in thread From: Mark Hatle @ 2025-06-16 2:29 UTC (permalink / raw) To: openembedded-core From: Mark Hatle <mark.hatle@amd.com> Required: rv32ima_zicsr_zifencei rv64ima_zicsr_zifencei See the arch/riscv/Makefile: riscv-march-$(CONFIG_ARCH_RV32I) := rv32ima riscv-march-$(CONFIG_ARCH_RV64I) := rv64ima riscv-march-$(CONFIG_TOOLCHAIN_NEEDS_EXPLICIT_ZICSR_ZIFENCEI) := $(riscv-march-y)_zicsr_zifencei Signed-off-by: Mark Hatle <mark.hatle@amd.com> --- meta/recipes-kernel/linux/linux-yocto.inc | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/meta/recipes-kernel/linux/linux-yocto.inc b/meta/recipes-kernel/linux/linux-yocto.inc index cdf2583698..80db85fe89 100644 --- a/meta/recipes-kernel/linux/linux-yocto.inc +++ b/meta/recipes-kernel/linux/linux-yocto.inc @@ -51,6 +51,11 @@ SRC_URI_RISCV = "\ SRC_URI:append:riscv32 = "${SRC_URI_RISCV}" SRC_URI:append:riscv64 = "${SRC_URI_RISCV}" +inherit features_check + +REQUIRED_TUNE_FEATURES:riscv32 = "rv 32 i m a zicsr zifencei" +REQUIRED_TUNE_FEATURES:riscv64 = "rv 64 i m a zicsr zifencei" + # A KMACHINE is the mapping of a yocto $MACHINE to what is built # by the kernel. This is typically the branch that should be built, # and it can be specific to the machine or shared -- 2.34.1 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [OE-core] [PATCH 6/6] linux-yocto.inc: State riscv required tune_features 2025-06-16 2:29 ` [PATCH 6/6] linux-yocto.inc: State riscv required tune_features Mark Hatle @ 2025-06-16 11:05 ` Bruce Ashfield 2025-06-16 14:07 ` Mark Hatle 0 siblings, 1 reply; 15+ messages in thread From: Bruce Ashfield @ 2025-06-16 11:05 UTC (permalink / raw) To: mark.hatle; +Cc: openembedded-core [-- Attachment #1: Type: text/plain, Size: 2329 bytes --] On Sun, Jun 15, 2025 at 10:29 PM Mark Hatle via lists.openembedded.org <mark.hatle=kernel.crashing.org@lists.openembedded.org> wrote: > From: Mark Hatle <mark.hatle@amd.com> > > Required: > rv32ima_zicsr_zifencei > rv64ima_zicsr_zifencei > > See the arch/riscv/Makefile: > > riscv-march-$(CONFIG_ARCH_RV32I) := rv32ima > riscv-march-$(CONFIG_ARCH_RV64I) := rv64ima > riscv-march-$(CONFIG_TOOLCHAIN_NEEDS_EXPLICIT_ZICSR_ZIFENCEI) := > $(riscv-march-y)_zicsr_zifencei > > Signed-off-by: Mark Hatle <mark.hatle@amd.com> > --- > meta/recipes-kernel/linux/linux-yocto.inc | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/meta/recipes-kernel/linux/linux-yocto.inc > b/meta/recipes-kernel/linux/linux-yocto.inc > index cdf2583698..80db85fe89 100644 > --- a/meta/recipes-kernel/linux/linux-yocto.inc > +++ b/meta/recipes-kernel/linux/linux-yocto.inc > @@ -51,6 +51,11 @@ SRC_URI_RISCV = "\ > SRC_URI:append:riscv32 = "${SRC_URI_RISCV}" > SRC_URI:append:riscv64 = "${SRC_URI_RISCV}" > > +inherit features_check > + > +REQUIRED_TUNE_FEATURES:riscv32 = "rv 32 i m a zicsr zifencei" > +REQUIRED_TUNE_FEATURES:riscv64 = "rv 64 i m a zicsr zifencei" > + > I don't think we should be enforcing this at this level. The kernel has always been responsible for setting the compiler options that it requires. And we don't check or otherwise manipulate that from the build system. What exactly are you trying to enforce / check here ? Bruce > # A KMACHINE is the mapping of a yocto $MACHINE to what is built > # by the kernel. This is typically the branch that should be built, > # and it can be specific to the machine or shared > -- > 2.34.1 > > > -=-=-=-=-=-=-=-=-=-=-=- > Links: You receive all messages sent to this group. > View/Reply Online (#218760): > https://lists.openembedded.org/g/openembedded-core/message/218760 > Mute This Topic: https://lists.openembedded.org/mt/113664657/1050810 > Group Owner: openembedded-core+owner@lists.openembedded.org > Unsubscribe: https://lists.openembedded.org/g/openembedded-core/unsub [ > bruce.ashfield@gmail.com] > -=-=-=-=-=-=-=-=-=-=-=- > > -- - Thou shalt not follow the NULL pointer, for chaos and madness await thee at its end - "Use the force Harry" - Gandalf, Star Trek II [-- Attachment #2: Type: text/html, Size: 4226 bytes --] ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [OE-core] [PATCH 6/6] linux-yocto.inc: State riscv required tune_features 2025-06-16 11:05 ` [OE-core] " Bruce Ashfield @ 2025-06-16 14:07 ` Mark Hatle 0 siblings, 0 replies; 15+ messages in thread From: Mark Hatle @ 2025-06-16 14:07 UTC (permalink / raw) To: Bruce Ashfield; +Cc: openembedded-core On 6/16/25 6:05 AM, Bruce Ashfield wrote: > > > On Sun, Jun 15, 2025 at 10:29 PM Mark Hatle via lists.openembedded.org > <http://lists.openembedded.org> > <mark.hatle=kernel.crashing.org@lists.openembedded.org > <mailto:kernel.crashing.org@lists.openembedded.org>> wrote: > > From: Mark Hatle <mark.hatle@amd.com <mailto:mark.hatle@amd.com>> > > Required: > rv32ima_zicsr_zifencei > rv64ima_zicsr_zifencei > > See the arch/riscv/Makefile: > > riscv-march-$(CONFIG_ARCH_RV32I) := rv32ima > riscv-march-$(CONFIG_ARCH_RV64I) := rv64ima > riscv-march-$(CONFIG_TOOLCHAIN_NEEDS_EXPLICIT_ZICSR_ZIFENCEI) := > $(riscv-march-y)_zicsr_zifencei > > Signed-off-by: Mark Hatle <mark.hatle@amd.com <mailto:mark.hatle@amd.com>> > --- > meta/recipes-kernel/linux/linux-yocto.inc | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/meta/recipes-kernel/linux/linux-yocto.inc > b/meta/recipes-kernel/linux/linux-yocto.inc > index cdf2583698..80db85fe89 100644 > --- a/meta/recipes-kernel/linux/linux-yocto.inc > +++ b/meta/recipes-kernel/linux/linux-yocto.inc > @@ -51,6 +51,11 @@ SRC_URI_RISCV = "\ > SRC_URI:append:riscv32 = "${SRC_URI_RISCV}" > SRC_URI:append:riscv64 = "${SRC_URI_RISCV}" > > +inherit features_check > + > +REQUIRED_TUNE_FEATURES:riscv32 = "rv 32 i m a zicsr zifencei" > +REQUIRED_TUNE_FEATURES:riscv64 = "rv 64 i m a zicsr zifencei" > + > > > I don't think we should be enforcing this at this level. The kernel has always been > responsible for setting the compiler options that it requires. And we don't > check or > otherwise manipulate that from the build system. > > What exactly are you trying to enforce / check here ? On risc-v there is a minimum risc-v ISA required by Linux, rv32ima + zicsr + zifencei (or rv64ima). The risc-v spec allows you to configure your CPU in a way that may not meet the minimum kernel requirement(s) (especially on FPGA based configurable CPUs.) Since the arch/riscv/Makefile has a minimum requirement specified in it, I added the feature check to prevent a long build and eventual runtime failure. (Since the kernel just sets whatever values it uses, you won't get a compilation failure, just a failure of "it doesn't boot".) (As an FYI, looking at how the kernel is configured and works, I doubt that there will be a future change to remove the 'm a zicsr and zifencei' requirements, the rv32i and rv64i are the base spec 32-bit and 64-bit ISAs.) --Mark > Bruce > > # A KMACHINE is the mapping of a yocto $MACHINE to what is built > # by the kernel. This is typically the branch that should be built, > # and it can be specific to the machine or shared > -- > 2.34.1 > > > -=-=-=-=-=-=-=-=-=-=-=- > Links: You receive all messages sent to this group. > View/Reply Online (#218760): > https://lists.openembedded.org/g/openembedded-core/message/218760 > <https://lists.openembedded.org/g/openembedded-core/message/218760> > Mute This Topic: https://lists.openembedded.org/mt/113664657/1050810 > <https://lists.openembedded.org/mt/113664657/1050810> > Group Owner: openembedded-core+owner@lists.openembedded.org > <mailto:openembedded-core%2Bowner@lists.openembedded.org> > Unsubscribe: https://lists.openembedded.org/g/openembedded-core/unsub > <https://lists.openembedded.org/g/openembedded-core/unsub> > [bruce.ashfield@gmail.com <mailto:bruce.ashfield@gmail.com>] > -=-=-=-=-=-=-=-=-=-=-=- > > > > -- > - Thou shalt not follow the NULL pointer, for chaos and madness await thee at > its end > - "Use the force Harry" - Gandalf, Star Trek II > ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [OE-core] [PATCH 0/6] ISA based RISC-V tune implementation 2025-06-16 2:29 [PATCH 0/6] ISA based RISC-V tune implementation Mark Hatle ` (5 preceding siblings ...) 2025-06-16 2:29 ` [PATCH 6/6] linux-yocto.inc: State riscv required tune_features Mark Hatle @ 2025-06-16 10:11 ` Gyorgy Sarvari 2025-06-16 14:12 ` Mark Hatle [not found] ` <18498B713347A8EF.22186@lists.openembedded.org> 6 siblings, 2 replies; 15+ messages in thread From: Gyorgy Sarvari @ 2025-06-16 10:11 UTC (permalink / raw) To: mark.hatle, openembedded-core On 6/16/25 04:29, Mark Hatle via lists.openembedded.org wrote: > From: Mark Hatle <mark.hatle@amd.com> > > The following implements the risc-v processor tune based on the ISA approach > as documented in the oe-architecture post: > > https://lists.openembedded.org/g/openembedded-architecture/message/2155 > > This set also attempts to make u-boot and kernel configurations dynamic > based on the TUNE_FEATURES. > > For the linux-yocto, I suspect that the config fragments should be > sent to the kmeta (kernel-cache), but I'd like a review from Bruce and > others before I do this. > > Additionally, this enables a new (optional) features_check for TUNE_FEATURES. > > I've found numerous items in the system have certain RISC-V ISA expectations > that may need to be addressed over time, however the obvious one is the > Linux kernel requires ima_zicsr_zifencei. Since it has it's own -march= > setting this will ensure the processor defintion will be compatible. > > Also dynamically configure the QEMU cpu based on the tune_features. This > is nice to ensure that what we're actually building should be able to run > on real hardware. However, it does highlight some of the (extension) > limitations in the current design. (limitations as in extension not yet > enabled.) > > Note: OpenSBI _requires_ the 'c' extension or it will not execute. I > suspect this can be fixed, but it's beyond my capabilities at this time. > I'm not a particularly advanced risc-v user, but I use qemuriscv64 to run smoketests on Firefox, with a barely-extended core-image-sato. After applying your this patch series, librsvg fails to compile with lot of "undefined reference" errors[1]. I haven't looked into this at all yet, hoping that someone would know the solution from the top of the head. Does this need some magic Rust flag maybe? Beside applying this series, I didn't do any other modifications, and without these changes librsvg builds (did I miss some new config, or another patch?) . [1]: full log: https://gist.githubusercontent.com/OldManYellsAtCloud/e9968f3c63df943e8fd54dc217ab15e6/raw ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [OE-core] [PATCH 0/6] ISA based RISC-V tune implementation 2025-06-16 10:11 ` [OE-core] [PATCH 0/6] ISA based RISC-V tune implementation Gyorgy Sarvari @ 2025-06-16 14:12 ` Mark Hatle [not found] ` <18498B713347A8EF.22186@lists.openembedded.org> 1 sibling, 0 replies; 15+ messages in thread From: Mark Hatle @ 2025-06-16 14:12 UTC (permalink / raw) To: Gyorgy Sarvari, openembedded-core, Khem Raj On 6/16/25 5:11 AM, Gyorgy Sarvari wrote: > On 6/16/25 04:29, Mark Hatle via lists.openembedded.org wrote: >> From: Mark Hatle <mark.hatle@amd.com> >> >> The following implements the risc-v processor tune based on the ISA approach >> as documented in the oe-architecture post: >> >> https://lists.openembedded.org/g/openembedded-architecture/message/2155 >> >> This set also attempts to make u-boot and kernel configurations dynamic >> based on the TUNE_FEATURES. >> >> For the linux-yocto, I suspect that the config fragments should be >> sent to the kmeta (kernel-cache), but I'd like a review from Bruce and >> others before I do this. >> >> Additionally, this enables a new (optional) features_check for TUNE_FEATURES. >> >> I've found numerous items in the system have certain RISC-V ISA expectations >> that may need to be addressed over time, however the obvious one is the >> Linux kernel requires ima_zicsr_zifencei. Since it has it's own -march= >> setting this will ensure the processor defintion will be compatible. >> >> Also dynamically configure the QEMU cpu based on the tune_features. This >> is nice to ensure that what we're actually building should be able to run >> on real hardware. However, it does highlight some of the (extension) >> limitations in the current design. (limitations as in extension not yet >> enabled.) >> >> Note: OpenSBI _requires_ the 'c' extension or it will not execute. I >> suspect this can be fixed, but it's beyond my capabilities at this time. >> > > I'm not a particularly advanced risc-v user, but I use qemuriscv64 to > run smoketests on Firefox, with a barely-extended core-image-sato. > > After applying your this patch series, librsvg fails to compile with lot > of "undefined reference" errors[1]. I haven't looked into this at all > yet, hoping that someone would know the solution from the top of the > head. Does this need some magic Rust flag maybe? > > Beside applying this series, I didn't do any other modifications, and > without these changes librsvg builds (did I miss some new config, or > another patch?) . The ONLY patch required to test this is the first one, the rest are all additional functionality based on the first patch. Honestly I have no idea how to debug this. The configuration selected: -march=rv64imafdc_zicsr_zifencei -mabi=lp64d is perfectly reasonable and contains the 'a' (atomic) operations, so I don't know how or why these atomic_loads_4 and _8 would not be defined, yet used by the compiler. I do see a reference in the error message to: .text._ZN69_$LT$smallvec..SmallVec$LT$A$GT$$u20$as$u20$core This configuration has _vector_ (v) support _disabled_. Could there be something in the toolchain that is assuming vector support is always enabled, if so that could be a large part of the problem. @Khem any ideas? > > [1]: full log: > https://gist.githubusercontent.com/OldManYellsAtCloud/e9968f3c63df943e8fd54dc217ab15e6/raw ^ permalink raw reply [flat|nested] 15+ messages in thread
[parent not found: <18498B713347A8EF.22186@lists.openembedded.org>]
* Re: [OE-core] [PATCH 0/6] ISA based RISC-V tune implementation [not found] ` <18498B713347A8EF.22186@lists.openembedded.org> @ 2025-06-16 16:00 ` Mark Hatle 0 siblings, 0 replies; 15+ messages in thread From: Mark Hatle @ 2025-06-16 16:00 UTC (permalink / raw) To: openembedded-core On 6/16/25 9:12 AM, Mark Hatle wrote: > > > On 6/16/25 5:11 AM, Gyorgy Sarvari wrote: >> On 6/16/25 04:29, Mark Hatle via lists.openembedded.org wrote: >>> From: Mark Hatle <mark.hatle@amd.com> >>> >>> The following implements the risc-v processor tune based on the ISA approach >>> as documented in the oe-architecture post: >>> >>> https://lists.openembedded.org/g/openembedded-architecture/message/2155 >>> >>> This set also attempts to make u-boot and kernel configurations dynamic >>> based on the TUNE_FEATURES. >>> >>> For the linux-yocto, I suspect that the config fragments should be >>> sent to the kmeta (kernel-cache), but I'd like a review from Bruce and >>> others before I do this. >>> >>> Additionally, this enables a new (optional) features_check for TUNE_FEATURES. >>> >>> I've found numerous items in the system have certain RISC-V ISA expectations >>> that may need to be addressed over time, however the obvious one is the >>> Linux kernel requires ima_zicsr_zifencei. Since it has it's own -march= >>> setting this will ensure the processor defintion will be compatible. >>> >>> Also dynamically configure the QEMU cpu based on the tune_features. This >>> is nice to ensure that what we're actually building should be able to run >>> on real hardware. However, it does highlight some of the (extension) >>> limitations in the current design. (limitations as in extension not yet >>> enabled.) >>> >>> Note: OpenSBI _requires_ the 'c' extension or it will not execute. I >>> suspect this can be fixed, but it's beyond my capabilities at this time. >>> >> >> I'm not a particularly advanced risc-v user, but I use qemuriscv64 to >> run smoketests on Firefox, with a barely-extended core-image-sato. >> >> After applying your this patch series, librsvg fails to compile with lot >> of "undefined reference" errors[1]. I haven't looked into this at all >> yet, hoping that someone would know the solution from the top of the >> head. Does this need some magic Rust flag maybe? >> >> Beside applying this series, I didn't do any other modifications, and >> without these changes librsvg builds (did I miss some new config, or >> another patch?) . > > The ONLY patch required to test this is the first one, the rest are all > additional functionality based on the first patch. > > Honestly I have no idea how to debug this. The configuration selected: > > -march=rv64imafdc_zicsr_zifencei -mabi=lp64d > > is perfectly reasonable and contains the 'a' (atomic) operations, so I don't > know how or why these atomic_loads_4 and _8 would not be defined, yet used by > the compiler. > > I do see a reference in the error message to: > > .text._ZN69_$LT$smallvec..SmallVec$LT$A$GT$$u20$as$u20$core > > This configuration has _vector_ (v) support _disabled_. > > Could there be something in the toolchain that is assuming vector support is > always enabled, if so that could be a large part of the problem. > > @Khem any ideas? I've reproduced the issue. This due to RUST. I'm also getting additional error messages about the ABI being incorrect (it's definitely not incorrect), so rust itself is configured in correctly after this change. Still investigating. --Mark >> >> [1]: full log: >> https://gist.githubusercontent.com/OldManYellsAtCloud/e9968f3c63df943e8fd54dc217ab15e6/raw >> >> >> -=-=-=-=-=-=-=-=-=-=-=- >> Links: You receive all messages sent to this group. >> View/Reply Online (#218827): https://lists.openembedded.org/g/openembedded-core/message/218827 >> Mute This Topic: https://lists.openembedded.org/mt/113664652/3616948 >> Group Owner: openembedded-core+owner@lists.openembedded.org >> Unsubscribe: https://lists.openembedded.org/g/openembedded-core/unsub [mark.hatle@kernel.crashing.org] >> -=-=-=-=-=-=-=-=-=-=-=- >> ^ permalink raw reply [flat|nested] 15+ messages in thread
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2025-06-16 2:29 [PATCH 0/6] ISA based RISC-V tune implementation Mark Hatle
2025-06-16 2:29 ` [PATCH 1/6] riscv tunes: ISA Implementation of RISC-V tune features Mark Hatle
2025-06-16 10:11 ` [OE-core] " Richard Purdie
2025-06-16 14:21 ` Mark Hatle
2025-06-16 2:29 ` [PATCH 2/6] linux-yocto: Enable risc-v TUNE_FEATURES ISA selections Mark Hatle
2025-06-16 10:50 ` Bruce Ashfield
2025-06-16 2:29 ` [PATCH 3/6] u-boot: Dynamic RISC-V ISA configuration Mark Hatle
2025-06-16 2:29 ` [PATCH 4/6] qemuriscv: Dynamically configure qemu CPU Mark Hatle
2025-06-16 2:29 ` [PATCH 5/6] features_check.bbclass: Add support for required TUNE_FEATURES Mark Hatle
2025-06-16 2:29 ` [PATCH 6/6] linux-yocto.inc: State riscv required tune_features Mark Hatle
2025-06-16 11:05 ` [OE-core] " Bruce Ashfield
2025-06-16 14:07 ` Mark Hatle
2025-06-16 10:11 ` [OE-core] [PATCH 0/6] ISA based RISC-V tune implementation Gyorgy Sarvari
2025-06-16 14:12 ` Mark Hatle
[not found] ` <18498B713347A8EF.22186@lists.openembedded.org>
2025-06-16 16:00 ` Mark Hatle
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