* [PATCH 01/24] linux-yocto: depend on libgcc for aarch64
2014-11-07 8:51 [PATCH 00/24] V2: Add machine qemuarm64 Kai Kang
@ 2014-11-07 8:51 ` Kai Kang
2014-11-07 8:51 ` [PATCH 02/24] Add machine qemuarm64 Kai Kang
` (24 subsequent siblings)
25 siblings, 0 replies; 51+ messages in thread
From: Kai Kang @ 2014-11-07 8:51 UTC (permalink / raw)
To: ross.burton; +Cc: koen.kooi, openembedded-core
Make aarch aarch64 kernel depend on libgcc.
In arch/arm64/Makefile, it adds LIBGCC to libs-y:
LIBGCC := $(shell $(CC) $(KBUILD_CFLAGS) -print-libgcc-file-name)
libs-y += $(LIBGCC)
In file Makefile in top directory, libs-y is assigned to to var
KBUILD_VMLINUX_MAIN. It uses script link-vmlinux.sh to link vmlinux.o,
and when execute function vmlinux_link() in link-vmlinux.sh,
KBUILD_VMLINUX_MAIN is passed to ${LD}.
If build without libgcc, the value of LIBGCC is just libgcc.a without
parent directory. linux-yocto fails to build:
| LD vmlinux.o
| aarch64-poky-linux-ld.bfd: cannot find libgcc.a: No such file or directory
Add libgcc to aarch64 kernel dependency.
Signed-off-by: Kai Kang <kai.kang@windriver.com>
---
meta/recipes-kernel/linux/linux-yocto.inc | 1 +
1 file changed, 1 insertion(+)
diff --git a/meta/recipes-kernel/linux/linux-yocto.inc b/meta/recipes-kernel/linux/linux-yocto.inc
index 4ed3188..9018985 100644
--- a/meta/recipes-kernel/linux/linux-yocto.inc
+++ b/meta/recipes-kernel/linux/linux-yocto.inc
@@ -7,6 +7,7 @@ LIC_FILES_CHKSUM = "file://COPYING;md5=d7810fab7487fb0aad327b76f1be7cd7"
INC_PR = "r4"
DEPENDS += "xz-native bc-native"
+DEPENDS_append_aarch64 = " libgcc"
# A KMACHINE is the mapping of a yocto $MACHINE to what is built
# by the kernel. This is typically the branch that should be built,
--
1.9.1
^ permalink raw reply related [flat|nested] 51+ messages in thread* [PATCH 02/24] Add machine qemuarm64
2014-11-07 8:51 [PATCH 00/24] V2: Add machine qemuarm64 Kai Kang
2014-11-07 8:51 ` [PATCH 01/24] linux-yocto: depend on libgcc for aarch64 Kai Kang
@ 2014-11-07 8:51 ` Kai Kang
2014-11-07 8:51 ` [PATCH 03/24] siteinfo: account for 32 and 64 bit arm Kai Kang
` (23 subsequent siblings)
25 siblings, 0 replies; 51+ messages in thread
From: Kai Kang @ 2014-11-07 8:51 UTC (permalink / raw)
To: ross.burton; +Cc: koen.kooi, openembedded-core
Add machine qemuarm64. The configure files are derived from linaro.
Update:
* rename genericarmv8 to qemuarm64 for coordination in oe-core
* include qemu.inc then remove common part of config
* disable using autoserial
* move arch-armv8.inc from machine/include/arm64 to machine/include/arm
[YOCTO #6487]
Signed-off-by: Kai Kang <kai.kang@windriver.com>
---
meta/conf/machine/include/arm/arch-armv8.inc | 20 ++++++++++++++++++++
meta/conf/machine/qemuarm64.conf | 12 ++++++++++++
2 files changed, 32 insertions(+)
create mode 100644 meta/conf/machine/include/arm/arch-armv8.inc
create mode 100644 meta/conf/machine/qemuarm64.conf
diff --git a/meta/conf/machine/include/arm/arch-armv8.inc b/meta/conf/machine/include/arm/arch-armv8.inc
new file mode 100644
index 0000000..c86142a
--- /dev/null
+++ b/meta/conf/machine/include/arm/arch-armv8.inc
@@ -0,0 +1,20 @@
+DEFAULTTUNE ?= "aarch64"
+
+ARMPKGARCH ?= "aarch64"
+
+TUNEVALID[aarch64] = "Enable instructions for aarch64"
+TUNEVALID[bigendian] = "Enable big-endian mode."
+TUNECONFLICTS[aarch64] = ""
+MACHINEOVERRIDES .= "${@bb.utils.contains("TUNE_FEATURES", "aarch64", ":aarch64", "" ,d)}"
+
+# Little Endian base configs
+AVAILTUNES += "aarch64 aarch64_be"
+TUNE_FEATURES_tune-aarch64 ?= "aarch64"
+TUNE_FEATURES_tune-aarch64_be ?= "${TUNE_FEATURES_tune-aarch64} bigendian"
+
+ARMPKGSFX_ENDIAN = "${@bb.utils.contains("TUNE_FEATURES", "bigendian", "_be", "", d)}"
+
+TUNE_ARCH = "aarch64${ARMPKGSFX_ENDIAN}"
+TUNE_PKGARCH = "aarch64${ARMPKGSFX_ENDIAN}"
+
+PACKAGE_EXTRA_ARCHS = "aarch64${ARMPKGSFX_ENDIAN}"
diff --git a/meta/conf/machine/qemuarm64.conf b/meta/conf/machine/qemuarm64.conf
new file mode 100644
index 0000000..20bcfba
--- /dev/null
+++ b/meta/conf/machine/qemuarm64.conf
@@ -0,0 +1,12 @@
+#@TYPE: Machine
+#@NAME: generic armv8 machine
+#@DESCRIPTION: Machine configuration for running a generic armv8
+
+require conf/machine/include/arm/arch-armv8.inc
+require conf/machine/include/qemu.inc
+
+MACHINE_FEATURES = ""
+
+KERNEL_IMAGETYPE = "Image"
+
+SERIAL_CONSOLE = "38400 ttyAMA0"
--
1.9.1
^ permalink raw reply related [flat|nested] 51+ messages in thread* [PATCH 03/24] siteinfo: account for 32 and 64 bit arm
2014-11-07 8:51 [PATCH 00/24] V2: Add machine qemuarm64 Kai Kang
2014-11-07 8:51 ` [PATCH 01/24] linux-yocto: depend on libgcc for aarch64 Kai Kang
2014-11-07 8:51 ` [PATCH 02/24] Add machine qemuarm64 Kai Kang
@ 2014-11-07 8:51 ` Kai Kang
2014-11-07 8:51 ` [PATCH 04/24] gcc-4.9: redefine default library install directory Kai Kang
` (22 subsequent siblings)
25 siblings, 0 replies; 51+ messages in thread
From: Kai Kang @ 2014-11-07 8:51 UTC (permalink / raw)
To: ross.burton; +Cc: koen.kooi, openembedded-core
From: Joe Slater <jslater@windriver.com>
Pull wordsize related items from arm-common and put in
arm-32. Leave them as they were. Copy arm-32 to arm-64
and comment out all variables. Re-define to correct
values leaving items which do not appear to be used
undefined.
Signed-off-by: Joe Slater <jslater@windriver.com>
---
meta/classes/siteinfo.bbclass | 8 ++++----
meta/site/arm-32 | 47 +++++++++++++++++++++++++++++++++++++++++++
meta/site/arm-64 | 46 ++++++++++++++++++++++++++++++++++++++++++
meta/site/arm-common | 38 ----------------------------------
4 files changed, 97 insertions(+), 42 deletions(-)
create mode 100644 meta/site/arm-32
create mode 100644 meta/site/arm-64
diff --git a/meta/classes/siteinfo.bbclass b/meta/classes/siteinfo.bbclass
index e90632a..b41db46 100644
--- a/meta/classes/siteinfo.bbclass
+++ b/meta/classes/siteinfo.bbclass
@@ -18,10 +18,10 @@
def siteinfo_data(d):
archinfo = {
"allarch": "endian-little bit-32", # bogus, but better than special-casing the checks below for allarch
- "aarch64": "endian-little bit-64 arm-common",
- "aarch64_be": "endian-big bit-64 arm-common",
- "arm": "endian-little bit-32 arm-common",
- "armeb": "endian-big bit-32 arm-common",
+ "aarch64": "endian-little bit-64 arm-common arm-64",
+ "aarch64_be": "endian-big bit-64 arm-common arm-64",
+ "arm": "endian-little bit-32 arm-common arm-32",
+ "armeb": "endian-big bit-32 arm-common arm-32",
"avr32": "endian-big bit-32 avr32-common",
"bfin": "endian-little bit-32 bfin-common",
"i386": "endian-little bit-32 ix86-common",
diff --git a/meta/site/arm-32 b/meta/site/arm-32
new file mode 100644
index 0000000..81fd8d3
--- /dev/null
+++ b/meta/site/arm-32
@@ -0,0 +1,47 @@
+# definitions assuming 32-bit arm architecture
+
+# apache
+ac_cv_sizeof_size_t=${ac_cv_sizeof_size_t=4}
+ac_cv_sizeof_ssize_t=${ac_cv_sizeof_ssize_t=4}
+
+# glib
+glib_cv_sizeof_gmutex=${glib_cv_sizeof_gmutex=24}
+glib_cv_sizeof_system_thread=${glib_cv_sizeof_system_thread=4}
+glib_cv_sizeof_gmutex=${glib_cv_sizeof_gmutex=24}
+
+# glib-2.0
+glib_cv_sizeof_gmutex=${glib_cv_sizeof_gmutex=24}
+glib_cv_sizeof_intmax_t=${glib_cv_sizeof_intmax_t=8}
+glib_cv_sizeof_ptrdiff_t=${glib_cv_sizeof_ptrdiff_t=4}
+glib_cv_sizeof_size_t=${glib_cv_sizeof_size_t=4}
+glib_cv_sizeof_system_thread=${glib_cv_sizeof_system_thread=4}
+ac_cv_alignof_guint32=4
+ac_cv_alignof_guint64=8
+ac_cv_alignof_unsigned_long=4
+
+# jikes
+ac_cv_sizeof_wchar_t=4
+
+# ORBit2
+ac_cv_alignof_CORBA_boolean=1
+ac_cv_alignof_CORBA_char=1
+ac_cv_alignof_CORBA_double=8
+ac_cv_alignof_CORBA_float=4
+ac_cv_alignof_CORBA_long=4
+ac_cv_alignof_CORBA_long_double=8
+ac_cv_alignof_CORBA_long_long=8
+ac_cv_alignof_CORBA_octet=1
+ac_cv_alignof_CORBA_pointer=4
+ac_cv_alignof_CORBA_short=2
+ac_cv_alignof_CORBA_struct=1
+ac_cv_alignof_CORBA_wchar=2
+
+# at-spi2-core
+ac_cv_alignof_char=1
+ac_cv_alignof_dbind_pointer=4
+ac_cv_alignof_dbind_struct=1
+ac_cv_alignof_dbus_bool_t=4
+ac_cv_alignof_dbus_int16_t=2
+ac_cv_alignof_dbus_int32_t=4
+ac_cv_alignof_dbus_int64_t=8
+ac_cv_alignof_double=8
diff --git a/meta/site/arm-64 b/meta/site/arm-64
new file mode 100644
index 0000000..90c09b2d54
--- /dev/null
+++ b/meta/site/arm-64
@@ -0,0 +1,46 @@
+# definitions assuming 64-bit arm architecture
+
+# general
+ac_cv_sizeof_wchar_t=4
+ac_cv_sizeof_size_t=8
+ac_cv_sizeof_ssize_t=8
+ac_cv_alignof_char=1
+ac_cv_alignof_double=8
+
+# glib
+#glib_cv_sizeof_gmutex=${glib_cv_sizeof_gmutex=24}
+#glib_cv_sizeof_system_thread=${glib_cv_sizeof_system_thread=4}
+#glib_cv_sizeof_gmutex=${glib_cv_sizeof_gmutex=24}
+
+# glib-2.0
+#glib_cv_sizeof_gmutex=${glib_cv_sizeof_gmutex=24}
+#glib_cv_sizeof_intmax_t=${glib_cv_sizeof_intmax_t=8}
+#glib_cv_sizeof_ptrdiff_t=${glib_cv_sizeof_ptrdiff_t=4}
+#glib_cv_sizeof_size_t=${glib_cv_sizeof_size_t=4}
+#glib_cv_sizeof_system_thread=${glib_cv_sizeof_system_thread=4}
+ac_cv_alignof_guint32=4
+ac_cv_alignof_guint64=8
+ac_cv_alignof_unsigned_long=8
+
+# ORBit2 (should be in meta-gnome/site/arm-64)
+#ac_cv_alignof_CORBA_boolean=1
+#ac_cv_alignof_CORBA_char=1
+#ac_cv_alignof_CORBA_double=8
+#ac_cv_alignof_CORBA_float=4
+#ac_cv_alignof_CORBA_long=4
+#ac_cv_alignof_CORBA_long_double=8
+#ac_cv_alignof_CORBA_long_long=8
+#ac_cv_alignof_CORBA_octet=1
+#ac_cv_alignof_CORBA_pointer=4
+#ac_cv_alignof_CORBA_short=2
+#ac_cv_alignof_CORBA_struct=1
+#ac_cv_alignof_CORBA_wchar=2
+
+# at-spi2-core
+ac_cv_alignof_dbind_pointer=8
+ac_cv_alignof_dbind_struct=1
+ac_cv_alignof_dbus_bool_t=4
+ac_cv_alignof_dbus_int16_t=2
+ac_cv_alignof_dbus_int32_t=4
+ac_cv_alignof_dbus_int64_t=8
+
diff --git a/meta/site/arm-common b/meta/site/arm-common
index 1893dc0..12e5d45 100644
--- a/meta/site/arm-common
+++ b/meta/site/arm-common
@@ -11,7 +11,6 @@ ac_cv_sctp=${ac_cv_sctp=no}
# apache
ac_cv_func_pthread_key_delete=${ac_cv_func_pthread_key_delete=yes}
apr_cv_process_shared_works=${apr_cv_process_shared_works=no}
-ac_cv_sizeof_ssize_t=${ac_cv_sizeof_ssize_t=4}
apr_cv_tcp_nodelay_with_cork=${apr_cv_tcp_nodelay_with_cork=yes}
# bash
@@ -51,8 +50,6 @@ ac_cv_func_fnmatch_works=${ac_cv_func_fnmatch_works=yes}
am_cv_func_working_getline=${am_cv_func_working_getline=yes}
# glib
-glib_cv_sizeof_gmutex=${glib_cv_sizeof_gmutex=24}
-glib_cv_sizeof_system_thread=${glib_cv_sizeof_system_thread=4}
glib_cv_stack_grows=${glib_cv_stack_grows=no}
glib_cv_uscore=${glib_cv_uscore=no}
glib_cv_use_pid_surrogate=${glib_cv_use_pid_surrogate=yes}
@@ -60,7 +57,6 @@ glib_cv_has__inline=${glib_cv_has__inline=yes}
glib_cv_has__inline__=${glib_cv_has__inline__=yes}
glib_cv_hasinline=${glib_cv_hasinline=yes}
glib_cv_sane_realloc=${glib_cv_sane_realloc=yes}
-glib_cv_sizeof_gmutex=${glib_cv_sizeof_gmutex=24}
glib_cv_uscore=${glib_cv_uscore=no}
glib_cv_va_val_copy=${glib_cv_va_val_copy=yes}
glib_cv_rtldglobal_broken=${glib_cv_rtldglobal_broken=no}
@@ -70,15 +66,7 @@ glib_cv_sys_pthread_cond_timedwait_posix=${glib_cv_sys_pthread_cond_timedwait_po
# glib-2.0
glib_cv_long_long_format=${glib_cv_long_long_format=ll}
-glib_cv_sizeof_gmutex=${glib_cv_sizeof_gmutex=24}
-glib_cv_sizeof_intmax_t=${glib_cv_sizeof_intmax_t=8}
-glib_cv_sizeof_ptrdiff_t=${glib_cv_sizeof_ptrdiff_t=4}
-glib_cv_sizeof_size_t=${glib_cv_sizeof_size_t=4}
-glib_cv_sizeof_system_thread=${glib_cv_sizeof_system_thread=4}
glib_cv_sys_use_pid_niceness_surrogate=${glib_cv_sys_use_pid_niceness_surrogate=yes}
-ac_cv_alignof_guint32=4
-ac_cv_alignof_guint64=8
-ac_cv_alignof_unsigned_long=4
#gstreamer
as_cv_unaligned_access=${as_cv_unaligned_access=no}
@@ -86,9 +74,6 @@ as_cv_unaligned_access=${as_cv_unaligned_access=no}
# httppc
ac_cv_strerror_r_SUSv3=${ac_cv_strerror_r_SUSv3=no}
-# jikes
-ac_cv_sizeof_wchar_t=4
-
# lftp
ac_cv_need_trio=${ac_cv_need_trio=no}
lftp_cv_va_val_copy=${lftp_cv_va_val_copy=yes}
@@ -119,20 +104,6 @@ mysql_cv_func_atomic_add=${mysql_cv_func_atomic_add=no}
ac_cv_regexec_segfault_emptystr=${ac_cv_regexec_segfault_emptystr=no}
nano_cv_func_regexec_segv_emptystr=${nano_cv_func_regexec_segv_emptystr=no}
-# ORBit2
-ac_cv_alignof_CORBA_boolean=1
-ac_cv_alignof_CORBA_char=1
-ac_cv_alignof_CORBA_double=8
-ac_cv_alignof_CORBA_float=4
-ac_cv_alignof_CORBA_long=4
-ac_cv_alignof_CORBA_long_double=8
-ac_cv_alignof_CORBA_long_long=8
-ac_cv_alignof_CORBA_octet=1
-ac_cv_alignof_CORBA_pointer=4
-ac_cv_alignof_CORBA_short=2
-ac_cv_alignof_CORBA_struct=1
-ac_cv_alignof_CORBA_wchar=2
-
# php
ac_cv_pread=${ac_cv_pread=no}
ac_cv_pwrite=${ac_cv_pwrite=no}
@@ -186,12 +157,3 @@ jm_cv_func_working_readdir=yes
# evolution-data-server
ac_cv_libiconv_utf8=${ac_cv_libiconv_utf8=yes}
-# at-spi2-core
-ac_cv_alignof_char=1
-ac_cv_alignof_dbind_pointer=4
-ac_cv_alignof_dbind_struct=1
-ac_cv_alignof_dbus_bool_t=4
-ac_cv_alignof_dbus_int16_t=2
-ac_cv_alignof_dbus_int32_t=4
-ac_cv_alignof_dbus_int64_t=8
-ac_cv_alignof_double=8
--
1.9.1
^ permalink raw reply related [flat|nested] 51+ messages in thread* [PATCH 04/24] gcc-4.9: redefine default library install directory
2014-11-07 8:51 [PATCH 00/24] V2: Add machine qemuarm64 Kai Kang
` (2 preceding siblings ...)
2014-11-07 8:51 ` [PATCH 03/24] siteinfo: account for 32 and 64 bit arm Kai Kang
@ 2014-11-07 8:51 ` Kai Kang
2014-11-07 8:51 ` [PATCH 05/24] libc-package.bbclass: add aarch64 target to locale_arch_options Kai Kang
` (21 subsequent siblings)
25 siblings, 0 replies; 51+ messages in thread
From: Kai Kang @ 2014-11-07 8:51 UTC (permalink / raw)
To: ross.burton; +Cc: koen.kooi, openembedded-core
Packages use 'aarch64-poky-linux-gcc -print-multi-os-directory' to get
the value of install directory. The value is set by MULTILIB_OSDIRNAMES
and default is '/lib64'. And the dynamic linker ld-linux-aarch64.so.1
from package eglibc is installed to /lib64.
But the default dynamic linker defined in gcc/config/aarch64/aarch64-linux.h
is:
MULTILIB_OSDIRNAMES = .=../lib64$(call if_multiarch,:aarch64$(AARCH_BE)-linux-gnu)
Then cause all the ELF files fail to launch because fail to find the
linker and libraries.
Redefine default library install directory to /lib to fix this issue.
Signed-off-by: Kai Kang <kai.kang@windriver.com>
---
meta/recipes-devtools/gcc/gcc-4.9.inc | 1 +
...0099-gcc-redefine-library-dir-for-aarch64.patch | 29 ++++++++++++++++++++++
2 files changed, 30 insertions(+)
create mode 100644 meta/recipes-devtools/gcc/gcc-4.9/0099-gcc-redefine-library-dir-for-aarch64.patch
diff --git a/meta/recipes-devtools/gcc/gcc-4.9.inc b/meta/recipes-devtools/gcc/gcc-4.9.inc
index 8f212b2..e3775cd 100644
--- a/meta/recipes-devtools/gcc/gcc-4.9.inc
+++ b/meta/recipes-devtools/gcc/gcc-4.9.inc
@@ -73,6 +73,7 @@ SRC_URI = "\
file://0056-top-level-reorder_gcc-bug-61144.patch \
file://0058-gcc-r212171.patch \
file://0059-gcc-PR-rtl-optimization-63348.patch \
+ file://0099-gcc-redefine-library-dir-for-aarch64.patch \
"
SRC_URI[md5sum] = "fddf71348546af523353bd43d34919c1"
SRC_URI[sha256sum] = "d334781a124ada6f38e63b545e2a3b8c2183049515a1abab6d513f109f1d717e"
diff --git a/meta/recipes-devtools/gcc/gcc-4.9/0099-gcc-redefine-library-dir-for-aarch64.patch b/meta/recipes-devtools/gcc/gcc-4.9/0099-gcc-redefine-library-dir-for-aarch64.patch
new file mode 100644
index 0000000..23cdb95
--- /dev/null
+++ b/meta/recipes-devtools/gcc/gcc-4.9/0099-gcc-redefine-library-dir-for-aarch64.patch
@@ -0,0 +1,29 @@
+Redefine default library directory for aarch64.
+
+Packages use 'aarch64-poky-linux-gcc -print-multi-os-directory' to get the
+value of install directory. The value is set by MULTILIB_OSDIRNAMES and default
+is '/lib64'. Add the dynamic linker ld-linux-aarch64.so.1 from package eglibc
+is installed to /lib64.
+
+But the default dynamic linker defined in gcc/config/aarch64/aarch64-linux.h
+is:
+
+#define GLIBC_DYNAMIC_LINKER "/lib/ld-linux-aarch64%{mbig-endian:_be}.so.1"
+
+Then cause all the ELF files fail to launch because fail to find the linker.
+
+Upstream-Status: Pending
+
+Signed-off-by: Kai Kang <kai.kang@windriver.com>
+---
+--- gcc-4.9.1/gcc/config/aarch64/t-aarch64-linux.orig 2014-09-19 14:38:47.550669143 +0800
++++ gcc-4.9.1/gcc/config/aarch64/t-aarch64-linux 2014-09-19 14:39:01.234669516 +0800
+@@ -22,7 +22,7 @@
+ LIB1ASMFUNCS = _aarch64_sync_cache_range
+
+ AARCH_BE = $(if $(findstring TARGET_BIG_ENDIAN_DEFAULT=1, $(tm_defines)),_be)
+-MULTILIB_OSDIRNAMES = .=../lib64$(call if_multiarch,:aarch64$(AARCH_BE)-linux-gnu)
++MULTILIB_OSDIRNAMES = .=../lib$(call if_multiarch,:aarch64$(AARCH_BE)-linux-gnu)
+ MULTIARCH_DIRNAME = $(call if_multiarch,aarch64$(AARCH_BE)-linux-gnu)
+
+ # Disable the multilib for linux-gnu targets for the time being; focus
--
1.9.1
^ permalink raw reply related [flat|nested] 51+ messages in thread* [PATCH 05/24] libc-package.bbclass: add aarch64 target to locale_arch_options
2014-11-07 8:51 [PATCH 00/24] V2: Add machine qemuarm64 Kai Kang
` (3 preceding siblings ...)
2014-11-07 8:51 ` [PATCH 04/24] gcc-4.9: redefine default library install directory Kai Kang
@ 2014-11-07 8:51 ` Kai Kang
2014-11-07 8:51 ` [PATCH 06/24] glibc-locale.inc: add aarch64 to BINARY_LOCALE_ARCHES Kai Kang
` (20 subsequent siblings)
25 siblings, 0 replies; 51+ messages in thread
From: Kai Kang @ 2014-11-07 8:51 UTC (permalink / raw)
To: ross.burton; +Cc: koen.kooi, openembedded-core
Add aarch64 target to locale_arch_options in libc-package.bbclass to
support Arm V8.
Signed-off-by: Kai Kang <kai.kang@windriver.com>
---
meta/classes/libc-package.bbclass | 1 +
1 file changed, 1 insertion(+)
diff --git a/meta/classes/libc-package.bbclass b/meta/classes/libc-package.bbclass
index c1bc399..5701e20 100644
--- a/meta/classes/libc-package.bbclass
+++ b/meta/classes/libc-package.bbclass
@@ -268,6 +268,7 @@ python package_do_split_gconvs () {
locale_arch_options = { \
"arm": " --uint32-align=4 --little-endian ", \
"armeb": " --uint32-align=4 --big-endian ", \
+ "aarch64": " --uint32-align=4 --little-endian ", \
"aarch64_be": " --uint32-align=4 --big-endian ", \
"sh4": " --uint32-align=4 --big-endian ", \
"powerpc": " --uint32-align=4 --big-endian ", \
--
1.9.1
^ permalink raw reply related [flat|nested] 51+ messages in thread* [PATCH 06/24] glibc-locale.inc: add aarch64 to BINARY_LOCALE_ARCHES
2014-11-07 8:51 [PATCH 00/24] V2: Add machine qemuarm64 Kai Kang
` (4 preceding siblings ...)
2014-11-07 8:51 ` [PATCH 05/24] libc-package.bbclass: add aarch64 target to locale_arch_options Kai Kang
@ 2014-11-07 8:51 ` Kai Kang
2014-11-07 8:51 ` [PATCH 07/24] libatomics-ops: add aarch64 target iniitial support Kai Kang
` (19 subsequent siblings)
25 siblings, 0 replies; 51+ messages in thread
From: Kai Kang @ 2014-11-07 8:51 UTC (permalink / raw)
To: ross.burton; +Cc: koen.kooi, openembedded-core
Add aarch64 to var BINARY_LOCALE_ARCHES. In libc-packages.class, it is
used to work with other vars to check and add cross-localedef-native as
a dependecy correctly.
Signed-off-by: Kai Kang <kai.kang@windriver.com>
---
meta/recipes-core/glibc/glibc-locale.inc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/meta/recipes-core/glibc/glibc-locale.inc b/meta/recipes-core/glibc/glibc-locale.inc
index d472605..df6d073 100644
--- a/meta/recipes-core/glibc/glibc-locale.inc
+++ b/meta/recipes-core/glibc/glibc-locale.inc
@@ -23,7 +23,7 @@ ENABLE_BINARY_LOCALE_GENERATION_pn-nativesdk-glibc-locale = "0"
#enable locale generation on these arches
# BINARY_LOCALE_ARCHES is a space separated list of regular expressions
-BINARY_LOCALE_ARCHES ?= "arm.* i[3-6]86 x86_64 powerpc mips mips64"
+BINARY_LOCALE_ARCHES ?= "arm.* aarch64 i[3-6]86 x86_64 powerpc mips mips64"
# set "1" to use cross-localedef for locale generation
# set "0" for qemu emulation of native localedef for locale generation
--
1.9.1
^ permalink raw reply related [flat|nested] 51+ messages in thread* [PATCH 07/24] libatomics-ops: add aarch64 target iniitial support
2014-11-07 8:51 [PATCH 00/24] V2: Add machine qemuarm64 Kai Kang
` (5 preceding siblings ...)
2014-11-07 8:51 ` [PATCH 06/24] glibc-locale.inc: add aarch64 to BINARY_LOCALE_ARCHES Kai Kang
@ 2014-11-07 8:51 ` Kai Kang
2014-11-07 8:51 ` [PATCH 08/24] qt4: add aarch64 support Kai Kang
` (18 subsequent siblings)
25 siblings, 0 replies; 51+ messages in thread
From: Kai Kang @ 2014-11-07 8:51 UTC (permalink / raw)
To: ross.burton; +Cc: koen.kooi, openembedded-core
Add patch for libatomics-ops to add aarch64 target iniitial
support. It is from linaro repo.
Signed-off-by: Kai Kang <kai.kang@windriver.com>
---
.../0001-libatomic_ops-Aarch64-basic-port.patch | 239 +++++++++++++++++++++
.../pulseaudio/libatomics-ops_7.2.bb | 1 +
2 files changed, 240 insertions(+)
create mode 100644 meta/recipes-multimedia/pulseaudio/files/0001-libatomic_ops-Aarch64-basic-port.patch
diff --git a/meta/recipes-multimedia/pulseaudio/files/0001-libatomic_ops-Aarch64-basic-port.patch b/meta/recipes-multimedia/pulseaudio/files/0001-libatomic_ops-Aarch64-basic-port.patch
new file mode 100644
index 0000000..a563b8b
--- /dev/null
+++ b/meta/recipes-multimedia/pulseaudio/files/0001-libatomic_ops-Aarch64-basic-port.patch
@@ -0,0 +1,239 @@
+From aac120d778ae5fc619b2fb8ef18ea18d3d5d20cc Mon Sep 17 00:00:00 2001
+From: Yvan Roux <yvan.roux@linaro.org>
+Date: Wed, 23 Jan 2013 17:14:16 +0100
+Subject: [PATCH] Aarch64 basic port
+
+Adapted-for-OpenEmbedded-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
+
+
+Upstream-Status: Backport
+
+It is original from
+https://github.com/ivmai/libatomic_ops/commit/cbbf86330fcb600cfe0f895cb970d922456005d6
+
+Signed-off-by: Kai Kang <kai.kang@windriver.com>
+---
+ src/atomic_ops.h | 4
+ src/atomic_ops/sysdeps/Makefile.am | 1
+ src/atomic_ops/sysdeps/gcc/aarch64.h | 184 +++++++++++++++++++++++++++++++++++
+ 3 files changed, 189 insertions(+)
+ create mode 100644 src/atomic_ops/sysdeps/gcc/aarch64.h
+
+--- libatomic_ops-7.2.orig/src/atomic_ops.h
++++ libatomic_ops-7.2/src/atomic_ops.h
+@@ -242,10 +242,14 @@
+ # endif /* __m68k__ */
+ # if defined(__powerpc__) || defined(__ppc__) || defined(__PPC__) \
+ || defined(__powerpc64__) || defined(__ppc64__)
+ # include "atomic_ops/sysdeps/gcc/powerpc.h"
+ # endif /* __powerpc__ */
++# if defined(__aarch64__)
++# include "atomic_ops/sysdeps/gcc/aarch64.h"
++# define AO_CAN_EMUL_CAS
++# endif /* __aarch64__ */
+ # if defined(__arm__) && !defined(AO_USE_PTHREAD_DEFS)
+ # include "atomic_ops/sysdeps/gcc/arm.h"
+ # define AO_CAN_EMUL_CAS
+ # endif /* __arm__ */
+ # if defined(__cris__) || defined(CRIS)
+--- libatomic_ops-7.2.orig/src/atomic_ops/sysdeps/Makefile.am
++++ libatomic_ops-7.2/src/atomic_ops/sysdeps/Makefile.am
+@@ -24,10 +24,11 @@ nobase_sysdep_HEADERS= generic_pthread.h
+ standard_ao_double_t.h \
+ README \
+ \
+ armcc/arm_v6.h \
+ \
++ gcc/aarch64.h \
+ gcc/alpha.h gcc/arm.h gcc/avr32.h gcc/cris.h \
+ gcc/hexagon.h gcc/hppa.h gcc/ia64.h gcc/m68k.h \
+ gcc/mips.h gcc/powerpc.h gcc/s390.h \
+ gcc/sh.h gcc/sparc.h gcc/x86.h gcc/x86_64.h \
+ \
+--- /dev/null
++++ libatomic_ops-7.2/src/atomic_ops/sysdeps/gcc/aarch64.h
+@@ -0,0 +1,184 @@
++/*
++ * Copyright (c) 1991-1994 by Xerox Corporation. All rights reserved.
++ * Copyright (c) 1996-1999 by Silicon Graphics. All rights reserved.
++ * Copyright (c) 1999-2003 by Hewlett-Packard Company. All rights reserved.
++ *
++ *
++ * THIS MATERIAL IS PROVIDED AS IS, WITH ABSOLUTELY NO WARRANTY EXPRESSED
++ * OR IMPLIED. ANY USE IS AT YOUR OWN RISK.
++ *
++ * Permission is hereby granted to use or copy this program
++ * for any purpose, provided the above notices are retained on all copies.
++ * Permission to modify the code and to distribute modified code is granted,
++ * provided the above notices are retained, and a notice that the code was
++ * modified is included with the above copyright notice.
++ *
++ */
++
++#include "../read_ordered.h"
++
++#include "../test_and_set_t_is_ao_t.h"
++
++AO_INLINE void
++AO_nop_full(void)
++{
++# ifndef AO_UNIPROCESSOR
++__sync_synchronize ();
++# endif
++}
++#define AO_HAVE_nop_full
++
++AO_INLINE AO_t
++AO_load(const volatile AO_t *addr)
++{
++ return __atomic_load_n (addr, __ATOMIC_RELAXED);
++}
++#define AO_HAVE_load
++
++AO_INLINE AO_t
++AO_load_acquire(const volatile AO_t *addr)
++{
++ return __atomic_load_n (addr, __ATOMIC_ACQUIRE);
++}
++#define AO_HAVE_load_acquire
++
++AO_INLINE void
++ AO_store(volatile AO_t *addr, AO_t value)
++{
++ __atomic_store_n(addr, value, __ATOMIC_RELAXED);
++}
++#define AO_HAVE_store
++
++AO_INLINE void
++ AO_store_release(volatile AO_t *addr, AO_t value)
++{
++ __atomic_store_n(addr, value, __ATOMIC_RELEASE);
++}
++#define AO_HAVE_store_release
++
++AO_INLINE AO_TS_VAL_t
++AO_test_and_set(volatile AO_TS_t *addr)
++{
++ return __atomic_test_and_set(addr, __ATOMIC_RELAXED);
++}
++# define AO_HAVE_test_and_set
++
++AO_INLINE AO_TS_VAL_t
++AO_test_and_set_acquire(volatile AO_TS_t *addr)
++{
++ return __atomic_test_and_set(addr, __ATOMIC_ACQUIRE);
++}
++# define AO_HAVE_test_and_set_acquire
++
++AO_INLINE AO_TS_VAL_t
++AO_test_and_set_release(volatile AO_TS_t *addr)
++{
++ return __atomic_test_and_set(addr, __ATOMIC_RELEASE);
++}
++# define AO_HAVE_test_and_set_release
++
++AO_INLINE AO_TS_VAL_t
++AO_test_and_set_full(volatile AO_TS_t *addr)
++{
++ return __atomic_test_and_set(addr, __ATOMIC_SEQ_CST);
++}
++# define AO_HAVE_test_and_set_full
++
++AO_INLINE AO_t
++AO_fetch_and_add(volatile AO_t *p, AO_t incr)
++{
++ return __atomic_fetch_add(p, incr, __ATOMIC_RELAXED);
++}
++#define AO_HAVE_fetch_and_add
++
++AO_INLINE AO_t
++AO_fetch_and_add_acquire(volatile AO_t *p, AO_t incr)
++{
++ return __atomic_fetch_add(p, incr, __ATOMIC_ACQUIRE);
++}
++#define AO_HAVE_fetch_and_add_acquire
++
++AO_INLINE AO_t
++AO_fetch_and_add_release(volatile AO_t *p, AO_t incr)
++{
++ return __atomic_fetch_add(p, incr, __ATOMIC_RELEASE);
++}
++#define AO_HAVE_fetch_and_add_release
++
++AO_INLINE AO_t
++AO_fetch_and_add_full(volatile AO_t *p, AO_t incr)
++{
++ return __atomic_fetch_add(p, incr, __ATOMIC_SEQ_CST);
++}
++#define AO_HAVE_fetch_and_add_full
++
++AO_INLINE AO_t
++AO_fetch_and_add1(volatile AO_t *p)
++{
++ return __atomic_fetch_add(p, 1, __ATOMIC_RELAXED);
++}
++#define AO_HAVE_fetch_and_add1
++
++AO_INLINE AO_t
++AO_fetch_and_add1_acquire(volatile AO_t *p)
++{
++ return __atomic_fetch_add(p, 1, __ATOMIC_ACQUIRE);
++}
++#define AO_HAVE_fetch_and_add1_acquire
++
++AO_INLINE AO_t
++AO_fetch_and_add1_release(volatile AO_t *p)
++{
++ return __atomic_fetch_add(p, 1, __ATOMIC_RELEASE);
++}
++#define AO_HAVE_fetch_and_add1_release
++
++AO_INLINE AO_t
++AO_fetch_and_add1_full(volatile AO_t *p)
++{
++ return __atomic_fetch_add(p, 1, __ATOMIC_SEQ_CST);
++}
++#define AO_HAVE_fetch_and_add1_full
++
++AO_INLINE AO_t
++AO_fetch_and_sub1(volatile AO_t *p)
++{
++ return __atomic_fetch_sub(p, 1, __ATOMIC_RELAXED);
++}
++#define AO_HAVE_fetch_and_sub1
++
++AO_INLINE AO_t
++AO_fetch_and_sub1_acquire(volatile AO_t *p)
++{
++ return __atomic_fetch_sub(p, 1, __ATOMIC_ACQUIRE);
++}
++#define AO_HAVE_fetch_and_sub1_acquire
++
++AO_INLINE AO_t
++AO_fetch_and_sub1_release(volatile AO_t *p)
++{
++ return __atomic_fetch_sub(p, 1, __ATOMIC_RELEASE);
++}
++#define AO_HAVE_fetch_and_sub1_release
++
++AO_INLINE AO_t
++AO_fetch_and_sub1_full(volatile AO_t *p)
++{
++ return __atomic_fetch_sub(p, 1, __ATOMIC_SEQ_CST);
++}
++#define AO_HAVE_fetch_and_sub1_full
++
++/* Returns nonzero if the comparison succeeded. */
++AO_INLINE int
++AO_compare_and_swap(volatile AO_t *addr, AO_t old_val, AO_t new_val)
++{
++ return __sync_bool_compare_and_swap(addr, old_val, new_val);
++}
++# define AO_HAVE_compare_and_swap
++
++AO_INLINE AO_t
++AO_fetch_compare_and_swap(volatile AO_t *addr, AO_t old_val, AO_t new_val)
++{
++ return __sync_val_compare_and_swap(addr, old_val, new_val);
++}
++# define AO_HAVE_fetch_compare_and_swap
diff --git a/meta/recipes-multimedia/pulseaudio/libatomics-ops_7.2.bb b/meta/recipes-multimedia/pulseaudio/libatomics-ops_7.2.bb
index 4632d24..5a58228 100644
--- a/meta/recipes-multimedia/pulseaudio/libatomics-ops_7.2.bb
+++ b/meta/recipes-multimedia/pulseaudio/libatomics-ops_7.2.bb
@@ -9,6 +9,7 @@ LIC_FILES_CHKSUM = "file://doc/COPYING;md5=94d55d512a9ba36caa9b7df079bae19f \
PR = "r1"
SRC_URI = "http://www.hpl.hp.com/research/linux/atomic_ops/download/libatomic_ops-${PV}.tar.gz \
+ file://0001-libatomic_ops-Aarch64-basic-port.patch \
"
SRC_URI[md5sum] = "890acdc83a7cd10e2e9536062d3741c8"
--
1.9.1
^ permalink raw reply related [flat|nested] 51+ messages in thread* [PATCH 08/24] qt4: add aarch64 support
2014-11-07 8:51 [PATCH 00/24] V2: Add machine qemuarm64 Kai Kang
` (6 preceding siblings ...)
2014-11-07 8:51 ` [PATCH 07/24] libatomics-ops: add aarch64 target iniitial support Kai Kang
@ 2014-11-07 8:51 ` Kai Kang
2014-11-07 8:51 ` [PATCH 09/24] libpng: add neon option for aarch64 Kai Kang
` (17 subsequent siblings)
25 siblings, 0 replies; 51+ messages in thread
From: Kai Kang @ 2014-11-07 8:51 UTC (permalink / raw)
To: ross.burton; +Cc: koen.kooi, openembedded-core
Add aarch64 support for qt4 packages.
Most of the patches are derived from debian:
http://anonscm.debian.org/cgit/pkg-kde/qt/qt4-x11.git/tree/debian/patches
Add arch check to set right QT_ARCH.
Disable webkit temporarily for qt4 and qt4-embedded that they fail to build:
| runtime/JSValueInlineMethods.h: In constructor
'JSC::JSValue::JSValue(const JSC::JSCell*)':
| runtime/JSValueInlineMethods.h:242:78: error: cast from 'JSC::JSCell*'
to 'int32_t {aka int}' loses precision [-fpermissive]
It has been fix by Qt5, but didn't backport to Qt4. There is an still open
defect for it:
https://bugreports.qt-project.org/browse/QTBUG-35442
Signed-off-by: Kai Kang <kai.kang@windriver.com>
---
meta/recipes-qt/qt4/qt4-4.8.6.inc | 7 +
.../0029-aarch64_arm64_fix_arch_detection.patch | 53 +++
.../0030-aarch64_arm64_qatomic_support.patch | 491 +++++++++++++++++++++
.../qt4/qt4-4.8.6/0031-aarch64_arm64_mkspecs.patch | 124 ++++++
| 18 +
meta/recipes-qt/qt4/qt4-native.inc | 4 +
meta/recipes-qt/qt4/qt4_arch.inc | 1 +
7 files changed, 698 insertions(+)
create mode 100644 meta/recipes-qt/qt4/qt4-4.8.6/0029-aarch64_arm64_fix_arch_detection.patch
create mode 100644 meta/recipes-qt/qt4/qt4-4.8.6/0030-aarch64_arm64_qatomic_support.patch
create mode 100644 meta/recipes-qt/qt4/qt4-4.8.6/0031-aarch64_arm64_mkspecs.patch
create mode 100644 meta/recipes-qt/qt4/qt4-4.8.6/0032-aarch64_add_header.patch
diff --git a/meta/recipes-qt/qt4/qt4-4.8.6.inc b/meta/recipes-qt/qt4/qt4-4.8.6.inc
index ae6692b..84f62fe 100644
--- a/meta/recipes-qt/qt4/qt4-4.8.6.inc
+++ b/meta/recipes-qt/qt4/qt4-4.8.6.inc
@@ -22,6 +22,10 @@ SRC_URI = "http://download.qt-project.org/official_releases/qt/4.8/${PV}/qt-ever
file://0019-Fixes-for-gcc-4.7.0-particularly-on-qemux86.patch \
file://0027-tools.pro-disable-qmeegographicssystemhelper.patch \
file://0028-Don-t-crash-on-broken-GIF-images.patch \
+ file://0029-aarch64_arm64_fix_arch_detection.patch \
+ file://0030-aarch64_arm64_qatomic_support.patch \
+ file://0031-aarch64_arm64_mkspecs.patch \
+ file://0032-aarch64_add_header.patch \
file://g++.conf \
file://linux.conf \
"
@@ -31,6 +35,9 @@ SRC_URI[sha256sum] = "8b14dd91b52862e09b8e6a963507b74bc2580787d171feda197badfa70
S = "${WORKDIR}/qt-everywhere-opensource-src-${PV}"
+# disable webkit for aarch64 temporarily that fails to compile
+QT_CONFIG_FLAGS_append_aarch64 = " -no-webkit"
+
FILES_${QT_BASE_NAME}-tools_append = " ${bindir}/qml ${bindir}/qmlplugindump"
FILES_${QT_BASE_NAME}-tools-dbg_append = " ${bindir}/.debug/qml ${bindir}/.debug/qmlplugindump"
diff --git a/meta/recipes-qt/qt4/qt4-4.8.6/0029-aarch64_arm64_fix_arch_detection.patch b/meta/recipes-qt/qt4/qt4-4.8.6/0029-aarch64_arm64_fix_arch_detection.patch
new file mode 100644
index 0000000..fbd32b1
--- /dev/null
+++ b/meta/recipes-qt/qt4/qt4-4.8.6/0029-aarch64_arm64_fix_arch_detection.patch
@@ -0,0 +1,53 @@
+From 800abbba658203fc8e746e3fc780a297cd4110cf Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Lisandro=20Dami=C3=A1n=20Nicanor=20P=C3=A9rez=20Meyer?=
+ <perezmeyer@gmail.com>
+Date: Wed, 20 Aug 2014 17:52:49 -0300
+Subject: [PATCH] Fix AArch64/arm64 detection.
+
+The detection needs to go before arm, else the system will detect AArch64/arm64
+as arm.
+
+This patch comes from Wookey, he has agreed to put it under BSD or Expat
+to allow it's inclusion in here:
+<https://bugs.debian.org/cgi-bin/bugreport.cgi?bug=735488#255>
+
+Change-Id: Ic2171c03fca8bb871347940fa3a2bc467776f797
+
+
+Upstream-Status: Pending
+
+Signed-off-by: Kai Kang <kai.kang@windriver.com>
+---
+ configure | 12 ++++++------
+ 1 file changed, 6 insertions(+), 6 deletions(-)
+
+diff --git a/configure b/configure
+index a9ba7c8..eb88b72 100755
+--- a/configure
++++ b/configure
+@@ -3241,17 +3241,17 @@ if [ -z "${CFG_HOST_ARCH}" ]; then
+ fi
+ CFG_HOST_ARCH=s390
+ ;;
+- *:*:arm*)
++ *:*:aarch64*|*:*:arm64*)
+ if [ "$OPT_VERBOSE" = "yes" ]; then
+- echo " ARM (arm)"
++ echo " AArch64 (aarch64)"
+ fi
+- CFG_HOST_ARCH=arm
++ CFG_HOST_ARCH=aarch64
+ ;;
+- *:*:aarch64*)
++ *:*:arm*)
+ if [ "$OPT_VERBOSE" = "yes" ]; then
+- echo " AArch64 (aarch64)"
++ echo " ARM (arm)"
+ fi
+- CFG_HOST_ARCH=aarch64
++ CFG_HOST_ARCH=arm
+ ;;
+ Linux:*:sparc*)
+ if [ "$OPT_VERBOSE" = "yes" ]; then
+--
+2.1.0
diff --git a/meta/recipes-qt/qt4/qt4-4.8.6/0030-aarch64_arm64_qatomic_support.patch b/meta/recipes-qt/qt4/qt4-4.8.6/0030-aarch64_arm64_qatomic_support.patch
new file mode 100644
index 0000000..ba4c2a6
--- /dev/null
+++ b/meta/recipes-qt/qt4/qt4-4.8.6/0030-aarch64_arm64_qatomic_support.patch
@@ -0,0 +1,491 @@
+From 294010b562c9846bb2bc4ee9c63ff78adc7c1f4f Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Lisandro=20Dami=C3=A1n=20Nicanor=20P=C3=A9rez=20Meyer?=
+ <perezmeyer@gmail.com>
+Date: Sat, 15 Mar 2014 15:40:49 -0300
+Subject: [PATCH] Add qatomic support for AArch64 (aka arm64).
+
+Patch by Mark Salter <msalter@redhat.com>
+licensed under BSD:
+
+<https://bugs.debian.org/cgi-bin/bugreport.cgi?bug=735488#195>
+
+This patch is known to not be the most correct way
+to implement them, as it seems to be possible to do it in a faster way,
+but should work non the less until we can provide something better.
+
+Change-Id: Ib392b27dc54691fd4c2ea9896240ad71fb8128cc
+
+
+Upstream-Status: Pending
+
+Signed-off-by: Kai Kang <kai.kang@windriver.com>
+
+---
+ src/corelib/arch/aarch64/arch.pri | 4 +
+ src/corelib/arch/aarch64/qatomic_aarch64.cpp | 70 ++++++
+ src/corelib/arch/arch.pri | 4 +-
+ src/corelib/arch/qatomic_aarch64.h | 335 +++++++++++++++++++++++++++
+ src/corelib/arch/qatomic_arch.h | 2 +
+ 5 files changed, 414 insertions(+), 1 deletion(-)
+ create mode 100644 src/corelib/arch/aarch64/arch.pri
+ create mode 100644 src/corelib/arch/aarch64/qatomic_aarch64.cpp
+ create mode 100644 src/corelib/arch/qatomic_aarch64.h
+
+diff --git a/src/corelib/arch/aarch64/arch.pri b/src/corelib/arch/aarch64/arch.pri
+new file mode 100644
+index 0000000..63523d9
+--- /dev/null
++++ b/src/corelib/arch/aarch64/arch.pri
+@@ -0,0 +1,4 @@
++#
++# AArch64 architecture
++#
++SOURCES += $$QT_ARCH_CPP/qatomic_aarch64.cpp
+diff --git a/src/corelib/arch/aarch64/qatomic_aarch64.cpp b/src/corelib/arch/aarch64/qatomic_aarch64.cpp
+new file mode 100644
+index 0000000..fc851b9
+--- /dev/null
++++ b/src/corelib/arch/aarch64/qatomic_aarch64.cpp
+@@ -0,0 +1,70 @@
++/****************************************************************************
++**
++** Copyright (C) 2012, 2013 Digia Plc and/or its subsidiary(-ies).
++** Contact: http://www.qt-project.org/legal
++**
++** This file is part of the QtCore module of the Qt Toolkit.
++**
++** $QT_BEGIN_LICENSE:LGPL$
++** Commercial License Usage
++** Licensees holding valid commercial Qt licenses may use this file in
++** accordance with the commercial license agreement provided with the
++** Software or, alternatively, in accordance with the terms contained in
++** a written agreement between you and Digia. For licensing terms and
++** conditions see http://qt.digia.com/licensing. For further information
++** use the contact form at http://qt.digia.com/contact-us.
++**
++** GNU Lesser General Public License Usage
++** Alternatively, this file may be used under the terms of the GNU Lesser
++** General Public License version 2.1 as published by the Free Software
++** Foundation and appearing in the file LICENSE.LGPL included in the
++** packaging of this file. Please review the following information to
++** ensure the GNU Lesser General Public License version 2.1 requirements
++** will be met: http://www.gnu.org/licenses/old-licenses/lgpl-2.1.html.
++**
++** In addition, as a special exception, Digia gives you certain additional
++** rights. These rights are described in the Digia Qt LGPL Exception
++** version 1.1, included in the file LGPL_EXCEPTION.txt in this package.
++**
++** GNU General Public License Usage
++** Alternatively, this file may be used under the terms of the GNU
++** General Public License version 3.0 as published by the Free Software
++** Foundation and appearing in the file LICENSE.GPL included in the
++** packaging of this file. Please review the following information to
++** ensure the GNU General Public License version 3.0 requirements will be
++** met: http://www.gnu.org/copyleft/gpl.html.
++**
++**
++** $QT_END_LICENSE$
++**
++****************************************************************************/
++
++#include <QtCore/qglobal.h>
++
++#include <unistd.h>
++#ifdef _POSIX_PRIORITY_SCHEDULING
++# include <sched.h>
++#endif
++#include <time.h>
++
++QT_BEGIN_NAMESPACE
++
++QT_USE_NAMESPACE
++
++Q_CORE_EXPORT void qt_atomic_yield(int *count)
++{
++#ifdef _POSIX_PRIORITY_SCHEDULING
++ if ((*count)++ < 50) {
++ sched_yield();
++ } else
++#endif
++ {
++ struct timespec tm;
++ tm.tv_sec = 0;
++ tm.tv_nsec = 2000001;
++ nanosleep(&tm, NULL);
++ *count = 0;
++ }
++}
++
++QT_END_NAMESPACE
+diff --git a/src/corelib/arch/arch.pri b/src/corelib/arch/arch.pri
+index cd23e5e..f50fca7 100644
+--- a/src/corelib/arch/arch.pri
++++ b/src/corelib/arch/arch.pri
+@@ -31,7 +31,9 @@ integrity:HEADERS += arch/qatomic_integrity.h
+ arch/qatomic_s390.h \
+ arch/qatomic_x86_64.h \
+ arch/qatomic_sh.h \
+- arch/qatomic_sh4a.h
++ arch/qatomic_sh4a.h \
++ arch/qatomic_aarch64.h \
++
+
+ QT_ARCH_CPP = $$QT_SOURCE_TREE/src/corelib/arch/$$QT_ARCH
+ DEPENDPATH += $$QT_ARCH_CPP
+diff --git a/src/corelib/arch/qatomic_aarch64.h b/src/corelib/arch/qatomic_aarch64.h
+new file mode 100644
+index 0000000..de61ca8
+--- /dev/null
++++ b/src/corelib/arch/qatomic_aarch64.h
+@@ -0,0 +1,335 @@
++/****************************************************************************
++**
++** Copyright (C) 2012 Digia Plc and/or its subsidiary(-ies).
++** Contact: http://www.qt-project.org/legal
++**
++** This file is part of the QtCore module of the Qt Toolkit.
++**
++** $QT_BEGIN_LICENSE:LGPL$
++** Commercial License Usage
++** Licensees holding valid commercial Qt licenses may use this file in
++** accordance with the commercial license agreement provided with the
++** Software or, alternatively, in accordance with the terms contained in
++** a written agreement between you and Digia. For licensing terms and
++** conditions see http://qt.digia.com/licensing. For further information
++** use the contact form at http://qt.digia.com/contact-us.
++**
++** GNU Lesser General Public License Usage
++** Alternatively, this file may be used under the terms of the GNU Lesser
++** General Public License version 2.1 as published by the Free Software
++** Foundation and appearing in the file LICENSE.LGPL included in the
++** packaging of this file. Please review the following information to
++** ensure the GNU Lesser General Public License version 2.1 requirements
++** will be met: http://www.gnu.org/licenses/old-licenses/lgpl-2.1.html.
++**
++** In addition, as a special exception, Digia gives you certain additional
++** rights. These rights are described in the Digia Qt LGPL Exception
++** version 1.1, included in the file LGPL_EXCEPTION.txt in this package.
++**
++** GNU General Public License Usage
++** Alternatively, this file may be used under the terms of the GNU
++** General Public License version 3.0 as published by the Free Software
++** Foundation and appearing in the file LICENSE.GPL included in the
++** packaging of this file. Please review the following information to
++** ensure the GNU General Public License version 3.0 requirements will be
++** met: http://www.gnu.org/copyleft/gpl.html.
++**
++**
++** $QT_END_LICENSE$
++**
++****************************************************************************/
++
++#ifndef QATOMIC_AARCH64_H
++#define QATOMIC_AARCH64_H
++
++QT_BEGIN_HEADER
++
++QT_BEGIN_NAMESPACE
++
++#define Q_ATOMIC_INT_REFERENCE_COUNTING_IS_ALWAYS_NATIVE
++
++inline bool QBasicAtomicInt::isReferenceCountingNative()
++{ return true; }
++inline bool QBasicAtomicInt::isReferenceCountingWaitFree()
++{ return false; }
++
++#define Q_ATOMIC_INT_TEST_AND_SET_IS_ALWAYS_NATIVE
++
++inline bool QBasicAtomicInt::isTestAndSetNative()
++{ return true; }
++inline bool QBasicAtomicInt::isTestAndSetWaitFree()
++{ return false; }
++
++#define Q_ATOMIC_INT_FETCH_AND_STORE_IS_ALWAYS_NATIVE
++
++inline bool QBasicAtomicInt::isFetchAndStoreNative()
++{ return true; }
++inline bool QBasicAtomicInt::isFetchAndStoreWaitFree()
++{ return false; }
++
++#define Q_ATOMIC_INT_FETCH_AND_ADD_IS_ALWAYS_NATIVE
++
++inline bool QBasicAtomicInt::isFetchAndAddNative()
++{ return true; }
++inline bool QBasicAtomicInt::isFetchAndAddWaitFree()
++{ return false; }
++
++#define Q_ATOMIC_POINTER_TEST_AND_SET_IS_ALWAYS_NATIVE
++
++template <typename T>
++Q_INLINE_TEMPLATE bool QBasicAtomicPointer<T>::isTestAndSetNative()
++{ return true; }
++template <typename T>
++Q_INLINE_TEMPLATE bool QBasicAtomicPointer<T>::isTestAndSetWaitFree()
++{ return false; }
++
++#define Q_ATOMIC_POINTER_FETCH_AND_STORE_IS_ALWAYS_NATIVE
++
++template <typename T>
++Q_INLINE_TEMPLATE bool QBasicAtomicPointer<T>::isFetchAndStoreNative()
++{ return true; }
++template <typename T>
++Q_INLINE_TEMPLATE bool QBasicAtomicPointer<T>::isFetchAndStoreWaitFree()
++{ return false; }
++
++#define Q_ATOMIC_POINTER_FETCH_AND_ADD_IS_ALWAYS_NATIVE
++
++template <typename T>
++Q_INLINE_TEMPLATE bool QBasicAtomicPointer<T>::isFetchAndAddNative()
++{ return true; }
++template <typename T>
++Q_INLINE_TEMPLATE bool QBasicAtomicPointer<T>::isFetchAndAddWaitFree()
++{ return false; }
++
++#ifndef Q_DATA_MEMORY_BARRIER
++# define Q_DATA_MEMORY_BARRIER asm volatile("dmb sy\n":::"memory")
++#endif
++#ifndef Q_COMPILER_MEMORY_BARRIER
++# define Q_COMPILER_MEMORY_BARRIER asm volatile("":::"memory")
++#endif
++
++inline bool QBasicAtomicInt::ref()
++{
++ int newValue;
++
++ Q_COMPILER_MEMORY_BARRIER;
++ newValue = __atomic_add_fetch(&_q_value, 1, __ATOMIC_ACQ_REL);
++ Q_COMPILER_MEMORY_BARRIER;
++
++ return newValue != 0;
++}
++
++inline bool QBasicAtomicInt::deref()
++{
++ int newValue;
++
++ Q_COMPILER_MEMORY_BARRIER;
++ newValue = __atomic_sub_fetch(&_q_value, 1, __ATOMIC_ACQ_REL);
++ Q_COMPILER_MEMORY_BARRIER;
++
++ return newValue != 0;
++}
++
++inline bool QBasicAtomicInt::testAndSetRelaxed(int expectedValue, int newValue)
++{
++ bool val;
++
++ Q_COMPILER_MEMORY_BARRIER;
++ val = __atomic_compare_exchange_n (&_q_value, &expectedValue, newValue,
++ false, __ATOMIC_RELAXED, __ATOMIC_RELAXED);
++ Q_COMPILER_MEMORY_BARRIER;
++ return val;
++}
++
++inline int QBasicAtomicInt::fetchAndStoreRelaxed(int newValue)
++{
++ int val;
++ Q_COMPILER_MEMORY_BARRIER;
++ val = __atomic_exchange_n(&_q_value, newValue, __ATOMIC_RELAXED);
++ Q_COMPILER_MEMORY_BARRIER;
++ return val;
++}
++
++inline int QBasicAtomicInt::fetchAndAddRelaxed(int valueToAdd)
++{
++ int val;
++ Q_COMPILER_MEMORY_BARRIER;
++ val = __atomic_fetch_add(&_q_value, valueToAdd, __ATOMIC_RELAXED);
++ Q_COMPILER_MEMORY_BARRIER;
++ return val;
++}
++
++template <typename T>
++Q_INLINE_TEMPLATE bool QBasicAtomicPointer<T>::testAndSetRelaxed(T *expectedValue, T *newValue)
++{
++ bool val;
++ Q_COMPILER_MEMORY_BARRIER;
++ val = __atomic_compare_exchange_n (&_q_value, &expectedValue, newValue,
++ false, __ATOMIC_RELAXED, __ATOMIC_RELAXED);
++ Q_COMPILER_MEMORY_BARRIER;
++ return val;
++}
++
++template <typename T>
++Q_INLINE_TEMPLATE T *QBasicAtomicPointer<T>::fetchAndStoreRelaxed(T *newValue)
++{
++ T *val;
++ Q_COMPILER_MEMORY_BARRIER;
++ val = __atomic_exchange_n(&_q_value, newValue, __ATOMIC_RELAXED);
++ Q_COMPILER_MEMORY_BARRIER;
++ return val;
++}
++
++template <typename T>
++Q_INLINE_TEMPLATE T *QBasicAtomicPointer<T>::fetchAndAddRelaxed(qptrdiff valueToAdd)
++{
++ T *val;
++ Q_COMPILER_MEMORY_BARRIER;
++ val = __atomic_fetch_add(&_q_value, valueToAdd, __ATOMIC_RELAXED);
++ Q_COMPILER_MEMORY_BARRIER;
++ return val;
++}
++
++inline bool QBasicAtomicInt::testAndSetAcquire(int expectedValue, int newValue)
++{
++ bool returnValue = testAndSetRelaxed(expectedValue, newValue);
++ Q_DATA_MEMORY_BARRIER;
++ return returnValue;
++}
++
++inline bool QBasicAtomicInt::testAndSetRelease(int expectedValue, int newValue)
++{
++ Q_DATA_MEMORY_BARRIER;
++ return testAndSetRelaxed(expectedValue, newValue);
++}
++
++inline bool QBasicAtomicInt::testAndSetOrdered(int expectedValue, int newValue)
++{
++ Q_DATA_MEMORY_BARRIER;
++ bool returnValue = testAndSetRelaxed(expectedValue, newValue);
++ Q_COMPILER_MEMORY_BARRIER;
++ return returnValue;
++}
++
++inline int QBasicAtomicInt::fetchAndStoreAcquire(int newValue)
++{
++ int returnValue = fetchAndStoreRelaxed(newValue);
++ Q_DATA_MEMORY_BARRIER;
++ return returnValue;
++}
++
++inline int QBasicAtomicInt::fetchAndStoreRelease(int newValue)
++{
++ Q_DATA_MEMORY_BARRIER;
++ return fetchAndStoreRelaxed(newValue);
++}
++
++inline int QBasicAtomicInt::fetchAndStoreOrdered(int newValue)
++{
++ Q_DATA_MEMORY_BARRIER;
++ int returnValue = fetchAndStoreRelaxed(newValue);
++ Q_COMPILER_MEMORY_BARRIER;
++ return returnValue;
++}
++
++inline int QBasicAtomicInt::fetchAndAddAcquire(int valueToAdd)
++{
++ int returnValue = fetchAndAddRelaxed(valueToAdd);
++ Q_DATA_MEMORY_BARRIER;
++ return returnValue;
++}
++
++inline int QBasicAtomicInt::fetchAndAddRelease(int valueToAdd)
++{
++ Q_DATA_MEMORY_BARRIER;
++ return fetchAndAddRelaxed(valueToAdd);
++}
++
++inline int QBasicAtomicInt::fetchAndAddOrdered(int valueToAdd)
++{
++ Q_DATA_MEMORY_BARRIER;
++ int returnValue = fetchAndAddRelaxed(valueToAdd);
++ Q_COMPILER_MEMORY_BARRIER;
++ return returnValue;
++}
++
++template <typename T>
++Q_INLINE_TEMPLATE bool QBasicAtomicPointer<T>::testAndSetAcquire(T *expectedValue, T *newValue)
++{
++ bool returnValue = testAndSetRelaxed(expectedValue, newValue);
++ Q_DATA_MEMORY_BARRIER;
++ return returnValue;
++}
++
++template <typename T>
++Q_INLINE_TEMPLATE bool QBasicAtomicPointer<T>::testAndSetRelease(T *expectedValue, T *newValue)
++{
++ Q_DATA_MEMORY_BARRIER;
++ return testAndSetRelaxed(expectedValue, newValue);
++}
++
++template <typename T>
++Q_INLINE_TEMPLATE bool QBasicAtomicPointer<T>::testAndSetOrdered(T *expectedValue, T *newValue)
++{
++ Q_DATA_MEMORY_BARRIER;
++ bool returnValue = testAndSetAcquire(expectedValue, newValue);
++ Q_COMPILER_MEMORY_BARRIER;
++ return returnValue;
++}
++
++template <typename T>
++Q_INLINE_TEMPLATE T *QBasicAtomicPointer<T>::fetchAndStoreAcquire(T *newValue)
++{
++ T *returnValue = fetchAndStoreRelaxed(newValue);
++ Q_DATA_MEMORY_BARRIER;
++ return returnValue;
++}
++
++template <typename T>
++Q_INLINE_TEMPLATE T *QBasicAtomicPointer<T>::fetchAndStoreRelease(T *newValue)
++{
++ Q_DATA_MEMORY_BARRIER;
++ return fetchAndStoreRelaxed(newValue);
++}
++
++template <typename T>
++Q_INLINE_TEMPLATE T *QBasicAtomicPointer<T>::fetchAndStoreOrdered(T *newValue)
++{
++ Q_DATA_MEMORY_BARRIER;
++ T *returnValue = fetchAndStoreRelaxed(newValue);
++ Q_COMPILER_MEMORY_BARRIER;
++ return returnValue;
++}
++
++template <typename T>
++Q_INLINE_TEMPLATE T *QBasicAtomicPointer<T>::fetchAndAddAcquire(qptrdiff valueToAdd)
++{
++ T *returnValue = fetchAndAddRelaxed(valueToAdd);
++ Q_DATA_MEMORY_BARRIER;
++ return returnValue;
++}
++
++template <typename T>
++Q_INLINE_TEMPLATE T *QBasicAtomicPointer<T>::fetchAndAddRelease(qptrdiff valueToAdd)
++{
++ Q_DATA_MEMORY_BARRIER;
++ return fetchAndAddRelaxed(valueToAdd);
++}
++
++template <typename T>
++Q_INLINE_TEMPLATE T *QBasicAtomicPointer<T>::fetchAndAddOrdered(qptrdiff valueToAdd)
++{
++ Q_DATA_MEMORY_BARRIER;
++ T *returnValue = fetchAndAddRelaxed(valueToAdd);
++ Q_COMPILER_MEMORY_BARRIER;
++ return returnValue;
++}
++
++#undef Q_DATA_MEMORY_BARRIER
++#undef Q_COMPILER_MEMORY_BARRIER
++
++QT_END_NAMESPACE
++
++QT_END_HEADER
++
++#endif // QATOMIC_AARCH64_H
+diff --git a/src/corelib/arch/qatomic_arch.h b/src/corelib/arch/qatomic_arch.h
+index 141726c..3e96926 100644
+--- a/src/corelib/arch/qatomic_arch.h
++++ b/src/corelib/arch/qatomic_arch.h
+@@ -94,6 +94,8 @@ QT_BEGIN_HEADER
+ # include "QtCore/qatomic_sh4a.h"
+ #elif defined(QT_ARCH_NACL)
+ # include "QtCore/qatomic_generic.h"
++#elif defined(QT_ARCH_AARCH64)
++# include "QtCore/qatomic_aarch64.h"
+ #else
+ # error "Qt has not been ported to this architecture"
+ #endif
+--
+2.1.0
+
diff --git a/meta/recipes-qt/qt4/qt4-4.8.6/0031-aarch64_arm64_mkspecs.patch b/meta/recipes-qt/qt4/qt4-4.8.6/0031-aarch64_arm64_mkspecs.patch
new file mode 100644
index 0000000..a01e7ad
--- /dev/null
+++ b/meta/recipes-qt/qt4/qt4-4.8.6/0031-aarch64_arm64_mkspecs.patch
@@ -0,0 +1,124 @@
+From 7090fc80ff630712a90de92403190f647dd38a39 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Lisandro=20Dami=C3=A1n=20Nicanor=20P=C3=A9rez=20Meyer?=
+ <perezmeyer@gmail.com>
+Date: Sat, 15 Mar 2014 15:35:00 -0300
+Subject: [PATCH] mkspecs for AArch64 (aka arm64).
+
+Patch by Marcin Juszkiewicz <marcin@juszkiewicz.com.pl>
+licensed under either Public Domain or BSD:
+
+<https://bugs.debian.org/cgi-bin/bugreport.cgi?bug=735488#179>
+
+Change-Id: I21f17953234cfb176bac023e52ecdc927fc5c1a9
+
+
+Upstream-Status: Pending
+
+Signed-off-by: Kai Kang <kai.kang@windriver.com>
+
+---
+ configure | 3 +++
+ mkspecs/linux-g++-aarch64/qmake.conf | 27 ++++++++++++++++++++
+ mkspecs/linux-g++-aarch64/qplatformdefs.h | 42 +++++++++++++++++++++++++++++++
+ 3 files changed, 72 insertions(+)
+ create mode 100644 mkspecs/linux-g++-aarch64/qmake.conf
+ create mode 100644 mkspecs/linux-g++-aarch64/qplatformdefs.h
+
+diff --git a/configure b/configure
+index a9ba7c8..e57d053 100755
+--- a/configure
++++ b/configure
+@@ -2808,6 +2808,9 @@ if [ "$CFG_EMBEDDED" != "no" ]; then
+ *86_64)
+ PLATFORM=qws/linux-x86_64-g++
+ ;;
++ aarch64)
++ PLATFORM=linux-aarch64-g++
++ ;;
+ *)
+ PLATFORM=qws/linux-generic-g++
+ ;;
+diff --git a/mkspecs/linux-g++-aarch64/qmake.conf b/mkspecs/linux-g++-aarch64/qmake.conf
+new file mode 100644
+index 0000000..ebc0a92
+--- /dev/null
++++ b/mkspecs/linux-g++-aarch64/qmake.conf
+@@ -0,0 +1,27 @@
++#
++# qmake configuration for linux-g++
++#
++# Written for GNU/Linux platforms that have both lib and lib64 directories,
++# like the AMD Opteron.
++#
++
++MAKEFILE_GENERATOR = UNIX
++TARGET_PLATFORM = unix
++TEMPLATE = app
++CONFIG += qt warn_on release incremental link_prl gdb_dwarf_index
++QT += core gui
++QMAKE_INCREMENTAL_STYLE = sublib
++
++QMAKE_CFLAGS =
++QMAKE_LFLAGS =
++
++QMAKE_CFLAGS_RELEASE += -O2
++
++include(../common/linux.conf)
++include(../common/gcc-base-unix.conf)
++include(../common/g++-unix.conf)
++
++QMAKE_LIBDIR_X11 = /usr/X11R6/lib64
++QMAKE_LIBDIR_OPENGL = /usr/X11R6/lib64
++
++load(qt_config)
+diff --git a/mkspecs/linux-g++-aarch64/qplatformdefs.h b/mkspecs/linux-g++-aarch64/qplatformdefs.h
+new file mode 100644
+index 0000000..562128b
+--- /dev/null
++++ b/mkspecs/linux-g++-aarch64/qplatformdefs.h
+@@ -0,0 +1,42 @@
++/****************************************************************************
++**
++** Copyright (C) 2012 Digia Plc and/or its subsidiary(-ies).
++** Contact: http://www.qt-project.org/legal
++**
++** This file is part of the qmake spec of the Qt Toolkit.
++**
++** $QT_BEGIN_LICENSE:LGPL$
++** Commercial License Usage
++** Licensees holding valid commercial Qt licenses may use this file in
++** accordance with the commercial license agreement provided with the
++** Software or, alternatively, in accordance with the terms contained in
++** a written agreement between you and Digia. For licensing terms and
++** conditions see http://qt.digia.com/licensing. For further information
++** use the contact form at http://qt.digia.com/contact-us.
++**
++** GNU Lesser General Public License Usage
++** Alternatively, this file may be used under the terms of the GNU Lesser
++** General Public License version 2.1 as published by the Free Software
++** Foundation and appearing in the file LICENSE.LGPL included in the
++** packaging of this file. Please review the following information to
++** ensure the GNU Lesser General Public License version 2.1 requirements
++** will be met: http://www.gnu.org/licenses/old-licenses/lgpl-2.1.html.
++**
++** In addition, as a special exception, Digia gives you certain additional
++** rights. These rights are described in the Digia Qt LGPL Exception
++** version 1.1, included in the file LGPL_EXCEPTION.txt in this package.
++**
++** GNU General Public License Usage
++** Alternatively, this file may be used under the terms of the GNU
++** General Public License version 3.0 as published by the Free Software
++** Foundation and appearing in the file LICENSE.GPL included in the
++** packaging of this file. Please review the following information to
++** ensure the GNU General Public License version 3.0 requirements will be
++** met: http://www.gnu.org/copyleft/gpl.html.
++**
++**
++** $QT_END_LICENSE$
++**
++****************************************************************************/
++
++#include "../linux-g++/qplatformdefs.h"
+--
+2.1.0
+
--git a/meta/recipes-qt/qt4/qt4-4.8.6/0032-aarch64_add_header.patch b/meta/recipes-qt/qt4/qt4-4.8.6/0032-aarch64_add_header.patch
new file mode 100644
index 0000000..7132224
--- /dev/null
+++ b/meta/recipes-qt/qt4/qt4-4.8.6/0032-aarch64_add_header.patch
@@ -0,0 +1,18 @@
+Add missing header for aarch64. And install ../corelib/arch/qatomic_aarch64.h.
+
+Upstream-Status: Pending
+
+Signed-off-by: Kai Kang <kai.kang@windriver.com>
+---
+diff -Nru qt-everywhere-opensource-src-4.8.6.orig/include/QtCore/qatomic_aarch64.h qt-everywhere-opensource-src-4.8.6/include/QtCore/qatomic_aarch64.h
+--- qt-everywhere-opensource-src-4.8.6.orig/include/QtCore/qatomic_aarch64.h 1970-01-01 08:30:00.000000000 +0830
++++ qt-everywhere-opensource-src-4.8.6/include/QtCore/qatomic_aarch64.h 2014-09-09 17:18:03.768352551 +0800
+@@ -0,0 +1 @@
++#include "../../src/corelib/arch/qatomic_aarch64.h"
+--- qt-everywhere-opensource-src-4.8.6/include/QtCore/headers.pri.orig 2014-09-09 18:05:37.100430311 +0800
++++ qt-everywhere-opensource-src-4.8.6/include/QtCore/headers.pri 2014-09-09 18:05:59.112430911 +0800
+@@ -1,3 +1,3 @@
+-SYNCQT.HEADER_FILES = ../corelib/statemachine/qabstractstate.h ../corelib/statemachine/qabstracttransition.h ../corelib/statemachine/qeventtransition.h ../corelib/statemachine/qfinalstate.h ../corelib/statemachine/qhistorystate.h ../corelib/statemachine/qsignaltransition.h ../corelib/statemachine/qstate.h ../corelib/statemachine/qstatemachine.h ../corelib/arch/qatomic_alpha.h ../corelib/arch/qatomic_arch.h ../corelib/arch/qatomic_arm.h ../corelib/arch/qatomic_armv5.h ../corelib/arch/qatomic_armv6.h ../corelib/arch/qatomic_armv7.h ../corelib/arch/qatomic_avr32.h ../corelib/arch/qatomic_bfin.h ../corelib/arch/qatomic_bootstrap.h ../corelib/arch/qatomic_generic.h ../corelib/arch/qatomic_i386.h ../corelib/arch/qatomic_ia64.h ../corelib/arch/qatomic_integrity.h ../corelib/arch/qatomic_m68k.h ../corelib/arch/qatomic_macosx.h ../corelib/arch/qatomic_mips.h ../corelib/arch/qatomic_parisc.h ../corelib/arch/qatomic_powerpc.h ../corelib/arch/qatomic_s390.h ../corelib/arch/qatomic_sh.h ../corelib/arch/qatomic_sh4a.h ../corelib/arch/qatomic_sparc.h ../corelib/arch/qatomic_symbian.h ../corelib/arch/qatomic_vxworks.h ../corelib/arch/qatomic_windows.h ../corelib/arch/qatomic_windowsce.h ../corelib/arch/qatomic_x86_64.h ../corelib/thread/qatomic.h ../corelib/thread/qbasicatomic.h ../corelib/thread/qmutex.h ../corelib/thread/qreadwritelock.h ../corelib/thread/qsemaphore.h ../corelib/thread/qthread.h ../corelib/thread/qthreadstorage.h ../corelib/thread/qwaitcondition.h ../corelib/xml/qxmlstream.h ../corelib/concurrent/qfuture.h ../corelib/concurrent/qfutureinterface.h ../corelib/concurrent/qfuturesynchronizer.h ../corelib/concurrent/qfuturewatcher.h ../corelib/concurrent/qrunnable.h ../corelib/concurrent/qtconcurrentcompilertest.h ../corelib/concurrent/qtconcurrentexception.h ../corelib/concurrent/qtconcurrentfilter.h ../corelib/concurrent/qtconcurrentfilterkernel.h ../corelib/concurrent/qtconcurrentfunctionwrappers.h ../corelib/concurrent/qtconcurrentiteratekernel.h ../corelib/concurrent/qtconcurrentmap.h ../corelib/concurrent/qtconcurrentmapkernel.h ../corelib/concurrent/qtconcurrentmedian.h ../corelib/concurrent/qtconcurrentreducekernel.h ../corelib/concurrent/qtconcurrentresultstore.h ../corelib/concurrent/qtconcurrentrun.h ../corelib/concurrent/qtconcurrentrunbase.h ../corelib/concurrent/qtconcurrentstoredfunctioncall.h ../corelib/concurrent/qtconcurrentthreadengine.h ../corelib/concurrent/qthreadpool.h ../corelib/kernel/qabstracteventdispatcher.h ../corelib/kernel/qabstractitemmodel.h ../corelib/kernel/qbasictimer.h ../corelib/kernel/qcoreapplication.h ../corelib/kernel/qcoreevent.h ../corelib/kernel/qeventloop.h ../corelib/kernel/qfunctions_nacl.h ../corelib/kernel/qfunctions_vxworks.h ../corelib/kernel/qfunctions_wince.h ../corelib/kernel/qmath.h ../corelib/kernel/qmetaobject.h ../corelib/kernel/qmetatype.h ../corelib/kernel/qmimedata.h ../corelib/kernel/qobject.h ../corelib/kernel/qobjectcleanuphandler.h ../corelib/kernel/qobjectdefs.h ../corelib/kernel/qpointer.h ../corelib/kernel/qsharedmemory.h ../corelib/kernel/qsignalmapper.h ../corelib/kernel/qsocketnotifier.h ../corelib/kernel/qsystemsemaphore.h ../corelib/kernel/qtimer.h ../corelib/kernel/qtranslator.h ../corelib/kernel/qvariant.h ../corelib/plugin/qfactoryinterface.h ../corelib/plugin/qlibrary.h ../corelib/plugin/qplugin.h ../corelib/plugin/qpluginloader.h ../corelib/plugin/quuid.h ../corelib/global/qconfig-dist.h ../corelib/global/qconfig-large.h ../corelib/global/qconfig-medium.h ../corelib/global/qconfig-minimal.h ../corelib/global/qconfig-nacl.h ../corelib/global/qconfig-small.h ../corelib/global/qendian.h ../corelib/global/qfeatures.h ../corelib/global/qglobal.h ../corelib/global/qlibraryinfo.h ../corelib/global/qnamespace.h ../corelib/global/qnumeric.h ../corelib/global/qt_windows.h ../corelib/global/qconfig.h ../corelib/codecs/qtextcodec.h ../corelib/codecs/qtextcodecplugin.h ../corelib/io/qabstractfileengine.h ../corelib/io/qbuffer.h ../corelib/io/qdatastream.h ../corelib/io/qdebug.h ../corelib/io/qdir.h ../corelib/io/qdiriterator.h ../corelib/io/qfile.h ../corelib/io/qfileinfo.h ../corelib/io/qfilesystemwatcher.h ../corelib/io/qfsfileengine.h ../corelib/io/qiodevice.h ../corelib/io/qprocess.h ../corelib/io/qresource.h ../corelib/io/qsettings.h ../corelib/io/qtemporaryfile.h ../corelib/io/qtextstream.h ../corelib/io/qurl.h ../corelib/animation/qabstractanimation.h ../corelib/animation/qanimationgroup.h ../corelib/animation/qparallelanimationgroup.h ../corelib/animation/qpauseanimation.h ../corelib/animation/qpropertyanimation.h ../corelib/animation/qsequentialanimationgroup.h ../corelib/animation/qvariantanimation.h ../corelib/tools/qalgorithms.h ../corelib/tools/qbitarray.h ../corelib/tools/qbytearray.h ../corelib/tools/qbytearraymatcher.h ../corelib/tools/qcache.h ../corelib/tools/qchar.h ../corelib/tools/qcontainerfwd.h ../corelib/tools/qcontiguouscache.h ../corelib/tools/qcryptographichash.h ../corelib/tools/qdatetime.h ../corelib/tools/qeasingcurve.h ../corelib/tools/qelapsedtimer.h ../corelib/tools/qhash.h ../corelib/tools/qiterator.h ../corelib/tools/qline.h ../corelib/tools/qlinkedlist.h ../corelib/tools/qlist.h ../corelib/tools/qlocale.h ../corelib/tools/qlocale_blackberry.h ../corelib/tools/qmap.h ../corelib/tools/qmargins.h ../corelib/tools/qpair.h ../corelib/tools/qpoint.h ../corelib/tools/qqueue.h ../corelib/tools/qrect.h ../corelib/tools/qregexp.h ../corelib/tools/qscopedpointer.h ../corelib/tools/qscopedvaluerollback.h ../corelib/tools/qset.h ../corelib/tools/qshareddata.h ../corelib/tools/qsharedpointer.h ../corelib/tools/qsharedpointer_impl.h ../corelib/tools/qsize.h ../corelib/tools/qstack.h ../corelib/tools/qstring.h ../corelib/tools/qstringbuilder.h ../corelib/tools/qstringlist.h ../corelib/tools/qstringmatcher.h ../corelib/tools/qtextboundaryfinder.h ../corelib/tools/qtimeline.h ../corelib/tools/qvarlengtharray.h ../corelib/tools/qvector.h ../../include/QtCore/QtCore
++SYNCQT.HEADER_FILES = ../corelib/statemachine/qabstractstate.h ../corelib/statemachine/qabstracttransition.h ../corelib/statemachine/qeventtransition.h ../corelib/statemachine/qfinalstate.h ../corelib/statemachine/qhistorystate.h ../corelib/statemachine/qsignaltransition.h ../corelib/statemachine/qstate.h ../corelib/statemachine/qstatemachine.h ../corelib/arch/qatomic_alpha.h ../corelib/arch/qatomic_arch.h ../corelib/arch/qatomic_arm.h ../corelib/arch/qatomic_armv5.h ../corelib/arch/qatomic_armv6.h ../corelib/arch/qatomic_armv7.h ../corelib/arch/qatomic_aarch64.h ../corelib/arch/qatomic_avr32.h ../corelib/arch/qatomic_bfin.h ../corelib/arch/qatomic_bootstrap.h ../corelib/arch/qatomic_generic.h ../corelib/arch/qatomic_i386.h ../corelib/arch/qatomic_ia64.h ../corelib/arch/qatomic_integrity.h ../corelib/arch/qatomic_m68k.h ../corelib/arch/qatomic_macosx.h ../corelib/arch/qatomic_mips.h ../corelib/arch/qatomic_parisc.h ../corelib/arch/qatomic_powerpc.h ../corelib/arch/qatomic_s390.h ../corelib/arch/qatomic_sh.h ../corelib/arch/qatomic_sh4a.h ../corelib/arch/qatomic_sparc.h ../corelib/arch/qatomic_symbian.h ../corelib/arch/qatomic_vxworks.h ../corelib/arch/qatomic_windows.h ../corelib/arch/qatomic_windowsce.h ../corelib/arch/qatomic_x86_64.h ../corelib/thread/qatomic.h ../corelib/thread/qbasicatomic.h ../corelib/thread/qmutex.h ../corelib/thread/qreadwritelock.h ../corelib/thread/qsemaphore.h ../corelib/thread/qthread.h ../corelib/thread/qthreadstorage.h ../corelib/thread/qwaitcondition.h ../corelib/xml/qxmlstream.h ../corelib/concurrent/qfuture.h ../corelib/concurrent/qfutureinterface.h ../corelib/concurrent/qfuturesynchronizer.h ../corelib/concurrent/qfuturewatcher.h ../corelib/concurrent/qrunnable.h ../corelib/concurrent/qtconcurrentcompilertest.h ../corelib/concurrent/qtconcurrentexception.h ../corelib/concurrent/qtconcurrentfilter.h ../corelib/concurrent/qtconcurrentfilterkernel.h ../corelib/concurrent/qtconcurrentfunctionwrappers.h ../corelib/concurrent/qtconcurrentiteratekernel.h ../corelib/concurrent/qtconcurrentmap.h ../corelib/concurrent/qtconcurrentmapkernel.h ../corelib/concurrent/qtconcurrentmedian.h ../corelib/concurrent/qtconcurrentreducekernel.h ../corelib/concurrent/qtconcurrentresultstore.h ../corelib/concurrent/qtconcurrentrun.h ../corelib/concurrent/qtconcurrentrunbase.h ../corelib/concurrent/qtconcurrentstoredfunctioncall.h ../corelib/concurrent/qtconcurrentthreadengine.h ../corelib/concurrent/qthreadpool.h ../corelib/kernel/qabstracteventdispatcher.h ../corelib/kernel/qabstractitemmodel.h ../corelib/kernel/qbasictimer.h ../corelib/kernel/qcoreapplication.h ../corelib/kernel/qcoreevent.h ../corelib/kernel/qeventloop.h ../corelib/kernel/qfunctions_nacl.h ../corelib/kernel/qfunctions_vxworks.h ../corelib/kernel/qfunctions_wince.h ../corelib/kernel/qmath.h ../corelib/kernel/qmetaobject.h ../corelib/kernel/qmetatype.h ../corelib/kernel/qmimedata.h ../corelib/kernel/qobject.h ../corelib/kernel/qobjectcleanuphandler.h ../corelib/kernel/qobjectdefs.h ../corelib/kernel/qpointer.h ../corelib/kernel/qsharedmemory.h ../corelib/kernel/qsignalmapper.h ../corelib/kernel/qsocketnotifier.h ../corelib/kernel/qsystemsemaphore.h ../corelib/kernel/qtimer.h ../corelib/kernel/qtranslator.h ../corelib/kernel/qvariant.h ../corelib/plugin/qfactoryinterface.h ../corelib/plugin/qlibrary.h ../corelib/plugin/qplugin.h ../corelib/plugin/qpluginloader.h ../corelib/plugin/quuid.h ../corelib/global/qconfig-dist.h ../corelib/global/qconfig-large.h ../corelib/global/qconfig-medium.h ../corelib/global/qconfig-minimal.h ../corelib/global/qconfig-nacl.h ../corelib/global/qconfig-small.h ../corelib/global/qendian.h ../corelib/global/qfeatures.h ../corelib/global/qglobal.h ../corelib/global/qlibraryinfo.h ../corelib/global/qnamespace.h ../corelib/global/qnumeric.h ../corelib/global/qt_windows.h ../corelib/global/qconfig.h ../corelib/codecs/qtextcodec.h ../corelib/codecs/qtextcodecplugin.h ../corelib/io/qabstractfileengine.h ../corelib/io/qbuffer.h ../corelib/io/qdatastream.h ../corelib/io/qdebug.h ../corelib/io/qdir.h ../corelib/io/qdiriterator.h ../corelib/io/qfile.h ../corelib/io/qfileinfo.h ../corelib/io/qfilesystemwatcher.h ../corelib/io/qfsfileengine.h ../corelib/io/qiodevice.h ../corelib/io/qprocess.h ../corelib/io/qresource.h ../corelib/io/qsettings.h ../corelib/io/qtemporaryfile.h ../corelib/io/qtextstream.h ../corelib/io/qurl.h ../corelib/animation/qabstractanimation.h ../corelib/animation/qanimationgroup.h ../corelib/animation/qparallelanimationgroup.h ../corelib/animation/qpauseanimation.h ../corelib/animation/qpropertyanimation.h ../corelib/animation/qsequentialanimationgroup.h ../corelib/animation/qvariantanimation.h ../corelib/tools/qalgorithms.h ../corelib/tools/qbitarray.h ../corelib/tools/qbytearray.h ../corelib/tools/qbytearraymatcher.h ../corelib/tools/qcache.h ../corelib/tools/qchar.h ../corelib/tools/qcontainerfwd.h ../corelib/tools/qcontiguouscache.h ../corelib/tools/qcryptographichash.h ../corelib/tools/qdatetime.h ../corelib/tools/qeasingcurve.h ../corelib/tools/qelapsedtimer.h ../corelib/tools/qhash.h ../corelib/tools/qiterator.h ../corelib/tools/qline.h ../corelib/tools/qlinkedlist.h ../corelib/tools/qlist.h ../corelib/tools/qlocale.h ../corelib/tools/qlocale_blackberry.h ../corelib/tools/qmap.h ../corelib/tools/qmargins.h ../corelib/tools/qpair.h ../corelib/tools/qpoint.h ../corelib/tools/qqueue.h ../corelib/tools/qrect.h ../corelib/tools/qregexp.h ../corelib/tools/qscopedpointer.h ../corelib/tools/qscopedvaluerollback.h ../corelib/tools/qset.h ../corelib/tools/qshareddata.h ../corelib/tools/qsharedpointer.h ../corelib/tools/qsharedpointer_impl.h ../corelib/tools/qsize.h ../corelib/tools/qstack.h ../corelib/tools/qstring.h ../corelib/tools/qstringbuilder.h ../corelib/tools/qstringlist.h ../corelib/tools/qstringmatcher.h ../corelib/tools/qtextboundaryfinder.h ../corelib/tools/qtimeline.h ../corelib/tools/qvarlengtharray.h ../corelib/tools/qvector.h ../../include/QtCore/QtCore
+ SYNCQT.HEADER_CLASSES = ../../include/QtCore/QAbstractState ../../include/QtCore/QAbstractTransition ../../include/QtCore/QEventTransition ../../include/QtCore/QFinalState ../../include/QtCore/QHistoryState ../../include/QtCore/QSignalTransition ../../include/QtCore/QState ../../include/QtCore/QStateMachine ../../include/QtCore/QAtomicInt ../../include/QtCore/QAtomicPointer ../../include/QtCore/QBasicAtomicInt ../../include/QtCore/QBasicAtomicPointer ../../include/QtCore/QMutex ../../include/QtCore/QMutexLocker ../../include/QtCore/QMutexData ../../include/QtCore/QReadWriteLock ../../include/QtCore/QReadLocker ../../include/QtCore/QWriteLocker ../../include/QtCore/QSemaphore ../../include/QtCore/QThread ../../include/QtCore/QThreadStorageData ../../include/QtCore/QThreadStorage ../../include/QtCore/QWaitCondition ../../include/QtCore/QXmlStreamStringRef ../../include/QtCore/QXmlStreamAttribute ../../include/QtCore/QXmlStreamAttributes ../../include/QtCore/QXmlStreamNamespaceDeclaration ../../include/QtCore/QXmlStreamNamespaceDeclarations ../../include/QtCore/QXmlStreamNotationDeclaration ../../include/QtCore/QXmlStreamNotationDeclarations ../../include/QtCore/QXmlStreamEntityDeclaration ../../include/QtCore/QXmlStreamEntityDeclarations ../../include/QtCore/QXmlStreamEntityResolver ../../include/QtCore/QXmlStreamReader ../../include/QtCore/QXmlStreamWriter ../../include/QtCore/QFuture ../../include/QtCore/QFutureIterator ../../include/QtCore/QMutableFutureIterator ../../include/QtCore/QFutureInterfaceBase ../../include/QtCore/QFutureInterface ../../include/QtCore/QFutureSynchronizer ../../include/QtCore/QFutureWatcherBase ../../include/QtCore/QFutureWatcher ../../include/QtCore/QRunnable ../../include/QtCore/QtConcurrentFilter ../../include/QtCore/QtConcurrentMap ../../include/QtCore/QtConcurrentRun ../../include/QtCore/QThreadPool ../../include/QtCore/QAbstractEventDispatcher ../../include/QtCore/QModelIndex ../../include/QtCore/QPersistentModelIndex ../../include/QtCore/QModelIndexList ../../include/QtCore/QAbstractItemModel ../../include/QtCore/QAbstractTableModel ../../include/QtCore/QAbstractListModel ../../include/QtCore/QBasicTimer ../../include/QtCore/QCoreApplication ../../include/QtCore/QtCleanUpFunction ../../include/QtCore/QEvent ../../include/QtCore/QTimerEvent ../../include/QtCore/QChildEvent ../../include/QtCore/QCustomEvent ../../include/QtCore/QDynamicPropertyChangeEvent ../../include/QtCore/QEventLoop ../../include/QtCore/QMetaMethod ../../include/QtCore/QMetaEnum ../../include/QtCore/QMetaProperty ../../include/QtCore/QMetaClassInfo ../../include/QtCore/QMetaType ../../include/QtCore/QMetaTypeId ../../include/QtCore/QMetaTypeId2 ../../include/QtCore/QMimeData ../../include/QtCore/QObjectList ../../include/QtCore/QObjectData ../../include/QtCore/QObject ../../include/QtCore/QObjectUserData ../../include/QtCore/QObjectCleanupHandler ../../include/QtCore/QGenericArgument ../../include/QtCore/QGenericReturnArgument ../../include/QtCore/QArgument ../../include/QtCore/QReturnArgument ../../include/QtCore/QMetaObject ../../include/QtCore/QMetaObjectAccessor ../../include/QtCore/QMetaObjectExtraData ../../include/QtCore/QPointer ../../include/QtCore/QSharedMemory ../../include/QtCore/QSignalMapper ../../include/QtCore/QSocketNotifier ../../include/QtCore/QSystemSemaphore ../../include/QtCore/QTimer ../../include/QtCore/QTranslator ../../include/QtCore/QVariant ../../include/QtCore/QVariantList ../../include/QtCore/QVariantMap ../../include/QtCore/QVariantHash ../../include/QtCore/QVariantComparisonHelper ../../include/QtCore/QFactoryInterface ../../include/QtCore/QLibrary ../../include/QtCore/QtPlugin ../../include/QtCore/QtPluginInstanceFunction ../../include/QtCore/QPluginLoader ../../include/QtCore/QUuid ../../include/QtCore/QtEndian ../../include/QtCore/QtGlobal ../../include/QtCore/QIntegerForSize ../../include/QtCore/QNoImplicitBoolCast ../../include/QtCore/Q_INT8 ../../include/QtCore/Q_UINT8 ../../include/QtCore/Q_INT16 ../../include/QtCore/Q_UINT16 ../../include/QtCore/Q_INT32 ../../include/QtCore/Q_UINT32 ../../include/QtCore/Q_INT64 ../../include/QtCore/Q_UINT64 ../../include/QtCore/Q_LLONG ../../include/QtCore/Q_ULLONG ../../include/QtCore/Q_LONG ../../include/QtCore/Q_ULONG ../../include/QtCore/QSysInfo ../../include/QtCore/QtMsgHandler ../../include/QtCore/QGlobalStatic ../../include/QtCore/QGlobalStaticDeleter ../../include/QtCore/QBool ../../include/QtCore/QTypeInfo ../../include/QtCore/QFlag ../../include/QtCore/QIncompatibleFlag ../../include/QtCore/QFlags ../../include/QtCore/QForeachContainer ../../include/QtCore/QForeachContainerBase ../../include/QtCore/QLibraryInfo ../../include/QtCore/Qt ../../include/QtCore/QInternal ../../include/QtCore/QCOORD ../../include/QtCore/QtConfig ../../include/QtCore/QTextCodec ../../include/QtCore/QTextEncoder ../../include/QtCore/QTextDecoder ../../include/QtCore/QTextCodecFactoryInterface ../../include/QtCore/QTextCodecPlugin ../../include/QtCore/QAbstractFileEngine ../../include/QtCore/QAbstractFileEngineHandler ../../include/QtCore/QAbstractFileEngineIterator ../../include/QtCore/QBuffer ../../include/QtCore/QDataStream ../../include/QtCore/QtDebug ../../include/QtCore/QDebug ../../include/QtCore/QNoDebug ../../include/QtCore/QDir ../../include/QtCore/QDirIterator ../../include/QtCore/QFile ../../include/QtCore/QFileInfo ../../include/QtCore/QFileInfoList ../../include/QtCore/QFileInfoListIterator ../../include/QtCore/QFileSystemWatcher ../../include/QtCore/QFSFileEngine ../../include/QtCore/QIODevice ../../include/QtCore/Q_PID ../../include/QtCore/QProcessEnvironment ../../include/QtCore/QProcess ../../include/QtCore/QResource ../../include/QtCore/QSettings ../../include/QtCore/QTemporaryFile ../../include/QtCore/QTextStream ../../include/QtCore/QTextStreamFunction ../../include/QtCore/QTextStreamManipulator ../../include/QtCore/QTS ../../include/QtCore/QTextIStream ../../include/QtCore/QTextOStream ../../include/QtCore/QUrl ../../include/QtCore/QAbstractAnimation ../../include/QtCore/QAnimationDriver ../../include/QtCore/QAnimationGroup ../../include/QtCore/QParallelAnimationGroup ../../include/QtCore/QPauseAnimation ../../include/QtCore/QPropertyAnimation ../../include/QtCore/QSequentialAnimationGroup ../../include/QtCore/QVariantAnimation ../../include/QtCore/QtAlgorithms ../../include/QtCore/QBitArray ../../include/QtCore/QBitRef ../../include/QtCore/QByteArray ../../include/QtCore/QByteRef ../../include/QtCore/QByteArrayMatcher ../../include/QtCore/QCache ../../include/QtCore/QLatin1Char ../../include/QtCore/QChar ../../include/QtCore/QtContainerFwd ../../include/QtCore/QContiguousCacheData ../../include/QtCore/QContiguousCacheTypedData ../../include/QtCore/QContiguousCache ../../include/QtCore/QCryptographicHash ../../include/QtCore/QDate ../../include/QtCore/QTime ../../include/QtCore/QDateTime ../../include/QtCore/QEasingCurve ../../include/QtCore/QElapsedTimer ../../include/QtCore/QHashData ../../include/QtCore/QHashDummyValue ../../include/QtCore/QHashDummyNode ../../include/QtCore/QHashNode ../../include/QtCore/QHash ../../include/QtCore/QMultiHash ../../include/QtCore/QHashIterator ../../include/QtCore/QMutableHashIterator ../../include/QtCore/QLine ../../include/QtCore/QLineF ../../include/QtCore/QLinkedListData ../../include/QtCore/QLinkedListNode ../../include/QtCore/QLinkedList ../../include/QtCore/QLinkedListIterator ../../include/QtCore/QMutableLinkedListIterator ../../include/QtCore/QListData ../../include/QtCore/QList ../../include/QtCore/QListIterator ../../include/QtCore/QMutableListIterator ../../include/QtCore/QSystemLocale ../../include/QtCore/QLocale ../../include/QtCore/QBBSystemLocaleData ../../include/QtCore/QMapData ../../include/QtCore/QMapNode ../../include/QtCore/QMapPayloadNode ../../include/QtCore/QMap ../../include/QtCore/QMultiMap ../../include/QtCore/QMapIterator ../../include/QtCore/QMutableMapIterator ../../include/QtCore/QMargins ../../include/QtCore/QPair ../../include/QtCore/QPoint ../../include/QtCore/QPointF ../../include/QtCore/QQueue ../../include/QtCore/QRect ../../include/QtCore/QRectF ../../include/QtCore/QRegExp ../../include/QtCore/QScopedPointerDeleter ../../include/QtCore/QScopedPointerArrayDeleter ../../include/QtCore/QScopedPointerPodDeleter ../../include/QtCore/QScopedPointer ../../include/QtCore/QScopedArrayPointer ../../include/QtCore/QScopedValueRollback ../../include/QtCore/QSet ../../include/QtCore/QSetIterator ../../include/QtCore/QMutableSetIterator ../../include/QtCore/QSharedData ../../include/QtCore/QSharedDataPointer ../../include/QtCore/QExplicitlySharedDataPointer ../../include/QtCore/QSharedPointer ../../include/QtCore/QWeakPointer ../../include/QtCore/QSize ../../include/QtCore/QSizeF ../../include/QtCore/QStack ../../include/QtCore/QStdWString ../../include/QtCore/QString ../../include/QtCore/QLatin1String ../../include/QtCore/QCharRef ../../include/QtCore/QConstString ../../include/QtCore/QStringRef ../../include/QtCore/QLatin1Literal ../../include/QtCore/QAbstractConcatenable ../../include/QtCore/QConcatenable ../../include/QtCore/QStringBuilder ../../include/QtCore/QStringListIterator ../../include/QtCore/QMutableStringListIterator ../../include/QtCore/QStringList ../../include/QtCore/QStringMatcher ../../include/QtCore/QTextBoundaryFinder ../../include/QtCore/QTimeLine ../../include/QtCore/QVarLengthArray ../../include/QtCore/QVectorData ../../include/QtCore/QVectorTypedData ../../include/QtCore/QVector ../../include/QtCore/QVectorIterator ../../include/QtCore/QMutableVectorIterator
+ SYNCQT.PRIVATE_HEADER_FILES = ../corelib/statemachine/qabstractstate_p.h ../corelib/statemachine/qabstracttransition_p.h ../corelib/statemachine/qeventtransition_p.h ../corelib/statemachine/qhistorystate_p.h ../corelib/statemachine/qsignaleventgenerator_p.h ../corelib/statemachine/qsignaltransition_p.h ../corelib/statemachine/qstate_p.h ../corelib/statemachine/qstatemachine_p.h ../corelib/thread/qmutex_p.h ../corelib/thread/qmutexpool_p.h ../corelib/thread/qorderedmutexlocker_p.h ../corelib/thread/qreadwritelock_p.h ../corelib/thread/qthread_p.h ../corelib/xml/qxmlstream_p.h ../corelib/xml/qxmlutils_p.h ../corelib/concurrent/qfutureinterface_p.h ../corelib/concurrent/qfuturewatcher_p.h ../corelib/concurrent/qthreadpool_p.h ../corelib/kernel/qabstracteventdispatcher_p.h ../corelib/kernel/qabstractitemmodel_p.h ../corelib/kernel/qcore_mac_p.h ../corelib/kernel/qcore_symbian_p.h ../corelib/kernel/qcore_unix_p.h ../corelib/kernel/qcoreapplication_p.h ../corelib/kernel/qcorecmdlineargs_p.h ../corelib/kernel/qcoreglobaldata_p.h ../corelib/kernel/qcrashhandler_p.h ../corelib/kernel/qeventdispatcher_blackberry_p.h ../corelib/kernel/qeventdispatcher_glib_p.h ../corelib/kernel/qeventdispatcher_symbian_p.h ../corelib/kernel/qeventdispatcher_unix_p.h ../corelib/kernel/qeventdispatcher_win_p.h ../corelib/kernel/qfunctions_p.h ../corelib/kernel/qmetaobject_p.h ../corelib/kernel/qobject_p.h ../corelib/kernel/qsharedmemory_p.h ../corelib/kernel/qsystemerror_p.h ../corelib/kernel/qsystemsemaphore_p.h ../corelib/kernel/qtranslator_p.h ../corelib/kernel/qvariant_p.h ../corelib/kernel/qwineventnotifier_p.h ../corelib/plugin/qelfparser_p.h ../corelib/plugin/qfactoryloader_p.h ../corelib/plugin/qlibrary_p.h ../corelib/plugin/qsystemlibrary_p.h ../corelib/global/qnumeric_p.h ../corelib/global/qt_pch.h ../corelib/codecs/qfontlaocodec_p.h ../corelib/codecs/qiconvcodec_p.h ../corelib/codecs/qisciicodec_p.h ../corelib/codecs/qlatincodec_p.h ../corelib/codecs/qsimplecodec_p.h ../corelib/codecs/qtextcodec_p.h ../corelib/codecs/qtsciicodec_p.h ../corelib/codecs/qutfcodec_p.h ../corelib/io/qabstractfileengine_p.h ../corelib/io/qdatastream_p.h ../corelib/io/qdataurl_p.h ../corelib/io/qdir_p.h ../corelib/io/qfile_p.h ../corelib/io/qfileinfo_p.h ../corelib/io/qfilesystemengine_p.h ../corelib/io/qfilesystementry_p.h ../corelib/io/qfilesystemiterator_p.h ../corelib/io/qfilesystemmetadata_p.h ../corelib/io/qfilesystemwatcher_dnotify_p.h ../corelib/io/qfilesystemwatcher_fsevents_p.h ../corelib/io/qfilesystemwatcher_inotify_p.h ../corelib/io/qfilesystemwatcher_kqueue_p.h ../corelib/io/qfilesystemwatcher_p.h ../corelib/io/qfilesystemwatcher_symbian_p.h ../corelib/io/qfilesystemwatcher_win_p.h ../corelib/io/qfsfileengine_iterator_p.h ../corelib/io/qfsfileengine_p.h ../corelib/io/qiodevice_p.h ../corelib/io/qnoncontiguousbytedevice_p.h ../corelib/io/qprocess_p.h ../corelib/io/qresource_iterator_p.h ../corelib/io/qresource_p.h ../corelib/io/qsettings_p.h ../corelib/io/qtldurl_p.h ../corelib/io/qurltlds_p.h ../corelib/io/qwindowspipewriter_p.h ../corelib/animation/qabstractanimation_p.h ../corelib/animation/qanimationgroup_p.h ../corelib/animation/qparallelanimationgroup_p.h ../corelib/animation/qpropertyanimation_p.h ../corelib/animation/qsequentialanimationgroup_p.h ../corelib/animation/qvariantanimation_p.h ../corelib/tools/qbytedata_p.h ../corelib/tools/qdatetime_p.h ../corelib/tools/qharfbuzz_p.h ../corelib/tools/qlocale_data_p.h ../corelib/tools/qlocale_p.h ../corelib/tools/qlocale_tools_p.h ../corelib/tools/qpodlist_p.h ../corelib/tools/qringbuffer_p.h ../corelib/tools/qscopedpointer_p.h ../corelib/tools/qsimd_p.h ../corelib/tools/qtools_p.h ../corelib/tools/qunicodetables_p.h
diff --git a/meta/recipes-qt/qt4/qt4-native.inc b/meta/recipes-qt/qt4/qt4-native.inc
index bb16da6..70bda73 100644
--- a/meta/recipes-qt/qt4/qt4-native.inc
+++ b/meta/recipes-qt/qt4/qt4-native.inc
@@ -18,6 +18,10 @@ SRC_URI = "http://download.qt-project.org/official_releases/qt/4.8/${PV}/qt-ever
file://0002-qkbdtty_qws-fix-build-with-old-kernel-headers.patch \
file://0003-webkit2-set-OUTPUT_DIR-value-if-empty.patch \
file://0021-configure-make-qt4-native-work-with-long-building-pa.patch \
+ file://0029-aarch64_arm64_fix_arch_detection.patch \
+ file://0030-aarch64_arm64_qatomic_support.patch \
+ file://0031-aarch64_arm64_mkspecs.patch \
+ file://0032-aarch64_add_header.patch \
file://g++.conf \
file://linux.conf \
"
diff --git a/meta/recipes-qt/qt4/qt4_arch.inc b/meta/recipes-qt/qt4/qt4_arch.inc
index c1d35ab..07512db 100644
--- a/meta/recipes-qt/qt4/qt4_arch.inc
+++ b/meta/recipes-qt/qt4/qt4_arch.inc
@@ -4,6 +4,7 @@ ARM_INSTRUCTION_SET = "arm"
set_arch() {
case ${TARGET_ARCH} in
+ aarch64) QT_ARCH=aarch64 ;;
arm*) QT_ARCH=arm ;;
i*86*) QT_ARCH=i386 ;;
mips*) QT_ARCH=mips ;;
--
1.9.1
^ permalink raw reply related [flat|nested] 51+ messages in thread* [PATCH 09/24] libpng: add neon option for aarch64
2014-11-07 8:51 [PATCH 00/24] V2: Add machine qemuarm64 Kai Kang
` (7 preceding siblings ...)
2014-11-07 8:51 ` [PATCH 08/24] qt4: add aarch64 support Kai Kang
@ 2014-11-07 8:51 ` Kai Kang
2014-12-16 19:30 ` Koen Kooi
2014-11-07 8:51 ` [PATCH 10/24] sysprof: disable build " Kai Kang
` (16 subsequent siblings)
25 siblings, 1 reply; 51+ messages in thread
From: Kai Kang @ 2014-11-07 8:51 UTC (permalink / raw)
To: ross.burton; +Cc: koen.kooi, openembedded-core
Add neon option for aarch64 just as for arm. It fails with:
| ./.libs/libpng16.so: undefined reference to `png_init_filter_functions_neon'
| collect2: error: ld returned 1 exit status
Signed-off-by: Kai Kang <kai.kang@windriver.com>
---
meta/recipes-multimedia/libpng/libpng_1.6.13.bb | 1 +
1 file changed, 1 insertion(+)
diff --git a/meta/recipes-multimedia/libpng/libpng_1.6.13.bb b/meta/recipes-multimedia/libpng/libpng_1.6.13.bb
index 0c6fd1f..3d32bfe 100644
--- a/meta/recipes-multimedia/libpng/libpng_1.6.13.bb
+++ b/meta/recipes-multimedia/libpng/libpng_1.6.13.bb
@@ -20,6 +20,7 @@ inherit autotools binconfig-disabled pkgconfig
# Work around missing symbols
EXTRA_OECONF_append_arm = " ${@bb.utils.contains("TUNE_FEATURES", "neon", "--enable-arm-neon=on", "--enable-arm-neon=off" ,d)}"
+EXTRA_OECONF_append_aarch64 = " ${@bb.utils.contains("TUNE_FEATURES", "neon", "--enable-arm-neon=on", "--enable-arm-neon=off" ,d)}"
PACKAGES =+ "${PN}-tools"
--
1.9.1
^ permalink raw reply related [flat|nested] 51+ messages in thread* Re: [PATCH 09/24] libpng: add neon option for aarch64
2014-11-07 8:51 ` [PATCH 09/24] libpng: add neon option for aarch64 Kai Kang
@ 2014-12-16 19:30 ` Koen Kooi
2014-12-17 8:47 ` Kang Kai
0 siblings, 1 reply; 51+ messages in thread
From: Koen Kooi @ 2014-12-16 19:30 UTC (permalink / raw)
To: Kai Kang; +Cc: openembedded-core, Koen Kooi
> Op 7 nov. 2014, om 09:51 heeft Kai Kang <kai.kang@windriver.com> het volgende geschreven:
>
> Add neon option for aarch64 just as for arm. It fails with:
>
> | ./.libs/libpng16.so: undefined reference to `png_init_filter_functions_neon'
> | collect2: error: ld returned 1 exit status
>
> Signed-off-by: Kai Kang <kai.kang@windriver.com>
> ---
> meta/recipes-multimedia/libpng/libpng_1.6.13.bb | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/meta/recipes-multimedia/libpng/libpng_1.6.13.bb b/meta/recipes-multimedia/libpng/libpng_1.6.13.bb
> index 0c6fd1f..3d32bfe 100644
> --- a/meta/recipes-multimedia/libpng/libpng_1.6.13.bb
> +++ b/meta/recipes-multimedia/libpng/libpng_1.6.13.bb
> @@ -20,6 +20,7 @@ inherit autotools binconfig-disabled pkgconfig
>
> # Work around missing symbols
> EXTRA_OECONF_append_arm = " ${@bb.utils.contains("TUNE_FEATURES", "neon", "--enable-arm-neon=on", "--enable-arm-neon=off" ,d)}"
> +EXTRA_OECONF_append_aarch64 = " ${@bb.utils.contains("TUNE_FEATURES", "neon", "--enable-arm-neon=on", "--enable-arm-neon=off" ,d)}"
You're introducing the same bug in a different way: overeager use of qualifiers. Just drop the _arm bit and it works.
^ permalink raw reply [flat|nested] 51+ messages in thread* Re: [PATCH 09/24] libpng: add neon option for aarch64
2014-12-16 19:30 ` Koen Kooi
@ 2014-12-17 8:47 ` Kang Kai
2014-12-17 11:04 ` Burton, Ross
0 siblings, 1 reply; 51+ messages in thread
From: Kang Kai @ 2014-12-17 8:47 UTC (permalink / raw)
To: Koen Kooi; +Cc: openembedded-core, Koen Kooi
[-- Attachment #1: Type: text/plain, Size: 1365 bytes --]
On 2014年12月17日 03:30, Koen Kooi wrote:
>> Op 7 nov. 2014, om 09:51 heeft Kai Kang <kai.kang@windriver.com> het volgende geschreven:
>>
>> Add neon option for aarch64 just as for arm. It fails with:
>>
>> | ./.libs/libpng16.so: undefined reference to `png_init_filter_functions_neon'
>> | collect2: error: ld returned 1 exit status
>>
>> Signed-off-by: Kai Kang <kai.kang@windriver.com>
>> ---
>> meta/recipes-multimedia/libpng/libpng_1.6.13.bb | 1 +
>> 1 file changed, 1 insertion(+)
>>
>> diff --git a/meta/recipes-multimedia/libpng/libpng_1.6.13.bb b/meta/recipes-multimedia/libpng/libpng_1.6.13.bb
>> index 0c6fd1f..3d32bfe 100644
>> --- a/meta/recipes-multimedia/libpng/libpng_1.6.13.bb
>> +++ b/meta/recipes-multimedia/libpng/libpng_1.6.13.bb
>> @@ -20,6 +20,7 @@ inherit autotools binconfig-disabled pkgconfig
>>
>> # Work around missing symbols
>> EXTRA_OECONF_append_arm = " ${@bb.utils.contains("TUNE_FEATURES", "neon", "--enable-arm-neon=on", "--enable-arm-neon=off" ,d)}"
>> +EXTRA_OECONF_append_aarch64 = " ${@bb.utils.contains("TUNE_FEATURES", "neon", "--enable-arm-neon=on", "--enable-arm-neon=off" ,d)}"
> You're introducing the same bug in a different way: overeager use of qualifiers. Just drop the _arm bit and it works.
>
OK. I'll remove the _arm to fix this issue.
Thanks.
--
Regards,
Neil | Kai Kang
[-- Attachment #2: Type: text/html, Size: 2063 bytes --]
^ permalink raw reply [flat|nested] 51+ messages in thread* Re: [PATCH 09/24] libpng: add neon option for aarch64
2014-12-17 8:47 ` Kang Kai
@ 2014-12-17 11:04 ` Burton, Ross
2014-12-18 1:18 ` Kang Kai
0 siblings, 1 reply; 51+ messages in thread
From: Burton, Ross @ 2014-12-17 11:04 UTC (permalink / raw)
To: Kang Kai; +Cc: Koen Kooi, OE-core, Koen Kooi
[-- Attachment #1: Type: text/plain, Size: 1703 bytes --]
I find Koen's patch for libpng neater so could you merge that into your
qemuarm64 branch? The autobuilder has been doing some builds so this
should be the last stage before it's all merged.
Ross
On 17 December 2014 at 08:47, Kang Kai <Kai.Kang@windriver.com> wrote:
>
> On 2014年12月17日 03:30, Koen Kooi wrote:
>
> Op 7 nov. 2014, om 09:51 heeft Kai Kang <kai.kang@windriver.com> <kai.kang@windriver.com> het volgende geschreven:
>
> Add neon option for aarch64 just as for arm. It fails with:
>
> | ./.libs/libpng16.so: undefined reference to `png_init_filter_functions_neon'
> | collect2: error: ld returned 1 exit status
>
> Signed-off-by: Kai Kang <kai.kang@windriver.com> <kai.kang@windriver.com>
> ---
> meta/recipes-multimedia/libpng/libpng_1.6.13.bb | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/meta/recipes-multimedia/libpng/libpng_1.6.13.bb b/meta/recipes-multimedia/libpng/libpng_1.6.13.bb
> index 0c6fd1f..3d32bfe 100644
> --- a/meta/recipes-multimedia/libpng/libpng_1.6.13.bb
> +++ b/meta/recipes-multimedia/libpng/libpng_1.6.13.bb
> @@ -20,6 +20,7 @@ inherit autotools binconfig-disabled pkgconfig
>
> # Work around missing symbols
> EXTRA_OECONF_append_arm = " ${@bb.utils.contains("TUNE_FEATURES", "neon", "--enable-arm-neon=on", "--enable-arm-neon=off" ,d)}"
> +EXTRA_OECONF_append_aarch64 = " ${@bb.utils.contains("TUNE_FEATURES", "neon", "--enable-arm-neon=on", "--enable-arm-neon=off" ,d)}"
>
> You're introducing the same bug in a different way: overeager use of qualifiers. Just drop the _arm bit and it works.
>
>
>
> OK. I'll remove the _arm to fix this issue.
>
> Thanks.
>
> --
> Regards,
> Neil | Kai Kang
>
>
[-- Attachment #2: Type: text/html, Size: 2903 bytes --]
^ permalink raw reply [flat|nested] 51+ messages in thread* Re: [PATCH 09/24] libpng: add neon option for aarch64
2014-12-17 11:04 ` Burton, Ross
@ 2014-12-18 1:18 ` Kang Kai
0 siblings, 0 replies; 51+ messages in thread
From: Kang Kai @ 2014-12-18 1:18 UTC (permalink / raw)
To: Burton, Ross; +Cc: Koen Kooi, OE-core, Koen Kooi
On 2014年12月17日 19:04, Burton, Ross wrote:
> I find Koen's patch for libpng neater so could you merge that into your
> qemuarm64 branch? The autobuilder has been doing some builds so this
> should be the last stage before it's all merged.
OK. I'll do it.
--Kai
>
> Ross
>
> On 17 December 2014 at 08:47, Kang Kai <Kai.Kang@windriver.com> wrote:
>> On 2014年12月17日 03:30, Koen Kooi wrote:
>>
>> Op 7 nov. 2014, om 09:51 heeft Kai Kang <kai.kang@windriver.com> <kai.kang@windriver.com> het volgende geschreven:
>>
>> Add neon option for aarch64 just as for arm. It fails with:
>>
>> | ./.libs/libpng16.so: undefined reference to `png_init_filter_functions_neon'
>> | collect2: error: ld returned 1 exit status
>>
>> Signed-off-by: Kai Kang <kai.kang@windriver.com> <kai.kang@windriver.com>
>> ---
>> meta/recipes-multimedia/libpng/libpng_1.6.13.bb | 1 +
>> 1 file changed, 1 insertion(+)
>>
>> diff --git a/meta/recipes-multimedia/libpng/libpng_1.6.13.bb b/meta/recipes-multimedia/libpng/libpng_1.6.13.bb
>> index 0c6fd1f..3d32bfe 100644
>> --- a/meta/recipes-multimedia/libpng/libpng_1.6.13.bb
>> +++ b/meta/recipes-multimedia/libpng/libpng_1.6.13.bb
>> @@ -20,6 +20,7 @@ inherit autotools binconfig-disabled pkgconfig
>>
>> # Work around missing symbols
>> EXTRA_OECONF_append_arm = " ${@bb.utils.contains("TUNE_FEATURES", "neon", "--enable-arm-neon=on", "--enable-arm-neon=off" ,d)}"
>> +EXTRA_OECONF_append_aarch64 = " ${@bb.utils.contains("TUNE_FEATURES", "neon", "--enable-arm-neon=on", "--enable-arm-neon=off" ,d)}"
>>
>> You're introducing the same bug in a different way: overeager use of qualifiers. Just drop the _arm bit and it works.
>>
>>
>>
>> OK. I'll remove the _arm to fix this issue.
>>
>> Thanks.
>>
>> --
>> Regards,
>> Neil | Kai Kang
>>
>>
--
Regards,
Neil | Kai Kang
^ permalink raw reply [flat|nested] 51+ messages in thread
* [PATCH 10/24] sysprof: disable build for aarch64
2014-11-07 8:51 [PATCH 00/24] V2: Add machine qemuarm64 Kai Kang
` (8 preceding siblings ...)
2014-11-07 8:51 ` [PATCH 09/24] libpng: add neon option for aarch64 Kai Kang
@ 2014-11-07 8:51 ` Kai Kang
2014-11-07 8:51 ` [PATCH 11/24] lttng: recognize aarch64 Kai Kang
` (15 subsequent siblings)
25 siblings, 0 replies; 51+ messages in thread
From: Kai Kang @ 2014-11-07 8:51 UTC (permalink / raw)
To: ross.burton; +Cc: koen.kooi, openembedded-core
From: Joe Slater <jslater@windriver.com>
Add COMPATIBLE_HOST to the recipe and prohibit
building for aarch64 and aarch64_be.
Signed-off-by: Joe Slater <jslater@windriver.com>
---
meta/recipes-kernel/sysprof/sysprof_git.bb | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/meta/recipes-kernel/sysprof/sysprof_git.bb b/meta/recipes-kernel/sysprof/sysprof_git.bb
index ef1e270..cfc814f 100644
--- a/meta/recipes-kernel/sysprof/sysprof_git.bb
+++ b/meta/recipes-kernel/sysprof/sysprof_git.bb
@@ -18,3 +18,8 @@ SRC_URI_append_mips64 = " file://rmb-mips.patch"
S = "${WORKDIR}/git"
inherit autotools pkgconfig
+
+# We do not yet work for aarch64.
+#
+COMPATIBLE_HOST = "^(?!aarch64).*"
+
--
1.9.1
^ permalink raw reply related [flat|nested] 51+ messages in thread* [PATCH 11/24] lttng: recognize aarch64
2014-11-07 8:51 [PATCH 00/24] V2: Add machine qemuarm64 Kai Kang
` (9 preceding siblings ...)
2014-11-07 8:51 ` [PATCH 10/24] sysprof: disable build " Kai Kang
@ 2014-11-07 8:51 ` Kai Kang
2014-11-07 8:51 ` [PATCH 12/24] guile: allow compilation for aarch64 Kai Kang
` (14 subsequent siblings)
25 siblings, 0 replies; 51+ messages in thread
From: Kai Kang @ 2014-11-07 8:51 UTC (permalink / raw)
To: ross.burton; +Cc: koen.kooi, openembedded-core
From: Joe Slater <jslater@windriver.com>
Add aarch64 architecture to liburcu and lttng-ust.
Internally it is treated the same as "arm".
Signed-off-by: Joe Slater <jslater@windriver.com>
---
meta/recipes-kernel/lttng/lttng-ust/add-aarch64.patch | 19 +++++++++++++++++++
meta/recipes-kernel/lttng/lttng-ust_2.5.0.bb | 1 +
meta/recipes-support/liburcu/files/aarch64.patch | 19 +++++++++++++++++++
meta/recipes-support/liburcu/liburcu_0.8.4.bb | 1 +
4 files changed, 40 insertions(+)
create mode 100644 meta/recipes-kernel/lttng/lttng-ust/add-aarch64.patch
create mode 100644 meta/recipes-support/liburcu/files/aarch64.patch
diff --git a/meta/recipes-kernel/lttng/lttng-ust/add-aarch64.patch b/meta/recipes-kernel/lttng/lttng-ust/add-aarch64.patch
new file mode 100644
index 0000000..cec5410
--- /dev/null
+++ b/meta/recipes-kernel/lttng/lttng-ust/add-aarch64.patch
@@ -0,0 +1,19 @@
+lttng-ust: add aarch64 recognition
+
+Treat the same as "arm".
+
+Upstream-Status: Pending
+
+Signed-off-by: joe.slater@windriver.com
+
+
+--- a/configure.ac
++++ b/configure.ac
+@@ -230,6 +230,7 @@ changequote([,])dnl
+ s390) NO_UNALIGNED_ACCESS=1 ;;
+ s390x) NO_UNALIGNED_ACCESS=1 ;;
+ arm*) NO_UNALIGNED_ACCESS=1 ;;
++ aarch64) NO_UNALIGNED_ACCESS=1 ;;
+ mips*) NO_UNALIGNED_ACCESS=1 ;;
+ tile*) NO_UNALIGNED_ACCESS=1 ;;
+ *) AC_MSG_ERROR([unable to detect alignment requirements (unsupported architecture ($host_cpu)?)]) ;;
diff --git a/meta/recipes-kernel/lttng/lttng-ust_2.5.0.bb b/meta/recipes-kernel/lttng/lttng-ust_2.5.0.bb
index 71ea5bc..e07d3c7 100644
--- a/meta/recipes-kernel/lttng/lttng-ust_2.5.0.bb
+++ b/meta/recipes-kernel/lttng/lttng-ust_2.5.0.bb
@@ -24,6 +24,7 @@ PE = "2"
SRC_URI = "git://git.lttng.org/lttng-ust.git;branch=stable-2.5 \
file://lttng-ust-doc-examples-disable.patch \
+ file://add-aarch64.patch \
"
S = "${WORKDIR}/git"
diff --git a/meta/recipes-support/liburcu/files/aarch64.patch b/meta/recipes-support/liburcu/files/aarch64.patch
new file mode 100644
index 0000000..c6cc8c2
--- /dev/null
+++ b/meta/recipes-support/liburcu/files/aarch64.patch
@@ -0,0 +1,19 @@
+libucru: recognize aarch64
+
+Make the same as "arm" internally.
+
+Upstream-Status: Pending
+
+Signed-off-by: joe.slater@windriver.com
+
+
+--- a/configure.ac
++++ b/configure.ac
+@@ -77,6 +77,7 @@ AS_CASE([$host_cpu],
+ [alpha*], [ARCHTYPE="alpha"],
+ [ia64], [ARCHTYPE="gcc"],
+ [arm*], [ARCHTYPE="arm"],
++ [aarch64], [ARCHTYPE="arm"],
+ [mips*], [ARCHTYPE="mips"],
+ [tile*], [ARCHTYPE="gcc"],
+ [ARCHTYPE="unknown"]
diff --git a/meta/recipes-support/liburcu/liburcu_0.8.4.bb b/meta/recipes-support/liburcu/liburcu_0.8.4.bb
index 963029e..083b4cb 100644
--- a/meta/recipes-support/liburcu/liburcu_0.8.4.bb
+++ b/meta/recipes-support/liburcu/liburcu_0.8.4.bb
@@ -9,6 +9,7 @@ LIC_FILES_CHKSUM = "file://LICENSE;md5=0f060c30a27922ce9c0d557a639b4fa3 \
SRC_URI = "http://lttng.org/files/urcu/userspace-rcu-${PV}.tar.bz2 \
file://Revert-Blacklist-ARM-gcc-4.8.0-4.8.1-4.8.2.patch \
+ file://aarch64.patch \
"
SRC_URI[md5sum] = "2ca6671b20a550aa0e8020a1a9a96fd4"
--
1.9.1
^ permalink raw reply related [flat|nested] 51+ messages in thread* [PATCH 12/24] guile: allow compilation for aarch64
2014-11-07 8:51 [PATCH 00/24] V2: Add machine qemuarm64 Kai Kang
` (10 preceding siblings ...)
2014-11-07 8:51 ` [PATCH 11/24] lttng: recognize aarch64 Kai Kang
@ 2014-11-07 8:51 ` Kai Kang
2014-11-07 8:51 ` [PATCH 13/24] libunwind: add aarch64 support Kai Kang
` (13 subsequent siblings)
25 siblings, 0 replies; 51+ messages in thread
From: Kai Kang @ 2014-11-07 8:51 UTC (permalink / raw)
To: ross.burton; +Cc: koen.kooi, openembedded-core
From: Joe Slater <jslater@windriver.com>
Add aarch64 endianness specification to scm file.
Signed-off-by: Joe Slater <jslater@windriver.com>
---
meta/recipes-devtools/guile/files/arm_aarch64.patch | 19 +++++++++++++++++++
meta/recipes-devtools/guile/guile_2.0.11.bb | 1 +
2 files changed, 20 insertions(+)
create mode 100644 meta/recipes-devtools/guile/files/arm_aarch64.patch
diff --git a/meta/recipes-devtools/guile/files/arm_aarch64.patch b/meta/recipes-devtools/guile/files/arm_aarch64.patch
new file mode 100644
index 0000000..f1788b6
--- /dev/null
+++ b/meta/recipes-devtools/guile/files/arm_aarch64.patch
@@ -0,0 +1,19 @@
+guile: add aarch64 recognition
+
+Assume little-endian.
+
+Upstream-Status: Pending
+
+Signed-off-by: joe.slater@windriver.com
+
+--- a/module/system/base/target.scm
++++ b/module/system/base/target.scm
+@@ -70,6 +70,8 @@
+ ((member cpu '("sparc" "sparc64" "powerpc" "powerpc64" "spu"
+ "mips" "mips64"))
+ (endianness big))
++ ((string-match "^aarch64" cpu)
++ (endianness little))
+ ((string-match "^arm.*eb" cpu)
+ (endianness big))
+ ((string-match "^arm.*" cpu)
diff --git a/meta/recipes-devtools/guile/guile_2.0.11.bb b/meta/recipes-devtools/guile/guile_2.0.11.bb
index bd23c2b..f2c0759 100644
--- a/meta/recipes-devtools/guile/guile_2.0.11.bb
+++ b/meta/recipes-devtools/guile/guile_2.0.11.bb
@@ -19,6 +19,7 @@ SRC_URI = "${GNU_MIRROR}/guile/guile-${PV}.tar.xz \
file://opensuse/guile-64bit.patch \
file://guile_2.0.6_fix_sed_error.patch \
file://arm_endianness.patch \
+ file://arm_aarch64.patch \
file://workaround-ice-ssa-corruption.patch \
"
--
1.9.1
^ permalink raw reply related [flat|nested] 51+ messages in thread* [PATCH 13/24] libunwind: add aarch64 support
2014-11-07 8:51 [PATCH 00/24] V2: Add machine qemuarm64 Kai Kang
` (11 preceding siblings ...)
2014-11-07 8:51 ` [PATCH 12/24] guile: allow compilation for aarch64 Kai Kang
@ 2014-11-07 8:51 ` Kai Kang
2014-12-08 20:56 ` Burton, Ross
2014-11-07 8:51 ` [PATCH 14/24] runqemu: add qemuarm64 support Kai Kang
` (12 subsequent siblings)
25 siblings, 1 reply; 51+ messages in thread
From: Kai Kang @ 2014-11-07 8:51 UTC (permalink / raw)
To: ross.burton; +Cc: koen.kooi, openembedded-core
From: Fathi Boudra <fathi.boudra@linaro.org>
* pass --enable-debug-frame on aarch64 architecture
* include patches:
- aarch64 port (backported from upstream)
- Support-building-with-older-compilers (fix undefined reference to
`unreachable' on older compilers)
Signed-off-by: Fathi Boudra <fathi.boudra@linaro.org>
---
.../libunwind/libunwind-1.1/AArch64-port.patch | 2529 ++++++++++++++++++++
.../Support-building-with-older-compilers.patch | 72 +
meta/recipes-support/libunwind/libunwind.inc | 1 +
meta/recipes-support/libunwind/libunwind_1.1.bb | 5 +
4 files changed, 2607 insertions(+)
create mode 100644 meta/recipes-support/libunwind/libunwind-1.1/AArch64-port.patch
create mode 100644 meta/recipes-support/libunwind/libunwind-1.1/Support-building-with-older-compilers.patch
diff --git a/meta/recipes-support/libunwind/libunwind-1.1/AArch64-port.patch b/meta/recipes-support/libunwind/libunwind-1.1/AArch64-port.patch
new file mode 100644
index 0000000..228ec32
--- /dev/null
+++ b/meta/recipes-support/libunwind/libunwind-1.1/AArch64-port.patch
@@ -0,0 +1,2529 @@
+From ac6c0a6535975f1dc2da6e4e2766614baac2a14a Mon Sep 17 00:00:00 2001
+From: Yvan Roux <yvan.roux@linaro.org>
+Date: Sat, 11 May 2013 09:18:23 -0600
+Subject: [PATCH] AArch64 port.
+
+Upstream-Status: Backport
+
+---
+ Makefile.am | 6
+ README | 1
+ configure.ac | 6
+ include/libunwind-aarch64.h | 187 ++++++++++++++++++++++
+ include/libunwind.h.in | 4
+ include/tdep-aarch64/dwarf-config.h | 52 ++++++
+ include/tdep-aarch64/jmpbuf.h | 33 +++
+ include/tdep-aarch64/libunwind_i.h | 294 +++++++++++++++++++++++++++++++++++
+ include/tdep/dwarf-config.h | 4
+ include/tdep/jmpbuf.h | 2
+ include/tdep/libunwind_i.h.in | 4
+ src/Makefile.am | 39 ++++
+ src/aarch64/Gcreate_addr_space.c | 60 +++++++
+ src/aarch64/Gget_proc_info.c | 39 ++++
+ src/aarch64/Gget_save_loc.c | 100 +++++++++++
+ src/aarch64/Gglobal.c | 57 ++++++
+ src/aarch64/Ginit.c | 187 ++++++++++++++++++++++
+ src/aarch64/Ginit_local.c | 55 ++++++
+ src/aarch64/Ginit_remote.c | 45 +++++
+ src/aarch64/Gis_signal_frame.c | 64 +++++++
+ src/aarch64/Gregs.c | 113 +++++++++++++
+ src/aarch64/Gresume.c | 177 +++++++++++++++++++++
+ src/aarch64/Gstep.c | 129 +++++++++++++++
+ src/aarch64/Lcreate_addr_space.c | 5
+ src/aarch64/Lget_proc_info.c | 5
+ src/aarch64/Lget_save_loc.c | 5
+ src/aarch64/Lglobal.c | 5
+ src/aarch64/Linit.c | 5
+ src/aarch64/Linit_local.c | 5
+ src/aarch64/Linit_remote.c | 5
+ src/aarch64/Lis_signal_frame.c | 5
+ src/aarch64/Lregs.c | 5
+ src/aarch64/Lresume.c | 5
+ src/aarch64/Lstep.c | 5
+ src/aarch64/gen-offsets.c | 68 ++++++++
+ src/aarch64/init.h | 127 +++++++++++++++
+ src/aarch64/is_fpreg.c | 32 +++
+ src/aarch64/offsets.h | 49 +++++
+ src/aarch64/regname.c | 106 ++++++++++++
+ src/aarch64/siglongjmp.S | 12 +
+ src/aarch64/unwind_i.h | 43 +++++
+ src/coredump/_UCD_access_reg_linux.c | 5
+ src/ptrace/_UPT_reg_offset.c | 36 ++++
+ 43 files changed, 2184 insertions(+), 7 deletions(-)
+ create mode 100644 include/libunwind-aarch64.h
+ create mode 100644 include/tdep-aarch64/dwarf-config.h
+ create mode 100644 include/tdep-aarch64/jmpbuf.h
+ create mode 100644 include/tdep-aarch64/libunwind_i.h
+ create mode 100644 src/aarch64/Gcreate_addr_space.c
+ create mode 100644 src/aarch64/Gget_proc_info.c
+ create mode 100644 src/aarch64/Gget_save_loc.c
+ create mode 100644 src/aarch64/Gglobal.c
+ create mode 100644 src/aarch64/Ginit.c
+ create mode 100644 src/aarch64/Ginit_local.c
+ create mode 100644 src/aarch64/Ginit_remote.c
+ create mode 100644 src/aarch64/Gis_signal_frame.c
+ create mode 100644 src/aarch64/Gregs.c
+ create mode 100644 src/aarch64/Gresume.c
+ create mode 100644 src/aarch64/Gstep.c
+ create mode 100644 src/aarch64/Lcreate_addr_space.c
+ create mode 100644 src/aarch64/Lget_proc_info.c
+ create mode 100644 src/aarch64/Lget_save_loc.c
+ create mode 100644 src/aarch64/Lglobal.c
+ create mode 100644 src/aarch64/Linit.c
+ create mode 100644 src/aarch64/Linit_local.c
+ create mode 100644 src/aarch64/Linit_remote.c
+ create mode 100644 src/aarch64/Lis_signal_frame.c
+ create mode 100644 src/aarch64/Lregs.c
+ create mode 100644 src/aarch64/Lresume.c
+ create mode 100644 src/aarch64/Lstep.c
+ create mode 100644 src/aarch64/gen-offsets.c
+ create mode 100644 src/aarch64/init.h
+ create mode 100644 src/aarch64/is_fpreg.c
+ create mode 100644 src/aarch64/offsets.h
+ create mode 100644 src/aarch64/regname.c
+ create mode 100644 src/aarch64/siglongjmp.S
+ create mode 100644 src/aarch64/unwind_i.h
+
+--- a/Makefile.am
++++ b/Makefile.am
+@@ -2,6 +2,9 @@ include_HEADERS = include/libunwind-dyna
+ include/libunwind-ptrace.h \
+ include/libunwind-coredump.h
+
++if ARCH_AARCH64
++include_HEADERS += include/libunwind-aarch64.h
++endif
+ if ARCH_ARM
+ include_HEADERS += include/libunwind-arm.h
+ endif
+@@ -41,6 +44,9 @@ SUBDIRS = src tests doc
+ noinst_HEADERS = include/dwarf.h include/dwarf_i.h include/dwarf-eh.h \
+ include/compiler.h include/libunwind_i.h include/mempool.h \
+ include/remote.h \
++ include/tdep-aarch64/dwarf-config.h \
++ include/tdep-aarch64/jmpbuf.h \
++ include/tdep-aarch64/libunwind_i.h \
+ include/tdep-arm/dwarf-config.h include/tdep-arm/ex_tables.h \
+ include/tdep-arm/jmpbuf.h include/tdep-arm/libunwind_i.h \
+ include/tdep-ia64/jmpbuf.h include/tdep-ia64/rse.h \
+--- a/README
++++ b/README
+@@ -9,6 +9,7 @@ several architecture/operating-system co
+ Linux/IA-64: Fully tested and supported.
+ Linux/PARISC: Works well, but C library missing unwind-info.
+ HP-UX/IA-64: Mostly works but known to have some serious limitations.
++ Linux/AArch64: Newly added.
+ Linux/PPC64: Newly added.
+ Linux/SuperH: Newly added.
+ FreeBSD/i386: Newly added.
+--- a/configure.ac
++++ b/configure.ac
+@@ -104,7 +104,7 @@ SET_ARCH([$target_cpu],[target_arch])
+
+ AC_ARG_ENABLE(coredump,
+ AS_HELP_STRING([--enable-coredump],[building libunwind-coredump library]),,
+- [AS_CASE([$host_arch], [arm*|mips*|sh*|x86*], [enable_coredump=yes], [enable_coredump=no])]
++ [AS_CASE([$host_arch], [aarch64*|arm*|mips*|sh*|x86*], [enable_coredump=yes], [enable_coredump=no])]
+ )
+
+ AC_MSG_CHECKING([if we should build libunwind-coredump])
+@@ -121,6 +121,7 @@ AC_MSG_RESULT([$target_os])
+
+ AM_CONDITIONAL(BUILD_COREDUMP, test x$enable_coredump = xyes)
+ AM_CONDITIONAL(REMOTE_ONLY, test x$target_arch != x$host_arch)
++AM_CONDITIONAL(ARCH_AARCH64, test x$target_arch = xaarch64)
+ AM_CONDITIONAL(ARCH_ARM, test x$target_arch = xarm)
+ AM_CONDITIONAL(ARCH_IA64, test x$target_arch = xia64)
+ AM_CONDITIONAL(ARCH_HPPA, test x$target_arch = xhppa)
+@@ -137,7 +138,7 @@ AM_CONDITIONAL(OS_FREEBSD, expr x$target
+ AC_MSG_CHECKING([for ELF helper width])
+ case "${target_arch}" in
+ (arm|hppa|ppc32|x86|sh) use_elf32=yes; AC_MSG_RESULT([32]);;
+-(ia64|ppc64|x86_64) use_elf64=yes; AC_MSG_RESULT([64]);;
++(aarch64|ia64|ppc64|x86_64) use_elf64=yes; AC_MSG_RESULT([64]);;
+ (mips) use_elfxx=yes; AC_MSG_RESULT([xx]);;
+ *) AC_MSG_ERROR([Unknown ELF target: ${target_arch}])
+ esac
+@@ -186,6 +187,7 @@ AS_HELP_STRING([--enable-cxx-exceptions]
+ # C++ exception handling doesn't work too well on x86
+ case $target_arch in
+ x86*) enable_cxx_exceptions=no;;
++ aarch64*) enable_cxx_exceptions=no;;
+ arm*) enable_cxx_exceptions=no;;
+ mips*) enable_cxx_exceptions=no;;
+ *) enable_cxx_exceptions=yes;;
+--- /dev/null
++++ b/include/libunwind-aarch64.h
+@@ -0,0 +1,187 @@
++/* libunwind - a platform-independent unwind library
++ Copyright (C) 2001-2004 Hewlett-Packard Co
++ Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
++ Copyright (C) 2013 Linaro Limited
++
++This file is part of libunwind.
++
++Permission is hereby granted, free of charge, to any person obtaining
++a copy of this software and associated documentation files (the
++"Software"), to deal in the Software without restriction, including
++without limitation the rights to use, copy, modify, merge, publish,
++distribute, sublicense, and/or sell copies of the Software, and to
++permit persons to whom the Software is furnished to do so, subject to
++the following conditions:
++
++The above copyright notice and this permission notice shall be
++included in all copies or substantial portions of the Software.
++
++THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
++EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
++MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
++NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
++LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
++OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
++WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
++
++#ifndef LIBUNWIND_H
++#define LIBUNWIND_H
++
++#if defined(__cplusplus) || defined(c_plusplus)
++extern "C" {
++#endif
++
++#include <inttypes.h>
++#include <stddef.h>
++#include <ucontext.h>
++
++#define UNW_TARGET aarch64
++#define UNW_TARGET_AARCH64 1
++
++#define _U_TDEP_QP_TRUE 0 /* see libunwind-dynamic.h */
++
++/* This needs to be big enough to accommodate "struct cursor", while
++ leaving some slack for future expansion. Changing this value will
++ require recompiling all users of this library. Stack allocation is
++ relatively cheap and unwind-state copying is relatively rare, so we
++ want to err on making it rather too big than too small. */
++
++#define UNW_TDEP_CURSOR_LEN 4096
++
++typedef uint64_t unw_word_t;
++typedef int64_t unw_sword_t;
++
++typedef long double unw_tdep_fpreg_t;
++
++typedef struct
++ {
++ /* no aarch64-specific auxiliary proc-info */
++ }
++unw_tdep_proc_info_t;
++
++typedef enum
++ {
++ /* 64-bit general registers. */
++ UNW_AARCH64_X0,
++ UNW_AARCH64_X1,
++ UNW_AARCH64_X2,
++ UNW_AARCH64_X3,
++ UNW_AARCH64_X4,
++ UNW_AARCH64_X5,
++ UNW_AARCH64_X6,
++ UNW_AARCH64_X7,
++ UNW_AARCH64_X8,
++
++ /* Temporary registers. */
++ UNW_AARCH64_X9,
++ UNW_AARCH64_X10,
++ UNW_AARCH64_X11,
++ UNW_AARCH64_X12,
++ UNW_AARCH64_X13,
++ UNW_AARCH64_X14,
++ UNW_AARCH64_X15,
++
++ /* Intra-procedure-call temporary registers. */
++ UNW_AARCH64_X16,
++ UNW_AARCH64_X17,
++
++ /* Callee-saved registers. */
++ UNW_AARCH64_X18,
++ UNW_AARCH64_X19,
++ UNW_AARCH64_X20,
++ UNW_AARCH64_X21,
++ UNW_AARCH64_X22,
++ UNW_AARCH64_X23,
++ UNW_AARCH64_X24,
++ UNW_AARCH64_X25,
++ UNW_AARCH64_X26,
++ UNW_AARCH64_X27,
++ UNW_AARCH64_X28,
++
++ /* 64-bit frame pointer. */
++ UNW_AARCH64_X29,
++
++ /* 64-bit link register. */
++ UNW_AARCH64_X30,
++
++ /* 64-bit stack pointer. */
++ UNW_AARCH64_SP = 31,
++ UNW_AARCH64_PC,
++ UNW_AARCH64_PSTATE,
++
++ /* 128-bit FP/Advanced SIMD registers. */
++ UNW_AARCH64_V0 = 64,
++ UNW_AARCH64_V1,
++ UNW_AARCH64_V2,
++ UNW_AARCH64_V3,
++ UNW_AARCH64_V4,
++ UNW_AARCH64_V5,
++ UNW_AARCH64_V6,
++ UNW_AARCH64_V7,
++ UNW_AARCH64_V8,
++ UNW_AARCH64_V9,
++ UNW_AARCH64_V10,
++ UNW_AARCH64_V11,
++ UNW_AARCH64_V12,
++ UNW_AARCH64_V13,
++ UNW_AARCH64_V14,
++ UNW_AARCH64_V15,
++ UNW_AARCH64_V16,
++ UNW_AARCH64_V17,
++ UNW_AARCH64_V18,
++ UNW_AARCH64_V19,
++ UNW_AARCH64_V20,
++ UNW_AARCH64_V21,
++ UNW_AARCH64_V22,
++ UNW_AARCH64_V23,
++ UNW_AARCH64_V24,
++ UNW_AARCH64_V25,
++ UNW_AARCH64_V26,
++ UNW_AARCH64_V27,
++ UNW_AARCH64_V28,
++ UNW_AARCH64_V29,
++ UNW_AARCH64_V30,
++ UNW_AARCH64_V31,
++
++ UNW_AARCH64_FPSR,
++ UNW_AARCH64_FPCR,
++
++ /* For AArch64, the CFA is the value of SP (x31) at the call site of the
++ previous frame. */
++ UNW_AARCH64_CFA = UNW_AARCH64_SP,
++
++ UNW_TDEP_LAST_REG = UNW_AARCH64_FPCR,
++
++ UNW_TDEP_IP = UNW_AARCH64_X30,
++ UNW_TDEP_SP = UNW_AARCH64_SP,
++ UNW_TDEP_EH = UNW_AARCH64_X0,
++
++ }
++aarch64_regnum_t;
++
++/* Use R0 through R3 to pass exception handling information. */
++#define UNW_TDEP_NUM_EH_REGS 4
++
++typedef struct unw_tdep_save_loc
++ {
++ /* Additional target-dependent info on a save location. */
++ }
++unw_tdep_save_loc_t;
++
++
++/* On AArch64, we can directly use ucontext_t as the unwind context. */
++typedef ucontext_t unw_tdep_context_t;
++
++#include "libunwind-common.h"
++#include "libunwind-dynamic.h"
++
++#define unw_tdep_getcontext(uc) (getcontext (uc), 0)
++#define unw_tdep_is_fpreg UNW_ARCH_OBJ(is_fpreg)
++
++extern int unw_tdep_is_fpreg (int);
++
++#if defined(__cplusplus) || defined(c_plusplus)
++}
++#endif
++
++#endif /* LIBUNWIND_H */
+--- a/include/libunwind.h.in
++++ b/include/libunwind.h.in
+@@ -3,7 +3,9 @@
+
+ #ifndef UNW_REMOTE_ONLY
+
+-#if defined __arm__
++#if defined __aarch64__
++#include "libunwind-aarch64.h"
++#elif defined __arm__
+ # include "libunwind-arm.h"
+ #elif defined __hppa__
+ # include "libunwind-hppa.h"
+--- /dev/null
++++ b/include/tdep-aarch64/dwarf-config.h
+@@ -0,0 +1,52 @@
++/* libunwind - a platform-independent unwind library
++ Copyright (C) 2008 CodeSourcery
++ Copyright (C) 2012 Tommi Rantala <tt.rantala@gmail.com>
++ Copyright (C) 2013 Linaro Limited
++
++This file is part of libunwind.
++
++Permission is hereby granted, free of charge, to any person obtaining
++a copy of this software and associated documentation files (the
++"Software"), to deal in the Software without restriction, including
++without limitation the rights to use, copy, modify, merge, publish,
++distribute, sublicense, and/or sell copies of the Software, and to
++permit persons to whom the Software is furnished to do so, subject to
++the following conditions:
++
++The above copyright notice and this permission notice shall be
++included in all copies or substantial portions of the Software.
++
++THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
++EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
++MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
++NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
++LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
++OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
++WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
++
++#ifndef dwarf_config_h
++#define dwarf_config_h
++
++/* This matches the value udes by GCC (see
++ gcc/config/aarch64/aarch64.h:DWARF_FRAME_REGISTERS. */
++#define DWARF_NUM_PRESERVED_REGS 97
++
++/* Return TRUE if the ADDR_SPACE uses big-endian byte-order. */
++#define dwarf_is_big_endian(addr_space) 0
++
++#define dwarf_to_unw_regnum(reg) (((reg) <= UNW_AARCH64_V31) ? (reg) : 0)
++
++/* Convert a pointer to a dwarf_cursor structure to a pointer to
++ unw_cursor_t. */
++#define dwarf_to_cursor(c) ((unw_cursor_t *) (c))
++
++typedef struct dwarf_loc
++ {
++ unw_word_t val;
++#ifndef UNW_LOCAL_ONLY
++ unw_word_t type; /* see DWARF_LOC_TYPE_* macros. */
++#endif
++ }
++dwarf_loc_t;
++
++#endif /* dwarf_config_h */
+--- /dev/null
++++ b/include/tdep-aarch64/jmpbuf.h
+@@ -0,0 +1,33 @@
++/* libunwind - a platform-independent unwind library
++ Copyright (C) 2008 CodeSourcery
++ Copyright (C) 2013 Linaro Limited
++
++This file is part of libunwind.
++
++Permission is hereby granted, free of charge, to any person obtaining
++a copy of this software and associated documentation files (the
++"Software"), to deal in the Software without restriction, including
++without limitation the rights to use, copy, modify, merge, publish,
++distribute, sublicense, and/or sell copies of the Software, and to
++permit persons to whom the Software is furnished to do so, subject to
++the following conditions:
++
++The above copyright notice and this permission notice shall be
++included in all copies or substantial portions of the Software.
++
++THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
++EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
++MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
++NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
++LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
++OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
++WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
++
++/* Use glibc's jump-buffer indices; NPTL peeks at SP: */
++
++/* FIXME for AArch64 */
++
++#define JB_SP 13
++#define JB_RP 14
++#define JB_MASK_SAVED 15
++#define JB_MASK 16
+--- /dev/null
++++ b/include/tdep-aarch64/libunwind_i.h
+@@ -0,0 +1,294 @@
++/* libunwind - a platform-independent unwind library
++ Copyright (C) 2001-2005 Hewlett-Packard Co
++ Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
++ Copyright (C) 2013 Linaro Limited
++
++This file is part of libunwind.
++
++Permission is hereby granted, free of charge, to any person obtaining
++a copy of this software and associated documentation files (the
++"Software"), to deal in the Software without restriction, including
++without limitation the rights to use, copy, modify, merge, publish,
++distribute, sublicense, and/or sell copies of the Software, and to
++permit persons to whom the Software is furnished to do so, subject to
++the following conditions:
++
++The above copyright notice and this permission notice shall be
++included in all copies or substantial portions of the Software.
++
++THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
++EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
++MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
++NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
++LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
++OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
++WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
++
++#ifndef AARCH64_LIBUNWIND_I_H
++#define AARCH64_LIBUNWIND_I_H
++
++/* Target-dependent definitions that are internal to libunwind but need
++ to be shared with target-independent code. */
++
++#include <stdlib.h>
++#include <libunwind.h>
++
++#include "elf64.h"
++#include "mempool.h"
++#include "dwarf.h"
++
++typedef struct
++ {
++ /* no aarch64-specific fast trace */
++ }
++unw_tdep_frame_t;
++
++#ifdef UNW_LOCAL_ONLY
++
++typedef unw_word_t aarch64_loc_t;
++
++#else /* !UNW_LOCAL_ONLY */
++
++typedef struct aarch64_loc
++ {
++ unw_word_t w0, w1;
++ }
++aarch64_loc_t;
++
++#endif /* !UNW_LOCAL_ONLY */
++
++struct unw_addr_space
++ {
++ struct unw_accessors acc;
++ int big_endian;
++ unw_caching_policy_t caching_policy;
++#ifdef HAVE_ATOMIC_OPS_H
++ AO_t cache_generation;
++#else
++ uint32_t cache_generation;
++#endif
++ unw_word_t dyn_generation; /* see dyn-common.h */
++ unw_word_t dyn_info_list_addr; /* (cached) dyn_info_list_addr */
++ struct dwarf_rs_cache global_cache;
++ struct unw_debug_frame_list *debug_frames;
++ };
++
++struct cursor
++ {
++ struct dwarf_cursor dwarf; /* must be first */
++ enum
++ {
++ AARCH64_SCF_NONE,
++ AARCH64_SCF_LINUX_RT_SIGFRAME,
++ }
++ sigcontext_format;
++ unw_word_t sigcontext_addr;
++ unw_word_t sigcontext_sp;
++ unw_word_t sigcontext_pc;
++ };
++
++#define DWARF_GET_LOC(l) ((l).val)
++
++#ifdef UNW_LOCAL_ONLY
++# define DWARF_NULL_LOC DWARF_LOC (0, 0)
++# define DWARF_IS_NULL_LOC(l) (DWARF_GET_LOC (l) == 0)
++# define DWARF_LOC(r, t) ((dwarf_loc_t) { .val = (r) })
++# define DWARF_IS_REG_LOC(l) 0
++# define DWARF_REG_LOC(c,r) (DWARF_LOC((unw_word_t) \
++ tdep_uc_addr((c)->as_arg, (r)), 0))
++# define DWARF_MEM_LOC(c,m) DWARF_LOC ((m), 0)
++# define DWARF_FPREG_LOC(c,r) (DWARF_LOC((unw_word_t) \
++ tdep_uc_addr((c)->as_arg, (r)), 0))
++
++static inline int
++dwarf_getfp (struct dwarf_cursor *c, dwarf_loc_t loc, unw_fpreg_t *val)
++{
++ if (!DWARF_GET_LOC (loc))
++ return -1;
++ *val = *(unw_fpreg_t *) DWARF_GET_LOC (loc);
++ return 0;
++}
++
++static inline int
++dwarf_putfp (struct dwarf_cursor *c, dwarf_loc_t loc, unw_fpreg_t val)
++{
++ if (!DWARF_GET_LOC (loc))
++ return -1;
++ *(unw_fpreg_t *) DWARF_GET_LOC (loc) = val;
++ return 0;
++}
++
++static inline int
++dwarf_get (struct dwarf_cursor *c, dwarf_loc_t loc, unw_word_t *val)
++{
++ if (!DWARF_GET_LOC (loc))
++ return -1;
++ *val = *(unw_word_t *) DWARF_GET_LOC (loc);
++ return 0;
++}
++
++static inline int
++dwarf_put (struct dwarf_cursor *c, dwarf_loc_t loc, unw_word_t val)
++{
++ if (!DWARF_GET_LOC (loc))
++ return -1;
++ *(unw_word_t *) DWARF_GET_LOC (loc) = val;
++ return 0;
++}
++
++#else /* !UNW_LOCAL_ONLY */
++# define DWARF_LOC_TYPE_FP (1 << 0)
++# define DWARF_LOC_TYPE_REG (1 << 1)
++# define DWARF_NULL_LOC DWARF_LOC (0, 0)
++# define DWARF_IS_NULL_LOC(l) \
++ ({ dwarf_loc_t _l = (l); _l.val == 0 && _l.type == 0; })
++# define DWARF_LOC(r, t) ((dwarf_loc_t) { .val = (r), .type = (t) })
++# define DWARF_IS_REG_LOC(l) (((l).type & DWARF_LOC_TYPE_REG) != 0)
++# define DWARF_IS_FP_LOC(l) (((l).type & DWARF_LOC_TYPE_FP) != 0)
++# define DWARF_REG_LOC(c,r) DWARF_LOC((r), DWARF_LOC_TYPE_REG)
++# define DWARF_MEM_LOC(c,m) DWARF_LOC ((m), 0)
++# define DWARF_FPREG_LOC(c,r) DWARF_LOC((r), (DWARF_LOC_TYPE_REG \
++ | DWARF_LOC_TYPE_FP))
++
++static inline int
++dwarf_getfp (struct dwarf_cursor *c, dwarf_loc_t loc, unw_fpreg_t *val)
++{
++ char *valp = (char *) &val;
++ unw_word_t addr;
++ int ret;
++
++ if (DWARF_IS_NULL_LOC (loc))
++ return -UNW_EBADREG;
++
++ if (DWARF_IS_REG_LOC (loc))
++ return (*c->as->acc.access_fpreg) (c->as, DWARF_GET_LOC (loc),
++ val, 0, c->as_arg);
++
++ addr = DWARF_GET_LOC (loc);
++ if ((ret = (*c->as->acc.access_mem) (c->as, addr + 0, (unw_word_t *) valp,
++ 0, c->as_arg)) < 0)
++ return ret;
++
++ return (*c->as->acc.access_mem) (c->as, addr + 4, (unw_word_t *) valp + 1, 0,
++ c->as_arg);
++}
++
++static inline int
++dwarf_putfp (struct dwarf_cursor *c, dwarf_loc_t loc, unw_fpreg_t val)
++{
++ char *valp = (char *) &val;
++ unw_word_t addr;
++ int ret;
++
++ if (DWARF_IS_NULL_LOC (loc))
++ return -UNW_EBADREG;
++
++ if (DWARF_IS_REG_LOC (loc))
++ return (*c->as->acc.access_fpreg) (c->as, DWARF_GET_LOC (loc),
++ &val, 1, c->as_arg);
++
++ addr = DWARF_GET_LOC (loc);
++ if ((ret = (*c->as->acc.access_mem) (c->as, addr + 0, (unw_word_t *) valp,
++ 1, c->as_arg)) < 0)
++ return ret;
++
++ return (*c->as->acc.access_mem) (c->as, addr + 4, (unw_word_t *) valp + 1,
++ 1, c->as_arg);
++}
++
++static inline int
++dwarf_get (struct dwarf_cursor *c, dwarf_loc_t loc, unw_word_t *val)
++{
++ if (DWARF_IS_NULL_LOC (loc))
++ return -UNW_EBADREG;
++
++ /* If a code-generator were to save a value of type unw_word_t in a
++ floating-point register, we would have to support this case. I
++ suppose it could happen with MMX registers, but does it really
++ happen? */
++ assert (!DWARF_IS_FP_LOC (loc));
++
++ if (DWARF_IS_REG_LOC (loc))
++ return (*c->as->acc.access_reg) (c->as, DWARF_GET_LOC (loc), val,
++ 0, c->as_arg);
++ else
++ return (*c->as->acc.access_mem) (c->as, DWARF_GET_LOC (loc), val,
++ 0, c->as_arg);
++}
++
++static inline int
++dwarf_put (struct dwarf_cursor *c, dwarf_loc_t loc, unw_word_t val)
++{
++ if (DWARF_IS_NULL_LOC (loc))
++ return -UNW_EBADREG;
++
++ /* If a code-generator were to save a value of type unw_word_t in a
++ floating-point register, we would have to support this case. I
++ suppose it could happen with MMX registers, but does it really
++ happen? */
++ assert (!DWARF_IS_FP_LOC (loc));
++
++ if (DWARF_IS_REG_LOC (loc))
++ return (*c->as->acc.access_reg) (c->as, DWARF_GET_LOC (loc), &val,
++ 1, c->as_arg);
++ else
++ return (*c->as->acc.access_mem) (c->as, DWARF_GET_LOC (loc), &val,
++ 1, c->as_arg);
++}
++
++#endif /* !UNW_LOCAL_ONLY */
++
++
++
++#define tdep_getcontext_trace unw_getcontext
++#define tdep_init_done UNW_OBJ(init_done)
++#define tdep_init UNW_OBJ(init)
++/* Platforms that support UNW_INFO_FORMAT_TABLE need to define
++ tdep_search_unwind_table. */
++#define tdep_search_unwind_table dwarf_search_unwind_table
++#define tdep_find_unwind_table dwarf_find_unwind_table
++#define tdep_uc_addr UNW_OBJ(uc_addr)
++#define tdep_get_elf_image UNW_ARCH_OBJ(get_elf_image)
++#define tdep_access_reg UNW_OBJ(access_reg)
++#define tdep_access_fpreg UNW_OBJ(access_fpreg)
++#define tdep_fetch_frame(c,ip,n) do {} while(0)
++#define tdep_cache_frame(c,rs) do {} while(0)
++#define tdep_reuse_frame(c,rs) do {} while(0)
++#define tdep_stash_frame(c,rs) do {} while(0)
++#define tdep_trace(cur,addr,n) (-UNW_ENOINFO)
++
++#ifdef UNW_LOCAL_ONLY
++# define tdep_find_proc_info(c,ip,n) \
++ dwarf_find_proc_info((c)->as, (ip), &(c)->pi, (n), \
++ (c)->as_arg)
++# define tdep_put_unwind_info(as,pi,arg) \
++ dwarf_put_unwind_info((as), (pi), (arg))
++#else
++# define tdep_find_proc_info(c,ip,n) \
++ (*(c)->as->acc.find_proc_info)((c)->as, (ip), &(c)->pi, (n), \
++ (c)->as_arg)
++# define tdep_put_unwind_info(as,pi,arg) \
++ (*(as)->acc.put_unwind_info)((as), (pi), (arg))
++#endif
++
++#define tdep_get_as(c) ((c)->dwarf.as)
++#define tdep_get_as_arg(c) ((c)->dwarf.as_arg)
++#define tdep_get_ip(c) ((c)->dwarf.ip)
++#define tdep_big_endian(as) ((as)->big_endian)
++
++extern int tdep_init_done;
++
++extern void tdep_init (void);
++extern int tdep_search_unwind_table (unw_addr_space_t as, unw_word_t ip,
++ unw_dyn_info_t *di, unw_proc_info_t *pi,
++ int need_unwind_info, void *arg);
++extern void *tdep_uc_addr (unw_tdep_context_t *uc, int reg);
++extern int tdep_get_elf_image (struct elf_image *ei, pid_t pid, unw_word_t ip,
++ unsigned long *segbase, unsigned long *mapoff,
++ char *path, size_t pathlen);
++extern int tdep_access_reg (struct cursor *c, unw_regnum_t reg,
++ unw_word_t *valp, int write);
++extern int tdep_access_fpreg (struct cursor *c, unw_regnum_t reg,
++ unw_fpreg_t *valp, int write);
++
++#endif /* AARCH64_LIBUNWIND_I_H */
+--- a/include/tdep/dwarf-config.h
++++ b/include/tdep/dwarf-config.h
+@@ -1,7 +1,9 @@
+ /* Provide a real file - not a symlink - as it would cause multiarch conflicts
+ when multiple different arch releases are installed simultaneously. */
+
+-#if defined __arm__
++#if defined __aarch64__
++# include "tdep-aarch64/dwarf-config.h"
++#elif defined __arm__
+ # include "tdep-arm/dwarf-config.h"
+ #elif defined __hppa__
+ # include "tdep-hppa/dwarf-config.h"
+--- a/include/tdep/jmpbuf.h
++++ b/include/tdep/jmpbuf.h
+@@ -3,6 +3,8 @@
+
+ #ifndef UNW_REMOTE_ONLY
+
++#if defined __aarch64__
++# include "tdep-aarch64/jmpbuf.h"
+ #if defined __arm__
+ # include "tdep-arm/jmpbuf.h"
+ #elif defined __hppa__
+--- a/include/tdep/libunwind_i.h.in
++++ b/include/tdep/libunwind_i.h.in
+@@ -3,7 +3,9 @@
+
+ #ifndef UNW_REMOTE_ONLY
+
+-#if defined __arm__
++#if defined __aarch64__
++# include "tdep-aarch64/libunwind_i.h"
++#elif defined __arm__
+ # include "tdep-arm/libunwind_i.h"
+ #elif defined __hppa__
+ # include "tdep-hppa/libunwind_i.h"
+--- a/src/Makefile.am
++++ b/src/Makefile.am
+@@ -170,6 +170,28 @@ libunwind_elfxx_la_SOURCES = elfxx.c
+ noinst_LTLIBRARIES += $(LIBUNWIND_ELF)
+ libunwind_la_LIBADD += $(LIBUNWIND_ELF)
+
++# The list of files that go into libunwind and libunwind-aarch64:
++noinst_HEADERS += aarch64/init.h aarch64/offsets.h aarch64/unwind_i.h
++libunwind_la_SOURCES_aarch64_common = $(libunwind_la_SOURCES_common) \
++ aarch64/is_fpreg.c aarch64/regname.c
++
++# The list of files that go into libunwind:
++libunwind_la_SOURCES_aarch64 = $(libunwind_la_SOURCES_aarch64_common) \
++ $(libunwind_la_SOURCES_local) \
++ aarch64/Lcreate_addr_space.c aarch64/Lget_proc_info.c \
++ aarch64/Lget_save_loc.c aarch64/Lglobal.c aarch64/Linit.c \
++ aarch64/Linit_local.c aarch64/Linit_remote.c \
++ aarch64/Lis_signal_frame.c aarch64/Lregs.c aarch64/Lresume.c \
++ aarch64/Lstep.c
++
++libunwind_aarch64_la_SOURCES_aarch64 = $(libunwind_la_SOURCES_aarch64_common) \
++ $(libunwind_la_SOURCES_generic) \
++ aarch64/Gcreate_addr_space.c aarch64/Gget_proc_info.c \
++ aarch64/Gget_save_loc.c aarch64/Gglobal.c aarch64/Ginit.c \
++ aarch64/Ginit_local.c aarch64/Ginit_remote.c \
++ aarch64/Gis_signal_frame.c aarch64/Gregs.c aarch64/Gresume.c \
++ aarch64/Gstep.c
++
+ # The list of files that go into libunwind and libunwind-arm:
+ noinst_HEADERS += arm/init.h arm/offsets.h arm/unwind_i.h
+ libunwind_la_SOURCES_arm_common = $(libunwind_la_SOURCES_common) \
+@@ -418,6 +440,18 @@ if OS_FREEBSD
+ libunwind_coredump_la_SOURCES += coredump/_UCD_access_reg_freebsd.c
+ endif
+
++if ARCH_AARCH64
++ lib_LTLIBRARIES += libunwind-aarch64.la
++ libunwind_la_SOURCES = $(libunwind_la_SOURCES_aarch64)
++ libunwind_aarch64_la_SOURCES = $(libunwind_aarch64_la_SOURCES_aarch64)
++ libunwind_aarch64_la_LDFLAGS = $(COMMON_SO_LDFLAGS) -version-info $(SOVERSION)
++ libunwind_aarch64_la_LIBADD = libunwind-dwarf-generic.la
++ libunwind_aarch64_la_LIBADD += libunwind-elf64.la
++if !REMOTE_ONLY
++ libunwind_aarch64_la_LIBADD += libunwind.la -lc
++endif
++ libunwind_setjmp_la_SOURCES += aarch64/siglongjmp.S
++else
+ if ARCH_ARM
+ lib_LTLIBRARIES += libunwind-arm.la
+ libunwind_la_SOURCES = $(libunwind_la_SOURCES_arm)
+@@ -545,6 +579,7 @@ endif # ARCH_MIPS
+ endif # ARCH_HPPA
+ endif # ARCH_IA64
+ endif # ARCH_ARM
++endif # ARCH_AARCH64
+
+ # libunwind-setjmp depends on libunwind-$(arch). Therefore must be added
+ # at the end.
+@@ -567,7 +602,8 @@ AM_CPPFLAGS = -I$(top_srcdir)/include -I
+ AM_CCASFLAGS = $(AM_CPPFLAGS)
+ noinst_HEADERS += unwind/unwind-internal.h
+
+-EXTRA_DIST = $(libunwind_la_SOURCES_arm) \
++EXTRA_DIST = $(libunwind_la_SOURCES_aarch64) \
++ $(libunwind_la_SOURCES_arm) \
+ $(libunwind_la_SOURCES_hppa) \
+ $(libunwind_la_SOURCES_ia64) \
+ $(libunwind_la_SOURCES_mips) \
+@@ -579,6 +615,7 @@ EXTRA_DIST = $(libunwind_la_SOURCES_arm)
+ $(libunwind_la_SOURCES_common) \
+ $(libunwind_la_SOURCES_local) \
+ $(libunwind_la_SOURCES_generic) \
++ $(libunwind_aarch64_la_SOURCES_aarch64) \
+ $(libunwind_arm_la_SOURCES_arm) \
+ $(libunwind_hppa_la_SOURCES_hppa) \
+ $(libunwind_ia64_la_SOURCES_ia64) \
+--- /dev/null
++++ b/src/aarch64/Gcreate_addr_space.c
+@@ -0,0 +1,60 @@
++/* libunwind - a platform-independent unwind library
++ Copyright (C) 2012 Tommi Rantala <tt.rantala@gmail.com>
++ Copyright (C) 2013 Linaro Limited
++
++This file is part of libunwind.
++
++Permission is hereby granted, free of charge, to any person obtaining
++a copy of this software and associated documentation files (the
++"Software"), to deal in the Software without restriction, including
++without limitation the rights to use, copy, modify, merge, publish,
++distribute, sublicense, and/or sell copies of the Software, and to
++permit persons to whom the Software is furnished to do so, subject to
++the following conditions:
++
++The above copyright notice and this permission notice shall be
++included in all copies or substantial portions of the Software.
++
++THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
++EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
++MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
++NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
++LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
++OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
++WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
++
++#include <string.h>
++#include <stdlib.h>
++
++#include "unwind_i.h"
++
++PROTECTED unw_addr_space_t
++unw_create_addr_space (unw_accessors_t *a, int byte_order)
++{
++#ifdef UNW_LOCAL_ONLY
++ return NULL;
++#else
++ unw_addr_space_t as;
++
++ /* AArch64 supports little-endian and big-endian. */
++ if (byte_order != 0 && byte_order != __LITTLE_ENDIAN
++ && byte_order != __BIG_ENDIAN)
++ return NULL;
++
++ as = malloc (sizeof (*as));
++ if (!as)
++ return NULL;
++
++ memset (as, 0, sizeof (*as));
++
++ as->acc = *a;
++
++ /* Default to little-endian for AArch64. */
++ if (byte_order == 0 || byte_order == __LITTLE_ENDIAN)
++ as->big_endian = 0;
++ else
++ as->big_endian = 1;
++
++ return as;
++#endif
++}
+--- /dev/null
++++ b/src/aarch64/Gget_proc_info.c
+@@ -0,0 +1,39 @@
++/* libunwind - a platform-independent unwind library
++ Copyright (C) 2008 CodeSourcery
++
++This file is part of libunwind.
++
++Permission is hereby granted, free of charge, to any person obtaining
++a copy of this software and associated documentation files (the
++"Software"), to deal in the Software without restriction, including
++without limitation the rights to use, copy, modify, merge, publish,
++distribute, sublicense, and/or sell copies of the Software, and to
++permit persons to whom the Software is furnished to do so, subject to
++the following conditions:
++
++The above copyright notice and this permission notice shall be
++included in all copies or substantial portions of the Software.
++
++THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
++EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
++MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
++NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
++LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
++OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
++WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
++
++#include "unwind_i.h"
++
++PROTECTED int
++unw_get_proc_info (unw_cursor_t *cursor, unw_proc_info_t *pi)
++{
++ struct cursor *c = (struct cursor *) cursor;
++ int ret;
++
++ ret = dwarf_make_proc_info (&c->dwarf);
++ if (ret < 0)
++ return ret;
++
++ *pi = c->dwarf.pi;
++ return 0;
++}
+--- /dev/null
++++ b/src/aarch64/Gget_save_loc.c
+@@ -0,0 +1,100 @@
++/* libunwind - a platform-independent unwind library
++ Copyright (C) 2008 CodeSourcery
++ Copyright (C) 2012 Tommi Rantala <tt.rantala@gmail.com>
++ Copyright (C) 2013 Linaro Limited
++
++This file is part of libunwind.
++
++Permission is hereby granted, free of charge, to any person obtaining
++a copy of this software and associated documentation files (the
++"Software"), to deal in the Software without restriction, including
++without limitation the rights to use, copy, modify, merge, publish,
++distribute, sublicense, and/or sell copies of the Software, and to
++permit persons to whom the Software is furnished to do so, subject to
++the following conditions:
++
++The above copyright notice and this permission notice shall be
++included in all copies or substantial portions of the Software.
++
++THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
++EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
++MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
++NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
++LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
++OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
++WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
++
++#include "unwind_i.h"
++
++PROTECTED int
++unw_get_save_loc (unw_cursor_t *cursor, int reg, unw_save_loc_t *sloc)
++{
++ struct cursor *c = (struct cursor *) cursor;
++ dwarf_loc_t loc;
++
++ switch (reg)
++ {
++ case UNW_AARCH64_X0:
++ case UNW_AARCH64_X1:
++ case UNW_AARCH64_X2:
++ case UNW_AARCH64_X3:
++ case UNW_AARCH64_X4:
++ case UNW_AARCH64_X5:
++ case UNW_AARCH64_X6:
++ case UNW_AARCH64_X7:
++ case UNW_AARCH64_X8:
++ case UNW_AARCH64_X9:
++ case UNW_AARCH64_X10:
++ case UNW_AARCH64_X11:
++ case UNW_AARCH64_X12:
++ case UNW_AARCH64_X13:
++ case UNW_AARCH64_X14:
++ case UNW_AARCH64_X15:
++ case UNW_AARCH64_X16:
++ case UNW_AARCH64_X17:
++ case UNW_AARCH64_X18:
++ case UNW_AARCH64_X19:
++ case UNW_AARCH64_X20:
++ case UNW_AARCH64_X21:
++ case UNW_AARCH64_X22:
++ case UNW_AARCH64_X23:
++ case UNW_AARCH64_X24:
++ case UNW_AARCH64_X25:
++ case UNW_AARCH64_X26:
++ case UNW_AARCH64_X27:
++ case UNW_AARCH64_X28:
++ case UNW_AARCH64_X29:
++ case UNW_AARCH64_X30:
++ case UNW_AARCH64_SP:
++ case UNW_AARCH64_PC:
++ case UNW_AARCH64_PSTATE:
++ loc = c->dwarf.loc[reg];
++ break;
++
++ default:
++ loc = DWARF_NULL_LOC; /* default to "not saved" */
++ break;
++ }
++
++ memset (sloc, 0, sizeof (*sloc));
++
++ if (DWARF_IS_NULL_LOC (loc))
++ {
++ sloc->type = UNW_SLT_NONE;
++ return 0;
++ }
++
++#if !defined(UNW_LOCAL_ONLY)
++ if (DWARF_IS_REG_LOC (loc))
++ {
++ sloc->type = UNW_SLT_REG;
++ sloc->u.regnum = DWARF_GET_LOC (loc);
++ }
++ else
++#endif
++ {
++ sloc->type = UNW_SLT_MEMORY;
++ sloc->u.addr = DWARF_GET_LOC (loc);
++ }
++ return 0;
++}
+--- /dev/null
++++ b/src/aarch64/Gglobal.c
+@@ -0,0 +1,57 @@
++/* libunwind - a platform-independent unwind library
++ Copyright (C) 2008 CodeSourcery
++ Copyright (C) 2012 Tommi Rantala <tt.rantala@gmail.com>
++ Copyright (C) 2013 Linaro Limited
++
++This file is part of libunwind.
++
++Permission is hereby granted, free of charge, to any person obtaining
++a copy of this software and associated documentation files (the
++"Software"), to deal in the Software without restriction, including
++without limitation the rights to use, copy, modify, merge, publish,
++distribute, sublicense, and/or sell copies of the Software, and to
++permit persons to whom the Software is furnished to do so, subject to
++the following conditions:
++
++The above copyright notice and this permission notice shall be
++included in all copies or substantial portions of the Software.
++
++THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
++EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
++MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
++NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
++LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
++OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
++WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
++
++#include "unwind_i.h"
++#include "dwarf_i.h"
++
++HIDDEN define_lock (aarch64_lock);
++HIDDEN int tdep_init_done;
++
++HIDDEN void
++tdep_init (void)
++{
++ intrmask_t saved_mask;
++
++ sigfillset (&unwi_full_mask);
++
++ lock_acquire (&aarch64_lock, saved_mask);
++ {
++ if (tdep_init_done)
++ /* another thread else beat us to it... */
++ goto out;
++
++ mi_init ();
++
++ dwarf_init ();
++
++#ifndef UNW_REMOTE_ONLY
++ aarch64_local_addr_space_init ();
++#endif
++ tdep_init_done = 1; /* signal that we're initialized... */
++ }
++ out:
++ lock_release (&aarch64_lock, saved_mask);
++}
+--- /dev/null
++++ b/src/aarch64/Ginit.c
+@@ -0,0 +1,187 @@
++/* libunwind - a platform-independent unwind library
++ Copyright (C) 2008 CodeSourcery
++ Copyright (C) 2012 Tommi Rantala <tt.rantala@gmail.com>
++ Copyright (C) 2013 Linaro Limited
++
++This file is part of libunwind.
++
++Permission is hereby granted, free of charge, to any person obtaining
++a copy of this software and associated documentation files (the
++"Software"), to deal in the Software without restriction, including
++without limitation the rights to use, copy, modify, merge, publish,
++distribute, sublicense, and/or sell copies of the Software, and to
++permit persons to whom the Software is furnished to do so, subject to
++the following conditions:
++
++The above copyright notice and this permission notice shall be
++included in all copies or substantial portions of the Software.
++
++THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
++EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
++MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
++NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
++LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
++OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
++WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
++
++#include <stdlib.h>
++#include <string.h>
++
++#include "unwind_i.h"
++
++#ifdef UNW_REMOTE_ONLY
++
++/* unw_local_addr_space is a NULL pointer in this case. */
++PROTECTED unw_addr_space_t unw_local_addr_space;
++
++#else /* !UNW_REMOTE_ONLY */
++
++static struct unw_addr_space local_addr_space;
++
++PROTECTED unw_addr_space_t unw_local_addr_space = &local_addr_space;
++
++static inline void *
++uc_addr (ucontext_t *uc, int reg)
++{
++ if (reg >= UNW_AARCH64_X0 && reg <= UNW_AARCH64_V31)
++ return &uc->uc_mcontext.regs[reg];
++ else
++ return NULL;
++}
++
++# ifdef UNW_LOCAL_ONLY
++
++HIDDEN void *
++tdep_uc_addr (ucontext_t *uc, int reg)
++{
++ return uc_addr (uc, reg);
++}
++
++# endif /* UNW_LOCAL_ONLY */
++
++HIDDEN unw_dyn_info_list_t _U_dyn_info_list;
++
++/* XXX fix me: there is currently no way to locate the dyn-info list
++ by a remote unwinder. On ia64, this is done via a special
++ unwind-table entry. Perhaps something similar can be done with
++ DWARF2 unwind info. */
++
++static void
++put_unwind_info (unw_addr_space_t as, unw_proc_info_t *proc_info, void *arg)
++{
++ /* it's a no-op */
++}
++
++static int
++get_dyn_info_list_addr (unw_addr_space_t as, unw_word_t *dyn_info_list_addr,
++ void *arg)
++{
++ *dyn_info_list_addr = (unw_word_t) &_U_dyn_info_list;
++ return 0;
++}
++
++static int
++access_mem (unw_addr_space_t as, unw_word_t addr, unw_word_t *val, int write,
++ void *arg)
++{
++ if (write)
++ {
++ Debug (16, "mem[%lx] <- %lx\n", addr, *val);
++ *(unw_word_t *) addr = *val;
++ }
++ else
++ {
++ *val = *(unw_word_t *) addr;
++ Debug (16, "mem[%lx] -> %lx\n", addr, *val);
++ }
++ return 0;
++}
++
++static int
++access_reg (unw_addr_space_t as, unw_regnum_t reg, unw_word_t *val, int write,
++ void *arg)
++{
++ unw_word_t *addr;
++ ucontext_t *uc = arg;
++
++ if (unw_is_fpreg (reg))
++ goto badreg;
++
++ if (!(addr = uc_addr (uc, reg)))
++ goto badreg;
++
++ if (write)
++ {
++ *(unw_word_t *) addr = *val;
++ Debug (12, "%s <- %lx\n", unw_regname (reg), *val);
++ }
++ else
++ {
++ *val = *(unw_word_t *) addr;
++ Debug (12, "%s -> %lx\n", unw_regname (reg), *val);
++ }
++ return 0;
++
++ badreg:
++ Debug (1, "bad register number %u\n", reg);
++ return -UNW_EBADREG;
++}
++
++static int
++access_fpreg (unw_addr_space_t as, unw_regnum_t reg, unw_fpreg_t *val,
++ int write, void *arg)
++{
++ ucontext_t *uc = arg;
++ unw_fpreg_t *addr;
++
++ if (!unw_is_fpreg (reg))
++ goto badreg;
++
++ if (!(addr = uc_addr (uc, reg)))
++ goto badreg;
++
++ if (write)
++ {
++ Debug (12, "%s <- %08lx.%08lx.%08lx\n", unw_regname (reg),
++ ((long *)val)[0], ((long *)val)[1], ((long *)val)[2]);
++ *(unw_fpreg_t *) addr = *val;
++ }
++ else
++ {
++ *val = *(unw_fpreg_t *) addr;
++ Debug (12, "%s -> %08lx.%08lx.%08lx\n", unw_regname (reg),
++ ((long *)val)[0], ((long *)val)[1], ((long *)val)[2]);
++ }
++ return 0;
++
++ badreg:
++ Debug (1, "bad register number %u\n", reg);
++ /* attempt to access a non-preserved register */
++ return -UNW_EBADREG;
++}
++
++static int
++get_static_proc_name (unw_addr_space_t as, unw_word_t ip,
++ char *buf, size_t buf_len, unw_word_t *offp,
++ void *arg)
++{
++ return _Uelf64_get_proc_name (as, getpid (), ip, buf, buf_len, offp);
++}
++
++HIDDEN void
++aarch64_local_addr_space_init (void)
++{
++ memset (&local_addr_space, 0, sizeof (local_addr_space));
++ local_addr_space.caching_policy = UNW_CACHE_GLOBAL;
++ local_addr_space.acc.find_proc_info = dwarf_find_proc_info;
++ local_addr_space.acc.put_unwind_info = put_unwind_info;
++ local_addr_space.acc.get_dyn_info_list_addr = get_dyn_info_list_addr;
++ local_addr_space.acc.access_mem = access_mem;
++ local_addr_space.acc.access_reg = access_reg;
++ local_addr_space.acc.access_fpreg = access_fpreg;
++ local_addr_space.acc.resume = aarch64_local_resume;
++ local_addr_space.acc.get_proc_name = get_static_proc_name;
++ unw_flush_cache (&local_addr_space, 0, 0);
++}
++
++#endif /* !UNW_REMOTE_ONLY */
+--- /dev/null
++++ b/src/aarch64/Ginit_local.c
+@@ -0,0 +1,55 @@
++/* libunwind - a platform-independent unwind library
++ Copyright (C) 2008 CodeSourcery
++ Copyright (C) 2011-2013 Linaro Limited
++
++This file is part of libunwind.
++
++Permission is hereby granted, free of charge, to any person obtaining
++a copy of this software and associated documentation files (the
++"Software"), to deal in the Software without restriction, including
++without limitation the rights to use, copy, modify, merge, publish,
++distribute, sublicense, and/or sell copies of the Software, and to
++permit persons to whom the Software is furnished to do so, subject to
++the following conditions:
++
++The above copyright notice and this permission notice shall be
++included in all copies or substantial portions of the Software.
++
++THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
++EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
++MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
++NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
++LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
++OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
++WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
++
++#include "unwind_i.h"
++#include "init.h"
++
++#ifdef UNW_REMOTE_ONLY
++
++PROTECTED int
++unw_init_local (unw_cursor_t *cursor, unw_context_t *uc)
++{
++ return -UNW_EINVAL;
++}
++
++#else /* !UNW_REMOTE_ONLY */
++
++PROTECTED int
++unw_init_local (unw_cursor_t *cursor, unw_context_t *uc)
++{
++ struct cursor *c = (struct cursor *) cursor;
++
++ if (!tdep_init_done)
++ tdep_init ();
++
++ Debug (1, "(cursor=%p)\n", c);
++
++ c->dwarf.as = unw_local_addr_space;
++ c->dwarf.as_arg = uc;
++
++ return common_init (c, 1);
++}
++
++#endif /* !UNW_REMOTE_ONLY */
+--- /dev/null
++++ b/src/aarch64/Ginit_remote.c
+@@ -0,0 +1,45 @@
++/* libunwind - a platform-independent unwind library
++ Copyright (C) 2008 CodeSourcery
++
++This file is part of libunwind.
++
++Permission is hereby granted, free of charge, to any person obtaining
++a copy of this software and associated documentation files (the
++"Software"), to deal in the Software without restriction, including
++without limitation the rights to use, copy, modify, merge, publish,
++distribute, sublicense, and/or sell copies of the Software, and to
++permit persons to whom the Software is furnished to do so, subject to
++the following conditions:
++
++The above copyright notice and this permission notice shall be
++included in all copies or substantial portions of the Software.
++
++THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
++EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
++MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
++NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
++LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
++OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
++WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
++
++#include "init.h"
++#include "unwind_i.h"
++
++PROTECTED int
++unw_init_remote (unw_cursor_t *cursor, unw_addr_space_t as, void *as_arg)
++{
++#ifdef UNW_LOCAL_ONLY
++ return -UNW_EINVAL;
++#else /* !UNW_LOCAL_ONLY */
++ struct cursor *c = (struct cursor *) cursor;
++
++ if (!tdep_init_done)
++ tdep_init ();
++
++ Debug (1, "(cursor=%p)\n", c);
++
++ c->dwarf.as = as;
++ c->dwarf.as_arg = as_arg;
++ return common_init (c, 0);
++#endif /* !UNW_LOCAL_ONLY */
++}
+--- /dev/null
++++ b/src/aarch64/Gis_signal_frame.c
+@@ -0,0 +1,64 @@
++/* libunwind - a platform-independent unwind library
++ Copyright (C) 2012 Tommi Rantala <tt.rantala@gmail.com>
++ Copyright (C) 2013 Linaro Limited
++
++This file is part of libunwind.
++
++Permission is hereby granted, free of charge, to any person obtaining
++a copy of this software and associated documentation files (the
++"Software"), to deal in the Software without restriction, including
++without limitation the rights to use, copy, modify, merge, publish,
++distribute, sublicense, and/or sell copies of the Software, and to
++permit persons to whom the Software is furnished to do so, subject to
++the following conditions:
++
++The above copyright notice and this permission notice shall be
++included in all copies or substantial portions of the Software.
++
++THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
++EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
++MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
++NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
++LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
++OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
++WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
++
++#include "unwind_i.h"
++
++/* The restorer stub will always have the form:
++
++ d2801168 movz x8, #0x8b
++ d4000001 svc #0x0
++*/
++
++PROTECTED int
++unw_is_signal_frame (unw_cursor_t *cursor)
++{
++#ifdef __linux__
++ struct cursor *c = (struct cursor *) cursor;
++ unw_word_t w0, ip;
++ unw_addr_space_t as;
++ unw_accessors_t *a;
++ void *arg;
++ int ret;
++
++ as = c->dwarf.as;
++ a = unw_get_accessors (as);
++ arg = c->dwarf.as_arg;
++
++ ip = c->dwarf.ip;
++
++ ret = (*a->access_mem) (as, ip, &w0, 0, arg);
++ if (ret < 0)
++ return ret;
++
++ /* FIXME: distinguish 32bit insn vs 64bit registers. */
++ if (w0 != 0xd4000001d2801168)
++ return 0;
++
++ return 1;
++
++#else
++ return -UNW_ENOINFO;
++#endif
++}
+--- /dev/null
++++ b/src/aarch64/Gregs.c
+@@ -0,0 +1,113 @@
++/* libunwind - a platform-independent unwind library
++ Copyright (C) 2008 CodeSourcery
++ Copyright (C) 2012 Tommi Rantala <tt.rantala@gmail.com>
++ Copyright (C) 2013 Linaro Limited
++
++This file is part of libunwind.
++
++Permission is hereby granted, free of charge, to any person obtaining
++a copy of this software and associated documentation files (the
++"Software"), to deal in the Software without restriction, including
++without limitation the rights to use, copy, modify, merge, publish,
++distribute, sublicense, and/or sell copies of the Software, and to
++permit persons to whom the Software is furnished to do so, subject to
++the following conditions:
++
++The above copyright notice and this permission notice shall be
++included in all copies or substantial portions of the Software.
++
++THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
++EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
++MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
++NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
++LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
++OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
++WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
++
++#include "unwind_i.h"
++
++HIDDEN int
++tdep_access_reg (struct cursor *c, unw_regnum_t reg, unw_word_t *valp,
++ int write)
++{
++ dwarf_loc_t loc = DWARF_NULL_LOC;
++ unsigned int mask;
++
++ switch (reg)
++ {
++ case UNW_AARCH64_X0:
++ case UNW_AARCH64_X1:
++ case UNW_AARCH64_X2:
++ case UNW_AARCH64_X3:
++ mask = 1 << reg;
++ if (write)
++ {
++ c->dwarf.eh_args[reg] = *valp;
++ c->dwarf.eh_valid_mask |= mask;
++ return 0;
++ }
++ else if ((c->dwarf.eh_valid_mask & mask) != 0)
++ {
++ *valp = c->dwarf.eh_args[reg];
++ return 0;
++ }
++ else
++ loc = c->dwarf.loc[reg];
++ break;
++
++ case UNW_AARCH64_X4:
++ case UNW_AARCH64_X5:
++ case UNW_AARCH64_X6:
++ case UNW_AARCH64_X7:
++ case UNW_AARCH64_X8:
++ case UNW_AARCH64_X9:
++ case UNW_AARCH64_X10:
++ case UNW_AARCH64_X11:
++ case UNW_AARCH64_X12:
++ case UNW_AARCH64_X13:
++ case UNW_AARCH64_X14:
++ case UNW_AARCH64_X15:
++ case UNW_AARCH64_X16:
++ case UNW_AARCH64_X17:
++ case UNW_AARCH64_X18:
++ case UNW_AARCH64_X19:
++ case UNW_AARCH64_X20:
++ case UNW_AARCH64_X21:
++ case UNW_AARCH64_X22:
++ case UNW_AARCH64_X23:
++ case UNW_AARCH64_X24:
++ case UNW_AARCH64_X25:
++ case UNW_AARCH64_X26:
++ case UNW_AARCH64_X27:
++ case UNW_AARCH64_X28:
++ case UNW_AARCH64_X29:
++ case UNW_AARCH64_X30:
++ case UNW_AARCH64_PC:
++ case UNW_AARCH64_PSTATE:
++ loc = c->dwarf.loc[reg];
++ break;
++
++ case UNW_AARCH64_SP:
++ if (write)
++ return -UNW_EREADONLYREG;
++ *valp = c->dwarf.cfa;
++ return 0;
++
++ default:
++ Debug (1, "bad register number %u\n", reg);
++ return -UNW_EBADREG;
++ }
++
++ if (write)
++ return dwarf_put (&c->dwarf, loc, *valp);
++ else
++ return dwarf_get (&c->dwarf, loc, valp);
++}
++
++HIDDEN int
++tdep_access_fpreg (struct cursor *c, unw_regnum_t reg, unw_fpreg_t *valp,
++ int write)
++{
++ Debug (1, "bad register number %u\n", reg);
++ return -UNW_EBADREG;
++}
+--- /dev/null
++++ b/src/aarch64/Gresume.c
+@@ -0,0 +1,177 @@
++/* libunwind - a platform-independent unwind library
++ Copyright (C) 2008 CodeSourcery
++ Copyright (C) 2011-2013 Linaro Limited
++ Copyright (C) 2012 Tommi Rantala <tt.rantala@gmail.com>
++
++This file is part of libunwind.
++
++Permission is hereby granted, free of charge, to any person obtaining
++a copy of this software and associated documentation files (the
++"Software"), to deal in the Software without restriction, including
++without limitation the rights to use, copy, modify, merge, publish,
++distribute, sublicense, and/or sell copies of the Software, and to
++permit persons to whom the Software is furnished to do so, subject to
++the following conditions:
++
++The above copyright notice and this permission notice shall be
++included in all copies or substantial portions of the Software.
++
++THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
++EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
++MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
++NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
++LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
++OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
++WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
++
++#include "unwind_i.h"
++#include "offsets.h"
++
++#ifndef UNW_REMOTE_ONLY
++
++HIDDEN inline int
++aarch64_local_resume (unw_addr_space_t as, unw_cursor_t *cursor, void *arg)
++{
++#ifdef __linux__
++ struct cursor *c = (struct cursor *) cursor;
++ unw_tdep_context_t *uc = c->dwarf.as_arg;
++
++ if (c->sigcontext_format == AARCH64_SCF_NONE)
++ {
++ /* Since there are no signals involved here we restore the non scratch
++ registers only. */
++ unsigned long regs[11];
++ regs[0] = uc->uc_mcontext.regs[19];
++ regs[1] = uc->uc_mcontext.regs[20];
++ regs[2] = uc->uc_mcontext.regs[21];
++ regs[3] = uc->uc_mcontext.regs[22];
++ regs[4] = uc->uc_mcontext.regs[23];
++ regs[5] = uc->uc_mcontext.regs[24];
++ regs[6] = uc->uc_mcontext.regs[25];
++ regs[7] = uc->uc_mcontext.regs[26];
++ regs[8] = uc->uc_mcontext.regs[27];
++ regs[9] = uc->uc_mcontext.regs[28];
++ regs[10] = uc->uc_mcontext.regs[30]; /* LR */
++ unsigned long sp = uc->uc_mcontext.sp;
++
++ struct regs_overlay {
++ char x[sizeof(regs)];
++ };
++
++ asm volatile (
++ "ldp x19, x20, [%0]\n"
++ "ldp x21, x22, [%0,16]\n"
++ "ldp x23, x24, [%0,32]\n"
++ "ldp x25, x26, [%0,48]\n"
++ "ldp x27, x28, [%0,64]\n"
++ "ldr x30, [%0,80]\n"
++ "mov sp, %1\n"
++ "ret \n"
++ :
++ : "r" (regs),
++ "r" (sp),
++ "m" (*(struct regs_overlay *)regs)
++ );
++ }
++ else
++ {
++ struct sigcontext *sc = (struct sigcontext *) c->sigcontext_addr;
++
++ if (c->dwarf.eh_valid_mask & 0x1) sc->regs[0] = c->dwarf.eh_args[0];
++ if (c->dwarf.eh_valid_mask & 0x2) sc->regs[1] = c->dwarf.eh_args[1];
++ if (c->dwarf.eh_valid_mask & 0x4) sc->regs[2] = c->dwarf.eh_args[2];
++ if (c->dwarf.eh_valid_mask & 0x8) sc->regs[3] = c->dwarf.eh_args[3];
++
++ sc->regs[4] = uc->uc_mcontext.regs[4];
++ sc->regs[5] = uc->uc_mcontext.regs[5];
++ sc->regs[6] = uc->uc_mcontext.regs[6];
++ sc->regs[7] = uc->uc_mcontext.regs[7];
++ sc->regs[8] = uc->uc_mcontext.regs[8];
++ sc->regs[9] = uc->uc_mcontext.regs[9];
++ sc->regs[10] = uc->uc_mcontext.regs[10];
++ sc->regs[11] = uc->uc_mcontext.regs[11];
++ sc->regs[12] = uc->uc_mcontext.regs[12];
++ sc->regs[13] = uc->uc_mcontext.regs[13];
++ sc->regs[14] = uc->uc_mcontext.regs[14];
++ sc->regs[15] = uc->uc_mcontext.regs[15];
++ sc->regs[16] = uc->uc_mcontext.regs[16];
++ sc->regs[17] = uc->uc_mcontext.regs[17];
++ sc->regs[18] = uc->uc_mcontext.regs[18];
++ sc->regs[19] = uc->uc_mcontext.regs[19];
++ sc->regs[20] = uc->uc_mcontext.regs[20];
++ sc->regs[21] = uc->uc_mcontext.regs[21];
++ sc->regs[22] = uc->uc_mcontext.regs[22];
++ sc->regs[23] = uc->uc_mcontext.regs[23];
++ sc->regs[24] = uc->uc_mcontext.regs[24];
++ sc->regs[25] = uc->uc_mcontext.regs[25];
++ sc->regs[26] = uc->uc_mcontext.regs[26];
++ sc->regs[27] = uc->uc_mcontext.regs[27];
++ sc->regs[28] = uc->uc_mcontext.regs[28];
++ sc->regs[29] = uc->uc_mcontext.regs[29];
++ sc->regs[30] = uc->uc_mcontext.regs[30];
++ sc->sp = uc->uc_mcontext.sp;
++ sc->pc = uc->uc_mcontext.pc;
++ sc->pstate = uc->uc_mcontext.pstate;
++
++ asm volatile (
++ "mov sp, %0\n"
++ "ret %1\n"
++ : : "r" (c->sigcontext_sp), "r" (c->sigcontext_pc)
++ );
++ }
++ unreachable();
++#else
++ printf ("%s: implement me\n", __FUNCTION__);
++#endif
++ return -UNW_EINVAL;
++}
++
++#endif /* !UNW_REMOTE_ONLY */
++
++static inline void
++establish_machine_state (struct cursor *c)
++{
++ unw_addr_space_t as = c->dwarf.as;
++ void *arg = c->dwarf.as_arg;
++ unw_fpreg_t fpval;
++ unw_word_t val;
++ int reg;
++
++ Debug (8, "copying out cursor state\n");
++
++ for (reg = 0; reg <= UNW_AARCH64_PSTATE; ++reg)
++ {
++ Debug (16, "copying %s %d\n", unw_regname (reg), reg);
++ if (unw_is_fpreg (reg))
++ {
++ if (tdep_access_fpreg (c, reg, &fpval, 0) >= 0)
++ as->acc.access_fpreg (as, reg, &fpval, 1, arg);
++ }
++ else
++ {
++ if (tdep_access_reg (c, reg, &val, 0) >= 0)
++ as->acc.access_reg (as, reg, &val, 1, arg);
++ }
++ }
++}
++
++PROTECTED int
++unw_resume (unw_cursor_t *cursor)
++{
++ struct cursor *c = (struct cursor *) cursor;
++
++ Debug (1, "(cursor=%p)\n", c);
++
++ if (!c->dwarf.ip)
++ {
++ /* This can happen easily when the frame-chain gets truncated
++ due to bad or missing unwind-info. */
++ Debug (1, "refusing to resume execution at address 0\n");
++ return -UNW_EINVAL;
++ }
++
++ establish_machine_state (c);
++
++ return (*c->dwarf.as->acc.resume) (c->dwarf.as, (unw_cursor_t *) c,
++ c->dwarf.as_arg);
++}
+--- /dev/null
++++ b/src/aarch64/Gstep.c
+@@ -0,0 +1,129 @@
++/* libunwind - a platform-independent unwind library
++ Copyright (C) 2008 CodeSourcery
++ Copyright (C) 2011-2013 Linaro Limited
++ Copyright (C) 2012 Tommi Rantala <tt.rantala@gmail.com>
++
++This file is part of libunwind.
++
++Permission is hereby granted, free of charge, to any person obtaining
++a copy of this software and associated documentation files (the
++"Software"), to deal in the Software without restriction, including
++without limitation the rights to use, copy, modify, merge, publish,
++distribute, sublicense, and/or sell copies of the Software, and to
++permit persons to whom the Software is furnished to do so, subject to
++the following conditions:
++
++The above copyright notice and this permission notice shall be
++included in all copies or substantial portions of the Software.
++
++THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
++EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
++MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
++NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
++LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
++OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
++WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
++
++#include "unwind_i.h"
++#include "offsets.h"
++
++PROTECTED int
++unw_handle_signal_frame (unw_cursor_t *cursor)
++{
++ struct cursor *c = (struct cursor *) cursor;
++ int ret;
++ unw_word_t sc_addr, sp, sp_addr = c->dwarf.cfa;
++ struct dwarf_loc sp_loc = DWARF_LOC (sp_addr, 0);
++
++ if ((ret = dwarf_get (&c->dwarf, sp_loc, &sp)) < 0)
++ return -UNW_EUNSPEC;
++
++ ret = unw_is_signal_frame (cursor);
++ Debug(1, "unw_is_signal_frame()=%d\n", ret);
++
++ /* Save the SP and PC to be able to return execution at this point
++ later in time (unw_resume). */
++ c->sigcontext_sp = c->dwarf.cfa;
++ c->sigcontext_pc = c->dwarf.ip;
++
++ if (ret)
++ {
++ c->sigcontext_format = AARCH64_SCF_LINUX_RT_SIGFRAME;
++ sc_addr = sp_addr + sizeof (siginfo_t) + LINUX_UC_MCONTEXT_OFF;
++ }
++ else
++ return -UNW_EUNSPEC;
++
++ c->sigcontext_addr = sc_addr;
++
++ /* Update the dwarf cursor.
++ Set the location of the registers to the corresponding addresses of the
++ uc_mcontext / sigcontext structure contents. */
++ c->dwarf.loc[UNW_AARCH64_X0] = DWARF_LOC (sc_addr + LINUX_SC_X0_OFF, 0);
++ c->dwarf.loc[UNW_AARCH64_X1] = DWARF_LOC (sc_addr + LINUX_SC_X1_OFF, 0);
++ c->dwarf.loc[UNW_AARCH64_X2] = DWARF_LOC (sc_addr + LINUX_SC_X2_OFF, 0);
++ c->dwarf.loc[UNW_AARCH64_X3] = DWARF_LOC (sc_addr + LINUX_SC_X3_OFF, 0);
++ c->dwarf.loc[UNW_AARCH64_X4] = DWARF_LOC (sc_addr + LINUX_SC_X4_OFF, 0);
++ c->dwarf.loc[UNW_AARCH64_X5] = DWARF_LOC (sc_addr + LINUX_SC_X5_OFF, 0);
++ c->dwarf.loc[UNW_AARCH64_X6] = DWARF_LOC (sc_addr + LINUX_SC_X6_OFF, 0);
++ c->dwarf.loc[UNW_AARCH64_X7] = DWARF_LOC (sc_addr + LINUX_SC_X7_OFF, 0);
++ c->dwarf.loc[UNW_AARCH64_X8] = DWARF_LOC (sc_addr + LINUX_SC_X8_OFF, 0);
++ c->dwarf.loc[UNW_AARCH64_X9] = DWARF_LOC (sc_addr + LINUX_SC_X9_OFF, 0);
++ c->dwarf.loc[UNW_AARCH64_X10] = DWARF_LOC (sc_addr + LINUX_SC_X10_OFF, 0);
++ c->dwarf.loc[UNW_AARCH64_X11] = DWARF_LOC (sc_addr + LINUX_SC_X11_OFF, 0);
++ c->dwarf.loc[UNW_AARCH64_X12] = DWARF_LOC (sc_addr + LINUX_SC_X12_OFF, 0);
++ c->dwarf.loc[UNW_AARCH64_X13] = DWARF_LOC (sc_addr + LINUX_SC_X13_OFF, 0);
++ c->dwarf.loc[UNW_AARCH64_X14] = DWARF_LOC (sc_addr + LINUX_SC_X14_OFF, 0);
++ c->dwarf.loc[UNW_AARCH64_X15] = DWARF_LOC (sc_addr + LINUX_SC_X15_OFF, 0);
++ c->dwarf.loc[UNW_AARCH64_X16] = DWARF_LOC (sc_addr + LINUX_SC_X16_OFF, 0);
++ c->dwarf.loc[UNW_AARCH64_X17] = DWARF_LOC (sc_addr + LINUX_SC_X17_OFF, 0);
++ c->dwarf.loc[UNW_AARCH64_X18] = DWARF_LOC (sc_addr + LINUX_SC_X18_OFF, 0);
++ c->dwarf.loc[UNW_AARCH64_X19] = DWARF_LOC (sc_addr + LINUX_SC_X19_OFF, 0);
++ c->dwarf.loc[UNW_AARCH64_X20] = DWARF_LOC (sc_addr + LINUX_SC_X20_OFF, 0);
++ c->dwarf.loc[UNW_AARCH64_X21] = DWARF_LOC (sc_addr + LINUX_SC_X21_OFF, 0);
++ c->dwarf.loc[UNW_AARCH64_X22] = DWARF_LOC (sc_addr + LINUX_SC_X22_OFF, 0);
++ c->dwarf.loc[UNW_AARCH64_X23] = DWARF_LOC (sc_addr + LINUX_SC_X23_OFF, 0);
++ c->dwarf.loc[UNW_AARCH64_X24] = DWARF_LOC (sc_addr + LINUX_SC_X24_OFF, 0);
++ c->dwarf.loc[UNW_AARCH64_X25] = DWARF_LOC (sc_addr + LINUX_SC_X25_OFF, 0);
++ c->dwarf.loc[UNW_AARCH64_X26] = DWARF_LOC (sc_addr + LINUX_SC_X26_OFF, 0);
++ c->dwarf.loc[UNW_AARCH64_X27] = DWARF_LOC (sc_addr + LINUX_SC_X27_OFF, 0);
++ c->dwarf.loc[UNW_AARCH64_X28] = DWARF_LOC (sc_addr + LINUX_SC_X28_OFF, 0);
++ c->dwarf.loc[UNW_AARCH64_X29] = DWARF_LOC (sc_addr + LINUX_SC_X29_OFF, 0);
++ c->dwarf.loc[UNW_AARCH64_X30] = DWARF_LOC (sc_addr + LINUX_SC_X30_OFF, 0);
++ c->dwarf.loc[UNW_AARCH64_SP] = DWARF_LOC (sc_addr + LINUX_SC_SP_OFF, 0);
++ c->dwarf.loc[UNW_AARCH64_PC] = DWARF_LOC (sc_addr + LINUX_SC_PC_OFF, 0);
++ c->dwarf.loc[UNW_AARCH64_PSTATE] = DWARF_LOC (sc_addr + LINUX_SC_PSTATE_OFF, 0);
++
++ /* Set SP/CFA and PC/IP. */
++ dwarf_get (&c->dwarf, c->dwarf.loc[UNW_AARCH64_SP], &c->dwarf.cfa);
++ dwarf_get (&c->dwarf, c->dwarf.loc[UNW_AARCH64_PC], &c->dwarf.ip);
++
++ c->dwarf.pi_valid = 0;
++
++ return 1;
++}
++
++PROTECTED int
++unw_step (unw_cursor_t *cursor)
++{
++ struct cursor *c = (struct cursor *) cursor;
++ int ret;
++
++ Debug (1, "(cursor=%p, ip=0x%016lx, cfa=0x%016lx))\n",
++ c, c->dwarf.ip, c->dwarf.cfa);
++
++ /* Check if this is a signal frame. */
++ if (unw_is_signal_frame (cursor))
++ return unw_handle_signal_frame (cursor);
++
++ ret = dwarf_step (&c->dwarf);
++ Debug(1, "dwarf_step()=%d\n", ret);
++
++ if (unlikely (ret == -UNW_ESTOPUNWIND))
++ return ret;
++
++ if (unlikely (ret < 0))
++ return 0;
++
++ return (c->dwarf.ip == 0) ? 0 : 1;
++}
+--- /dev/null
++++ b/src/aarch64/Lcreate_addr_space.c
+@@ -0,0 +1,5 @@
++#define UNW_LOCAL_ONLY
++#include <libunwind.h>
++#if defined(UNW_LOCAL_ONLY) && !defined(UNW_REMOTE_ONLY)
++#include "Gcreate_addr_space.c"
++#endif
+--- /dev/null
++++ b/src/aarch64/Lget_proc_info.c
+@@ -0,0 +1,5 @@
++#define UNW_LOCAL_ONLY
++#include <libunwind.h>
++#if defined(UNW_LOCAL_ONLY) && !defined(UNW_REMOTE_ONLY)
++#include "Gget_proc_info.c"
++#endif
+--- /dev/null
++++ b/src/aarch64/Lget_save_loc.c
+@@ -0,0 +1,5 @@
++#define UNW_LOCAL_ONLY
++#include <libunwind.h>
++#if defined(UNW_LOCAL_ONLY) && !defined(UNW_REMOTE_ONLY)
++#include "Gget_save_loc.c"
++#endif
+--- /dev/null
++++ b/src/aarch64/Lglobal.c
+@@ -0,0 +1,5 @@
++#define UNW_LOCAL_ONLY
++#include <libunwind.h>
++#if defined(UNW_LOCAL_ONLY) && !defined(UNW_REMOTE_ONLY)
++#include "Gglobal.c"
++#endif
+--- /dev/null
++++ b/src/aarch64/Linit.c
+@@ -0,0 +1,5 @@
++#define UNW_LOCAL_ONLY
++#include <libunwind.h>
++#if defined(UNW_LOCAL_ONLY) && !defined(UNW_REMOTE_ONLY)
++#include "Ginit.c"
++#endif
+--- /dev/null
++++ b/src/aarch64/Linit_local.c
+@@ -0,0 +1,5 @@
++#define UNW_LOCAL_ONLY
++#include <libunwind.h>
++#if defined(UNW_LOCAL_ONLY) && !defined(UNW_REMOTE_ONLY)
++#include "Ginit_local.c"
++#endif
+--- /dev/null
++++ b/src/aarch64/Linit_remote.c
+@@ -0,0 +1,5 @@
++#define UNW_LOCAL_ONLY
++#include <libunwind.h>
++#if defined(UNW_LOCAL_ONLY) && !defined(UNW_REMOTE_ONLY)
++#include "Ginit_remote.c"
++#endif
+--- /dev/null
++++ b/src/aarch64/Lis_signal_frame.c
+@@ -0,0 +1,5 @@
++#define UNW_LOCAL_ONLY
++#include <libunwind.h>
++#if defined(UNW_LOCAL_ONLY) && !defined(UNW_REMOTE_ONLY)
++#include "Gis_signal_frame.c"
++#endif
+--- /dev/null
++++ b/src/aarch64/Lregs.c
+@@ -0,0 +1,5 @@
++#define UNW_LOCAL_ONLY
++#include <libunwind.h>
++#if defined(UNW_LOCAL_ONLY) && !defined(UNW_REMOTE_ONLY)
++#include "Gregs.c"
++#endif
+--- /dev/null
++++ b/src/aarch64/Lresume.c
+@@ -0,0 +1,5 @@
++#define UNW_LOCAL_ONLY
++#include <libunwind.h>
++#if defined(UNW_LOCAL_ONLY) && !defined(UNW_REMOTE_ONLY)
++#include "Gresume.c"
++#endif
+--- /dev/null
++++ b/src/aarch64/Lstep.c
+@@ -0,0 +1,5 @@
++#define UNW_LOCAL_ONLY
++#include <libunwind.h>
++#if defined(UNW_LOCAL_ONLY) && !defined(UNW_REMOTE_ONLY)
++#include "Gstep.c"
++#endif
+--- /dev/null
++++ b/src/aarch64/gen-offsets.c
+@@ -0,0 +1,68 @@
++#include <stdio.h>
++#include <stddef.h>
++#include <ucontext.h>
++#include <asm/sigcontext.h>
++
++#define UC(N,X) \
++ printf ("#define LINUX_UC_" N "_OFF\t0x%X\n", offsetof (ucontext_t, X))
++
++#define SC(N,X) \
++ printf ("#define LINUX_SC_" N "_OFF\t0x%X\n", offsetof (struct sigcontext, X))
++
++int
++main (void)
++{
++ printf (
++"/* Linux-specific definitions: */\n\n"
++
++"/* Define various structure offsets to simplify cross-compilation. */\n\n"
++
++"/* Offsets for AArch64 Linux \"ucontext_t\": */\n\n");
++
++ UC ("FLAGS", uc_flags);
++ UC ("LINK", uc_link);
++ UC ("STACK", uc_stack);
++ UC ("MCONTEXT", uc_mcontext);
++ UC ("SIGMASK", uc_sigmask);
++
++ printf ("\n/* Offsets for AArch64 Linux \"struct sigcontext\": */\n\n");
++
++ SC ("R0", regs[0]);
++ SC ("R1", regs[1]);
++ SC ("R2", regs[2]);
++ SC ("R3", regs[3]);
++ SC ("R4", regs[4]);
++ SC ("R5", regs[5]);
++ SC ("R6", regs[6]);
++ SC ("R7", regs[7]);
++ SC ("R8", regs[8]);
++ SC ("R9", regs[9]);
++ SC ("R10", regs[10]);
++ SC ("R11", regs[11]);
++ SC ("R12", regs[12]);
++ SC ("R13", regs[13]);
++ SC ("R14", regs[14]);
++ SC ("R15", regs[15]);
++ SC ("R16", regs[16]);
++ SC ("R17", regs[17]);
++ SC ("R18", regs[18]);
++ SC ("R19", regs[19]);
++ SC ("R20", regs[20]);
++ SC ("R21", regs[21]);
++ SC ("R22", regs[22]);
++ SC ("R23", regs[23]);
++ SC ("R24", regs[24]);
++ SC ("R25", regs[25]);
++ SC ("R26", regs[26]);
++ SC ("R27", regs[27]);
++ SC ("R28", regs[28]);
++ SC ("R29", regs[29]);
++ SC ("R30", regs[30]);
++ SC ("R31", regs[31]);
++
++ SC ("PC", pc);
++ SC ("SP", sp);
++ SC ("Fault", fault_address);
++ SC ("state", pstate);
++ return 0;
++}
+--- /dev/null
++++ b/src/aarch64/init.h
+@@ -0,0 +1,127 @@
++/* libunwind - a platform-independent unwind library
++ Copyright (C) 2012 Tommi Rantala <tt.rantala@gmail.com>
++ Copyright (C) 2013 Linaro Limited
++
++This file is part of libunwind.
++
++Permission is hereby granted, free of charge, to any person obtaining
++a copy of this software and associated documentation files (the
++"Software"), to deal in the Software without restriction, including
++without limitation the rights to use, copy, modify, merge, publish,
++distribute, sublicense, and/or sell copies of the Software, and to
++permit persons to whom the Software is furnished to do so, subject to
++the following conditions:
++
++The above copyright notice and this permission notice shall be
++included in all copies or substantial portions of the Software.
++
++THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
++EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
++MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
++NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
++LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
++OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
++WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
++
++#include "unwind_i.h"
++
++static inline int
++common_init (struct cursor *c, unsigned use_prev_instr)
++{
++ int ret, i;
++
++ c->dwarf.loc[UNW_AARCH64_X0] = DWARF_REG_LOC (&c->dwarf, UNW_AARCH64_X0);
++ c->dwarf.loc[UNW_AARCH64_X1] = DWARF_REG_LOC (&c->dwarf, UNW_AARCH64_X1);
++ c->dwarf.loc[UNW_AARCH64_X2] = DWARF_REG_LOC (&c->dwarf, UNW_AARCH64_X2);
++ c->dwarf.loc[UNW_AARCH64_X3] = DWARF_REG_LOC (&c->dwarf, UNW_AARCH64_X3);
++ c->dwarf.loc[UNW_AARCH64_X4] = DWARF_REG_LOC (&c->dwarf, UNW_AARCH64_X4);
++ c->dwarf.loc[UNW_AARCH64_X5] = DWARF_REG_LOC (&c->dwarf, UNW_AARCH64_X5);
++ c->dwarf.loc[UNW_AARCH64_X6] = DWARF_REG_LOC (&c->dwarf, UNW_AARCH64_X6);
++ c->dwarf.loc[UNW_AARCH64_X7] = DWARF_REG_LOC (&c->dwarf, UNW_AARCH64_X7);
++ c->dwarf.loc[UNW_AARCH64_X8] = DWARF_REG_LOC (&c->dwarf, UNW_AARCH64_X8);
++ c->dwarf.loc[UNW_AARCH64_X9] = DWARF_REG_LOC (&c->dwarf, UNW_AARCH64_X9);
++ c->dwarf.loc[UNW_AARCH64_X10] = DWARF_REG_LOC (&c->dwarf, UNW_AARCH64_X10);
++ c->dwarf.loc[UNW_AARCH64_X11] = DWARF_REG_LOC (&c->dwarf, UNW_AARCH64_X11);
++ c->dwarf.loc[UNW_AARCH64_X12] = DWARF_REG_LOC (&c->dwarf, UNW_AARCH64_X12);
++ c->dwarf.loc[UNW_AARCH64_X13] = DWARF_REG_LOC (&c->dwarf, UNW_AARCH64_X13);
++ c->dwarf.loc[UNW_AARCH64_X14] = DWARF_REG_LOC (&c->dwarf, UNW_AARCH64_X14);
++ c->dwarf.loc[UNW_AARCH64_X15] = DWARF_REG_LOC (&c->dwarf, UNW_AARCH64_X15);
++ c->dwarf.loc[UNW_AARCH64_X16] = DWARF_REG_LOC (&c->dwarf, UNW_AARCH64_X16);
++ c->dwarf.loc[UNW_AARCH64_X17] = DWARF_REG_LOC (&c->dwarf, UNW_AARCH64_X17);
++ c->dwarf.loc[UNW_AARCH64_X18] = DWARF_REG_LOC (&c->dwarf, UNW_AARCH64_X18);
++ c->dwarf.loc[UNW_AARCH64_X19] = DWARF_REG_LOC (&c->dwarf, UNW_AARCH64_X19);
++ c->dwarf.loc[UNW_AARCH64_X20] = DWARF_REG_LOC (&c->dwarf, UNW_AARCH64_X20);
++ c->dwarf.loc[UNW_AARCH64_X21] = DWARF_REG_LOC (&c->dwarf, UNW_AARCH64_X21);
++ c->dwarf.loc[UNW_AARCH64_X22] = DWARF_REG_LOC (&c->dwarf, UNW_AARCH64_X22);
++ c->dwarf.loc[UNW_AARCH64_X23] = DWARF_REG_LOC (&c->dwarf, UNW_AARCH64_X23);
++ c->dwarf.loc[UNW_AARCH64_X24] = DWARF_REG_LOC (&c->dwarf, UNW_AARCH64_X24);
++ c->dwarf.loc[UNW_AARCH64_X25] = DWARF_REG_LOC (&c->dwarf, UNW_AARCH64_X25);
++ c->dwarf.loc[UNW_AARCH64_X26] = DWARF_REG_LOC (&c->dwarf, UNW_AARCH64_X26);
++ c->dwarf.loc[UNW_AARCH64_X27] = DWARF_REG_LOC (&c->dwarf, UNW_AARCH64_X27);
++ c->dwarf.loc[UNW_AARCH64_X28] = DWARF_REG_LOC (&c->dwarf, UNW_AARCH64_X28);
++ c->dwarf.loc[UNW_AARCH64_X29] = DWARF_REG_LOC (&c->dwarf, UNW_AARCH64_X29);
++ c->dwarf.loc[UNW_AARCH64_X30] = DWARF_REG_LOC (&c->dwarf, UNW_AARCH64_X30);
++ c->dwarf.loc[UNW_AARCH64_SP] = DWARF_REG_LOC (&c->dwarf, UNW_AARCH64_SP);
++ c->dwarf.loc[UNW_AARCH64_PC] = DWARF_REG_LOC (&c->dwarf, UNW_AARCH64_PC);
++ c->dwarf.loc[UNW_AARCH64_PSTATE] = DWARF_REG_LOC (&c->dwarf,
++ UNW_AARCH64_PSTATE);
++ c->dwarf.loc[UNW_AARCH64_V0] = DWARF_REG_LOC (&c->dwarf, UNW_AARCH64_V0);
++ c->dwarf.loc[UNW_AARCH64_V1] = DWARF_REG_LOC (&c->dwarf, UNW_AARCH64_V1);
++ c->dwarf.loc[UNW_AARCH64_V2] = DWARF_REG_LOC (&c->dwarf, UNW_AARCH64_V2);
++ c->dwarf.loc[UNW_AARCH64_V3] = DWARF_REG_LOC (&c->dwarf, UNW_AARCH64_V3);
++ c->dwarf.loc[UNW_AARCH64_V4] = DWARF_REG_LOC (&c->dwarf, UNW_AARCH64_V4);
++ c->dwarf.loc[UNW_AARCH64_V5] = DWARF_REG_LOC (&c->dwarf, UNW_AARCH64_V5);
++ c->dwarf.loc[UNW_AARCH64_V6] = DWARF_REG_LOC (&c->dwarf, UNW_AARCH64_V6);
++ c->dwarf.loc[UNW_AARCH64_V7] = DWARF_REG_LOC (&c->dwarf, UNW_AARCH64_V7);
++ c->dwarf.loc[UNW_AARCH64_V8] = DWARF_REG_LOC (&c->dwarf, UNW_AARCH64_V8);
++ c->dwarf.loc[UNW_AARCH64_V9] = DWARF_REG_LOC (&c->dwarf, UNW_AARCH64_V9);
++ c->dwarf.loc[UNW_AARCH64_V10] = DWARF_REG_LOC (&c->dwarf, UNW_AARCH64_V10);
++ c->dwarf.loc[UNW_AARCH64_V11] = DWARF_REG_LOC (&c->dwarf, UNW_AARCH64_V11);
++ c->dwarf.loc[UNW_AARCH64_V12] = DWARF_REG_LOC (&c->dwarf, UNW_AARCH64_V12);
++ c->dwarf.loc[UNW_AARCH64_V13] = DWARF_REG_LOC (&c->dwarf, UNW_AARCH64_V13);
++ c->dwarf.loc[UNW_AARCH64_V14] = DWARF_REG_LOC (&c->dwarf, UNW_AARCH64_V14);
++ c->dwarf.loc[UNW_AARCH64_V15] = DWARF_REG_LOC (&c->dwarf, UNW_AARCH64_V15);
++ c->dwarf.loc[UNW_AARCH64_V16] = DWARF_REG_LOC (&c->dwarf, UNW_AARCH64_V16);
++ c->dwarf.loc[UNW_AARCH64_V17] = DWARF_REG_LOC (&c->dwarf, UNW_AARCH64_V17);
++ c->dwarf.loc[UNW_AARCH64_V18] = DWARF_REG_LOC (&c->dwarf, UNW_AARCH64_V18);
++ c->dwarf.loc[UNW_AARCH64_V19] = DWARF_REG_LOC (&c->dwarf, UNW_AARCH64_V19);
++ c->dwarf.loc[UNW_AARCH64_V20] = DWARF_REG_LOC (&c->dwarf, UNW_AARCH64_V20);
++ c->dwarf.loc[UNW_AARCH64_V21] = DWARF_REG_LOC (&c->dwarf, UNW_AARCH64_V21);
++ c->dwarf.loc[UNW_AARCH64_V22] = DWARF_REG_LOC (&c->dwarf, UNW_AARCH64_V22);
++ c->dwarf.loc[UNW_AARCH64_V23] = DWARF_REG_LOC (&c->dwarf, UNW_AARCH64_V23);
++ c->dwarf.loc[UNW_AARCH64_V24] = DWARF_REG_LOC (&c->dwarf, UNW_AARCH64_V24);
++ c->dwarf.loc[UNW_AARCH64_V25] = DWARF_REG_LOC (&c->dwarf, UNW_AARCH64_V25);
++ c->dwarf.loc[UNW_AARCH64_V26] = DWARF_REG_LOC (&c->dwarf, UNW_AARCH64_V26);
++ c->dwarf.loc[UNW_AARCH64_V27] = DWARF_REG_LOC (&c->dwarf, UNW_AARCH64_V27);
++ c->dwarf.loc[UNW_AARCH64_V28] = DWARF_REG_LOC (&c->dwarf, UNW_AARCH64_V28);
++ c->dwarf.loc[UNW_AARCH64_V29] = DWARF_REG_LOC (&c->dwarf, UNW_AARCH64_V29);
++ c->dwarf.loc[UNW_AARCH64_V30] = DWARF_REG_LOC (&c->dwarf, UNW_AARCH64_V30);
++ c->dwarf.loc[UNW_AARCH64_V31] = DWARF_REG_LOC (&c->dwarf, UNW_AARCH64_V31);
++
++ for (i = UNW_AARCH64_PSTATE + 1; i < UNW_AARCH64_V0; ++i)
++ c->dwarf.loc[i] = DWARF_NULL_LOC;
++
++ ret = dwarf_get (&c->dwarf, c->dwarf.loc[UNW_AARCH64_PC], &c->dwarf.ip);
++ if (ret < 0)
++ return ret;
++
++ ret = dwarf_get (&c->dwarf, c->dwarf.loc[UNW_AARCH64_SP], &c->dwarf.cfa);
++ if (ret < 0)
++ return ret;
++
++ c->sigcontext_format = AARCH64_SCF_NONE;
++ c->sigcontext_addr = 0;
++ c->sigcontext_sp = 0;
++ c->sigcontext_pc = 0;
++
++ c->dwarf.args_size = 0;
++ c->dwarf.ret_addr_column = 0;
++ c->dwarf.stash_frames = 0;
++ c->dwarf.use_prev_instr = use_prev_instr;
++ c->dwarf.pi_valid = 0;
++ c->dwarf.pi_is_dynamic = 0;
++ c->dwarf.hint = 0;
++ c->dwarf.prev_rs = 0;
++
++ return 0;
++}
+--- /dev/null
++++ b/src/aarch64/is_fpreg.c
+@@ -0,0 +1,32 @@
++/* libunwind - a platform-independent unwind library
++ Copyright (C) 2008 CodeSourcery
++ Copyright (C) 2013 Linaro Limited
++
++This file is part of libunwind.
++
++Permission is hereby granted, free of charge, to any person obtaining
++a copy of this software and associated documentation files (the
++"Software"), to deal in the Software without restriction, including
++without limitation the rights to use, copy, modify, merge, publish,
++distribute, sublicense, and/or sell copies of the Software, and to
++permit persons to whom the Software is furnished to do so, subject to
++the following conditions:
++
++The above copyright notice and this permission notice shall be
++included in all copies or substantial portions of the Software.
++
++THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
++EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
++MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
++NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
++LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
++OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
++WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
++
++#include "libunwind_i.h"
++
++PROTECTED int
++unw_is_fpreg (int regnum)
++{
++ return (regnum >= UNW_AARCH64_V0 && regnum <= UNW_AARCH64_V31);
++}
+--- /dev/null
++++ b/src/aarch64/offsets.h
+@@ -0,0 +1,49 @@
++/* Linux-specific definitions: */
++
++/* Define various structure offsets to simplify cross-compilation. */
++
++/* Offsets for AArch64 Linux "ucontext_t": */
++
++#define LINUX_UC_FLAGS_OFF 0x0
++#define LINUX_UC_LINK_OFF 0x8
++#define LINUX_UC_STACK_OFF 0x10
++#define LINUX_UC_SIGMASK_OFF 0x28
++#define LINUX_UC_MCONTEXT_OFF 0xb0
++
++/* Offsets for AArch64 Linux "struct sigcontext": */
++
++#define LINUX_SC_FAULTADDRESS_OFF 0x00
++#define LINUX_SC_X0_OFF 0x008
++#define LINUX_SC_X1_OFF 0x010
++#define LINUX_SC_X2_OFF 0x018
++#define LINUX_SC_X3_OFF 0x020
++#define LINUX_SC_X4_OFF 0x028
++#define LINUX_SC_X5_OFF 0x030
++#define LINUX_SC_X6_OFF 0x038
++#define LINUX_SC_X7_OFF 0x040
++#define LINUX_SC_X8_OFF 0x048
++#define LINUX_SC_X9_OFF 0x050
++#define LINUX_SC_X10_OFF 0x058
++#define LINUX_SC_X11_OFF 0x060
++#define LINUX_SC_X12_OFF 0x068
++#define LINUX_SC_X13_OFF 0x070
++#define LINUX_SC_X14_OFF 0x078
++#define LINUX_SC_X15_OFF 0x080
++#define LINUX_SC_X16_OFF 0x088
++#define LINUX_SC_X17_OFF 0x090
++#define LINUX_SC_X18_OFF 0x098
++#define LINUX_SC_X19_OFF 0x0a0
++#define LINUX_SC_X20_OFF 0x0a8
++#define LINUX_SC_X21_OFF 0x0b0
++#define LINUX_SC_X22_OFF 0x0b8
++#define LINUX_SC_X23_OFF 0x0c0
++#define LINUX_SC_X24_OFF 0x0c8
++#define LINUX_SC_X25_OFF 0x0d0
++#define LINUX_SC_X26_OFF 0x0d8
++#define LINUX_SC_X27_OFF 0x0e0
++#define LINUX_SC_X28_OFF 0x0e8
++#define LINUX_SC_X29_OFF 0x0f0
++#define LINUX_SC_X30_OFF 0x0f8
++#define LINUX_SC_SP_OFF 0x100
++#define LINUX_SC_PC_OFF 0x108
++#define LINUX_SC_PSTATE_OFF 0x110
+--- /dev/null
++++ b/src/aarch64/regname.c
+@@ -0,0 +1,106 @@
++/* libunwind - a platform-independent unwind library
++ Copyright (C) 2012 Tommi Rantala <tt.rantala@gmail.com>
++ Copyright (C) 2013 Linaro Limited
++
++This file is part of libunwind.
++
++Permission is hereby granted, free of charge, to any person obtaining
++a copy of this software and associated documentation files (the
++"Software"), to deal in the Software without restriction, including
++without limitation the rights to use, copy, modify, merge, publish,
++distribute, sublicense, and/or sell copies of the Software, and to
++permit persons to whom the Software is furnished to do so, subject to
++the following conditions:
++
++The above copyright notice and this permission notice shall be
++included in all copies or substantial portions of the Software.
++
++THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
++EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
++MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
++NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
++LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
++OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
++WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
++
++#include "unwind_i.h"
++
++static const char *const regname[] =
++ {
++ [UNW_AARCH64_X0] = "x0",
++ [UNW_AARCH64_X1] = "x1",
++ [UNW_AARCH64_X2] = "x2",
++ [UNW_AARCH64_X3] = "x3",
++ [UNW_AARCH64_X4] = "x4",
++ [UNW_AARCH64_X5] = "x5",
++ [UNW_AARCH64_X6] = "x6",
++ [UNW_AARCH64_X7] = "x7",
++ [UNW_AARCH64_X8] = "x8",
++ [UNW_AARCH64_X9] = "x9",
++ [UNW_AARCH64_X10] = "x10",
++ [UNW_AARCH64_X11] = "x11",
++ [UNW_AARCH64_X12] = "x12",
++ [UNW_AARCH64_X13] = "x13",
++ [UNW_AARCH64_X14] = "x14",
++ [UNW_AARCH64_X15] = "x15",
++ [UNW_AARCH64_X16] = "ip0",
++ [UNW_AARCH64_X17] = "ip1",
++ [UNW_AARCH64_X18] = "x18",
++ [UNW_AARCH64_X19] = "x19",
++ [UNW_AARCH64_X20] = "x20",
++ [UNW_AARCH64_X21] = "x21",
++ [UNW_AARCH64_X22] = "x22",
++ [UNW_AARCH64_X23] = "x23",
++ [UNW_AARCH64_X24] = "x24",
++ [UNW_AARCH64_X25] = "x25",
++ [UNW_AARCH64_X26] = "x26",
++ [UNW_AARCH64_X27] = "x27",
++ [UNW_AARCH64_X28] = "x28",
++ [UNW_AARCH64_X29] = "fp",
++ [UNW_AARCH64_X30] = "lr",
++ [UNW_AARCH64_SP] = "sp",
++ [UNW_AARCH64_PC] = "pc",
++ [UNW_AARCH64_V0] = "v0",
++ [UNW_AARCH64_V1] = "v1",
++ [UNW_AARCH64_V2] = "v2",
++ [UNW_AARCH64_V3] = "v3",
++ [UNW_AARCH64_V4] = "v4",
++ [UNW_AARCH64_V5] = "v5",
++ [UNW_AARCH64_V6] = "v6",
++ [UNW_AARCH64_V7] = "v7",
++ [UNW_AARCH64_V8] = "v8",
++ [UNW_AARCH64_V9] = "v9",
++ [UNW_AARCH64_V10] = "v10",
++ [UNW_AARCH64_V11] = "v11",
++ [UNW_AARCH64_V12] = "v12",
++ [UNW_AARCH64_V13] = "v13",
++ [UNW_AARCH64_V14] = "v14",
++ [UNW_AARCH64_V15] = "v15",
++ [UNW_AARCH64_V16] = "v16",
++ [UNW_AARCH64_V17] = "v17",
++ [UNW_AARCH64_V18] = "v18",
++ [UNW_AARCH64_V19] = "v19",
++ [UNW_AARCH64_V20] = "v20",
++ [UNW_AARCH64_V21] = "v21",
++ [UNW_AARCH64_V22] = "v22",
++ [UNW_AARCH64_V23] = "v23",
++ [UNW_AARCH64_V24] = "v24",
++ [UNW_AARCH64_V25] = "v25",
++ [UNW_AARCH64_V26] = "v26",
++ [UNW_AARCH64_V27] = "v27",
++ [UNW_AARCH64_V28] = "v28",
++ [UNW_AARCH64_V29] = "v29",
++ [UNW_AARCH64_V30] = "v30",
++ [UNW_AARCH64_V31] = "v31",
++ [UNW_AARCH64_FPSR] = "fpsr",
++ [UNW_AARCH64_FPCR] = "fpcr",
++ };
++
++PROTECTED const char *
++unw_regname (unw_regnum_t reg)
++{
++ if (reg < (unw_regnum_t) ARRAY_SIZE (regname) && regname[reg] != NULL)
++ return regname[reg];
++ else
++ return "???";
++}
+--- /dev/null
++++ b/src/aarch64/siglongjmp.S
+@@ -0,0 +1,12 @@
++ /* Dummy implementation for now. */
++
++ .global _UI_siglongjmp_cont
++ .global _UI_longjmp_cont
++
++_UI_siglongjmp_cont:
++_UI_longjmp_cont:
++ ret
++#ifdef __linux__
++ /* We do not need executable stack. */
++ .section .note.GNU-stack,"",%progbits
++#endif
+--- /dev/null
++++ b/src/aarch64/unwind_i.h
+@@ -0,0 +1,43 @@
++/* libunwind - a platform-independent unwind library
++ Copyright (C) 2008 CodeSourcery
++ Copyright (C) 2013 Linaro Limited
++
++This file is part of libunwind.
++
++Permission is hereby granted, free of charge, to any person obtaining
++a copy of this software and associated documentation files (the
++"Software"), to deal in the Software without restriction, including
++without limitation the rights to use, copy, modify, merge, publish,
++distribute, sublicense, and/or sell copies of the Software, and to
++permit persons to whom the Software is furnished to do so, subject to
++the following conditions:
++
++The above copyright notice and this permission notice shall be
++included in all copies or substantial portions of the Software.
++
++THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
++EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
++MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
++NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
++LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
++OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
++WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
++
++#ifndef unwind_i_h
++#define unwind_i_h
++
++#include <stdint.h>
++
++#include <libunwind-aarch64.h>
++
++#include "libunwind_i.h"
++
++#define aarch64_lock UNW_OBJ(lock)
++#define aarch64_local_resume UNW_OBJ(local_resume)
++#define aarch64_local_addr_space_init UNW_OBJ(local_addr_space_init)
++
++extern void aarch64_local_addr_space_init (void);
++extern int aarch64_local_resume (unw_addr_space_t as, unw_cursor_t *cursor,
++ void *arg);
++
++#endif /* unwind_i_h */
+--- a/src/coredump/_UCD_access_reg_linux.c
++++ b/src/coredump/_UCD_access_reg_linux.c
+@@ -39,7 +39,10 @@ _UCD_access_reg (unw_addr_space_t as,
+ return -UNW_EINVAL;
+ }
+
+-#if defined(UNW_TARGET_ARM)
++#if defined(UNW_TARGET_AARCH64)
++ if (regnum < 0 || regnum >= UNW_AARCH64_FPCR)
++ goto badreg;
++#elif defined(UNW_TARGET_ARM)
+ if (regnum < 0 || regnum >= 16)
+ goto badreg;
+ #elif defined(UNW_TARGET_SH)
+--- a/src/ptrace/_UPT_reg_offset.c
++++ b/src/ptrace/_UPT_reg_offset.c
+@@ -1,6 +1,7 @@
+ /* libunwind - a platform-independent unwind library
+ Copyright (C) 2003-2004 Hewlett-Packard Co
+ Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
++ Copyright (C) 2013 Linaro Limited
+
+ This file is part of libunwind.
+
+@@ -501,6 +502,41 @@ const int _UPT_reg_offset[UNW_REG_LAST +
+ [UNW_ARM_R15] = 0x3c,
+ #elif defined(UNW_TARGET_MIPS)
+ #elif defined(UNW_TARGET_SH)
++#elif defined(UNW_TARGET_AARCH64)
++ [UNW_AARCH64_X0] = 0x00,
++ [UNW_AARCH64_X1] = 0x08,
++ [UNW_AARCH64_X2] = 0x10,
++ [UNW_AARCH64_X3] = 0x18,
++ [UNW_AARCH64_X4] = 0x20,
++ [UNW_AARCH64_X5] = 0x28,
++ [UNW_AARCH64_X6] = 0x30,
++ [UNW_AARCH64_X7] = 0x38,
++ [UNW_AARCH64_X8] = 0x40,
++ [UNW_AARCH64_X9] = 0x48,
++ [UNW_AARCH64_X10] = 0x50,
++ [UNW_AARCH64_X11] = 0x58,
++ [UNW_AARCH64_X12] = 0x60,
++ [UNW_AARCH64_X13] = 0x68,
++ [UNW_AARCH64_X14] = 0x70,
++ [UNW_AARCH64_X15] = 0x78,
++ [UNW_AARCH64_X16] = 0x80,
++ [UNW_AARCH64_X17] = 0x88,
++ [UNW_AARCH64_X18] = 0x90,
++ [UNW_AARCH64_X19] = 0x98,
++ [UNW_AARCH64_X20] = 0xa0,
++ [UNW_AARCH64_X21] = 0xa8,
++ [UNW_AARCH64_X22] = 0xb0,
++ [UNW_AARCH64_X23] = 0xb8,
++ [UNW_AARCH64_X24] = 0xc0,
++ [UNW_AARCH64_X25] = 0xc8,
++ [UNW_AARCH64_X26] = 0xd0,
++ [UNW_AARCH64_X27] = 0xd8,
++ [UNW_AARCH64_X28] = 0xe0,
++ [UNW_AARCH64_X29] = 0xe8,
++ [UNW_AARCH64_X30] = 0xf0,
++ [UNW_AARCH64_SP] = 0xf8,
++ [UNW_AARCH64_PC] = 0x100,
++ [UNW_AARCH64_PSTATE] = 0x108
+ #else
+ # error Fix me.
+ #endif
diff --git a/meta/recipes-support/libunwind/libunwind-1.1/Support-building-with-older-compilers.patch b/meta/recipes-support/libunwind/libunwind-1.1/Support-building-with-older-compilers.patch
new file mode 100644
index 0000000..268b702
--- /dev/null
+++ b/meta/recipes-support/libunwind/libunwind-1.1/Support-building-with-older-compilers.patch
@@ -0,0 +1,72 @@
+From 10b064ffe902d5af31bb49bd8e4f03c545f8d462 Mon Sep 17 00:00:00 2001
+From: Ladislav Michl <ladis@linux-mips.org>
+Date: Tue, 13 Nov 2012 11:19:47 +0100
+Subject: [PATCH] Support building with older compilers.
+
+Add a check for __builtin_unreachable.
+
+Upstream-Status: Pending
+---
+ configure.ac | 11 +++++++++++
+ include/libunwind_i.h | 6 ++++++
+ src/arm/Gresume.c | 2 +-
+ src/sh/Gresume.c | 2 +-
+ 4 files changed, 19 insertions(+), 2 deletions(-)
+
+--- a/configure.ac
++++ b/configure.ac
+@@ -285,6 +285,17 @@ if test x$have__builtin___clear_cache =
+ fi
+ AC_MSG_RESULT([$have__builtin___clear_cache])
+
++AC_MSG_CHECKING([for __builtin_unreachable])
++AC_LINK_IFELSE(
++ [AC_LANG_PROGRAM([[]], [[__builtin_unreachable()]])],
++ [have__builtin_unreachable=yes],
++ [have__builtin_unreachable=no])
++if test x$have__builtin_unreachable = xyes; then
++ AC_DEFINE([HAVE__BUILTIN_UNREACHABLE], [1],
++ [Defined if __builtin_unreachable() is available])
++fi
++AC_MSG_RESULT([$have__builtin_unreachable])
++
+ AC_MSG_CHECKING([for __sync atomics])
+ AC_LINK_IFELSE(
+ [AC_LANG_PROGRAM([[]], [[
+--- a/include/libunwind_i.h
++++ b/include/libunwind_i.h
+@@ -72,6 +72,12 @@ WITH THE SOFTWARE OR THE USE OR OTHER DE
+ # endif
+ #endif
+
++#if defined(HAVE__BUILTIN_UNREACHABLE)
++# define unreachable() __builtin_unreachable()
++#else
++# define unreachable() do { } while (1)
++#endif
++
+ #ifdef DEBUG
+ # define UNW_DEBUG 1
+ #else
+--- a/src/arm/Gresume.c
++++ b/src/arm/Gresume.c
+@@ -96,7 +96,7 @@ arm_local_resume (unw_addr_space_t as, u
+ : : "r" (c->sigcontext_sp), "r" (c->sigcontext_pc)
+ );
+ }
+- __builtin_unreachable();
++ unreachable();
+ #else
+ printf ("%s: implement me\n", __FUNCTION__);
+ #endif
+--- a/src/sh/Gresume.c
++++ b/src/sh/Gresume.c
+@@ -109,7 +109,7 @@ sh_local_resume (unw_addr_space_t as, un
+ "r" (c->sigcontext_pc)
+ );
+ }
+- __builtin_unreachable();
++ unreachable();
+ #endif
+ return -UNW_EINVAL;
+ }
diff --git a/meta/recipes-support/libunwind/libunwind.inc b/meta/recipes-support/libunwind/libunwind.inc
index b27b9e5..6743b21 100644
--- a/meta/recipes-support/libunwind/libunwind.inc
+++ b/meta/recipes-support/libunwind/libunwind.inc
@@ -11,6 +11,7 @@ PACKAGECONFIG ??= ""
PACKAGECONFIG[lzma] = "--enable-minidebuginfo,--disable-minidebuginfo,lzma"
EXTRA_OECONF_arm = "--enable-debug-frame"
+EXTRA_OECONF_aarch64 = "--enable-debug-frame"
CFLAGS += "${ATOMICOPS}"
ATOMICOPS_armv5 = "-DAO_USE_PTHREAD_DEFS=1"
diff --git a/meta/recipes-support/libunwind/libunwind_1.1.bb b/meta/recipes-support/libunwind/libunwind_1.1.bb
index bc38e36..2e52430 100644
--- a/meta/recipes-support/libunwind/libunwind_1.1.bb
+++ b/meta/recipes-support/libunwind/libunwind_1.1.bb
@@ -1,4 +1,9 @@
require libunwind.inc
+SRC_URI += "\
+ file://Support-building-with-older-compilers.patch \
+ file://AArch64-port.patch \
+"
+
SRC_URI[md5sum] = "fb4ea2f6fbbe45bf032cd36e586883ce"
SRC_URI[sha256sum] = "9dfe0fcae2a866de9d3942c66995e4b460230446887dbdab302d41a8aee8d09a"
--
1.9.1
^ permalink raw reply related [flat|nested] 51+ messages in thread* Re: [PATCH 13/24] libunwind: add aarch64 support
2014-11-07 8:51 ` [PATCH 13/24] libunwind: add aarch64 support Kai Kang
@ 2014-12-08 20:56 ` Burton, Ross
2014-12-17 8:53 ` Kang Kai
0 siblings, 1 reply; 51+ messages in thread
From: Burton, Ross @ 2014-12-08 20:56 UTC (permalink / raw)
To: Kai Kang; +Cc: Koen Kooi, OE-core
[-- Attachment #1: Type: text/plain, Size: 389 bytes --]
On 7 November 2014 at 08:51, Kai Kang <kai.kang@windriver.com> wrote:
> - Support-building-with-older-compilers (fix undefined reference to
> `unreachable' on older compilers)
>
This patch is missing a signed-off-by header, and considering that oe-core
has gcc 4.9 do we still need this, or is it specific to a commercial
product that is using an older toolchain?
Ross
[-- Attachment #2: Type: text/html, Size: 784 bytes --]
^ permalink raw reply [flat|nested] 51+ messages in thread
* Re: [PATCH 13/24] libunwind: add aarch64 support
2014-12-08 20:56 ` Burton, Ross
@ 2014-12-17 8:53 ` Kang Kai
2014-12-17 9:23 ` Fathi Boudra
0 siblings, 1 reply; 51+ messages in thread
From: Kang Kai @ 2014-12-17 8:53 UTC (permalink / raw)
To: Burton, Ross; +Cc: Koen Kooi, OE-core
On 2014年12月09日 04:56, Burton, Ross wrote:
> On 7 November 2014 at 08:51, Kai Kang <kai.kang@windriver.com> wrote:
>
>> - Support-building-with-older-compilers (fix undefined reference to
>> `unreachable' on older compilers)
>>
> This patch is missing a signed-off-by header, and considering that oe-core
> has gcc 4.9 do we still need this, or is it specific to a commercial
> product that is using an older toolchain?
It is ok to drop this patch for gcc 4.9. I'll do it.
--Kai
>
> Ross
>
--
Regards,
Neil | Kai Kang
^ permalink raw reply [flat|nested] 51+ messages in thread
* Re: [PATCH 13/24] libunwind: add aarch64 support
2014-12-17 8:53 ` Kang Kai
@ 2014-12-17 9:23 ` Fathi Boudra
2014-12-17 9:41 ` Kang Kai
0 siblings, 1 reply; 51+ messages in thread
From: Fathi Boudra @ 2014-12-17 9:23 UTC (permalink / raw)
To: Kang Kai; +Cc: Koen Kooi, OE-core
On 17 December 2014 at 10:53, Kang Kai <Kai.Kang@windriver.com> wrote:
> On 2014年12月09日 04:56, Burton, Ross wrote:
>>
>> On 7 November 2014 at 08:51, Kai Kang <kai.kang@windriver.com> wrote:
>>
>>> - Support-building-with-older-compilers (fix undefined reference to
>>> `unreachable' on older compilers)
>>>
>> This patch is missing a signed-off-by header, and considering that oe-core
>> has gcc 4.9 do we still need this, or is it specific to a commercial
>> product that is using an older toolchain?
we still need this.
>
> It is ok to drop this patch for gcc 4.9. I'll do it.
no, it isn't ok to drop this patch. aarch64 support is still needed in
libunwind.
> --Kai
>
>>
>> Ross
>>
>
>
> --
> Regards,
> Neil | Kai Kang
^ permalink raw reply [flat|nested] 51+ messages in thread
* Re: [PATCH 13/24] libunwind: add aarch64 support
2014-12-17 9:23 ` Fathi Boudra
@ 2014-12-17 9:41 ` Kang Kai
0 siblings, 0 replies; 51+ messages in thread
From: Kang Kai @ 2014-12-17 9:41 UTC (permalink / raw)
To: Fathi Boudra; +Cc: Koen Kooi, OE-core
On 2014年12月17日 17:23, Fathi Boudra wrote:
> On 17 December 2014 at 10:53, Kang Kai <Kai.Kang@windriver.com> wrote:
>> On 2014年12月09日 04:56, Burton, Ross wrote:
>>> On 7 November 2014 at 08:51, Kai Kang <kai.kang@windriver.com> wrote:
>>>
>>>> - Support-building-with-older-compilers (fix undefined reference to
>>>> `unreachable' on older compilers)
>>>>
>>> This patch is missing a signed-off-by header, and considering that oe-core
>>> has gcc 4.9 do we still need this, or is it specific to a commercial
>>> product that is using an older toolchain?
> we still need this.
>
>> It is ok to drop this patch for gcc 4.9. I'll do it.
> no, it isn't ok to drop this patch. aarch64 support is still needed in
> libunwind.
I mean Support-building-with-older-compilers.patch. Do we still need it?
--Kai
>
>> --Kai
>>
>>> Ross
>>>
>>
>> --
>> Regards,
>> Neil | Kai Kang
>
--
Regards,
Neil | Kai Kang
^ permalink raw reply [flat|nested] 51+ messages in thread
* [PATCH 14/24] runqemu: add qemuarm64 support.
2014-11-07 8:51 [PATCH 00/24] V2: Add machine qemuarm64 Kai Kang
` (12 preceding siblings ...)
2014-11-07 8:51 ` [PATCH 13/24] libunwind: add aarch64 support Kai Kang
@ 2014-11-07 8:51 ` Kai Kang
2014-11-07 8:51 ` [PATCH 15/24] kexec-tools: add aarch64 support Kai Kang
` (11 subsequent siblings)
25 siblings, 0 replies; 51+ messages in thread
From: Kai Kang @ 2014-11-07 8:51 UTC (permalink / raw)
To: ross.burton; +Cc: koen.kooi, openembedded-core
Update scripts runqemu and runqemu-internal to support to boot
qemuarm64.
Signed-off-by: Kai Kang <kai.kang@windriver.com>
---
scripts/runqemu | 5 ++++-
scripts/runqemu-internal | 26 ++++++++++++++++++++++++++
2 files changed, 30 insertions(+), 1 deletion(-)
diff --git a/scripts/runqemu b/scripts/runqemu
index ff64a1d..da35bb8 100755
--- a/scripts/runqemu
+++ b/scripts/runqemu
@@ -108,7 +108,7 @@ process_filename() {
while true; do
arg=${1}
case "$arg" in
- "qemux86" | "qemux86-64" | "qemuarm" | "qemumips" | "qemumipsel" | \
+ "qemux86" | "qemux86-64" | "qemuarm" | "qemuarm64" | "qemumips" | "qemumipsel" | \
"qemumips64" | "qemush4" | "qemuppc" | "qemumicroblaze" | "qemuzynq")
[ -z "$MACHINE" ] && MACHINE=$arg || \
error "conflicting MACHINE types [$MACHINE] and [$arg]"
@@ -301,6 +301,9 @@ QEMUX86_64_DEFAULT_FSTYPE=ext3
QEMUARM_DEFAULT_KERNEL=zImage-qemuarm.bin
QEMUARM_DEFAULT_FSTYPE=ext3
+QEMUARM64_DEFAULT_KERNEL=Image-qemuarm64.bin
+QEMUARM64_DEFAULT_FSTYPE=ext3
+
QEMUMIPS_DEFAULT_KERNEL=vmlinux-qemumips.bin
QEMUMIPS_DEFAULT_FSTYPE=ext3
diff --git a/scripts/runqemu-internal b/scripts/runqemu-internal
index 38745dd..c219419 100755
--- a/scripts/runqemu-internal
+++ b/scripts/runqemu-internal
@@ -50,6 +50,9 @@ else
"qemuarm")
mem_size=128
;;
+ "qemuarm64")
+ mem_size=128
+ ;;
"qemumicroblaze")
mem_size=64
;;
@@ -260,8 +263,17 @@ else
DROOT="/dev/hda"
ROOTFS_OPTIONS="-hda $ROOTFS"
fi
+ if [ "$MACHINE" = "qemuarm64" ]; then
+ QEMU_NETWORK_CMD="-netdev user,id=net0 -device virtio-net-device,netdev=net0"
+ DROOT="/dev/vda"
+ ROOTFS_OPTIONS="-drive id=disk0,file=$ROOTFS -device virtio-blk-device,drive=disk0"
+ fi
+
KERNCMDLINE="mem=$QEMU_MEMORY"
QEMU_UI_OPTIONS="-show-cursor -usb -usbdevice wacom-tablet"
+ if [ $MACHINE = 'qemuarm64' ]; then
+ QEMU_UI_OPTIONS="-nographic"
+ fi
NFS_INSTANCE=`echo $TAP | sed 's/tap//'`
export NFS_INSTANCE
@@ -274,6 +286,7 @@ fi
case "$MACHINE" in
"qemuarm") ;;
+ "qemuarm64") ;;
"qemumicroblaze") ;;
"qemumips") ;;
"qemumipsel") ;;
@@ -362,6 +375,19 @@ if [ "$MACHINE" = "qemuarm" -o "$MACHINE" = "qemuarmv6" -o "$MACHINE" = "qemuarm
fi
fi
+if [ "$MACHINE" = "qemuarm64" ]; then
+ QEMU=qemu-system-aarch64
+
+ export QEMU_AUDIO_DRV="none"
+ QEMU_UI_OPTIONS="$QEMU_UI_OPTIONS"
+ if [ "${FSTYPE:0:3}" = "ext" -o "$FSTYPE" = "btrfs" ]; then
+ KERNCMDLINE="root=/dev/vda rw console=ttyAMA0,38400 mem=$QEMU_MEMORY highres=off"
+ # qemu-system-aarch64 only support '-machine virt -cpu cortex-a57' for now
+ QEMUOPTIONS="$QEMU_NETWORK_CMD -machine virt -cpu cortex-a57 $ROOTFS_OPTIONS $QEMU_UI_OPTIONS"
+ fi
+fi
+
+
if [ "$MACHINE" = "qemux86" ]; then
QEMU=qemu-system-i386
if [ "$KVM_ACTIVE" = "yes" ]; then
--
1.9.1
^ permalink raw reply related [flat|nested] 51+ messages in thread* [PATCH 15/24] kexec-tools: add aarch64 support
2014-11-07 8:51 [PATCH 00/24] V2: Add machine qemuarm64 Kai Kang
` (13 preceding siblings ...)
2014-11-07 8:51 ` [PATCH 14/24] runqemu: add qemuarm64 support Kai Kang
@ 2014-11-07 8:51 ` Kai Kang
2014-11-07 8:51 ` [PATCH 16/24] packagegroup-core-tools-profile: remove sysprof for aarch64 Kai Kang
` (10 subsequent siblings)
25 siblings, 0 replies; 51+ messages in thread
From: Kai Kang @ 2014-11-07 8:51 UTC (permalink / raw)
To: ross.burton; +Cc: koen.kooi, openembedded-core
Add patch from
https://fedorapeople.org/~hrw/aarch64/for-fedora/kexec-aarch64.patch
to add aarch64 support for kexec-tools.
Signed-off-by: Kai Kang <kai.kang@windriver.com>
---
meta/recipes-kernel/kexec/kexec-tools.inc | 2 +-
.../kexec/kexec-tools/kexec-aarch64.patch | 801 +++++++++++++++++++++
meta/recipes-kernel/kexec/kexec-tools_2.0.8.bb | 4 +-
3 files changed, 805 insertions(+), 2 deletions(-)
create mode 100644 meta/recipes-kernel/kexec/kexec-tools/kexec-aarch64.patch
diff --git a/meta/recipes-kernel/kexec/kexec-tools.inc b/meta/recipes-kernel/kexec/kexec-tools.inc
index 7e3b7ad..312424a 100644
--- a/meta/recipes-kernel/kexec/kexec-tools.inc
+++ b/meta/recipes-kernel/kexec/kexec-tools.inc
@@ -12,7 +12,7 @@ SRC_URI = "${KERNELORG_MIRROR}/linux/utils/kernel/kexec/kexec-tools-${PV}.tar.gz
inherit autotools-brokensep
-COMPATIBLE_HOST = '(x86_64.*|i.86.*|arm.*|powerpc.*|mips.*)-(linux|freebsd.*)'
+COMPATIBLE_HOST = '(x86_64.*|i.86.*|arm.*|aarch64.*|powerpc.*|mips.*)-(linux|freebsd.*)'
INSANE_SKIP_${PN} = "arch"
diff --git a/meta/recipes-kernel/kexec/kexec-tools/kexec-aarch64.patch b/meta/recipes-kernel/kexec/kexec-tools/kexec-aarch64.patch
new file mode 100644
index 0000000..b697a54
--- /dev/null
+++ b/meta/recipes-kernel/kexec/kexec-tools/kexec-aarch64.patch
@@ -0,0 +1,801 @@
+From: Geoff Levand <geoff@infradead.org>
+Date: Mon, 15 Jul 2013 23:32:36 +0000 (-0700)
+Subject: Add arm64 support
+X-Git-Url: https://git.linaro.org/gitweb?p=people%2Fgeoff%2Fkexec-tools.git;a=commitdiff_plain;h=fbf5ac6c2c70ec0f6da2b9ff563e573999752c01
+
+Add arm64 support
+
+Signed-off-by: Geoff Levand <geoff@infradead.org>
+
+Get patch from:
+https://fedorapeople.org/~hrw/aarch64/for-fedora/kexec-aarch64.patch
+
+Upstream-Status: Pending
+
+Signed-off-by: Kai Kang <kai.kang@windriver.com>
+---
+
+Index: kexec-tools-2.0.4/configure.ac
+===================================================================
+--- kexec-tools-2.0.4.orig/configure.ac
++++ kexec-tools-2.0.4/configure.ac
+@@ -30,6 +30,9 @@ case $target_cpu in
+ powerpc64 )
+ ARCH="ppc64"
+ ;;
++ aarch64 )
++ ARCH="arm64"
++ ;;
+ arm* )
+ ARCH="arm"
+ ;;
+Index: kexec-tools-2.0.4/kexec/Makefile
+===================================================================
+--- kexec-tools-2.0.4.orig/kexec/Makefile
++++ kexec-tools-2.0.4/kexec/Makefile
+@@ -70,6 +70,7 @@ KEXEC_SRCS += $($(ARCH)_FS2DT)
+
+ include $(srcdir)/kexec/arch/alpha/Makefile
+ include $(srcdir)/kexec/arch/arm/Makefile
++include $(srcdir)/kexec/arch/arm64/Makefile
+ include $(srcdir)/kexec/arch/i386/Makefile
+ include $(srcdir)/kexec/arch/ia64/Makefile
+ include $(srcdir)/kexec/arch/mips/Makefile
+Index: kexec-tools-2.0.4/kexec/arch/arm64/Makefile
+===================================================================
+--- /dev/null
++++ kexec-tools-2.0.4/kexec/arch/arm64/Makefile
+@@ -0,0 +1,13 @@
++
++arm64_KEXEC_SRCS += \
++ kexec/arch/arm64/kexec-arm64.c \
++ kexec/arch/arm64/kexec-elf-arm64.c \
++ kexec/arch/arm64/crashdump-arm64.c
++
++arm64_ARCH_REUSE_INITRD =
++arm64_ADD_SEGMENT =
++arm64_VIRT_TO_PHYS =
++
++dist += $(arm64_KEXEC_SRCS) \
++ kexec/arch/arm64/Makefile \
++ kexec/arch/arm64/kexec-arm64.h
+Index: kexec-tools-2.0.4/kexec/arch/arm64/crashdump-arm64.c
+===================================================================
+--- /dev/null
++++ kexec-tools-2.0.4/kexec/arch/arm64/crashdump-arm64.c
+@@ -0,0 +1,305 @@
++/*
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation (version 2 of the License).
++ */
++
++#include "../../kexec.h"
++#include "../../kexec-elf.h"
++#include "../../crashdump.h"
++
++int is_crashkernel_mem_reserved(void)
++{
++ return 0;
++}
++
++#if 0
++/*
++ * Used to save various memory ranges/regions needed for the captured
++ * kernel to boot. (lime memmap= option in other archs)
++ */
++static struct memory_range crash_memory_ranges[CRASH_MAX_MEMORY_RANGES];
++struct memory_ranges usablemem_rgns = {
++ .size = 0,
++ .ranges = crash_memory_ranges,
++};
++
++/* memory range reserved for crashkernel */
++static struct memory_range crash_reserved_mem;
++
++static struct crash_elf_info elf_info = {
++ .class = ELFCLASS32,
++ .data = ELFDATA2LSB,
++ .machine = EM_ARM,
++ .page_offset = PAGE_OFFSET,
++};
++
++unsigned long phys_offset;
++
++/**
++ * crash_range_callback() - callback called for each iomem region
++ * @data: not used
++ * @nr: not used
++ * @str: name of the memory region
++ * @base: start address of the memory region
++ * @length: size of the memory region
++ *
++ * This function is called once for each memory region found in /proc/iomem. It
++ * locates system RAM and crashkernel reserved memory and places these to
++ * variables: @crash_memory_ranges and @crash_reserved_mem. Number of memory
++ * regions is placed in @crash_memory_nr_ranges.
++ */
++static int crash_range_callback(void *UNUSED(data), int UNUSED(nr),
++ char *str, unsigned long base,
++ unsigned long length)
++{
++ struct memory_range *range;
++
++ if (usablemem_rgns.size >= CRASH_MAX_MEMORY_RANGES)
++ return 1;
++
++ range = usablemem_rgns.ranges + usablemem_rgns.size;
++
++ if (strncmp(str, "System RAM\n", 11) == 0) {
++ range->start = base;
++ range->end = base + length - 1;
++ range->type = RANGE_RAM;
++ usablemem_rgns.size++;
++ } else if (strncmp(str, "Crash kernel\n", 13) == 0) {
++ crash_reserved_mem.start = base;
++ crash_reserved_mem.end = base + length - 1;
++ crash_reserved_mem.type = RANGE_RAM;
++ }
++
++ return 0;
++}
++
++/**
++ * crash_exclude_range() - excludes memory region reserved for crashkernel
++ *
++ * Function locates where crashkernel reserved memory is and removes that region
++ * from the available memory regions.
++ */
++static void crash_exclude_range(void)
++{
++ const struct memory_range *range = &crash_reserved_mem;
++ int i;
++
++ for (i = 0; i < usablemem_rgns.size; i++) {
++ struct memory_range *r = usablemem_rgns.ranges + i;
++
++ /*
++ * We assume that crash area is fully contained in
++ * some larger memory area.
++ */
++ if (r->start <= range->start && r->end >= range->end) {
++ struct memory_range *new;
++ /*
++ * Let's split this area into 2 smaller ones and
++ * remove excluded range from between. First create
++ * new entry for the remaining area.
++ */
++ new = usablemem_rgns.ranges + usablemem_rgns.size;
++ new->start = range->end + 1;
++ new->end = r->end;
++ usablemem_rgns.size++;
++ /*
++ * Next update this area to end before excluded range.
++ */
++ r->end = range->start - 1;
++ break;
++ }
++ }
++}
++
++static int range_cmp(const void *a1, const void *a2)
++{
++ const struct memory_range *r1 = a1;
++ const struct memory_range *r2 = a2;
++
++ if (r1->start > r2->start)
++ return 1;
++ if (r1->start < r2->start)
++ return -1;
++
++ return 0;
++}
++
++/**
++ * crash_get_memory_ranges() - read system physical memory
++ *
++ * Function reads through system physical memory and stores found memory regions
++ * in @crash_memory_ranges. Number of memory regions found is placed in
++ * @crash_memory_nr_ranges. Regions are sorted in ascending order.
++ *
++ * Returns %0 in case of success and %-1 otherwise (errno is set).
++ */
++static int crash_get_memory_ranges(void)
++{
++ /*
++ * First read all memory regions that can be considered as
++ * system memory including the crash area.
++ */
++ kexec_iomem_for_each_line(NULL, crash_range_callback, NULL);
++
++ if (usablemem_rgns.size < 1) {
++ errno = EINVAL;
++ return -1;
++ }
++
++ /*
++ * Exclude memory reserved for crashkernel (this may result a split memory
++ * region).
++ */
++ crash_exclude_range();
++
++ /*
++ * Make sure that the memory regions are sorted.
++ */
++ qsort(usablemem_rgns.ranges, usablemem_rgns.size,
++ sizeof(*usablemem_rgns.ranges), range_cmp);
++
++ return 0;
++}
++
++/**
++ * cmdline_add_elfcorehdr() - adds elfcorehdr= to @cmdline
++ * @cmdline: buffer where parameter is placed
++ * @elfcorehdr: physical address of elfcorehdr
++ *
++ * Function appends 'elfcorehdr=start' at the end of the command line given in
++ * @cmdline. Note that @cmdline must be at least %COMMAND_LINE_SIZE bytes long
++ * (inclunding %NUL).
++ */
++static void cmdline_add_elfcorehdr(char *cmdline, unsigned long elfcorehdr)
++{
++ char buf[COMMAND_LINE_SIZE];
++ int buflen;
++
++ buflen = snprintf(buf, sizeof(buf), "%s elfcorehdr=%#lx",
++ cmdline, elfcorehdr);
++ if (buflen < 0)
++ die("Failed to construct elfcorehdr= command line parameter\n");
++ if (buflen >= sizeof(buf))
++ die("Command line overflow\n");
++
++ (void) strncpy(cmdline, buf, COMMAND_LINE_SIZE);
++ cmdline[COMMAND_LINE_SIZE - 1] = '\0';
++}
++
++/**
++ * cmdline_add_mem() - adds mem= parameter to kernel command line
++ * @cmdline: buffer where parameter is placed
++ * @size: size of the kernel reserved memory (in bytes)
++ *
++ * This function appends 'mem=size' at the end of the command line given in
++ * @cmdline. Note that @cmdline must be at least %COMMAND_LINE_SIZE bytes long
++ * (including %NUL).
++ */
++static void cmdline_add_mem(char *cmdline, unsigned long size)
++{
++ char buf[COMMAND_LINE_SIZE];
++ int buflen;
++
++ buflen = snprintf(buf, sizeof(buf), "%s mem=%ldK", cmdline, size >> 10);
++ if (buflen < 0)
++ die("Failed to construct mem= command line parameter\n");
++ if (buflen >= sizeof(buf))
++ die("Command line overflow\n");
++
++ (void) strncpy(cmdline, buf, COMMAND_LINE_SIZE);
++ cmdline[COMMAND_LINE_SIZE - 1] = '\0';
++}
++
++static unsigned long long range_size(const struct memory_range *r)
++{
++ return r->end - r->start + 1;
++}
++
++static void dump_memory_ranges(void)
++{
++ int i;
++
++ if (!kexec_debug)
++ return;
++
++ dbgprintf("crashkernel: [%#llx - %#llx] (%ldM)\n",
++ crash_reserved_mem.start, crash_reserved_mem.end,
++ (unsigned long)range_size(&crash_reserved_mem) >> 20);
++
++ for (i = 0; i < usablemem_rgns.size; i++) {
++ struct memory_range *r = usablemem_rgns.ranges + i;
++ dbgprintf("memory range: [%#llx - %#llx] (%ldM)\n",
++ r->start, r->end, (unsigned long)range_size(r) >> 20);
++ }
++}
++
++/**
++ * load_crashdump_segments() - loads additional segments needed for kdump
++ * @info: kexec info structure
++ * @mod_cmdline: kernel command line
++ *
++ * This function loads additional segments which are needed for the dump capture
++ * kernel. It also updates kernel command line passed in @mod_cmdline to have
++ * right parameters for the dump capture kernel.
++ *
++ * Return %0 in case of success and %-1 in case of error.
++ */
++int load_crashdump_segments(struct kexec_info *info, char *mod_cmdline)
++{
++ unsigned long elfcorehdr;
++ unsigned long bufsz;
++ void *buf;
++ int err;
++
++ /*
++ * First fetch all the memory (RAM) ranges that we are going to pass to
++ * the crashdump kernel during panic.
++ */
++ err = crash_get_memory_ranges();
++ if (err)
++ return err;
++
++ /*
++ * Now that we have memory regions sorted, we can use first memory
++ * region as PHYS_OFFSET.
++ */
++ phys_offset = usablemem_rgns.ranges->start;
++ dbgprintf("phys_offset: %#lx\n", phys_offset);
++
++ err = crash_create_elf32_headers(info, &elf_info,
++ usablemem_rgns.ranges,
++ usablemem_rgns.size, &buf, &bufsz,
++ ELF_CORE_HEADER_ALIGN);
++ if (err)
++ return err;
++
++ /*
++ * We allocate ELF core header from the end of the memory area reserved
++ * for the crashkernel. We align the header to SECTION_SIZE (which is
++ * 1MB) so that available memory passed in kernel command line will be
++ * aligned to 1MB. This is because kernel create_mapping() wants memory
++ * regions to be aligned to SECTION_SIZE.
++ */
++ elfcorehdr = add_buffer_phys_virt(info, buf, bufsz, bufsz, 1 << 20,
++ crash_reserved_mem.start,
++ crash_reserved_mem.end, -1, 0);
++
++ dbgprintf("elfcorehdr: %#lx\n", elfcorehdr);
++ cmdline_add_elfcorehdr(mod_cmdline, elfcorehdr);
++
++ /*
++ * Add 'mem=size' parameter to dump capture kernel command line. This
++ * prevents the dump capture kernel from using any other memory regions
++ * which belong to the primary kernel.
++ */
++ cmdline_add_mem(mod_cmdline, elfcorehdr - crash_reserved_mem.start);
++
++ dump_memory_ranges();
++ dbgprintf("kernel command line: \"%s\"\n", mod_cmdline);
++
++ return 0;
++}
++
++#endif
++
+Index: kexec-tools-2.0.4/kexec/arch/arm64/include/arch/options.h
+===================================================================
+--- /dev/null
++++ kexec-tools-2.0.4/kexec/arch/arm64/include/arch/options.h
+@@ -0,0 +1,26 @@
++#ifndef KEXEC_ARCH_ARM64_OPTIONS_H
++#define KEXEC_ARCH_ARM64_OPTIONS_H
++
++//#define OPT_ARCH_MAX ((OPT_MAX)+0)
++
++#define OPT_APPEND ((OPT_MAX)+0)
++#define OPT_RAMDISK ((OPT_MAX)+1)
++#define OPT_DTB ((OPT_MAX)+2)
++
++#define OPT_ARCH_MAX ((OPT_MAX)+3)
++
++
++#define KEXEC_ARCH_OPTIONS \
++ KEXEC_OPTIONS \
++ { "append", 1, NULL, OPT_APPEND }, \
++ { "command-line", 1, NULL, OPT_APPEND }, \
++ { "dtb", 1, NULL, OPT_DTB }, \
++ { "initrd", 1, NULL, OPT_RAMDISK }, \
++ { "ramdisk", 1, NULL, OPT_RAMDISK }, \
++
++#define KEXEC_ARCH_OPT_STR KEXEC_OPT_STR /* Only accept long arch options. */
++
++#define KEXEC_ALL_OPTIONS KEXEC_ARCH_OPTIONS
++#define KEXEC_ALL_OPT_STR KEXEC_ARCH_OPT_STR
++
++#endif /* KEXEC_ARCH_ARM64_OPTIONS_H */
+Index: kexec-tools-2.0.4/kexec/arch/arm64/kexec-arm64.c
+===================================================================
+--- /dev/null
++++ kexec-tools-2.0.4/kexec/arch/arm64/kexec-arm64.c
+@@ -0,0 +1,177 @@
++/*
++ * ARM64 kexec support.
++ */
++
++#define _GNU_SOURCE
++
++#include <errno.h>
++#include <stddef.h>
++
++//#include <linux/kexec.h>
++
++#include "../../kexec.h"
++#include "../../kexec-syscall.h"
++#include "kexec-arm64.h"
++
++
++void arch_usage(void)
++{
++ fprintf(stderr, "%s:%d: ->\n", __func__, __LINE__);
++
++ printf(
++" --append=STRING Set the kernel command line to STRING.\n"
++" --command-line=STRING Set the kernel command line to STRING.\n"
++" --dtb=FILE Use FILE as the device tree blob.\n"
++" --initrd=FILE Use FILE as the kernel initial ramdisk.\n"
++" --ramdisk=FILE Use FILE as the kernel initial ramdisk.\n");
++
++ fprintf(stderr, "%s:%d: <-\n", __func__, __LINE__);
++}
++
++int arch_process_options(int UNUSED(argc), char **UNUSED(argv))
++{
++ fprintf(stderr, "%s:%d: do\n", __func__, __LINE__);
++ return 0;
++}
++
++const struct arch_map_entry arches[] = {
++ { "aarch64", KEXEC_ARCH_ARM64 },
++ { NULL, 0 },
++};
++
++void arch_update_purgatory(struct kexec_info *UNUSED(info))
++{
++ fprintf(stderr, "%s:%d: do\n", __func__, __LINE__);
++}
++
++unsigned long virt_to_phys(unsigned long addr)
++{
++ fprintf(stderr, "%s:%d: %016lx -> %016lx\n", __func__, __LINE__, addr,
++ addr + 0x080000000UL);
++ return addr + 0x080000000UL;
++}
++
++void add_segment(struct kexec_info *info, const void *buf, size_t bufsz,
++ unsigned long base, size_t memsz)
++{
++ fprintf(stderr, "%s:%d: ->\n", __func__, __LINE__);
++ add_segment_phys_virt(info, buf, bufsz, base, memsz, 1);
++ fprintf(stderr, "%s:%d: <-\n", __func__, __LINE__);
++}
++
++static int get_memory_ranges_1(struct memory_range **range, int *ranges,
++ unsigned long kexec_flags)
++{
++ static struct memory_range memory_range[KEXEC_SEGMENT_MAX];
++ const char *iomem;
++ int range_count = 0;
++ char line[MAX_LINE];
++ FILE *fp;
++
++ iomem = proc_iomem();
++ fp = fopen(iomem, "r");
++
++ if (!fp) {
++ fprintf(stderr, "Cannot open %s: %s\n",
++ iomem, strerror(errno));
++ return -1;
++ }
++
++ dbgprintf("memory ranges:\n");
++
++ while(fgets(line, sizeof(line), fp) != 0) {
++ struct memory_range r;
++ char *str;
++ int consumed;
++
++ if (range_count >= KEXEC_SEGMENT_MAX)
++ break;
++
++ if (sscanf(line, "%Lx-%Lx : %n", &r.start, &r.end, &consumed)
++ != 2)
++ continue;
++
++ str = line + consumed;
++ r.end++;
++
++ if (memcmp(str, "System RAM\n", 11)) {
++ dbgprintf(" Skip: %016Lx - %016Lx : %s", r.start, r.end,
++ str);
++ continue;
++ }
++
++ r.type = RANGE_RAM;
++ memory_range[range_count] = r;
++ range_count++;
++
++ dbgprintf(" Add: %016Lx - %016Lx : %s", r.start, r.end, str);
++ }
++
++ fclose(fp);
++ *range = memory_range;
++ *ranges = range_count;
++
++ return 0;
++}
++
++static int get_memory_ranges_2(struct memory_range **range, int *ranges,
++ unsigned long UNUSED(kexec_flags))
++{
++ static struct memory_range memory_range[2];
++
++ memory_range[0].start = 0x080000000;
++ memory_range[0].end = 0x100000000;
++ memory_range[0].type = RANGE_RAM;
++
++ memory_range[1].start = 0x900000000;
++ memory_range[1].end = 0x880000000;
++ memory_range[1].type = RANGE_RAM;
++
++ *range = memory_range;
++ *ranges = sizeof(memory_range) / sizeof(memory_range[0]);
++
++ return 0;
++}
++
++int get_memory_ranges(struct memory_range **range, int *ranges,
++ unsigned long kexec_flags)
++{
++ /* FIXME: Should get this info from device tree. */
++
++ return get_memory_ranges_1(range, ranges, kexec_flags);
++}
++
++struct file_type file_type[] = {
++ { "elf-arm64", elf_arm64_probe, elf_arm64_load, elf_arm64_usage },
++};
++
++int file_types = sizeof(file_type) / sizeof(file_type[0]);
++
++int arch_compat_trampoline(struct kexec_info *info)
++{
++ fprintf(stderr, "%s:%d: do\n", __func__, __LINE__);
++ return 0;
++}
++
++void arch_reuse_initrd(void)
++{
++}
++
++int machine_verify_elf_rel(struct mem_ehdr *ehdr)
++{
++ (void)ehdr;
++
++ fprintf(stderr, "%s:%d: do\n", __func__, __LINE__);
++ return 0;
++}
++
++void machine_apply_elf_rel(struct mem_ehdr *ehdr, unsigned long r_type,
++ void *location, unsigned long address, unsigned long value)
++{
++ (void)ehdr;
++ (void)r_type;
++ (void)location;
++ (void)address;
++ (void)value;
++ fprintf(stderr, "%s:%d: do\n", __func__, __LINE__);
++}
+Index: kexec-tools-2.0.4/kexec/arch/arm64/kexec-arm64.h
+===================================================================
+--- /dev/null
++++ kexec-tools-2.0.4/kexec/arch/arm64/kexec-arm64.h
+@@ -0,0 +1,20 @@
++/*
++ * ARM64 kexec support.
++ */
++
++#if !defined(KEXEC_ARM64_H)
++#define KEXEC_ARM64_H
++
++/* #include <linux/kexec.h> FIXME: this is broken */
++#include <sys/types.h>
++
++#include "../../kexec.h"
++
++#define KEXEC_SEGMENT_MAX 16 /* FIXME: this should come from <linux/kexec.h> */
++
++int elf_arm64_probe(const char *buf, off_t len);
++int elf_arm64_load(int argc, char **argv, const char *buf, off_t len,
++ struct kexec_info *info);
++void elf_arm64_usage(void);
++
++#endif
+\ No newline at end of file
+Index: kexec-tools-2.0.4/kexec/arch/arm64/kexec-elf-arm64.c
+===================================================================
+--- /dev/null
++++ kexec-tools-2.0.4/kexec/arch/arm64/kexec-elf-arm64.c
+@@ -0,0 +1,114 @@
++/*
++ * ARM64 kexec support.
++ */
++
++#define _GNU_SOURCE
++
++#include <elf.h>
++#include <getopt.h>
++
++#include "../../kexec-syscall.h"
++
++#include "kexec-arm64.h"
++#include "arch/options.h"
++
++#if !defined(EM_AARCH64)
++# define EM_AARCH64 183
++#endif
++
++int elf_arm64_probe(const char *buf, off_t len)
++{
++ int result;
++ struct mem_ehdr ehdr;
++
++ fprintf(stderr, "%s:%d: ->\n", __func__, __LINE__);
++
++ result = build_elf_exec_info(buf, len, &ehdr, 0);
++
++ if (result < 0) {
++ dbgprintf("Not an ELF executable\n");
++ goto out;
++ }
++
++ if (ehdr.e_machine != EM_AARCH64) {
++ dbgprintf("Not an AARCH64 executable\n");
++ result = -1;
++ goto out;
++ }
++
++ result = 0;
++
++out:
++ free_elf_info(&ehdr);
++ fprintf(stderr, "%s:%d: <-\n", __func__, __LINE__);
++ return result;
++}
++
++int elf_arm64_load(int argc, char **argv, const char *buf, off_t len,
++ struct kexec_info *info)
++{
++ static const struct option options[] = {
++ KEXEC_ARCH_OPTIONS
++ { 0 }
++ };
++ static const char short_options[] = KEXEC_OPT_STR "";
++ const char *command_line = NULL;
++ unsigned int command_line_len = 0;
++ const char *ramdisk = NULL;
++ const char *dtb = NULL;
++ int opt;
++ struct mem_ehdr ehdr;
++ int result;
++
++ fprintf(stderr, "%s:%d: ->\n", __func__, __LINE__);
++
++ while ((opt = getopt_long(argc, argv, short_options, options, 0))
++ != -1) {
++ switch (opt) {
++ default:
++ if (opt < OPT_MAX) /* Ignore core options */
++ break;
++ case OPT_APPEND:
++ command_line = optarg;
++ command_line_len = strlen(command_line) + 1;
++ break;
++ case OPT_RAMDISK:
++ ramdisk = optarg;
++ break;
++ case OPT_DTB:
++ dtb = optarg;
++ break;
++ }
++ }
++
++ fprintf(stderr, "%s:%d: command_line: %s\n", __func__, __LINE__, command_line);
++ fprintf(stderr, "%s:%d: ramdisk: %s\n", __func__, __LINE__, ramdisk);
++ fprintf(stderr, "%s:%d: dtb: %s\n", __func__, __LINE__, dtb);
++
++ if (info->kexec_flags & KEXEC_ON_CRASH) {
++ fprintf(stderr, "kexec: kdump not yet supported on arm64\n");
++ return -1;
++ }
++
++ result = build_elf_exec_info(buf, len, &ehdr, 0);
++
++ if (result < 0) {
++ free_elf_info(&ehdr);
++ fprintf(stderr, "%s:%d: free_elf_info failed\n", __func__,
++ __LINE__);
++ return result;
++ }
++
++ elf_exec_build_load(info, &ehdr, buf, len, 0);
++
++ info->entry = (void*)0x80080000UL; // FIXME
++
++ fprintf(stderr, "%s:%d: <-\n", __func__, __LINE__);
++ return 0;
++}
++
++void elf_arm64_usage(void)
++{
++ fprintf(stderr, "%s:%d: ->\n", __func__, __LINE__);
++ fprintf(stderr, "%s:%d: <-\n", __func__, __LINE__);
++}
+Index: kexec-tools-2.0.4/kexec/kexec-syscall.h
+===================================================================
+--- kexec-tools-2.0.4.orig/kexec/kexec-syscall.h
++++ kexec-tools-2.0.4/kexec/kexec-syscall.h
+@@ -39,8 +39,8 @@
+ #ifdef __s390__
+ #define __NR_kexec_load 277
+ #endif
+-#ifdef __arm__
+-#define __NR_kexec_load __NR_SYSCALL_BASE + 347
++#if defined(__arm__) || defined(__arm64__)
++#define __NR_kexec_load __NR_SYSCALL_BASE + 347
+ #endif
+ #if defined(__mips__)
+ #define __NR_kexec_load 4311
+@@ -72,6 +72,8 @@ static inline long kexec_load(void *entr
+ #define KEXEC_ARCH_PPC64 (21 << 16)
+ #define KEXEC_ARCH_IA_64 (50 << 16)
+ #define KEXEC_ARCH_ARM (40 << 16)
++#define KEXEC_ARCH_ARM64 (183 << 16)
++/* #define KEXEC_ARCH_AARCH64 (183 << 16) */
+ #define KEXEC_ARCH_S390 (22 << 16)
+ #define KEXEC_ARCH_SH (42 << 16)
+ #define KEXEC_ARCH_MIPS_LE (10 << 16)
+@@ -114,5 +116,8 @@ static inline long kexec_load(void *entr
+ #if defined(__mips__)
+ #define KEXEC_ARCH_NATIVE KEXEC_ARCH_MIPS
+ #endif
++#if defined(__arm64__)
++#define KEXEC_ARCH_NATIVE KEXEC_ARCH_ARM64
++#endif
+
+ #endif /* KEXEC_SYSCALL_H */
+Index: kexec-tools-2.0.4/kexec/kexec.c
+===================================================================
+--- kexec-tools-2.0.4.orig/kexec/kexec.c
++++ kexec-tools-2.0.4/kexec/kexec.c
+@@ -659,6 +659,8 @@ static int my_load(const char *type, int
+ info.backup_start = 0;
+ info.kexec_flags = kexec_flags;
+
++ fprintf(stderr, "%s:%d: do\n", __func__, __LINE__);
++
+ result = 0;
+ if (argc - fileind <= 0) {
+ fprintf(stderr, "No kernel specified\n");
+Index: kexec-tools-2.0.4/purgatory/arch/arm64/Makefile
+===================================================================
+--- /dev/null
++++ kexec-tools-2.0.4/purgatory/arch/arm64/Makefile
+@@ -0,0 +1,7 @@
++#
++# Purgatory arm64
++#
++
++arm64_PURGATORY_SRCS =
++
++dist += purgatory/arch/arm64/Makefile $(arm64_PURGATORY_SRCS)
+Index: kexec-tools-2.0.4/configure
+===================================================================
+--- kexec-tools-2.0.4.orig/configure
++++ kexec-tools-2.0.4/configure
+@@ -2256,6 +2256,9 @@ case $target_cpu in
+ powerpc64 )
+ ARCH="ppc64"
+ ;;
++ aarch64 )
++ ARCH="arm64"
++ ;;
+ arm* )
+ ARCH="arm"
+ ;;
diff --git a/meta/recipes-kernel/kexec/kexec-tools_2.0.8.bb b/meta/recipes-kernel/kexec/kexec-tools_2.0.8.bb
index 559bc6a..c478732 100644
--- a/meta/recipes-kernel/kexec/kexec-tools_2.0.8.bb
+++ b/meta/recipes-kernel/kexec/kexec-tools_2.0.8.bb
@@ -2,7 +2,9 @@ require kexec-tools.inc
export LDFLAGS = "-L${STAGING_LIBDIR}"
EXTRA_OECONF = " --with-zlib=yes"
-SRC_URI += "file://kexec-tools-Refine-kdump-device_tree-sort.patch"
+SRC_URI += "file://kexec-tools-Refine-kdump-device_tree-sort.patch \
+ file://kexec-aarch64.patch \
+ "
SRC_URI[md5sum] = "45bd2bc676ae202579e4c185563126af"
SRC_URI[sha256sum] = "95083c707577154a2241c5af0985f1eb3412d1ba208ef91813e9158b0a901179"
--
1.9.1
^ permalink raw reply related [flat|nested] 51+ messages in thread* [PATCH 16/24] packagegroup-core-tools-profile: remove sysprof for aarch64
2014-11-07 8:51 [PATCH 00/24] V2: Add machine qemuarm64 Kai Kang
` (14 preceding siblings ...)
2014-11-07 8:51 ` [PATCH 15/24] kexec-tools: add aarch64 support Kai Kang
@ 2014-11-07 8:51 ` Kai Kang
2014-12-08 20:51 ` Burton, Ross
2014-11-07 8:51 ` [PATCH 17/24] qemu: add single step support " Kai Kang
` (9 subsequent siblings)
25 siblings, 1 reply; 51+ messages in thread
From: Kai Kang @ 2014-11-07 8:51 UTC (permalink / raw)
To: ross.burton; +Cc: koen.kooi, openembedded-core
Remove sysprof from packagegroup-core-tools-profile that sysprof doesn't
support arch aarch64.
Signed-off-by: Kai Kang <kai.kang@windriver.com>
---
meta/recipes-core/packagegroups/packagegroup-core-tools-profile.bb | 2 ++
1 file changed, 2 insertions(+)
diff --git a/meta/recipes-core/packagegroups/packagegroup-core-tools-profile.bb b/meta/recipes-core/packagegroups/packagegroup-core-tools-profile.bb
index 41d2548..3cf7027 100644
--- a/meta/recipes-core/packagegroups/packagegroup-core-tools-profile.bb
+++ b/meta/recipes-core/packagegroups/packagegroup-core-tools-profile.bb
@@ -12,6 +12,8 @@ PACKAGE_ARCH = "${MACHINE_ARCH}"
inherit packagegroup
PROFILE_TOOLS_X = "${@bb.utils.contains('DISTRO_FEATURES', 'x11', 'sysprof', '', d)}"
+# sysprof doesn't support aarch64
+PROFILE_TOOLS_X_aarch64 = ""
PROFILE_TOOLS_SYSTEMD = "${@bb.utils.contains('DISTRO_FEATURES', 'systemd', 'systemd-analyze', '', d)}"
RRECOMMENDS_${PN} = "\
--
1.9.1
^ permalink raw reply related [flat|nested] 51+ messages in thread* Re: [PATCH 16/24] packagegroup-core-tools-profile: remove sysprof for aarch64
2014-11-07 8:51 ` [PATCH 16/24] packagegroup-core-tools-profile: remove sysprof for aarch64 Kai Kang
@ 2014-12-08 20:51 ` Burton, Ross
2014-12-09 1:48 ` Kang Kai
0 siblings, 1 reply; 51+ messages in thread
From: Burton, Ross @ 2014-12-08 20:51 UTC (permalink / raw)
To: Kai Kang; +Cc: Koen Kooi, OE-core
[-- Attachment #1: Type: text/plain, Size: 261 bytes --]
On 7 November 2014 at 08:51, Kai Kang <kai.kang@windriver.com> wrote:
> +# sysprof doesn't support aarch64
> +PROFILE_TOOLS_X_aarch64 = ""
>
The rest of the file uses for example SYSPROF and SYSPROF_aarch64, please
match the existing pattern.
Ross
[-- Attachment #2: Type: text/html, Size: 701 bytes --]
^ permalink raw reply [flat|nested] 51+ messages in thread
* Re: [PATCH 16/24] packagegroup-core-tools-profile: remove sysprof for aarch64
2014-12-08 20:51 ` Burton, Ross
@ 2014-12-09 1:48 ` Kang Kai
2014-12-09 11:56 ` Burton, Ross
0 siblings, 1 reply; 51+ messages in thread
From: Kang Kai @ 2014-12-09 1:48 UTC (permalink / raw)
To: Burton, Ross; +Cc: Koen Kooi, OE-core
On 2014年12月09日 04:51, Burton, Ross wrote:
> On 7 November 2014 at 08:51, Kai Kang <kai.kang@windriver.com> wrote:
>
>> +# sysprof doesn't support aarch64
>> +PROFILE_TOOLS_X_aarch64 = ""
>>
> The rest of the file uses for example SYSPROF and SYSPROF_aarch64, please
> match the existing pattern.
In the following var definition, it uses PROFILE_TOOLS_X:
RRECOMMENDS_${PN} = "\
perf \
trace-cmd \
kernel-module-oprofile \
blktrace \
${PROFILE_TOOLS_X} \
${PROFILE_TOOLS_SYSTEMD} \
"
I suppose that use SYSPROF_aarch64 doesn't work here.
--Kai
>
> Ross
>
--
Regards,
Neil | Kai Kang
^ permalink raw reply [flat|nested] 51+ messages in thread* Re: [PATCH 16/24] packagegroup-core-tools-profile: remove sysprof for aarch64
2014-12-09 1:48 ` Kang Kai
@ 2014-12-09 11:56 ` Burton, Ross
2014-12-09 17:45 ` Khem Raj
2014-12-10 1:39 ` Kang Kai
0 siblings, 2 replies; 51+ messages in thread
From: Burton, Ross @ 2014-12-09 11:56 UTC (permalink / raw)
To: Kang Kai; +Cc: Koen Kooi, OE-core
[-- Attachment #1: Type: text/plain, Size: 503 bytes --]
On 9 December 2014 at 01:48, Kang Kai <Kai.Kang@windriver.com> wrote:
> In the following var definition, it uses PROFILE_TOOLS_X:
>
> RRECOMMENDS_${PN} = "\
> perf \
> trace-cmd \
> kernel-module-oprofile \
> blktrace \
> ${PROFILE_TOOLS_X} \
> ${PROFILE_TOOLS_SYSTEMD} \
> "
>
> I suppose that use SYSPROF_aarch64 doesn't work here.
>
But this is exactly what lttng does:
SYSPROF="sysprof"
SYSPROF_aarch64=""
RRECOMMENDS_${PN} = "${SYSPROF}"
Ross
[-- Attachment #2: Type: text/html, Size: 1110 bytes --]
^ permalink raw reply [flat|nested] 51+ messages in thread* Re: [PATCH 16/24] packagegroup-core-tools-profile: remove sysprof for aarch64
2014-12-09 11:56 ` Burton, Ross
@ 2014-12-09 17:45 ` Khem Raj
2014-12-10 1:39 ` Kang Kai
1 sibling, 0 replies; 51+ messages in thread
From: Khem Raj @ 2014-12-09 17:45 UTC (permalink / raw)
To: Burton, Ross; +Cc: Koen Kooi, OE-core
[-- Attachment #1: Type: text/plain, Size: 899 bytes --]
> On Dec 9, 2014, at 3:56 AM, Burton, Ross <ross.burton@intel.com> wrote:
>
>
> On 9 December 2014 at 01:48, Kang Kai <Kai.Kang@windriver.com <mailto:Kai.Kang@windriver.com>> wrote:
> In the following var definition, it uses PROFILE_TOOLS_X:
>
> RRECOMMENDS_${PN} = "\
> perf \
> trace-cmd \
> kernel-module-oprofile \
> blktrace \
> ${PROFILE_TOOLS_X} \
> ${PROFILE_TOOLS_SYSTEMD} \
> "
>
> I suppose that use SYSPROF_aarch64 doesn't work here.
>
> But this is exactly what lttng does:
>
> SYSPROF=“sysprof"
shouldn’t this be ?= for better understasnding
> SYSPROF_aarch64=“"
> RRECOMMENDS_${PN} = "${SYSPROF}"
>
> Ross
> --
> _______________________________________________
> Openembedded-core mailing list
> Openembedded-core@lists.openembedded.org
> http://lists.openembedded.org/mailman/listinfo/openembedded-core
[-- Attachment #2: Type: text/html, Size: 2405 bytes --]
^ permalink raw reply [flat|nested] 51+ messages in thread* Re: [PATCH 16/24] packagegroup-core-tools-profile: remove sysprof for aarch64
2014-12-09 11:56 ` Burton, Ross
2014-12-09 17:45 ` Khem Raj
@ 2014-12-10 1:39 ` Kang Kai
2014-12-10 12:27 ` Burton, Ross
1 sibling, 1 reply; 51+ messages in thread
From: Kang Kai @ 2014-12-10 1:39 UTC (permalink / raw)
To: Burton, Ross; +Cc: Koen Kooi, OE-core
On 2014年12月09日 19:56, Burton, Ross wrote:
> On 9 December 2014 at 01:48, Kang Kai <Kai.Kang@windriver.com> wrote:
>
>> In the following var definition, it uses PROFILE_TOOLS_X:
>>
>> RRECOMMENDS_${PN} = "\
>> perf \
>> trace-cmd \
>> kernel-module-oprofile \
>> blktrace \
>> ${PROFILE_TOOLS_X} \
>> ${PROFILE_TOOLS_SYSTEMD} \
>> "
>>
>> I suppose that use SYSPROF_aarch64 doesn't work here.
>>
> But this is exactly what lttng does:
>
> SYSPROF="sysprof"
> SYSPROF_aarch64=""
> RRECOMMENDS_${PN} = "${SYSPROF}"
I think I misunderstood you. Do you mean update like this:
SYSPROF = "${@bb.utils.contains('DISTRO_FEATURES', 'x11', 'sysprof', '',
d)}"
SYSPROF_aarch64 = ""
RRECOMMENDS_${PN} = "\
... \
${SYSPROF} \
"
I'll update it.
Thanks,
Kai
>
> Ross
>
--
Regards,
Neil | Kai Kang
^ permalink raw reply [flat|nested] 51+ messages in thread* Re: [PATCH 16/24] packagegroup-core-tools-profile: remove sysprof for aarch64
2014-12-10 1:39 ` Kang Kai
@ 2014-12-10 12:27 ` Burton, Ross
2014-12-17 9:00 ` Kang Kai
0 siblings, 1 reply; 51+ messages in thread
From: Burton, Ross @ 2014-12-10 12:27 UTC (permalink / raw)
To: Kang Kai; +Cc: Koen Kooi, OE-core
[-- Attachment #1: Type: text/plain, Size: 372 bytes --]
On 10 December 2014 at 01:39, Kang Kai <Kai.Kang@windriver.com> wrote:
> I think I misunderstood you. Do you mean update like this:
>
> SYSPROF = "${@bb.utils.contains('DISTRO_FEATURES', 'x11', 'sysprof', '',
> d)}"
> SYSPROF_aarch64 = ""
>
> RRECOMMENDS_${PN} = "\
> ... \
> ${SYSPROF} \
>
> "
>
> I'll update it.
>
Yep, that's it.
Ross
[-- Attachment #2: Type: text/html, Size: 887 bytes --]
^ permalink raw reply [flat|nested] 51+ messages in thread* Re: [PATCH 16/24] packagegroup-core-tools-profile: remove sysprof for aarch64
2014-12-10 12:27 ` Burton, Ross
@ 2014-12-17 9:00 ` Kang Kai
0 siblings, 0 replies; 51+ messages in thread
From: Kang Kai @ 2014-12-17 9:00 UTC (permalink / raw)
To: Burton, Ross; +Cc: Koen Kooi, OE-core
On 2014年12月10日 20:27, Burton, Ross wrote:
> On 10 December 2014 at 01:39, Kang Kai <Kai.Kang@windriver.com> wrote:
>
>> I think I misunderstood you. Do you mean update like this:
>>
>> SYSPROF = "${@bb.utils.contains('DISTRO_FEATURES', 'x11', 'sysprof', '',
>> d)}"
>> SYSPROF_aarch64 = ""
>>
>> RRECOMMENDS_${PN} = "\
>> ... \
>> ${SYSPROF} \
>>
>> "
>>
>> I'll update it.
>>
> Yep, that's it.
I didn't find the usage of SYSPROF in lttng recipes. Neither in this
serial commits nor the oe-core master branch.
Where did you find it?
Thanks,
Kai
>
> Ross
>
--
Regards,
Neil | Kai Kang
^ permalink raw reply [flat|nested] 51+ messages in thread
* [PATCH 17/24] qemu: add single step support for aarch64
2014-11-07 8:51 [PATCH 00/24] V2: Add machine qemuarm64 Kai Kang
` (15 preceding siblings ...)
2014-11-07 8:51 ` [PATCH 16/24] packagegroup-core-tools-profile: remove sysprof for aarch64 Kai Kang
@ 2014-11-07 8:51 ` Kai Kang
2014-12-08 20:53 ` Burton, Ross
2014-11-07 8:51 ` [PATCH 18/24] Revert "gcc-4.9: redefine default library install directory" Kai Kang
` (8 subsequent siblings)
25 siblings, 1 reply; 51+ messages in thread
From: Kai Kang @ 2014-11-07 8:51 UTC (permalink / raw)
To: ross.burton; +Cc: koen.kooi, openembedded-core
Backport patches to enable signle-step support for aarch64.
Signed-off-by: Kai Kang <kai.kang@windriver.com>
---
...Collect-up-the-debug-cp-register-definiti.patch | 177 ++++++++++++
...Allow-STATE_BOTH-reginfo-descriptions-for.patch | 57 ++++
...Provide-both-32-and-64-bit-versions-of-de.patch | 89 ++++++
...get-arm-Adjust-debug-ID-registers-per-CPU.patch | 142 ++++++++++
...Don-t-allow-AArch32-to-access-RES0-CPSR-b.patch | 118 ++++++++
...Correctly-handle-PSTATE.SS-when-taking-ex.patch | 38 +++
...Set-PSTATE.SS-correctly-on-exception-retu.patch | 152 +++++++++++
...A64-Avoid-duplicate-exit_tb-0-in-non-link.patch | 47 ++++
...Implement-ARMv8-single-step-handling-for-.patch | 302 +++++++++++++++++++++
...Implement-ARMv8-single-stepping-for-AArch.patch | 212 +++++++++++++++
...t-arm-Implement-MDSCR_EL1-as-having-state.patch | 36 +++
meta/recipes-devtools/qemu/qemu_2.1.2.bb | 13 +-
12 files changed, 1382 insertions(+), 1 deletion(-)
create mode 100644 meta/recipes-devtools/qemu/qemu/0001-target-arm-Collect-up-the-debug-cp-register-definiti.patch
create mode 100644 meta/recipes-devtools/qemu/qemu/0002-target-arm-Allow-STATE_BOTH-reginfo-descriptions-for.patch
create mode 100644 meta/recipes-devtools/qemu/qemu/0003-target-arm-Provide-both-32-and-64-bit-versions-of-de.patch
create mode 100644 meta/recipes-devtools/qemu/qemu/0004-target-arm-Adjust-debug-ID-registers-per-CPU.patch
create mode 100644 meta/recipes-devtools/qemu/qemu/0005-target-arm-Don-t-allow-AArch32-to-access-RES0-CPSR-b.patch
create mode 100644 meta/recipes-devtools/qemu/qemu/0006-target-arm-Correctly-handle-PSTATE.SS-when-taking-ex.patch
create mode 100644 meta/recipes-devtools/qemu/qemu/0007-target-arm-Set-PSTATE.SS-correctly-on-exception-retu.patch
create mode 100644 meta/recipes-devtools/qemu/qemu/0008-target-arm-A64-Avoid-duplicate-exit_tb-0-in-non-link.patch
create mode 100644 meta/recipes-devtools/qemu/qemu/0009-target-arm-Implement-ARMv8-single-step-handling-for-.patch
create mode 100644 meta/recipes-devtools/qemu/qemu/0010-target-arm-Implement-ARMv8-single-stepping-for-AArch.patch
create mode 100644 meta/recipes-devtools/qemu/qemu/0011-target-arm-Implement-MDSCR_EL1-as-having-state.patch
diff --git a/meta/recipes-devtools/qemu/qemu/0001-target-arm-Collect-up-the-debug-cp-register-definiti.patch b/meta/recipes-devtools/qemu/qemu/0001-target-arm-Collect-up-the-debug-cp-register-definiti.patch
new file mode 100644
index 0000000..84c9c86
--- /dev/null
+++ b/meta/recipes-devtools/qemu/qemu/0001-target-arm-Collect-up-the-debug-cp-register-definiti.patch
@@ -0,0 +1,177 @@
+From 503006983a19be0b481946afac2cab0bdd21f124 Mon Sep 17 00:00:00 2001
+From: Peter Maydell <peter.maydell@linaro.org>
+Date: Tue, 19 Aug 2014 18:56:25 +0100
+Subject: [PATCH 01/11] target-arm: Collect up the debug cp register
+ definitions
+
+At the moment we have a mixed set of mostly dummy register
+definitions for various debug related registers which have
+been added piecemeal in order to get Linux kernels to boot.
+In preparation for actually implementing debug support,
+bring them all together into one place.
+
+This commit doesn't change behaviour: we still expose
+exactly the same registers and behaviour to the guest
+in all configurations.
+
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
+
+Upstream-Status: Backport
+Signed-off-by: Kai Kang <kai.kang@windriver.com>
+---
+ target-arm/helper.c | 85 +++++++++++++++++++++++++++++++++--------------------
+ 1 file changed, 53 insertions(+), 32 deletions(-)
+
+diff --git a/target-arm/helper.c b/target-arm/helper.c
+index f630d96..a9be7ba 100644
+--- a/target-arm/helper.c
++++ b/target-arm/helper.c
+@@ -389,12 +389,6 @@ static void tlbimvaa_write(CPUARMState *env, const ARMCPRegInfo *ri,
+ }
+
+ static const ARMCPRegInfo cp_reginfo[] = {
+- /* DBGDIDR: just RAZ. In particular this means the "debug architecture
+- * version" bits will read as a reserved value, which should cause
+- * Linux to not try to use the debug hardware.
+- */
+- { .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0,
+- .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
+ { .name = "FCSEIDR", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 0,
+ .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c13_fcse),
+ .resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, },
+@@ -471,6 +465,13 @@ static const ARMCPRegInfo not_v7_cp_reginfo[] = {
+ { .name = "DUMMY", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = CP_ANY,
+ .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
+ .resetvalue = 0 },
++ /* We don't implement pre-v7 debug but most CPUs had at least a DBGDIDR;
++ * implementing it as RAZ means the "debug architecture version" bits
++ * will read as a reserved value, which should cause Linux to not try
++ * to use the debug hardware.
++ */
++ { .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0,
++ .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
+ REGINFO_SENTINEL
+ };
+
+@@ -712,13 +713,6 @@ static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri)
+ }
+
+ static const ARMCPRegInfo v7_cp_reginfo[] = {
+- /* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped
+- * debug components
+- */
+- { .name = "DBGDRAR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0,
+- .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
+- { .name = "DBGDSAR", .cp = 14, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
+- .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
+ /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */
+ { .name = "NOP", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
+ .access = PL1_W, .type = ARM_CP_NOP },
+@@ -1734,11 +1728,6 @@ static const ARMCPRegInfo lpae_cp_reginfo[] = {
+ { .name = "AMAIR1", .cp = 15, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 1,
+ .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_OVERRIDE,
+ .resetvalue = 0 },
+- /* 64 bit access versions of the (dummy) debug registers */
+- { .name = "DBGDRAR", .cp = 14, .crm = 1, .opc1 = 0,
+- .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
+- { .name = "DBGDSAR", .cp = 14, .crm = 2, .opc1 = 0,
+- .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
+ { .name = "PAR", .cp = 15, .crm = 7, .opc1 = 0,
+ .access = PL1_RW, .type = ARM_CP_64BIT,
+ .fieldoffset = offsetof(CPUARMState, cp15.par_el1), .resetvalue = 0 },
+@@ -2083,16 +2072,6 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
+ .opc1 = 0, .crn = 3, .crm = 0, .opc2 = 0,
+ .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c3),
+ .resetvalue = 0, .writefn = dacr_write, .raw_writefn = raw_write, },
+- /* Dummy implementation of monitor debug system control register:
+- * we don't support debug.
+- */
+- { .name = "MDSCR_EL1", .state = ARM_CP_STATE_AA64,
+- .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2,
+- .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+- /* We define a dummy WI OSLAR_EL1, because Linux writes to it. */
+- { .name = "OSLAR_EL1", .state = ARM_CP_STATE_AA64,
+- .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 4,
+- .access = PL1_W, .type = ARM_CP_NOP },
+ { .name = "ELR_EL1", .state = ARM_CP_STATE_AA64,
+ .type = ARM_CP_NO_MIGRATE,
+ .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 1,
+@@ -2206,13 +2185,55 @@ static CPAccessResult ctr_el0_access(CPUARMState *env, const ARMCPRegInfo *ri)
+ return CP_ACCESS_OK;
+ }
+
+-static void define_aarch64_debug_regs(ARMCPU *cpu)
++static const ARMCPRegInfo debug_cp_reginfo[] = {
++ /* DBGDIDR: just RAZ. In particular this means the "debug architecture
++ * version" bits will read as a reserved value, which should cause
++ * Linux to not try to use the debug hardware.
++ */
++ { .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0,
++ .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
++ /* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped
++ * debug components
++ */
++ { .name = "DBGDRAR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0,
++ .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
++ { .name = "DBGDSAR", .cp = 14, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
++ .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
++ /* Dummy implementation of monitor debug system control register:
++ * we don't support debug.
++ */
++ { .name = "MDSCR_EL1", .state = ARM_CP_STATE_AA64,
++ .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2,
++ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
++ /* We define a dummy WI OSLAR_EL1, because Linux writes to it. */
++ { .name = "OSLAR_EL1", .state = ARM_CP_STATE_AA64,
++ .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 4,
++ .access = PL1_W, .type = ARM_CP_NOP },
++ REGINFO_SENTINEL
++};
++
++static const ARMCPRegInfo debug_lpae_cp_reginfo[] = {
++ /* 64 bit access versions of the (dummy) debug registers */
++ { .name = "DBGDRAR", .cp = 14, .crm = 1, .opc1 = 0,
++ .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
++ { .name = "DBGDSAR", .cp = 14, .crm = 2, .opc1 = 0,
++ .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
++ REGINFO_SENTINEL
++};
++
++static void define_debug_regs(ARMCPU *cpu)
+ {
+- /* Define breakpoint and watchpoint registers. These do nothing
+- * but read as written, for now.
++ /* Define v7 and v8 architectural debug registers.
++ * These are just dummy implementations for now.
+ */
+ int i;
+
++ define_arm_cp_regs(cpu, debug_cp_reginfo);
++
++ if (arm_feature(&cpu->env, ARM_FEATURE_LPAE)) {
++ define_arm_cp_regs(cpu, debug_lpae_cp_reginfo);
++ }
++
+ for (i = 0; i < 16; i++) {
+ ARMCPRegInfo dbgregs[] = {
+ { .name = "DBGBVR", .state = ARM_CP_STATE_AA64,
+@@ -2353,6 +2374,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
+ };
+ define_one_arm_cp_reg(cpu, &clidr);
+ define_arm_cp_regs(cpu, v7_cp_reginfo);
++ define_debug_regs(cpu);
+ } else {
+ define_arm_cp_regs(cpu, not_v7_cp_reginfo);
+ }
+@@ -2426,7 +2448,6 @@ void register_cp_regs_for_features(ARMCPU *cpu)
+ define_one_arm_cp_reg(cpu, &rvbar);
+ define_arm_cp_regs(cpu, v8_idregs);
+ define_arm_cp_regs(cpu, v8_cp_reginfo);
+- define_aarch64_debug_regs(cpu);
+ }
+ if (arm_feature(env, ARM_FEATURE_EL2)) {
+ define_arm_cp_regs(cpu, v8_el2_cp_reginfo);
+--
+2.1.1.273.g97b8860
+
diff --git a/meta/recipes-devtools/qemu/qemu/0002-target-arm-Allow-STATE_BOTH-reginfo-descriptions-for.patch b/meta/recipes-devtools/qemu/qemu/0002-target-arm-Allow-STATE_BOTH-reginfo-descriptions-for.patch
new file mode 100644
index 0000000..398276b
--- /dev/null
+++ b/meta/recipes-devtools/qemu/qemu/0002-target-arm-Allow-STATE_BOTH-reginfo-descriptions-for.patch
@@ -0,0 +1,57 @@
+From 58a1d8ceabbbf0ddaa8d6d81faa2f77816d35e18 Mon Sep 17 00:00:00 2001
+From: Peter Maydell <peter.maydell@linaro.org>
+Date: Tue, 19 Aug 2014 18:56:25 +0100
+Subject: [PATCH 02/11] target-arm: Allow STATE_BOTH reginfo descriptions for
+ more than cp14
+
+Currently the STATE_BOTH shorthand for allowing a single reginfo struct
+to define handling for both AArch32 and AArch64 views of a register
+only permits this where the AArch32 view is in cp15. It turns out that
+the debug registers in cp14 also have neatly lined up encodings;
+allow these also to share reginfo structs by permitting a STATE_BOTH
+reginfo to specify the .cp field (and continue to default to 15 if
+it is not specified).
+
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
+
+Upstream-Status: Backport
+Signed-off-by: Kai Kang <kai.kang@windriver.com>
+---
+ target-arm/helper.c | 11 ++++++++---
+ 1 file changed, 8 insertions(+), 3 deletions(-)
+
+diff --git a/target-arm/helper.c b/target-arm/helper.c
+index a9be7ba..8239aea 100644
+--- a/target-arm/helper.c
++++ b/target-arm/helper.c
+@@ -2800,9 +2800,11 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
+ /* The AArch32 view of a shared register sees the lower 32 bits
+ * of a 64 bit backing field. It is not migratable as the AArch64
+ * view handles that. AArch64 also handles reset.
+- * We assume it is a cp15 register.
++ * We assume it is a cp15 register if the .cp field is left unset.
+ */
+- r2->cp = 15;
++ if (r2->cp == 0) {
++ r2->cp = 15;
++ }
+ r2->type |= ARM_CP_NO_MIGRATE;
+ r2->resetfn = arm_cp_reset_ignore;
+ #ifdef HOST_WORDS_BIGENDIAN
+@@ -2815,8 +2817,11 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
+ /* To allow abbreviation of ARMCPRegInfo
+ * definitions, we treat cp == 0 as equivalent to
+ * the value for "standard guest-visible sysreg".
++ * STATE_BOTH definitions are also always "standard
++ * sysreg" in their AArch64 view (the .cp value may
++ * be non-zero for the benefit of the AArch32 view).
+ */
+- if (r->cp == 0) {
++ if (r->cp == 0 || r->state == ARM_CP_STATE_BOTH) {
+ r2->cp = CP_REG_ARM64_SYSREG_CP;
+ }
+ *key = ENCODE_AA64_CP_REG(r2->cp, r2->crn, crm,
+--
+2.1.1.273.g97b8860
+
diff --git a/meta/recipes-devtools/qemu/qemu/0003-target-arm-Provide-both-32-and-64-bit-versions-of-de.patch b/meta/recipes-devtools/qemu/qemu/0003-target-arm-Provide-both-32-and-64-bit-versions-of-de.patch
new file mode 100644
index 0000000..849f20a
--- /dev/null
+++ b/meta/recipes-devtools/qemu/qemu/0003-target-arm-Provide-both-32-and-64-bit-versions-of-de.patch
@@ -0,0 +1,89 @@
+From 10aae1049fe90b84798af2751051ea896437a831 Mon Sep 17 00:00:00 2001
+From: Peter Maydell <peter.maydell@linaro.org>
+Date: Tue, 19 Aug 2014 18:56:25 +0100
+Subject: [PATCH 03/11] target-arm: Provide both 32 and 64 bit versions of
+ debug registers
+
+Bring the 32 bit and 64 bit views of the debug registers into
+line by providing the same set of registers in both cases.
+(This still isn't a complete set, but it is consistent.)
+
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
+
+Upstream-Status: Backport
+Signed-off-by: Kai Kang <kai.kang@windriver.com>
+---
+ target-arm/helper.c | 34 ++++++++++++++++++++--------------
+ 1 file changed, 20 insertions(+), 14 deletions(-)
+
+diff --git a/target-arm/helper.c b/target-arm/helper.c
+index 8239aea..700057d 100644
+--- a/target-arm/helper.c
++++ b/target-arm/helper.c
+@@ -2193,21 +2193,27 @@ static const ARMCPRegInfo debug_cp_reginfo[] = {
+ { .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0,
+ .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
+ /* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped
+- * debug components
++ * debug components. The AArch64 version of DBGDRAR is named MDRAR_EL1;
++ * unlike DBGDRAR it is never accessible from EL0.
++ * DBGDSAR is deprecated and must RAZ from v8 anyway, so it has no AArch64
++ * accessor.
+ */
+ { .name = "DBGDRAR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0,
+ .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
++ { .name = "MDRAR_EL1", .state = ARM_CP_STATE_AA64,
++ .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 0,
++ .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
+ { .name = "DBGDSAR", .cp = 14, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
+ .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
+ /* Dummy implementation of monitor debug system control register:
+- * we don't support debug.
++ * we don't support debug. (The 32-bit alias is DBGDSCRext.)
+ */
+- { .name = "MDSCR_EL1", .state = ARM_CP_STATE_AA64,
+- .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2,
++ { .name = "MDSCR_EL1", .state = ARM_CP_STATE_BOTH,
++ .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2,
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+ /* We define a dummy WI OSLAR_EL1, because Linux writes to it. */
+- { .name = "OSLAR_EL1", .state = ARM_CP_STATE_AA64,
+- .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 4,
++ { .name = "OSLAR_EL1", .state = ARM_CP_STATE_BOTH,
++ .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 4,
+ .access = PL1_W, .type = ARM_CP_NOP },
+ REGINFO_SENTINEL
+ };
+@@ -2236,20 +2242,20 @@ static void define_debug_regs(ARMCPU *cpu)
+
+ for (i = 0; i < 16; i++) {
+ ARMCPRegInfo dbgregs[] = {
+- { .name = "DBGBVR", .state = ARM_CP_STATE_AA64,
+- .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 4,
++ { .name = "DBGBVR", .state = ARM_CP_STATE_BOTH,
++ .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 4,
+ .access = PL1_RW,
+ .fieldoffset = offsetof(CPUARMState, cp15.dbgbvr[i]) },
+- { .name = "DBGBCR", .state = ARM_CP_STATE_AA64,
+- .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 5,
++ { .name = "DBGBCR", .state = ARM_CP_STATE_BOTH,
++ .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 5,
+ .access = PL1_RW,
+ .fieldoffset = offsetof(CPUARMState, cp15.dbgbcr[i]) },
+- { .name = "DBGWVR", .state = ARM_CP_STATE_AA64,
+- .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 6,
++ { .name = "DBGWVR", .state = ARM_CP_STATE_BOTH,
++ .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 6,
+ .access = PL1_RW,
+ .fieldoffset = offsetof(CPUARMState, cp15.dbgwvr[i]) },
+- { .name = "DBGWCR", .state = ARM_CP_STATE_AA64,
+- .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 7,
++ { .name = "DBGWCR", .state = ARM_CP_STATE_BOTH,
++ .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 7,
+ .access = PL1_RW,
+ .fieldoffset = offsetof(CPUARMState, cp15.dbgwcr[i]) },
+ REGINFO_SENTINEL
+--
+2.1.1.273.g97b8860
+
diff --git a/meta/recipes-devtools/qemu/qemu/0004-target-arm-Adjust-debug-ID-registers-per-CPU.patch b/meta/recipes-devtools/qemu/qemu/0004-target-arm-Adjust-debug-ID-registers-per-CPU.patch
new file mode 100644
index 0000000..cff6e8c
--- /dev/null
+++ b/meta/recipes-devtools/qemu/qemu/0004-target-arm-Adjust-debug-ID-registers-per-CPU.patch
@@ -0,0 +1,142 @@
+From 48eb3ae64b3e17151cf8f42af185e6f43baf707b Mon Sep 17 00:00:00 2001
+From: Peter Maydell <peter.maydell@linaro.org>
+Date: Tue, 19 Aug 2014 18:56:25 +0100
+Subject: [PATCH 04/11] target-arm: Adjust debug ID registers per-CPU
+
+Allow each CPU type to specify the value for the debug ID
+registers, by putting them in the ARMCPU struct, and use
+the resulting information to only expose the correct number
+of watchpoint and breakpoint registers for the CPU.
+
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
+
+Upstream-Status: Backport
+Signed-off-by: Kai Kang <kai.kang@windriver.com>
+---
+ target-arm/cpu-qom.h | 1 +
+ target-arm/cpu.c | 3 +++
+ target-arm/cpu64.c | 1 +
+ target-arm/helper.c | 33 ++++++++++++++++++++++++++-------
+ 4 files changed, 31 insertions(+), 7 deletions(-)
+
+diff --git a/target-arm/cpu-qom.h b/target-arm/cpu-qom.h
+index ee4fbb1..07f3c9e 100644
+--- a/target-arm/cpu-qom.h
++++ b/target-arm/cpu-qom.h
+@@ -148,6 +148,7 @@ typedef struct ARMCPU {
+ uint64_t id_aa64isar1;
+ uint64_t id_aa64mmfr0;
+ uint64_t id_aa64mmfr1;
++ uint32_t dbgdidr;
+ uint32_t clidr;
+ /* The elements of this array are the CCSIDR values for each cache,
+ * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc.
+diff --git a/target-arm/cpu.c b/target-arm/cpu.c
+index 7cebb76..e27cca2 100644
+--- a/target-arm/cpu.c
++++ b/target-arm/cpu.c
+@@ -640,6 +640,7 @@ static void cortex_a8_initfn(Object *obj)
+ cpu->id_isar2 = 0x21232031;
+ cpu->id_isar3 = 0x11112131;
+ cpu->id_isar4 = 0x00111142;
++ cpu->dbgdidr = 0x15141000;
+ cpu->clidr = (1 << 27) | (2 << 24) | 3;
+ cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */
+ cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */
+@@ -712,6 +713,7 @@ static void cortex_a9_initfn(Object *obj)
+ cpu->id_isar2 = 0x21232041;
+ cpu->id_isar3 = 0x11112131;
+ cpu->id_isar4 = 0x00111142;
++ cpu->dbgdidr = 0x35141000;
+ cpu->clidr = (1 << 27) | (1 << 24) | 3;
+ cpu->ccsidr[0] = 0xe00fe015; /* 16k L1 dcache. */
+ cpu->ccsidr[1] = 0x200fe015; /* 16k L1 icache. */
+@@ -773,6 +775,7 @@ static void cortex_a15_initfn(Object *obj)
+ cpu->id_isar2 = 0x21232041;
+ cpu->id_isar3 = 0x11112131;
+ cpu->id_isar4 = 0x10011142;
++ cpu->dbgdidr = 0x3515f021;
+ cpu->clidr = 0x0a200023;
+ cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
+ cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
+diff --git a/target-arm/cpu64.c b/target-arm/cpu64.c
+index 8b2081c..38d2b84 100644
+--- a/target-arm/cpu64.c
++++ b/target-arm/cpu64.c
+@@ -127,6 +127,7 @@ static void aarch64_a57_initfn(Object *obj)
+ cpu->id_aa64dfr0 = 0x10305106;
+ cpu->id_aa64isar0 = 0x00010000;
+ cpu->id_aa64mmfr0 = 0x00001124;
++ cpu->dbgdidr = 0x3516d000;
+ cpu->clidr = 0x0a200023;
+ cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
+ cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
+diff --git a/target-arm/helper.c b/target-arm/helper.c
+index 700057d..22bf6d3 100644
+--- a/target-arm/helper.c
++++ b/target-arm/helper.c
+@@ -2186,12 +2186,6 @@ static CPAccessResult ctr_el0_access(CPUARMState *env, const ARMCPRegInfo *ri)
+ }
+
+ static const ARMCPRegInfo debug_cp_reginfo[] = {
+- /* DBGDIDR: just RAZ. In particular this means the "debug architecture
+- * version" bits will read as a reserved value, which should cause
+- * Linux to not try to use the debug hardware.
+- */
+- { .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0,
+- .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
+ /* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped
+ * debug components. The AArch64 version of DBGDRAR is named MDRAR_EL1;
+ * unlike DBGDRAR it is never accessible from EL0.
+@@ -2233,14 +2227,32 @@ static void define_debug_regs(ARMCPU *cpu)
+ * These are just dummy implementations for now.
+ */
+ int i;
++ int wrps, brps;
++ ARMCPRegInfo dbgdidr = {
++ .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0,
++ .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = cpu->dbgdidr,
++ };
++
++ brps = extract32(cpu->dbgdidr, 24, 4);
++ wrps = extract32(cpu->dbgdidr, 28, 4);
++
++ /* The DBGDIDR and ID_AA64DFR0_EL1 define various properties
++ * of the debug registers such as number of breakpoints;
++ * check that if they both exist then they agree.
++ */
++ if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
++ assert(extract32(cpu->id_aa64dfr0, 12, 4) == brps);
++ assert(extract32(cpu->id_aa64dfr0, 20, 4) == wrps);
++ }
+
++ define_one_arm_cp_reg(cpu, &dbgdidr);
+ define_arm_cp_regs(cpu, debug_cp_reginfo);
+
+ if (arm_feature(&cpu->env, ARM_FEATURE_LPAE)) {
+ define_arm_cp_regs(cpu, debug_lpae_cp_reginfo);
+ }
+
+- for (i = 0; i < 16; i++) {
++ for (i = 0; i < brps + 1; i++) {
+ ARMCPRegInfo dbgregs[] = {
+ { .name = "DBGBVR", .state = ARM_CP_STATE_BOTH,
+ .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 4,
+@@ -2250,6 +2262,13 @@ static void define_debug_regs(ARMCPU *cpu)
+ .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 5,
+ .access = PL1_RW,
+ .fieldoffset = offsetof(CPUARMState, cp15.dbgbcr[i]) },
++ REGINFO_SENTINEL
++ };
++ define_arm_cp_regs(cpu, dbgregs);
++ }
++
++ for (i = 0; i < wrps + 1; i++) {
++ ARMCPRegInfo dbgregs[] = {
+ { .name = "DBGWVR", .state = ARM_CP_STATE_BOTH,
+ .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 6,
+ .access = PL1_RW,
+--
+2.1.1.273.g97b8860
+
diff --git a/meta/recipes-devtools/qemu/qemu/0005-target-arm-Don-t-allow-AArch32-to-access-RES0-CPSR-b.patch b/meta/recipes-devtools/qemu/qemu/0005-target-arm-Don-t-allow-AArch32-to-access-RES0-CPSR-b.patch
new file mode 100644
index 0000000..1e2211b
--- /dev/null
+++ b/meta/recipes-devtools/qemu/qemu/0005-target-arm-Don-t-allow-AArch32-to-access-RES0-CPSR-b.patch
@@ -0,0 +1,118 @@
+From 4051e12c5df1c46b542b28ed43f1614a42245ecf Mon Sep 17 00:00:00 2001
+From: Peter Maydell <peter.maydell@linaro.org>
+Date: Tue, 19 Aug 2014 18:56:26 +0100
+Subject: [PATCH 05/11] target-arm: Don't allow AArch32 to access RES0 CPSR
+ bits
+
+The CPSR has a new-in-v8 execution state bit (IL), and
+also some state which has effects in AArch32 but appears
+only in the SPSR format (SS) but is RES0 in the CPSR.
+
+Add the IL bit to CPSR_EXEC, and enforce that guest direct
+reads and writes to CPSR can't read or write the RES0
+bits, so the guest can't get at the SS bit which we store
+in uncached_cpsr. This includes not permitting exception
+returns to copy reserved bits from an SPSR into CPSR.
+
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
+
+Upstream-Status: Backport
+Signed-off-by: Kai Kang <kai.kang@windriver.com>
+---
+ target-arm/cpu.h | 12 ++++++++++--
+ target-arm/op_helper.c | 2 +-
+ target-arm/translate.c | 13 +++++++------
+ 3 files changed, 18 insertions(+), 9 deletions(-)
+
+diff --git a/target-arm/cpu.h b/target-arm/cpu.h
+index 79205ba..8380c13 100644
+--- a/target-arm/cpu.h
++++ b/target-arm/cpu.h
+@@ -411,7 +411,13 @@ int arm_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
+ #define CPSR_E (1U << 9)
+ #define CPSR_IT_2_7 (0xfc00U)
+ #define CPSR_GE (0xfU << 16)
+-#define CPSR_RESERVED (0xfU << 20)
++#define CPSR_IL (1U << 20)
++/* Note that the RESERVED bits include bit 21, which is PSTATE_SS in
++ * an AArch64 SPSR but RES0 in AArch32 SPSR and CPSR. In QEMU we use
++ * env->uncached_cpsr bit 21 to store PSTATE.SS when executing in AArch32,
++ * where it is live state but not accessible to the AArch32 code.
++ */
++#define CPSR_RESERVED (0x7U << 21)
+ #define CPSR_J (1U << 24)
+ #define CPSR_IT_0_1 (3U << 25)
+ #define CPSR_Q (1U << 27)
+@@ -428,7 +434,9 @@ int arm_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
+ /* Bits writable in user mode. */
+ #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE)
+ /* Execution state bits. MRS read as zero, MSR writes ignored. */
+-#define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J)
++#define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL)
++/* Mask of bits which may be set by exception return copying them from SPSR */
++#define CPSR_ERET_MASK (~CPSR_RESERVED)
+
+ #define TTBCR_N (7U << 0) /* TTBCR.EAE==0 */
+ #define TTBCR_T0SZ (7U << 0) /* TTBCR.EAE==1 */
+diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c
+index 25ad902..180a4a0 100644
+--- a/target-arm/op_helper.c
++++ b/target-arm/op_helper.c
+@@ -258,7 +258,7 @@ void HELPER(exception_with_syndrome)(CPUARMState *env, uint32_t excp,
+
+ uint32_t HELPER(cpsr_read)(CPUARMState *env)
+ {
+- return cpsr_read(env) & ~CPSR_EXEC;
++ return cpsr_read(env) & ~(CPSR_EXEC | CPSR_RESERVED);
+ }
+
+ void HELPER(cpsr_write)(CPUARMState *env, uint32_t val, uint32_t mask)
+diff --git a/target-arm/translate.c b/target-arm/translate.c
+index 4012185..4cde309 100644
+--- a/target-arm/translate.c
++++ b/target-arm/translate.c
+@@ -3908,9 +3908,10 @@ static uint32_t msr_mask(CPUARMState *env, DisasContext *s, int flags, int spsr)
+ mask &= ~(CPSR_E | CPSR_GE);
+ if (!arm_feature(env, ARM_FEATURE_THUMB2))
+ mask &= ~CPSR_IT;
+- /* Mask out execution state bits. */
+- if (!spsr)
+- mask &= ~CPSR_EXEC;
++ /* Mask out execution state and reserved bits. */
++ if (!spsr) {
++ mask &= ~(CPSR_EXEC | CPSR_RESERVED);
++ }
+ /* Mask out privileged bits. */
+ if (IS_USER(s))
+ mask &= CPSR_USER;
+@@ -3954,7 +3955,7 @@ static void gen_exception_return(DisasContext *s, TCGv_i32 pc)
+ TCGv_i32 tmp;
+ store_reg(s, 15, pc);
+ tmp = load_cpu_field(spsr);
+- gen_set_cpsr(tmp, 0xffffffff);
++ gen_set_cpsr(tmp, CPSR_ERET_MASK);
+ tcg_temp_free_i32(tmp);
+ s->is_jmp = DISAS_UPDATE;
+ }
+@@ -3962,7 +3963,7 @@ static void gen_exception_return(DisasContext *s, TCGv_i32 pc)
+ /* Generate a v6 exception return. Marks both values as dead. */
+ static void gen_rfe(DisasContext *s, TCGv_i32 pc, TCGv_i32 cpsr)
+ {
+- gen_set_cpsr(cpsr, 0xffffffff);
++ gen_set_cpsr(cpsr, CPSR_ERET_MASK);
+ tcg_temp_free_i32(cpsr);
+ store_reg(s, 15, pc);
+ s->is_jmp = DISAS_UPDATE;
+@@ -8836,7 +8837,7 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s)
+ if ((insn & (1 << 22)) && !user) {
+ /* Restore CPSR from SPSR. */
+ tmp = load_cpu_field(spsr);
+- gen_set_cpsr(tmp, 0xffffffff);
++ gen_set_cpsr(tmp, CPSR_ERET_MASK);
+ tcg_temp_free_i32(tmp);
+ s->is_jmp = DISAS_UPDATE;
+ }
+--
+2.1.1.273.g97b8860
+
diff --git a/meta/recipes-devtools/qemu/qemu/0006-target-arm-Correctly-handle-PSTATE.SS-when-taking-ex.patch b/meta/recipes-devtools/qemu/qemu/0006-target-arm-Correctly-handle-PSTATE.SS-when-taking-ex.patch
new file mode 100644
index 0000000..2c824e0
--- /dev/null
+++ b/meta/recipes-devtools/qemu/qemu/0006-target-arm-Correctly-handle-PSTATE.SS-when-taking-ex.patch
@@ -0,0 +1,38 @@
+From 662cefb7753c1f04d960b443c60e7622c83144d3 Mon Sep 17 00:00:00 2001
+From: Peter Maydell <peter.maydell@linaro.org>
+Date: Tue, 19 Aug 2014 18:56:26 +0100
+Subject: [PATCH 06/11] target-arm: Correctly handle PSTATE.SS when taking
+ exception to AArch32
+
+When an exception is taken to AArch32, we must clear the PSTATE.SS
+bit for the exception handler, and must also ensure that the SS bit
+is not set in the value saved to SPSR_<mode>. Achieve both of these
+aims by clearing the bit in uncached_cpsr before saving it to the SPSR.
+
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
+
+Upstream-Status: Backport
+Signed-off-by: Kai Kang <kai.kang@windriver.com>
+---
+ target-arm/helper.c | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/target-arm/helper.c b/target-arm/helper.c
+index 22bf6d3..f981569 100644
+--- a/target-arm/helper.c
++++ b/target-arm/helper.c
+@@ -3550,6 +3550,10 @@ void arm_cpu_do_interrupt(CPUState *cs)
+ addr += env->cp15.vbar_el[1];
+ }
+ switch_mode (env, new_mode);
++ /* For exceptions taken to AArch32 we must clear the SS bit in both
++ * PSTATE and in the old-state value we save to SPSR_<mode>, so zero it now.
++ */
++ env->uncached_cpsr &= ~PSTATE_SS;
+ env->spsr = cpsr_read(env);
+ /* Clear IT bits. */
+ env->condexec_bits = 0;
+--
+2.1.1.273.g97b8860
+
diff --git a/meta/recipes-devtools/qemu/qemu/0007-target-arm-Set-PSTATE.SS-correctly-on-exception-retu.patch b/meta/recipes-devtools/qemu/qemu/0007-target-arm-Set-PSTATE.SS-correctly-on-exception-retu.patch
new file mode 100644
index 0000000..ba9f4ad
--- /dev/null
+++ b/meta/recipes-devtools/qemu/qemu/0007-target-arm-Set-PSTATE.SS-correctly-on-exception-retu.patch
@@ -0,0 +1,152 @@
+From 3a2982038afa0f04fc99b259e8ad8c18be0b04cb Mon Sep 17 00:00:00 2001
+From: Peter Maydell <peter.maydell@linaro.org>
+Date: Tue, 19 Aug 2014 18:56:26 +0100
+Subject: [PATCH 07/11] target-arm: Set PSTATE.SS correctly on exception return
+ from AArch64
+
+Set the PSTATE.SS bit correctly on exception returns from AArch64,
+as required by the debug single-step functionality.
+
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
+
+Upstream-Status: Backport
+Signed-off-by: Kai Kang <kai.kang@windriver.com>
+---
+ target-arm/cpu.h | 61 ++++++++++++++++++++++++++++++++++++++++++++++++++
+ target-arm/op_helper.c | 20 +++++++++++++++++
+ 2 files changed, 81 insertions(+)
+
+diff --git a/target-arm/cpu.h b/target-arm/cpu.h
+index 8380c13..74f7b15 100644
+--- a/target-arm/cpu.h
++++ b/target-arm/cpu.h
+@@ -220,6 +220,7 @@ typedef struct CPUARMState {
+ uint64_t dbgbcr[16]; /* breakpoint control registers */
+ uint64_t dbgwvr[16]; /* watchpoint value registers */
+ uint64_t dbgwcr[16]; /* watchpoint control registers */
++ uint64_t mdscr_el1;
+ /* If the counter is enabled, this stores the last time the counter
+ * was reset. Otherwise it stores the counter value
+ */
+@@ -1119,6 +1120,66 @@ static inline int cpu_mmu_index (CPUARMState *env)
+ return arm_current_pl(env);
+ }
+
++/* Return the Exception Level targeted by debug exceptions;
++ * currently always EL1 since we don't implement EL2 or EL3.
++ */
++static inline int arm_debug_target_el(CPUARMState *env)
++{
++ return 1;
++}
++
++static inline bool aa64_generate_debug_exceptions(CPUARMState *env)
++{
++ if (arm_current_pl(env) == arm_debug_target_el(env)) {
++ if ((extract32(env->cp15.mdscr_el1, 13, 1) == 0)
++ || (env->daif & PSTATE_D)) {
++ return false;
++ }
++ }
++ return true;
++}
++
++static inline bool aa32_generate_debug_exceptions(CPUARMState *env)
++{
++ if (arm_current_pl(env) == 0 && arm_el_is_aa64(env, 1)) {
++ return aa64_generate_debug_exceptions(env);
++ }
++ return arm_current_pl(env) != 2;
++}
++
++/* Return true if debugging exceptions are currently enabled.
++ * This corresponds to what in ARM ARM pseudocode would be
++ * if UsingAArch32() then
++ * return AArch32.GenerateDebugExceptions()
++ * else
++ * return AArch64.GenerateDebugExceptions()
++ * We choose to push the if() down into this function for clarity,
++ * since the pseudocode has it at all callsites except for the one in
++ * CheckSoftwareStep(), where it is elided because both branches would
++ * always return the same value.
++ *
++ * Parts of the pseudocode relating to EL2 and EL3 are omitted because we
++ * don't yet implement those exception levels or their associated trap bits.
++ */
++static inline bool arm_generate_debug_exceptions(CPUARMState *env)
++{
++ if (env->aarch64) {
++ return aa64_generate_debug_exceptions(env);
++ } else {
++ return aa32_generate_debug_exceptions(env);
++ }
++}
++
++/* Is single-stepping active? (Note that the "is EL_D AArch64?" check
++ * implicitly means this always returns false in pre-v8 CPUs.)
++ */
++static inline bool arm_singlestep_active(CPUARMState *env)
++{
++ return extract32(env->cp15.mdscr_el1, 0, 1)
++ && arm_el_is_aa64(env, arm_debug_target_el(env))
++ && arm_generate_debug_exceptions(env);
++}
++
+ #include "exec/cpu-all.h"
+
+ /* Bit usage in the TB flags field: bit 31 indicates whether we are
+diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c
+index 180a4a0..62cc07d 100644
+--- a/target-arm/op_helper.c
++++ b/target-arm/op_helper.c
+@@ -380,12 +380,26 @@ void HELPER(exception_return)(CPUARMState *env)
+
+ env->exclusive_addr = -1;
+
++ /* We must squash the PSTATE.SS bit to zero unless both of the
++ * following hold:
++ * 1. debug exceptions are currently disabled
++ * 2. singlestep will be active in the EL we return to
++ * We check 1 here and 2 after we've done the pstate/cpsr write() to
++ * transition to the EL we're going to.
++ */
++ if (arm_generate_debug_exceptions(env)) {
++ spsr &= ~PSTATE_SS;
++ }
++
+ if (spsr & PSTATE_nRW) {
+ /* TODO: We currently assume EL1/2/3 are running in AArch64. */
+ env->aarch64 = 0;
+ new_el = 0;
+ env->uncached_cpsr = 0x10;
+ cpsr_write(env, spsr, ~0);
++ if (!arm_singlestep_active(env)) {
++ env->uncached_cpsr &= ~PSTATE_SS;
++ }
+ for (i = 0; i < 15; i++) {
+ env->regs[i] = env->xregs[i];
+ }
+@@ -410,6 +424,9 @@ void HELPER(exception_return)(CPUARMState *env)
+ }
+ env->aarch64 = 1;
+ pstate_write(env, spsr);
++ if (!arm_singlestep_active(env)) {
++ env->pstate &= ~PSTATE_SS;
++ }
+ env->xregs[31] = env->sp_el[new_el];
+ env->pc = env->elr_el[cur_el];
+ }
+@@ -429,6 +446,9 @@ illegal_return:
+ spsr &= PSTATE_NZCV | PSTATE_DAIF;
+ spsr |= pstate_read(env) & ~(PSTATE_NZCV | PSTATE_DAIF);
+ pstate_write(env, spsr);
++ if (!arm_singlestep_active(env)) {
++ env->pstate &= ~PSTATE_SS;
++ }
+ }
+
+ /* ??? Flag setting arithmetic is awkward because we need to do comparisons.
+--
+2.1.1.273.g97b8860
+
diff --git a/meta/recipes-devtools/qemu/qemu/0008-target-arm-A64-Avoid-duplicate-exit_tb-0-in-non-link.patch b/meta/recipes-devtools/qemu/qemu/0008-target-arm-A64-Avoid-duplicate-exit_tb-0-in-non-link.patch
new file mode 100644
index 0000000..5eb6aec
--- /dev/null
+++ b/meta/recipes-devtools/qemu/qemu/0008-target-arm-A64-Avoid-duplicate-exit_tb-0-in-non-link.patch
@@ -0,0 +1,47 @@
+From cc9c1ed14e876d724107fe72f74dcac71a003fbc Mon Sep 17 00:00:00 2001
+From: Peter Maydell <peter.maydell@linaro.org>
+Date: Tue, 19 Aug 2014 18:56:26 +0100
+Subject: [PATCH 08/11] target-arm: A64: Avoid duplicate exit_tb(0) in
+ non-linked goto_tb
+
+If gen_goto_tb() decides not to link the two TBs, then the
+fallback path generates unnecessary code:
+ * if singlestep is enabled then we generate unreachable code
+ after the gen_exception_internal(EXCP_DEBUG)
+ * if singlestep is disabled then we will generate exit_tb(0)
+ twice, once in gen_goto_tb() and once coming out of the
+ main loop with is_jmp set to DISAS_JUMP
+
+Correct these deficiencies by only emitting exit_tb() in the
+non-singlestep case, in which case we can use DISAS_TB_JUMP
+to suppress the main-loop exit_tb().
+
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
+
+Upstream-Status: Backport
+Signed-off-by: Kai Kang <kai.kang@windriver.com>
+---
+ target-arm/translate-a64.c | 5 +++--
+ 1 file changed, 3 insertions(+), 2 deletions(-)
+
+diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
+index 2e21948..21a997f 100644
+--- a/target-arm/translate-a64.c
++++ b/target-arm/translate-a64.c
+@@ -234,9 +234,10 @@ static inline void gen_goto_tb(DisasContext *s, int n, uint64_t dest)
+ gen_a64_set_pc_im(dest);
+ if (s->singlestep_enabled) {
+ gen_exception_internal(EXCP_DEBUG);
++ } else {
++ tcg_gen_exit_tb(0);
++ s->is_jmp = DISAS_TB_JUMP;
+ }
+- tcg_gen_exit_tb(0);
+- s->is_jmp = DISAS_JUMP;
+ }
+ }
+
+--
+2.1.1.273.g97b8860
+
diff --git a/meta/recipes-devtools/qemu/qemu/0009-target-arm-Implement-ARMv8-single-step-handling-for-.patch b/meta/recipes-devtools/qemu/qemu/0009-target-arm-Implement-ARMv8-single-step-handling-for-.patch
new file mode 100644
index 0000000..c918521
--- /dev/null
+++ b/meta/recipes-devtools/qemu/qemu/0009-target-arm-Implement-ARMv8-single-step-handling-for-.patch
@@ -0,0 +1,302 @@
+From 7ea47fe7be86faed4f38f0093ca1226b9b6043eb Mon Sep 17 00:00:00 2001
+From: Peter Maydell <peter.maydell@linaro.org>
+Date: Tue, 19 Aug 2014 18:56:26 +0100
+Subject: [PATCH 09/11] target-arm: Implement ARMv8 single-step handling for
+ A64 code
+
+Implement ARMv8 software single-step handling for A64 code:
+correctly update the single-step state machine and generate
+debug exceptions when stepping A64 code.
+
+This patch has no behavioural change since MDSCR_EL1.SS can't
+be set by the guest yet.
+
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
+
+Upstream-Status: Backport
+Signed-off-by: Kai Kang <kai.kang@windriver.com>
+---
+ target-arm/cpu.h | 21 +++++++++++
+ target-arm/helper.h | 1 +
+ target-arm/internals.h | 6 +++
+ target-arm/op_helper.c | 5 +++
+ target-arm/translate-a64.c | 91 +++++++++++++++++++++++++++++++++++++++++++---
+ target-arm/translate.h | 12 ++++++
+ 6 files changed, 131 insertions(+), 5 deletions(-)
+
+diff --git a/target-arm/cpu.h b/target-arm/cpu.h
+index 74f7b15..3d3e1d5 100644
+--- a/target-arm/cpu.h
++++ b/target-arm/cpu.h
+@@ -1211,6 +1211,10 @@ static inline bool arm_singlestep_active(CPUARMState *env)
+ #define ARM_TBFLAG_AA64_EL_MASK (0x3 << ARM_TBFLAG_AA64_EL_SHIFT)
+ #define ARM_TBFLAG_AA64_FPEN_SHIFT 2
+ #define ARM_TBFLAG_AA64_FPEN_MASK (1 << ARM_TBFLAG_AA64_FPEN_SHIFT)
++#define ARM_TBFLAG_AA64_SS_ACTIVE_SHIFT 3
++#define ARM_TBFLAG_AA64_SS_ACTIVE_MASK (1 << ARM_TBFLAG_AA64_SS_ACTIVE_SHIFT)
++#define ARM_TBFLAG_AA64_PSTATE_SS_SHIFT 4
++#define ARM_TBFLAG_AA64_PSTATE_SS_MASK (1 << ARM_TBFLAG_AA64_PSTATE_SS_SHIFT)
+
+ /* some convenience accessor macros */
+ #define ARM_TBFLAG_AARCH64_STATE(F) \
+@@ -1235,6 +1239,10 @@ static inline bool arm_singlestep_active(CPUARMState *env)
+ (((F) & ARM_TBFLAG_AA64_EL_MASK) >> ARM_TBFLAG_AA64_EL_SHIFT)
+ #define ARM_TBFLAG_AA64_FPEN(F) \
+ (((F) & ARM_TBFLAG_AA64_FPEN_MASK) >> ARM_TBFLAG_AA64_FPEN_SHIFT)
++#define ARM_TBFLAG_AA64_SS_ACTIVE(F) \
++ (((F) & ARM_TBFLAG_AA64_SS_ACTIVE_MASK) >> ARM_TBFLAG_AA64_SS_ACTIVE_SHIFT)
++#define ARM_TBFLAG_AA64_PSTATE_SS(F) \
++ (((F) & ARM_TBFLAG_AA64_PSTATE_SS_MASK) >> ARM_TBFLAG_AA64_PSTATE_SS_SHIFT)
+
+ static inline void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
+ target_ulong *cs_base, int *flags)
+@@ -1248,6 +1256,19 @@ static inline void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
+ if (fpen == 3 || (fpen == 1 && arm_current_pl(env) != 0)) {
+ *flags |= ARM_TBFLAG_AA64_FPEN_MASK;
+ }
++ /* The SS_ACTIVE and PSTATE_SS bits correspond to the state machine
++ * states defined in the ARM ARM for software singlestep:
++ * SS_ACTIVE PSTATE.SS State
++ * 0 x Inactive (the TB flag for SS is always 0)
++ * 1 0 Active-pending
++ * 1 1 Active-not-pending
++ */
++ if (arm_singlestep_active(env)) {
++ *flags |= ARM_TBFLAG_AA64_SS_ACTIVE_MASK;
++ if (env->pstate & PSTATE_SS) {
++ *flags |= ARM_TBFLAG_AA64_PSTATE_SS_MASK;
++ }
++ }
+ } else {
+ int privmode;
+ *pc = env->regs[15];
+diff --git a/target-arm/helper.h b/target-arm/helper.h
+index facfcd2..1d7003b 100644
+--- a/target-arm/helper.h
++++ b/target-arm/helper.h
+@@ -64,6 +64,7 @@ DEF_HELPER_3(set_cp_reg64, void, env, ptr, i64)
+ DEF_HELPER_2(get_cp_reg64, i64, env, ptr)
+
+ DEF_HELPER_3(msr_i_pstate, void, env, i32, i32)
++DEF_HELPER_1(clear_pstate_ss, void, env)
+ DEF_HELPER_1(exception_return, void, env)
+
+ DEF_HELPER_2(get_r13_banked, i32, env, i32)
+diff --git a/target-arm/internals.h b/target-arm/internals.h
+index 08fa697..53c2e3c 100644
+--- a/target-arm/internals.h
++++ b/target-arm/internals.h
+@@ -290,4 +290,10 @@ static inline uint32_t syn_data_abort(int same_el, int ea, int cm, int s1ptw,
+ | (ea << 9) | (cm << 8) | (s1ptw << 7) | (wnr << 6) | fsc;
+ }
+
++static inline uint32_t syn_swstep(int same_el, int isv, int ex)
++{
++ return (EC_SOFTWARESTEP << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)
++ | (isv << 24) | (ex << 6) | 0x22;
++}
++
+ #endif
+diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c
+index 62cc07d..fe40358 100644
+--- a/target-arm/op_helper.c
++++ b/target-arm/op_helper.c
+@@ -369,6 +369,11 @@ void HELPER(msr_i_pstate)(CPUARMState *env, uint32_t op, uint32_t imm)
+ }
+ }
+
++void HELPER(clear_pstate_ss)(CPUARMState *env)
++{
++ env->pstate &= ~PSTATE_SS;
++}
++
+ void HELPER(exception_return)(CPUARMState *env)
+ {
+ int cur_el = arm_current_pl(env);
+diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
+index 21a997f..8e66b6c 100644
+--- a/target-arm/translate-a64.c
++++ b/target-arm/translate-a64.c
+@@ -205,10 +205,39 @@ static void gen_exception_insn(DisasContext *s, int offset, int excp,
+ s->is_jmp = DISAS_EXC;
+ }
+
++static void gen_ss_advance(DisasContext *s)
++{
++ /* If the singlestep state is Active-not-pending, advance to
++ * Active-pending.
++ */
++ if (s->ss_active) {
++ s->pstate_ss = 0;
++ gen_helper_clear_pstate_ss(cpu_env);
++ }
++}
++
++static void gen_step_complete_exception(DisasContext *s)
++{
++ /* We just completed step of an insn. Move from Active-not-pending
++ * to Active-pending, and then also take the swstep exception.
++ * This corresponds to making the (IMPDEF) choice to prioritize
++ * swstep exceptions over asynchronous exceptions taken to an exception
++ * level where debug is disabled. This choice has the advantage that
++ * we do not need to maintain internal state corresponding to the
++ * ISV/EX syndrome bits between completion of the step and generation
++ * of the exception, and our syndrome information is always correct.
++ */
++ gen_ss_advance(s);
++ gen_exception(EXCP_UDEF, syn_swstep(s->ss_same_el, 1, s->is_ldex));
++ s->is_jmp = DISAS_EXC;
++}
++
+ static inline bool use_goto_tb(DisasContext *s, int n, uint64_t dest)
+ {
+- /* No direct tb linking with singlestep or deterministic io */
+- if (s->singlestep_enabled || (s->tb->cflags & CF_LAST_IO)) {
++ /* No direct tb linking with singlestep (either QEMU's or the ARM
++ * debug architecture kind) or deterministic io
++ */
++ if (s->singlestep_enabled || s->ss_active || (s->tb->cflags & CF_LAST_IO)) {
+ return false;
+ }
+
+@@ -232,7 +261,9 @@ static inline void gen_goto_tb(DisasContext *s, int n, uint64_t dest)
+ s->is_jmp = DISAS_TB_JUMP;
+ } else {
+ gen_a64_set_pc_im(dest);
+- if (s->singlestep_enabled) {
++ if (s->ss_active) {
++ gen_step_complete_exception(s);
++ } else if (s->singlestep_enabled) {
+ gen_exception_internal(EXCP_DEBUG);
+ } else {
+ tcg_gen_exit_tb(0);
+@@ -1449,6 +1480,12 @@ static void disas_exc(DisasContext *s, uint32_t insn)
+ unallocated_encoding(s);
+ break;
+ }
++ /* For SVC, HVC and SMC we advance the single-step state
++ * machine before taking the exception. This is architecturally
++ * mandated, to ensure that single-stepping a system call
++ * instruction works properly.
++ */
++ gen_ss_advance(s);
+ gen_exception_insn(s, 0, EXCP_SWI, syn_aa64_svc(imm16));
+ break;
+ case 1:
+@@ -1729,6 +1766,7 @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn)
+
+ if (is_excl) {
+ if (!is_store) {
++ s->is_ldex = true;
+ gen_load_exclusive(s, rt, rt2, tcg_addr, size, is_pair);
+ } else {
+ gen_store_exclusive(s, rs, rt, rt2, tcg_addr, size, is_pair);
+@@ -10869,6 +10907,26 @@ void gen_intermediate_code_internal_a64(ARMCPU *cpu,
+ dc->current_pl = arm_current_pl(env);
+ dc->features = env->features;
+
++ /* Single step state. The code-generation logic here is:
++ * SS_ACTIVE == 0:
++ * generate code with no special handling for single-stepping (except
++ * that anything that can make us go to SS_ACTIVE == 1 must end the TB;
++ * this happens anyway because those changes are all system register or
++ * PSTATE writes).
++ * SS_ACTIVE == 1, PSTATE.SS == 1: (active-not-pending)
++ * emit code for one insn
++ * emit code to clear PSTATE.SS
++ * emit code to generate software step exception for completed step
++ * end TB (as usual for having generated an exception)
++ * SS_ACTIVE == 1, PSTATE.SS == 0: (active-pending)
++ * emit code to generate a software step exception
++ * end the TB
++ */
++ dc->ss_active = ARM_TBFLAG_AA64_SS_ACTIVE(tb->flags);
++ dc->pstate_ss = ARM_TBFLAG_AA64_PSTATE_SS(tb->flags);
++ dc->is_ldex = false;
++ dc->ss_same_el = (arm_debug_target_el(env) == dc->current_pl);
++
+ init_tmp_a64_array(dc);
+
+ next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
+@@ -10917,6 +10975,23 @@ void gen_intermediate_code_internal_a64(ARMCPU *cpu,
+ tcg_gen_debug_insn_start(dc->pc);
+ }
+
++ if (dc->ss_active && !dc->pstate_ss) {
++ /* Singlestep state is Active-pending.
++ * If we're in this state at the start of a TB then either
++ * a) we just took an exception to an EL which is being debugged
++ * and this is the first insn in the exception handler
++ * b) debug exceptions were masked and we just unmasked them
++ * without changing EL (eg by clearing PSTATE.D)
++ * In either case we're going to take a swstep exception in the
++ * "did not step an insn" case, and so the syndrome ISV and EX
++ * bits should be zero.
++ */
++ assert(num_insns == 0);
++ gen_exception(EXCP_UDEF, syn_swstep(dc->ss_same_el, 0, 0));
++ dc->is_jmp = DISAS_EXC;
++ break;
++ }
++
+ disas_a64_insn(env, dc);
+
+ if (tcg_check_temp_count()) {
+@@ -10933,6 +11008,7 @@ void gen_intermediate_code_internal_a64(ARMCPU *cpu,
+ } while (!dc->is_jmp && tcg_ctx.gen_opc_ptr < gen_opc_end &&
+ !cs->singlestep_enabled &&
+ !singlestep &&
++ !dc->ss_active &&
+ dc->pc < next_page_start &&
+ num_insns < max_insns);
+
+@@ -10940,7 +11016,8 @@ void gen_intermediate_code_internal_a64(ARMCPU *cpu,
+ gen_io_end();
+ }
+
+- if (unlikely(cs->singlestep_enabled) && dc->is_jmp != DISAS_EXC) {
++ if (unlikely(cs->singlestep_enabled || dc->ss_active)
++ && dc->is_jmp != DISAS_EXC) {
+ /* Note that this means single stepping WFI doesn't halt the CPU.
+ * For conditional branch insns this is harmless unreachable code as
+ * gen_goto_tb() has already handled emitting the debug exception
+@@ -10950,7 +11027,11 @@ void gen_intermediate_code_internal_a64(ARMCPU *cpu,
+ if (dc->is_jmp != DISAS_JUMP) {
+ gen_a64_set_pc_im(dc->pc);
+ }
+- gen_exception_internal(EXCP_DEBUG);
++ if (cs->singlestep_enabled) {
++ gen_exception_internal(EXCP_DEBUG);
++ } else {
++ gen_step_complete_exception(dc);
++ }
+ } else {
+ switch (dc->is_jmp) {
+ case DISAS_NEXT:
+diff --git a/target-arm/translate.h b/target-arm/translate.h
+index 31a0104..b90d275 100644
+--- a/target-arm/translate.h
++++ b/target-arm/translate.h
+@@ -40,6 +40,18 @@ typedef struct DisasContext {
+ * that it is set at the point where we actually touch the FP regs.
+ */
+ bool fp_access_checked;
++ /* ARMv8 single-step state (this is distinct from the QEMU gdbstub
++ * single-step support).
++ */
++ bool ss_active;
++ bool pstate_ss;
++ /* True if the insn just emitted was a load-exclusive instruction
++ * (necessary for syndrome information for single step exceptions),
++ * ie A64 LDX*, LDAX*, A32/T32 LDREX*, LDAEX*.
++ */
++ bool is_ldex;
++ /* True if a single-step exception will be taken to the current EL */
++ bool ss_same_el;
+ #define TMP_A64_MAX 16
+ int tmp_a64_count;
+ TCGv_i64 tmp_a64[TMP_A64_MAX];
+--
+2.1.1.273.g97b8860
+
diff --git a/meta/recipes-devtools/qemu/qemu/0010-target-arm-Implement-ARMv8-single-stepping-for-AArch.patch b/meta/recipes-devtools/qemu/qemu/0010-target-arm-Implement-ARMv8-single-stepping-for-AArch.patch
new file mode 100644
index 0000000..22a90c4
--- /dev/null
+++ b/meta/recipes-devtools/qemu/qemu/0010-target-arm-Implement-ARMv8-single-stepping-for-AArch.patch
@@ -0,0 +1,212 @@
+From 50225ad0c185a16c472b3dce984c312e4399a3ef Mon Sep 17 00:00:00 2001
+From: Peter Maydell <peter.maydell@linaro.org>
+Date: Tue, 19 Aug 2014 18:56:27 +0100
+Subject: [PATCH 10/11] target-arm: Implement ARMv8 single-stepping for AArch32
+ code
+
+ARMv8 single-stepping requires the exception level that controls
+the single-stepping to be in AArch64 execution state, but the
+code being stepped may be in AArch64 or AArch32. Implement the
+necessary support code for single-stepping AArch32 code.
+
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
+
+Upstream-Status: Backport
+Signed-off-by: Kai Kang <kai.kang@windriver.com>
+---
+ target-arm/cpu.h | 21 ++++++++++++++
+ target-arm/translate.c | 76 ++++++++++++++++++++++++++++++++++++++++++++++++--
+ 2 files changed, 95 insertions(+), 2 deletions(-)
+
+diff --git a/target-arm/cpu.h b/target-arm/cpu.h
+index 3d3e1d5..8098b8d 100644
+--- a/target-arm/cpu.h
++++ b/target-arm/cpu.h
+@@ -1205,6 +1205,10 @@ static inline bool arm_singlestep_active(CPUARMState *env)
+ #define ARM_TBFLAG_BSWAP_CODE_MASK (1 << ARM_TBFLAG_BSWAP_CODE_SHIFT)
+ #define ARM_TBFLAG_CPACR_FPEN_SHIFT 17
+ #define ARM_TBFLAG_CPACR_FPEN_MASK (1 << ARM_TBFLAG_CPACR_FPEN_SHIFT)
++#define ARM_TBFLAG_SS_ACTIVE_SHIFT 18
++#define ARM_TBFLAG_SS_ACTIVE_MASK (1 << ARM_TBFLAG_SS_ACTIVE_SHIFT)
++#define ARM_TBFLAG_PSTATE_SS_SHIFT 19
++#define ARM_TBFLAG_PSTATE_SS_MASK (1 << ARM_TBFLAG_PSTATE_SS_SHIFT)
+
+ /* Bit usage when in AArch64 state */
+ #define ARM_TBFLAG_AA64_EL_SHIFT 0
+@@ -1235,6 +1239,10 @@ static inline bool arm_singlestep_active(CPUARMState *env)
+ (((F) & ARM_TBFLAG_BSWAP_CODE_MASK) >> ARM_TBFLAG_BSWAP_CODE_SHIFT)
+ #define ARM_TBFLAG_CPACR_FPEN(F) \
+ (((F) & ARM_TBFLAG_CPACR_FPEN_MASK) >> ARM_TBFLAG_CPACR_FPEN_SHIFT)
++#define ARM_TBFLAG_SS_ACTIVE(F) \
++ (((F) & ARM_TBFLAG_SS_ACTIVE_MASK) >> ARM_TBFLAG_SS_ACTIVE_SHIFT)
++#define ARM_TBFLAG_PSTATE_SS(F) \
++ (((F) & ARM_TBFLAG_PSTATE_SS_MASK) >> ARM_TBFLAG_PSTATE_SS_SHIFT)
+ #define ARM_TBFLAG_AA64_EL(F) \
+ (((F) & ARM_TBFLAG_AA64_EL_MASK) >> ARM_TBFLAG_AA64_EL_SHIFT)
+ #define ARM_TBFLAG_AA64_FPEN(F) \
+@@ -1292,6 +1300,19 @@ static inline void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
+ if (fpen == 3 || (fpen == 1 && arm_current_pl(env) != 0)) {
+ *flags |= ARM_TBFLAG_CPACR_FPEN_MASK;
+ }
++ /* The SS_ACTIVE and PSTATE_SS bits correspond to the state machine
++ * states defined in the ARM ARM for software singlestep:
++ * SS_ACTIVE PSTATE.SS State
++ * 0 x Inactive (the TB flag for SS is always 0)
++ * 1 0 Active-pending
++ * 1 1 Active-not-pending
++ */
++ if (arm_singlestep_active(env)) {
++ *flags |= ARM_TBFLAG_SS_ACTIVE_MASK;
++ if (env->uncached_cpsr & PSTATE_SS) {
++ *flags |= ARM_TBFLAG_PSTATE_SS_MASK;
++ }
++ }
+ }
+
+ *cs_base = 0;
+diff --git a/target-arm/translate.c b/target-arm/translate.c
+index 4cde309..2c0b1de 100644
+--- a/target-arm/translate.c
++++ b/target-arm/translate.c
+@@ -205,6 +205,33 @@ static void gen_exception(int excp, uint32_t syndrome)
+ tcg_temp_free_i32(tcg_excp);
+ }
+
++static void gen_ss_advance(DisasContext *s)
++{
++ /* If the singlestep state is Active-not-pending, advance to
++ * Active-pending.
++ */
++ if (s->ss_active) {
++ s->pstate_ss = 0;
++ gen_helper_clear_pstate_ss(cpu_env);
++ }
++}
++
++static void gen_step_complete_exception(DisasContext *s)
++{
++ /* We just completed step of an insn. Move from Active-not-pending
++ * to Active-pending, and then also take the swstep exception.
++ * This corresponds to making the (IMPDEF) choice to prioritize
++ * swstep exceptions over asynchronous exceptions taken to an exception
++ * level where debug is disabled. This choice has the advantage that
++ * we do not need to maintain internal state corresponding to the
++ * ISV/EX syndrome bits between completion of the step and generation
++ * of the exception, and our syndrome information is always correct.
++ */
++ gen_ss_advance(s);
++ gen_exception(EXCP_UDEF, syn_swstep(s->ss_same_el, 1, s->is_ldex));
++ s->is_jmp = DISAS_EXC;
++}
++
+ static void gen_smul_dual(TCGv_i32 a, TCGv_i32 b)
+ {
+ TCGv_i32 tmp1 = tcg_temp_new_i32();
+@@ -3860,7 +3887,7 @@ static inline void gen_goto_tb(DisasContext *s, int n, target_ulong dest)
+
+ static inline void gen_jmp (DisasContext *s, uint32_t dest)
+ {
+- if (unlikely(s->singlestep_enabled)) {
++ if (unlikely(s->singlestep_enabled || s->ss_active)) {
+ /* An indirect jump so that we still trigger the debug exception. */
+ if (s->thumb)
+ dest |= 1;
+@@ -7281,6 +7308,8 @@ static void gen_load_exclusive(DisasContext *s, int rt, int rt2,
+ {
+ TCGv_i32 tmp = tcg_temp_new_i32();
+
++ s->is_ldex = true;
++
+ switch (size) {
+ case 0:
+ gen_aa32_ld8u(tmp, addr, get_mem_index(s));
+@@ -10917,6 +10946,26 @@ static inline void gen_intermediate_code_internal(ARMCPU *cpu,
+ dc->current_pl = arm_current_pl(env);
+ dc->features = env->features;
+
++ /* Single step state. The code-generation logic here is:
++ * SS_ACTIVE == 0:
++ * generate code with no special handling for single-stepping (except
++ * that anything that can make us go to SS_ACTIVE == 1 must end the TB;
++ * this happens anyway because those changes are all system register or
++ * PSTATE writes).
++ * SS_ACTIVE == 1, PSTATE.SS == 1: (active-not-pending)
++ * emit code for one insn
++ * emit code to clear PSTATE.SS
++ * emit code to generate software step exception for completed step
++ * end TB (as usual for having generated an exception)
++ * SS_ACTIVE == 1, PSTATE.SS == 0: (active-pending)
++ * emit code to generate a software step exception
++ * end the TB
++ */
++ dc->ss_active = ARM_TBFLAG_SS_ACTIVE(tb->flags);
++ dc->pstate_ss = ARM_TBFLAG_PSTATE_SS(tb->flags);
++ dc->is_ldex = false;
++ dc->ss_same_el = false; /* Can't be true since EL_d must be AArch64 */
++
+ cpu_F0s = tcg_temp_new_i32();
+ cpu_F1s = tcg_temp_new_i32();
+ cpu_F0d = tcg_temp_new_i64();
+@@ -11026,6 +11075,22 @@ static inline void gen_intermediate_code_internal(ARMCPU *cpu,
+ tcg_gen_debug_insn_start(dc->pc);
+ }
+
++ if (dc->ss_active && !dc->pstate_ss) {
++ /* Singlestep state is Active-pending.
++ * If we're in this state at the start of a TB then either
++ * a) we just took an exception to an EL which is being debugged
++ * and this is the first insn in the exception handler
++ * b) debug exceptions were masked and we just unmasked them
++ * without changing EL (eg by clearing PSTATE.D)
++ * In either case we're going to take a swstep exception in the
++ * "did not step an insn" case, and so the syndrome ISV and EX
++ * bits should be zero.
++ */
++ assert(num_insns == 0);
++ gen_exception(EXCP_UDEF, syn_swstep(dc->ss_same_el, 0, 0));
++ goto done_generating;
++ }
++
+ if (dc->thumb) {
+ disas_thumb_insn(env, dc);
+ if (dc->condexec_mask) {
+@@ -11058,6 +11123,7 @@ static inline void gen_intermediate_code_internal(ARMCPU *cpu,
+ } while (!dc->is_jmp && tcg_ctx.gen_opc_ptr < gen_opc_end &&
+ !cs->singlestep_enabled &&
+ !singlestep &&
++ !dc->ss_active &&
+ dc->pc < next_page_start &&
+ num_insns < max_insns);
+
+@@ -11073,12 +11139,15 @@ static inline void gen_intermediate_code_internal(ARMCPU *cpu,
+ /* At this stage dc->condjmp will only be set when the skipped
+ instruction was a conditional branch or trap, and the PC has
+ already been written. */
+- if (unlikely(cs->singlestep_enabled)) {
++ if (unlikely(cs->singlestep_enabled || dc->ss_active)) {
+ /* Make sure the pc is updated, and raise a debug exception. */
+ if (dc->condjmp) {
+ gen_set_condexec(dc);
+ if (dc->is_jmp == DISAS_SWI) {
++ gen_ss_advance(dc);
+ gen_exception(EXCP_SWI, syn_aa32_svc(dc->svc_imm, dc->thumb));
++ } else if (dc->ss_active) {
++ gen_step_complete_exception(dc);
+ } else {
+ gen_exception_internal(EXCP_DEBUG);
+ }
+@@ -11090,7 +11159,10 @@ static inline void gen_intermediate_code_internal(ARMCPU *cpu,
+ }
+ gen_set_condexec(dc);
+ if (dc->is_jmp == DISAS_SWI && !dc->condjmp) {
++ gen_ss_advance(dc);
+ gen_exception(EXCP_SWI, syn_aa32_svc(dc->svc_imm, dc->thumb));
++ } else if (dc->ss_active) {
++ gen_step_complete_exception(dc);
+ } else {
+ /* FIXME: Single stepping a WFI insn will not halt
+ the CPU. */
+--
+2.1.1.273.g97b8860
+
diff --git a/meta/recipes-devtools/qemu/qemu/0011-target-arm-Implement-MDSCR_EL1-as-having-state.patch b/meta/recipes-devtools/qemu/qemu/0011-target-arm-Implement-MDSCR_EL1-as-having-state.patch
new file mode 100644
index 0000000..28c76ad
--- /dev/null
+++ b/meta/recipes-devtools/qemu/qemu/0011-target-arm-Implement-MDSCR_EL1-as-having-state.patch
@@ -0,0 +1,36 @@
+From 0e5e8935bb93e80bb95dc79f51f5bf874ba2ab99 Mon Sep 17 00:00:00 2001
+From: Peter Maydell <peter.maydell@linaro.org>
+Date: Tue, 19 Aug 2014 18:56:27 +0100
+Subject: [PATCH 11/11] target-arm: Implement MDSCR_EL1 as having state
+
+Now that all the new code to support single-stepping is in
+place, wire up the guest-visible MDSCR_EL1, so the guest
+can enable single-stepping.
+
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
+
+Upstream-Status: Backport
+Signed-off-by: Kai Kang <kai.kang@windriver.com>
+---
+ target-arm/helper.c | 4 +++-
+ 1 file changed, 3 insertions(+), 1 deletion(-)
+
+diff --git a/target-arm/helper.c b/target-arm/helper.c
+index f981569..2a77c97 100644
+--- a/target-arm/helper.c
++++ b/target-arm/helper.c
+@@ -2204,7 +2204,9 @@ static const ARMCPRegInfo debug_cp_reginfo[] = {
+ */
+ { .name = "MDSCR_EL1", .state = ARM_CP_STATE_BOTH,
+ .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2,
+- .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
++ .access = PL1_RW,
++ .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1),
++ .resetvalue = 0 },
+ /* We define a dummy WI OSLAR_EL1, because Linux writes to it. */
+ { .name = "OSLAR_EL1", .state = ARM_CP_STATE_BOTH,
+ .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 4,
+--
+2.1.1.273.g97b8860
+
diff --git a/meta/recipes-devtools/qemu/qemu_2.1.2.bb b/meta/recipes-devtools/qemu/qemu_2.1.2.bb
index 0e20605..46ee897 100644
--- a/meta/recipes-devtools/qemu/qemu_2.1.2.bb
+++ b/meta/recipes-devtools/qemu/qemu_2.1.2.bb
@@ -6,7 +6,18 @@ LIC_FILES_CHKSUM = "file://COPYING;md5=441c28d2cf86e15a37fa47e15a72fbac \
SRC_URI += "file://configure-fix-Darwin-target-detection.patch \
file://qemu-enlarge-env-entry-size.patch \
file://Qemu-Arm-versatilepb-Add-memory-size-checking.patch \
- "
+ file://0001-target-arm-Collect-up-the-debug-cp-register-definiti.patch \
+ file://0002-target-arm-Allow-STATE_BOTH-reginfo-descriptions-for.patch \
+ file://0003-target-arm-Provide-both-32-and-64-bit-versions-of-de.patch \
+ file://0004-target-arm-Adjust-debug-ID-registers-per-CPU.patch \
+ file://0005-target-arm-Don-t-allow-AArch32-to-access-RES0-CPSR-b.patch \
+ file://0006-target-arm-Correctly-handle-PSTATE.SS-when-taking-ex.patch \
+ file://0007-target-arm-Set-PSTATE.SS-correctly-on-exception-retu.patch \
+ file://0008-target-arm-A64-Avoid-duplicate-exit_tb-0-in-non-link.patch \
+ file://0009-target-arm-Implement-ARMv8-single-step-handling-for-.patch \
+ file://0010-target-arm-Implement-ARMv8-single-stepping-for-AArch.patch \
+ file://0011-target-arm-Implement-MDSCR_EL1-as-having-state.patch \
+ "
SRC_URI_prepend = "http://wiki.qemu-project.org/download/${BP}.tar.bz2"
SRC_URI[md5sum] = "0ff197c4ed4b695620bc4734e77c888f"
SRC_URI[sha256sum] = "fd10f5e45cf5a736fa5a3e1c279ae9821534e700beb7d1aab88a07648a394885"
--
1.9.1
^ permalink raw reply related [flat|nested] 51+ messages in thread* Re: [PATCH 17/24] qemu: add single step support for aarch64
2014-11-07 8:51 ` [PATCH 17/24] qemu: add single step support " Kai Kang
@ 2014-12-08 20:53 ` Burton, Ross
2014-12-09 1:53 ` Kang Kai
0 siblings, 1 reply; 51+ messages in thread
From: Burton, Ross @ 2014-12-08 20:53 UTC (permalink / raw)
To: Kai Kang; +Cc: Koen Kooi, OE-core
[-- Attachment #1: Type: text/plain, Size: 222 bytes --]
On 7 November 2014 at 08:51, Kai Kang <kai.kang@windriver.com> wrote:
> Backport patches to enable signle-step support for aarch64.
>
As these are all related, can they be concatenated into a single patch?
Ross
[-- Attachment #2: Type: text/html, Size: 634 bytes --]
^ permalink raw reply [flat|nested] 51+ messages in thread
* Re: [PATCH 17/24] qemu: add single step support for aarch64
2014-12-08 20:53 ` Burton, Ross
@ 2014-12-09 1:53 ` Kang Kai
0 siblings, 0 replies; 51+ messages in thread
From: Kang Kai @ 2014-12-09 1:53 UTC (permalink / raw)
To: Burton, Ross; +Cc: Koen Kooi, OE-core
On 2014年12月09日 04:53, Burton, Ross wrote:
> On 7 November 2014 at 08:51, Kai Kang <kai.kang@windriver.com> wrote:
>
>> Backport patches to enable signle-step support for aarch64.
>>
> As these are all related, can they be concatenated into a single patch?
OK if you think that is better. I'll update it.
--Kai
>
> Ross
>
--
Regards,
Neil | Kai Kang
^ permalink raw reply [flat|nested] 51+ messages in thread
* [PATCH 18/24] Revert "gcc-4.9: redefine default library install directory"
2014-11-07 8:51 [PATCH 00/24] V2: Add machine qemuarm64 Kai Kang
` (16 preceding siblings ...)
2014-11-07 8:51 ` [PATCH 17/24] qemu: add single step support " Kai Kang
@ 2014-11-07 8:51 ` Kai Kang
2014-11-07 8:51 ` [PATCH 19/24] gcc: Disable aarch64 multilib options Kai Kang
` (7 subsequent siblings)
25 siblings, 0 replies; 51+ messages in thread
From: Kai Kang @ 2014-11-07 8:51 UTC (permalink / raw)
To: ross.burton; +Cc: koen.kooi, openembedded-core
This reverts commit 208c5e37f98cd98629bad0562fbbc77d7b71e8ff.
GCC can choose the right value as defined by the system, it's the libc
that needs to know how to get to the ABI specific version of the dynamic
loader. Which is in /lib even if aarch64 libraries are installed in
lib64 due to the specifications in the ABI.
Signed-off-by: Mark Hatle <mark.hatle@windriver.com>
Signed-off-by: Kai Kang <kai.kang@windriver.com>
---
meta/recipes-devtools/gcc/gcc-4.9.inc | 1 -
...0099-gcc-redefine-library-dir-for-aarch64.patch | 29 ----------------------
2 files changed, 30 deletions(-)
delete mode 100644 meta/recipes-devtools/gcc/gcc-4.9/0099-gcc-redefine-library-dir-for-aarch64.patch
diff --git a/meta/recipes-devtools/gcc/gcc-4.9.inc b/meta/recipes-devtools/gcc/gcc-4.9.inc
index e3775cd..8f212b2 100644
--- a/meta/recipes-devtools/gcc/gcc-4.9.inc
+++ b/meta/recipes-devtools/gcc/gcc-4.9.inc
@@ -73,7 +73,6 @@ SRC_URI = "\
file://0056-top-level-reorder_gcc-bug-61144.patch \
file://0058-gcc-r212171.patch \
file://0059-gcc-PR-rtl-optimization-63348.patch \
- file://0099-gcc-redefine-library-dir-for-aarch64.patch \
"
SRC_URI[md5sum] = "fddf71348546af523353bd43d34919c1"
SRC_URI[sha256sum] = "d334781a124ada6f38e63b545e2a3b8c2183049515a1abab6d513f109f1d717e"
diff --git a/meta/recipes-devtools/gcc/gcc-4.9/0099-gcc-redefine-library-dir-for-aarch64.patch b/meta/recipes-devtools/gcc/gcc-4.9/0099-gcc-redefine-library-dir-for-aarch64.patch
deleted file mode 100644
index 23cdb95..0000000
--- a/meta/recipes-devtools/gcc/gcc-4.9/0099-gcc-redefine-library-dir-for-aarch64.patch
+++ /dev/null
@@ -1,29 +0,0 @@
-Redefine default library directory for aarch64.
-
-Packages use 'aarch64-poky-linux-gcc -print-multi-os-directory' to get the
-value of install directory. The value is set by MULTILIB_OSDIRNAMES and default
-is '/lib64'. Add the dynamic linker ld-linux-aarch64.so.1 from package eglibc
-is installed to /lib64.
-
-But the default dynamic linker defined in gcc/config/aarch64/aarch64-linux.h
-is:
-
-#define GLIBC_DYNAMIC_LINKER "/lib/ld-linux-aarch64%{mbig-endian:_be}.so.1"
-
-Then cause all the ELF files fail to launch because fail to find the linker.
-
-Upstream-Status: Pending
-
-Signed-off-by: Kai Kang <kai.kang@windriver.com>
----
---- gcc-4.9.1/gcc/config/aarch64/t-aarch64-linux.orig 2014-09-19 14:38:47.550669143 +0800
-+++ gcc-4.9.1/gcc/config/aarch64/t-aarch64-linux 2014-09-19 14:39:01.234669516 +0800
-@@ -22,7 +22,7 @@
- LIB1ASMFUNCS = _aarch64_sync_cache_range
-
- AARCH_BE = $(if $(findstring TARGET_BIG_ENDIAN_DEFAULT=1, $(tm_defines)),_be)
--MULTILIB_OSDIRNAMES = .=../lib64$(call if_multiarch,:aarch64$(AARCH_BE)-linux-gnu)
-+MULTILIB_OSDIRNAMES = .=../lib$(call if_multiarch,:aarch64$(AARCH_BE)-linux-gnu)
- MULTIARCH_DIRNAME = $(call if_multiarch,aarch64$(AARCH_BE)-linux-gnu)
-
- # Disable the multilib for linux-gnu targets for the time being; focus
--
1.9.1
^ permalink raw reply related [flat|nested] 51+ messages in thread* [PATCH 19/24] gcc: Disable aarch64 multilib options
2014-11-07 8:51 [PATCH 00/24] V2: Add machine qemuarm64 Kai Kang
` (17 preceding siblings ...)
2014-11-07 8:51 ` [PATCH 18/24] Revert "gcc-4.9: redefine default library install directory" Kai Kang
@ 2014-11-07 8:51 ` Kai Kang
2014-12-08 20:52 ` Burton, Ross
2014-11-07 8:51 ` [PATCH 20/24] glibc-package: aarch64 enable symlink for ABI compliance Kai Kang
` (6 subsequent siblings)
25 siblings, 1 reply; 51+ messages in thread
From: Kai Kang @ 2014-11-07 8:51 UTC (permalink / raw)
To: ross.burton; +Cc: koen.kooi, openembedded-core
From: Mark Hatle <mark.hatle@windriver.com>
We want to revert to default gcc behavior to support oe-core's ability
to change the libdir.
Signed-off-by: Mark Hatle <mark.hatle@windriver.com>
---
meta/recipes-devtools/gcc/gcc-4.9.inc | 1 +
.../gcc/gcc-4.9/0057-aarch64-config.patch | 32 ++++++++++++++++++++++
2 files changed, 33 insertions(+)
create mode 100644 meta/recipes-devtools/gcc/gcc-4.9/0057-aarch64-config.patch
diff --git a/meta/recipes-devtools/gcc/gcc-4.9.inc b/meta/recipes-devtools/gcc/gcc-4.9.inc
index 8f212b2..2568e99 100644
--- a/meta/recipes-devtools/gcc/gcc-4.9.inc
+++ b/meta/recipes-devtools/gcc/gcc-4.9.inc
@@ -71,6 +71,7 @@ SRC_URI = "\
file://0054-gcc-Makefile.in-fix-parallel-building-failure.patch \
file://0055-PR-rtl-optimization-61801.patch \
file://0056-top-level-reorder_gcc-bug-61144.patch \
+ file://0057-aarch64-config.patch \
file://0058-gcc-r212171.patch \
file://0059-gcc-PR-rtl-optimization-63348.patch \
"
diff --git a/meta/recipes-devtools/gcc/gcc-4.9/0057-aarch64-config.patch b/meta/recipes-devtools/gcc/gcc-4.9/0057-aarch64-config.patch
new file mode 100644
index 0000000..f295596
--- /dev/null
+++ b/meta/recipes-devtools/gcc/gcc-4.9/0057-aarch64-config.patch
@@ -0,0 +1,32 @@
+Disable the MULTILIB_OSDIRNAMES and other multilib options.
+
+Hard coding the MULTILIB_OSDIRNAMES with ../lib64 is causing problems on
+systems where the libdir is NOT set to /lib64. This is allowed by the ABI, as
+long as the dynamic loader is present in /lib.
+
+We simply want to use the default rules in gcc to find and configure the
+normal libdir.
+
+Signed-off-by: Mark Hatle <mark.hatle@windriver.com>
+
+Index: gcc-4.9.1/gcc/config/aarch64/t-aarch64-linux
+===================================================================
+--- gcc-4.9.1.orig/gcc/config/aarch64/t-aarch64-linux
++++ gcc-4.9.1/gcc/config/aarch64/t-aarch64-linux
+@@ -21,11 +21,11 @@
+ LIB1ASMSRC = aarch64/lib1funcs.asm
+ LIB1ASMFUNCS = _aarch64_sync_cache_range
+
+-AARCH_BE = $(if $(findstring TARGET_BIG_ENDIAN_DEFAULT=1, $(tm_defines)),_be)
+-MULTILIB_OSDIRNAMES = .=../lib64$(call if_multiarch,:aarch64$(AARCH_BE)-linux-gnu)
+-MULTIARCH_DIRNAME = $(call if_multiarch,aarch64$(AARCH_BE)-linux-gnu)
++#AARCH_BE = $(if $(findstring TARGET_BIG_ENDIAN_DEFAULT=1, $(tm_defines)),_be)
++#MULTILIB_OSDIRNAMES = .=../lib64$(call if_multiarch,:aarch64$(AARCH_BE)-linux-gnu)
++#MULTIARCH_DIRNAME = $(call if_multiarch,aarch64$(AARCH_BE)-linux-gnu)
+
+ # Disable the multilib for linux-gnu targets for the time being; focus
+ # on the baremetal targets.
+-MULTILIB_OPTIONS =
+-MULTILIB_DIRNAMES =
++#MULTILIB_OPTIONS =
++#MULTILIB_DIRNAMES =
--
1.9.1
^ permalink raw reply related [flat|nested] 51+ messages in thread* Re: [PATCH 19/24] gcc: Disable aarch64 multilib options
2014-11-07 8:51 ` [PATCH 19/24] gcc: Disable aarch64 multilib options Kai Kang
@ 2014-12-08 20:52 ` Burton, Ross
2014-12-09 1:54 ` Kang Kai
0 siblings, 1 reply; 51+ messages in thread
From: Burton, Ross @ 2014-12-08 20:52 UTC (permalink / raw)
To: Kai Kang; +Cc: Koen Kooi, OE-core
[-- Attachment #1: Type: text/plain, Size: 582 bytes --]
On 7 November 2014 at 08:51, Kai Kang <kai.kang@windriver.com> wrote:
> +Disable the MULTILIB_OSDIRNAMES and other multilib options.
> +
> +Hard coding the MULTILIB_OSDIRNAMES with ../lib64 is causing problems on
> +systems where the libdir is NOT set to /lib64. This is allowed by the
> ABI, as
> +long as the dynamic loader is present in /lib.
> +
> +We simply want to use the default rules in gcc to find and configure the
> +normal libdir.
> +
> +Signed-off-by: Mark Hatle <mark.hatle@windriver.com>
>
This patch is missing an Upstream-Status header.
Ross
[-- Attachment #2: Type: text/html, Size: 1127 bytes --]
^ permalink raw reply [flat|nested] 51+ messages in thread
* Re: [PATCH 19/24] gcc: Disable aarch64 multilib options
2014-12-08 20:52 ` Burton, Ross
@ 2014-12-09 1:54 ` Kang Kai
0 siblings, 0 replies; 51+ messages in thread
From: Kang Kai @ 2014-12-09 1:54 UTC (permalink / raw)
To: Burton, Ross; +Cc: Koen Kooi, OE-core
On 2014年12月09日 04:52, Burton, Ross wrote:
> On 7 November 2014 at 08:51, Kai Kang <kai.kang@windriver.com> wrote:
>
>> +Disable the MULTILIB_OSDIRNAMES and other multilib options.
>> +
>> +Hard coding the MULTILIB_OSDIRNAMES with ../lib64 is causing problems on
>> +systems where the libdir is NOT set to /lib64. This is allowed by the
>> ABI, as
>> +long as the dynamic loader is present in /lib.
>> +
>> +We simply want to use the default rules in gcc to find and configure the
>> +normal libdir.
>> +
>> +Signed-off-by: Mark Hatle <mark.hatle@windriver.com>
>>
> This patch is missing an Upstream-Status header.
Thanks. I'll update it.
--Kai
>
> Ross
>
--
Regards,
Neil | Kai Kang
^ permalink raw reply [flat|nested] 51+ messages in thread
* [PATCH 20/24] glibc-package: aarch64 enable symlink for ABI compliance
2014-11-07 8:51 [PATCH 00/24] V2: Add machine qemuarm64 Kai Kang
` (18 preceding siblings ...)
2014-11-07 8:51 ` [PATCH 19/24] gcc: Disable aarch64 multilib options Kai Kang
@ 2014-11-07 8:51 ` Kai Kang
2014-11-07 8:51 ` [PATCH 21/24] aarch-arm64: Update tune files Kai Kang
` (5 subsequent siblings)
25 siblings, 0 replies; 51+ messages in thread
From: Kai Kang @ 2014-11-07 8:51 UTC (permalink / raw)
To: ross.burton; +Cc: koen.kooi, openembedded-core
From: Mark Hatle <mark.hatle@windriver.com>
aarch64 requires the ld.so to be present in /lib, even if the rest
of the libraries are installed into an alternative directory.
See: https://sourceware.org/glibc/wiki/ABIList
Signed-off-by: Mark Hatle <mark.hatle@windriver.com>
---
meta/recipes-core/glibc/glibc-package.inc | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/meta/recipes-core/glibc/glibc-package.inc b/meta/recipes-core/glibc/glibc-package.inc
index 6212e5b..984362e 100644
--- a/meta/recipes-core/glibc/glibc-package.inc
+++ b/meta/recipes-core/glibc/glibc-package.inc
@@ -32,6 +32,8 @@ RPROVIDES_glibc-thread-db = "eglibc-thread-db"
RPROVIDES_${PN}-pcprofile = "eglibc-pcprofile"
RPROVIDES_${PN}-dbg = "eglibc-dbg"
libc_baselibs = "${base_libdir}/libcrypt*.so.* ${base_libdir}/libcrypt-*.so ${base_libdir}/libc.so.* ${base_libdir}/libc-*.so ${base_libdir}/libm*.so.* ${base_libdir}/libm-*.so ${base_libdir}/ld*.so.* ${base_libdir}/ld-*.so ${base_libdir}/libpthread*.so.* ${base_libdir}/libpthread-*.so ${base_libdir}/libresolv*.so.* ${base_libdir}/libresolv-*.so ${base_libdir}/librt*.so.* ${base_libdir}/librt-*.so ${base_libdir}/libutil*.so.* ${base_libdir}/libutil-*.so ${base_libdir}/libnsl*.so.* ${base_libdir}/libnsl-*.so ${base_libdir}/libnss_files*.so.* ${base_libdir}/libnss_files-*.so ${base_libdir}/libnss_compat*.so.* ${base_libdir}/libnss_compat-*.so ${base_libdir}/libnss_dns*.so.* ${base_libdir}/libnss_dns-*.so ${base_libdir}/libdl*.so.* ${base_libdir}/libdl-*.so ${base_libdir}/libanl*.so.* ${base_libdir}/libanl-*.so ${base_libdir}/libBrokenLocale*.so.* ${base_libdir}/libBrokenLocale-*.so"
+libc_baselibs_append_aarch64 = " /lib/ld-linux-aarch64*.so.1"
+INSANE_SKIP_glibc_append_aarch64 = " libdir"
FILES_${PN} = "${libc_baselibs} ${libexecdir}/* ${@base_conditional('USE_LDCONFIG', '1', '${base_sbindir}/ldconfig ${sysconfdir}/ld.so.conf', '', d)}"
FILES_ldd = "${bindir}/ldd"
@@ -103,6 +105,20 @@ do_install_append () {
fi
}
+do_install_append_aarch64 () {
+ if [ "${base_libdir}" != "/lib" ] ; then
+ # The aarch64 ABI says the dynamic linker -must- be /lib/ld-linux-aarch64[_be].so.1
+ install -d ${D}/lib
+ if [ -e ${D}${base_libdir}/ld-linux-aarch64.so.1 ]; then
+ ln -s ${@base_path_relative('/lib', '${base_libdir}')}/ld-linux-aarch64.so.1 \
+ ${D}/lib/ld-linux-aarch64.so.1
+ elif [ -e ${D}${base_libdir}/ld-linux-aarch64_be.so.1 ]; then
+ ln -s ${@base_path_relative('/lib', '${base_libdir}')}/ld-linux-aarch64_be.so.1 \
+ ${D}/lib/ld-linux-aarch64_be.so.1
+ fi
+ fi
+}
+
do_install_locale () {
dest=${D}/${includedir}/glibc-locale-internal-${MULTIMACH_TARGET_SYS}
install -d ${dest}${base_libdir} ${dest}${bindir} ${dest}${libdir} ${dest}${datadir}
--
1.9.1
^ permalink raw reply related [flat|nested] 51+ messages in thread* [PATCH 21/24] aarch-arm64: Update tune files
2014-11-07 8:51 [PATCH 00/24] V2: Add machine qemuarm64 Kai Kang
` (19 preceding siblings ...)
2014-11-07 8:51 ` [PATCH 20/24] glibc-package: aarch64 enable symlink for ABI compliance Kai Kang
@ 2014-11-07 8:51 ` Kai Kang
2014-11-07 8:51 ` [PATCH 22/24] linux-yocto: Fixup linux-yocto for aarch64 Kai Kang
` (4 subsequent siblings)
25 siblings, 0 replies; 51+ messages in thread
From: Kai Kang @ 2014-11-07 8:51 UTC (permalink / raw)
To: ross.burton; +Cc: koen.kooi, openembedded-core
From: Mark Hatle <mark.hatle@windriver.com>
arch-arm64 is the base tune file for aarch64. Update this to allow the
system to work with both aarch32 and aarch64 (multilib).
arch-armv8 is for compatibility, it simply uses the base config for now.
feature-arm-thumb was updated, since aarch64 mode does NOT have thumb support.
We should only be processing warnings and additional arguments if thumb
support is enabled on the processor core.
Signed-off-by: Mark Hatle <mark.hatle@windriver.com>
---
meta/conf/machine/include/arm/arch-arm64.inc | 36 ++++++++++++++++++++++
meta/conf/machine/include/arm/arch-armv8.inc | 21 +------------
.../conf/machine/include/arm/feature-arm-thumb.inc | 10 ++++--
3 files changed, 44 insertions(+), 23 deletions(-)
create mode 100644 meta/conf/machine/include/arm/arch-arm64.inc
diff --git a/meta/conf/machine/include/arm/arch-arm64.inc b/meta/conf/machine/include/arm/arch-arm64.inc
new file mode 100644
index 0000000..5376b87
--- /dev/null
+++ b/meta/conf/machine/include/arm/arch-arm64.inc
@@ -0,0 +1,36 @@
+DEFAULTTUNE ?= "aarch64"
+
+require conf/machine/include/arm/arch-armv7a.inc
+
+TUNEVALID[aarch64] = "Enable instructions for aarch64"
+
+MACHINEOVERRIDES .= "${@bb.utils.contains("TUNE_FEATURES", "aarch64", ":aarch64", "" ,d)}"
+
+# Little Endian base configs
+AVAILTUNES += "aarch64 aarch64_be"
+ARMPKGARCH_tune-aarch64 ?= "aarch64"
+ARMPKGARCH_tune-aarch64_be ?= "aarch64_be"
+TUNE_FEATURES_tune-aarch64 ?= "aarch64"
+TUNE_FEATURES_tune-aarch64_be ?= "${TUNE_FEATURES_tune-aarch64} bigendian"
+BASE_LIB_tune-aarch64 = "lib64"
+BASE_LIB_tune-aarch64_be = "lib64"
+
+PACKAGE_EXTRA_ARCHS_tune-aarch64 = "aarch64"
+PACKAGE_EXTRA_ARCHS_tune-aarch64_be = "aarch64_be"
+
+ARMPKGSFX_ENDIAN_64 = "${@bb.utils.contains("TUNE_FEATURES", "bigendian", "_be", "", d)}"
+TUNE_ARCH_64 = "aarch64${ARMPKGSFX_ENDIAN_64}"
+TUNE_PKGARCH_64 = "aarch64${ARMPKGSFX_ENDIAN_64}"
+ABIEXTENSION_64 = ""
+TARGET_FPU_64 = ""
+
+# Duplicated from arch-arm.inc
+TUNE_ARCH_32 = "${@bb.utils.contains("TUNE_FEATURES", "bigendian", "armeb", "arm", d)}"
+TUNE_PKGARCH_32 = "${ARMPKGARCH}${ARMPKGSFX_THUMB}${ARMPKGSFX_DSP}${ARMPKGSFX_EABI}${ARMPKGSFX_ENDIAN}${ARMPKGSFX_FPU}"
+ABIEXTENSION_32 = "eabi"
+TARGET_FPU_32 = "${@d.getVar('ARMPKGSFX_FPU', True).strip('-') or 'soft'}"
+
+TUNE_ARCH = "${@bb.utils.contains("TUNE_FEATURES", "aarch64", "${TUNE_ARCH_64}", "${TUNE_ARCH_32}" ,d)}"
+TUNE_PKGARCH = "${@bb.utils.contains("TUNE_FEATURES", "aarch64", "${TUNE_PKGARCH_64}", "${TUNE_PKGARCH_32}" ,d)}"
+ABIEXTENSION = "${@bb.utils.contains("TUNE_FEATURES", "aarch64", "${ABIEXTENSION_64}", "${ABIEXTENSION_32}" ,d)}"
+TARGET_FPU = "${@bb.utils.contains("TUNE_FEATURES", "aarch64", "${TARGET_FPU_64}", "${TARGET_FPU_32}" ,d)}"
diff --git a/meta/conf/machine/include/arm/arch-armv8.inc b/meta/conf/machine/include/arm/arch-armv8.inc
index c86142a..5e832fa 100644
--- a/meta/conf/machine/include/arm/arch-armv8.inc
+++ b/meta/conf/machine/include/arm/arch-armv8.inc
@@ -1,20 +1 @@
-DEFAULTTUNE ?= "aarch64"
-
-ARMPKGARCH ?= "aarch64"
-
-TUNEVALID[aarch64] = "Enable instructions for aarch64"
-TUNEVALID[bigendian] = "Enable big-endian mode."
-TUNECONFLICTS[aarch64] = ""
-MACHINEOVERRIDES .= "${@bb.utils.contains("TUNE_FEATURES", "aarch64", ":aarch64", "" ,d)}"
-
-# Little Endian base configs
-AVAILTUNES += "aarch64 aarch64_be"
-TUNE_FEATURES_tune-aarch64 ?= "aarch64"
-TUNE_FEATURES_tune-aarch64_be ?= "${TUNE_FEATURES_tune-aarch64} bigendian"
-
-ARMPKGSFX_ENDIAN = "${@bb.utils.contains("TUNE_FEATURES", "bigendian", "_be", "", d)}"
-
-TUNE_ARCH = "aarch64${ARMPKGSFX_ENDIAN}"
-TUNE_PKGARCH = "aarch64${ARMPKGSFX_ENDIAN}"
-
-PACKAGE_EXTRA_ARCHS = "aarch64${ARMPKGSFX_ENDIAN}"
+require conf/machine/include/arm/arch-arm64.inc
diff --git a/meta/conf/machine/include/arm/feature-arm-thumb.inc b/meta/conf/machine/include/arm/feature-arm-thumb.inc
index a94386f..8e6619d 100644
--- a/meta/conf/machine/include/arm/feature-arm-thumb.inc
+++ b/meta/conf/machine/include/arm/feature-arm-thumb.inc
@@ -18,6 +18,8 @@ ARM_THUMB_SUFFIX .= "${@bb.utils.contains('TUNE_FEATURES', 'armv7m', 't2', '', d
# some recipe explicitly sets ARM_INSTRUCTION_SET to "arm"
ARM_M_OPT = "${@bb.utils.contains('TUNE_FEATURES', 'arm', '${ARM_THUMB_OPT}', 'thumb', d)}"
python () {
+ if bb.utils.contains('TUNE_FEATURES', 'thumb', 'False', 'True', d):
+ return
selected = d.getVar('ARM_INSTRUCTION_SET', True)
if selected == None:
return
@@ -37,8 +39,10 @@ ARMPKGSFX_THUMB .= "${@bb.utils.contains('TUNE_FEATURES', 'thumb', '${ARM_THUMB_
# arm system and vice versa. It is strongly recommended that DISTROs not
# turn this off - the actual cost is very small.
TUNEVALID[no-thumb-interwork] = "Disable mixing of thumb and ARM functions"
-TUNE_CCARGS .= "${@bb.utils.contains('TUNE_FEATURES', 'no-thumb-interwork', ' -mno-thumb-interwork', ' -mthumb-interwork', d)}"
-OVERRIDES .= "${@bb.utils.contains('TUNE_FEATURES', 'no-thumb-interwork', ':thumb-interwork', '', d)}"
+THUMB_TUNE_CCARGS .= "${@bb.utils.contains('TUNE_FEATURES', 'no-thumb-interwork', ' -mno-thumb-interwork', ' -mthumb-interwork', d)}"
+THUMB_OVERRIDES .= "${@bb.utils.contains('TUNE_FEATURES', 'no-thumb-interwork', ':thumb-interwork', '', d)}"
+TUNE_CCARGS .= "${@bb.utils.contains('TUNE_FEATURES', 'thumb', ' ${THUMB_TUNE_CCARGS}', '', d)}"
+OVERRIDES .= "${@bb.utils.contains('TUNE_FEATURES', 'thumb', ' ${THUMB_OVERRIDES}', '', d)}"
# what about armv7m devices which don't support -marm (e.g. Cortex-M3)?
-TARGET_CC_KERNEL_ARCH += "-mno-thumb-interwork -marm"
+TARGET_CC_KERNEL_ARCH += "${@bb.utils.contains('TUNE_FEATURES', 'thumb', '-mno-thumb-interwork -marm', '', d)}"
--
1.9.1
^ permalink raw reply related [flat|nested] 51+ messages in thread* [PATCH 22/24] linux-yocto: Fixup linux-yocto for aarch64
2014-11-07 8:51 [PATCH 00/24] V2: Add machine qemuarm64 Kai Kang
` (20 preceding siblings ...)
2014-11-07 8:51 ` [PATCH 21/24] aarch-arm64: Update tune files Kai Kang
@ 2014-11-07 8:51 ` Kai Kang
2014-11-07 8:51 ` [PATCH 23/24] local.conf.sample: Add qemuarm64 Kai Kang
` (3 subsequent siblings)
25 siblings, 0 replies; 51+ messages in thread
From: Kai Kang @ 2014-11-07 8:51 UTC (permalink / raw)
To: ross.burton; +Cc: koen.kooi, openembedded-core
From: Mark Hatle <mark.hatle@windriver.com>
linux-yocto is updated to pass the sysroot path to the compiler when necessary.
linux-yocto_ver.bb are updated to reference the correct linux-yocto branchs and
SRCREVs.
Signed-off-by: Mark Hatle <mark.hatle@windriver.com>
Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com
---
meta/recipes-kernel/linux/linux-yocto.inc | 2 ++
meta/recipes-kernel/linux/linux-yocto_3.14.bb | 4 +++-
meta/recipes-kernel/linux/linux-yocto_3.17.bb | 4 +++-
3 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/meta/recipes-kernel/linux/linux-yocto.inc b/meta/recipes-kernel/linux/linux-yocto.inc
index 9018985..7416af9 100644
--- a/meta/recipes-kernel/linux/linux-yocto.inc
+++ b/meta/recipes-kernel/linux/linux-yocto.inc
@@ -8,6 +8,8 @@ INC_PR = "r4"
DEPENDS += "xz-native bc-native"
DEPENDS_append_aarch64 = " libgcc"
+KERNEL_CC_append_aarch64 = " ${TOOLCHAIN_OPTIONS}"
+KERNEL_LD_append_aarch64 = " ${TOOLCHAIN_OPTIONS}"
# A KMACHINE is the mapping of a yocto $MACHINE to what is built
# by the kernel. This is typically the branch that should be built,
diff --git a/meta/recipes-kernel/linux/linux-yocto_3.14.bb b/meta/recipes-kernel/linux/linux-yocto_3.14.bb
index a2f4b4d..2213884 100644
--- a/meta/recipes-kernel/linux/linux-yocto_3.14.bb
+++ b/meta/recipes-kernel/linux/linux-yocto_3.14.bb
@@ -4,6 +4,7 @@ require recipes-kernel/linux/linux-yocto.inc
# board specific branches
KBRANCH_qemuarm ?= "standard/arm-versatile-926ejs"
+KBRANCH_qemuarm64 ?= "standard/qemuarm64"
KBRANCH_qemumips ?= "standard/mti-malta32"
KBRANCH_qemuppc ?= "standard/qemuppc"
KBRANCH_qemux86 ?= "standard/common-pc/base"
@@ -11,6 +12,7 @@ KBRANCH_qemux86-64 ?= "standard/common-pc-64/base"
KBRANCH_qemumips64 ?= "standard/mti-malta64"
SRCREV_machine_qemuarm ?= "127b621f2a4d3b1111e24423c12fac001e047c1c"
+SRCREV_machine_qemuarm64 ?= "902f34d36102a4b2008b776ecae686f80d307e12"
SRCREV_machine_qemumips ?= "c3b9f1b2397f0847ab4844d1cdb8e02574434d78"
SRCREV_machine_qemuppc ?= "73e2411cdd91764d0601c0869857f53381c2a177"
SRCREV_machine_qemux86 ?= "e19a1b40de44e756defdfb40349342d8037609bd"
@@ -27,7 +29,7 @@ PV = "${LINUX_VERSION}+git${SRCPV}"
KMETA = "meta"
-COMPATIBLE_MACHINE = "qemuarm|qemux86|qemuppc|qemumips|qemumips64|qemux86-64"
+COMPATIBLE_MACHINE = "qemuarm|qemuarm64|qemux86|qemuppc|qemumips|qemumips64|qemux86-64"
# Functionality flags
KERNEL_EXTRA_FEATURES ?= "features/netfilter/netfilter.scc"
diff --git a/meta/recipes-kernel/linux/linux-yocto_3.17.bb b/meta/recipes-kernel/linux/linux-yocto_3.17.bb
index 3838dbf..15c9b24 100644
--- a/meta/recipes-kernel/linux/linux-yocto_3.17.bb
+++ b/meta/recipes-kernel/linux/linux-yocto_3.17.bb
@@ -4,6 +4,7 @@ require recipes-kernel/linux/linux-yocto.inc
# board specific branches
KBRANCH_qemuarm ?= "standard/arm-versatile-926ejs"
+KBRANCH_qemuarm64 ?= "standard/qemuarm64"
KBRANCH_qemumips ?= "standard/mti-malta32"
KBRANCH_qemuppc ?= "standard/qemuppc"
KBRANCH_qemux86 ?= "standard/common-pc"
@@ -11,6 +12,7 @@ KBRANCH_qemux86-64 ?= "standard/common-pc-64/base"
KBRANCH_qemumips64 ?= "standard/mti-malta64"
SRCREV_machine_qemuarm ?= "e86f70699655d1f5bf2518c8dcdb949a39161c86"
+SRCREV_machine_qemuarm64 ?= "268b7677421eef003a84f31c6bd0b8ec3acc1e36"
SRCREV_machine_qemumips ?= "0acaa5991a61fbab0d897157049ac2e638e9c7bf"
SRCREV_machine_qemuppc ?= "50e33fec112527de12c2833cd8a283dd4a75ae33"
SRCREV_machine_qemux86 ?= "1a6dd1205de5b7c6135a42fec00550738ff777b5"
@@ -27,7 +29,7 @@ PV = "${LINUX_VERSION}+git${SRCPV}"
KMETA = "meta"
-COMPATIBLE_MACHINE = "qemuarm|qemux86|qemuppc|qemumips|qemumips64|qemux86-64"
+COMPATIBLE_MACHINE = "qemuarm|qemuarm64|qemux86|qemuppc|qemumips|qemumips64|qemux86-64"
# Functionality flags
KERNEL_EXTRA_FEATURES ?= "features/netfilter/netfilter.scc"
--
1.9.1
^ permalink raw reply related [flat|nested] 51+ messages in thread* [PATCH 23/24] local.conf.sample: Add qemuarm64
2014-11-07 8:51 [PATCH 00/24] V2: Add machine qemuarm64 Kai Kang
` (21 preceding siblings ...)
2014-11-07 8:51 ` [PATCH 22/24] linux-yocto: Fixup linux-yocto for aarch64 Kai Kang
@ 2014-11-07 8:51 ` Kai Kang
2014-11-07 8:51 ` [PATCH 24/24] poky.conf: Add support for aarch64 to QEMU Kai Kang
` (2 subsequent siblings)
25 siblings, 0 replies; 51+ messages in thread
From: Kai Kang @ 2014-11-07 8:51 UTC (permalink / raw)
To: ross.burton; +Cc: koen.kooi, openembedded-core
From: Mark Hatle <mark.hatle@windriver.com>
Add an example machine configuration for qemuarm64.
Signed-off-by: Mark Hatle <mark.hatle@windriver.com>
---
meta-yocto/conf/local.conf.sample | 1 +
1 file changed, 1 insertion(+)
diff --git a/meta-yocto/conf/local.conf.sample b/meta-yocto/conf/local.conf.sample
index 93c85c2..a1d99f9 100644
--- a/meta-yocto/conf/local.conf.sample
+++ b/meta-yocto/conf/local.conf.sample
@@ -18,6 +18,7 @@
# of emulated machines available which can boot and run in the QEMU emulator:
#
#MACHINE ?= "qemuarm"
+#MACHINE ?= "qemuarm64"
#MACHINE ?= "qemumips"
#MACHINE ?= "qemuppc"
#MACHINE ?= "qemux86"
--
1.9.1
^ permalink raw reply related [flat|nested] 51+ messages in thread* [PATCH 24/24] poky.conf: Add support for aarch64 to QEMU
2014-11-07 8:51 [PATCH 00/24] V2: Add machine qemuarm64 Kai Kang
` (22 preceding siblings ...)
2014-11-07 8:51 ` [PATCH 23/24] local.conf.sample: Add qemuarm64 Kai Kang
@ 2014-11-07 8:51 ` Kai Kang
2014-11-07 9:18 ` [PATCH 00/24] V2: Add machine qemuarm64 Koen Kooi
2014-11-07 11:01 ` Paul Barker
25 siblings, 0 replies; 51+ messages in thread
From: Kai Kang @ 2014-11-07 8:51 UTC (permalink / raw)
To: ross.burton; +Cc: koen.kooi, openembedded-core
From: Mark Hatle <mark.hatle@windriver.com>
Signed-off-by: Mark Hatle <mark.hatle@windriver.com>
---
meta-yocto/conf/distro/poky.conf | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/meta-yocto/conf/distro/poky.conf b/meta-yocto/conf/distro/poky.conf
index e1dfea4..9e22e54 100644
--- a/meta-yocto/conf/distro/poky.conf
+++ b/meta-yocto/conf/distro/poky.conf
@@ -44,7 +44,7 @@ DISTRO_EXTRA_RDEPENDS_append_qemux86-64 = " ${POKYQEMUDEPS}"
TCLIBCAPPEND = ""
-QEMU_TARGETS ?= "arm i386 mips mipsel ppc x86_64"
+QEMU_TARGETS ?= "arm aarch64 i386 mips mipsel ppc x86_64"
# Other QEMU_TARGETS "mips64 mips64el sh4"
PREMIRRORS ??= "\
--
1.9.1
^ permalink raw reply related [flat|nested] 51+ messages in thread* Re: [PATCH 00/24] V2: Add machine qemuarm64
2014-11-07 8:51 [PATCH 00/24] V2: Add machine qemuarm64 Kai Kang
` (23 preceding siblings ...)
2014-11-07 8:51 ` [PATCH 24/24] poky.conf: Add support for aarch64 to QEMU Kai Kang
@ 2014-11-07 9:18 ` Koen Kooi
2014-11-07 14:27 ` Mark Hatle
2014-11-07 11:01 ` Paul Barker
25 siblings, 1 reply; 51+ messages in thread
From: Koen Kooi @ 2014-11-07 9:18 UTC (permalink / raw)
To: Kai Kang; +Cc: Koen Kooi, openembedded-core
> Op 7 nov. 2014, om 09:51 heeft Kai Kang <kai.kang@windriver.com> het volgende geschreven:
>
> V2:
> * rebase on master and drop qemu upgrade commit
> * built for lib32-core-image-sato core-image-sato-sdk meta-toolchain and world
>
> V1:
> The original configuration files and tune fils for arm arch64 are from linaro.
> And we rename it to qemuarm64 for consistency.
Consistent to what? All current qemu machines are named after the qemu arch, so consistent would be 'qemuaarch64'. The 'arm64' moniker is *only* used in the kernel and that was caused by Linus being grumpy, everything else is 'aarch64' or 'armv8'
^ permalink raw reply [flat|nested] 51+ messages in thread* Re: [PATCH 00/24] V2: Add machine qemuarm64
2014-11-07 9:18 ` [PATCH 00/24] V2: Add machine qemuarm64 Koen Kooi
@ 2014-11-07 14:27 ` Mark Hatle
2014-11-13 15:04 ` Koen Kooi
0 siblings, 1 reply; 51+ messages in thread
From: Mark Hatle @ 2014-11-07 14:27 UTC (permalink / raw)
To: openembedded-core
On 11/7/14, 3:18 AM, Koen Kooi wrote:
>
>> Op 7 nov. 2014, om 09:51 heeft Kai Kang <kai.kang@windriver.com> het volgende geschreven:
>>
>> V2:
>> * rebase on master and drop qemu upgrade commit
>> * built for lib32-core-image-sato core-image-sato-sdk meta-toolchain and world
>>
>> V1:
>> The original configuration files and tune fils for arm arch64 are from linaro.
>> And we rename it to qemuarm64 for consistency.
>
> Consistent to what? All current qemu machines are named after the qemu arch, so consistent would be 'qemuaarch64'. The 'arm64' moniker is *only* used in the kernel and that was caused by Linus being grumpy, everything else is 'aarch64' or 'armv8'
>
The arm64 name -did- come from Linaro:
http://git.linaro.org/openembedded/meta-linaro.git/tree/HEAD:/meta-aarch64/conf/machine/include
The arch-armv8.inc file (that arch-arm64.inc was based on) is located in the
directly "arm64".
In addition, the tune file that forms the basis of the ARM tunes is called
'arch-arm.inc'. Not arch-aarch32.inc. If you want to rename that, we can
discuss it.. but to match that naming I chose 'arch-arm64.inc'.
(arch-armv8.inc was kept, but only includes the arch-arm64.inc file since there
are no custom optimizations for 'v8' that I can find.)
As far as the machine name goes the original Linaro version, genericarmv8.conf
and genericarmv8b.conf, don't match any of the naming conventions that are
currently used by QEMU BSPs.
Looking at the existing machine names:
qemuarm.conf qemumips64.conf qemumips.conf qemuppc.conf qemux86-64.conf
qemux86.conf
Each of the suffix names used match the Linux kernel arch naming.
So based on that reasoning the generic little endian machine was defined as
qemuarm64.conf.
--Mark
^ permalink raw reply [flat|nested] 51+ messages in thread
* Re: [PATCH 00/24] V2: Add machine qemuarm64
2014-11-07 14:27 ` Mark Hatle
@ 2014-11-13 15:04 ` Koen Kooi
0 siblings, 0 replies; 51+ messages in thread
From: Koen Kooi @ 2014-11-13 15:04 UTC (permalink / raw)
To: Mark Hatle
Cc: Steve McIntyre, Patches and discussions about the oe-core layer
CC:ing Steve M. from ARM who went through various arm naming issues for debian.
> Op 7 nov. 2014, om 15:27 heeft Mark Hatle <mark.hatle@windriver.com> het volgende geschreven:
>
> On 11/7/14, 3:18 AM, Koen Kooi wrote:
>>
>>> Op 7 nov. 2014, om 09:51 heeft Kai Kang <kai.kang@windriver.com> het volgende geschreven:
>>>
>>> V2:
>>> * rebase on master and drop qemu upgrade commit
>>> * built for lib32-core-image-sato core-image-sato-sdk meta-toolchain and world
>>>
>>> V1:
>>> The original configuration files and tune fils for arm arch64 are from linaro.
>>> And we rename it to qemuarm64 for consistency.
>>
>> Consistent to what? All current qemu machines are named after the qemu arch, so consistent would be 'qemuaarch64'. The 'arm64' moniker is *only* used in the kernel and that was caused by Linus being grumpy, everything else is 'aarch64' or 'armv8'
>>
>
> The arm64 name -did- come from Linaro:
>
> http://git.linaro.org/openembedded/meta-linaro.git/tree/HEAD:/meta-aarch64/conf/machine/include
>
> The arch-armv8.inc file (that arch-arm64.inc was based on) is located in the directly "arm64".
>
> In addition, the tune file that forms the basis of the ARM tunes is called 'arch-arm.inc'. Not arch-aarch32.inc. If you want to rename that, we can discuss it.. but to match that naming I chose 'arch-arm64.inc'.
'aarch32' is not the same as 'arm', the arch-arm.inc covers armv4..armv7a with it various includes. aarch32 is s subset of armv7a, so please don't use that to denote 32bit arms.
> (arch-armv8.inc was kept, but only includes the arch-arm64.inc file since there are no custom optimizations for 'v8' that I can find.)
>
> As far as the machine name goes the original Linaro version, genericarmv8.conf and genericarmv8b.conf, don't match any of the naming conventions that are currently used by QEMU BSPs.
>
> Looking at the existing machine names:
>
> qemuarm.conf qemumips64.conf qemumips.conf qemuppc.conf qemux86-64.conf qemux86.conf
>
> Each of the suffix names used match the Linux kernel arch naming.
It seems to be following the qemu architecture name, which tends to match the kernel arch name, but not always.
Apart from the naming issues, aarch64 support is incomplete in meta-aarch64 since things like ILP32 are missing as well as agreement over page size options.
^ permalink raw reply [flat|nested] 51+ messages in thread
* Re: [PATCH 00/24] V2: Add machine qemuarm64
2014-11-07 8:51 [PATCH 00/24] V2: Add machine qemuarm64 Kai Kang
` (24 preceding siblings ...)
2014-11-07 9:18 ` [PATCH 00/24] V2: Add machine qemuarm64 Koen Kooi
@ 2014-11-07 11:01 ` Paul Barker
2014-11-10 9:25 ` Kang Kai
25 siblings, 1 reply; 51+ messages in thread
From: Paul Barker @ 2014-11-07 11:01 UTC (permalink / raw)
To: Kai Kang; +Cc: Koen Kooi, OE Core
On 7 November 2014 08:51, Kai Kang <kai.kang@windriver.com> wrote:
> gcc-4.9: redefine default library install directory
> Revert "gcc-4.9: redefine default library install directory"
Can the original commit just be removed from the series rather than reverted?
Thanks,
--
Paul Barker
Email: paul@paulbarker.me.uk
http://www.paulbarker.me.uk
^ permalink raw reply [flat|nested] 51+ messages in thread* Re: [PATCH 00/24] V2: Add machine qemuarm64
2014-11-07 11:01 ` Paul Barker
@ 2014-11-10 9:25 ` Kang Kai
2014-11-10 11:26 ` Burton, Ross
0 siblings, 1 reply; 51+ messages in thread
From: Kang Kai @ 2014-11-10 9:25 UTC (permalink / raw)
To: Paul Barker; +Cc: Koen Kooi, OE Core
On 2014年11月07日 19:01, Paul Barker wrote:
> On 7 November 2014 08:51, Kai Kang <kai.kang@windriver.com> wrote:
>> gcc-4.9: redefine default library install directory
>> Revert "gcc-4.9: redefine default library install directory"
> Can the original commit just be removed from the series rather than reverted?
We just want to keep the history how we get here. If nobody cares it,
I'll remove them.
Thanks,
--Kai
>
> Thanks,
>
--
Regards,
Neil | Kai Kang
^ permalink raw reply [flat|nested] 51+ messages in thread
* Re: [PATCH 00/24] V2: Add machine qemuarm64
2014-11-10 9:25 ` Kang Kai
@ 2014-11-10 11:26 ` Burton, Ross
2014-11-11 2:51 ` Kang Kai
0 siblings, 1 reply; 51+ messages in thread
From: Burton, Ross @ 2014-11-10 11:26 UTC (permalink / raw)
To: Kang Kai; +Cc: Koen Kooi, OE Core
[-- Attachment #1: Type: text/plain, Size: 575 bytes --]
On 10 November 2014 09:25, Kang Kai <Kai.Kang@windriver.com> wrote:
> gcc-4.9: redefine default library install directory
>>> Revert "gcc-4.9: redefine default library install directory"
>>>
>> Can the original commit just be removed from the series rather than
>> reverted?
>>
>
> We just want to keep the history how we get here. If nobody cares it, I'll
> remove them.
>
Nothing is gained by knowing that you tried something and it was wrong. If
nothing else is required to be done to this series then we'll remove that
pair when merging.
Ross
[-- Attachment #2: Type: text/html, Size: 1194 bytes --]
^ permalink raw reply [flat|nested] 51+ messages in thread
* Re: [PATCH 00/24] V2: Add machine qemuarm64
2014-11-10 11:26 ` Burton, Ross
@ 2014-11-11 2:51 ` Kang Kai
0 siblings, 0 replies; 51+ messages in thread
From: Kang Kai @ 2014-11-11 2:51 UTC (permalink / raw)
To: Burton, Ross; +Cc: Koen Kooi, OE Core
On 2014年11月10日 19:26, Burton, Ross wrote:
> On 10 November 2014 09:25, Kang Kai <Kai.Kang@windriver.com> wrote:
>
>> gcc-4.9: redefine default library install directory
>>>> Revert "gcc-4.9: redefine default library install directory"
>>>>
>>> Can the original commit just be removed from the series rather than
>>> reverted?
>>>
>> We just want to keep the history how we get here. If nobody cares it, I'll
>> remove them.
>>
> Nothing is gained by knowing that you tried something and it was wrong. If
> nothing else is required to be done to this series then we'll remove that
> pair when merging.
OK. I also dropped the 2 commit on branch poky-contrib/kangkai/qemuarm64.
--Kai
>
> Ross
>
--
Regards,
Neil | Kai Kang
^ permalink raw reply [flat|nested] 51+ messages in thread