From: Timur Tabi <ttabi@nvidia.com>
To: Danilo Krummrich <dakr@kernel.org>,
John Hubbard <jhubbard@nvidia.com>,
Joel Fernandes <joelagnelf@nvidia.com>,
Eliot Courtney <ecourtney@nvidia.com>,
Alexandre Courbot <acourbot@nvidia.com>,
<rust-for-linux@vger.kernel.org>
Subject: [PATCH v2 5/6] gpu: nova-core: skip the IFR header if present
Date: Tue, 14 Apr 2026 18:50:46 -0500 [thread overview]
Message-ID: <20260414235047.439322-6-ttabi@nvidia.com> (raw)
In-Reply-To: <20260414235047.439322-1-ttabi@nvidia.com>
The GPU's ROM may begin with an Init-from-ROM (IFR) header that precedes
the PCI Expansion ROM images (VBIOS). When present, the PROM shadow
method must parse this header to determine the offset where the PCI ROM
images actually begin, and adjust all subsequent reads accordingly.
On most GPUs this is not needed because the IFR microcode has already
applied the ROM offset so that PROM reads transparently skip the header.
On GA100, for whatever reason, the IFR offset is not applied to PROM
reads. Therefore, the search for the PCI expansion must skip the IFR
header, if found.
Signed-off-by: Timur Tabi <ttabi@nvidia.com>
---
drivers/gpu/nova-core/vbios.rs | 67 +++++++++++++++++++++++++++++++++-
1 file changed, 66 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/nova-core/vbios.rs b/drivers/gpu/nova-core/vbios.rs
index e726594eb130..000e823b9e47 100644
--- a/drivers/gpu/nova-core/vbios.rs
+++ b/drivers/gpu/nova-core/vbios.rs
@@ -89,13 +89,78 @@ struct VbiosIterator<'a> {
last_found: bool,
}
+/// Offset of FIXED0 field in IFR header
+const NV_PBUS_IFR_FMT_FIXED0: usize = 0x00000000;
+/// Offset of FIXED1 field in IFR header
+const NV_PBUS_IFR_FMT_FIXED1: usize = 0x00000004;
+/// Offset of FIXED2 field in IFR header
+const NV_PBUS_IFR_FMT_FIXED2: usize = 0x00000008;
+/// IFR signature: ASCII "NVGI" as a little-endian u32.
+const NV_PBUS_IFR_FMT_FIXED0_SIGNATURE_VALUE: u32 = 0x4947564E;
+/// ROM directory signature: ASCII "RFRD" as a little-endian u32.
+const NV_ROM_DIRECTORY_IDENTIFIER: u32 = 0x44524652;
+/// Offset of the NV_PMGR_ROM_ADDR_OFFSET register in IFR Extended section
+const IFR_SW_EXT_ROM_ADDR_OFFSET: usize = 4;
+/// Size of Redundant Firmware Flash Status section
+const RFW_FLASH_STATUS_SIZE: usize = 4096;
+
+bitfield! {
+ struct IfrFixed1(u32) {
+ 15:8 version as u8;
+ 30:16 fixed_data_size as u16;
+ }
+}
+
+bitfield! {
+ struct IfrFixed2(u32) {
+ 19:0 total_data_size as u32;
+ }
+}
+
impl<'a> VbiosIterator<'a> {
fn new(dev: &'a device::Device, bar0: &'a Bar0) -> Result<Self> {
+ let signature = bar0.try_read32(ROM_OFFSET + NV_PBUS_IFR_FMT_FIXED0)?;
+
+ // The ROM may start with an Init-from-ROM (IFR) header before the PCI
+ // Expansion ROM images. Most GPUs apply the IFR offset transparently, but
+ // GA100 does not, so we must skip the header manually if present.
+
+ let current_offset = if signature == NV_PBUS_IFR_FMT_FIXED0_SIGNATURE_VALUE {
+ let fixed1 = IfrFixed1(bar0.try_read32(ROM_OFFSET + NV_PBUS_IFR_FMT_FIXED1)?);
+
+ match fixed1.version() {
+ // Note: We do not actually expect to see v1 or v2 on these GPUs
+ 1 | 2 => {
+ let fixed_data_size = fixed1.fixed_data_size() as usize;
+ let pmgr_rom_addr_offset = fixed_data_size + IFR_SW_EXT_ROM_ADDR_OFFSET;
+ bar0.try_read32(ROM_OFFSET + pmgr_rom_addr_offset)? as usize
+ }
+ 3 => {
+ let fixed2 = IfrFixed2(bar0.try_read32(ROM_OFFSET + NV_PBUS_IFR_FMT_FIXED2)?);
+ let total_data_size = fixed2.total_data_size() as usize;
+ let dir_offset = bar0.try_read32(ROM_OFFSET + total_data_size)? as usize
+ + RFW_FLASH_STATUS_SIZE;
+ let dir_sig = bar0.try_read32(ROM_OFFSET + dir_offset)?;
+ if dir_sig != NV_ROM_DIRECTORY_IDENTIFIER {
+ dev_err!(dev, "could not find IFR ROM directory\n");
+ return Err(EINVAL);
+ }
+ bar0.try_read32(ROM_OFFSET + dir_offset + 8)? as usize
+ }
+ _ => {
+ dev_err!(dev, "unsupported IFR header version {}\n", fixed1.version());
+ return Err(EINVAL);
+ }
+ }
+ } else {
+ 0
+ };
+
Ok(Self {
dev,
bar0,
data: KVec::new(),
- current_offset: 0,
+ current_offset,
last_found: false,
})
}
--
2.53.0
next prev parent reply other threads:[~2026-04-14 23:51 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-04-14 23:50 [PATCH v2 0/6] gpu: nova-core: add GA100 support Timur Tabi
2026-04-14 23:50 ` [PATCH v2 1/6] gpu: nova-core: use correct fwsignature for GA100 Timur Tabi
2026-04-15 13:45 ` Gary Guo
2026-04-15 16:45 ` Timur Tabi
2026-04-15 16:55 ` Gary Guo
2026-04-15 16:58 ` Timur Tabi
2026-04-14 23:50 ` [PATCH v2 2/6] gpu: nova-core: do not consider 0xBB77 as a valid PCI ROM header signature Timur Tabi
2026-04-14 23:50 ` [PATCH v2 3/6] gpu: nova-core: only boot FRTS if its region is allocated Timur Tabi
2026-04-15 4:33 ` Eliot Courtney
2026-04-14 23:50 ` [PATCH v2 4/6] gpu: nova-core: add FbHal::frts_size() for GA100 support Timur Tabi
2026-04-15 4:36 ` Eliot Courtney
2026-04-15 6:55 ` Alexandre Courbot
2026-04-15 13:48 ` Gary Guo
2026-04-15 13:57 ` Alexandre Courbot
2026-04-15 16:57 ` Gary Guo
2026-04-15 16:59 ` Timur Tabi
2026-04-14 23:50 ` Timur Tabi [this message]
2026-04-15 5:23 ` [PATCH v2 5/6] gpu: nova-core: skip the IFR header if present Eliot Courtney
2026-04-15 21:08 ` Timur Tabi
2026-04-16 0:00 ` Timur Tabi
2026-04-17 4:09 ` Alexandre Courbot
2026-04-15 6:54 ` Alexandre Courbot
2026-04-15 13:49 ` Gary Guo
2026-04-15 14:00 ` Alexandre Courbot
2026-04-14 23:50 ` [PATCH v2 6/6] gpu: nova-core: enable GA100 Timur Tabi
2026-04-15 13:51 ` Gary Guo
2026-04-15 16:43 ` Timur Tabi
2026-04-15 16:58 ` Gary Guo
2026-04-15 17:01 ` Timur Tabi
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