From: Andi Shyti <andi.shyti@linux.intel.com>
To: Andrzej Hajda <andrzej.hajda@intel.com>
Cc: Andi Shyti <andi.shyti@linux.intel.com>,
Jonathan Cavitt <jonathan.cavitt@intel.com>,
Matt Roper <matthew.d.roper@intel.com>,
Chris Wilson <chris@chris-wilson.co.uk>,
Mika Kuoppala <mika.kuoppala@linux.intel.com>,
Nirmoy Das <nirmoy.das@intel.com>,
intel-gfx <intel-gfx@lists.freedesktop.org>,
linux-stable <stable@vger.kernel.org>,
dri-evel <dri-devel@lists.freedesktop.org>
Subject: Re: [Intel-gfx] [PATCH v7 2/9] drm/i915: Add the has_aux_ccs device property
Date: Fri, 21 Jul 2023 12:00:12 +0200 [thread overview]
Message-ID: <ZLpXLIVb5DUm8xSx@ashyti-mobl2.lan> (raw)
In-Reply-To: <26ccff3c-b50a-e6e6-97d1-18bb40833108@intel.com>
Hi Andrzej,
On Fri, Jul 21, 2023 at 11:41:22AM +0200, Andrzej Hajda wrote:
> On 20.07.2023 23:07, Andi Shyti wrote:
> > We always assumed that a device might either have AUX or FLAT
> > CCS, but this is an approximation that is not always true as it
> > requires some further per device checks.
> >
> > Add the "has_aux_ccs" flag in the intel_device_info structure in
> > order to have a per device flag indicating of the AUX CCS.
>
> As Matt mentioned in v6, aux_ccs is present also in older platforms.
> This is about presence/necessity (?) of aux_ccs table invalidation.
> Maybe has_aux_ccs_inv, dunno?
yes, true! It's aux_ccs_inv.
> Moreover you define flag per device, but this is rather per engine,
> theoretically could be also:
> MTL:
> .aux_ccs_inv_mask = BIT(RCS0) | BIT(BCS0) | ...
> Others:
> .aux_ccs_inv_mask = BIT(RCS0) | ...
there is already some engine discrimination that is mandatory
later in the series. Doing it here it's a bit replicated.
> looks overkill,
> maybe helper function would be simpler, up to you.
Yes, a helper function that checks on the platform and returns
true or false... it looks hardcoded to me, while the info
structure is hardcoded by definition and looks easier to
maintain by just toggling on/off a single flag in that structure.
That's why I decided to place it there.
But, because there are already two people suggesting it, then I
will try it in v8.
Thanks,
Andi
next prev parent reply other threads:[~2023-07-21 10:00 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-20 21:07 [PATCH v7 0/9] Update AUX invalidation sequence Andi Shyti
2023-07-20 21:07 ` [PATCH v7 1/9] drm/i915/gt: Cleanup aux invalidation registers Andi Shyti
2023-07-20 21:07 ` [PATCH v7 2/9] drm/i915: Add the has_aux_ccs device property Andi Shyti
2023-07-21 9:25 ` [v7,2/9] " Krzysztofik, Janusz
2023-07-21 10:02 ` Andi Shyti
2023-07-21 9:41 ` [Intel-gfx] [PATCH v7 2/9] " Andrzej Hajda
2023-07-21 10:00 ` Andi Shyti [this message]
2023-07-20 21:07 ` [PATCH v7 3/9] drm/i915/gt: Ensure memory quiesced before invalidation Andi Shyti
2023-07-20 21:07 ` [PATCH v7 4/9] drm/i915/gt: Rename flags with bit_group_X according to the datasheet Andi Shyti
2023-07-20 21:07 ` [PATCH v7 5/9] drm/i915/gt: Enable the CCS_FLUSH bit in the pipe control Andi Shyti
2023-07-21 10:05 ` [Intel-gfx] " Andrzej Hajda
2023-07-21 10:10 ` Andi Shyti
2023-07-21 10:17 ` Andrzej Hajda
2023-07-21 10:23 ` Andi Shyti
2023-07-21 11:41 ` [v7,5/9] " Krzysztofik, Janusz
2023-07-21 12:09 ` Andi Shyti
2023-07-20 21:07 ` [PATCH v7 6/9] drm/i915/gt: Refactor intel_emit_pipe_control_cs() in a single function Andi Shyti
2023-07-21 10:10 ` [Intel-gfx] " Andrzej Hajda
2023-07-21 10:12 ` Andi Shyti
2023-07-21 11:54 ` [v7,6/9] " Krzysztofik, Janusz
2023-07-20 21:07 ` [PATCH v7 7/9] drm/i915/gt: Ensure memory quiesced before invalidation for all engines Andi Shyti
2023-07-21 12:10 ` [v7,7/9] " Krzysztofik, Janusz
2023-07-21 12:45 ` Andi Shyti
2023-07-20 21:07 ` [PATCH v7 8/9] drm/i915/gt: Poll aux invalidation register bit on invalidation Andi Shyti
2023-07-20 21:07 ` [PATCH v7 9/9] drm/i915/gt: Support aux invalidation on all engines Andi Shyti
2023-07-21 13:39 ` [v7,9/9] " Krzysztofik, Janusz
2023-07-21 14:02 ` Andi Shyti
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