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From: Andi Shyti <andi.shyti@linux.intel.com>
To: "Krzysztofik, Janusz" <janusz.krzysztofik@intel.com>
Cc: "Cavitt, Jonathan" <jonathan.cavitt@intel.com>,
	"Roper, Matthew D" <matthew.d.roper@intel.com>,
	Chris Wilson <chris@chris-wilson.co.uk>,
	Mika Kuoppala <mika.kuoppala@linux.intel.com>,
	"Das, Nirmoy" <nirmoy.das@intel.com>,
	"Hajda, Andrzej" <andrzej.hajda@intel.com>,
	Andi Shyti <andi.shyti@linux.intel.com>,
	intel-gfx <intel-gfx@lists.freedesktop.org>,
	linux-stable <stable@vger.kernel.org>,
	dri-evel <dri-devel@lists.freedesktop.org>
Subject: Re: [v7,5/9] drm/i915/gt: Enable the CCS_FLUSH bit in the pipe control
Date: Fri, 21 Jul 2023 14:09:13 +0200	[thread overview]
Message-ID: <ZLp1aa2lbM3abmBG@ashyti-mobl2.lan> (raw)
In-Reply-To: <4155037.1IzOArtZ34@jkrzyszt-mobl2.ger.corp.intel.com>

Hi Janusz,

> > Enable the CCS_FLUSH bit 13 in the control pipe for render and
> > compute engines in platforms starting from Meteor Lake (BSPEC
> > 43904 and 47112).
> > 
> > Fixes: 972282c4cf24 ("drm/i915/gen12: Add aux table invalidate for all engines")
> 
> I'm not sure why you think that your change fixes that commit.  Can you please 
> explain?

Hardware folks have provided a new sequence for performing the
quiescing of the engines... that's how it is :)

Thanks,
Andi

  reply	other threads:[~2023-07-21 12:09 UTC|newest]

Thread overview: 27+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-07-20 21:07 [PATCH v7 0/9] Update AUX invalidation sequence Andi Shyti
2023-07-20 21:07 ` [PATCH v7 1/9] drm/i915/gt: Cleanup aux invalidation registers Andi Shyti
2023-07-20 21:07 ` [PATCH v7 2/9] drm/i915: Add the has_aux_ccs device property Andi Shyti
2023-07-21  9:25   ` [v7,2/9] " Krzysztofik, Janusz
2023-07-21 10:02     ` Andi Shyti
2023-07-21  9:41   ` [Intel-gfx] [PATCH v7 2/9] " Andrzej Hajda
2023-07-21 10:00     ` Andi Shyti
2023-07-20 21:07 ` [PATCH v7 3/9] drm/i915/gt: Ensure memory quiesced before invalidation Andi Shyti
2023-07-20 21:07 ` [PATCH v7 4/9] drm/i915/gt: Rename flags with bit_group_X according to the datasheet Andi Shyti
2023-07-20 21:07 ` [PATCH v7 5/9] drm/i915/gt: Enable the CCS_FLUSH bit in the pipe control Andi Shyti
2023-07-21 10:05   ` [Intel-gfx] " Andrzej Hajda
2023-07-21 10:10     ` Andi Shyti
2023-07-21 10:17   ` Andrzej Hajda
2023-07-21 10:23     ` Andi Shyti
2023-07-21 11:41   ` [v7,5/9] " Krzysztofik, Janusz
2023-07-21 12:09     ` Andi Shyti [this message]
2023-07-20 21:07 ` [PATCH v7 6/9] drm/i915/gt: Refactor intel_emit_pipe_control_cs() in a single function Andi Shyti
2023-07-21 10:10   ` [Intel-gfx] " Andrzej Hajda
2023-07-21 10:12     ` Andi Shyti
2023-07-21 11:54   ` [v7,6/9] " Krzysztofik, Janusz
2023-07-20 21:07 ` [PATCH v7 7/9] drm/i915/gt: Ensure memory quiesced before invalidation for all engines Andi Shyti
2023-07-21 12:10   ` [v7,7/9] " Krzysztofik, Janusz
2023-07-21 12:45     ` Andi Shyti
2023-07-20 21:07 ` [PATCH v7 8/9] drm/i915/gt: Poll aux invalidation register bit on invalidation Andi Shyti
2023-07-20 21:07 ` [PATCH v7 9/9] drm/i915/gt: Support aux invalidation on all engines Andi Shyti
2023-07-21 13:39   ` [v7,9/9] " Krzysztofik, Janusz
2023-07-21 14:02     ` Andi Shyti

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