From: Andi Shyti <andi.shyti@linux.intel.com>
To: "Krzysztofik, Janusz" <janusz.krzysztofik@intel.com>
Cc: "Cavitt, Jonathan" <jonathan.cavitt@intel.com>,
"Roper, Matthew D" <matthew.d.roper@intel.com>,
Chris Wilson <chris@chris-wilson.co.uk>,
Mika Kuoppala <mika.kuoppala@linux.intel.com>,
"Das, Nirmoy" <nirmoy.das@intel.com>,
"Hajda, Andrzej" <andrzej.hajda@intel.com>,
Andi Shyti <andi.shyti@linux.intel.com>,
intel-gfx <intel-gfx@lists.freedesktop.org>,
linux-stable <stable@vger.kernel.org>,
dri-evel <dri-devel@lists.freedesktop.org>
Subject: Re: [v7,2/9] drm/i915: Add the has_aux_ccs device property
Date: Fri, 21 Jul 2023 12:02:20 +0200 [thread overview]
Message-ID: <ZLpXrADgrQjybo0/@ashyti-mobl2.lan> (raw)
In-Reply-To: <2423957.jE0xQCEvom@jkrzyszt-mobl2.ger.corp.intel.com>
Hi Janusz,
On Fri, Jul 21, 2023 at 09:25:03AM +0000, Krzysztofik, Janusz wrote:
> Hi Andy,
>
> On Thursday, 20 July 2023 23:07:30 CEST Andi Shyti wrote:
> > We always assumed that a device might either have AUX or FLAT
> > CCS, but this is an approximation that is not always true
>
> If there exists a device that can have CCSs that fall into either none or both
> of those categories then I think we should have that device or two listed here
> as an example, regardless of deducible from the change or not. Or if there
> are no such devices so far, but we are going to introduce some, then I think
> we should provide that information here.
true! I will improve the commit log.
[...]
> > --- a/drivers/gpu/drm/i915/i915_pci.c
> > +++ b/drivers/gpu/drm/i915/i915_pci.c
> > @@ -643,7 +643,8 @@ static const struct intel_device_info jsl_info = {
> > TGL_CACHELEVEL, \
> > .has_global_mocs = 1, \
> > .has_pxp = 1, \
> > - .max_pat_index = 3
> > + .max_pat_index = 3, \
> > + .has_aux_ccs = 1
>
> NIT: Can we please have the last element also followed by comma, like in other
> places (e.g. see below)? That will simplify future patches.
>
> Other than that, LGTM.
As Andrzej and Matt suggested I will take another approach, i.e.
adding a helper function that tells whether the aux invalidation
is necessary or not.
Thanks,
Andi
next prev parent reply other threads:[~2023-07-21 10:02 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-20 21:07 [PATCH v7 0/9] Update AUX invalidation sequence Andi Shyti
2023-07-20 21:07 ` [PATCH v7 1/9] drm/i915/gt: Cleanup aux invalidation registers Andi Shyti
2023-07-20 21:07 ` [PATCH v7 2/9] drm/i915: Add the has_aux_ccs device property Andi Shyti
2023-07-21 9:25 ` [v7,2/9] " Krzysztofik, Janusz
2023-07-21 10:02 ` Andi Shyti [this message]
2023-07-21 9:41 ` [Intel-gfx] [PATCH v7 2/9] " Andrzej Hajda
2023-07-21 10:00 ` Andi Shyti
2023-07-20 21:07 ` [PATCH v7 3/9] drm/i915/gt: Ensure memory quiesced before invalidation Andi Shyti
2023-07-20 21:07 ` [PATCH v7 4/9] drm/i915/gt: Rename flags with bit_group_X according to the datasheet Andi Shyti
2023-07-20 21:07 ` [PATCH v7 5/9] drm/i915/gt: Enable the CCS_FLUSH bit in the pipe control Andi Shyti
2023-07-21 10:05 ` [Intel-gfx] " Andrzej Hajda
2023-07-21 10:10 ` Andi Shyti
2023-07-21 10:17 ` Andrzej Hajda
2023-07-21 10:23 ` Andi Shyti
2023-07-21 11:41 ` [v7,5/9] " Krzysztofik, Janusz
2023-07-21 12:09 ` Andi Shyti
2023-07-20 21:07 ` [PATCH v7 6/9] drm/i915/gt: Refactor intel_emit_pipe_control_cs() in a single function Andi Shyti
2023-07-21 10:10 ` [Intel-gfx] " Andrzej Hajda
2023-07-21 10:12 ` Andi Shyti
2023-07-21 11:54 ` [v7,6/9] " Krzysztofik, Janusz
2023-07-20 21:07 ` [PATCH v7 7/9] drm/i915/gt: Ensure memory quiesced before invalidation for all engines Andi Shyti
2023-07-21 12:10 ` [v7,7/9] " Krzysztofik, Janusz
2023-07-21 12:45 ` Andi Shyti
2023-07-20 21:07 ` [PATCH v7 8/9] drm/i915/gt: Poll aux invalidation register bit on invalidation Andi Shyti
2023-07-20 21:07 ` [PATCH v7 9/9] drm/i915/gt: Support aux invalidation on all engines Andi Shyti
2023-07-21 13:39 ` [v7,9/9] " Krzysztofik, Janusz
2023-07-21 14:02 ` Andi Shyti
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