From: Andi Shyti <andi.shyti@linux.intel.com>
To: Andrzej Hajda <andrzej.hajda@intel.com>
Cc: Andi Shyti <andi.shyti@linux.intel.com>,
Jonathan Cavitt <jonathan.cavitt@intel.com>,
Matt Roper <matthew.d.roper@intel.com>,
Chris Wilson <chris@chris-wilson.co.uk>,
Mika Kuoppala <mika.kuoppala@linux.intel.com>,
Nirmoy Das <nirmoy.das@intel.com>,
intel-gfx <intel-gfx@lists.freedesktop.org>,
linux-stable <stable@vger.kernel.org>,
dri-evel <dri-devel@lists.freedesktop.org>
Subject: Re: [Intel-gfx] [PATCH v7 6/9] drm/i915/gt: Refactor intel_emit_pipe_control_cs() in a single function
Date: Fri, 21 Jul 2023 12:12:10 +0200 [thread overview]
Message-ID: <ZLpZ+m4rlTTUHHrO@ashyti-mobl2.lan> (raw)
In-Reply-To: <1cb56f45-cb68-82f2-dc43-b4706b2e12c1@intel.com>
On Fri, Jul 21, 2023 at 12:10:48PM +0200, Andrzej Hajda wrote:
> On 20.07.2023 23:07, Andi Shyti wrote:
> > Just a trivial refactoring for reducing the number of code
> > duplicate. This will come at handy in the next commits.
> >
> > Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
> > Cc: <stable@vger.kernel.org> # v5.8+
> > ---
> > drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 44 +++++++++++++-----------
> > 1 file changed, 23 insertions(+), 21 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> > index 9d050b9a19194..202d6ff8b5264 100644
> > --- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> > +++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> > @@ -177,23 +177,31 @@ u32 *gen12_emit_aux_table_inv(struct intel_gt *gt, u32 *cs, const i915_reg_t inv
> > return cs;
> > }
> > +static u32 *intel_emit_pipe_control_cs(struct i915_request *rq, u32 bit_group_0,
> > + u32 bit_group_1, u32 offset)
>
>
> s/intel/gen12/
>
> but this and few other issues were raised already by Matt in v6.
Thanks!
Andi
next prev parent reply other threads:[~2023-07-21 10:12 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-20 21:07 [PATCH v7 0/9] Update AUX invalidation sequence Andi Shyti
2023-07-20 21:07 ` [PATCH v7 1/9] drm/i915/gt: Cleanup aux invalidation registers Andi Shyti
2023-07-20 21:07 ` [PATCH v7 2/9] drm/i915: Add the has_aux_ccs device property Andi Shyti
2023-07-21 9:25 ` [v7,2/9] " Krzysztofik, Janusz
2023-07-21 10:02 ` Andi Shyti
2023-07-21 9:41 ` [Intel-gfx] [PATCH v7 2/9] " Andrzej Hajda
2023-07-21 10:00 ` Andi Shyti
2023-07-20 21:07 ` [PATCH v7 3/9] drm/i915/gt: Ensure memory quiesced before invalidation Andi Shyti
2023-07-20 21:07 ` [PATCH v7 4/9] drm/i915/gt: Rename flags with bit_group_X according to the datasheet Andi Shyti
2023-07-20 21:07 ` [PATCH v7 5/9] drm/i915/gt: Enable the CCS_FLUSH bit in the pipe control Andi Shyti
2023-07-21 10:05 ` [Intel-gfx] " Andrzej Hajda
2023-07-21 10:10 ` Andi Shyti
2023-07-21 10:17 ` Andrzej Hajda
2023-07-21 10:23 ` Andi Shyti
2023-07-21 11:41 ` [v7,5/9] " Krzysztofik, Janusz
2023-07-21 12:09 ` Andi Shyti
2023-07-20 21:07 ` [PATCH v7 6/9] drm/i915/gt: Refactor intel_emit_pipe_control_cs() in a single function Andi Shyti
2023-07-21 10:10 ` [Intel-gfx] " Andrzej Hajda
2023-07-21 10:12 ` Andi Shyti [this message]
2023-07-21 11:54 ` [v7,6/9] " Krzysztofik, Janusz
2023-07-20 21:07 ` [PATCH v7 7/9] drm/i915/gt: Ensure memory quiesced before invalidation for all engines Andi Shyti
2023-07-21 12:10 ` [v7,7/9] " Krzysztofik, Janusz
2023-07-21 12:45 ` Andi Shyti
2023-07-20 21:07 ` [PATCH v7 8/9] drm/i915/gt: Poll aux invalidation register bit on invalidation Andi Shyti
2023-07-20 21:07 ` [PATCH v7 9/9] drm/i915/gt: Support aux invalidation on all engines Andi Shyti
2023-07-21 13:39 ` [v7,9/9] " Krzysztofik, Janusz
2023-07-21 14:02 ` Andi Shyti
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