* [U-Boot] [PATCH v5 1/2] arm: cache: add support for LPAE for region D$ behavior
@ 2016-08-15 4:33 Stefan Agner
2016-08-15 4:33 ` [U-Boot] [PATCH v5 2/2] arm: cache: always flush cache line size for page table Stefan Agner
2016-08-29 12:00 ` [U-Boot] [U-Boot, v5, 1/2] arm: cache: add support for LPAE for region D$ behavior Tom Rini
0 siblings, 2 replies; 4+ messages in thread
From: Stefan Agner @ 2016-08-15 4:33 UTC (permalink / raw)
To: u-boot
From: Stefan Agner <stefan.agner@toradex.com>
Add LPAE support for mmu_set_region_dcache_behaviour. The function
is in use in some LPAE capable board such TI DRA7xx or NXP i.MX 7.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
---
Changes in v5:
- Add this LPAE enablement patch
Changes in v4: None
Changes in v3: None
Changes in v2: None
arch/arm/lib/cache-cp15.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c
index 1121dc3..3aabda1 100644
--- a/arch/arm/lib/cache-cp15.c
+++ b/arch/arm/lib/cache-cp15.c
@@ -61,7 +61,11 @@ __weak void mmu_page_table_flush(unsigned long start, unsigned long stop)
void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
enum dcache_option option)
{
+#ifdef CONFIG_ARMV7_LPAE
+ u64 *page_table = (u64 *)gd->arch.tlb_addr;
+#else
u32 *page_table = (u32 *)gd->arch.tlb_addr;
+#endif
unsigned long upto, end;
end = ALIGN(start + size, MMU_SECTION_SIZE) >> MMU_SECTION_SHIFT;
--
2.9.0
^ permalink raw reply related [flat|nested] 4+ messages in thread* [U-Boot] [PATCH v5 2/2] arm: cache: always flush cache line size for page table
2016-08-15 4:33 [U-Boot] [PATCH v5 1/2] arm: cache: add support for LPAE for region D$ behavior Stefan Agner
@ 2016-08-15 4:33 ` Stefan Agner
2016-08-29 12:00 ` [U-Boot] [U-Boot, v5, " Tom Rini
2016-08-29 12:00 ` [U-Boot] [U-Boot, v5, 1/2] arm: cache: add support for LPAE for region D$ behavior Tom Rini
1 sibling, 1 reply; 4+ messages in thread
From: Stefan Agner @ 2016-08-15 4:33 UTC (permalink / raw)
To: u-boot
From: Stefan Agner <stefan.agner@toradex.com>
The page table is maintained by the CPU, hence it is safe to always
align cache flush to a whole cache line size. This allows to use
mmu_page_table_flush for a single page table, e.g. when configure
only small regions through mmu_set_region_dcache_behaviour.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Tested-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
---
Changes in v5:
- Convert to a type the size of a CPU pointer (unsigned long)
- Rebase on LPAE enablement patch
Changes in v4:
- Fixed spelling misstake for real
Changes in v3:
- Fixed spelling misstake
Changes in v2:
- Move cache line alignment from mmu_page_table_flush to
mmu_set_region_dcache_behaviour
arch/arm/lib/cache-cp15.c | 14 +++++++++++++-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c
index 3aabda1..70e94f0 100644
--- a/arch/arm/lib/cache-cp15.c
+++ b/arch/arm/lib/cache-cp15.c
@@ -66,6 +66,7 @@ void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
#else
u32 *page_table = (u32 *)gd->arch.tlb_addr;
#endif
+ unsigned long startpt, stoppt;
unsigned long upto, end;
end = ALIGN(start + size, MMU_SECTION_SIZE) >> MMU_SECTION_SHIFT;
@@ -74,7 +75,18 @@ void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
option);
for (upto = start; upto < end; upto++)
set_section_dcache(upto, option);
- mmu_page_table_flush((u32)&page_table[start], (u32)&page_table[end]);
+
+ /*
+ * Make sure range is cache line aligned
+ * Only CPU maintains page tables, hence it is safe to always
+ * flush complete cache lines...
+ */
+
+ startpt = (unsigned long)&page_table[start];
+ startpt &= ~(CONFIG_SYS_CACHELINE_SIZE - 1);
+ stoppt = (unsigned long)&page_table[end];
+ stoppt = ALIGN(stoppt, CONFIG_SYS_CACHELINE_SIZE);
+ mmu_page_table_flush(startpt, stoppt);
}
__weak void dram_bank_mmu_setup(int bank)
--
2.9.0
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [U-Boot] [U-Boot, v5, 1/2] arm: cache: add support for LPAE for region D$ behavior
2016-08-15 4:33 [U-Boot] [PATCH v5 1/2] arm: cache: add support for LPAE for region D$ behavior Stefan Agner
2016-08-15 4:33 ` [U-Boot] [PATCH v5 2/2] arm: cache: always flush cache line size for page table Stefan Agner
@ 2016-08-29 12:00 ` Tom Rini
1 sibling, 0 replies; 4+ messages in thread
From: Tom Rini @ 2016-08-29 12:00 UTC (permalink / raw)
To: u-boot
On Sun, Aug 14, 2016 at 09:33:00PM -0700, Stefan Agner wrote:
> From: Stefan Agner <stefan.agner@toradex.com>
>
> Add LPAE support for mmu_set_region_dcache_behaviour. The function
> is in use in some LPAE capable board such TI DRA7xx or NXP i.MX 7.
>
> Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Applied to u-boot/master, thanks!
--
Tom
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2016-08-15 4:33 [U-Boot] [PATCH v5 1/2] arm: cache: add support for LPAE for region D$ behavior Stefan Agner
2016-08-15 4:33 ` [U-Boot] [PATCH v5 2/2] arm: cache: always flush cache line size for page table Stefan Agner
2016-08-29 12:00 ` [U-Boot] [U-Boot, v5, " Tom Rini
2016-08-29 12:00 ` [U-Boot] [U-Boot, v5, 1/2] arm: cache: add support for LPAE for region D$ behavior Tom Rini
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