[PATCH v2 00/10] cache operation cleanups for Andes AE350 platform

[PATCH v2 00/10] cache operation cleanups for Andes AE350 platform

[Yu Chien Peter Lin]

This patchset is intended to enable L2-cache in U-boot SPL, along with
cache operations cleanup for AE350 platforms.

Changes v1 -> v2:
- Drop plicsw related patch
- Include RB tags from Rick and Leo

The patchset is based on commit:
a209c3e6b48cf042d0220245a2d1636f74389c17

Leo Yu-Chi Liang (1):
  riscv: Remove redundant Kconfig "RISCV_NDS_CACHE"

Yu Chien Peter Lin (9):
  board: AndesTech: ax25-ae350.c: Enable v5l2-cache in spl_board_init()
  driver: cache: cache-v5l2: Update memory-mapped scheme to support Gen2
    platform
  riscv: cpu: ax25: Simplify cache enabling logic in harts_early_init()
  riscv: ae350: dts: Update L2 cache compatible string
  riscv: ax25: cache.c: Cleanups to L1/L2 cache function used in SPL
  configs: ae350: Enable v5l2 cache for AE350 platforms in SPL
  configs: ae350: Increase maximum retry count for AE350 platforms
  configs: ae350: Display CPU and board info for AE350 platforms
  driver: cache-v5l2: Fix type casting warning on RV32

 arch/riscv/cpu/ax25/Kconfig             |  11 +--
 arch/riscv/cpu/ax25/cache.c             | 118 ++++++++----------------
 arch/riscv/cpu/ax25/cpu.c               |  49 +++-------
 arch/riscv/dts/ae350_32.dts             |   2 +-
 arch/riscv/dts/ae350_64.dts             |   2 +-
 arch/riscv/include/asm/arch-andes/csr.h |  29 ++++++
 board/AndesTech/ax25-ae350/ax25-ae350.c |  17 ++--
 configs/ae350_rv32_defconfig            |   3 +
 configs/ae350_rv32_spl_defconfig        |   5 +
 configs/ae350_rv32_spl_xip_defconfig    |   5 +
 configs/ae350_rv32_xip_defconfig        |   3 +
 configs/ae350_rv64_defconfig            |   3 +
 configs/ae350_rv64_spl_defconfig        |   5 +
 configs/ae350_rv64_spl_xip_defconfig    |   5 +
 configs/ae350_rv64_xip_defconfig        |   3 +
 drivers/cache/Kconfig                   |   1 -
 drivers/cache/cache-v5l2.c              |  36 ++++++--
 17 files changed, 149 insertions(+), 148 deletions(-)
 create mode 100644 arch/riscv/include/asm/arch-andes/csr.h

-- 
2.34.1

[PATCH v2 01/10] riscv: Remove redundant Kconfig "RISCV_NDS_CACHE"

[Yu Chien Peter Lin]

From: Leo Yu-Chi Liang <ycliang@andestech.com>

There is no need for RISCV_NDS_CACHE config to control cache switches.

Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Rick Chen <rick@andestech.com>
---
 arch/riscv/cpu/ax25/Kconfig | 10 -----
 arch/riscv/cpu/ax25/cache.c | 84 +------------------------------------
 drivers/cache/Kconfig       |  1 -
 3 files changed, 2 insertions(+), 93 deletions(-)

diff --git a/arch/riscv/cpu/ax25/Kconfig b/arch/riscv/cpu/ax25/Kconfig
index 4a7295d30c..eca68ea2a7 100644
--- a/arch/riscv/cpu/ax25/Kconfig
+++ b/arch/riscv/cpu/ax25/Kconfig
@@ -12,13 +12,3 @@ config RISCV_NDS
 	help
 	  Run U-Boot on AndeStar V5 platforms and use some specific features
 	  which are provided by Andes Technology AndeStar V5 families.
-
-if RISCV_NDS
-
-config RISCV_NDS_CACHE
-	bool "AndeStar V5 families specific cache support"
-	depends on RISCV_MMODE || SPL_RISCV_MMODE
-	help
-	  Provide Andes Technology AndeStar V5 families specific cache support.
-
-endif
diff --git a/arch/riscv/cpu/ax25/cache.c b/arch/riscv/cpu/ax25/cache.c
index 35f23c748d..1c0c3772a1 100644
--- a/arch/riscv/cpu/ax25/cache.c
+++ b/arch/riscv/cpu/ax25/cache.c
@@ -67,106 +67,26 @@ void invalidate_dcache_range(unsigned long start, unsigned long end)
 
 void icache_enable(void)
 {
-#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
-#ifdef CONFIG_RISCV_NDS_CACHE
-#if CONFIG_IS_ENABLED(RISCV_MMODE)
-	asm volatile (
-		"csrr t1, mcache_ctl\n\t"
-		"ori t0, t1, 0x1\n\t"
-		"csrw mcache_ctl, t0\n\t"
-	);
-#endif
-#endif
-#endif
 }
 
 void icache_disable(void)
 {
-#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
-#ifdef CONFIG_RISCV_NDS_CACHE
-#if CONFIG_IS_ENABLED(RISCV_MMODE)
-	asm volatile (
-		"fence.i\n\t"
-		"csrr t1, mcache_ctl\n\t"
-		"andi t0, t1, ~0x1\n\t"
-		"csrw mcache_ctl, t0\n\t"
-	);
-#endif
-#endif
-#endif
 }
 
 void dcache_enable(void)
 {
-#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
-#ifdef CONFIG_RISCV_NDS_CACHE
-#if CONFIG_IS_ENABLED(RISCV_MMODE)
-	asm volatile (
-		"csrr t1, mcache_ctl\n\t"
-		"ori t0, t1, 0x2\n\t"
-		"csrw mcache_ctl, t0\n\t"
-	);
-#endif
-#ifdef CONFIG_V5L2_CACHE
-	_cache_enable();
-#endif
-#endif
-#endif
 }
 
 void dcache_disable(void)
 {
-#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
-#ifdef CONFIG_RISCV_NDS_CACHE
-#if CONFIG_IS_ENABLED(RISCV_MMODE)
-	csr_write(CCTL_REG_MCCTLCOMMAND_NUM, CCTL_L1D_WBINVAL_ALL);
-	asm volatile (
-		"csrr t1, mcache_ctl\n\t"
-		"andi t0, t1, ~0x2\n\t"
-		"csrw mcache_ctl, t0\n\t"
-	);
-#endif
-#ifdef CONFIG_V5L2_CACHE
-	_cache_disable();
-#endif
-#endif
-#endif
 }
 
 int icache_status(void)
 {
-	int ret = 0;
-
-#ifdef CONFIG_RISCV_NDS_CACHE
-#if CONFIG_IS_ENABLED(RISCV_MMODE)
-	asm volatile (
-		"csrr t1, mcache_ctl\n\t"
-		"andi	%0, t1, 0x01\n\t"
-		: "=r" (ret)
-		:
-		: "memory"
-	);
-#endif
-#endif
-
-	return ret;
+	return 0;
 }
 
 int dcache_status(void)
 {
-	int ret = 0;
-
-#ifdef CONFIG_RISCV_NDS_CACHE
-#if CONFIG_IS_ENABLED(RISCV_MMODE)
-	asm volatile (
-		"csrr t1, mcache_ctl\n\t"
-		"andi	%0, t1, 0x02\n\t"
-		: "=r" (ret)
-		:
-		: "memory"
-	);
-#endif
-#endif
-
-	return ret;
+	return 0;
 }
diff --git a/drivers/cache/Kconfig b/drivers/cache/Kconfig
index 40f41a817c..6cb8c3e980 100644
--- a/drivers/cache/Kconfig
+++ b/drivers/cache/Kconfig
@@ -25,7 +25,6 @@ config L2X0_CACHE
 config V5L2_CACHE
 	bool "Andes V5L2 cache driver"
 	select CACHE
-	depends on RISCV_NDS_CACHE
 	help
 	  Support Andes V5L2 cache controller in AE350 platform.
 	  It will configure tag and data ram timing control from the
-- 
2.34.1

[PATCH v2 02/10] board: AndesTech: ax25-ae350.c: Enable v5l2-cache in spl_board_init()

[Yu Chien Peter Lin]

The L2-cache is not enabled currently, the enbale_caches() will call
the v5l2_enable() callback to enable it in SPL.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Rick Chen <rick@andestech.com>
---
 board/AndesTech/ax25-ae350/ax25-ae350.c | 17 +++++++++--------
 1 file changed, 9 insertions(+), 8 deletions(-)

diff --git a/board/AndesTech/ax25-ae350/ax25-ae350.c b/board/AndesTech/ax25-ae350/ax25-ae350.c
index 63a966e092..1c2288b6ce 100644
--- a/board/AndesTech/ax25-ae350/ax25-ae350.c
+++ b/board/AndesTech/ax25-ae350/ax25-ae350.c
@@ -5,6 +5,7 @@
  */
 
 #include <common.h>
+#include <cpu_func.h>
 #include <flash.h>
 #include <image.h>
 #include <init.h>
@@ -72,6 +73,14 @@ void *board_fdt_blob_setup(int *err)
 	return NULL;
 }
 
+#ifdef CONFIG_SPL_BOARD_INIT
+void spl_board_init()
+{
+	/* enable v5l2 cache */
+	enable_caches();
+}
+#endif
+
 int smc_init(void)
 {
 	int node = -1;
@@ -96,18 +105,10 @@ int smc_init(void)
 	return 0;
 }
 
-static void v5l2_init(void)
-{
-	struct udevice *dev;
-
-	uclass_get_device(UCLASS_CACHE, 0, &dev);
-}
-
 #ifdef CONFIG_BOARD_EARLY_INIT_F
 int board_early_init_f(void)
 {
 	smc_init();
-	v5l2_init();
 
 	return 0;
 }
-- 
2.34.1

[PATCH v2 03/10] driver: cache: cache-v5l2: Update memory-mapped scheme to support Gen2 platform

[Yu Chien Peter Lin]

The L2C configuration register has MAP field to indicate its version
is v0 (Gen1) or v1 (Gen2) L2-cache. This patch makes the driver
compatible with both memory-mapped scheme.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
---
 drivers/cache/cache-v5l2.c | 32 ++++++++++++++++++++++++--------
 1 file changed, 24 insertions(+), 8 deletions(-)

diff --git a/drivers/cache/cache-v5l2.c b/drivers/cache/cache-v5l2.c
index bbdb76bd57..e782430c57 100644
--- a/drivers/cache/cache-v5l2.c
+++ b/drivers/cache/cache-v5l2.c
@@ -34,6 +34,14 @@ struct l2cache {
 	volatile u64	cctl_status;
 };
 
+/* Configuration register */
+#define MEM_MAP_OFF	20
+#define MEM_MAP_MSK	BIT(MEM_MAP_OFF)
+/* offset of v0 memory map (Gen1) */
+static u32 cmd_stride = 0x10;
+static u32 status_stride = 0x0;
+static u32 status_bit_offset = 0x4;
+
 /* Control Register */
 #define L2_ENABLE	0x1
 /* prefetch */
@@ -53,14 +61,15 @@ struct l2cache {
 #define DRAMICTL_MSK	BIT(DRAMICTL_OFF)
 
 /* CCTL Command Register */
-#define CCTL_CMD_REG(base, hart)	((ulong)(base) + 0x40 + (hart) * 0x10)
+#define CCTL_CMD_REG(base, hart)	((ulong)(base) + 0x40 + (hart) * (cmd_stride))
 #define L2_WBINVAL_ALL	0x12
 
 /* CCTL Status Register */
-#define CCTL_STATUS_MSK(hart)		(0xf << ((hart) * 4))
-#define CCTL_STATUS_IDLE(hart)		(0 << ((hart) * 4))
-#define CCTL_STATUS_PROCESS(hart)	(1 << ((hart) * 4))
-#define CCTL_STATUS_ILLEGAL(hart)	(2 << ((hart) * 4))
+#define CCTL_STATUS_REG(base, hart)	((ulong)(base) + 0x80 + (hart) * (status_stride))
+#define CCTL_STATUS_MSK(hart)		(0xf << ((hart) * (status_bit_offset)))
+#define CCTL_STATUS_IDLE(hart)		(0 << ((hart) * (status_bit_offset)))
+#define CCTL_STATUS_PROCESS(hart)	(1 << ((hart) * (status_bit_offset)))
+#define CCTL_STATUS_ILLEGAL(hart)	(2 << ((hart) * (status_bit_offset)))
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -133,12 +142,19 @@ static int v5l2_probe(struct udevice *dev)
 {
 	struct v5l2_plat *plat = dev_get_plat(dev);
 	struct l2cache *regs = plat->regs;
-	u32 ctl_val;
+	u32 cfg_val, ctl_val;
 
+	cfg_val = readl(&regs->configure);
 	ctl_val = readl(&regs->control);
 
-	if (!(ctl_val & L2_ENABLE))
-		ctl_val |= L2_ENABLE;
+	/* If true, v1 memory map (Gen2) */
+	if (cfg_val & MEM_MAP_MSK) {
+		cmd_stride = 0x1000;
+		status_stride = 0x1000;
+		status_bit_offset = 0x0;
+	}
+
+	ctl_val |= L2_ENABLE;
 
 	if (plat->iprefetch != -EINVAL) {
 		ctl_val &= ~(IPREPETCH_MSK);
-- 
2.34.1

Re: [PATCH v2 03/10] driver: cache: cache-v5l2: Update memory-mapped scheme to support Gen2 platform

[Rick Chen]

> From: Peter Yu-Chien Lin(林宇謙) <peterlin@andestech.com>
> Sent: Monday, February 06, 2023 4:11 PM
> To: u-boot@lists.denx.de
> Cc: Leo Yu-Chi Liang(梁育齊) <ycliang@andestech.com>; Rick Jian-Zhi Chen(陳建志) <rick@andestech.com>; prabhakar.csengg@gmail.com; Peter Yu-Chien Lin(林宇謙) <peterlin@andestech.com>
> Subject: [PATCH v2 03/10] driver: cache: cache-v5l2: Update memory-mapped scheme to support Gen2 platform
>
> The L2C configuration register has MAP field to indicate its version is v0 (Gen1) or v1 (Gen2) L2-cache. This patch makes the driver compatible with both memory-mapped scheme.
>
> Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
> ---
>  drivers/cache/cache-v5l2.c | 32 ++++++++++++++++++++++++--------
>  1 file changed, 24 insertions(+), 8 deletions(-)

Reviewed-by: Rick Chen <rick@andestech.com>

[PATCH v2 04/10] riscv: cpu: ax25: Simplify cache enabling logic in harts_early_init()

[Yu Chien Peter Lin]

As the OpenSBI v1.2 does not enable the cache [0], we enable
the i/d-cache in harts_early_init() and do not disable in
cleanup_before_linux(). This patch also simplifies the logic
and moves the CSR encoding to include/asm/arch-andes/csr.h.

[0] https://github.com/riscv-software-src/opensbi/commit/bd7ef4139829da5c30fa980f7498d385124408fa

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
---
 arch/riscv/cpu/ax25/cpu.c               | 49 ++++++-------------------
 arch/riscv/include/asm/arch-andes/csr.h | 29 +++++++++++++++
 2 files changed, 41 insertions(+), 37 deletions(-)
 create mode 100644 arch/riscv/include/asm/arch-andes/csr.h

diff --git a/arch/riscv/cpu/ax25/cpu.c b/arch/riscv/cpu/ax25/cpu.c
index a46674f7c2..2c7565ad49 100644
--- a/arch/riscv/cpu/ax25/cpu.c
+++ b/arch/riscv/cpu/ax25/cpu.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright (C) 2017 Andes Technology Corporation
+ * Copyright (C) 2023 Andes Technology Corporation
  * Rick Chen, Andes Technology Corporation <rick@andestech.com>
  */
 
@@ -10,23 +10,7 @@
 #include <irq_func.h>
 #include <asm/cache.h>
 #include <asm/csr.h>
-
-#define CSR_MCACHE_CTL	0x7ca
-#define CSR_MMISC_CTL		0x7d0
-#define CSR_MARCHID			0xf12
-
-#define V5_MCACHE_CTL_IC_EN_OFFSET      0
-#define V5_MCACHE_CTL_DC_EN_OFFSET      1
-#define V5_MCACHE_CTL_CCTL_SUEN_OFFSET	8
-#define V5_MCACHE_CTL_DC_COHEN_OFFSET		19
-#define V5_MCACHE_CTL_DC_COHSTA_OFFSET	20
-
-#define V5_MCACHE_CTL_IC_EN					BIT(V5_MCACHE_CTL_IC_EN_OFFSET)
-#define V5_MCACHE_CTL_DC_EN					BIT(V5_MCACHE_CTL_DC_EN_OFFSET)
-#define V5_MCACHE_CTL_CCTL_SUEN			BIT(V5_MCACHE_CTL_CCTL_SUEN_OFFSET)
-#define V5_MCACHE_CTL_DC_COHEN_EN   BIT(V5_MCACHE_CTL_DC_COHEN_OFFSET)
-#define V5_MCACHE_CTL_DC_COHSTA_EN  BIT(V5_MCACHE_CTL_DC_COHSTA_OFFSET)
-
+#include <asm/arch-andes/csr.h>
 
 /*
  * cleanup_before_linux() is called just before we call linux
@@ -38,38 +22,29 @@ int cleanup_before_linux(void)
 {
 	disable_interrupts();
 
-	/* turn off I/D-cache */
 	cache_flush();
-	icache_disable();
-	dcache_disable();
 
 	return 0;
 }
 
 void harts_early_init(void)
 {
+	/* Enable I/D-cache in SPL */
 	if (CONFIG_IS_ENABLED(RISCV_MMODE)) {
-		unsigned long long mcache_ctl_val = csr_read(CSR_MCACHE_CTL);
+		unsigned long mcache_ctl_val = csr_read(CSR_MCACHE_CTL);
+
+		mcache_ctl_val |= (MCACHE_CTL_DC_COHEN | MCACHE_CTL_IC_EN |
+				   MCACHE_CTL_DC_EN);
 
-		if (!(mcache_ctl_val & V5_MCACHE_CTL_DC_COHEN_EN))
-			mcache_ctl_val |= V5_MCACHE_CTL_DC_COHEN_EN;
-		if (!(mcache_ctl_val & V5_MCACHE_CTL_IC_EN))
-			mcache_ctl_val |= V5_MCACHE_CTL_IC_EN;
-		if (!(mcache_ctl_val & V5_MCACHE_CTL_DC_EN))
-			mcache_ctl_val |= V5_MCACHE_CTL_DC_EN;
-		if (!(mcache_ctl_val & V5_MCACHE_CTL_CCTL_SUEN))
-			mcache_ctl_val |= V5_MCACHE_CTL_CCTL_SUEN;
 		csr_write(CSR_MCACHE_CTL, mcache_ctl_val);
 
 		/*
-		 * Check DC_COHEN_EN, if cannot write to mcache_ctl,
-		 * we assume this bitmap not support L2 CM
+		 * Check mcache_ctl.DC_COHEN, we assume this platform does
+		 * not support CM if the bit is hard-wired to 0.
 		 */
-		mcache_ctl_val = csr_read(CSR_MCACHE_CTL);
-		if ((mcache_ctl_val & V5_MCACHE_CTL_DC_COHEN_EN)) {
-		/* Wait for DC_COHSTA bit be set */
-			while (!(mcache_ctl_val & V5_MCACHE_CTL_DC_COHSTA_EN))
-				mcache_ctl_val = csr_read(CSR_MCACHE_CTL);
+		if (csr_read(CSR_MCACHE_CTL) & MCACHE_CTL_DC_COHEN) {
+			/* Wait for DC_COHSTA bit to be set */
+			while (!(csr_read(CSR_MCACHE_CTL)& MCACHE_CTL_DC_COHSTA));
 		}
 	}
 }
diff --git a/arch/riscv/include/asm/arch-andes/csr.h b/arch/riscv/include/asm/arch-andes/csr.h
new file mode 100644
index 0000000000..a03ccd5b3e
--- /dev/null
+++ b/arch/riscv/include/asm/arch-andes/csr.h
@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2023 Andes Technology Corporation
+ */
+
+#ifndef _ASM_ANDES_CSR_H
+#define _ASM_ANDES_CSR_H
+
+#include <asm/asm.h>
+#include <linux/const.h>
+
+#define CSR_MCACHE_CTL 0x7ca
+#define CSR_MMISC_CTL 0x7d0
+#define CSR_MARCHID 0xf12
+#define CSR_MCCTLCOMMAND 0x7cc
+
+#define MCACHE_CTL_IC_EN_OFFSET 0
+#define MCACHE_CTL_DC_EN_OFFSET 1
+#define MCACHE_CTL_DC_COHEN_OFFSET 19
+#define MCACHE_CTL_DC_COHSTA_OFFSET 20
+
+#define MCACHE_CTL_IC_EN BIT(MCACHE_CTL_IC_EN_OFFSET)
+#define MCACHE_CTL_DC_EN BIT(MCACHE_CTL_DC_EN_OFFSET)
+#define MCACHE_CTL_DC_COHEN BIT(MCACHE_CTL_DC_COHEN_OFFSET)
+#define MCACHE_CTL_DC_COHSTA BIT(MCACHE_CTL_DC_COHSTA_OFFSET)
+
+#define CCTL_L1D_WBINVAL_ALL 6
+
+#endif /* _ASM_ANDES_CSR_H */
-- 
2.34.1

Re: [PATCH v2 04/10] riscv: cpu: ax25: Simplify cache enabling logic in harts_early_init()

[Rick Chen]

> From: Peter Yu-Chien Lin(林宇謙) <peterlin@andestech.com>
> Sent: Monday, February 06, 2023 4:11 PM
> To: u-boot@lists.denx.de
> Cc: Leo Yu-Chi Liang(梁育齊) <ycliang@andestech.com>; Rick Jian-Zhi Chen(陳建志) <rick@andestech.com>; prabhakar.csengg@gmail.com; Peter Yu-Chien Lin(林宇謙) <peterlin@andestech.com>
> Subject: [PATCH v2 04/10] riscv: cpu: ax25: Simplify cache enabling logic in harts_early_init()
>
> As the OpenSBI v1.2 does not enable the cache [0], we enable the i/d-cache in harts_early_init() and do not disable in cleanup_before_linux(). This patch also simplifies the logic and moves the CSR encoding to include/asm/arch-andes/csr.h.
>
> [0] https://github.com/riscv-software-src/opensbi/commit/bd7ef4139829da5c30fa980f7498d385124408fa
>
> Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
> ---
>  arch/riscv/cpu/ax25/cpu.c               | 49 ++++++-------------------
>  arch/riscv/include/asm/arch-andes/csr.h | 29 +++++++++++++++
>  2 files changed, 41 insertions(+), 37 deletions(-)  create mode 100644 arch/riscv/include/asm/arch-andes/csr.h

Reviewed-by: Rick Chen <rick@andestech.com>

[PATCH v2 05/10] riscv: ae350: dts: Update L2 cache compatible string

[Yu Chien Peter Lin]

Update the compatible string of L2 cache.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
---
 arch/riscv/dts/ae350_32.dts | 2 +-
 arch/riscv/dts/ae350_64.dts | 2 +-
 drivers/cache/cache-v5l2.c  | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/riscv/dts/ae350_32.dts b/arch/riscv/dts/ae350_32.dts
index 96ef8bd8dd..61af6d5465 100644
--- a/arch/riscv/dts/ae350_32.dts
+++ b/arch/riscv/dts/ae350_32.dts
@@ -112,7 +112,7 @@
 	};
 
 	L2: l2-cache@e0500000 {
-		compatible = "v5l2cache";
+		compatible = "cache";
 		cache-level = <2>;
 		cache-size = <0x40000>;
 		reg = <0xe0500000 0x40000>;
diff --git a/arch/riscv/dts/ae350_64.dts b/arch/riscv/dts/ae350_64.dts
index cddbaec98a..8c7db29b4f 100644
--- a/arch/riscv/dts/ae350_64.dts
+++ b/arch/riscv/dts/ae350_64.dts
@@ -112,7 +112,7 @@
 	};
 
 	L2: l2-cache@e0500000 {
-		compatible = "v5l2cache";
+		compatible = "cache";
 		cache-level = <2>;
 		cache-size = <0x40000>;
 		reg = <0x0 0xe0500000 0x0 0x40000>;
diff --git a/drivers/cache/cache-v5l2.c b/drivers/cache/cache-v5l2.c
index e782430c57..c6d3a8f893 100644
--- a/drivers/cache/cache-v5l2.c
+++ b/drivers/cache/cache-v5l2.c
@@ -184,7 +184,7 @@ static int v5l2_probe(struct udevice *dev)
 }
 
 static const struct udevice_id v5l2_cache_ids[] = {
-	{ .compatible = "v5l2cache" },
+	{ .compatible = "cache" },
 	{}
 };
 
-- 
2.34.1

Re: [PATCH v2 05/10] riscv: ae350: dts: Update L2 cache compatible string

[Rick Chen]

> From: Peter Yu-Chien Lin(林宇謙) <peterlin@andestech.com>
> Sent: Monday, February 06, 2023 4:11 PM
> To: u-boot@lists.denx.de
> Cc: Leo Yu-Chi Liang(梁育齊) <ycliang@andestech.com>; Rick Jian-Zhi Chen(陳建志) <rick@andestech.com>; prabhakar.csengg@gmail.com; Peter Yu-Chien Lin(林宇謙) <peterlin@andestech.com>
> Subject: [PATCH v2 05/10] riscv: ae350: dts: Update L2 cache compatible string
>
> Update the compatible string of L2 cache.
>
> Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
> ---
>  arch/riscv/dts/ae350_32.dts | 2 +-
>  arch/riscv/dts/ae350_64.dts | 2 +-
>  drivers/cache/cache-v5l2.c  | 2 +-
>  3 files changed, 3 insertions(+), 3 deletions(-)

Reviewed-by: Rick Chen <rick@andestech.com>

[PATCH v2 06/10] riscv: ax25: cache.c: Cleanups to L1/L2 cache function used in SPL

[Yu Chien Peter Lin]

This patch refines L1 cache enable/disable and v5l2-cache enable
functions.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
---
 arch/riscv/cpu/ax25/cache.c | 98 +++++++++++++++++++++++++------------
 1 file changed, 68 insertions(+), 30 deletions(-)

diff --git a/arch/riscv/cpu/ax25/cache.c b/arch/riscv/cpu/ax25/cache.c
index 1c0c3772a1..40d77f671c 100644
--- a/arch/riscv/cpu/ax25/cache.c
+++ b/arch/riscv/cpu/ax25/cache.c
@@ -1,57 +1,51 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright (C) 2017 Andes Technology Corporation
+ * Copyright (C) 2023 Andes Technology Corporation
  * Rick Chen, Andes Technology Corporation <rick@andestech.com>
  */
 
+#include <asm/csr.h>
+#include <asm/asm.h>
 #include <common.h>
+#include <cache.h>
 #include <cpu_func.h>
 #include <dm.h>
-#include <asm/cache.h>
 #include <dm/uclass-internal.h>
-#include <cache.h>
-#include <asm/csr.h>
-
-#ifdef CONFIG_RISCV_NDS_CACHE
-#if CONFIG_IS_ENABLED(RISCV_MMODE)
-/* mcctlcommand */
-#define CCTL_REG_MCCTLCOMMAND_NUM	0x7cc
-
-/* D-cache operation */
-#define CCTL_L1D_WBINVAL_ALL	6
-#endif
-#endif
+#include <asm/arch-andes/csr.h>
 
 #ifdef CONFIG_V5L2_CACHE
-static void _cache_enable(void)
+void enable_caches(void)
 {
-	struct udevice *dev = NULL;
-
-	uclass_find_first_device(UCLASS_CACHE, &dev);
-
-	if (dev)
-		cache_enable(dev);
+	struct udevice *dev;
+	int ret;
+
+	ret = uclass_get_device_by_driver(UCLASS_CACHE,
+					  DM_DRIVER_GET(v5l2_cache),
+					  &dev);
+	if (ret) {
+		log_debug("Cannot enable v5l2 cache\n");
+	} else {
+		ret = cache_enable(dev);
+		if (ret)
+			log_debug("v5l2 cache enable failed\n");
+	}
 }
 
-static void _cache_disable(void)
+static void cache_ops(int (*ops)(struct udevice *dev))
 {
 	struct udevice *dev = NULL;
 
 	uclass_find_first_device(UCLASS_CACHE, &dev);
 
 	if (dev)
-		cache_disable(dev);
+		ops(dev);
 }
 #endif
 
 void flush_dcache_all(void)
 {
-#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
-#ifdef CONFIG_RISCV_NDS_CACHE
 #if CONFIG_IS_ENABLED(RISCV_MMODE)
-	csr_write(CCTL_REG_MCCTLCOMMAND_NUM, CCTL_L1D_WBINVAL_ALL);
-#endif
-#endif
+	csr_write(CSR_MCCTLCOMMAND, CCTL_L1D_WBINVAL_ALL);
 #endif
 }
 
@@ -67,26 +61,70 @@ void invalidate_dcache_range(unsigned long start, unsigned long end)
 
 void icache_enable(void)
 {
+#if CONFIG_IS_ENABLED(RISCV_MMODE)
+	asm volatile("csrsi %0, 0x1" :: "i"(CSR_MCACHE_CTL));
+#endif
 }
 
 void icache_disable(void)
 {
+#if CONFIG_IS_ENABLED(RISCV_MMODE)
+	asm volatile("csrci %0, 0x1" :: "i"(CSR_MCACHE_CTL));
+#endif
 }
 
 void dcache_enable(void)
 {
+#if CONFIG_IS_ENABLED(RISCV_MMODE)
+	asm volatile("csrsi %0, 0x2" :: "i"(CSR_MCACHE_CTL));
+#endif
+
+#ifdef CONFIG_V5L2_CACHE
+	cache_ops(cache_enable);
+#endif
 }
 
 void dcache_disable(void)
 {
+#if CONFIG_IS_ENABLED(RISCV_MMODE)
+	asm volatile("csrci %0, 0x2" :: "i"(CSR_MCACHE_CTL));
+#endif
+
+#ifdef CONFIG_V5L2_CACHE
+	cache_ops(cache_disable);
+#endif
 }
 
 int icache_status(void)
 {
-	return 0;
+	int ret = 0;
+
+#if CONFIG_IS_ENABLED(RISCV_MMODE)
+	asm volatile (
+		"csrr t1, %1\n\t"
+		"andi %0, t1, 0x01\n\t"
+		: "=r" (ret)
+		: "i"(CSR_MCACHE_CTL)
+		: "memory"
+	);
+#endif
+
+	return !!ret;
 }
 
 int dcache_status(void)
 {
-	return 0;
+	int ret = 0;
+
+#if CONFIG_IS_ENABLED(RISCV_MMODE)
+	asm volatile (
+		"csrr t1, %1\n\t"
+		"andi %0, t1, 0x02\n\t"
+		: "=r" (ret)
+		: "i" (CSR_MCACHE_CTL)
+		: "memory"
+	);
+#endif
+
+	return !!ret;
 }
-- 
2.34.1

Re: [PATCH v2 06/10] riscv: ax25: cache.c: Cleanups to L1/L2 cache function used in SPL

[Rick Chen]

> From: Peter Yu-Chien Lin(林宇謙) <peterlin@andestech.com>
> Sent: Monday, February 06, 2023 4:11 PM
> To: u-boot@lists.denx.de
> Cc: Leo Yu-Chi Liang(梁育齊) <ycliang@andestech.com>; Rick Jian-Zhi Chen(陳建志) <rick@andestech.com>; prabhakar.csengg@gmail.com; Peter Yu-Chien Lin(林宇謙) <peterlin@andestech.com>
> Subject: [PATCH v2 06/10] riscv: ax25: cache.c: Cleanups to L1/L2 cache function used in SPL
>
> This patch refines L1 cache enable/disable and v5l2-cache enable functions.
>
> Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
> ---
>  arch/riscv/cpu/ax25/cache.c | 98 +++++++++++++++++++++++++------------
>  1 file changed, 68 insertions(+), 30 deletions(-)

Reviewed-by: Rick Chen <rick@andestech.com>

[PATCH v2 07/10] configs: ae350: Enable v5l2 cache for AE350 platforms in SPL

[Yu Chien Peter Lin]

To reduce the code size, CONFIG_V5L2_CACHE was disabled since commit:
ca06444aac2c643db3a3f2eb37afc60fae15177e

Turing on does not significantly increase the size of u-boot-spl.bin,
so we enable it by default to improve performance.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
---
 arch/riscv/cpu/ax25/Kconfig          | 1 +
 configs/ae350_rv32_spl_defconfig     | 2 ++
 configs/ae350_rv32_spl_xip_defconfig | 2 ++
 configs/ae350_rv64_spl_defconfig     | 2 ++
 configs/ae350_rv64_spl_xip_defconfig | 2 ++
 5 files changed, 9 insertions(+)

diff --git a/arch/riscv/cpu/ax25/Kconfig b/arch/riscv/cpu/ax25/Kconfig
index eca68ea2a7..82bb5a2a53 100644
--- a/arch/riscv/cpu/ax25/Kconfig
+++ b/arch/riscv/cpu/ax25/Kconfig
@@ -6,6 +6,7 @@ config RISCV_NDS
 	imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE)
 	imply ANDES_PLICSW if (RISCV_MMODE || SPL_RISCV_MMODE)
 	imply ANDES_PLMT_TIMER if (RISCV_MMODE || SPL_RISCV_MMODE)
+	imply V5L2_CACHE
 	imply SPL_CPU
 	imply SPL_OPENSBI
 	imply SPL_LOAD_FIT
diff --git a/configs/ae350_rv32_spl_defconfig b/configs/ae350_rv32_spl_defconfig
index a66db65621..f5bd7a9a7e 100644
--- a/configs/ae350_rv32_spl_defconfig
+++ b/configs/ae350_rv32_spl_defconfig
@@ -22,6 +22,8 @@ CONFIG_BOOTDELAY=3
 CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_SPL_MAX_SIZE=0x100000
 CONFIG_SPL_BSS_START_ADDR=0x4000000
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_CACHE=y
 CONFIG_SYS_PBSIZE=1050
 CONFIG_SYS_BOOTM_LEN=0x4000000
 CONFIG_CMD_IMLS=y
diff --git a/configs/ae350_rv32_spl_xip_defconfig b/configs/ae350_rv32_spl_xip_defconfig
index 606962c0a7..014dcbedf6 100644
--- a/configs/ae350_rv32_spl_xip_defconfig
+++ b/configs/ae350_rv32_spl_xip_defconfig
@@ -23,6 +23,8 @@ CONFIG_BOOTDELAY=3
 CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_SPL_MAX_SIZE=0x100000
 CONFIG_SPL_BSS_START_ADDR=0x4000000
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_CACHE=y
 CONFIG_SYS_PBSIZE=1050
 CONFIG_SYS_BOOTM_LEN=0x4000000
 CONFIG_CMD_IMLS=y
diff --git a/configs/ae350_rv64_spl_defconfig b/configs/ae350_rv64_spl_defconfig
index f235db7990..51d23d050d 100644
--- a/configs/ae350_rv64_spl_defconfig
+++ b/configs/ae350_rv64_spl_defconfig
@@ -22,6 +22,8 @@ CONFIG_BOOTDELAY=3
 CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_SPL_MAX_SIZE=0x100000
 CONFIG_SPL_BSS_START_ADDR=0x4000000
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_CACHE=y
 CONFIG_SYS_PBSIZE=1050
 CONFIG_SYS_BOOTM_LEN=0x4000000
 CONFIG_CMD_IMLS=y
diff --git a/configs/ae350_rv64_spl_xip_defconfig b/configs/ae350_rv64_spl_xip_defconfig
index 4cbfd52fb1..c44df4b561 100644
--- a/configs/ae350_rv64_spl_xip_defconfig
+++ b/configs/ae350_rv64_spl_xip_defconfig
@@ -23,6 +23,8 @@ CONFIG_BOOTDELAY=3
 CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_SPL_MAX_SIZE=0x100000
 CONFIG_SPL_BSS_START_ADDR=0x4000000
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_CACHE=y
 CONFIG_SYS_PBSIZE=1050
 CONFIG_SYS_BOOTM_LEN=0x4000000
 CONFIG_CMD_IMLS=y
-- 
2.34.1

Re: [PATCH v2 07/10] configs: ae350: Enable v5l2 cache for AE350 platforms in SPL

[Rick Chen]

> From: Peter Yu-Chien Lin(林宇謙) <peterlin@andestech.com>
> Sent: Monday, February 06, 2023 4:11 PM
> To: u-boot@lists.denx.de
> Cc: Leo Yu-Chi Liang(梁育齊) <ycliang@andestech.com>; Rick Jian-Zhi Chen(陳建志) <rick@andestech.com>; prabhakar.csengg@gmail.com; Peter Yu-Chien Lin(林宇謙) <peterlin@andestech.com>
> Subject: [PATCH v2 07/10] configs: ae350: Enable v5l2 cache for AE350 platforms in SPL
>
> To reduce the code size, CONFIG_V5L2_CACHE was disabled since commit:
> ca06444aac2c643db3a3f2eb37afc60fae15177e
>
> Turing on does not significantly increase the size of u-boot-spl.bin, so we enable it by default to improve performance.
>
> Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
> ---
>  arch/riscv/cpu/ax25/Kconfig          | 1 +
>  configs/ae350_rv32_spl_defconfig     | 2 ++
>  configs/ae350_rv32_spl_xip_defconfig | 2 ++
>  configs/ae350_rv64_spl_defconfig     | 2 ++
>  configs/ae350_rv64_spl_xip_defconfig | 2 ++
>  5 files changed, 9 insertions(+)

Reviewed-by: Rick Chen <rick@andestech.com>

[PATCH v2 08/10] configs: ae350: Increase maximum retry count for AE350 platforms

[Yu Chien Peter Lin]

Loading an image via TFTP is often interrupted when retrying more than
10 times, increase the number of retries so that it does not simply stop
the transfer.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
---
 configs/ae350_rv32_defconfig         | 1 +
 configs/ae350_rv32_spl_defconfig     | 1 +
 configs/ae350_rv32_spl_xip_defconfig | 1 +
 configs/ae350_rv32_xip_defconfig     | 1 +
 configs/ae350_rv64_defconfig         | 1 +
 configs/ae350_rv64_spl_defconfig     | 1 +
 configs/ae350_rv64_spl_xip_defconfig | 1 +
 configs/ae350_rv64_xip_defconfig     | 1 +
 8 files changed, 8 insertions(+)

diff --git a/configs/ae350_rv32_defconfig b/configs/ae350_rv32_defconfig
index e5c8358e54..a9d158dc8d 100644
--- a/configs/ae350_rv32_defconfig
+++ b/configs/ae350_rv32_defconfig
@@ -26,6 +26,7 @@ CONFIG_CMD_CACHE=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_NET_RETRY_COUNT=50
 CONFIG_BOOTP_SEND_HOSTNAME=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_MMC=y
diff --git a/configs/ae350_rv32_spl_defconfig b/configs/ae350_rv32_spl_defconfig
index f5bd7a9a7e..54587018d5 100644
--- a/configs/ae350_rv32_spl_defconfig
+++ b/configs/ae350_rv32_spl_defconfig
@@ -34,6 +34,7 @@ CONFIG_BOOTP_PREFER_SERVERIP=y
 CONFIG_CMD_CACHE=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_NET_RETRY_COUNT=50
 CONFIG_BOOTP_SEND_HOSTNAME=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_MMC=y
diff --git a/configs/ae350_rv32_spl_xip_defconfig b/configs/ae350_rv32_spl_xip_defconfig
index 014dcbedf6..b626153723 100644
--- a/configs/ae350_rv32_spl_xip_defconfig
+++ b/configs/ae350_rv32_spl_xip_defconfig
@@ -35,6 +35,7 @@ CONFIG_BOOTP_PREFER_SERVERIP=y
 CONFIG_CMD_CACHE=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_NET_RETRY_COUNT=50
 CONFIG_BOOTP_SEND_HOSTNAME=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_MMC=y
diff --git a/configs/ae350_rv32_xip_defconfig b/configs/ae350_rv32_xip_defconfig
index 069a9d3982..628522cd4d 100644
--- a/configs/ae350_rv32_xip_defconfig
+++ b/configs/ae350_rv32_xip_defconfig
@@ -27,6 +27,7 @@ CONFIG_CMD_CACHE=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_NET_RETRY_COUNT=50
 CONFIG_BOOTP_SEND_HOSTNAME=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_MMC=y
diff --git a/configs/ae350_rv64_defconfig b/configs/ae350_rv64_defconfig
index c373b99b95..c058f76780 100644
--- a/configs/ae350_rv64_defconfig
+++ b/configs/ae350_rv64_defconfig
@@ -26,6 +26,7 @@ CONFIG_CMD_CACHE=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_NET_RETRY_COUNT=50
 CONFIG_BOOTP_SEND_HOSTNAME=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_MMC=y
diff --git a/configs/ae350_rv64_spl_defconfig b/configs/ae350_rv64_spl_defconfig
index 51d23d050d..9664baf705 100644
--- a/configs/ae350_rv64_spl_defconfig
+++ b/configs/ae350_rv64_spl_defconfig
@@ -34,6 +34,7 @@ CONFIG_BOOTP_PREFER_SERVERIP=y
 CONFIG_CMD_CACHE=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_NET_RETRY_COUNT=50
 CONFIG_BOOTP_SEND_HOSTNAME=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_MMC=y
diff --git a/configs/ae350_rv64_spl_xip_defconfig b/configs/ae350_rv64_spl_xip_defconfig
index c44df4b561..b754888409 100644
--- a/configs/ae350_rv64_spl_xip_defconfig
+++ b/configs/ae350_rv64_spl_xip_defconfig
@@ -35,6 +35,7 @@ CONFIG_BOOTP_PREFER_SERVERIP=y
 CONFIG_CMD_CACHE=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_NET_RETRY_COUNT=50
 CONFIG_BOOTP_SEND_HOSTNAME=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_MMC=y
diff --git a/configs/ae350_rv64_xip_defconfig b/configs/ae350_rv64_xip_defconfig
index 4fed2ead1d..380ae096ee 100644
--- a/configs/ae350_rv64_xip_defconfig
+++ b/configs/ae350_rv64_xip_defconfig
@@ -27,6 +27,7 @@ CONFIG_CMD_CACHE=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_NET_RETRY_COUNT=50
 CONFIG_BOOTP_SEND_HOSTNAME=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_MMC=y
-- 
2.34.1

[PATCH v2 09/10] configs: ae350: Display CPU and board info for AE350 platforms

[Yu Chien Peter Lin]

Display information about CPU and board during start up.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
---
 configs/ae350_rv32_defconfig         | 2 ++
 configs/ae350_rv32_spl_defconfig     | 2 ++
 configs/ae350_rv32_spl_xip_defconfig | 2 ++
 configs/ae350_rv32_xip_defconfig     | 2 ++
 configs/ae350_rv64_defconfig         | 2 ++
 configs/ae350_rv64_spl_defconfig     | 2 ++
 configs/ae350_rv64_spl_xip_defconfig | 2 ++
 configs/ae350_rv64_xip_defconfig     | 2 ++
 8 files changed, 16 insertions(+)

diff --git a/configs/ae350_rv32_defconfig b/configs/ae350_rv32_defconfig
index a9d158dc8d..fd1bf5fa4f 100644
--- a/configs/ae350_rv32_defconfig
+++ b/configs/ae350_rv32_defconfig
@@ -14,6 +14,8 @@ CONFIG_SYS_MONITOR_LEN=786432
 CONFIG_FIT=y
 CONFIG_SYS_MONITOR_BASE=0x88000000
 CONFIG_BOOTDELAY=3
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_DISPLAY_BOARDINFO=y
 CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_SYS_PBSIZE=1050
 CONFIG_SYS_BOOTM_LEN=0x4000000
diff --git a/configs/ae350_rv32_spl_defconfig b/configs/ae350_rv32_spl_defconfig
index 54587018d5..4d3623a894 100644
--- a/configs/ae350_rv32_spl_defconfig
+++ b/configs/ae350_rv32_spl_defconfig
@@ -19,6 +19,8 @@ CONFIG_FIT=y
 CONFIG_SPL_LOAD_FIT_ADDRESS=0x00200000
 CONFIG_SYS_MONITOR_BASE=0x88000000
 CONFIG_BOOTDELAY=3
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_DISPLAY_BOARDINFO=y
 CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_SPL_MAX_SIZE=0x100000
 CONFIG_SPL_BSS_START_ADDR=0x4000000
diff --git a/configs/ae350_rv32_spl_xip_defconfig b/configs/ae350_rv32_spl_xip_defconfig
index b626153723..a076b77834 100644
--- a/configs/ae350_rv32_spl_xip_defconfig
+++ b/configs/ae350_rv32_spl_xip_defconfig
@@ -20,6 +20,8 @@ CONFIG_FIT=y
 CONFIG_SPL_LOAD_FIT_ADDRESS=0x80010000
 CONFIG_SYS_MONITOR_BASE=0x88000000
 CONFIG_BOOTDELAY=3
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_DISPLAY_BOARDINFO=y
 CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_SPL_MAX_SIZE=0x100000
 CONFIG_SPL_BSS_START_ADDR=0x4000000
diff --git a/configs/ae350_rv32_xip_defconfig b/configs/ae350_rv32_xip_defconfig
index 628522cd4d..da1bd2b10b 100644
--- a/configs/ae350_rv32_xip_defconfig
+++ b/configs/ae350_rv32_xip_defconfig
@@ -15,6 +15,8 @@ CONFIG_SYS_MONITOR_LEN=786432
 CONFIG_FIT=y
 CONFIG_SYS_MONITOR_BASE=0x88000000
 CONFIG_BOOTDELAY=3
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_DISPLAY_BOARDINFO=y
 CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_SYS_PBSIZE=1050
 CONFIG_SYS_BOOTM_LEN=0x4000000
diff --git a/configs/ae350_rv64_defconfig b/configs/ae350_rv64_defconfig
index c058f76780..959258176a 100644
--- a/configs/ae350_rv64_defconfig
+++ b/configs/ae350_rv64_defconfig
@@ -14,6 +14,8 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xfffd70
 CONFIG_FIT=y
 CONFIG_SYS_MONITOR_BASE=0x88000000
 CONFIG_BOOTDELAY=3
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_DISPLAY_BOARDINFO=y
 CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_SYS_PBSIZE=1050
 CONFIG_SYS_BOOTM_LEN=0x4000000
diff --git a/configs/ae350_rv64_spl_defconfig b/configs/ae350_rv64_spl_defconfig
index 9664baf705..0217027e6d 100644
--- a/configs/ae350_rv64_spl_defconfig
+++ b/configs/ae350_rv64_spl_defconfig
@@ -19,6 +19,8 @@ CONFIG_FIT=y
 CONFIG_SPL_LOAD_FIT_ADDRESS=0x00200000
 CONFIG_SYS_MONITOR_BASE=0x88000000
 CONFIG_BOOTDELAY=3
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_DISPLAY_BOARDINFO=y
 CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_SPL_MAX_SIZE=0x100000
 CONFIG_SPL_BSS_START_ADDR=0x4000000
diff --git a/configs/ae350_rv64_spl_xip_defconfig b/configs/ae350_rv64_spl_xip_defconfig
index b754888409..5a1fa8b6a1 100644
--- a/configs/ae350_rv64_spl_xip_defconfig
+++ b/configs/ae350_rv64_spl_xip_defconfig
@@ -20,6 +20,8 @@ CONFIG_FIT=y
 CONFIG_SPL_LOAD_FIT_ADDRESS=0x80010000
 CONFIG_SYS_MONITOR_BASE=0x88000000
 CONFIG_BOOTDELAY=3
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_DISPLAY_BOARDINFO=y
 CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_SPL_MAX_SIZE=0x100000
 CONFIG_SPL_BSS_START_ADDR=0x4000000
diff --git a/configs/ae350_rv64_xip_defconfig b/configs/ae350_rv64_xip_defconfig
index 380ae096ee..c3fcbf3d28 100644
--- a/configs/ae350_rv64_xip_defconfig
+++ b/configs/ae350_rv64_xip_defconfig
@@ -15,6 +15,8 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xfffd70
 CONFIG_FIT=y
 CONFIG_SYS_MONITOR_BASE=0x88000000
 CONFIG_BOOTDELAY=3
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_DISPLAY_BOARDINFO=y
 CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_SYS_PBSIZE=1050
 CONFIG_SYS_BOOTM_LEN=0x4000000
-- 
2.34.1

Re: [PATCH v2 09/10] configs: ae350: Display CPU and board info for AE350 platforms

[Rick Chen]

> From: Peter Yu-Chien Lin(林宇謙) <peterlin@andestech.com>
> Sent: Monday, February 06, 2023 4:11 PM
> To: u-boot@lists.denx.de
> Cc: Leo Yu-Chi Liang(梁育齊) <ycliang@andestech.com>; Rick Jian-Zhi Chen(陳建志) <rick@andestech.com>; prabhakar.csengg@gmail.com; Peter Yu-Chien Lin(林宇謙) <peterlin@andestech.com>
> Subject: [PATCH v2 09/10] configs: ae350: Display CPU and board info for AE350 platforms
>
> Display information about CPU and board during start up.
>
> Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
> ---
>  configs/ae350_rv32_defconfig         | 2 ++
>  configs/ae350_rv32_spl_defconfig     | 2 ++
>  configs/ae350_rv32_spl_xip_defconfig | 2 ++
>  configs/ae350_rv32_xip_defconfig     | 2 ++
>  configs/ae350_rv64_defconfig         | 2 ++
>  configs/ae350_rv64_spl_defconfig     | 2 ++
>  configs/ae350_rv64_spl_xip_defconfig | 2 ++
>  configs/ae350_rv64_xip_defconfig     | 2 ++
>  8 files changed, 16 insertions(+)

Reviewed-by: Rick Chen <rick@andestech.com>

[PATCH v2 10/10] driver: cache-v5l2: Fix type casting warning on RV32

[Yu Chien Peter Lin]

This patch fixes following warning for the riscv32 toolchain.

drivers/cache/cache-v5l2.c:122:16: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
  122 |         regs = (struct l2cache *)dev_read_addr(dev);
      |                ^

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
---
 drivers/cache/cache-v5l2.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/cache/cache-v5l2.c b/drivers/cache/cache-v5l2.c
index c6d3a8f893..eda07d3f29 100644
--- a/drivers/cache/cache-v5l2.c
+++ b/drivers/cache/cache-v5l2.c
@@ -119,7 +119,7 @@ static int v5l2_of_to_plat(struct udevice *dev)
 	struct v5l2_plat *plat = dev_get_plat(dev);
 	struct l2cache *regs;
 
-	regs = (struct l2cache *)dev_read_addr(dev);
+	regs = (struct l2cache *)(uintptr_t)dev_read_addr(dev);
 	plat->regs = regs;
 
 	plat->iprefetch = -EINVAL;
-- 
2.34.1