[PATCH 3/5] clk/qcom: apq8096: fix the sdhci clock

[PATCH 3/5] clk/qcom: apq8096: fix the sdhci clock

[Jorge Ramirez-Ortiz]

Select the right clock for sdhci.

Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
---
 drivers/clk/qcom/clock-apq8096.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/qcom/clock-apq8096.c b/drivers/clk/qcom/clock-apq8096.c
index bc00826a5e8..551f52d5197 100644
--- a/drivers/clk/qcom/clock-apq8096.c
+++ b/drivers/clk/qcom/clock-apq8096.c
@@ -83,7 +83,7 @@ static ulong apq8096_clk_set_rate(struct clk *clk, ulong rate)
 	struct msm_clk_priv *priv = dev_get_priv(clk->dev);
 
 	switch (clk->id) {
-	case GCC_SDCC1_APPS_CLK: /* SDC1 */
+	case GCC_SDCC2_APPS_CLK: /* SDC2 */
 		return clk_init_sdc(priv, rate);
 		break;
 	case GCC_BLSP2_UART2_APPS_CLK: /*UART2*/
-- 
2.34.1

Re: [PATCH 3/5] clk/qcom: apq8096: fix the sdhci clock

[neil.armstrong]

On 07/04/2025 14:05, Jorge Ramirez-Ortiz wrote:
> Select the right clock for sdhci.
> 
> Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com>
> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
> ---
>   drivers/clk/qcom/clock-apq8096.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/qcom/clock-apq8096.c b/drivers/clk/qcom/clock-apq8096.c
> index bc00826a5e8..551f52d5197 100644
> --- a/drivers/clk/qcom/clock-apq8096.c
> +++ b/drivers/clk/qcom/clock-apq8096.c
> @@ -83,7 +83,7 @@ static ulong apq8096_clk_set_rate(struct clk *clk, ulong rate)
>   	struct msm_clk_priv *priv = dev_get_priv(clk->dev);
>   
>   	switch (clk->id) {
> -	case GCC_SDCC1_APPS_CLK: /* SDC1 */
> +	case GCC_SDCC2_APPS_CLK: /* SDC2 */

Should be GCC_SDCC2_AHB_CLK

>   		return clk_init_sdc(priv, rate);
>   		break;
>   	case GCC_BLSP2_UART2_APPS_CLK: /*UART2*/

Re: [PATCH 3/5] clk/qcom: apq8096: fix the sdhci clock

[Jorge Ramirez]

On 07/04/25 14:36:51, neil.armstrong@linaro.org wrote:
> On 07/04/2025 14:05, Jorge Ramirez-Ortiz wrote:
> > Select the right clock for sdhci.
> > 
> > Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com>
> > Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
> > ---
> >   drivers/clk/qcom/clock-apq8096.c | 2 +-
> >   1 file changed, 1 insertion(+), 1 deletion(-)
> > 
> > diff --git a/drivers/clk/qcom/clock-apq8096.c b/drivers/clk/qcom/clock-apq8096.c
> > index bc00826a5e8..551f52d5197 100644
> > --- a/drivers/clk/qcom/clock-apq8096.c
> > +++ b/drivers/clk/qcom/clock-apq8096.c
> > @@ -83,7 +83,7 @@ static ulong apq8096_clk_set_rate(struct clk *clk, ulong rate)
> >   	struct msm_clk_priv *priv = dev_get_priv(clk->dev);
> >   	switch (clk->id) {
> > -	case GCC_SDCC1_APPS_CLK: /* SDC1 */
> > +	case GCC_SDCC2_APPS_CLK: /* SDC2 */
> 
> Should be GCC_SDCC2_AHB_CLK

why? also if I do that, mcc fails to probe

> 
> >   		return clk_init_sdc(priv, rate);
> >   		break;
> >   	case GCC_BLSP2_UART2_APPS_CLK: /*UART2*/
> 

Re: [PATCH 3/5] clk/qcom: apq8096: fix the sdhci clock

[Caleb Connolly]

On 4/7/25 16:17, Jorge Ramirez wrote:
> On 07/04/25 14:36:51, neil.armstrong@linaro.org wrote:
>> On 07/04/2025 14:05, Jorge Ramirez-Ortiz wrote:
>>> Select the right clock for sdhci.
>>>
>>> Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com>
>>> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
>>> ---
>>>    drivers/clk/qcom/clock-apq8096.c | 2 +-
>>>    1 file changed, 1 insertion(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/clk/qcom/clock-apq8096.c b/drivers/clk/qcom/clock-apq8096.c
>>> index bc00826a5e8..551f52d5197 100644
>>> --- a/drivers/clk/qcom/clock-apq8096.c
>>> +++ b/drivers/clk/qcom/clock-apq8096.c
>>> @@ -83,7 +83,7 @@ static ulong apq8096_clk_set_rate(struct clk *clk, ulong rate)
>>>    	struct msm_clk_priv *priv = dev_get_priv(clk->dev);
>>>    	switch (clk->id) {
>>> -	case GCC_SDCC1_APPS_CLK: /* SDC1 */
>>> +	case GCC_SDCC2_APPS_CLK: /* SDC2 */
>>
>> Should be GCC_SDCC2_AHB_CLK
> 
> why? also if I do that, mcc fails to probe

GCC_SDCC2_APPS_CLK is correct, that's the "core" clock and the one the 
sdhci_msm driver calls clk_set_rate() on. So this patch is good. I 
suspect the misuse of GCC_SDCC1_APPS_CLK is from way back when this 
board had a custom DT that didn't follow upstream.

Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org>>
>>
>>>    		return clk_init_sdc(priv, rate);
>>>    		break;
>>>    	case GCC_BLSP2_UART2_APPS_CLK: /*UART2*/
>>

-- 
Caleb (they/them)

Re: [PATCH 3/5] clk/qcom: apq8096: fix the sdhci clock

[neil.armstrong]

On 07/04/2025 16:17, Jorge Ramirez wrote:
> On 07/04/25 14:36:51, neil.armstrong@linaro.org wrote:
>> On 07/04/2025 14:05, Jorge Ramirez-Ortiz wrote:
>>> Select the right clock for sdhci.
>>>
>>> Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com>
>>> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
>>> ---
>>>    drivers/clk/qcom/clock-apq8096.c | 2 +-
>>>    1 file changed, 1 insertion(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/clk/qcom/clock-apq8096.c b/drivers/clk/qcom/clock-apq8096.c
>>> index bc00826a5e8..551f52d5197 100644
>>> --- a/drivers/clk/qcom/clock-apq8096.c
>>> +++ b/drivers/clk/qcom/clock-apq8096.c
>>> @@ -83,7 +83,7 @@ static ulong apq8096_clk_set_rate(struct clk *clk, ulong rate)
>>>    	struct msm_clk_priv *priv = dev_get_priv(clk->dev);
>>>    	switch (clk->id) {
>>> -	case GCC_SDCC1_APPS_CLK: /* SDC1 */
>>> +	case GCC_SDCC2_APPS_CLK: /* SDC2 */
>>
>> Should be GCC_SDCC2_AHB_CLK
> 
> why? also if I do that, mcc fails to probe

The discussion at https://lore.kernel.org/all/Z/OqoqnPb1gfk5iG@trex/ made me thought using GCC_SDCC2_AHB_CLK fixed the sdhci set_rate, but I maybe did misread.

Neil

> 
>>
>>>    		return clk_init_sdc(priv, rate);
>>>    		break;
>>>    	case GCC_BLSP2_UART2_APPS_CLK: /*UART2*/
>>

Re: [PATCH 3/5] clk/qcom: apq8096: fix the sdhci clock

[Jorge Ramirez]

On 07/04/25 17:12:45, neil.armstrong@linaro.org wrote:
> On 07/04/2025 16:17, Jorge Ramirez wrote:
> > On 07/04/25 14:36:51, neil.armstrong@linaro.org wrote:
> > > On 07/04/2025 14:05, Jorge Ramirez-Ortiz wrote:
> > > > Select the right clock for sdhci.
> > > > 
> > > > Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com>
> > > > Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
> > > > ---
> > > >    drivers/clk/qcom/clock-apq8096.c | 2 +-
> > > >    1 file changed, 1 insertion(+), 1 deletion(-)
> > > > 
> > > > diff --git a/drivers/clk/qcom/clock-apq8096.c b/drivers/clk/qcom/clock-apq8096.c
> > > > index bc00826a5e8..551f52d5197 100644
> > > > --- a/drivers/clk/qcom/clock-apq8096.c
> > > > +++ b/drivers/clk/qcom/clock-apq8096.c
> > > > @@ -83,7 +83,7 @@ static ulong apq8096_clk_set_rate(struct clk *clk, ulong rate)
> > > >    	struct msm_clk_priv *priv = dev_get_priv(clk->dev);
> > > >    	switch (clk->id) {
> > > > -	case GCC_SDCC1_APPS_CLK: /* SDC1 */
> > > > +	case GCC_SDCC2_APPS_CLK: /* SDC2 */
> > > 
> > > Should be GCC_SDCC2_AHB_CLK
> > 
> > why? also if I do that, mcc fails to probe
> 
> The discussion at https://lore.kernel.org/all/Z/OqoqnPb1gfk5iG@trex/ made me thought using GCC_SDCC2_AHB_CLK fixed the sdhci set_rate, but I maybe did misread.
> 
> Neil

can I add your review/acked?

> 
> > 
> > > 
> > > >    		return clk_init_sdc(priv, rate);
> > > >    		break;
> > > >    	case GCC_BLSP2_UART2_APPS_CLK: /*UART2*/
> > > 
> 

[PATCH 1/5] board: qualcomm: dragonboard820c: update readme

[Jorge Ramirez-Ortiz]

Update build instructions.

Be sure to use the u-boot-nodtb.bin image, as the Snapdragon platform
prioritizes the embedded Device Tree Blob (DTB) when present, rather
than the external one. The external DTB—modified by LK—is the version
required by the DB820c.

Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Christopher Obbard <christopher.obbard@linaro.org>
Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org>>
---
 board/qualcomm/dragonboard820c/readme.txt | 47 ++++++++++-------------
 1 file changed, 21 insertions(+), 26 deletions(-)

diff --git a/board/qualcomm/dragonboard820c/readme.txt b/board/qualcomm/dragonboard820c/readme.txt
index 966e9520e85..a01d24122cb 100644
--- a/board/qualcomm/dragonboard820c/readme.txt
+++ b/board/qualcomm/dragonboard820c/readme.txt
@@ -16,10 +16,7 @@
                      Build & Run instructions
 ================================================================================
 
-1) Install mkbootimg and dtbTool from Codeaurora:
-
-   git://codeaurora.org/quic/kernel/skales
-   commit 8492547e404e969262d9070dee9bdd15668bb70f worked for me.
+1) Install mkbootimg
 
 2) Setup CROSS_COMPILE to aarch64 compiler or if you use ccache just do
    CROSS_COMPILE="ccache aarch64-linux-gnu-"
@@ -33,15 +30,15 @@
 
    $ touch rd
 
-5) Generate qualcomm device tree table with dtbTool
+5) Append the dtb to the u-boot binary discarding the internal dtb.
 
-   $ dtbTool -o dt.img arch/arm/dts
+   $ gzip u-boot-nodtb.bin
+   $ cat u-boot.dtb >> u-boot-nodtb.bin.gz
 
 6) Generate Android boot image with mkbootimg:
 
-   $ mkbootimg --kernel=u-boot-dtb.bin             \
+   $ mkbootimg --kernel=u-boot-nodtb.bin.gz          \
                --output=u-boot.img                 \
-               --dt=dt.img                         \
                --pagesize 4096                     \
                --base 0x80000000                   \
                --ramdisk=rd                        \
@@ -251,44 +248,42 @@ Wait for 5 seconds before proceeding
 [5300] booting linux @ 0x80080000, ramdisk @ 0x82200000 (0), tags/device tree @ 0x82000000
 [5310] Jumping to kernel via monitor
 
-U-Boot 2017.11-00145-ge895117 (Nov 29 2017 - 10:04:06 +0100)
+U-Boot 2025.04-rc5-00020-g40a61ca0e7eb-dirty (Apr 07 2025 - 09:37:03 +0200)
 Qualcomm-DragonBoard 820C
 
-DRAM:  3 GiB
-PSCI:  v1.0
-MMC:   sdhci@74a4900: 0
+DRAM:  3.5 GiB (effective 3 GiB)
+Core:  136 devices, 18 uclasses, devicetree: board
+MMC:   Bulk clocks not available (-19), trying core clock
+mmc@74a4900: 0
+Loading Environment from EXT4... OK
 In:    serial@75b0000
 Out:   serial@75b0000
 Err:   serial@75b0000
-Net:   Net Initialization Skipped
-No ethernet found.
+Net:   No ethernet found.
 Hit any key to stop autoboot:  0
 switch to partitions #0, OK
 mmc0 is current device
 Scanning mmc 0:1...
 Found /extlinux/extlinux.conf
 Retrieving file: /extlinux/extlinux.conf
-433 bytes read in 71 ms (5.9 KiB/s)
 1:      nfs root
-
+Enter choice: 1:        nfs root
 Retrieving file: /uImage
-19397184 bytes read in 2024 ms (9.1 MiB/s)
-append: root=/dev/nfs rw nfsroot=192.168.1.2:/db820c/rootfs,v3,tcp rootwait ip=dhcp consoleblank=0 console=tty0 console=ttyMSM0,115200n8 earlyprintk earlycon=msm_serial_dm,0x75b0000 androidboot.bootdevice=624000.ufshc androidboot.verifiedbootstate=orange androidboot.ver0
-
+append: root=/dev/nfs rw nfsroot=192.168.1.6:/home/jramirez/Src/qualcomm-lt/db820c/rootfs,v3,tcp rootwait ip=dhcp consoleblank=0 console=tty0 console=ttyMSM0,115200n8 earlyprintk earlyco0
 Retrieving file: /apq8096-db820c.dtb
-38134 bytes read in 37 ms (1005.9 KiB/s)
-
-## Booting kernel from Legacy Image at 95000000 ...
+## Booting kernel from Legacy Image at 155000000 ...
    Image Name:   Dragonboard820c
    Image Type:   AArch64 Linux Kernel Image (uncompressed)
    Data Size:    19397120 Bytes = 18.5 MiB
    Load Address: 80080000
    Entry Point:  80080000
    Verifying Checksum ... OK
-## Flattened Device Tree blob at 93000000
-   Booting using the fdt blob at 0x93000000
-   Loading Kernel Image ... OK
-   Using Device Tree in place at 0000000093000000, end 000000009300c4f5
+## Flattened Device Tree blob at 148600000
+   Booting using the fdt blob at 0x148600000
+Working FDT set to 148600000
+   Loading Kernel Image to 80080000
+   Using Device Tree in place at 0000000148600000, end 000000014860c4f5
+Working FDT set to 148600000
 
 Starting kernel ...
 
-- 
2.34.1

[PATCH 2/5] clk/qcom: apq8096: fix set rate for the uart clock

[Jorge Ramirez-Ortiz]

The function should return a valid rate.

Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org>
---
 drivers/clk/qcom/clock-apq8096.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/qcom/clock-apq8096.c b/drivers/clk/qcom/clock-apq8096.c
index c77d69128b0..bc00826a5e8 100644
--- a/drivers/clk/qcom/clock-apq8096.c
+++ b/drivers/clk/qcom/clock-apq8096.c
@@ -87,7 +87,8 @@ static ulong apq8096_clk_set_rate(struct clk *clk, ulong rate)
 		return clk_init_sdc(priv, rate);
 		break;
 	case GCC_BLSP2_UART2_APPS_CLK: /*UART2*/
-		return clk_init_uart(priv);
+		clk_init_uart(priv);
+		return 7372800;
 	default:
 		return 0;
 	}
-- 
2.34.1

[PATCH 3/5] clk/qcom: apq8096: fix the sdhci clock

[Jorge Ramirez-Ortiz]

Select the right clock for sdhci.

Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com>
Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org>
---
 drivers/clk/qcom/clock-apq8096.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/qcom/clock-apq8096.c b/drivers/clk/qcom/clock-apq8096.c
index bc00826a5e8..551f52d5197 100644
--- a/drivers/clk/qcom/clock-apq8096.c
+++ b/drivers/clk/qcom/clock-apq8096.c
@@ -83,7 +83,7 @@ static ulong apq8096_clk_set_rate(struct clk *clk, ulong rate)
 	struct msm_clk_priv *priv = dev_get_priv(clk->dev);
 
 	switch (clk->id) {
-	case GCC_SDCC1_APPS_CLK: /* SDC1 */
+	case GCC_SDCC2_APPS_CLK: /* SDC2 */
 		return clk_init_sdc(priv, rate);
 		break;
 	case GCC_BLSP2_UART2_APPS_CLK: /*UART2*/
-- 
2.34.1

[PATCH 4/5] clk: stub: add qcom,glink-smd-rpm

[Jorge Ramirez-Ortiz]

Add support for the resource power manager clocks over SMD/GLINK to be
stubbed.

Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com>
Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
---
 drivers/clk/clk-stub.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/clk-stub.c b/drivers/clk/clk-stub.c
index 5fbbb07b7f7..38ed0d094fa 100644
--- a/drivers/clk/clk-stub.c
+++ b/drivers/clk/clk-stub.c
@@ -14,7 +14,7 @@
 static const struct udevice_id nop_parent_ids[] = {
 	{ .compatible = "qcom,rpm-proc" },
 	{ .compatible = "qcom,glink-rpm" },
-	{ .compatible = "qcom,rpm-sm6115" },
+	{ .compatible = "qcom,glink-smd-rpm" },
 	{ }
 };
 
-- 
2.34.1

[PATCH 5/5] configs: dragonboard820: updates

[Jorge Ramirez-Ortiz]

Configure GPIO and CLK_STUBS
CLK_STUBS is required for MMC initialization

Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
---
 configs/dragonboard820c_defconfig | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/configs/dragonboard820c_defconfig b/configs/dragonboard820c_defconfig
index e29bea7deb2..2a5b7212f74 100644
--- a/configs/dragonboard820c_defconfig
+++ b/configs/dragonboard820c_defconfig
@@ -45,4 +45,6 @@ CONFIG_PINCTRL_QCOM_APQ8096=y
 CONFIG_DM_PMIC=y
 CONFIG_PMIC_QCOM=y
 CONFIG_MSM_SERIAL=y
+CONFIG_MSM_GPIO=y
 CONFIG_SPMI_MSM=y
+CONFIG_CLK_STUB=y
-- 
2.34.1

Re: [PATCH 4/5] clk: stub: add qcom,glink-smd-rpm

[Caleb Connolly]

On 4/7/25 19:56, Jorge Ramirez-Ortiz wrote:
> Add support for the resource power manager clocks over SMD/GLINK to be
> stubbed.
> 
> Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com>
> Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>

Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org>

Thanks!> ---
>   drivers/clk/clk-stub.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/clk-stub.c b/drivers/clk/clk-stub.c
> index 5fbbb07b7f7..38ed0d094fa 100644
> --- a/drivers/clk/clk-stub.c
> +++ b/drivers/clk/clk-stub.c
> @@ -14,7 +14,7 @@
>   static const struct udevice_id nop_parent_ids[] = {
>   	{ .compatible = "qcom,rpm-proc" },
>   	{ .compatible = "qcom,glink-rpm" },
> -	{ .compatible = "qcom,rpm-sm6115" },
> +	{ .compatible = "qcom,glink-smd-rpm" },
>   	{ }
>   };
>   

-- 
Caleb (they/them)

Re: [PATCH 5/5] configs: dragonboard820: updates

[Caleb Connolly]

On 4/7/25 19:56, Jorge Ramirez-Ortiz wrote:
> Configure GPIO and CLK_STUBS
> CLK_STUBS is required for MMC initialization
> 
> Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com>
> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>

Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org>> ---
>   configs/dragonboard820c_defconfig | 2 ++
>   1 file changed, 2 insertions(+)
> 
> diff --git a/configs/dragonboard820c_defconfig b/configs/dragonboard820c_defconfig
> index e29bea7deb2..2a5b7212f74 100644
> --- a/configs/dragonboard820c_defconfig
> +++ b/configs/dragonboard820c_defconfig
> @@ -45,4 +45,6 @@ CONFIG_PINCTRL_QCOM_APQ8096=y
>   CONFIG_DM_PMIC=y
>   CONFIG_PMIC_QCOM=y
>   CONFIG_MSM_SERIAL=y
> +CONFIG_MSM_GPIO=y
>   CONFIG_SPMI_MSM=y
> +CONFIG_CLK_STUB=y

-- 
Caleb (they/them)

Re: [PATCH 1/5] board: qualcomm: dragonboard820c: update readme

[Caleb Connolly]

On Mon, 07 Apr 2025 19:56:13 +0200, Jorge Ramirez-Ortiz wrote:
> Update build instructions.
> 
> Be sure to use the u-boot-nodtb.bin image, as the Snapdragon platform
> prioritizes the embedded Device Tree Blob (DTB) when present, rather
> than the external one. The external DTB—modified by LK—is the version
> required by the DB820c.
> 
> [...]

Applied, thanks!

[1/5] board: qualcomm: dragonboard820c: update readme
      https://source.denx.de/u-boot/custodians/u-boot-snapdragon/-/commit/805d2d4d3662
[2/5] clk/qcom: apq8096: fix set rate for the uart clock
      https://source.denx.de/u-boot/custodians/u-boot-snapdragon/-/commit/5cbc99a3119f
[3/5] clk/qcom: apq8096: fix the sdhci clock
      https://source.denx.de/u-boot/custodians/u-boot-snapdragon/-/commit/ed3417741fdd
[4/5] clk: stub: add qcom,glink-smd-rpm
      https://source.denx.de/u-boot/custodians/u-boot-snapdragon/-/commit/1a3a35c1fb35
[5/5] configs: dragonboard820: updates
      https://source.denx.de/u-boot/custodians/u-boot-snapdragon/-/commit/e4ffc6a32358

Best regards,
-- 
Caleb Connolly <caleb.connolly@linaro.org>