[PATCH 00/10] Add RK3368 YMD8_MB board support

[PATCH 00/10] Add RK3368 YMD8_MB board support

[WeiHao Li]

YMD8_MB is an RK3368-based board purchased from Xianyu, a Chinese secondhand
marketplace. It comes with 1GB RAM, 8GB eMMC, and an 8-inch MIPI display.
Detailed information about this board is documented on the following link.

https://ieiao.github.io/wiki/embedded-dev/rockchip/rk3368

This series of patches aims to add missing drivers for the RK3368 and enable
VOP driver support, making U-Boot initially usable on this board.

The VOP driver modifications are based on the following repository.

https://github.com/muratdemirtas/rockchip-rk3399-uboot-mipi-dsi

The original repository for this series of patches can be found at

https://github.com/ieiao/u-boot/tree/ymd8_mb

WeiHao Li (10):
  clk: rockchip: rk3368: fix gmac clock error
  mmc: rockchip: fix clock get wrong index
  net: rockchip: rk3368: add set_to_rmii
  clk: rockchip: rk3368: Add bus clk get/set
  clk: rockchip: rk3368: Adjust pll clk get
  clk: rockchip: rk3368: Add vop clk get/set
  video: rockchip: vop add bridge support
  video: rockchip: add rk3368 vop support
  video: panel: add rm72014 panel support
  board: rockchip: add rk3368 ymd8_mb support

 arch/arm/dts/Makefile                         |   1 +
 arch/arm/dts/rk3368-ymd8-mb-u-boot.dtsi       |  44 +++
 arch/arm/dts/rk3368-ymd8-mb.dts               | 326 +++++++++++++++++
 arch/arm/dts/rk3368.dtsi                      | 258 +++++++++++++
 .../include/asm/arch-rockchip/cru_rk3368.h    |  65 ++++
 .../include/asm/arch-rockchip/grf_rk3368.h    | 111 +++++-
 arch/arm/mach-rockchip/rk3368/Kconfig         |   6 +
 board/rockchip/ymd8_mb/Kconfig                |  12 +
 board/rockchip/ymd8_mb/MAINTAINERS            |   6 +
 board/rockchip/ymd8_mb/Makefile               |   7 +
 board/rockchip/ymd8_mb/README                 |   1 +
 board/rockchip/ymd8_mb/ymd8_mb_rk3368.c       |  19 +
 configs/ymd8-mb_defconfig                     |  72 ++++
 drivers/clk/rockchip/clk_rk3368.c             | 338 +++++++++++++++++-
 drivers/mmc/rockchip_dw_mmc.c                 |   2 +-
 drivers/net/gmac_rockchip.c                   |  17 +
 drivers/video/Kconfig                         |   7 +
 drivers/video/Makefile                        |   1 +
 drivers/video/rm72014.c                       | 199 +++++++++++
 drivers/video/rockchip/Makefile               |   1 +
 drivers/video/rockchip/dw_mipi_dsi_rockchip.c |  20 ++
 drivers/video/rockchip/rk3368_vop.c           |  81 +++++
 drivers/video/rockchip/rk_vop.c               |  92 +++--
 .../include/dt-bindings/clock/rk3368-cru.h    |   1 +
 include/configs/ymd8_mb.h                     |  11 +
 25 files changed, 1668 insertions(+), 30 deletions(-)
 create mode 100644 arch/arm/dts/rk3368-ymd8-mb-u-boot.dtsi
 create mode 100644 arch/arm/dts/rk3368-ymd8-mb.dts
 create mode 100644 board/rockchip/ymd8_mb/Kconfig
 create mode 100644 board/rockchip/ymd8_mb/MAINTAINERS
 create mode 100644 board/rockchip/ymd8_mb/Makefile
 create mode 100644 board/rockchip/ymd8_mb/README
 create mode 100644 board/rockchip/ymd8_mb/ymd8_mb_rk3368.c
 create mode 100644 configs/ymd8-mb_defconfig
 create mode 100644 drivers/video/rm72014.c
 create mode 100644 drivers/video/rockchip/rk3368_vop.c
 create mode 100644 include/configs/ymd8_mb.h

-- 
2.39.5

[PATCH 01/10] clk: rockchip: rk3368: fix gmac clock error

[WeiHao Li]

Signed-off-by: WeiHao Li <ieiao@outlook.com>
---
 drivers/clk/rockchip/clk_rk3368.c | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/drivers/clk/rockchip/clk_rk3368.c b/drivers/clk/rockchip/clk_rk3368.c
index 630253fbb1..6691801384 100644
--- a/drivers/clk/rockchip/clk_rk3368.c
+++ b/drivers/clk/rockchip/clk_rk3368.c
@@ -329,11 +329,9 @@ static ulong rk3368_gmac_set_clk(struct rk3368_cru *cru, ulong set_rate)
 		ulong pll_rate;
 		u8 div;
 
-		if (((con >> GMAC_PLL_SHIFT) & GMAC_PLL_MASK) ==
-		    GMAC_PLL_SELECT_GENERAL)
+		if ((con & GMAC_PLL_MASK) == GMAC_PLL_SELECT_GENERAL)
 			pll_rate = GPLL_HZ;
-		else if (((con >> GMAC_PLL_SHIFT) & GMAC_PLL_MASK) ==
-			 GMAC_PLL_SELECT_CODEC)
+		else if ((con & GMAC_PLL_MASK) == GMAC_PLL_SELECT_CODEC)
 			pll_rate = CPLL_HZ;
 		else
 			/* CPLL is not set */
-- 
2.39.5

[PATCH 02/10] mmc: rockchip: fix clock get wrong index

[WeiHao Li]

Signed-off-by: WeiHao Li <ieiao@outlook.com>
---
 drivers/mmc/rockchip_dw_mmc.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/mmc/rockchip_dw_mmc.c b/drivers/mmc/rockchip_dw_mmc.c
index 7a72abaa38..a3f001d7e7 100644
--- a/drivers/mmc/rockchip_dw_mmc.c
+++ b/drivers/mmc/rockchip_dw_mmc.c
@@ -132,7 +132,7 @@ static int rockchip_dwmmc_probe(struct udevice *dev)
 
 	ret = clk_get_by_phandle(dev, &dtplat->clocks[1], &priv->clk);
 #else
-	ret = clk_get_by_index(dev, 1, &priv->clk);
+	ret = clk_get_by_index(dev, 0, &priv->clk);
 #endif
 	if (ret < 0 && ret != -ENOSYS)
 		return log_msg_ret("clk", ret);
-- 
2.39.5

[PATCH 03/10] net: rockchip: rk3368: add set_to_rmii

[WeiHao Li]

Signed-off-by: WeiHao Li <ieiao@outlook.com>
---
 drivers/net/gmac_rockchip.c | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/drivers/net/gmac_rockchip.c b/drivers/net/gmac_rockchip.c
index c8cfe7448d..1977853e75 100644
--- a/drivers/net/gmac_rockchip.c
+++ b/drivers/net/gmac_rockchip.c
@@ -552,6 +552,22 @@ static void rk3368_gmac_set_to_rgmii(struct gmac_rockchip_plat *pdata)
 		     pdata->tx_delay << RK3368_CLK_TX_DL_CFG_GMAC_SHIFT);
 }
 
+static void rk3368_gmac_set_to_rmii(struct gmac_rockchip_plat *pdata)
+{
+	struct rk3368_grf *grf;
+	enum {
+		RK3368_GMAC_PHY_INTF_SEL_RMII = 1 << 11,
+		RK3368_GMAC_PHY_INTF_SEL_MASK = GENMASK(11, 9),
+		RK3368_RMII_MODE_MASK  = BIT(6),
+		RK3368_RMII_MODE       = BIT(6),
+	};
+
+	grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+	rk_clrsetreg(&grf->soc_con15,
+		     RK3368_RMII_MODE_MASK | RK3368_GMAC_PHY_INTF_SEL_MASK,
+		     RK3368_RMII_MODE | RK3368_GMAC_PHY_INTF_SEL_RMII);
+}
+
 static void rk3399_gmac_set_to_rgmii(struct gmac_rockchip_plat *pdata)
 {
 	struct rk3399_grf_regs *grf;
@@ -755,6 +771,7 @@ const struct rk_gmac_ops rk3328_gmac_ops = {
 const struct rk_gmac_ops rk3368_gmac_ops = {
 	.fix_mac_speed = rk3368_gmac_fix_mac_speed,
 	.set_to_rgmii = rk3368_gmac_set_to_rgmii,
+	.set_to_rmii = rk3368_gmac_set_to_rmii,
 };
 
 const struct rk_gmac_ops rk3399_gmac_ops = {
-- 
2.39.5

[PATCH 04/10] clk: rockchip: rk3368: Add bus clk get/set

[WeiHao Li]

Patch get form Rockchip downstream uboot repository.

Signed-off-by: WeiHao Li <ieiao@outlook.com>
---
 .../include/asm/arch-rockchip/cru_rk3368.h    | 60 ++++++++++++
 drivers/clk/rockchip/clk_rk3368.c             | 94 +++++++++++++++++++
 2 files changed, 154 insertions(+)

diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3368.h b/arch/arm/include/asm/arch-rockchip/cru_rk3368.h
index ed2a612185..29f90454d4 100644
--- a/arch/arm/include/asm/arch-rockchip/cru_rk3368.h
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk3368.h
@@ -80,6 +80,49 @@ enum {
 	PLL_RESET			= 1,
 	PLL_RESET_MASK			= GENMASK(5, 5),
 
+	/* CLKSEL1CON */
+	CORE_ACLK_DIV_SHIFT		= 0,
+	CORE_ACLK_DIV_MASK		= 0x1f << CORE_ACLK_DIV_SHIFT,
+	CORE_DBG_DIV_SHIFT		= 8,
+	CORE_DBG_DIV_MASK		= 0x1f << CORE_DBG_DIV_SHIFT,
+
+	CORE_CLK_PLL_SEL_SHIFT		= 7,
+	CORE_CLK_PLL_SEL_MASK		= 1 << CORE_CLK_PLL_SEL_SHIFT,
+	CORE_CLK_PLL_SEL_APLL		= 0,
+	CORE_CLK_PLL_SEL_GPLL,
+	CORE_DIV_CON_SHIFT		= 0,
+	CORE_DIV_CON_MASK		= 0x1f << CORE_DIV_CON_SHIFT,
+
+	/* CLKSEL8CON */
+	PCLK_BUS_DIV_CON_SHIFT		= 12,
+	PCLK_BUS_DIV_CON_MASK		= 0x7 << PCLK_BUS_DIV_CON_SHIFT,
+	HCLK_BUS_DIV_CON_SHIFT		= 8,
+	HCLK_BUS_DIV_CON_MASK		= 0x3 << HCLK_BUS_DIV_CON_SHIFT,
+	CLK_BUS_PLL_SEL_CPLL		= 0,
+	CLK_BUS_PLL_SEL_GPLL		= 1,
+	CLK_BUS_PLL_SEL_SHIFT		= 7,
+	CLK_BUS_PLL_SEL_MASK		= 1 << CLK_BUS_PLL_SEL_SHIFT,
+	ACLK_BUS_DIV_CON_SHIFT		= 0,
+	ACLK_BUS_DIV_CON_MASK		= 0x1f << ACLK_BUS_DIV_CON_SHIFT,
+
+	/* CLKSEL9CON */
+	PCLK_PERI_DIV_CON_SHIFT		= 12,
+	PCLK_PERI_DIV_CON_MASK		= 0x3 << PCLK_PERI_DIV_CON_SHIFT,
+	HCLK_PERI_DIV_CON_SHIFT		= 8,
+	HCLK_PERI_DIV_CON_MASK		= 3 << HCLK_PERI_DIV_CON_SHIFT,
+	CLK_PERI_PLL_SEL_CPLL		= 0,
+	CLK_PERI_PLL_SEL_GPLL,
+	CLK_PERI_PLL_SEL_SHIFT		= 7,
+	CLK_PERI_PLL_SEL_MASK		= 1 << CLK_PERI_PLL_SEL_SHIFT,
+	ACLK_PERI_DIV_CON_SHIFT		= 0,
+	ACLK_PERI_DIV_CON_MASK		= 0x1f,
+
+	/* CLKSEL10CON */
+	CLK_CRYPTO_DIV_CON_SHIFT	= 14,
+	CLK_CRYPTO_DIV_CON_MASK		= 0x3 << CLK_CRYPTO_DIV_CON_SHIFT,
+	PCLK_ALIVE_DIV_CON_SHIFT	= 8,
+	PCLK_ALIVE_DIV_CON_MASK		= 0x1f << PCLK_ALIVE_DIV_CON_SHIFT,
+
 	/* CLKSEL12_CON */
 	MCU_STCLK_DIV_SHIFT		= 8,
 	MCU_STCLK_DIV_MASK		= GENMASK(10, 8),
@@ -90,6 +133,23 @@ enum {
 	MCU_CLK_DIV_SHIFT		= 0,
 	MCU_CLK_DIV_MASK		= GENMASK(4, 0),
 
+	/* CLKSEL19_CON */
+	ACLK_VOP_PLL_SEL_SHIFT		= 6,
+	ACLK_VOP_PLL_SEL_MASK		= GENMASK(7, 6),
+	ACLK_VOP_PLL_SEL_CPLL		= 0,
+	ACLK_VOP_PLL_SEL_GPLL		= 1,
+	ACLK_VOP_DIV_SHIFT		= 0,
+	ACLK_VOP_DIV_MASK		= GENMASK(4, 0),
+
+	/* CLKSEL20_CON */
+	DCLK_VOP_PLL_SEL_SHIFT		= 8,
+	DCLK_VOP_PLL_SEL_MASK		= GENMASK(9, 8),
+	DCLK_VOP_PLL_SEL_CPLL		= 0,
+	DCLK_VOP_PLL_SEL_GPLL		= 1,
+	DCLK_VOP_PLL_SEL_NPLL		= 2,
+	DCLK_VOP_DIV_SHIFT		= 0,
+	DCLK_VOP_DIV_MASK		= GENMASK(7, 0),
+
 	/* CLKSEL_CON25 */
 	CLK_SARADC_DIV_CON_SHIFT	= 8,
 	CLK_SARADC_DIV_CON_MASK		= GENMASK(15, 8),
diff --git a/drivers/clk/rockchip/clk_rk3368.c b/drivers/clk/rockchip/clk_rk3368.c
index 6691801384..aba7f2cd47 100644
--- a/drivers/clk/rockchip/clk_rk3368.c
+++ b/drivers/clk/rockchip/clk_rk3368.c
@@ -451,6 +451,82 @@ static ulong rk3368_saradc_set_clk(struct rk3368_cru *cru, uint hz)
 	return rk3368_saradc_get_clk(cru);
 }
 
+#if !IS_ENABLED(CONFIG_XPL_BUILD)
+static ulong rk3368_bus_get_clk(struct rk3368_cru *cru, ulong clk_id)
+{
+	u32 div, con, parent;
+
+	switch (clk_id) {
+	case ACLK_BUS:
+		con = readl(&cru->clksel_con[8]);
+		div = (con & ACLK_BUS_DIV_CON_MASK) >> ACLK_BUS_DIV_CON_SHIFT;
+		parent = rkclk_pll_get_rate(cru, GPLL);
+		break;
+	case HCLK_BUS:
+		con = readl(&cru->clksel_con[8]);
+		div = (con & HCLK_BUS_DIV_CON_MASK) >> HCLK_BUS_DIV_CON_SHIFT;
+		parent = rk3368_bus_get_clk(cru, ACLK_BUS);
+		break;
+	case PCLK_BUS:
+	case PCLK_PWM0:
+	case PCLK_PWM1:
+	case PCLK_I2C0:
+	case PCLK_I2C1:
+		con = readl(&cru->clksel_con[8]);
+		div = (con & PCLK_BUS_DIV_CON_MASK) >> PCLK_BUS_DIV_CON_SHIFT;
+		parent = rk3368_bus_get_clk(cru, ACLK_BUS);
+		break;
+	default:
+		return -ENOENT;
+	}
+
+	return DIV_TO_RATE(parent, div);
+}
+
+static ulong rk3368_bus_set_clk(struct rk3368_cru *cru,
+				ulong clk_id, ulong hz)
+{
+	int src_clk_div;
+
+	/*
+	 * select gpll as pd_bus bus clock source and
+	 * set up dependent divisors for PCLK/HCLK and ACLK clocks.
+	 */
+	switch (clk_id) {
+	case ACLK_BUS:
+		src_clk_div = DIV_ROUND_UP(rkclk_pll_get_rate(cru, GPLL), hz);
+		assert(src_clk_div - 1 < 31);
+		rk_clrsetreg(&cru->clksel_con[8],
+			     CLK_BUS_PLL_SEL_MASK | ACLK_BUS_DIV_CON_MASK,
+			     CLK_BUS_PLL_SEL_GPLL << CLK_BUS_PLL_SEL_SHIFT |
+			     (src_clk_div - 1) << ACLK_BUS_DIV_CON_SHIFT);
+		break;
+	case HCLK_BUS:
+		src_clk_div = DIV_ROUND_UP(rk3368_bus_get_clk(cru,
+							      ACLK_BUS),
+					   hz);
+		assert(src_clk_div - 1 < 3);
+		rk_clrsetreg(&cru->clksel_con[8],
+			     HCLK_BUS_DIV_CON_MASK,
+			     (src_clk_div - 1) << HCLK_BUS_DIV_CON_SHIFT);
+		break;
+	case PCLK_BUS:
+		src_clk_div = DIV_ROUND_UP(rk3368_bus_get_clk(cru,
+							      ACLK_BUS),
+					   hz);
+		assert(src_clk_div - 1 < 3);
+		rk_clrsetreg(&cru->clksel_con[8],
+			     PCLK_BUS_DIV_CON_MASK,
+			     (src_clk_div - 1) << PCLK_BUS_DIV_CON_SHIFT);
+		break;
+	default:
+		printf("do not support this bus freq\n");
+		return -EINVAL;
+	}
+	return rk3368_bus_get_clk(cru, clk_id);
+}
+#endif
+
 static ulong rk3368_clk_get_rate(struct clk *clk)
 {
 	struct rk3368_clk_priv *priv = dev_get_priv(clk->dev);
@@ -467,6 +543,17 @@ static ulong rk3368_clk_get_rate(struct clk *clk)
 	case SCLK_SPI0 ... SCLK_SPI2:
 		rate = rk3368_spi_get_clk(priv->cru, clk->id);
 		break;
+#if !IS_ENABLED(CONFIG_XPL_BUILD)
+	case ACLK_BUS:
+	case HCLK_BUS:
+	case PCLK_BUS:
+	case PCLK_PWM0:
+	case PCLK_PWM1:
+	case PCLK_I2C0:
+	case PCLK_I2C1:
+		rate = rk3368_bus_get_clk(priv->cru, clk->id);
+		break;
+#endif
 #if !IS_ENABLED(CONFIG_XPL_BUILD) || CONFIG_IS_ENABLED(MMC)
 	case HCLK_SDMMC:
 	case HCLK_EMMC:
@@ -498,6 +585,13 @@ static ulong rk3368_clk_set_rate(struct clk *clk, ulong rate)
 		ret = rk3368_ddr_set_clk(priv->cru, rate);
 		break;
 #endif
+#if !IS_ENABLED(CONFIG_XPL_BUILD)
+	case ACLK_BUS:
+	case HCLK_BUS:
+	case PCLK_BUS:
+		rate = rk3368_bus_set_clk(priv->cru, clk->id, rate);
+		break;
+#endif
 #if !IS_ENABLED(CONFIG_XPL_BUILD) || CONFIG_IS_ENABLED(MMC)
 	case HCLK_SDMMC:
 	case HCLK_EMMC:
-- 
2.39.5

[PATCH 05/10] clk: rockchip: rk3368: Adjust pll clk get

[WeiHao Li]

Patch get form Rockchip downstream uboot repository.

Signed-off-by: WeiHao Li <ieiao@outlook.com>
---
 drivers/clk/rockchip/clk_rk3368.c | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/drivers/clk/rockchip/clk_rk3368.c b/drivers/clk/rockchip/clk_rk3368.c
index aba7f2cd47..2a20c8b50f 100644
--- a/drivers/clk/rockchip/clk_rk3368.c
+++ b/drivers/clk/rockchip/clk_rk3368.c
@@ -534,11 +534,13 @@ static ulong rk3368_clk_get_rate(struct clk *clk)
 
 	debug("%s: id %ld\n", __func__, clk->id);
 	switch (clk->id) {
+	case PLL_APLLB:
+	case PLL_APLLL:
+	case PLL_DPLL:
 	case PLL_CPLL:
-		rate = rkclk_pll_get_rate(priv->cru, CPLL);
-		break;
 	case PLL_GPLL:
-		rate = rkclk_pll_get_rate(priv->cru, GPLL);
+	case PLL_NPLL:
+		rate = rkclk_pll_get_rate(priv->cru, clk->id - 1);
 		break;
 	case SCLK_SPI0 ... SCLK_SPI2:
 		rate = rk3368_spi_get_clk(priv->cru, clk->id);
-- 
2.39.5

[PATCH 06/10] clk: rockchip: rk3368: Add vop clk get/set

[WeiHao Li]

Patch get form Rockchip downstream uboot repository.

Signed-off-by: WeiHao Li <ieiao@outlook.com>
---
 .../include/asm/arch-rockchip/cru_rk3368.h    |   5 +
 .../include/asm/arch-rockchip/grf_rk3368.h    | 111 ++++++++-
 drivers/clk/rockchip/clk_rk3368.c             | 230 ++++++++++++++++++
 .../include/dt-bindings/clock/rk3368-cru.h    |   1 +
 4 files changed, 346 insertions(+), 1 deletion(-)

diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3368.h b/arch/arm/include/asm/arch-rockchip/cru_rk3368.h
index 29f90454d4..8178d4e013 100644
--- a/arch/arm/include/asm/arch-rockchip/cru_rk3368.h
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk3368.h
@@ -150,6 +150,11 @@ enum {
 	DCLK_VOP_DIV_SHIFT		= 0,
 	DCLK_VOP_DIV_MASK		= GENMASK(7, 0),
 
+	/* CLKSEL21_CON */
+	HCLK_VOP_DIV_SHIFT		= 0,
+	HCLK_VOP_DIV_MASK		= GENMASK(5, 0),
+	HCLK_VOP_DIV_WIDTH		= 5,
+
 	/* CLKSEL_CON25 */
 	CLK_SARADC_DIV_CON_SHIFT	= 8,
 	CLK_SARADC_DIV_CON_MASK		= GENMASK(15, 8),
diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3368.h b/arch/arm/include/asm/arch-rockchip/grf_rk3368.h
index 0079d20078..ef6cd167e2 100644
--- a/arch/arm/include/asm/arch-rockchip/grf_rk3368.h
+++ b/arch/arm/include/asm/arch-rockchip/grf_rk3368.h
@@ -77,11 +77,99 @@ struct rk3368_grf {
 	u32 soc_con15;
 	u32 soc_con16;
 	u32 soc_con17;
-	u32 reserved5[0x6e];
+	u32 reserved5[0xe];
+	u32 soc_status0;
+	u32 soc_status1;
+	u32 soc_status2;
+	u32 soc_status3;
+	u32 soc_status4;
+	u32 soc_status5;
+	u32 soc_status6;
+	u32 soc_status7;
+	u32 soc_status8;
+	u32 soc_status9;
+	u32 soc_status10;
+	u32 soc_status11;
+	u32 soc_status12;
+	u32 soc_status13;
+	u32 soc_status14;
+	u32 soc_status15;
+	u32 reserved6[0x10];
+	u32 cpu_con0;
+	u32 cpu_con1;
+	u32 cpu_con2;
+	u32 cpu_con3;
+	u32 reserved7[0x4];
+	u32 cpu_status0;
+	u32 cpu_status1;
+	u32 reserved8[0x6];
+	u32 cci_status0;
+	u32 cci_status1;
+	u32 cci_status2;
+	u32 cci_status3;
+	u32 cci_status4;
+	u32 cci_status5;
+	u32 cci_status6;
+	u32 cci_status7;
+	u32 cci_status8;
+	u32 cci_status9;
+	u32 cci_status10;
+	u32 cci_status11;
+	u32 cci_status12;
+	u32 cci_status13;
+	u32 cci_status14;
+	u32 cci_status15;
+	u32 reserved9[0x20];
 	u32 ddrc0_con0;
+	u32 reserved10[0x1f];
+	u32 sig_detect_con;
+	u32 reserved11[0x3];
+	u32 sig_detect_status;
+	u32 reserved12[0x3];
+	u32 sig_detect_clr;
+	u32 reserved13[0x17];
+	u32 uoc0_con0;
+	u32 reserved14[0x5];
+	u32 uoc1_con1;
+	u32 uoc1_con2;
+	u32 uoc1_con3;
+	u32 uoc1_con4;
+	u32 uoc1_con5;
+	u32 reserved15[0x3];
+	u32 uoc3_con0;
+	u32 uoc3_con1;
+	u32 uoc4_con0;
+	u32 uoc4_con1;
+	u32 reserved16[0xe];
+	u32 usbphy_con0;
+	u32 usbphy_con1;
+	u32 usbphy_con2;
+	u32 usbphy_con3;
+	u32 usbphy_con4;
+	u32 usbphy_con5;
+	u32 usbphy_con6;
+	u32 usbphy_con7;
+	u32 usbphy_con8;
+	u32 usbphy_con9;
+	u32 usbphy_con10;
+	u32 usbphy_con11;
+	u32 usbphy_con12;
+	u32 usbphy_con13;
+	u32 usbphy_con14;
+	u32 usbphy_con15;
+	u32 reserved17[0x10];
+	u32 pvtm_con0;
+	u32 pvtm_con1;
+	u32 pvtm_con2;
+	u32 pvtm_status0;
+	u32 pvtm_status1;
+	u32 pvtm_status2;
+	u32 reserved18[0x3a];
+	u32 io_vsel;
 };
 check_member(rk3368_grf, soc_con17, 0x444);
 check_member(rk3368_grf, ddrc0_con0, 0x600);
+check_member(rk3368_grf, io_vsel, 0x900);
 
 struct rk3368_pmu_grf {
 	u32 gpio0a_iomux;
@@ -104,6 +192,27 @@ struct rk3368_pmu_grf {
 check_member(rk3368_pmu_grf, gpio0h_sr, 0x34);
 check_member(rk3368_pmu_grf, os_reg[0], 0x200);
 
+/* GRF_SOC_CON7 */
+enum {
+	RK3368_DPHY_TX0_RXMODE_SHIFT = 6,
+	RK3368_DPHY_TX0_RXMODE_MASK =
+	   0x1 << RK3368_DPHY_TX0_RXMODE_SHIFT,
+	RK3368_DPHY_TX0_RXMODE_EN = 1,
+	RK3368_DPHY_TX0_RXMODE_DIS = 0,
+
+	RK3368_DPHY_TX0_TXSTOPMODE_SHIFT = 7,
+	RK3368_DPHY_TX0_TXSTOPMODE_MASK =
+	   0xf << RK3368_DPHY_TX0_TXSTOPMODE_SHIFT,
+	RK3368_DPHY_TX0_TXSTOPMODE_EN = 0xf,
+	RK3368_DPHY_TX0_TXSTOPMODE_DIS = 0,
+
+	RK3368_DPHY_TX0_TURNDISABLE_SHIFT = 5,
+	RK3368_DPHY_TX0_TURNDISABLE_MASK =
+	   0x1 << RK3368_DPHY_TX0_TURNDISABLE_SHIFT,
+	RK3368_DPHY_TX0_TURNDISABLE_EN = 1,
+	RK3368_DPHY_TX0_TURNDISABLE_DIS = 0,
+};
+
 /*GRF_SOC_CON11/12/13*/
 enum {
 	MCU_SRAM_BASE_BIT27_BIT12_SHIFT	= 0,
diff --git a/drivers/clk/rockchip/clk_rk3368.c b/drivers/clk/rockchip/clk_rk3368.c
index 2a20c8b50f..17707600ee 100644
--- a/drivers/clk/rockchip/clk_rk3368.c
+++ b/drivers/clk/rockchip/clk_rk3368.c
@@ -31,9 +31,27 @@ struct rk3368_clk_plat {
 #endif
 
 struct pll_div {
+	ulong rate;
 	u32 nr;
 	u32 nf;
 	u32 no;
+	u32 nb;
+};
+
+#define RK3368_PLL_RATE(_rate, _nr, _nf, _no, _nb)	\
+{							\
+	.rate	= _rate##U,				\
+	.nr = _nr,					\
+	.nf = _nf,					\
+	.no = _no,					\
+	.nb = _nb,					\
+}
+
+static struct pll_div rk3368_pll_rates[] = {
+	/* _mhz,  _nr, _nf, _no, _nb */
+	RK3368_PLL_RATE(594000000, 1, 99, 4, 16),
+	RK3368_PLL_RATE(424200000, 5, 707, 8, 0),
+	RK3368_PLL_RATE(410000000, 3, 205, 4, 16),
 };
 
 #define OSC_HZ		(24 * 1000 * 1000)
@@ -41,6 +59,7 @@ struct pll_div {
 #define APLL_B_HZ	(816 * 1000 * 1000)
 #define GPLL_HZ		(576 * 1000 * 1000)
 #define CPLL_HZ		(400 * 1000 * 1000)
+#define NPLL_HZ		(594 * 1000 * 1000)
 
 #define DIV_TO_RATE(input_rate, div)    ((input_rate) / ((div) + 1))
 
@@ -61,6 +80,105 @@ static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 6);
 
 static ulong rk3368_clk_get_rate(struct clk *clk);
 
+#define VCO_MAX_KHZ	2200000
+#define VCO_MIN_KHZ	440000
+#define FREF_MAX_KHZ	2200000
+#define FREF_MIN_KHZ	269
+#define PLL_LIMIT_FREQ	400000000
+
+struct pll_div *rkclk_get_pll_config(ulong freq_hz)
+{
+	unsigned int rate_count = ARRAY_SIZE(rk3368_pll_rates);
+	int i;
+
+	for (i = 0; i < rate_count; i++) {
+		if (freq_hz == rk3368_pll_rates[i].rate)
+			return &rk3368_pll_rates[i];
+	}
+	return NULL;
+}
+
+static int pll_para_config(ulong freq_hz, struct pll_div *div, uint *ext_div)
+{
+	struct pll_div *best_div = NULL;
+	uint ref_khz = OSC_HZ / 1000, nr, nf = 0;
+	uint fref_khz;
+	uint diff_khz, best_diff_khz;
+	const uint max_nr = 1 << 6, max_nf = 1 << 12, max_no = 1 << 4;
+	uint vco_khz;
+	uint no = 1;
+	uint freq_khz = freq_hz / 1000;
+
+	if (!freq_hz) {
+		printf("%s: the frequency can not be 0 Hz\n", __func__);
+		return -EINVAL;
+	}
+
+	no = DIV_ROUND_UP(VCO_MIN_KHZ, freq_khz);
+	if (ext_div) {
+		*ext_div = DIV_ROUND_UP(PLL_LIMIT_FREQ, freq_hz);
+		no = DIV_ROUND_UP(no, *ext_div);
+	}
+
+	best_div = rkclk_get_pll_config(freq_hz * (*ext_div));
+	if (best_div) {
+		div->nr = best_div->nr;
+		div->nf = best_div->nf;
+		div->no = best_div->no;
+		div->nb = best_div->nb;
+		return 0;
+	}
+
+	/* only even divisors (and 1) are supported */
+	if (no > 1)
+		no = DIV_ROUND_UP(no, 2) * 2;
+
+	vco_khz = freq_khz * no;
+	if (ext_div)
+		vco_khz *= *ext_div;
+
+	if (vco_khz < VCO_MIN_KHZ || vco_khz > VCO_MAX_KHZ || no > max_no) {
+		printf("%s: Cannot find out VCO for Frequency (%luHz).\n",
+		       __func__, freq_hz);
+		return -1;
+	}
+
+	div->no = no;
+
+	best_diff_khz = vco_khz;
+	for (nr = 1; nr < max_nr && best_diff_khz; nr++) {
+		fref_khz = ref_khz / nr;
+		if (fref_khz < FREF_MIN_KHZ)
+			break;
+		if (fref_khz > FREF_MAX_KHZ)
+			continue;
+
+		nf = vco_khz / fref_khz;
+		if (nf >= max_nf)
+			continue;
+		diff_khz = vco_khz - nf * fref_khz;
+		if (nf + 1 < max_nf && diff_khz > fref_khz / 2) {
+			nf++;
+			diff_khz = fref_khz - diff_khz;
+		}
+
+		if (diff_khz >= best_diff_khz)
+			continue;
+
+		best_diff_khz = diff_khz;
+		div->nr = nr;
+		div->nf = nf;
+	}
+
+	if (best_diff_khz > 4 * 1000) {
+		printf("%s:Fail to match output freq %lu,best_is %u Hz\n",
+		       __func__, freq_hz, best_diff_khz * 1000);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
 /* Get pll rate by id */
 static uint32_t rkclk_pll_get_rate(struct rk3368_cru *cru,
 				   enum rk3368_pll_id pll_id)
@@ -525,6 +643,104 @@ static ulong rk3368_bus_set_clk(struct rk3368_cru *cru,
 	}
 	return rk3368_bus_get_clk(cru, clk_id);
 }
+
+static ulong rk3368_vop_get_clk(struct rk3368_cru *cru,  int clk_id)
+{
+	u32 div, con, parent, sel;
+
+	switch (clk_id) {
+	case DCLK_VOP:
+		con = readl(&cru->clksel_con[20]);
+		div = con & DCLK_VOP_DIV_MASK;
+		parent = rkclk_pll_get_rate(cru, NPLL);
+		break;
+	case ACLK_VOP:
+		con = readl(&cru->clksel_con[19]);
+		div = con & ACLK_VOP_DIV_MASK;
+		sel =  (con & (ACLK_VOP_PLL_SEL_MASK <<
+			ACLK_VOP_PLL_SEL_SHIFT)) >>
+			ACLK_VOP_PLL_SEL_SHIFT;
+		if (sel == ACLK_VOP_PLL_SEL_CPLL)
+			parent = rkclk_pll_get_rate(cru, CPLL);
+		else if (ACLK_VOP_PLL_SEL_GPLL)
+			parent = rkclk_pll_get_rate(cru, GPLL);
+		else
+			parent = 480000000;
+		break;
+	case HCLK_VOP:
+		parent = rk3368_vop_get_clk(cru, ACLK_VOP);
+		con = readl(&cru->clksel_con[21]);
+		div = con & HCLK_VOP_DIV_MASK;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	return DIV_TO_RATE(parent, div);
+}
+
+static ulong rk3368_vop_set_clk(struct rk3368_cru *cru, int clk_id, uint hz)
+{
+	struct pll_div npll_config = {0};
+	u32 lcdc_div;
+	int ret;
+
+	switch (clk_id) {
+	case DCLK_VOP:
+		if (!(NPLL_HZ % hz)) {
+			rkclk_set_pll(cru, NPLL, rkclk_get_pll_config(NPLL_HZ));
+			lcdc_div = NPLL_HZ / hz;
+		} else {
+			ret = pll_para_config(hz, &npll_config, &lcdc_div);
+			if (ret)
+				return ret;
+
+			rkclk_set_pll(cru, NPLL, &npll_config);
+		}
+		/* vop dclk source clk: npll,dclk_div: 1 */
+		rk_clrsetreg(&cru->clksel_con[20],
+			     (DCLK_VOP_PLL_SEL_MASK << DCLK_VOP_PLL_SEL_SHIFT) |
+			     (DCLK_VOP_DIV_MASK << DCLK_VOP_DIV_SHIFT),
+			     (DCLK_VOP_PLL_SEL_NPLL << DCLK_VOP_PLL_SEL_SHIFT) |
+			     (lcdc_div - 1) << DCLK_VOP_DIV_SHIFT);
+		break;
+	case ACLK_VOP:
+		if ((rkclk_pll_get_rate(cru, CPLL) % hz) == 0) {
+			lcdc_div = rkclk_pll_get_rate(cru, CPLL) / hz;
+			rk_clrsetreg(&cru->clksel_con[19],
+				     (ACLK_VOP_PLL_SEL_MASK <<
+				     ACLK_VOP_PLL_SEL_SHIFT) |
+				     (ACLK_VOP_DIV_MASK <<
+				     ACLK_VOP_DIV_SHIFT),
+				     (ACLK_VOP_PLL_SEL_CPLL <<
+				     ACLK_VOP_PLL_SEL_SHIFT) |
+				     (lcdc_div - 1) <<
+				     ACLK_VOP_DIV_SHIFT);
+		} else {
+			lcdc_div = rkclk_pll_get_rate(cru, GPLL) / hz;
+			rk_clrsetreg(&cru->clksel_con[19],
+				     (ACLK_VOP_PLL_SEL_MASK <<
+				     ACLK_VOP_PLL_SEL_SHIFT) |
+				     (ACLK_VOP_DIV_MASK <<
+				     ACLK_VOP_DIV_SHIFT),
+				     (ACLK_VOP_PLL_SEL_GPLL <<
+				     ACLK_VOP_PLL_SEL_SHIFT) |
+				     (lcdc_div - 1) <<
+				     ACLK_VOP_DIV_SHIFT);
+		}
+		break;
+	case HCLK_VOP:
+		lcdc_div = rk3368_vop_get_clk(cru, ACLK_VOP) / hz;
+		rk_clrsetreg(&cru->clksel_con[21],
+			     HCLK_VOP_DIV_MASK,
+			     (lcdc_div - 1) << HCLK_VOP_DIV_SHIFT);
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	return rk3368_vop_get_clk(cru, clk_id);
+}
 #endif
 
 static ulong rk3368_clk_get_rate(struct clk *clk)
@@ -565,6 +781,13 @@ static ulong rk3368_clk_get_rate(struct clk *clk)
 	case SCLK_SARADC:
 		rate = rk3368_saradc_get_clk(priv->cru);
 		break;
+#if !IS_ENABLED(CONFIG_XPL_BUILD)
+	case ACLK_VOP:
+	case DCLK_VOP:
+	case HCLK_VOP:
+		rate = rk3368_vop_get_clk(priv->cru, clk->id);
+		break;
+#endif
 	default:
 		return -ENOENT;
 	}
@@ -609,6 +832,13 @@ static ulong rk3368_clk_set_rate(struct clk *clk, ulong rate)
 	case SCLK_SARADC:
 		ret =  rk3368_saradc_set_clk(priv->cru, rate);
 		break;
+#if !defined(CONFIG_XPL_BUILD)
+	case ACLK_VOP:
+	case DCLK_VOP:
+	case HCLK_VOP:
+		ret = rk3368_vop_set_clk(priv->cru, clk->id, rate);
+		break;
+#endif
 	default:
 		return -ENOENT;
 	}
diff --git a/dts/upstream/include/dt-bindings/clock/rk3368-cru.h b/dts/upstream/include/dt-bindings/clock/rk3368-cru.h
index ebae3cbf81..b951e29069 100644
--- a/dts/upstream/include/dt-bindings/clock/rk3368-cru.h
+++ b/dts/upstream/include/dt-bindings/clock/rk3368-cru.h
@@ -72,6 +72,7 @@
 #define SCLK_SFC		126
 #define SCLK_MAC		127
 #define SCLK_MACREF_OUT		128
+#define SCLK_MIPIDSI_24M	129
 #define SCLK_TIMER10		133
 #define SCLK_TIMER11		134
 #define SCLK_TIMER12		135
-- 
2.39.5

[PATCH 07/10] video: rockchip: vop add bridge support

[WeiHao Li]

Signed-off-by: muratdemirtas <muratdemirtaseu@outlook.com>
Signed-off-by: WeiHao Li <ieiao@outlook.com>
---
 drivers/video/rockchip/rk_vop.c | 92 +++++++++++++++++++++++++--------
 1 file changed, 71 insertions(+), 21 deletions(-)

diff --git a/drivers/video/rockchip/rk_vop.c b/drivers/video/rockchip/rk_vop.c
index 17dfe62c9d..71786da77e 100644
--- a/drivers/video/rockchip/rk_vop.c
+++ b/drivers/video/rockchip/rk_vop.c
@@ -14,6 +14,8 @@
 #include <reset.h>
 #include <syscon.h>
 #include <video.h>
+#include <video_bridge.h>
+#include <panel.h>
 #include <asm/global_data.h>
 #include <asm/gpio.h>
 #include <asm/io.h>
@@ -257,6 +259,8 @@ static int rk_display_init(struct udevice *dev, ulong fbbase, ofnode ep_node)
 	ofnode remote;
 	const char *compat;
 	struct reset_ctl dclk_rst;
+	struct udevice *bridge;
+	struct udevice *panel;
 
 	debug("%s(%s, 0x%lx, %s)\n", __func__,
 	      dev_read_name(dev), fbbase, ofnode_get_name(ep_node));
@@ -298,6 +302,10 @@ static int rk_display_init(struct udevice *dev, ulong fbbase, ofnode ep_node)
 			return -EINVAL;
 		}
 
+		uclass_find_device_by_ofnode(UCLASS_VIDEO_BRIDGE, remote, &bridge);
+		if (bridge)
+			break;
+
 		uclass_find_device_by_ofnode(UCLASS_DISPLAY, remote, &disp);
 		if (disp)
 			break;
@@ -326,27 +334,60 @@ static int rk_display_init(struct udevice *dev, ulong fbbase, ofnode ep_node)
 	}
 	debug("vop_id=%d\n", vop_id);
 
-	disp_uc_plat = dev_get_uclass_plat(disp);
-	debug("Found device '%s', disp_uc_priv=%p\n", disp->name, disp_uc_plat);
-	if (display_in_use(disp)) {
-		debug("   - device in use\n");
-		return -EBUSY;
-	}
+	if (bridge) {
+		/* video bridge detected, probe it */
+		ret = device_probe(bridge);
+		if (ret) {
+			debug("%s: device '%s' bridge won't probe (ret=%d)\n",
+			      __func__, dev->name, ret);
+			return ret;
+		}
 
-	disp_uc_plat->source_id = remote_vop_id;
-	disp_uc_plat->src_dev = dev;
+		/* Attach the DSI controller and the display to the bridge. */
+		ret = video_bridge_attach(bridge);
+		if (ret) {
+			debug("Failed to attach video bridge: %d\n", ret);
+			return ret;
+		}
 
-	ret = device_probe(disp);
-	if (ret) {
-		debug("%s: device '%s' display won't probe (ret=%d)\n",
-		      __func__, dev->name, ret);
-		return ret;
-	}
+		/*
+		 * Get the panel device
+		 * TODO: Maybe fetch it from the bridge private data.
+		 */
+		ret = uclass_first_device_err(UCLASS_PANEL, &panel);
+		if (ret) {
+			debug("Panel device error: %d\n", ret);
+			return ret;
+		}
 
-	ret = display_read_timing(disp, &timing);
-	if (ret) {
-		debug("%s: Failed to read timings\n", __func__);
-		return ret;
+		ret = panel_get_display_timing(panel, &timing);
+		if (ret) {
+			debug("%s: Failed to read timings\n", __func__);
+			return ret;
+		}
+	} else {
+		disp_uc_plat = dev_get_uclass_plat(disp);
+		debug("Found device '%s', disp_uc_priv=%p\n", disp->name, disp_uc_plat);
+		if (display_in_use(disp)) {
+			debug("   - device in use\n");
+			return -EBUSY;
+		}
+
+		disp_uc_plat->source_id = remote_vop_id;
+		disp_uc_plat->src_dev = dev;
+
+		ret = device_probe(disp);
+		if (ret) {
+			debug("%s: device '%s' display won't probe (ret=%d)\n",
+			      __func__, dev->name, ret);
+			return ret;
+		}
+
+		ret = display_read_timing(disp, &timing);
+		if (ret) {
+			debug("%s: Failed to read timings\n", __func__);
+			return ret;
+		}
 	}
 
 	ret = clk_get_by_index(dev, 1, &clk);
@@ -383,9 +424,18 @@ static int rk_display_init(struct udevice *dev, ulong fbbase, ofnode ep_node)
 
 	rkvop_enable(dev, fbbase, 1 << l2bpp, &timing, &dclk_rst);
 
-	ret = display_enable(disp, 1 << l2bpp, &timing);
-	if (ret)
-		return ret;
+	if (bridge) {
+		/* Attach the DSI controller and the display to the bridge. */
+		ret = video_bridge_set_backlight(bridge, 80);
+		if (ret) {
+			printf("Failed to start the video bridge: %d\n", ret);
+			return ret;
+		}
+	} else {
+		ret = display_enable(disp, 1 << l2bpp, &timing);
+		if (ret)
+			return ret;
+	}
 
 	uc_priv->xsize = timing.hactive.typ;
 	uc_priv->ysize = timing.vactive.typ;
-- 
2.39.5

[PATCH 08/10] video: rockchip: add rk3368 vop support

[WeiHao Li]

Signed-off-by: WeiHao Li <ieiao@outlook.com>
---
 drivers/video/rockchip/Makefile               |  1 +
 drivers/video/rockchip/dw_mipi_dsi_rockchip.c | 20 +++++
 drivers/video/rockchip/rk3368_vop.c           | 81 +++++++++++++++++++
 3 files changed, 102 insertions(+)
 create mode 100644 drivers/video/rockchip/rk3368_vop.c

diff --git a/drivers/video/rockchip/Makefile b/drivers/video/rockchip/Makefile
index f55beceebf..83c0b7aef9 100644
--- a/drivers/video/rockchip/Makefile
+++ b/drivers/video/rockchip/Makefile
@@ -7,6 +7,7 @@ ifdef CONFIG_VIDEO_ROCKCHIP
 obj-y += rk_vop.o
 obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288_vop.o
 obj-$(CONFIG_ROCKCHIP_RK3328) += rk3328_vop.o
+obj-$(CONFIG_ROCKCHIP_RK3368) += rk3368_vop.o
 obj-$(CONFIG_ROCKCHIP_RK3399) += rk3399_vop.o
 obj-$(CONFIG_DISPLAY_ROCKCHIP_EDP) += rk_edp.o
 obj-$(CONFIG_DISPLAY_ROCKCHIP_LVDS) += rk_lvds.o
diff --git a/drivers/video/rockchip/dw_mipi_dsi_rockchip.c b/drivers/video/rockchip/dw_mipi_dsi_rockchip.c
index fa51217351..122974d601 100644
--- a/drivers/video/rockchip/dw_mipi_dsi_rockchip.c
+++ b/drivers/video/rockchip/dw_mipi_dsi_rockchip.c
@@ -134,6 +134,11 @@
 #define DW_MIPI_NEEDS_PHY_CFG_CLK	BIT(0)
 #define DW_MIPI_NEEDS_GRF_CLK		BIT(1)
 
+#define RK3368_GRF_SOC_CON7		0x41c
+#define RK3368_DSI_FORCETXSTOPMODE	(0xf << 7)
+#define RK3368_DSI_FORCERXMODE		(0x1 << 6)
+#define RK3368_DSI_TURNDISABLE		(0x1 << 5)
+
 #define RK3399_GRF_SOC_CON20		0x6250
 #define RK3399_DSI0_LCDC_SEL		BIT(0)
 #define RK3399_DSI1_LCDC_SEL		BIT(4)
@@ -911,6 +916,18 @@ struct video_bridge_ops dw_mipi_dsi_rockchip_ops = {
 	.set_backlight = dw_mipi_dsi_rockchip_set_bl,
 };
 
+static const struct rockchip_dw_dsi_chip_data rk3368_chip_data[] = {
+	{
+		.reg = 0xff960000,
+		.lanecfg1_grf_reg = RK3368_GRF_SOC_CON7,
+		.lanecfg1 = HIWORD_UPDATE(0, RK3368_DSI_TURNDISABLE |
+					     RK3368_DSI_FORCETXSTOPMODE |
+					     RK3368_DSI_FORCERXMODE),
+		.max_data_lanes = 4,
+	},
+	{ /* sentinel */ }
+};
+
 static const struct rockchip_dw_dsi_chip_data rk3399_chip_data[] = {
 	{
 		.reg = 0xff960000,
@@ -980,6 +997,9 @@ static const struct rockchip_dw_dsi_chip_data rk3568_chip_data[] = {
 };
 
 static const struct udevice_id dw_mipi_dsi_rockchip_dt_ids[] = {
+	{ .compatible = "rockchip,rk3368-mipi-dsi",
+	  .data = (long)&rk3368_chip_data,
+	},
 	{ .compatible = "rockchip,rk3399-mipi-dsi",
 	  .data = (long)&rk3399_chip_data,
 	},
diff --git a/drivers/video/rockchip/rk3368_vop.c b/drivers/video/rockchip/rk3368_vop.c
new file mode 100644
index 0000000000..46c719c75c
--- /dev/null
+++ b/drivers/video/rockchip/rk3368_vop.c
@@ -0,0 +1,81 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH
+ * Copyright (c) 2015 Google, Inc
+ * Copyright 2014 Rockchip Inc.
+ */
+
+#include <display.h>
+#include <dm.h>
+#include <regmap.h>
+#include <syscon.h>
+#include <video.h>
+#include <asm/global_data.h>
+#include <asm/arch-rockchip/clock.h>
+#include <asm/arch-rockchip/hardware.h>
+#include <linux/delay.h>
+#include "rk_vop.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void rk3368_set_pin_polarity(struct udevice *dev,
+				    enum vop_modes mode, u32 polarity)
+{
+	struct rk_vop_priv *priv = dev_get_priv(dev);
+	struct rk3288_vop *regs = priv->regs;
+
+	/* The RK3368 VOP (v3.2) has its polarity configuration in ctrl0 */
+	clrsetbits_le32(&regs->dsp_ctrl0,
+			M_DSP_DCLK_POL | M_DSP_DEN_POL |
+			M_DSP_VSYNC_POL | M_DSP_HSYNC_POL,
+			V_DSP_PIN_POL(polarity));
+}
+
+/*
+ * Try some common regulators. We should really get these from the
+ * device tree somehow.
+ */
+static const char * const rk3368_regulator_names[] = {
+	"vcc18_lcd",
+	"VCC18_LCD",
+	"vdd10_lcd_pwren_h",
+	"vdd10_lcd",
+	"VDD10_LCD",
+	"vcc33_lcd"
+};
+
+static int rk3368_vop_probe(struct udevice *dev)
+{
+	/* Before relocation we don't need to do anything */
+	if (!(gd->flags & GD_FLG_RELOC))
+		return 0;
+
+	/* Probe regulators required for the RK3368 VOP */
+	rk_vop_probe_regulators(dev, rk3368_regulator_names,
+				ARRAY_SIZE(rk3368_regulator_names));
+
+	return rk_vop_probe(dev);
+}
+
+struct rkvop_driverdata rk3368_driverdata = {
+	.set_pin_polarity = rk3368_set_pin_polarity,
+};
+
+static const struct udevice_id rk3368_vop_ids[] = {
+	{ .compatible = "rockchip,rk3368-vop",
+	  .data = (ulong)&rk3368_driverdata },
+	{ }
+};
+
+static const struct video_ops rk3368_vop_ops = {
+};
+
+U_BOOT_DRIVER(rockchip_rk3368_vop) = {
+	.name		= "rockchip_rk3368_vop",
+	.id		= UCLASS_VIDEO,
+	.of_match 	= rk3368_vop_ids,
+	.ops		= &rk3368_vop_ops,
+	.bind		= rk_vop_bind,
+	.probe		= rk3368_vop_probe,
+	.priv_auto	= sizeof(struct rk_vop_priv),
+};
-- 
2.39.5

[PATCH 09/10] video: panel: add rm72014 panel support

[WeiHao Li]

Signed-off-by: WeiHao Li <ieiao@outlook.com>
---
 drivers/video/Kconfig   |   7 ++
 drivers/video/Makefile  |   1 +
 drivers/video/rm72014.c | 199 ++++++++++++++++++++++++++++++++++++++++
 3 files changed, 207 insertions(+)
 create mode 100644 drivers/video/rm72014.c

diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index dfe4b3b8a0..7e2a001082 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -596,6 +596,13 @@ config VIDEO_LCD_RAYDIUM_RM68200
 	Say Y here if you want to enable support for Raydium RM68200
 	720x1280 DSI video mode panel.
 
+config VIDEO_LCD_RM72014
+	bool "RM72014 DSI LCD panel support"
+	select VIDEO_MIPI_DSI
+	help
+	Say Y here if you want to enable support for unknown RM72014
+	800x1280 DSI video mode panel.
+
 config VIDEO_LCD_RENESAS_R61307
 	tristate "Renesas R61307 DSI video mode panel"
 	depends on PANEL && BACKLIGHT
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index ebe4a3961f..06ba4cfdcb 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -67,6 +67,7 @@ obj-$(CONFIG_VIDEO_LCD_MOT) += mot-panel.o
 obj-$(CONFIG_VIDEO_LCD_NOVATEK_NT35510) += novatek-nt35510.o
 obj-$(CONFIG_VIDEO_LCD_ORISETECH_OTM8009A) += orisetech_otm8009a.o
 obj-$(CONFIG_VIDEO_LCD_RAYDIUM_RM68200) += raydium-rm68200.o
+obj-$(CONFIG_VIDEO_LCD_RM72014) += rm72014.o
 obj-$(CONFIG_VIDEO_LCD_RENESAS_R61307) += renesas-r61307.o
 obj-$(CONFIG_VIDEO_LCD_RENESAS_R69328) += renesas-r69328.o
 obj-$(CONFIG_VIDEO_LCD_SAMSUNG_LTL106HL02) += samsung-ltl106hl02.o
diff --git a/drivers/video/rm72014.c b/drivers/video/rm72014.c
new file mode 100644
index 0000000000..d13583cfbc
--- /dev/null
+++ b/drivers/video/rm72014.c
@@ -0,0 +1,199 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2022 Ondrej Jirman <megi@xff.cz>
+ */
+#include <backlight.h>
+#include <dm.h>
+#include <mipi_dsi.h>
+#include <panel.h>
+#include <asm/gpio.h>
+#include <dm/device_compat.h>
+#include <linux/delay.h>
+#include <power/regulator.h>
+
+struct rm72014_panel_priv {
+	struct udevice *reg;
+	struct gpio_desc reset;
+	struct udevice *backlight;
+};
+
+static const struct display_timing default_timing = {
+	.pixelclock.typ		= 80000000,
+	.hactive.typ		= 800,
+	.hfront_porch.typ	= 210,
+	.hback_porch.typ	= 18,
+	.hsync_len.typ		= 18,
+	.vactive.typ		= 1280,
+	.vfront_porch.typ	= 8,
+	.vback_porch.typ	= 6,
+	.vsync_len.typ		= 6,
+	.flags			= DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW,
+};
+
+#define dsi_dcs_write_seq(device, seq...) do {					\
+		static const u8 d[] = { seq };					\
+		int ret;							\
+		ret = mipi_dsi_dcs_write_buffer(device, d, ARRAY_SIZE(d));	\
+		if (ret < 0)							\
+			return ret;						\
+	} while (0)
+
+static int rm72014_init_sequence(struct udevice *dev)
+{
+	struct mipi_dsi_panel_plat *plat = dev_get_plat(dev);
+	struct mipi_dsi_device *device = plat->device;
+	int ret;
+
+	dsi_dcs_write_seq(device, 0x53, 0x24);
+	dsi_dcs_write_seq(device, 0xf0, 0x5a, 0x5a);
+	mdelay(30);
+	dsi_dcs_write_seq(device, 0x11);
+	mdelay(120);
+	dsi_dcs_write_seq(device, 0x29);
+	mdelay(30);
+	dsi_dcs_write_seq(device, 0xc3, 0x40, 0x00, 0x28);
+	dsi_dcs_write_seq(device, 0x50, 0x77);
+	dsi_dcs_write_seq(device, 0xe1, 0x66);
+	dsi_dcs_write_seq(device, 0xdc, 0x67);
+	dsi_dcs_write_seq(device, 0xd3, 0xc8);
+	dsi_dcs_write_seq(device, 0x50, 0x00);
+	dsi_dcs_write_seq(device, 0xf0, 0x5a);
+	dsi_dcs_write_seq(device, 0xf5, 0x80);
+	mdelay(120);
+
+	ret = mipi_dsi_dcs_exit_sleep_mode(device);
+	if (ret)
+		return ret;
+
+	/* Panel is operational 120 msec after reset */
+	mdelay(120);
+
+	ret = mipi_dsi_dcs_set_display_on(device);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+static int rm72014_panel_enable_backlight(struct udevice *dev)
+{
+	struct mipi_dsi_panel_plat *plat = dev_get_plat(dev);
+	struct mipi_dsi_device *device = plat->device;
+	struct rm72014_panel_priv *priv = dev_get_priv(dev);
+	int ret;
+
+	ret = mipi_dsi_attach(device);
+	if (ret < 0) {
+		printf("mipi_dsi_attach failed %d\n", ret);
+		return ret;
+	}
+
+	ret = rm72014_init_sequence(dev);
+	if (ret) {
+		printf("rm72014_init_sequence failed %d\n", ret);
+		return ret;
+	}
+
+	if (priv->backlight) {
+		ret = backlight_enable(priv->backlight);
+		if (ret) {
+			printf("backlight enabled failed %d\n", ret);
+			return ret;
+		}
+
+		backlight_set_brightness(priv->backlight, 60);
+	}
+
+	mdelay(10);
+
+	return 0;
+}
+
+static int rm72014_panel_get_display_timing(struct udevice *dev,
+					   struct display_timing *timings)
+{
+	memcpy(timings, &default_timing, sizeof(*timings));
+
+	return 0;
+}
+
+static int rm72014_panel_of_to_plat(struct udevice *dev)
+{
+	struct rm72014_panel_priv *priv = dev_get_priv(dev);
+	int ret;
+
+	if (CONFIG_IS_ENABLED(DM_REGULATOR)) {
+		ret = uclass_get_device_by_phandle(UCLASS_REGULATOR, dev,
+						   "power-supply", &priv->reg);
+		if (ret) {
+			debug("%s: Warning: cannot get power supply: ret=%d\n",
+			      __func__, ret);
+			if (ret != -ENOENT)
+				return ret;
+		}
+	}
+
+	ret = uclass_get_device_by_phandle(UCLASS_PANEL_BACKLIGHT, dev,
+					   "backlight", &priv->backlight);
+	if (ret)
+		dev_warn(dev, "failed to get backlight\n");
+
+	ret = gpio_request_by_name(dev, "reset-gpios", 0, &priv->reset,
+				   GPIOD_IS_OUT);
+	if (ret) {
+		dev_err(dev, "warning: cannot get reset GPIO (%d)\n", ret);
+		if (ret != -ENOENT)
+			return ret;
+	}
+
+	return 0;
+}
+
+static int rm72014_panel_probe(struct udevice *dev)
+{
+	struct rm72014_panel_priv *priv = dev_get_priv(dev);
+	struct mipi_dsi_panel_plat *plat = dev_get_plat(dev);
+	int ret;
+
+	ret = regulator_set_enable_if_allowed(priv->reg, true);
+	if (ret && ret != -ENOSYS) {
+		debug("%s: failed to enable regulator '%s' %d\n",
+		      __func__, priv->reg->name, ret);
+		return ret;
+	}
+
+	dm_gpio_set_value(&priv->reset, 0);
+	mdelay(5);
+	dm_gpio_set_value(&priv->reset, 1);
+
+	mdelay(180);
+
+	/* fill characteristics of DSI data link */
+	plat->lanes = 4;
+	plat->format = MIPI_DSI_FMT_RGB888;
+	plat->mode_flags = MIPI_DSI_MODE_VIDEO |
+			   MIPI_DSI_MODE_VIDEO_BURST;
+
+	return 0;
+}
+
+static const struct panel_ops rm72014_panel_ops = {
+	.enable_backlight = rm72014_panel_enable_backlight,
+	.get_display_timing = rm72014_panel_get_display_timing,
+};
+
+static const struct udevice_id rm72014_panel_ids[] = {
+	{ .compatible = "unknown,rm72014" },
+	{ }
+};
+
+U_BOOT_DRIVER(rm72014_panel) = {
+	.name		= "rm72014_panel",
+	.id		= UCLASS_PANEL,
+	.of_match	= rm72014_panel_ids,
+	.ops		= &rm72014_panel_ops,
+	.of_to_plat	= rm72014_panel_of_to_plat,
+	.probe		= rm72014_panel_probe,
+	.plat_auto	= sizeof(struct mipi_dsi_panel_plat),
+	.priv_auto	= sizeof(struct rm72014_panel_priv),
+};
-- 
2.39.5

[PATCH 10/10] board: rockchip: add rk3368 ymd8_mb support

[WeiHao Li]

Signed-off-by: WeiHao Li <ieiao@outlook.com>
---
 arch/arm/dts/Makefile                   |   1 +
 arch/arm/dts/rk3368-ymd8-mb-u-boot.dtsi |  44 ++++
 arch/arm/dts/rk3368-ymd8-mb.dts         | 326 ++++++++++++++++++++++++
 arch/arm/dts/rk3368.dtsi                | 258 +++++++++++++++++++
 arch/arm/mach-rockchip/rk3368/Kconfig   |   6 +
 board/rockchip/ymd8_mb/Kconfig          |  12 +
 board/rockchip/ymd8_mb/MAINTAINERS      |   6 +
 board/rockchip/ymd8_mb/Makefile         |   7 +
 board/rockchip/ymd8_mb/README           |   1 +
 board/rockchip/ymd8_mb/ymd8_mb_rk3368.c |  19 ++
 configs/ymd8-mb_defconfig               |  72 ++++++
 include/configs/ymd8_mb.h               |  11 +
 12 files changed, 763 insertions(+)
 create mode 100644 arch/arm/dts/rk3368-ymd8-mb-u-boot.dtsi
 create mode 100644 arch/arm/dts/rk3368-ymd8-mb.dts
 create mode 100644 board/rockchip/ymd8_mb/Kconfig
 create mode 100644 board/rockchip/ymd8_mb/MAINTAINERS
 create mode 100644 board/rockchip/ymd8_mb/Makefile
 create mode 100644 board/rockchip/ymd8_mb/README
 create mode 100644 board/rockchip/ymd8_mb/ymd8_mb_rk3368.c
 create mode 100644 configs/ymd8-mb_defconfig
 create mode 100644 include/configs/ymd8_mb.h

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 0dc7e190eb..1dfd1c5236 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -73,6 +73,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3368) += \
 	rk3368-sheep.dtb \
 	rk3368-geekbox.dtb \
 	rk3368-px5-evb.dtb \
+	rk3368-ymd8-mb.dtb
 
 dtb-$(CONFIG_ARCH_S5P4418) += \
 	s5p4418-nanopi2.dtb
diff --git a/arch/arm/dts/rk3368-ymd8-mb-u-boot.dtsi b/arch/arm/dts/rk3368-ymd8-mb-u-boot.dtsi
new file mode 100644
index 0000000000..925264e620
--- /dev/null
+++ b/arch/arm/dts/rk3368-ymd8-mb-u-boot.dtsi
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
+ */
+
+#include "rk3368-u-boot.dtsi"
+
+&pinctrl {
+	bootph-all;
+};
+
+&service_msch {
+	bootph-all;
+};
+
+&dmc {
+	bootph-all;
+	status = "okay";
+};
+
+&pmugrf {
+	bootph-all;
+};
+
+&cru {
+	bootph-all;
+};
+
+&grf {
+	bootph-all;
+};
+
+&uart2 {
+	bootph-all;
+	clock-frequency = <24000000>;
+};
+
+&pwm1 {
+	bootph-all;
+};
+
+&vop {
+	bootph-all;
+};
diff --git a/arch/arm/dts/rk3368-ymd8-mb.dts b/arch/arm/dts/rk3368-ymd8-mb.dts
new file mode 100644
index 0000000000..661390b9d5
--- /dev/null
+++ b/arch/arm/dts/rk3368-ymd8-mb.dts
@@ -0,0 +1,326 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2025 Weihao Li
+ */
+
+/dts-v1/;
+#include "rk3368.dtsi"
+#include <dt-bindings/input/input.h>
+
+/ {
+	model = "YMD8_MB";
+	compatible = "rockchip,YMD8_MB", "rockchip,rk3368";
+
+	aliases {
+		mmc0 = &emmc;
+	};
+
+	chosen {
+		stdout-path = "serial2:115200n8";
+	};
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0x0 0x0 0x40000000>;
+	};
+
+	keys: gpio-keys {
+		compatible = "gpio-keys";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pwr_key>;
+
+		power {
+			gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>;
+			label = "GPIO Power";
+			linux,code = <KEY_POWER>;
+			wakeup-source;
+		};
+	};
+
+	vcc_sys: vcc-sys-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_sys";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	backlight: backlight {
+		compatible = "pwm-backlight";
+		power-supply = <&vcc_sys>;
+		enable-gpios = <&gpio0 RK_PD1 GPIO_ACTIVE_HIGH>;
+		brightness-levels = <
+			  0   1   2   3   4   5   6   7
+			  8   9  10  11  12  13  14  15
+			 16  17  18  19  20  21  22  23
+			 24  25  26  27  28  29  30  31
+			 32  33  34  35  36  37  38  39
+			 40  41  42  43  44  45  46  47
+			 48  49  50  51  52  53  54  55
+			 56  57  58  59  60  61  62  63
+			 64  65  66  67  68  69  70  71
+			 72  73  74  75  76  77  78  79
+			 80  81  82  83  84  85  86  87
+			 88  89  90  91  92  93  94  95
+			 96  97  98  99 100 101 102 103
+			104 105 106 107 108 109 110 111
+			112 113 114 115 116 117 118 119
+			120 121 122 123 124 125 126 127
+			128 129 130 131 132 133 134 135
+			136 137 138 139 140 141 142 143
+			144 145 146 147 148 149 150 151
+			152 153 154 155 156 157 158 159
+			160 161 162 163 164 165 166 167
+			168 169 170 171 172 173 174 175
+			176 177 178 179 180 181 182 183
+			184 185 186 187 188 189 190 191
+			192 193 194 195 196 197 198 199
+			200 201 202 203 204 205 206 207
+			208 209 210 211 212 213 214 215
+			216 217 218 219 220 221 222 223
+			224 225 226 227 228 229 230 231
+			232 233 234 235 236 237 238 239
+			240 241 242 243 244 245 246 247
+			248 249 250 251 252 253 254 255>;
+		default-brightness-level = <50>;
+		pwms = <&pwm1 0 25000 0>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pwm1_pin>;
+		status = "okay";
+	};
+
+	panel: panel {
+		compatible = "unknown,rm72014";
+		power-supply = <&vcc_io>;
+		backlight = <&backlight>;
+		reset-gpios = <&gpio0 RK_PC3 GPIO_ACTIVE_HIGH>;
+		status = "okay";
+
+		port {
+			panel_dsi_in: endpoint {
+				remote-endpoint = <&dsi_out_panel>;
+			};
+		};
+	};
+};
+
+&emmc {
+	status = "okay";
+	bus-width = <8>;
+	cap-mmc-highspeed;
+	clock-frequency = <150000000>;
+	mmc-hs200-1_8v;
+	no-sdio;
+	no-sd;
+	non-removable;
+	pinctrl-names = "default";
+	pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_bus8>;
+	vmmc-supply = <&vcc_io>;
+	vqmmc-supply = <&vcc18_flash>;
+};
+
+&i2c0 {
+	status = "okay";
+
+	rk808: pmic@1b {
+		compatible = "rockchip,rk808";
+		reg = <0x1b>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pmic_int>, <&pmic_sleep>;
+		interrupt-parent = <&gpio0>;
+		interrupts = <RK_PA1 IRQ_TYPE_LEVEL_LOW>;
+		rockchip,system-power-controller;
+		vcc1-supply = <&vcc_sys>;
+		vcc2-supply = <&vcc_sys>;
+		vcc3-supply = <&vcc_sys>;
+		vcc4-supply = <&vcc_sys>;
+		vcc6-supply = <&vcc_sys>;
+		vcc7-supply = <&vcc_sys>;
+		vcc8-supply = <&vcc_io>;
+		vcc9-supply = <&vcc_sys>;
+		vcc10-supply = <&vcc_sys>;
+		vcc11-supply = <&vcc_sys>;
+		vcc12-supply = <&vcc_io>;
+		clock-output-names = "xin32k", "rk808-clkout2";
+		#clock-cells = <1>;
+
+		regulators {
+			vdd_cpu: DCDC_REG1 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <700000>;
+				regulator-max-microvolt = <1500000>;
+				regulator-name = "vdd_cpu";
+			};
+
+			vdd_log: DCDC_REG2 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <700000>;
+				regulator-max-microvolt = <1200000>;
+				regulator-name = "vdd_log";
+			};
+
+			vcc_ddr: DCDC_REG3 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1200000>;
+				regulator-max-microvolt = <1200000>;
+				regulator-name = "vcc_ddr";
+			};
+
+			vcc_io: DCDC_REG4 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-name = "vcc_io";
+			};
+
+			vcc18_flash: LDO_REG1 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "vcc18_flash";
+			};
+
+			vcc33_lcd: LDO_REG2 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-name = "vcca_33";
+			};
+
+			vdd_10: LDO_REG3 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1000000>;
+				regulator-max-microvolt = <1000000>;
+				regulator-name = "vdd_10";
+			};
+
+			vcca_18: LDO_REG4 {
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "vcca_18";
+			};
+
+			vccio_sd: LDO_REG5 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-name = "vccio_sd";
+			};
+
+			vdd10_lcd: LDO_REG6 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1000000>;
+				regulator-max-microvolt = <1000000>;
+				regulator-name = "vdd10_lcd";
+			};
+
+			vcc_18: LDO_REG7 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "vcc_18";
+			};
+
+			vcc18_lcd: LDO_REG8 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "vcc18_lcd";
+			};
+
+			vcc_sd: SWITCH_REG1 {
+				regulator-name = "vcc_sd";
+			};
+
+			vcc_lan: SWITCH_REG2 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-name = "vcc_lan";
+			};
+		};
+	};
+};
+
+&pinctrl {
+	keys {
+		pwr_key: pwr-key {
+			rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	pmic {
+		pmic_sleep: pmic-sleep {
+			rockchip,pins = <0 RK_PA0 2 &pcfg_pull_none>;
+		};
+
+		pmic_int: pmic-int {
+			rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+};
+
+&tsadc {
+	status = "okay";
+	rockchip,hw-tshut-mode = <0>; /* CRU */
+	rockchip,hw-tshut-polarity = <1>; /* high */
+};
+
+&uart2 {
+	status = "okay";
+};
+
+&usb_host0_ehci {
+	status = "okay";
+};
+
+&usb_otg {
+	status = "okay";
+};
+
+&wdt {
+	status = "okay";
+};
+
+&pwm1 {
+	status = "okay";
+};
+
+&vop_mmu {
+	status = "okay";
+};
+
+&vop {
+	status = "okay";
+};
+
+&mipi_dsi {
+	status = "okay";
+
+	ports {
+		mipi_out: port@1 {
+			reg = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			dsi_out_panel: endpoint {
+				remote-endpoint = <&panel_dsi_in>;
+			};
+		};
+	};
+};
+
+&video_phy {
+	status = "okay";
+};
diff --git a/arch/arm/dts/rk3368.dtsi b/arch/arm/dts/rk3368.dtsi
index 4c64fbefb4..77ff551681 100644
--- a/arch/arm/dts/rk3368.dtsi
+++ b/arch/arm/dts/rk3368.dtsi
@@ -650,6 +650,62 @@
 			compatible = "rockchip,rk3368-io-voltage-domain";
 			status = "disabled";
 		};
+
+		lvds: lvds {
+			compatible = "rockchip,rk3368-lvds";
+			phys = <&video_phy>;
+			phy-names = "phy";
+			status = "disabled";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				lvds_in: port {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					lvds_in_vop: endpoint@0 {
+						reg = <0>;
+						remote-endpoint = <&vop_out_lvds>;
+					};
+				};
+			};
+		};
+
+		rgb: rgb {
+			compatible = "rockchip,rk3368-rgb";
+			phys = <&video_phy>;
+			phy-names = "phy";
+			pinctrl-names = "default";
+			pinctrl-0 = <&lcdc_rgb_pins>;
+			status = "disabled";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				rgb_in: port {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					rgb_in_vop: endpoint@0 {
+						reg = <0>;
+						remote-endpoint = <&vop_out_rgb>;
+					};
+				};
+			};
+		};
+
+		edp_phy: edp-phy {
+			compatible = "rockchip,rk3368-dp-phy";
+			clocks = <&cru SCLK_EDP_24M>;
+			clock-names = "24m";
+			resets = <&cru SRST_EDP_24M>;
+			reset-names = "edp_24m";
+			#phy-cells = <0>;
+			status = "disabled";
+		};
 	};
 
 	wdt: watchdog@ff800000 {
@@ -740,6 +796,167 @@
 		status = "disabled";
 	};
 
+	vop: vop@ff930000 {
+		compatible = "rockchip,rk3368-vop";
+		rockchip,grf = <&grf>;
+		reg = <0x0 0xff930000 0x0 0x2fc>, <0x0 0xff931000 0x0 0x400>;
+		reg-names = "regs", "gamma_lut";
+		interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>;
+		clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
+		assigned-clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
+		assigned-clock-rates = <400000000>, <200000000>;
+		resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
+		reset-names = "axi", "ahb", "dclk";
+		iommus = <&vop_mmu>;
+		status = "disabled";
+
+		vop_out: port {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			vop_out_dsi: endpoint@0 {
+				reg = <0>;
+				remote-endpoint = <&dsi_in_vop>;
+			};
+
+			vop_out_edp: endpoint@1 {
+				reg = <1>;
+				remote-endpoint = <&edp_in_vop>;
+			};
+
+			vop_out_hdmi: endpoint@2 {
+				reg = <2>;
+				remote-endpoint = <&hdmi_in_vop>;
+			};
+
+			vop_out_lvds: endpoint@3 {
+				reg = <3>;
+				remote-endpoint = <&lvds_in_vop>;
+			};
+
+			vop_out_rgb: endpoint@4 {
+				reg = <4>;
+				remote-endpoint = <&rgb_in_vop>;
+			};
+		};
+	};
+
+	display_subsystem: display-subsystem {
+		compatible = "rockchip,display-subsystem";
+		ports = <&vop_out>;
+		status = "disabled";
+	};
+
+	mipi_dsi: mipi-dsi@ff960000 {
+		compatible = "rockchip,rk3368-mipi-dsi", "snps,dw-mipi-dsi";
+		reg = <0x0 0xff960000 0x0 0x4000>;
+		interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru PCLK_MIPI_DSI0>;
+		clock-names = "pclk";
+		resets = <&cru SRST_MIPIDSI0>;
+		reset-names = "apb";
+		phys = <&video_phy>;
+		phy-names = "dphy";
+		rockchip,grf = <&grf>;
+		status = "disabled";
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			mipi_in: port@0 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				dsi_in_vop: endpoint@0 {
+					reg = <0>;
+					remote-endpoint = <&vop_out_dsi>;
+				};
+			};
+
+			mipi_out: port@1 {
+				reg = <1>;
+			};
+
+		};
+	};
+
+	video_phy: video-phy@ff968000 {
+		compatible = "rockchip,rk3368-dsi-dphy";
+		reg = <0x0 0xff968000 0x0 0x4000>,
+		      <0x0 0xff960000 0x0 0x4000>;
+		clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_DPHYTX0>,
+			 <&cru PCLK_MIPI_DSI0>;
+		clock-names = "ref", "pclk", "pclk_host";
+		#clock-cells = <0>;
+		resets = <&cru SRST_MIPIDPHYTX>;
+		reset-names = "apb";
+		#phy-cells = <0>;
+		status = "disabled";
+	};
+
+	edp: edp@ff970000 {
+		compatible = "rockchip,rk3368-edp";
+		reg = <0x0 0xff970000 0x0 0x8000>;
+		interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
+		clock-names = "dp", "pclk";
+		resets = <&cru SRST_EDP>;
+		reset-names = "dp";
+		rockchip,grf = <&grf>;
+		phys = <&edp_phy>;
+		phy-names = "dp";
+		pinctrl-names = "default";
+		pinctrl-0 = <&edp_hpd>;
+		status = "disabled";
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			edp_in: port {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				edp_in_vop: endpoint@0 {
+					reg = <0>;
+					remote-endpoint = <&vop_out_edp>;
+				};
+			};
+		};
+	};
+
+	hdmi: hdmi@ff980000 {
+		compatible = "rockchip,rk3368-dw-hdmi";
+		reg = <0x0 0xff980000 0x0 0x20000>;
+		reg-io-width = <4>;
+		interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>, <&cru SCLK_HDMI_CEC>;
+		clock-names = "iahb", "isfr", "cec";
+		pinctrl-names = "default";
+		pinctrl-0 = <&hdmi_i2c_xfer>, <&hdmi_cec>;
+		resets = <&cru SRST_HDMI>;
+		reset-names = "hdmi";
+		rockchip,grf = <&grf>;
+		status = "disabled";
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			hdmi_in: port {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				hdmi_in_vop: endpoint@0 {
+					reg = <0>;
+					remote-endpoint = <&vop_out_hdmi>;
+				};
+			};
+		};
+	};
+
 	hevc_mmu: iommu@ff9a0440 {
 		compatible = "rockchip,iommu";
 		reg = <0x0 0xff9a0440 0x0 0x40>,
@@ -1214,5 +1431,46 @@
 				rockchip,pins = <0 RK_PD1 3 &pcfg_pull_none>;
 			};
 		};
+
+		lcdc {
+			lcdc_rgb_pins: lcdc-rgb-pins {
+				rockchip,pins =
+					<0 14 RK_FUNC_1 &pcfg_pull_none>,  /* LCDC_D10 */
+					<0 15 RK_FUNC_1 &pcfg_pull_none>,  /* LCDC_D11 */
+					<0 16 RK_FUNC_1 &pcfg_pull_none>,  /* LCDC_D12 */
+					<0 17 RK_FUNC_1 &pcfg_pull_none>,  /* LCDC_D13 */
+					<0 18 RK_FUNC_1 &pcfg_pull_none>,  /* LCDC_D14 */
+					<0 19 RK_FUNC_1 &pcfg_pull_none>,  /* LCDC_D15 */
+					<0 20 RK_FUNC_1 &pcfg_pull_none>,  /* LCDC_D16 */
+					<0 21 RK_FUNC_1 &pcfg_pull_none>,  /* LCDC_D17 */
+					<0 22 RK_FUNC_1 &pcfg_pull_none>,  /* LCDC_D18 */
+					<0 23 RK_FUNC_1 &pcfg_pull_none>,  /* LCDC_D19 */
+					<0 24 RK_FUNC_1 &pcfg_pull_none>,  /* LCDC_D20 */
+					<0 25 RK_FUNC_1 &pcfg_pull_none>,  /* LCDC_D21 */
+					<0 26 RK_FUNC_1 &pcfg_pull_none>,  /* LCDC_D22 */
+					<0 27 RK_FUNC_1 &pcfg_pull_none>,  /* LCDC_D23 */
+					<0 31 RK_FUNC_1 &pcfg_pull_none>,  /* DCLK */
+					<0 30 RK_FUNC_1 &pcfg_pull_none>,  /* DEN */
+					<0 28 RK_FUNC_1 &pcfg_pull_none>,  /* HSYNC */
+					<0 29 RK_FUNC_1 &pcfg_pull_none>;  /* VSYNC */
+			};
+		};
+
+		edp {
+			edp_hpd: edp-hpd {
+				rockchip,pins = <2 23 RK_FUNC_2 &pcfg_pull_none>;
+			};
+		};
+
+		hdmi {
+			hdmi_cec: hdmi-cec {
+				rockchip,pins = <3 23 RK_FUNC_1 &pcfg_pull_none>;
+			};
+
+			hdmi_i2c_xfer: hdmi-i2c-xfer {
+				rockchip,pins = <3 26 RK_FUNC_1 &pcfg_pull_none>,
+						<3 27 RK_FUNC_1 &pcfg_pull_none>;
+			};
+		};
 	};
 };
diff --git a/arch/arm/mach-rockchip/rk3368/Kconfig b/arch/arm/mach-rockchip/rk3368/Kconfig
index a7be30bbd8..1d05a6784f 100644
--- a/arch/arm/mach-rockchip/rk3368/Kconfig
+++ b/arch/arm/mach-rockchip/rk3368/Kconfig
@@ -21,6 +21,11 @@ config TARGET_EVB_PX5
          HDMI video input/output interface, audio codec ES8396,
          WIFI/BT (on RTL8723BS), Gsensor BMA250E and light&proximity
          sensor STK3410.
+
+config TARGET_YMD8_MB
+	select BOARD_EARLY_INIT_R
+	bool "YMD8_MB board"
+
 endchoice
 
 config ROCKCHIP_BOOT_MODE_REG
@@ -44,6 +49,7 @@ config SPL_LIBGENERIC_SUPPORT
 source "board/rockchip/sheep_rk3368/Kconfig"
 source "board/geekbuying/geekbox/Kconfig"
 source "board/rockchip/evb_px5/Kconfig"
+source "board/rockchip/ymd8_mb/Kconfig"
 
 config SPL_STACK_R_ADDR
 	default 0x04000000
diff --git a/board/rockchip/ymd8_mb/Kconfig b/board/rockchip/ymd8_mb/Kconfig
new file mode 100644
index 0000000000..346c6f4bea
--- /dev/null
+++ b/board/rockchip/ymd8_mb/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_YMD8_MB
+
+config SYS_BOARD
+	default "ymd8_mb"
+
+config SYS_VENDOR
+	default "rockchip"
+
+config SYS_CONFIG_NAME
+	default "ymd8_mb"
+
+endif
diff --git a/board/rockchip/ymd8_mb/MAINTAINERS b/board/rockchip/ymd8_mb/MAINTAINERS
new file mode 100644
index 0000000000..a5156b8be3
--- /dev/null
+++ b/board/rockchip/ymd8_mb/MAINTAINERS
@@ -0,0 +1,6 @@
+RK3368 YMD8_MB Board
+M:	Weihao Li <cn.liweihao@gmail.com>
+S:	Maintained
+F:	board/rockchip/ymd8_mb_rk3368/
+F:	include/configs/ymd8_mb.h
+F:	configs/ymd8-mb_defconfig
diff --git a/board/rockchip/ymd8_mb/Makefile b/board/rockchip/ymd8_mb/Makefile
new file mode 100644
index 0000000000..a3a34edb43
--- /dev/null
+++ b/board/rockchip/ymd8_mb/Makefile
@@ -0,0 +1,7 @@
+#
+# (C) Copyright 2016 Rockchip Electronics Co., Ltd
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y	+= ymd8_mb_rk3368.o
diff --git a/board/rockchip/ymd8_mb/README b/board/rockchip/ymd8_mb/README
new file mode 100644
index 0000000000..de980f2f23
--- /dev/null
+++ b/board/rockchip/ymd8_mb/README
@@ -0,0 +1 @@
+see board/rockchip/sheep_rk3368/README
diff --git a/board/rockchip/ymd8_mb/ymd8_mb_rk3368.c b/board/rockchip/ymd8_mb/ymd8_mb_rk3368.c
new file mode 100644
index 0000000000..96d4e04e95
--- /dev/null
+++ b/board/rockchip/ymd8_mb/ymd8_mb_rk3368.c
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Authors: Weihao Li <cn.liweihao@gmail.com>
+ */
+
+#include <init.h>
+#include <syscon.h>
+#include <asm/global_data.h>
+#include <asm/arch-rockchip/hardware.h>
+#include <asm/arch-rockchip/clock.h>
+#include <asm/arch-rockchip/grf_rk3368.h>
+#include <asm/arch-rockchip/cru_rk3368.h>
+
+int board_early_init_r(void)
+{
+	struct rk3368_cru *cru = rockchip_get_cru();
+	rk_clrsetreg(&cru->clksel_con[43], GMAC_PLL_MASK, GMAC_PLL_SELECT_CODEC);
+	return 0;
+}
diff --git a/configs/ymd8-mb_defconfig b/configs/ymd8-mb_defconfig
new file mode 100644
index 0000000000..f9a2b371ec
--- /dev/null
+++ b/configs/ymd8-mb_defconfig
@@ -0,0 +1,72 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_COUNTER_FREQUENCY=24000000
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_TEXT_BASE=0x00200000
+CONFIG_SYS_MALLOC_F_LEN=0x1000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
+CONFIG_ENV_SIZE=0x1f000
+CONFIG_DEFAULT_DEVICE_TREE="rk3368-ymd8-mb"
+CONFIG_DM_RESET=y
+CONFIG_ROCKCHIP_RK3368=y
+CONFIG_TARGET_YMD8_MB=y
+CONFIG_SYS_LOAD_ADDR=0x800800
+CONFIG_DEBUG_UART_BASE=0xFF690000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART=y
+# CONFIG_EFI_LOADER is not set
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3368-ymd8-mb.dtb"
+# CONFIG_CONSOLE_MUX is not set
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+# CONFIG_CYCLIC is not set
+CONFIG_LAST_STAGE_INIT=y
+CONFIG_CMD_PWM=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_BMP=y
+# CONFIG_CMD_CLS is not set
+CONFIG_CMD_REGULATOR=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_CLK=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_PHY_TI_GENERIC=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_RMII=y
+CONFIG_GMAC_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY=y
+CONFIG_PINCTRL=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_RK8XX=y
+CONFIG_REGULATOR_PWM=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_REGULATOR_RK8XX=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_RAM=y
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_SYS_NS16550_MEM32=y
+CONFIG_SYSRESET=y
+CONFIG_VIDEO=y
+# CONFIG_VIDEO_DAMAGE is not set
+CONFIG_BACKLIGHT_GPIO=y
+# CONFIG_SIMPLE_PANEL is not set
+CONFIG_VIDEO_LCD_RM72014=y
+CONFIG_DISPLAY=y
+CONFIG_VIDEO_ROCKCHIP=y
+CONFIG_VIDEO_ROCKCHIP_MAX_XRES=1280
+CONFIG_VIDEO_ROCKCHIP_MAX_YRES=1920
+CONFIG_DISPLAY_ROCKCHIP_MIPI=y
+CONFIG_DISPLAY_ROCKCHIP_DW_MIPI=y
+CONFIG_VIDEO_BRIDGE=y
+# CONFIG_FAT_WRITE is not set
+CONFIG_ERRNO_STR=y
diff --git a/include/configs/ymd8_mb.h b/include/configs/ymd8_mb.h
new file mode 100644
index 0000000000..ff0ceb4e5f
--- /dev/null
+++ b/include/configs/ymd8_mb.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2017 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef __CONFIGS_YMD8_MB_H
+#define __CONFIGS_YMD8_MB_H
+
+#include <configs/rk3368_common.h>
+
+#endif
-- 
2.39.5

Re: [PATCH 10/10] board: rockchip: add rk3368 ymd8_mb support

[Quentin Schulz]

Hi WeiHao Li,

On 8/7/25 9:44 AM, WeiHao Li wrote:
> [You don't often get email from cn.liweihao@gmail.com. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ]
> 

Please always include a few words in the commit log.

I believe the description of the board as told in the cover letter is 
good enough, so start with that maybe :)

> Signed-off-by: WeiHao Li <ieiao@outlook.com>
> ---
>   arch/arm/dts/Makefile                   |   1 +
>   arch/arm/dts/rk3368-ymd8-mb-u-boot.dtsi |  44 ++++
>   arch/arm/dts/rk3368-ymd8-mb.dts         | 326 ++++++++++++++++++++++++
>   arch/arm/dts/rk3368.dtsi                | 258 +++++++++++++++++++
>   arch/arm/mach-rockchip/rk3368/Kconfig   |   6 +
>   board/rockchip/ymd8_mb/Kconfig          |  12 +
>   board/rockchip/ymd8_mb/MAINTAINERS      |   6 +
>   board/rockchip/ymd8_mb/Makefile         |   7 +
>   board/rockchip/ymd8_mb/README           |   1 +
>   board/rockchip/ymd8_mb/ymd8_mb_rk3368.c |  19 ++
>   configs/ymd8-mb_defconfig               |  72 ++++++
>   include/configs/ymd8_mb.h               |  11 +
>   12 files changed, 763 insertions(+)
>   create mode 100644 arch/arm/dts/rk3368-ymd8-mb-u-boot.dtsi
>   create mode 100644 arch/arm/dts/rk3368-ymd8-mb.dts
>   create mode 100644 board/rockchip/ymd8_mb/Kconfig
>   create mode 100644 board/rockchip/ymd8_mb/MAINTAINERS
>   create mode 100644 board/rockchip/ymd8_mb/Makefile
>   create mode 100644 board/rockchip/ymd8_mb/README
>   create mode 100644 board/rockchip/ymd8_mb/ymd8_mb_rk3368.c
>   create mode 100644 configs/ymd8-mb_defconfig
>   create mode 100644 include/configs/ymd8_mb.h
> 
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index 0dc7e190eb..1dfd1c5236 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -73,6 +73,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3368) += \
>          rk3368-sheep.dtb \
>          rk3368-geekbox.dtb \
>          rk3368-px5-evb.dtb \
> +       rk3368-ymd8-mb.dtb
> 
>   dtb-$(CONFIG_ARCH_S5P4418) += \
>          s5p4418-nanopi2.dtb
> diff --git a/arch/arm/dts/rk3368-ymd8-mb-u-boot.dtsi b/arch/arm/dts/rk3368-ymd8-mb-u-boot.dtsi
> new file mode 100644
> index 0000000000..925264e620
> --- /dev/null
> +++ b/arch/arm/dts/rk3368-ymd8-mb-u-boot.dtsi
> @@ -0,0 +1,44 @@
> +// SPDX-License-Identifier: GPL-2.0+ OR X11
> +/*
> + * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
> + */
> +

I'm quite sure Theobroma didn't work on that, and not in 2017 :)

Please remove us (Theobroma got renamed to Cherry Embedded Solutions 
last year) from this copyright notice and provide the appropriate 
copyright holder there instead.

> +#include "rk3368-u-boot.dtsi"
> +
> +&pinctrl {
> +       bootph-all;
> +};
> +
> +&service_msch {
> +       bootph-all;
> +};
> +
> +&dmc {
> +       bootph-all;
> +       status = "okay";
> +};
> +
> +&pmugrf {
> +       bootph-all;
> +};
> +
> +&cru {
> +       bootph-all;
> +};
> +
> +&grf {
> +       bootph-all;
> +};
> +
> +&uart2 {
> +       bootph-all;
> +       clock-frequency = <24000000>;
> +};
> +
> +&pwm1 {
> +       bootph-all;
> +};
> +
> +&vop {
> +       bootph-all;
> +};
> diff --git a/arch/arm/dts/rk3368-ymd8-mb.dts b/arch/arm/dts/rk3368-ymd8-mb.dts
> new file mode 100644
> index 0000000000..661390b9d5
> --- /dev/null
> +++ b/arch/arm/dts/rk3368-ymd8-mb.dts

Are you planning to support this board in upstream Linux as well? I'm 
sure Heiko would welcome it. If so, maybe think about selecting 
OF_UPSTREAM for your board once the device tree is merged upstream and 
appears in dts/upstream directory in U-Boot? It may not be easy to do as 
no RK3368-based board has been migrated to use OF_UPSTREAM yet.

We typically do not allow (in Rockchip) to support new boards without 
OF_UPSTREAM, but considering how old and how little activity we see for 
RK3368 maybe Kever will let this pass?

> @@ -0,0 +1,326 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (c) 2025 Weihao Li
> + */
> +
> +/dts-v1/;
> +#include "rk3368.dtsi"
> +#include <dt-bindings/input/input.h>
> +
> +/ {
> +       model = "YMD8_MB";
> +       compatible = "rockchip,YMD8_MB", "rockchip,rk3368";

The first compatible isn't right if Rockchip isn't the actual 
manufacturer/seller of the whole product. I couldn't see anything on the 
PCB picture you posted on your wiki but maybe there's some information 
on the casing or elsewhere?

[...]

> diff --git a/arch/arm/dts/rk3368.dtsi b/arch/arm/dts/rk3368.dtsi
> index 4c64fbefb4..77ff551681 100644
> --- a/arch/arm/dts/rk3368.dtsi
> +++ b/arch/arm/dts/rk3368.dtsi

Nope, this we won't allow.

If you add support for a board, don't modify the device tree of the SoC 
in the same patch. Please separate those changes from the patch adding 
supoprt for the board.

Here, because the rk3368.dtsi already exists, you'll need a patch per 
logical thing you are adding. There are a few I could notice here:
- hdmi
- lvds
- rgb
- edp
- dsi
- vop

First, only add what you tested. I believe this would be DSI+VOP only?

Second, where did you get all the info? I don't see anything in upstream 
Linux's rk3368.dtsi so it must come from somewhere else? Where? Please 
specify this in the commit logs. it would be very nice to have this sent 
and reviewed by the Linux kernel community as well.

[...]

> diff --git a/arch/arm/mach-rockchip/rk3368/Kconfig b/arch/arm/mach-rockchip/rk3368/Kconfig
> index a7be30bbd8..1d05a6784f 100644
> --- a/arch/arm/mach-rockchip/rk3368/Kconfig
> +++ b/arch/arm/mach-rockchip/rk3368/Kconfig
> @@ -21,6 +21,11 @@ config TARGET_EVB_PX5
>            HDMI video input/output interface, audio codec ES8396,
>            WIFI/BT (on RTL8723BS), Gsensor BMA250E and light&proximity
>            sensor STK3410.
> +
> +config TARGET_YMD8_MB
> +       select BOARD_EARLY_INIT_R
> +       bool "YMD8_MB board"
> +

Please add a help text so we have some clue what this board actually is.

[...]

> diff --git a/board/rockchip/ymd8_mb/MAINTAINERS b/board/rockchip/ymd8_mb/MAINTAINERS
> new file mode 100644
> index 0000000000..a5156b8be3
> --- /dev/null
> +++ b/board/rockchip/ymd8_mb/MAINTAINERS
> @@ -0,0 +1,6 @@
> +RK3368 YMD8_MB Board
> +M:     Weihao Li <cn.liweihao@gmail.com>
> +S:     Maintained
> +F:     board/rockchip/ymd8_mb_rk3368/

This is also missing the new device tree you added which you need to 
maintain.

> +F:     include/configs/ymd8_mb.h
> +F:     configs/ymd8-mb_defconfig
> diff --git a/board/rockchip/ymd8_mb/Makefile b/board/rockchip/ymd8_mb/Makefile
> new file mode 100644
> index 0000000000..a3a34edb43
> --- /dev/null
> +++ b/board/rockchip/ymd8_mb/Makefile
> @@ -0,0 +1,7 @@
> +#
> +# (C) Copyright 2016 Rockchip Electronics Co., Ltd
> +#
> +# SPDX-License-Identifier:     GPL-2.0+
> +#
> +
> +obj-y  += ymd8_mb_rk3368.o
> diff --git a/board/rockchip/ymd8_mb/README b/board/rockchip/ymd8_mb/README
> new file mode 100644
> index 0000000000..de980f2f23
> --- /dev/null
> +++ b/board/rockchip/ymd8_mb/README
> @@ -0,0 +1 @@
> +see board/rockchip/sheep_rk3368/README

I don't think that's right.

Remove this file and add a proper entry in doc/board/rockchip for this 
board (or its own documentation file like we did for Theobroma boards, 
up to you if there are important details that typically differ from 
other Rockchip boards).

Cheers,
Quentin

Re: [PATCH 10/10] board: rockchip: add rk3368 ymd8_mb support

[李维豪]

Hi Quentin,

Thanks for your review.

Quentin Schulz <quentin.schulz@cherry.de> 于2025年8月11日周一 23:01写道：
>
> Hi WeiHao Li,
>
> On 8/7/25 9:44 AM, WeiHao Li wrote:
> > [You don't often get email from cn.liweihao@gmail.com. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ]
> >
>
> Please always include a few words in the commit log.
>

I will add some necessary description in the commit log.

> I believe the description of the board as told in the cover letter is
> good enough, so start with that maybe :)
>
> > Signed-off-by: WeiHao Li <ieiao@outlook.com>
> > ---
> >   arch/arm/dts/Makefile                   |   1 +
> >   arch/arm/dts/rk3368-ymd8-mb-u-boot.dtsi |  44 ++++
> >   arch/arm/dts/rk3368-ymd8-mb.dts         | 326 ++++++++++++++++++++++++
> >   arch/arm/dts/rk3368.dtsi                | 258 +++++++++++++++++++
> >   arch/arm/mach-rockchip/rk3368/Kconfig   |   6 +
> >   board/rockchip/ymd8_mb/Kconfig          |  12 +
> >   board/rockchip/ymd8_mb/MAINTAINERS      |   6 +
> >   board/rockchip/ymd8_mb/Makefile         |   7 +
> >   board/rockchip/ymd8_mb/README           |   1 +
> >   board/rockchip/ymd8_mb/ymd8_mb_rk3368.c |  19 ++
> >   configs/ymd8-mb_defconfig               |  72 ++++++
> >   include/configs/ymd8_mb.h               |  11 +
> >   12 files changed, 763 insertions(+)
> >   create mode 100644 arch/arm/dts/rk3368-ymd8-mb-u-boot.dtsi
> >   create mode 100644 arch/arm/dts/rk3368-ymd8-mb.dts
> >   create mode 100644 board/rockchip/ymd8_mb/Kconfig
> >   create mode 100644 board/rockchip/ymd8_mb/MAINTAINERS
> >   create mode 100644 board/rockchip/ymd8_mb/Makefile
> >   create mode 100644 board/rockchip/ymd8_mb/README
> >   create mode 100644 board/rockchip/ymd8_mb/ymd8_mb_rk3368.c
> >   create mode 100644 configs/ymd8-mb_defconfig
> >   create mode 100644 include/configs/ymd8_mb.h
> >
> > diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> > index 0dc7e190eb..1dfd1c5236 100644
> > --- a/arch/arm/dts/Makefile
> > +++ b/arch/arm/dts/Makefile
> > @@ -73,6 +73,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3368) += \
> >          rk3368-sheep.dtb \
> >          rk3368-geekbox.dtb \
> >          rk3368-px5-evb.dtb \
> > +       rk3368-ymd8-mb.dtb
> >
> >   dtb-$(CONFIG_ARCH_S5P4418) += \
> >          s5p4418-nanopi2.dtb
> > diff --git a/arch/arm/dts/rk3368-ymd8-mb-u-boot.dtsi b/arch/arm/dts/rk3368-ymd8-mb-u-boot.dtsi
> > new file mode 100644
> > index 0000000000..925264e620
> > --- /dev/null
> > +++ b/arch/arm/dts/rk3368-ymd8-mb-u-boot.dtsi
> > @@ -0,0 +1,44 @@
> > +// SPDX-License-Identifier: GPL-2.0+ OR X11
> > +/*
> > + * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
> > + */
> > +
>
> I'm quite sure Theobroma didn't work on that, and not in 2017 :)
>
> Please remove us (Theobroma got renamed to Cherry Embedded Solutions
> last year) from this copyright notice and provide the appropriate
> copyright holder there instead.
>

Got it.

> > +#include "rk3368-u-boot.dtsi"
> > +
> > +&pinctrl {
> > +       bootph-all;
> > +};
> > +
> > +&service_msch {
> > +       bootph-all;
> > +};
> > +
> > +&dmc {
> > +       bootph-all;
> > +       status = "okay";
> > +};
> > +
> > +&pmugrf {
> > +       bootph-all;
> > +};
> > +
> > +&cru {
> > +       bootph-all;
> > +};
> > +
> > +&grf {
> > +       bootph-all;
> > +};
> > +
> > +&uart2 {
> > +       bootph-all;
> > +       clock-frequency = <24000000>;
> > +};
> > +
> > +&pwm1 {
> > +       bootph-all;
> > +};
> > +
> > +&vop {
> > +       bootph-all;
> > +};
> > diff --git a/arch/arm/dts/rk3368-ymd8-mb.dts b/arch/arm/dts/rk3368-ymd8-mb.dts
> > new file mode 100644
> > index 0000000000..661390b9d5
> > --- /dev/null
> > +++ b/arch/arm/dts/rk3368-ymd8-mb.dts
>
> Are you planning to support this board in upstream Linux as well? I'm
> sure Heiko would welcome it. If so, maybe think about selecting
> OF_UPSTREAM for your board once the device tree is merged upstream and
> appears in dts/upstream directory in U-Boot? It may not be easy to do as
> no RK3368-based board has been migrated to use OF_UPSTREAM yet.
>
> We typically do not allow (in Rockchip) to support new boards without
> OF_UPSTREAM, but considering how old and how little activity we see for
> RK3368 maybe Kever will let this pass?
>

Yes, I'm planning to suport this board in upstream Linux. but it may take some
time.

Maybe I can separate this patch serial to 2 set, one for driver fix, another for
board support., the board support patchset submit after upstream Linux merged?

> > @@ -0,0 +1,326 @@
> > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> > +/*
> > + * Copyright (c) 2025 Weihao Li
> > + */
> > +
> > +/dts-v1/;
> > +#include "rk3368.dtsi"
> > +#include <dt-bindings/input/input.h>
> > +
> > +/ {
> > +       model = "YMD8_MB";
> > +       compatible = "rockchip,YMD8_MB", "rockchip,rk3368";
>
> The first compatible isn't right if Rockchip isn't the actual
> manufacturer/seller of the whole product. I couldn't see anything on the
> PCB picture you posted on your wiki but maybe there's some information
> on the casing or elsewhere?

I do not find any manufacturer info for now, I will try to search later.

>
> [...]
>
> > diff --git a/arch/arm/dts/rk3368.dtsi b/arch/arm/dts/rk3368.dtsi
> > index 4c64fbefb4..77ff551681 100644
> > --- a/arch/arm/dts/rk3368.dtsi
> > +++ b/arch/arm/dts/rk3368.dtsi
>
> Nope, this we won't allow.
>
> If you add support for a board, don't modify the device tree of the SoC
> in the same patch. Please separate those changes from the patch adding
> supoprt for the board.
>
> Here, because the rk3368.dtsi already exists, you'll need a patch per
> logical thing you are adding. There are a few I could notice here:
> - hdmi
> - lvds
> - rgb
> - edp
> - dsi
> - vop
>
> First, only add what you tested. I believe this would be DSI+VOP only?
>

It's reasonable, I'll fix that.

> Second, where did you get all the info? I don't see anything in upstream
> Linux's rk3368.dtsi so it must come from somewhere else? Where? Please
> specify this in the commit logs. it would be very nice to have this sent
> and reviewed by the Linux kernel community as well.
>

I cross-referenced the downstream U-Boot and Linux repositories of
Rockchip and made some reasonable inferences based on drivers for the
same series of SoCs.

I will add this information to commit log at next submit.

> [...]
>
> > diff --git a/arch/arm/mach-rockchip/rk3368/Kconfig b/arch/arm/mach-rockchip/rk3368/Kconfig
> > index a7be30bbd8..1d05a6784f 100644
> > --- a/arch/arm/mach-rockchip/rk3368/Kconfig
> > +++ b/arch/arm/mach-rockchip/rk3368/Kconfig
> > @@ -21,6 +21,11 @@ config TARGET_EVB_PX5
> >            HDMI video input/output interface, audio codec ES8396,
> >            WIFI/BT (on RTL8723BS), Gsensor BMA250E and light&proximity
> >            sensor STK3410.
> > +
> > +config TARGET_YMD8_MB
> > +       select BOARD_EARLY_INIT_R
> > +       bool "YMD8_MB board"
> > +
>
> Please add a help text so we have some clue what this board actually is.
>

Got it.

> [...]
>
> > diff --git a/board/rockchip/ymd8_mb/MAINTAINERS b/board/rockchip/ymd8_mb/MAINTAINERS
> > new file mode 100644
> > index 0000000000..a5156b8be3
> > --- /dev/null
> > +++ b/board/rockchip/ymd8_mb/MAINTAINERS
> > @@ -0,0 +1,6 @@
> > +RK3368 YMD8_MB Board
> > +M:     Weihao Li <cn.liweihao@gmail.com>
> > +S:     Maintained
> > +F:     board/rockchip/ymd8_mb_rk3368/
>
> This is also missing the new device tree you added which you need to
> maintain.

Got it

>
> > +F:     include/configs/ymd8_mb.h
> > +F:     configs/ymd8-mb_defconfig
> > diff --git a/board/rockchip/ymd8_mb/Makefile b/board/rockchip/ymd8_mb/Makefile
> > new file mode 100644
> > index 0000000000..a3a34edb43
> > --- /dev/null
> > +++ b/board/rockchip/ymd8_mb/Makefile
> > @@ -0,0 +1,7 @@
> > +#
> > +# (C) Copyright 2016 Rockchip Electronics Co., Ltd
> > +#
> > +# SPDX-License-Identifier:     GPL-2.0+
> > +#
> > +
> > +obj-y  += ymd8_mb_rk3368.o
> > diff --git a/board/rockchip/ymd8_mb/README b/board/rockchip/ymd8_mb/README
> > new file mode 100644
> > index 0000000000..de980f2f23
> > --- /dev/null
> > +++ b/board/rockchip/ymd8_mb/README
> > @@ -0,0 +1 @@
> > +see board/rockchip/sheep_rk3368/README
>
> I don't think that's right.
>
> Remove this file and add a proper entry in doc/board/rockchip for this
> board (or its own documentation file like we did for Theobroma boards,
> up to you if there are important details that typically differ from
> other Rockchip boards).

I forgot to modify it when I separate patch, I'll adjust that.

>
> Cheers,
> Quentin

Best regards,
WeiHao

Re: [PATCH 10/10] board: rockchip: add rk3368 ymd8_mb support

[Quentin Schulz]

Hi WeiHao,

On 8/12/25 3:25 AM, 李维豪 wrote:
> Hi Quentin,
> 
> Thanks for your review.
> 
> Quentin Schulz <quentin.schulz@cherry.de> 于2025年8月11日周一 23:01写道：
>>
>> Hi WeiHao Li,
>>
>> On 8/7/25 9:44 AM, WeiHao Li wrote:
>>> [You don't often get email from cn.liweihao@gmail.com. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ]
>>>
>>
>> Please always include a few words in the commit log.
>>
> 
> I will add some necessary description in the commit log.
> 
>> I believe the description of the board as told in the cover letter is
>> good enough, so start with that maybe :)
>>
>>> Signed-off-by: WeiHao Li <ieiao@outlook.com>
>>> ---
>>>    arch/arm/dts/Makefile                   |   1 +
>>>    arch/arm/dts/rk3368-ymd8-mb-u-boot.dtsi |  44 ++++
>>>    arch/arm/dts/rk3368-ymd8-mb.dts         | 326 ++++++++++++++++++++++++
>>>    arch/arm/dts/rk3368.dtsi                | 258 +++++++++++++++++++
>>>    arch/arm/mach-rockchip/rk3368/Kconfig   |   6 +
>>>    board/rockchip/ymd8_mb/Kconfig          |  12 +
>>>    board/rockchip/ymd8_mb/MAINTAINERS      |   6 +
>>>    board/rockchip/ymd8_mb/Makefile         |   7 +
>>>    board/rockchip/ymd8_mb/README           |   1 +
>>>    board/rockchip/ymd8_mb/ymd8_mb_rk3368.c |  19 ++
>>>    configs/ymd8-mb_defconfig               |  72 ++++++
>>>    include/configs/ymd8_mb.h               |  11 +
>>>    12 files changed, 763 insertions(+)
>>>    create mode 100644 arch/arm/dts/rk3368-ymd8-mb-u-boot.dtsi
>>>    create mode 100644 arch/arm/dts/rk3368-ymd8-mb.dts
>>>    create mode 100644 board/rockchip/ymd8_mb/Kconfig
>>>    create mode 100644 board/rockchip/ymd8_mb/MAINTAINERS
>>>    create mode 100644 board/rockchip/ymd8_mb/Makefile
>>>    create mode 100644 board/rockchip/ymd8_mb/README
>>>    create mode 100644 board/rockchip/ymd8_mb/ymd8_mb_rk3368.c
>>>    create mode 100644 configs/ymd8-mb_defconfig
>>>    create mode 100644 include/configs/ymd8_mb.h
>>>
>>> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
>>> index 0dc7e190eb..1dfd1c5236 100644
>>> --- a/arch/arm/dts/Makefile
>>> +++ b/arch/arm/dts/Makefile
>>> @@ -73,6 +73,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3368) += \
>>>           rk3368-sheep.dtb \
>>>           rk3368-geekbox.dtb \
>>>           rk3368-px5-evb.dtb \
>>> +       rk3368-ymd8-mb.dtb
>>>
>>>    dtb-$(CONFIG_ARCH_S5P4418) += \
>>>           s5p4418-nanopi2.dtb
>>> diff --git a/arch/arm/dts/rk3368-ymd8-mb-u-boot.dtsi b/arch/arm/dts/rk3368-ymd8-mb-u-boot.dtsi
>>> new file mode 100644
>>> index 0000000000..925264e620
>>> --- /dev/null
>>> +++ b/arch/arm/dts/rk3368-ymd8-mb-u-boot.dtsi
>>> @@ -0,0 +1,44 @@
>>> +// SPDX-License-Identifier: GPL-2.0+ OR X11
>>> +/*
>>> + * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
>>> + */
>>> +
>>
>> I'm quite sure Theobroma didn't work on that, and not in 2017 :)
>>
>> Please remove us (Theobroma got renamed to Cherry Embedded Solutions
>> last year) from this copyright notice and provide the appropriate
>> copyright holder there instead.
>>
> 
> Got it.
> 
>>> +#include "rk3368-u-boot.dtsi"
>>> +
>>> +&pinctrl {
>>> +       bootph-all;
>>> +};
>>> +
>>> +&service_msch {
>>> +       bootph-all;
>>> +};
>>> +
>>> +&dmc {
>>> +       bootph-all;
>>> +       status = "okay";
>>> +};
>>> +
>>> +&pmugrf {
>>> +       bootph-all;
>>> +};
>>> +
>>> +&cru {
>>> +       bootph-all;
>>> +};
>>> +
>>> +&grf {
>>> +       bootph-all;
>>> +};
>>> +
>>> +&uart2 {
>>> +       bootph-all;
>>> +       clock-frequency = <24000000>;
>>> +};
>>> +
>>> +&pwm1 {
>>> +       bootph-all;
>>> +};
>>> +
>>> +&vop {
>>> +       bootph-all;
>>> +};
>>> diff --git a/arch/arm/dts/rk3368-ymd8-mb.dts b/arch/arm/dts/rk3368-ymd8-mb.dts
>>> new file mode 100644
>>> index 0000000000..661390b9d5
>>> --- /dev/null
>>> +++ b/arch/arm/dts/rk3368-ymd8-mb.dts
>>
>> Are you planning to support this board in upstream Linux as well? I'm
>> sure Heiko would welcome it. If so, maybe think about selecting
>> OF_UPSTREAM for your board once the device tree is merged upstream and
>> appears in dts/upstream directory in U-Boot? It may not be easy to do as
>> no RK3368-based board has been migrated to use OF_UPSTREAM yet.
>>
>> We typically do not allow (in Rockchip) to support new boards without
>> OF_UPSTREAM, but considering how old and how little activity we see for
>> RK3368 maybe Kever will let this pass?
>>
> 
> Yes, I'm planning to suport this board in upstream Linux. but it may take some
> time.

That's great to hear. Have fun!

> 
> Maybe I can separate this patch serial to 2 set, one for driver fix, another for
> board support., the board support patchset submit after upstream Linux merged?
> 

That seems like a good idea to me! You may need to send device tree 
fixes for rk3368.dtsi in U-Boot so that we can see the "user" of the 
drivers you are writing/fixing but we don't necessarily need an actual 
end product using it if I remember correctly.

If you send the patch series for adding support to your board before the 
patch series for the driver fixes is merged, please specify the former 
depends on the latter by providing the link to the latter in the mailing 
list archive (e.g. from lore.kernel.org/u-boot) in the cover-letter of 
the former.

>>> @@ -0,0 +1,326 @@
>>> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
>>> +/*
>>> + * Copyright (c) 2025 Weihao Li
>>> + */
>>> +
>>> +/dts-v1/;
>>> +#include "rk3368.dtsi"
>>> +#include <dt-bindings/input/input.h>
>>> +
>>> +/ {
>>> +       model = "YMD8_MB";
>>> +       compatible = "rockchip,YMD8_MB", "rockchip,rk3368";
>>
>> The first compatible isn't right if Rockchip isn't the actual
>> manufacturer/seller of the whole product. I couldn't see anything on the
>> PCB picture you posted on your wiki but maybe there's some information
>> on the casing or elsewhere?
> 
> I do not find any manufacturer info for now, I will try to search later.
> 
>>
>> [...]
>>
>>> diff --git a/arch/arm/dts/rk3368.dtsi b/arch/arm/dts/rk3368.dtsi
>>> index 4c64fbefb4..77ff551681 100644
>>> --- a/arch/arm/dts/rk3368.dtsi
>>> +++ b/arch/arm/dts/rk3368.dtsi
>>
>> Nope, this we won't allow.
>>
>> If you add support for a board, don't modify the device tree of the SoC
>> in the same patch. Please separate those changes from the patch adding
>> supoprt for the board.
>>
>> Here, because the rk3368.dtsi already exists, you'll need a patch per
>> logical thing you are adding. There are a few I could notice here:
>> - hdmi
>> - lvds
>> - rgb
>> - edp
>> - dsi
>> - vop
>>
>> First, only add what you tested. I believe this would be DSI+VOP only?
>>
> 
> It's reasonable, I'll fix that.
> 
>> Second, where did you get all the info? I don't see anything in upstream
>> Linux's rk3368.dtsi so it must come from somewhere else? Where? Please
>> specify this in the commit logs. it would be very nice to have this sent
>> and reviewed by the Linux kernel community as well.
>>
> 
> I cross-referenced the downstream U-Boot and Linux repositories of
> Rockchip and made some reasonable inferences based on drivers for the
> same series of SoCs.
> 
> I will add this information to commit log at next submit.
> 

Thanks. Ideally once the nodes are added in the kernel device tree, 
U-Boot device tree nodes should be sync'ed to match if they differ and 
do the appropriate changes in drivers. This would make it easier to do 
the migration to OF_UPSTREAM for example.

Cheers,
Quentin

Re: [PATCH 02/10] mmc: rockchip: fix clock get wrong index

[Jonas Karlman]

Hi,

On 8/7/2025 9:44 AM, WeiHao Li wrote:
> Signed-off-by: WeiHao Li <ieiao@outlook.com>
> ---
>  drivers/mmc/rockchip_dw_mmc.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/mmc/rockchip_dw_mmc.c b/drivers/mmc/rockchip_dw_mmc.c
> index 7a72abaa38..a3f001d7e7 100644
> --- a/drivers/mmc/rockchip_dw_mmc.c
> +++ b/drivers/mmc/rockchip_dw_mmc.c
> @@ -132,7 +132,7 @@ static int rockchip_dwmmc_probe(struct udevice *dev)
>  
>  	ret = clk_get_by_phandle(dev, &dtplat->clocks[1], &priv->clk);
>  #else
> -	ret = clk_get_by_index(dev, 1, &priv->clk);
> +	ret = clk_get_by_index(dev, 0, &priv->clk);

Index 1 is the ciu clk and matches the linux driver and u-boot driver
usage of the clock.

Please explain why you think this should use index 0?

Could it be the device tree that is using "wrong" clock order?,
the dt-binding define following order: biu, ciu, ciu-drive, ciu-sample.

Or possible an issue in the rk3368 u-boot clk driver?

Also if this is wrong then &dtplat->clocks[1] should also be changed.

Regards,
Jonas

>  #endif
>  	if (ret < 0 && ret != -ENOSYS)
>  		return log_msg_ret("clk", ret);

Re: [PATCH 02/10] mmc: rockchip: fix clock get wrong index

[李维豪]

Hi Jonas,

Thanks for your review.

Jonas Karlman <jonas@kwiboo.se> 于2025年8月13日周三 01:50写道：
>
> Hi,
>
> On 8/7/2025 9:44 AM, WeiHao Li wrote:
> > Signed-off-by: WeiHao Li <ieiao@outlook.com>
> > ---
> >  drivers/mmc/rockchip_dw_mmc.c | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/mmc/rockchip_dw_mmc.c b/drivers/mmc/rockchip_dw_mmc.c
> > index 7a72abaa38..a3f001d7e7 100644
> > --- a/drivers/mmc/rockchip_dw_mmc.c
> > +++ b/drivers/mmc/rockchip_dw_mmc.c
> > @@ -132,7 +132,7 @@ static int rockchip_dwmmc_probe(struct udevice *dev)
> >
> >       ret = clk_get_by_phandle(dev, &dtplat->clocks[1], &priv->clk);
> >  #else
> > -     ret = clk_get_by_index(dev, 1, &priv->clk);
> > +     ret = clk_get_by_index(dev, 0, &priv->clk);
>
> Index 1 is the ciu clk and matches the linux driver and u-boot driver
> usage of the clock.
>
> Please explain why you think this should use index 0?
>
> Could it be the device tree that is using "wrong" clock order?,
> the dt-binding define following order: biu, ciu, ciu-drive, ciu-sample.
>
> Or possible an issue in the rk3368 u-boot clk driver?
>
> Also if this is wrong then &dtplat->clocks[1] should also be changed.

I'm also a little confused about this part, so I rechecking this part
last night.

I saw the rockchip downstream uboot driver uses index 0 at first and it works.
But I noticed upstream driver commit history switch index between 0 and 1
multi times, and stay 1 at then end.

Then I looked rockchip other SOC's clock driver like RK3399 and RK3288, both
of these drivers are support HCLK_EMMC&SCLK_EMMC and its have exactly
same logic.

Because of that, I think the best solution is add SCLK_EMMC clock for RK3368,
I'll add and test it later.

Please ignore this patch, I think it's inappropriate.

>
> Regards,
> Jonas
>
> >  #endif
> >       if (ret < 0 && ret != -ENOSYS)
> >               return log_msg_ret("clk", ret);
>

Best regards,
WeiHao