[PATCH 0/1] armv8: reduce core errata dispatch work

[PATCH 0/1] armv8: reduce core errata dispatch work

[Josh Law]

Hey folks,

apply_core_errata() runs during early ARMv8 CPU entry, before
lowlevel_init(). Today it still checks the Cortex-A53 and Cortex-A57
paths even when the build has no matching core erratum enabled.

This patch leaves that dispatch code out unless one of the supported
errata is enabled. For the A57 errata case, it reads MIDR_EL1 once and
reuses the extracted CPU part number.

The erratum register writes stay behind the same CPU checks as before.
For qemu_arm64_defconfig, where none of these errata are enabled,
apply_core_errata() goes from 15 dispatch instructions to a single ret.
For ls2080aqds_qspi_defconfig, which keeps the A57 path, the dispatch
side goes from 33 instructions to 26. A KVM microbench of the same
dispatch sequences showed 1.30x for the no errata case and 1.09x for
the A57 miss case.

Josh Law (1):
  armv8: reduce core errata dispatch work

 arch/arm/cpu/armv8/start.S | 35 ++++++++++++++++++++++++-----------
 1 file changed, 24 insertions(+), 11 deletions(-)

-- 
2.47.3

[PATCH 1/1] armv8: reduce core errata dispatch work

[Josh Law]

apply_core_errata() currently runs both Cortex A53 and A57 part
checks even when no matching erratum is built in. For boards with no
ARM core errata, that means two MIDR_EL1 reads and two comparisons
on every CPU entry before lowlevel_init().

Only build the dispatch code when one of the supported errata is
enabled. When A57 errata are enabled, read MIDR_EL1 once and reuse
the extracted part number.

Measured on qemu_arm64_defconfig and ls2080aqds_qspi_defconfig:

Case                         before   after
qemu start.o text bytes      392      336
qemu linked text bytes       1437007  1436963
qemu dispatch instructions   15       1
ls2080 start.o text bytes    600      576
ls2080 dispatch instructions 33       26

A KVM virt microbench using the same dispatch instruction sequences
and one million calls gave:

Case            before ticks/call  after ticks/call  speedup
no errata path  27.09              20.78             1.30x
A57 miss path   28.93              26.50             1.09x

Signed-off-by: Josh Law <josh2@disroot.org>
---
 arch/arm/cpu/armv8/start.S | 35 ++++++++++++++++++++++++-----------
 1 file changed, 24 insertions(+), 11 deletions(-)

diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S
index 40c342e97e9..5c847ed0f85 100644
--- a/arch/arm/cpu/armv8/start.S
+++ b/arch/arm/cpu/armv8/start.S
@@ -209,30 +209,41 @@ master_cpu:
 
 /*-----------------------------------------------------------------------*/
 
+#if defined(CONFIG_ARM_ERRATA_826974) || defined(CONFIG_ARM_ERRATA_828024) || \
+	defined(CONFIG_ARM_ERRATA_829520) || defined(CONFIG_ARM_ERRATA_833069) || \
+	defined(CONFIG_ARM_ERRATA_833471)
+#define ARMV8_CORTEX_A57_ERRATA
+#endif
+
 WEAK(apply_core_errata)
 
+#if defined(CONFIG_ARM_ERRATA_855873) || defined(ARMV8_CORTEX_A57_ERRATA)
 	mov	x29, lr			/* Save LR */
 	/* For now, we support Cortex-A53, Cortex-A57 specific errata */
+	mrs	x0, midr_el1
+	ubfx	x1, x0, #4, #12		/* CPU part number */
 
-	/* Check if we are running on a Cortex-A53 core */
-	branch_if_a53_core x0, apply_a53_core_errata
+#ifdef CONFIG_ARM_ERRATA_855873
+	cmp	x1, #0xD03		/* Cortex-A53 MPCore processor */
+	b.eq	apply_a53_core_errata
+#endif
 
-	/* Check if we are running on a Cortex-A57 core */
-	branch_if_a57_core x0, apply_a57_core_errata
+#ifdef ARMV8_CORTEX_A57_ERRATA
+	cmp	x1, #0xD07		/* Cortex-A57 MPCore processor */
+	b.eq	apply_a57_core_errata
+#endif
 0:
 	mov	lr, x29			/* Restore LR */
+#endif
 	ret
 
-apply_a53_core_errata:
-
 #ifdef CONFIG_ARM_ERRATA_855873
-	mrs	x0, midr_el1
+apply_a53_core_errata:
 	tst	x0, #(0xf << 20)
 	b.ne	0b
 
-	mrs	x0, midr_el1
-	and	x0, x0, #0xf
-	cmp	x0, #3
+	and	x1, x0, #0xf
+	cmp	x1, #3
 	b.lt	0b
 
 	mrs	x0, S3_1_c15_c2_0	/* cpuactlr_el1 */
@@ -240,9 +251,10 @@ apply_a53_core_errata:
 	orr	x0, x0, #1 << 44
 	msr	S3_1_c15_c2_0, x0	/* cpuactlr_el1 */
 	isb
-#endif
 	b 0b
+#endif
 
+#ifdef ARMV8_CORTEX_A57_ERRATA
 apply_a57_core_errata:
 
 #ifdef CONFIG_ARM_ERRATA_828024
@@ -294,6 +306,7 @@ apply_a57_core_errata:
 	isb
 #endif
 	b 0b
+#endif
 ENDPROC(apply_core_errata)
 
 /*-----------------------------------------------------------------------*/
-- 
2.47.3

Re: [PATCH 0/1] armv8: reduce core errata dispatch work

[Krzysztof Kozlowski]

On 24/05/2026 14:38, Josh Law wrote:
> Hey folks,
> 
> apply_core_errata() runs during early ARMv8 CPU entry, before
> lowlevel_init(). Today it still checks the Cortex-A53 and Cortex-A57
> paths even when the build has no matching core erratum enabled.
> 
> This patch leaves that dispatch code out unless one of the supported
> errata is enabled. For the A57 errata case, it reads MIDR_EL1 once and
> reuses the extracted CPU part number.
> 
> The erratum register writes stay behind the same CPU checks as before.
> For qemu_arm64_defconfig, where none of these errata are enabled,
> apply_core_errata() goes from 15 dispatch instructions to a single ret.
> For ls2080aqds_qspi_defconfig, which keeps the A57 path, the dispatch
> side goes from 33 instructions to 26. A KVM microbench of the same
> dispatch sequences showed 1.30x for the no errata case and 1.09x for
> the A57 miss case.
> 
> Josh Law (1):
>   armv8: reduce core errata dispatch work

That's another identity from Josh Law, since all previous got NAKed, and
100% AI generated code without review and without tests (I don't believe
what was claimed above).

I recommend ignoring and here is some background:

https://lore.kernel.org/all/cbd0aafa-bd45-4f4d-a2dd-440473657dba@lucifer.local/

Best regards,
Krzysztof

Re: [PATCH 0/1] armv8: reduce core errata dispatch work

[Ilias Apalodimas]

Thanks for the heads up Krzysztof

On Tue, May 26, 2026, 08:01 Krzysztof Kozlowski <krzk@kernel.org> wrote:

> On 24/05/2026 14:38, Josh Law wrote:
> > Hey folks,
> >
> > apply_core_errata() runs during early ARMv8 CPU entry, before
> > lowlevel_init(). Today it still checks the Cortex-A53 and Cortex-A57
> > paths even when the build has no matching core erratum enabled.
> >
> > This patch leaves that dispatch code out unless one of the supported
> > errata is enabled. For the A57 errata case, it reads MIDR_EL1 once and
> > reuses the extracted CPU part number.
> >
> > The erratum register writes stay behind the same CPU checks as before.
> > For qemu_arm64_defconfig, where none of these errata are enabled,
> > apply_core_errata() goes from 15 dispatch instructions to a single ret.
> > For ls2080aqds_qspi_defconfig, which keeps the A57 path, the dispatch
> > side goes from 33 instructions to 26. A KVM microbench of the same
> > dispatch sequences showed 1.30x for the no errata case and 1.09x for
> > the A57 miss case.
> >
> > Josh Law (1):
> >   armv8: reduce core errata dispatch work
>
> That's another identity from Josh Law, since all previous got NAKed, and
> 100% AI generated code without review and without tests (I don't believe
> what was claimed above).
>
> I recommend ignoring and here is some background:
>
>
> https://lore.kernel.org/all/cbd0aafa-bd45-4f4d-a2dd-440473657dba@lucifer.local/
>
> Best regards,
> Krzysztof
>

Re: [PATCH 0/1] armv8: reduce core errata dispatch work

[Josh Law]

On May 26, 2026 12:11:06 PM GMT+01:00, Ilias Apalodimas
<ilias.apalodimas@linaro.org> wrote:
>Thanks for the heads up Krzysztof


Hey Ilias, Could you please review the patch "code wise"?

I did put the testing I had in patch 1s commit description 

I know it may not be sufficient enough, but unfortunately my machine 
isn't the strongest, so sometimes KVM crashes booting u-boot

Proof:

josh@armbox:~# uname -m
aarch64

josh@armbox:~# ls /dev/kvm
/dev/kvm

josh@armbox:~/contrib/u-boot#  qemu-system-aarch64 \
>     -machine virt,accel=kvm \
>     -cpu host \
>     -m 1024 \
>     -display none \
>     -serial stdio \
>     -monitor none \
>     -no-reboot \
>     -bios build-qemu-arm64/u-boot.bin
qemu-system-aarch64: Failed to put registers after init: Invalid argument


Note: ^ I did get tcg sort of working + a KVM small test, (for the results) but u-boot doesn't like me :(


If you would like to still pursue this, I'll try to build it. And give
correct numbers

It's fine if you don't.

If there is a bug in the diff or if the test coverage is not
enough for this path I will take care of it. If you are concerned about
authorship, provenance, or how I tested it, please ask me directly what you
need for this submission. 

I get that the U-Boot team wants a tad more oversight here. Id rather
be judged on the patch itself, on the basis of the diff
and the evidence in this thread, not on history from a different project.
 
[Snip extras! :)]

Thanks! :)

Re: [PATCH 0/1] armv8: reduce core errata dispatch work

[Tom Rini]

[-- Attachment #1: Type: text/plain, Size: 1524 bytes --]

On Tue, May 26, 2026 at 08:01:16AM +0200, Krzysztof Kozlowski wrote:
> On 24/05/2026 14:38, Josh Law wrote:
> > Hey folks,
> > 
> > apply_core_errata() runs during early ARMv8 CPU entry, before
> > lowlevel_init(). Today it still checks the Cortex-A53 and Cortex-A57
> > paths even when the build has no matching core erratum enabled.
> > 
> > This patch leaves that dispatch code out unless one of the supported
> > errata is enabled. For the A57 errata case, it reads MIDR_EL1 once and
> > reuses the extracted CPU part number.
> > 
> > The erratum register writes stay behind the same CPU checks as before.
> > For qemu_arm64_defconfig, where none of these errata are enabled,
> > apply_core_errata() goes from 15 dispatch instructions to a single ret.
> > For ls2080aqds_qspi_defconfig, which keeps the A57 path, the dispatch
> > side goes from 33 instructions to 26. A KVM microbench of the same
> > dispatch sequences showed 1.30x for the no errata case and 1.09x for
> > the A57 miss case.
> > 
> > Josh Law (1):
> >   armv8: reduce core errata dispatch work
> 
> That's another identity from Josh Law, since all previous got NAKed, and
> 100% AI generated code without review and without tests (I don't believe
> what was claimed above).
> 
> I recommend ignoring and here is some background:
> 
> https://lore.kernel.org/all/cbd0aafa-bd45-4f4d-a2dd-440473657dba@lucifer.local/

Well crap. Thanks for the link! I've moved all of the submissions to
Deferred in patchwork.

-- 
Tom

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