[U-Boot] [PATCH v3 05/14] mx51: Fix USB PHY clocks

["Benoît Thébaudeau" <benoit.thebaudeau@advansee.com>]

The i.MX51 has a single USB PHY clock, while the i.MX53 has two. These 3 clocks
have different clock gate control bit-fields.

The existing code was correct only for i.MX53, so this patch fixes the i.MX51
use case.

Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Jana Rapava <fermata7@gmail.com>
Cc: Wolfgang Grandegger <wg@denx.de>
Cc: Igor Grinberg <grinberg@compulab.co.il>
---
This patch supersedes http://patchwork.ozlabs.org/patch/187458/ .
Changes for v2:
 - Split patch into 3 parts (the 3, 4 and 5 from this v2 series).
 - Merge the various set_usb_phy*_clk() functions (they were identical).
Changes for v3:
 - Use same functions on i.MX51 (with one empty) as on i.MX53 in order to avoid
   #ifdef's.

 .../arch/arm/cpu/armv7/mx5/clock.c                 |   25 ++++++++++++++------
 .../arch/arm/include/asm/arch-mx5/clock.h          |    3 ++-
 .../drivers/usb/host/ehci-mx5.c                    |    3 ++-
 3 files changed, 22 insertions(+), 9 deletions(-)

diff --git u-boot-imx-e1eb75b.orig/arch/arm/cpu/armv7/mx5/clock.c u-boot-imx-e1eb75b/arch/arm/cpu/armv7/mx5/clock.c
index df7e5cd..fd5456e 100644
--- u-boot-imx-e1eb75b.orig/arch/arm/cpu/armv7/mx5/clock.c
+++ u-boot-imx-e1eb75b/arch/arm/cpu/armv7/mx5/clock.c
@@ -126,23 +126,33 @@ int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
 }
 #endif
 
-void set_usb_phy1_clk(void)
+void set_usb_phy_clk(void)
 {
 	clrbits_le32(&mxc_ccm->cscmr1, MXC_CCM_CSCMR1_USB_PHY_CLK_SEL);
 }
 
+#if defined(CONFIG_MX51)
 void enable_usb_phy1_clk(unsigned char enable)
 {
 	unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
 
-	clrsetbits_le32(&mxc_ccm->CCGR4,
-			MXC_CCM_CCGR4_USB_PHY1(MXC_CCM_CCGR_CG_MASK),
-			MXC_CCM_CCGR4_USB_PHY1(cg));
+	clrsetbits_le32(&mxc_ccm->CCGR2,
+			MXC_CCM_CCGR2_USB_PHY(MXC_CCM_CCGR_CG_MASK),
+			MXC_CCM_CCGR2_USB_PHY(cg));
 }
 
-void set_usb_phy2_clk(void)
+void enable_usb_phy2_clk(unsigned char enable)
 {
-	clrbits_le32(&mxc_ccm->cscmr1, MXC_CCM_CSCMR1_USB_PHY_CLK_SEL);
+	/* i.MX51 has a single USB PHY clock, so do nothing here. */
+}
+#elif defined(CONFIG_MX53)
+void enable_usb_phy1_clk(unsigned char enable)
+{
+	unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
+
+	clrsetbits_le32(&mxc_ccm->CCGR4,
+			MXC_CCM_CCGR4_USB_PHY1(MXC_CCM_CCGR_CG_MASK),
+			MXC_CCM_CCGR4_USB_PHY1(cg));
 }
 
 void enable_usb_phy2_clk(unsigned char enable)
@@ -153,6 +163,7 @@ void enable_usb_phy2_clk(unsigned char enable)
 			MXC_CCM_CCGR4_USB_PHY2(MXC_CCM_CCGR_CG_MASK),
 			MXC_CCM_CCGR4_USB_PHY2(cg));
 }
+#endif
 
 /*
  * Calculate the frequency of PLLn.
@@ -803,7 +814,7 @@ void mxc_set_sata_internal_clock(void)
 	u32 *tmp_base =
 		(u32 *)(IIM_BASE_ADDR + 0x180c);
 
-	set_usb_phy1_clk();
+	set_usb_phy_clk();
 
 	clrsetbits_le32(tmp_base, 0x6, 0x4);
 }
diff --git u-boot-imx-e1eb75b.orig/arch/arm/include/asm/arch-mx5/clock.h u-boot-imx-e1eb75b/arch/arm/include/asm/arch-mx5/clock.h
index 55e3b51..668e913 100644
--- u-boot-imx-e1eb75b.orig/arch/arm/include/asm/arch-mx5/clock.h
+++ u-boot-imx-e1eb75b/arch/arm/include/asm/arch-mx5/clock.h
@@ -56,7 +56,8 @@ u32 imx_get_uartclk(void);
 u32 imx_get_fecclk(void);
 unsigned int mxc_get_clock(enum mxc_clock clk);
 int mxc_set_clock(u32 ref, u32 freq, u32 clk_type);
-void set_usb_phy2_clk(void);
+void set_usb_phy_clk(void);
+void enable_usb_phy1_clk(unsigned char enable);
 void enable_usb_phy2_clk(unsigned char enable);
 void set_usboh3_clk(void);
 void enable_usboh3_clk(unsigned char enable);
diff --git u-boot-imx-e1eb75b.orig/drivers/usb/host/ehci-mx5.c u-boot-imx-e1eb75b/drivers/usb/host/ehci-mx5.c
index 58cdcbe..fbfd310 100644
--- u-boot-imx-e1eb75b.orig/drivers/usb/host/ehci-mx5.c
+++ u-boot-imx-e1eb75b/drivers/usb/host/ehci-mx5.c
@@ -221,7 +221,8 @@ int ehci_hcd_init(void)
 
 	set_usboh3_clk();
 	enable_usboh3_clk(1);
-	set_usb_phy2_clk();
+	set_usb_phy_clk();
+	enable_usb_phy1_clk(1);
 	enable_usb_phy2_clk(1);
 	mdelay(1);