From: "Benoît Thébaudeau" <benoit.thebaudeau@advansee.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH v2 06/14] mx5 clocks: Add and use CCSR definitions
Date: Thu, 27 Sep 2012 22:22:22 +0200 (CEST) [thread overview]
Message-ID: <2052331962.5372389.1348777342031.JavaMail.root@advansee.com> (raw)
In-Reply-To: <1065839952.5372238.1348777198067.JavaMail.root@advansee.com>
This fixes config_pll_clk(), which used 0x20 instead of 0x200 for PLL4_CLOCK.
Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
---
This patch supersedes http://patchwork.ozlabs.org/patch/177404/ .
Changes for v2:
- Consequences from the previous cleanup patches.
.../arch/arm/cpu/armv7/mx5/clock.c | 34 +++++++++++++-------
.../arch/arm/include/asm/arch-mx5/crm_regs.h | 23 +++++++++++++
2 files changed, 46 insertions(+), 11 deletions(-)
diff --git u-boot-imx-e1eb75b.orig/arch/arm/cpu/armv7/mx5/clock.c u-boot-imx-e1eb75b/arch/arm/cpu/armv7/mx5/clock.c
index f727cfa..137a6f9 100644
--- u-boot-imx-e1eb75b.orig/arch/arm/cpu/armv7/mx5/clock.c
+++ u-boot-imx-e1eb75b/arch/arm/cpu/armv7/mx5/clock.c
@@ -36,7 +36,9 @@ enum pll_clocks {
PLL1_CLOCK = 0,
PLL2_CLOCK,
PLL3_CLOCK,
+#ifdef CONFIG_MX53
PLL4_CLOCK,
+#endif
PLL_CLOCKS,
};
@@ -318,10 +320,10 @@ static u32 get_lp_apm(void)
u32 ret_val = 0;
u32 ccsr = readl(&mxc_ccm->ccsr);
- if (((ccsr >> 9) & 1) == 0)
- ret_val = MXC_HCLK;
- else
+ if (ccsr & MXC_CCM_CCSR_LP_APM)
ret_val = MXC_CLK32 * 1024;
+ else
+ ret_val = MXC_HCLK;
return ret_val;
}
@@ -587,40 +589,50 @@ static int config_pll_clk(enum pll_clocks index, struct pll_param *pll_param)
switch (index) {
case PLL1_CLOCK:
/* Switch ARM to PLL2 clock */
- writel(ccsr | 0x4, &mxc_ccm->ccsr);
+ writel(ccsr | MXC_CCM_CCSR_PLL1_SW_CLK_SEL,
+ &mxc_ccm->ccsr);
CHANGE_PLL_SETTINGS(pll, pll_param->pd,
pll_param->mfi, pll_param->mfn,
pll_param->mfd);
/* Switch back */
- writel(ccsr & ~0x4, &mxc_ccm->ccsr);
+ writel(ccsr & ~MXC_CCM_CCSR_PLL1_SW_CLK_SEL,
+ &mxc_ccm->ccsr);
break;
case PLL2_CLOCK:
/* Switch to pll2 bypass clock */
- writel(ccsr | 0x2, &mxc_ccm->ccsr);
+ writel(ccsr | MXC_CCM_CCSR_PLL2_SW_CLK_SEL,
+ &mxc_ccm->ccsr);
CHANGE_PLL_SETTINGS(pll, pll_param->pd,
pll_param->mfi, pll_param->mfn,
pll_param->mfd);
/* Switch back */
- writel(ccsr & ~0x2, &mxc_ccm->ccsr);
+ writel(ccsr & ~MXC_CCM_CCSR_PLL2_SW_CLK_SEL,
+ &mxc_ccm->ccsr);
break;
case PLL3_CLOCK:
/* Switch to pll3 bypass clock */
- writel(ccsr | 0x1, &mxc_ccm->ccsr);
+ writel(ccsr | MXC_CCM_CCSR_PLL3_SW_CLK_SEL,
+ &mxc_ccm->ccsr);
CHANGE_PLL_SETTINGS(pll, pll_param->pd,
pll_param->mfi, pll_param->mfn,
pll_param->mfd);
/* Switch back */
- writel(ccsr & ~0x1, &mxc_ccm->ccsr);
+ writel(ccsr & ~MXC_CCM_CCSR_PLL3_SW_CLK_SEL,
+ &mxc_ccm->ccsr);
break;
+#ifdef CONFIG_MX53
case PLL4_CLOCK:
/* Switch to pll4 bypass clock */
- writel(ccsr | 0x20, &mxc_ccm->ccsr);
+ writel(ccsr | MXC_CCM_CCSR_PLL4_SW_CLK_SEL,
+ &mxc_ccm->ccsr);
CHANGE_PLL_SETTINGS(pll, pll_param->pd,
pll_param->mfi, pll_param->mfn,
pll_param->mfd);
/* Switch back */
- writel(ccsr & ~0x20, &mxc_ccm->ccsr);
+ writel(ccsr & ~MXC_CCM_CCSR_PLL4_SW_CLK_SEL,
+ &mxc_ccm->ccsr);
break;
+#endif
default:
return -EINVAL;
}
diff --git u-boot-imx-e1eb75b.orig/arch/arm/include/asm/arch-mx5/crm_regs.h u-boot-imx-e1eb75b/arch/arm/include/asm/arch-mx5/crm_regs.h
index 3b0ed64..56dceb4 100644
--- u-boot-imx-e1eb75b.orig/arch/arm/include/asm/arch-mx5/crm_regs.h
+++ u-boot-imx-e1eb75b/arch/arm/include/asm/arch-mx5/crm_regs.h
@@ -82,6 +82,29 @@ struct mxc_ccm_reg {
u32 cmeor;
};
+/* Define the bits in register CCSR */
+#if defined(CONFIG_MX51)
+#define MXC_CCM_CCSR_LP_APM (0x1 << 9)
+#elif defined(CONFIG_MX53)
+#define MXC_CCM_CCSR_LP_APM (0x1 << 10)
+#define MXC_CCM_CCSR_PLL4_SW_CLK_SEL (0x1 << 9)
+#endif
+#define MXC_CCM_CCSR_STEP_SEL_OFFSET 7
+#define MXC_CCM_CCSR_STEP_SEL_MASK (0x3 << 7)
+#define MXC_CCM_CCSR_STEP_SEL(v) (((v) & 0x3) << 7)
+#define MXC_CCM_CCSR_STEP_SEL_RD(r) (((r) >> 7) & 0x3)
+#define MXC_CCM_CCSR_PLL2_DIV_PODF_OFFSET 5
+#define MXC_CCM_CCSR_PLL2_DIV_PODF_MASK (0x3 << 5)
+#define MXC_CCM_CCSR_PLL2_DIV_PODF(v) (((v) & 0x3) << 5)
+#define MXC_CCM_CCSR_PLL2_DIV_PODF_RD(r) (((r) >> 5) & 0x3)
+#define MXC_CCM_CCSR_PLL3_DIV_PODF_OFFSET 3
+#define MXC_CCM_CCSR_PLL3_DIV_PODF_MASK (0x3 << 3)
+#define MXC_CCM_CCSR_PLL3_DIV_PODF(v) (((v) & 0x3) << 3)
+#define MXC_CCM_CCSR_PLL3_DIV_PODF_RD(r) (((r) >> 3) & 0x3)
+#define MXC_CCM_CCSR_PLL1_SW_CLK_SEL (0x1 << 2)
+#define MXC_CCM_CCSR_PLL2_SW_CLK_SEL (0x1 << 1)
+#define MXC_CCM_CCSR_PLL3_SW_CLK_SEL 0x1
+
/* Define the bits in register CACRR */
#define MXC_CCM_CACRR_ARM_PODF_OFFSET 0
#define MXC_CCM_CACRR_ARM_PODF_MASK 0x7
next prev parent reply other threads:[~2012-09-27 20:22 UTC|newest]
Thread overview: 52+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-08-14 18:05 [U-Boot] [PATCH 00/10] mx5: Fix clocks Benoît Thébaudeau
2012-08-14 18:06 ` [U-Boot] [PATCH 01/10] mx5: Undeclare imx_decode_pll() Benoît Thébaudeau
2012-08-23 9:10 ` Stefano Babic
2012-08-14 18:06 ` [U-Boot] [PATCH 02/10] mx5: Use explicit clock gate names Benoît Thébaudeau
2012-08-14 18:54 ` Marek Vasut
2012-08-14 19:13 ` Benoît Thébaudeau
2012-09-27 20:19 ` [U-Boot] [PATCH v2 01/14] mx5/6: Define default SoC input clock frequencies Benoît Thébaudeau
2012-09-27 20:20 ` [U-Boot] [PATCH v2 02/14] mx5 clocks: Cleanup Benoît Thébaudeau
2012-09-28 8:44 ` Stefano Babic
2012-09-27 20:21 ` [U-Boot] [PATCH v2 03/14] mx5: Use explicit clock gate names Benoît Thébaudeau
2012-09-28 8:53 ` Stefano Babic
2012-09-27 20:21 ` [U-Boot] [PATCH v2 04/14] mx5: Fix clock gate values Benoît Thébaudeau
2012-09-27 20:21 ` [U-Boot] [PATCH v2 05/14] mx51: Fix USB PHY clocks Benoît Thébaudeau
2012-09-27 20:47 ` Marek Vasut
2012-09-28 7:26 ` Igor Grinberg
2012-09-28 10:27 ` Benoît Thébaudeau
2012-09-28 10:43 ` Stefano Babic
2012-09-28 13:00 ` Benoît Thébaudeau
2012-09-28 15:02 ` Stefano Babic
2012-09-28 17:09 ` [U-Boot] [PATCH v3 " Benoît Thébaudeau
2012-10-02 8:35 ` Igor Grinberg
2012-09-27 20:22 ` Benoît Thébaudeau [this message]
2012-09-27 20:22 ` [U-Boot] [PATCH v2 07/14] mx5 clocks: Fix get_lp_apm() Benoît Thébaudeau
2012-09-27 20:22 ` [U-Boot] [PATCH v2 08/14] mx5 clocks: Fix get_periph_clk() Benoît Thébaudeau
2012-09-27 20:23 ` [U-Boot] [PATCH v2 09/14] mx5 clocks: Fix get_ipg_per_clk() Benoît Thébaudeau
2012-09-28 9:31 ` Stefano Babic
2012-09-28 10:42 ` Benoît Thébaudeau
2012-09-28 10:45 ` Stefano Babic
2012-09-28 12:55 ` Benoît Thébaudeau
2012-09-28 15:01 ` Stefano Babic
2012-09-27 20:23 ` [U-Boot] [PATCH v2 10/14] mx5 clocks: Fix get_uart_clk() Benoît Thébaudeau
2012-09-27 20:23 ` [U-Boot] [PATCH v2 11/14] mx5 clocks: Simplify imx_get_cspiclk() Benoît Thébaudeau
2012-09-27 20:23 ` [U-Boot] [PATCH v2 12/14] mx5 clocks: Fix MXC_FEC_CLK Benoît Thébaudeau
2012-09-27 20:24 ` [U-Boot] [PATCH v2 13/14] mx51: Fix I2C clock ID check Benoît Thébaudeau
2012-09-27 20:24 ` [U-Boot] [PATCH v2 14/14] mx5/6 clocks: Fix SDHC clocks Benoît Thébaudeau
2012-09-28 8:42 ` [U-Boot] [PATCH v2 01/14] mx5/6: Define default SoC input clock frequencies Stefano Babic
2012-09-30 10:28 ` Stefano Babic
2012-09-30 13:55 ` Benoît Thébaudeau
2012-09-30 14:05 ` Stefano Babic
2012-08-14 18:06 ` [U-Boot] [PATCH 03/10] mx5 clocks: Add and use CCSR definitions Benoît Thébaudeau
2012-08-14 18:55 ` Marek Vasut
2012-08-14 19:14 ` Benoît Thébaudeau
2012-08-14 19:11 ` Marek Vasut
2012-08-14 18:07 ` [U-Boot] [PATCH 04/10] mx5 clocks: Fix get_lp_apm() Benoît Thébaudeau
2012-08-14 18:07 ` [U-Boot] [PATCH 05/10] mx5 clocks: Fix get_periph_clk() Benoît Thébaudeau
2012-08-14 18:07 ` [U-Boot] [PATCH 06/10] mx5 clocks: Fix get_ipg_per_clk() Benoît Thébaudeau
2012-08-14 18:07 ` [U-Boot] [PATCH 07/10] mx5 clocks: Fix get_uart_clk() Benoît Thébaudeau
2012-08-20 9:52 ` Stefano Babic
2012-08-20 10:05 ` Stefano Babic
2012-08-14 18:07 ` [U-Boot] [PATCH 08/10] mx5 clocks: Simplify imx_get_cspiclk() Benoît Thébaudeau
2012-08-14 18:08 ` [U-Boot] [PATCH 09/10] mx5 clocks: Fix eSDHC clock Benoît Thébaudeau
2012-08-14 18:08 ` [U-Boot] [PATCH 10/10] mx5 clocks: Fix MXC_FEC_CLK Benoît Thébaudeau
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