[U-Boot] [PATCH v2 02/14] mx5 clocks: Cleanup

["Benoît Thébaudeau" <benoit.thebaudeau@advansee.com>]

Clean up the i.MX5 clock driver:
 - Use readl() and writel() instead of their __raw_ counterparts.
 - Use the clr/setbits_le32() family of macros rather than expanding code.
 - Use accessor macros for bit-fields instead of _MASK and _OFFSET.

Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
---
Changes for v2:
 - New patch.

 .../arch/arm/cpu/armv7/mx5/clock.c                 |  237 ++++++++------------
 .../arch/arm/include/asm/arch-mx5/crm_regs.h       |   99 +++++++-
 2 files changed, 184 insertions(+), 152 deletions(-)

diff --git u-boot-imx-e1eb75b.orig/arch/arm/cpu/armv7/mx5/clock.c u-boot-imx-e1eb75b/arch/arm/cpu/armv7/mx5/clock.c
index 1f95536..5fca775 100644
--- u-boot-imx-e1eb75b.orig/arch/arm/cpu/armv7/mx5/clock.c
+++ u-boot-imx-e1eb75b/arch/arm/cpu/armv7/mx5/clock.c
@@ -89,94 +89,65 @@ struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
 
 void set_usboh3_clk(void)
 {
-	unsigned int reg;
-
-	reg = readl(&mxc_ccm->cscmr1) &
-		 ~MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK;
-	reg |= 1 << MXC_CCM_CSCMR1_USBOH3_CLK_SEL_OFFSET;
-	writel(reg, &mxc_ccm->cscmr1);
-
-	reg = readl(&mxc_ccm->cscdr1);
-	reg &= ~MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK;
-	reg &= ~MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK;
-	reg |= 4 << MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET;
-	reg |= 1 << MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET;
-
-	writel(reg, &mxc_ccm->cscdr1);
+	clrsetbits_le32(&mxc_ccm->cscmr1,
+			MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK,
+			MXC_CCM_CSCMR1_USBOH3_CLK_SEL(1));
+	clrsetbits_le32(&mxc_ccm->cscdr1,
+			MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK |
+			MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK,
+			MXC_CCM_CSCDR1_USBOH3_CLK_PRED(4) |
+			MXC_CCM_CSCDR1_USBOH3_CLK_PODF(1));
 }
 
 void enable_usboh3_clk(unsigned char enable)
 {
-	unsigned int reg;
-
-	reg = readl(&mxc_ccm->CCGR2);
 	if (enable)
-		reg |= 1 << MXC_CCM_CCGR2_CG14_OFFSET;
+		setbits_le32(&mxc_ccm->CCGR2, 1 << MXC_CCM_CCGR2_CG14_OFFSET);
 	else
-		reg &= ~(1 << MXC_CCM_CCGR2_CG14_OFFSET);
-	writel(reg, &mxc_ccm->CCGR2);
+		clrbits_le32(&mxc_ccm->CCGR2, 1 << MXC_CCM_CCGR2_CG14_OFFSET);
 }
 
 #ifdef CONFIG_I2C_MXC
 /* i2c_num can be from 0 - 2 */
 int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
 {
-	u32 reg;
 	u32 mask;
 
 	if (i2c_num > 2)
 		return -EINVAL;
 	mask = MXC_CCM_CCGR_CG_MASK << ((i2c_num + 9) << 1);
-	reg = __raw_readl(&mxc_ccm->CCGR1);
 	if (enable)
-		reg |= mask;
+		setbits_le32(&mxc_ccm->CCGR1, mask);
 	else
-		reg &= ~mask;
-	__raw_writel(reg, &mxc_ccm->CCGR1);
+		clrbits_le32(&mxc_ccm->CCGR1, mask);
 	return 0;
 }
 #endif
 
 void set_usb_phy1_clk(void)
 {
-	unsigned int reg;
-
-	reg = readl(&mxc_ccm->cscmr1);
-	reg &= ~MXC_CCM_CSCMR1_USB_PHY_CLK_SEL;
-	writel(reg, &mxc_ccm->cscmr1);
+	clrbits_le32(&mxc_ccm->cscmr1, MXC_CCM_CSCMR1_USB_PHY_CLK_SEL);
 }
 
 void enable_usb_phy1_clk(unsigned char enable)
 {
-	unsigned int reg;
-
-	reg = readl(&mxc_ccm->CCGR4);
 	if (enable)
-		reg |= 1 << MXC_CCM_CCGR4_CG5_OFFSET;
+		setbits_le32(&mxc_ccm->CCGR4, 1 << MXC_CCM_CCGR4_CG5_OFFSET);
 	else
-		reg &= ~(1 << MXC_CCM_CCGR4_CG5_OFFSET);
-	writel(reg, &mxc_ccm->CCGR4);
+		clrbits_le32(&mxc_ccm->CCGR4, 1 << MXC_CCM_CCGR4_CG5_OFFSET);
 }
 
 void set_usb_phy2_clk(void)
 {
-	unsigned int reg;
-
-	reg = readl(&mxc_ccm->cscmr1);
-	reg &= ~MXC_CCM_CSCMR1_USB_PHY_CLK_SEL;
-	writel(reg, &mxc_ccm->cscmr1);
+	clrbits_le32(&mxc_ccm->cscmr1, MXC_CCM_CSCMR1_USB_PHY_CLK_SEL);
 }
 
 void enable_usb_phy2_clk(unsigned char enable)
 {
-	unsigned int reg;
-
-	reg = readl(&mxc_ccm->CCGR4);
 	if (enable)
-		reg |= 1 << MXC_CCM_CCGR4_CG6_OFFSET;
+		setbits_le32(&mxc_ccm->CCGR4, 1 << MXC_CCM_CCGR4_CG6_OFFSET);
 	else
-		reg &= ~(1 << MXC_CCM_CCGR4_CG6_OFFSET);
-	writel(reg, &mxc_ccm->CCGR4);
+		clrbits_le32(&mxc_ccm->CCGR4, 1 << MXC_CCM_CCGR4_CG6_OFFSET);
 }
 
 /*
@@ -191,19 +162,19 @@ static uint32_t decode_pll(struct mxc_pll_reg *pll, uint32_t infreq)
 	ctrl = readl(&pll->ctrl);
 
 	if (ctrl & MXC_DPLLC_CTL_HFSM) {
-		mfn = __raw_readl(&pll->hfs_mfn);
-		mfd = __raw_readl(&pll->hfs_mfd);
-		op = __raw_readl(&pll->hfs_op);
+		mfn = readl(&pll->hfs_mfn);
+		mfd = readl(&pll->hfs_mfd);
+		op = readl(&pll->hfs_op);
 	} else {
-		mfn = __raw_readl(&pll->mfn);
-		mfd = __raw_readl(&pll->mfd);
-		op = __raw_readl(&pll->op);
+		mfn = readl(&pll->mfn);
+		mfd = readl(&pll->mfd);
+		op = readl(&pll->op);
 	}
 
 	mfd &= MXC_DPLLC_MFD_MFD_MASK;
 	mfn &= MXC_DPLLC_MFN_MFN_MASK;
 	pdf = op & MXC_DPLLC_OP_PDF_MASK;
-	mfi = (op & MXC_DPLLC_OP_MFI_MASK) >> MXC_DPLLC_OP_MFI_OFFSET;
+	mfi = MXC_DPLLC_OP_MFI_RD(op);
 
 	/* 21.2.3 */
 	if (mfi < 5)
@@ -240,8 +211,7 @@ u32 get_mcu_main_clk(void)
 {
 	u32 reg, freq;
 
-	reg = (__raw_readl(&mxc_ccm->cacrr) & MXC_CCM_CACRR_ARM_PODF_MASK) >>
-		MXC_CCM_CACRR_ARM_PODF_OFFSET;
+	reg = MXC_CCM_CACRR_ARM_PODF_RD(readl(&mxc_ccm->cacrr));
 	freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
 	return freq / (reg + 1);
 }
@@ -253,12 +223,11 @@ u32 get_periph_clk(void)
 {
 	u32 reg;
 
-	reg = __raw_readl(&mxc_ccm->cbcdr);
+	reg = readl(&mxc_ccm->cbcdr);
 	if (!(reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL))
 		return decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK);
-	reg = __raw_readl(&mxc_ccm->cbcmr);
-	switch ((reg & MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK) >>
-		MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET) {
+	reg = readl(&mxc_ccm->cbcmr);
+	switch (MXC_CCM_CBCMR_PERIPH_CLK_SEL_RD(reg)) {
 	case 0:
 		return decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
 	case 1:
@@ -278,9 +247,8 @@ static u32 get_ipg_clk(void)
 
 	freq = get_ahb_clk();
 
-	reg = __raw_readl(&mxc_ccm->cbcdr);
-	div = ((reg & MXC_CCM_CBCDR_IPG_PODF_MASK) >>
-			MXC_CCM_CBCDR_IPG_PODF_OFFSET) + 1;
+	reg = readl(&mxc_ccm->cbcdr);
+	div = MXC_CCM_CBCDR_IPG_PODF_RD(reg) + 1;
 
 	return freq / div;
 }
@@ -292,17 +260,13 @@ static u32 get_ipg_per_clk(void)
 {
 	u32 pred1, pred2, podf;
 
-	if (__raw_readl(&mxc_ccm->cbcmr) & MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL)
+	if (readl(&mxc_ccm->cbcmr) & MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL)
 		return get_ipg_clk();
 	/* Fixme: not handle what about lpm*/
-	podf = __raw_readl(&mxc_ccm->cbcdr);
-	pred1 = (podf & MXC_CCM_CBCDR_PERCLK_PRED1_MASK) >>
-		MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET;
-	pred2 = (podf & MXC_CCM_CBCDR_PERCLK_PRED2_MASK) >>
-		MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET;
-	podf = (podf & MXC_CCM_CBCDR_PERCLK_PODF_MASK) >>
-		MXC_CCM_CBCDR_PERCLK_PODF_OFFSET;
-
+	podf = readl(&mxc_ccm->cbcdr);
+	pred1 = MXC_CCM_CBCDR_PERCLK_PRED1_RD(podf);
+	pred2 = MXC_CCM_CBCDR_PERCLK_PRED2_RD(podf);
+	podf = MXC_CCM_CBCDR_PERCLK_PODF_RD(podf);
 	return get_periph_clk() / ((pred1 + 1) * (pred2 + 1) * (podf + 1));
 }
 
@@ -313,9 +277,8 @@ static u32 get_uart_clk(void)
 {
 	unsigned int freq, reg, pred, podf;
 
-	reg = __raw_readl(&mxc_ccm->cscmr1);
-	switch ((reg & MXC_CCM_CSCMR1_UART_CLK_SEL_MASK) >>
-		MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET) {
+	reg = readl(&mxc_ccm->cscmr1);
+	switch (MXC_CCM_CSCMR1_UART_CLK_SEL_RD(reg)) {
 	case 0x0:
 		freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
 		break;
@@ -329,13 +292,9 @@ static u32 get_uart_clk(void)
 		return 66500000;
 	}
 
-	reg = __raw_readl(&mxc_ccm->cscdr1);
-
-	pred = (reg & MXC_CCM_CSCDR1_UART_CLK_PRED_MASK) >>
-		MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET;
-
-	podf = (reg & MXC_CCM_CSCDR1_UART_CLK_PODF_MASK) >>
-		MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET;
+	reg = readl(&mxc_ccm->cscdr1);
+	pred = MXC_CCM_CSCDR1_UART_CLK_PRED_RD(reg);
+	podf = MXC_CCM_CSCDR1_UART_CLK_PODF_RD(reg);
 	freq /= (pred + 1) * (podf + 1);
 
 	return freq;
@@ -347,7 +306,7 @@ static u32 get_uart_clk(void)
 static u32 get_lp_apm(void)
 {
 	u32 ret_val = 0;
-	u32 ccsr = __raw_readl(&mxc_ccm->ccsr);
+	u32 ccsr = readl(&mxc_ccm->ccsr);
 
 	if (((ccsr >> 9) & 1) == 0)
 		ret_val = MXC_HCLK;
@@ -363,15 +322,12 @@ static u32 get_lp_apm(void)
 static u32 imx_get_cspiclk(void)
 {
 	u32 ret_val = 0, pdf, pre_pdf, clk_sel;
-	u32 cscmr1 = __raw_readl(&mxc_ccm->cscmr1);
-	u32 cscdr2 = __raw_readl(&mxc_ccm->cscdr2);
+	u32 cscmr1 = readl(&mxc_ccm->cscmr1);
+	u32 cscdr2 = readl(&mxc_ccm->cscdr2);
 
-	pre_pdf = (cscdr2 & MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK) \
-			>> MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET;
-	pdf = (cscdr2 & MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK) \
-			>> MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET;
-	clk_sel = (cscmr1 & MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK) \
-			>> MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET;
+	pre_pdf = MXC_CCM_CSCDR2_CSPI_CLK_PRED_RD(cscdr2);
+	pdf = MXC_CCM_CSCDR2_CSPI_CLK_PODF_RD(cscdr2);
+	clk_sel = MXC_CCM_CSCMR1_CSPI_CLK_SEL_RD(cscmr1);
 
 	switch (clk_sel) {
 	case 0:
@@ -396,28 +352,25 @@ static u32 imx_get_cspiclk(void)
 
 static u32 get_axi_a_clk(void)
 {
-	u32 cbcdr =  __raw_readl(&mxc_ccm->cbcdr);
-	u32 pdf = (cbcdr & MXC_CCM_CBCDR_AXI_A_PODF_MASK) \
-			>> MXC_CCM_CBCDR_AXI_A_PODF_OFFSET;
+	u32 cbcdr = readl(&mxc_ccm->cbcdr);
+	u32 pdf = MXC_CCM_CBCDR_AXI_A_PODF_RD(cbcdr);
 
 	return  get_periph_clk() / (pdf + 1);
 }
 
 static u32 get_axi_b_clk(void)
 {
-	u32 cbcdr =  __raw_readl(&mxc_ccm->cbcdr);
-	u32 pdf = (cbcdr & MXC_CCM_CBCDR_AXI_B_PODF_MASK) \
-			>> MXC_CCM_CBCDR_AXI_B_PODF_OFFSET;
+	u32 cbcdr = readl(&mxc_ccm->cbcdr);
+	u32 pdf = MXC_CCM_CBCDR_AXI_B_PODF_RD(cbcdr);
 
 	return  get_periph_clk() / (pdf + 1);
 }
 
 static u32 get_emi_slow_clk(void)
 {
-	u32 cbcdr = __raw_readl(&mxc_ccm->cbcdr);
+	u32 cbcdr = readl(&mxc_ccm->cbcdr);
 	u32 emi_clk_sel = cbcdr & MXC_CCM_CBCDR_EMI_CLK_SEL;
-	u32 pdf = (cbcdr & MXC_CCM_CBCDR_EMI_PODF_MASK) \
-			>> MXC_CCM_CBCDR_EMI_PODF_OFFSET;
+	u32 pdf = MXC_CCM_CBCDR_EMI_PODF_RD(cbcdr);
 
 	if (emi_clk_sel)
 		return  get_ahb_clk() / (pdf + 1);
@@ -428,14 +381,12 @@ static u32 get_emi_slow_clk(void)
 static u32 get_ddr_clk(void)
 {
 	u32 ret_val = 0;
-	u32 cbcmr = __raw_readl(&mxc_ccm->cbcmr);
-	u32 ddr_clk_sel = (cbcmr & MXC_CCM_CBCMR_DDR_CLK_SEL_MASK) \
-				>> MXC_CCM_CBCMR_DDR_CLK_SEL_OFFSET;
+	u32 cbcmr = readl(&mxc_ccm->cbcmr);
+	u32 ddr_clk_sel = MXC_CCM_CBCMR_DDR_CLK_SEL_RD(cbcmr);
 #ifdef CONFIG_MX51
-	u32 cbcdr = __raw_readl(&mxc_ccm->cbcdr);
+	u32 cbcdr = readl(&mxc_ccm->cbcdr);
 	if (cbcdr & MXC_CCM_CBCDR_DDR_HIFREQ_SEL) {
-		u32 ddr_clk_podf = (cbcdr & MXC_CCM_CBCDR_DDR_PODF_MASK) >> \
-					MXC_CCM_CBCDR_DDR_PODF_OFFSET;
+		u32 ddr_clk_podf = MXC_CCM_CBCDR_DDR_PODF_RD(cbcdr);
 
 		ret_val = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
 		ret_val /= ddr_clk_podf + 1;
@@ -603,62 +554,62 @@ static int calc_pll_params(u32 ref, u32 target, struct pll_param *pll)
 
 #define CHANGE_PLL_SETTINGS(pll, pd, fi, fn, fd) \
 	{	\
-		__raw_writel(0x1232, &pll->ctrl);		\
-		__raw_writel(0x2, &pll->config);		\
-		__raw_writel((((pd) - 1) << 0) | ((fi) << 4),	\
-			&pll->op);				\
-		__raw_writel(fn, &(pll->mfn));			\
-		__raw_writel((fd) - 1, &pll->mfd);		\
-		__raw_writel((((pd) - 1) << 0) | ((fi) << 4),	\
-			&pll->hfs_op);				\
-		__raw_writel(fn, &pll->hfs_mfn);		\
-		__raw_writel((fd) - 1, &pll->hfs_mfd);		\
-		__raw_writel(0x1232, &pll->ctrl);		\
-		while (!__raw_readl(&pll->ctrl) & 0x1)		\
+		writel(0x1232, &pll->ctrl);		\
+		writel(0x2, &pll->config);		\
+		writel((((pd) - 1) << 0) | ((fi) << 4),	\
+			&pll->op);			\
+		writel(fn, &(pll->mfn));		\
+		writel((fd) - 1, &pll->mfd);		\
+		writel((((pd) - 1) << 0) | ((fi) << 4),	\
+			&pll->hfs_op);			\
+		writel(fn, &pll->hfs_mfn);		\
+		writel((fd) - 1, &pll->hfs_mfd);	\
+		writel(0x1232, &pll->ctrl);		\
+		while (!readl(&pll->ctrl) & 0x1)	\
 			;\
 	}
 
 static int config_pll_clk(enum pll_clocks index, struct pll_param *pll_param)
 {
-	u32 ccsr = __raw_readl(&mxc_ccm->ccsr);
+	u32 ccsr = readl(&mxc_ccm->ccsr);
 	struct mxc_pll_reg *pll = mxc_plls[index];
 
 	switch (index) {
 	case PLL1_CLOCK:
 		/* Switch ARM to PLL2 clock */
-		__raw_writel(ccsr | 0x4, &mxc_ccm->ccsr);
+		writel(ccsr | 0x4, &mxc_ccm->ccsr);
 		CHANGE_PLL_SETTINGS(pll, pll_param->pd,
 					pll_param->mfi, pll_param->mfn,
 					pll_param->mfd);
 		/* Switch back */
-		__raw_writel(ccsr & ~0x4, &mxc_ccm->ccsr);
+		writel(ccsr & ~0x4, &mxc_ccm->ccsr);
 		break;
 	case PLL2_CLOCK:
 		/* Switch to pll2 bypass clock */
-		__raw_writel(ccsr | 0x2, &mxc_ccm->ccsr);
+		writel(ccsr | 0x2, &mxc_ccm->ccsr);
 		CHANGE_PLL_SETTINGS(pll, pll_param->pd,
 					pll_param->mfi, pll_param->mfn,
 					pll_param->mfd);
 		/* Switch back */
-		__raw_writel(ccsr & ~0x2, &mxc_ccm->ccsr);
+		writel(ccsr & ~0x2, &mxc_ccm->ccsr);
 		break;
 	case PLL3_CLOCK:
 		/* Switch to pll3 bypass clock */
-		__raw_writel(ccsr | 0x1, &mxc_ccm->ccsr);
+		writel(ccsr | 0x1, &mxc_ccm->ccsr);
 		CHANGE_PLL_SETTINGS(pll, pll_param->pd,
 					pll_param->mfi, pll_param->mfn,
 					pll_param->mfd);
 		/* Switch back */
-		__raw_writel(ccsr & ~0x1, &mxc_ccm->ccsr);
+		writel(ccsr & ~0x1, &mxc_ccm->ccsr);
 		break;
 	case PLL4_CLOCK:
 		/* Switch to pll4 bypass clock */
-		__raw_writel(ccsr | 0x20, &mxc_ccm->ccsr);
+		writel(ccsr | 0x20, &mxc_ccm->ccsr);
 		CHANGE_PLL_SETTINGS(pll, pll_param->pd,
 					pll_param->mfi, pll_param->mfn,
 					pll_param->mfd);
 		/* Switch back */
-		__raw_writel(ccsr & ~0x20, &mxc_ccm->ccsr);
+		writel(ccsr & ~0x20, &mxc_ccm->ccsr);
 		break;
 	default:
 		return -EINVAL;
@@ -687,7 +638,6 @@ static int config_core_clk(u32 ref, u32 freq)
 
 static int config_nfc_clk(u32 nfc_clk)
 {
-	u32 reg;
 	u32 parent_rate = get_emi_slow_clk();
 	u32 div = parent_rate / nfc_clk;
 
@@ -697,11 +647,10 @@ static int config_nfc_clk(u32 nfc_clk)
 		div++;
 	if (parent_rate / div > NFC_CLK_MAX)
 		div++;
-	reg = __raw_readl(&mxc_ccm->cbcdr);
-	reg &= ~MXC_CCM_CBCDR_NFC_PODF_MASK;
-	reg |= (div - 1) << MXC_CCM_CBCDR_NFC_PODF_OFFSET;
-	__raw_writel(reg, &mxc_ccm->cbcdr);
-	while (__raw_readl(&mxc_ccm->cdhipr) != 0)
+	clrsetbits_le32(&mxc_ccm->cbcdr,
+			MXC_CCM_CBCDR_NFC_PODF_MASK,
+			MXC_CCM_CBCDR_NFC_PODF(div - 1));
+	while (readl(&mxc_ccm->cdhipr) != 0)
 		;
 	return 0;
 }
@@ -714,16 +663,15 @@ static int config_periph_clk(u32 ref, u32 freq)
 
 	memset(&pll_param, 0, sizeof(struct pll_param));
 
-	if (__raw_readl(&mxc_ccm->cbcdr) & MXC_CCM_CBCDR_PERIPH_CLK_SEL) {
+	if (readl(&mxc_ccm->cbcdr) & MXC_CCM_CBCDR_PERIPH_CLK_SEL) {
 		ret = calc_pll_params(ref, freq, &pll_param);
 		if (ret != 0) {
 			printf("Error:Can't find pll parameters: %d\n",
 				ret);
 			return ret;
 		}
-		switch ((__raw_readl(&mxc_ccm->cbcmr) & \
-			MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK) >> \
-			MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET) {
+		switch (MXC_CCM_CBCMR_PERIPH_CLK_SEL_RD(
+				readl(&mxc_ccm->cbcmr))) {
 		case 0:
 			return config_pll_clk(PLL1_CLOCK, &pll_param);
 			break;
@@ -742,8 +690,7 @@ static int config_ddr_clk(u32 emi_clk)
 {
 	u32 clk_src;
 	s32 shift = 0, clk_sel, div = 1;
-	u32 cbcmr = __raw_readl(&mxc_ccm->cbcmr);
-	u32 cbcdr = __raw_readl(&mxc_ccm->cbcdr);
+	u32 cbcmr = readl(&mxc_ccm->cbcmr);
 
 	if (emi_clk > MAX_DDR_CLK) {
 		printf("Warning:DDR clock should not exceed %d MHz\n",
@@ -753,7 +700,7 @@ static int config_ddr_clk(u32 emi_clk)
 
 	clk_src = get_periph_clk();
 	/* Find DDR clock input */
-	clk_sel = (cbcmr >> 10) & 0x3;
+	clk_sel = MXC_CCM_CBCMR_DDR_CLK_SEL_RD(cbcmr);
 	switch (clk_sel) {
 	case 0:
 		shift = 16;
@@ -778,12 +725,10 @@ static int config_ddr_clk(u32 emi_clk)
 	if (div > 8)
 		div = 8;
 
-	cbcdr = cbcdr & ~(0x7 << shift);
-	cbcdr |= ((div - 1) << shift);
-	__raw_writel(cbcdr, &mxc_ccm->cbcdr);
-	while (__raw_readl(&mxc_ccm->cdhipr) != 0)
+	clrsetbits_le32(&mxc_ccm->cbcdr, 0x7 << shift, (div - 1) << shift);
+	while (readl(&mxc_ccm->cdhipr) != 0)
 		;
-	__raw_writel(0x0, &mxc_ccm->ccdr);
+	writel(0x0, &mxc_ccm->ccdr);
 
 	return 0;
 }
@@ -856,7 +801,7 @@ void mxc_set_sata_internal_clock(void)
 
 	set_usb_phy1_clk();
 
-	writel((readl(tmp_base) & (~0x6)) | 0x4, tmp_base);
+	clrsetbits_le32(tmp_base, 0x6, 0x4);
 }
 #endif
 
diff --git u-boot-imx-e1eb75b.orig/arch/arm/include/asm/arch-mx5/crm_regs.h u-boot-imx-e1eb75b/arch/arm/include/asm/arch-mx5/crm_regs.h
index 4e0fc1b..ab0e818 100644
--- u-boot-imx-e1eb75b.orig/arch/arm/include/asm/arch-mx5/crm_regs.h
+++ u-boot-imx-e1eb75b/arch/arm/include/asm/arch-mx5/crm_regs.h
@@ -85,115 +85,200 @@ struct mxc_ccm_reg {
 /* Define the bits in register CACRR */
 #define MXC_CCM_CACRR_ARM_PODF_OFFSET		0
 #define MXC_CCM_CACRR_ARM_PODF_MASK		0x7
+#define MXC_CCM_CACRR_ARM_PODF(v)		((v) & 0x7)
+#define MXC_CCM_CACRR_ARM_PODF_RD(r)		((r) & 0x7)
 
 /* Define the bits in register CBCDR */
 #define MXC_CCM_CBCDR_DDR_HIFREQ_SEL		(0x1 << 30)
-#define MXC_CCM_CBCDR_DDR_PODF_MASK		(0x7 << 27)
 #define MXC_CCM_CBCDR_DDR_PODF_OFFSET		27
+#define MXC_CCM_CBCDR_DDR_PODF_MASK		(0x7 << 27)
+#define MXC_CCM_CBCDR_DDR_PODF(v)		(((v) & 0x7) << 27)
+#define MXC_CCM_CBCDR_DDR_PODF_RD(r)		(((r) >> 27) & 0x7)
 #define MXC_CCM_CBCDR_EMI_CLK_SEL		(0x1 << 26)
 #define MXC_CCM_CBCDR_PERIPH_CLK_SEL		(0x1 << 25)
 #define MXC_CCM_CBCDR_EMI_PODF_OFFSET		22
 #define MXC_CCM_CBCDR_EMI_PODF_MASK		(0x7 << 22)
+#define MXC_CCM_CBCDR_EMI_PODF(v)		(((v) & 0x7) << 22)
+#define MXC_CCM_CBCDR_EMI_PODF_RD(r)		(((r) >> 22) & 0x7)
 #define MXC_CCM_CBCDR_AXI_B_PODF_OFFSET		19
 #define MXC_CCM_CBCDR_AXI_B_PODF_MASK		(0x7 << 19)
+#define MXC_CCM_CBCDR_AXI_B_PODF(v)		(((v) & 0x7) << 19)
+#define MXC_CCM_CBCDR_AXI_B_PODF_RD(r)		(((r) >> 19) & 0x7)
 #define MXC_CCM_CBCDR_AXI_A_PODF_OFFSET		16
 #define MXC_CCM_CBCDR_AXI_A_PODF_MASK		(0x7 << 16)
+#define MXC_CCM_CBCDR_AXI_A_PODF(v)		(((v) & 0x7) << 16)
+#define MXC_CCM_CBCDR_AXI_A_PODF_RD(r)		(((r) >> 16) & 0x7)
 #define MXC_CCM_CBCDR_NFC_PODF_OFFSET		13
 #define MXC_CCM_CBCDR_NFC_PODF_MASK		(0x7 << 13)
+#define MXC_CCM_CBCDR_NFC_PODF(v)		(((v) & 0x7) << 13)
+#define MXC_CCM_CBCDR_NFC_PODF_RD(r)		(((r) >> 13) & 0x7)
 #define MXC_CCM_CBCDR_AHB_PODF_OFFSET		10
 #define MXC_CCM_CBCDR_AHB_PODF_MASK		(0x7 << 10)
+#define MXC_CCM_CBCDR_AHB_PODF(v)		(((v) & 0x7) << 10)
+#define MXC_CCM_CBCDR_AHB_PODF_RD(r)		(((r) >> 10) & 0x7)
 #define MXC_CCM_CBCDR_IPG_PODF_OFFSET		8
 #define MXC_CCM_CBCDR_IPG_PODF_MASK		(0x3 << 8)
+#define MXC_CCM_CBCDR_IPG_PODF(v)		(((v) & 0x3) << 8)
+#define MXC_CCM_CBCDR_IPG_PODF_RD(r)		(((r) >> 8) & 0x3)
 #define MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET	6
 #define MXC_CCM_CBCDR_PERCLK_PRED1_MASK		(0x3 << 6)
+#define MXC_CCM_CBCDR_PERCLK_PRED1(v)		(((v) & 0x3) << 6)
+#define MXC_CCM_CBCDR_PERCLK_PRED1_RD(r)	(((r) >> 6) & 0x3)
 #define MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET	3
 #define MXC_CCM_CBCDR_PERCLK_PRED2_MASK		(0x7 << 3)
+#define MXC_CCM_CBCDR_PERCLK_PRED2(v)		(((v) & 0x7) << 3)
+#define MXC_CCM_CBCDR_PERCLK_PRED2_RD(r)	(((r) >> 3) & 0x7)
 #define MXC_CCM_CBCDR_PERCLK_PODF_OFFSET	0
 #define MXC_CCM_CBCDR_PERCLK_PODF_MASK		0x7
+#define MXC_CCM_CBCDR_PERCLK_PODF(v)		((v) & 0x7)
+#define MXC_CCM_CBCDR_PERCLK_PODF_RD(r)		((r) & 0x7)
 
 /* Define the bits in register CSCMR1 */
 #define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_OFFSET		30
 #define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_MASK		(0x3 << 30)
+#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL(v)		(((v) & 0x3) << 30)
+#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_RD(r)		(((r) >> 30) & 0x3)
 #define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_OFFSET		28
 #define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_MASK		(0x3 << 28)
-#define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL_OFFSET		26
+#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL(v)		(((v) & 0x3) << 28)
+#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_RD(r)		(((r) >> 28) & 0x3)
 #define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL			(0x1 << 26)
 #define MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET		24
 #define MXC_CCM_CSCMR1_UART_CLK_SEL_MASK		(0x3 << 24)
+#define MXC_CCM_CSCMR1_UART_CLK_SEL(v)			(((v) & 0x3) << 24)
+#define MXC_CCM_CSCMR1_UART_CLK_SEL_RD(r)		(((r) >> 24) & 0x3)
 #define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_OFFSET		22
 #define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK		(0x3 << 22)
+#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL(v)		(((v) & 0x3) << 22)
+#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_RD(r)		(((r) >> 22) & 0x3)
 #define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_OFFSET	20
 #define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_MASK	(0x3 << 20)
+#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL(v)		(((v) & 0x3) << 20)
+#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_RD(r)	(((r) >> 20) & 0x3)
 #define MXC_CCM_CSCMR1_ESDHC3_CLK_SEL			(0x1 << 19)
 #define MXC_CCM_CSCMR1_ESDHC4_CLK_SEL			(0x1 << 18)
 #define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_OFFSET	16
 #define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_MASK	(0x3 << 16)
+#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL(v)		(((v) & 0x3) << 16)
+#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_RD(r)	(((r) >> 16) & 0x3)
 #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET		14
 #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK		(0x3 << 14)
+#define MXC_CCM_CSCMR1_SSI1_CLK_SEL(v)			(((v) & 0x3) << 14)
+#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_RD(r)		(((r) >> 14) & 0x3)
 #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET		12
 #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK		(0x3 << 12)
+#define MXC_CCM_CSCMR1_SSI2_CLK_SEL(v)			(((v) & 0x3) << 12)
+#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_RD(r)		(((r) >> 12) & 0x3)
 #define MXC_CCM_CSCMR1_SSI3_CLK_SEL			(0x1 << 11)
 #define MXC_CCM_CSCMR1_VPU_RCLK_SEL			(0x1 << 10)
 #define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_OFFSET		8
 #define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_MASK		(0x3 << 8)
+#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL(v)		(((v) & 0x3) << 8)
+#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_RD(r)		(((r) >> 8) & 0x3)
 #define MXC_CCM_CSCMR1_TVE_CLK_SEL			(0x1 << 7)
 #define MXC_CCM_CSCMR1_TVE_EXT_CLK_SEL			(0x1 << 6)
 #define MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET		4
 #define MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK		(0x3 << 4)
+#define MXC_CCM_CSCMR1_CSPI_CLK_SEL(v)			(((v) & 0x3) << 4)
+#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_RD(r)		(((r) >> 4) & 0x3)
 #define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_OFFSET		2
 #define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_MASK		(0x3 << 2)
+#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL(v)			(((v) & 0x3) << 2)
+#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_RD(r)		(((r) >> 2) & 0x3)
 #define MXC_CCM_CSCMR1_SSI_EXT2_COM_CLK_SEL		(0x1 << 1)
 #define MXC_CCM_CSCMR1_SSI_EXT1_COM_CLK_SEL		0x1
 
 /* Define the bits in register CSCDR2 */
 #define MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET		25
 #define MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK		(0x7 << 25)
+#define MXC_CCM_CSCDR2_CSPI_CLK_PRED(v)			(((v) & 0x7) << 25)
+#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_RD(r)		(((r) >> 25) & 0x7)
 #define MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET		19
 #define MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK		(0x3F << 19)
+#define MXC_CCM_CSCDR2_CSPI_CLK_PODF(v)			(((v) & 0x3F) << 19)
+#define MXC_CCM_CSCDR2_CSPI_CLK_PODF_RD(r)		(((r) >> 19) & 0x3F)
 #define MXC_CCM_CSCDR2_SIM_CLK_PRED_OFFSET		16
 #define MXC_CCM_CSCDR2_SIM_CLK_PRED_MASK		(0x7 << 16)
+#define MXC_CCM_CSCDR2_SIM_CLK_PRED(v)			(((v) & 0x7) << 16)
+#define MXC_CCM_CSCDR2_SIM_CLK_PRED_RD(r)		(((r) >> 16) & 0x7)
 #define MXC_CCM_CSCDR2_SIM_CLK_PODF_OFFSET		9
 #define MXC_CCM_CSCDR2_SIM_CLK_PODF_MASK		(0x3F << 9)
+#define MXC_CCM_CSCDR2_SIM_CLK_PODF(v)			(((v) & 0x3F) << 9)
+#define MXC_CCM_CSCDR2_SIM_CLK_PODF_RD(r)		(((r) >> 9) & 0x3F)
 #define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED_OFFSET		6
-#define MXC_CCM_CSCDR2_SLIMBUS_PRED_MASK		(0x7 << 6)
-#define MXC_CCM_CSCDR2_SLIMBUS_PODF_OFFSET		0
-#define MXC_CCM_CSCDR2_SLIMBUS_PODF_MASK		0x3F
+#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED_MASK		(0x7 << 6)
+#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED(v)		(((v) & 0x7) << 6)
+#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED_RD(r)		(((r) >> 6) & 0x7)
+#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PODF_OFFSET		0
+#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PODF_MASK		0x3F
+#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PODF(v)		((v) & 0x3F)
+#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PODF_RD(r)		((r) & 0x3F)
 
 /* Define the bits in register CBCMR */
 #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET		14
 #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK		(0x3 << 14)
+#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL(v)		(((v) & 0x3) << 14)
+#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_RD(r)		(((r) >> 14) & 0x3)
 #define MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET		12
 #define MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK		(0x3 << 12)
+#define MXC_CCM_CBCMR_PERIPH_CLK_SEL(v)			(((v) & 0x3) << 12)
+#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_RD(r)		(((r) >> 12) & 0x3)
 #define MXC_CCM_CBCMR_DDR_CLK_SEL_OFFSET		10
 #define MXC_CCM_CBCMR_DDR_CLK_SEL_MASK			(0x3 << 10)
+#define MXC_CCM_CBCMR_DDR_CLK_SEL(v)			(((v) & 0x3) << 10)
+#define MXC_CCM_CBCMR_DDR_CLK_SEL_RD(r)			(((r) >> 10) & 0x3)
 #define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_OFFSET		8
 #define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_MASK		(0x3 << 8)
+#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL(v)		(((v) & 0x3) << 8)
+#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_RD(r)		(((r) >> 8) & 0x3)
 #define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_OFFSET		6
 #define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_MASK		(0x3 << 6)
+#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL(v)		(((v) & 0x3) << 6)
+#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_RD(r)		(((r) >> 6) & 0x3)
 #define MXC_CCM_CBCMR_GPU_CLK_SEL_OFFSET		4
 #define MXC_CCM_CBCMR_GPU_CLK_SEL_MASK			(0x3 << 4)
+#define MXC_CCM_CBCMR_GPU_CLK_SEL(v)			(((v) & 0x3) << 4)
+#define MXC_CCM_CBCMR_GPU_CLK_SEL_RD(r)			(((r) >> 4) & 0x3)
 #define MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL		(0x1 << 1)
 #define MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL		(0x1 << 0)
 
 /* Define the bits in register CSCDR1 */
 #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_OFFSET	22
 #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_MASK	(0x7 << 22)
+#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED(v)		(((v) & 0x7) << 22)
+#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_RD(r)	(((r) >> 22) & 0x7)
 #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_OFFSET	19
 #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_MASK	(0x7 << 19)
+#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF(v)		(((v) & 0x7) << 19)
+#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_RD(r)	(((r) >> 19) & 0x7)
 #define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_OFFSET	16
 #define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_MASK	(0x7 << 16)
+#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED(v)		(((v) & 0x7) << 16)
+#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_RD(r)	(((r) >> 16) & 0x7)
 #define MXC_CCM_CSCDR1_PGC_CLK_PODF_OFFSET		14
 #define MXC_CCM_CSCDR1_PGC_CLK_PODF_MASK		(0x3 << 14)
+#define MXC_CCM_CSCDR1_PGC_CLK_PODF(v)			(((v) & 0x3) << 14)
+#define MXC_CCM_CSCDR1_PGC_CLK_PODF_RD(r)		(((r) >> 14) & 0x3)
 #define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_OFFSET	11
 #define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_MASK	(0x7 << 11)
+#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF(v)		(((v) & 0x7) << 11)
+#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_RD(r)	(((r) >> 11) & 0x7)
 #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET		8
 #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK		(0x7 << 8)
+#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED(v)		(((v) & 0x7) << 8)
+#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_RD(r)		(((r) >> 8) & 0x7)
 #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET		6
 #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK		(0x3 << 6)
+#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF(v)		(((v) & 0x3) << 6)
+#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_RD(r)		(((r) >> 6) & 0x3)
 #define MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET		3
 #define MXC_CCM_CSCDR1_UART_CLK_PRED_MASK		(0x7 << 3)
+#define MXC_CCM_CSCDR1_UART_CLK_PRED(v)			(((v) & 0x7) << 3)
+#define MXC_CCM_CSCDR1_UART_CLK_PRED_RD(r)		(((r) >> 3) & 0x7)
 #define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET		0
 #define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK		0x7
+#define MXC_CCM_CSCDR1_UART_CLK_PODF(v)			((v) & 0x7)
+#define MXC_CCM_CSCDR1_UART_CLK_PODF_RD(r)		((r) & 0x7)
 
 /* Define the bits in register CCDR */
 #define MXC_CCM_CCDR_IPU_HS_MASK			(0x1 << 17)
@@ -213,8 +298,10 @@ struct mxc_ccm_reg {
 #define	MXC_DPLLC_CTL_DPDCK0_2_EN			(1 << 12)
 
 #define	MXC_DPLLC_OP_PDF_MASK				0xf
-#define	MXC_DPLLC_OP_MFI_MASK				(0xf << 4)
 #define	MXC_DPLLC_OP_MFI_OFFSET				4
+#define	MXC_DPLLC_OP_MFI_MASK				(0xf << 4)
+#define	MXC_DPLLC_OP_MFI(v)				(((v) & 0xf) << 4)
+#define	MXC_DPLLC_OP_MFI_RD(r)				(((r) >> 4) & 0xf)
 
 #define	MXC_DPLLC_MFD_MFD_MASK				0x7ffffff