From: Stefano Babic <sbabic@denx.de>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH v2 01/14] mx5/6: Define default SoC input clock frequencies
Date: Fri, 28 Sep 2012 10:42:31 +0200 [thread overview]
Message-ID: <506562F7.4030809@denx.de> (raw)
In-Reply-To: <1065839952.5372238.1348777198067.JavaMail.root@advansee.com>
On 27/09/2012 22:19, Beno?t Th?baudeau wrote:
> Define default SoC input clock frequencies for i.MX5/6 in order to get rid of
> duplicated definitions.
>
> Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
> Cc: Stefano Babic <sbabic@denx.de>
> Cc: Jason Liu <r64343@freescale.com>
> Cc: Matt Sealey <matt@genesi-usa.com>
> Cc: Fabio Estevam <fabio.estevam@freescale.com>
> ---
> The CONFIG_SYS_MX{5|6}_HCLK and CONFIG_SYS_MX{5|6}_CLK32 definitions set
> to 24000000 and 32768 should also be removed from any new board config file
> added in the meantime if this is applied to the next branch instead of the
> master branch. I am thinking especially about include/configs/mx6qsabresd.h .
That is correct. Fabio, waht do you mind if I drop directly the two
defines from your "configs: mx6: Add a common config file" ?
>
> This patch supersedes http://patchwork.ozlabs.org/patch/177303/ .
> Changes for v2:
> - Remove duplicated definition usages instead of spreading them.
We have mainly already discussed about this patch. This alignes the code
for MX5 to the other iMX SOCs.
> .../arch/arm/cpu/armv7/mx5/clock.c | 45 +++++++++-----------
> .../arch/arm/cpu/armv7/mx6/clock.c | 20 ++++-----
> .../arch/arm/imx-common/timer.c | 12 +++---
> .../arch/arm/include/asm/arch-mx5/clock.h | 14 ++++++
> .../arch/arm/include/asm/arch-mx6/clock.h | 14 ++++++
> .../board/freescale/mx53loco/mx53loco.c | 2 +-
> .../include/configs/ima3-mx53.h | 3 --
> .../include/configs/mx51_efikamx.h | 2 -
> .../include/configs/mx51evk.h | 2 -
> .../include/configs/mx53ard.h | 2 -
> .../include/configs/mx53evk.h | 2 -
> .../include/configs/mx53loco.h | 2 -
> .../include/configs/mx53smd.h | 2 -
> .../include/configs/mx6qarm2.h | 2 -
> .../include/configs/mx6qsabrelite.h | 2 -
> .../include/configs/vision2.h | 2 -
> 16 files changed, 64 insertions(+), 64 deletions(-)
>
> diff --git u-boot-imx-e1eb75b.orig/arch/arm/cpu/armv7/mx5/clock.c u-boot-imx-e1eb75b/arch/arm/cpu/armv7/mx5/clock.c
> index c67c3cf..1f95536 100644
> --- u-boot-imx-e1eb75b.orig/arch/arm/cpu/armv7/mx5/clock.c
> +++ u-boot-imx-e1eb75b/arch/arm/cpu/armv7/mx5/clock.c
> @@ -69,7 +69,7 @@ struct fixed_pll_mfd {
> };
>
> const struct fixed_pll_mfd fixed_mfd[] = {
> - {CONFIG_SYS_MX5_HCLK, 24 * 16},
> + {MXC_HCLK, 24 * 16},
> };
>
> struct pll_param {
> @@ -242,7 +242,7 @@ u32 get_mcu_main_clk(void)
>
> reg = (__raw_readl(&mxc_ccm->cacrr) & MXC_CCM_CACRR_ARM_PODF_MASK) >>
> MXC_CCM_CACRR_ARM_PODF_OFFSET;
> - freq = decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_SYS_MX5_HCLK);
> + freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
> return freq / (reg + 1);
> }
>
> @@ -255,14 +255,14 @@ u32 get_periph_clk(void)
>
> reg = __raw_readl(&mxc_ccm->cbcdr);
> if (!(reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL))
> - return decode_pll(mxc_plls[PLL2_CLOCK], CONFIG_SYS_MX5_HCLK);
> + return decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK);
> reg = __raw_readl(&mxc_ccm->cbcmr);
> switch ((reg & MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK) >>
> MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET) {
> case 0:
> - return decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_SYS_MX5_HCLK);
> + return decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
> case 1:
> - return decode_pll(mxc_plls[PLL3_CLOCK], CONFIG_SYS_MX5_HCLK);
> + return decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK);
> default:
> return 0;
> }
> @@ -317,16 +317,13 @@ static u32 get_uart_clk(void)
> switch ((reg & MXC_CCM_CSCMR1_UART_CLK_SEL_MASK) >>
> MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET) {
> case 0x0:
> - freq = decode_pll(mxc_plls[PLL1_CLOCK],
> - CONFIG_SYS_MX5_HCLK);
> + freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
> break;
> case 0x1:
> - freq = decode_pll(mxc_plls[PLL2_CLOCK],
> - CONFIG_SYS_MX5_HCLK);
> + freq = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK);
> break;
> case 0x2:
> - freq = decode_pll(mxc_plls[PLL3_CLOCK],
> - CONFIG_SYS_MX5_HCLK);
> + freq = decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK);
> break;
> default:
> return 66500000;
> @@ -353,9 +350,9 @@ static u32 get_lp_apm(void)
> u32 ccsr = __raw_readl(&mxc_ccm->ccsr);
>
> if (((ccsr >> 9) & 1) == 0)
> - ret_val = CONFIG_SYS_MX5_HCLK;
> + ret_val = MXC_HCLK;
> else
> - ret_val = ((32768 * 1024));
> + ret_val = MXC_CLK32 * 1024;
>
> return ret_val;
> }
> @@ -378,18 +375,15 @@ static u32 imx_get_cspiclk(void)
>
> switch (clk_sel) {
> case 0:
> - ret_val = decode_pll(mxc_plls[PLL1_CLOCK],
> - CONFIG_SYS_MX5_HCLK) /
> + ret_val = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK) /
> ((pre_pdf + 1) * (pdf + 1));
> break;
> case 1:
> - ret_val = decode_pll(mxc_plls[PLL2_CLOCK],
> - CONFIG_SYS_MX5_HCLK) /
> + ret_val = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK) /
> ((pre_pdf + 1) * (pdf + 1));
> break;
> case 2:
> - ret_val = decode_pll(mxc_plls[PLL3_CLOCK],
> - CONFIG_SYS_MX5_HCLK) /
> + ret_val = decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK) /
> ((pre_pdf + 1) * (pdf + 1));
> break;
> default:
> @@ -443,7 +437,7 @@ static u32 get_ddr_clk(void)
> u32 ddr_clk_podf = (cbcdr & MXC_CCM_CBCDR_DDR_PODF_MASK) >> \
> MXC_CCM_CBCDR_DDR_PODF_OFFSET;
>
> - ret_val = decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_SYS_MX5_HCLK);
> + ret_val = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
> ret_val /= ddr_clk_podf + 1;
>
> return ret_val;
> @@ -488,8 +482,7 @@ unsigned int mxc_get_clock(enum mxc_clock clk)
> case MXC_CSPI_CLK:
> return imx_get_cspiclk();
> case MXC_FEC_CLK:
> - return decode_pll(mxc_plls[PLL1_CLOCK],
> - CONFIG_SYS_MX5_HCLK);
> + return decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
> case MXC_SATA_CLK:
> return get_ahb_clk();
> case MXC_DDR_CLK:
> @@ -874,14 +867,14 @@ int do_mx5_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
> {
> u32 freq;
>
> - freq = decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_SYS_MX5_HCLK);
> + freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
> printf("PLL1 %8d MHz\n", freq / 1000000);
> - freq = decode_pll(mxc_plls[PLL2_CLOCK], CONFIG_SYS_MX5_HCLK);
> + freq = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK);
> printf("PLL2 %8d MHz\n", freq / 1000000);
> - freq = decode_pll(mxc_plls[PLL3_CLOCK], CONFIG_SYS_MX5_HCLK);
> + freq = decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK);
> printf("PLL3 %8d MHz\n", freq / 1000000);
> #ifdef CONFIG_MX53
> - freq = decode_pll(mxc_plls[PLL4_CLOCK], CONFIG_SYS_MX5_HCLK);
> + freq = decode_pll(mxc_plls[PLL4_CLOCK], MXC_HCLK);
> printf("PLL4 %8d MHz\n", freq / 1000000);
> #endif
>
> diff --git u-boot-imx-e1eb75b.orig/arch/arm/cpu/armv7/mx6/clock.c u-boot-imx-e1eb75b/arch/arm/cpu/armv7/mx6/clock.c
> index fddb373..7b31e4f 100644
> --- u-boot-imx-e1eb75b.orig/arch/arm/cpu/armv7/mx6/clock.c
> +++ u-boot-imx-e1eb75b/arch/arm/cpu/armv7/mx6/clock.c
> @@ -108,7 +108,7 @@ static u32 get_mcu_main_clk(void)
> reg = __raw_readl(&imx_ccm->cacrr);
> reg &= MXC_CCM_CACRR_ARM_PODF_MASK;
> reg >>= MXC_CCM_CACRR_ARM_PODF_OFFSET;
> - freq = decode_pll(PLL_SYS, CONFIG_SYS_MX6_HCLK);
> + freq = decode_pll(PLL_SYS, MXC_HCLK);
>
> return freq / (reg + 1);
> }
> @@ -125,11 +125,11 @@ u32 get_periph_clk(void)
>
> switch (reg) {
> case 0:
> - freq = decode_pll(PLL_USBOTG, CONFIG_SYS_MX6_HCLK);
> + freq = decode_pll(PLL_USBOTG, MXC_HCLK);
> break;
> case 1:
> case 2:
> - freq = CONFIG_SYS_MX6_HCLK;
> + freq = MXC_HCLK;
> break;
> default:
> break;
> @@ -141,7 +141,7 @@ u32 get_periph_clk(void)
>
> switch (reg) {
> case 0:
> - freq = decode_pll(PLL_BUS, CONFIG_SYS_MX6_HCLK);
> + freq = decode_pll(PLL_BUS, MXC_HCLK);
> break;
> case 1:
> freq = PLL2_PFD2_FREQ;
> @@ -237,7 +237,7 @@ static u32 get_emi_slow_clk(void)
> root_freq = get_axi_clk();
> break;
> case 1:
> - root_freq = decode_pll(PLL_USBOTG, CONFIG_SYS_MX6_HCLK);
> + root_freq = decode_pll(PLL_USBOTG, MXC_HCLK);
> break;
> case 2:
> root_freq = PLL2_PFD2_FREQ;
> @@ -309,7 +309,7 @@ u32 imx_get_uartclk(void)
>
> u32 imx_get_fecclk(void)
> {
> - return decode_pll(PLL_ENET, CONFIG_SYS_MX6_HCLK);
> + return decode_pll(PLL_ENET, MXC_HCLK);
> }
>
> int enable_sata_clock(void)
> @@ -389,13 +389,13 @@ unsigned int mxc_get_clock(enum mxc_clock clk)
> int do_mx6_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
> {
> u32 freq;
> - freq = decode_pll(PLL_SYS, CONFIG_SYS_MX6_HCLK);
> + freq = decode_pll(PLL_SYS, MXC_HCLK);
> printf("PLL_SYS %8d MHz\n", freq / 1000000);
> - freq = decode_pll(PLL_BUS, CONFIG_SYS_MX6_HCLK);
> + freq = decode_pll(PLL_BUS, MXC_HCLK);
> printf("PLL_BUS %8d MHz\n", freq / 1000000);
> - freq = decode_pll(PLL_USBOTG, CONFIG_SYS_MX6_HCLK);
> + freq = decode_pll(PLL_USBOTG, MXC_HCLK);
> printf("PLL_OTG %8d MHz\n", freq / 1000000);
> - freq = decode_pll(PLL_ENET, CONFIG_SYS_MX6_HCLK);
> + freq = decode_pll(PLL_ENET, MXC_HCLK);
> printf("PLL_NET %8d MHz\n", freq / 1000000);
>
> printf("\n");
> diff --git u-boot-imx-e1eb75b.orig/arch/arm/imx-common/timer.c u-boot-imx-e1eb75b/arch/arm/imx-common/timer.c
> index e2725e1..b021903 100644
> --- u-boot-imx-e1eb75b.orig/arch/arm/imx-common/timer.c
> +++ u-boot-imx-e1eb75b/arch/arm/imx-common/timer.c
> @@ -27,6 +27,7 @@
> #include <asm/io.h>
> #include <div64.h>
> #include <asm/arch/imx-regs.h>
> +#include <asm/arch/clock.h>
>
> /* General purpose timers registers */
> struct mxc_gpt {
> @@ -44,7 +45,6 @@ static struct mxc_gpt *cur_gpt = (struct mxc_gpt *)GPT1_BASE_ADDR;
> #define GPTCR_FRR (1 << 9) /* Freerun / restart */
> #define GPTCR_CLKSOURCE_32 (4 << 6) /* Clock source */
> #define GPTCR_TEN 1 /* Timer enable */
> -#define CLK_32KHZ 32768 /* 32Khz input */
>
> DECLARE_GLOBAL_DATA_PTR;
>
> @@ -54,14 +54,14 @@ DECLARE_GLOBAL_DATA_PTR;
> static inline unsigned long long tick_to_time(unsigned long long tick)
> {
> tick *= CONFIG_SYS_HZ;
> - do_div(tick, CLK_32KHZ);
> + do_div(tick, MXC_CLK32);
>
> return tick;
> }
>
> static inline unsigned long long us_to_tick(unsigned long long usec)
> {
> - usec = usec * CLK_32KHZ + 999999;
> + usec = usec * MXC_CLK32 + 999999;
> do_div(usec, 1000000);
>
> return usec;
> @@ -86,7 +86,7 @@ int timer_init(void)
> __raw_writel(i | GPTCR_CLKSOURCE_32 | GPTCR_TEN, &cur_gpt->control);
>
> val = __raw_readl(&cur_gpt->counter);
> - lastinc = val / (CLK_32KHZ / CONFIG_SYS_HZ);
> + lastinc = val / (MXC_CLK32 / CONFIG_SYS_HZ);
> timestamp = 0;
>
> return 0;
> @@ -114,7 +114,7 @@ ulong get_timer_masked(void)
> {
> /*
> * get_ticks() returns a long long (64 bit), it wraps in
> - * 2^64 / CONFIG_MX25_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~
> + * 2^64 / MXC_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~
> * 5 * 10^9 days... and get_ticks() * CONFIG_SYS_HZ wraps in
> * 5 * 10^6 days - long enough.
> */
> @@ -145,5 +145,5 @@ void __udelay(unsigned long usec)
> */
> ulong get_tbclk(void)
> {
> - return CLK_32KHZ;
> + return MXC_CLK32;
> }
> diff --git u-boot-imx-e1eb75b.orig/arch/arm/include/asm/arch-mx5/clock.h u-boot-imx-e1eb75b/arch/arm/include/asm/arch-mx5/clock.h
> index 8d8fa18..55e3b51 100644
> --- u-boot-imx-e1eb75b.orig/arch/arm/include/asm/arch-mx5/clock.h
> +++ u-boot-imx-e1eb75b/arch/arm/include/asm/arch-mx5/clock.h
> @@ -24,6 +24,20 @@
> #ifndef __ASM_ARCH_CLOCK_H
> #define __ASM_ARCH_CLOCK_H
>
> +#include <common.h>
> +
> +#ifdef CONFIG_SYS_MX5_HCLK
> +#define MXC_HCLK CONFIG_SYS_MX5_HCLK
> +#else
> +#define MXC_HCLK 24000000
> +#endif
> +
> +#ifdef CONFIG_SYS_MX5_CLK32
> +#define MXC_CLK32 CONFIG_SYS_MX5_CLK32
> +#else
> +#define MXC_CLK32 32768
> +#endif
> +
> enum mxc_clock {
> MXC_ARM_CLK = 0,
> MXC_AHB_CLK,
> diff --git u-boot-imx-e1eb75b.orig/arch/arm/include/asm/arch-mx6/clock.h u-boot-imx-e1eb75b/arch/arm/include/asm/arch-mx6/clock.h
> index c55c18d..44b2359 100644
> --- u-boot-imx-e1eb75b.orig/arch/arm/include/asm/arch-mx6/clock.h
> +++ u-boot-imx-e1eb75b/arch/arm/include/asm/arch-mx6/clock.h
> @@ -24,6 +24,20 @@
> #ifndef __ASM_ARCH_CLOCK_H
> #define __ASM_ARCH_CLOCK_H
>
> +#include <common.h>
> +
> +#ifdef CONFIG_SYS_MX6_HCLK
> +#define MXC_HCLK CONFIG_SYS_MX6_HCLK
> +#else
> +#define MXC_HCLK 24000000
> +#endif
> +
> +#ifdef CONFIG_SYS_MX6_CLK32
> +#define MXC_CLK32 CONFIG_SYS_MX6_CLK32
> +#else
> +#define MXC_CLK32 32768
> +#endif
> +
> enum mxc_clock {
> MXC_ARM_CLK = 0,
> MXC_PER_CLK,
> diff --git u-boot-imx-e1eb75b.orig/board/freescale/mx53loco/mx53loco.c u-boot-imx-e1eb75b/board/freescale/mx53loco/mx53loco.c
> index 8f82125..6543209 100644
> --- u-boot-imx-e1eb75b.orig/board/freescale/mx53loco/mx53loco.c
> +++ u-boot-imx-e1eb75b/board/freescale/mx53loco/mx53loco.c
> @@ -394,7 +394,7 @@ static int power_init(void)
> static void clock_1GHz(void)
> {
> int ret;
> - u32 ref_clk = CONFIG_SYS_MX5_HCLK;
> + u32 ref_clk = MXC_HCLK;
> /*
> * After increasing voltage to 1.25V, we can switch
> * CPU clock to 1GHz and DDR to 400MHz safely
> diff --git u-boot-imx-e1eb75b.orig/include/configs/ima3-mx53.h u-boot-imx-e1eb75b/include/configs/ima3-mx53.h
> index dbc59b9..499fb37 100644
> --- u-boot-imx-e1eb75b.orig/include/configs/ima3-mx53.h
> +++ u-boot-imx-e1eb75b/include/configs/ima3-mx53.h
> @@ -28,9 +28,6 @@
> #include <asm/arch/imx-regs.h>
> #include <asm/arch/mx5x_pins.h>
>
> -#define CONFIG_SYS_MX5_HCLK 24000000
> -#define CONFIG_SYS_MX5_CLK32 32768
> -
> #define CONFIG_DISPLAY_CPUINFO
> #define CONFIG_DISPLAY_BOARDINFO
>
> diff --git u-boot-imx-e1eb75b.orig/include/configs/mx51_efikamx.h u-boot-imx-e1eb75b/include/configs/mx51_efikamx.h
> index 439b5f3..ffe771f 100644
> --- u-boot-imx-e1eb75b.orig/include/configs/mx51_efikamx.h
> +++ u-boot-imx-e1eb75b/include/configs/mx51_efikamx.h
> @@ -37,8 +37,6 @@
>
> #include <asm/arch/imx-regs.h>
>
> -#define CONFIG_SYS_MX5_HCLK 24000000
> -#define CONFIG_SYS_MX5_CLK32 32768
> #define CONFIG_DISPLAY_CPUINFO
> #define CONFIG_DISPLAY_BOARDINFO
>
> diff --git u-boot-imx-e1eb75b.orig/include/configs/mx51evk.h u-boot-imx-e1eb75b/include/configs/mx51evk.h
> index 7b027b4..34b0783 100644
> --- u-boot-imx-e1eb75b.orig/include/configs/mx51evk.h
> +++ u-boot-imx-e1eb75b/include/configs/mx51evk.h
> @@ -28,8 +28,6 @@
>
> #define CONFIG_MX51 /* in a mx51 */
>
> -#define CONFIG_SYS_MX5_HCLK 24000000
> -#define CONFIG_SYS_MX5_CLK32 32768
> #define CONFIG_DISPLAY_CPUINFO
> #define CONFIG_DISPLAY_BOARDINFO
>
> diff --git u-boot-imx-e1eb75b.orig/include/configs/mx53ard.h u-boot-imx-e1eb75b/include/configs/mx53ard.h
> index 6ab4cde..fea93b4 100644
> --- u-boot-imx-e1eb75b.orig/include/configs/mx53ard.h
> +++ u-boot-imx-e1eb75b/include/configs/mx53ard.h
> @@ -24,8 +24,6 @@
>
> #define CONFIG_MX53
>
> -#define CONFIG_SYS_MX5_HCLK 24000000
> -#define CONFIG_SYS_MX5_CLK32 32768
> #define CONFIG_DISPLAY_CPUINFO
> #define CONFIG_DISPLAY_BOARDINFO
>
> diff --git u-boot-imx-e1eb75b.orig/include/configs/mx53evk.h u-boot-imx-e1eb75b/include/configs/mx53evk.h
> index b46855f..832050e 100644
> --- u-boot-imx-e1eb75b.orig/include/configs/mx53evk.h
> +++ u-boot-imx-e1eb75b/include/configs/mx53evk.h
> @@ -24,8 +24,6 @@
>
> #define CONFIG_MX53
>
> -#define CONFIG_SYS_MX5_HCLK 24000000
> -#define CONFIG_SYS_MX5_CLK32 32768
> #define CONFIG_DISPLAY_CPUINFO
> #define CONFIG_DISPLAY_BOARDINFO
>
> diff --git u-boot-imx-e1eb75b.orig/include/configs/mx53loco.h u-boot-imx-e1eb75b/include/configs/mx53loco.h
> index 8cbaf08..6a6aaa1 100644
> --- u-boot-imx-e1eb75b.orig/include/configs/mx53loco.h
> +++ u-boot-imx-e1eb75b/include/configs/mx53loco.h
> @@ -25,8 +25,6 @@
>
> #define CONFIG_MX53
>
> -#define CONFIG_SYS_MX5_HCLK 24000000
> -#define CONFIG_SYS_MX5_CLK32 32768
> #define CONFIG_DISPLAY_BOARDINFO
>
> #define CONFIG_MACH_TYPE MACH_TYPE_MX53_LOCO
> diff --git u-boot-imx-e1eb75b.orig/include/configs/mx53smd.h u-boot-imx-e1eb75b/include/configs/mx53smd.h
> index f54d328..ff2a290 100644
> --- u-boot-imx-e1eb75b.orig/include/configs/mx53smd.h
> +++ u-boot-imx-e1eb75b/include/configs/mx53smd.h
> @@ -24,8 +24,6 @@
>
> #define CONFIG_MX53
>
> -#define CONFIG_SYS_MX5_HCLK 24000000
> -#define CONFIG_SYS_MX5_CLK32 32768
> #define CONFIG_DISPLAY_CPUINFO
> #define CONFIG_DISPLAY_BOARDINFO
>
> diff --git u-boot-imx-e1eb75b.orig/include/configs/mx6qarm2.h u-boot-imx-e1eb75b/include/configs/mx6qarm2.h
> index 6c17895..965bea3 100644
> --- u-boot-imx-e1eb75b.orig/include/configs/mx6qarm2.h
> +++ u-boot-imx-e1eb75b/include/configs/mx6qarm2.h
> @@ -23,8 +23,6 @@
> #define __CONFIG_H
>
> #define CONFIG_MX6Q
> -#define CONFIG_SYS_MX6_HCLK 24000000
> -#define CONFIG_SYS_MX6_CLK32 32768
> #define CONFIG_DISPLAY_CPUINFO
> #define CONFIG_DISPLAY_BOARDINFO
>
> diff --git u-boot-imx-e1eb75b.orig/include/configs/mx6qsabrelite.h u-boot-imx-e1eb75b/include/configs/mx6qsabrelite.h
> index 72d0154..e7bf658 100644
> --- u-boot-imx-e1eb75b.orig/include/configs/mx6qsabrelite.h
> +++ u-boot-imx-e1eb75b/include/configs/mx6qsabrelite.h
> @@ -23,8 +23,6 @@
> #define __CONFIG_H
>
> #define CONFIG_MX6Q
> -#define CONFIG_SYS_MX6_HCLK 24000000
> -#define CONFIG_SYS_MX6_CLK32 32768
> #define CONFIG_DISPLAY_CPUINFO
> #define CONFIG_DISPLAY_BOARDINFO
>
> diff --git u-boot-imx-e1eb75b.orig/include/configs/vision2.h u-boot-imx-e1eb75b/include/configs/vision2.h
> index fba897c..848df88 100644
> --- u-boot-imx-e1eb75b.orig/include/configs/vision2.h
> +++ u-boot-imx-e1eb75b/include/configs/vision2.h
> @@ -30,8 +30,6 @@
>
> #include <asm/arch/imx-regs.h>
>
> -#define CONFIG_SYS_MX5_HCLK 24000000
> -#define CONFIG_SYS_MX5_CLK32 32768
> #define CONFIG_DISPLAY_CPUINFO
> #define CONFIG_DISPLAY_BOARDINFO
>
>
Acked-by: Stefano Babic <sbabic@denx.de>
Tested-by: Stefano Babic <sbabic@denx.de>
Best regards,
Stefano Babic
--
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DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
next prev parent reply other threads:[~2012-09-28 8:42 UTC|newest]
Thread overview: 52+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-08-14 18:05 [U-Boot] [PATCH 00/10] mx5: Fix clocks Benoît Thébaudeau
2012-08-14 18:06 ` [U-Boot] [PATCH 01/10] mx5: Undeclare imx_decode_pll() Benoît Thébaudeau
2012-08-23 9:10 ` Stefano Babic
2012-08-14 18:06 ` [U-Boot] [PATCH 02/10] mx5: Use explicit clock gate names Benoît Thébaudeau
2012-08-14 18:54 ` Marek Vasut
2012-08-14 19:13 ` Benoît Thébaudeau
2012-09-27 20:19 ` [U-Boot] [PATCH v2 01/14] mx5/6: Define default SoC input clock frequencies Benoît Thébaudeau
2012-09-27 20:20 ` [U-Boot] [PATCH v2 02/14] mx5 clocks: Cleanup Benoît Thébaudeau
2012-09-28 8:44 ` Stefano Babic
2012-09-27 20:21 ` [U-Boot] [PATCH v2 03/14] mx5: Use explicit clock gate names Benoît Thébaudeau
2012-09-28 8:53 ` Stefano Babic
2012-09-27 20:21 ` [U-Boot] [PATCH v2 04/14] mx5: Fix clock gate values Benoît Thébaudeau
2012-09-27 20:21 ` [U-Boot] [PATCH v2 05/14] mx51: Fix USB PHY clocks Benoît Thébaudeau
2012-09-27 20:47 ` Marek Vasut
2012-09-28 7:26 ` Igor Grinberg
2012-09-28 10:27 ` Benoît Thébaudeau
2012-09-28 10:43 ` Stefano Babic
2012-09-28 13:00 ` Benoît Thébaudeau
2012-09-28 15:02 ` Stefano Babic
2012-09-28 17:09 ` [U-Boot] [PATCH v3 " Benoît Thébaudeau
2012-10-02 8:35 ` Igor Grinberg
2012-09-27 20:22 ` [U-Boot] [PATCH v2 06/14] mx5 clocks: Add and use CCSR definitions Benoît Thébaudeau
2012-09-27 20:22 ` [U-Boot] [PATCH v2 07/14] mx5 clocks: Fix get_lp_apm() Benoît Thébaudeau
2012-09-27 20:22 ` [U-Boot] [PATCH v2 08/14] mx5 clocks: Fix get_periph_clk() Benoît Thébaudeau
2012-09-27 20:23 ` [U-Boot] [PATCH v2 09/14] mx5 clocks: Fix get_ipg_per_clk() Benoît Thébaudeau
2012-09-28 9:31 ` Stefano Babic
2012-09-28 10:42 ` Benoît Thébaudeau
2012-09-28 10:45 ` Stefano Babic
2012-09-28 12:55 ` Benoît Thébaudeau
2012-09-28 15:01 ` Stefano Babic
2012-09-27 20:23 ` [U-Boot] [PATCH v2 10/14] mx5 clocks: Fix get_uart_clk() Benoît Thébaudeau
2012-09-27 20:23 ` [U-Boot] [PATCH v2 11/14] mx5 clocks: Simplify imx_get_cspiclk() Benoît Thébaudeau
2012-09-27 20:23 ` [U-Boot] [PATCH v2 12/14] mx5 clocks: Fix MXC_FEC_CLK Benoît Thébaudeau
2012-09-27 20:24 ` [U-Boot] [PATCH v2 13/14] mx51: Fix I2C clock ID check Benoît Thébaudeau
2012-09-27 20:24 ` [U-Boot] [PATCH v2 14/14] mx5/6 clocks: Fix SDHC clocks Benoît Thébaudeau
2012-09-28 8:42 ` Stefano Babic [this message]
2012-09-30 10:28 ` [U-Boot] [PATCH v2 01/14] mx5/6: Define default SoC input clock frequencies Stefano Babic
2012-09-30 13:55 ` Benoît Thébaudeau
2012-09-30 14:05 ` Stefano Babic
2012-08-14 18:06 ` [U-Boot] [PATCH 03/10] mx5 clocks: Add and use CCSR definitions Benoît Thébaudeau
2012-08-14 18:55 ` Marek Vasut
2012-08-14 19:14 ` Benoît Thébaudeau
2012-08-14 19:11 ` Marek Vasut
2012-08-14 18:07 ` [U-Boot] [PATCH 04/10] mx5 clocks: Fix get_lp_apm() Benoît Thébaudeau
2012-08-14 18:07 ` [U-Boot] [PATCH 05/10] mx5 clocks: Fix get_periph_clk() Benoît Thébaudeau
2012-08-14 18:07 ` [U-Boot] [PATCH 06/10] mx5 clocks: Fix get_ipg_per_clk() Benoît Thébaudeau
2012-08-14 18:07 ` [U-Boot] [PATCH 07/10] mx5 clocks: Fix get_uart_clk() Benoît Thébaudeau
2012-08-20 9:52 ` Stefano Babic
2012-08-20 10:05 ` Stefano Babic
2012-08-14 18:07 ` [U-Boot] [PATCH 08/10] mx5 clocks: Simplify imx_get_cspiclk() Benoît Thébaudeau
2012-08-14 18:08 ` [U-Boot] [PATCH 09/10] mx5 clocks: Fix eSDHC clock Benoît Thébaudeau
2012-08-14 18:08 ` [U-Boot] [PATCH 10/10] mx5 clocks: Fix MXC_FEC_CLK Benoît Thébaudeau
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