From: Marek Vasut <marex@denx.de>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 03/10] mx5 clocks: Add and use CCSR definitions
Date: Tue, 14 Aug 2012 21:11:10 +0200 [thread overview]
Message-ID: <201208142111.10802.marex@denx.de> (raw)
In-Reply-To: <1369929236.2410129.1344971699769.JavaMail.root@advansee.com>
Dear Beno?t Th?baudeau,
> Dear Marek Vasut,
>
> > Dear Beno?t Th?baudeau,
> >
> > > This fixes config_pll_clk(), which used 0x20 instead of 0x200 for
> > > PLL4_CLOCK.
> > >
> > > Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
> > > Cc: Stefano Babic <sbabic@denx.de>
> > > ---
> > >
> > > .../arch/arm/cpu/armv7/mx5/clock.c | 34
> > >
> > > +++++++++++++------- .../arch/arm/include/asm/arch-mx5/crm_regs.h
> > >
> > > 17 ++++++++++ 2 files changed, 40 insertions(+), 11 deletions(-)
> > >
> > > diff --git u-boot-4d3c95f.orig/arch/arm/cpu/armv7/mx5/clock.c
> > > u-boot-4d3c95f/arch/arm/cpu/armv7/mx5/clock.c index
> > > 9b083c0..10843a4
> > > 100644
> > > --- u-boot-4d3c95f.orig/arch/arm/cpu/armv7/mx5/clock.c
> > > +++ u-boot-4d3c95f/arch/arm/cpu/armv7/mx5/clock.c
> > > @@ -36,7 +36,9 @@ enum pll_clocks {
> > >
> > > PLL1_CLOCK = 0,
> > > PLL2_CLOCK,
> > > PLL3_CLOCK,
> > >
> > > +#ifdef CONFIG_MX53
> > >
> > > PLL4_CLOCK,
> > >
> > > +#endif
> > >
> > > PLL_CLOCKS,
> > >
> > > };
> > >
> > > @@ -379,10 +381,10 @@ static u32 get_lp_apm(void)
> > >
> > > u32 ret_val = 0;
> > > u32 ccsr = __raw_readl(&mxc_ccm->ccsr);
> > >
> > > - if (((ccsr >> 9) & 1) == 0)
> > > - ret_val = CONFIG_SYS_MX5_HCLK;
> > > + if (ccsr & MXC_CCM_CCSR_LP_APM)
> > > + ret_val = 32768 * 1024;
> > >
> > > else
> > >
> > > - ret_val = ((32768 * 1024));
> > > + ret_val = CONFIG_SYS_MX5_HCLK;
> > >
> > > return ret_val;
> > >
> > > }
> > >
> > > @@ -660,40 +662,50 @@ static int config_pll_clk(enum pll_clocks
> > > index,
> > > struct pll_param *pll_param) switch (index) {
> > >
> > > case PLL1_CLOCK:
> > > /* Switch ARM to PLL2 clock */
> > >
> > > - __raw_writel(ccsr | 0x4, &mxc_ccm->ccsr);
> > > + __raw_writel(ccsr | MXC_CCM_CCSR_PLL1_SW_CLK_SEL,
> > > + &mxc_ccm->ccsr);
> > >
> > > CHANGE_PLL_SETTINGS(pll, pll_param->pd,
> > >
> > > pll_param->mfi, pll_param->mfn,
> > > pll_param->mfd);
> > >
> > > /* Switch back */
> > >
> > > - __raw_writel(ccsr & ~0x4, &mxc_ccm->ccsr);
> > > + __raw_writel(ccsr & ~MXC_CCM_CCSR_PLL1_SW_CLK_SEL,
> > > + &mxc_ccm->ccsr);
> >
> > Why use __raw_writel() instead of writel() ? Besides ... again,
> > clrsetbits_le32() is a better bet.
>
> Sure, but it's again for consistency with the existing code.
Existing code looks crappy, any reason to not fix it ;-)
[...]
next prev parent reply other threads:[~2012-08-14 19:11 UTC|newest]
Thread overview: 52+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-08-14 18:05 [U-Boot] [PATCH 00/10] mx5: Fix clocks Benoît Thébaudeau
2012-08-14 18:06 ` [U-Boot] [PATCH 01/10] mx5: Undeclare imx_decode_pll() Benoît Thébaudeau
2012-08-23 9:10 ` Stefano Babic
2012-08-14 18:06 ` [U-Boot] [PATCH 02/10] mx5: Use explicit clock gate names Benoît Thébaudeau
2012-08-14 18:54 ` Marek Vasut
2012-08-14 19:13 ` Benoît Thébaudeau
2012-09-27 20:19 ` [U-Boot] [PATCH v2 01/14] mx5/6: Define default SoC input clock frequencies Benoît Thébaudeau
2012-09-27 20:20 ` [U-Boot] [PATCH v2 02/14] mx5 clocks: Cleanup Benoît Thébaudeau
2012-09-28 8:44 ` Stefano Babic
2012-09-27 20:21 ` [U-Boot] [PATCH v2 03/14] mx5: Use explicit clock gate names Benoît Thébaudeau
2012-09-28 8:53 ` Stefano Babic
2012-09-27 20:21 ` [U-Boot] [PATCH v2 04/14] mx5: Fix clock gate values Benoît Thébaudeau
2012-09-27 20:21 ` [U-Boot] [PATCH v2 05/14] mx51: Fix USB PHY clocks Benoît Thébaudeau
2012-09-27 20:47 ` Marek Vasut
2012-09-28 7:26 ` Igor Grinberg
2012-09-28 10:27 ` Benoît Thébaudeau
2012-09-28 10:43 ` Stefano Babic
2012-09-28 13:00 ` Benoît Thébaudeau
2012-09-28 15:02 ` Stefano Babic
2012-09-28 17:09 ` [U-Boot] [PATCH v3 " Benoît Thébaudeau
2012-10-02 8:35 ` Igor Grinberg
2012-09-27 20:22 ` [U-Boot] [PATCH v2 06/14] mx5 clocks: Add and use CCSR definitions Benoît Thébaudeau
2012-09-27 20:22 ` [U-Boot] [PATCH v2 07/14] mx5 clocks: Fix get_lp_apm() Benoît Thébaudeau
2012-09-27 20:22 ` [U-Boot] [PATCH v2 08/14] mx5 clocks: Fix get_periph_clk() Benoît Thébaudeau
2012-09-27 20:23 ` [U-Boot] [PATCH v2 09/14] mx5 clocks: Fix get_ipg_per_clk() Benoît Thébaudeau
2012-09-28 9:31 ` Stefano Babic
2012-09-28 10:42 ` Benoît Thébaudeau
2012-09-28 10:45 ` Stefano Babic
2012-09-28 12:55 ` Benoît Thébaudeau
2012-09-28 15:01 ` Stefano Babic
2012-09-27 20:23 ` [U-Boot] [PATCH v2 10/14] mx5 clocks: Fix get_uart_clk() Benoît Thébaudeau
2012-09-27 20:23 ` [U-Boot] [PATCH v2 11/14] mx5 clocks: Simplify imx_get_cspiclk() Benoît Thébaudeau
2012-09-27 20:23 ` [U-Boot] [PATCH v2 12/14] mx5 clocks: Fix MXC_FEC_CLK Benoît Thébaudeau
2012-09-27 20:24 ` [U-Boot] [PATCH v2 13/14] mx51: Fix I2C clock ID check Benoît Thébaudeau
2012-09-27 20:24 ` [U-Boot] [PATCH v2 14/14] mx5/6 clocks: Fix SDHC clocks Benoît Thébaudeau
2012-09-28 8:42 ` [U-Boot] [PATCH v2 01/14] mx5/6: Define default SoC input clock frequencies Stefano Babic
2012-09-30 10:28 ` Stefano Babic
2012-09-30 13:55 ` Benoît Thébaudeau
2012-09-30 14:05 ` Stefano Babic
2012-08-14 18:06 ` [U-Boot] [PATCH 03/10] mx5 clocks: Add and use CCSR definitions Benoît Thébaudeau
2012-08-14 18:55 ` Marek Vasut
2012-08-14 19:14 ` Benoît Thébaudeau
2012-08-14 19:11 ` Marek Vasut [this message]
2012-08-14 18:07 ` [U-Boot] [PATCH 04/10] mx5 clocks: Fix get_lp_apm() Benoît Thébaudeau
2012-08-14 18:07 ` [U-Boot] [PATCH 05/10] mx5 clocks: Fix get_periph_clk() Benoît Thébaudeau
2012-08-14 18:07 ` [U-Boot] [PATCH 06/10] mx5 clocks: Fix get_ipg_per_clk() Benoît Thébaudeau
2012-08-14 18:07 ` [U-Boot] [PATCH 07/10] mx5 clocks: Fix get_uart_clk() Benoît Thébaudeau
2012-08-20 9:52 ` Stefano Babic
2012-08-20 10:05 ` Stefano Babic
2012-08-14 18:07 ` [U-Boot] [PATCH 08/10] mx5 clocks: Simplify imx_get_cspiclk() Benoît Thébaudeau
2012-08-14 18:08 ` [U-Boot] [PATCH 09/10] mx5 clocks: Fix eSDHC clock Benoît Thébaudeau
2012-08-14 18:08 ` [U-Boot] [PATCH 10/10] mx5 clocks: Fix MXC_FEC_CLK Benoît Thébaudeau
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