[lm-sensors] [PATCH 1/2] hwmon: (coretemp) Detect the thermal

[lm-sensors] [PATCH 1/2] hwmon: (coretemp) Detect the thermal

[Huaxu Wan]

The thermal sensors of Intel CPUs can be detected by CPUID instruction,
indicated by CPUID.06H.EAX[0].

Signed-off-by: Huaxu Wan <huaxu.wan@intel.com>
---
 drivers/hwmon/coretemp.c |   24 +++++++-----------------
 1 files changed, 7 insertions(+), 17 deletions(-)

diff --git a/drivers/hwmon/coretemp.c b/drivers/hwmon/coretemp.c
index 2d7bcee..55122d8 100644
--- a/drivers/hwmon/coretemp.c
+++ b/drivers/hwmon/coretemp.c
@@ -440,6 +440,7 @@ static int __init coretemp_init(void)
 {
 	int i, err = -ENODEV;
 	struct pdev_entry *p, *n;
+	u32 eax;
 
 	/* quick check if we run Intel */
 	if (cpu_data(0).x86_vendor != X86_VENDOR_INTEL)
@@ -450,23 +451,12 @@ static int __init coretemp_init(void)
 		goto exit;
 
 	for_each_online_cpu(i) {
-		struct cpuinfo_x86 *c = &cpu_data(i);
-
-		/* check if family 6, models 0xe (Pentium M DC),
-		  0xf (Core 2 DC 65nm), 0x16 (Core 2 SC 65nm),
-		  0x17 (Penryn 45nm), 0x1a (Nehalem), 0x1c (Atom),
-		  0x1e (Lynnfield) */
-		if ((c->cpuid_level < 0) || (c->x86 != 0x6) ||
-		    !((c->x86_model = 0xe) || (c->x86_model = 0xf) ||
-			(c->x86_model = 0x16) || (c->x86_model = 0x17) ||
-			(c->x86_model = 0x1a) || (c->x86_model = 0x1c) ||
-			(c->x86_model = 0x1e))) {
-
-			/* supported CPU not found, but report the unknown
-			   family 6 CPU */
-			if ((c->x86 = 0x6) && (c->x86_model > 0xf))
-				printk(KERN_WARNING DRVNAME ": Unknown CPU "
-					"model %x\n", c->x86_model);
+		/* check if the CPU has thermal sensor */
+		eax = cpuid_eax(0x06);
+		if (!(eax & 0x01)) {
+			struct cpuinfo_x86 *c = &cpu_data(i);
+			printk_once(KERN_WARNING DRVNAME ": CPU (model=0x%x)"
+				" has no thermal sensor!\n", c->x86_model);
 			continue;
 		}
 
-- 
1.6.3.3.363.g725cf7

_______________________________________________
lm-sensors mailing list
lm-sensors@lm-sensors.org
http://lists.lm-sensors.org/mailman/listinfo/lm-sensors

[lm-sensors] [PATCH 1/2] hwmon: (coretemp) Detect the thermal

[Huaxu Wan]

The thermal sensors of Intel(R) CPUs can be detected by CPUID instruction,
indicated by CPUID.06H.EAX[0].

Signed-off-by: Huaxu Wan <huaxu.wan@linux.intel.com>
---
 drivers/hwmon/coretemp.c |   24 +++++++-----------------
 1 files changed, 7 insertions(+), 17 deletions(-)

diff --git a/drivers/hwmon/coretemp.c b/drivers/hwmon/coretemp.c
index e9b7fbc..237c68d 100644
--- a/drivers/hwmon/coretemp.c
+++ b/drivers/hwmon/coretemp.c
@@ -440,6 +440,7 @@ static int __init coretemp_init(void)
 {
        int i, err = -ENODEV;
        struct pdev_entry *p, *n;
+       u32 eax;

        /* quick check if we run Intel */
        if (cpu_data(0).x86_vendor != X86_VENDOR_INTEL)
@@ -450,23 +451,12 @@ static int __init coretemp_init(void)
                goto exit;

        for_each_online_cpu(i) {
-               struct cpuinfo_x86 *c = &cpu_data(i);
-
-               /* check if family 6, models 0xe (Pentium M DC),
-                 0xf (Core 2 DC 65nm), 0x16 (Core 2 SC 65nm),
-                 0x17 (Penryn 45nm), 0x1a (Nehalem), 0x1c (Atom),
-                 0x1e (Lynnfield) */
-               if ((c->cpuid_level < 0) || (c->x86 != 0x6) ||
-                   !((c->x86_model = 0xe) || (c->x86_model = 0xf) ||
-                       (c->x86_model = 0x16) || (c->x86_model = 0x17) ||
-                       (c->x86_model = 0x1a) || (c->x86_model = 0x1c) ||
-                       (c->x86_model = 0x1e))) {
-
-                       /* supported CPU not found, but report the unknown
-                          family 6 CPU */
-                       if ((c->x86 = 0x6) && (c->x86_model > 0xf))
-                               printk(KERN_WARNING DRVNAME ": Unknown CPU "
-                                       "model 0x%x\n", c->x86_model);
+               /* check if the CPU has thermal sensor */
+               eax = cpuid_eax(0x06);
+               if (!(eax & 0x01)) {
+                       struct cpuinfo_x86 *c = &cpu_data(i);
+                       printk_once(KERN_WARNING DRVNAME ": CPU (model=0x%x)"
+                               " has no thermal sensor!\n", c->x86_model);
                        continue;
                }

--
1.6.3.3.363.g725cf7

_______________________________________________
lm-sensors mailing list
lm-sensors@lm-sensors.org
http://lists.lm-sensors.org/mailman/listinfo/lm-sensors

[PATCH 1/2] hwmon: (coretemp) Detect the thermal sensors by CPUID

[Huaxu Wan]

The thermal sensors of Intel(R) CPUs can be detected by CPUID instruction,
indicated by CPUID.06H.EAX[0].

Signed-off-by: Huaxu Wan <huaxu.wan@linux.intel.com>
---
 drivers/hwmon/coretemp.c |   24 +++++++-----------------
 1 files changed, 7 insertions(+), 17 deletions(-)

diff --git a/drivers/hwmon/coretemp.c b/drivers/hwmon/coretemp.c
index e9b7fbc..237c68d 100644
--- a/drivers/hwmon/coretemp.c
+++ b/drivers/hwmon/coretemp.c
@@ -440,6 +440,7 @@ static int __init coretemp_init(void)
 {
        int i, err = -ENODEV;
        struct pdev_entry *p, *n;
+       u32 eax;

        /* quick check if we run Intel */
        if (cpu_data(0).x86_vendor != X86_VENDOR_INTEL)
@@ -450,23 +451,12 @@ static int __init coretemp_init(void)
                goto exit;

        for_each_online_cpu(i) {
-               struct cpuinfo_x86 *c = &cpu_data(i);
-
-               /* check if family 6, models 0xe (Pentium M DC),
-                 0xf (Core 2 DC 65nm), 0x16 (Core 2 SC 65nm),
-                 0x17 (Penryn 45nm), 0x1a (Nehalem), 0x1c (Atom),
-                 0x1e (Lynnfield) */
-               if ((c->cpuid_level < 0) || (c->x86 != 0x6) ||
-                   !((c->x86_model == 0xe) || (c->x86_model == 0xf) ||
-                       (c->x86_model == 0x16) || (c->x86_model == 0x17) ||
-                       (c->x86_model == 0x1a) || (c->x86_model == 0x1c) ||
-                       (c->x86_model == 0x1e))) {
-
-                       /* supported CPU not found, but report the unknown
-                          family 6 CPU */
-                       if ((c->x86 == 0x6) && (c->x86_model > 0xf))
-                               printk(KERN_WARNING DRVNAME ": Unknown CPU "
-                                       "model 0x%x\n", c->x86_model);
+               /* check if the CPU has thermal sensor */
+               eax = cpuid_eax(0x06);
+               if (!(eax & 0x01)) {
+                       struct cpuinfo_x86 *c = &cpu_data(i);
+                       printk_once(KERN_WARNING DRVNAME ": CPU (model=0x%x)"
+                               " has no thermal sensor!\n", c->x86_model);
                        continue;
                }

--
1.6.3.3.363.g725cf7

Re: [lm-sensors] [PATCH 1/2] hwmon: (coretemp) Detect the thermal

[Jean Delvare]

Hi Huawu,

On Fri, 7 May 2010 17:54:59 +0800, Huaxu Wan wrote:
> 
> The thermal sensors of Intel(R) CPUs can be detected by CPUID instruction,
> indicated by CPUID.06H.EAX[0].

I can see that you are sending these two patches for quite some time
and I understand you'd like them to get finally reviewed and merged.
Unfortunately I simply don't have the time for this. So please don't
wait for my ack, just send your patches to Andrew Morton and hopefully
he will take care.

> 
> Signed-off-by: Huaxu Wan <huaxu.wan@linux.intel.com>
> ---
>  drivers/hwmon/coretemp.c |   24 +++++++-----------------
>  1 files changed, 7 insertions(+), 17 deletions(-)
> 
> diff --git a/drivers/hwmon/coretemp.c b/drivers/hwmon/coretemp.c
> index e9b7fbc..237c68d 100644
> --- a/drivers/hwmon/coretemp.c
> +++ b/drivers/hwmon/coretemp.c
> @@ -440,6 +440,7 @@ static int __init coretemp_init(void)
>  {
>         int i, err = -ENODEV;
>         struct pdev_entry *p, *n;
> +       u32 eax;
> 
>         /* quick check if we run Intel */
>         if (cpu_data(0).x86_vendor != X86_VENDOR_INTEL)
> @@ -450,23 +451,12 @@ static int __init coretemp_init(void)
>                 goto exit;
> 
>         for_each_online_cpu(i) {
> -               struct cpuinfo_x86 *c = &cpu_data(i);
> -
> -               /* check if family 6, models 0xe (Pentium M DC),
> -                 0xf (Core 2 DC 65nm), 0x16 (Core 2 SC 65nm),
> -                 0x17 (Penryn 45nm), 0x1a (Nehalem), 0x1c (Atom),
> -                 0x1e (Lynnfield) */
> -               if ((c->cpuid_level < 0) || (c->x86 != 0x6) ||
> -                   !((c->x86_model = 0xe) || (c->x86_model = 0xf) ||
> -                       (c->x86_model = 0x16) || (c->x86_model = 0x17) ||
> -                       (c->x86_model = 0x1a) || (c->x86_model = 0x1c) ||
> -                       (c->x86_model = 0x1e))) {
> -
> -                       /* supported CPU not found, but report the unknown
> -                          family 6 CPU */
> -                       if ((c->x86 = 0x6) && (c->x86_model > 0xf))
> -                               printk(KERN_WARNING DRVNAME ": Unknown CPU "
> -                                       "model 0x%x\n", c->x86_model);
> +               /* check if the CPU has thermal sensor */
> +               eax = cpuid_eax(0x06);
> +               if (!(eax & 0x01)) {
> +                       struct cpuinfo_x86 *c = &cpu_data(i);
> +                       printk_once(KERN_WARNING DRVNAME ": CPU (model=0x%x)"
> +                               " has no thermal sensor!\n", c->x86_model);
>                         continue;
>                 }
> 
> --
> 1.6.3.3.363.g725cf7


-- 
Jean Delvare

_______________________________________________
lm-sensors mailing list
lm-sensors@lm-sensors.org
http://lists.lm-sensors.org/mailman/listinfo/lm-sensors

Re: [PATCH 1/2] hwmon: (coretemp) Detect the thermal sensors by CPUID

[Jean Delvare]

Hi Huawu,

On Fri, 7 May 2010 17:54:59 +0800, Huaxu Wan wrote:
> 
> The thermal sensors of Intel(R) CPUs can be detected by CPUID instruction,
> indicated by CPUID.06H.EAX[0].

I can see that you are sending these two patches for quite some time
and I understand you'd like them to get finally reviewed and merged.
Unfortunately I simply don't have the time for this. So please don't
wait for my ack, just send your patches to Andrew Morton and hopefully
he will take care.

> 
> Signed-off-by: Huaxu Wan <huaxu.wan@linux.intel.com>
> ---
>  drivers/hwmon/coretemp.c |   24 +++++++-----------------
>  1 files changed, 7 insertions(+), 17 deletions(-)
> 
> diff --git a/drivers/hwmon/coretemp.c b/drivers/hwmon/coretemp.c
> index e9b7fbc..237c68d 100644
> --- a/drivers/hwmon/coretemp.c
> +++ b/drivers/hwmon/coretemp.c
> @@ -440,6 +440,7 @@ static int __init coretemp_init(void)
>  {
>         int i, err = -ENODEV;
>         struct pdev_entry *p, *n;
> +       u32 eax;
> 
>         /* quick check if we run Intel */
>         if (cpu_data(0).x86_vendor != X86_VENDOR_INTEL)
> @@ -450,23 +451,12 @@ static int __init coretemp_init(void)
>                 goto exit;
> 
>         for_each_online_cpu(i) {
> -               struct cpuinfo_x86 *c = &cpu_data(i);
> -
> -               /* check if family 6, models 0xe (Pentium M DC),
> -                 0xf (Core 2 DC 65nm), 0x16 (Core 2 SC 65nm),
> -                 0x17 (Penryn 45nm), 0x1a (Nehalem), 0x1c (Atom),
> -                 0x1e (Lynnfield) */
> -               if ((c->cpuid_level < 0) || (c->x86 != 0x6) ||
> -                   !((c->x86_model == 0xe) || (c->x86_model == 0xf) ||
> -                       (c->x86_model == 0x16) || (c->x86_model == 0x17) ||
> -                       (c->x86_model == 0x1a) || (c->x86_model == 0x1c) ||
> -                       (c->x86_model == 0x1e))) {
> -
> -                       /* supported CPU not found, but report the unknown
> -                          family 6 CPU */
> -                       if ((c->x86 == 0x6) && (c->x86_model > 0xf))
> -                               printk(KERN_WARNING DRVNAME ": Unknown CPU "
> -                                       "model 0x%x\n", c->x86_model);
> +               /* check if the CPU has thermal sensor */
> +               eax = cpuid_eax(0x06);
> +               if (!(eax & 0x01)) {
> +                       struct cpuinfo_x86 *c = &cpu_data(i);
> +                       printk_once(KERN_WARNING DRVNAME ": CPU (model=0x%x)"
> +                               " has no thermal sensor!\n", c->x86_model);
>                         continue;
>                 }
> 
> --
> 1.6.3.3.363.g725cf7


-- 
Jean Delvare

Re: [lm-sensors] [PATCH 1/2] hwmon: (coretemp) Detect the thermal

[Carsten Emde]

[-- Attachment #1: Type: text/plain, Size: 347 bytes --]

Hi Huaxu,

> The thermal sensors of Intel(R) CPUs can be detected by CPUID instruction,
> indicated by CPUID.06H.EAX[0].
Thanks, works great, successfully tested it on an i7 machine.

I would propose to use dev_warn() instead of printk_once(), since all
other per-cpu info is also logged this way.

Signed-off-by: Carsten Emde <C.Emde@osadl.org>


[-- Attachment #2: coretemp-simplify-intel-thermal-sensor-recognition.patch --]
[-- Type: text/x-patch, Size: 1536 bytes --]

---
 drivers/hwmon/coretemp.c |   23 +++++++----------------
 1 file changed, 7 insertions(+), 16 deletions(-)

Index: head/drivers/hwmon/coretemp.c
===================================================================
--- head.orig/drivers/hwmon/coretemp.c
+++ head/drivers/hwmon/coretemp.c
@@ -440,6 +440,7 @@ static int __init coretemp_init(void)
 {
 	int i, err = -ENODEV;
 	struct pdev_entry *p, *n;
+	u32 eax;
 
 	/* quick check if we run Intel */
 	if (cpu_data(0).x86_vendor != X86_VENDOR_INTEL)
@@ -450,23 +451,13 @@ static int __init coretemp_init(void)
 		goto exit;
 
 	for_each_online_cpu(i) {
-		struct cpuinfo_x86 *c = &cpu_data(i);
+		/* check if the CPU has thermal sensor */
+		eax = cpuid_eax(0x06);
+		if (!(eax & 0x01)) {
+			struct cpuinfo_x86 *c = &cpu_data(i);
 
-		/* check if family 6, models 0xe (Pentium M DC),
-		  0xf (Core 2 DC 65nm), 0x16 (Core 2 SC 65nm),
-		  0x17 (Penryn 45nm), 0x1a (Nehalem), 0x1c (Atom),
-		  0x1e (Lynnfield) */
-		if ((c->cpuid_level < 0) || (c->x86 != 0x6) ||
-		    !((c->x86_model == 0xe) || (c->x86_model == 0xf) ||
-			(c->x86_model == 0x16) || (c->x86_model == 0x17) ||
-			(c->x86_model == 0x1a) || (c->x86_model == 0x1c) ||
-			(c->x86_model == 0x1e))) {
-
-			/* supported CPU not found, but report the unknown
-			   family 6 CPU */
-			if ((c->x86 == 0x6) && (c->x86_model > 0xf))
-				printk(KERN_WARNING DRVNAME ": Unknown CPU "
-					"model 0x%x\n", c->x86_model);
+			dev_warn("CPU (model=0x%x) has no thermal sensor!\n",
+			    c->x86_model);
 			continue;
 		}
 

[-- Attachment #3: Type: text/plain, Size: 153 bytes --]

_______________________________________________
lm-sensors mailing list
lm-sensors@lm-sensors.org
http://lists.lm-sensors.org/mailman/listinfo/lm-sensors

Re: [lm-sensors] [PATCH 1/2] hwmon: (coretemp) Detect the thermal sensors by CPUID

[Carsten Emde]

[-- Attachment #1: Type: text/plain, Size: 347 bytes --]

Hi Huaxu,

> The thermal sensors of Intel(R) CPUs can be detected by CPUID instruction,
> indicated by CPUID.06H.EAX[0].
Thanks, works great, successfully tested it on an i7 machine.

I would propose to use dev_warn() instead of printk_once(), since all
other per-cpu info is also logged this way.

Signed-off-by: Carsten Emde <C.Emde@osadl.org>


[-- Attachment #2: coretemp-simplify-intel-thermal-sensor-recognition.patch --]
[-- Type: text/x-patch, Size: 1536 bytes --]

---
 drivers/hwmon/coretemp.c |   23 +++++++----------------
 1 file changed, 7 insertions(+), 16 deletions(-)

Index: head/drivers/hwmon/coretemp.c
===================================================================
--- head.orig/drivers/hwmon/coretemp.c
+++ head/drivers/hwmon/coretemp.c
@@ -440,6 +440,7 @@ static int __init coretemp_init(void)
 {
 	int i, err = -ENODEV;
 	struct pdev_entry *p, *n;
+	u32 eax;
 
 	/* quick check if we run Intel */
 	if (cpu_data(0).x86_vendor != X86_VENDOR_INTEL)
@@ -450,23 +451,13 @@ static int __init coretemp_init(void)
 		goto exit;
 
 	for_each_online_cpu(i) {
-		struct cpuinfo_x86 *c = &cpu_data(i);
+		/* check if the CPU has thermal sensor */
+		eax = cpuid_eax(0x06);
+		if (!(eax & 0x01)) {
+			struct cpuinfo_x86 *c = &cpu_data(i);
 
-		/* check if family 6, models 0xe (Pentium M DC),
-		  0xf (Core 2 DC 65nm), 0x16 (Core 2 SC 65nm),
-		  0x17 (Penryn 45nm), 0x1a (Nehalem), 0x1c (Atom),
-		  0x1e (Lynnfield) */
-		if ((c->cpuid_level < 0) || (c->x86 != 0x6) ||
-		    !((c->x86_model == 0xe) || (c->x86_model == 0xf) ||
-			(c->x86_model == 0x16) || (c->x86_model == 0x17) ||
-			(c->x86_model == 0x1a) || (c->x86_model == 0x1c) ||
-			(c->x86_model == 0x1e))) {
-
-			/* supported CPU not found, but report the unknown
-			   family 6 CPU */
-			if ((c->x86 == 0x6) && (c->x86_model > 0xf))
-				printk(KERN_WARNING DRVNAME ": Unknown CPU "
-					"model 0x%x\n", c->x86_model);
+			dev_warn("CPU (model=0x%x) has no thermal sensor!\n",
+			    c->x86_model);
 			continue;
 		}
 

Re: [lm-sensors] [PATCH 1/2] hwmon: (coretemp) Detect the thermal

[Huaxu Wan]

On 15:21 Fri 07 May, Carsten Emde wrote:
> Hi Huaxu,
> 
> > The thermal sensors of Intel(R) CPUs can be detected by CPUID instruction,
> > indicated by CPUID.06H.EAX[0].
> Thanks, works great, successfully tested it on an i7 machine.
> 
> I would propose to use dev_warn() instead of printk_once(), since all
> other per-cpu info is also logged this way.
> 
> Signed-off-by: Carsten Emde <C.Emde@osadl.org>
> 

That reminds me that dev_warn is right one on multiple CPU system, especially with different CPUs. Thank you.

> ---
>  drivers/hwmon/coretemp.c |   23 +++++++----------------
>  1 file changed, 7 insertions(+), 16 deletions(-)
> 
> Index: head/drivers/hwmon/coretemp.c
> =================================> --- head.orig/drivers/hwmon/coretemp.c
> +++ head/drivers/hwmon/coretemp.c
> @@ -440,6 +440,7 @@ static int __init coretemp_init(void)
>  {
>  	int i, err = -ENODEV;
>  	struct pdev_entry *p, *n;
> +	u32 eax;
>  
>  	/* quick check if we run Intel */
>  	if (cpu_data(0).x86_vendor != X86_VENDOR_INTEL)
> @@ -450,23 +451,13 @@ static int __init coretemp_init(void)
>  		goto exit;
>  
>  	for_each_online_cpu(i) {
> -		struct cpuinfo_x86 *c = &cpu_data(i);
> +		/* check if the CPU has thermal sensor */
> +		eax = cpuid_eax(0x06);
> +		if (!(eax & 0x01)) {
> +			struct cpuinfo_x86 *c = &cpu_data(i);
>  
> -		/* check if family 6, models 0xe (Pentium M DC),
> -		  0xf (Core 2 DC 65nm), 0x16 (Core 2 SC 65nm),
> -		  0x17 (Penryn 45nm), 0x1a (Nehalem), 0x1c (Atom),
> -		  0x1e (Lynnfield) */
> -		if ((c->cpuid_level < 0) || (c->x86 != 0x6) ||
> -		    !((c->x86_model = 0xe) || (c->x86_model = 0xf) ||
> -			(c->x86_model = 0x16) || (c->x86_model = 0x17) ||
> -			(c->x86_model = 0x1a) || (c->x86_model = 0x1c) ||
> -			(c->x86_model = 0x1e))) {
> -
> -			/* supported CPU not found, but report the unknown
> -			   family 6 CPU */
> -			if ((c->x86 = 0x6) && (c->x86_model > 0xf))
> -				printk(KERN_WARNING DRVNAME ": Unknown CPU "
> -					"model 0x%x\n", c->x86_model);
> +			dev_warn("CPU (model=0x%x) has no thermal sensor!\n",
> +			    c->x86_model);
>  			continue;
>  		}
>  


-- 
Thanks
Huaxu

_______________________________________________
lm-sensors mailing list
lm-sensors@lm-sensors.org
http://lists.lm-sensors.org/mailman/listinfo/lm-sensors

Re: [lm-sensors] [PATCH 1/2] hwmon: (coretemp) Detect the thermal sensors by CPUID

[Huaxu Wan]

On 15:21 Fri 07 May, Carsten Emde wrote:
> Hi Huaxu,
> 
> > The thermal sensors of Intel(R) CPUs can be detected by CPUID instruction,
> > indicated by CPUID.06H.EAX[0].
> Thanks, works great, successfully tested it on an i7 machine.
> 
> I would propose to use dev_warn() instead of printk_once(), since all
> other per-cpu info is also logged this way.
> 
> Signed-off-by: Carsten Emde <C.Emde@osadl.org>
> 

That reminds me that dev_warn is right one on multiple CPU system, especially with different CPUs. Thank you.

> ---
>  drivers/hwmon/coretemp.c |   23 +++++++----------------
>  1 file changed, 7 insertions(+), 16 deletions(-)
> 
> Index: head/drivers/hwmon/coretemp.c
> ===================================================================
> --- head.orig/drivers/hwmon/coretemp.c
> +++ head/drivers/hwmon/coretemp.c
> @@ -440,6 +440,7 @@ static int __init coretemp_init(void)
>  {
>  	int i, err = -ENODEV;
>  	struct pdev_entry *p, *n;
> +	u32 eax;
>  
>  	/* quick check if we run Intel */
>  	if (cpu_data(0).x86_vendor != X86_VENDOR_INTEL)
> @@ -450,23 +451,13 @@ static int __init coretemp_init(void)
>  		goto exit;
>  
>  	for_each_online_cpu(i) {
> -		struct cpuinfo_x86 *c = &cpu_data(i);
> +		/* check if the CPU has thermal sensor */
> +		eax = cpuid_eax(0x06);
> +		if (!(eax & 0x01)) {
> +			struct cpuinfo_x86 *c = &cpu_data(i);
>  
> -		/* check if family 6, models 0xe (Pentium M DC),
> -		  0xf (Core 2 DC 65nm), 0x16 (Core 2 SC 65nm),
> -		  0x17 (Penryn 45nm), 0x1a (Nehalem), 0x1c (Atom),
> -		  0x1e (Lynnfield) */
> -		if ((c->cpuid_level < 0) || (c->x86 != 0x6) ||
> -		    !((c->x86_model == 0xe) || (c->x86_model == 0xf) ||
> -			(c->x86_model == 0x16) || (c->x86_model == 0x17) ||
> -			(c->x86_model == 0x1a) || (c->x86_model == 0x1c) ||
> -			(c->x86_model == 0x1e))) {
> -
> -			/* supported CPU not found, but report the unknown
> -			   family 6 CPU */
> -			if ((c->x86 == 0x6) && (c->x86_model > 0xf))
> -				printk(KERN_WARNING DRVNAME ": Unknown CPU "
> -					"model 0x%x\n", c->x86_model);
> +			dev_warn("CPU (model=0x%x) has no thermal sensor!\n",
> +			    c->x86_model);
>  			continue;
>  		}
>  


-- 
Thanks
Huaxu

[lm-sensors] [PATCH 1/2 V2] hwmon: (coretemp) Detect the thermal

[Huaxu Wan]

The thermal sensors of Intel(R) CPUs can be detected by CPUID instruction,
indicated by CPUID.06H.EAX[0].

Signed-off-by: Huaxu Wan <huaxu.wan@linux.intel.com>
Signed-off-by: Carsten Emde <C.Emde@osadl.org>
---
 drivers/hwmon/coretemp.c |   24 +++++++-----------------
 1 files changed, 7 insertions(+), 17 deletions(-)

diff --git a/drivers/hwmon/coretemp.c b/drivers/hwmon/coretemp.c
index e9b7fbc..d194207 100644
--- a/drivers/hwmon/coretemp.c
+++ b/drivers/hwmon/coretemp.c
@@ -440,6 +440,7 @@ static int __init coretemp_init(void)
 {
 	int i, err = -ENODEV;
 	struct pdev_entry *p, *n;
+	u32 eax;
 
 	/* quick check if we run Intel */
 	if (cpu_data(0).x86_vendor != X86_VENDOR_INTEL)
@@ -450,23 +451,12 @@ static int __init coretemp_init(void)
 		goto exit;
 
 	for_each_online_cpu(i) {
-		struct cpuinfo_x86 *c = &cpu_data(i);
-
-		/* check if family 6, models 0xe (Pentium M DC),
-		  0xf (Core 2 DC 65nm), 0x16 (Core 2 SC 65nm),
-		  0x17 (Penryn 45nm), 0x1a (Nehalem), 0x1c (Atom),
-		  0x1e (Lynnfield) */
-		if ((c->cpuid_level < 0) || (c->x86 != 0x6) ||
-		    !((c->x86_model = 0xe) || (c->x86_model = 0xf) ||
-			(c->x86_model = 0x16) || (c->x86_model = 0x17) ||
-			(c->x86_model = 0x1a) || (c->x86_model = 0x1c) ||
-			(c->x86_model = 0x1e))) {
-
-			/* supported CPU not found, but report the unknown
-			   family 6 CPU */
-			if ((c->x86 = 0x6) && (c->x86_model > 0xf))
-				printk(KERN_WARNING DRVNAME ": Unknown CPU "
-					"model 0x%x\n", c->x86_model);
+ 		/* check if the CPU has thermal sensor */
+ 		eax = cpuid_eax(0x06);
+ 		if (!(eax & 0x01)) {
+ 			struct cpuinfo_x86 *c = &cpu_data(i);
+ 			printk(KERN_WARNING DRVNAME ": CPU (model=0x%x)"
+ 				" has no thermal sensor!\n", c->x86_model);
 			continue;
 		}
 
-- 
1.6.3.3.363.g725cf7


_______________________________________________
lm-sensors mailing list
lm-sensors@lm-sensors.org
http://lists.lm-sensors.org/mailman/listinfo/lm-sensors

[PATCH 1/2 V2] hwmon: (coretemp) Detect the thermal sensors by CPUID

[Huaxu Wan]

The thermal sensors of Intel(R) CPUs can be detected by CPUID instruction,
indicated by CPUID.06H.EAX[0].

Signed-off-by: Huaxu Wan <huaxu.wan@linux.intel.com>
Signed-off-by: Carsten Emde <C.Emde@osadl.org>
---
 drivers/hwmon/coretemp.c |   24 +++++++-----------------
 1 files changed, 7 insertions(+), 17 deletions(-)

diff --git a/drivers/hwmon/coretemp.c b/drivers/hwmon/coretemp.c
index e9b7fbc..d194207 100644
--- a/drivers/hwmon/coretemp.c
+++ b/drivers/hwmon/coretemp.c
@@ -440,6 +440,7 @@ static int __init coretemp_init(void)
 {
 	int i, err = -ENODEV;
 	struct pdev_entry *p, *n;
+	u32 eax;
 
 	/* quick check if we run Intel */
 	if (cpu_data(0).x86_vendor != X86_VENDOR_INTEL)
@@ -450,23 +451,12 @@ static int __init coretemp_init(void)
 		goto exit;
 
 	for_each_online_cpu(i) {
-		struct cpuinfo_x86 *c = &cpu_data(i);
-
-		/* check if family 6, models 0xe (Pentium M DC),
-		  0xf (Core 2 DC 65nm), 0x16 (Core 2 SC 65nm),
-		  0x17 (Penryn 45nm), 0x1a (Nehalem), 0x1c (Atom),
-		  0x1e (Lynnfield) */
-		if ((c->cpuid_level < 0) || (c->x86 != 0x6) ||
-		    !((c->x86_model == 0xe) || (c->x86_model == 0xf) ||
-			(c->x86_model == 0x16) || (c->x86_model == 0x17) ||
-			(c->x86_model == 0x1a) || (c->x86_model == 0x1c) ||
-			(c->x86_model == 0x1e))) {
-
-			/* supported CPU not found, but report the unknown
-			   family 6 CPU */
-			if ((c->x86 == 0x6) && (c->x86_model > 0xf))
-				printk(KERN_WARNING DRVNAME ": Unknown CPU "
-					"model 0x%x\n", c->x86_model);
+ 		/* check if the CPU has thermal sensor */
+ 		eax = cpuid_eax(0x06);
+ 		if (!(eax & 0x01)) {
+ 			struct cpuinfo_x86 *c = &cpu_data(i);
+ 			printk(KERN_WARNING DRVNAME ": CPU (model=0x%x)"
+ 				" has no thermal sensor!\n", c->x86_model);
 			continue;
 		}
 
-- 
1.6.3.3.363.g725cf7

Re: [lm-sensors] [PATCH 1/2 V2] hwmon: (coretemp) Detect the

[Valdis.Kletnieks]

[-- Attachment #1.1: Type: text/plain, Size: 2265 bytes --]

On Mon, 10 May 2010 11:35:25 +0800, Huaxu Wan said:
> 
> The thermal sensors of Intel(R) CPUs can be detected by CPUID instruction,
> indicated by CPUID.06H.EAX[0].
> 
> Signed-off-by: Huaxu Wan <huaxu.wan@linux.intel.com>
> Signed-off-by: Carsten Emde <C.Emde@osadl.org>
> ---
>  drivers/hwmon/coretemp.c |   24 +++++++-----------------
>  1 files changed, 7 insertions(+), 17 deletions(-)
> 
> diff --git a/drivers/hwmon/coretemp.c b/drivers/hwmon/coretemp.c
> index e9b7fbc..d194207 100644
> --- a/drivers/hwmon/coretemp.c
> +++ b/drivers/hwmon/coretemp.c
> @@ -440,6 +440,7 @@ static int __init coretemp_init(void)
>  {
>  	int i, err = -ENODEV;
>  	struct pdev_entry *p, *n;
> +	u32 eax;
>  
>  	/* quick check if we run Intel */
>  	if (cpu_data(0).x86_vendor != X86_VENDOR_INTEL)
> @@ -450,23 +451,12 @@ static int __init coretemp_init(void)
>  		goto exit;
>  
>  	for_each_online_cpu(i) {
> -		struct cpuinfo_x86 *c = &cpu_data(i);
> -
> -		/* check if family 6, models 0xe (Pentium M DC),
> -		  0xf (Core 2 DC 65nm), 0x16 (Core 2 SC 65nm),
> -		  0x17 (Penryn 45nm), 0x1a (Nehalem), 0x1c (Atom),
> -		  0x1e (Lynnfield) */
> -		if ((c->cpuid_level < 0) || (c->x86 != 0x6) ||
> -		    !((c->x86_model == 0xe) || (c->x86_model == 0xf) ||
> -			(c->x86_model == 0x16) || (c->x86_model == 0x17) ||
> -			(c->x86_model == 0x1a) || (c->x86_model == 0x1c) ||
> -			(c->x86_model == 0x1e))) {

So we remove something that checks the CPU level for a model we *expect*
to find a thermal sensor, and only throws a KERN_WARNING if we're on a
model we don't know about...

> + 		/* check if the CPU has thermal sensor */
> + 		eax = cpuid_eax(0x06);
> + 		if (!(eax & 0x01)) {
> + 			struct cpuinfo_x86 *c = &cpu_data(i);
> + 			printk(KERN_WARNING DRVNAME ": CPU (model=0x%x)"
> + 				" has no thermal sensor!\n", c->x86_model);

And replace it with a totally unprotected check that's going to fire off
a KERN_WARNING on every single CPU that Intel ever made that doesn't
include a hardware thermal sensor - including all the family 0-5,
and model < 0x0e hardware.

KERN_WARNING is for "We expected to find the hardware but it's gone off
for a walk on us".  If you wanted to say "Hmm.. this CPU doesn't have one"
you probably wanted KERN_DEBUG or *maybe* KERN_INFO.

[-- Attachment #1.2: Type: application/pgp-signature, Size: 227 bytes --]

[-- Attachment #2: Type: text/plain, Size: 153 bytes --]

_______________________________________________
lm-sensors mailing list
lm-sensors@lm-sensors.org
http://lists.lm-sensors.org/mailman/listinfo/lm-sensors

Re: [PATCH 1/2 V2] hwmon: (coretemp) Detect the thermal sensors by CPUID

[Valdis.Kletnieks]

[-- Attachment #1: Type: text/plain, Size: 2265 bytes --]

On Mon, 10 May 2010 11:35:25 +0800, Huaxu Wan said:
> 
> The thermal sensors of Intel(R) CPUs can be detected by CPUID instruction,
> indicated by CPUID.06H.EAX[0].
> 
> Signed-off-by: Huaxu Wan <huaxu.wan@linux.intel.com>
> Signed-off-by: Carsten Emde <C.Emde@osadl.org>
> ---
>  drivers/hwmon/coretemp.c |   24 +++++++-----------------
>  1 files changed, 7 insertions(+), 17 deletions(-)
> 
> diff --git a/drivers/hwmon/coretemp.c b/drivers/hwmon/coretemp.c
> index e9b7fbc..d194207 100644
> --- a/drivers/hwmon/coretemp.c
> +++ b/drivers/hwmon/coretemp.c
> @@ -440,6 +440,7 @@ static int __init coretemp_init(void)
>  {
>  	int i, err = -ENODEV;
>  	struct pdev_entry *p, *n;
> +	u32 eax;
>  
>  	/* quick check if we run Intel */
>  	if (cpu_data(0).x86_vendor != X86_VENDOR_INTEL)
> @@ -450,23 +451,12 @@ static int __init coretemp_init(void)
>  		goto exit;
>  
>  	for_each_online_cpu(i) {
> -		struct cpuinfo_x86 *c = &cpu_data(i);
> -
> -		/* check if family 6, models 0xe (Pentium M DC),
> -		  0xf (Core 2 DC 65nm), 0x16 (Core 2 SC 65nm),
> -		  0x17 (Penryn 45nm), 0x1a (Nehalem), 0x1c (Atom),
> -		  0x1e (Lynnfield) */
> -		if ((c->cpuid_level < 0) || (c->x86 != 0x6) ||
> -		    !((c->x86_model == 0xe) || (c->x86_model == 0xf) ||
> -			(c->x86_model == 0x16) || (c->x86_model == 0x17) ||
> -			(c->x86_model == 0x1a) || (c->x86_model == 0x1c) ||
> -			(c->x86_model == 0x1e))) {

So we remove something that checks the CPU level for a model we *expect*
to find a thermal sensor, and only throws a KERN_WARNING if we're on a
model we don't know about...

> + 		/* check if the CPU has thermal sensor */
> + 		eax = cpuid_eax(0x06);
> + 		if (!(eax & 0x01)) {
> + 			struct cpuinfo_x86 *c = &cpu_data(i);
> + 			printk(KERN_WARNING DRVNAME ": CPU (model=0x%x)"
> + 				" has no thermal sensor!\n", c->x86_model);

And replace it with a totally unprotected check that's going to fire off
a KERN_WARNING on every single CPU that Intel ever made that doesn't
include a hardware thermal sensor - including all the family 0-5,
and model < 0x0e hardware.

KERN_WARNING is for "We expected to find the hardware but it's gone off
for a walk on us".  If you wanted to say "Hmm.. this CPU doesn't have one"
you probably wanted KERN_DEBUG or *maybe* KERN_INFO.

[-- Attachment #2: Type: application/pgp-signature, Size: 227 bytes --]

Re: [lm-sensors] [PATCH 1/2 V2] hwmon: (coretemp) Detect the

[Huaxu Wan]

On 08:45 Mon 10 May, Valdis.Kletnieks@vt.edu wrote:
> On Mon, 10 May 2010 11:35:25 +0800, Huaxu Wan said:
> > -
> > -		/* check if family 6, models 0xe (Pentium M DC),
> > -		  0xf (Core 2 DC 65nm), 0x16 (Core 2 SC 65nm),
> > -		  0x17 (Penryn 45nm), 0x1a (Nehalem), 0x1c (Atom),
> > -		  0x1e (Lynnfield) */
> > -		if ((c->cpuid_level < 0) || (c->x86 != 0x6) ||
> > -		    !((c->x86_model = 0xe) || (c->x86_model = 0xf) ||
> > -			(c->x86_model = 0x16) || (c->x86_model = 0x17) ||
> > -			(c->x86_model = 0x1a) || (c->x86_model = 0x1c) ||
> > -			(c->x86_model = 0x1e))) {
> 
> So we remove something that checks the CPU level for a model we *expect*
> to find a thermal sensor, and only throws a KERN_WARNING if we're on a
> model we don't know about...
> 
> > + 		/* check if the CPU has thermal sensor */
> > + 		eax = cpuid_eax(0x06);
> > + 		if (!(eax & 0x01)) {
> > + 			struct cpuinfo_x86 *c = &cpu_data(i);
> > + 			printk(KERN_WARNING DRVNAME ": CPU (model=0x%x)"
> > + 				" has no thermal sensor!\n", c->x86_model);
> 
> And replace it with a totally unprotected check that's going to fire off
> a KERN_WARNING on every single CPU that Intel ever made that doesn't
> include a hardware thermal sensor - including all the family 0-5,
> and model < 0x0e hardware.

Oops! That's a bug. Thank you!

> 
> KERN_WARNING is for "We expected to find the hardware but it's gone off
> for a walk on us".  If you wanted to say "Hmm.. this CPU doesn't have one"
> you probably wanted KERN_DEBUG or *maybe* KERN_INFO.

I think the better one is KERN_INFO here. 

-- 
Thanks
Huaxu

_______________________________________________
lm-sensors mailing list
lm-sensors@lm-sensors.org
http://lists.lm-sensors.org/mailman/listinfo/lm-sensors

Re: [PATCH 1/2 V2] hwmon: (coretemp) Detect the thermal sensors by CPUID

[Huaxu Wan]

On 08:45 Mon 10 May, Valdis.Kletnieks@vt.edu wrote:
> On Mon, 10 May 2010 11:35:25 +0800, Huaxu Wan said:
> > -
> > -		/* check if family 6, models 0xe (Pentium M DC),
> > -		  0xf (Core 2 DC 65nm), 0x16 (Core 2 SC 65nm),
> > -		  0x17 (Penryn 45nm), 0x1a (Nehalem), 0x1c (Atom),
> > -		  0x1e (Lynnfield) */
> > -		if ((c->cpuid_level < 0) || (c->x86 != 0x6) ||
> > -		    !((c->x86_model == 0xe) || (c->x86_model == 0xf) ||
> > -			(c->x86_model == 0x16) || (c->x86_model == 0x17) ||
> > -			(c->x86_model == 0x1a) || (c->x86_model == 0x1c) ||
> > -			(c->x86_model == 0x1e))) {
> 
> So we remove something that checks the CPU level for a model we *expect*
> to find a thermal sensor, and only throws a KERN_WARNING if we're on a
> model we don't know about...
> 
> > + 		/* check if the CPU has thermal sensor */
> > + 		eax = cpuid_eax(0x06);
> > + 		if (!(eax & 0x01)) {
> > + 			struct cpuinfo_x86 *c = &cpu_data(i);
> > + 			printk(KERN_WARNING DRVNAME ": CPU (model=0x%x)"
> > + 				" has no thermal sensor!\n", c->x86_model);
> 
> And replace it with a totally unprotected check that's going to fire off
> a KERN_WARNING on every single CPU that Intel ever made that doesn't
> include a hardware thermal sensor - including all the family 0-5,
> and model < 0x0e hardware.

Oops! That's a bug. Thank you!

> 
> KERN_WARNING is for "We expected to find the hardware but it's gone off
> for a walk on us".  If you wanted to say "Hmm.. this CPU doesn't have one"
> you probably wanted KERN_DEBUG or *maybe* KERN_INFO.

I think the better one is KERN_INFO here. 

-- 
Thanks
Huaxu

[lm-sensors] [PATCH 1/2 V3] hwmon: (coretemp) Detect the thermal

[Huaxu Wan]

The thermal sensors of Intel(R) CPUs can be detected by CPUID instruction,
indicated by CPUID.06H.EAX[0].

Signed-off-by: Huaxu Wan <huaxu.wan@linux.intel.com>
Signed-off-by: Carsten Emde <C.Emde@osadl.org>
---
 drivers/hwmon/coretemp.c |   34 +++++++++++++---------------------
 1 files changed, 13 insertions(+), 21 deletions(-)

diff --git a/drivers/hwmon/coretemp.c b/drivers/hwmon/coretemp.c
index e9b7fbc..be0ddcf 100644
--- a/drivers/hwmon/coretemp.c
+++ b/drivers/hwmon/coretemp.c
@@ -451,28 +451,20 @@ static int __init coretemp_init(void)

        for_each_online_cpu(i) {
                struct cpuinfo_x86 *c = &cpu_data(i);
+               /*
+                * CPUID.06H.EAX[0] indicates whether the CPU has thermal
+                * sensors. We check this bit only, all the early CPUs
+                * without thermal sensors will be filtered out.
+                */
+               if (c->cpuid_level >= 6 && (cpuid_eax(0x06) & 0x01)) {
+                       err = coretemp_device_add(i);
+                       if (err)
+                               goto exit_devices_unreg;

-               /* check if family 6, models 0xe (Pentium M DC),
-                 0xf (Core 2 DC 65nm), 0x16 (Core 2 SC 65nm),
-                 0x17 (Penryn 45nm), 0x1a (Nehalem), 0x1c (Atom),
-                 0x1e (Lynnfield) */
-               if ((c->cpuid_level < 0) || (c->x86 != 0x6) ||
-                   !((c->x86_model = 0xe) || (c->x86_model = 0xf) ||
-                       (c->x86_model = 0x16) || (c->x86_model = 0x17) ||
-                       (c->x86_model = 0x1a) || (c->x86_model = 0x1c) ||
-                       (c->x86_model = 0x1e))) {
-
-                       /* supported CPU not found, but report the unknown
-                          family 6 CPU */
-                       if ((c->x86 = 0x6) && (c->x86_model > 0xf))
-                               printk(KERN_WARNING DRVNAME ": Unknown CPU "
-                                       "model 0x%x\n", c->x86_model);
-                       continue;
-               }
-
-               err = coretemp_device_add(i);
-               if (err)
-                       goto exit_devices_unreg;
+               } else {
+                       printk(KERN_INFO DRVNAME ": CPU (model=0x%x)"
+                               " has no thermal sensor!\n", c->x86_model);
+               }
        }
        if (list_empty(&pdev_list)) {
                err = -ENODEV;
--
1.6.3.3.363.g725cf7

_______________________________________________
lm-sensors mailing list
lm-sensors@lm-sensors.org
http://lists.lm-sensors.org/mailman/listinfo/lm-sensors

[PATCH 1/2 V3] hwmon: (coretemp) Detect the thermal sensors by CPUID

[Huaxu Wan]

The thermal sensors of Intel(R) CPUs can be detected by CPUID instruction,
indicated by CPUID.06H.EAX[0].

Signed-off-by: Huaxu Wan <huaxu.wan@linux.intel.com>
Signed-off-by: Carsten Emde <C.Emde@osadl.org>
---
 drivers/hwmon/coretemp.c |   34 +++++++++++++---------------------
 1 files changed, 13 insertions(+), 21 deletions(-)

diff --git a/drivers/hwmon/coretemp.c b/drivers/hwmon/coretemp.c
index e9b7fbc..be0ddcf 100644
--- a/drivers/hwmon/coretemp.c
+++ b/drivers/hwmon/coretemp.c
@@ -451,28 +451,20 @@ static int __init coretemp_init(void)

        for_each_online_cpu(i) {
                struct cpuinfo_x86 *c = &cpu_data(i);
+               /*
+                * CPUID.06H.EAX[0] indicates whether the CPU has thermal
+                * sensors. We check this bit only, all the early CPUs
+                * without thermal sensors will be filtered out.
+                */
+               if (c->cpuid_level >= 6 && (cpuid_eax(0x06) & 0x01)) {
+                       err = coretemp_device_add(i);
+                       if (err)
+                               goto exit_devices_unreg;

-               /* check if family 6, models 0xe (Pentium M DC),
-                 0xf (Core 2 DC 65nm), 0x16 (Core 2 SC 65nm),
-                 0x17 (Penryn 45nm), 0x1a (Nehalem), 0x1c (Atom),
-                 0x1e (Lynnfield) */
-               if ((c->cpuid_level < 0) || (c->x86 != 0x6) ||
-                   !((c->x86_model == 0xe) || (c->x86_model == 0xf) ||
-                       (c->x86_model == 0x16) || (c->x86_model == 0x17) ||
-                       (c->x86_model == 0x1a) || (c->x86_model == 0x1c) ||
-                       (c->x86_model == 0x1e))) {
-
-                       /* supported CPU not found, but report the unknown
-                          family 6 CPU */
-                       if ((c->x86 == 0x6) && (c->x86_model > 0xf))
-                               printk(KERN_WARNING DRVNAME ": Unknown CPU "
-                                       "model 0x%x\n", c->x86_model);
-                       continue;
-               }
-
-               err = coretemp_device_add(i);
-               if (err)
-                       goto exit_devices_unreg;
+               } else {
+                       printk(KERN_INFO DRVNAME ": CPU (model=0x%x)"
+                               " has no thermal sensor!\n", c->x86_model);
+               }
        }
        if (list_empty(&pdev_list)) {
                err = -ENODEV;
--
1.6.3.3.363.g725cf7

Re: [lm-sensors] [PATCH 1/2 V3] hwmon: (coretemp) Detect the

[Valdis.Kletnieks]

[-- Attachment #1.1: Type: text/plain, Size: 1333 bytes --]

On Tue, 11 May 2010 16:01:12 +0800, Huaxu Wan said:
> The thermal sensors of Intel(R) CPUs can be detected by CPUID instruction,
> indicated by CPUID.06H.EAX[0].
> 
> Signed-off-by: Huaxu Wan <huaxu.wan@linux.intel.com>
> Signed-off-by: Carsten Emde <C.Emde@osadl.org>
> ---
>  drivers/hwmon/coretemp.c |   34 +++++++++++++---------------------
>  1 files changed, 13 insertions(+), 21 deletions(-)
> 
> diff --git a/drivers/hwmon/coretemp.c b/drivers/hwmon/coretemp.c
> index e9b7fbc..be0ddcf 100644
> --- a/drivers/hwmon/coretemp.c
> +++ b/drivers/hwmon/coretemp.c
> @@ -451,28 +451,20 @@ static int __init coretemp_init(void)
> 
>         for_each_online_cpu(i) {
>                 struct cpuinfo_x86 *c = &cpu_data(i);
> +               /*
> +                * CPUID.06H.EAX[0] indicates whether the CPU has thermal
> +                * sensors. We check this bit only, all the early CPUs
> +                * without thermal sensors will be filtered out.
> +                */
> +               if (c->cpuid_level >= 6 && (cpuid_eax(0x06) & 0x01)) {
> +                       err = coretemp_device_add(i);
> +                       if (err)
> +                               goto exit_devices_unreg;

OK, that looks sane. :)  For what it's worth, feel free to stick on a

Reviewed-By: Valdis Kletnieks <valdis.kletnieks@vt.edu>

[-- Attachment #1.2: Type: application/pgp-signature, Size: 227 bytes --]

[-- Attachment #2: Type: text/plain, Size: 153 bytes --]

_______________________________________________
lm-sensors mailing list
lm-sensors@lm-sensors.org
http://lists.lm-sensors.org/mailman/listinfo/lm-sensors

Re: [PATCH 1/2 V3] hwmon: (coretemp) Detect the thermal sensors by CPUID

[Valdis.Kletnieks]

[-- Attachment #1: Type: text/plain, Size: 1333 bytes --]

On Tue, 11 May 2010 16:01:12 +0800, Huaxu Wan said:
> The thermal sensors of Intel(R) CPUs can be detected by CPUID instruction,
> indicated by CPUID.06H.EAX[0].
> 
> Signed-off-by: Huaxu Wan <huaxu.wan@linux.intel.com>
> Signed-off-by: Carsten Emde <C.Emde@osadl.org>
> ---
>  drivers/hwmon/coretemp.c |   34 +++++++++++++---------------------
>  1 files changed, 13 insertions(+), 21 deletions(-)
> 
> diff --git a/drivers/hwmon/coretemp.c b/drivers/hwmon/coretemp.c
> index e9b7fbc..be0ddcf 100644
> --- a/drivers/hwmon/coretemp.c
> +++ b/drivers/hwmon/coretemp.c
> @@ -451,28 +451,20 @@ static int __init coretemp_init(void)
> 
>         for_each_online_cpu(i) {
>                 struct cpuinfo_x86 *c = &cpu_data(i);
> +               /*
> +                * CPUID.06H.EAX[0] indicates whether the CPU has thermal
> +                * sensors. We check this bit only, all the early CPUs
> +                * without thermal sensors will be filtered out.
> +                */
> +               if (c->cpuid_level >= 6 && (cpuid_eax(0x06) & 0x01)) {
> +                       err = coretemp_device_add(i);
> +                       if (err)
> +                               goto exit_devices_unreg;

OK, that looks sane. :)  For what it's worth, feel free to stick on a

Reviewed-By: Valdis Kletnieks <valdis.kletnieks@vt.edu>

[-- Attachment #2: Type: application/pgp-signature, Size: 227 bytes --]

Re: [lm-sensors] [PATCH 1/2 V3] hwmon: (coretemp) Detect the

[Henrique de Moraes Holschuh]

On Tue, 11 May 2010, Huaxu Wan wrote:
> +                       printk(KERN_INFO DRVNAME ": CPU (model=0x%x)"
> +                               " has no thermal sensor!\n", c->x86_model);

IMHO, it is better to drop that "!" since it is now a simple status message,
otherwise it still looks like there is something wrong with the CPU not
having a thermal sensor.

Minor thing, really, so feel free to ignore this comment.

-- 
  "One disk to rule them all, One disk to find them. One disk to bring
  them all and in the darkness grind them. In the Land of Redmond
  where the shadows lie." -- The Silicon Valley Tarot
  Henrique Holschuh

_______________________________________________
lm-sensors mailing list
lm-sensors@lm-sensors.org
http://lists.lm-sensors.org/mailman/listinfo/lm-sensors

Re: [lm-sensors] [PATCH 1/2 V3] hwmon: (coretemp) Detect the thermal sensors by CPUID

[Henrique de Moraes Holschuh]

On Tue, 11 May 2010, Huaxu Wan wrote:
> +                       printk(KERN_INFO DRVNAME ": CPU (model=0x%x)"
> +                               " has no thermal sensor!\n", c->x86_model);

IMHO, it is better to drop that "!" since it is now a simple status message,
otherwise it still looks like there is something wrong with the CPU not
having a thermal sensor.

Minor thing, really, so feel free to ignore this comment.

-- 
  "One disk to rule them all, One disk to find them. One disk to bring
  them all and in the darkness grind them. In the Land of Redmond
  where the shadows lie." -- The Silicon Valley Tarot
  Henrique Holschuh

[lm-sensors] [PATCH 1/2 V3 minor change] hwmon: (coretemp) Detect

[Huaxu Wan]

The thermal sensors of Intel(R) CPUs can be detected by CPUID instruction,
indicated by CPUID.06H.EAX[0].

Signed-off-by: Huaxu Wan <huaxu.wan@linux.intel.com>
Signed-off-by: Carsten Emde <C.Emde@osadl.org>
Reviewed-By: Valdis Kletnieks <valdis.kletnieks@vt.edu>
---
 drivers/hwmon/coretemp.c |   34 +++++++++++++---------------------
 1 files changed, 13 insertions(+), 21 deletions(-)

diff --git a/drivers/hwmon/coretemp.c b/drivers/hwmon/coretemp.c
index e9b7fbc..885da2b 100644
--- a/drivers/hwmon/coretemp.c
+++ b/drivers/hwmon/coretemp.c
@@ -451,28 +451,20 @@ static int __init coretemp_init(void)
 
 	for_each_online_cpu(i) {
 		struct cpuinfo_x86 *c = &cpu_data(i);
+ 		/* 
+		 * CPUID.06H.EAX[0] indicates whether the CPU has thermal
+		 * sensors. We check this bit only, all the early CPUs
+		 * without thermal sensors will be filtered out. 
+		 */
+		if (c->cpuid_level >= 6 && (cpuid_eax(0x06) & 0x01)) {
+			err = coretemp_device_add(i);
+			if (err)
+				goto exit_devices_unreg;
 
-		/* check if family 6, models 0xe (Pentium M DC),
-		  0xf (Core 2 DC 65nm), 0x16 (Core 2 SC 65nm),
-		  0x17 (Penryn 45nm), 0x1a (Nehalem), 0x1c (Atom),
-		  0x1e (Lynnfield) */
-		if ((c->cpuid_level < 0) || (c->x86 != 0x6) ||
-		    !((c->x86_model = 0xe) || (c->x86_model = 0xf) ||
-			(c->x86_model = 0x16) || (c->x86_model = 0x17) ||
-			(c->x86_model = 0x1a) || (c->x86_model = 0x1c) ||
-			(c->x86_model = 0x1e))) {
-
-			/* supported CPU not found, but report the unknown
-			   family 6 CPU */
-			if ((c->x86 = 0x6) && (c->x86_model > 0xf))
-				printk(KERN_WARNING DRVNAME ": Unknown CPU "
-					"model 0x%x\n", c->x86_model);
-			continue;
-		}
-
-		err = coretemp_device_add(i);
-		if (err)
-			goto exit_devices_unreg;
+		} else {
+			printk(KERN_INFO DRVNAME ": CPU (model=0x%x)"
+				" has no thermal sensor.\n", c->x86_model);
+		} 
 	}
 	if (list_empty(&pdev_list)) {
 		err = -ENODEV;
-- 
1.6.3.3.363.g725cf7


_______________________________________________
lm-sensors mailing list
lm-sensors@lm-sensors.org
http://lists.lm-sensors.org/mailman/listinfo/lm-sensors

[PATCH 1/2 V3 minor change] hwmon: (coretemp) Detect the thermal sensors by CPUID

[Huaxu Wan]

The thermal sensors of Intel(R) CPUs can be detected by CPUID instruction,
indicated by CPUID.06H.EAX[0].

Signed-off-by: Huaxu Wan <huaxu.wan@linux.intel.com>
Signed-off-by: Carsten Emde <C.Emde@osadl.org>
Reviewed-By: Valdis Kletnieks <valdis.kletnieks@vt.edu>
---
 drivers/hwmon/coretemp.c |   34 +++++++++++++---------------------
 1 files changed, 13 insertions(+), 21 deletions(-)

diff --git a/drivers/hwmon/coretemp.c b/drivers/hwmon/coretemp.c
index e9b7fbc..885da2b 100644
--- a/drivers/hwmon/coretemp.c
+++ b/drivers/hwmon/coretemp.c
@@ -451,28 +451,20 @@ static int __init coretemp_init(void)
 
 	for_each_online_cpu(i) {
 		struct cpuinfo_x86 *c = &cpu_data(i);
+ 		/* 
+		 * CPUID.06H.EAX[0] indicates whether the CPU has thermal
+		 * sensors. We check this bit only, all the early CPUs
+		 * without thermal sensors will be filtered out. 
+		 */
+		if (c->cpuid_level >= 6 && (cpuid_eax(0x06) & 0x01)) {
+			err = coretemp_device_add(i);
+			if (err)
+				goto exit_devices_unreg;
 
-		/* check if family 6, models 0xe (Pentium M DC),
-		  0xf (Core 2 DC 65nm), 0x16 (Core 2 SC 65nm),
-		  0x17 (Penryn 45nm), 0x1a (Nehalem), 0x1c (Atom),
-		  0x1e (Lynnfield) */
-		if ((c->cpuid_level < 0) || (c->x86 != 0x6) ||
-		    !((c->x86_model == 0xe) || (c->x86_model == 0xf) ||
-			(c->x86_model == 0x16) || (c->x86_model == 0x17) ||
-			(c->x86_model == 0x1a) || (c->x86_model == 0x1c) ||
-			(c->x86_model == 0x1e))) {
-
-			/* supported CPU not found, but report the unknown
-			   family 6 CPU */
-			if ((c->x86 == 0x6) && (c->x86_model > 0xf))
-				printk(KERN_WARNING DRVNAME ": Unknown CPU "
-					"model 0x%x\n", c->x86_model);
-			continue;
-		}
-
-		err = coretemp_device_add(i);
-		if (err)
-			goto exit_devices_unreg;
+		} else {
+			printk(KERN_INFO DRVNAME ": CPU (model=0x%x)"
+				" has no thermal sensor.\n", c->x86_model);
+		} 
 	}
 	if (list_empty(&pdev_list)) {
 		err = -ENODEV;
-- 
1.6.3.3.363.g725cf7

[lm-sensors] [PATCH 0/2] hwmon: Update coretemp to current Intel

[Carsten Emde]

Hi!

Here comes the current version of the coretemp patches. Huaxu did the initial
work; Jean suggested to submit them directly to Andrew.

I made some style changes as advised by checkpatch.

The patches have been tested successfully on Core 2 Duo and Quad, and on
Nehalem and Nehalem/Westmere where temperature readings were plausible and
changed with load as expected. When tested on an Atom processor (N270), the
temperature values were identical to previous versions of the coretemp
module and also changed with load. However, the readings should be higher
by 10 to 15C as compared to the outside temperature of the processor. Huaxu,
could you check? I would guess TjMax to be 105 instead of 90C in these
processors.

        Carsten.


_______________________________________________
lm-sensors mailing list
lm-sensors@lm-sensors.org
http://lists.lm-sensors.org/mailman/listinfo/lm-sensors

[PATCH 0/2] hwmon: Update coretemp to current Intel processors

[Carsten Emde]

Hi!

Here comes the current version of the coretemp patches. Huaxu did the initial
work; Jean suggested to submit them directly to Andrew.

I made some style changes as advised by checkpatch.

The patches have been tested successfully on Core 2 Duo and Quad, and on
Nehalem and Nehalem/Westmere where temperature readings were plausible and
changed with load as expected. When tested on an Atom processor (N270), the
temperature values were identical to previous versions of the coretemp
module and also changed with load. However, the readings should be higher
by 10 to 15C as compared to the outside temperature of the processor. Huaxu,
could you check? I would guess TjMax to be 105 instead of 90C in these
processors.

        Carsten.

[lm-sensors] [PATCH 1/2] Detect the thermal sensors by CPUID

[Carsten Emde]

The thermal sensors of Intel(R) CPUs can be detected by CPUID instruction,
indicated by CPUID.06H.EAX[0].

CC: Andrew Morton <akpm@linux-foundation.org>
CC: Jean Delvare <khali@linux-fr.org>
CC: Henrique de Moraes Holschuh <hmh@hmh.eng.br>
Signed-off-by: Huaxu Wan <huaxu.wan@linux.intel.com>
Signed-off-by: Carsten Emde <C.Emde@osadl.org>
Reviewed-By: Valdis Kletnieks <valdis.kletnieks@vt.edu>

---
 drivers/hwmon/coretemp.c |   34 +++++++++++++---------------------
 1 file changed, 13 insertions(+), 21 deletions(-)

Index: head/drivers/hwmon/coretemp.c
=================================--- head.orig/drivers/hwmon/coretemp.c
+++ head/drivers/hwmon/coretemp.c
@@ -451,28 +451,20 @@ static int __init coretemp_init(void)
 
 	for_each_online_cpu(i) {
 		struct cpuinfo_x86 *c = &cpu_data(i);
-
-		/* check if family 6, models 0xe (Pentium M DC),
-		  0xf (Core 2 DC 65nm), 0x16 (Core 2 SC 65nm),
-		  0x17 (Penryn 45nm), 0x1a (Nehalem), 0x1c (Atom),
-		  0x1e (Lynnfield) */
-		if ((c->cpuid_level < 0) || (c->x86 != 0x6) ||
-		    !((c->x86_model = 0xe) || (c->x86_model = 0xf) ||
-			(c->x86_model = 0x16) || (c->x86_model = 0x17) ||
-			(c->x86_model = 0x1a) || (c->x86_model = 0x1c) ||
-			(c->x86_model = 0x1e))) {
-
-			/* supported CPU not found, but report the unknown
-			   family 6 CPU */
-			if ((c->x86 = 0x6) && (c->x86_model > 0xf))
-				printk(KERN_WARNING DRVNAME ": Unknown CPU "
-					"model 0x%x\n", c->x86_model);
-			continue;
+		/*
+		 * CPUID.06H.EAX[0] indicates whether the CPU has thermal
+		 * sensors. We check this bit only, all the early CPUs
+		 * without thermal sensors will be filtered out.
+		 */
+		if (c->cpuid_level >= 6 && (cpuid_eax(0x06) & 0x01)) {
+			err = coretemp_device_add(i);
+			if (err)
+				goto exit_devices_unreg;
+
+		} else {
+			printk(KERN_INFO DRVNAME ": CPU (model=0x%x)"
+				" has no thermal sensor.\n", c->x86_model);
 		}
-
-		err = coretemp_device_add(i);
-		if (err)
-			goto exit_devices_unreg;
 	}
 	if (list_empty(&pdev_list)) {
 		err = -ENODEV;


_______________________________________________
lm-sensors mailing list
lm-sensors@lm-sensors.org
http://lists.lm-sensors.org/mailman/listinfo/lm-sensors

[PATCH 1/2] Detect the thermal sensors by CPUID

[Carsten Emde]

[-- Attachment #1: coretemp-simplify-intel-thermal-sensor-recognition.patch --]
[-- Type: text/plain, Size: 2062 bytes --]

The thermal sensors of Intel(R) CPUs can be detected by CPUID instruction,
indicated by CPUID.06H.EAX[0].

CC: Andrew Morton <akpm@linux-foundation.org>
CC: Jean Delvare <khali@linux-fr.org>
CC: Henrique de Moraes Holschuh <hmh@hmh.eng.br>
Signed-off-by: Huaxu Wan <huaxu.wan@linux.intel.com>
Signed-off-by: Carsten Emde <C.Emde@osadl.org>
Reviewed-By: Valdis Kletnieks <valdis.kletnieks@vt.edu>

---
 drivers/hwmon/coretemp.c |   34 +++++++++++++---------------------
 1 file changed, 13 insertions(+), 21 deletions(-)

Index: head/drivers/hwmon/coretemp.c
===================================================================
--- head.orig/drivers/hwmon/coretemp.c
+++ head/drivers/hwmon/coretemp.c
@@ -451,28 +451,20 @@ static int __init coretemp_init(void)
 
 	for_each_online_cpu(i) {
 		struct cpuinfo_x86 *c = &cpu_data(i);
-
-		/* check if family 6, models 0xe (Pentium M DC),
-		  0xf (Core 2 DC 65nm), 0x16 (Core 2 SC 65nm),
-		  0x17 (Penryn 45nm), 0x1a (Nehalem), 0x1c (Atom),
-		  0x1e (Lynnfield) */
-		if ((c->cpuid_level < 0) || (c->x86 != 0x6) ||
-		    !((c->x86_model == 0xe) || (c->x86_model == 0xf) ||
-			(c->x86_model == 0x16) || (c->x86_model == 0x17) ||
-			(c->x86_model == 0x1a) || (c->x86_model == 0x1c) ||
-			(c->x86_model == 0x1e))) {
-
-			/* supported CPU not found, but report the unknown
-			   family 6 CPU */
-			if ((c->x86 == 0x6) && (c->x86_model > 0xf))
-				printk(KERN_WARNING DRVNAME ": Unknown CPU "
-					"model 0x%x\n", c->x86_model);
-			continue;
+		/*
+		 * CPUID.06H.EAX[0] indicates whether the CPU has thermal
+		 * sensors. We check this bit only, all the early CPUs
+		 * without thermal sensors will be filtered out.
+		 */
+		if (c->cpuid_level >= 6 && (cpuid_eax(0x06) & 0x01)) {
+			err = coretemp_device_add(i);
+			if (err)
+				goto exit_devices_unreg;
+
+		} else {
+			printk(KERN_INFO DRVNAME ": CPU (model=0x%x)"
+				" has no thermal sensor.\n", c->x86_model);
 		}
-
-		err = coretemp_device_add(i);
-		if (err)
-			goto exit_devices_unreg;
 	}
 	if (list_empty(&pdev_list)) {
 		err = -ENODEV;

[lm-sensors] [PATCH 2/2] Get TjMax value from MSR

[Carsten Emde]

The MSR IA32_TEMPERATURE_TARGET contains the TjMax value in the newer
Intel processors.

CC: Andrew Morton <akpm@linux-foundation.org>
CC: Jean Delvare <khali@linux-fr.org>
Signed-off-by: Huaxu Wan <huaxu.wan@linux.intel.com>
Signed-off-by: Carsten Emde <C.Emde@osadl.org>

---
 arch/x86/include/asm/msr-index.h |    2 +
 drivers/hwmon/coretemp.c         |   61 ++++++++++++++++++++++++++++++++++++---
 2 files changed, 59 insertions(+), 4 deletions(-)

Index: head/arch/x86/include/asm/msr-index.h
=================================--- head.orig/arch/x86/include/asm/msr-index.h
+++ head/arch/x86/include/asm/msr-index.h
@@ -235,6 +235,8 @@
 
 #define MSR_IA32_MISC_ENABLE		0x000001a0
 
+#define MSR_IA32_TEMPERATURE_TARGET	0x000001a2
+
 /* MISC_ENABLE bits: architectural */
 #define MSR_IA32_MISC_ENABLE_FAST_STRING	(1ULL << 0)
 #define MSR_IA32_MISC_ENABLE_TCC		(1ULL << 1)
Index: head/drivers/hwmon/coretemp.c
=================================--- head.orig/drivers/hwmon/coretemp.c
+++ head/drivers/hwmon/coretemp.c
@@ -241,6 +241,55 @@ static int __devinit adjust_tjmax(struct
 	return tjmax;
 }
 
+static int __devinit get_tjmax(struct cpuinfo_x86 *c, u32 id,
+			       struct device *dev)
+{
+	/* The 100C is default for both mobile and non mobile CPUs */
+	int err;
+	u32 eax, edx;
+	u32 val;
+
+	/* A new feature of current Intel(R) processors, the
+	   IA32_TEMPERATURE_TARGET contains the TjMax value */
+	err = rdmsr_safe_on_cpu(id, MSR_IA32_TEMPERATURE_TARGET, &eax, &edx);
+	if (err) {
+		dev_warn(dev, "Unable to read TjMax from CPU.\n");
+	} else {
+		val = (eax >> 16) & 0xff;
+		/*
+		 * If the TjMax is not plausible, an assumption
+		 * will be used
+		 */
+		if ((val > 80) && (val < 120)) {
+			dev_info(dev, "TjMax is %d C.\n", val);
+			return val * 1000;
+		}
+	}
+
+	/*
+	 * An assumption is made for early CPUs and unreadable MSR.
+	 * NOTE: the given value may not be correct.
+	 */
+
+	switch (c->x86_model) {
+	case 0xe:
+	case 0xf:
+	case 0x16:
+	case 0x1a:
+		dev_warn(dev, "TjMax is assumed as 100 C!\n");
+		return 100000;
+		break;
+	case 0x17:
+	case 0x1c:		/* Atom CPUs */
+		return adjust_tjmax(c, id, dev);
+		break;
+	default:
+		dev_warn(dev, "CPU (model=0x%x) is not supported yet,"
+			" using default TjMax of 100C.\n", c->x86_model);
+		return 100000;
+	}
+}
+
 static int __devinit coretemp_probe(struct platform_device *pdev)
 {
 	struct coretemp_data *data;
@@ -283,14 +332,18 @@ static int __devinit coretemp_probe(stru
 		}
 	}
 
-	data->tjmax = adjust_tjmax(c, data->id, &pdev->dev);
+	data->tjmax = get_tjmax(c, data->id, &pdev->dev);
 	platform_set_drvdata(pdev, data);
 
-	/* read the still undocumented IA32_TEMPERATURE_TARGET it exists
-	   on older CPUs but not in this register, Atoms don't have it either */
+	/*
+	 * read the still undocumented IA32_TEMPERATURE_TARGET. It exists
+	 * on older CPUs but not in this register,
+	 * Atoms don't have it either.
+	 */
 
 	if ((c->x86_model > 0xe) && (c->x86_model != 0x1c)) {
-		err = rdmsr_safe_on_cpu(data->id, 0x1a2, &eax, &edx);
+		err = rdmsr_safe_on_cpu(data->id, MSR_IA32_TEMPERATURE_TARGET,
+		    &eax, &edx);
 		if (err) {
 			dev_warn(&pdev->dev, "Unable to read"
 					" IA32_TEMPERATURE_TARGET MSR\n");


_______________________________________________
lm-sensors mailing list
lm-sensors@lm-sensors.org
http://lists.lm-sensors.org/mailman/listinfo/lm-sensors

[PATCH 2/2] Get TjMax value from MSR

[Carsten Emde]

[-- Attachment #1: coretemp-add-tjmax-method-for-i-series-processors.patch --]
[-- Type: text/plain, Size: 3294 bytes --]

The MSR IA32_TEMPERATURE_TARGET contains the TjMax value in the newer
Intel processors.

CC: Andrew Morton <akpm@linux-foundation.org>
CC: Jean Delvare <khali@linux-fr.org>
Signed-off-by: Huaxu Wan <huaxu.wan@linux.intel.com>
Signed-off-by: Carsten Emde <C.Emde@osadl.org>

---
 arch/x86/include/asm/msr-index.h |    2 +
 drivers/hwmon/coretemp.c         |   61 ++++++++++++++++++++++++++++++++++++---
 2 files changed, 59 insertions(+), 4 deletions(-)

Index: head/arch/x86/include/asm/msr-index.h
===================================================================
--- head.orig/arch/x86/include/asm/msr-index.h
+++ head/arch/x86/include/asm/msr-index.h
@@ -235,6 +235,8 @@
 
 #define MSR_IA32_MISC_ENABLE		0x000001a0
 
+#define MSR_IA32_TEMPERATURE_TARGET	0x000001a2
+
 /* MISC_ENABLE bits: architectural */
 #define MSR_IA32_MISC_ENABLE_FAST_STRING	(1ULL << 0)
 #define MSR_IA32_MISC_ENABLE_TCC		(1ULL << 1)
Index: head/drivers/hwmon/coretemp.c
===================================================================
--- head.orig/drivers/hwmon/coretemp.c
+++ head/drivers/hwmon/coretemp.c
@@ -241,6 +241,55 @@ static int __devinit adjust_tjmax(struct
 	return tjmax;
 }
 
+static int __devinit get_tjmax(struct cpuinfo_x86 *c, u32 id,
+			       struct device *dev)
+{
+	/* The 100C is default for both mobile and non mobile CPUs */
+	int err;
+	u32 eax, edx;
+	u32 val;
+
+	/* A new feature of current Intel(R) processors, the
+	   IA32_TEMPERATURE_TARGET contains the TjMax value */
+	err = rdmsr_safe_on_cpu(id, MSR_IA32_TEMPERATURE_TARGET, &eax, &edx);
+	if (err) {
+		dev_warn(dev, "Unable to read TjMax from CPU.\n");
+	} else {
+		val = (eax >> 16) & 0xff;
+		/*
+		 * If the TjMax is not plausible, an assumption
+		 * will be used
+		 */
+		if ((val > 80) && (val < 120)) {
+			dev_info(dev, "TjMax is %d C.\n", val);
+			return val * 1000;
+		}
+	}
+
+	/*
+	 * An assumption is made for early CPUs and unreadable MSR.
+	 * NOTE: the given value may not be correct.
+	 */
+
+	switch (c->x86_model) {
+	case 0xe:
+	case 0xf:
+	case 0x16:
+	case 0x1a:
+		dev_warn(dev, "TjMax is assumed as 100 C!\n");
+		return 100000;
+		break;
+	case 0x17:
+	case 0x1c:		/* Atom CPUs */
+		return adjust_tjmax(c, id, dev);
+		break;
+	default:
+		dev_warn(dev, "CPU (model=0x%x) is not supported yet,"
+			" using default TjMax of 100C.\n", c->x86_model);
+		return 100000;
+	}
+}
+
 static int __devinit coretemp_probe(struct platform_device *pdev)
 {
 	struct coretemp_data *data;
@@ -283,14 +332,18 @@ static int __devinit coretemp_probe(stru
 		}
 	}
 
-	data->tjmax = adjust_tjmax(c, data->id, &pdev->dev);
+	data->tjmax = get_tjmax(c, data->id, &pdev->dev);
 	platform_set_drvdata(pdev, data);
 
-	/* read the still undocumented IA32_TEMPERATURE_TARGET it exists
-	   on older CPUs but not in this register, Atoms don't have it either */
+	/*
+	 * read the still undocumented IA32_TEMPERATURE_TARGET. It exists
+	 * on older CPUs but not in this register,
+	 * Atoms don't have it either.
+	 */
 
 	if ((c->x86_model > 0xe) && (c->x86_model != 0x1c)) {
-		err = rdmsr_safe_on_cpu(data->id, 0x1a2, &eax, &edx);
+		err = rdmsr_safe_on_cpu(data->id, MSR_IA32_TEMPERATURE_TARGET,
+		    &eax, &edx);
 		if (err) {
 			dev_warn(&pdev->dev, "Unable to read"
 					" IA32_TEMPERATURE_TARGET MSR\n");

Re: [lm-sensors] [PATCH 0/2] hwmon: Update coretemp to current

[Dmitry Gromov]

[-- Attachment #1.1: Type: text/plain, Size: 1019 bytes --]

Hi!

On Mon, May 17, 2010 at 05:41, Carsten Emde <C.Emde@osadl.org> wrote:

> Hi!
>
> Here comes the current version of the coretemp patches. Huaxu did the
> initial
> work; Jean suggested to submit them directly to Andrew.
>
> I made some style changes as advised by checkpatch.
>
> The patches have been tested successfully on Core 2 Duo and Quad, and on
> Nehalem and Nehalem/Westmere where temperature readings were plausible and
> changed with load as expected. When tested on an Atom processor (N270), the
> temperature values were identical to previous versions of the coretemp
> module and also changed with load. However, the readings should be higher
> by 10 to 15C as compared to the outside temperature of the processor.
> Huaxu,
> could you check? I would guess TjMax to be 105 instead of 90C in these
> processors.
>
>
I apologize, if I ask a stupid question, but are you saying that TjMax in
coretemp.c should be set to higher value than Tcase-max value specified in
Intel documents?

Thanks!

-- 
DG
NJ

[-- Attachment #1.2: Type: text/html, Size: 1446 bytes --]

[-- Attachment #2: Type: text/plain, Size: 153 bytes --]

_______________________________________________
lm-sensors mailing list
lm-sensors@lm-sensors.org
http://lists.lm-sensors.org/mailman/listinfo/lm-sensors

Re: [lm-sensors] [PATCH 0/2] hwmon: Update coretemp to current

[Carsten Emde]

Dmitry,

>> Here comes the current version of the coretemp patches. Huaxu did the
>> initial work; Jean suggested to submit them directly to Andrew.
>>
>> I made some style changes as advised by checkpatch.
>>
>> The patches have been tested successfully on Core 2 Duo and Quad, and on
>> Nehalem and Nehalem/Westmere where temperature readings were plausible and
>> changed with load as expected. When tested on an Atom processor (N270), the
>> temperature values were identical to previous versions of the coretemp
>> module and also changed with load. However, the readings should be higher
>> by 10 to 15C as compared to the outside temperature of the processor.
>> Huaxu, could you check? I would guess TjMax to be 105 instead of 90C in these
>> processors.
> I apologize, if I ask a stupid question, but are you saying that TjMax in
> coretemp.c should be set to higher value than Tcase-max value specified in
> Intel documents?
Hmm, no. I am saying that I would like the reading to be correct. I have 
measured the outside temperature of the case with an infrared 
thermometer [1] and found it to be higher than the readings returned by 
the coretemp module. In all other CPUs I have, the coretemp readings are 
higher than the case temperature.

	Carsten.


[1] http://www.osadl.org/uploads/media/IPCworld-2008-4.pdf

_______________________________________________
lm-sensors mailing list
lm-sensors@lm-sensors.org
http://lists.lm-sensors.org/mailman/listinfo/lm-sensors

Re: [lm-sensors] [PATCH 0/2] hwmon: Update coretemp to current Intel processors

[Carsten Emde]

Dmitry,

>> Here comes the current version of the coretemp patches. Huaxu did the
>> initial work; Jean suggested to submit them directly to Andrew.
>>
>> I made some style changes as advised by checkpatch.
>>
>> The patches have been tested successfully on Core 2 Duo and Quad, and on
>> Nehalem and Nehalem/Westmere where temperature readings were plausible and
>> changed with load as expected. When tested on an Atom processor (N270), the
>> temperature values were identical to previous versions of the coretemp
>> module and also changed with load. However, the readings should be higher
>> by 10 to 15C as compared to the outside temperature of the processor.
>> Huaxu, could you check? I would guess TjMax to be 105 instead of 90C in these
>> processors.
> I apologize, if I ask a stupid question, but are you saying that TjMax in
> coretemp.c should be set to higher value than Tcase-max value specified in
> Intel documents?
Hmm, no. I am saying that I would like the reading to be correct. I have 
measured the outside temperature of the case with an infrared 
thermometer [1] and found it to be higher than the readings returned by 
the coretemp module. In all other CPUs I have, the coretemp readings are 
higher than the case temperature.

	Carsten.


[1] http://www.osadl.org/uploads/media/IPCworld-2008-4.pdf

Re: [lm-sensors] [PATCH 0/2] hwmon: Update coretemp to current

[Dmitry Gromov]

Hi!

On Tue, May 18, 2010 at 03:01, Carsten Emde <C.Emde@osadl.org> wrote:
> Dmitry,
>
>>> Here comes the current version of the coretemp patches. Huaxu did the
>>> initial work; Jean suggested to submit them directly to Andrew.
>>>
>>> I made some style changes as advised by checkpatch.
>>>
>>> The patches have been tested successfully on Core 2 Duo and Quad, and on
>>> Nehalem and Nehalem/Westmere where temperature readings were plausible
>>> and
>>> changed with load as expected. When tested on an Atom processor (N270),
>>> the
>>> temperature values were identical to previous versions of the coretemp
>>> module and also changed with load. However, the readings should be higher
>>> by 10 to 15C as compared to the outside temperature of the processor.
>>> Huaxu, could you check? I would guess TjMax to be 105 instead of 90C in
>>> these
>>> processors.
>>
>> I apologize, if I ask a stupid question, but are you saying that TjMax in
>> coretemp.c should be set to higher value than Tcase-max value specified in
>> Intel documents?
>
> Hmm, no. I am saying that I would like the reading to be correct. I have
> measured the outside temperature of the case with an infrared thermometer
> [1] and found it to be higher than the readings returned by the coretemp
> module. In all other CPUs I have, the coretemp readings are higher than the
> case temperature.
>

Thank you very much for an explanation, Carsten.


-- 
DG
NJ

_______________________________________________
lm-sensors mailing list
lm-sensors@lm-sensors.org
http://lists.lm-sensors.org/mailman/listinfo/lm-sensors

Re: [lm-sensors] [PATCH 0/2] hwmon: Update coretemp to current Intel processors

[Dmitry Gromov]

Hi!

On Tue, May 18, 2010 at 03:01, Carsten Emde <C.Emde@osadl.org> wrote:
> Dmitry,
>
>>> Here comes the current version of the coretemp patches. Huaxu did the
>>> initial work; Jean suggested to submit them directly to Andrew.
>>>
>>> I made some style changes as advised by checkpatch.
>>>
>>> The patches have been tested successfully on Core 2 Duo and Quad, and on
>>> Nehalem and Nehalem/Westmere where temperature readings were plausible
>>> and
>>> changed with load as expected. When tested on an Atom processor (N270),
>>> the
>>> temperature values were identical to previous versions of the coretemp
>>> module and also changed with load. However, the readings should be higher
>>> by 10 to 15C as compared to the outside temperature of the processor.
>>> Huaxu, could you check? I would guess TjMax to be 105 instead of 90C in
>>> these
>>> processors.
>>
>> I apologize, if I ask a stupid question, but are you saying that TjMax in
>> coretemp.c should be set to higher value than Tcase-max value specified in
>> Intel documents?
>
> Hmm, no. I am saying that I would like the reading to be correct. I have
> measured the outside temperature of the case with an infrared thermometer
> [1] and found it to be higher than the readings returned by the coretemp
> module. In all other CPUs I have, the coretemp readings are higher than the
> case temperature.
>

Thank you very much for an explanation, Carsten.


-- 
DG
NJ

Re: [lm-sensors] [PATCH 0/2] hwmon: Update coretemp to current

[Huaxu Wan]

On 09:01 Tue 18 May, Carsten Emde wrote:
> Dmitry,
> 
> >>Here comes the current version of the coretemp patches. Huaxu did the
> >>initial work; Jean suggested to submit them directly to Andrew.
> >>
> >>I made some style changes as advised by checkpatch.
> >>
> >>The patches have been tested successfully on Core 2 Duo and Quad, and on
> >>Nehalem and Nehalem/Westmere where temperature readings were plausible and
> >>changed with load as expected. When tested on an Atom processor (N270), the
> >>temperature values were identical to previous versions of the coretemp
> >>module and also changed with load. However, the readings should be higher
> >>by 10 to 15C as compared to the outside temperature of the processor.
> >>Huaxu, could you check? I would guess TjMax to be 105 instead of 90C in these
> >>processors.
> >I apologize, if I ask a stupid question, but are you saying that TjMax in
> >coretemp.c should be set to higher value than Tcase-max value specified in
> >Intel documents?
> Hmm, no. I am saying that I would like the reading to be correct. I
> have measured the outside temperature of the case with an infrared
> thermometer [1] and found it to be higher than the readings returned
> by the coretemp module. In all other CPUs I have, the coretemp
> readings are higher than the case temperature.
> 
> [1] http://www.osadl.org/uploads/media/IPCworld-2008-4.pdf
> 

Hi Carsten,

I have no N270 and infrared thermometer in hand, so I can't check it by myself.
I'll find a channel and file this issue to them. 

Thank you.


Huaxu

_______________________________________________
lm-sensors mailing list
lm-sensors@lm-sensors.org
http://lists.lm-sensors.org/mailman/listinfo/lm-sensors

Re: [lm-sensors] [PATCH 0/2] hwmon: Update coretemp to current Intel processors

[Huaxu Wan]

On 09:01 Tue 18 May, Carsten Emde wrote:
> Dmitry,
> 
> >>Here comes the current version of the coretemp patches. Huaxu did the
> >>initial work; Jean suggested to submit them directly to Andrew.
> >>
> >>I made some style changes as advised by checkpatch.
> >>
> >>The patches have been tested successfully on Core 2 Duo and Quad, and on
> >>Nehalem and Nehalem/Westmere where temperature readings were plausible and
> >>changed with load as expected. When tested on an Atom processor (N270), the
> >>temperature values were identical to previous versions of the coretemp
> >>module and also changed with load. However, the readings should be higher
> >>by 10 to 15C as compared to the outside temperature of the processor.
> >>Huaxu, could you check? I would guess TjMax to be 105 instead of 90C in these
> >>processors.
> >I apologize, if I ask a stupid question, but are you saying that TjMax in
> >coretemp.c should be set to higher value than Tcase-max value specified in
> >Intel documents?
> Hmm, no. I am saying that I would like the reading to be correct. I
> have measured the outside temperature of the case with an infrared
> thermometer [1] and found it to be higher than the readings returned
> by the coretemp module. In all other CPUs I have, the coretemp
> readings are higher than the case temperature.
> 
> [1] http://www.osadl.org/uploads/media/IPCworld-2008-4.pdf
> 

Hi Carsten,

I have no N270 and infrared thermometer in hand, so I can't check it by myself.
I'll find a channel and file this issue to them. 

Thank you.


Huaxu

Re: [lm-sensors] [PATCH 0/2] hwmon: Update coretemp to current

[Wan, Huaxu]

[-- Attachment #2: Type: text/plain, Size: 1562 bytes --]

Hi,

The TjMax of N270 is 90C, according the official documents [1][2].

.
[1]http://ark.intel.com/Product.aspx?id=36331&processor=N270&spec-codes=SLB73
[2]http://download.intel.com/design/processor/datashts/319977.pdf

Thanks
Huaxu

________________________________
From: Dmitry Gromov [mailto:gromovd@gmail.com]
Sent: Tuesday, May 18, 2010 12:48 PM
To: Carsten Emde
Cc: Andrew Morton; LKML; LM Sensors; Wan, Huaxu
Subject: Re: [lm-sensors] [PATCH 0/2] hwmon: Update coretemp to current Intel processors

Hi!

On Mon, May 17, 2010 at 05:41, Carsten Emde <C.Emde@osadl.org<mailto:C.Emde@osadl.org>> wrote:
Hi!

Here comes the current version of the coretemp patches. Huaxu did the initial
work; Jean suggested to submit them directly to Andrew.

I made some style changes as advised by checkpatch.

The patches have been tested successfully on Core 2 Duo and Quad, and on
Nehalem and Nehalem/Westmere where temperature readings were plausible and
changed with load as expected. When tested on an Atom processor (N270), the
temperature values were identical to previous versions of the coretemp
module and also changed with load. However, the readings should be higher
by 10 to 15C as compared to the outside temperature of the processor. Huaxu,
could you check? I would guess TjMax to be 105 instead of 90C in these
processors.


I apologize, if I ask a stupid question, but are you saying that TjMax in coretemp.c should be set to higher value than Tcase-max value specified in Intel documents?

Thanks!

--
DG
NJ


[-- Attachment #3: Type: text/html, Size: 2846 bytes --]

Re: [lm-sensors] [PATCH 0/2] hwmon: Update coretemp to current

[Dmitry Gromov]

[-- Attachment #1.1: Type: text/plain, Size: 811 bytes --]

Hi!

On Tue, May 18, 2010 at 01:07, Wan, Huaxu <huaxu.wan@intel.com> wrote:

>  Hi,
>
> The TjMax of N270 is 90C, according the official documents [1][2].
>
> .
> [1]
> http://ark.intel.com/Product.aspx?id=36331&processor=N270&spec-codes=SLB73
> [2]http://download.intel.com/design/processor/datashts/319977.pdf
>
> Thanks
> Huaxu
>
> Thank you, this is exactly why I;m asking. I think, "guessing" values here
can be dangerous - who knows what critical apps they will relied upon.

And 90C seems to be good for N200 series of Atom CPUs only - I could not
find TjMax value published for N330 Dual Core  (quite popular one). Intel
only published Tcase for it:
http://ark.intel.com/Product.aspx?id=35641
So, if for N270 Tcase = TjMax = 90C, then, I'd suggest to use Tcase = 85.2C
for N330 TjMax value.


-- 
DG
NJ

[-- Attachment #1.2: Type: text/html, Size: 1804 bytes --]

[-- Attachment #2: Type: text/plain, Size: 153 bytes --]

_______________________________________________
lm-sensors mailing list
lm-sensors@lm-sensors.org
http://lists.lm-sensors.org/mailman/listinfo/lm-sensors

Re: [lm-sensors] [PATCH 0/2] hwmon: Update coretemp to current

[Carsten Emde]

On 05/18/2010 08:45 AM, Dmitry Gromov wrote:
> On Tue, May 18, 2010 at 01:07, Wan, Huaxu<huaxu.wan@intel.com>  wrote:
>> The TjMax of N270 is 90C, according the official documents [1][2].
>> [1] http://ark.intel.com/Product.aspx?id6331&processor=N270&spec-codes=SLB73
>> [2] http://download.intel.com/design/processor/datashts/319977.pdf
>> Thank you, this is exactly why I'm asking. I think, "guessing" values here
> can be dangerous - who knows what critical apps they will relied upon.
Yes, of course. I never wanted to use a guessed and not documented
value. I only wanted the temperature reading to be plausible.

> And 90C seems to be good for N200 series of Atom CPUs only - I could not
> find TjMax value published for N330 Dual Core  (quite popular one). Intel
> only published Tcase for it:
> http://ark.intel.com/Product.aspx?id5641
> So, if for N270 Tcase = TjMax = 90C, then, I'd suggest to use Tcase = 85.2C
> for N330 TjMax value.
They have the same CPU model ID:

# grep model /proc/cpuinfo
model		: 28
model name	: Intel(R) Atom(TM) CPU N270   @ 1.60GHz

# grep model /proc/cpuinfo
model		: 28
model name	: Intel(R) Atom(TM) CPU  330   @ 1.60GHz

I would like to propose to use the patch as it is. It's the best
version we ever had.

	Carsten.

_______________________________________________
lm-sensors mailing list
lm-sensors@lm-sensors.org
http://lists.lm-sensors.org/mailman/listinfo/lm-sensors

Re: [lm-sensors] [PATCH 0/2] hwmon: Update coretemp to current Intel processors

[Carsten Emde]

On 05/18/2010 08:45 AM, Dmitry Gromov wrote:
> On Tue, May 18, 2010 at 01:07, Wan, Huaxu<huaxu.wan@intel.com>  wrote:
>> The TjMax of N270 is 90C, according the official documents [1][2].
>> [1] http://ark.intel.com/Product.aspx?id=36331&processor=N270&spec-codes=SLB73
>> [2] http://download.intel.com/design/processor/datashts/319977.pdf
>> Thank you, this is exactly why I'm asking. I think, "guessing" values here
> can be dangerous - who knows what critical apps they will relied upon.
Yes, of course. I never wanted to use a guessed and not documented
value. I only wanted the temperature reading to be plausible.

> And 90C seems to be good for N200 series of Atom CPUs only - I could not
> find TjMax value published for N330 Dual Core  (quite popular one). Intel
> only published Tcase for it:
> http://ark.intel.com/Product.aspx?id=35641
> So, if for N270 Tcase = TjMax = 90C, then, I'd suggest to use Tcase = 85.2C
> for N330 TjMax value.
They have the same CPU model ID:

# grep model /proc/cpuinfo
model		: 28
model name	: Intel(R) Atom(TM) CPU N270   @ 1.60GHz

# grep model /proc/cpuinfo
model		: 28
model name	: Intel(R) Atom(TM) CPU  330   @ 1.60GHz

I would like to propose to use the patch as it is. It's the best
version we ever had.

	Carsten.

Re: [lm-sensors] [PATCH 0/2] hwmon: Update coretemp to current

[Huaxu Wan]

On 02:45 Tue 18 May, Dmitry Gromov wrote:
> Hi!
> 
> And 90C seems to be good for N200 series of Atom CPUs only - I could not
> find TjMax value published for N330 Dual Core  (quite popular one). Intel
> only published Tcase for it:
> http://ark.intel.com/Product.aspx?id5641
> So, if for N270 Tcase = TjMax = 90C, then, I'd suggest to use Tcase = 85.2C
> for N330 TjMax value.

Quoted a sentence from [1], "Unless specified otherwise, all specifications for 
the processor are at TJ = 90°C", I believe the TjMax of 330 is 90C too.

[1]http://download.intel.com/design/processor/datashts/320528.pdf

Thanks
Huaxu

_______________________________________________
lm-sensors mailing list
lm-sensors@lm-sensors.org
http://lists.lm-sensors.org/mailman/listinfo/lm-sensors

Re: [lm-sensors] [PATCH 0/2] hwmon: Update coretemp to current Intel processors

[Huaxu Wan]

On 02:45 Tue 18 May, Dmitry Gromov wrote:
> Hi!
> 
> And 90C seems to be good for N200 series of Atom CPUs only - I could not
> find TjMax value published for N330 Dual Core  (quite popular one). Intel
> only published Tcase for it:
> http://ark.intel.com/Product.aspx?id=35641
> So, if for N270 Tcase = TjMax = 90C, then, I'd suggest to use Tcase = 85.2C
> for N330 TjMax value.

Quoted a sentence from [1], "Unless specified otherwise, all specifications for 
the processor are at TJ = 90°C", I believe the TjMax of 330 is 90C too.

[1]http://download.intel.com/design/processor/datashts/320528.pdf

Thanks
Huaxu

Re: [lm-sensors] [PATCH 0/2] hwmon: Update coretemp to current

[Dmitry Gromov]

Hi!

On Tue, May 18, 2010 at 20:50, Huaxu Wan <huaxu.wan@linux.intel.com> wrote:
> On 02:45 Tue 18 May, Dmitry Gromov wrote:
>> Hi!
>>
>> And 90C seems to be good for N200 series of Atom CPUs only - I could not
>> find TjMax value published for N330 Dual Core  (quite popular one). Intel
>> only published Tcase for it:
>> http://ark.intel.com/Product.aspx?id5641
>> So, if for N270 Tcase = TjMax = 90C, then, I'd suggest to use Tcase = 85.2C
>> for N330 TjMax value.
>
> Quoted a sentence from [1], "Unless specified otherwise, all specifications for
> the processor are at TJ = 90°C", I believe the TjMax of 330 is 90C too.
>

Well, that refers for the values in that specific table and entire
document (which I went through as well) does not specify TjMax :(
Similar document for N270 series does specify TjMax explicitly in Table 14:
http://download.intel.com/design/processor/datashts/320032.pdf

Another document, "Thermal and Mechanical Design Guidelines" for Atom
300 series:
http://download.intel.com/design/processor/designex/320530.pdf
specifies Tcase-max = 85.2C
Thinking about this a bit, I think Tcase-max should be lower than
TjMax, which probably is still 90C.
The document itself is a good reading too.

Anyway, thank you very much for your help, Huaxu!

-- 
DG
NJ

_______________________________________________
lm-sensors mailing list
lm-sensors@lm-sensors.org
http://lists.lm-sensors.org/mailman/listinfo/lm-sensors

Re: [lm-sensors] [PATCH 0/2] hwmon: Update coretemp to current Intel processors

[Dmitry Gromov]

Hi!

On Tue, May 18, 2010 at 20:50, Huaxu Wan <huaxu.wan@linux.intel.com> wrote:
> On 02:45 Tue 18 May, Dmitry Gromov wrote:
>> Hi!
>>
>> And 90C seems to be good for N200 series of Atom CPUs only - I could not
>> find TjMax value published for N330 Dual Core  (quite popular one). Intel
>> only published Tcase for it:
>> http://ark.intel.com/Product.aspx?id=35641
>> So, if for N270 Tcase = TjMax = 90C, then, I'd suggest to use Tcase = 85.2C
>> for N330 TjMax value.
>
> Quoted a sentence from [1], "Unless specified otherwise, all specifications for
> the processor are at TJ = 90°C", I believe the TjMax of 330 is 90C too.
>

Well, that refers for the values in that specific table and entire
document (which I went through as well) does not specify TjMax :(
Similar document for N270 series does specify TjMax explicitly in Table 14:
http://download.intel.com/design/processor/datashts/320032.pdf

Another document, "Thermal and Mechanical Design Guidelines" for Atom
300 series:
http://download.intel.com/design/processor/designex/320530.pdf
specifies Tcase-max = 85.2C
Thinking about this a bit, I think Tcase-max should be lower than
TjMax, which probably is still 90C.
The document itself is a good reading too.

Anyway, thank you very much for your help, Huaxu!

-- 
DG
NJ

[lm-sensors] [PATCH 2/2] hwmon: (coretemp) Get TjMax value from MSR

[Huaxu Wan]

The MSR IA32_TEMPERATURE_TARGET contains the TjMax value after the i series
processers.

Signed-off-by: Huaxu Wan <huaxu.wan@intel.com>
---
 drivers/hwmon/coretemp.c |   46 +++++++++++++++++++++++++++++++++++++++++++++-
 1 files changed, 45 insertions(+), 1 deletions(-)

diff --git a/drivers/hwmon/coretemp.c b/drivers/hwmon/coretemp.c
index 55122d8..6039ea5 100644
--- a/drivers/hwmon/coretemp.c
+++ b/drivers/hwmon/coretemp.c
@@ -241,6 +241,50 @@ static int __devinit adjust_tjmax(struct cpuinfo_x86 *c, u32 id, struct device *
 	return tjmax;
 }
 
+static int __devinit get_tjmax(struct cpuinfo_x86 *c, u32 id, struct device *dev)
+{
+	/* The 100C is default for both mobile and non mobile CPUs */
+	int err;
+	u32 eax, edx;
+	u32 val;
+
+	/* A new feature in the i series processors, the 
+	   IA32_TEMPERATURE_TARGET contains the TjMax value */
+	err = rdmsr_safe_on_cpu(id, 0x1a2, &eax, &edx);
+	if (err){
+		printk_once(KERN_WARNING DRVNAME  " : Unable to read TjMax from CPU, an"
+			" assumption value is used! \n");
+	} else {
+		val = (eax >> 16 ) & 0xff;
+		/* If the TjMax is not reasonable, an assumption value 
+		   will be used */
+		if (( val > 80) && (val < 120)){
+			printk_once(KERN_WARNING DRVNAME " : The TjMax is %d\n C", val);
+			return val * 1000;
+		}
+	}
+
+	/* For the early CPUs, an approximation is given.
+	 NOTE: the given value may not be correct. */
+	switch(c->x86_model){
+	case 0xe :
+	case 0xf :
+	case 0x16 :
+	case 0x1a :
+		printk_once(KERN_WARNING DRVNAME  " : TjMax is assumed as 100 C! \n");
+		return 100000;
+		break;
+	case 0x17 :
+	case 0x1c :		/* Atom CPUs */
+		return adjust_tjmax(c, id, dev);
+		break;
+	default :
+		printk_once(KERN_WARNING DRVNAME " : Your CPU is not support yet,"
+			"using the default TjMax: 100 C.\n");
+		return 100000;
+	}
+}
+
 static int __devinit coretemp_probe(struct platform_device *pdev)
 {
 	struct coretemp_data *data;
@@ -283,7 +327,7 @@ static int __devinit coretemp_probe(struct platform_device *pdev)
 		}
 	}
 
-	data->tjmax = adjust_tjmax(c, data->id, &pdev->dev);
+	data->tjmax = get_tjmax(c, data->id, &pdev->dev);
 	platform_set_drvdata(pdev, data);
 
 	/* read the still undocumented IA32_TEMPERATURE_TARGET it exists
-- 
1.6.3.3.363.g725cf7


_______________________________________________
lm-sensors mailing list
lm-sensors@lm-sensors.org
http://lists.lm-sensors.org/mailman/listinfo/lm-sensors

Re: [lm-sensors] [PATCH 2/2] hwmon: (coretemp) Get TjMax value from

[Luca Tettamanti]

On Fri, Mar 5, 2010 at 4:38 PM, Huaxu Wan <huaxu.wan@linux.intel.com> wrote:
> The MSR IA32_TEMPERATURE_TARGET contains the TjMax value after the i series
> processers.
[...]
> +               printk_once(KERN_WARNING DRVNAME  " : Unable to read TjMax from CPU, an"
> +                       " assumption value is used! \n");
[...]
> +       } else {
> +               val = (eax >> 16 ) & 0xff;
> +               /* If the TjMax is not reasonable, an assumption value

Hi,
I'm not a native speaker but "assumption value" doesn't seem correct to me.
"assumed value" maybe? Or even better (IMHO) "default value"?

Luca

_______________________________________________
lm-sensors mailing list
lm-sensors@lm-sensors.org
http://lists.lm-sensors.org/mailman/listinfo/lm-sensors

Re: [lm-sensors] [PATCH 2/2] hwmon: (coretemp) Get TjMax value from

[Huaxu Wan]

On 17:19 Fri 05 Mar, Luca Tettamanti wrote:
> 
> Hi,
> I'm not a native speaker but "assumption value" doesn't seem correct to me.
> "assumed value" maybe? Or even better (IMHO) "default value"?
> 

I meant the TjMax value may not be correct, the "default value" may mislead
the user into thinking it is correct. I googled the "assumption value", and
found they are used in some sentences, so I use them too :P


Hi Jean,

Do you have any comments on the two patches? I'll make another patch to
update documents if they are accepted.


Thanks
Huaxu

_______________________________________________
lm-sensors mailing list
lm-sensors@lm-sensors.org
http://lists.lm-sensors.org/mailman/listinfo/lm-sensors

[lm-sensors] [PATCH 2/2] hwmon: (coretemp) Get TjMax value from MSR

[Huaxu Wan]

The MSR IA32_TEMPERATURE_TARGET contains the TjMax value in the newer
processers.

Signed-off-by: Huaxu Wan <huaxu.wan@linux.intel.com>
---
 drivers/hwmon/coretemp.c |   45 ++++++++++++++++++++++++++++++++++++++++++++-
 1 files changed, 44 insertions(+), 1 deletions(-)

diff --git a/drivers/hwmon/coretemp.c b/drivers/hwmon/coretemp.c
index 237c68d..7a01032 100644
--- a/drivers/hwmon/coretemp.c
+++ b/drivers/hwmon/coretemp.c
@@ -241,6 +241,49 @@ static int __devinit adjust_tjmax(struct cpuinfo_x86 *c, u32 id, struct device *
        return tjmax;
 }

+static int __devinit get_tjmax(struct cpuinfo_x86 *c, u32 id, struct device *dev)
+{
+       /* The 100C is default for both mobile and non mobile CPUs */
+       int err;
+       u32 eax, edx;
+       u32 val;
+
+       /* A new feature of current Intel(R) processors, the
+          IA32_TEMPERATURE_TARGET(0x1a2) contains the TjMax value */
+       err = rdmsr_safe_on_cpu(id, 0x1a2, &eax, &edx);
+       if (err){
+               printk_once(KERN_WARNING DRVNAME  " : Unable to read TjMax from CPU.\n");
+       } else {
+               val = (eax >> 16 ) & 0xff;
+               /* If the TjMax is not reasonable, an assumption value
+                  will be used */
+               if (( val > 80) && (val < 120)){
+                       printk_once(KERN_INFO DRVNAME " : The TjMax is %d C. \n", val);
+                       return val * 1000;
+               }
+       }
+
+       /* For the early CPUs, an approximation is given.
+        NOTE: the given value may not be correct. */
+       switch(c->x86_model){
+       case 0xe :
+       case 0xf :
+       case 0x16 :
+       case 0x1a :
+               printk_once(KERN_WARNING DRVNAME  " : TjMax is assumed as 100 C! \n");
+               return 100000;
+               break;
+       case 0x17 :
+       case 0x1c :             /* Atom CPUs */
+               return adjust_tjmax(c, id, dev);
+               break;
+       default :
+               printk_once(KERN_WARNING DRVNAME " : Your CPU is not support yet,"
+                       "using the default TjMax: 100 C.\n");
+               return 100000;
+       }
+}
+
 static int __devinit coretemp_probe(struct platform_device *pdev)
 {
        struct coretemp_data *data;
@@ -283,7 +326,7 @@ static int __devinit coretemp_probe(struct platform_device *pdev)
                }
        }

-       data->tjmax = adjust_tjmax(c, data->id, &pdev->dev);
+       data->tjmax = get_tjmax(c, data->id, &pdev->dev);
        platform_set_drvdata(pdev, data);

        /* read the still undocumented IA32_TEMPERATURE_TARGET it exists
--
1.6.3.3.363.g725cf7

_______________________________________________
lm-sensors mailing list
lm-sensors@lm-sensors.org
http://lists.lm-sensors.org/mailman/listinfo/lm-sensors

[PATCH 2/2] hwmon: (coretemp) Get TjMax value from MSR

[Huaxu Wan]

The MSR IA32_TEMPERATURE_TARGET contains the TjMax value in the newer
processers.

Signed-off-by: Huaxu Wan <huaxu.wan@linux.intel.com>
---
 drivers/hwmon/coretemp.c |   45 ++++++++++++++++++++++++++++++++++++++++++++-
 1 files changed, 44 insertions(+), 1 deletions(-)

diff --git a/drivers/hwmon/coretemp.c b/drivers/hwmon/coretemp.c
index 237c68d..7a01032 100644
--- a/drivers/hwmon/coretemp.c
+++ b/drivers/hwmon/coretemp.c
@@ -241,6 +241,49 @@ static int __devinit adjust_tjmax(struct cpuinfo_x86 *c, u32 id, struct device *
        return tjmax;
 }

+static int __devinit get_tjmax(struct cpuinfo_x86 *c, u32 id, struct device *dev)
+{
+       /* The 100C is default for both mobile and non mobile CPUs */
+       int err;
+       u32 eax, edx;
+       u32 val;
+
+       /* A new feature of current Intel(R) processors, the
+          IA32_TEMPERATURE_TARGET(0x1a2) contains the TjMax value */
+       err = rdmsr_safe_on_cpu(id, 0x1a2, &eax, &edx);
+       if (err){
+               printk_once(KERN_WARNING DRVNAME  " : Unable to read TjMax from CPU.\n");
+       } else {
+               val = (eax >> 16 ) & 0xff;
+               /* If the TjMax is not reasonable, an assumption value
+                  will be used */
+               if (( val > 80) && (val < 120)){
+                       printk_once(KERN_INFO DRVNAME " : The TjMax is %d C. \n", val);
+                       return val * 1000;
+               }
+       }
+
+       /* For the early CPUs, an approximation is given.
+        NOTE: the given value may not be correct. */
+       switch(c->x86_model){
+       case 0xe :
+       case 0xf :
+       case 0x16 :
+       case 0x1a :
+               printk_once(KERN_WARNING DRVNAME  " : TjMax is assumed as 100 C! \n");
+               return 100000;
+               break;
+       case 0x17 :
+       case 0x1c :             /* Atom CPUs */
+               return adjust_tjmax(c, id, dev);
+               break;
+       default :
+               printk_once(KERN_WARNING DRVNAME " : Your CPU is not support yet,"
+                       "using the default TjMax: 100 C.\n");
+               return 100000;
+       }
+}
+
 static int __devinit coretemp_probe(struct platform_device *pdev)
 {
        struct coretemp_data *data;
@@ -283,7 +326,7 @@ static int __devinit coretemp_probe(struct platform_device *pdev)
                }
        }

-       data->tjmax = adjust_tjmax(c, data->id, &pdev->dev);
+       data->tjmax = get_tjmax(c, data->id, &pdev->dev);
        platform_set_drvdata(pdev, data);

        /* read the still undocumented IA32_TEMPERATURE_TARGET it exists
--
1.6.3.3.363.g725cf7

Re: [lm-sensors] [PATCH 2/2] hwmon: (coretemp) Get TjMax value from

[Carsten Emde]

[-- Attachment #1: Type: text/plain, Size: 435 bytes --]

Hi Huaxu,

> The MSR IA32_TEMPERATURE_TARGET contains the TjMax value in the newer
> processers.
I took the liberty to make some very minor changes to your patch:
- Unified and adapted messages and comments
- Added a definition of MSR_IA32_TEMPERATURE_TARGET to the arch header
- Replaced 0x1a2 by MSR_IA32_TEMPERATURE_TARGET
- Applied changes suggested by checkpatch

Hope you like it.

Signed-off-by: Carsten Emde <C.Emde@osadl.org>

[-- Attachment #2: coretemp-add-tjmax-method-for-i-series-processors.patch --]
[-- Type: text/x-patch, Size: 3105 bytes --]

---
 arch/x86/include/asm/msr-index.h |    3 ++
 drivers/hwmon/coretemp.c         |   54 ++++++++++++++++++++++++++++++++++++---
 2 files changed, 53 insertions(+), 4 deletions(-)

Index: head/arch/x86/include/asm/msr-index.h
===================================================================
--- head.orig/arch/x86/include/asm/msr-index.h
+++ head/arch/x86/include/asm/msr-index.h
@@ -277,6 +277,9 @@
 #define MSR_IA32_MCG_EIP		0x00000189
 #define MSR_IA32_MCG_RESERVED		0x0000018a
 
+/* Specific to i series processors */
+#define MSR_IA32_TEMPERATURE_TARGET	0x000001a2
+
 /* Pentium IV performance counter MSRs */
 #define MSR_P4_BPU_PERFCTR0		0x00000300
 #define MSR_P4_BPU_PERFCTR1		0x00000301
Index: head/drivers/hwmon/coretemp.c
===================================================================
--- head.orig/drivers/hwmon/coretemp.c
+++ head/drivers/hwmon/coretemp.c
@@ -153,7 +153,8 @@ static struct coretemp_data *coretemp_up
 	return data;
 }
 
-static int __devinit adjust_tjmax(struct cpuinfo_x86 *c, u32 id, struct device *dev)
+static int __devinit adjust_tjmax(struct cpuinfo_x86 *c, u32 id,
+				  struct device *dev)
 {
 	/* The 100C is default for both mobile and non mobile CPUs */
 
@@ -241,6 +242,51 @@ static int __devinit adjust_tjmax(struct
 	return tjmax;
 }
 
+static int __devinit get_tjmax(struct cpuinfo_x86 *c, u32 id,
+			       struct device *dev)
+{
+	int err;
+	u32 eax, edx;
+	u32 val;
+
+	err = rdmsr_safe_on_cpu(id, MSR_IA32_TEMPERATURE_TARGET, &eax, &edx);
+	if (err)
+		dev_warn(dev, "Unable to read TjMax from CPU.\n");
+	else {
+		val = (eax >> 16) & 0xff;
+		if (val > 80 && val < 120) {
+			dev_info(dev, "TjMax is %dC.\n", val);
+			return val * 1000;
+		} else {
+			dev_warn(dev, "TjMax of %dC not plausible,"
+			    " using 100C instead." , val);
+			return 100000;
+		}
+	}
+
+	/*
+	 * An assumption is made for early CPUs and unreadable MSR.
+	 * NOTE: the given value may not be correct.
+	 */
+	switch (c->x86_model) {
+	case 0x0e:
+	case 0x0f:
+	case 0x16:
+	case 0x1a:
+		dev_warn(dev, "TjMax is assumed as 100C!\n");
+		return 100000;
+		break;
+	case 0x17:
+	case 0x1c: /* Atom CPUs */
+		return adjust_tjmax(c, id, dev);
+		break;
+	default:
+		dev_warn(dev, "CPU (model=0x%x) is not supported yet,"
+		    " using default TjMax of 100C.\n", c->x86_model);
+		return 100000;
+	}
+}
+
 static int __devinit coretemp_probe(struct platform_device *pdev)
 {
 	struct coretemp_data *data;
@@ -283,14 +329,14 @@ static int __devinit coretemp_probe(stru
 		}
 	}
 
-	data->tjmax = adjust_tjmax(c, data->id, &pdev->dev);
+	data->tjmax = get_tjmax(c, data->id, &pdev->dev);
 	platform_set_drvdata(pdev, data);
 
 	/* read the still undocumented IA32_TEMPERATURE_TARGET it exists
 	   on older CPUs but not in this register, Atoms don't have it either */
-
 	if ((c->x86_model > 0xe) && (c->x86_model != 0x1c)) {
-		err = rdmsr_safe_on_cpu(data->id, 0x1a2, &eax, &edx);
+		err = rdmsr_safe_on_cpu(data->id, MSR_IA32_TEMPERATURE_TARGET,
+		     &eax, &edx);
 		if (err) {
 			dev_warn(&pdev->dev, "Unable to read"
 					" IA32_TEMPERATURE_TARGET MSR\n");

[-- Attachment #3: Type: text/plain, Size: 153 bytes --]

_______________________________________________
lm-sensors mailing list
lm-sensors@lm-sensors.org
http://lists.lm-sensors.org/mailman/listinfo/lm-sensors

Re: [lm-sensors] [PATCH 2/2] hwmon: (coretemp) Get TjMax value from MSR

[Carsten Emde]

[-- Attachment #1: Type: text/plain, Size: 435 bytes --]

Hi Huaxu,

> The MSR IA32_TEMPERATURE_TARGET contains the TjMax value in the newer
> processers.
I took the liberty to make some very minor changes to your patch:
- Unified and adapted messages and comments
- Added a definition of MSR_IA32_TEMPERATURE_TARGET to the arch header
- Replaced 0x1a2 by MSR_IA32_TEMPERATURE_TARGET
- Applied changes suggested by checkpatch

Hope you like it.

Signed-off-by: Carsten Emde <C.Emde@osadl.org>

[-- Attachment #2: coretemp-add-tjmax-method-for-i-series-processors.patch --]
[-- Type: text/x-patch, Size: 3105 bytes --]

---
 arch/x86/include/asm/msr-index.h |    3 ++
 drivers/hwmon/coretemp.c         |   54 ++++++++++++++++++++++++++++++++++++---
 2 files changed, 53 insertions(+), 4 deletions(-)

Index: head/arch/x86/include/asm/msr-index.h
===================================================================
--- head.orig/arch/x86/include/asm/msr-index.h
+++ head/arch/x86/include/asm/msr-index.h
@@ -277,6 +277,9 @@
 #define MSR_IA32_MCG_EIP		0x00000189
 #define MSR_IA32_MCG_RESERVED		0x0000018a
 
+/* Specific to i series processors */
+#define MSR_IA32_TEMPERATURE_TARGET	0x000001a2
+
 /* Pentium IV performance counter MSRs */
 #define MSR_P4_BPU_PERFCTR0		0x00000300
 #define MSR_P4_BPU_PERFCTR1		0x00000301
Index: head/drivers/hwmon/coretemp.c
===================================================================
--- head.orig/drivers/hwmon/coretemp.c
+++ head/drivers/hwmon/coretemp.c
@@ -153,7 +153,8 @@ static struct coretemp_data *coretemp_up
 	return data;
 }
 
-static int __devinit adjust_tjmax(struct cpuinfo_x86 *c, u32 id, struct device *dev)
+static int __devinit adjust_tjmax(struct cpuinfo_x86 *c, u32 id,
+				  struct device *dev)
 {
 	/* The 100C is default for both mobile and non mobile CPUs */
 
@@ -241,6 +242,51 @@ static int __devinit adjust_tjmax(struct
 	return tjmax;
 }
 
+static int __devinit get_tjmax(struct cpuinfo_x86 *c, u32 id,
+			       struct device *dev)
+{
+	int err;
+	u32 eax, edx;
+	u32 val;
+
+	err = rdmsr_safe_on_cpu(id, MSR_IA32_TEMPERATURE_TARGET, &eax, &edx);
+	if (err)
+		dev_warn(dev, "Unable to read TjMax from CPU.\n");
+	else {
+		val = (eax >> 16) & 0xff;
+		if (val > 80 && val < 120) {
+			dev_info(dev, "TjMax is %dC.\n", val);
+			return val * 1000;
+		} else {
+			dev_warn(dev, "TjMax of %dC not plausible,"
+			    " using 100C instead." , val);
+			return 100000;
+		}
+	}
+
+	/*
+	 * An assumption is made for early CPUs and unreadable MSR.
+	 * NOTE: the given value may not be correct.
+	 */
+	switch (c->x86_model) {
+	case 0x0e:
+	case 0x0f:
+	case 0x16:
+	case 0x1a:
+		dev_warn(dev, "TjMax is assumed as 100C!\n");
+		return 100000;
+		break;
+	case 0x17:
+	case 0x1c: /* Atom CPUs */
+		return adjust_tjmax(c, id, dev);
+		break;
+	default:
+		dev_warn(dev, "CPU (model=0x%x) is not supported yet,"
+		    " using default TjMax of 100C.\n", c->x86_model);
+		return 100000;
+	}
+}
+
 static int __devinit coretemp_probe(struct platform_device *pdev)
 {
 	struct coretemp_data *data;
@@ -283,14 +329,14 @@ static int __devinit coretemp_probe(stru
 		}
 	}
 
-	data->tjmax = adjust_tjmax(c, data->id, &pdev->dev);
+	data->tjmax = get_tjmax(c, data->id, &pdev->dev);
 	platform_set_drvdata(pdev, data);
 
 	/* read the still undocumented IA32_TEMPERATURE_TARGET it exists
 	   on older CPUs but not in this register, Atoms don't have it either */
-
 	if ((c->x86_model > 0xe) && (c->x86_model != 0x1c)) {
-		err = rdmsr_safe_on_cpu(data->id, 0x1a2, &eax, &edx);
+		err = rdmsr_safe_on_cpu(data->id, MSR_IA32_TEMPERATURE_TARGET,
+		     &eax, &edx);
 		if (err) {
 			dev_warn(&pdev->dev, "Unable to read"
 					" IA32_TEMPERATURE_TARGET MSR\n");

Re: [lm-sensors] [PATCH 2/2] hwmon: (coretemp) Get TjMax value from

[Huaxu Wan]

On 15:29 Fri 07 May, Carsten Emde wrote:

> +	err = rdmsr_safe_on_cpu(id, MSR_IA32_TEMPERATURE_TARGET, &eax, &edx);
> +	if (err)
> +		dev_warn(dev, "Unable to read TjMax from CPU.\n");
> +	else {
> +		val = (eax >> 16) & 0xff;
> +		if (val > 80 && val < 120) {
> +			dev_info(dev, "TjMax is %dC.\n", val);
> +			return val * 1000;
> +		} else {
> +			dev_warn(dev, "TjMax of %dC not plausible,"
> +			    " using 100C instead." , val);
> +			return 100000;
> +		}
> +	}

The CPU, in the following case switch, may return no err at the above rdmsr. The
val is 0 with CPU model 0x0f in my test. The function should not return when
(val > 80 && val < 120) is false. 

> +
> +	/*
> +	 * An assumption is made for early CPUs and unreadable MSR.
> +	 * NOTE: the given value may not be correct.
> +	 */
> +	switch (c->x86_model) {
> +	case 0x0e:
> +	case 0x0f:
> +	case 0x16:
> +	case 0x1a:
> +		dev_warn(dev, "TjMax is assumed as 100C!\n");
> +		return 100000;
> +		break;
> +	case 0x17:
> +	case 0x1c: /* Atom CPUs */
> +		return adjust_tjmax(c, id, dev);
> +		break;
> +	default:
> +		dev_warn(dev, "CPU (model=0x%x) is not supported yet,"
> +		    " using default TjMax of 100C.\n", c->x86_model);
> +		return 100000;
> +	}
> +}

-- 
Thanks
Huaxu

_______________________________________________
lm-sensors mailing list
lm-sensors@lm-sensors.org
http://lists.lm-sensors.org/mailman/listinfo/lm-sensors

Re: [lm-sensors] [PATCH 2/2] hwmon: (coretemp) Get TjMax value from MSR

[Huaxu Wan]

On 15:29 Fri 07 May, Carsten Emde wrote:

> +	err = rdmsr_safe_on_cpu(id, MSR_IA32_TEMPERATURE_TARGET, &eax, &edx);
> +	if (err)
> +		dev_warn(dev, "Unable to read TjMax from CPU.\n");
> +	else {
> +		val = (eax >> 16) & 0xff;
> +		if (val > 80 && val < 120) {
> +			dev_info(dev, "TjMax is %dC.\n", val);
> +			return val * 1000;
> +		} else {
> +			dev_warn(dev, "TjMax of %dC not plausible,"
> +			    " using 100C instead." , val);
> +			return 100000;
> +		}
> +	}

The CPU, in the following case switch, may return no err at the above rdmsr. The
val is 0 with CPU model 0x0f in my test. The function should not return when
(val > 80 && val < 120) is false. 

> +
> +	/*
> +	 * An assumption is made for early CPUs and unreadable MSR.
> +	 * NOTE: the given value may not be correct.
> +	 */
> +	switch (c->x86_model) {
> +	case 0x0e:
> +	case 0x0f:
> +	case 0x16:
> +	case 0x1a:
> +		dev_warn(dev, "TjMax is assumed as 100C!\n");
> +		return 100000;
> +		break;
> +	case 0x17:
> +	case 0x1c: /* Atom CPUs */
> +		return adjust_tjmax(c, id, dev);
> +		break;
> +	default:
> +		dev_warn(dev, "CPU (model=0x%x) is not supported yet,"
> +		    " using default TjMax of 100C.\n", c->x86_model);
> +		return 100000;
> +	}
> +}

-- 
Thanks
Huaxu

[lm-sensors] [PATCH 2/2 V2] hwmon: (coretemp) Get TjMax value from

[Huaxu Wan]

The MSR IA32_TEMPERATURE_TARGET contains the TjMax value in the newer
processers.

Signed-off-by: Huaxu Wan <huaxu.wan@linux.intel.com>
Signed-off-by: Carsten Emde <C.Emde@osadl.org>
---
 arch/x86/include/asm/msr-index.h |    2 +
 drivers/hwmon/coretemp.c         |   52 ++++++++++++++++++++++++++++++++++++-
 2 files changed, 52 insertions(+), 2 deletions(-)

diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index 4604e6a..9bc0cf8 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -232,6 +232,8 @@
 
 #define MSR_IA32_MISC_ENABLE		0x000001a0
 
+#define MSR_IA32_TEMPERATURE_TARGET	0x000001a2
+
 /* MISC_ENABLE bits: architectural */
 #define MSR_IA32_MISC_ENABLE_FAST_STRING	(1ULL << 0)
 #define MSR_IA32_MISC_ENABLE_TCC		(1ULL << 1)
diff --git a/drivers/hwmon/coretemp.c b/drivers/hwmon/coretemp.c
index d194207..9959390 100644
--- a/drivers/hwmon/coretemp.c
+++ b/drivers/hwmon/coretemp.c
@@ -241,6 +241,54 @@ static int __devinit adjust_tjmax(struct cpuinfo_x86 *c, u32 id, struct device *
 	return tjmax;
 }
 
+static int __devinit get_tjmax(struct cpuinfo_x86 *c, u32 id, struct device *dev)
+{
+	/* The 100C is default for both mobile and non mobile CPUs */
+	int err;
+	u32 eax, edx;
+	u32 val;
+
+	/* A new feature of current Intel(R) processors, the
+	   IA32_TEMPERATURE_TARGET contains the TjMax value */
+	err = rdmsr_safe_on_cpu(id, MSR_IA32_TEMPERATURE_TARGET, &eax, &edx);
+	if (err){
+		dev_warn(dev, "Unable to read TjMax from CPU.\n");
+	} else {
+		val = (eax >> 16 ) & 0xff;
+		/*
+		 * If the TjMax is not plausible, an assumption
+		 * will be used
+		 */
+		if (( val > 80) && (val < 120)){
+			dev_info(dev, "TjMax is %d C. \n", val);
+			return val * 1000;
+		}
+	}
+
+	/*
+	 * An assumption is made for early CPUs and unreadable MSR.
+	 * NOTE: the given value may not be correct.
+	 */
+
+	switch(c->x86_model){
+	case 0xe :
+	case 0xf :
+	case 0x16 :
+	case 0x1a :
+		dev_warn(dev, "TjMax is assumed as 100 C! \n");
+		return 100000;
+		break;
+	case 0x17 :
+	case 0x1c :		/* Atom CPUs */
+		return adjust_tjmax(c, id, dev);
+		break;
+	default :
+		dev_warn(dev, "CPU (model=0x%x) is not supported yet,"
+			" using default TjMax of 100C.\n", c->x86_model);
+		return 100000;
+	}
+}
+
 static int __devinit coretemp_probe(struct platform_device *pdev)
 {
 	struct coretemp_data *data;
@@ -283,14 +331,14 @@ static int __devinit coretemp_probe(struct platform_device *pdev)
 		}
 	}
 
-	data->tjmax = adjust_tjmax(c, data->id, &pdev->dev);
+	data->tjmax = get_tjmax(c, data->id, &pdev->dev);
 	platform_set_drvdata(pdev, data);
 
 	/* read the still undocumented IA32_TEMPERATURE_TARGET it exists
 	   on older CPUs but not in this register, Atoms don't have it either */
 
 	if ((c->x86_model > 0xe) && (c->x86_model != 0x1c)) {
-		err = rdmsr_safe_on_cpu(data->id, 0x1a2, &eax, &edx);
+		err = rdmsr_safe_on_cpu(data->id, MSR_IA32_TEMPERATURE_TARGET, &eax, &edx);
 		if (err) {
 			dev_warn(&pdev->dev, "Unable to read"
 					" IA32_TEMPERATURE_TARGET MSR\n");
-- 
1.6.3.3.363.g725cf7


_______________________________________________
lm-sensors mailing list
lm-sensors@lm-sensors.org
http://lists.lm-sensors.org/mailman/listinfo/lm-sensors

[PATCH 2/2 V2] hwmon: (coretemp) Get TjMax value from MSR

[Huaxu Wan]

The MSR IA32_TEMPERATURE_TARGET contains the TjMax value in the newer
processers.

Signed-off-by: Huaxu Wan <huaxu.wan@linux.intel.com>
Signed-off-by: Carsten Emde <C.Emde@osadl.org>
---
 arch/x86/include/asm/msr-index.h |    2 +
 drivers/hwmon/coretemp.c         |   52 ++++++++++++++++++++++++++++++++++++-
 2 files changed, 52 insertions(+), 2 deletions(-)

diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index 4604e6a..9bc0cf8 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -232,6 +232,8 @@
 
 #define MSR_IA32_MISC_ENABLE		0x000001a0
 
+#define MSR_IA32_TEMPERATURE_TARGET	0x000001a2
+
 /* MISC_ENABLE bits: architectural */
 #define MSR_IA32_MISC_ENABLE_FAST_STRING	(1ULL << 0)
 #define MSR_IA32_MISC_ENABLE_TCC		(1ULL << 1)
diff --git a/drivers/hwmon/coretemp.c b/drivers/hwmon/coretemp.c
index d194207..9959390 100644
--- a/drivers/hwmon/coretemp.c
+++ b/drivers/hwmon/coretemp.c
@@ -241,6 +241,54 @@ static int __devinit adjust_tjmax(struct cpuinfo_x86 *c, u32 id, struct device *
 	return tjmax;
 }
 
+static int __devinit get_tjmax(struct cpuinfo_x86 *c, u32 id, struct device *dev)
+{
+	/* The 100C is default for both mobile and non mobile CPUs */
+	int err;
+	u32 eax, edx;
+	u32 val;
+
+	/* A new feature of current Intel(R) processors, the
+	   IA32_TEMPERATURE_TARGET contains the TjMax value */
+	err = rdmsr_safe_on_cpu(id, MSR_IA32_TEMPERATURE_TARGET, &eax, &edx);
+	if (err){
+		dev_warn(dev, "Unable to read TjMax from CPU.\n");
+	} else {
+		val = (eax >> 16 ) & 0xff;
+		/*
+		 * If the TjMax is not plausible, an assumption
+		 * will be used
+		 */
+		if (( val > 80) && (val < 120)){
+			dev_info(dev, "TjMax is %d C. \n", val);
+			return val * 1000;
+		}
+	}
+
+	/*
+	 * An assumption is made for early CPUs and unreadable MSR.
+	 * NOTE: the given value may not be correct.
+	 */
+
+	switch(c->x86_model){
+	case 0xe :
+	case 0xf :
+	case 0x16 :
+	case 0x1a :
+		dev_warn(dev, "TjMax is assumed as 100 C! \n");
+		return 100000;
+		break;
+	case 0x17 :
+	case 0x1c :		/* Atom CPUs */
+		return adjust_tjmax(c, id, dev);
+		break;
+	default :
+		dev_warn(dev, "CPU (model=0x%x) is not supported yet,"
+			" using default TjMax of 100C.\n", c->x86_model);
+		return 100000;
+	}
+}
+
 static int __devinit coretemp_probe(struct platform_device *pdev)
 {
 	struct coretemp_data *data;
@@ -283,14 +331,14 @@ static int __devinit coretemp_probe(struct platform_device *pdev)
 		}
 	}
 
-	data->tjmax = adjust_tjmax(c, data->id, &pdev->dev);
+	data->tjmax = get_tjmax(c, data->id, &pdev->dev);
 	platform_set_drvdata(pdev, data);
 
 	/* read the still undocumented IA32_TEMPERATURE_TARGET it exists
 	   on older CPUs but not in this register, Atoms don't have it either */
 
 	if ((c->x86_model > 0xe) && (c->x86_model != 0x1c)) {
-		err = rdmsr_safe_on_cpu(data->id, 0x1a2, &eax, &edx);
+		err = rdmsr_safe_on_cpu(data->id, MSR_IA32_TEMPERATURE_TARGET, &eax, &edx);
 		if (err) {
 			dev_warn(&pdev->dev, "Unable to read"
 					" IA32_TEMPERATURE_TARGET MSR\n");
-- 
1.6.3.3.363.g725cf7

Re: [lm-sensors] [PATCH 2/2] hwmon: (coretemp) Get TjMax value from

[Maxim Levitsky]

On Fri, 2010-05-07 at 17:59 +0800, Huaxu Wan wrote: 
> The MSR IA32_TEMPERATURE_TARGET contains the TjMax value in the newer
> processers.

I know that TjMax on my system is 85, and now coretemp reports wrong
temperatures.
First of all BIOS using stupid tricks actualy reports CPU temperature
through ACPI, and assuming it was correct TjMax is 85.
It also shuts down the system if I 'lie' to it that cpu temperature is
85C.

Coretemp was working correctly in 2.6.34

cat /proc/cpuinfo

processor	: 0
vendor_id	: GenuineIntel
cpu family	: 6
model		: 15
model name	: Intel(R) Core(TM)2 Duo CPU     T5450  @ 1.66GHz
stepping	: 13
cpu MHz		: 1667.000
cache size	: 2048 KB
physical id	: 0
siblings	: 2
core id		: 0
cpu cores	: 2
apicid		: 0
initial apicid	: 0
fpu		: yes
fpu_exception	: yes
cpuid level	: 10
wp		: yes
flags		: fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx lm constant_tsc arch_perfmon pebs bts rep_good aperfmperf pni dtes64 monitor ds_cpl est tm2 ssse3 cx16 xtpr pdcm lahf_lm
bogomips	: 3324.70
clflush size	: 64
cache_alignment	: 64
address sizes	: 36 bits physical, 48 bits virtual
power management:

processor	: 1
vendor_id	: GenuineIntel
cpu family	: 6
model		: 15
model name	: Intel(R) Core(TM)2 Duo CPU     T5450  @ 1.66GHz
stepping	: 13
cpu MHz		: 1667.000
cache size	: 2048 KB
physical id	: 0
siblings	: 2
core id		: 1
cpu cores	: 2
apicid		: 1
initial apicid	: 1
fpu		: yes
fpu_exception	: yes
cpuid level	: 10
wp		: yes
flags		: fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx lm constant_tsc arch_perfmon pebs bts rep_good aperfmperf pni dtes64 monitor ds_cpl est tm2 ssse3 cx16 xtpr pdcm lahf_lm
bogomips	: 3324.99
clflush size	: 64
cache_alignment	: 64
address sizes	: 36 bits physical, 48 bits virtual
power management:


Best regards,
	Maxim Levitsky


_______________________________________________
lm-sensors mailing list
lm-sensors@lm-sensors.org
http://lists.lm-sensors.org/mailman/listinfo/lm-sensors

Re: [PATCH 2/2] hwmon: (coretemp) Get TjMax value from MSR

[Maxim Levitsky]

On Fri, 2010-05-07 at 17:59 +0800, Huaxu Wan wrote: 
> The MSR IA32_TEMPERATURE_TARGET contains the TjMax value in the newer
> processers.

I know that TjMax on my system is 85, and now coretemp reports wrong
temperatures.
First of all BIOS using stupid tricks actualy reports CPU temperature
through ACPI, and assuming it was correct TjMax is 85.
It also shuts down the system if I 'lie' to it that cpu temperature is
85C.

Coretemp was working correctly in 2.6.34

cat /proc/cpuinfo

processor	: 0
vendor_id	: GenuineIntel
cpu family	: 6
model		: 15
model name	: Intel(R) Core(TM)2 Duo CPU     T5450  @ 1.66GHz
stepping	: 13
cpu MHz		: 1667.000
cache size	: 2048 KB
physical id	: 0
siblings	: 2
core id		: 0
cpu cores	: 2
apicid		: 0
initial apicid	: 0
fpu		: yes
fpu_exception	: yes
cpuid level	: 10
wp		: yes
flags		: fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx lm constant_tsc arch_perfmon pebs bts rep_good aperfmperf pni dtes64 monitor ds_cpl est tm2 ssse3 cx16 xtpr pdcm lahf_lm
bogomips	: 3324.70
clflush size	: 64
cache_alignment	: 64
address sizes	: 36 bits physical, 48 bits virtual
power management:

processor	: 1
vendor_id	: GenuineIntel
cpu family	: 6
model		: 15
model name	: Intel(R) Core(TM)2 Duo CPU     T5450  @ 1.66GHz
stepping	: 13
cpu MHz		: 1667.000
cache size	: 2048 KB
physical id	: 0
siblings	: 2
core id		: 1
cpu cores	: 2
apicid		: 1
initial apicid	: 1
fpu		: yes
fpu_exception	: yes
cpuid level	: 10
wp		: yes
flags		: fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx lm constant_tsc arch_perfmon pebs bts rep_good aperfmperf pni dtes64 monitor ds_cpl est tm2 ssse3 cx16 xtpr pdcm lahf_lm
bogomips	: 3324.99
clflush size	: 64
cache_alignment	: 64
address sizes	: 36 bits physical, 48 bits virtual
power management:


Best regards,
	Maxim Levitsky

Re: [lm-sensors] [PATCH 2/2] hwmon: (coretemp) Get TjMax value from

[Maxim Levitsky]

On Sat, 2010-05-29 at 08:39 +0300, Maxim Levitsky wrote: 
> On Fri, 2010-05-07 at 17:59 +0800, Huaxu Wan wrote: 
> > The MSR IA32_TEMPERATURE_TARGET contains the TjMax value in the newer
> > processers.
> 
> I know that TjMax on my system is 85, and now coretemp reports wrong
> temperatures.
> First of all BIOS using stupid tricks actualy reports CPU temperature
> through ACPI, and assuming it was correct TjMax is 85.
> It also shuts down the system if I 'lie' to it that cpu temperature is
> 85C.
> 
> Coretemp was working correctly in 2.6.34

The following patch unbreaks the driver:


commit 8ff4f666908dd208a10f1b6b38286303fdb774fc
Author: Maxim Levitsky <maximlevitsky@gmail.com>
Date:   Sat May 29 08:57:09 2010 +0300

coretemp: unbreak tjmax reports on Core2 CPUs

Core2 CPUS don't report TjMax, but its not always 100C

Signed-off-by: Maxim Levitsky <maximlevitsky@gmail.com>


diff --git a/drivers/hwmon/coretemp.c b/drivers/hwmon/coretemp.c
index 2988da1..fb100a4 100644
--- a/drivers/hwmon/coretemp.c
+++ b/drivers/hwmon/coretemp.c
@@ -276,11 +276,8 @@ static int __devinit get_tjmax(struct cpuinfo_x86
*c, u32 id,
case 0xf:
case 0x16:
case 0x1a:
- dev_warn(dev, "TjMax is assumed as 100 C!\n");
- return 100000;
- break;
case 0x17:
- case 0x1c: /* Atom CPUs */
+ case 0x1c:
return adjust_tjmax(c, id, dev);
break;
default:



_______________________________________________
lm-sensors mailing list
lm-sensors@lm-sensors.org
http://lists.lm-sensors.org/mailman/listinfo/lm-sensors

Re: [PATCH 2/2] hwmon: (coretemp) Get TjMax value from MSR

[Maxim Levitsky]

On Sat, 2010-05-29 at 08:39 +0300, Maxim Levitsky wrote: 
> On Fri, 2010-05-07 at 17:59 +0800, Huaxu Wan wrote: 
> > The MSR IA32_TEMPERATURE_TARGET contains the TjMax value in the newer
> > processers.
> 
> I know that TjMax on my system is 85, and now coretemp reports wrong
> temperatures.
> First of all BIOS using stupid tricks actualy reports CPU temperature
> through ACPI, and assuming it was correct TjMax is 85.
> It also shuts down the system if I 'lie' to it that cpu temperature is
> 85C.
> 
> Coretemp was working correctly in 2.6.34

The following patch unbreaks the driver:


commit 8ff4f666908dd208a10f1b6b38286303fdb774fc
Author: Maxim Levitsky <maximlevitsky@gmail.com>
Date:   Sat May 29 08:57:09 2010 +0300

coretemp: unbreak tjmax reports on Core2 CPUs

Core2 CPUS don't report TjMax, but its not always 100C

Signed-off-by: Maxim Levitsky <maximlevitsky@gmail.com>


diff --git a/drivers/hwmon/coretemp.c b/drivers/hwmon/coretemp.c
index 2988da1..fb100a4 100644
--- a/drivers/hwmon/coretemp.c
+++ b/drivers/hwmon/coretemp.c
@@ -276,11 +276,8 @@ static int __devinit get_tjmax(struct cpuinfo_x86
*c, u32 id,
case 0xf:
case 0x16:
case 0x1a:
- dev_warn(dev, "TjMax is assumed as 100 C!\n");
- return 100000;
- break;
case 0x17:
- case 0x1c: /* Atom CPUs */
+ case 0x1c:
return adjust_tjmax(c, id, dev);
break;
default:

Re: [lm-sensors] [PATCH 2/2] hwmon: (coretemp) Get TjMax value from

[Huaxu Wan]

On 08:39 Sat 29 May, Maxim Levitsky wrote:
> On Fri, 2010-05-07 at 17:59 +0800, Huaxu Wan wrote: 
> > The MSR IA32_TEMPERATURE_TARGET contains the TjMax value in the newer
> > processers.
> 
> I know that TjMax on my system is 85, and now coretemp reports wrong
> temperatures.
> First of all BIOS using stupid tricks actualy reports CPU temperature
> through ACPI, and assuming it was correct TjMax is 85.
> It also shuts down the system if I 'lie' to it that cpu temperature is
> 85C.

From the list at [1], the TjMax(Tjunction) of T5450 is 100C. Does anyone
here can make a double check?

[1] http://ark.intel.com/Product.aspx?id0787&processor=T5450&spec-codes=SLA4F

Thanks
Huaxu



> 
> Coretemp was working correctly in 2.6.34
> 
> cat /proc/cpuinfo
> 
> processor	: 0
> vendor_id	: GenuineIntel
> cpu family	: 6
> model		: 15
> model name	: Intel(R) Core(TM)2 Duo CPU     T5450  @ 1.66GHz
> stepping	: 13
> cpu MHz		: 1667.000
> cache size	: 2048 KB
> physical id	: 0
> siblings	: 2
> core id		: 0
> cpu cores	: 2
> apicid		: 0
> initial apicid	: 0
> fpu		: yes
> fpu_exception	: yes
> cpuid level	: 10
> wp		: yes
> flags		: fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx lm constant_tsc arch_perfmon pebs bts rep_good aperfmperf pni dtes64 monitor ds_cpl est tm2 ssse3 cx16 xtpr pdcm lahf_lm
> bogomips	: 3324.70
> clflush size	: 64
> cache_alignment	: 64
> address sizes	: 36 bits physical, 48 bits virtual
> power management:
> 
> processor	: 1
> vendor_id	: GenuineIntel
> cpu family	: 6
> model		: 15
> model name	: Intel(R) Core(TM)2 Duo CPU     T5450  @ 1.66GHz
> stepping	: 13
> cpu MHz		: 1667.000
> cache size	: 2048 KB
> physical id	: 0
> siblings	: 2
> core id		: 1
> cpu cores	: 2
> apicid		: 1
> initial apicid	: 1
> fpu		: yes
> fpu_exception	: yes
> cpuid level	: 10
> wp		: yes
> flags		: fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx lm constant_tsc arch_perfmon pebs bts rep_good aperfmperf pni dtes64 monitor ds_cpl est tm2 ssse3 cx16 xtpr pdcm lahf_lm
> bogomips	: 3324.99
> clflush size	: 64
> cache_alignment	: 64
> address sizes	: 36 bits physical, 48 bits virtual
> power management:
> 
> 
> Best regards,
> 	Maxim Levitsky
> 

_______________________________________________
lm-sensors mailing list
lm-sensors@lm-sensors.org
http://lists.lm-sensors.org/mailman/listinfo/lm-sensors

Re: [PATCH 2/2] hwmon: (coretemp) Get TjMax value from MSR

[Huaxu Wan]

On 08:39 Sat 29 May, Maxim Levitsky wrote:
> On Fri, 2010-05-07 at 17:59 +0800, Huaxu Wan wrote: 
> > The MSR IA32_TEMPERATURE_TARGET contains the TjMax value in the newer
> > processers.
> 
> I know that TjMax on my system is 85, and now coretemp reports wrong
> temperatures.
> First of all BIOS using stupid tricks actualy reports CPU temperature
> through ACPI, and assuming it was correct TjMax is 85.
> It also shuts down the system if I 'lie' to it that cpu temperature is
> 85C.

>From the list at [1], the TjMax(Tjunction) of T5450 is 100C. Does anyone
here can make a double check?

[1] http://ark.intel.com/Product.aspx?id=30787&processor=T5450&spec-codes=SLA4F

Thanks
Huaxu



> 
> Coretemp was working correctly in 2.6.34
> 
> cat /proc/cpuinfo
> 
> processor	: 0
> vendor_id	: GenuineIntel
> cpu family	: 6
> model		: 15
> model name	: Intel(R) Core(TM)2 Duo CPU     T5450  @ 1.66GHz
> stepping	: 13
> cpu MHz		: 1667.000
> cache size	: 2048 KB
> physical id	: 0
> siblings	: 2
> core id		: 0
> cpu cores	: 2
> apicid		: 0
> initial apicid	: 0
> fpu		: yes
> fpu_exception	: yes
> cpuid level	: 10
> wp		: yes
> flags		: fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx lm constant_tsc arch_perfmon pebs bts rep_good aperfmperf pni dtes64 monitor ds_cpl est tm2 ssse3 cx16 xtpr pdcm lahf_lm
> bogomips	: 3324.70
> clflush size	: 64
> cache_alignment	: 64
> address sizes	: 36 bits physical, 48 bits virtual
> power management:
> 
> processor	: 1
> vendor_id	: GenuineIntel
> cpu family	: 6
> model		: 15
> model name	: Intel(R) Core(TM)2 Duo CPU     T5450  @ 1.66GHz
> stepping	: 13
> cpu MHz		: 1667.000
> cache size	: 2048 KB
> physical id	: 0
> siblings	: 2
> core id		: 1
> cpu cores	: 2
> apicid		: 1
> initial apicid	: 1
> fpu		: yes
> fpu_exception	: yes
> cpuid level	: 10
> wp		: yes
> flags		: fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx lm constant_tsc arch_perfmon pebs bts rep_good aperfmperf pni dtes64 monitor ds_cpl est tm2 ssse3 cx16 xtpr pdcm lahf_lm
> bogomips	: 3324.99
> clflush size	: 64
> cache_alignment	: 64
> address sizes	: 36 bits physical, 48 bits virtual
> power management:
> 
> 
> Best regards,
> 	Maxim Levitsky
> 

Re: [lm-sensors] [PATCH 2/2] hwmon: (coretemp) Get TjMax value from

[Maxim Levitsky]

On Mon, 2010-05-31 at 09:39 +0800, Huaxu Wan wrote: 
> On 08:39 Sat 29 May, Maxim Levitsky wrote:
> > On Fri, 2010-05-07 at 17:59 +0800, Huaxu Wan wrote: 
> > > The MSR IA32_TEMPERATURE_TARGET contains the TjMax value in the newer
> > > processers.
> > 
> > I know that TjMax on my system is 85, and now coretemp reports wrong
> > temperatures.
> > First of all BIOS using stupid tricks actualy reports CPU temperature
> > through ACPI, and assuming it was correct TjMax is 85.
> > It also shuts down the system if I 'lie' to it that cpu temperature is
> > 85C.
> 
> From the list at [1], the TjMax(Tjunction) of T5450 is 100C. Does anyone
> here can make a double check?
> 
> [1] http://ark.intel.com/Product.aspx?id0787&processor=T5450&spec-codes=SLA4F

This is very interesting.

With TjMax 85C, the CPUs idle temperature is reported at around 45~50C
GPU temperature that is around 60C

BIOS also reports 45~50C.

BIOS hooks an SMI to CPU thermal report, and stores the temperature it
read in ram, then ACPI code reads it, reports and passes to the EC
(embedded controller).

If I write myself 85 to embedded controller, systems shuts down.
(values less that 85, eg 84 don't shut system).

Thats all I know.

Best regards,
Maxim Levitsky


_______________________________________________
lm-sensors mailing list
lm-sensors@lm-sensors.org
http://lists.lm-sensors.org/mailman/listinfo/lm-sensors

Re: [PATCH 2/2] hwmon: (coretemp) Get TjMax value from MSR

[Maxim Levitsky]

On Mon, 2010-05-31 at 09:39 +0800, Huaxu Wan wrote: 
> On 08:39 Sat 29 May, Maxim Levitsky wrote:
> > On Fri, 2010-05-07 at 17:59 +0800, Huaxu Wan wrote: 
> > > The MSR IA32_TEMPERATURE_TARGET contains the TjMax value in the newer
> > > processers.
> > 
> > I know that TjMax on my system is 85, and now coretemp reports wrong
> > temperatures.
> > First of all BIOS using stupid tricks actualy reports CPU temperature
> > through ACPI, and assuming it was correct TjMax is 85.
> > It also shuts down the system if I 'lie' to it that cpu temperature is
> > 85C.
> 
> From the list at [1], the TjMax(Tjunction) of T5450 is 100C. Does anyone
> here can make a double check?
> 
> [1] http://ark.intel.com/Product.aspx?id=30787&processor=T5450&spec-codes=SLA4F

This is very interesting.

With TjMax 85C, the CPUs idle temperature is reported at around 45~50C
GPU temperature that is around 60C

BIOS also reports 45~50C.

BIOS hooks an SMI to CPU thermal report, and stores the temperature it
read in ram, then ACPI code reads it, reports and passes to the EC
(embedded controller).

If I write myself 85 to embedded controller, systems shuts down.
(values less that 85, eg 84 don't shut system).

Thats all I know.

Best regards,
Maxim Levitsky

Re: [lm-sensors] [PATCH 2/2] hwmon: (coretemp) Get TjMax value from

[Maxim Levitsky]

On Wed, 2010-06-02 at 19:34 +0300, Maxim Levitsky wrote: 
> On Mon, 2010-05-31 at 09:39 +0800, Huaxu Wan wrote: 
> > On 08:39 Sat 29 May, Maxim Levitsky wrote:
> > > On Fri, 2010-05-07 at 17:59 +0800, Huaxu Wan wrote: 
> > > > The MSR IA32_TEMPERATURE_TARGET contains the TjMax value in the newer
> > > > processers.
> > > 
> > > I know that TjMax on my system is 85, and now coretemp reports wrong
> > > temperatures.
> > > First of all BIOS using stupid tricks actualy reports CPU temperature
> > > through ACPI, and assuming it was correct TjMax is 85.
> > > It also shuts down the system if I 'lie' to it that cpu temperature is
> > > 85C.
> > 
> > From the list at [1], the TjMax(Tjunction) of T5450 is 100C. Does anyone
> > here can make a double check?
> > 
> > [1] http://ark.intel.com/Product.aspx?id0787&processor=T5450&spec-codes=SLA4F
> 
> This is very interesting.
> 
> With TjMax 85C, the CPUs idle temperature is reported at around 45~50C
> GPU temperature that is around 60C
> 
> BIOS also reports 45~50C.
> 
> BIOS hooks an SMI to CPU thermal report, and stores the temperature it
> read in ram, then ACPI code reads it, reports and passes to the EC
> (embedded controller).
> 
> If I write myself 85 to embedded controller, systems shuts down.
> (values less that 85, eg 84 don't shut system).


Another clue is that right after resume from ram, after long delay
(~hour) the displayed temperature with TjMax 85 is 33C. Since room
temperature here is around 27C, this seems more plausible that 
33 + 15 = 48C 


Best regards,
Maxim Levitsky


_______________________________________________
lm-sensors mailing list
lm-sensors@lm-sensors.org
http://lists.lm-sensors.org/mailman/listinfo/lm-sensors

Re: [PATCH 2/2] hwmon: (coretemp) Get TjMax value from MSR

[Maxim Levitsky]

On Wed, 2010-06-02 at 19:34 +0300, Maxim Levitsky wrote: 
> On Mon, 2010-05-31 at 09:39 +0800, Huaxu Wan wrote: 
> > On 08:39 Sat 29 May, Maxim Levitsky wrote:
> > > On Fri, 2010-05-07 at 17:59 +0800, Huaxu Wan wrote: 
> > > > The MSR IA32_TEMPERATURE_TARGET contains the TjMax value in the newer
> > > > processers.
> > > 
> > > I know that TjMax on my system is 85, and now coretemp reports wrong
> > > temperatures.
> > > First of all BIOS using stupid tricks actualy reports CPU temperature
> > > through ACPI, and assuming it was correct TjMax is 85.
> > > It also shuts down the system if I 'lie' to it that cpu temperature is
> > > 85C.
> > 
> > From the list at [1], the TjMax(Tjunction) of T5450 is 100C. Does anyone
> > here can make a double check?
> > 
> > [1] http://ark.intel.com/Product.aspx?id=30787&processor=T5450&spec-codes=SLA4F
> 
> This is very interesting.
> 
> With TjMax 85C, the CPUs idle temperature is reported at around 45~50C
> GPU temperature that is around 60C
> 
> BIOS also reports 45~50C.
> 
> BIOS hooks an SMI to CPU thermal report, and stores the temperature it
> read in ram, then ACPI code reads it, reports and passes to the EC
> (embedded controller).
> 
> If I write myself 85 to embedded controller, systems shuts down.
> (values less that 85, eg 84 don't shut system).


Another clue is that right after resume from ram, after long delay
(~hour) the displayed temperature with TjMax 85 is 33C. Since room
temperature here is around 27C, this seems more plausible that 
33 + 15 = 48C 


Best regards,
Maxim Levitsky

Re: [lm-sensors] [PATCH 2/2] hwmon: (coretemp) Get TjMax value from

[Maxim Levitsky]

On Wed, 2010-06-02 at 23:10 +0300, Maxim Levitsky wrote: 
> On Wed, 2010-06-02 at 19:34 +0300, Maxim Levitsky wrote: 
> > On Mon, 2010-05-31 at 09:39 +0800, Huaxu Wan wrote: 
> > > On 08:39 Sat 29 May, Maxim Levitsky wrote:
> > > > On Fri, 2010-05-07 at 17:59 +0800, Huaxu Wan wrote: 
> > > > > The MSR IA32_TEMPERATURE_TARGET contains the TjMax value in the newer
> > > > > processers.
> > > > 
> > > > I know that TjMax on my system is 85, and now coretemp reports wrong
> > > > temperatures.
> > > > First of all BIOS using stupid tricks actualy reports CPU temperature
> > > > through ACPI, and assuming it was correct TjMax is 85.
> > > > It also shuts down the system if I 'lie' to it that cpu temperature is
> > > > 85C.
> > > 
> > > From the list at [1], the TjMax(Tjunction) of T5450 is 100C. Does anyone
> > > here can make a double check?
> > > 
> > > [1] http://ark.intel.com/Product.aspx?id0787&processor=T5450&spec-codes=SLA4F
> > 
> > This is very interesting.
> > 
> > With TjMax 85C, the CPUs idle temperature is reported at around 45~50C
> > GPU temperature that is around 60C
> > 
> > BIOS also reports 45~50C.
> > 
> > BIOS hooks an SMI to CPU thermal report, and stores the temperature it
> > read in ram, then ACPI code reads it, reports and passes to the EC
> > (embedded controller).
> > 
> > If I write myself 85 to embedded controller, systems shuts down.
> > (values less that 85, eg 84 don't shut system).
> 
> 
> Another clue is that right after resume from ram, after long delay
> (~hour) the displayed temperature with TjMax 85 is 33C. Since room
> temperature here is around 27C, this seems more plausible that 
> 33 + 15 = 48C 


Any update? 
> 
> 
> Best regards,
> Maxim Levitsky
> 



_______________________________________________
lm-sensors mailing list
lm-sensors@lm-sensors.org
http://lists.lm-sensors.org/mailman/listinfo/lm-sensors

Re: [PATCH 2/2] hwmon: (coretemp) Get TjMax value from MSR

[Maxim Levitsky]

On Wed, 2010-06-02 at 23:10 +0300, Maxim Levitsky wrote: 
> On Wed, 2010-06-02 at 19:34 +0300, Maxim Levitsky wrote: 
> > On Mon, 2010-05-31 at 09:39 +0800, Huaxu Wan wrote: 
> > > On 08:39 Sat 29 May, Maxim Levitsky wrote:
> > > > On Fri, 2010-05-07 at 17:59 +0800, Huaxu Wan wrote: 
> > > > > The MSR IA32_TEMPERATURE_TARGET contains the TjMax value in the newer
> > > > > processers.
> > > > 
> > > > I know that TjMax on my system is 85, and now coretemp reports wrong
> > > > temperatures.
> > > > First of all BIOS using stupid tricks actualy reports CPU temperature
> > > > through ACPI, and assuming it was correct TjMax is 85.
> > > > It also shuts down the system if I 'lie' to it that cpu temperature is
> > > > 85C.
> > > 
> > > From the list at [1], the TjMax(Tjunction) of T5450 is 100C. Does anyone
> > > here can make a double check?
> > > 
> > > [1] http://ark.intel.com/Product.aspx?id=30787&processor=T5450&spec-codes=SLA4F
> > 
> > This is very interesting.
> > 
> > With TjMax 85C, the CPUs idle temperature is reported at around 45~50C
> > GPU temperature that is around 60C
> > 
> > BIOS also reports 45~50C.
> > 
> > BIOS hooks an SMI to CPU thermal report, and stores the temperature it
> > read in ram, then ACPI code reads it, reports and passes to the EC
> > (embedded controller).
> > 
> > If I write myself 85 to embedded controller, systems shuts down.
> > (values less that 85, eg 84 don't shut system).
> 
> 
> Another clue is that right after resume from ram, after long delay
> (~hour) the displayed temperature with TjMax 85 is 33C. Since room
> temperature here is around 27C, this seems more plausible that 
> 33 + 15 = 48C 


Any update? 
> 
> 
> Best regards,
> Maxim Levitsky
> 

Re: [lm-sensors] [PATCH 2/2] hwmon: (coretemp) Get TjMax value from

[Wan, Huaxu]

>On Wed, 2010-06-02 at 23:10 +0300, Maxim Levitsky wrote: 
>> On Wed, 2010-06-02 at 19:34 +0300, Maxim Levitsky wrote: 
>> > On Mon, 2010-05-31 at 09:39 +0800, Huaxu Wan wrote: 
>> > > On 08:39 Sat 29 May, Maxim Levitsky wrote:
>> > > > On Fri, 2010-05-07 at 17:59 +0800, Huaxu Wan wrote: 
>> > > > > The MSR IA32_TEMPERATURE_TARGET contains the TjMax 
>value in the newer
>> > > > > processers.
>> > > > 
>> > > > I know that TjMax on my system is 85, and now coretemp 
>reports wrong
>> > > > temperatures.
>> > > > First of all BIOS using stupid tricks actualy reports 
>CPU temperature
>> > > > through ACPI, and assuming it was correct TjMax is 85.
>> > > > It also shuts down the system if I 'lie' to it that 
>cpu temperature is
>> > > > 85C.
>> > > 
>> > > From the list at [1], the TjMax(Tjunction) of T5450 is 
>100C. Does anyone
>> > > here can make a double check?
>> > > 
>> > > [1] 
>http://ark.intel.com/Product.aspx?id0787&processor=T5450&spec
>-codes=SLA4F
>> > 
>> > This is very interesting.
>> > 
>> > With TjMax 85C, the CPUs idle temperature is reported at 
>around 45~50C
>> > GPU temperature that is around 50C 
>> > 
>> > BIOS also reports 45~50C.
>> > 
>> > BIOS hooks an SMI to CPU thermal report, and stores the 
>temperature it
>> > read in ram, then ACPI code reads it, reports and passes to the EC
>> > (embedded controller).
>> > 
>> > If I write myself 85 to embedded controller, systems shuts down.
>> > (values less that 85, eg 84 don't shut system).
>> 
>> 
>> Another clue is that right after resume from ram, after long delay
>> (~hour) the displayed temperature with TjMax 85 is 33C. Since room
>> temperature here is around 27C, this seems more plausible that 
>> 33 + 15 = 48C 
>
>
>Any update? 

I'm occupied by other things, sorry for slow response. But, as said in a 
spec, I can't remember which one now, there are too many, the relative
value read from DTS is accurate approaching to TjMax. The accuracy
deteriorates to +-10C at 50C. Any DTS reading below 50C should be
considered to indicate only a temperature below 50C and not a specific
temperature.

So, the value around 50C can't be taken as real chip temperature. I
would like this issue could be confirmed by more users to avoid it as a 
particular case. At the meantime, I still looking for a laptop with T5450, 
this may take some time. 

Thanks
Huaxu 
_______________________________________________
lm-sensors mailing list
lm-sensors@lm-sensors.org
http://lists.lm-sensors.org/mailman/listinfo/lm-sensors

RE: [PATCH 2/2] hwmon: (coretemp) Get TjMax value from MSR

[Wan, Huaxu]

>On Wed, 2010-06-02 at 23:10 +0300, Maxim Levitsky wrote: 
>> On Wed, 2010-06-02 at 19:34 +0300, Maxim Levitsky wrote: 
>> > On Mon, 2010-05-31 at 09:39 +0800, Huaxu Wan wrote: 
>> > > On 08:39 Sat 29 May, Maxim Levitsky wrote:
>> > > > On Fri, 2010-05-07 at 17:59 +0800, Huaxu Wan wrote: 
>> > > > > The MSR IA32_TEMPERATURE_TARGET contains the TjMax 
>value in the newer
>> > > > > processers.
>> > > > 
>> > > > I know that TjMax on my system is 85, and now coretemp 
>reports wrong
>> > > > temperatures.
>> > > > First of all BIOS using stupid tricks actualy reports 
>CPU temperature
>> > > > through ACPI, and assuming it was correct TjMax is 85.
>> > > > It also shuts down the system if I 'lie' to it that 
>cpu temperature is
>> > > > 85C.
>> > > 
>> > > From the list at [1], the TjMax(Tjunction) of T5450 is 
>100C. Does anyone
>> > > here can make a double check?
>> > > 
>> > > [1] 
>http://ark.intel.com/Product.aspx?id=30787&processor=T5450&spec
>-codes=SLA4F
>> > 
>> > This is very interesting.
>> > 
>> > With TjMax 85C, the CPUs idle temperature is reported at 
>around 45~50C
>> > GPU temperature that is around 50C 
>> > 
>> > BIOS also reports 45~50C.
>> > 
>> > BIOS hooks an SMI to CPU thermal report, and stores the 
>temperature it
>> > read in ram, then ACPI code reads it, reports and passes to the EC
>> > (embedded controller).
>> > 
>> > If I write myself 85 to embedded controller, systems shuts down.
>> > (values less that 85, eg 84 don't shut system).
>> 
>> 
>> Another clue is that right after resume from ram, after long delay
>> (~hour) the displayed temperature with TjMax 85 is 33C. Since room
>> temperature here is around 27C, this seems more plausible that 
>> 33 + 15 = 48C 
>
>
>Any update? 

I'm occupied by other things, sorry for slow response. But, as said in a 
spec, I can't remember which one now, there are too many, the relative
value read from DTS is accurate approaching to TjMax. The accuracy
deteriorates to +-10C at 50C. Any DTS reading below 50C should be
considered to indicate only a temperature below 50C and not a specific
temperature.

So, the value around 50C can't be taken as real chip temperature. I
would like this issue could be confirmed by more users to avoid it as a 
particular case. At the meantime, I still looking for a laptop with T5450, 
this may take some time. 

Thanks
Huaxu 

Re: [lm-sensors] [PATCH 2/2] hwmon: (coretemp) Get TjMax value from

[Maxim Levitsky]

On Sun, 2010-06-13 at 10:27 +0800, Wan, Huaxu wrote: 
> >On Wed, 2010-06-02 at 23:10 +0300, Maxim Levitsky wrote: 
> >> On Wed, 2010-06-02 at 19:34 +0300, Maxim Levitsky wrote: 
> >> > On Mon, 2010-05-31 at 09:39 +0800, Huaxu Wan wrote: 
> >> > > On 08:39 Sat 29 May, Maxim Levitsky wrote:
> >> > > > On Fri, 2010-05-07 at 17:59 +0800, Huaxu Wan wrote: 
> >> > > > > The MSR IA32_TEMPERATURE_TARGET contains the TjMax 
> >value in the newer
> >> > > > > processers.
> >> > > > 
> >> > > > I know that TjMax on my system is 85, and now coretemp 
> >reports wrong
> >> > > > temperatures.
> >> > > > First of all BIOS using stupid tricks actualy reports 
> >CPU temperature
> >> > > > through ACPI, and assuming it was correct TjMax is 85.
> >> > > > It also shuts down the system if I 'lie' to it that 
> >cpu temperature is
> >> > > > 85C.
> >> > > 
> >> > > From the list at [1], the TjMax(Tjunction) of T5450 is 
> >100C. Does anyone
> >> > > here can make a double check?
> >> > > 
> >> > > [1] 
> >http://ark.intel.com/Product.aspx?id0787&processor=T5450&spec
> >-codes=SLA4F
> >> > 
> >> > This is very interesting.
> >> > 
> >> > With TjMax 85C, the CPUs idle temperature is reported at 
> >around 45~50C
> >> > GPU temperature that is around 50C 
> >> > 
> >> > BIOS also reports 45~50C.
> >> > 
> >> > BIOS hooks an SMI to CPU thermal report, and stores the 
> >temperature it
> >> > read in ram, then ACPI code reads it, reports and passes to the EC
> >> > (embedded controller).
> >> > 
> >> > If I write myself 85 to embedded controller, systems shuts down.
> >> > (values less that 85, eg 84 don't shut system).
> >> 
> >> 
> >> Another clue is that right after resume from ram, after long delay
> >> (~hour) the displayed temperature with TjMax 85 is 33C. Since room
> >> temperature here is around 27C, this seems more plausible that 
> >> 33 + 15 = 48C 
> >
> >
> >Any update? 
> 
> I'm occupied by other things, sorry for slow response. But, as said in a 
> spec, I can't remember which one now, there are too many, the relative
> value read from DTS is accurate approaching to TjMax. The accuracy
> deteriorates to +-10C at 50C. Any DTS reading below 50C should be
> considered to indicate only a temperature below 50C and not a specific
> temperature.
> 
> So, the value around 50C can't be taken as real chip temperature. I
> would like this issue could be confirmed by more users to avoid it as a 
> particular case. At the meantime, I still looking for a laptop with T5450, 
> this may take some time. 
> 
> Thanks
> Huaxu 

Any update?

Best regards,
Maxim Levitsky


_______________________________________________
lm-sensors mailing list
lm-sensors@lm-sensors.org
http://lists.lm-sensors.org/mailman/listinfo/lm-sensors

RE: [PATCH 2/2] hwmon: (coretemp) Get TjMax value from MSR

[Maxim Levitsky]

On Sun, 2010-06-13 at 10:27 +0800, Wan, Huaxu wrote: 
> >On Wed, 2010-06-02 at 23:10 +0300, Maxim Levitsky wrote: 
> >> On Wed, 2010-06-02 at 19:34 +0300, Maxim Levitsky wrote: 
> >> > On Mon, 2010-05-31 at 09:39 +0800, Huaxu Wan wrote: 
> >> > > On 08:39 Sat 29 May, Maxim Levitsky wrote:
> >> > > > On Fri, 2010-05-07 at 17:59 +0800, Huaxu Wan wrote: 
> >> > > > > The MSR IA32_TEMPERATURE_TARGET contains the TjMax 
> >value in the newer
> >> > > > > processers.
> >> > > > 
> >> > > > I know that TjMax on my system is 85, and now coretemp 
> >reports wrong
> >> > > > temperatures.
> >> > > > First of all BIOS using stupid tricks actualy reports 
> >CPU temperature
> >> > > > through ACPI, and assuming it was correct TjMax is 85.
> >> > > > It also shuts down the system if I 'lie' to it that 
> >cpu temperature is
> >> > > > 85C.
> >> > > 
> >> > > From the list at [1], the TjMax(Tjunction) of T5450 is 
> >100C. Does anyone
> >> > > here can make a double check?
> >> > > 
> >> > > [1] 
> >http://ark.intel.com/Product.aspx?id=30787&processor=T5450&spec
> >-codes=SLA4F
> >> > 
> >> > This is very interesting.
> >> > 
> >> > With TjMax 85C, the CPUs idle temperature is reported at 
> >around 45~50C
> >> > GPU temperature that is around 50C 
> >> > 
> >> > BIOS also reports 45~50C.
> >> > 
> >> > BIOS hooks an SMI to CPU thermal report, and stores the 
> >temperature it
> >> > read in ram, then ACPI code reads it, reports and passes to the EC
> >> > (embedded controller).
> >> > 
> >> > If I write myself 85 to embedded controller, systems shuts down.
> >> > (values less that 85, eg 84 don't shut system).
> >> 
> >> 
> >> Another clue is that right after resume from ram, after long delay
> >> (~hour) the displayed temperature with TjMax 85 is 33C. Since room
> >> temperature here is around 27C, this seems more plausible that 
> >> 33 + 15 = 48C 
> >
> >
> >Any update? 
> 
> I'm occupied by other things, sorry for slow response. But, as said in a 
> spec, I can't remember which one now, there are too many, the relative
> value read from DTS is accurate approaching to TjMax. The accuracy
> deteriorates to +-10C at 50C. Any DTS reading below 50C should be
> considered to indicate only a temperature below 50C and not a specific
> temperature.
> 
> So, the value around 50C can't be taken as real chip temperature. I
> would like this issue could be confirmed by more users to avoid it as a 
> particular case. At the meantime, I still looking for a laptop with T5450, 
> this may take some time. 
> 
> Thanks
> Huaxu 

Any update?

Best regards,
Maxim Levitsky

Re: [lm-sensors] [PATCH 2/2] hwmon: (coretemp) Get TjMax value from

[Huaxu Wan]

CC Fenghua. 

Could you found a Laptop with T5450 at hand? I can't found anywhere.

-Huaxu

On Mon, 2010-07-26 at 11:16 +0300, Maxim Levitsky wrote:
> On Sun, 2010-06-13 at 10:27 +0800, Wan, Huaxu wrote: 
> > >On Wed, 2010-06-02 at 23:10 +0300, Maxim Levitsky wrote: 
> > >> On Wed, 2010-06-02 at 19:34 +0300, Maxim Levitsky wrote: 
> > >> > On Mon, 2010-05-31 at 09:39 +0800, Huaxu Wan wrote: 
> > >> > > On 08:39 Sat 29 May, Maxim Levitsky wrote:
> > >> > > > On Fri, 2010-05-07 at 17:59 +0800, Huaxu Wan wrote: 
> > >> > > > > The MSR IA32_TEMPERATURE_TARGET contains the TjMax 
> > >value in the newer
> > >> > > > > processers.
> > >> > > > 
> > >> > > > I know that TjMax on my system is 85, and now coretemp 
> > >reports wrong
> > >> > > > temperatures.
> > >> > > > First of all BIOS using stupid tricks actualy reports 
> > >CPU temperature
> > >> > > > through ACPI, and assuming it was correct TjMax is 85.
> > >> > > > It also shuts down the system if I 'lie' to it that 
> > >cpu temperature is
> > >> > > > 85C.
> > >> > > 
> > >> > > From the list at [1], the TjMax(Tjunction) of T5450 is 
> > >100C. Does anyone
> > >> > > here can make a double check?
> > >> > > 
> > >> > > [1] 
> > >http://ark.intel.com/Product.aspx?id0787&processor=T5450&spec
> > >-codes=SLA4F
> > >> > 
> > >> > This is very interesting.
> > >> > 
> > >> > With TjMax 85C, the CPUs idle temperature is reported at 
> > >around 45~50C
> > >> > GPU temperature that is around 50C 
> > >> > 
> > >> > BIOS also reports 45~50C.
> > >> > 
> > >> > BIOS hooks an SMI to CPU thermal report, and stores the 
> > >temperature it
> > >> > read in ram, then ACPI code reads it, reports and passes to the EC
> > >> > (embedded controller).
> > >> > 
> > >> > If I write myself 85 to embedded controller, systems shuts down.
> > >> > (values less that 85, eg 84 don't shut system).
> > >> 
> > >> 
> > >> Another clue is that right after resume from ram, after long delay
> > >> (~hour) the displayed temperature with TjMax 85 is 33C. Since room
> > >> temperature here is around 27C, this seems more plausible that 
> > >> 33 + 15 = 48C 
> > >
> > >
> > >Any update? 
> > 
> > I'm occupied by other things, sorry for slow response. But, as said in a 
> > spec, I can't remember which one now, there are too many, the relative
> > value read from DTS is accurate approaching to TjMax. The accuracy
> > deteriorates to +-10C at 50C. Any DTS reading below 50C should be
> > considered to indicate only a temperature below 50C and not a specific
> > temperature.
> > 
> > So, the value around 50C can't be taken as real chip temperature. I
> > would like this issue could be confirmed by more users to avoid it as a 
> > particular case. At the meantime, I still looking for a laptop with T5450, 
> > this may take some time. 
> > 
> > Thanks
> > Huaxu 
> 
> Any update?
> 
> Best regards,
> Maxim Levitsky
> 



_______________________________________________
lm-sensors mailing list
lm-sensors@lm-sensors.org
http://lists.lm-sensors.org/mailman/listinfo/lm-sensors

RE: [PATCH 2/2] hwmon: (coretemp) Get TjMax value from MSR

[Huaxu Wan]

CC Fenghua. 

Could you found a Laptop with T5450 at hand? I can't found anywhere.

-Huaxu

On Mon, 2010-07-26 at 11:16 +0300, Maxim Levitsky wrote:
> On Sun, 2010-06-13 at 10:27 +0800, Wan, Huaxu wrote: 
> > >On Wed, 2010-06-02 at 23:10 +0300, Maxim Levitsky wrote: 
> > >> On Wed, 2010-06-02 at 19:34 +0300, Maxim Levitsky wrote: 
> > >> > On Mon, 2010-05-31 at 09:39 +0800, Huaxu Wan wrote: 
> > >> > > On 08:39 Sat 29 May, Maxim Levitsky wrote:
> > >> > > > On Fri, 2010-05-07 at 17:59 +0800, Huaxu Wan wrote: 
> > >> > > > > The MSR IA32_TEMPERATURE_TARGET contains the TjMax 
> > >value in the newer
> > >> > > > > processers.
> > >> > > > 
> > >> > > > I know that TjMax on my system is 85, and now coretemp 
> > >reports wrong
> > >> > > > temperatures.
> > >> > > > First of all BIOS using stupid tricks actualy reports 
> > >CPU temperature
> > >> > > > through ACPI, and assuming it was correct TjMax is 85.
> > >> > > > It also shuts down the system if I 'lie' to it that 
> > >cpu temperature is
> > >> > > > 85C.
> > >> > > 
> > >> > > From the list at [1], the TjMax(Tjunction) of T5450 is 
> > >100C. Does anyone
> > >> > > here can make a double check?
> > >> > > 
> > >> > > [1] 
> > >http://ark.intel.com/Product.aspx?id=30787&processor=T5450&spec
> > >-codes=SLA4F
> > >> > 
> > >> > This is very interesting.
> > >> > 
> > >> > With TjMax 85C, the CPUs idle temperature is reported at 
> > >around 45~50C
> > >> > GPU temperature that is around 50C 
> > >> > 
> > >> > BIOS also reports 45~50C.
> > >> > 
> > >> > BIOS hooks an SMI to CPU thermal report, and stores the 
> > >temperature it
> > >> > read in ram, then ACPI code reads it, reports and passes to the EC
> > >> > (embedded controller).
> > >> > 
> > >> > If I write myself 85 to embedded controller, systems shuts down.
> > >> > (values less that 85, eg 84 don't shut system).
> > >> 
> > >> 
> > >> Another clue is that right after resume from ram, after long delay
> > >> (~hour) the displayed temperature with TjMax 85 is 33C. Since room
> > >> temperature here is around 27C, this seems more plausible that 
> > >> 33 + 15 = 48C 
> > >
> > >
> > >Any update? 
> > 
> > I'm occupied by other things, sorry for slow response. But, as said in a 
> > spec, I can't remember which one now, there are too many, the relative
> > value read from DTS is accurate approaching to TjMax. The accuracy
> > deteriorates to +-10C at 50C. Any DTS reading below 50C should be
> > considered to indicate only a temperature below 50C and not a specific
> > temperature.
> > 
> > So, the value around 50C can't be taken as real chip temperature. I
> > would like this issue could be confirmed by more users to avoid it as a 
> > particular case. At the meantime, I still looking for a laptop with T5450, 
> > this may take some time. 
> > 
> > Thanks
> > Huaxu 
> 
> Any update?
> 
> Best regards,
> Maxim Levitsky
> 

Re: [lm-sensors] [PATCH 2/2] hwmon: (coretemp) Get TjMax value from

[Fenghua Yu]

On Sun, Aug 29, 2010 at 06:42:36PM -0700, Huaxu Wan wrote:
> On Mon, 2010-07-26 at 11:16 +0300, Maxim Levitsky wrote:
> > On Sun, 2010-06-13 at 10:27 +0800, Wan, Huaxu wrote: 
> > > >On Wed, 2010-06-02 at 23:10 +0300, Maxim Levitsky wrote: 
> > > >> On Wed, 2010-06-02 at 19:34 +0300, Maxim Levitsky wrote: 
> > > >> > On Mon, 2010-05-31 at 09:39 +0800, Huaxu Wan wrote: 
> > > >> > > On 08:39 Sat 29 May, Maxim Levitsky wrote:
> > > >> > > > On Fri, 2010-05-07 at 17:59 +0800, Huaxu Wan wrote: 
> > > >> > > > > The MSR IA32_TEMPERATURE_TARGET contains the TjMax 
> > > >value in the newer
> > > >> > > > > processers.
> > > >> > > > 
> > > >> > > > I know that TjMax on my system is 85, and now coretemp 
> > > >reports wrong
> > > >> > > > temperatures.
> > > >> > > > First of all BIOS using stupid tricks actualy reports 
> > > >CPU temperature
> > > >> > > > through ACPI, and assuming it was correct TjMax is 85.
> > > >> > > > It also shuts down the system if I 'lie' to it that 
> > > >cpu temperature is
> > > >> > > > 85C.
> > > >> > > 
> > > >> > > From the list at [1], the TjMax(Tjunction) of T5450 is 
> > > >100C. Does anyone
> > > >> > > here can make a double check?
> > > >> > > 
> > > >> > > [1] 
> > > >http://ark.intel.com/Product.aspx?id0787&processor=T5450&spec
> > > >-codes=SLA4F
> > > >> > 
> > > >> > This is very interesting.
> > > >> > 
> > > >> > With TjMax 85C, the CPUs idle temperature is reported at 
> > > >around 45~50C
> > > >> > GPU temperature that is around 50C 
> > > >> > 
> > > >> > BIOS also reports 45~50C.
> > > >> > 
> > > >> > BIOS hooks an SMI to CPU thermal report, and stores the 
> > > >temperature it
> > > >> > read in ram, then ACPI code reads it, reports and passes to the EC
> > > >> > (embedded controller).
> > > >> > 
> > > >> > If I write myself 85 to embedded controller, systems shuts down.
> > > >> > (values less that 85, eg 84 don't shut system).
> > > >> 
> > > >> 
> > > >> Another clue is that right after resume from ram, after long delay
> > > >> (~hour) the displayed temperature with TjMax 85 is 33C. Since room
> > > >> temperature here is around 27C, this seems more plausible that 
> > > >> 33 + 15 = 48C 
> > > >
> > > >
> > > >Any update? 
> > > 
> > > I'm occupied by other things, sorry for slow response. But, as said in a 
> > > spec, I can't remember which one now, there are too many, the relative
> > > value read from DTS is accurate approaching to TjMax. The accuracy
> > > deteriorates to +-10C at 50C. Any DTS reading below 50C should be
> > > considered to indicate only a temperature below 50C and not a specific
> > > temperature.
> > > 
> > > So, the value around 50C can't be taken as real chip temperature. I
> > > would like this issue could be confirmed by more users to avoid it as a 
> > > particular case. At the meantime, I still looking for a laptop with T5450, 
> > > this may take some time. 

Hi, Maxim,

Could you send out thermal zone info under /proc/acpi/thermal_zone/TZ*?

Thanks.

-Fenghua

_______________________________________________
lm-sensors mailing list
lm-sensors@lm-sensors.org
http://lists.lm-sensors.org/mailman/listinfo/lm-sensors

Re: [PATCH 2/2] hwmon: (coretemp) Get TjMax value from MSR

[Fenghua Yu]

On Sun, Aug 29, 2010 at 06:42:36PM -0700, Huaxu Wan wrote:
> On Mon, 2010-07-26 at 11:16 +0300, Maxim Levitsky wrote:
> > On Sun, 2010-06-13 at 10:27 +0800, Wan, Huaxu wrote: 
> > > >On Wed, 2010-06-02 at 23:10 +0300, Maxim Levitsky wrote: 
> > > >> On Wed, 2010-06-02 at 19:34 +0300, Maxim Levitsky wrote: 
> > > >> > On Mon, 2010-05-31 at 09:39 +0800, Huaxu Wan wrote: 
> > > >> > > On 08:39 Sat 29 May, Maxim Levitsky wrote:
> > > >> > > > On Fri, 2010-05-07 at 17:59 +0800, Huaxu Wan wrote: 
> > > >> > > > > The MSR IA32_TEMPERATURE_TARGET contains the TjMax 
> > > >value in the newer
> > > >> > > > > processers.
> > > >> > > > 
> > > >> > > > I know that TjMax on my system is 85, and now coretemp 
> > > >reports wrong
> > > >> > > > temperatures.
> > > >> > > > First of all BIOS using stupid tricks actualy reports 
> > > >CPU temperature
> > > >> > > > through ACPI, and assuming it was correct TjMax is 85.
> > > >> > > > It also shuts down the system if I 'lie' to it that 
> > > >cpu temperature is
> > > >> > > > 85C.
> > > >> > > 
> > > >> > > From the list at [1], the TjMax(Tjunction) of T5450 is 
> > > >100C. Does anyone
> > > >> > > here can make a double check?
> > > >> > > 
> > > >> > > [1] 
> > > >http://ark.intel.com/Product.aspx?id=30787&processor=T5450&spec
> > > >-codes=SLA4F
> > > >> > 
> > > >> > This is very interesting.
> > > >> > 
> > > >> > With TjMax 85C, the CPUs idle temperature is reported at 
> > > >around 45~50C
> > > >> > GPU temperature that is around 50C 
> > > >> > 
> > > >> > BIOS also reports 45~50C.
> > > >> > 
> > > >> > BIOS hooks an SMI to CPU thermal report, and stores the 
> > > >temperature it
> > > >> > read in ram, then ACPI code reads it, reports and passes to the EC
> > > >> > (embedded controller).
> > > >> > 
> > > >> > If I write myself 85 to embedded controller, systems shuts down.
> > > >> > (values less that 85, eg 84 don't shut system).
> > > >> 
> > > >> 
> > > >> Another clue is that right after resume from ram, after long delay
> > > >> (~hour) the displayed temperature with TjMax 85 is 33C. Since room
> > > >> temperature here is around 27C, this seems more plausible that 
> > > >> 33 + 15 = 48C 
> > > >
> > > >
> > > >Any update? 
> > > 
> > > I'm occupied by other things, sorry for slow response. But, as said in a 
> > > spec, I can't remember which one now, there are too many, the relative
> > > value read from DTS is accurate approaching to TjMax. The accuracy
> > > deteriorates to +-10C at 50C. Any DTS reading below 50C should be
> > > considered to indicate only a temperature below 50C and not a specific
> > > temperature.
> > > 
> > > So, the value around 50C can't be taken as real chip temperature. I
> > > would like this issue could be confirmed by more users to avoid it as a 
> > > particular case. At the meantime, I still looking for a laptop with T5450, 
> > > this may take some time. 

Hi, Maxim,

Could you send out thermal zone info under /proc/acpi/thermal_zone/TZ*?

Thanks.

-Fenghua