[PATCH 10/16] cxl/core: Enable CXL.mem timeout

[Ben Cheatham <Benjamin.Cheatham@amd.com>]

Add functions to enable and disable CXL.mem transaction timeout. Enable
timeout as part of CXL isolation set up.

Signed-off-by: Ben Cheatham <Benjamin.Cheatham@amd.com>
---
 drivers/cxl/core/pci.c  | 22 ++++++++++++++++++++++
 drivers/cxl/core/port.c | 14 +++++++++-----
 drivers/cxl/cxl.h       |  4 ++++
 include/cxl/isolation.h |  5 +++++
 4 files changed, 40 insertions(+), 5 deletions(-)

diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c
index 89fb6d3854e3..dd6c602d57d3 100644
--- a/drivers/cxl/core/pci.c
+++ b/drivers/cxl/core/pci.c
@@ -1237,3 +1237,25 @@ int cxl_disable_isolation(struct cxl_dport *dport)
 	dev_dbg(dport->dport_dev, "Disabled CXL.mem isolation\n");
 	return 0;
 }
+
+void cxl_enable_timeout(struct cxl_dport *dport)
+{
+	u32 ctrl;
+
+	ctrl = readl(dport->regs.isolation + CXL_ISOLATION_CTRL_OFFSET);
+	ctrl |= CXL_ISOLATION_CTRL_MEM_TIME_ENABLE;
+	writel(ctrl, dport->regs.isolation + CXL_ISOLATION_CTRL_OFFSET);
+
+	dev_dbg(dport->dport_dev, "Enabled CXL.mem transaction timeout\n");
+}
+
+void cxl_disable_timeout(struct cxl_dport *dport)
+{
+	u32 ctrl;
+
+	ctrl = readl(dport->regs.isolation + CXL_ISOLATION_CTRL_OFFSET);
+	ctrl &= ~CXL_ISOLATION_CTRL_MEM_TIME_ENABLE;
+	writel(ctrl, dport->regs.isolation + CXL_ISOLATION_CTRL_OFFSET);
+
+	dev_dbg(dport->dport_dev, "Disabled CXL.mem transaction timeout\n");
+}
diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
index c9e7bfc082d5..6591e83e719c 100644
--- a/drivers/cxl/core/port.c
+++ b/drivers/cxl/core/port.c
@@ -1312,15 +1312,15 @@ static int cxl_dport_setup_interrupts(struct device *host,
 }
 
 /**
- * cxl_dport_enable_isolation - Enable CXL Isolation for a CXL dport. This is
- * an optional capability only supported by PCIe Root Ports.
+ * cxl_dport_enable_timeout_isolation - Enable CXL Isolation for a CXL dport.
+ * This is an optional capability only supported by PCIe Root Ports.
  * @host: Host device for @dport
  * @dport: CXL-capable PCIe Root Port
  *
  * Returns 0 if capability unsupported, or when enabled.
  */
-static int cxl_dport_enable_isolation(struct device *host,
-				      struct cxl_dport *dport)
+static int cxl_dport_enable_timeout_isolation(struct device *host,
+					      struct cxl_dport *dport)
 {
 	u32 cap;
 	int rc;
@@ -1342,6 +1342,10 @@ static int cxl_dport_enable_isolation(struct device *host,
 		return rc == -ENXIO ? 0 : rc;
 
 	cxl_enable_isolation(dport);
+
+	if (!(cap & CXL_ISOLATION_CAP_MEM_TIME_SUPP))
+		cxl_enable_timeout(dport);
+
 	return 0;
 }
 
@@ -1408,7 +1412,7 @@ __devm_cxl_add_dport(struct cxl_port *port, struct device *dport_dev,
 			&component_reg_phys);
 
 	if (IS_ENABLED(CONFIG_CXL_ISOLATION)) {
-		rc = cxl_dport_enable_isolation(host, dport);
+		rc = cxl_dport_enable_timeout_isolation(host, dport);
 		if (rc)
 			return ERR_PTR(rc);
 	}
diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
index 8da1e40ab4e7..7f9c6bd6e010 100644
--- a/drivers/cxl/cxl.h
+++ b/drivers/cxl/cxl.h
@@ -136,10 +136,14 @@ static inline int ways_to_eiw(unsigned int ways, u8 *eiw)
 
 /* CXL 3.2 8.2.4.24 CXL Timeout and Isolation Capability Structure */
 #define CXL_ISOLATION_CAPABILITY_OFFSET 0x0
+#define   CXL_ISOLATION_CAP_MEM_TIME_MASK GENMASK(3, 0)
+#define   CXL_ISOLATION_CAP_MEM_TIME_SUPP BIT(4)
 #define   CXL_ISOLATION_CAP_MEM_ISO_SUPP BIT(16)
 #define   CXL_ISOLATION_CAP_INTR_SUPP BIT(26)
 #define   CXL_ISOLATION_CAP_INTR_MASK GENMASK(31, 27)
 #define CXL_ISOLATION_CTRL_OFFSET 0x8
+#define   CXL_ISOLATION_CTRL_MEM_TIME_MASK GENMASK(3, 0)
+#define   CXL_ISOLATION_CTRL_MEM_TIME_ENABLE BIT(4)
 #define   CXL_ISOLATION_CTRL_MEM_ISO_ENABLE BIT(16)
 #define   CXL_ISOLATION_CTRL_MEM_INTR_ENABLE BIT(26)
 #define CXL_ISOLATION_STATUS_OFFSET 0xC
diff --git a/include/cxl/isolation.h b/include/cxl/isolation.h
index 3ad05ccc5e01..73282ac262a6 100644
--- a/include/cxl/isolation.h
+++ b/include/cxl/isolation.h
@@ -28,10 +28,15 @@ struct cxl_dport;
 #if IS_ENABLED(CONFIG_CXL_BUS)
 void cxl_enable_isolation(struct cxl_dport *dport);
 int cxl_disable_isolation(struct cxl_dport *dport);
+void cxl_enable_timeout(struct cxl_dport *dport);
+void cxl_disable_timeout(struct cxl_dport *dport);
+
 #else /* !CONFIG_CXL_BUS */
 static inline void cxl_enable_isolation(struct cxl_dport *dport) {}
 static inline int cxl_disable_isolation(struct cxl_dport *dport)
 { return -ENXIO; }
+static inline void cxl_enable_timeout(struct cxl_dport *dport) {}
+static inline void cxl_disable_timeout(struct cxl_dport *dport) {}
 #endif /* !CONFIG_CXL_BUS */
 
 #ifdef CONFIG_CXL_ISOLATION
-- 
2.34.1