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From: Ben Cheatham <Benjamin.Cheatham@amd.com>
To: <linux-cxl@vger.kernel.org>, <linux-pci@vger.kernel.org>,
	<linux-acpi@vger.kernel.org>
Cc: Ben Cheatham <Benjamin.Cheatham@amd.com>
Subject: [PATCH 11/16] cxl/pci: Add isolation handler
Date: Wed, 30 Jul 2025 16:47:13 -0500	[thread overview]
Message-ID: <20250730214718.10679-12-Benjamin.Cheatham@amd.com> (raw)
In-Reply-To: <20250730214718.10679-1-Benjamin.Cheatham@amd.com>

Add an error isolation handler for type 3 CXL devices. The current
behavior is to log any AER information and then panic.

Signed-off-by: Ben Cheatham <Benjamin.Cheatham@amd.com>
---
 drivers/cxl/pci.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c
index 2a56936ac4f2..b0f2400c6ac9 100644
--- a/drivers/cxl/pci.c
+++ b/drivers/cxl/pci.c
@@ -900,6 +900,13 @@ static struct attribute_group cxl_rcd_group = {
 };
 __ATTRIBUTE_GROUPS(cxl_rcd);
 
+static enum cxl_err_results
+cxl_pci_isolation_handler(struct cxl_dev_state *cxlds, bool lnk_down)
+{
+	cxl_error_detected(cxlds->dev);
+	return CXL_ERR_PANIC;
+}
+
 static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
 {
 	struct pci_host_bridge *host_bridge = pci_find_host_bridge(pdev->bus);
@@ -1006,6 +1013,8 @@ static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
 	if (rc)
 		dev_dbg(&pdev->dev, "No CXL Features discovered\n");
 
+	cxlds->isolation_handler = cxl_pci_isolation_handler;
+
 	cxlmd = devm_cxl_add_memdev(&pdev->dev, cxlds);
 	if (IS_ERR(cxlmd))
 		return PTR_ERR(cxlmd);
-- 
2.34.1


  parent reply	other threads:[~2025-07-30 21:50 UTC|newest]

Thread overview: 37+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-07-30 21:47 [PATCH 00/16] CXL.mem error isolation support Ben Cheatham
2025-07-30 21:47 ` [PATCH 01/16] cxl/regs: Add cxl_unmap_component_regs() Ben Cheatham
2025-09-12 14:46   ` Jonathan Cameron
2025-09-17 17:26     ` Cheatham, Benjamin
2025-07-30 21:47 ` [PATCH 02/16] cxl/regs: Add CXL Isolation capability mapping Ben Cheatham
2025-09-12 14:47   ` Jonathan Cameron
2025-07-30 21:47 ` [PATCH 03/16] PCI: PCIe portdrv: Add CXL Isolation service driver Ben Cheatham
2025-09-12 15:14   ` Jonathan Cameron
2025-09-17 17:26     ` Cheatham, Benjamin
2025-07-30 21:47 ` [PATCH 04/16] PCI: PCIe portdrv: Allocate CXL isolation MSI/-X vector Ben Cheatham
2025-08-04 21:39   ` Bjorn Helgaas
2025-08-06 17:58     ` Cheatham, Benjamin
2025-07-30 21:47 ` [PATCH 05/16] PCI: PCIe portdrv: Add interface for getting CXL isolation IRQ Ben Cheatham
2025-07-31  5:59   ` Lukas Wunner
2025-07-31 13:13     ` Cheatham, Benjamin
2025-07-30 21:47 ` [PATCH 06/16] cxl/core: Enable CXL.mem isolation Ben Cheatham
2025-09-12 15:21   ` Jonathan Cameron
2025-09-17 17:26     ` Cheatham, Benjamin
2025-07-30 21:47 ` [PATCH 07/16] cxl/core: Set up isolation interrupts Ben Cheatham
2025-09-12 15:25   ` Jonathan Cameron
2025-09-17 17:27     ` Cheatham, Benjamin
2025-07-30 21:47 ` [PATCH 08/16] cxl/core: Enable CXL " Ben Cheatham
2025-07-30 21:47 ` [PATCH 09/16] cxl/core: Prevent onlining CXL memory behind isolated ports Ben Cheatham
2025-07-30 21:47 ` [PATCH 10/16] cxl/core: Enable CXL.mem timeout Ben Cheatham
2025-07-30 21:47 ` Ben Cheatham [this message]
2025-07-30 21:47 ` [PATCH 12/16] PCI: PCIe portdrv: Add cxl_isolation sysfs attributes Ben Cheatham
2025-09-12 15:33   ` Jonathan Cameron
2025-09-17 17:27     ` Cheatham, Benjamin
2025-07-30 21:47 ` [PATCH 13/16] cxl/core, PCI: PCIe portdrv: Add CXL timeout range programming Ben Cheatham
2025-08-04 21:39   ` Bjorn Helgaas
2025-08-06 17:58     ` Cheatham, Benjamin
2025-09-12 15:55   ` Jonathan Cameron
2025-09-17 17:27     ` Cheatham, Benjamin
2025-07-30 21:47 ` [PATCH 14/16] ACPI: Add CXL isolation _OSC fields Ben Cheatham
2025-08-22 19:19   ` Rafael J. Wysocki
2025-07-30 21:47 ` [PATCH 15/16] cxl/core, cxl/acpi: Enable CXL isolation based on _OSC handshake Ben Cheatham
2025-07-30 21:47 ` [PATCH 16/16] cxl/core, cxl/acpi: Add CXL isolation notify handler Ben Cheatham

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