[PATCH 15/16] cxl/core, cxl/acpi: Enable CXL isolation based on _OSC handshake

[Ben Cheatham <Benjamin.Cheatham@amd.com>]

Enable CXL isolation based on the result of _OSC handshake, if
applicable. In the absence of a _OSC interpretation callback (i.e.
platform is non-ACPI), assume that we have control of all features.

A link for the ECN (expected in CXL 4.0 spec) that introduces the
relevant parts of the _OSC method (CXL 3.2 9.18.2) can be found below.
spec). This link is only accesible to CXL SSWG members, so here's a brief
overview:

The ECN introduces an _OSC field for controlling whether the OSPM can write
to the CXL.mem Isolation Enable bit in the CXL isolation control
register (CXL 3.2 8.2.4.24.2). If the firmware reserves control, the
OSPM is expected to not modify the isolation enable bit when writing the
register.

Link: https://members.computeexpresslink.org/wg/software_systems/document/3118
Signed-off-by: Ben Cheatham <Benjamin.Cheatham@amd.com>
---
 drivers/cxl/acpi.c      | 24 ++++++++++++++++++++++++
 drivers/cxl/core/port.c | 17 +++++++++++++++--
 drivers/cxl/cxl.h       |  5 +++++
 include/cxl/isolation.h |  4 ++++
 4 files changed, 48 insertions(+), 2 deletions(-)

diff --git a/drivers/cxl/acpi.c b/drivers/cxl/acpi.c
index badaa99ab33a..b964f02fb56b 100644
--- a/drivers/cxl/acpi.c
+++ b/drivers/cxl/acpi.c
@@ -8,6 +8,7 @@
 #include <linux/pci.h>
 #include <linux/node.h>
 #include <asm/div64.h>
+#include <cxl/isolation.h>
 #include "cxlpci.h"
 #include "cxl.h"
 
@@ -367,9 +368,32 @@ static int cxl_acpi_setup_hostbridge_uport(struct cxl_root *cxl_root,
 	return 0;
 }
 
+static void decode_isolation_osc(struct cxl_port *hb, u32 iso_cap)
+{
+	bool err_corr = FIELD_GET(CXL_ISOLATION_CAP_ERR_COR_SUPP, iso_cap);
+	struct acpi_device *adev = ACPI_COMPANION(hb->uport_dev);
+	struct acpi_pci_root *pci_root;
+	u32 osc_ctrl;
+
+	if (!adev)
+		return;
+
+	pci_root = acpi_pci_find_root(adev->handle);
+	if (!pci_root)
+		return;
+
+	osc_ctrl = pci_root->osc_ext_control_set;
+	if (osc_ctrl & OSC_CXL_MEM_ISOLATION_CONTROL)
+		hb->isolation_caps |= CXL_ISOLATION_MEM_ENABLE;
+
+	if (!err_corr || (osc_ctrl & OSC_CXL_ISOLATION_NOTIF_CONTROL))
+		hb->isolation_caps |= CXL_ISOLATION_INTERRUPTS;
+}
+
 static const struct cxl_root_ops acpi_root_ops = {
 	.qos_class = cxl_acpi_qos_class,
 	.setup_hostbridge_uport = cxl_acpi_setup_hostbridge_uport,
+	.get_isolation_caps = decode_isolation_osc,
 };
 
 static void del_cxl_resource(struct resource *res)
diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
index b5a306341bb2..e9eb7a8a5f72 100644
--- a/drivers/cxl/core/port.c
+++ b/drivers/cxl/core/port.c
@@ -1322,7 +1322,8 @@ static int cxl_dport_setup_interrupts(struct device *host,
 static int cxl_dport_enable_timeout_isolation(struct device *host,
 					      struct cxl_dport *dport)
 {
-	u32 cap;
+	struct cxl_port *port = dport->port;
+	u32 cap, ctrl;
 	int rc;
 
 	if (!dport->reg_map.component_map.isolation.valid)
@@ -1337,11 +1338,23 @@ static int cxl_dport_enable_timeout_isolation(struct device *host,
 	if (!(cap & CXL_ISOLATION_CAP_MEM_ISO_SUPP))
 		return 0;
 
+	struct cxl_root *root __free(put_cxl_root) = find_cxl_root(dport->port);
+	if (root && root->ops && root->ops->get_isolation_caps)
+		root->ops->get_isolation_caps(port, cap);
+	else
+		port->isolation_caps = ~0;
+
+	ctrl = readl(dport->regs.isolation + CXL_ISOLATION_CTRL_OFFSET);
+	if (!(port->isolation_caps & CXL_ISOLATION_MEM_ENABLE) &&
+	    !(ctrl & CXL_ISOLATION_CTRL_MEM_ISO_ENABLE))
+		return 0;
+
 	rc = cxl_dport_setup_interrupts(host, dport);
 	if (rc)
 		return rc == -ENXIO ? 0 : rc;
 
-	cxl_enable_isolation(dport);
+	if (port->isolation_caps & CXL_ISOLATION_MEM_ENABLE)
+		cxl_enable_isolation(dport);
 
 	if (!(cap & CXL_ISOLATION_CAP_MEM_TIME_SUPP))
 		cxl_enable_timeout(dport);
diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
index 7f9c6bd6e010..aa36eba79181 100644
--- a/drivers/cxl/cxl.h
+++ b/drivers/cxl/cxl.h
@@ -139,6 +139,7 @@ static inline int ways_to_eiw(unsigned int ways, u8 *eiw)
 #define   CXL_ISOLATION_CAP_MEM_TIME_MASK GENMASK(3, 0)
 #define   CXL_ISOLATION_CAP_MEM_TIME_SUPP BIT(4)
 #define   CXL_ISOLATION_CAP_MEM_ISO_SUPP BIT(16)
+#define   CXL_ISOLATION_CAP_ERR_COR_SUPP BIT(25)
 #define   CXL_ISOLATION_CAP_INTR_SUPP BIT(26)
 #define   CXL_ISOLATION_CAP_INTR_MASK GENMASK(31, 27)
 #define CXL_ISOLATION_CTRL_OFFSET 0x8
@@ -629,6 +630,7 @@ struct cxl_dax_region {
  * @cdat: Cached CDAT data
  * @cdat_available: Should a CDAT attribute be available in sysfs
  * @pci_latency: Upstream latency in picoseconds
+ * @isolation_caps: Isolation capabilities given by platform firmware
  */
 struct cxl_port {
 	struct device dev;
@@ -654,6 +656,7 @@ struct cxl_port {
 	} cdat;
 	bool cdat_available;
 	long pci_latency;
+	u32 isolation_caps;
 };
 
 /**
@@ -679,6 +682,8 @@ struct cxl_root_ops {
 			 int *qos_class);
 	int (*setup_hostbridge_uport)(struct cxl_root *cxl_root,
 				      struct device *bridge_dev);
+	void (*get_isolation_caps)(struct cxl_port *hb,
+				   u32 iso_cap);
 };
 
 static inline struct cxl_dport *
diff --git a/include/cxl/isolation.h b/include/cxl/isolation.h
index f2c4feb5a42b..54b57c42e46e 100644
--- a/include/cxl/isolation.h
+++ b/include/cxl/isolation.h
@@ -4,6 +4,10 @@
 
 #include <linux/pci.h>
 
+/* CXL Isolation capabilities we have control over */
+#define CXL_ISOLATION_MEM_ENABLE BIT(0)
+#define CXL_ISOLATION_INTERRUPTS BIT(1)
+
 /**
  * enum cxl_err_results - Possible results of an CXL isolation handler
  * @CXL_ERR_NONE: Device can recover without CXL core intervention
-- 
2.34.1