* [PATCH v2 1/9] hw/arm/aspeed: Convert SRAM MemoryRegion to array type
2026-05-25 5:30 [PATCH v2 0/9] hw/arm/aspeed: Introduce initial AST1040 support Jamin Lin
@ 2026-05-25 5:30 ` Jamin Lin
2026-05-25 5:30 ` [PATCH v2 2/9] hw/arm/aspeed: Convert SRAM size definition " Jamin Lin
` (9 subsequent siblings)
10 siblings, 0 replies; 12+ messages in thread
From: Jamin Lin @ 2026-05-25 5:30 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Kane Chen, Andrew Jeffery, Joel Stanley, Pierrick Bouvier,
open list:ASPEED BMCs, open list:All patches CC here
Cc: Jamin Lin, Troy Lee
Several kinds of RAM are supported across Aspeed SoCs, including
SRAM, SDRAM, HyperRAM, secure SRAM, and generic SRAM. In addition,
different SoCs may expose multiple SRAM regions at different MMIO
addresses.
The current implementation models SRAM with a single MemoryRegion
instance, which makes future expansion cumbersome when additional
SRAM types or regions are introduced.
Prepare for future SoC designs by converting the SRAM MemoryRegion
from a single object into an array-based structure. This change
introduces ASPEED_SRAM_NUM and converts existing SRAM users to
reference sram[0].
No functional change.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
include/hw/arm/aspeed_soc.h | 3 ++-
hw/arm/aspeed_ast10x0.c | 5 +++--
hw/arm/aspeed_ast2400.c | 6 +++---
hw/arm/aspeed_ast2600.c | 6 +++---
hw/arm/aspeed_ast27x0.c | 4 ++--
5 files changed, 13 insertions(+), 11 deletions(-)
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index d7b3647ca1..e6942b2936 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -60,6 +60,7 @@
#define ASPEED_PCIE_NUM 3
#define ASPEED_INTC_NUM 2
#define ASPEED_IOEXP_NUM 2
+#define ASPEED_SRAM_NUM 1
struct AspeedSoCState {
DeviceState parent;
@@ -67,7 +68,7 @@ struct AspeedSoCState {
MemoryRegion *memory;
MemoryRegion *dram_mr;
MemoryRegion dram_container;
- MemoryRegion sram;
+ MemoryRegion sram[ASPEED_SRAM_NUM];
MemoryRegion spi_boot_container;
MemoryRegion spi_boot;
MemoryRegion vbootrom;
diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c
index 41a4e82c1f..3e478f7520 100644
--- a/hw/arm/aspeed_ast10x0.c
+++ b/hw/arm/aspeed_ast10x0.c
@@ -240,14 +240,15 @@ static bool aspeed_soc_ast10x0_realize(Aspeed10x0SoCState *a, Error **errp)
/* Internal SRAM */
sram_name = g_strdup_printf("aspeed.sram.%d",
CPU(a->armv7m.cpu)->cpu_index);
- memory_region_init_ram(&s->sram, OBJECT(s), sram_name, sc->sram_size, &err);
+ memory_region_init_ram(&s->sram[0], OBJECT(s), sram_name, sc->sram_size,
+ &err);
if (err != NULL) {
error_propagate(errp, err);
return false;
}
memory_region_add_subregion(s->memory,
sc->memmap[ASPEED_DEV_SRAM],
- &s->sram);
+ &s->sram[0]);
memory_region_init_ram(&s->secsram, OBJECT(s), "sec.sram",
sc->secsram_size, &err);
if (err != NULL) {
diff --git a/hw/arm/aspeed_ast2400.c b/hw/arm/aspeed_ast2400.c
index b1b826b7e0..d79aa832f3 100644
--- a/hw/arm/aspeed_ast2400.c
+++ b/hw/arm/aspeed_ast2400.c
@@ -281,12 +281,12 @@ static void aspeed_ast2400_soc_realize(DeviceState *dev, Error **errp)
/* SRAM */
sram_name = g_strdup_printf("aspeed.sram.%d", CPU(&a->cpu[0])->cpu_index);
- if (!memory_region_init_ram(&s->sram, OBJECT(s), sram_name, sc->sram_size,
- errp)) {
+ if (!memory_region_init_ram(&s->sram[0], OBJECT(s), sram_name,
+ sc->sram_size, errp)) {
return;
}
memory_region_add_subregion(s->memory,
- sc->memmap[ASPEED_DEV_SRAM], &s->sram);
+ sc->memmap[ASPEED_DEV_SRAM], &s->sram[0]);
/* SCU */
if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) {
diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c
index efb1d8c063..a69103de89 100644
--- a/hw/arm/aspeed_ast2600.c
+++ b/hw/arm/aspeed_ast2600.c
@@ -437,12 +437,12 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
/* SRAM */
sram_name = g_strdup_printf("aspeed.sram.%d", CPU(&a->cpu[0])->cpu_index);
- if (!memory_region_init_ram(&s->sram, OBJECT(s), sram_name, sc->sram_size,
- errp)) {
+ if (!memory_region_init_ram(&s->sram[0], OBJECT(s), sram_name,
+ sc->sram_size, errp)) {
return;
}
memory_region_add_subregion(s->memory,
- sc->memmap[ASPEED_DEV_SRAM], &s->sram);
+ sc->memmap[ASPEED_DEV_SRAM], &s->sram[0]);
/* DPMCU */
aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->dpmcu),
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
index 87dcb82e1b..0fb5e4b24c 100644
--- a/hw/arm/aspeed_ast27x0.c
+++ b/hw/arm/aspeed_ast27x0.c
@@ -778,12 +778,12 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
/* SRAM */
name = g_strdup_printf("aspeed.sram.%d", CPU(&a->cpu[0])->cpu_index);
- if (!memory_region_init_ram(&s->sram, OBJECT(s), name, sc->sram_size,
+ if (!memory_region_init_ram(&s->sram[0], OBJECT(s), name, sc->sram_size,
errp)) {
return;
}
memory_region_add_subregion(s->memory,
- sc->memmap[ASPEED_DEV_SRAM], &s->sram);
+ sc->memmap[ASPEED_DEV_SRAM], &s->sram[0]);
/* VBOOTROM */
if (!memory_region_init_ram(&s->vbootrom, OBJECT(s), "aspeed.vbootrom",
--
2.43.0
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH v2 2/9] hw/arm/aspeed: Convert SRAM size definition to array type
2026-05-25 5:30 [PATCH v2 0/9] hw/arm/aspeed: Introduce initial AST1040 support Jamin Lin
2026-05-25 5:30 ` [PATCH v2 1/9] hw/arm/aspeed: Convert SRAM MemoryRegion to array type Jamin Lin
@ 2026-05-25 5:30 ` Jamin Lin
2026-05-25 5:30 ` [PATCH v2 3/9] hw/arm/aspeed: Rename SRAM memmap entry for multi-SRAM support Jamin Lin
` (8 subsequent siblings)
10 siblings, 0 replies; 12+ messages in thread
From: Jamin Lin @ 2026-05-25 5:30 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Kane Chen, Andrew Jeffery, Joel Stanley, Pierrick Bouvier,
open list:ASPEED BMCs, open list:All patches CC here
Cc: Jamin Lin, Troy Lee
Prepare the Aspeed SoC model for future platforms that may contain
multiple SRAM regions with different sizes and MMIO mappings.
The current implementation stores SRAM size information in a single
sram_size field, which limits extensibility when additional SRAM
instances are introduced.
Convert sram_size into an array-based definition and update all
existing users to reference sram_size[0]. This aligns with the
previous SRAM MemoryRegion array conversion and provides a scalable
foundation for supporting multiple SRAM regions in future SoCs.
No functional change.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
include/hw/arm/aspeed_soc.h | 2 +-
hw/arm/aspeed_ast10x0.c | 8 ++++----
hw/arm/aspeed_ast2400.c | 6 +++---
hw/arm/aspeed_ast2600.c | 4 ++--
hw/arm/aspeed_ast27x0.c | 8 ++++----
5 files changed, 14 insertions(+), 14 deletions(-)
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index e6942b2936..3a7db959a9 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -172,7 +172,7 @@ struct AspeedSoCClass {
/** valid_cpu_types: NULL terminated array of a single CPU type. */
const char * const *valid_cpu_types;
uint32_t silicon_rev;
- uint64_t sram_size;
+ uint64_t sram_size[ASPEED_SRAM_NUM];
uint64_t secsram_size;
int pcie_num;
int spis_num;
diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c
index 3e478f7520..9e597a75ec 100644
--- a/hw/arm/aspeed_ast10x0.c
+++ b/hw/arm/aspeed_ast10x0.c
@@ -240,8 +240,8 @@ static bool aspeed_soc_ast10x0_realize(Aspeed10x0SoCState *a, Error **errp)
/* Internal SRAM */
sram_name = g_strdup_printf("aspeed.sram.%d",
CPU(a->armv7m.cpu)->cpu_index);
- memory_region_init_ram(&s->sram[0], OBJECT(s), sram_name, sc->sram_size,
- &err);
+ memory_region_init_ram(&s->sram[0], OBJECT(s), sram_name,
+ sc->sram_size[0], &err);
if (err != NULL) {
error_propagate(errp, err);
return false;
@@ -493,7 +493,7 @@ static void aspeed_soc_ast1030_class_init(ObjectClass *klass, const void *data)
sc->valid_cpu_types = valid_cpu_types;
sc->silicon_rev = AST1030_A1_SILICON_REV;
- sc->sram_size = 0xc0000;
+ sc->sram_size[0] = 0xc0000;
sc->secsram_size = 0x40000; /* 256 * KiB */
sc->spis_num = 2;
sc->ehcis_num = 0;
@@ -521,7 +521,7 @@ static void aspeed_soc_ast1060_class_init(ObjectClass *klass, const void *data)
sc->valid_cpu_types = valid_cpu_types;
sc->silicon_rev = AST1060_A2_SILICON_REV;
- sc->sram_size = 0xc0000;
+ sc->sram_size[0] = 0xc0000;
sc->secsram_size = 0x40000; /* 256 * KiB */
sc->spis_num = 2;
sc->wdts_num = 4;
diff --git a/hw/arm/aspeed_ast2400.c b/hw/arm/aspeed_ast2400.c
index d79aa832f3..c4e5388999 100644
--- a/hw/arm/aspeed_ast2400.c
+++ b/hw/arm/aspeed_ast2400.c
@@ -282,7 +282,7 @@ static void aspeed_ast2400_soc_realize(DeviceState *dev, Error **errp)
/* SRAM */
sram_name = g_strdup_printf("aspeed.sram.%d", CPU(&a->cpu[0])->cpu_index);
if (!memory_region_init_ram(&s->sram[0], OBJECT(s), sram_name,
- sc->sram_size, errp)) {
+ sc->sram_size[0], errp)) {
return;
}
memory_region_add_subregion(s->memory,
@@ -533,7 +533,7 @@ static void aspeed_soc_ast2400_class_init(ObjectClass *oc, const void *data)
sc->valid_cpu_types = valid_cpu_types;
sc->silicon_rev = AST2400_A1_SILICON_REV;
- sc->sram_size = 0x8000;
+ sc->sram_size[0] = 0x8000;
sc->spis_num = 1;
sc->ehcis_num = 1;
sc->wdts_num = 2;
@@ -560,7 +560,7 @@ static void aspeed_soc_ast2500_class_init(ObjectClass *oc, const void *data)
sc->valid_cpu_types = valid_cpu_types;
sc->silicon_rev = AST2500_A1_SILICON_REV;
- sc->sram_size = 0x9000;
+ sc->sram_size[0] = 0x9000;
sc->spis_num = 2;
sc->ehcis_num = 2;
sc->wdts_num = 3;
diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c
index a69103de89..2f8f49a376 100644
--- a/hw/arm/aspeed_ast2600.c
+++ b/hw/arm/aspeed_ast2600.c
@@ -438,7 +438,7 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
/* SRAM */
sram_name = g_strdup_printf("aspeed.sram.%d", CPU(&a->cpu[0])->cpu_index);
if (!memory_region_init_ram(&s->sram[0], OBJECT(s), sram_name,
- sc->sram_size, errp)) {
+ sc->sram_size[0], errp)) {
return;
}
memory_region_add_subregion(s->memory,
@@ -764,7 +764,7 @@ static void aspeed_soc_ast2600_class_init(ObjectClass *oc, const void *data)
sc->valid_cpu_types = valid_cpu_types;
sc->silicon_rev = AST2600_A3_SILICON_REV;
- sc->sram_size = 0x16400;
+ sc->sram_size[0] = 0x16400;
sc->spis_num = 2;
sc->ehcis_num = 2;
sc->wdts_num = 4;
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
index 0fb5e4b24c..30883ea7ce 100644
--- a/hw/arm/aspeed_ast27x0.c
+++ b/hw/arm/aspeed_ast27x0.c
@@ -778,8 +778,8 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
/* SRAM */
name = g_strdup_printf("aspeed.sram.%d", CPU(&a->cpu[0])->cpu_index);
- if (!memory_region_init_ram(&s->sram[0], OBJECT(s), name, sc->sram_size,
- errp)) {
+ if (!memory_region_init_ram(&s->sram[0], OBJECT(s), name,
+ sc->sram_size[0], errp)) {
return;
}
memory_region_add_subregion(s->memory,
@@ -1151,7 +1151,7 @@ static void aspeed_soc_ast2700a1_class_init(ObjectClass *oc, const void *data)
sc->valid_cpu_types = valid_cpu_types;
sc->silicon_rev = AST2700_A1_SILICON_REV;
- sc->sram_size = 0x20000;
+ sc->sram_size[0] = 0x20000;
sc->pcie_num = 3;
sc->spis_num = 3;
sc->sgpio_num = 2;
@@ -1181,7 +1181,7 @@ static void aspeed_soc_ast2700a2_class_init(ObjectClass *oc, const void *data)
sc->valid_cpu_types = valid_cpu_types;
sc->silicon_rev = AST2700_A2_SILICON_REV;
- sc->sram_size = 0x20000;
+ sc->sram_size[0] = 0x20000;
sc->pcie_num = 3;
sc->spis_num = 3;
sc->sgpio_num = 2;
--
2.43.0
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH v2 3/9] hw/arm/aspeed: Rename SRAM memmap entry for multi-SRAM support
2026-05-25 5:30 [PATCH v2 0/9] hw/arm/aspeed: Introduce initial AST1040 support Jamin Lin
2026-05-25 5:30 ` [PATCH v2 1/9] hw/arm/aspeed: Convert SRAM MemoryRegion to array type Jamin Lin
2026-05-25 5:30 ` [PATCH v2 2/9] hw/arm/aspeed: Convert SRAM size definition " Jamin Lin
@ 2026-05-25 5:30 ` Jamin Lin
2026-05-25 5:30 ` [PATCH v2 4/9] hw/arm/aspeed: Consolidate secure SRAM into SRAM array Jamin Lin
` (7 subsequent siblings)
10 siblings, 0 replies; 12+ messages in thread
From: Jamin Lin @ 2026-05-25 5:30 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Kane Chen, Andrew Jeffery, Joel Stanley, Pierrick Bouvier,
open list:ASPEED BMCs, open list:All patches CC here
Cc: Jamin Lin, Troy Lee
Some Aspeed SoCs contain multiple SRAM regions with different
MMIO mappings, such as internal SRAM and secure SRAM.
Prepare for future multi-SRAM support by renaming the SRAM
memmap entry from ASPEED_DEV_SRAM to ASPEED_DEV_SRAM0.
This makes the numbering explicit and aligns with the
array-based SRAM representation introduced previously.
No functional change.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
include/hw/arm/aspeed_soc.h | 2 +-
hw/arm/aspeed_ast10x0.c | 4 ++--
hw/arm/aspeed_ast2400.c | 6 +++---
hw/arm/aspeed_ast2600.c | 4 ++--
hw/arm/aspeed_ast27x0-ssp.c | 4 ++--
hw/arm/aspeed_ast27x0-tsp.c | 4 ++--
hw/arm/aspeed_ast27x0.c | 4 ++--
7 files changed, 14 insertions(+), 14 deletions(-)
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index 3a7db959a9..dda602e9f2 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -228,7 +228,7 @@ enum {
ASPEED_DEV_SECSRAM,
ASPEED_DEV_EMMC_BC,
ASPEED_DEV_VIDEO,
- ASPEED_DEV_SRAM,
+ ASPEED_DEV_SRAM0,
ASPEED_DEV_SDHCI,
ASPEED_DEV_GPIO,
ASPEED_DEV_GPIO_1_8V,
diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c
index 9e597a75ec..b55f788342 100644
--- a/hw/arm/aspeed_ast10x0.c
+++ b/hw/arm/aspeed_ast10x0.c
@@ -20,7 +20,7 @@
#define ASPEED_SOC_IOMEM_SIZE 0x00200000
static const hwaddr aspeed_soc_ast1030_memmap[] = {
- [ASPEED_DEV_SRAM] = 0x00000000,
+ [ASPEED_DEV_SRAM0] = 0x00000000,
[ASPEED_DEV_SECSRAM] = 0x79000000,
[ASPEED_DEV_IOMEM] = 0x7E600000,
[ASPEED_DEV_PWM] = 0x7E610000,
@@ -247,7 +247,7 @@ static bool aspeed_soc_ast10x0_realize(Aspeed10x0SoCState *a, Error **errp)
return false;
}
memory_region_add_subregion(s->memory,
- sc->memmap[ASPEED_DEV_SRAM],
+ sc->memmap[ASPEED_DEV_SRAM0],
&s->sram[0]);
memory_region_init_ram(&s->secsram, OBJECT(s), "sec.sram",
sc->secsram_size, &err);
diff --git a/hw/arm/aspeed_ast2400.c b/hw/arm/aspeed_ast2400.c
index c4e5388999..79a653f65f 100644
--- a/hw/arm/aspeed_ast2400.c
+++ b/hw/arm/aspeed_ast2400.c
@@ -38,7 +38,7 @@ static const hwaddr aspeed_soc_ast2400_memmap[] = {
[ASPEED_DEV_XDMA] = 0x1E6E7000,
[ASPEED_DEV_VIDEO] = 0x1E700000,
[ASPEED_DEV_ADC] = 0x1E6E9000,
- [ASPEED_DEV_SRAM] = 0x1E720000,
+ [ASPEED_DEV_SRAM0] = 0x1E720000,
[ASPEED_DEV_SDHCI] = 0x1E740000,
[ASPEED_DEV_GPIO] = 0x1E780000,
[ASPEED_DEV_RTC] = 0x1E781000,
@@ -75,7 +75,7 @@ static const hwaddr aspeed_soc_ast2500_memmap[] = {
[ASPEED_DEV_XDMA] = 0x1E6E7000,
[ASPEED_DEV_ADC] = 0x1E6E9000,
[ASPEED_DEV_VIDEO] = 0x1E700000,
- [ASPEED_DEV_SRAM] = 0x1E720000,
+ [ASPEED_DEV_SRAM0] = 0x1E720000,
[ASPEED_DEV_SDHCI] = 0x1E740000,
[ASPEED_DEV_GPIO] = 0x1E780000,
[ASPEED_DEV_RTC] = 0x1E781000,
@@ -286,7 +286,7 @@ static void aspeed_ast2400_soc_realize(DeviceState *dev, Error **errp)
return;
}
memory_region_add_subregion(s->memory,
- sc->memmap[ASPEED_DEV_SRAM], &s->sram[0]);
+ sc->memmap[ASPEED_DEV_SRAM0], &s->sram[0]);
/* SCU */
if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) {
diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c
index 2f8f49a376..d1f18e471a 100644
--- a/hw/arm/aspeed_ast2600.c
+++ b/hw/arm/aspeed_ast2600.c
@@ -23,7 +23,7 @@
static const hwaddr aspeed_soc_ast2600_memmap[] = {
[ASPEED_DEV_SPI_BOOT] = 0x00000000,
- [ASPEED_DEV_SRAM] = 0x10000000,
+ [ASPEED_DEV_SRAM0] = 0x10000000,
[ASPEED_DEV_DPMCU] = 0x18000000,
/* 0x16000000 0x17FFFFFF : AHB BUS do LPC Bus bridge */
[ASPEED_DEV_IOMEM] = 0x1E600000,
@@ -442,7 +442,7 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
return;
}
memory_region_add_subregion(s->memory,
- sc->memmap[ASPEED_DEV_SRAM], &s->sram[0]);
+ sc->memmap[ASPEED_DEV_SRAM0], &s->sram[0]);
/* DPMCU */
aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->dpmcu),
diff --git a/hw/arm/aspeed_ast27x0-ssp.c b/hw/arm/aspeed_ast27x0-ssp.c
index 8b84300e0f..b3c4eb1915 100644
--- a/hw/arm/aspeed_ast27x0-ssp.c
+++ b/hw/arm/aspeed_ast27x0-ssp.c
@@ -20,7 +20,7 @@
static const hwaddr aspeed_soc_ast27x0ssp_memmap[] = {
[ASPEED_DEV_SDRAM] = 0x00000000,
- [ASPEED_DEV_SRAM] = 0x70000000,
+ [ASPEED_DEV_SRAM0] = 0x70000000,
[ASPEED_DEV_INTC] = 0x72100000,
[ASPEED_DEV_SCU] = 0x72C02000,
[ASPEED_DEV_TIMER1] = 0x72C10000,
@@ -182,7 +182,7 @@ static void aspeed_soc_ast27x0ssp_realize(DeviceState *dev_soc, Error **errp)
/* SRAM */
memory_region_init_alias(&s->sram_alias, OBJECT(s), "sram.alias",
s->sram, 0, memory_region_size(s->sram));
- memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SRAM],
+ memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SRAM0],
&s->sram_alias);
/* SCU */
diff --git a/hw/arm/aspeed_ast27x0-tsp.c b/hw/arm/aspeed_ast27x0-tsp.c
index e7c7b74491..6098d1aae3 100644
--- a/hw/arm/aspeed_ast27x0-tsp.c
+++ b/hw/arm/aspeed_ast27x0-tsp.c
@@ -20,7 +20,7 @@
static const hwaddr aspeed_soc_ast27x0tsp_memmap[] = {
[ASPEED_DEV_SDRAM] = 0x00000000,
- [ASPEED_DEV_SRAM] = 0x70000000,
+ [ASPEED_DEV_SRAM0] = 0x70000000,
[ASPEED_DEV_INTC] = 0x72100000,
[ASPEED_DEV_SCU] = 0x72C02000,
[ASPEED_DEV_TIMER1] = 0x72C10000,
@@ -182,7 +182,7 @@ static void aspeed_soc_ast27x0tsp_realize(DeviceState *dev_soc, Error **errp)
/* SRAM */
memory_region_init_alias(&s->sram_alias, OBJECT(s), "sram.alias",
s->sram, 0, memory_region_size(s->sram));
- memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SRAM],
+ memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SRAM0],
&s->sram_alias);
/* SCU */
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
index 30883ea7ce..d7ce14e8c5 100644
--- a/hw/arm/aspeed_ast27x0.c
+++ b/hw/arm/aspeed_ast27x0.c
@@ -30,7 +30,7 @@
static const hwaddr aspeed_soc_ast2700_memmap[] = {
[ASPEED_DEV_VBOOTROM] = 0x00000000,
[ASPEED_DEV_IOMEM] = 0x00020000,
- [ASPEED_DEV_SRAM] = 0x10000000,
+ [ASPEED_DEV_SRAM0] = 0x10000000,
[ASPEED_DEV_DPMCU] = 0x11000000,
[ASPEED_DEV_IOMEM0] = 0x12000000,
[ASPEED_DEV_EHCI1] = 0x12061000,
@@ -783,7 +783,7 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
return;
}
memory_region_add_subregion(s->memory,
- sc->memmap[ASPEED_DEV_SRAM], &s->sram[0]);
+ sc->memmap[ASPEED_DEV_SRAM0], &s->sram[0]);
/* VBOOTROM */
if (!memory_region_init_ram(&s->vbootrom, OBJECT(s), "aspeed.vbootrom",
--
2.43.0
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH v2 4/9] hw/arm/aspeed: Consolidate secure SRAM into SRAM array
2026-05-25 5:30 [PATCH v2 0/9] hw/arm/aspeed: Introduce initial AST1040 support Jamin Lin
` (2 preceding siblings ...)
2026-05-25 5:30 ` [PATCH v2 3/9] hw/arm/aspeed: Rename SRAM memmap entry for multi-SRAM support Jamin Lin
@ 2026-05-25 5:30 ` Jamin Lin
2026-05-25 5:30 ` [PATCH v2 5/9] hw/misc/aspeed_scu: Add AST1040 A0 silicon revision ID Jamin Lin
` (6 subsequent siblings)
10 siblings, 0 replies; 12+ messages in thread
From: Jamin Lin @ 2026-05-25 5:30 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Kane Chen, Andrew Jeffery, Joel Stanley, Pierrick Bouvier,
open list:ASPEED BMCs, open list:All patches CC here
Cc: Jamin Lin, Troy Lee
Some Aspeed SoCs contain multiple SRAM regions with different
sizes and MMIO mappings, such as internal SRAM and secure SRAM.
The current implementation models secure SRAM separately from the
generic SRAM representation, which complicates future multi-SRAM
support and expansion.
Increase ASPEED_SRAM_NUM to 2 and migrate secure SRAM to use the
common SRAM array representation. Rename the secure SRAM memmap
entry to ASPEED_DEV_SRAM1 and update AST10x0 to initialize both
SRAM regions through sram[] and sram_size[].
This unifies SRAM-like regions under a common representation and
prepares for future SoCs with additional SRAM regions.
No functional change.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
include/hw/arm/aspeed_soc.h | 6 ++----
hw/arm/aspeed_ast10x0.c | 16 +++++++++-------
2 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index dda602e9f2..3aac144cd4 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -60,7 +60,7 @@
#define ASPEED_PCIE_NUM 3
#define ASPEED_INTC_NUM 2
#define ASPEED_IOEXP_NUM 2
-#define ASPEED_SRAM_NUM 1
+#define ASPEED_SRAM_NUM 2
struct AspeedSoCState {
DeviceState parent;
@@ -89,7 +89,6 @@ struct AspeedSoCState {
AspeedSBCState sbc;
AspeedSLIState sli;
AspeedSLIState sliio;
- MemoryRegion secsram;
UnimplementedDeviceState sbc_unimplemented;
AspeedSDMCState sdmc;
AspeedPWMState pwm;
@@ -173,7 +172,6 @@ struct AspeedSoCClass {
const char * const *valid_cpu_types;
uint32_t silicon_rev;
uint64_t sram_size[ASPEED_SRAM_NUM];
- uint64_t secsram_size;
int pcie_num;
int spis_num;
int sgpio_num;
@@ -225,10 +223,10 @@ enum {
ASPEED_DEV_SCU,
ASPEED_DEV_ADC,
ASPEED_DEV_SBC,
- ASPEED_DEV_SECSRAM,
ASPEED_DEV_EMMC_BC,
ASPEED_DEV_VIDEO,
ASPEED_DEV_SRAM0,
+ ASPEED_DEV_SRAM1,
ASPEED_DEV_SDHCI,
ASPEED_DEV_GPIO,
ASPEED_DEV_GPIO_1_8V,
diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c
index b55f788342..93c81195b5 100644
--- a/hw/arm/aspeed_ast10x0.c
+++ b/hw/arm/aspeed_ast10x0.c
@@ -21,7 +21,7 @@
static const hwaddr aspeed_soc_ast1030_memmap[] = {
[ASPEED_DEV_SRAM0] = 0x00000000,
- [ASPEED_DEV_SECSRAM] = 0x79000000,
+ [ASPEED_DEV_SRAM1] = 0x79000000, /* SEC SRAM */
[ASPEED_DEV_IOMEM] = 0x7E600000,
[ASPEED_DEV_PWM] = 0x7E610000,
[ASPEED_DEV_FMC] = 0x7E620000,
@@ -249,14 +249,16 @@ static bool aspeed_soc_ast10x0_realize(Aspeed10x0SoCState *a, Error **errp)
memory_region_add_subregion(s->memory,
sc->memmap[ASPEED_DEV_SRAM0],
&s->sram[0]);
- memory_region_init_ram(&s->secsram, OBJECT(s), "sec.sram",
- sc->secsram_size, &err);
+
+ /* Internal SEC SRAM */
+ memory_region_init_ram(&s->sram[1], OBJECT(s), "sec.sram",
+ sc->sram_size[1], &err);
if (err != NULL) {
error_propagate(errp, err);
return false;
}
- memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SECSRAM],
- &s->secsram);
+ memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SRAM1],
+ &s->sram[1]);
/* SCU */
if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) {
@@ -494,7 +496,7 @@ static void aspeed_soc_ast1030_class_init(ObjectClass *klass, const void *data)
sc->valid_cpu_types = valid_cpu_types;
sc->silicon_rev = AST1030_A1_SILICON_REV;
sc->sram_size[0] = 0xc0000;
- sc->secsram_size = 0x40000; /* 256 * KiB */
+ sc->sram_size[1] = 0x40000; /* SEC SRAM 256 * KiB */
sc->spis_num = 2;
sc->ehcis_num = 0;
sc->wdts_num = 4;
@@ -522,7 +524,7 @@ static void aspeed_soc_ast1060_class_init(ObjectClass *klass, const void *data)
sc->valid_cpu_types = valid_cpu_types;
sc->silicon_rev = AST1060_A2_SILICON_REV;
sc->sram_size[0] = 0xc0000;
- sc->secsram_size = 0x40000; /* 256 * KiB */
+ sc->sram_size[1] = 0x40000; /* SEC SRAM 256 * KiB */
sc->spis_num = 2;
sc->wdts_num = 4;
sc->uarts_num = 1;
--
2.43.0
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH v2 5/9] hw/misc/aspeed_scu: Add AST1040 A0 silicon revision ID
2026-05-25 5:30 [PATCH v2 0/9] hw/arm/aspeed: Introduce initial AST1040 support Jamin Lin
` (3 preceding siblings ...)
2026-05-25 5:30 ` [PATCH v2 4/9] hw/arm/aspeed: Consolidate secure SRAM into SRAM array Jamin Lin
@ 2026-05-25 5:30 ` Jamin Lin
2026-05-25 5:30 ` [PATCH v2 6/9] hw/arm/aspeed: Introduce AST1040 A0 SoC model Jamin Lin
` (5 subsequent siblings)
10 siblings, 0 replies; 12+ messages in thread
From: Jamin Lin @ 2026-05-25 5:30 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Kane Chen, Andrew Jeffery, Joel Stanley, Pierrick Bouvier,
open list:ASPEED BMCs, open list:All patches CC here
Cc: Jamin Lin, Troy Lee
Add the AST1040 A0 silicon revision definition and register it
in the supported Aspeed silicon revision table.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
include/hw/misc/aspeed_scu.h | 1 +
hw/misc/aspeed_scu.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/include/hw/misc/aspeed_scu.h b/include/hw/misc/aspeed_scu.h
index d003955428..c30940ab76 100644
--- a/include/hw/misc/aspeed_scu.h
+++ b/include/hw/misc/aspeed_scu.h
@@ -46,6 +46,7 @@ struct AspeedSCUState {
#define AST2600_A3_SILICON_REV 0x05030303U
#define AST1030_A1_SILICON_REV 0x80010000U
#define AST1060_A2_SILICON_REV 0xA0030000U
+#define AST1040_A0_SILICON_REV 0x81000000U
#define AST2700_A1_SILICON_REV 0x06010103U
#define AST2700_A2_SILICON_REV 0x06020103U
diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c
index e4160356e4..507dc4ea9f 100644
--- a/hw/misc/aspeed_scu.c
+++ b/hw/misc/aspeed_scu.c
@@ -562,6 +562,7 @@ static uint32_t aspeed_silicon_revs[] = {
AST1060_A2_SILICON_REV,
AST2700_A1_SILICON_REV,
AST2700_A2_SILICON_REV,
+ AST1040_A0_SILICON_REV,
};
bool is_supported_silicon_rev(uint32_t silicon_rev)
--
2.43.0
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH v2 6/9] hw/arm/aspeed: Introduce AST1040 A0 SoC model
2026-05-25 5:30 [PATCH v2 0/9] hw/arm/aspeed: Introduce initial AST1040 support Jamin Lin
` (4 preceding siblings ...)
2026-05-25 5:30 ` [PATCH v2 5/9] hw/misc/aspeed_scu: Add AST1040 A0 silicon revision ID Jamin Lin
@ 2026-05-25 5:30 ` Jamin Lin
2026-05-25 5:30 ` [PATCH v2 7/9] hw/arm/aspeed: Add AST1040 EVB machine model Jamin Lin
` (4 subsequent siblings)
10 siblings, 0 replies; 12+ messages in thread
From: Jamin Lin @ 2026-05-25 5:30 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Kane Chen, Andrew Jeffery, Joel Stanley, Pierrick Bouvier,
open list:ASPEED BMCs, open list:All patches CC here
Cc: Jamin Lin, Troy Lee
The AST1040 is based on an ARM Cortex-M4F CPU core. Since QEMU
currently does not provide Cortex-M4F support, use the existing
Cortex-M4 CPU model as a temporary replacement.
This initial implementation provides the basic infrastructure
required to boot firmware and run a minimal firmware shell,
including:
- ARM Cortex-M4 CPU integration
- NVIC interrupt controller support
- Internal HyperRAM and SRAM memory regions
- SCU integration
- UART devices and interrupt wiring
AST1040 SCU behavior is compatible with the AST2700 SCUIO model,
so reuse the existing AST2700 SCUIO implementation directly
instead of introducing another identical SCU model. This reduces
duplicate code and helps minimize long-term codebase maintenance.
Several peripherals are currently modeled as unimplemented
devices and can be added incrementally in future updates.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
hw/arm/aspeed_ast1040.c | 254 ++++++++++++++++++++++++++++++++++++++++
hw/arm/meson.build | 3 +-
2 files changed, 256 insertions(+), 1 deletion(-)
create mode 100644 hw/arm/aspeed_ast1040.c
diff --git a/hw/arm/aspeed_ast1040.c b/hw/arm/aspeed_ast1040.c
new file mode 100644
index 0000000000..8efcdad8f6
--- /dev/null
+++ b/hw/arm/aspeed_ast1040.c
@@ -0,0 +1,254 @@
+/*
+ * ASPEED AST1040 SoC
+ *
+ * Copyright (C) 2026 ASPEED Technology Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "system/address-spaces.h"
+#include "system/system.h"
+#include "hw/core/qdev-clock.h"
+#include "hw/misc/unimp.h"
+#include "hw/arm/aspeed_soc.h"
+
+static const hwaddr aspeed_soc_ast1040_memmap[] = {
+ [ASPEED_DEV_SRAM1] = 0x00000000, /* Hyper RAM */
+ [ASPEED_DEV_FMC] = 0x74000000,
+ [ASPEED_DEV_SPI0] = 0x74010000,
+ [ASPEED_DEV_SPI1] = 0x74020000,
+ [ASPEED_DEV_PWM] = 0x740C0000,
+ [ASPEED_DEV_UDC] = 0x74120000,
+ [ASPEED_DEV_SRAM0] = 0x74B80000,
+ [ASPEED_DEV_ADC] = 0x74C00000,
+ [ASPEED_DEV_JTAG0] = 0x74C01000,
+ [ASPEED_DEV_SCU] = 0x74C02000,
+ [ASPEED_DEV_ESPI] = 0x74C05000,
+ [ASPEED_DEV_JTAG1] = 0x74C09000,
+ [ASPEED_DEV_GPIO] = 0x74C0B000,
+ [ASPEED_DEV_SGPIOM0] = 0x74C0C000,
+ [ASPEED_DEV_SGPIOM1] = 0x74C0D000,
+ [ASPEED_DEV_I2C] = 0x74C0F000,
+ [ASPEED_DEV_I3C] = 0x74C20000,
+ [ASPEED_DEV_UART0] = 0x74C33000,
+ [ASPEED_DEV_UART1] = 0x74C33100,
+ [ASPEED_DEV_UART2] = 0x74C33200,
+ [ASPEED_DEV_UART3] = 0x74C33300,
+ [ASPEED_DEV_UART4] = 0x74C33400,
+ [ASPEED_DEV_UART5] = 0x74C33500,
+ [ASPEED_DEV_UART6] = 0x74C33600,
+ [ASPEED_DEV_UART7] = 0x74C33700,
+ [ASPEED_DEV_UART8] = 0x74C33800,
+ [ASPEED_DEV_UART9] = 0x74C33900,
+ [ASPEED_DEV_UART10] = 0x74C33A00,
+ [ASPEED_DEV_UART11] = 0x74C33B00,
+ [ASPEED_DEV_UART12] = 0x74C33C00,
+ [ASPEED_DEV_WDT] = 0x74C37000,
+ [ASPEED_DEV_TIMER1] = 0x74C3A000,
+};
+
+static const int aspeed_soc_ast1040_irqmap[] = {
+ [ASPEED_DEV_ESPI] = 10,
+ [ASPEED_DEV_I2C] = 64, /* 64 ~ 77 */
+ [ASPEED_DEV_ADC] = 80,
+ [ASPEED_DEV_GPIO] = 82,
+ [ASPEED_DEV_SGPIOM0] = 85,
+ [ASPEED_DEV_TIMER1] = 92,
+ [ASPEED_DEV_I3C] = 96, /* 96 ~ 103 */
+ [ASPEED_DEV_WDT] = 112,
+ [ASPEED_DEV_FMC] = 121,
+ [ASPEED_DEV_SPI0] = 122,
+ [ASPEED_DEV_SPI1] = 123,
+ [ASPEED_DEV_PWM] = 125,
+ [ASPEED_DEV_UART0] = 135,
+ [ASPEED_DEV_UART1] = 136,
+ [ASPEED_DEV_UART2] = 137,
+ [ASPEED_DEV_UART3] = 138,
+ [ASPEED_DEV_UART4] = 139,
+ [ASPEED_DEV_UART5] = 140,
+ [ASPEED_DEV_UART6] = 141,
+ [ASPEED_DEV_UART7] = 142,
+ [ASPEED_DEV_UART8] = 143,
+ [ASPEED_DEV_UART9] = 144,
+ [ASPEED_DEV_UART10] = 145,
+ [ASPEED_DEV_UART11] = 146,
+ [ASPEED_DEV_UART12] = 147,
+ [ASPEED_DEV_JTAG0] = 162,
+};
+
+static qemu_irq aspeed_soc_ast1040_get_irq(AspeedSoCState *s, int dev)
+{
+ Aspeed10x0SoCState *a = ASPEED10X0_SOC(s);
+ AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
+
+ return qdev_get_gpio_in(DEVICE(&a->armv7m), sc->irqmap[dev]);
+}
+
+static void aspeed_soc_ast1040_init(Object *obj)
+{
+ Aspeed10x0SoCState *a = ASPEED10X0_SOC(obj);
+ AspeedSoCState *s = ASPEED_SOC(obj);
+ AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
+ int i;
+ object_initialize_child(obj, "armv7m", &a->armv7m, TYPE_ARMV7M);
+
+ s->sysclk = qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0);
+
+ /* AST1040 uses the AST2700 SCUIO model */
+ object_initialize_child(obj, "scu", &s->scu, TYPE_ASPEED_2700_SCUIO);
+ qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev", sc->silicon_rev);
+
+ object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu), "hw-strap1");
+ object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu), "hw-strap2");
+
+ for (i = 0; i < sc->uarts_num; i++) {
+ object_initialize_child(obj, "uart[*]", &s->uart[i], TYPE_SERIAL_MM);
+ }
+
+ object_initialize_child(obj, "pwm", &s->pwm, TYPE_UNIMPLEMENTED_DEVICE);
+ object_initialize_child(obj, "espi", &s->espi, TYPE_UNIMPLEMENTED_DEVICE);
+ object_initialize_child(obj, "udc", &s->udc, TYPE_UNIMPLEMENTED_DEVICE);
+ object_initialize_child(obj, "sgpiom[0]", &s->sgpiom[0],
+ TYPE_UNIMPLEMENTED_DEVICE);
+ object_initialize_child(obj, "sgpiom[1]", &s->sgpiom[1],
+ TYPE_UNIMPLEMENTED_DEVICE);
+ object_initialize_child(obj, "jtag[0]", &s->jtag[0],
+ TYPE_UNIMPLEMENTED_DEVICE);
+ object_initialize_child(obj, "jtag[1]", &s->jtag[1],
+ TYPE_UNIMPLEMENTED_DEVICE);
+}
+
+static void aspeed_soc_ast1040_realize(DeviceState *dev_soc, Error **errp)
+{
+ Aspeed10x0SoCState *a = ASPEED10X0_SOC(dev_soc);
+ AspeedSoCState *s = ASPEED_SOC(dev_soc);
+ AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
+ g_autofree char *hyperram_name = NULL;
+ g_autofree char *sram_name = NULL;
+ DeviceState *armv7m;
+ Error *err = NULL;
+ int uart;
+ int i;
+
+ if (!clock_has_source(s->sysclk)) {
+ error_setg(errp, "sysclk clock must be wired up by the board code");
+ return;
+ }
+
+ /* AST1040 CPU Core */
+ armv7m = DEVICE(&a->armv7m);
+ qdev_prop_set_uint32(armv7m, "num-irq", 256);
+ qdev_prop_set_string(armv7m, "cpu-type",
+ aspeed_soc_cpu_type(sc->valid_cpu_types));
+ qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk);
+ object_property_set_link(OBJECT(&a->armv7m), "memory",
+ OBJECT(s->memory), &error_abort);
+ sysbus_realize(SYS_BUS_DEVICE(&a->armv7m), &error_abort);
+
+ /* Internal SRAM */
+ sram_name = g_strdup_printf("aspeed.sram.%d",
+ CPU(a->armv7m.cpu)->cpu_index);
+ memory_region_init_ram(&s->sram[0], OBJECT(s), sram_name,
+ sc->sram_size[0], &err);
+ if (err) {
+ error_propagate(errp, err);
+ return;
+ }
+ memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SRAM0],
+ &s->sram[0]);
+
+ /* Internal Hyper RAM */
+ hyperram_name = g_strdup_printf("aspeed.hyperram.%d",
+ CPU(a->armv7m.cpu)->cpu_index);
+ memory_region_init_ram(&s->sram[1], OBJECT(s), hyperram_name,
+ sc->sram_size[1], &err);
+ if (err) {
+ error_propagate(errp, err);
+ return;
+ }
+ memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SRAM1],
+ &s->sram[1]);
+
+ /* SCU */
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) {
+ return;
+ }
+ aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->scu), 0,
+ sc->memmap[ASPEED_DEV_SCU]);
+
+ /* UART */
+ for (i = 0, uart = sc->uarts_base; i < sc->uarts_num; i++, uart++) {
+ if (!aspeed_soc_uart_realize(s->memory, &s->uart[i],
+ sc->memmap[uart], errp)) {
+ return;
+ }
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
+ aspeed_soc_ast1040_get_irq(s, uart));
+ }
+
+ /* Unimplemented peripherals */
+ aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->pwm),
+ "aspeed.pwm",
+ sc->memmap[ASPEED_DEV_PWM], 0x10000);
+
+ aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->espi),
+ "aspeed.espi",
+ sc->memmap[ASPEED_DEV_ESPI], 0x1000);
+
+ aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->udc),
+ "aspeed.udc",
+ sc->memmap[ASPEED_DEV_UDC], 0x4000);
+
+ aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->sgpiom[0]),
+ "aspeed.sgpiom0",
+ sc->memmap[ASPEED_DEV_SGPIOM0], 0x1000);
+
+ aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->sgpiom[1]),
+ "aspeed.sgpiom1",
+ sc->memmap[ASPEED_DEV_SGPIOM1], 0x1000);
+
+ aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->jtag[0]),
+ "aspeed.jtag0",
+ sc->memmap[ASPEED_DEV_JTAG0], 0x100);
+
+ aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->jtag[1]),
+ "aspeed.jtag1",
+ sc->memmap[ASPEED_DEV_JTAG1], 0x100);
+}
+
+static void aspeed_soc_ast1040_class_init(ObjectClass *klass, const void *data)
+{
+ static const char * const valid_cpu_types[] = {
+ ARM_CPU_TYPE_NAME("cortex-m4"), /* TODO cortex-m4f */
+ NULL
+ };
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ AspeedSoCClass *sc = ASPEED_SOC_CLASS(dc);
+
+ /* Reason: The Aspeed SoC can only be instantiated from a board */
+ dc->user_creatable = false;
+ dc->realize = aspeed_soc_ast1040_realize;
+
+ sc->valid_cpu_types = valid_cpu_types;
+ sc->silicon_rev = AST1040_A0_SILICON_REV;
+ sc->sram_size[0] = 128 * KiB;
+ sc->sram_size[1] = 16 * MiB; /* Hyper RAM */
+ sc->uarts_num = 13;
+ sc->uarts_base = ASPEED_DEV_UART0;
+ sc->irqmap = aspeed_soc_ast1040_irqmap;
+ sc->memmap = aspeed_soc_ast1040_memmap;
+ sc->num_cpus = 1;
+}
+
+static const TypeInfo aspeed_soc_ast1040_types[] = {
+ {
+ .name = "ast1040-a0",
+ .parent = TYPE_ASPEED10X0_SOC,
+ .instance_init = aspeed_soc_ast1040_init,
+ .class_init = aspeed_soc_ast1040_class_init,
+ }
+};
+
+DEFINE_TYPES(aspeed_soc_ast1040_types)
diff --git a/hw/arm/meson.build b/hw/arm/meson.build
index 80068f70bb..fa3a848492 100644
--- a/hw/arm/meson.build
+++ b/hw/arm/meson.build
@@ -62,7 +62,8 @@ arm_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files(
'aspeed_ast2600_gb200nvl.c',
'aspeed_ast2600_rainier.c',
'aspeed_ast10x0.c',
- 'aspeed_ast10x0_evb.c'))
+ 'aspeed_ast10x0_evb.c',
+ 'aspeed_ast1040.c'))
arm_common_ss.add(when: ['CONFIG_ASPEED_SOC', 'TARGET_AARCH64'], if_true: files(
'aspeed_ast1700.c',
'aspeed_ast27x0.c',
--
2.43.0
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH v2 7/9] hw/arm/aspeed: Add AST1040 EVB machine model
2026-05-25 5:30 [PATCH v2 0/9] hw/arm/aspeed: Introduce initial AST1040 support Jamin Lin
` (5 preceding siblings ...)
2026-05-25 5:30 ` [PATCH v2 6/9] hw/arm/aspeed: Introduce AST1040 A0 SoC model Jamin Lin
@ 2026-05-25 5:30 ` Jamin Lin
2026-05-25 5:30 ` [PATCH v2 8/9] tests/function/aspeed: Add AST1040 functional test Jamin Lin
` (3 subsequent siblings)
10 siblings, 0 replies; 12+ messages in thread
From: Jamin Lin @ 2026-05-25 5:30 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Kane Chen, Andrew Jeffery, Joel Stanley, Pierrick Bouvier,
open list:ASPEED BMCs, open list:All patches CC here
Cc: Jamin Lin, Troy Lee
AST1040 is the next-generation device following AST1030 and is
primarily designed as a bridge/BIC controller platform. Introduce
a dedicated AST1040 EVB machine implementation for firmware
development and validation.
Although the existing ast10x0 EVB machine code already provides
a reusable minibmc initialization flow, AST1040 requires
different platform settings, including:
- Different SYSCLK frequency
- Different internal flash size
To avoid overloading the existing AST1030-specific helper,
introduce a separate aspeed_bic_machine_init() implementation in
a dedicated source file.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
hw/arm/aspeed_ast1040_evb.c | 73 +++++++++++++++++++++++++++++++++++++
hw/arm/meson.build | 3 +-
2 files changed, 75 insertions(+), 1 deletion(-)
create mode 100644 hw/arm/aspeed_ast1040_evb.c
diff --git a/hw/arm/aspeed_ast1040_evb.c b/hw/arm/aspeed_ast1040_evb.c
new file mode 100644
index 0000000000..1d9b55247f
--- /dev/null
+++ b/hw/arm/aspeed_ast1040_evb.c
@@ -0,0 +1,73 @@
+/*
+ * ASPEED AST1040 EVB
+ *
+ * Copyright (C) 2026 ASPEED Technology Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "hw/arm/boot.h"
+#include "hw/arm/machines-qom.h"
+#include "hw/arm/aspeed.h"
+#include "hw/arm/aspeed_soc.h"
+#include "hw/core/qdev-clock.h"
+#include "system/system.h"
+
+#define AST1040_INTERNAL_FLASH_SIZE (4 * MiB)
+/* Main SYSCLK frequency in Hz (400MHz) */
+#define SYSCLK_FRQ 400000000ULL
+
+static void aspeed_bic_machine_init(MachineState *machine)
+{
+ AspeedMachineState *bmc = ASPEED_MACHINE(machine);
+ AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine);
+ Clock *sysclk;
+
+ sysclk = clock_new(OBJECT(machine), "SYSCLK");
+ clock_set_hz(sysclk, SYSCLK_FRQ);
+
+ bmc->soc = ASPEED_SOC(object_new(amc->soc_name));
+ object_property_add_child(OBJECT(machine), "soc", OBJECT(bmc->soc));
+ object_unref(OBJECT(bmc->soc));
+ qdev_connect_clock_in(DEVICE(bmc->soc), "sysclk", sysclk);
+
+ object_property_set_link(OBJECT(bmc->soc), "memory",
+ OBJECT(get_system_memory()), &error_abort);
+ aspeed_connect_serial_hds_to_uarts(bmc);
+ qdev_realize(DEVICE(bmc->soc), NULL, &error_abort);
+
+ armv7m_load_kernel(ARM_CPU(first_cpu),
+ machine->kernel_filename,
+ 0,
+ AST1040_INTERNAL_FLASH_SIZE);
+}
+
+static void aspeed_machine_ast1040_evb_class_init(ObjectClass *oc,
+ const void *data)
+{
+ MachineClass *mc = MACHINE_CLASS(oc);
+ AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
+
+ mc->desc = "Aspeed AST1040 BIC EVB (Cortex-M4F)";
+ amc->soc_name = "ast1040-a0";
+ amc->hw_strap1 = 0;
+ amc->hw_strap2 = 0;
+ mc->init = aspeed_bic_machine_init;
+ mc->default_ram_size = 0;
+ amc->macs_mask = 0;
+ amc->uart_default = ASPEED_DEV_UART12;
+ aspeed_machine_class_init_cpus_defaults(mc);
+}
+
+static const TypeInfo aspeed_ast1040_evb_types[] = {
+ {
+ .name = MACHINE_TYPE_NAME("ast1040-evb"),
+ .parent = TYPE_ASPEED_MACHINE,
+ .class_init = aspeed_machine_ast1040_evb_class_init,
+ .interfaces = arm_machine_interfaces,
+ }
+};
+
+DEFINE_TYPES(aspeed_ast1040_evb_types)
diff --git a/hw/arm/meson.build b/hw/arm/meson.build
index fa3a848492..9b75cc7fb1 100644
--- a/hw/arm/meson.build
+++ b/hw/arm/meson.build
@@ -63,7 +63,8 @@ arm_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files(
'aspeed_ast2600_rainier.c',
'aspeed_ast10x0.c',
'aspeed_ast10x0_evb.c',
- 'aspeed_ast1040.c'))
+ 'aspeed_ast1040.c',
+ 'aspeed_ast1040_evb.c'))
arm_common_ss.add(when: ['CONFIG_ASPEED_SOC', 'TARGET_AARCH64'], if_true: files(
'aspeed_ast1700.c',
'aspeed_ast27x0.c',
--
2.43.0
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH v2 8/9] tests/function/aspeed: Add AST1040 functional test
2026-05-25 5:30 [PATCH v2 0/9] hw/arm/aspeed: Introduce initial AST1040 support Jamin Lin
` (6 preceding siblings ...)
2026-05-25 5:30 ` [PATCH v2 7/9] hw/arm/aspeed: Add AST1040 EVB machine model Jamin Lin
@ 2026-05-25 5:30 ` Jamin Lin
2026-05-25 5:30 ` [PATCH v2 9/9] docs/system/arm/aspeed: Add AST1040 Bridge IC evaluation board Jamin Lin
` (2 subsequent siblings)
10 siblings, 0 replies; 12+ messages in thread
From: Jamin Lin @ 2026-05-25 5:30 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Kane Chen, Andrew Jeffery, Joel Stanley, Pierrick Bouvier,
open list:ASPEED BMCs, open list:All patches CC here
Cc: Jamin Lin, Troy Lee
Add a new functional test for the ast1040-evb machine to
validate Zephyr firmware boot flow in QEMU.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
tests/functional/arm/meson.build | 1 +
tests/functional/arm/test_aspeed_ast1040.py | 35 +++++++++++++++++++++
2 files changed, 36 insertions(+)
create mode 100644 tests/functional/arm/test_aspeed_ast1040.py
diff --git a/tests/functional/arm/meson.build b/tests/functional/arm/meson.build
index 2f538f29a2..786b4b2985 100644
--- a/tests/functional/arm/meson.build
+++ b/tests/functional/arm/meson.build
@@ -33,6 +33,7 @@ tests_arm_system_quick = [
tests_arm_system_thorough = [
'aspeed_ast1030',
+ 'aspeed_ast1040',
'aspeed_ast1060',
'aspeed_palmetto',
'aspeed_romulus',
diff --git a/tests/functional/arm/test_aspeed_ast1040.py b/tests/functional/arm/test_aspeed_ast1040.py
new file mode 100644
index 0000000000..e4d8ecb37a
--- /dev/null
+++ b/tests/functional/arm/test_aspeed_ast1040.py
@@ -0,0 +1,35 @@
+#!/usr/bin/env python3
+#
+# Functional test that boots the ASPEED SoCs with firmware
+#
+# Copyright (C) 2026 ASPEED Technology Inc
+#
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+from aspeed import AspeedTest
+from qemu_test import Asset, exec_command_and_wait_for_pattern
+
+
+class AST1040Machine(AspeedTest):
+
+ ASSET_ZEPHYR_3_07 = Asset(
+ ('https://github.com/AspeedTech-BMC'
+ '/zephyr/releases/download/v00.03.07/ast1040-evb-demo.zip'),
+ 'b5189797c22c2d732ddc27670c1efdeba821a2747c9c7434f190791125baa121')
+
+ def test_arm_ast1040_zephyros(self):
+ self.set_machine('ast1040-evb')
+
+ kernel_name = "zephyr.bin"
+ kernel_file = self.archive_extract(
+ self.ASSET_ZEPHYR_3_07, member=kernel_name)
+
+ self.vm.set_console()
+ self.vm.add_args('-kernel', kernel_file, '-nographic')
+ self.vm.launch()
+ self.wait_for_console_pattern("uart:~$")
+ exec_command_and_wait_for_pattern(self, "help",
+ "Available commands")
+
+if __name__ == '__main__':
+ AspeedTest.main()
--
2.43.0
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH v2 9/9] docs/system/arm/aspeed: Add AST1040 Bridge IC evaluation board
2026-05-25 5:30 [PATCH v2 0/9] hw/arm/aspeed: Introduce initial AST1040 support Jamin Lin
` (7 preceding siblings ...)
2026-05-25 5:30 ` [PATCH v2 8/9] tests/function/aspeed: Add AST1040 functional test Jamin Lin
@ 2026-05-25 5:30 ` Jamin Lin
2026-05-26 4:58 ` [PATCH v2 0/9] hw/arm/aspeed: Introduce initial AST1040 support Cédric Le Goater
2026-05-26 5:02 ` Cédric Le Goater
10 siblings, 0 replies; 12+ messages in thread
From: Jamin Lin @ 2026-05-25 5:30 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Kane Chen, Andrew Jeffery, Joel Stanley, Pierrick Bouvier,
open list:ASPEED BMCs, open list:All patches CC here
Cc: Jamin Lin, Troy Lee
Update the Aspeed AST10x0 documentation to include the
AST1040 evaluation board and clarify the AST10x0 family
classification.
The documentation now describes:
- AST1030 and AST1040 as Bridge IC devices
- AST1060 as a Platform Root of Trust processor
- AST1040 Cortex-M4F CPU frequency running at 400 MHz
Also add the ast1040-evb machine entry to the supported
AST10x0 SoC based machine list.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
docs/system/arm/aspeed.rst | 18 +++++++++++++-----
1 file changed, 13 insertions(+), 5 deletions(-)
diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst
index df2f539b02..7c8639c3da 100644
--- a/docs/system/arm/aspeed.rst
+++ b/docs/system/arm/aspeed.rst
@@ -440,18 +440,26 @@ Use ``tio`` or another terminal emulator to connect to the consoles:
$ tio /dev/pts/57
-Aspeed MiniBMC and Platform Root of Trust processor family boards (``ast1030-evb``, ``ast1060-evb``)
-====================================================================================================
+Aspeed Bridge IC and Platform Root of Trust processor family boards (``ast1030-evb``, ``ast1040-evb``, ``ast1060-evb``)
+=======================================================================================================================
-The QEMU Aspeed machines model mini BMCs and Platform Root of Trust processors of various Aspeed
-evaluation boards. They are based on different releases of the Aspeed SoC : the AST1030 (MiniBMC)
-and AST1060 (Platform Root of Trust Processor), both integrating an Arm Cortex M4F CPU (200MHz).
+The QEMU Aspeed machines model Bridge ICs and Platform Root of Trust processors
+of various Aspeed evaluation boards. They are based on different members of
+the Aspeed AST10x0 SoC family:
+
+- AST1030 : Bridge IC
+- AST1040 : Bridge IC
+- AST1060 : Platform Root of Trust processor
+
+The AST1030 and AST1060 integrate an Arm Cortex-M4F CPU running at 200 MHz.
+The AST1040 integrates an Arm Cortex-M4F CPU running at 400 MHz.
The SoC comes with SRAM, SPI, I2C, etc.
AST10x0 SoC based machines :
- ``ast1030-evb`` Aspeed AST1030 Evaluation board (Cortex-M4F)
+- ``ast1040-evb`` Aspeed AST1040 Evaluation board (Cortex-M4F)
- ``ast1060-evb`` Aspeed AST1060 Evaluation board (Cortex-M4F)
Supported devices
--
2.43.0
^ permalink raw reply related [flat|nested] 12+ messages in thread* Re: [PATCH v2 0/9] hw/arm/aspeed: Introduce initial AST1040 support
2026-05-25 5:30 [PATCH v2 0/9] hw/arm/aspeed: Introduce initial AST1040 support Jamin Lin
` (8 preceding siblings ...)
2026-05-25 5:30 ` [PATCH v2 9/9] docs/system/arm/aspeed: Add AST1040 Bridge IC evaluation board Jamin Lin
@ 2026-05-26 4:58 ` Cédric Le Goater
2026-05-26 5:02 ` Cédric Le Goater
10 siblings, 0 replies; 12+ messages in thread
From: Cédric Le Goater @ 2026-05-26 4:58 UTC (permalink / raw)
To: Jamin Lin, Peter Maydell, Steven Lee, Troy Lee, Kane Chen,
Andrew Jeffery, Joel Stanley, Pierrick Bouvier,
open list:ASPEED BMCs, open list:All patches CC here
Cc: Troy Lee
On 5/25/26 07:30, Jamin Lin wrote:
> This series introduces the initial ASPEED AST1040 support for QEMU.
>
> AST1040 is the next-generation bridge/BIC controller platform
> following AST1030 and is based on an ARM Cortex-M4F CPU core.
> Since QEMU currently does not provide Cortex-M4F support, the
> existing Cortex-M4 CPU model is used temporarily.
>
> The current implementation provides enough functionality to boot
> basic firmware environments with UART console support, HyperRAM/SRAM
> mapping, and NVIC interrupt handling.
>
> Currently this series is able to boot Zephyr successfully to the
> shell prompt:
>
> uart:~$
>
> Example command line:
>
> ./build/qemu-system-arm \
> -machine ast1040-evb \
> -kernel <zephyr.elf> \
> -serial mon:stdio \
> -snapshot \
> -nographic
>
> There are many different types of RAM, including DRAM, SRAM, SDRAM, PSRAM,
> SECSRAM, and HyperRAM. To support these memory types, we need to introduce
> distinct variable names for their memory regions and memory sizes.
>
> In addition, the SoC contains multiple SRAM instances. To make the code more
> flexible and maintainable, I am considering changing the array structure to
> support internal memory types such as SRAM, SDRAM, PSRAM, HyperRAM, and SECSRAM.
>
> For example:
>
> sram[NUM]
> sram_size[NUM]
> ASPEED_DEV_SRAMX
>
> v1:
> - AST1040 silicon revision ID
> - SDRAM support in the Aspeed SoC framework
> - Initial AST1040 SoC model
> - AST1040 EVB machine model
>
> v2:
> - Add AST1040 functional test
> - Add AST1040 documentation
> - Convert SRAM MemoryRegion to array type
> - Convert SRAM size definition to array type
>
> Jamin Lin (9):
> hw/arm/aspeed: Convert SRAM MemoryRegion to array type
> hw/arm/aspeed: Convert SRAM size definition to array type
> hw/arm/aspeed: Rename SRAM memmap entry for multi-SRAM support
> hw/arm/aspeed: Consolidate secure SRAM into SRAM array
> hw/misc/aspeed_scu: Add AST1040 A0 silicon revision ID
> hw/arm/aspeed: Introduce AST1040 A0 SoC model
> hw/arm/aspeed: Add AST1040 EVB machine model
> tests/function/aspeed: Add AST1040 functional test
> docs/system/arm/aspeed: Add AST1040 Bridge IC evaluation board
>
> docs/system/arm/aspeed.rst | 18 +-
> include/hw/arm/aspeed_soc.h | 11 +-
> include/hw/misc/aspeed_scu.h | 1 +
> hw/arm/aspeed_ast1040.c | 254 ++++++++++++++++++++
> hw/arm/aspeed_ast1040_evb.c | 73 ++++++
> hw/arm/aspeed_ast10x0.c | 29 ++-
> hw/arm/aspeed_ast2400.c | 14 +-
> hw/arm/aspeed_ast2600.c | 10 +-
> hw/arm/aspeed_ast27x0-ssp.c | 4 +-
> hw/arm/aspeed_ast27x0-tsp.c | 4 +-
> hw/arm/aspeed_ast27x0.c | 12 +-
> hw/misc/aspeed_scu.c | 1 +
> hw/arm/meson.build | 4 +-
> tests/functional/arm/meson.build | 1 +
> tests/functional/arm/test_aspeed_ast1040.py | 35 +++
> 15 files changed, 424 insertions(+), 47 deletions(-)
> create mode 100644 hw/arm/aspeed_ast1040.c
> create mode 100644 hw/arm/aspeed_ast1040_evb.c
> create mode 100644 tests/functional/arm/test_aspeed_ast1040.py
>
For the series,
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Thanks,
C.
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH v2 0/9] hw/arm/aspeed: Introduce initial AST1040 support
2026-05-25 5:30 [PATCH v2 0/9] hw/arm/aspeed: Introduce initial AST1040 support Jamin Lin
` (9 preceding siblings ...)
2026-05-26 4:58 ` [PATCH v2 0/9] hw/arm/aspeed: Introduce initial AST1040 support Cédric Le Goater
@ 2026-05-26 5:02 ` Cédric Le Goater
10 siblings, 0 replies; 12+ messages in thread
From: Cédric Le Goater @ 2026-05-26 5:02 UTC (permalink / raw)
To: Jamin Lin, Peter Maydell, Steven Lee, Troy Lee, Kane Chen,
Andrew Jeffery, Joel Stanley, Pierrick Bouvier,
open list:ASPEED BMCs, open list:All patches CC here
Cc: Troy Lee
On 5/25/26 07:30, Jamin Lin wrote:
> This series introduces the initial ASPEED AST1040 support for QEMU.
>
> AST1040 is the next-generation bridge/BIC controller platform
> following AST1030 and is based on an ARM Cortex-M4F CPU core.
> Since QEMU currently does not provide Cortex-M4F support, the
> existing Cortex-M4 CPU model is used temporarily.
>
> The current implementation provides enough functionality to boot
> basic firmware environments with UART console support, HyperRAM/SRAM
> mapping, and NVIC interrupt handling.
>
> Currently this series is able to boot Zephyr successfully to the
> shell prompt:
>
> uart:~$
>
> Example command line:
>
> ./build/qemu-system-arm \
> -machine ast1040-evb \
> -kernel <zephyr.elf> \
> -serial mon:stdio \
> -snapshot \
> -nographic
>
> There are many different types of RAM, including DRAM, SRAM, SDRAM, PSRAM,
> SECSRAM, and HyperRAM. To support these memory types, we need to introduce
> distinct variable names for their memory regions and memory sizes.
>
> In addition, the SoC contains multiple SRAM instances. To make the code more
> flexible and maintainable, I am considering changing the array structure to
> support internal memory types such as SRAM, SDRAM, PSRAM, HyperRAM, and SECSRAM.
>
> For example:
>
> sram[NUM]
> sram_size[NUM]
> ASPEED_DEV_SRAMX
>
> v1:
> - AST1040 silicon revision ID
> - SDRAM support in the Aspeed SoC framework
> - Initial AST1040 SoC model
> - AST1040 EVB machine model
>
> v2:
> - Add AST1040 functional test
> - Add AST1040 documentation
> - Convert SRAM MemoryRegion to array type
> - Convert SRAM size definition to array type
>
> Jamin Lin (9):
> hw/arm/aspeed: Convert SRAM MemoryRegion to array type
> hw/arm/aspeed: Convert SRAM size definition to array type
> hw/arm/aspeed: Rename SRAM memmap entry for multi-SRAM support
> hw/arm/aspeed: Consolidate secure SRAM into SRAM array
> hw/misc/aspeed_scu: Add AST1040 A0 silicon revision ID
> hw/arm/aspeed: Introduce AST1040 A0 SoC model
> hw/arm/aspeed: Add AST1040 EVB machine model
> tests/function/aspeed: Add AST1040 functional test
> docs/system/arm/aspeed: Add AST1040 Bridge IC evaluation board
>
> docs/system/arm/aspeed.rst | 18 +-
> include/hw/arm/aspeed_soc.h | 11 +-
> include/hw/misc/aspeed_scu.h | 1 +
> hw/arm/aspeed_ast1040.c | 254 ++++++++++++++++++++
> hw/arm/aspeed_ast1040_evb.c | 73 ++++++
> hw/arm/aspeed_ast10x0.c | 29 ++-
> hw/arm/aspeed_ast2400.c | 14 +-
> hw/arm/aspeed_ast2600.c | 10 +-
> hw/arm/aspeed_ast27x0-ssp.c | 4 +-
> hw/arm/aspeed_ast27x0-tsp.c | 4 +-
> hw/arm/aspeed_ast27x0.c | 12 +-
> hw/misc/aspeed_scu.c | 1 +
> hw/arm/meson.build | 4 +-
> tests/functional/arm/meson.build | 1 +
> tests/functional/arm/test_aspeed_ast1040.py | 35 +++
> 15 files changed, 424 insertions(+), 47 deletions(-)
> create mode 100644 hw/arm/aspeed_ast1040.c
> create mode 100644 hw/arm/aspeed_ast1040_evb.c
> create mode 100644 tests/functional/arm/test_aspeed_ast1040.py
>
Applied to
https://github.com/legoater/qemu aspeed-next
Thanks,
C.
^ permalink raw reply [flat|nested] 12+ messages in thread