* [PATCH v5 01/10] hw/arm/ast27x0: Start SSP in powered-off state to match hardware behavior
2026-07-08 9:20 [PATCH v5 00/10] Add SSP/TSP power control and DRAM remap support for AST2700 Jamin Lin
@ 2026-07-08 9:20 ` Jamin Lin
2026-07-08 9:20 ` [PATCH v5 02/10] hw/arm/ast27x0: Start TSP " Jamin Lin
` (9 subsequent siblings)
10 siblings, 0 replies; 17+ messages in thread
From: Jamin Lin @ 2026-07-08 9:20 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Kane Chen, Andrew Jeffery, Joel Stanley, Pierrick Bouvier,
open list:ASPEED BMCs, open list:All patches CC here
Cc: Jamin Lin, Troy Lee
In the previous design, both the PSP and SSP were started together during
SoC initialization. However, on real hardware, the SSP begins in a powered-off
state. The typical boot sequence involves the PSP powering up first, loading
the SSP firmware binary into shared memory via DRAM remap, and then releasing
the SSP reset and enabling it through SCU control registers.
To more accurately model this behavior in QEMU, this commit sets the
"start-powered-off" property for the SSP's ARMv7M core. This change ensures
the SSP remains off until explicitly enabled via the SCU, simulating the
real-world flow where the PSP controls SSP boot through SCU interaction.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
hw/arm/aspeed_ast27x0-ssp.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/hw/arm/aspeed_ast27x0-ssp.c b/hw/arm/aspeed_ast27x0-ssp.c
index e03653086c..9c984d23cd 100644
--- a/hw/arm/aspeed_ast27x0-ssp.c
+++ b/hw/arm/aspeed_ast27x0-ssp.c
@@ -192,6 +192,13 @@ static void aspeed_soc_ast27x0ssp_realize(DeviceState *dev_soc, Error **errp)
qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk);
object_property_set_link(OBJECT(&a->armv7m), "memory",
OBJECT(s->memory), &error_abort);
+ /*
+ * The SSP starts in a powered-down state and can be powered up
+ * by setting the SSP Control Register through the SCU
+ * (System Control Unit)
+ */
+ object_property_set_bool(OBJECT(&a->armv7m), "start-powered-off", true,
+ &error_abort);
sysbus_realize(SYS_BUS_DEVICE(&a->armv7m), &error_abort);
/* SDRAM */
--
2.43.0
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH v5 02/10] hw/arm/ast27x0: Start TSP in powered-off state to match hardware behavior
2026-07-08 9:20 [PATCH v5 00/10] Add SSP/TSP power control and DRAM remap support for AST2700 Jamin Lin
2026-07-08 9:20 ` [PATCH v5 01/10] hw/arm/ast27x0: Start SSP in powered-off state to match hardware behavior Jamin Lin
@ 2026-07-08 9:20 ` Jamin Lin
2026-07-08 9:20 ` [PATCH v5 03/10] hw/arm/ast27x0: Add DRAM alias for SSP SDRAM remap Jamin Lin
` (8 subsequent siblings)
10 siblings, 0 replies; 17+ messages in thread
From: Jamin Lin @ 2026-07-08 9:20 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Kane Chen, Andrew Jeffery, Joel Stanley, Pierrick Bouvier,
open list:ASPEED BMCs, open list:All patches CC here
Cc: Jamin Lin, Troy Lee
In the previous design, both the PSP and TSP were started together during
SoC initialization. However, on real hardware, the TSP begins in a powered-off
state. The typical boot sequence involves the PSP powering up first, loading
the TSP firmware binary into shared memory via DRAM remap, and then releasing
the TSP reset and enabling it through SCU control registers.
To more accurately model this behavior in QEMU, this commit sets the
"start-powered-off" property for the TSP's ARMv7M core. This change ensures
the TSP remains off until explicitly enabled via the SCU, simulating the
real-world flow where the PSP controls TSP boot through SCU interaction.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
hw/arm/aspeed_ast27x0-tsp.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/hw/arm/aspeed_ast27x0-tsp.c b/hw/arm/aspeed_ast27x0-tsp.c
index 39ba062a20..4212e7bd4c 100644
--- a/hw/arm/aspeed_ast27x0-tsp.c
+++ b/hw/arm/aspeed_ast27x0-tsp.c
@@ -192,6 +192,13 @@ static void aspeed_soc_ast27x0tsp_realize(DeviceState *dev_soc, Error **errp)
qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk);
object_property_set_link(OBJECT(&a->armv7m), "memory",
OBJECT(s->memory), &error_abort);
+ /*
+ * The TSP starts in a powered-down state and can be powered up
+ * by setting the TSP Control Register through the SCU
+ * (System Control Unit)
+ */
+ object_property_set_bool(OBJECT(&a->armv7m), "start-powered-off", true,
+ &error_abort);
sysbus_realize(SYS_BUS_DEVICE(&a->armv7m), &error_abort);
/* SDRAM */
--
2.43.0
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH v5 03/10] hw/arm/ast27x0: Add DRAM alias for SSP SDRAM remap
2026-07-08 9:20 [PATCH v5 00/10] Add SSP/TSP power control and DRAM remap support for AST2700 Jamin Lin
2026-07-08 9:20 ` [PATCH v5 01/10] hw/arm/ast27x0: Start SSP in powered-off state to match hardware behavior Jamin Lin
2026-07-08 9:20 ` [PATCH v5 02/10] hw/arm/ast27x0: Start TSP " Jamin Lin
@ 2026-07-08 9:20 ` Jamin Lin
2026-07-08 9:20 ` [PATCH v5 04/10] hw/arm/ast27x0: Add DRAM alias for TSP " Jamin Lin
` (7 subsequent siblings)
10 siblings, 0 replies; 17+ messages in thread
From: Jamin Lin @ 2026-07-08 9:20 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Kane Chen, Andrew Jeffery, Joel Stanley, Pierrick Bouvier,
open list:ASPEED BMCs, open list:All patches CC here
Cc: Jamin Lin, Troy Lee
This commit adds two MemoryRegion aliases to support PSP access to
SSP SDRAM through shared memory remapping.
The SSP exposes two DRAM aliases:
- remap1 maps PSP DRAM at 0x400000000 to SSP SDRAM offset 0x5880000
- remap2 maps PSP DRAM at 0x42C000000 to SSP SDRAM offset 0x0
These mappings follow the default SCU register configuration used by
the ASPEED SDK firmware, which defines the memory window mapping
between PSP and the SSP.
Set SSP CPUID 4.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
include/hw/misc/aspeed_scu.h | 4 ++++
hw/arm/aspeed_ast27x0-fc.c | 2 ++
hw/arm/aspeed_ast27x0-ssp.c | 6 ++++++
hw/arm/aspeed_ast27x0.c | 4 ++++
hw/misc/aspeed_scu.c | 32 ++++++++++++++++++++++++++++++++
5 files changed, 48 insertions(+)
diff --git a/include/hw/misc/aspeed_scu.h b/include/hw/misc/aspeed_scu.h
index 904549465f..ae49f6ab9a 100644
--- a/include/hw/misc/aspeed_scu.h
+++ b/include/hw/misc/aspeed_scu.h
@@ -44,6 +44,10 @@ struct AspeedSCUState {
struct Aspeed2700SCUState {
AspeedSCUState parent_obj;
+
+ MemoryRegion dram_remap_alias[3];
+ MemoryRegion *dram;
+ int ssp_cpuid;
};
#define AST2400_A1_SILICON_REV 0x02010303U
diff --git a/hw/arm/aspeed_ast27x0-fc.c b/hw/arm/aspeed_ast27x0-fc.c
index 058cea42ed..ce245118af 100644
--- a/hw/arm/aspeed_ast27x0-fc.c
+++ b/hw/arm/aspeed_ast27x0-fc.c
@@ -102,6 +102,8 @@ static bool ast2700fc_ca35_init(MachineState *machine, Error **errp)
sc->uarts_num, serial_hd(1));
aspeed_soc_uart_set_chr(soc->uart, ASPEED_DEV_UART7, sc->uarts_base,
sc->uarts_num, serial_hd(2));
+ object_property_set_int(OBJECT(&s->ca35), "ssp-cpuid", 4,
+ &error_abort);
if (!qdev_realize(DEVICE(&s->ca35), NULL, errp)) {
return false;
}
diff --git a/hw/arm/aspeed_ast27x0-ssp.c b/hw/arm/aspeed_ast27x0-ssp.c
index 9c984d23cd..778876a60e 100644
--- a/hw/arm/aspeed_ast27x0-ssp.c
+++ b/hw/arm/aspeed_ast27x0-ssp.c
@@ -232,6 +232,12 @@ static void aspeed_soc_ast27x0ssp_realize(DeviceState *dev_soc, Error **errp)
memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SCUIO],
&a->scuio_alias);
+ /* SDRAM remap alias used by PSP to access SSP SDRAM */
+ memory_region_add_subregion(&s->sdram, 0, &a->scu->dram_remap_alias[1]);
+ memory_region_add_subregion(&s->sdram,
+ memory_region_size(&a->scu->dram_remap_alias[1]),
+ &a->scu->dram_remap_alias[0]);
+
/* INTC */
if (!sysbus_realize(SYS_BUS_DEVICE(&a->intc[0]), errp)) {
return;
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
index dd6dd0377c..10d3e35a9b 100644
--- a/hw/arm/aspeed_ast27x0.c
+++ b/hw/arm/aspeed_ast27x0.c
@@ -442,6 +442,8 @@ static void aspeed_soc_ast2700_init(Object *obj)
"hw-strap1");
object_property_add_alias(obj, "hw-prot-key", OBJECT(&a->scu),
"hw-prot-key");
+ object_property_add_alias(obj, "ssp-cpuid", OBJECT(&a->scu),
+ "ssp-cpuid");
object_initialize_child(obj, "scuio", &s->scuio, TYPE_ASPEED_2700_SCUIO);
qdev_prop_set_uint32(DEVICE(&s->scuio), "silicon-rev",
@@ -808,6 +810,8 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
sc->memmap[ASPEED_DEV_VBOOTROM], &s->vbootrom);
/* SCU */
+ object_property_set_link(OBJECT(&a->scu), "dram", OBJECT(s->dram_mr),
+ &error_abort);
if (!sysbus_realize(SYS_BUS_DEVICE(&a->scu), errp)) {
return;
}
diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c
index ca93c3699d..cc0aa3234a 100644
--- a/hw/misc/aspeed_scu.c
+++ b/hw/misc/aspeed_scu.c
@@ -20,6 +20,7 @@
#include "qemu/guest-random.h"
#include "qemu/module.h"
#include "trace.h"
+#include "qemu/units.h"
#define TO_REG(offset) ((offset) >> 2)
@@ -932,9 +933,39 @@ static void aspeed_ast2700_scu_reset_hold(Object *obj, ResetType type)
static void aspeed_2700_scu_realize(DeviceState *dev, Error **errp)
{
+ Aspeed2700SCUState *a = ASPEED_2700_SCU(dev);
+
aspeed_scu_realize(dev, errp);
+
+ if (a->ssp_cpuid > 0) {
+ if (!a->dram) {
+ error_setg(errp, TYPE_ASPEED_2700_SCU ": 'dram' link not set");
+ return;
+ }
+ /*
+ * The SSP coprocessor uses two memory aliases (remap1 and remap2)
+ * to access shared memory regions in the PSP DRAM:
+ *
+ * - remap1 maps PSP DRAM at 0x400000000 (size: 0x1A77E000) to
+ * SSP SDRAM offset 0x5880000
+ * - remap2 maps PSP DRAM at 0x42C000000 (size: 0x05880000) to
+ * SSP SDRAM offset 0x0
+ */
+ memory_region_init_alias(&a->dram_remap_alias[0], OBJECT(a),
+ "ssp.dram.remap1", a->dram,
+ 0, 0x1a77e000);
+ memory_region_init_alias(&a->dram_remap_alias[1], OBJECT(a),
+ "ssp.dram.remap2", a->dram,
+ 0x2c000000, 0x05880000);
+ }
}
+static const Property aspeed_2700_scu_properties[] = {
+ DEFINE_PROP_INT32("ssp-cpuid", Aspeed2700SCUState, ssp_cpuid, -1),
+ DEFINE_PROP_LINK("dram", Aspeed2700SCUState, dram, TYPE_MEMORY_REGION,
+ MemoryRegion *),
+};
+
static void aspeed_2700_scu_class_init(ObjectClass *klass, const void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
@@ -944,6 +975,7 @@ static void aspeed_2700_scu_class_init(ObjectClass *klass, const void *data)
dc->desc = "ASPEED 2700 System Control Unit";
dc->realize = aspeed_2700_scu_realize;
rc->phases.hold = aspeed_ast2700_scu_reset_hold;
+ device_class_set_props(dc, aspeed_2700_scu_properties);
asc->resets = ast2700_a0_resets;
asc->calc_hpll = aspeed_2600_scu_calc_hpll;
asc->get_apb = aspeed_2700_scu_get_apb_freq;
--
2.43.0
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH v5 04/10] hw/arm/ast27x0: Add DRAM alias for TSP SDRAM remap
2026-07-08 9:20 [PATCH v5 00/10] Add SSP/TSP power control and DRAM remap support for AST2700 Jamin Lin
` (2 preceding siblings ...)
2026-07-08 9:20 ` [PATCH v5 03/10] hw/arm/ast27x0: Add DRAM alias for SSP SDRAM remap Jamin Lin
@ 2026-07-08 9:20 ` Jamin Lin
2026-07-08 9:20 ` [PATCH v5 05/10] hw/misc/aspeed_scu: Implement SSP reset and power-on control via SCU registers Jamin Lin
` (6 subsequent siblings)
10 siblings, 0 replies; 17+ messages in thread
From: Jamin Lin @ 2026-07-08 9:20 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Kane Chen, Andrew Jeffery, Joel Stanley, Pierrick Bouvier,
open list:ASPEED BMCs, open list:All patches CC here
Cc: Jamin Lin, Troy Lee
This commit adds a MemoryRegion alias to support PSP access to
TSP SDRAM through shared memory remapping.
The TSP coprocessor exposes one DRAM alias:
- remap maps PSP DRAM at 0x42E000000 to TSP SDRAM offset 0x0
These mappings follow the default SCU register configuration used by
the ASPEED SDK firmware, which defines the memory window mapping
between PSP and TSP.
Set TSP CPUID 5.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
include/hw/misc/aspeed_scu.h | 1 +
hw/arm/aspeed_ast27x0-fc.c | 2 ++
hw/arm/aspeed_ast27x0-tsp.c | 3 +++
hw/arm/aspeed_ast27x0.c | 2 ++
hw/misc/aspeed_scu.c | 18 ++++++++++++++++++
5 files changed, 26 insertions(+)
diff --git a/include/hw/misc/aspeed_scu.h b/include/hw/misc/aspeed_scu.h
index ae49f6ab9a..1c3a220d96 100644
--- a/include/hw/misc/aspeed_scu.h
+++ b/include/hw/misc/aspeed_scu.h
@@ -48,6 +48,7 @@ struct Aspeed2700SCUState {
MemoryRegion dram_remap_alias[3];
MemoryRegion *dram;
int ssp_cpuid;
+ int tsp_cpuid;
};
#define AST2400_A1_SILICON_REV 0x02010303U
diff --git a/hw/arm/aspeed_ast27x0-fc.c b/hw/arm/aspeed_ast27x0-fc.c
index ce245118af..113248b98e 100644
--- a/hw/arm/aspeed_ast27x0-fc.c
+++ b/hw/arm/aspeed_ast27x0-fc.c
@@ -104,6 +104,8 @@ static bool ast2700fc_ca35_init(MachineState *machine, Error **errp)
sc->uarts_num, serial_hd(2));
object_property_set_int(OBJECT(&s->ca35), "ssp-cpuid", 4,
&error_abort);
+ object_property_set_int(OBJECT(&s->ca35), "tsp-cpuid", 5,
+ &error_abort);
if (!qdev_realize(DEVICE(&s->ca35), NULL, errp)) {
return false;
}
diff --git a/hw/arm/aspeed_ast27x0-tsp.c b/hw/arm/aspeed_ast27x0-tsp.c
index 4212e7bd4c..369576bde3 100644
--- a/hw/arm/aspeed_ast27x0-tsp.c
+++ b/hw/arm/aspeed_ast27x0-tsp.c
@@ -232,6 +232,9 @@ static void aspeed_soc_ast27x0tsp_realize(DeviceState *dev_soc, Error **errp)
memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SCUIO],
&a->scuio_alias);
+ /* SDRAM remap alias used by PSP to access TSP SDRAM */
+ memory_region_add_subregion(&s->sdram, 0, &a->scu->dram_remap_alias[2]);
+
/* INTC */
if (!sysbus_realize(SYS_BUS_DEVICE(&a->intc[0]), errp)) {
return;
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
index 10d3e35a9b..9c13efa3a6 100644
--- a/hw/arm/aspeed_ast27x0.c
+++ b/hw/arm/aspeed_ast27x0.c
@@ -444,6 +444,8 @@ static void aspeed_soc_ast2700_init(Object *obj)
"hw-prot-key");
object_property_add_alias(obj, "ssp-cpuid", OBJECT(&a->scu),
"ssp-cpuid");
+ object_property_add_alias(obj, "tsp-cpuid", OBJECT(&a->scu),
+ "tsp-cpuid");
object_initialize_child(obj, "scuio", &s->scuio, TYPE_ASPEED_2700_SCUIO);
qdev_prop_set_uint32(DEVICE(&s->scuio), "silicon-rev",
diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c
index cc0aa3234a..88c1a57299 100644
--- a/hw/misc/aspeed_scu.c
+++ b/hw/misc/aspeed_scu.c
@@ -958,10 +958,28 @@ static void aspeed_2700_scu_realize(DeviceState *dev, Error **errp)
"ssp.dram.remap2", a->dram,
0x2c000000, 0x05880000);
}
+
+ if (a->tsp_cpuid > 0) {
+ if (!a->dram) {
+ error_setg(errp, TYPE_ASPEED_2700_SCU ": 'dram' link not set");
+ return;
+ }
+ /*
+ * The TSP coprocessor uses one memory alias (remap) to access a shared
+ * region in the PSP DRAM:
+ *
+ * - remap maps PSP DRAM at 0x42E000000 (size: 32MB) to TSP SDRAM
+ * offset 0x0
+ */
+ memory_region_init_alias(&a->dram_remap_alias[2], OBJECT(a),
+ "tsp.dram.remap", a->dram,
+ 0x2e000000, 32 * MiB);
+ }
}
static const Property aspeed_2700_scu_properties[] = {
DEFINE_PROP_INT32("ssp-cpuid", Aspeed2700SCUState, ssp_cpuid, -1),
+ DEFINE_PROP_INT32("tsp-cpuid", Aspeed2700SCUState, tsp_cpuid, -1),
DEFINE_PROP_LINK("dram", Aspeed2700SCUState, dram, TYPE_MEMORY_REGION,
MemoryRegion *),
};
--
2.43.0
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH v5 05/10] hw/misc/aspeed_scu: Implement SSP reset and power-on control via SCU registers
2026-07-08 9:20 [PATCH v5 00/10] Add SSP/TSP power control and DRAM remap support for AST2700 Jamin Lin
` (3 preceding siblings ...)
2026-07-08 9:20 ` [PATCH v5 04/10] hw/arm/ast27x0: Add DRAM alias for TSP " Jamin Lin
@ 2026-07-08 9:20 ` Jamin Lin
2026-07-08 9:20 ` [PATCH v5 06/10] hw/misc/aspeed_scu: Implement TSP " Jamin Lin
` (5 subsequent siblings)
10 siblings, 0 replies; 17+ messages in thread
From: Jamin Lin @ 2026-07-08 9:20 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Kane Chen, Andrew Jeffery, Joel Stanley, Pierrick Bouvier,
open list:ASPEED BMCs, open list:All patches CC here
Cc: Jamin Lin, Troy Lee
This patch implements SSP reset and power control logic in the SCU for AST2700.
It introduces support for the following behavior:
1. SSP Reset Trigger (via SCU 0x200):
- SSP reset is triggered by writing 1 to bit 30 (RW1S) of SYS_RESET_CTRL_1.
2. SSP Reset State and Source Hold (via SCU 0x120):
- Upon reset, bit 8 (RST_RB) is set to indicate the SSP is in reset.
- Bit 10 (RST_SRC_RB) is set to indicate the reset was triggered by an external source.
- Bit 1 (RST) is a software-controlled bit used to request holding SSP in reset.
- If an external reset source is present and bit 1 is set, bit 9 (RST_HOLD_RB)
will also be asserted to indicate the SSP is being held in reset.
- If bit 1 is cleared, RST_HOLD_RB will be deasserted accordingly.
3. Hold Release and Power-on:
- If RST_HOLD_RB is clear (0), SSP is powered on immediately after reset is deasserted.
- If RST_HOLD_RB is set (1), the user must write ENABLE (bit 0) to SSP_CTRL_0 to release
the hold and power on SSP explicitly.
- Writing ENABLE (bit 0) is a one-shot operation and will auto-clear after execution.
4. Reset Status Clear (via SCU 0x204):
- The reset status can be cleared by writing 1 to bit 30 (RW1C) of SYS_RST_CLR_1,
which will deassert RST_SRC_RB and potentially trigger power-on if no hold is active.
5. SSP Power Control Logic:
- `handle_ssp_tsp_on()` clears RST_SRC_RB and RST_RB (if not held), and invokes
`arm_set_cpu_on_and_reset(cpuid)` to power on the SSP core (CPUID 4).
- `handle_ssp_tsp_off()` sets RST_RB and RST_SRC_RB; if RST is active, also asserts
RST_HOLD_RB and invokes `arm_set_cpu_off(cpuid)`.
6. Register Initialization and Definitions:
- Adds SCU register definitions for SSP_CTRL_0 (0x120), SYS_RST_CTRL_1 (0x200),
and SYS_RST_CLR_1 (0x204).
- Updates the reset values for these registers during SCU initialization.
The default values are based on EVB (evaluation board) register dump observations.
This patch enables proper modeling of SSP lifecycle management across reset,
hold, and power-on states for the AST2700 SoC.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
hw/misc/aspeed_scu.c | 109 +++++++++++++++++++++++++++++++++++++++++++
1 file changed, 109 insertions(+)
diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c
index 88c1a57299..07901f2ab0 100644
--- a/hw/misc/aspeed_scu.c
+++ b/hw/misc/aspeed_scu.c
@@ -21,6 +21,7 @@
#include "qemu/module.h"
#include "trace.h"
#include "qemu/units.h"
+#include "target/arm/arm-powerctl.h"
#define TO_REG(offset) ((offset) >> 2)
@@ -144,6 +145,17 @@
#define AST2700_HW_STRAP1_SEC2 TO_REG(0x28)
#define AST2700_HW_STRAP1_SEC3 TO_REG(0x2C)
+/* SSP TSP */
+#define AST2700_SCU_SSP_CTRL_0 TO_REG(0x120)
+#define AST2700_SSP_TSP_ENABLE BIT(0)
+#define AST2700_SSP_TSP_RST BIT(1)
+#define AST2700_SSP_TSP_RST_RB BIT(8)
+#define AST2700_SSP_TSP_RST_HOLD_RB BIT(9)
+#define AST2700_SSP_TSP_RST_SRC_RB BIT(10)
+#define AST2700_SCU_SYS_RST_CTRL_1 TO_REG(0x200)
+#define AST2700_SCU_SYS_RST_CLR_1 TO_REG(0x204)
+#define AST2700_SCU_SYS_RST_SSP BIT(30)
+
#define AST2700_SCU_CLK_SEL_1 TO_REG(0x280)
#define AST2700_SCU_HPLL_PARAM TO_REG(0x300)
#define AST2700_SCU_HPLL_EXT_PARAM TO_REG(0x304)
@@ -842,6 +854,35 @@ static void aspeed_2600_scu_class_init(ObjectClass *klass, const void *data)
asc->ops = &aspeed_ast2600_scu_ops;
}
+static void handle_2700_ssp_tsp_on(struct AspeedSCUState *s, int cpuid,
+ int reg)
+{
+ uint32_t val = s->regs[reg];
+
+ val &= ~AST2700_SSP_TSP_RST_SRC_RB;
+ if (!(val & AST2700_SSP_TSP_RST_HOLD_RB)) {
+ val &= ~AST2700_SSP_TSP_RST_RB;
+ arm_set_cpu_on_and_reset(cpuid);
+ }
+
+ s->regs[reg] = val;
+}
+
+static void handle_2700_ssp_tsp_off(struct AspeedSCUState *s, int cpuid,
+ int reg)
+{
+ uint32_t val = s->regs[reg];
+
+ val |= AST2700_SSP_TSP_RST_RB;
+ val |= AST2700_SSP_TSP_RST_SRC_RB;
+ if (val & AST2700_SSP_TSP_RST) {
+ val |= AST2700_SSP_TSP_RST_HOLD_RB;
+ }
+ arm_set_cpu_off(cpuid);
+
+ s->regs[reg] = val;
+}
+
static uint64_t aspeed_ast2700_scu_read(void *opaque, hwaddr offset,
unsigned size)
{
@@ -862,10 +903,14 @@ static uint64_t aspeed_ast2700_scu_read(void *opaque, hwaddr offset,
static void aspeed_ast2700_scu_write(void *opaque, hwaddr offset,
uint64_t data64, unsigned size)
{
+ Aspeed2700SCUState *a = ASPEED_2700_SCU(opaque);
AspeedSCUState *s = ASPEED_SCU(opaque);
int reg = TO_REG(offset);
/* Truncate here so bitwise operations below behave as expected */
uint32_t data = data64;
+ uint32_t active;
+ uint32_t oldval;
+ int cpuid;
if (reg >= ASPEED_AST2700_SCU_NR_REGS) {
qemu_log_mask(LOG_GUEST_ERROR,
@@ -877,6 +922,63 @@ static void aspeed_ast2700_scu_write(void *opaque, hwaddr offset,
trace_aspeed_ast2700_scu_write(offset, size, data);
switch (reg) {
+ case AST2700_SCU_SSP_CTRL_0:
+ cpuid = a->ssp_cpuid;
+ if (cpuid < 0) {
+ return;
+ }
+ oldval = s->regs[reg];
+ data &= 0xff;
+ active = oldval ^ data;
+
+ /*
+ * If reset bit is being released (1 -> 0) and no other reset source
+ * is active, clear HOLD_RB and power on the corresponding CPU.
+ */
+ if ((active & AST2700_SSP_TSP_RST) && !(data & AST2700_SSP_TSP_RST)) {
+ s->regs[reg] &= ~AST2700_SSP_TSP_RST_HOLD_RB;
+ if ((oldval & AST2700_SSP_TSP_RST_RB) &&
+ !(oldval & AST2700_SSP_TSP_RST_SRC_RB)) {
+ handle_2700_ssp_tsp_on(s, cpuid, reg);
+ }
+ }
+
+ /*
+ * If ENABLE bit is newly set and reset state is ready,
+ * clear HOLD_RB and power on the corresponding CPU.
+ */
+ if ((active & AST2700_SSP_TSP_ENABLE) &&
+ (oldval & AST2700_SSP_TSP_RST_RB) &&
+ (oldval & AST2700_SSP_TSP_RST_HOLD_RB) &&
+ !(oldval & AST2700_SSP_TSP_RST_SRC_RB)) {
+ s->regs[reg] &= ~AST2700_SSP_TSP_RST_HOLD_RB;
+ handle_2700_ssp_tsp_on(s, cpuid, reg);
+ }
+
+ /* Auto-clear the ENABLE bit (one-shot behavior) */
+ data &= ~AST2700_SSP_TSP_ENABLE;
+ s->regs[reg] = (s->regs[reg] & ~0xff) | (data & 0xff);
+ return;
+ case AST2700_SCU_SYS_RST_CTRL_1:
+ if (a->ssp_cpuid < 0) {
+ return;
+ }
+ if (data & AST2700_SCU_SYS_RST_SSP) {
+ handle_2700_ssp_tsp_off(s, a->ssp_cpuid, AST2700_SCU_SSP_CTRL_0);
+ }
+ s->regs[reg] |= data;
+ return;
+ case AST2700_SCU_SYS_RST_CLR_1:
+ if (a->ssp_cpuid < 0) {
+ return;
+ }
+ oldval = s->regs[AST2700_SCU_SYS_RST_CTRL_1];
+ active = data & oldval;
+ if (active & AST2700_SCU_SYS_RST_SSP) {
+ handle_2700_ssp_tsp_on(s, a->ssp_cpuid, AST2700_SCU_SSP_CTRL_0);
+ }
+ s->regs[AST2700_SCU_SYS_RST_CTRL_1] &= ~active;
+ return;
default:
qemu_log_mask(LOG_GUEST_ERROR,
"%s: Unhandled write at offset 0x%" HWADDR_PRIx "\n",
@@ -904,6 +1006,8 @@ static const uint32_t ast2700_a0_resets[ASPEED_AST2700_SCU_NR_REGS] = {
[AST2700_HW_STRAP1_SEC1] = 0x000000FF,
[AST2700_HW_STRAP1_SEC2] = 0x00000000,
[AST2700_HW_STRAP1_SEC3] = 0x1000408F,
+ [AST2700_SCU_SSP_CTRL_0] = 0x000007FE,
+ [AST2700_SCU_SYS_RST_CTRL_1] = 0xFFC37FDC,
[AST2700_SCU_HPLL_PARAM] = 0x0000009f,
[AST2700_SCU_HPLL_EXT_PARAM] = 0x8000004f,
[AST2700_SCU_DPLL_PARAM] = 0x0080009f,
@@ -923,12 +1027,17 @@ static const uint32_t ast2700_a0_resets[ASPEED_AST2700_SCU_NR_REGS] = {
static void aspeed_ast2700_scu_reset_hold(Object *obj, ResetType type)
{
+ Aspeed2700SCUState *a = ASPEED_2700_SCU(obj);
AspeedSCUState *s = ASPEED_SCU(obj);
AspeedSCUClass *asc = ASPEED_SCU_GET_CLASS(obj);
memcpy(s->regs, asc->resets, asc->nr_regs * 4);
s->regs[AST2700_SILICON_REV] = s->silicon_rev;
s->regs[AST2700_HW_STRAP1] = s->hw_strap1;
+
+ if (a->ssp_cpuid > 0) {
+ arm_set_cpu_off(a->ssp_cpuid);
+ }
}
static void aspeed_2700_scu_realize(DeviceState *dev, Error **errp)
--
2.43.0
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH v5 06/10] hw/misc/aspeed_scu: Implement TSP reset and power-on control via SCU registers
2026-07-08 9:20 [PATCH v5 00/10] Add SSP/TSP power control and DRAM remap support for AST2700 Jamin Lin
` (4 preceding siblings ...)
2026-07-08 9:20 ` [PATCH v5 05/10] hw/misc/aspeed_scu: Implement SSP reset and power-on control via SCU registers Jamin Lin
@ 2026-07-08 9:20 ` Jamin Lin
2026-07-08 9:20 ` [PATCH v5 07/10] hw/misc/aspeed_scu: Add SCU support for SSP SDRAM remap Jamin Lin
` (4 subsequent siblings)
10 siblings, 0 replies; 17+ messages in thread
From: Jamin Lin @ 2026-07-08 9:20 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Kane Chen, Andrew Jeffery, Joel Stanley, Pierrick Bouvier,
open list:ASPEED BMCs, open list:All patches CC here
Cc: Jamin Lin, Troy Lee
This patch implements TSP reset and power control logic in the SCU module
for AST2700. It introduces support for the following behavior:
1. TSP Reset Trigger (via SCU 0x220):
- TSP reset is triggered by writing 1 to bit 9 (RW1S) of SYS_RESET_CTRL_2.
2. TSP Reset State and Source Hold (via SCU 0x160):
- Upon reset, bit 8 (RST_RB) is set to indicate the TSP is in reset.
- Bit 10 (RST_SRC_RB) is set to indicate the reset was triggered by an external source.
- Bit 1 (RST) is a software-controlled bit used to request holding TSP in reset.
- If an external reset source is present and bit 1 is set, bit 9 (RST_HOLD_RB)
will also be asserted to indicate the TSP is being held in reset.
- If bit 1 is cleared, RST_HOLD_RB will be deasserted accordingly.
3. Hold Release and Power-on:
- If RST_HOLD_RB is clear (0), TSP is powered on immediately after reset is deasserted.
- If RST_HOLD_RB is set (1), the user must write ENABLE (bit 0) to TSP_CTRL_0 to release
the hold and power on TSP explicitly.
- Writing ENABLE (bit 0) is a one-shot operation and will auto-clear after execution.
4. Reset Status Clear (via SCU 0x224):
- The reset status can be cleared by writing 1 to bit 9 (RW1C) of SYS_RST_CLR_2,
which will deassert RST_SRC_RB and potentially trigger power-on if no hold is active.
5. TSP Power Control Logic:
- handle_ssp_tsp_on() clears RST_SRC_RB and RST_RB (if not held), and invokes
arm_set_cpu_on_and_reset(cpuid) to power on the TSP core (CPUID 5).
- handle_ssp_tsp_off() sets RST_RB and RST_SRC_RB; if RST is active, also asserts
RST_HOLD_RB and invokes arm_set_cpu_off(cpuid).
The default values are based on EVB (evaluation board) register dump observations.
TSP reset control shares the same helper functions and register bit layout as SSP,
with logic selected by cpuid and distinct external reset sources.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
hw/misc/aspeed_scu.c | 37 ++++++++++++++++++++++++++++++++++++-
1 file changed, 36 insertions(+), 1 deletion(-)
diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c
index 07901f2ab0..2a20253410 100644
--- a/hw/misc/aspeed_scu.c
+++ b/hw/misc/aspeed_scu.c
@@ -147,6 +147,7 @@
/* SSP TSP */
#define AST2700_SCU_SSP_CTRL_0 TO_REG(0x120)
+#define AST2700_SCU_TSP_CTRL_0 TO_REG(0x160)
#define AST2700_SSP_TSP_ENABLE BIT(0)
#define AST2700_SSP_TSP_RST BIT(1)
#define AST2700_SSP_TSP_RST_RB BIT(8)
@@ -155,6 +156,9 @@
#define AST2700_SCU_SYS_RST_CTRL_1 TO_REG(0x200)
#define AST2700_SCU_SYS_RST_CLR_1 TO_REG(0x204)
#define AST2700_SCU_SYS_RST_SSP BIT(30)
+#define AST2700_SCU_SYS_RST_CTRL_2 TO_REG(0x220)
+#define AST2700_SCU_SYS_RST_CLR_2 TO_REG(0x224)
+#define AST2700_SCU_SYS_RST_TSP BIT(9)
#define AST2700_SCU_CLK_SEL_1 TO_REG(0x280)
#define AST2700_SCU_HPLL_PARAM TO_REG(0x300)
@@ -923,7 +927,10 @@ static void aspeed_ast2700_scu_write(void *opaque, hwaddr offset,
switch (reg) {
case AST2700_SCU_SSP_CTRL_0:
- cpuid = a->ssp_cpuid;
+ case AST2700_SCU_TSP_CTRL_0:
+ cpuid = (reg == AST2700_SCU_SSP_CTRL_0) ?
+ a->ssp_cpuid : a->tsp_cpuid;
+
if (cpuid < 0) {
return;
}
@@ -979,6 +986,28 @@ static void aspeed_ast2700_scu_write(void *opaque, hwaddr offset,
}
s->regs[AST2700_SCU_SYS_RST_CTRL_1] &= ~active;
return;
+ case AST2700_SCU_SYS_RST_CTRL_2:
+ if (a->tsp_cpuid < 0) {
+ return;
+ }
+ data &= 0x00001fff;
+ if (data & AST2700_SCU_SYS_RST_TSP) {
+ handle_2700_ssp_tsp_off(s, a->tsp_cpuid, AST2700_SCU_TSP_CTRL_0);
+ }
+ s->regs[reg] |= data;
+ return;
+ case AST2700_SCU_SYS_RST_CLR_2:
+ if (a->tsp_cpuid < 0) {
+ return;
+ }
+ data &= 0x00001fff;
+ oldval = s->regs[AST2700_SCU_SYS_RST_CTRL_2];
+ active = data & oldval;
+ if (active & AST2700_SCU_SYS_RST_TSP) {
+ handle_2700_ssp_tsp_on(s, a->tsp_cpuid, AST2700_SCU_TSP_CTRL_0);
+ }
+ s->regs[AST2700_SCU_SYS_RST_CTRL_2] &= ~active;
+ return;
default:
qemu_log_mask(LOG_GUEST_ERROR,
"%s: Unhandled write at offset 0x%" HWADDR_PRIx "\n",
@@ -1007,7 +1036,9 @@ static const uint32_t ast2700_a0_resets[ASPEED_AST2700_SCU_NR_REGS] = {
[AST2700_HW_STRAP1_SEC2] = 0x00000000,
[AST2700_HW_STRAP1_SEC3] = 0x1000408F,
[AST2700_SCU_SSP_CTRL_0] = 0x000007FE,
+ [AST2700_SCU_TSP_CTRL_0] = 0x000007FE,
[AST2700_SCU_SYS_RST_CTRL_1] = 0xFFC37FDC,
+ [AST2700_SCU_SYS_RST_CTRL_2] = 0x00001FFF,
[AST2700_SCU_HPLL_PARAM] = 0x0000009f,
[AST2700_SCU_HPLL_EXT_PARAM] = 0x8000004f,
[AST2700_SCU_DPLL_PARAM] = 0x0080009f,
@@ -1038,6 +1069,10 @@ static void aspeed_ast2700_scu_reset_hold(Object *obj, ResetType type)
if (a->ssp_cpuid > 0) {
arm_set_cpu_off(a->ssp_cpuid);
}
+
+ if (a->tsp_cpuid > 0) {
+ arm_set_cpu_off(a->tsp_cpuid);
+ }
}
static void aspeed_2700_scu_realize(DeviceState *dev, Error **errp)
--
2.43.0
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH v5 07/10] hw/misc/aspeed_scu: Add SCU support for SSP SDRAM remap
2026-07-08 9:20 [PATCH v5 00/10] Add SSP/TSP power control and DRAM remap support for AST2700 Jamin Lin
` (5 preceding siblings ...)
2026-07-08 9:20 ` [PATCH v5 06/10] hw/misc/aspeed_scu: Implement TSP " Jamin Lin
@ 2026-07-08 9:20 ` Jamin Lin
2026-07-08 9:20 ` [PATCH v5 08/10] hw/misc/aspeed_scu: Add SCU support for TSP " Jamin Lin
` (3 subsequent siblings)
10 siblings, 0 replies; 17+ messages in thread
From: Jamin Lin @ 2026-07-08 9:20 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Kane Chen, Andrew Jeffery, Joel Stanley, Pierrick Bouvier,
open list:ASPEED BMCs, open list:All patches CC here
Cc: Jamin Lin, Troy Lee
This commit adds SCU register support for SSP SDRAM remap control and runtime
activation. It introduces logic for the PSP to dynamically configure the mapping
of its own DRAM windows into SSP-visible SDRAM space, enabling shared memory
communication via memory region aliases.
- coprocessor_sdram_remap[0]: maps PSP DRAM offset 0x400000000 (size: 0x1A77E000) to SSP SDRAM
offset 0x5880000
- coprocessor_sdram_remap[1]: maps PSP DRAM offset 0x42C000000 (size: 0x05880000) to SSP SDRAM
offset 0x0
The SCU registers AST2700_SCU_SSP_CTRL_1/2 and
AST2700_SCU_SSP_REMAP_ADDR_{1,2} / REMAP_SIZE_{1,2} allow runtime reconfiguration
of alias offset, base, and size.
|------------------------------------------| |----------------------------|
| PSP DRAM | | SSP SDRAM |
|------------------------------------------| |----------------------------|
| 0x4_0000_0000 (SCU_124 << 4) | --> | 0x0000_0000 |
| remap1 base |---| | | - SCU_150: target addr |
| size: 0x1A77E000 (SCU_14C) | | | | remap2 |
|------------------------------------------| | | |----------------------------|
| | | | | |
| 0x4_2C00_0000 (SCU_128 << 4) |-----| | 0x5880000 |
| remap2 base | | | - SCU_148: target addr |
| size: 0x05880000 (SCU_154) | |---> | remap1 |
|------------------------------------------| |----------------------------|
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
hw/misc/aspeed_scu.c | 62 ++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 62 insertions(+)
diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c
index 2a20253410..6eeb1b12e1 100644
--- a/hw/misc/aspeed_scu.c
+++ b/hw/misc/aspeed_scu.c
@@ -147,6 +147,14 @@
/* SSP TSP */
#define AST2700_SCU_SSP_CTRL_0 TO_REG(0x120)
+#define AST2700_SCU_SSP_CTRL_1 TO_REG(0x124)
+#define AST2700_SCU_SSP_CTRL_2 TO_REG(0x128)
+#define AST2700_SCU_SSP_REMAP_ADDR_0 TO_REG(0x140)
+#define AST2700_SCU_SSP_REMAP_SIZE_0 TO_REG(0x144)
+#define AST2700_SCU_SSP_REMAP_ADDR_1 TO_REG(0x148)
+#define AST2700_SCU_SSP_REMAP_SIZE_1 TO_REG(0x14C)
+#define AST2700_SCU_SSP_REMAP_ADDR_2 TO_REG(0x150)
+#define AST2700_SCU_SSP_REMAP_SIZE_2 TO_REG(0x154)
#define AST2700_SCU_TSP_CTRL_0 TO_REG(0x160)
#define AST2700_SSP_TSP_ENABLE BIT(0)
#define AST2700_SSP_TSP_RST BIT(1)
@@ -909,6 +917,7 @@ static void aspeed_ast2700_scu_write(void *opaque, hwaddr offset,
{
Aspeed2700SCUState *a = ASPEED_2700_SCU(opaque);
AspeedSCUState *s = ASPEED_SCU(opaque);
+ MemoryRegion *mr = NULL;
int reg = TO_REG(offset);
/* Truncate here so bitwise operations below behave as expected */
uint32_t data = data64;
@@ -966,6 +975,43 @@ static void aspeed_ast2700_scu_write(void *opaque, hwaddr offset,
data &= ~AST2700_SSP_TSP_ENABLE;
s->regs[reg] = (s->regs[reg] & ~0xff) | (data & 0xff);
return;
+ case AST2700_SCU_SSP_CTRL_1:
+ case AST2700_SCU_SSP_CTRL_2:
+ mr = (reg == AST2700_SCU_SSP_CTRL_1) ?
+ &a->dram_remap_alias[0] : &a->dram_remap_alias[1];
+ if (a->ssp_cpuid < 0 || mr == NULL) {
+ return;
+ }
+ data &= 0x7fffffff;
+ memory_region_transaction_begin();
+ memory_region_set_alias_offset(mr,
+ ((uint64_t) data << 4) & 0x3ffffffff);
+ memory_region_transaction_commit();
+ break;
+ case AST2700_SCU_SSP_REMAP_ADDR_1:
+ case AST2700_SCU_SSP_REMAP_ADDR_2:
+ mr = (reg == AST2700_SCU_SSP_REMAP_ADDR_1) ?
+ &a->dram_remap_alias[0] : &a->dram_remap_alias[1];
+ if (a->ssp_cpuid < 0 || mr == NULL) {
+ return;
+ }
+ data &= 0x3fffffff;
+ memory_region_transaction_begin();
+ memory_region_set_address(mr, data);
+ memory_region_transaction_commit();
+ break;
+ case AST2700_SCU_SSP_REMAP_SIZE_1:
+ case AST2700_SCU_SSP_REMAP_SIZE_2:
+ mr = (reg == AST2700_SCU_SSP_REMAP_SIZE_1) ?
+ &a->dram_remap_alias[0] : &a->dram_remap_alias[1];
+ if (a->ssp_cpuid < 0 || mr == NULL) {
+ return;
+ }
+ data &= 0x3fffffff;
+ memory_region_transaction_begin();
+ memory_region_set_size(mr, data);
+ memory_region_transaction_commit();
+ break;
case AST2700_SCU_SYS_RST_CTRL_1:
if (a->ssp_cpuid < 0) {
return;
@@ -1036,6 +1082,14 @@ static const uint32_t ast2700_a0_resets[ASPEED_AST2700_SCU_NR_REGS] = {
[AST2700_HW_STRAP1_SEC2] = 0x00000000,
[AST2700_HW_STRAP1_SEC3] = 0x1000408F,
[AST2700_SCU_SSP_CTRL_0] = 0x000007FE,
+ [AST2700_SCU_SSP_CTRL_1] = 0x40000000,
+ [AST2700_SCU_SSP_CTRL_2] = 0x42C00000,
+ [AST2700_SCU_SSP_REMAP_ADDR_0] = 0x1FFFE000,
+ [AST2700_SCU_SSP_REMAP_SIZE_0] = 0x00002000,
+ [AST2700_SCU_SSP_REMAP_ADDR_1] = 0x05880000,
+ [AST2700_SCU_SSP_REMAP_SIZE_1] = 0x1A77E000,
+ [AST2700_SCU_SSP_REMAP_ADDR_2] = 0x00000000,
+ [AST2700_SCU_SSP_REMAP_SIZE_2] = 0x05880000,
[AST2700_SCU_TSP_CTRL_0] = 0x000007FE,
[AST2700_SCU_SYS_RST_CTRL_1] = 0xFFC37FDC,
[AST2700_SCU_SYS_RST_CTRL_2] = 0x00001FFF,
@@ -1068,6 +1122,14 @@ static void aspeed_ast2700_scu_reset_hold(Object *obj, ResetType type)
if (a->ssp_cpuid > 0) {
arm_set_cpu_off(a->ssp_cpuid);
+ memory_region_transaction_begin();
+ memory_region_set_address(&a->dram_remap_alias[0], 0x5880000);
+ memory_region_set_alias_offset(&a->dram_remap_alias[0], 0);
+ memory_region_set_size(&a->dram_remap_alias[0], 0x1a77e000);
+ memory_region_set_address(&a->dram_remap_alias[1], 0);
+ memory_region_set_alias_offset(&a->dram_remap_alias[1], 0x2c000000);
+ memory_region_set_size(&a->dram_remap_alias[1], 0x5880000);
+ memory_region_transaction_commit();
}
if (a->tsp_cpuid > 0) {
--
2.43.0
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH v5 08/10] hw/misc/aspeed_scu: Add SCU support for TSP SDRAM remap
2026-07-08 9:20 [PATCH v5 00/10] Add SSP/TSP power control and DRAM remap support for AST2700 Jamin Lin
` (6 preceding siblings ...)
2026-07-08 9:20 ` [PATCH v5 07/10] hw/misc/aspeed_scu: Add SCU support for SSP SDRAM remap Jamin Lin
@ 2026-07-08 9:20 ` Jamin Lin
2026-07-08 9:20 ` [PATCH v5 09/10] tests/functional/aarch64/test_aspeed_ast2700fc: Boot SSP/TSP via PSP and load binaries from DRAM Jamin Lin
` (2 subsequent siblings)
10 siblings, 0 replies; 17+ messages in thread
From: Jamin Lin @ 2026-07-08 9:20 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Kane Chen, Andrew Jeffery, Joel Stanley, Pierrick Bouvier,
open list:ASPEED BMCs, open list:All patches CC here
Cc: Jamin Lin, Troy Lee
This commit adds SCU register support for TSP SDRAM remap control and runtime
activation. Unlike SSP, the TSP does not support configurable target address remapping
through SCU registers. It only supports setting the PSP DRAM base and size, which
are then aliased into the TSP-visible SDRAM window.
coprocessor_sdram_remap[2]: maps PSP DRAM offset 0x42E000000 (size: 32MB) to TSP SDRAM
offset 0x0
The SCU registers AST2700_SCU_TSP_CTRL_1 and
AST2700_SCU_TSP_REMAP_SIZE_2 allow runtime reconfiguration of the DRAM base (alias offset)
and mapping size.
|------------------------------------------| |----------------------------|
| PSP DRAM | | TSP SDRAM |
|------------------------------------------| |----------------------------|
| 0x42E0_0000_0 (SCU_168 << 4) | | 0x0000_0000 |
| remap base |------> | - fixed target addr |
| size: 32MB (SCU_194) | | |
|------------------------------------------| |----------------------------|
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
hw/misc/aspeed_scu.c | 29 +++++++++++++++++++++++++++++
1 file changed, 29 insertions(+)
diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c
index 6eeb1b12e1..5c3f563dd5 100644
--- a/hw/misc/aspeed_scu.c
+++ b/hw/misc/aspeed_scu.c
@@ -161,6 +161,8 @@
#define AST2700_SSP_TSP_RST_RB BIT(8)
#define AST2700_SSP_TSP_RST_HOLD_RB BIT(9)
#define AST2700_SSP_TSP_RST_SRC_RB BIT(10)
+#define AST2700_SCU_TSP_CTRL_1 TO_REG(0x168)
+#define AST2700_SCU_TSP_REMAP_SIZE_2 TO_REG(0x194)
#define AST2700_SCU_SYS_RST_CTRL_1 TO_REG(0x200)
#define AST2700_SCU_SYS_RST_CLR_1 TO_REG(0x204)
#define AST2700_SCU_SYS_RST_SSP BIT(30)
@@ -1012,6 +1014,27 @@ static void aspeed_ast2700_scu_write(void *opaque, hwaddr offset,
memory_region_set_size(mr, data);
memory_region_transaction_commit();
break;
+ case AST2700_SCU_TSP_CTRL_1:
+ mr = &a->dram_remap_alias[2];
+ if (a->tsp_cpuid < 0 || mr == NULL) {
+ return;
+ }
+ data &= 0x7fffffff;
+ memory_region_transaction_begin();
+ memory_region_set_alias_offset(mr,
+ ((uint64_t) data << 4) & 0x3ffffffff);
+ memory_region_transaction_commit();
+ break;
+ case AST2700_SCU_TSP_REMAP_SIZE_2:
+ mr = &a->dram_remap_alias[2];
+ if (a->tsp_cpuid < 0 || mr == NULL) {
+ return;
+ }
+ data &= 0x3fffffff;
+ memory_region_transaction_begin();
+ memory_region_set_size(mr, data);
+ memory_region_transaction_commit();
+ break;
case AST2700_SCU_SYS_RST_CTRL_1:
if (a->ssp_cpuid < 0) {
return;
@@ -1091,6 +1114,8 @@ static const uint32_t ast2700_a0_resets[ASPEED_AST2700_SCU_NR_REGS] = {
[AST2700_SCU_SSP_REMAP_ADDR_2] = 0x00000000,
[AST2700_SCU_SSP_REMAP_SIZE_2] = 0x05880000,
[AST2700_SCU_TSP_CTRL_0] = 0x000007FE,
+ [AST2700_SCU_TSP_CTRL_1] = 0x42E00000,
+ [AST2700_SCU_TSP_REMAP_SIZE_2] = 0x02000000,
[AST2700_SCU_SYS_RST_CTRL_1] = 0xFFC37FDC,
[AST2700_SCU_SYS_RST_CTRL_2] = 0x00001FFF,
[AST2700_SCU_HPLL_PARAM] = 0x0000009f,
@@ -1134,6 +1159,10 @@ static void aspeed_ast2700_scu_reset_hold(Object *obj, ResetType type)
if (a->tsp_cpuid > 0) {
arm_set_cpu_off(a->tsp_cpuid);
+ memory_region_transaction_begin();
+ memory_region_set_alias_offset(&a->dram_remap_alias[2], 0x2e000000);
+ memory_region_set_size(&a->dram_remap_alias[2], 32 * MiB);
+ memory_region_transaction_commit();
}
}
--
2.43.0
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH v5 09/10] tests/functional/aarch64/test_aspeed_ast2700fc: Boot SSP/TSP via PSP and load binaries from DRAM
2026-07-08 9:20 [PATCH v5 00/10] Add SSP/TSP power control and DRAM remap support for AST2700 Jamin Lin
` (7 preceding siblings ...)
2026-07-08 9:20 ` [PATCH v5 08/10] hw/misc/aspeed_scu: Add SCU support for TSP " Jamin Lin
@ 2026-07-08 9:20 ` Jamin Lin
2026-07-08 9:20 ` [PATCH v5 10/10] docs: Add support vbootrom and update Manual boot for ast2700fc Jamin Lin
2026-07-08 22:59 ` [PATCH v5 00/10] Add SSP/TSP power control and DRAM remap support for AST2700 Philippe Mathieu-Daudé
10 siblings, 0 replies; 17+ messages in thread
From: Jamin Lin @ 2026-07-08 9:20 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Kane Chen, Andrew Jeffery, Joel Stanley, Pierrick Bouvier,
open list:ASPEED BMCs, open list:All patches CC here
Cc: Jamin Lin, Troy Lee
SSP and TSP now boot in a powered-off state by default. Enabling them requires
the PSP (Cortex-A35) to explicitly set SCU control registers at runtime. This
behavior aligns with real hardware.
Update the AST2700 FC functional test to reflect this behavior by enabling
SSP and TSP from the U-Boot shell before booting OpenBMC. The test now
programs the required SCU registers, saves the environment, and boots the
system so that SSP and TSP are powered on when the PSP starts.
Additionally, switch SSP and TSP loading from ELF-based CPU loaders to
binary images loaded into PSP DRAM at fixed addresses, and remove the use
of snapshot mode.
Changes include:
- Add enable_ast2700_ssp_tsp() to configure SCU registers via U-Boot
- Remove snapshot option from QEMU command line
- Load SSP binary at DRAM address 0x42C000000
- Load TSP binary at DRAM address 0x42E000000
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
.../aarch64/test_aspeed_ast2700fc.py | 29 ++++++++++---------
1 file changed, 16 insertions(+), 13 deletions(-)
diff --git a/tests/functional/aarch64/test_aspeed_ast2700fc.py b/tests/functional/aarch64/test_aspeed_ast2700fc.py
index df889134ed..c0204ceb6c 100755
--- a/tests/functional/aarch64/test_aspeed_ast2700fc.py
+++ b/tests/functional/aarch64/test_aspeed_ast2700fc.py
@@ -23,7 +23,7 @@ def do_test_aarch64_aspeed_sdk_start(self, image):
self.vm.add_args('-device', 'e1000e,netdev=net1,bus=pcie.2')
self.vm.add_args('-netdev', 'user,id=net1')
self.vm.add_args('-drive', 'file=' + image + ',if=mtd,format=raw',
- '-net', 'nic', '-net', 'user', '-snapshot')
+ '-net', 'nic', '-net', 'user')
self.vm.launch()
@@ -31,6 +31,12 @@ def disable_kernel_crypto_selftest(self):
exec_command_and_wait_for_pattern(self,
'setenv bootargs "${bootargs} cryptomgr.notests=1"', '=>')
+ def enable_ast2700_ssp_tsp(self):
+ exec_command_and_wait_for_pattern(self,
+ 'setenv bootcmd "mw 12c02204 40000000; mw 12c02120 1; '
+ 'mw 12c02224 00000200; mw 12c02160 1; run bootspi"', '=>')
+ exec_command_and_wait_for_pattern(self, 'saveenv', 'OK')
+
def enable_ast2700_pcie2(self):
exec_command_and_wait_for_pattern(self,
'cp 100420000 403000000 900000', '=>')
@@ -48,6 +54,7 @@ def verify_openbmc_boot_and_login(self, name):
wait_for_console_pattern(self, 'Hit any key to stop autoboot')
exec_command_and_wait_for_pattern(self, '\012', '=>')
self.disable_kernel_crypto_selftest()
+ self.enable_ast2700_ssp_tsp()
self.enable_ast2700_pcie2()
wait_for_console_pattern(self, 'Starting kernel ...')
@@ -55,16 +62,6 @@ def verify_openbmc_boot_and_login(self, name):
exec_command_and_wait_for_pattern(self, 'root', 'Password:')
exec_command_and_wait_for_pattern(self, '0penBmc', f'root@{name}:~#')
- def load_ast2700fc_coprocessor(self, name):
- load_elf_list = {
- 'ssp': self.scratch_file(name, 'zephyr-aspeed-ssp.elf'),
- 'tsp': self.scratch_file(name, 'zephyr-aspeed-tsp.elf')
- }
-
- for cpu_num, key in enumerate(load_elf_list, start=4):
- file = load_elf_list[key]
- self.vm.add_args('-device',
- f'loader,file={file},cpu-num={cpu_num}')
ASSET_SDK_V1101_AST2700 = Asset(
'https://github.com/AspeedTech-BMC/openbmc/releases/download/v11.01/ast2700-default-image.tar.gz',
@@ -123,6 +120,14 @@ def start_ast2700fc_test(self, name):
'addr': '0x400000000',
'file': self.scratch_file(name, 'u-boot.bin')
},
+ {
+ 'addr': '0x42C000000',
+ 'file': self.scratch_file(name, 'zephyr-aspeed-ssp.bin')
+ },
+ {
+ 'addr': '0x42E000000',
+ 'file': self.scratch_file(name, 'zephyr-aspeed-tsp.bin')
+ },
{
'addr': '0x430000000',
'file': self.scratch_file(name, 'bl31.bin')
@@ -143,13 +148,11 @@ def start_ast2700fc_test(self, name):
self.vm.add_args('-device',
f'loader,addr=0x430000000,cpu-num={i}')
- self.load_ast2700fc_coprocessor(name)
self.do_test_aarch64_aspeed_sdk_start(
self.scratch_file(name, 'image-bmc'))
def start_ast2700fc_test_vbootrom(self, name):
self.vm.add_args('-bios', 'ast27x0_bootrom.bin')
- self.load_ast2700fc_coprocessor(name)
self.do_test_aarch64_aspeed_sdk_start(
self.scratch_file(name, 'image-bmc'))
--
2.43.0
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH v5 10/10] docs: Add support vbootrom and update Manual boot for ast2700fc
2026-07-08 9:20 [PATCH v5 00/10] Add SSP/TSP power control and DRAM remap support for AST2700 Jamin Lin
` (8 preceding siblings ...)
2026-07-08 9:20 ` [PATCH v5 09/10] tests/functional/aarch64/test_aspeed_ast2700fc: Boot SSP/TSP via PSP and load binaries from DRAM Jamin Lin
@ 2026-07-08 9:20 ` Jamin Lin
2026-07-08 22:55 ` Philippe Mathieu-Daudé
2026-07-08 22:59 ` [PATCH v5 00/10] Add SSP/TSP power control and DRAM remap support for AST2700 Philippe Mathieu-Daudé
10 siblings, 1 reply; 17+ messages in thread
From: Jamin Lin @ 2026-07-08 9:20 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Kane Chen, Andrew Jeffery, Joel Stanley, Pierrick Bouvier,
open list:ASPEED BMCs, open list:All patches CC here
Cc: Jamin Lin, Troy Lee
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
docs/system/arm/aspeed.rst | 42 +++++++++++++++++++++++++++++++-------
1 file changed, 35 insertions(+), 7 deletions(-)
diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst
index 2d51ceeb84..b6dd757f6e 100644
--- a/docs/system/arm/aspeed.rst
+++ b/docs/system/arm/aspeed.rst
@@ -386,18 +386,25 @@ Booting the ast2700fc machine
AST2700 features four Cortex-A35 primary processors and two Cortex-M4 coprocessors.
**ast2700-evb** machine focuses on emulating the four Cortex-A35 primary processors,
**ast2700fc** machine extends **ast2700-evb** by adding support for the two Cortex-M4 coprocessors.
+There are two methods to boot the ast2700fc machine.
+
+Manual boot using ``-device loader``:
+
+In this approach, users manually load firmware and assign entry points via QEMU loader devices.
+By default, the PSP begins execution at address ``0x430000000``, the load address of the bl31
+firmware. The SSP and TSP start in the powered-off state and must be explicitly enabled by the
+PSP through writes to SCU registers.
Steps to boot the AST2700fc machine:
-1. Ensure you have the following AST2700A1 binaries available in a directory
+1. Ensure you have the following AST2700 binaries available in a directory
- * u-boot-nodtb.bin
- * u-boot.dtb
+ * u-boot.bin
* bl31.bin
* optee/tee-raw.bin
* image-bmc
- * zephyr-aspeed-ssp.elf (for SSP firmware, CPU 5)
- * zephyr-aspeed-tsp.elf (for TSP firmware, CPU 6)
+ * zephyr-aspeed-ssp.bin (for SSP firmware, CPU 5)
+ * zephyr-aspeed-tsp.bin (for TSP firmware, CPU 6)
2. Execute the following command to start ``ast2700fc`` machine:
@@ -407,6 +414,8 @@ Steps to boot the AST2700fc machine:
$ qemu-system-aarch64 -M ast2700fc \
-device loader,force-raw=on,addr=0x400000000,file=${IMGDIR}/u-boot.bin \
+ -device loader,force-raw=on,addr=0x42C000000,file=${IMGDIR}/zephyr-aspeed-ssp.bin \
+ -device loader,force-raw=on,addr=0x42E000000,file=${IMGDIR}/zephyr-aspeed-tsp.bin \
-device loader,force-raw=on,addr=0x430000000,file=${IMGDIR}/bl31.bin \
-device loader,force-raw=on,addr=0x430080000,file=${IMGDIR}/optee/tee-raw.bin \
-device loader,cpu-num=0,addr=0x430000000 \
@@ -414,12 +423,31 @@ Steps to boot the AST2700fc machine:
-device loader,cpu-num=2,addr=0x430000000 \
-device loader,cpu-num=3,addr=0x430000000 \
-drive file=${IMGDIR}/image-bmc,if=mtd,format=raw \
- -device loader,file=${IMGDIR}/zephyr-aspeed-ssp.elf,cpu-num=4 \
- -device loader,file=${IMGDIR}/zephyr-aspeed-tsp.elf,cpu-num=5 \
-serial pty -serial pty -serial pty \
-snapshot \
-S -nographic
+Boot using a virtual boot ROM (-bios):
+
+In this method, the virtual boot ROM (vbootrom) handles the full initialization sequence.
+It starts the PSP, which then enables the SSP and TSP by programming the appropriate SCU
+registers, following the hardware behavior.
+
+Execute the following command to start ``ast2700fc`` machine:
+
+.. code-block:: bash
+
+ IMGDIR=ast2700-default
+
+ $ qemu-system-aarch64 -M ast2700fc \
+ -bios ast27x0_bootrom.bin \
+ -drive file=${IMGDIR}/image-bmc,if=mtd,format=raw \
+ -serial pty -serial pty -serial pty \
+ -snapshot \
+ -S -nographic
+
+Serial Console Redirection:
+
After launching QEMU, serial devices will be automatically redirected.
Example output:
--
2.43.0
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [PATCH v5 10/10] docs: Add support vbootrom and update Manual boot for ast2700fc
2026-07-08 9:20 ` [PATCH v5 10/10] docs: Add support vbootrom and update Manual boot for ast2700fc Jamin Lin
@ 2026-07-08 22:55 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 17+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-07-08 22:55 UTC (permalink / raw)
To: Jamin Lin, Cédric Le Goater, Pierrick Bouvier, Mark Burton,
Alex Bennée, Daniel Henrique Barboza, Alexander Graf,
Mohamed Mediouni
Cc: Troy Lee, Steven Lee, Peter Maydell, Kane Chen, Joel Stanley,
open list:All patches CC here, Andrew Jeffery,
open list:ASPEED BMCs, Troy Lee
Hello,
On 8/7/26 11:20, Jamin Lin wrote:
> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
> ---
> docs/system/arm/aspeed.rst | 42 +++++++++++++++++++++++++++++++-------
> 1 file changed, 35 insertions(+), 7 deletions(-)
>
> diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst
> index 2d51ceeb84..b6dd757f6e 100644
> --- a/docs/system/arm/aspeed.rst
> +++ b/docs/system/arm/aspeed.rst
> @@ -386,18 +386,25 @@ Booting the ast2700fc machine
> AST2700 features four Cortex-A35 primary processors and two Cortex-M4 coprocessors.
> **ast2700-evb** machine focuses on emulating the four Cortex-A35 primary processors,
> **ast2700fc** machine extends **ast2700-evb** by adding support for the two Cortex-M4 coprocessors.
> +There are two methods to boot the ast2700fc machine.
> +
> +Manual boot using ``-device loader``:
> +
> +In this approach, users manually load firmware and assign entry points via QEMU loader devices.
> +By default, the PSP begins execution at address ``0x430000000``, the load address of the bl31
> +firmware. The SSP and TSP start in the powered-off state and must be explicitly enabled by the
> +PSP through writes to SCU registers.
>
> Steps to boot the AST2700fc machine:
>
> -1. Ensure you have the following AST2700A1 binaries available in a directory
> +1. Ensure you have the following AST2700 binaries available in a directory
>
> - * u-boot-nodtb.bin
> - * u-boot.dtb
> + * u-boot.bin
> * bl31.bin
> * optee/tee-raw.bin
> * image-bmc
> - * zephyr-aspeed-ssp.elf (for SSP firmware, CPU 5)
> - * zephyr-aspeed-tsp.elf (for TSP firmware, CPU 6)
> + * zephyr-aspeed-ssp.bin (for SSP firmware, CPU 5)
> + * zephyr-aspeed-tsp.bin (for TSP firmware, CPU 6)
>
> 2. Execute the following command to start ``ast2700fc`` machine:
>
> @@ -407,6 +414,8 @@ Steps to boot the AST2700fc machine:
>
> $ qemu-system-aarch64 -M ast2700fc \
> -device loader,force-raw=on,addr=0x400000000,file=${IMGDIR}/u-boot.bin \
> + -device loader,force-raw=on,addr=0x42C000000,file=${IMGDIR}/zephyr-aspeed-ssp.bin \
> + -device loader,force-raw=on,addr=0x42E000000,file=${IMGDIR}/zephyr-aspeed-tsp.bin \
> -device loader,force-raw=on,addr=0x430000000,file=${IMGDIR}/bl31.bin \
> -device loader,force-raw=on,addr=0x430080000,file=${IMGDIR}/optee/tee-raw.bin \
> -device loader,cpu-num=0,addr=0x430000000 \
Orthogonal to your work, I found this setup interesting to stress
my work-in-progress 'split-accel' branch, running QEMU with HVF
when possible, otherwise TCG.
I manually started the SSP & TSP first:
=> mw 12c02204 40000000
mw 12c02204 40000000
=> mw 12c02120 1
mw 12c02120 1
=> mw 12c02224 00000200
mw 12c02224 00000200
=> mw 12c02160 1
mw 12c02160 1
Surprisingly I could boot up to the guest login prompt spending
most of the time using HVF
(qemu) info accel
36 transitions, 10943 SW and 86815 HW executions
Accelerator settings:
one-insn-per-tb: off
Translation buffer state:
gen code size 9098100/1072906240
TB count 16086
TB avg target size 14 max=468 bytes
TB avg host size 230 bytes (expansion ratio: 15.8)
cross page TB count 12 (0%)
direct jump count 8371 (52%) (2 jumps=5949 36%)
TB hash buckets 4813/8192 (58.75% head buckets used)
TB hash occupancy 21.05% avg chain occ. Histogram: [0,10)%|█▁▇▁
▃▁▁▁▁|[90,100]%
TB hash avg chain 1.059 buckets. Histogram: 1|█▁|2
Statistics:
TB flush count 0
TB invalidate count 8796
TLB full flushes 0
TLB partial flushes 268
TLB elided flushes 53158
CPU#0: cortex-a35
HVF cumulative execution time: 7.020s
CPU#1: cortex-a35
HVF cumulative execution time: 6.000s
CPU#2: cortex-a35
HVF cumulative execution time: 6.805s
CPU#3: cortex-a35
HVF cumulative execution time: 7.656s
CPU#4: cortex-m4
HVF cumulative execution time: 0.000s
CPU#5: cortex-m4
HVF cumulative execution time: 0.000s
(qemu)
Over 10700 "SW executions" are the M-profiles running,
only 162 correspond to A-profiles :)
Thanks for this motivating setup!
Phil.
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v5 00/10] Add SSP/TSP power control and DRAM remap support for AST2700
2026-07-08 9:20 [PATCH v5 00/10] Add SSP/TSP power control and DRAM remap support for AST2700 Jamin Lin
` (9 preceding siblings ...)
2026-07-08 9:20 ` [PATCH v5 10/10] docs: Add support vbootrom and update Manual boot for ast2700fc Jamin Lin
@ 2026-07-08 22:59 ` Philippe Mathieu-Daudé
2026-07-09 1:03 ` Jamin Lin
10 siblings, 1 reply; 17+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-07-08 22:59 UTC (permalink / raw)
To: Jamin Lin, Cédric Le Goater, Peter Maydell, Steven Lee,
Troy Lee, Kane Chen, Andrew Jeffery, Joel Stanley,
Pierrick Bouvier, open list:ASPEED BMCs,
open list:All patches CC here
Cc: Troy Lee
On 8/7/26 11:20, Jamin Lin wrote:
> This series improves AST2700 platform support by aligning SSP/TSP
> power and reset behavior with hardware, and enabling DRAM remapping
> required for proper firmware boot flow.
> Jamin Lin (10):
> hw/arm/ast27x0: Start SSP in powered-off state to match hardware
> behavior
> hw/arm/ast27x0: Start TSP in powered-off state to match hardware
> behavior
> hw/arm/ast27x0: Add DRAM alias for SSP SDRAM remap
> hw/arm/ast27x0: Add DRAM alias for TSP SDRAM remap
> hw/misc/aspeed_scu: Implement SSP reset and power-on control via SCU
> registers
> hw/misc/aspeed_scu: Implement TSP reset and power-on control via SCU
> registers
> hw/misc/aspeed_scu: Add SCU support for SSP SDRAM remap
> hw/misc/aspeed_scu: Add SCU support for TSP SDRAM remap
> tests/functional/aarch64/test_aspeed_ast2700fc: Boot SSP/TSP via PSP
> and load binaries from DRAM
> docs: Add support vbootrom and update Manual boot for ast2700fc
Series:
Tested-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
2 notes:
1/ I3C errors in dmesg:
[ 8.151230] 14c20000.i3c0: MIPI I3C HCI v0.0 r00
[ 8.151498] 14c20000.i3c0: unsupported HCI version
[ 8.151761] mipi-i3c-hci 14c20000.i3c0: probe with driver
mipi-i3c-hci failed with error -93
[ 8.152250] 14c21000.i3c1: MIPI I3C HCI v0.0 r00
[ 8.152518] 14c21000.i3c1: unsupported HCI version
[ 8.152779] mipi-i3c-hci 14c21000.i3c1: probe with driver
mipi-i3c-hci failed with error -93
[ 8.153322] 14c22000.i3c2: MIPI I3C HCI v0.0 r00
[ 8.153588] 14c22000.i3c2: unsupported HCI version
[ 8.153853] mipi-i3c-hci 14c22000.i3c2: probe with driver
mipi-i3c-hci failed with error -93
...
2/ shutdown not working
[ 246.405297] systemd-shutdown[1]: Entering exitrd...
shutdown: poweroff --timeout=90000000us --log-level info
--log-target=kmsg --log-color --exit-code=0
/shutdown: line 97: poweroff: not found
Execute poweroff -f if all unmounted ok, or exec /init
shutdown-sh#
^ permalink raw reply [flat|nested] 17+ messages in thread* RE: [PATCH v5 00/10] Add SSP/TSP power control and DRAM remap support for AST2700
2026-07-08 22:59 ` [PATCH v5 00/10] Add SSP/TSP power control and DRAM remap support for AST2700 Philippe Mathieu-Daudé
@ 2026-07-09 1:03 ` Jamin Lin
2026-07-09 1:10 ` Jamin Lin
0 siblings, 1 reply; 17+ messages in thread
From: Jamin Lin @ 2026-07-09 1:03 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, Cédric Le Goater, Peter Maydell,
Steven Lee, Troy Lee, Kane Chen, Andrew Jeffery, Joel Stanley,
Pierrick Bouvier, open list:ASPEED BMCs,
open list:All patches CC here
Cc: Troy Lee
Hi Philippe
> On 8/7/26 11:20, Jamin Lin wrote:
> > This series improves AST2700 platform support by aligning SSP/TSP
> > power and reset behavior with hardware, and enabling DRAM remapping
> > required for proper firmware boot flow.
>
>
> > Jamin Lin (10):
> > hw/arm/ast27x0: Start SSP in powered-off state to match hardware
> > behavior
> > hw/arm/ast27x0: Start TSP in powered-off state to match hardware
> > behavior
> > hw/arm/ast27x0: Add DRAM alias for SSP SDRAM remap
> > hw/arm/ast27x0: Add DRAM alias for TSP SDRAM remap
> > hw/misc/aspeed_scu: Implement SSP reset and power-on control via SCU
> > registers
> > hw/misc/aspeed_scu: Implement TSP reset and power-on control via
> SCU
> > registers
> > hw/misc/aspeed_scu: Add SCU support for SSP SDRAM remap
> > hw/misc/aspeed_scu: Add SCU support for TSP SDRAM remap
> > tests/functional/aarch64/test_aspeed_ast2700fc: Boot SSP/TSP via PSP
> > and load binaries from DRAM
> > docs: Add support vbootrom and update Manual boot for ast2700fc
>
> Series:
> Tested-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
>
> 2 notes:
>
> 1/ I3C errors in dmesg:
>
> [ 8.151230] 14c20000.i3c0: MIPI I3C HCI v0.0 r00
> [ 8.151498] 14c20000.i3c0: unsupported HCI version
> [ 8.151761] mipi-i3c-hci 14c20000.i3c0: probe with driver
> mipi-i3c-hci failed with error -93
> [ 8.152250] 14c21000.i3c1: MIPI I3C HCI v0.0 r00
> [ 8.152518] 14c21000.i3c1: unsupported HCI version
> [ 8.152779] mipi-i3c-hci 14c21000.i3c1: probe with driver
> mipi-i3c-hci failed with error -93
> [ 8.153322] 14c22000.i3c2: MIPI I3C HCI v0.0 r00
> [ 8.153588] 14c22000.i3c2: unsupported HCI version
> [ 8.153853] mipi-i3c-hci 14c22000.i3c2: probe with driver
> mipi-i3c-hci failed with error -93
> ...
The AST2700 I3C controller implements the MIPI I3C HCI specification, which is not yet supported by QEMU.
Currently, QEMU only provides an I3C model for the DesignWare controller used on the AST2600.
>
> 2/ shutdown not working
>
> [ 246.405297] systemd-shutdown[1]: Entering exitrd...
> shutdown: poweroff --timeout=90000000us --log-level info --log-target=kmsg
> --log-color --exit-code=0
> /shutdown: line 97: poweroff: not found
> Execute poweroff -f if all unmounted ok, or exec /init shutdown-sh#
OpenBMC currently only supports reboot.
Invoking shutdown causes the system to return to the Linux initramfs instead of powering off.
Thanks,
Jamin
^ permalink raw reply [flat|nested] 17+ messages in thread
* RE: [PATCH v5 00/10] Add SSP/TSP power control and DRAM remap support for AST2700
2026-07-09 1:03 ` Jamin Lin
@ 2026-07-09 1:10 ` Jamin Lin
2026-07-09 1:16 ` Murray-Pitts, Lucien
0 siblings, 1 reply; 17+ messages in thread
From: Jamin Lin @ 2026-07-09 1:10 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, Cédric Le Goater, Peter Maydell,
Steven Lee, Troy Lee, Kane Chen, Andrew Jeffery, Joel Stanley,
Pierrick Bouvier, open list:ASPEED BMCs,
open list:All patches CC here, Nabih Estefan, Joe Komlodi,
Murray-Pitts, Lucien
Cc: Troy Lee
+ Joe(Google), Nabih(Google), Lucien(siemens)
*
> Hi Philippe
>
> > On 8/7/26 11:20, Jamin Lin wrote:
> > > This series improves AST2700 platform support by aligning SSP/TSP
> > > power and reset behavior with hardware, and enabling DRAM remapping
> > > required for proper firmware boot flow.
> >
> >
> > > Jamin Lin (10):
> > > hw/arm/ast27x0: Start SSP in powered-off state to match hardware
> > > behavior
> > > hw/arm/ast27x0: Start TSP in powered-off state to match hardware
> > > behavior
> > > hw/arm/ast27x0: Add DRAM alias for SSP SDRAM remap
> > > hw/arm/ast27x0: Add DRAM alias for TSP SDRAM remap
> > > hw/misc/aspeed_scu: Implement SSP reset and power-on control via
> SCU
> > > registers
> > > hw/misc/aspeed_scu: Implement TSP reset and power-on control via
> > SCU
> > > registers
> > > hw/misc/aspeed_scu: Add SCU support for SSP SDRAM remap
> > > hw/misc/aspeed_scu: Add SCU support for TSP SDRAM remap
> > > tests/functional/aarch64/test_aspeed_ast2700fc: Boot SSP/TSP via PSP
> > > and load binaries from DRAM
> > > docs: Add support vbootrom and update Manual boot for ast2700fc
> >
> > Series:
> > Tested-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
> >
> > 2 notes:
> >
> > 1/ I3C errors in dmesg:
> >
> > [ 8.151230] 14c20000.i3c0: MIPI I3C HCI v0.0 r00
> > [ 8.151498] 14c20000.i3c0: unsupported HCI version
> > [ 8.151761] mipi-i3c-hci 14c20000.i3c0: probe with driver
> > mipi-i3c-hci failed with error -93
> > [ 8.152250] 14c21000.i3c1: MIPI I3C HCI v0.0 r00
> > [ 8.152518] 14c21000.i3c1: unsupported HCI version
> > [ 8.152779] mipi-i3c-hci 14c21000.i3c1: probe with driver
> > mipi-i3c-hci failed with error -93
> > [ 8.153322] 14c22000.i3c2: MIPI I3C HCI v0.0 r00
> > [ 8.153588] 14c22000.i3c2: unsupported HCI version
> > [ 8.153853] mipi-i3c-hci 14c22000.i3c2: probe with driver
> > mipi-i3c-hci failed with error -93
> > ...
>
> The AST2700 I3C controller implements the MIPI I3C HCI specification, which
> is not yet supported by QEMU.
> Currently, QEMU only provides an I3C model for the DesignWare controller
> used on the AST2600.
>
Nabih, Joe, Lucien,
As far as I know, you have implemented support for the I3C HCI controller on the AST2700 platform, and it appears to work well in your local QEMU environment.
Do you have any plans to upstream this work?
If you are planning to upstream the I3C HCI support, it would be greatly appreciated.
Thanks,
Jamin
> >
> > 2/ shutdown not working
> >
> > [ 246.405297] systemd-shutdown[1]: Entering exitrd...
> > shutdown: poweroff --timeout=90000000us --log-level info
> > --log-target=kmsg --log-color --exit-code=0
> > /shutdown: line 97: poweroff: not found Execute poweroff -f if all
> > unmounted ok, or exec /init shutdown-sh#
>
> OpenBMC currently only supports reboot.
> Invoking shutdown causes the system to return to the Linux initramfs instead of
> powering off.
>
> Thanks,
> Jamin
^ permalink raw reply [flat|nested] 17+ messages in thread
* RE: [PATCH v5 00/10] Add SSP/TSP power control and DRAM remap support for AST2700
2026-07-09 1:10 ` Jamin Lin
@ 2026-07-09 1:16 ` Murray-Pitts, Lucien
2026-07-13 4:50 ` Jamin Lin
0 siblings, 1 reply; 17+ messages in thread
From: Murray-Pitts, Lucien @ 2026-07-09 1:16 UTC (permalink / raw)
To: Jamin Lin, Philippe Mathieu-Daudé, Cédric Le Goater,
Peter Maydell, Steven Lee, Troy Lee, Kane Chen, Andrew Jeffery,
Joel Stanley, Pierrick Bouvier, open list:ASPEED BMCs,
open list:All patches CC here, Nabih Estefan, Joe Komlodi
Cc: Troy Lee
Hi Jamin,
> As far as I know, you have implemented support for the I3C HCI controller on the AST2700 platform, and it appears to work well in your local QEMU environment.
The model we wrote was against the Linux kernel drivers specific to the AST2700 kernel drivers we see and are not generic HCI versions.
We have discussed it but weren’t making a huge rush because of internal process of upstreaming from taking time.
If that’s useful and if these are ahead of others in this thread I can expedite the work of upstreaming - please le me know your priorities for that.
Cheers,
Luc
-----Original Message-----
From: Jamin Lin <jamin_lin@aspeedtech.com>
Sent: Thursday, July 9, 2026 10:11 AM
To: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>; Cédric Le Goater <clg@kaod.org>; Peter Maydell <peter.maydell@linaro.org>; Steven Lee <steven_lee@aspeedtech.com>; Troy Lee <leetroy@gmail.com>; Kane Chen <kane_chen@aspeedtech.com>; Andrew Jeffery <andrew@codeconstruct.com.au>; Joel Stanley <joel@jms.id.au>; Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>; open list:ASPEED BMCs <qemu-arm@nongnu.org>; open list:All patches CC here <qemu-devel@nongnu.org>; Nabih Estefan <nabihestefan@google.com>; Joe Komlodi <komlodi@google.com>; Murray-Pitts, Lucien (DI SW EDA HAV SLSPE) <lucien.murray-pitts@siemens.com>
Cc: Troy Lee <troy_lee@aspeedtech.com>
Subject: RE: [PATCH v5 00/10] Add SSP/TSP power control and DRAM remap support for AST2700
+ Joe(Google), Nabih(Google), Lucien(siemens)
*
> Hi Philippe
>
> > On 8/7/26 11:20, Jamin Lin wrote:
> > > This series improves AST2700 platform support by aligning SSP/TSP
> > > power and reset behavior with hardware, and enabling DRAM
> > > remapping required for proper firmware boot flow.
> >
> >
> > > Jamin Lin (10):
> > > hw/arm/ast27x0: Start SSP in powered-off state to match hardware
> > > behavior
> > > hw/arm/ast27x0: Start TSP in powered-off state to match hardware
> > > behavior
> > > hw/arm/ast27x0: Add DRAM alias for SSP SDRAM remap
> > > hw/arm/ast27x0: Add DRAM alias for TSP SDRAM remap
> > > hw/misc/aspeed_scu: Implement SSP reset and power-on control
> > > via
> SCU
> > > registers
> > > hw/misc/aspeed_scu: Implement TSP reset and power-on control
> > > via
> > SCU
> > > registers
> > > hw/misc/aspeed_scu: Add SCU support for SSP SDRAM remap
> > > hw/misc/aspeed_scu: Add SCU support for TSP SDRAM remap
> > > tests/functional/aarch64/test_aspeed_ast2700fc: Boot SSP/TSP via PSP
> > > and load binaries from DRAM
> > > docs: Add support vbootrom and update Manual boot for ast2700fc
> >
> > Series:
> > Tested-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
> >
> > 2 notes:
> >
> > 1/ I3C errors in dmesg:
> >
> > [ 8.151230] 14c20000.i3c0: MIPI I3C HCI v0.0 r00
> > [ 8.151498] 14c20000.i3c0: unsupported HCI version
> > [ 8.151761] mipi-i3c-hci 14c20000.i3c0: probe with driver
> > mipi-i3c-hci failed with error -93
> > [ 8.152250] 14c21000.i3c1: MIPI I3C HCI v0.0 r00
> > [ 8.152518] 14c21000.i3c1: unsupported HCI version
> > [ 8.152779] mipi-i3c-hci 14c21000.i3c1: probe with driver
> > mipi-i3c-hci failed with error -93
> > [ 8.153322] 14c22000.i3c2: MIPI I3C HCI v0.0 r00
> > [ 8.153588] 14c22000.i3c2: unsupported HCI version
> > [ 8.153853] mipi-i3c-hci 14c22000.i3c2: probe with driver
> > mipi-i3c-hci failed with error -93
> > ...
>
> The AST2700 I3C controller implements the MIPI I3C HCI specification,
> which is not yet supported by QEMU.
> Currently, QEMU only provides an I3C model for the DesignWare
> controller used on the AST2600.
>
Nabih, Joe, Lucien,
As far as I know, you have implemented support for the I3C HCI controller on the AST2700 platform, and it appears to work well in your local QEMU environment.
Do you have any plans to upstream this work?
If you are planning to upstream the I3C HCI support, it would be greatly appreciated.
Thanks,
Jamin
> >
> > 2/ shutdown not working
> >
> > [ 246.405297] systemd-shutdown[1]: Entering exitrd...
> > shutdown: poweroff --timeout=90000000us --log-level info
> > --log-target=kmsg --log-color --exit-code=0
> > /shutdown: line 97: poweroff: not found Execute poweroff -f if all
> > unmounted ok, or exec /init shutdown-sh#
>
> OpenBMC currently only supports reboot.
> Invoking shutdown causes the system to return to the Linux initramfs
> instead of powering off.
>
> Thanks,
> Jamin
^ permalink raw reply [flat|nested] 17+ messages in thread
* RE: [PATCH v5 00/10] Add SSP/TSP power control and DRAM remap support for AST2700
2026-07-09 1:16 ` Murray-Pitts, Lucien
@ 2026-07-13 4:50 ` Jamin Lin
0 siblings, 0 replies; 17+ messages in thread
From: Jamin Lin @ 2026-07-13 4:50 UTC (permalink / raw)
To: Murray-Pitts, Lucien, Philippe Mathieu-Daudé,
Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Kane Chen, Andrew Jeffery, Joel Stanley, Pierrick Bouvier,
open list:ASPEED BMCs, open list:All patches CC here,
Nabih Estefan, Joe Komlodi
Cc: Troy Lee
Hi Lucien
>
> Hi Jamin,
>
> > As far as I know, you have implemented support for the I3C HCI controller on
> the AST2700 platform, and it appears to work well in your local QEMU
> environment.
>
> The model we wrote was against the Linux kernel drivers specific to the
> AST2700 kernel drivers we see and are not generic HCI versions.
>
> We have discussed it but weren’t making a huge rush because of internal
> process of upstreaming from taking time.
> If that’s useful and if these are ahead of others in this thread I can expedite
> the work of upstreaming - please le me know your priorities for that.
>
Thank you for your reply.
I'm currently investigating whether customers who have already implemented an I3C HCI model would be willing to upstream their work.
We have also received inquiries from other customers asking about I3C HCI support.
If no existing implementation is expected to be upstreamed, I may consider working on this task and contributing it upstream myself.
This is not a top priority or an urgent task at the moment.
I'm simply trying to understand whether there are any plans to upstream an existing implementation so that we can decide whether ASPEED should invest effort in developing this model.
If your team is planning to upstream your implementation, I would greatly appreciate it.
Thanks,
Jamin
> Cheers,
> Luc
>
> -----Original Message-----
> From: Jamin Lin <jamin_lin@aspeedtech.com>
> Sent: Thursday, July 9, 2026 10:11 AM
> To: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>; Cédric Le Goater
> <clg@kaod.org>; Peter Maydell <peter.maydell@linaro.org>; Steven Lee
> <steven_lee@aspeedtech.com>; Troy Lee <leetroy@gmail.com>; Kane Chen
> <kane_chen@aspeedtech.com>; Andrew Jeffery
> <andrew@codeconstruct.com.au>; Joel Stanley <joel@jms.id.au>; Pierrick
> Bouvier <pierrick.bouvier@oss.qualcomm.com>; open list:ASPEED BMCs
> <qemu-arm@nongnu.org>; open list:All patches CC here
> <qemu-devel@nongnu.org>; Nabih Estefan <nabihestefan@google.com>; Joe
> Komlodi <komlodi@google.com>; Murray-Pitts, Lucien (DI SW EDA HAV SLSPE)
> <lucien.murray-pitts@siemens.com>
> Cc: Troy Lee <troy_lee@aspeedtech.com>
> Subject: RE: [PATCH v5 00/10] Add SSP/TSP power control and DRAM remap
> support for AST2700
>
> + Joe(Google), Nabih(Google), Lucien(siemens)
>
> *
> > Hi Philippe
> >
> > > On 8/7/26 11:20, Jamin Lin wrote:
> > > > This series improves AST2700 platform support by aligning SSP/TSP
> > > > power and reset behavior with hardware, and enabling DRAM
> > > > remapping required for proper firmware boot flow.
> > >
> > >
> > > > Jamin Lin (10):
> > > > hw/arm/ast27x0: Start SSP in powered-off state to match hardware
> > > > behavior
> > > > hw/arm/ast27x0: Start TSP in powered-off state to match hardware
> > > > behavior
> > > > hw/arm/ast27x0: Add DRAM alias for SSP SDRAM remap
> > > > hw/arm/ast27x0: Add DRAM alias for TSP SDRAM remap
> > > > hw/misc/aspeed_scu: Implement SSP reset and power-on control
> > > > via
> > SCU
> > > > registers
> > > > hw/misc/aspeed_scu: Implement TSP reset and power-on control
> > > > via
> > > SCU
> > > > registers
> > > > hw/misc/aspeed_scu: Add SCU support for SSP SDRAM remap
> > > > hw/misc/aspeed_scu: Add SCU support for TSP SDRAM remap
> > > > tests/functional/aarch64/test_aspeed_ast2700fc: Boot SSP/TSP via
> PSP
> > > > and load binaries from DRAM
> > > > docs: Add support vbootrom and update Manual boot for ast2700fc
> > >
> > > Series:
> > > Tested-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
> > >
> > > 2 notes:
> > >
> > > 1/ I3C errors in dmesg:
> > >
> > > [ 8.151230] 14c20000.i3c0: MIPI I3C HCI v0.0 r00
> > > [ 8.151498] 14c20000.i3c0: unsupported HCI version
> > > [ 8.151761] mipi-i3c-hci 14c20000.i3c0: probe with driver
> > > mipi-i3c-hci failed with error -93
> > > [ 8.152250] 14c21000.i3c1: MIPI I3C HCI v0.0 r00
> > > [ 8.152518] 14c21000.i3c1: unsupported HCI version
> > > [ 8.152779] mipi-i3c-hci 14c21000.i3c1: probe with driver
> > > mipi-i3c-hci failed with error -93
> > > [ 8.153322] 14c22000.i3c2: MIPI I3C HCI v0.0 r00
> > > [ 8.153588] 14c22000.i3c2: unsupported HCI version
> > > [ 8.153853] mipi-i3c-hci 14c22000.i3c2: probe with driver
> > > mipi-i3c-hci failed with error -93
> > > ...
> >
> > The AST2700 I3C controller implements the MIPI I3C HCI specification,
> > which is not yet supported by QEMU.
> > Currently, QEMU only provides an I3C model for the DesignWare
> > controller used on the AST2600.
> >
> Nabih, Joe, Lucien,
>
> As far as I know, you have implemented support for the I3C HCI controller on
> the AST2700 platform, and it appears to work well in your local QEMU
> environment.
> Do you have any plans to upstream this work?
> If you are planning to upstream the I3C HCI support, it would be greatly
> appreciated.
>
> Thanks,
> Jamin
> > >
> > > 2/ shutdown not working
> > >
> > > [ 246.405297] systemd-shutdown[1]: Entering exitrd...
> > > shutdown: poweroff --timeout=90000000us --log-level info
> > > --log-target=kmsg --log-color --exit-code=0
> > > /shutdown: line 97: poweroff: not found Execute poweroff -f if all
> > > unmounted ok, or exec /init shutdown-sh#
> >
> > OpenBMC currently only supports reboot.
> > Invoking shutdown causes the system to return to the Linux initramfs
> > instead of powering off.
> >
> > Thanks,
> > Jamin
^ permalink raw reply [flat|nested] 17+ messages in thread