* [PATCH v6 01/11] hw/arm/aspeed_ast1700: Correct AST2700 SCU to SCUIO
2026-07-23 2:23 [PATCH v6 00/11] Add SSP/TSP power control and DRAM remap support for AST2700 Jamin Lin
@ 2026-07-23 2:23 ` Jamin Lin
2026-07-23 2:23 ` [PATCH v6 02/11] hw/arm/ast27x0: Start SSP in powered-off state to match hardware behavior Jamin Lin
` (9 subsequent siblings)
10 siblings, 0 replies; 12+ messages in thread
From: Jamin Lin @ 2026-07-23 2:23 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Kane Chen, Andrew Jeffery, Joel Stanley, Pierrick Bouvier,
open list:ASPEED BMCs, open list:All patches CC here
Cc: Jamin Lin, Troy Lee
Per the AST1700 datasheet, its SCU register layout matches the AST2700
SCUIO (I/O-die SCU), not the AST2700 SCU. Correct the I/O expander to
instantiate TYPE_ASPEED_2700_SCUIO instead of TYPE_ASPEED_2700_SCU, and
rename the "scu" field/property to "scuio" throughout
aspeed_ast1700.c/h so the type change is clear at every call site.
Fixes: b500ab00552da06566a505a397255f4c031670aa ("hw/arm/aspeed: Attach SCU device to AST1700 model")
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Kane Chen <kane_chen@aspeedtech.com>
---
include/hw/arm/aspeed_ast1700.h | 2 +-
hw/arm/aspeed_ast1700.c | 22 +++++++++++-----------
2 files changed, 12 insertions(+), 12 deletions(-)
diff --git a/include/hw/arm/aspeed_ast1700.h b/include/hw/arm/aspeed_ast1700.h
index 39c5977cf1..86bdb266b0 100644
--- a/include/hw/arm/aspeed_ast1700.h
+++ b/include/hw/arm/aspeed_ast1700.h
@@ -41,7 +41,7 @@ struct AspeedAST1700SoCState {
MemoryRegion sram;
AspeedSMCState spi;
AspeedADCState adc;
- Aspeed2700SCUState scu;
+ AspeedSCUState scuio;
AspeedGPIOState gpio;
AspeedSGPIOState sgpiom[AST1700_SGPIO_NUM];
AspeedI2CState i2c;
diff --git a/hw/arm/aspeed_ast1700.c b/hw/arm/aspeed_ast1700.c
index 5af5da5b8a..418c9fcd45 100644
--- a/hw/arm/aspeed_ast1700.c
+++ b/hw/arm/aspeed_ast1700.c
@@ -22,7 +22,7 @@ enum {
ASPEED_AST1700_DEV_PWM,
ASPEED_AST1700_DEV_SRAM,
ASPEED_AST1700_DEV_ADC,
- ASPEED_AST1700_DEV_SCU,
+ ASPEED_AST1700_DEV_SCUIO,
ASPEED_AST1700_DEV_GPIO,
ASPEED_AST1700_DEV_SGPIOM0,
ASPEED_AST1700_DEV_SGPIOM1,
@@ -39,7 +39,7 @@ static const hwaddr aspeed_ast1700_io_memmap[] = {
[ASPEED_AST1700_DEV_PWM] = 0x000C0000,
[ASPEED_AST1700_DEV_SRAM] = 0x00BC0000,
[ASPEED_AST1700_DEV_ADC] = 0x00C00000,
- [ASPEED_AST1700_DEV_SCU] = 0x00C02000,
+ [ASPEED_AST1700_DEV_SCUIO] = 0x00C02000,
[ASPEED_AST1700_DEV_GPIO] = 0x00C0B000,
[ASPEED_AST1700_DEV_SGPIOM0] = 0x00C0C000,
[ASPEED_AST1700_DEV_SGPIOM1] = 0x00C0D000,
@@ -108,15 +108,15 @@ static void aspeed_ast1700_realize(DeviceState *dev, Error **errp)
aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_ADC],
sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->adc), 0));
- /* SCU */
- qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev",
+ /* SCUIO */
+ qdev_prop_set_uint32(DEVICE(&s->scuio), "silicon-rev",
s->silicon_rev);
- if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) {
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->scuio), errp)) {
return;
}
memory_region_add_subregion(&s->iomem,
- aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_SCU],
- sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->scu), 0));
+ aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_SCUIO],
+ sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->scuio), 0));
/* GPIO */
if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) {
@@ -171,7 +171,7 @@ static void aspeed_ast1700_realize(DeviceState *dev, Error **errp)
hwaddr wdt_offset = aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_WDT] +
i * awc->iosize;
- object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu),
+ object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scuio),
errp);
if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) {
return;
@@ -207,9 +207,9 @@ static void aspeed_ast1700_instance_init(Object *obj)
object_initialize_child(obj, "ioexp-adc", &s->adc,
"aspeed.adc-ast2700");
- /* SCU */
- object_initialize_child(obj, "ioexp-scu", &s->scu,
- TYPE_ASPEED_2700_SCU);
+ /* SCUIO */
+ object_initialize_child(obj, "ioexp-scu", &s->scuio,
+ TYPE_ASPEED_2700_SCUIO);
/* GPIO */
object_initialize_child(obj, "ioexp-gpio", &s->gpio,
--
2.43.0
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH v6 02/11] hw/arm/ast27x0: Start SSP in powered-off state to match hardware behavior
2026-07-23 2:23 [PATCH v6 00/11] Add SSP/TSP power control and DRAM remap support for AST2700 Jamin Lin
2026-07-23 2:23 ` [PATCH v6 01/11] hw/arm/aspeed_ast1700: Correct AST2700 SCU to SCUIO Jamin Lin
@ 2026-07-23 2:23 ` Jamin Lin
2026-07-23 2:23 ` [PATCH v6 03/11] hw/arm/ast27x0: Start TSP " Jamin Lin
` (8 subsequent siblings)
10 siblings, 0 replies; 12+ messages in thread
From: Jamin Lin @ 2026-07-23 2:23 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Kane Chen, Andrew Jeffery, Joel Stanley, Pierrick Bouvier,
open list:ASPEED BMCs, open list:All patches CC here
Cc: Jamin Lin, Troy Lee, Cédric Le Goater,
Philippe Mathieu-Daudé
In the previous design, both the PSP and SSP were started together during
SoC initialization. However, on real hardware, the SSP begins in a powered-off
state. The typical boot sequence involves the PSP powering up first, loading
the SSP firmware binary into shared memory via DRAM remap, and then releasing
the SSP reset and enabling it through SCU control registers.
To more accurately model this behavior in QEMU, this commit sets the
"start-powered-off" property for the SSP's ARMv7M core. This change ensures
the SSP remains off until explicitly enabled via the SCU, simulating the
real-world flow where the PSP controls SSP boot through SCU interaction.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Tested-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
---
hw/arm/aspeed_ast27x0-ssp.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/hw/arm/aspeed_ast27x0-ssp.c b/hw/arm/aspeed_ast27x0-ssp.c
index e03653086c..9c984d23cd 100644
--- a/hw/arm/aspeed_ast27x0-ssp.c
+++ b/hw/arm/aspeed_ast27x0-ssp.c
@@ -192,6 +192,13 @@ static void aspeed_soc_ast27x0ssp_realize(DeviceState *dev_soc, Error **errp)
qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk);
object_property_set_link(OBJECT(&a->armv7m), "memory",
OBJECT(s->memory), &error_abort);
+ /*
+ * The SSP starts in a powered-down state and can be powered up
+ * by setting the SSP Control Register through the SCU
+ * (System Control Unit)
+ */
+ object_property_set_bool(OBJECT(&a->armv7m), "start-powered-off", true,
+ &error_abort);
sysbus_realize(SYS_BUS_DEVICE(&a->armv7m), &error_abort);
/* SDRAM */
--
2.43.0
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH v6 03/11] hw/arm/ast27x0: Start TSP in powered-off state to match hardware behavior
2026-07-23 2:23 [PATCH v6 00/11] Add SSP/TSP power control and DRAM remap support for AST2700 Jamin Lin
2026-07-23 2:23 ` [PATCH v6 01/11] hw/arm/aspeed_ast1700: Correct AST2700 SCU to SCUIO Jamin Lin
2026-07-23 2:23 ` [PATCH v6 02/11] hw/arm/ast27x0: Start SSP in powered-off state to match hardware behavior Jamin Lin
@ 2026-07-23 2:23 ` Jamin Lin
2026-07-23 2:23 ` [PATCH v6 04/11] hw/arm/ast27x0: Add DRAM alias for SSP SDRAM remap Jamin Lin
` (7 subsequent siblings)
10 siblings, 0 replies; 12+ messages in thread
From: Jamin Lin @ 2026-07-23 2:23 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Kane Chen, Andrew Jeffery, Joel Stanley, Pierrick Bouvier,
open list:ASPEED BMCs, open list:All patches CC here
Cc: Jamin Lin, Troy Lee, Cédric Le Goater,
Philippe Mathieu-Daudé
In the previous design, both the PSP and TSP were started together during
SoC initialization. However, on real hardware, the TSP begins in a powered-off
state. The typical boot sequence involves the PSP powering up first, loading
the TSP firmware binary into shared memory via DRAM remap, and then releasing
the TSP reset and enabling it through SCU control registers.
To more accurately model this behavior in QEMU, this commit sets the
"start-powered-off" property for the TSP's ARMv7M core. This change ensures
the TSP remains off until explicitly enabled via the SCU, simulating the
real-world flow where the PSP controls TSP boot through SCU interaction.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Tested-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
---
hw/arm/aspeed_ast27x0-tsp.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/hw/arm/aspeed_ast27x0-tsp.c b/hw/arm/aspeed_ast27x0-tsp.c
index 39ba062a20..4212e7bd4c 100644
--- a/hw/arm/aspeed_ast27x0-tsp.c
+++ b/hw/arm/aspeed_ast27x0-tsp.c
@@ -192,6 +192,13 @@ static void aspeed_soc_ast27x0tsp_realize(DeviceState *dev_soc, Error **errp)
qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk);
object_property_set_link(OBJECT(&a->armv7m), "memory",
OBJECT(s->memory), &error_abort);
+ /*
+ * The TSP starts in a powered-down state and can be powered up
+ * by setting the TSP Control Register through the SCU
+ * (System Control Unit)
+ */
+ object_property_set_bool(OBJECT(&a->armv7m), "start-powered-off", true,
+ &error_abort);
sysbus_realize(SYS_BUS_DEVICE(&a->armv7m), &error_abort);
/* SDRAM */
--
2.43.0
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH v6 04/11] hw/arm/ast27x0: Add DRAM alias for SSP SDRAM remap
2026-07-23 2:23 [PATCH v6 00/11] Add SSP/TSP power control and DRAM remap support for AST2700 Jamin Lin
` (2 preceding siblings ...)
2026-07-23 2:23 ` [PATCH v6 03/11] hw/arm/ast27x0: Start TSP " Jamin Lin
@ 2026-07-23 2:23 ` Jamin Lin
2026-07-23 2:23 ` [PATCH v6 05/11] hw/arm/ast27x0: Add DRAM alias for TSP " Jamin Lin
` (6 subsequent siblings)
10 siblings, 0 replies; 12+ messages in thread
From: Jamin Lin @ 2026-07-23 2:23 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Kane Chen, Andrew Jeffery, Joel Stanley, Pierrick Bouvier,
open list:ASPEED BMCs, open list:All patches CC here
Cc: Jamin Lin, Troy Lee, Philippe Mathieu-Daudé
This commit adds two MemoryRegion aliases to support PSP access to
SSP SDRAM through shared memory remapping.
The SSP exposes two DRAM aliases:
- remap1 maps PSP DRAM at 0x400000000 to SSP SDRAM offset 0x5880000
- remap2 maps PSP DRAM at 0x42C000000 to SSP SDRAM offset 0x0
These mappings follow the default SCU register configuration used by
the ASPEED SDK firmware, which defines the memory window mapping
between PSP and the SSP.
The alias MemoryRegions belong to the SSP coprocessor state itself
(Aspeed27x0CoprocessorState), since that is what they represent; the
SCU only holds pointers to them (ssp_remap[0]/ssp_remap[1]) so its
control registers can reposition/resize the aliases at runtime. These
can't be QOM link properties since the SCU is already realized by the
time the SSP sets them, so the pointers are written in directly.
The SSP cpu_index is only known once the SSP's armv7m core is
realized, so it is written directly into the shared SCU at that
point. Its "not wired up" default of -1 is now set explicitly in the
SCU's own realize(), since nothing else sets it via a QOM property
anymore.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Tested-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
---
include/hw/arm/aspeed_coprocessor.h | 2 ++
include/hw/misc/aspeed_scu.h | 3 +++
hw/arm/aspeed_ast27x0-fc.c | 2 ++
hw/arm/aspeed_ast27x0-ssp.c | 38 +++++++++++++++++++++++++++++
hw/misc/aspeed_scu.c | 3 +++
5 files changed, 48 insertions(+)
diff --git a/include/hw/arm/aspeed_coprocessor.h b/include/hw/arm/aspeed_coprocessor.h
index 23c3b97f06..d9d0ae7b6d 100644
--- a/include/hw/arm/aspeed_coprocessor.h
+++ b/include/hw/arm/aspeed_coprocessor.h
@@ -52,6 +52,8 @@ struct Aspeed27x0CoprocessorState {
MemoryRegion scu_alias;
MemoryRegion scuio_alias;
MemoryRegion fmc_alias;
+ MemoryRegion dram_remap[2];
+ MemoryRegion *dram;
Aspeed2700SCUState *scu;
AspeedSCUState *scuio;
AspeedSMCState *fmc;
diff --git a/include/hw/misc/aspeed_scu.h b/include/hw/misc/aspeed_scu.h
index 904549465f..01e8854104 100644
--- a/include/hw/misc/aspeed_scu.h
+++ b/include/hw/misc/aspeed_scu.h
@@ -44,6 +44,9 @@ struct AspeedSCUState {
struct Aspeed2700SCUState {
AspeedSCUState parent_obj;
+
+ MemoryRegion *ssp_remap[2];
+ int ssp_cpuid;
};
#define AST2400_A1_SILICON_REV 0x02010303U
diff --git a/hw/arm/aspeed_ast27x0-fc.c b/hw/arm/aspeed_ast27x0-fc.c
index 058cea42ed..af700e748f 100644
--- a/hw/arm/aspeed_ast27x0-fc.c
+++ b/hw/arm/aspeed_ast27x0-fc.c
@@ -155,6 +155,8 @@ static bool ast2700fc_ssp_init(Ast2700FCState *s, AspeedSoCState *psp,
&error_abort);
object_property_set_link(OBJECT(&s->ssp), "sram",
OBJECT(&psp->sram), &error_abort);
+ object_property_set_link(OBJECT(&s->ssp), "dram",
+ OBJECT(psp->dram_mr), &error_abort);
object_property_set_link(OBJECT(&s->ssp), "scu",
OBJECT(&s->ca35.scu), &error_abort);
object_property_set_link(OBJECT(&s->ssp), "scuio",
diff --git a/hw/arm/aspeed_ast27x0-ssp.c b/hw/arm/aspeed_ast27x0-ssp.c
index 9c984d23cd..2b0cf5041f 100644
--- a/hw/arm/aspeed_ast27x0-ssp.c
+++ b/hw/arm/aspeed_ast27x0-ssp.c
@@ -184,6 +184,12 @@ static void aspeed_soc_ast27x0ssp_realize(DeviceState *dev_soc, Error **errp)
return;
}
+ if (!a->dram) {
+ error_setg(errp, TYPE_ASPEED27X0SSP_COPROCESSOR
+ ": 'dram' link is not set");
+ return;
+ }
+
/* AST27X0 SSP Core */
armv7m = DEVICE(&a->armv7m);
qdev_prop_set_uint32(armv7m, "num-irq", 256);
@@ -201,6 +207,12 @@ static void aspeed_soc_ast27x0ssp_realize(DeviceState *dev_soc, Error **errp)
&error_abort);
sysbus_realize(SYS_BUS_DEVICE(&a->armv7m), &error_abort);
+ /*
+ * cpu_index is only known once the armv7m core above is realized;
+ * write it directly into the shared SCU.
+ */
+ a->scu->ssp_cpuid = CPU(a->armv7m.cpu)->cpu_index;
+
/* SDRAM */
sdram_name = g_strdup_printf("aspeed.sdram.%d",
CPU(a->armv7m.cpu)->cpu_index);
@@ -232,6 +244,30 @@ static void aspeed_soc_ast27x0ssp_realize(DeviceState *dev_soc, Error **errp)
memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SCUIO],
&a->scuio_alias);
+ /*
+ * DRAM remap aliases used by PSP to access SSP SDRAM:
+ * - remap[0] maps PSP DRAM at 0x400000000 (size: 0x1A77E000) to
+ * SSP SDRAM offset 0x5880000
+ * - remap[1] maps PSP DRAM at 0x42C000000 (size: 0x05880000) to
+ * SSP SDRAM offset 0x0
+ */
+ memory_region_init_alias(&a->dram_remap[0], OBJECT(a), "ssp.dram.remap1",
+ a->dram, 0, 0x1a77e000);
+ memory_region_init_alias(&a->dram_remap[1], OBJECT(a), "ssp.dram.remap2",
+ a->dram, 0x2c000000, 0x05880000);
+ memory_region_add_subregion(&s->sdram, 0, &a->dram_remap[1]);
+ memory_region_add_subregion(&s->sdram,
+ memory_region_size(&a->dram_remap[1]),
+ &a->dram_remap[0]);
+
+ /*
+ * The SCU is already realized at this point (it belongs to the PSP,
+ * which is realized before the SSP), so the remaps are linked in
+ * directly instead of via QOM properties.
+ */
+ a->scu->ssp_remap[0] = &a->dram_remap[0];
+ a->scu->ssp_remap[1] = &a->dram_remap[1];
+
/* INTC */
if (!sysbus_realize(SYS_BUS_DEVICE(&a->intc[0]), errp)) {
return;
@@ -317,6 +353,8 @@ static const Property aspeed_27x0_coprocessor_properties[] = {
TYPE_ASPEED_SCU, AspeedSCUState *),
DEFINE_PROP_LINK("fmc", Aspeed27x0CoprocessorState, fmc, TYPE_ASPEED_SMC,
AspeedSMCState *),
+ DEFINE_PROP_LINK("dram", Aspeed27x0CoprocessorState, dram,
+ TYPE_MEMORY_REGION, MemoryRegion *),
};
static void aspeed_soc_ast27x0ssp_class_init(ObjectClass *klass,
diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c
index ca93c3699d..4025ea3205 100644
--- a/hw/misc/aspeed_scu.c
+++ b/hw/misc/aspeed_scu.c
@@ -932,6 +932,9 @@ static void aspeed_ast2700_scu_reset_hold(Object *obj, ResetType type)
static void aspeed_2700_scu_realize(DeviceState *dev, Error **errp)
{
+ Aspeed2700SCUState *a = ASPEED_2700_SCU(dev);
+
+ a->ssp_cpuid = -1;
aspeed_scu_realize(dev, errp);
}
--
2.43.0
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH v6 05/11] hw/arm/ast27x0: Add DRAM alias for TSP SDRAM remap
2026-07-23 2:23 [PATCH v6 00/11] Add SSP/TSP power control and DRAM remap support for AST2700 Jamin Lin
` (3 preceding siblings ...)
2026-07-23 2:23 ` [PATCH v6 04/11] hw/arm/ast27x0: Add DRAM alias for SSP SDRAM remap Jamin Lin
@ 2026-07-23 2:23 ` Jamin Lin
2026-07-23 2:23 ` [PATCH v6 06/11] hw/misc/aspeed_scu: Implement SSP reset and power-on control via SCU registers Jamin Lin
` (5 subsequent siblings)
10 siblings, 0 replies; 12+ messages in thread
From: Jamin Lin @ 2026-07-23 2:23 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Kane Chen, Andrew Jeffery, Joel Stanley, Pierrick Bouvier,
open list:ASPEED BMCs, open list:All patches CC here
Cc: Jamin Lin, Troy Lee, Philippe Mathieu-Daudé
This commit adds a MemoryRegion alias to support PSP access to
TSP SDRAM through shared memory remapping.
The TSP coprocessor exposes one DRAM alias:
- remap maps PSP DRAM at 0x42E000000 to TSP SDRAM offset 0x0
These mappings follow the default SCU register configuration used by
the ASPEED SDK firmware, which defines the memory window mapping
between PSP and TSP.
The alias MemoryRegion belongs to the TSP coprocessor state itself
(Aspeed27x0CoprocessorState), mirroring the SSP remap; the SCU only
holds a pointer to it (tsp_remap) so its control registers can
reposition/resize the alias at runtime. This can't be a QOM link
property since the SCU is already realized by the time the TSP sets
it, so the pointer is written in directly.
The TSP cpu_index is only known once the TSP's armv7m core is
realized, so it is written directly into the shared SCU at that
point. Its "not wired up" default of -1 is now set explicitly in the
SCU's own realize(), since nothing else sets it via a QOM property
anymore.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Tested-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
---
include/hw/misc/aspeed_scu.h | 2 ++
hw/arm/aspeed_ast27x0-fc.c | 2 ++
hw/arm/aspeed_ast27x0-tsp.c | 30 ++++++++++++++++++++++++++++++
hw/misc/aspeed_scu.c | 1 +
4 files changed, 35 insertions(+)
diff --git a/include/hw/misc/aspeed_scu.h b/include/hw/misc/aspeed_scu.h
index 01e8854104..aef13e8915 100644
--- a/include/hw/misc/aspeed_scu.h
+++ b/include/hw/misc/aspeed_scu.h
@@ -46,7 +46,9 @@ struct Aspeed2700SCUState {
AspeedSCUState parent_obj;
MemoryRegion *ssp_remap[2];
+ MemoryRegion *tsp_remap;
int ssp_cpuid;
+ int tsp_cpuid;
};
#define AST2400_A1_SILICON_REV 0x02010303U
diff --git a/hw/arm/aspeed_ast27x0-fc.c b/hw/arm/aspeed_ast27x0-fc.c
index af700e748f..e51d8024eb 100644
--- a/hw/arm/aspeed_ast27x0-fc.c
+++ b/hw/arm/aspeed_ast27x0-fc.c
@@ -191,6 +191,8 @@ static bool ast2700fc_tsp_init(Ast2700FCState *s, AspeedSoCState *psp,
&error_abort);
object_property_set_link(OBJECT(&s->tsp), "sram",
OBJECT(&psp->sram), &error_abort);
+ object_property_set_link(OBJECT(&s->tsp), "dram",
+ OBJECT(psp->dram_mr), &error_abort);
object_property_set_link(OBJECT(&s->tsp), "scu",
OBJECT(&s->ca35.scu), &error_abort);
object_property_set_link(OBJECT(&s->tsp), "scuio",
diff --git a/hw/arm/aspeed_ast27x0-tsp.c b/hw/arm/aspeed_ast27x0-tsp.c
index 4212e7bd4c..9a860f6ea3 100644
--- a/hw/arm/aspeed_ast27x0-tsp.c
+++ b/hw/arm/aspeed_ast27x0-tsp.c
@@ -184,6 +184,12 @@ static void aspeed_soc_ast27x0tsp_realize(DeviceState *dev_soc, Error **errp)
return;
}
+ if (!a->dram) {
+ error_setg(errp, TYPE_ASPEED27X0TSP_COPROCESSOR
+ ": 'dram' link is not set");
+ return;
+ }
+
/* AST27X0 TSP Core */
armv7m = DEVICE(&a->armv7m);
qdev_prop_set_uint32(armv7m, "num-irq", 256);
@@ -201,6 +207,12 @@ static void aspeed_soc_ast27x0tsp_realize(DeviceState *dev_soc, Error **errp)
&error_abort);
sysbus_realize(SYS_BUS_DEVICE(&a->armv7m), &error_abort);
+ /*
+ * cpu_index is only known once the armv7m core above is realized;
+ * write it directly into the shared SCU.
+ */
+ a->scu->tsp_cpuid = CPU(a->armv7m.cpu)->cpu_index;
+
/* SDRAM */
sdram_name = g_strdup_printf("aspeed.sdram.%d",
CPU(a->armv7m.cpu)->cpu_index);
@@ -232,6 +244,22 @@ static void aspeed_soc_ast27x0tsp_realize(DeviceState *dev_soc, Error **errp)
memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SCUIO],
&a->scuio_alias);
+ /*
+ * DRAM remap alias used by PSP to access TSP SDRAM:
+ * - remap maps PSP DRAM at 0x42E000000 (size: 32MB) to TSP SDRAM
+ * offset 0x0
+ */
+ memory_region_init_alias(&a->dram_remap[0], OBJECT(a), "tsp.dram.remap",
+ a->dram, 0x2e000000, 32 * MiB);
+ memory_region_add_subregion(&s->sdram, 0, &a->dram_remap[0]);
+
+ /*
+ * The SCU is already realized at this point (it belongs to the PSP,
+ * which is realized before the TSP), so the remap is linked in
+ * directly instead of via a QOM property.
+ */
+ a->scu->tsp_remap = &a->dram_remap[0];
+
/* INTC */
if (!sysbus_realize(SYS_BUS_DEVICE(&a->intc[0]), errp)) {
return;
@@ -317,6 +345,8 @@ static const Property aspeed_27x0_coprocessor_properties[] = {
TYPE_ASPEED_SCU, AspeedSCUState *),
DEFINE_PROP_LINK("fmc", Aspeed27x0CoprocessorState, fmc, TYPE_ASPEED_SMC,
AspeedSMCState *),
+ DEFINE_PROP_LINK("dram", Aspeed27x0CoprocessorState, dram,
+ TYPE_MEMORY_REGION, MemoryRegion *),
};
static void aspeed_soc_ast27x0tsp_class_init(ObjectClass *klass,
diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c
index 4025ea3205..5d34dbea5e 100644
--- a/hw/misc/aspeed_scu.c
+++ b/hw/misc/aspeed_scu.c
@@ -935,6 +935,7 @@ static void aspeed_2700_scu_realize(DeviceState *dev, Error **errp)
Aspeed2700SCUState *a = ASPEED_2700_SCU(dev);
a->ssp_cpuid = -1;
+ a->tsp_cpuid = -1;
aspeed_scu_realize(dev, errp);
}
--
2.43.0
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH v6 06/11] hw/misc/aspeed_scu: Implement SSP reset and power-on control via SCU registers
2026-07-23 2:23 [PATCH v6 00/11] Add SSP/TSP power control and DRAM remap support for AST2700 Jamin Lin
` (4 preceding siblings ...)
2026-07-23 2:23 ` [PATCH v6 05/11] hw/arm/ast27x0: Add DRAM alias for TSP " Jamin Lin
@ 2026-07-23 2:23 ` Jamin Lin
2026-07-23 2:23 ` [PATCH v6 07/11] hw/misc/aspeed_scu: Implement TSP " Jamin Lin
` (4 subsequent siblings)
10 siblings, 0 replies; 12+ messages in thread
From: Jamin Lin @ 2026-07-23 2:23 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Kane Chen, Andrew Jeffery, Joel Stanley, Pierrick Bouvier,
open list:ASPEED BMCs, open list:All patches CC here
Cc: Jamin Lin, Troy Lee, Philippe Mathieu-Daudé
This patch implements SSP reset and power control logic in the SCU for AST2700.
It introduces support for the following behavior:
1. SSP Reset Trigger (via SCU 0x200):
- SSP reset is triggered by writing 1 to bit 30 (RW1S) of SYS_RESET_CTRL_1.
2. SSP Reset State and Source Hold (via SCU 0x120):
- Upon reset, bit 8 (RST_RB) is set to indicate the SSP is in reset.
- Bit 10 (RST_SRC_RB) is set to indicate the reset was triggered by an external source.
- Bit 1 (RST) is a software-controlled bit used to request holding SSP in reset.
- If an external reset source is present and bit 1 is set, bit 9 (RST_HOLD_RB)
will also be asserted to indicate the SSP is being held in reset.
- If bit 1 is cleared, RST_HOLD_RB will be deasserted accordingly.
3. Hold Release and Power-on:
- If RST_HOLD_RB is clear (0), SSP is powered on immediately after reset is deasserted.
- If RST_HOLD_RB is set (1), the user must write ENABLE (bit 0) to SSP_CTRL_0 to release
the hold and power on SSP explicitly.
- Writing ENABLE (bit 0) is a one-shot operation and will auto-clear after execution.
4. Reset Status Clear (via SCU 0x204):
- The reset status can be cleared by writing 1 to bit 30 (RW1C) of SYS_RST_CLR_1,
which will deassert RST_SRC_RB and potentially trigger power-on if no hold is active.
5. SSP Power Control Logic:
- `handle_ssp_tsp_on()` clears RST_SRC_RB and RST_RB (if not held), and invokes
`arm_set_cpu_on_and_reset(cpuid)` to power on the SSP core (CPUID 4).
- `handle_ssp_tsp_off()` sets RST_RB and RST_SRC_RB; if RST is active, also asserts
RST_HOLD_RB and invokes `arm_set_cpu_off(cpuid)`.
6. Register Initialization and Definitions:
- Adds SCU register definitions for SSP_CTRL_0 (0x120), SYS_RST_CTRL_1 (0x200),
and SYS_RST_CLR_1 (0x204).
- Updates the reset values for these registers during SCU initialization.
The default values are based on EVB (evaluation board) register dump observations.
This patch enables proper modeling of SSP lifecycle management across reset,
hold, and power-on states for the AST2700 SoC.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Tested-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
---
hw/misc/aspeed_scu.c | 109 +++++++++++++++++++++++++++++++++++++++++++
1 file changed, 109 insertions(+)
diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c
index 5d34dbea5e..0fdeaf5648 100644
--- a/hw/misc/aspeed_scu.c
+++ b/hw/misc/aspeed_scu.c
@@ -20,6 +20,7 @@
#include "qemu/guest-random.h"
#include "qemu/module.h"
#include "trace.h"
+#include "target/arm/arm-powerctl.h"
#define TO_REG(offset) ((offset) >> 2)
@@ -143,6 +144,17 @@
#define AST2700_HW_STRAP1_SEC2 TO_REG(0x28)
#define AST2700_HW_STRAP1_SEC3 TO_REG(0x2C)
+/* SSP TSP */
+#define AST2700_SCU_SSP_CTRL_0 TO_REG(0x120)
+#define AST2700_SSP_TSP_ENABLE BIT(0)
+#define AST2700_SSP_TSP_RST BIT(1)
+#define AST2700_SSP_TSP_RST_RB BIT(8)
+#define AST2700_SSP_TSP_RST_HOLD_RB BIT(9)
+#define AST2700_SSP_TSP_RST_SRC_RB BIT(10)
+#define AST2700_SCU_SYS_RST_CTRL_1 TO_REG(0x200)
+#define AST2700_SCU_SYS_RST_CLR_1 TO_REG(0x204)
+#define AST2700_SCU_SYS_RST_SSP BIT(30)
+
#define AST2700_SCU_CLK_SEL_1 TO_REG(0x280)
#define AST2700_SCU_HPLL_PARAM TO_REG(0x300)
#define AST2700_SCU_HPLL_EXT_PARAM TO_REG(0x304)
@@ -841,6 +853,35 @@ static void aspeed_2600_scu_class_init(ObjectClass *klass, const void *data)
asc->ops = &aspeed_ast2600_scu_ops;
}
+static void handle_2700_ssp_tsp_on(struct AspeedSCUState *s, int cpuid,
+ int reg)
+{
+ uint32_t val = s->regs[reg];
+
+ val &= ~AST2700_SSP_TSP_RST_SRC_RB;
+ if (!(val & AST2700_SSP_TSP_RST_HOLD_RB)) {
+ val &= ~AST2700_SSP_TSP_RST_RB;
+ arm_set_cpu_on_and_reset(cpuid);
+ }
+
+ s->regs[reg] = val;
+}
+
+static void handle_2700_ssp_tsp_off(struct AspeedSCUState *s, int cpuid,
+ int reg)
+{
+ uint32_t val = s->regs[reg];
+
+ val |= AST2700_SSP_TSP_RST_RB;
+ val |= AST2700_SSP_TSP_RST_SRC_RB;
+ if (val & AST2700_SSP_TSP_RST) {
+ val |= AST2700_SSP_TSP_RST_HOLD_RB;
+ }
+ arm_set_cpu_off(cpuid);
+
+ s->regs[reg] = val;
+}
+
static uint64_t aspeed_ast2700_scu_read(void *opaque, hwaddr offset,
unsigned size)
{
@@ -861,10 +902,14 @@ static uint64_t aspeed_ast2700_scu_read(void *opaque, hwaddr offset,
static void aspeed_ast2700_scu_write(void *opaque, hwaddr offset,
uint64_t data64, unsigned size)
{
+ Aspeed2700SCUState *a = ASPEED_2700_SCU(opaque);
AspeedSCUState *s = ASPEED_SCU(opaque);
int reg = TO_REG(offset);
/* Truncate here so bitwise operations below behave as expected */
uint32_t data = data64;
+ uint32_t active;
+ uint32_t oldval;
+ int cpuid;
if (reg >= ASPEED_AST2700_SCU_NR_REGS) {
qemu_log_mask(LOG_GUEST_ERROR,
@@ -876,6 +921,63 @@ static void aspeed_ast2700_scu_write(void *opaque, hwaddr offset,
trace_aspeed_ast2700_scu_write(offset, size, data);
switch (reg) {
+ case AST2700_SCU_SSP_CTRL_0:
+ cpuid = a->ssp_cpuid;
+ if (cpuid < 0) {
+ return;
+ }
+ oldval = s->regs[reg];
+ data &= 0xff;
+ active = oldval ^ data;
+
+ /*
+ * If reset bit is being released (1 -> 0) and no other reset source
+ * is active, clear HOLD_RB and power on the corresponding CPU.
+ */
+ if ((active & AST2700_SSP_TSP_RST) && !(data & AST2700_SSP_TSP_RST)) {
+ s->regs[reg] &= ~AST2700_SSP_TSP_RST_HOLD_RB;
+ if ((oldval & AST2700_SSP_TSP_RST_RB) &&
+ !(oldval & AST2700_SSP_TSP_RST_SRC_RB)) {
+ handle_2700_ssp_tsp_on(s, cpuid, reg);
+ }
+ }
+
+ /*
+ * If ENABLE bit is newly set and reset state is ready,
+ * clear HOLD_RB and power on the corresponding CPU.
+ */
+ if ((active & AST2700_SSP_TSP_ENABLE) &&
+ (oldval & AST2700_SSP_TSP_RST_RB) &&
+ (oldval & AST2700_SSP_TSP_RST_HOLD_RB) &&
+ !(oldval & AST2700_SSP_TSP_RST_SRC_RB)) {
+ s->regs[reg] &= ~AST2700_SSP_TSP_RST_HOLD_RB;
+ handle_2700_ssp_tsp_on(s, cpuid, reg);
+ }
+
+ /* Auto-clear the ENABLE bit (one-shot behavior) */
+ data &= ~AST2700_SSP_TSP_ENABLE;
+ s->regs[reg] = (s->regs[reg] & ~0xff) | (data & 0xff);
+ return;
+ case AST2700_SCU_SYS_RST_CTRL_1:
+ if (a->ssp_cpuid < 0) {
+ return;
+ }
+ if (data & AST2700_SCU_SYS_RST_SSP) {
+ handle_2700_ssp_tsp_off(s, a->ssp_cpuid, AST2700_SCU_SSP_CTRL_0);
+ }
+ s->regs[reg] |= data;
+ return;
+ case AST2700_SCU_SYS_RST_CLR_1:
+ if (a->ssp_cpuid < 0) {
+ return;
+ }
+ oldval = s->regs[AST2700_SCU_SYS_RST_CTRL_1];
+ active = data & oldval;
+ if (active & AST2700_SCU_SYS_RST_SSP) {
+ handle_2700_ssp_tsp_on(s, a->ssp_cpuid, AST2700_SCU_SSP_CTRL_0);
+ }
+ s->regs[AST2700_SCU_SYS_RST_CTRL_1] &= ~active;
+ return;
default:
qemu_log_mask(LOG_GUEST_ERROR,
"%s: Unhandled write at offset 0x%" HWADDR_PRIx "\n",
@@ -903,6 +1005,8 @@ static const uint32_t ast2700_a0_resets[ASPEED_AST2700_SCU_NR_REGS] = {
[AST2700_HW_STRAP1_SEC1] = 0x000000FF,
[AST2700_HW_STRAP1_SEC2] = 0x00000000,
[AST2700_HW_STRAP1_SEC3] = 0x1000408F,
+ [AST2700_SCU_SSP_CTRL_0] = 0x000007FE,
+ [AST2700_SCU_SYS_RST_CTRL_1] = 0xFFC37FDC,
[AST2700_SCU_HPLL_PARAM] = 0x0000009f,
[AST2700_SCU_HPLL_EXT_PARAM] = 0x8000004f,
[AST2700_SCU_DPLL_PARAM] = 0x0080009f,
@@ -922,12 +1026,17 @@ static const uint32_t ast2700_a0_resets[ASPEED_AST2700_SCU_NR_REGS] = {
static void aspeed_ast2700_scu_reset_hold(Object *obj, ResetType type)
{
+ Aspeed2700SCUState *a = ASPEED_2700_SCU(obj);
AspeedSCUState *s = ASPEED_SCU(obj);
AspeedSCUClass *asc = ASPEED_SCU_GET_CLASS(obj);
memcpy(s->regs, asc->resets, asc->nr_regs * 4);
s->regs[AST2700_SILICON_REV] = s->silicon_rev;
s->regs[AST2700_HW_STRAP1] = s->hw_strap1;
+
+ if (a->ssp_cpuid > 0) {
+ arm_set_cpu_off(a->ssp_cpuid);
+ }
}
static void aspeed_2700_scu_realize(DeviceState *dev, Error **errp)
--
2.43.0
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH v6 07/11] hw/misc/aspeed_scu: Implement TSP reset and power-on control via SCU registers
2026-07-23 2:23 [PATCH v6 00/11] Add SSP/TSP power control and DRAM remap support for AST2700 Jamin Lin
` (5 preceding siblings ...)
2026-07-23 2:23 ` [PATCH v6 06/11] hw/misc/aspeed_scu: Implement SSP reset and power-on control via SCU registers Jamin Lin
@ 2026-07-23 2:23 ` Jamin Lin
2026-07-23 2:23 ` [PATCH v6 08/11] hw/misc/aspeed_scu: Add SCU support for SSP SDRAM remap Jamin Lin
` (3 subsequent siblings)
10 siblings, 0 replies; 12+ messages in thread
From: Jamin Lin @ 2026-07-23 2:23 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Kane Chen, Andrew Jeffery, Joel Stanley, Pierrick Bouvier,
open list:ASPEED BMCs, open list:All patches CC here
Cc: Jamin Lin, Troy Lee, Philippe Mathieu-Daudé
This patch implements TSP reset and power control logic in the SCU module
for AST2700. It introduces support for the following behavior:
1. TSP Reset Trigger (via SCU 0x220):
- TSP reset is triggered by writing 1 to bit 9 (RW1S) of SYS_RESET_CTRL_2.
2. TSP Reset State and Source Hold (via SCU 0x160):
- Upon reset, bit 8 (RST_RB) is set to indicate the TSP is in reset.
- Bit 10 (RST_SRC_RB) is set to indicate the reset was triggered by an external source.
- Bit 1 (RST) is a software-controlled bit used to request holding TSP in reset.
- If an external reset source is present and bit 1 is set, bit 9 (RST_HOLD_RB)
will also be asserted to indicate the TSP is being held in reset.
- If bit 1 is cleared, RST_HOLD_RB will be deasserted accordingly.
3. Hold Release and Power-on:
- If RST_HOLD_RB is clear (0), TSP is powered on immediately after reset is deasserted.
- If RST_HOLD_RB is set (1), the user must write ENABLE (bit 0) to TSP_CTRL_0 to release
the hold and power on TSP explicitly.
- Writing ENABLE (bit 0) is a one-shot operation and will auto-clear after execution.
4. Reset Status Clear (via SCU 0x224):
- The reset status can be cleared by writing 1 to bit 9 (RW1C) of SYS_RST_CLR_2,
which will deassert RST_SRC_RB and potentially trigger power-on if no hold is active.
5. TSP Power Control Logic:
- handle_ssp_tsp_on() clears RST_SRC_RB and RST_RB (if not held), and invokes
arm_set_cpu_on_and_reset(cpuid) to power on the TSP core (CPUID 5).
- handle_ssp_tsp_off() sets RST_RB and RST_SRC_RB; if RST is active, also asserts
RST_HOLD_RB and invokes arm_set_cpu_off(cpuid).
The default values are based on EVB (evaluation board) register dump observations.
TSP reset control shares the same helper functions and register bit layout as SSP,
with logic selected by cpuid and distinct external reset sources.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Tested-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
---
hw/misc/aspeed_scu.c | 37 ++++++++++++++++++++++++++++++++++++-
1 file changed, 36 insertions(+), 1 deletion(-)
diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c
index 0fdeaf5648..fdb1cf59b4 100644
--- a/hw/misc/aspeed_scu.c
+++ b/hw/misc/aspeed_scu.c
@@ -146,6 +146,7 @@
/* SSP TSP */
#define AST2700_SCU_SSP_CTRL_0 TO_REG(0x120)
+#define AST2700_SCU_TSP_CTRL_0 TO_REG(0x160)
#define AST2700_SSP_TSP_ENABLE BIT(0)
#define AST2700_SSP_TSP_RST BIT(1)
#define AST2700_SSP_TSP_RST_RB BIT(8)
@@ -154,6 +155,9 @@
#define AST2700_SCU_SYS_RST_CTRL_1 TO_REG(0x200)
#define AST2700_SCU_SYS_RST_CLR_1 TO_REG(0x204)
#define AST2700_SCU_SYS_RST_SSP BIT(30)
+#define AST2700_SCU_SYS_RST_CTRL_2 TO_REG(0x220)
+#define AST2700_SCU_SYS_RST_CLR_2 TO_REG(0x224)
+#define AST2700_SCU_SYS_RST_TSP BIT(9)
#define AST2700_SCU_CLK_SEL_1 TO_REG(0x280)
#define AST2700_SCU_HPLL_PARAM TO_REG(0x300)
@@ -922,7 +926,10 @@ static void aspeed_ast2700_scu_write(void *opaque, hwaddr offset,
switch (reg) {
case AST2700_SCU_SSP_CTRL_0:
- cpuid = a->ssp_cpuid;
+ case AST2700_SCU_TSP_CTRL_0:
+ cpuid = (reg == AST2700_SCU_SSP_CTRL_0) ?
+ a->ssp_cpuid : a->tsp_cpuid;
+
if (cpuid < 0) {
return;
}
@@ -978,6 +985,28 @@ static void aspeed_ast2700_scu_write(void *opaque, hwaddr offset,
}
s->regs[AST2700_SCU_SYS_RST_CTRL_1] &= ~active;
return;
+ case AST2700_SCU_SYS_RST_CTRL_2:
+ if (a->tsp_cpuid < 0) {
+ return;
+ }
+ data &= 0x00001fff;
+ if (data & AST2700_SCU_SYS_RST_TSP) {
+ handle_2700_ssp_tsp_off(s, a->tsp_cpuid, AST2700_SCU_TSP_CTRL_0);
+ }
+ s->regs[reg] |= data;
+ return;
+ case AST2700_SCU_SYS_RST_CLR_2:
+ if (a->tsp_cpuid < 0) {
+ return;
+ }
+ data &= 0x00001fff;
+ oldval = s->regs[AST2700_SCU_SYS_RST_CTRL_2];
+ active = data & oldval;
+ if (active & AST2700_SCU_SYS_RST_TSP) {
+ handle_2700_ssp_tsp_on(s, a->tsp_cpuid, AST2700_SCU_TSP_CTRL_0);
+ }
+ s->regs[AST2700_SCU_SYS_RST_CTRL_2] &= ~active;
+ return;
default:
qemu_log_mask(LOG_GUEST_ERROR,
"%s: Unhandled write at offset 0x%" HWADDR_PRIx "\n",
@@ -1006,7 +1035,9 @@ static const uint32_t ast2700_a0_resets[ASPEED_AST2700_SCU_NR_REGS] = {
[AST2700_HW_STRAP1_SEC2] = 0x00000000,
[AST2700_HW_STRAP1_SEC3] = 0x1000408F,
[AST2700_SCU_SSP_CTRL_0] = 0x000007FE,
+ [AST2700_SCU_TSP_CTRL_0] = 0x000007FE,
[AST2700_SCU_SYS_RST_CTRL_1] = 0xFFC37FDC,
+ [AST2700_SCU_SYS_RST_CTRL_2] = 0x00001FFF,
[AST2700_SCU_HPLL_PARAM] = 0x0000009f,
[AST2700_SCU_HPLL_EXT_PARAM] = 0x8000004f,
[AST2700_SCU_DPLL_PARAM] = 0x0080009f,
@@ -1037,6 +1068,10 @@ static void aspeed_ast2700_scu_reset_hold(Object *obj, ResetType type)
if (a->ssp_cpuid > 0) {
arm_set_cpu_off(a->ssp_cpuid);
}
+
+ if (a->tsp_cpuid > 0) {
+ arm_set_cpu_off(a->tsp_cpuid);
+ }
}
static void aspeed_2700_scu_realize(DeviceState *dev, Error **errp)
--
2.43.0
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH v6 08/11] hw/misc/aspeed_scu: Add SCU support for SSP SDRAM remap
2026-07-23 2:23 [PATCH v6 00/11] Add SSP/TSP power control and DRAM remap support for AST2700 Jamin Lin
` (6 preceding siblings ...)
2026-07-23 2:23 ` [PATCH v6 07/11] hw/misc/aspeed_scu: Implement TSP " Jamin Lin
@ 2026-07-23 2:23 ` Jamin Lin
2026-07-23 2:23 ` [PATCH v6 09/11] hw/misc/aspeed_scu: Add SCU support for TSP " Jamin Lin
` (2 subsequent siblings)
10 siblings, 0 replies; 12+ messages in thread
From: Jamin Lin @ 2026-07-23 2:23 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Kane Chen, Andrew Jeffery, Joel Stanley, Pierrick Bouvier,
open list:ASPEED BMCs, open list:All patches CC here
Cc: Jamin Lin, Troy Lee, Philippe Mathieu-Daudé
This commit adds SCU register support for SSP SDRAM remap control and runtime
activation. It introduces logic for the PSP to dynamically configure the mapping
of its own DRAM windows into SSP-visible SDRAM space, enabling shared memory
communication via memory region aliases.
- coprocessor_sdram_remap[0]: maps PSP DRAM offset 0x400000000 (size: 0x1A77E000) to SSP SDRAM
offset 0x5880000
- coprocessor_sdram_remap[1]: maps PSP DRAM offset 0x42C000000 (size: 0x05880000) to SSP SDRAM
offset 0x0
The SCU registers AST2700_SCU_SSP_CTRL_1/2 and
AST2700_SCU_SSP_REMAP_ADDR_{1,2} / REMAP_SIZE_{1,2} allow runtime reconfiguration
of alias offset, base, and size.
|------------------------------------------| |----------------------------|
| PSP DRAM | | SSP SDRAM |
|------------------------------------------| |----------------------------|
| 0x4_0000_0000 (SCU_124 << 4) | --> | 0x0000_0000 |
| remap1 base |---| | | - SCU_150: target addr |
| size: 0x1A77E000 (SCU_14C) | | | | remap2 |
|------------------------------------------| | | |----------------------------|
| | | | | |
| 0x4_2C00_0000 (SCU_128 << 4) |-----| | 0x5880000 |
| remap2 base | | | - SCU_148: target addr |
| size: 0x05880000 (SCU_154) | |---> | remap1 |
|------------------------------------------| |----------------------------|
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Tested-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
---
hw/misc/aspeed_scu.c | 62 ++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 62 insertions(+)
diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c
index fdb1cf59b4..407c1743fc 100644
--- a/hw/misc/aspeed_scu.c
+++ b/hw/misc/aspeed_scu.c
@@ -146,6 +146,14 @@
/* SSP TSP */
#define AST2700_SCU_SSP_CTRL_0 TO_REG(0x120)
+#define AST2700_SCU_SSP_CTRL_1 TO_REG(0x124)
+#define AST2700_SCU_SSP_CTRL_2 TO_REG(0x128)
+#define AST2700_SCU_SSP_REMAP_ADDR_0 TO_REG(0x140)
+#define AST2700_SCU_SSP_REMAP_SIZE_0 TO_REG(0x144)
+#define AST2700_SCU_SSP_REMAP_ADDR_1 TO_REG(0x148)
+#define AST2700_SCU_SSP_REMAP_SIZE_1 TO_REG(0x14C)
+#define AST2700_SCU_SSP_REMAP_ADDR_2 TO_REG(0x150)
+#define AST2700_SCU_SSP_REMAP_SIZE_2 TO_REG(0x154)
#define AST2700_SCU_TSP_CTRL_0 TO_REG(0x160)
#define AST2700_SSP_TSP_ENABLE BIT(0)
#define AST2700_SSP_TSP_RST BIT(1)
@@ -908,6 +916,7 @@ static void aspeed_ast2700_scu_write(void *opaque, hwaddr offset,
{
Aspeed2700SCUState *a = ASPEED_2700_SCU(opaque);
AspeedSCUState *s = ASPEED_SCU(opaque);
+ MemoryRegion *mr = NULL;
int reg = TO_REG(offset);
/* Truncate here so bitwise operations below behave as expected */
uint32_t data = data64;
@@ -965,6 +974,43 @@ static void aspeed_ast2700_scu_write(void *opaque, hwaddr offset,
data &= ~AST2700_SSP_TSP_ENABLE;
s->regs[reg] = (s->regs[reg] & ~0xff) | (data & 0xff);
return;
+ case AST2700_SCU_SSP_CTRL_1:
+ case AST2700_SCU_SSP_CTRL_2:
+ mr = (reg == AST2700_SCU_SSP_CTRL_1) ?
+ a->ssp_remap[0] : a->ssp_remap[1];
+ if (a->ssp_cpuid < 0 || mr == NULL) {
+ return;
+ }
+ data &= 0x7fffffff;
+ memory_region_transaction_begin();
+ memory_region_set_alias_offset(mr,
+ ((uint64_t) data << 4) & 0x3ffffffff);
+ memory_region_transaction_commit();
+ break;
+ case AST2700_SCU_SSP_REMAP_ADDR_1:
+ case AST2700_SCU_SSP_REMAP_ADDR_2:
+ mr = (reg == AST2700_SCU_SSP_REMAP_ADDR_1) ?
+ a->ssp_remap[0] : a->ssp_remap[1];
+ if (a->ssp_cpuid < 0 || mr == NULL) {
+ return;
+ }
+ data &= 0x3fffffff;
+ memory_region_transaction_begin();
+ memory_region_set_address(mr, data);
+ memory_region_transaction_commit();
+ break;
+ case AST2700_SCU_SSP_REMAP_SIZE_1:
+ case AST2700_SCU_SSP_REMAP_SIZE_2:
+ mr = (reg == AST2700_SCU_SSP_REMAP_SIZE_1) ?
+ a->ssp_remap[0] : a->ssp_remap[1];
+ if (a->ssp_cpuid < 0 || mr == NULL) {
+ return;
+ }
+ data &= 0x3fffffff;
+ memory_region_transaction_begin();
+ memory_region_set_size(mr, data);
+ memory_region_transaction_commit();
+ break;
case AST2700_SCU_SYS_RST_CTRL_1:
if (a->ssp_cpuid < 0) {
return;
@@ -1035,6 +1081,14 @@ static const uint32_t ast2700_a0_resets[ASPEED_AST2700_SCU_NR_REGS] = {
[AST2700_HW_STRAP1_SEC2] = 0x00000000,
[AST2700_HW_STRAP1_SEC3] = 0x1000408F,
[AST2700_SCU_SSP_CTRL_0] = 0x000007FE,
+ [AST2700_SCU_SSP_CTRL_1] = 0x40000000,
+ [AST2700_SCU_SSP_CTRL_2] = 0x42C00000,
+ [AST2700_SCU_SSP_REMAP_ADDR_0] = 0x1FFFE000,
+ [AST2700_SCU_SSP_REMAP_SIZE_0] = 0x00002000,
+ [AST2700_SCU_SSP_REMAP_ADDR_1] = 0x05880000,
+ [AST2700_SCU_SSP_REMAP_SIZE_1] = 0x1A77E000,
+ [AST2700_SCU_SSP_REMAP_ADDR_2] = 0x00000000,
+ [AST2700_SCU_SSP_REMAP_SIZE_2] = 0x05880000,
[AST2700_SCU_TSP_CTRL_0] = 0x000007FE,
[AST2700_SCU_SYS_RST_CTRL_1] = 0xFFC37FDC,
[AST2700_SCU_SYS_RST_CTRL_2] = 0x00001FFF,
@@ -1067,6 +1121,14 @@ static void aspeed_ast2700_scu_reset_hold(Object *obj, ResetType type)
if (a->ssp_cpuid > 0) {
arm_set_cpu_off(a->ssp_cpuid);
+ memory_region_transaction_begin();
+ memory_region_set_address(a->ssp_remap[0], 0x5880000);
+ memory_region_set_alias_offset(a->ssp_remap[0], 0);
+ memory_region_set_size(a->ssp_remap[0], 0x1a77e000);
+ memory_region_set_address(a->ssp_remap[1], 0);
+ memory_region_set_alias_offset(a->ssp_remap[1], 0x2c000000);
+ memory_region_set_size(a->ssp_remap[1], 0x5880000);
+ memory_region_transaction_commit();
}
if (a->tsp_cpuid > 0) {
--
2.43.0
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH v6 09/11] hw/misc/aspeed_scu: Add SCU support for TSP SDRAM remap
2026-07-23 2:23 [PATCH v6 00/11] Add SSP/TSP power control and DRAM remap support for AST2700 Jamin Lin
` (7 preceding siblings ...)
2026-07-23 2:23 ` [PATCH v6 08/11] hw/misc/aspeed_scu: Add SCU support for SSP SDRAM remap Jamin Lin
@ 2026-07-23 2:23 ` Jamin Lin
2026-07-23 2:23 ` [PATCH v6 10/11] tests/functional/aarch64/test_aspeed_ast2700fc: Boot SSP/TSP via PSP and load binaries from DRAM Jamin Lin
2026-07-23 2:23 ` [PATCH v6 11/11] docs: Add support vbootrom and update Manual boot for ast2700fc Jamin Lin
10 siblings, 0 replies; 12+ messages in thread
From: Jamin Lin @ 2026-07-23 2:23 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Kane Chen, Andrew Jeffery, Joel Stanley, Pierrick Bouvier,
open list:ASPEED BMCs, open list:All patches CC here
Cc: Jamin Lin, Troy Lee, Philippe Mathieu-Daudé
This commit adds SCU register support for TSP SDRAM remap control and runtime
activation. Unlike SSP, the TSP does not support configurable target address remapping
through SCU registers. It only supports setting the PSP DRAM base and size, which
are then aliased into the TSP-visible SDRAM window.
coprocessor_sdram_remap[2]: maps PSP DRAM offset 0x42E000000 (size: 32MB) to TSP SDRAM
offset 0x0
The SCU registers AST2700_SCU_TSP_CTRL_1 and
AST2700_SCU_TSP_REMAP_SIZE_2 allow runtime reconfiguration of the DRAM base (alias offset)
and mapping size.
|------------------------------------------| |----------------------------|
| PSP DRAM | | TSP SDRAM |
|------------------------------------------| |----------------------------|
| 0x42E0_0000_0 (SCU_168 << 4) | | 0x0000_0000 |
| remap base |------> | - fixed target addr |
| size: 32MB (SCU_194) | | |
|------------------------------------------| |----------------------------|
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Tested-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
---
hw/misc/aspeed_scu.c | 30 ++++++++++++++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c
index 407c1743fc..74b7674b06 100644
--- a/hw/misc/aspeed_scu.c
+++ b/hw/misc/aspeed_scu.c
@@ -20,6 +20,7 @@
#include "qemu/guest-random.h"
#include "qemu/module.h"
#include "trace.h"
+#include "qemu/units.h"
#include "target/arm/arm-powerctl.h"
#define TO_REG(offset) ((offset) >> 2)
@@ -160,6 +161,8 @@
#define AST2700_SSP_TSP_RST_RB BIT(8)
#define AST2700_SSP_TSP_RST_HOLD_RB BIT(9)
#define AST2700_SSP_TSP_RST_SRC_RB BIT(10)
+#define AST2700_SCU_TSP_CTRL_1 TO_REG(0x168)
+#define AST2700_SCU_TSP_REMAP_SIZE_2 TO_REG(0x194)
#define AST2700_SCU_SYS_RST_CTRL_1 TO_REG(0x200)
#define AST2700_SCU_SYS_RST_CLR_1 TO_REG(0x204)
#define AST2700_SCU_SYS_RST_SSP BIT(30)
@@ -1011,6 +1014,27 @@ static void aspeed_ast2700_scu_write(void *opaque, hwaddr offset,
memory_region_set_size(mr, data);
memory_region_transaction_commit();
break;
+ case AST2700_SCU_TSP_CTRL_1:
+ mr = a->tsp_remap;
+ if (a->tsp_cpuid < 0 || mr == NULL) {
+ return;
+ }
+ data &= 0x7fffffff;
+ memory_region_transaction_begin();
+ memory_region_set_alias_offset(mr,
+ ((uint64_t) data << 4) & 0x3ffffffff);
+ memory_region_transaction_commit();
+ break;
+ case AST2700_SCU_TSP_REMAP_SIZE_2:
+ mr = a->tsp_remap;
+ if (a->tsp_cpuid < 0 || mr == NULL) {
+ return;
+ }
+ data &= 0x3fffffff;
+ memory_region_transaction_begin();
+ memory_region_set_size(mr, data);
+ memory_region_transaction_commit();
+ break;
case AST2700_SCU_SYS_RST_CTRL_1:
if (a->ssp_cpuid < 0) {
return;
@@ -1090,6 +1114,8 @@ static const uint32_t ast2700_a0_resets[ASPEED_AST2700_SCU_NR_REGS] = {
[AST2700_SCU_SSP_REMAP_ADDR_2] = 0x00000000,
[AST2700_SCU_SSP_REMAP_SIZE_2] = 0x05880000,
[AST2700_SCU_TSP_CTRL_0] = 0x000007FE,
+ [AST2700_SCU_TSP_CTRL_1] = 0x42E00000,
+ [AST2700_SCU_TSP_REMAP_SIZE_2] = 0x02000000,
[AST2700_SCU_SYS_RST_CTRL_1] = 0xFFC37FDC,
[AST2700_SCU_SYS_RST_CTRL_2] = 0x00001FFF,
[AST2700_SCU_HPLL_PARAM] = 0x0000009f,
@@ -1133,6 +1159,10 @@ static void aspeed_ast2700_scu_reset_hold(Object *obj, ResetType type)
if (a->tsp_cpuid > 0) {
arm_set_cpu_off(a->tsp_cpuid);
+ memory_region_transaction_begin();
+ memory_region_set_alias_offset(a->tsp_remap, 0x2e000000);
+ memory_region_set_size(a->tsp_remap, 32 * MiB);
+ memory_region_transaction_commit();
}
}
--
2.43.0
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH v6 10/11] tests/functional/aarch64/test_aspeed_ast2700fc: Boot SSP/TSP via PSP and load binaries from DRAM
2026-07-23 2:23 [PATCH v6 00/11] Add SSP/TSP power control and DRAM remap support for AST2700 Jamin Lin
` (8 preceding siblings ...)
2026-07-23 2:23 ` [PATCH v6 09/11] hw/misc/aspeed_scu: Add SCU support for TSP " Jamin Lin
@ 2026-07-23 2:23 ` Jamin Lin
2026-07-23 2:23 ` [PATCH v6 11/11] docs: Add support vbootrom and update Manual boot for ast2700fc Jamin Lin
10 siblings, 0 replies; 12+ messages in thread
From: Jamin Lin @ 2026-07-23 2:23 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Kane Chen, Andrew Jeffery, Joel Stanley, Pierrick Bouvier,
open list:ASPEED BMCs, open list:All patches CC here
Cc: Jamin Lin, Troy Lee, Philippe Mathieu-Daudé
SSP and TSP now boot in a powered-off state by default. Enabling them requires
the PSP (Cortex-A35) to explicitly set SCU control registers at runtime. This
behavior aligns with real hardware.
Update the AST2700 FC functional test to reflect this behavior by enabling
SSP and TSP from the U-Boot shell before booting OpenBMC. The test now
programs the required SCU registers, saves the environment, and boots the
system so that SSP and TSP are powered on when the PSP starts.
Additionally, switch SSP and TSP loading from ELF-based CPU loaders to
binary images loaded into PSP DRAM at fixed addresses, and remove the use
of snapshot mode.
Changes include:
- Add enable_ast2700_ssp_tsp() to configure SCU registers via U-Boot
- Remove snapshot option from QEMU command line
- Load SSP binary at DRAM address 0x42C000000
- Load TSP binary at DRAM address 0x42E000000
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Tested-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
---
.../aarch64/test_aspeed_ast2700fc.py | 29 ++++++++++---------
1 file changed, 16 insertions(+), 13 deletions(-)
diff --git a/tests/functional/aarch64/test_aspeed_ast2700fc.py b/tests/functional/aarch64/test_aspeed_ast2700fc.py
index df889134ed..c0204ceb6c 100755
--- a/tests/functional/aarch64/test_aspeed_ast2700fc.py
+++ b/tests/functional/aarch64/test_aspeed_ast2700fc.py
@@ -23,7 +23,7 @@ def do_test_aarch64_aspeed_sdk_start(self, image):
self.vm.add_args('-device', 'e1000e,netdev=net1,bus=pcie.2')
self.vm.add_args('-netdev', 'user,id=net1')
self.vm.add_args('-drive', 'file=' + image + ',if=mtd,format=raw',
- '-net', 'nic', '-net', 'user', '-snapshot')
+ '-net', 'nic', '-net', 'user')
self.vm.launch()
@@ -31,6 +31,12 @@ def disable_kernel_crypto_selftest(self):
exec_command_and_wait_for_pattern(self,
'setenv bootargs "${bootargs} cryptomgr.notests=1"', '=>')
+ def enable_ast2700_ssp_tsp(self):
+ exec_command_and_wait_for_pattern(self,
+ 'setenv bootcmd "mw 12c02204 40000000; mw 12c02120 1; '
+ 'mw 12c02224 00000200; mw 12c02160 1; run bootspi"', '=>')
+ exec_command_and_wait_for_pattern(self, 'saveenv', 'OK')
+
def enable_ast2700_pcie2(self):
exec_command_and_wait_for_pattern(self,
'cp 100420000 403000000 900000', '=>')
@@ -48,6 +54,7 @@ def verify_openbmc_boot_and_login(self, name):
wait_for_console_pattern(self, 'Hit any key to stop autoboot')
exec_command_and_wait_for_pattern(self, '\012', '=>')
self.disable_kernel_crypto_selftest()
+ self.enable_ast2700_ssp_tsp()
self.enable_ast2700_pcie2()
wait_for_console_pattern(self, 'Starting kernel ...')
@@ -55,16 +62,6 @@ def verify_openbmc_boot_and_login(self, name):
exec_command_and_wait_for_pattern(self, 'root', 'Password:')
exec_command_and_wait_for_pattern(self, '0penBmc', f'root@{name}:~#')
- def load_ast2700fc_coprocessor(self, name):
- load_elf_list = {
- 'ssp': self.scratch_file(name, 'zephyr-aspeed-ssp.elf'),
- 'tsp': self.scratch_file(name, 'zephyr-aspeed-tsp.elf')
- }
-
- for cpu_num, key in enumerate(load_elf_list, start=4):
- file = load_elf_list[key]
- self.vm.add_args('-device',
- f'loader,file={file},cpu-num={cpu_num}')
ASSET_SDK_V1101_AST2700 = Asset(
'https://github.com/AspeedTech-BMC/openbmc/releases/download/v11.01/ast2700-default-image.tar.gz',
@@ -123,6 +120,14 @@ def start_ast2700fc_test(self, name):
'addr': '0x400000000',
'file': self.scratch_file(name, 'u-boot.bin')
},
+ {
+ 'addr': '0x42C000000',
+ 'file': self.scratch_file(name, 'zephyr-aspeed-ssp.bin')
+ },
+ {
+ 'addr': '0x42E000000',
+ 'file': self.scratch_file(name, 'zephyr-aspeed-tsp.bin')
+ },
{
'addr': '0x430000000',
'file': self.scratch_file(name, 'bl31.bin')
@@ -143,13 +148,11 @@ def start_ast2700fc_test(self, name):
self.vm.add_args('-device',
f'loader,addr=0x430000000,cpu-num={i}')
- self.load_ast2700fc_coprocessor(name)
self.do_test_aarch64_aspeed_sdk_start(
self.scratch_file(name, 'image-bmc'))
def start_ast2700fc_test_vbootrom(self, name):
self.vm.add_args('-bios', 'ast27x0_bootrom.bin')
- self.load_ast2700fc_coprocessor(name)
self.do_test_aarch64_aspeed_sdk_start(
self.scratch_file(name, 'image-bmc'))
--
2.43.0
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH v6 11/11] docs: Add support vbootrom and update Manual boot for ast2700fc
2026-07-23 2:23 [PATCH v6 00/11] Add SSP/TSP power control and DRAM remap support for AST2700 Jamin Lin
` (9 preceding siblings ...)
2026-07-23 2:23 ` [PATCH v6 10/11] tests/functional/aarch64/test_aspeed_ast2700fc: Boot SSP/TSP via PSP and load binaries from DRAM Jamin Lin
@ 2026-07-23 2:23 ` Jamin Lin
10 siblings, 0 replies; 12+ messages in thread
From: Jamin Lin @ 2026-07-23 2:23 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Kane Chen, Andrew Jeffery, Joel Stanley, Pierrick Bouvier,
open list:ASPEED BMCs, open list:All patches CC here
Cc: Jamin Lin, Troy Lee, Philippe Mathieu-Daudé
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Tested-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
---
docs/system/arm/aspeed.rst | 42 +++++++++++++++++++++++++++++++-------
1 file changed, 35 insertions(+), 7 deletions(-)
diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst
index 2d51ceeb84..b6dd757f6e 100644
--- a/docs/system/arm/aspeed.rst
+++ b/docs/system/arm/aspeed.rst
@@ -386,18 +386,25 @@ Booting the ast2700fc machine
AST2700 features four Cortex-A35 primary processors and two Cortex-M4 coprocessors.
**ast2700-evb** machine focuses on emulating the four Cortex-A35 primary processors,
**ast2700fc** machine extends **ast2700-evb** by adding support for the two Cortex-M4 coprocessors.
+There are two methods to boot the ast2700fc machine.
+
+Manual boot using ``-device loader``:
+
+In this approach, users manually load firmware and assign entry points via QEMU loader devices.
+By default, the PSP begins execution at address ``0x430000000``, the load address of the bl31
+firmware. The SSP and TSP start in the powered-off state and must be explicitly enabled by the
+PSP through writes to SCU registers.
Steps to boot the AST2700fc machine:
-1. Ensure you have the following AST2700A1 binaries available in a directory
+1. Ensure you have the following AST2700 binaries available in a directory
- * u-boot-nodtb.bin
- * u-boot.dtb
+ * u-boot.bin
* bl31.bin
* optee/tee-raw.bin
* image-bmc
- * zephyr-aspeed-ssp.elf (for SSP firmware, CPU 5)
- * zephyr-aspeed-tsp.elf (for TSP firmware, CPU 6)
+ * zephyr-aspeed-ssp.bin (for SSP firmware, CPU 5)
+ * zephyr-aspeed-tsp.bin (for TSP firmware, CPU 6)
2. Execute the following command to start ``ast2700fc`` machine:
@@ -407,6 +414,8 @@ Steps to boot the AST2700fc machine:
$ qemu-system-aarch64 -M ast2700fc \
-device loader,force-raw=on,addr=0x400000000,file=${IMGDIR}/u-boot.bin \
+ -device loader,force-raw=on,addr=0x42C000000,file=${IMGDIR}/zephyr-aspeed-ssp.bin \
+ -device loader,force-raw=on,addr=0x42E000000,file=${IMGDIR}/zephyr-aspeed-tsp.bin \
-device loader,force-raw=on,addr=0x430000000,file=${IMGDIR}/bl31.bin \
-device loader,force-raw=on,addr=0x430080000,file=${IMGDIR}/optee/tee-raw.bin \
-device loader,cpu-num=0,addr=0x430000000 \
@@ -414,12 +423,31 @@ Steps to boot the AST2700fc machine:
-device loader,cpu-num=2,addr=0x430000000 \
-device loader,cpu-num=3,addr=0x430000000 \
-drive file=${IMGDIR}/image-bmc,if=mtd,format=raw \
- -device loader,file=${IMGDIR}/zephyr-aspeed-ssp.elf,cpu-num=4 \
- -device loader,file=${IMGDIR}/zephyr-aspeed-tsp.elf,cpu-num=5 \
-serial pty -serial pty -serial pty \
-snapshot \
-S -nographic
+Boot using a virtual boot ROM (-bios):
+
+In this method, the virtual boot ROM (vbootrom) handles the full initialization sequence.
+It starts the PSP, which then enables the SSP and TSP by programming the appropriate SCU
+registers, following the hardware behavior.
+
+Execute the following command to start ``ast2700fc`` machine:
+
+.. code-block:: bash
+
+ IMGDIR=ast2700-default
+
+ $ qemu-system-aarch64 -M ast2700fc \
+ -bios ast27x0_bootrom.bin \
+ -drive file=${IMGDIR}/image-bmc,if=mtd,format=raw \
+ -serial pty -serial pty -serial pty \
+ -snapshot \
+ -S -nographic
+
+Serial Console Redirection:
+
After launching QEMU, serial devices will be automatically redirected.
Example output:
--
2.43.0
^ permalink raw reply related [flat|nested] 12+ messages in thread