[PATCH v7 00/34] pinctrl: airoha: split on shared and SoC drivers, add more SoCs

[PATCH v7 00/34] pinctrl: airoha: split on shared and SoC drivers, add more SoCs

[Mikhail Kshevetskiy]

This patchset
 * fixes more airoha pinctrl issues
 * split combined driver on common code and several SoC specific drivers
 * improves an7583 pinctrl support
 * adds support of en7523 SoC
 * adds support of an7563 SoC

The driver split changes are based on Matheus Sampaio Queiroga work.

Changes v2:
 * more issues of airoha pinctrl driver was fixed
 * SoC specific register addresses, bitfields, macroses were
   removed from common header and placed to SoC specific file
 * fixed address of LAN LED mappings registers for en7523 SoC
 * improves support of an7583 pinctrl

Changes v3:
 * improve searching of chip scu regmap necessary for drivers
   operations

Changes v4:
 * an7583: add support of OLT pin function
 * an7581: do a proper fix of pcie_reset pins mux/conf.

Changes v5:
 * improve description of an7583 i2c pinmux fix
 * rename an7583 registers to match its an7583 names
 * add support of an7563 SoC

Changes v6:
 * fix some of the issues found by
   https://sashiko.dev/#/patchset/20260622113046.3619139-1-mikhail.kshevetskiy%40iopsys.eu
 * update device tree binding
 * add bindings for en7523 and an7563

Changes v7:
 * a lot of IRQ support fixes, now there is chances that IRQ code is
   really working
 * device tree bindings moved to the separate patches
 * fix some of the issues found by
   https://sashiko.dev/#/patchset/20260628143733.273651-1-mikhail.kshevetskiy@iopsys.eu

Mikhail Kshevetskiy (34):
  dt-bindings: pinctrl: airoha: en7581: fix misprint in i2s function
    name
  dt-bindings: pinctrl: airoha: en7581: fix pwm pin-groups
  dt-bindings: pinctrl: airoha: an7583: fix device tree binding schema
  pinctrl: airoha: an7581: fix misprint in bitfield name
  pinctrl: airoha: an7583: fix I2C0_SDA_PD register bit order
  pinctrl: airoha: an7583: there are no muxes to enable i2c buses
  dt-bindings: pinctrl: airoha: an7583: remove i2c pin function
  pinctrl: airoha: an7581: fix mux/conf of pcie_reset pins
  dt-bindings: pinctrl: airoha: en7581: allow configuration of
    pcie_reset pins as gpio or pwm
  pinctrl: airoha: an7583: fix muxing of non-gpio default pins
  dt-bindings: pinctrl: airoha: an7583: allow configuration of non-gpio
    default pins as gpio and pwm
  pinctrl: airoha: add missed get_direction() function for gpio_chip
  pinctrl: airoha: add set_direction() helper for gpio_chip
  pinctrl: airoha: fix potential kenel panic in IRQ handling code
  pinctrl: airoha: fix IRQ mask/unmask code
  pinctrl: airoha: add missed IRQ resource helpers
  pinctrl: airoha: fix edge-triggered interrupts handling
  pinctrl: airoha: remove not needed irq_type[] array
  pinctrl: airoha: move common definitions to the separate header
  pinctrl: airoha: split driver on shared code and SoC specific drivers
  pinctrl: airoha: an7581: remove en7581 prefix from variable names
  pinctrl: airoha: an7583: remove an7583 prefix from variable names and
    definitions
  pinctrl: airoha: an7583: rename registers to match its an7583 names
  pinctrl: airoha: an7583: add support for npu_uart pinmux
  dt-bindings: pinctrl: airoha: an7583: add npu_uart pin group
  pinctrl: airoha: an7583: add support for pon_alt pinmux
  dt-bindings: pinctrl: airoha: an7583: add pon_alt pin group
  pinctrl: airoha: an7583: add support for olt pinmux
  dt-bindings: pinctrl: airoha: an7583: add olt function/group
  pinctrl: airoha: add support of en7523 SoC
  pinctrl: airoha: try to find chip scu node by phandle first
  dt-bindings: pinctrl: airoha: add support of en7523 pin controller
  pinctrl: airoha: add support of an7563 SoC
  dt-bindings: pinctrl: airoha: add support of an7563 pin controller

 .../pinctrl/airoha,an7563-pinctrl.yaml        |  348 +++
 .../pinctrl/airoha,an7583-pinctrl.yaml        |   65 +-
 .../pinctrl/airoha,en7523-pinctrl.yaml        |  375 +++
 .../pinctrl/airoha,en7581-pinctrl.yaml        |   15 +-
 drivers/pinctrl/airoha/Kconfig                |   42 +-
 drivers/pinctrl/airoha/Makefile               |    7 +
 drivers/pinctrl/airoha/airoha-common.h        |  169 ++
 drivers/pinctrl/airoha/pinctrl-airoha.c       | 2608 +----------------
 drivers/pinctrl/airoha/pinctrl-an7563.c       | 1115 +++++++
 drivers/pinctrl/airoha/pinctrl-an7581.c       | 1487 ++++++++++
 drivers/pinctrl/airoha/pinctrl-an7583.c       | 1497 ++++++++++
 drivers/pinctrl/airoha/pinctrl-en7523.c       | 1125 +++++++
 12 files changed, 6369 insertions(+), 2484 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/airoha,an7563-pinctrl.yaml
 create mode 100644 Documentation/devicetree/bindings/pinctrl/airoha,en7523-pinctrl.yaml
 create mode 100644 drivers/pinctrl/airoha/airoha-common.h
 create mode 100644 drivers/pinctrl/airoha/pinctrl-an7563.c
 create mode 100644 drivers/pinctrl/airoha/pinctrl-an7581.c
 create mode 100644 drivers/pinctrl/airoha/pinctrl-an7583.c
 create mode 100644 drivers/pinctrl/airoha/pinctrl-en7523.c

-- 
2.53.0

[PATCH v7 01/34] dt-bindings: pinctrl: airoha: en7581: fix misprint in i2s function name

[Mikhail Kshevetskiy]

i2s pin-function is missed, instead i2c pin-function defined twice. The
second of them operates with i2s pin-group.

The patch fixes the misprint. It also match actual pinctrl driver.

Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
---
 .../devicetree/bindings/pinctrl/airoha,en7581-pinctrl.yaml      | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/pinctrl/airoha,en7581-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/airoha,en7581-pinctrl.yaml
index 21fd4f1ba78b0..0c5a7eb6d563e 100644
--- a/Documentation/devicetree/bindings/pinctrl/airoha,en7581-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/airoha,en7581-pinctrl.yaml
@@ -166,7 +166,7 @@ patternProperties:
           - if:
               properties:
                 function:
-                  const: i2c
+                  const: i2s
             then:
               properties:
                 groups:
-- 
2.53.0

Re: [PATCH v7 01/34] dt-bindings: pinctrl: airoha: en7581: fix misprint in i2s function name

[Lorenzo Bianconi]

[-- Attachment #1: Type: text/plain, Size: 1118 bytes --]

> i2s pin-function is missed, instead i2c pin-function defined twice. The
> second of them operates with i2s pin-group.
> 
> The patch fixes the misprint. It also match actual pinctrl driver.

I guess you shold add a Fixes tag here.

Regards,
Lorenzo

> 
> Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
> ---
>  .../devicetree/bindings/pinctrl/airoha,en7581-pinctrl.yaml      | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/Documentation/devicetree/bindings/pinctrl/airoha,en7581-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/airoha,en7581-pinctrl.yaml
> index 21fd4f1ba78b0..0c5a7eb6d563e 100644
> --- a/Documentation/devicetree/bindings/pinctrl/airoha,en7581-pinctrl.yaml
> +++ b/Documentation/devicetree/bindings/pinctrl/airoha,en7581-pinctrl.yaml
> @@ -166,7 +166,7 @@ patternProperties:
>            - if:
>                properties:
>                  function:
> -                  const: i2c
> +                  const: i2s
>              then:
>                properties:
>                  groups:
> -- 
> 2.53.0
> 

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Re: [PATCH v7 01/34] dt-bindings: pinctrl: airoha: en7581: fix misprint in i2s function name

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:

Pre-existing issues:
- [Low] Incomplete fix: identical copy-paste misprint for 'i2s' function was missed in the sibling binding 'airoha,an7583-pinctrl.yaml'.
--

--- Patch [1]: [PATCH v7 01/34] dt-bindings: pinctrl: airoha: en7581: fix misprint in i2s function name ---
commit 0749f859891dd657945c83f8003df4b6494d5a24
Author: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>

dt-bindings: pinctrl: airoha: en7581: fix misprint in i2s function name

This patch fixes a misprint in the EN7581 pinctrl binding where the "i2c"
pin function was defined twice, hiding the "i2s" pin function. The correction
aligns the binding with the actual pinctrl driver.

> diff --git a/Documentation/devicetree/bindings/pinctrl/airoha,en7581-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/airoha,en7581-pinctrl.yaml
> --- a/Documentation/devicetree/bindings/pinctrl/airoha,en7581-pinctrl.yaml
> +++ b/Documentation/devicetree/bindings/pinctrl/airoha,en7581-pinctrl.yaml
> @@ -166,7 +166,7 @@ patternProperties:
>            - if:
>                properties:
>                  function:
> -                  const: i2c
> +                  const: i2s

[Severity: Low]
This isn't a bug introduced by this patch, but does the same misprint exist
in the sibling binding for the AN7583?

Looking at Documentation/devicetree/bindings/pinctrl/airoha,an7583-pinctrl.yaml
in the patternProperties:^mux(-|$):allOf block:

          - if:
              properties:
                function:
                  const: i2c
            then:
              properties:
                groups:
                  enum: [i2s]

Should this file also be updated alongside the EN7581 changes to prevent
schema validation from improperly failing when checking the i2c or i2s pin
functions on the AN7583 SoC?

>              then:
>                properties:
>                  groups:
>                    enum: [i2s]

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260727074234.3761170-1-mikhail.kshevetskiy@iopsys.eu?part=1

[PATCH v7 02/34] dt-bindings: pinctrl: airoha: en7581: fix pwm pin-groups

[Mikhail Kshevetskiy]

According to commit 08a5af468e613b ("pinctrl: airoha: fix pwm pin function
for an7581 and an7583") there is no gpio47 pin-group, so device schema must
be fixed.

Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
---
 .../devicetree/bindings/pinctrl/airoha,en7581-pinctrl.yaml      | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/pinctrl/airoha,en7581-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/airoha,en7581-pinctrl.yaml
index 0c5a7eb6d563e..12dd85b5b4105 100644
--- a/Documentation/devicetree/bindings/pinctrl/airoha,en7581-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/airoha,en7581-pinctrl.yaml
@@ -208,7 +208,7 @@ patternProperties:
                          gpio20, gpio21, gpio22, gpio23, gpio24, gpio25,
                          gpio26, gpio27, gpio28, gpio29, gpio30, gpio31,
                          gpio36, gpio37, gpio38, gpio39, gpio40, gpio41,
-                         gpio42, gpio43, gpio44, gpio45, gpio46, gpio47]
+                         gpio42, gpio43, gpio44, gpio45, gpio46]
           - if:
               properties:
                 function:
-- 
2.53.0

Re: [PATCH v7 02/34] dt-bindings: pinctrl: airoha: en7581: fix pwm pin-groups

[Lorenzo Bianconi]

[-- Attachment #1: Type: text/plain, Size: 1313 bytes --]

> According to commit 08a5af468e613b ("pinctrl: airoha: fix pwm pin function
> for an7581 and an7583") there is no gpio47 pin-group, so device schema must
> be fixed.

same here, missing Fixes tag.

Regards,
Lorenzo

> 
> Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
> ---
>  .../devicetree/bindings/pinctrl/airoha,en7581-pinctrl.yaml      | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/Documentation/devicetree/bindings/pinctrl/airoha,en7581-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/airoha,en7581-pinctrl.yaml
> index 0c5a7eb6d563e..12dd85b5b4105 100644
> --- a/Documentation/devicetree/bindings/pinctrl/airoha,en7581-pinctrl.yaml
> +++ b/Documentation/devicetree/bindings/pinctrl/airoha,en7581-pinctrl.yaml
> @@ -208,7 +208,7 @@ patternProperties:
>                           gpio20, gpio21, gpio22, gpio23, gpio24, gpio25,
>                           gpio26, gpio27, gpio28, gpio29, gpio30, gpio31,
>                           gpio36, gpio37, gpio38, gpio39, gpio40, gpio41,
> -                         gpio42, gpio43, gpio44, gpio45, gpio46, gpio47]
> +                         gpio42, gpio43, gpio44, gpio45, gpio46]
>            - if:
>                properties:
>                  function:
> -- 
> 2.53.0
> 

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[PATCH v7 03/34] dt-bindings: pinctrl: airoha: an7583: fix device tree binding schema

[Mikhail Kshevetskiy]

An7583 device tree binding schema was more or less blinly copied from
corresponding en7581 schema. As result it's not correct.

There are following issues:
 * i2s pin-function is not really defined for an7583
 * i2s pin-function by mistake was replaced by i2c pin-function in the
   functions/groups checks
 * pcm_spi pin-function defined for less number of pin-groups
 * pwm pin-function should have more pin-groups elements
 * unexisting pins was defined

This patch fixes an7583 schema, so it matches actual pinctrl driver.

Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
---
 .../pinctrl/airoha,an7583-pinctrl.yaml        | 37 +++++++------------
 1 file changed, 14 insertions(+), 23 deletions(-)

diff --git a/Documentation/devicetree/bindings/pinctrl/airoha,an7583-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/airoha,an7583-pinctrl.yaml
index 79910214d9b5c..f52802a3ad79d 100644
--- a/Documentation/devicetree/bindings/pinctrl/airoha,an7583-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/airoha,an7583-pinctrl.yaml
@@ -61,7 +61,7 @@ patternProperties:
             description:
               A string containing the name of the function to mux to the group.
             enum: [pon, tod_1pps, sipo, mdio, uart, i2c, jtag, pcm, spi,
-                   pcm_spi, i2s, emmc, pnand, pcie_reset, pwm, phy1_led0,
+                   pcm_spi, emmc, pnand, pcie_reset, pwm, phy1_led0,
                    phy2_led0, phy3_led0, phy4_led0, phy1_led1, phy2_led1,
                    phy3_led1, phy4_led1]
 
@@ -159,17 +159,8 @@ patternProperties:
               properties:
                 groups:
                   items:
-                    enum: [pcm_spi, pcm_spi_int, pcm_spi_rst, pcm_spi_cs1,
-                           pcm_spi_cs2, pcm_spi_cs3, pcm_spi_cs4]
-                  maxItems: 7
-          - if:
-              properties:
-                function:
-                  const: i2c
-            then:
-              properties:
-                groups:
-                  enum: [i2s]
+                    enum: [pcm_spi, pcm_spi_rst, pcm_spi_cs1]
+                  maxItems: 3
           - if:
               properties:
                 function:
@@ -207,7 +198,8 @@ patternProperties:
                          gpio20, gpio21, gpio22, gpio23, gpio24, gpio25,
                          gpio26, gpio27, gpio28, gpio29, gpio30, gpio31,
                          gpio36, gpio37, gpio38, gpio39, gpio40, gpio41,
-                         gpio42, gpio43, gpio44, gpio45, gpio46, gpio47]
+                         gpio42, gpio43, gpio44, gpio45, gpio46, gpio47,
+                         gpio48]
           - if:
               properties:
                 function:
@@ -288,17 +280,16 @@ patternProperties:
             description:
               An array of strings. Each string contains the name of a pin.
             items:
-              enum: [uart1_txd, uart1_rxd, i2c_scl, i2c_sda, spi_cs0, spi_clk,
-                     spi_mosi, spi_miso, gpio0, gpio1, gpio2, gpio3, gpio4,
-                     gpio5, gpio6, gpio7, gpio8, gpio9, gpio10, gpio11, gpio12,
-                     gpio13, gpio14, gpio15, gpio16, gpio17, gpio18, gpio19,
-                     gpio20, gpio21, gpio22, gpio23, gpio24, gpio25, gpio26,
-                     gpio27, gpio28, gpio29, gpio30, gpio31, gpio32, gpio33,
-                     gpio34, gpio35, gpio36, gpio37, gpio38, gpio39, gpio40,
-                     gpio41, gpio42, gpio43, gpio44, gpio45, gpio46,
-                     pcie_reset0, pcie_reset1, pcie_reset2]
+              enum: [gpio0, gpio1, gpio2, gpio3, gpio4, gpio5, gpio6, gpio7,
+                     gpio8, gpio9, gpio10, gpio11, gpio12, gpio13, gpio14,
+                     gpio15, gpio16, gpio17, gpio18, gpio19, gpio20, gpio21,
+                     gpio22, gpio23, gpio24, gpio25, gpio26, gpio27, gpio28,
+                     gpio29, gpio30, gpio31, gpio32, gpio33, gpio34, gpio35,
+                     gpio36, gpio37, gpio38, i2c0_scl, i2c0_sda, i2c1_scl,
+                     i2c1_sda, spi_clk, spi_cs, spi_mosi, spi_miso, uart_txd,
+                     uart_rxd, pcie_reset0, pcie_reset1, mdc_0, mdio_0]
             minItems: 1
-            maxItems: 58
+            maxItems: 53
 
           bias-disable: true
 
-- 
2.53.0

[PATCH v7 04/34] pinctrl: airoha: an7581: fix misprint in bitfield name

[Mikhail Kshevetskiy]

Fix misprint in bitfield name of GPIO_2ND_I2C_MODE register

Fixes: 1c8ace2d0725 ("pinctrl: airoha: Add support for EN7581 SoC")
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
---
 drivers/pinctrl/airoha/pinctrl-airoha.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/pinctrl/airoha/pinctrl-airoha.c b/drivers/pinctrl/airoha/pinctrl-airoha.c
index abfb018f207e5..a3cfee6ace778 100644
--- a/drivers/pinctrl/airoha/pinctrl-airoha.c
+++ b/drivers/pinctrl/airoha/pinctrl-airoha.c
@@ -49,7 +49,7 @@
 
 /* MUX */
 #define REG_GPIO_2ND_I2C_MODE			0x0214
-#define GPIO_MDC_IO_MASTER_MODE_MODE		BIT(14)
+#define GPIO_MDC_IO_MASTER_MODE_MASK		BIT(14)
 #define GPIO_I2C_MASTER_MODE_MODE		BIT(13)
 #define GPIO_I2S_MODE_MASK			BIT(12)
 #define GPIO_I2C_SLAVE_MODE_MODE		BIT(11)
@@ -1026,8 +1026,8 @@ static const struct airoha_pinctrl_func_group mdio_func_group[] = {
 		.regmap[0] = {
 			AIROHA_FUNC_MUX,
 			REG_GPIO_2ND_I2C_MODE,
-			GPIO_MDC_IO_MASTER_MODE_MODE,
-			GPIO_MDC_IO_MASTER_MODE_MODE
+			GPIO_MDC_IO_MASTER_MODE_MASK,
+			GPIO_MDC_IO_MASTER_MODE_MASK
 		},
 		.regmap[1] = {
 			AIROHA_FUNC_MUX,
@@ -1051,8 +1051,8 @@ static const struct airoha_pinctrl_func_group an7583_mdio_func_group[] = {
 		.regmap[1] = {
 			AIROHA_FUNC_MUX,
 			REG_GPIO_SPI_CS1_MODE,
-			GPIO_MDC_IO_MASTER_MODE_MODE,
-			GPIO_MDC_IO_MASTER_MODE_MODE
+			GPIO_MDC_IO_MASTER_MODE_MASK,
+			GPIO_MDC_IO_MASTER_MODE_MASK
 		},
 		.regmap_size = 2,
 	},
-- 
2.53.0

Re: [PATCH v7 04/34] pinctrl: airoha: an7581: fix misprint in bitfield name

[Lorenzo Bianconi]

[-- Attachment #1: Type: text/plain, Size: 1768 bytes --]

> Fix misprint in bitfield name of GPIO_2ND_I2C_MODE register
> 
> Fixes: 1c8ace2d0725 ("pinctrl: airoha: Add support for EN7581 SoC")
> Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>

Acked-by: Lorenzo Bianconi <lorenzo@kernel.org>

I guess you can fix GPIO_I2C_MASTER_MODE_MODE too.

Regards,
Lorenzo

> ---
>  drivers/pinctrl/airoha/pinctrl-airoha.c | 10 +++++-----
>  1 file changed, 5 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/pinctrl/airoha/pinctrl-airoha.c b/drivers/pinctrl/airoha/pinctrl-airoha.c
> index abfb018f207e5..a3cfee6ace778 100644
> --- a/drivers/pinctrl/airoha/pinctrl-airoha.c
> +++ b/drivers/pinctrl/airoha/pinctrl-airoha.c
> @@ -49,7 +49,7 @@
>  
>  /* MUX */
>  #define REG_GPIO_2ND_I2C_MODE			0x0214
> -#define GPIO_MDC_IO_MASTER_MODE_MODE		BIT(14)
> +#define GPIO_MDC_IO_MASTER_MODE_MASK		BIT(14)
>  #define GPIO_I2C_MASTER_MODE_MODE		BIT(13)
>  #define GPIO_I2S_MODE_MASK			BIT(12)
>  #define GPIO_I2C_SLAVE_MODE_MODE		BIT(11)
> @@ -1026,8 +1026,8 @@ static const struct airoha_pinctrl_func_group mdio_func_group[] = {
>  		.regmap[0] = {
>  			AIROHA_FUNC_MUX,
>  			REG_GPIO_2ND_I2C_MODE,
> -			GPIO_MDC_IO_MASTER_MODE_MODE,
> -			GPIO_MDC_IO_MASTER_MODE_MODE
> +			GPIO_MDC_IO_MASTER_MODE_MASK,
> +			GPIO_MDC_IO_MASTER_MODE_MASK
>  		},
>  		.regmap[1] = {
>  			AIROHA_FUNC_MUX,
> @@ -1051,8 +1051,8 @@ static const struct airoha_pinctrl_func_group an7583_mdio_func_group[] = {
>  		.regmap[1] = {
>  			AIROHA_FUNC_MUX,
>  			REG_GPIO_SPI_CS1_MODE,
> -			GPIO_MDC_IO_MASTER_MODE_MODE,
> -			GPIO_MDC_IO_MASTER_MODE_MODE
> +			GPIO_MDC_IO_MASTER_MODE_MASK,
> +			GPIO_MDC_IO_MASTER_MODE_MASK
>  		},
>  		.regmap_size = 2,
>  	},
> -- 
> 2.53.0
> 

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Re: [PATCH v7 04/34] pinctrl: airoha: an7581: fix misprint in bitfield name

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:

Pre-existing issues:
- [High] `an7583_mdio_func_group` incorrectly applies `GPIO_MDC_IO_MASTER_MODE_MASK` to the `REG_GPIO_SPI_CS1_MODE` register, causing hardware configuration corruption.
--

--- Patch [4]: [PATCH v7 04/34] pinctrl: airoha: an7581: fix misprint in bitfield name ---
commit 69c3ff6d2f6ded4cac1d3fa356dd0e46f67e9ed4
Author: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>

pinctrl: airoha: an7581: fix misprint in bitfield name

This commit fixes a typo in the bitfield name for the GPIO_2ND_I2C_MODE
register, renaming GPIO_MDC_IO_MASTER_MODE_MODE to
GPIO_MDC_IO_MASTER_MODE_MASK.

> diff --git a/drivers/pinctrl/airoha/pinctrl-airoha.c b/drivers/pinctrl/airoha/pinctrl-airoha.c
> index 04b4424c688b2..63c82268aa823 100644
> --- a/drivers/pinctrl/airoha/pinctrl-airoha.c
> +++ b/drivers/pinctrl/airoha/pinctrl-airoha.c

[ ... ]

> @@ -1051,8 +1051,8 @@ static const struct airoha_pinctrl_func_group an7583_mdio_func_group[] = {
>  		.regmap[1] = {
>  			AIROHA_FUNC_MUX,
>  			REG_GPIO_SPI_CS1_MODE,
> -			GPIO_MDC_IO_MASTER_MODE_MODE,
> -			GPIO_MDC_IO_MASTER_MODE_MODE
> +			GPIO_MDC_IO_MASTER_MODE_MASK,
> +			GPIO_MDC_IO_MASTER_MODE_MASK

[Severity: High]
This isn't a bug introduced by this patch, but is it intentional to use
GPIO_MDC_IO_MASTER_MODE_MASK with the REG_GPIO_SPI_CS1_MODE register here in
an7583_mdio_func_group?

It appears that BIT(14) in REG_GPIO_SPI_CS1_MODE maps to
GPIO_PCM_SPI_MODE_MASK rather than MDC IO master mode. Could this fail to
enable the MDC IO master mode for MDIO and unintentionally alter the PCM SPI
mode instead?

>  		},
>  		.regmap_size = 2,
>  	},

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260727074234.3761170-1-mikhail.kshevetskiy@iopsys.eu?part=4

[PATCH v7 05/34] pinctrl: airoha: an7583: fix I2C0_SDA_PD register bit order

[Mikhail Kshevetskiy]

I2C1_SCL_PD and RG_I2C1_SDA_PD bits are swapped, fix it.

Fixes: 3ffeb17a9a27 ("pinctrl: airoha: add support for Airoha AN7583 PINs")
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
---
 drivers/pinctrl/airoha/pinctrl-airoha.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/pinctrl/airoha/pinctrl-airoha.c b/drivers/pinctrl/airoha/pinctrl-airoha.c
index a3cfee6ace778..b5cd4f476caea 100644
--- a/drivers/pinctrl/airoha/pinctrl-airoha.c
+++ b/drivers/pinctrl/airoha/pinctrl-airoha.c
@@ -184,8 +184,8 @@
 #define I2C_SDA_PU_MASK				BIT(0)
 
 #define REG_I2C_SDA_PD				0x0048
-#define AN7583_I2C1_SDA_PD_MASK			BIT(16)
-#define AN7583_I2C1_SCL_PD_MASK			BIT(15)
+#define AN7583_I2C1_SCL_PD_MASK			BIT(16)
+#define AN7583_I2C1_SDA_PD_MASK			BIT(15)
 #define SPI_MISO_PD_MASK			BIT(14)
 #define SPI_MOSI_PD_MASK			BIT(13)
 #define SPI_CLK_PD_MASK				BIT(12)
-- 
2.53.0

Re: [PATCH v7 05/34] pinctrl: airoha: an7583: fix I2C0_SDA_PD register bit order

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:

Pre-existing issues:
- [High] The driver hardcodes handle_simple_irq and clears the interrupt status after handling, leading to lost edge-triggered interrupts.
- [High] The EN7581 I2C0 pins have their configuration masks swapped compared to their pin definitions.
--

--- Patch [5]: [PATCH v7 05/34] pinctrl: airoha: an7583: fix I2C0_SDA_PD register bit order ---
commit 71ba4b6ac3f1b7dcaded906468f0a3ce96cffdb2
Author: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>

pinctrl: airoha: an7583: fix I2C0_SDA_PD register bit order
    
I2C1_SCL_PD and RG_I2C1_SDA_PD bits are swapped, fix it.

> diff --git a/drivers/pinctrl/airoha/pinctrl-airoha.c b/drivers/pinctrl/airoha/pinctrl-airoha.c
> index 63c82268aa823..4076bd0261d17 100644
> --- a/drivers/pinctrl/airoha/pinctrl-airoha.c
> +++ b/drivers/pinctrl/airoha/pinctrl-airoha.c
> @@ -184,8 +184,8 @@
>  #define I2C_SDA_PU_MASK				BIT(0)
>  
>  #define REG_I2C_SDA_PD				0x0048
> -#define AN7583_I2C1_SDA_PD_MASK			BIT(16)
> -#define AN7583_I2C1_SCL_PD_MASK			BIT(15)
> +#define AN7583_I2C1_SCL_PD_MASK			BIT(16)
> +#define AN7583_I2C1_SDA_PD_MASK			BIT(15)

[Severity: High]
This isn't a bug introduced by this patch, but while you are fixing
swapped pins here, I noticed that the EN7581 I2C0 pins also appear to have
their configuration masks swapped.

For example, in en7581_pinctrl_pullup_conf:

drivers/pinctrl/airoha/pinctrl-airoha.c:en7581_pinctrl_pullup_conf[]
	PINCTRL_CONF_DESC(2, REG_I2C_SDA_PU, I2C_SDA_PU_MASK),
	PINCTRL_CONF_DESC(3, REG_I2C_SDA_PU, I2C_SCL_PU_MASK),

Is it possible that pin 2 (i2c_scl) incorrectly gets the SDA pull-up mask,
and pin 3 (i2c_sda) gets the SCL pull-up mask?

This same swap appears in en7581_pinctrl_pulldown_conf,
en7581_pinctrl_drive_e2_conf, and en7581_pinctrl_drive_e4_conf. Could
applying these settings via device tree modify the wrong hardware lines and
prevent I2C communication?

[Severity: High]
This is a pre-existing issue, but I also noticed a potential problem in
how edge-triggered interrupts are handled.

drivers/pinctrl/airoha/pinctrl-airoha.c:airoha_pinctrl_add_gpiochip()
	girq->default_type = IRQ_TYPE_NONE;
	girq->handler = handle_simple_irq;

By unconditionally hardcoding handle_simple_irq, doesn't this bypass the
core IRQ edge flow logic (handle_edge_irq) required for correct acknowledge
ordering?

In airoha_irq_handler():

drivers/pinctrl/airoha/pinctrl-airoha.c:airoha_irq_handler()
			generic_handle_irq(irq_find_mapping(girq->domain,
							    offset));
			regmap_write(pinctrl->regmap,
				     pinctrl->gpiochip.status[i], BIT(irq));

If an edge-triggered interrupt occurs while a previous interrupt for the
same pin is actively being handled by generic_handle_irq(), and then the
status bit is manually cleared by regmap_write(), does this permanently
erase the hardware record of the second edge and drop the interrupt?

>  #define SPI_MISO_PD_MASK			BIT(14)
>  #define SPI_MOSI_PD_MASK			BIT(13)
>  #define SPI_CLK_PD_MASK				BIT(12)

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260727074234.3761170-1-mikhail.kshevetskiy@iopsys.eu?part=5

[PATCH v7 06/34] pinctrl: airoha: an7583: there are no muxes to enable i2c buses

[Mikhail Kshevetskiy]

In the AN7583 case there are no mux bits to enable i2c buses, so i2c pin
function is not necessary.

Fixes: 3ffeb17a9a27 ("pinctrl: airoha: add support for Airoha AN7583 PINs")
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
---
 drivers/pinctrl/airoha/pinctrl-airoha.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/pinctrl/airoha/pinctrl-airoha.c b/drivers/pinctrl/airoha/pinctrl-airoha.c
index b5cd4f476caea..caa1afcc1697f 100644
--- a/drivers/pinctrl/airoha/pinctrl-airoha.c
+++ b/drivers/pinctrl/airoha/pinctrl-airoha.c
@@ -1821,7 +1821,6 @@ static const struct airoha_pinctrl_func an7583_pinctrl_funcs[] = {
 	PINCTRL_FUNC_DESC("sipo", sipo),
 	PINCTRL_FUNC_DESC("mdio", an7583_mdio),
 	PINCTRL_FUNC_DESC("uart", uart),
-	PINCTRL_FUNC_DESC("i2c", i2c),
 	PINCTRL_FUNC_DESC("jtag", jtag),
 	PINCTRL_FUNC_DESC("pcm", pcm),
 	PINCTRL_FUNC_DESC("spi", spi),
-- 
2.53.0

Re: [PATCH v7 06/34] pinctrl: airoha: an7583: there are no muxes to enable i2c buses

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [Medium] The 'i2c' function is removed from the AN7583 pinctrl driver but remains explicitly documented and allowed in the device tree binding schema.
- [Low] The 'i2c0' and 'i2c1' pin groups for AN7583 are left completely unreferenced and unusable by the devicetree.
--

--- Patch [6]: [PATCH v7 06/34] pinctrl: airoha: an7583: there are no muxes to enable i2c buses ---
commit 22df8bb0430afc8490b745f45493ae811f88f9d8
Author: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>

pinctrl: airoha: an7583: there are no muxes to enable i2c buses
    
In the AN7583 case there are no mux bits to enable i2c buses, so i2c pin
function is not necessary.
    
Fixes: 3ffeb17a9a27 ("pinctrl: airoha: add support for Airoha AN7583 PINs")

> diff --git a/drivers/pinctrl/airoha/pinctrl-airoha.c b/drivers/pinctrl/airoha/pinctrl-airoha.c
> index 4076bd0261d17..cad56ac3c0614 100644
> --- a/drivers/pinctrl/airoha/pinctrl-airoha.c
> +++ b/drivers/pinctrl/airoha/pinctrl-airoha.c
> @@ -1821,7 +1821,6 @@ static const struct airoha_pinctrl_func an7583_pinctrl_funcs[] = {
>  	PINCTRL_FUNC_DESC("sipo", sipo),
>  	PINCTRL_FUNC_DESC("mdio", an7583_mdio),
>  	PINCTRL_FUNC_DESC("uart", uart),
> -	PINCTRL_FUNC_DESC("i2c", i2c),

[Severity: Medium]
With the removal of the "i2c" function here, does the device tree binding
schema need to be updated as well?

The schema currently lists "i2c" as a valid function and enforces group
constraints for it:

Documentation/devicetree/bindings/pinctrl/airoha,an7583-pinctrl.yaml:
            enum: [pon, tod_1pps, sipo, mdio, uart, i2c, jtag, pcm, spi,
...
          properties:
            function:
              const: i2c
        then:
          properties:
            groups:
              enum: [i2c1]

Could this cause validly-schema-checked device trees to fail at runtime
since the driver will no longer support this configuration?

[Severity: Low]
Does removing the "i2c" function leave the "i2c0" and "i2c1" pin groups as
dead code?

Looking at drivers/pinctrl/airoha/pinctrl-airoha.c:an7583_pinctrl_groups:
    PINCTRL_PIN_GROUP("i2c0", an7583_i2c0),
    PINCTRL_PIN_GROUP("i2c1", an7583_i2c1),

Since no pinmux function references these groups anymore, should they be
removed to avoid leaving unused static data structures?

>  	PINCTRL_FUNC_DESC("jtag", jtag),
>  	PINCTRL_FUNC_DESC("pcm", pcm),
>  	PINCTRL_FUNC_DESC("spi", spi),

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260727074234.3761170-1-mikhail.kshevetskiy@iopsys.eu?part=6

[PATCH v7 07/34] dt-bindings: pinctrl: airoha: an7583: remove i2c pin function

[Mikhail Kshevetskiy]

In the AN7583 case there are no mux bits to enable i2c buses, so remove i2c
pin function from device tree binding schema.

Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
---
 .../bindings/pinctrl/airoha,an7583-pinctrl.yaml        | 10 +---------
 1 file changed, 1 insertion(+), 9 deletions(-)

diff --git a/Documentation/devicetree/bindings/pinctrl/airoha,an7583-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/airoha,an7583-pinctrl.yaml
index f52802a3ad79d..8d8ec6adb97d1 100644
--- a/Documentation/devicetree/bindings/pinctrl/airoha,an7583-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/airoha,an7583-pinctrl.yaml
@@ -60,7 +60,7 @@ patternProperties:
           function:
             description:
               A string containing the name of the function to mux to the group.
-            enum: [pon, tod_1pps, sipo, mdio, uart, i2c, jtag, pcm, spi,
+            enum: [pon, tod_1pps, sipo, mdio, uart, jtag, pcm, spi,
                    pcm_spi, emmc, pnand, pcie_reset, pwm, phy1_led0,
                    phy2_led0, phy3_led0, phy4_led0, phy1_led1, phy2_led1,
                    phy3_led1, phy4_led1]
@@ -117,14 +117,6 @@ patternProperties:
                     enum: [uart2, uart2_cts_rts, hsuart, hsuart_cts_rts,
                            uart4, uart5]
                   maxItems: 2
-          - if:
-              properties:
-                function:
-                  const: i2c
-            then:
-              properties:
-                groups:
-                  enum: [i2c1]
           - if:
               properties:
                 function:
-- 
2.53.0

Re: [PATCH v7 07/34] dt-bindings: pinctrl: airoha: an7583: remove i2c pin function

[Lorenzo Bianconi]

[-- Attachment #1: Type: text/plain, Size: 1791 bytes --]

> In the AN7583 case there are no mux bits to enable i2c buses, so remove i2c
> pin function from device tree binding schema.

missing Fixes tag.

Regards,
Lorenzo

> 
> Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
> ---
>  .../bindings/pinctrl/airoha,an7583-pinctrl.yaml        | 10 +---------
>  1 file changed, 1 insertion(+), 9 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/pinctrl/airoha,an7583-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/airoha,an7583-pinctrl.yaml
> index f52802a3ad79d..8d8ec6adb97d1 100644
> --- a/Documentation/devicetree/bindings/pinctrl/airoha,an7583-pinctrl.yaml
> +++ b/Documentation/devicetree/bindings/pinctrl/airoha,an7583-pinctrl.yaml
> @@ -60,7 +60,7 @@ patternProperties:
>            function:
>              description:
>                A string containing the name of the function to mux to the group.
> -            enum: [pon, tod_1pps, sipo, mdio, uart, i2c, jtag, pcm, spi,
> +            enum: [pon, tod_1pps, sipo, mdio, uart, jtag, pcm, spi,
>                     pcm_spi, emmc, pnand, pcie_reset, pwm, phy1_led0,
>                     phy2_led0, phy3_led0, phy4_led0, phy1_led1, phy2_led1,
>                     phy3_led1, phy4_led1]
> @@ -117,14 +117,6 @@ patternProperties:
>                      enum: [uart2, uart2_cts_rts, hsuart, hsuart_cts_rts,
>                             uart4, uart5]
>                    maxItems: 2
> -          - if:
> -              properties:
> -                function:
> -                  const: i2c
> -            then:
> -              properties:
> -                groups:
> -                  enum: [i2c1]
>            - if:
>                properties:
>                  function:
> -- 
> 2.53.0
> 

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]

[PATCH v7 08/34] pinctrl: airoha: an7581: fix mux/conf of pcie_reset pins

[Mikhail Kshevetskiy]

In the an7581 case
 * gpio47 and pcie_reset0 shares pin 60,
 * gpio48 and pcie_reset1 shares pin 61,
 * gpio49 and pcie_reset2 shares pin 62.
but current driver treat them as pins 61--63. This is wrong.

Also current an7581 pinmux implementation have following issues:
 * current pcie_reset pin function actually sets corresponding
   pins as gpios.
 * there is no proper way to set pcie_reset pins as gpios.
 * there is no way to set pcie_reset pins as pwm.

This patch fixes above issues.

WARNING:
There is a contradiction in the Airoha documentation. AN7581 programming
guide claims:
 - gpio44 and pcie_reset0 shares the same pin
 - gpio45 and pcie_reset1 shares the same pin
 - gpio46 and pcie_reset2 shares the same pin
While AN7581 datasheet claims:
 - gpio47 and pcie_reset0 shares the same pin
 - gpio48 and pcie_reset1 shares the same pin
 - gpio49 and pcie_reset2 shares the same pin
The datasheet should be considered as a more reliable source.
Thanks to Benjamin Larsson for clarification.

Fixes: 1c8ace2d0725 ("pinctrl: airoha: Add support for EN7581 SoC")
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
---
 drivers/pinctrl/airoha/pinctrl-airoha.c | 122 +++++++++++++++++++-----
 1 file changed, 97 insertions(+), 25 deletions(-)

diff --git a/drivers/pinctrl/airoha/pinctrl-airoha.c b/drivers/pinctrl/airoha/pinctrl-airoha.c
index caa1afcc1697f..b30b593e9dbf0 100644
--- a/drivers/pinctrl/airoha/pinctrl-airoha.c
+++ b/drivers/pinctrl/airoha/pinctrl-airoha.c
@@ -469,9 +469,9 @@ static struct pinctrl_pin_desc en7581_pinctrl_pins[] = {
 	PINCTRL_PIN(57, "gpio44"),
 	PINCTRL_PIN(58, "gpio45"),
 	PINCTRL_PIN(59, "gpio46"),
-	PINCTRL_PIN(61, "pcie_reset0"),
-	PINCTRL_PIN(62, "pcie_reset1"),
-	PINCTRL_PIN(63, "pcie_reset2"),
+	PINCTRL_PIN(60, "pcie_reset0"),
+	PINCTRL_PIN(61, "pcie_reset1"),
+	PINCTRL_PIN(62, "pcie_reset2"),
 };
 
 static const int en7581_pon_pins[] = { 49, 50, 51, 52, 53, 54 };
@@ -554,9 +554,12 @@ static const int en7581_gpio43_pins[] = { 56 };
 static const int en7581_gpio44_pins[] = { 57 };
 static const int en7581_gpio45_pins[] = { 58 };
 static const int en7581_gpio46_pins[] = { 59 };
-static const int en7581_pcie_reset0_pins[] = { 61 };
-static const int en7581_pcie_reset1_pins[] = { 62 };
-static const int en7581_pcie_reset2_pins[] = { 63 };
+static const int en7581_gpio47_pins[] = { 60 };
+static const int en7581_gpio48_pins[] = { 61 };
+static const int en7581_gpio49_pins[] = { 62 };
+static const int en7581_pcie_reset0_pins[] = { 60 };
+static const int en7581_pcie_reset1_pins[] = { 61 };
+static const int en7581_pcie_reset2_pins[] = { 62 };
 
 static const struct pingroup en7581_pinctrl_groups[] = {
 	PINCTRL_PIN_GROUP("pon", en7581_pon),
@@ -639,6 +642,9 @@ static const struct pingroup en7581_pinctrl_groups[] = {
 	PINCTRL_PIN_GROUP("gpio44", en7581_gpio44),
 	PINCTRL_PIN_GROUP("gpio45", en7581_gpio45),
 	PINCTRL_PIN_GROUP("gpio46", en7581_gpio46),
+	PINCTRL_PIN_GROUP("gpio47", en7581_gpio47),
+	PINCTRL_PIN_GROUP("gpio48", en7581_gpio48),
+	PINCTRL_PIN_GROUP("gpio49", en7581_gpio49),
 	PINCTRL_PIN_GROUP("pcie_reset0", en7581_pcie_reset0),
 	PINCTRL_PIN_GROUP("pcie_reset1", en7581_pcie_reset1),
 	PINCTRL_PIN_GROUP("pcie_reset2", en7581_pcie_reset2),
@@ -882,6 +888,7 @@ static const char *const an7583_pcm_spi_groups[] = { "pcm_spi",
 static const char *const i2s_groups[] = { "i2s" };
 static const char *const emmc_groups[] = { "emmc" };
 static const char *const pnand_groups[] = { "pnand" };
+static const char *const gpio_groups[] = { "gpio47", "gpio48", "gpio49" };
 static const char *const pcie_reset_groups[] = { "pcie_reset0", "pcie_reset1",
 						 "pcie_reset2" };
 static const char *const an7583_pcie_reset_groups[] = { "pcie_reset0", "pcie_reset1" };
@@ -906,7 +913,8 @@ static const char *const pwm_groups[] = { "gpio0", "gpio1",
 					  "gpio40", "gpio41",
 					  "gpio42", "gpio43",
 					  "gpio44", "gpio45",
-					  "gpio46" };
+					  "gpio46", "gpio47",
+					  "gpio48", "gpio49" };
 static const char *const an7583_pwm_groups[] = { "gpio0", "gpio1",
 						 "gpio2", "gpio3",
 						 "gpio4", "gpio5",
@@ -1405,6 +1413,45 @@ static const struct airoha_pinctrl_func_group pnand_func_group[] = {
 	},
 };
 
+#define AIROHA_PINCTRL_GPIO(gpio, mux_val)			\
+	{							\
+		.name = (gpio),					\
+		.regmap[0] = {					\
+			AIROHA_FUNC_MUX,			\
+			REG_GPIO_PON_MODE,			\
+			(mux_val),				\
+			(mux_val)				\
+		},						\
+		.regmap_size = 1,				\
+	}
+
+#define AIROHA_PINCTRL_GPIO_EXT(gpio, mux_val, smux_val)	\
+	{							\
+		.name = (gpio),					\
+		.regmap[0] = {					\
+			AIROHA_FUNC_PWM_EXT_MUX,		\
+			REG_GPIO_FLASH_MODE_CFG_EXT,		\
+			(mux_val),				\
+			0					\
+		},						\
+		.regmap[1] = {					\
+			AIROHA_FUNC_MUX,			\
+			REG_GPIO_PON_MODE,			\
+			(smux_val),				\
+			(smux_val)				\
+		},						\
+		.regmap_size = 2,				\
+	}
+
+static const struct airoha_pinctrl_func_group gpio_func_group[] = {
+	AIROHA_PINCTRL_GPIO_EXT("gpio47", GPIO47_FLASH_MODE_CFG,
+				GPIO_PCIE_RESET0_MASK),
+	AIROHA_PINCTRL_GPIO_EXT("gpio48", GPIO48_FLASH_MODE_CFG,
+				GPIO_PCIE_RESET1_MASK),
+	AIROHA_PINCTRL_GPIO_EXT("gpio49", GPIO49_FLASH_MODE_CFG,
+				GPIO_PCIE_RESET2_MASK),
+};
+
 static const struct airoha_pinctrl_func_group pcie_reset_func_group[] = {
 	{
 		.name = "pcie_reset0",
@@ -1412,7 +1459,7 @@ static const struct airoha_pinctrl_func_group pcie_reset_func_group[] = {
 			AIROHA_FUNC_MUX,
 			REG_GPIO_PON_MODE,
 			GPIO_PCIE_RESET0_MASK,
-			GPIO_PCIE_RESET0_MASK
+			0
 		},
 		.regmap_size = 1,
 	}, {
@@ -1421,7 +1468,7 @@ static const struct airoha_pinctrl_func_group pcie_reset_func_group[] = {
 			AIROHA_FUNC_MUX,
 			REG_GPIO_PON_MODE,
 			GPIO_PCIE_RESET1_MASK,
-			GPIO_PCIE_RESET1_MASK
+			0
 		},
 		.regmap_size = 1,
 	}, {
@@ -1430,7 +1477,7 @@ static const struct airoha_pinctrl_func_group pcie_reset_func_group[] = {
 			AIROHA_FUNC_MUX,
 			REG_GPIO_PON_MODE,
 			GPIO_PCIE_RESET2_MASK,
-			GPIO_PCIE_RESET2_MASK
+			0
 		},
 		.regmap_size = 1,
 	},
@@ -1483,6 +1530,24 @@ static const struct airoha_pinctrl_func_group an7583_pcie_reset_func_group[] = {
 		.regmap_size = 1,			\
 	}						\
 
+#define AIROHA_PINCTRL_PWM_EXT_SEC(gpio, mux_val, smux_val)	\
+	{							\
+		.name = (gpio),					\
+		.regmap[0] = {					\
+			AIROHA_FUNC_PWM_EXT_MUX,		\
+			REG_GPIO_FLASH_MODE_CFG_EXT,		\
+			(mux_val),				\
+			(mux_val)				\
+		},						\
+		.regmap[1] = {					\
+			AIROHA_FUNC_MUX,			\
+			REG_GPIO_PON_MODE,			\
+			(smux_val),				\
+			(smux_val)				\
+		},						\
+		.regmap_size = 2,				\
+	}
+
 static const struct airoha_pinctrl_func_group pwm_func_group[] = {
 	AIROHA_PINCTRL_PWM("gpio0", GPIO0_FLASH_MODE_CFG),
 	AIROHA_PINCTRL_PWM("gpio1", GPIO1_FLASH_MODE_CFG),
@@ -1527,6 +1592,12 @@ static const struct airoha_pinctrl_func_group pwm_func_group[] = {
 	AIROHA_PINCTRL_PWM_EXT("gpio44", GPIO44_FLASH_MODE_CFG),
 	AIROHA_PINCTRL_PWM_EXT("gpio45", GPIO45_FLASH_MODE_CFG),
 	AIROHA_PINCTRL_PWM_EXT("gpio46", GPIO46_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM_EXT_SEC("gpio47", GPIO47_FLASH_MODE_CFG,
+				   GPIO_PCIE_RESET0_MASK),
+	AIROHA_PINCTRL_PWM_EXT_SEC("gpio48", GPIO48_FLASH_MODE_CFG,
+				   GPIO_PCIE_RESET1_MASK),
+	AIROHA_PINCTRL_PWM_EXT_SEC("gpio49", GPIO49_FLASH_MODE_CFG,
+				   GPIO_PCIE_RESET2_MASK),
 };
 
 static const struct airoha_pinctrl_func_group an7583_pwm_func_group[] = {
@@ -1803,6 +1874,7 @@ static const struct airoha_pinctrl_func en7581_pinctrl_funcs[] = {
 	PINCTRL_FUNC_DESC("i2s", i2s),
 	PINCTRL_FUNC_DESC("emmc", emmc),
 	PINCTRL_FUNC_DESC("pnand", pnand),
+	PINCTRL_FUNC_DESC("gpio", gpio),
 	PINCTRL_FUNC_DESC("pcie_reset", pcie_reset),
 	PINCTRL_FUNC_DESC("pwm", pwm),
 	PINCTRL_FUNC_DESC("phy1_led0", phy1_led0),
@@ -1895,9 +1967,9 @@ static const struct airoha_pinctrl_conf en7581_pinctrl_pullup_conf[] = {
 	PINCTRL_CONF_DESC(57, REG_GPIO_H_PU, BIT(12)),
 	PINCTRL_CONF_DESC(58, REG_GPIO_H_PU, BIT(13)),
 	PINCTRL_CONF_DESC(59, REG_GPIO_H_PU, BIT(14)),
-	PINCTRL_CONF_DESC(61, REG_I2C_SDA_PU, PCIE0_RESET_PU_MASK),
-	PINCTRL_CONF_DESC(62, REG_I2C_SDA_PU, PCIE1_RESET_PU_MASK),
-	PINCTRL_CONF_DESC(63, REG_I2C_SDA_PU, PCIE2_RESET_PU_MASK),
+	PINCTRL_CONF_DESC(60, REG_I2C_SDA_PU, PCIE0_RESET_PU_MASK),
+	PINCTRL_CONF_DESC(61, REG_I2C_SDA_PU, PCIE1_RESET_PU_MASK),
+	PINCTRL_CONF_DESC(62, REG_I2C_SDA_PU, PCIE2_RESET_PU_MASK),
 };
 
 static const struct airoha_pinctrl_conf an7583_pinctrl_pullup_conf[] = {
@@ -2012,9 +2084,9 @@ static const struct airoha_pinctrl_conf en7581_pinctrl_pulldown_conf[] = {
 	PINCTRL_CONF_DESC(57, REG_GPIO_H_PD, BIT(12)),
 	PINCTRL_CONF_DESC(58, REG_GPIO_H_PD, BIT(13)),
 	PINCTRL_CONF_DESC(59, REG_GPIO_H_PD, BIT(14)),
-	PINCTRL_CONF_DESC(61, REG_I2C_SDA_PD, PCIE0_RESET_PD_MASK),
-	PINCTRL_CONF_DESC(62, REG_I2C_SDA_PD, PCIE1_RESET_PD_MASK),
-	PINCTRL_CONF_DESC(63, REG_I2C_SDA_PD, PCIE2_RESET_PD_MASK),
+	PINCTRL_CONF_DESC(60, REG_I2C_SDA_PD, PCIE0_RESET_PD_MASK),
+	PINCTRL_CONF_DESC(61, REG_I2C_SDA_PD, PCIE1_RESET_PD_MASK),
+	PINCTRL_CONF_DESC(62, REG_I2C_SDA_PD, PCIE2_RESET_PD_MASK),
 };
 
 static const struct airoha_pinctrl_conf an7583_pinctrl_pulldown_conf[] = {
@@ -2129,9 +2201,9 @@ static const struct airoha_pinctrl_conf en7581_pinctrl_drive_e2_conf[] = {
 	PINCTRL_CONF_DESC(57, REG_GPIO_H_E2, BIT(12)),
 	PINCTRL_CONF_DESC(58, REG_GPIO_H_E2, BIT(13)),
 	PINCTRL_CONF_DESC(59, REG_GPIO_H_E2, BIT(14)),
-	PINCTRL_CONF_DESC(61, REG_I2C_SDA_E2, PCIE0_RESET_E2_MASK),
-	PINCTRL_CONF_DESC(62, REG_I2C_SDA_E2, PCIE1_RESET_E2_MASK),
-	PINCTRL_CONF_DESC(63, REG_I2C_SDA_E2, PCIE2_RESET_E2_MASK),
+	PINCTRL_CONF_DESC(60, REG_I2C_SDA_E2, PCIE0_RESET_E2_MASK),
+	PINCTRL_CONF_DESC(61, REG_I2C_SDA_E2, PCIE1_RESET_E2_MASK),
+	PINCTRL_CONF_DESC(62, REG_I2C_SDA_E2, PCIE2_RESET_E2_MASK),
 };
 
 static const struct airoha_pinctrl_conf an7583_pinctrl_drive_e2_conf[] = {
@@ -2246,9 +2318,9 @@ static const struct airoha_pinctrl_conf en7581_pinctrl_drive_e4_conf[] = {
 	PINCTRL_CONF_DESC(57, REG_GPIO_H_E4, BIT(12)),
 	PINCTRL_CONF_DESC(58, REG_GPIO_H_E4, BIT(13)),
 	PINCTRL_CONF_DESC(59, REG_GPIO_H_E4, BIT(14)),
-	PINCTRL_CONF_DESC(61, REG_I2C_SDA_E4, PCIE0_RESET_E4_MASK),
-	PINCTRL_CONF_DESC(62, REG_I2C_SDA_E4, PCIE1_RESET_E4_MASK),
-	PINCTRL_CONF_DESC(63, REG_I2C_SDA_E4, PCIE2_RESET_E4_MASK),
+	PINCTRL_CONF_DESC(60, REG_I2C_SDA_E4, PCIE0_RESET_E4_MASK),
+	PINCTRL_CONF_DESC(61, REG_I2C_SDA_E4, PCIE1_RESET_E4_MASK),
+	PINCTRL_CONF_DESC(62, REG_I2C_SDA_E4, PCIE2_RESET_E4_MASK),
 };
 
 static const struct airoha_pinctrl_conf an7583_pinctrl_drive_e4_conf[] = {
@@ -2308,9 +2380,9 @@ static const struct airoha_pinctrl_conf an7583_pinctrl_drive_e4_conf[] = {
 };
 
 static const struct airoha_pinctrl_conf en7581_pinctrl_pcie_rst_od_conf[] = {
-	PINCTRL_CONF_DESC(61, REG_PCIE_RESET_OD, PCIE0_RESET_OD_MASK),
-	PINCTRL_CONF_DESC(62, REG_PCIE_RESET_OD, PCIE1_RESET_OD_MASK),
-	PINCTRL_CONF_DESC(63, REG_PCIE_RESET_OD, PCIE2_RESET_OD_MASK),
+	PINCTRL_CONF_DESC(60, REG_PCIE_RESET_OD, PCIE0_RESET_OD_MASK),
+	PINCTRL_CONF_DESC(61, REG_PCIE_RESET_OD, PCIE1_RESET_OD_MASK),
+	PINCTRL_CONF_DESC(62, REG_PCIE_RESET_OD, PCIE2_RESET_OD_MASK),
 };
 
 static const struct airoha_pinctrl_conf an7583_pinctrl_pcie_rst_od_conf[] = {
-- 
2.53.0

Re: [PATCH v7 08/34] pinctrl: airoha: an7581: fix mux/conf of pcie_reset pins

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:

New issues:
- [Low] The `AIROHA_PINCTRL_GPIO` macro is defined in the patch but is never used anywhere in the codebase.

Pre-existing issues:
- [High] The patch corrects the PCIe reset pinmux polarity for the EN7581 SoC but neglects to fix the identical issue for the AN7583 SoC, leaving its PCIe reset functionality broken.
--

--- Patch [8]: [PATCH v7 08/34] pinctrl: airoha: an7581: fix mux/conf of pcie_reset pins ---
commit a65ef4d0c5f236d794130131b423b8c2bc834683
Author: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>

pinctrl: airoha: an7581: fix mux/conf of pcie_reset pins

This commit corrects the pin numbering for PCIe reset pins on the AN7581
SoC to match the datasheet. It also fixes the pinmux configuration so that
selecting the PCIe reset function correctly enables it, rather than setting
the pins as GPIOs.

> diff --git a/drivers/pinctrl/airoha/pinctrl-airoha.c b/drivers/pinctrl/airoha/pinctrl-airoha.c
> index cad56ac3c0614..4bbda392625ad 100644
> --- a/drivers/pinctrl/airoha/pinctrl-airoha.c
> +++ b/drivers/pinctrl/airoha/pinctrl-airoha.c
[ ... ]
> @@ -1405,6 +1413,45 @@ static const struct airoha_pinctrl_func_group pnand_func_group[] = {
>  	},
>  };
>  
> +#define AIROHA_PINCTRL_GPIO(gpio, mux_val)			\
> +	{							\
> +		.name = (gpio),					\
> +		.regmap[0] = {					\
> +			AIROHA_FUNC_MUX,			\
> +			REG_GPIO_PON_MODE,			\
> +			(mux_val),				\
> +			(mux_val)				\
> +		},						\
> +		.regmap_size = 1,				\
> +	}

[Severity: Low]
Is it necessary to include AIROHA_PINCTRL_GPIO? It looks like this macro
is defined but never used anywhere in the codebase.

> +
> +#define AIROHA_PINCTRL_GPIO_EXT(gpio, mux_val, smux_val)	\
> +	{							\
> +		.name = (gpio),					\
[ ... ]
> @@ -1430,7 +1477,7 @@ static const struct airoha_pinctrl_func_group pcie_reset_func_group[] = {
>  			AIROHA_FUNC_MUX,
>  			REG_GPIO_PON_MODE,
>  			GPIO_PCIE_RESET2_MASK,
> -			GPIO_PCIE_RESET2_MASK
> +			0
>  		},
>  		.regmap_size = 1,
>  	},

[Severity: High]
This is a pre-existing issue, but by fixing the PCIe reset polarity for
the EN7581 SoC here, does the identical issue remain for the AN7583 SoC?

Looking at an7583_pcie_reset_func_group, it still configures the pins as
GPIOs rather than PCIe resets by using GPIO_PCIE_RESET0_MASK:

static const struct airoha_pinctrl_func_group an7583_pcie_reset_func_group[] = {
	{
		.name = "pcie_reset0",
		.regmap[0] = {
			AIROHA_FUNC_MUX,
			REG_GPIO_PON_MODE,
			GPIO_PCIE_RESET0_MASK,
			GPIO_PCIE_RESET0_MASK
		},
		.regmap_size = 1,
	},
...

Should an7583_pcie_reset_func_group be updated similarly to ensure PCIe
reset works correctly on the AN7583 SoC?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260727074234.3761170-1-mikhail.kshevetskiy@iopsys.eu?part=8

[PATCH v7 09/34] dt-bindings: pinctrl: airoha: en7581: allow configuration of pcie_reset pins as gpio or pwm

[Mikhail Kshevetskiy]

In the an7581 case
 * gpio47 and pcie_reset0 shares the same pin,
 * gpio48 and pcie_reset1 shares the same pin,
 * gpio49 and pcie_reset2 shares the same pin.

This patch defines a way to configure these pins as gpio or pwm.

Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
---
 .../bindings/pinctrl/airoha,en7581-pinctrl.yaml     | 13 +++++++++++--
 1 file changed, 11 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/pinctrl/airoha,en7581-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/airoha,en7581-pinctrl.yaml
index 12dd85b5b4105..1f281d3c47cba 100644
--- a/Documentation/devicetree/bindings/pinctrl/airoha,en7581-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/airoha,en7581-pinctrl.yaml
@@ -61,7 +61,7 @@ patternProperties:
             description:
               A string containing the name of the function to mux to the group.
             enum: [pon, tod_1pps, sipo, mdio, uart, i2c, jtag, pcm, spi,
-                   pcm_spi, i2s, emmc, pnand, pcie_reset, pwm, phy1_led0,
+                   pcm_spi, i2s, emmc, pnand, gpio, pcie_reset, pwm, phy1_led0,
                    phy2_led0, phy3_led0, phy4_led0, phy1_led1, phy2_led1,
                    phy3_led1, phy4_led1]
 
@@ -187,6 +187,14 @@ patternProperties:
               properties:
                 groups:
                   enum: [pnand]
+          - if:
+              properties:
+                function:
+                  const: gpio
+            then:
+              properties:
+                groups:
+                  enum: [gpio47, gpio48, gpio49]
           - if:
               properties:
                 function:
@@ -208,7 +216,8 @@ patternProperties:
                          gpio20, gpio21, gpio22, gpio23, gpio24, gpio25,
                          gpio26, gpio27, gpio28, gpio29, gpio30, gpio31,
                          gpio36, gpio37, gpio38, gpio39, gpio40, gpio41,
-                         gpio42, gpio43, gpio44, gpio45, gpio46]
+                         gpio42, gpio43, gpio44, gpio45, gpio46, gpio47,
+                         gpio48, gpio49]
           - if:
               properties:
                 function:
-- 
2.53.0

[PATCH v7 10/34] pinctrl: airoha: an7583: fix muxing of non-gpio default pins

[Mikhail Kshevetskiy]

Current an7583 pinmux implementation have following issues:
 * pins 51 and 52 can't be set as pcie_reset, current pcie_reset code
   will sets pins to gpio mode instead.
 * there is no proper way to set pins 41--54 to gpio mode.
 * pins 41--53 can't be actually set as pwm pins. These pins must be
   muxed to gpio mode as well.

This patch fixes above issues.

Fixes: 3ffeb17a9a27 ("pinctrl: airoha: add support for Airoha AN7583 PINs")
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
---
 drivers/pinctrl/airoha/pinctrl-airoha.c | 99 +++++++++++++++++++++----
 1 file changed, 86 insertions(+), 13 deletions(-)

diff --git a/drivers/pinctrl/airoha/pinctrl-airoha.c b/drivers/pinctrl/airoha/pinctrl-airoha.c
index b30b593e9dbf0..820b7b0443851 100644
--- a/drivers/pinctrl/airoha/pinctrl-airoha.c
+++ b/drivers/pinctrl/airoha/pinctrl-airoha.c
@@ -84,6 +84,18 @@
 #define GPIO_SPI_CS1_MODE_MASK			BIT(0)
 
 #define REG_GPIO_PON_MODE			0x021c
+#define AN7583_MDIO_0_GPIO_MODE_MASK		BIT(26)
+#define AN7583_MDC_0_GPIO_MODE_MASK		BIT(25)
+#define AN7583_UART_RXD_GPIO_MODE_MASK		BIT(24)
+#define AN7583_UART_TXD_GPIO_MODE_MASK		BIT(23)
+#define AN7583_SPI_MISO_GPIO_MODE_MASK		BIT(22)
+#define AN7583_SPI_MOSI_GPIO_MODE_MASK		BIT(21)
+#define AN7583_SPI_CS_GPIO_MODE_MASK		BIT(20)
+#define AN7583_SPI_CLK_GPIO_MODE_MASK		BIT(19)
+#define AN7583_I2C1_SDA_GPIO_MODE_MASK		BIT(18)
+#define AN7583_I2C1_SCL_GPIO_MODE_MASK		BIT(17)
+#define AN7583_I2C0_SDA_GPIO_MODE_MASK		BIT(16)
+#define AN7583_I2C0_SCL_GPIO_MODE_MASK		BIT(15)
 #define GPIO_PARALLEL_NAND_MODE_MASK		BIT(14)
 #define GPIO_SGMII_MDIO_MODE_MASK		BIT(13)
 #define GPIO_PCIE_RESET2_MASK			BIT(12)
@@ -782,6 +794,10 @@ static const int an7583_gpio45_pins[] = { 47 };
 static const int an7583_gpio46_pins[] = { 48 };
 static const int an7583_gpio47_pins[] = { 49 };
 static const int an7583_gpio48_pins[] = { 50 };
+static const int an7583_gpio49_pins[] = { 51 };
+static const int an7583_gpio50_pins[] = { 52 };
+static const int an7583_gpio51_pins[] = { 53 };
+static const int an7583_gpio52_pins[] = { 54 };
 static const int an7583_pcie_reset0_pins[] = { 51 };
 static const int an7583_pcie_reset1_pins[] = { 52 };
 
@@ -862,6 +878,10 @@ static const struct pingroup an7583_pinctrl_groups[] = {
 	PINCTRL_PIN_GROUP("gpio46", an7583_gpio46),
 	PINCTRL_PIN_GROUP("gpio47", an7583_gpio47),
 	PINCTRL_PIN_GROUP("gpio48", an7583_gpio48),
+	PINCTRL_PIN_GROUP("gpio49", an7583_gpio49),
+	PINCTRL_PIN_GROUP("gpio50", an7583_gpio50),
+	PINCTRL_PIN_GROUP("gpio51", an7583_gpio51),
+	PINCTRL_PIN_GROUP("gpio52", an7583_gpio52),
 	PINCTRL_PIN_GROUP("pcie_reset0", an7583_pcie_reset0),
 	PINCTRL_PIN_GROUP("pcie_reset1", an7583_pcie_reset1),
 };
@@ -891,6 +911,11 @@ static const char *const pnand_groups[] = { "pnand" };
 static const char *const gpio_groups[] = { "gpio47", "gpio48", "gpio49" };
 static const char *const pcie_reset_groups[] = { "pcie_reset0", "pcie_reset1",
 						 "pcie_reset2" };
+static const char *const an7583_gpio_groups[] = { "gpio39", "gpio40", "gpio41",
+						  "gpio42", "gpio43", "gpio44",
+						  "gpio45", "gpio46", "gpio47",
+						  "gpio48", "gpio49", "gpio50",
+						  "gpio51", "gpio52" };
 static const char *const an7583_pcie_reset_groups[] = { "pcie_reset0", "pcie_reset1" };
 static const char *const pwm_groups[] = { "gpio0", "gpio1",
 					  "gpio2", "gpio3",
@@ -937,7 +962,8 @@ static const char *const an7583_pwm_groups[] = { "gpio0", "gpio1",
 						 "gpio42", "gpio43",
 						 "gpio44", "gpio45",
 						 "gpio46", "gpio47",
-						 "gpio48" };
+						 "gpio48", "gpio49",
+						 "gpio50", "gpio51" };
 static const char *const phy1_led0_groups[] = { "gpio33", "gpio34",
 						"gpio35", "gpio42" };
 static const char *const phy2_led0_groups[] = { "gpio33", "gpio34",
@@ -1483,6 +1509,36 @@ static const struct airoha_pinctrl_func_group pcie_reset_func_group[] = {
 	},
 };
 
+static const struct airoha_pinctrl_func_group an7583_gpio_func_group[] = {
+	AIROHA_PINCTRL_GPIO_EXT("gpio39", GPIO39_FLASH_MODE_CFG,
+				AN7583_I2C0_SCL_GPIO_MODE_MASK),
+	AIROHA_PINCTRL_GPIO_EXT("gpio40", GPIO40_FLASH_MODE_CFG,
+				AN7583_I2C0_SDA_GPIO_MODE_MASK),
+	AIROHA_PINCTRL_GPIO_EXT("gpio41", GPIO41_FLASH_MODE_CFG,
+				AN7583_I2C1_SCL_GPIO_MODE_MASK),
+	AIROHA_PINCTRL_GPIO_EXT("gpio42", GPIO42_FLASH_MODE_CFG,
+				AN7583_I2C1_SDA_GPIO_MODE_MASK),
+	AIROHA_PINCTRL_GPIO_EXT("gpio43", GPIO43_FLASH_MODE_CFG,
+				AN7583_SPI_CLK_GPIO_MODE_MASK),
+	AIROHA_PINCTRL_GPIO_EXT("gpio44", GPIO44_FLASH_MODE_CFG,
+				AN7583_SPI_CS_GPIO_MODE_MASK),
+	AIROHA_PINCTRL_GPIO_EXT("gpio45", GPIO45_FLASH_MODE_CFG,
+				AN7583_SPI_MOSI_GPIO_MODE_MASK),
+	AIROHA_PINCTRL_GPIO_EXT("gpio46", GPIO46_FLASH_MODE_CFG,
+				AN7583_SPI_MISO_GPIO_MODE_MASK),
+	AIROHA_PINCTRL_GPIO_EXT("gpio47", GPIO47_FLASH_MODE_CFG,
+				AN7583_UART_TXD_GPIO_MODE_MASK),
+	AIROHA_PINCTRL_GPIO_EXT("gpio48", GPIO48_FLASH_MODE_CFG,
+				AN7583_UART_RXD_GPIO_MODE_MASK),
+	AIROHA_PINCTRL_GPIO_EXT("gpio49", GPIO49_FLASH_MODE_CFG,
+				GPIO_PCIE_RESET0_MASK),
+	AIROHA_PINCTRL_GPIO_EXT("gpio50", GPIO50_FLASH_MODE_CFG,
+				GPIO_PCIE_RESET1_MASK),
+	AIROHA_PINCTRL_GPIO_EXT("gpio51", GPIO51_FLASH_MODE_CFG,
+				AN7583_MDC_0_GPIO_MODE_MASK),
+	AIROHA_PINCTRL_GPIO("gpio52", AN7583_MDIO_0_GPIO_MODE_MASK),
+};
+
 static const struct airoha_pinctrl_func_group an7583_pcie_reset_func_group[] = {
 	{
 		.name = "pcie_reset0",
@@ -1490,7 +1546,7 @@ static const struct airoha_pinctrl_func_group an7583_pcie_reset_func_group[] = {
 			AIROHA_FUNC_MUX,
 			REG_GPIO_PON_MODE,
 			GPIO_PCIE_RESET0_MASK,
-			GPIO_PCIE_RESET0_MASK
+			0
 		},
 		.regmap_size = 1,
 	}, {
@@ -1499,7 +1555,7 @@ static const struct airoha_pinctrl_func_group an7583_pcie_reset_func_group[] = {
 			AIROHA_FUNC_MUX,
 			REG_GPIO_PON_MODE,
 			GPIO_PCIE_RESET1_MASK,
-			GPIO_PCIE_RESET1_MASK
+			0
 		},
 		.regmap_size = 1,
 	},
@@ -1636,16 +1692,32 @@ static const struct airoha_pinctrl_func_group an7583_pwm_func_group[] = {
 	AIROHA_PINCTRL_PWM_EXT("gpio36", GPIO36_FLASH_MODE_CFG),
 	AIROHA_PINCTRL_PWM_EXT("gpio37", GPIO37_FLASH_MODE_CFG),
 	AIROHA_PINCTRL_PWM_EXT("gpio38", GPIO38_FLASH_MODE_CFG),
-	AIROHA_PINCTRL_PWM_EXT("gpio39", GPIO39_FLASH_MODE_CFG),
-	AIROHA_PINCTRL_PWM_EXT("gpio40", GPIO40_FLASH_MODE_CFG),
-	AIROHA_PINCTRL_PWM_EXT("gpio41", GPIO41_FLASH_MODE_CFG),
-	AIROHA_PINCTRL_PWM_EXT("gpio42", GPIO42_FLASH_MODE_CFG),
-	AIROHA_PINCTRL_PWM_EXT("gpio43", GPIO43_FLASH_MODE_CFG),
-	AIROHA_PINCTRL_PWM_EXT("gpio44", GPIO44_FLASH_MODE_CFG),
-	AIROHA_PINCTRL_PWM_EXT("gpio45", GPIO45_FLASH_MODE_CFG),
-	AIROHA_PINCTRL_PWM_EXT("gpio46", GPIO46_FLASH_MODE_CFG),
-	AIROHA_PINCTRL_PWM_EXT("gpio47", GPIO47_FLASH_MODE_CFG),
-	AIROHA_PINCTRL_PWM_EXT("gpio48", GPIO48_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM_EXT_SEC("gpio39", GPIO39_FLASH_MODE_CFG,
+				   AN7583_I2C0_SCL_GPIO_MODE_MASK),
+	AIROHA_PINCTRL_PWM_EXT_SEC("gpio40", GPIO40_FLASH_MODE_CFG,
+				   AN7583_I2C0_SDA_GPIO_MODE_MASK),
+	AIROHA_PINCTRL_PWM_EXT_SEC("gpio41", GPIO41_FLASH_MODE_CFG,
+				   AN7583_I2C1_SCL_GPIO_MODE_MASK),
+	AIROHA_PINCTRL_PWM_EXT_SEC("gpio42", GPIO42_FLASH_MODE_CFG,
+				   AN7583_I2C1_SDA_GPIO_MODE_MASK),
+	AIROHA_PINCTRL_PWM_EXT_SEC("gpio43", GPIO43_FLASH_MODE_CFG,
+				   AN7583_SPI_CLK_GPIO_MODE_MASK),
+	AIROHA_PINCTRL_PWM_EXT_SEC("gpio44", GPIO44_FLASH_MODE_CFG,
+				   AN7583_SPI_CS_GPIO_MODE_MASK),
+	AIROHA_PINCTRL_PWM_EXT_SEC("gpio45", GPIO45_FLASH_MODE_CFG,
+				   AN7583_SPI_MOSI_GPIO_MODE_MASK),
+	AIROHA_PINCTRL_PWM_EXT_SEC("gpio46", GPIO46_FLASH_MODE_CFG,
+				   AN7583_SPI_MISO_GPIO_MODE_MASK),
+	AIROHA_PINCTRL_PWM_EXT_SEC("gpio47", GPIO47_FLASH_MODE_CFG,
+				   AN7583_UART_TXD_GPIO_MODE_MASK),
+	AIROHA_PINCTRL_PWM_EXT_SEC("gpio48", GPIO48_FLASH_MODE_CFG,
+				   AN7583_UART_RXD_GPIO_MODE_MASK),
+	AIROHA_PINCTRL_PWM_EXT_SEC("gpio49", GPIO49_FLASH_MODE_CFG,
+				   GPIO_PCIE_RESET0_MASK),
+	AIROHA_PINCTRL_PWM_EXT_SEC("gpio50", GPIO50_FLASH_MODE_CFG,
+				   GPIO_PCIE_RESET1_MASK),
+	AIROHA_PINCTRL_PWM_EXT_SEC("gpio51", GPIO51_FLASH_MODE_CFG,
+				   AN7583_MDC_0_GPIO_MODE_MASK),
 };
 
 #define AIROHA_PINCTRL_PHY_LED0(gpio, mux_val, map_mask, map_val)	\
@@ -1899,6 +1971,7 @@ static const struct airoha_pinctrl_func an7583_pinctrl_funcs[] = {
 	PINCTRL_FUNC_DESC("pcm_spi", an7583_pcm_spi),
 	PINCTRL_FUNC_DESC("emmc", emmc),
 	PINCTRL_FUNC_DESC("pnand", pnand),
+	PINCTRL_FUNC_DESC("gpio", an7583_gpio),
 	PINCTRL_FUNC_DESC("pcie_reset", an7583_pcie_reset),
 	PINCTRL_FUNC_DESC("pwm", an7583_pwm),
 	PINCTRL_FUNC_DESC("phy1_led0", an7583_phy1_led0),
-- 
2.53.0

[PATCH v7 11/34] dt-bindings: pinctrl: airoha: an7583: allow configuration of non-gpio default pins as gpio and pwm

[Mikhail Kshevetskiy]

Some AN7583 pins have non-gpio default settings. This patch provides a way
to configure such pins as GPIO or PWM.

Please note that gpio52 pin can't be configured as PWM pin.

Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
---
 .../bindings/pinctrl/airoha,an7583-pinctrl.yaml    | 14 ++++++++++++--
 1 file changed, 12 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/pinctrl/airoha,an7583-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/airoha,an7583-pinctrl.yaml
index 8d8ec6adb97d1..bedcb6374f1a0 100644
--- a/Documentation/devicetree/bindings/pinctrl/airoha,an7583-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/airoha,an7583-pinctrl.yaml
@@ -61,7 +61,7 @@ patternProperties:
             description:
               A string containing the name of the function to mux to the group.
             enum: [pon, tod_1pps, sipo, mdio, uart, jtag, pcm, spi,
-                   pcm_spi, emmc, pnand, pcie_reset, pwm, phy1_led0,
+                   pcm_spi, emmc, pnand, gpio, pcie_reset, pwm, phy1_led0,
                    phy2_led0, phy3_led0, phy4_led0, phy1_led1, phy2_led1,
                    phy3_led1, phy4_led1]
 
@@ -169,6 +169,16 @@ patternProperties:
               properties:
                 groups:
                   enum: [pnand]
+          - if:
+              properties:
+                function:
+                  const: gpio
+            then:
+              properties:
+                groups:
+                  enum: [gpio39, gpio40, gpio41, gpio42, gpio43, gpio44,
+                         gpio45, gpio46, gpio47, gpio48, gpio49, gpio50,
+                         gpio51, gpio52]
           - if:
               properties:
                 function:
@@ -191,7 +201,7 @@ patternProperties:
                          gpio26, gpio27, gpio28, gpio29, gpio30, gpio31,
                          gpio36, gpio37, gpio38, gpio39, gpio40, gpio41,
                          gpio42, gpio43, gpio44, gpio45, gpio46, gpio47,
-                         gpio48]
+                         gpio48, gpio49, gpio50, gpio51]
           - if:
               properties:
                 function:
-- 
2.53.0

[PATCH v7 12/34] pinctrl: airoha: add missed get_direction() function for gpio_chip

[Mikhail Kshevetskiy]

This patch adds missed get_direction() function for gpio_chip.
Also it reimplements pinconf's get_direction() function using
newly defined function.

Fixes: 1c8ace2d0725 ("pinctrl: airoha: Add support for EN7581 SoC")
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
---
 drivers/pinctrl/airoha/pinctrl-airoha.c | 41 ++++++++++++++++++-------
 1 file changed, 30 insertions(+), 11 deletions(-)

diff --git a/drivers/pinctrl/airoha/pinctrl-airoha.c b/drivers/pinctrl/airoha/pinctrl-airoha.c
index 820b7b0443851..b52eb39c55ff3 100644
--- a/drivers/pinctrl/airoha/pinctrl-airoha.c
+++ b/drivers/pinctrl/airoha/pinctrl-airoha.c
@@ -2502,6 +2502,27 @@ static int airoha_gpio_get(struct gpio_chip *chip, unsigned int gpio)
 	return err ? err : !!(val & BIT(pin));
 }
 
+static int airoha_gpio_get_direction(struct gpio_chip *chip, unsigned int gpio)
+{
+	struct airoha_pinctrl *pinctrl = gpiochip_get_data(chip);
+	u32 mask, index, val;
+	int err, field_shift;
+
+	field_shift = 2 * (gpio % AIROHA_REG_GPIOCTRL_NUM_PIN);
+	mask = GENMASK(field_shift + 1, field_shift);
+	index = gpio / AIROHA_REG_GPIOCTRL_NUM_PIN;
+
+	err = regmap_read(pinctrl->regmap,
+			  pinctrl->gpiochip.dir[index], &val);
+	if (err)
+		return err;
+
+	if ((val & mask) > BIT(field_shift))
+		return -EINVAL;
+
+	return (val & mask) ? GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN;
+}
+
 static int airoha_gpio_direction_output(struct gpio_chip *chip,
 					unsigned int gpio, int value)
 {
@@ -2648,6 +2669,7 @@ static int airoha_pinctrl_add_gpiochip(struct airoha_pinctrl *pinctrl,
 	gc->free = gpiochip_generic_free;
 	gc->direction_input = pinctrl_gpio_direction_input;
 	gc->direction_output = airoha_gpio_direction_output;
+	gc->get_direction = airoha_gpio_get_direction;
 	gc->set = airoha_gpio_set;
 	gc->get = airoha_gpio_get;
 	gc->base = -1;
@@ -2855,21 +2877,18 @@ static int airoha_pinctrl_set_conf(struct airoha_pinctrl *pinctrl,
 static int airoha_pinconf_get_direction(struct pinctrl_dev *pctrl_dev, u32 p)
 {
 	struct airoha_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
-	u32 val, mask;
-	int err, pin;
-	u8 index;
+	int err, gpio;
 
-	pin = airoha_convert_pin_to_reg_offset(pctrl_dev, NULL, p);
-	if (pin < 0)
-		return pin;
+	gpio = airoha_convert_pin_to_reg_offset(pctrl_dev, NULL, p);
+	if (gpio < 0)
+		return gpio;
 
-	index = pin / AIROHA_REG_GPIOCTRL_NUM_PIN;
-	err = regmap_read(pinctrl->regmap, pinctrl->gpiochip.dir[index], &val);
-	if (err)
+	err = airoha_gpio_get_direction(&pinctrl->gpiochip.chip, gpio);
+	if (err < 0)
 		return err;
 
-	mask = BIT(2 * (pin % AIROHA_REG_GPIOCTRL_NUM_PIN));
-	return val & mask ? PIN_CONFIG_OUTPUT_ENABLE : PIN_CONFIG_INPUT_ENABLE;
+	return err == GPIO_LINE_DIRECTION_OUT ?
+	       PIN_CONFIG_OUTPUT_ENABLE : PIN_CONFIG_INPUT_ENABLE;
 }
 
 static int airoha_pinconf_get(struct pinctrl_dev *pctrl_dev,
-- 
2.53.0

Re: [PATCH v7 12/34] pinctrl: airoha: add missed get_direction() function for gpio_chip

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] The newly added `airoha_gpio_get_direction` strictly checks a 2-bit direction field, but the existing `airoha_pinmux_set_direction` only updates a 1-bit mask, causing `get_direction` to return `-EINVAL`.
--

--- Patch [12]: [PATCH v7 12/34] pinctrl: airoha: add missed get_direction() function for gpio_chip ---
commit d5d33bb49ecef808432dc746e944b058a238f703
Author: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>

pinctrl: airoha: add missed get_direction() function for gpio_chip

This patch adds a missing get_direction function for the airoha gpio_chip.
It also updates pinconf to use this new function.

> diff --git a/drivers/pinctrl/airoha/pinctrl-airoha.c b/drivers/pinctrl/airoha/pinctrl-airoha.c
> index 4dae8c654f995..6a0ba54053fe7 100644
> --- a/drivers/pinctrl/airoha/pinctrl-airoha.c
> +++ b/drivers/pinctrl/airoha/pinctrl-airoha.c
[ ... ]
> @@ -2502,6 +2502,27 @@ static int airoha_gpio_get(struct gpio_chip *chip, unsigned int gpio)
>  	return err ? err : !!(val & BIT(pin));
>  }
>  
> +static int airoha_gpio_get_direction(struct gpio_chip *chip, unsigned int gpio)
> +{
> +	struct airoha_pinctrl *pinctrl = gpiochip_get_data(chip);
> +	u32 mask, index, val;
> +	int err, field_shift;
> +
> +	field_shift = 2 * (gpio % AIROHA_REG_GPIOCTRL_NUM_PIN);
> +	mask = GENMASK(field_shift + 1, field_shift);
> +	index = gpio / AIROHA_REG_GPIOCTRL_NUM_PIN;
> +
> +	err = regmap_read(pinctrl->regmap,
> +			  pinctrl->gpiochip.dir[index], &val);
> +	if (err)
> +		return err;
> +
> +	if ((val & mask) > BIT(field_shift))
> +		return -EINVAL;

[Severity: High]
Will this strict 2-bit check cause get_direction to permanently fail for pins 
configured with the upper bit set by the bootloader or hardware?

Looking at airoha_pinmux_set_direction() in the same file, it only uses a
1-bit mask when setting the direction:

drivers/pinctrl/airoha/pinctrl-airoha.c:airoha_pinmux_set_direction() {
    ...
    /* set direction */
    mask = BIT(2 * (pin % AIROHA_REG_GPIOCTRL_NUM_PIN));
    index = pin / AIROHA_REG_GPIOCTRL_NUM_PIN;
    return regmap_update_bits(pinctrl->regmap,
                              pinctrl->gpiochip.dir[index], mask,
                              !input ? mask : 0);
}

If the hardware or bootloader initially sets the upper direction bit for a
pin, setting the direction via airoha_pinmux_set_direction() will only
update the lower bit. When airoha_gpio_get_direction() is called later,
the upper bit will still be set. The expression (val & mask) would then be
greater than BIT(field_shift), causing it to return -EINVAL unconditionally.

Does airoha_pinmux_set_direction() need to be updated to clear the upper
bit, or should this newly added get_direction logic be more lenient?

> +
> +	return (val & mask) ? GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN;
> +}

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260727074234.3761170-1-mikhail.kshevetskiy@iopsys.eu?part=12

Re: [PATCH v7 12/34] pinctrl: airoha: add missed get_direction() function for gpio_chip

[Lorenzo Bianconi]

[-- Attachment #1: Type: text/plain, Size: 3348 bytes --]

> This patch adds missed get_direction() function for gpio_chip.
> Also it reimplements pinconf's get_direction() function using
> newly defined function.
> 
> Fixes: 1c8ace2d0725 ("pinctrl: airoha: Add support for EN7581 SoC")
> Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
> ---
>  drivers/pinctrl/airoha/pinctrl-airoha.c | 41 ++++++++++++++++++-------
>  1 file changed, 30 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/pinctrl/airoha/pinctrl-airoha.c b/drivers/pinctrl/airoha/pinctrl-airoha.c
> index 820b7b0443851..b52eb39c55ff3 100644
> --- a/drivers/pinctrl/airoha/pinctrl-airoha.c
> +++ b/drivers/pinctrl/airoha/pinctrl-airoha.c
> @@ -2502,6 +2502,27 @@ static int airoha_gpio_get(struct gpio_chip *chip, unsigned int gpio)
>  	return err ? err : !!(val & BIT(pin));
>  }
>  
> +static int airoha_gpio_get_direction(struct gpio_chip *chip, unsigned int gpio)
> +{
> +	struct airoha_pinctrl *pinctrl = gpiochip_get_data(chip);
> +	u32 mask, index, val;
> +	int err, field_shift;
> +
> +	field_shift = 2 * (gpio % AIROHA_REG_GPIOCTRL_NUM_PIN);
> +	mask = GENMASK(field_shift + 1, field_shift);

before we where checking just BIT(field_shift) as mask, while now we are
checking two bits.

> +	index = gpio / AIROHA_REG_GPIOCTRL_NUM_PIN;
> +
> +	err = regmap_read(pinctrl->regmap,
> +			  pinctrl->gpiochip.dir[index], &val);
> +	if (err)
> +		return err;
> +
> +	if ((val & mask) > BIT(field_shift))
> +		return -EINVAL;
> +
> +	return (val & mask) ? GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN;

nit: unnecessary brackets.

> +}
> +
>  static int airoha_gpio_direction_output(struct gpio_chip *chip,
>  					unsigned int gpio, int value)
>  {
> @@ -2648,6 +2669,7 @@ static int airoha_pinctrl_add_gpiochip(struct airoha_pinctrl *pinctrl,
>  	gc->free = gpiochip_generic_free;
>  	gc->direction_input = pinctrl_gpio_direction_input;
>  	gc->direction_output = airoha_gpio_direction_output;
> +	gc->get_direction = airoha_gpio_get_direction;
>  	gc->set = airoha_gpio_set;
>  	gc->get = airoha_gpio_get;
>  	gc->base = -1;
> @@ -2855,21 +2877,18 @@ static int airoha_pinctrl_set_conf(struct airoha_pinctrl *pinctrl,
>  static int airoha_pinconf_get_direction(struct pinctrl_dev *pctrl_dev, u32 p)
>  {
>  	struct airoha_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
> -	u32 val, mask;
> -	int err, pin;
> -	u8 index;
> +	int err, gpio;
>  
> -	pin = airoha_convert_pin_to_reg_offset(pctrl_dev, NULL, p);
> -	if (pin < 0)
> -		return pin;
> +	gpio = airoha_convert_pin_to_reg_offset(pctrl_dev, NULL, p);

if you do not rename pin in gpio here the patch will be simpler.

Regards,
Lorenzo

> +	if (gpio < 0)
> +		return gpio;
>  
> -	index = pin / AIROHA_REG_GPIOCTRL_NUM_PIN;
> -	err = regmap_read(pinctrl->regmap, pinctrl->gpiochip.dir[index], &val);
> -	if (err)
> +	err = airoha_gpio_get_direction(&pinctrl->gpiochip.chip, gpio);
> +	if (err < 0)
>  		return err;
>  
> -	mask = BIT(2 * (pin % AIROHA_REG_GPIOCTRL_NUM_PIN));
> -	return val & mask ? PIN_CONFIG_OUTPUT_ENABLE : PIN_CONFIG_INPUT_ENABLE;
> +	return err == GPIO_LINE_DIRECTION_OUT ?
> +	       PIN_CONFIG_OUTPUT_ENABLE : PIN_CONFIG_INPUT_ENABLE;
>  }
>  
>  static int airoha_pinconf_get(struct pinctrl_dev *pctrl_dev,
> -- 
> 2.53.0
> 

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]

Re: [PATCH v7 12/34] pinctrl: airoha: add missed get_direction() function for gpio_chip

[Mikhail Kshevetskiy]

On 7/27/26 11:04, Lorenzo Bianconi wrote:
>> This patch adds missed get_direction() function for gpio_chip.
>> Also it reimplements pinconf's get_direction() function using
>> newly defined function.
>>
>> Fixes: 1c8ace2d0725 ("pinctrl: airoha: Add support for EN7581 SoC")
>> Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
>> ---
>>  drivers/pinctrl/airoha/pinctrl-airoha.c | 41 ++++++++++++++++++-------
>>  1 file changed, 30 insertions(+), 11 deletions(-)
>>
>> diff --git a/drivers/pinctrl/airoha/pinctrl-airoha.c b/drivers/pinctrl/airoha/pinctrl-airoha.c
>> index 820b7b0443851..b52eb39c55ff3 100644
>> --- a/drivers/pinctrl/airoha/pinctrl-airoha.c
>> +++ b/drivers/pinctrl/airoha/pinctrl-airoha.c
>> @@ -2502,6 +2502,27 @@ static int airoha_gpio_get(struct gpio_chip *chip, unsigned int gpio)
>>  	return err ? err : !!(val & BIT(pin));
>>  }
>>  
>> +static int airoha_gpio_get_direction(struct gpio_chip *chip, unsigned int gpio)
>> +{
>> +	struct airoha_pinctrl *pinctrl = gpiochip_get_data(chip);
>> +	u32 mask, index, val;
>> +	int err, field_shift;
>> +
>> +	field_shift = 2 * (gpio % AIROHA_REG_GPIOCTRL_NUM_PIN);
>> +	mask = GENMASK(field_shift + 1, field_shift);
> before we where checking just BIT(field_shift) as mask, while now we are
> checking two bits. 
As I know upper bits treated as reserved. I think we should not use gpio
operations if upper bit is not zero.
What is your opinion?
>  
>
>> +	index = gpio / AIROHA_REG_GPIOCTRL_NUM_PIN;
>> +
>> +	err = regmap_read(pinctrl->regmap,
>> +			  pinctrl->gpiochip.dir[index], &val);
>> +	if (err)
>> +		return err;
>> +
>> +	if ((val & mask) > BIT(field_shift))
>> +		return -EINVAL;
>> +
>> +	return (val & mask) ? GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN;
> nit: unnecessary brackets.
>
>> +}
>> +
>>  static int airoha_gpio_direction_output(struct gpio_chip *chip,
>>  					unsigned int gpio, int value)
>>  {
>> @@ -2648,6 +2669,7 @@ static int airoha_pinctrl_add_gpiochip(struct airoha_pinctrl *pinctrl,
>>  	gc->free = gpiochip_generic_free;
>>  	gc->direction_input = pinctrl_gpio_direction_input;
>>  	gc->direction_output = airoha_gpio_direction_output;
>> +	gc->get_direction = airoha_gpio_get_direction;
>>  	gc->set = airoha_gpio_set;
>>  	gc->get = airoha_gpio_get;
>>  	gc->base = -1;
>> @@ -2855,21 +2877,18 @@ static int airoha_pinctrl_set_conf(struct airoha_pinctrl *pinctrl,
>>  static int airoha_pinconf_get_direction(struct pinctrl_dev *pctrl_dev, u32 p)
>>  {
>>  	struct airoha_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
>> -	u32 val, mask;
>> -	int err, pin;
>> -	u8 index;
>> +	int err, gpio;
>>  
>> -	pin = airoha_convert_pin_to_reg_offset(pctrl_dev, NULL, p);
>> -	if (pin < 0)
>> -		return pin;
>> +	gpio = airoha_convert_pin_to_reg_offset(pctrl_dev, NULL, p);
> if you do not rename pin in gpio here the patch will be simpler.
>
> Regards,
> Lorenzo
>
>> +	if (gpio < 0)
>> +		return gpio;
>>  
>> -	index = pin / AIROHA_REG_GPIOCTRL_NUM_PIN;
>> -	err = regmap_read(pinctrl->regmap, pinctrl->gpiochip.dir[index], &val);
>> -	if (err)
>> +	err = airoha_gpio_get_direction(&pinctrl->gpiochip.chip, gpio);
>> +	if (err < 0)
>>  		return err;
>>  
>> -	mask = BIT(2 * (pin % AIROHA_REG_GPIOCTRL_NUM_PIN));
>> -	return val & mask ? PIN_CONFIG_OUTPUT_ENABLE : PIN_CONFIG_INPUT_ENABLE;
>> +	return err == GPIO_LINE_DIRECTION_OUT ?
>> +	       PIN_CONFIG_OUTPUT_ENABLE : PIN_CONFIG_INPUT_ENABLE;
>>  }
>>  
>>  static int airoha_pinconf_get(struct pinctrl_dev *pctrl_dev,
>> -- 
>> 2.53.0
>>

Re: [PATCH v7 12/34] pinctrl: airoha: add missed get_direction() function for gpio_chip

[Lorenzo Bianconi]

[-- Attachment #1: Type: text/plain, Size: 3940 bytes --]

On Jul 27, Mikhail Kshevetskiy wrote:
> On 7/27/26 11:04, Lorenzo Bianconi wrote:
> >> This patch adds missed get_direction() function for gpio_chip.
> >> Also it reimplements pinconf's get_direction() function using
> >> newly defined function.
> >>
> >> Fixes: 1c8ace2d0725 ("pinctrl: airoha: Add support for EN7581 SoC")
> >> Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
> >> ---
> >>  drivers/pinctrl/airoha/pinctrl-airoha.c | 41 ++++++++++++++++++-------
> >>  1 file changed, 30 insertions(+), 11 deletions(-)
> >>
> >> diff --git a/drivers/pinctrl/airoha/pinctrl-airoha.c b/drivers/pinctrl/airoha/pinctrl-airoha.c
> >> index 820b7b0443851..b52eb39c55ff3 100644
> >> --- a/drivers/pinctrl/airoha/pinctrl-airoha.c
> >> +++ b/drivers/pinctrl/airoha/pinctrl-airoha.c
> >> @@ -2502,6 +2502,27 @@ static int airoha_gpio_get(struct gpio_chip *chip, unsigned int gpio)
> >>  	return err ? err : !!(val & BIT(pin));
> >>  }
> >>  
> >> +static int airoha_gpio_get_direction(struct gpio_chip *chip, unsigned int gpio)
> >> +{
> >> +	struct airoha_pinctrl *pinctrl = gpiochip_get_data(chip);
> >> +	u32 mask, index, val;
> >> +	int err, field_shift;
> >> +
> >> +	field_shift = 2 * (gpio % AIROHA_REG_GPIOCTRL_NUM_PIN);
> >> +	mask = GENMASK(field_shift + 1, field_shift);
> > before we where checking just BIT(field_shift) as mask, while now we are
> > checking two bits. 
> As I know upper bits treated as reserved. I think we should not use gpio
> operations if upper bit is not zero.
> What is your opinion?

I guess it is better to use a mask of just one bit here.

Regards,
Lorenzo

> >  
> >
> >> +	index = gpio / AIROHA_REG_GPIOCTRL_NUM_PIN;
> >> +
> >> +	err = regmap_read(pinctrl->regmap,
> >> +			  pinctrl->gpiochip.dir[index], &val);
> >> +	if (err)
> >> +		return err;
> >> +
> >> +	if ((val & mask) > BIT(field_shift))
> >> +		return -EINVAL;
> >> +
> >> +	return (val & mask) ? GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN;
> > nit: unnecessary brackets.
> >
> >> +}
> >> +
> >>  static int airoha_gpio_direction_output(struct gpio_chip *chip,
> >>  					unsigned int gpio, int value)
> >>  {
> >> @@ -2648,6 +2669,7 @@ static int airoha_pinctrl_add_gpiochip(struct airoha_pinctrl *pinctrl,
> >>  	gc->free = gpiochip_generic_free;
> >>  	gc->direction_input = pinctrl_gpio_direction_input;
> >>  	gc->direction_output = airoha_gpio_direction_output;
> >> +	gc->get_direction = airoha_gpio_get_direction;
> >>  	gc->set = airoha_gpio_set;
> >>  	gc->get = airoha_gpio_get;
> >>  	gc->base = -1;
> >> @@ -2855,21 +2877,18 @@ static int airoha_pinctrl_set_conf(struct airoha_pinctrl *pinctrl,
> >>  static int airoha_pinconf_get_direction(struct pinctrl_dev *pctrl_dev, u32 p)
> >>  {
> >>  	struct airoha_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
> >> -	u32 val, mask;
> >> -	int err, pin;
> >> -	u8 index;
> >> +	int err, gpio;
> >>  
> >> -	pin = airoha_convert_pin_to_reg_offset(pctrl_dev, NULL, p);
> >> -	if (pin < 0)
> >> -		return pin;
> >> +	gpio = airoha_convert_pin_to_reg_offset(pctrl_dev, NULL, p);
> > if you do not rename pin in gpio here the patch will be simpler.
> >
> > Regards,
> > Lorenzo
> >
> >> +	if (gpio < 0)
> >> +		return gpio;
> >>  
> >> -	index = pin / AIROHA_REG_GPIOCTRL_NUM_PIN;
> >> -	err = regmap_read(pinctrl->regmap, pinctrl->gpiochip.dir[index], &val);
> >> -	if (err)
> >> +	err = airoha_gpio_get_direction(&pinctrl->gpiochip.chip, gpio);
> >> +	if (err < 0)
> >>  		return err;
> >>  
> >> -	mask = BIT(2 * (pin % AIROHA_REG_GPIOCTRL_NUM_PIN));
> >> -	return val & mask ? PIN_CONFIG_OUTPUT_ENABLE : PIN_CONFIG_INPUT_ENABLE;
> >> +	return err == GPIO_LINE_DIRECTION_OUT ?
> >> +	       PIN_CONFIG_OUTPUT_ENABLE : PIN_CONFIG_INPUT_ENABLE;
> >>  }
> >>  
> >>  static int airoha_pinconf_get(struct pinctrl_dev *pctrl_dev,
> >> -- 
> >> 2.53.0
> >>

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]

[PATCH v7 13/34] pinctrl: airoha: add set_direction() helper for gpio_chip

[Mikhail Kshevetskiy]

The patch creates set_direction() helper for gpio_chip abstraction.
It also implements/reimplements some function using newly defined
helper.

This is cosmetic patch used to place gpio_chip specific code together.
No functional changes.

Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
---
 drivers/pinctrl/airoha/pinctrl-airoha.c | 59 ++++++++++++++++---------
 1 file changed, 38 insertions(+), 21 deletions(-)

diff --git a/drivers/pinctrl/airoha/pinctrl-airoha.c b/drivers/pinctrl/airoha/pinctrl-airoha.c
index b52eb39c55ff3..faad5d3ada31c 100644
--- a/drivers/pinctrl/airoha/pinctrl-airoha.c
+++ b/drivers/pinctrl/airoha/pinctrl-airoha.c
@@ -2523,12 +2523,43 @@ static int airoha_gpio_get_direction(struct gpio_chip *chip, unsigned int gpio)
 	return (val & mask) ? GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN;
 }
 
+static int airoha_gpio_set_direction(struct gpio_chip *chip, unsigned int gpio,
+				     bool input)
+{
+	struct airoha_pinctrl *pinctrl = gpiochip_get_data(chip);
+	u32 mask, index;
+	int err, field_shift;
+
+	/* set output enable */
+	mask = BIT(gpio % AIROHA_PIN_BANK_SIZE);
+	index = gpio / AIROHA_PIN_BANK_SIZE;
+	err = regmap_update_bits(pinctrl->regmap, pinctrl->gpiochip.out[index],
+				 mask, !input ? mask : 0);
+	if (err)
+		return err;
+
+	/* set direction */
+	field_shift = 2 * (gpio % AIROHA_REG_GPIOCTRL_NUM_PIN);
+	mask = GENMASK(field_shift + 1, field_shift);
+	index = gpio / AIROHA_REG_GPIOCTRL_NUM_PIN;
+
+	return regmap_update_bits(pinctrl->regmap,
+				  pinctrl->gpiochip.dir[index],
+				  mask, !input ? BIT(field_shift) : 0);
+}
+
+static int airoha_gpio_direction_input(struct gpio_chip *chip,
+				       unsigned int gpio)
+{
+	return airoha_gpio_set_direction(chip, gpio, true);
+}
+
 static int airoha_gpio_direction_output(struct gpio_chip *chip,
 					unsigned int gpio, int value)
 {
 	int err;
 
-	err = pinctrl_gpio_direction_output(chip, gpio);
+	err = airoha_gpio_set_direction(chip, gpio, false);
 	if (err)
 		return err;
 
@@ -2667,7 +2698,7 @@ static int airoha_pinctrl_add_gpiochip(struct airoha_pinctrl *pinctrl,
 	gc->label = dev_name(dev);
 	gc->request = gpiochip_generic_request;
 	gc->free = gpiochip_generic_free;
-	gc->direction_input = pinctrl_gpio_direction_input;
+	gc->direction_input = airoha_gpio_direction_input;
 	gc->direction_output = airoha_gpio_direction_output;
 	gc->get_direction = airoha_gpio_get_direction;
 	gc->set = airoha_gpio_set;
@@ -2750,27 +2781,13 @@ static int airoha_pinmux_set_direction(struct pinctrl_dev *pctrl_dev,
 					unsigned int p, bool input)
 {
 	struct airoha_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
-	u32 mask, index;
-	int err, pin;
+	int gpio;
 
-	pin = airoha_convert_pin_to_reg_offset(pctrl_dev, range, p);
-	if (pin < 0)
-		return pin;
-
-	/* set output enable */
-	mask = BIT(pin % AIROHA_PIN_BANK_SIZE);
-	index = pin / AIROHA_PIN_BANK_SIZE;
-	err = regmap_update_bits(pinctrl->regmap, pinctrl->gpiochip.out[index],
-				 mask, !input ? mask : 0);
-	if (err)
-		return err;
+	gpio = airoha_convert_pin_to_reg_offset(pctrl_dev, range, p);
+	if (gpio < 0)
+		return gpio;
 
-	/* set direction */
-	mask = BIT(2 * (pin % AIROHA_REG_GPIOCTRL_NUM_PIN));
-	index = pin / AIROHA_REG_GPIOCTRL_NUM_PIN;
-	return regmap_update_bits(pinctrl->regmap,
-				  pinctrl->gpiochip.dir[index], mask,
-				  !input ? mask : 0);
+	return airoha_gpio_set_direction(&pinctrl->gpiochip.chip, gpio, input);
 }
 
 static const struct pinmux_ops airoha_pmxops = {
-- 
2.53.0

Re: [PATCH v7 13/34] pinctrl: airoha: add set_direction() helper for gpio_chip

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] Unintended modification of adjacent bits in the GPIO direction register due to incorrect mask size, violating the 'No functional changes' claim.
--

--- Patch [13]: [PATCH v7 13/34] pinctrl: airoha: add set_direction() helper for gpio_chip ---
commit e729e6b2ed1ea68da146d1ea646d1135a1f27b5e
Author: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>

pinctrl: airoha: add set_direction() helper for gpio_chip
    
The patch creates a set_direction() helper for the gpio_chip abstraction and
reimplements existing direction configuration to use this helper. The commit
message claims this is purely a cosmetic patch with no functional changes.

> diff --git a/drivers/pinctrl/airoha/pinctrl-airoha.c b/drivers/pinctrl/airoha/pinctrl-airoha.c
> index 6a0ba54053fe7..fcf498f7720c9 100644
> --- a/drivers/pinctrl/airoha/pinctrl-airoha.c
> +++ b/drivers/pinctrl/airoha/pinctrl-airoha.c
[ ... ]
> @@ -2523,12 +2523,43 @@ static int airoha_gpio_get_direction(struct gpio_chip *chip, unsigned int gpio)
[ ... ]
> +static int airoha_gpio_set_direction(struct gpio_chip *chip, unsigned int gpio,
> +				     bool input)
> +{
[ ... ]
> +	/* set direction */
> +	field_shift = 2 * (gpio % AIROHA_REG_GPIOCTRL_NUM_PIN);
> +	mask = GENMASK(field_shift + 1, field_shift);
> +	index = gpio / AIROHA_REG_GPIOCTRL_NUM_PIN;
> +
> +	return regmap_update_bits(pinctrl->regmap,
> +				  pinctrl->gpiochip.dir[index],
> +				  mask, !input ? BIT(field_shift) : 0);
> +}

[Severity: Medium]
Does this new helper introduce a functional change contrary to the commit
message?

In the removed airoha_pinmux_set_direction() code shown below, the mask
covered exactly 1 bit:

    mask = BIT(2 * (pin % AIROHA_REG_GPIOCTRL_NUM_PIN));

Here in the new airoha_gpio_set_direction(), the mask spans 2 bits via
GENMASK(field_shift + 1, field_shift). The regmap_update_bits() call now
explicitly clears the upper bit of this 2-bit field.

Could this zeroing of the upper bit, which was previously preserved,
alter undocumented hardware state?

[ ... ]
> @@ -2752,27 +2783,13 @@ static int airoha_pinmux_set_direction(struct pinctrl_dev *pctrl_dev,
[ ... ]
> -	/* set direction */
> -	mask = BIT(2 * (pin % AIROHA_REG_GPIOCTRL_NUM_PIN));
> -	index = pin / AIROHA_REG_GPIOCTRL_NUM_PIN;
> -	return regmap_update_bits(pinctrl->regmap,
> -				  pinctrl->gpiochip.dir[index], mask,
> -				  !input ? mask : 0);
> +	return airoha_gpio_set_direction(&pinctrl->gpiochip.chip, gpio, input);
>  }

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260727074234.3761170-1-mikhail.kshevetskiy@iopsys.eu?part=13

Re: [PATCH v7 13/34] pinctrl: airoha: add set_direction() helper for gpio_chip

[Lorenzo Bianconi]

[-- Attachment #1: Type: text/plain, Size: 3970 bytes --]

> The patch creates set_direction() helper for gpio_chip abstraction.
> It also implements/reimplements some function using newly defined
> helper.
> 
> This is cosmetic patch used to place gpio_chip specific code together.
> No functional changes.
> 
> Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
> ---
>  drivers/pinctrl/airoha/pinctrl-airoha.c | 59 ++++++++++++++++---------
>  1 file changed, 38 insertions(+), 21 deletions(-)
> 
> diff --git a/drivers/pinctrl/airoha/pinctrl-airoha.c b/drivers/pinctrl/airoha/pinctrl-airoha.c
> index b52eb39c55ff3..faad5d3ada31c 100644
> --- a/drivers/pinctrl/airoha/pinctrl-airoha.c
> +++ b/drivers/pinctrl/airoha/pinctrl-airoha.c
> @@ -2523,12 +2523,43 @@ static int airoha_gpio_get_direction(struct gpio_chip *chip, unsigned int gpio)
>  	return (val & mask) ? GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN;
>  }
>  
> +static int airoha_gpio_set_direction(struct gpio_chip *chip, unsigned int gpio,
> +				     bool input)
> +{
> +	struct airoha_pinctrl *pinctrl = gpiochip_get_data(chip);
> +	u32 mask, index;
> +	int err, field_shift;
> +
> +	/* set output enable */
> +	mask = BIT(gpio % AIROHA_PIN_BANK_SIZE);
> +	index = gpio / AIROHA_PIN_BANK_SIZE;
> +	err = regmap_update_bits(pinctrl->regmap, pinctrl->gpiochip.out[index],
> +				 mask, !input ? mask : 0);
> +	if (err)
> +		return err;
> +
> +	/* set direction */
> +	field_shift = 2 * (gpio % AIROHA_REG_GPIOCTRL_NUM_PIN);
> +	mask = GENMASK(field_shift + 1, field_shift);

same here, why using 2 bits as mask?

> +	index = gpio / AIROHA_REG_GPIOCTRL_NUM_PIN;
> +
> +	return regmap_update_bits(pinctrl->regmap,
> +				  pinctrl->gpiochip.dir[index],
> +				  mask, !input ? BIT(field_shift) : 0);
> +}
> +
> +static int airoha_gpio_direction_input(struct gpio_chip *chip,
> +				       unsigned int gpio)
> +{
> +	return airoha_gpio_set_direction(chip, gpio, true);
> +}
> +
>  static int airoha_gpio_direction_output(struct gpio_chip *chip,
>  					unsigned int gpio, int value)
>  {
>  	int err;
>  
> -	err = pinctrl_gpio_direction_output(chip, gpio);
> +	err = airoha_gpio_set_direction(chip, gpio, false);
>  	if (err)
>  		return err;
>  
> @@ -2667,7 +2698,7 @@ static int airoha_pinctrl_add_gpiochip(struct airoha_pinctrl *pinctrl,
>  	gc->label = dev_name(dev);
>  	gc->request = gpiochip_generic_request;
>  	gc->free = gpiochip_generic_free;
> -	gc->direction_input = pinctrl_gpio_direction_input;
> +	gc->direction_input = airoha_gpio_direction_input;
>  	gc->direction_output = airoha_gpio_direction_output;
>  	gc->get_direction = airoha_gpio_get_direction;
>  	gc->set = airoha_gpio_set;
> @@ -2750,27 +2781,13 @@ static int airoha_pinmux_set_direction(struct pinctrl_dev *pctrl_dev,
>  					unsigned int p, bool input)
>  {
>  	struct airoha_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
> -	u32 mask, index;
> -	int err, pin;
> +	int gpio;
>  
> -	pin = airoha_convert_pin_to_reg_offset(pctrl_dev, range, p);
> -	if (pin < 0)
> -		return pin;
> -
> -	/* set output enable */
> -	mask = BIT(pin % AIROHA_PIN_BANK_SIZE);
> -	index = pin / AIROHA_PIN_BANK_SIZE;
> -	err = regmap_update_bits(pinctrl->regmap, pinctrl->gpiochip.out[index],
> -				 mask, !input ? mask : 0);
> -	if (err)
> -		return err;
> +	gpio = airoha_convert_pin_to_reg_offset(pctrl_dev, range, p);

same here, if you do not rename pin in gpio the patch will be simpler.

Regards,
Lorenzo

> +	if (gpio < 0)
> +		return gpio;
>  
> -	/* set direction */
> -	mask = BIT(2 * (pin % AIROHA_REG_GPIOCTRL_NUM_PIN));
> -	index = pin / AIROHA_REG_GPIOCTRL_NUM_PIN;
> -	return regmap_update_bits(pinctrl->regmap,
> -				  pinctrl->gpiochip.dir[index], mask,
> -				  !input ? mask : 0);
> +	return airoha_gpio_set_direction(&pinctrl->gpiochip.chip, gpio, input);
>  }
>  
>  static const struct pinmux_ops airoha_pmxops = {
> -- 
> 2.53.0
> 

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]

[PATCH v7 14/34] pinctrl: airoha: fix potential kenel panic in IRQ handling code

[Mikhail Kshevetskiy]

airoha_irq_unmask(), airoha_irq_mask(), airoha_irq_type() functions
gets invalid pointers when initialize gpiochip and pinctrl variables.
Generally this should lead to kernel panic.

Details:

    gpiochip = irq_data_get_irq_chip_data(data);

will initialize gpiochip variable with data->chip_data value. This value
initialized inside gpiochip_irq_map() function

    static int gpiochip_irq_map(struct irq_domain *d, unsigned int irq,
			        irq_hw_number_t hwirq)
    {
	struct gpio_chip *gc = d->host_data;
        ...
	irq_set_chip_data(irq, gc);
	...
    }

Thus gpiochip variable of 'struct airoha_pinctrl_gpiochip *' type will be
initialized with a pointer to unrelated variable of 'struct gpio_chip'
type.

pinctrl pointer derived from the gpiochip variable

    pinctrl = container_of(gpiochip, struct airoha_pinctrl, gpiochip);

thus it will get wrong value as well.

So any access to the data pointed by gpiochip and pinctrl variables is
extremelly dangerous.

This patch implements correct logic of getting gpiochip and pinctrl
pointers.

Fixes: 1c8ace2d0725 ("pinctrl: airoha: Add support for EN7581 SoC")
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
---
 drivers/pinctrl/airoha/pinctrl-airoha.c | 20 +++++++++-----------
 1 file changed, 9 insertions(+), 11 deletions(-)

diff --git a/drivers/pinctrl/airoha/pinctrl-airoha.c b/drivers/pinctrl/airoha/pinctrl-airoha.c
index faad5d3ada31c..6cf4ed5976fb0 100644
--- a/drivers/pinctrl/airoha/pinctrl-airoha.c
+++ b/drivers/pinctrl/airoha/pinctrl-airoha.c
@@ -2569,18 +2569,17 @@ static int airoha_gpio_direction_output(struct gpio_chip *chip,
 /* irq callbacks */
 static void airoha_irq_unmask(struct irq_data *data)
 {
+	struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
+	struct airoha_pinctrl *pinctrl = gpiochip_get_data(gc);
+	struct airoha_pinctrl_gpiochip *gpiochip = &pinctrl->gpiochip;
 	u8 offset = data->hwirq % AIROHA_REG_GPIOCTRL_NUM_PIN;
 	u8 index = data->hwirq / AIROHA_REG_GPIOCTRL_NUM_PIN;
 	u32 mask = GENMASK(2 * offset + 1, 2 * offset);
-	struct airoha_pinctrl_gpiochip *gpiochip;
-	struct airoha_pinctrl *pinctrl;
 	u32 val = BIT(2 * offset);
 
-	gpiochip = irq_data_get_irq_chip_data(data);
 	if (WARN_ON_ONCE(data->hwirq >= ARRAY_SIZE(gpiochip->irq_type)))
 		return;
 
-	pinctrl = container_of(gpiochip, struct airoha_pinctrl, gpiochip);
 	switch (gpiochip->irq_type[data->hwirq]) {
 	case IRQ_TYPE_LEVEL_LOW:
 		val = val << 1;
@@ -2606,14 +2605,12 @@ static void airoha_irq_unmask(struct irq_data *data)
 
 static void airoha_irq_mask(struct irq_data *data)
 {
+	struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
+	struct airoha_pinctrl *pinctrl = gpiochip_get_data(gc);
+	struct airoha_pinctrl_gpiochip *gpiochip = &pinctrl->gpiochip;
 	u8 offset = data->hwirq % AIROHA_REG_GPIOCTRL_NUM_PIN;
 	u8 index = data->hwirq / AIROHA_REG_GPIOCTRL_NUM_PIN;
 	u32 mask = GENMASK(2 * offset + 1, 2 * offset);
-	struct airoha_pinctrl_gpiochip *gpiochip;
-	struct airoha_pinctrl *pinctrl;
-
-	gpiochip = irq_data_get_irq_chip_data(data);
-	pinctrl = container_of(gpiochip, struct airoha_pinctrl, gpiochip);
 
 	regmap_clear_bits(pinctrl->regmap, gpiochip->level[index], mask);
 	regmap_clear_bits(pinctrl->regmap, gpiochip->edge[index], mask);
@@ -2621,9 +2618,10 @@ static void airoha_irq_mask(struct irq_data *data)
 
 static int airoha_irq_type(struct irq_data *data, unsigned int type)
 {
-	struct airoha_pinctrl_gpiochip *gpiochip;
+	struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
+	struct airoha_pinctrl *pinctrl = gpiochip_get_data(gc);
+	struct airoha_pinctrl_gpiochip *gpiochip = &pinctrl->gpiochip;
 
-	gpiochip = irq_data_get_irq_chip_data(data);
 	if (data->hwirq >= ARRAY_SIZE(gpiochip->irq_type))
 		return -EINVAL;
 
-- 
2.53.0

Re: [PATCH v7 14/34] pinctrl: airoha: fix potential kenel panic in IRQ handling code

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider:

Pre-existing issues:
- [High] The shared parent IRQ is requested before the gpiochip and its IRQ domain are fully initialized, creating race conditions that lead to NULL pointer dereferences on probe and Use-After-Free during teardown.
- [High] The driver hardcodes `handle_simple_irq` for all interrupts and manually ACKs status bits after handling, causing race conditions that permanently lose edge interrupts.
- [High] The irq_chip callbacks call regmap functions on a syscon regmap, attempting to acquire a sleepable spinlock while holding a raw spinlock.
--

--- Patch [14]: [PATCH v7 14/34] pinctrl: airoha: fix potential kenel panic in IRQ handling code ---
commit 4e32db00b413a54d784b7251323863762cc5e739
Author: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>

    pinctrl: airoha: fix potential kenel panic in IRQ handling code
    
    This commit fixes invalid pointer initializations for gpiochip and pinctrl
    variables in the irq callback functions. Previously, these pointers were
    derived incorrectly, leading to dangerous memory accesses. The patch updates
    the code to correctly obtain the required pointers.

> pinctrl: airoha: fix potential kenel panic in IRQ handling code

This isn't a bug, but there's a typo (kenel) in the subject line.

[ ... ]

> So any access to the data pointed by gpiochip and pinctrl variables is
> extremelly dangerous.

This isn't a bug, but there's a typo (extremelly) here.

> diff --git a/drivers/pinctrl/airoha/pinctrl-airoha.c b/drivers/pinctrl/airoha/pinctrl-airoha.c
> index fcf498f7720c9..6b881ab56d9c3 100644
> --- a/drivers/pinctrl/airoha/pinctrl-airoha.c
> +++ b/drivers/pinctrl/airoha/pinctrl-airoha.c
> @@ -2606,14 +2605,12 @@ static void airoha_irq_unmask(struct irq_data *data)
>  
>  static void airoha_irq_mask(struct irq_data *data)
>  {
> +	struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
> +	struct airoha_pinctrl *pinctrl = gpiochip_get_data(gc);
> +	struct airoha_pinctrl_gpiochip *gpiochip = &pinctrl->gpiochip;
>  	u8 offset = data->hwirq % AIROHA_REG_GPIOCTRL_NUM_PIN;
>  	u8 index = data->hwirq / AIROHA_REG_GPIOCTRL_NUM_PIN;
>  	u32 mask = GENMASK(2 * offset + 1, 2 * offset);
>  
>  	regmap_clear_bits(pinctrl->regmap, gpiochip->level[index], mask);

[Severity: High]
This is a pre-existing issue, but on real-time kernels, wouldn't this result
in a scheduling while atomic bug?

The airoha_irq_mask() and airoha_irq_unmask() callbacks execute in atomic
hardirq context holding a raw_spinlock_t. However, they call
regmap_clear_bits() and regmap_update_bits() which attempt to acquire the
syscon regmap's lock.

Since the regmap from airoha_pinctrl_probe() uses a standard spinlock_t
(which becomes a sleepable rt_mutex on real-time kernels), could acquiring it
here trigger an invalid locking sequence?

[ ... ]

While reviewing this, I noticed a couple of other pre-existing regressions
in the driver's interrupt handling code:

[Severity: High]
This isn't a bug introduced by this patch, but does the devres cleanup order
create a use-after-free or null pointer dereference risk?

In airoha_pinctrl_add_gpiochip(), the parent interrupt is requested before the
gpiochip is added:

	err = devm_request_irq(dev, irq, airoha_irq_handler, IRQF_SHARED,
				dev_name(dev), pinctrl);
	if (err) {
		dev_err(dev, "error requesting irq %d: %d\n", irq, err);
		return err;
	}

	return devm_gpiochip_add_data(dev, gc, pinctrl);

Due to devres ordering (first-in, last-out), the domain will be destroyed
before the parent interrupt is freed during device unbind or if a later probe
step fails.

If an interrupt fires during this teardown window, wouldn't
airoha_irq_handler() dereference the freed girq->domain pointer here?

			generic_handle_irq(irq_find_mapping(girq->domain,
							    offset));

Could the request be moved after the gpiochip is added to ensure safe
teardown?

[Severity: High]
This is a pre-existing issue, but could this logic permanently lose concurrent
edge events?

In airoha_pinctrl_add_gpiochip(), the driver hardcodes handle_simple_irq for
all interrupts, regardless of their type:

	girq->handler = handle_simple_irq;
	gpio_irq_chip_set_chip(girq, &airoha_gpio_irq_chip);

And in airoha_irq_handler(), the hardware status bit is manually cleared
after handling the event:

			generic_handle_irq(irq_find_mapping(girq->domain,
							    offset));
			regmap_write(pinctrl->regmap,
				     pinctrl->gpiochip.status[i], BIT(irq));

If a second edge event arrives while the child handler is executing, wouldn't
the manual regmap_write unconditionally clear the status bit and cause the
new edge event to be discarded?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260727074234.3761170-1-mikhail.kshevetskiy@iopsys.eu?part=14

Re: [PATCH v7 14/34] pinctrl: airoha: fix potential kenel panic in IRQ handling code

[Lorenzo Bianconi]

[-- Attachment #1: Type: text/plain, Size: 4398 bytes --]

> airoha_irq_unmask(), airoha_irq_mask(), airoha_irq_type() functions
> gets invalid pointers when initialize gpiochip and pinctrl variables.
> Generally this should lead to kernel panic.
> 
> Details:
> 
>     gpiochip = irq_data_get_irq_chip_data(data);
> 
> will initialize gpiochip variable with data->chip_data value. This value
> initialized inside gpiochip_irq_map() function
> 
>     static int gpiochip_irq_map(struct irq_domain *d, unsigned int irq,
> 			        irq_hw_number_t hwirq)
>     {
> 	struct gpio_chip *gc = d->host_data;
>         ...
> 	irq_set_chip_data(irq, gc);
> 	...
>     }
> 
> Thus gpiochip variable of 'struct airoha_pinctrl_gpiochip *' type will be
> initialized with a pointer to unrelated variable of 'struct gpio_chip'
> type.
> 
> pinctrl pointer derived from the gpiochip variable
> 
>     pinctrl = container_of(gpiochip, struct airoha_pinctrl, gpiochip);
> 
> thus it will get wrong value as well.
> 
> So any access to the data pointed by gpiochip and pinctrl variables is
> extremelly dangerous.
> 
> This patch implements correct logic of getting gpiochip and pinctrl
> pointers.
> 
> Fixes: 1c8ace2d0725 ("pinctrl: airoha: Add support for EN7581 SoC")
> Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
> ---
>  drivers/pinctrl/airoha/pinctrl-airoha.c | 20 +++++++++-----------
>  1 file changed, 9 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/pinctrl/airoha/pinctrl-airoha.c b/drivers/pinctrl/airoha/pinctrl-airoha.c
> index faad5d3ada31c..6cf4ed5976fb0 100644
> --- a/drivers/pinctrl/airoha/pinctrl-airoha.c
> +++ b/drivers/pinctrl/airoha/pinctrl-airoha.c
> @@ -2569,18 +2569,17 @@ static int airoha_gpio_direction_output(struct gpio_chip *chip,
>  /* irq callbacks */
>  static void airoha_irq_unmask(struct irq_data *data)
>  {
> +	struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
> +	struct airoha_pinctrl *pinctrl = gpiochip_get_data(gc);
> +	struct airoha_pinctrl_gpiochip *gpiochip = &pinctrl->gpiochip;
>  	u8 offset = data->hwirq % AIROHA_REG_GPIOCTRL_NUM_PIN;
>  	u8 index = data->hwirq / AIROHA_REG_GPIOCTRL_NUM_PIN;
>  	u32 mask = GENMASK(2 * offset + 1, 2 * offset);
> -	struct airoha_pinctrl_gpiochip *gpiochip;
> -	struct airoha_pinctrl *pinctrl;
>  	u32 val = BIT(2 * offset);
>  
> -	gpiochip = irq_data_get_irq_chip_data(data);

I agree the proposed approach is more standard and I am fine with it, but can
you please provide more details about how it can panic?

gpio_chip is the first element of airoha_pinctrl_gpiochip so it is fine to cast
irq_data_get_irq_chip_data() return value to airoha_pinctrl_gpiochip, right?

Regards,
Lorenzo

>  	if (WARN_ON_ONCE(data->hwirq >= ARRAY_SIZE(gpiochip->irq_type)))
>  		return;
>  
> -	pinctrl = container_of(gpiochip, struct airoha_pinctrl, gpiochip);
>  	switch (gpiochip->irq_type[data->hwirq]) {
>  	case IRQ_TYPE_LEVEL_LOW:
>  		val = val << 1;
> @@ -2606,14 +2605,12 @@ static void airoha_irq_unmask(struct irq_data *data)
>  
>  static void airoha_irq_mask(struct irq_data *data)
>  {
> +	struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
> +	struct airoha_pinctrl *pinctrl = gpiochip_get_data(gc);
> +	struct airoha_pinctrl_gpiochip *gpiochip = &pinctrl->gpiochip;
>  	u8 offset = data->hwirq % AIROHA_REG_GPIOCTRL_NUM_PIN;
>  	u8 index = data->hwirq / AIROHA_REG_GPIOCTRL_NUM_PIN;
>  	u32 mask = GENMASK(2 * offset + 1, 2 * offset);
> -	struct airoha_pinctrl_gpiochip *gpiochip;
> -	struct airoha_pinctrl *pinctrl;
> -
> -	gpiochip = irq_data_get_irq_chip_data(data);
> -	pinctrl = container_of(gpiochip, struct airoha_pinctrl, gpiochip);
>  
>  	regmap_clear_bits(pinctrl->regmap, gpiochip->level[index], mask);
>  	regmap_clear_bits(pinctrl->regmap, gpiochip->edge[index], mask);
> @@ -2621,9 +2618,10 @@ static void airoha_irq_mask(struct irq_data *data)
>  
>  static int airoha_irq_type(struct irq_data *data, unsigned int type)
>  {
> -	struct airoha_pinctrl_gpiochip *gpiochip;
> +	struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
> +	struct airoha_pinctrl *pinctrl = gpiochip_get_data(gc);
> +	struct airoha_pinctrl_gpiochip *gpiochip = &pinctrl->gpiochip;
>  
> -	gpiochip = irq_data_get_irq_chip_data(data);
>  	if (data->hwirq >= ARRAY_SIZE(gpiochip->irq_type))
>  		return -EINVAL;
>  
> -- 
> 2.53.0
> 

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]

Re: [PATCH v7 14/34] pinctrl: airoha: fix potential kenel panic in IRQ handling code

[Mikhail Kshevetskiy]

On 7/27/26 11:31, Lorenzo Bianconi wrote:
>> airoha_irq_unmask(), airoha_irq_mask(), airoha_irq_type() functions
>> gets invalid pointers when initialize gpiochip and pinctrl variables.
>> Generally this should lead to kernel panic.
>>
>> Details:
>>
>>     gpiochip = irq_data_get_irq_chip_data(data);
>>
>> will initialize gpiochip variable with data->chip_data value. This value
>> initialized inside gpiochip_irq_map() function
>>
>>     static int gpiochip_irq_map(struct irq_domain *d, unsigned int irq,
>> 			        irq_hw_number_t hwirq)
>>     {
>> 	struct gpio_chip *gc = d->host_data;
>>         ...
>> 	irq_set_chip_data(irq, gc);
>> 	...
>>     }
>>
>> Thus gpiochip variable of 'struct airoha_pinctrl_gpiochip *' type will be
>> initialized with a pointer to unrelated variable of 'struct gpio_chip'
>> type.
>>
>> pinctrl pointer derived from the gpiochip variable
>>
>>     pinctrl = container_of(gpiochip, struct airoha_pinctrl, gpiochip);
>>
>> thus it will get wrong value as well.
>>
>> So any access to the data pointed by gpiochip and pinctrl variables is
>> extremelly dangerous.
>>
>> This patch implements correct logic of getting gpiochip and pinctrl
>> pointers.
>>
>> Fixes: 1c8ace2d0725 ("pinctrl: airoha: Add support for EN7581 SoC")
>> Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
>> ---
>>  drivers/pinctrl/airoha/pinctrl-airoha.c | 20 +++++++++-----------
>>  1 file changed, 9 insertions(+), 11 deletions(-)
>>
>> diff --git a/drivers/pinctrl/airoha/pinctrl-airoha.c b/drivers/pinctrl/airoha/pinctrl-airoha.c
>> index faad5d3ada31c..6cf4ed5976fb0 100644
>> --- a/drivers/pinctrl/airoha/pinctrl-airoha.c
>> +++ b/drivers/pinctrl/airoha/pinctrl-airoha.c
>> @@ -2569,18 +2569,17 @@ static int airoha_gpio_direction_output(struct gpio_chip *chip,
>>  /* irq callbacks */
>>  static void airoha_irq_unmask(struct irq_data *data)
>>  {
>> +	struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
>> +	struct airoha_pinctrl *pinctrl = gpiochip_get_data(gc);
>> +	struct airoha_pinctrl_gpiochip *gpiochip = &pinctrl->gpiochip;
>>  	u8 offset = data->hwirq % AIROHA_REG_GPIOCTRL_NUM_PIN;
>>  	u8 index = data->hwirq / AIROHA_REG_GPIOCTRL_NUM_PIN;
>>  	u32 mask = GENMASK(2 * offset + 1, 2 * offset);
>> -	struct airoha_pinctrl_gpiochip *gpiochip;
>> -	struct airoha_pinctrl *pinctrl;
>>  	u32 val = BIT(2 * offset);
>>  
>> -	gpiochip = irq_data_get_irq_chip_data(data);
> I agree the proposed approach is more standard and I am fine with it, but can
> you please provide more details about how it can panic?
>
> gpio_chip is the first element of airoha_pinctrl_gpiochip so it is fine to cast
> irq_data_get_irq_chip_data() return value to airoha_pinctrl_gpiochip, right?

Sorry, you are right, the will be no panic unless structure fields will
be reordered.
I'll fix commit message


>
> Regards,
> Lorenzo
>
>>  	if (WARN_ON_ONCE(data->hwirq >= ARRAY_SIZE(gpiochip->irq_type)))
>>  		return;
>>  
>> -	pinctrl = container_of(gpiochip, struct airoha_pinctrl, gpiochip);
>>  	switch (gpiochip->irq_type[data->hwirq]) {
>>  	case IRQ_TYPE_LEVEL_LOW:
>>  		val = val << 1;
>> @@ -2606,14 +2605,12 @@ static void airoha_irq_unmask(struct irq_data *data)
>>  
>>  static void airoha_irq_mask(struct irq_data *data)
>>  {
>> +	struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
>> +	struct airoha_pinctrl *pinctrl = gpiochip_get_data(gc);
>> +	struct airoha_pinctrl_gpiochip *gpiochip = &pinctrl->gpiochip;
>>  	u8 offset = data->hwirq % AIROHA_REG_GPIOCTRL_NUM_PIN;
>>  	u8 index = data->hwirq / AIROHA_REG_GPIOCTRL_NUM_PIN;
>>  	u32 mask = GENMASK(2 * offset + 1, 2 * offset);
>> -	struct airoha_pinctrl_gpiochip *gpiochip;
>> -	struct airoha_pinctrl *pinctrl;
>> -
>> -	gpiochip = irq_data_get_irq_chip_data(data);
>> -	pinctrl = container_of(gpiochip, struct airoha_pinctrl, gpiochip);
>>  
>>  	regmap_clear_bits(pinctrl->regmap, gpiochip->level[index], mask);
>>  	regmap_clear_bits(pinctrl->regmap, gpiochip->edge[index], mask);
>> @@ -2621,9 +2618,10 @@ static void airoha_irq_mask(struct irq_data *data)
>>  
>>  static int airoha_irq_type(struct irq_data *data, unsigned int type)
>>  {
>> -	struct airoha_pinctrl_gpiochip *gpiochip;
>> +	struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
>> +	struct airoha_pinctrl *pinctrl = gpiochip_get_data(gc);
>> +	struct airoha_pinctrl_gpiochip *gpiochip = &pinctrl->gpiochip;
>>  
>> -	gpiochip = irq_data_get_irq_chip_data(data);
>>  	if (data->hwirq >= ARRAY_SIZE(gpiochip->irq_type))
>>  		return -EINVAL;
>>  
>> -- 
>> 2.53.0
>>

[PATCH v7 15/34] pinctrl: airoha: fix IRQ mask/unmask code

[Mikhail Kshevetskiy]

When using IRQCHIP_IMMUTABLE, airoha_irq_unmask() must manually call
gpiochip_enable_irq() and airoha_irq_mask() must call
gpiochip_disable_irq(). Without these calls, gpiolib never sets the
GPIOD_FLAG_IRQ_IS_ENABLED bit. Because this bit is missing,
gpiod_direction_output() will not realize the pin is actively used
as an interrupt.

Fixes: 1c8ace2d0725 ("pinctrl: airoha: Add support for EN7581 SoC")
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
---
 drivers/pinctrl/airoha/pinctrl-airoha.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/pinctrl/airoha/pinctrl-airoha.c b/drivers/pinctrl/airoha/pinctrl-airoha.c
index 6cf4ed5976fb0..f85941ccea560 100644
--- a/drivers/pinctrl/airoha/pinctrl-airoha.c
+++ b/drivers/pinctrl/airoha/pinctrl-airoha.c
@@ -2580,6 +2580,7 @@ static void airoha_irq_unmask(struct irq_data *data)
 	if (WARN_ON_ONCE(data->hwirq >= ARRAY_SIZE(gpiochip->irq_type)))
 		return;
 
+	gpiochip_enable_irq(gc, irqd_to_hwirq(data));
 	switch (gpiochip->irq_type[data->hwirq]) {
 	case IRQ_TYPE_LEVEL_LOW:
 		val = val << 1;
@@ -2614,6 +2615,7 @@ static void airoha_irq_mask(struct irq_data *data)
 
 	regmap_clear_bits(pinctrl->regmap, gpiochip->level[index], mask);
 	regmap_clear_bits(pinctrl->regmap, gpiochip->edge[index], mask);
+	gpiochip_disable_irq(gc, irqd_to_hwirq(data));
 }
 
 static int airoha_irq_type(struct irq_data *data, unsigned int type)
-- 
2.53.0

Re: [PATCH v7 15/34] pinctrl: airoha: fix IRQ mask/unmask code

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider:

New issues:
- [High] Adding `gpiochip_enable_irq()` and `gpiochip_disable_irq()` triggers continuous WARN_ON traces and fails to set the IRQ enabled flag due to missing GPIOCHIP_IRQ_RESOURCE_HELPERS.

Pre-existing issues:
- [High] Missing GPIOCHIP_IRQ_RESOURCE_HELPERS causes a module refcount leak, leading to a Use-After-Free panic on module unload.
- [High] The IRQ mask and unmask callbacks call regmap functions that acquire a spinlock_t while a raw_spinlock_t is held, violating lock nesting rules.
--

--- Patch [15]: [PATCH v7 15/34] pinctrl: airoha: fix IRQ mask/unmask code ---
commit f9ea4e1f8ee631522df69bbad30882277aa2e0a4
Author: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>

pinctrl: airoha: fix IRQ mask/unmask code

This commit adds gpiochip_enable_irq and gpiochip_disable_irq calls to
the mask and unmask callbacks. This ensures gpiolib correctly tracks when a
pin is actively used as an interrupt.

> diff --git a/drivers/pinctrl/airoha/pinctrl-airoha.c b/drivers/pinctrl/airoha/pinctrl-airoha.c
> index 6b881ab56d9c3..2dc97e0711003 100644
> --- a/drivers/pinctrl/airoha/pinctrl-airoha.c
> +++ b/drivers/pinctrl/airoha/pinctrl-airoha.c
> @@ -2580,6 +2580,7 @@ static void airoha_irq_unmask(struct irq_data *data)
>  	if (WARN_ON_ONCE(data->hwirq >= ARRAY_SIZE(gpiochip->irq_type)))
>  		return;
>  
> +	gpiochip_enable_irq(gc, irqd_to_hwirq(data));

[Severity: High]
Will this trigger a continuous WARN_ON trace and fail to set the flag?

The driver defines airoha_gpio_irq_chip as IRQCHIP_IMMUTABLE but omits the
GPIOCHIP_IRQ_RESOURCE_HELPERS macro. Because of this, .irq_request_resources
is NULL, so the IRQ core bypasses gpiochip_reqres_irq.

Since gpiochip_lock_as_irq is never called, the GPIOD_FLAG_USED_AS_IRQ
bit is never set on the GPIO descriptor.

The newly added gpiochip_enable_irq call has a safety check:

WARN_ON(!test_bit(GPIOD_FLAG_USED_AS_IRQ, &desc->flags));

Because the flag is missing, does this trigger a kernel stack trace on every
mask/unmask operation, completely preventing GPIOD_FLAG_IRQ_IS_ENABLED from
being updated?

[Severity: High]
This is a pre-existing issue, but does the missing
GPIOCHIP_IRQ_RESOURCE_HELPERS macro also cause a module refcount leak?

By bypassing gpiochip_reqres_irq, the try_module_get(gc->gpiodev->owner)
call that pins the GPIO controller module in memory is skipped.

If the pinctrl-airoha module is unloaded while an IRQ is requested, will
subsequent IRQ triggers or unregister operations access freed memory and
cause a use-after-free panic?

[ ... ]

> @@ -2614,6 +2615,7 @@ static void airoha_irq_mask(struct irq_data *data)
>  
>  	regmap_clear_bits(pinctrl->regmap, gpiochip->level[index], mask);
>  	regmap_clear_bits(pinctrl->regmap, gpiochip->edge[index], mask);

[Severity: High]
This is a pre-existing issue, but does calling regmap_clear_bits here
cause a lock nesting violation?

The IRQ core calls the .irq_mask and .irq_unmask callbacks with the irq
descriptor lock held, which is a raw_spinlock_t.

The driver calls regmap_clear_bits and regmap_update_bits on a regmap
that initializes its lock as a spinlock_t. Acquiring a spinlock_t while
holding a raw_spinlock_t is an invalid wait-type nesting violation.

On PREEMPT_RT kernels where spinlock_t is a sleepable rt_mutex, does
acquiring it while holding a raw_spinlock_t result in sleeping in atomic
context?

> +	gpiochip_disable_irq(gc, irqd_to_hwirq(data));
>  }

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260727074234.3761170-1-mikhail.kshevetskiy@iopsys.eu?part=15

Re: [PATCH v7 15/34] pinctrl: airoha: fix IRQ mask/unmask code

[Lorenzo Bianconi]

[-- Attachment #1: Type: text/plain, Size: 1587 bytes --]

> When using IRQCHIP_IMMUTABLE, airoha_irq_unmask() must manually call
> gpiochip_enable_irq() and airoha_irq_mask() must call
> gpiochip_disable_irq(). Without these calls, gpiolib never sets the
> GPIOD_FLAG_IRQ_IS_ENABLED bit. Because this bit is missing,
> gpiod_direction_output() will not realize the pin is actively used
> as an interrupt.

Acked-by: Lorenzo Bianconi <lorenzo@kernel.org>

> 
> Fixes: 1c8ace2d0725 ("pinctrl: airoha: Add support for EN7581 SoC")
> Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
> ---
>  drivers/pinctrl/airoha/pinctrl-airoha.c | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/drivers/pinctrl/airoha/pinctrl-airoha.c b/drivers/pinctrl/airoha/pinctrl-airoha.c
> index 6cf4ed5976fb0..f85941ccea560 100644
> --- a/drivers/pinctrl/airoha/pinctrl-airoha.c
> +++ b/drivers/pinctrl/airoha/pinctrl-airoha.c
> @@ -2580,6 +2580,7 @@ static void airoha_irq_unmask(struct irq_data *data)
>  	if (WARN_ON_ONCE(data->hwirq >= ARRAY_SIZE(gpiochip->irq_type)))
>  		return;
>  
> +	gpiochip_enable_irq(gc, irqd_to_hwirq(data));
>  	switch (gpiochip->irq_type[data->hwirq]) {
>  	case IRQ_TYPE_LEVEL_LOW:
>  		val = val << 1;
> @@ -2614,6 +2615,7 @@ static void airoha_irq_mask(struct irq_data *data)
>  
>  	regmap_clear_bits(pinctrl->regmap, gpiochip->level[index], mask);
>  	regmap_clear_bits(pinctrl->regmap, gpiochip->edge[index], mask);
> +	gpiochip_disable_irq(gc, irqd_to_hwirq(data));
>  }
>  
>  static int airoha_irq_type(struct irq_data *data, unsigned int type)
> -- 
> 2.53.0
> 

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]

[PATCH v7 16/34] pinctrl: airoha: add missed IRQ resource helpers

[Mikhail Kshevetskiy]

Without hooking .irq_request_resources, gpiolib cannot set
GPIOD_FLAG_USED_AS_IRQ. This breaks pin direction locking and can allow
userspace or another driver to reconfigure an active IRQ pin as an output

Fixes: 1c8ace2d0725 ("pinctrl: airoha: Add support for EN7581 SoC")
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
---
 drivers/pinctrl/airoha/pinctrl-airoha.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/pinctrl/airoha/pinctrl-airoha.c b/drivers/pinctrl/airoha/pinctrl-airoha.c
index f85941ccea560..d218a1f01648b 100644
--- a/drivers/pinctrl/airoha/pinctrl-airoha.c
+++ b/drivers/pinctrl/airoha/pinctrl-airoha.c
@@ -2676,6 +2676,7 @@ static const struct irq_chip airoha_gpio_irq_chip = {
 	.irq_mask_ack = airoha_irq_mask,
 	.irq_set_type = airoha_irq_type,
 	.flags = IRQCHIP_SET_TYPE_MASKED | IRQCHIP_IMMUTABLE,
+	GPIOCHIP_IRQ_RESOURCE_HELPERS,
 };
 
 static int airoha_pinctrl_add_gpiochip(struct airoha_pinctrl *pinctrl,
-- 
2.53.0

Re: [PATCH v7 16/34] pinctrl: airoha: add missed IRQ resource helpers

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider:

Pre-existing issues:
- [High] Raw Spinlock Nesting Violation: `airoha_irq_mask` and `airoha_irq_unmask` acquire a `spinlock_t` while holding a `raw_spinlock_t`.
- [High] Lost edge-triggered interrupts due to clearing the hardware status register after executing the IRQ handler.
- [High] Unsafe IRQ mapping and early shared IRQ registration can result in executing an invalid IRQ 0.
--

--- Patch [16]: [PATCH v7 16/34] pinctrl: airoha: add missed IRQ resource helpers ---
commit ca6b3b2f26911552b2347a6203653d8c640120dd
Author: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>

pinctrl: airoha: add missed IRQ resource helpers

Without hooking .irq_request_resources, gpiolib cannot set
GPIOD_FLAG_USED_AS_IRQ. This breaks pin direction locking and can allow
userspace or another driver to reconfigure an active IRQ pin as an output.

> diff --git a/drivers/pinctrl/airoha/pinctrl-airoha.c b/drivers/pinctrl/airoha/pinctrl-airoha.c
> index 2dc97e0711003..c886ecc2c39e9 100644
> --- a/drivers/pinctrl/airoha/pinctrl-airoha.c
> +++ b/drivers/pinctrl/airoha/pinctrl-airoha.c
> @@ -2676,6 +2676,7 @@ static const struct irq_chip airoha_gpio_irq_chip = {
>  	.irq_mask_ack = airoha_irq_mask,

[Severity: High]
This isn't a bug introduced by this patch, but can this cause a lock nesting
violation?

The IRQ core calls .irq_mask and .irq_unmask with the IRQ descriptor's
raw_spinlock_t held. Inside airoha_irq_mask(), the driver calls
regmap_clear_bits():

drivers/pinctrl/airoha/pinctrl-airoha.c:airoha_irq_mask() {
	...
	regmap_clear_bits(pinctrl->regmap, gpiochip->level[index], mask);
	regmap_clear_bits(pinctrl->regmap, gpiochip->edge[index], mask);
	...
}

And inside airoha_irq_unmask(), it calls regmap_update_bits():

drivers/pinctrl/airoha/pinctrl-airoha.c:airoha_irq_unmask() {
	...
	regmap_update_bits(pinctrl->regmap, gpiochip->level[index],
			   mask, val);
	...
}

Since pinctrl->regmap defaults to using a standard sleepable spinlock_t,
acquiring it inside a raw_spinlock_t critical section is a wait-type lock
nesting violation. This will cause a "sleeping in atomic context" kernel panic
on PREEMPT_RT kernels, or lockdep splats with CONFIG_PROVE_RAW_LOCK_NESTING=y.

>  	.irq_set_type = airoha_irq_type,
>  	.flags = IRQCHIP_SET_TYPE_MASKED | IRQCHIP_IMMUTABLE,
> +	GPIOCHIP_IRQ_RESOURCE_HELPERS,
>  };
>  
>  static int airoha_pinctrl_add_gpiochip(struct airoha_pinctrl *pinctrl,

[Severity: High]
This is a pre-existing issue, but could this cause lost edge-triggered
interrupts?

In airoha_irq_handler(), the hardware status bit is read, generic_handle_irq()
is dispatched, and only after it returns is the status cleared via
regmap_write():

drivers/pinctrl/airoha/pinctrl-airoha.c:airoha_irq_handler() {
	...
	generic_handle_irq(irq_find_mapping(girq->domain, offset));
	regmap_write(pinctrl->regmap, pinctrl->gpiochip.status[i], BIT(irq));
	...
}

If a new edge-triggered interrupt arrives while the child IRQ handler is
executing, the hardware status bit will be set again. The unconditional clear
after the handler returns will discard this new interrupt edge, leading to lost
interrupts.

Does the hardware status need to be acknowledged before invoking the handler
for edge-triggered interrupts?


[Severity: High]
This is also a pre-existing issue, but could this early shared IRQ registration
lead to executing an invalid IRQ?

In airoha_pinctrl_add_gpiochip(), devm_request_irq() is called with IRQF_SHARED
before devm_gpiochip_add_data() initializes the irqdomain:

drivers/pinctrl/airoha/pinctrl-airoha.c:airoha_pinctrl_add_gpiochip() {
	...
	err = devm_request_irq(dev, irq, airoha_irq_handler, IRQF_SHARED,
				dev_name(dev), pinctrl);
	...
	return devm_gpiochip_add_data(dev, gc, pinctrl);
}

If the shared interrupt triggers immediately from another device on the same
line, airoha_irq_handler() runs while the domain is still NULL. This causes
irq_find_mapping(NULL, offset) to return 0.

Passing 0 to generic_handle_irq() will execute IRQ 0 (often a system timer or
invalid IRQ), leading to system instability or an invalid IRQ trap.

Should the IRQ be requested after the domain is created, and use
generic_handle_domain_irq() to handle unmapped IRQs safely?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260727074234.3761170-1-mikhail.kshevetskiy@iopsys.eu?part=16

Re: [PATCH v7 16/34] pinctrl: airoha: add missed IRQ resource helpers

[Lorenzo Bianconi]

[-- Attachment #1: Type: text/plain, Size: 1107 bytes --]

> Without hooking .irq_request_resources, gpiolib cannot set
> GPIOD_FLAG_USED_AS_IRQ. This breaks pin direction locking and can allow
> userspace or another driver to reconfigure an active IRQ pin as an output
> 
> Fixes: 1c8ace2d0725 ("pinctrl: airoha: Add support for EN7581 SoC")
> Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>

Acked-by: Lorenzo Bianconi <lorenzo@kernel.org>

> ---
>  drivers/pinctrl/airoha/pinctrl-airoha.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/pinctrl/airoha/pinctrl-airoha.c b/drivers/pinctrl/airoha/pinctrl-airoha.c
> index f85941ccea560..d218a1f01648b 100644
> --- a/drivers/pinctrl/airoha/pinctrl-airoha.c
> +++ b/drivers/pinctrl/airoha/pinctrl-airoha.c
> @@ -2676,6 +2676,7 @@ static const struct irq_chip airoha_gpio_irq_chip = {
>  	.irq_mask_ack = airoha_irq_mask,
>  	.irq_set_type = airoha_irq_type,
>  	.flags = IRQCHIP_SET_TYPE_MASKED | IRQCHIP_IMMUTABLE,
> +	GPIOCHIP_IRQ_RESOURCE_HELPERS,
>  };
>  
>  static int airoha_pinctrl_add_gpiochip(struct airoha_pinctrl *pinctrl,
> -- 
> 2.53.0
> 

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]

[PATCH v7 17/34] pinctrl: airoha: fix edge-triggered interrupts handling

[Mikhail Kshevetskiy]

Edge-triggered interrupts are handled incorrectly because of
 * no irq_ack() handler was defined,
 * no handle_level_irq() handler was used,

This patch probably fixes an issue

Fixes: 1c8ace2d0725 ("pinctrl: airoha: Add support for EN7581 SoC")
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
---
 drivers/pinctrl/airoha/pinctrl-airoha.c | 38 +++++++++++++++++++++----
 1 file changed, 33 insertions(+), 5 deletions(-)

diff --git a/drivers/pinctrl/airoha/pinctrl-airoha.c b/drivers/pinctrl/airoha/pinctrl-airoha.c
index d218a1f01648b..df3a1d7c7b571 100644
--- a/drivers/pinctrl/airoha/pinctrl-airoha.c
+++ b/drivers/pinctrl/airoha/pinctrl-airoha.c
@@ -2613,11 +2613,28 @@ static void airoha_irq_mask(struct irq_data *data)
 	u8 index = data->hwirq / AIROHA_REG_GPIOCTRL_NUM_PIN;
 	u32 mask = GENMASK(2 * offset + 1, 2 * offset);
 
+	if (data->hwirq >= ARRAY_SIZE(gpiochip->irq_type))
+		return;
+
 	regmap_clear_bits(pinctrl->regmap, gpiochip->level[index], mask);
 	regmap_clear_bits(pinctrl->regmap, gpiochip->edge[index], mask);
 	gpiochip_disable_irq(gc, irqd_to_hwirq(data));
 }
 
+static void airoha_irq_ack(struct irq_data *data)
+{
+	struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
+	struct airoha_pinctrl *pinctrl = gpiochip_get_data(gc);
+	struct airoha_pinctrl_gpiochip *gpiochip = &pinctrl->gpiochip;
+	u8 offset = data->hwirq % AIROHA_PIN_BANK_SIZE;
+	u8 index = data->hwirq / AIROHA_PIN_BANK_SIZE;
+
+	if (data->hwirq >= ARRAY_SIZE(gpiochip->irq_type))
+		return;
+
+	regmap_write(pinctrl->regmap, gpiochip->status[index], BIT(offset));
+}
+
 static int airoha_irq_type(struct irq_data *data, unsigned int type)
 {
 	struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
@@ -2627,13 +2644,25 @@ static int airoha_irq_type(struct irq_data *data, unsigned int type)
 	if (data->hwirq >= ARRAY_SIZE(gpiochip->irq_type))
 		return -EINVAL;
 
+	if (type == IRQ_TYPE_NONE) {
+		gpiochip->irq_type[data->hwirq] = IRQ_TYPE_NONE;
+		irq_set_handler_locked(data, handle_bad_irq);
+
+		return 0;
+	}
+
 	if (type == IRQ_TYPE_PROBE) {
 		if (gpiochip->irq_type[data->hwirq])
 			return 0;
 
-		type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
+		type = IRQ_TYPE_EDGE_BOTH;
 	}
+
 	gpiochip->irq_type[data->hwirq] = type & IRQ_TYPE_SENSE_MASK;
+	if (type & IRQ_TYPE_EDGE_BOTH)
+		irq_set_handler_locked(data, handle_edge_irq);
+	else
+		irq_set_handler_locked(data, handle_level_irq);
 
 	return 0;
 }
@@ -2658,8 +2687,7 @@ static irqreturn_t airoha_irq_handler(int irq, void *data)
 		for_each_set_bit(irq, &status, AIROHA_PIN_BANK_SIZE) {
 			u32 offset = irq + i * AIROHA_PIN_BANK_SIZE;
 
-			generic_handle_irq(irq_find_mapping(girq->domain,
-							    offset));
+			generic_handle_domain_irq(girq->domain, offset);
 			regmap_write(pinctrl->regmap,
 				     pinctrl->gpiochip.status[i], BIT(irq));
 		}
@@ -2673,7 +2701,7 @@ static const struct irq_chip airoha_gpio_irq_chip = {
 	.name = "airoha-gpio-irq",
 	.irq_unmask = airoha_irq_unmask,
 	.irq_mask = airoha_irq_mask,
-	.irq_mask_ack = airoha_irq_mask,
+	.irq_ack = airoha_irq_ack,
 	.irq_set_type = airoha_irq_type,
 	.flags = IRQCHIP_SET_TYPE_MASKED | IRQCHIP_IMMUTABLE,
 	GPIOCHIP_IRQ_RESOURCE_HELPERS,
@@ -2708,7 +2736,7 @@ static int airoha_pinctrl_add_gpiochip(struct airoha_pinctrl *pinctrl,
 	gc->ngpio = AIROHA_NUM_PINS;
 
 	girq->default_type = IRQ_TYPE_NONE;
-	girq->handler = handle_simple_irq;
+	girq->handler = handle_bad_irq;
 	gpio_irq_chip_set_chip(girq, &airoha_gpio_irq_chip);
 
 	irq = platform_get_irq(pdev, 0);
-- 
2.53.0

Re: [PATCH v7 17/34] pinctrl: airoha: fix edge-triggered interrupts handling

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:

New issues:
- [High] Leftover manual status clear in `airoha_irq_handler` double-acknowledges edge-triggered interrupts, causing newly latched edge events to be permanently lost.

Pre-existing issues:
- [High] The irq_chip callbacks acquire a non-raw spinlock (`spinlock_t`) inside a raw spinlock critical section, causing a lockdep violation and a panic on PREEMPT_RT kernels.
--

--- Patch [17]: [PATCH v7 17/34] pinctrl: airoha: fix edge-triggered interrupts handling ---
commit 2624d620bd965f151504e589dca531b9b80d52fe
Author: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>

pinctrl: airoha: fix edge-triggered interrupts handling

This patch aims to fix edge-triggered interrupts handling for the Airoha
EN7581 SoC. It defines an irq_ack handler, switches to using the appropriate
handle_level_irq or handle_edge_irq handler based on the interrupt type,
and assigns the handler type.

> diff --git a/drivers/pinctrl/airoha/pinctrl-airoha.c b/drivers/pinctrl/airoha/pinctrl-airoha.c
> index c886ecc2c39e9..0a865cf0c2728 100644
> --- a/drivers/pinctrl/airoha/pinctrl-airoha.c
> +++ b/drivers/pinctrl/airoha/pinctrl-airoha.c
> @@ -2613,11 +2613,28 @@ static void airoha_irq_mask(struct irq_data *data)
>  	u8 index = data->hwirq / AIROHA_REG_GPIOCTRL_NUM_PIN;
>  	u32 mask = GENMASK(2 * offset + 1, 2 * offset);
>  
> +	if (data->hwirq >= ARRAY_SIZE(gpiochip->irq_type))
> +		return;
> +
>  	regmap_clear_bits(pinctrl->regmap, gpiochip->level[index], mask);
>  	regmap_clear_bits(pinctrl->regmap, gpiochip->edge[index], mask);

[Severity: High]
This is a pre-existing issue, but does calling regmap operations here cause
a lock nesting violation on PREEMPT_RT kernels?

The core IRQ flow handlers call irq_chip callbacks like irq_mask and irq_ack
while holding the IRQ descriptor lock, which is a raw_spinlock_t. Because
the driver initializes this regmap via device_node_to_regmap, it defaults to
using a standard spinlock_t.

On PREEMPT_RT, spinlock_t becomes a sleeping rt_mutex. Acquiring a sleeping
lock while holding a raw_spinlock_t causes a kernel panic. Since this patch
adds airoha_irq_ack which also uses regmap_write, it introduces another path
for this same lockdep violation.

>  	gpiochip_disable_irq(gc, irqd_to_hwirq(data));
>  }

[ ... ]

> @@ -2658,8 +2687,7 @@ static irqreturn_t airoha_irq_handler(int irq, void *data)
>  		for_each_set_bit(irq, &status, AIROHA_PIN_BANK_SIZE) {
>  			u32 offset = irq + i * AIROHA_PIN_BANK_SIZE;
>  
> -			generic_handle_irq(irq_find_mapping(girq->domain,
> -							    offset));
> +			generic_handle_domain_irq(girq->domain, offset);
>  			regmap_write(pinctrl->regmap,
>  				     pinctrl->gpiochip.status[i], BIT(irq));

[Severity: High]
Are edge interrupts permanently lost due to this trailing regmap_write?

With this patch properly configuring handle_edge_irq for edge interrupts,
the core IRQ code calls the newly added airoha_irq_ack function before
invoking the device driver's action handler. This early ack correctly clears
the hardware status bit so new edges can be latched.

However, when the driver's action handler completes and the call to
generic_handle_domain_irq returns, this manual regmap_write unconditionally
clears the status bit a second time. If a new edge arrives and is latched 
while the ISR is executing, wouldn't this trailing write wipe out the newly
latched state in the hardware status register?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260727074234.3761170-1-mikhail.kshevetskiy@iopsys.eu?part=17

Re: [PATCH v7 17/34] pinctrl: airoha: fix edge-triggered interrupts handling

[Lorenzo Bianconi]

[-- Attachment #1: Type: text/plain, Size: 3908 bytes --]

> Edge-triggered interrupts are handled incorrectly because of
>  * no irq_ack() handler was defined,
>  * no handle_level_irq() handler was used,
> 
> This patch probably fixes an issue
> 
> Fixes: 1c8ace2d0725 ("pinctrl: airoha: Add support for EN7581 SoC")
> Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>

Acked-by: Lorenzo Bianconi <lorenzo@kernel.org>

> ---
>  drivers/pinctrl/airoha/pinctrl-airoha.c | 38 +++++++++++++++++++++----
>  1 file changed, 33 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/pinctrl/airoha/pinctrl-airoha.c b/drivers/pinctrl/airoha/pinctrl-airoha.c
> index d218a1f01648b..df3a1d7c7b571 100644
> --- a/drivers/pinctrl/airoha/pinctrl-airoha.c
> +++ b/drivers/pinctrl/airoha/pinctrl-airoha.c
> @@ -2613,11 +2613,28 @@ static void airoha_irq_mask(struct irq_data *data)
>  	u8 index = data->hwirq / AIROHA_REG_GPIOCTRL_NUM_PIN;
>  	u32 mask = GENMASK(2 * offset + 1, 2 * offset);
>  
> +	if (data->hwirq >= ARRAY_SIZE(gpiochip->irq_type))
> +		return;
> +
>  	regmap_clear_bits(pinctrl->regmap, gpiochip->level[index], mask);
>  	regmap_clear_bits(pinctrl->regmap, gpiochip->edge[index], mask);
>  	gpiochip_disable_irq(gc, irqd_to_hwirq(data));
>  }
>  
> +static void airoha_irq_ack(struct irq_data *data)
> +{
> +	struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
> +	struct airoha_pinctrl *pinctrl = gpiochip_get_data(gc);
> +	struct airoha_pinctrl_gpiochip *gpiochip = &pinctrl->gpiochip;
> +	u8 offset = data->hwirq % AIROHA_PIN_BANK_SIZE;
> +	u8 index = data->hwirq / AIROHA_PIN_BANK_SIZE;
> +
> +	if (data->hwirq >= ARRAY_SIZE(gpiochip->irq_type))
> +		return;
> +
> +	regmap_write(pinctrl->regmap, gpiochip->status[index], BIT(offset));
> +}
> +
>  static int airoha_irq_type(struct irq_data *data, unsigned int type)
>  {
>  	struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
> @@ -2627,13 +2644,25 @@ static int airoha_irq_type(struct irq_data *data, unsigned int type)
>  	if (data->hwirq >= ARRAY_SIZE(gpiochip->irq_type))
>  		return -EINVAL;
>  
> +	if (type == IRQ_TYPE_NONE) {
> +		gpiochip->irq_type[data->hwirq] = IRQ_TYPE_NONE;
> +		irq_set_handler_locked(data, handle_bad_irq);
> +
> +		return 0;
> +	}
> +
>  	if (type == IRQ_TYPE_PROBE) {
>  		if (gpiochip->irq_type[data->hwirq])
>  			return 0;
>  
> -		type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
> +		type = IRQ_TYPE_EDGE_BOTH;
>  	}
> +
>  	gpiochip->irq_type[data->hwirq] = type & IRQ_TYPE_SENSE_MASK;
> +	if (type & IRQ_TYPE_EDGE_BOTH)
> +		irq_set_handler_locked(data, handle_edge_irq);
> +	else
> +		irq_set_handler_locked(data, handle_level_irq);
>  
>  	return 0;
>  }
> @@ -2658,8 +2687,7 @@ static irqreturn_t airoha_irq_handler(int irq, void *data)
>  		for_each_set_bit(irq, &status, AIROHA_PIN_BANK_SIZE) {
>  			u32 offset = irq + i * AIROHA_PIN_BANK_SIZE;
>  
> -			generic_handle_irq(irq_find_mapping(girq->domain,
> -							    offset));
> +			generic_handle_domain_irq(girq->domain, offset);
>  			regmap_write(pinctrl->regmap,
>  				     pinctrl->gpiochip.status[i], BIT(irq));
>  		}
> @@ -2673,7 +2701,7 @@ static const struct irq_chip airoha_gpio_irq_chip = {
>  	.name = "airoha-gpio-irq",
>  	.irq_unmask = airoha_irq_unmask,
>  	.irq_mask = airoha_irq_mask,
> -	.irq_mask_ack = airoha_irq_mask,
> +	.irq_ack = airoha_irq_ack,
>  	.irq_set_type = airoha_irq_type,
>  	.flags = IRQCHIP_SET_TYPE_MASKED | IRQCHIP_IMMUTABLE,
>  	GPIOCHIP_IRQ_RESOURCE_HELPERS,
> @@ -2708,7 +2736,7 @@ static int airoha_pinctrl_add_gpiochip(struct airoha_pinctrl *pinctrl,
>  	gc->ngpio = AIROHA_NUM_PINS;
>  
>  	girq->default_type = IRQ_TYPE_NONE;
> -	girq->handler = handle_simple_irq;
> +	girq->handler = handle_bad_irq;
>  	gpio_irq_chip_set_chip(girq, &airoha_gpio_irq_chip);
>  
>  	irq = platform_get_irq(pdev, 0);
> -- 
> 2.53.0
> 

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]

[PATCH v7 18/34] pinctrl: airoha: remove not needed irq_type[] array

[Mikhail Kshevetskiy]

irq_type[] array inside airoha_pinctrl_gpiochip structure is not
actually necessary. Use trigger type from 'struct irq_data' instead.

Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
---
 drivers/pinctrl/airoha/pinctrl-airoha.c | 22 ++++++++--------------
 1 file changed, 8 insertions(+), 14 deletions(-)

diff --git a/drivers/pinctrl/airoha/pinctrl-airoha.c b/drivers/pinctrl/airoha/pinctrl-airoha.c
index df3a1d7c7b571..65447d7e5965a 100644
--- a/drivers/pinctrl/airoha/pinctrl-airoha.c
+++ b/drivers/pinctrl/airoha/pinctrl-airoha.c
@@ -382,8 +382,6 @@ struct airoha_pinctrl_gpiochip {
 	const u32 *status;
 	const u32 *level;
 	const u32 *edge;
-
-	u32 irq_type[AIROHA_NUM_PINS];
 };
 
 struct airoha_pinctrl_confs_info {
@@ -2577,11 +2575,11 @@ static void airoha_irq_unmask(struct irq_data *data)
 	u32 mask = GENMASK(2 * offset + 1, 2 * offset);
 	u32 val = BIT(2 * offset);
 
-	if (WARN_ON_ONCE(data->hwirq >= ARRAY_SIZE(gpiochip->irq_type)))
+	if (WARN_ON_ONCE(data->hwirq >= AIROHA_NUM_PINS))
 		return;
 
 	gpiochip_enable_irq(gc, irqd_to_hwirq(data));
-	switch (gpiochip->irq_type[data->hwirq]) {
+	switch (irqd_get_trigger_type(data)) {
 	case IRQ_TYPE_LEVEL_LOW:
 		val = val << 1;
 		fallthrough;
@@ -2613,7 +2611,7 @@ static void airoha_irq_mask(struct irq_data *data)
 	u8 index = data->hwirq / AIROHA_REG_GPIOCTRL_NUM_PIN;
 	u32 mask = GENMASK(2 * offset + 1, 2 * offset);
 
-	if (data->hwirq >= ARRAY_SIZE(gpiochip->irq_type))
+	if (data->hwirq >= AIROHA_NUM_PINS)
 		return;
 
 	regmap_clear_bits(pinctrl->regmap, gpiochip->level[index], mask);
@@ -2629,7 +2627,7 @@ static void airoha_irq_ack(struct irq_data *data)
 	u8 offset = data->hwirq % AIROHA_PIN_BANK_SIZE;
 	u8 index = data->hwirq / AIROHA_PIN_BANK_SIZE;
 
-	if (data->hwirq >= ARRAY_SIZE(gpiochip->irq_type))
+	if (data->hwirq >= AIROHA_NUM_PINS)
 		return;
 
 	regmap_write(pinctrl->regmap, gpiochip->status[index], BIT(offset));
@@ -2637,28 +2635,24 @@ static void airoha_irq_ack(struct irq_data *data)
 
 static int airoha_irq_type(struct irq_data *data, unsigned int type)
 {
-	struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
-	struct airoha_pinctrl *pinctrl = gpiochip_get_data(gc);
-	struct airoha_pinctrl_gpiochip *gpiochip = &pinctrl->gpiochip;
-
-	if (data->hwirq >= ARRAY_SIZE(gpiochip->irq_type))
+	if (data->hwirq >= AIROHA_NUM_PINS)
 		return -EINVAL;
 
 	if (type == IRQ_TYPE_NONE) {
-		gpiochip->irq_type[data->hwirq] = IRQ_TYPE_NONE;
+		irqd_set_trigger_type(data, type);
 		irq_set_handler_locked(data, handle_bad_irq);
 
 		return 0;
 	}
 
 	if (type == IRQ_TYPE_PROBE) {
-		if (gpiochip->irq_type[data->hwirq])
+		if (irqd_get_trigger_type(data))
 			return 0;
 
 		type = IRQ_TYPE_EDGE_BOTH;
 	}
 
-	gpiochip->irq_type[data->hwirq] = type & IRQ_TYPE_SENSE_MASK;
+	irqd_set_trigger_type(data, type);
 	if (type & IRQ_TYPE_EDGE_BOTH)
 		irq_set_handler_locked(data, handle_edge_irq);
 	else
-- 
2.53.0

Re: [PATCH v7 18/34] pinctrl: airoha: remove not needed irq_type[] array

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:

Pre-existing issues:
- [High] The irq_chip callbacks (mask, unmask, ack) call regmap functions on a regmap that uses a sleepable spinlock, leading to a sleeping in atomic bug on PREEMPT_RT.
--

--- Patch [18]: [PATCH v7 18/34] pinctrl: airoha: remove not needed irq_type[] array ---
commit 36bbed24ea5a5464c148e69474b3311bae84ccc0
Author: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>

pinctrl: airoha: remove not needed irq_type[] array

irq_type[] array inside airoha_pinctrl_gpiochip structure is not
actually necessary. Use trigger type from 'struct irq_data' instead.

> diff --git a/drivers/pinctrl/airoha/pinctrl-airoha.c b/drivers/pinctrl/airoha/pinctrl-airoha.c
> index 0a865cf0c2728..6d4b282c21eaf 100644
> --- a/drivers/pinctrl/airoha/pinctrl-airoha.c
> +++ b/drivers/pinctrl/airoha/pinctrl-airoha.c

[ ... ]

> @@ -2613,7 +2611,7 @@ static void airoha_irq_mask(struct irq_data *data)
>  	u8 index = data->hwirq / AIROHA_REG_GPIOCTRL_NUM_PIN;
>  	u32 mask = GENMASK(2 * offset + 1, 2 * offset);
>  
> -	if (data->hwirq >= ARRAY_SIZE(gpiochip->irq_type))
> +	if (data->hwirq >= AIROHA_NUM_PINS)
>  		return;
>  
>  	regmap_clear_bits(pinctrl->regmap, gpiochip->level[index], mask);

[Severity: High]
This is a pre-existing issue and was not introduced by the patch under review,
but could these regmap operations trigger a sleeping in atomic bug on preempt-rt
kernels?

The genirq core calls irq_chip callbacks such as airoha_irq_mask(),
airoha_irq_unmask(), and airoha_irq_ack() while holding the irq descriptor lock.
This lock is a raw_spinlock_t which disables interrupts and preemption.

Because pinctrl->regmap is instantiated from a syscon without setting
use_raw_spinlock = true, its internal lock defaults to a standard spinlock_t.

On preempt-rt kernels, a standard spinlock_t is an rt_mutex and can sleep.
Attempting to acquire it during regmap operations like regmap_clear_bits(),
regmap_set_bits(), and regmap_write() while holding a raw_spinlock_t will
cause a kernel panic.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260727074234.3761170-1-mikhail.kshevetskiy@iopsys.eu?part=18

Re: [PATCH v7 18/34] pinctrl: airoha: remove not needed irq_type[] array

[Lorenzo Bianconi]

[-- Attachment #1: Type: text/plain, Size: 3251 bytes --]

> irq_type[] array inside airoha_pinctrl_gpiochip structure is not
> actually necessary. Use trigger type from 'struct irq_data' instead.
> 
> Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>

Acked-by: Lorenzo Bianconi <lorenzo@kernel.org>

> ---
>  drivers/pinctrl/airoha/pinctrl-airoha.c | 22 ++++++++--------------
>  1 file changed, 8 insertions(+), 14 deletions(-)
> 
> diff --git a/drivers/pinctrl/airoha/pinctrl-airoha.c b/drivers/pinctrl/airoha/pinctrl-airoha.c
> index df3a1d7c7b571..65447d7e5965a 100644
> --- a/drivers/pinctrl/airoha/pinctrl-airoha.c
> +++ b/drivers/pinctrl/airoha/pinctrl-airoha.c
> @@ -382,8 +382,6 @@ struct airoha_pinctrl_gpiochip {
>  	const u32 *status;
>  	const u32 *level;
>  	const u32 *edge;
> -
> -	u32 irq_type[AIROHA_NUM_PINS];
>  };
>  
>  struct airoha_pinctrl_confs_info {
> @@ -2577,11 +2575,11 @@ static void airoha_irq_unmask(struct irq_data *data)
>  	u32 mask = GENMASK(2 * offset + 1, 2 * offset);
>  	u32 val = BIT(2 * offset);
>  
> -	if (WARN_ON_ONCE(data->hwirq >= ARRAY_SIZE(gpiochip->irq_type)))
> +	if (WARN_ON_ONCE(data->hwirq >= AIROHA_NUM_PINS))
>  		return;
>  
>  	gpiochip_enable_irq(gc, irqd_to_hwirq(data));
> -	switch (gpiochip->irq_type[data->hwirq]) {
> +	switch (irqd_get_trigger_type(data)) {
>  	case IRQ_TYPE_LEVEL_LOW:
>  		val = val << 1;
>  		fallthrough;
> @@ -2613,7 +2611,7 @@ static void airoha_irq_mask(struct irq_data *data)
>  	u8 index = data->hwirq / AIROHA_REG_GPIOCTRL_NUM_PIN;
>  	u32 mask = GENMASK(2 * offset + 1, 2 * offset);
>  
> -	if (data->hwirq >= ARRAY_SIZE(gpiochip->irq_type))
> +	if (data->hwirq >= AIROHA_NUM_PINS)
>  		return;
>  
>  	regmap_clear_bits(pinctrl->regmap, gpiochip->level[index], mask);
> @@ -2629,7 +2627,7 @@ static void airoha_irq_ack(struct irq_data *data)
>  	u8 offset = data->hwirq % AIROHA_PIN_BANK_SIZE;
>  	u8 index = data->hwirq / AIROHA_PIN_BANK_SIZE;
>  
> -	if (data->hwirq >= ARRAY_SIZE(gpiochip->irq_type))
> +	if (data->hwirq >= AIROHA_NUM_PINS)
>  		return;
>  
>  	regmap_write(pinctrl->regmap, gpiochip->status[index], BIT(offset));
> @@ -2637,28 +2635,24 @@ static void airoha_irq_ack(struct irq_data *data)
>  
>  static int airoha_irq_type(struct irq_data *data, unsigned int type)
>  {
> -	struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
> -	struct airoha_pinctrl *pinctrl = gpiochip_get_data(gc);
> -	struct airoha_pinctrl_gpiochip *gpiochip = &pinctrl->gpiochip;
> -
> -	if (data->hwirq >= ARRAY_SIZE(gpiochip->irq_type))
> +	if (data->hwirq >= AIROHA_NUM_PINS)
>  		return -EINVAL;
>  
>  	if (type == IRQ_TYPE_NONE) {
> -		gpiochip->irq_type[data->hwirq] = IRQ_TYPE_NONE;
> +		irqd_set_trigger_type(data, type);
>  		irq_set_handler_locked(data, handle_bad_irq);
>  
>  		return 0;
>  	}
>  
>  	if (type == IRQ_TYPE_PROBE) {
> -		if (gpiochip->irq_type[data->hwirq])
> +		if (irqd_get_trigger_type(data))
>  			return 0;
>  
>  		type = IRQ_TYPE_EDGE_BOTH;
>  	}
>  
> -	gpiochip->irq_type[data->hwirq] = type & IRQ_TYPE_SENSE_MASK;
> +	irqd_set_trigger_type(data, type);
>  	if (type & IRQ_TYPE_EDGE_BOTH)
>  		irq_set_handler_locked(data, handle_edge_irq);
>  	else
> -- 
> 2.53.0
> 

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]

[PATCH v7 19/34] pinctrl: airoha: move common definitions to the separate header

[Mikhail Kshevetskiy]

Let's move the SoC independent definitions and declarations of structures
required for Airoha SoC-specific pinctrl drivers to a common header. Later
we'll have several SoC-specific drivers, so this step is necessary.

Also move GPIO related register addresses. It's not changed across en7523/
an7581/an7583 chips and will be used by common gpio code.

We will not move to the common header file other register addresses,
register bitfields definitions and macroses that use SoC specific
information. We will keep SoC specific definitions inside SoC specific
files.

No functional changes.

Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
---
 drivers/pinctrl/airoha/airoha-common.h  | 163 ++++++++++
 drivers/pinctrl/airoha/pinctrl-airoha.c | 414 ++++++++----------------
 2 files changed, 305 insertions(+), 272 deletions(-)
 create mode 100644 drivers/pinctrl/airoha/airoha-common.h

diff --git a/drivers/pinctrl/airoha/airoha-common.h b/drivers/pinctrl/airoha/airoha-common.h
new file mode 100644
index 0000000000000..40d7e515c09eb
--- /dev/null
+++ b/drivers/pinctrl/airoha/airoha-common.h
@@ -0,0 +1,163 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Author: Lorenzo Bianconi <lorenzo@kernel.org>
+ * Author: Benjamin Larsson <benjamin.larsson@genexis.eu>
+ * Author: Markus Gothe <markus.gothe@genexis.eu>
+ */
+
+#ifndef __AIROHA_COMMON_HEADER__
+#define __AIROHA_COMMON_HEADER__
+
+#include <dt-bindings/pinctrl/mt65xx.h>
+#include <linux/bitfield.h>
+#include <linux/bits.h>
+#include <linux/cleanup.h>
+#include <linux/gpio/driver.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/irqdomain.h>
+#include <linux/mfd/syscon.h>
+#include <linux/of.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <linux/pinctrl/consumer.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/pinctrl/pinconf.h>
+#include <linux/pinctrl/pinconf-generic.h>
+#include <linux/pinctrl/pinmux.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/types.h>
+
+#include "../core.h"
+#include "../pinconf.h"
+#include "../pinmux.h"
+
+/* GPIOs */
+#define REG_GPIO_CTRL				0x0000
+#define REG_GPIO_DATA				0x0004
+#define REG_GPIO_INT				0x0008
+#define REG_GPIO_INT_EDGE			0x000c
+#define REG_GPIO_INT_LEVEL			0x0010
+#define REG_GPIO_OE				0x0014
+#define REG_GPIO_CTRL1				0x0020
+#define REG_GPIO_CTRL2				0x0060
+#define REG_GPIO_CTRL3				0x0064
+#define REG_GPIO_DATA1				0x0070
+#define REG_GPIO_OE1				0x0078
+#define REG_GPIO_INT1				0x007c
+#define REG_GPIO_INT_EDGE1			0x0080
+#define REG_GPIO_INT_EDGE2			0x0084
+#define REG_GPIO_INT_EDGE3			0x0088
+#define REG_GPIO_INT_LEVEL1			0x008c
+#define REG_GPIO_INT_LEVEL2			0x0090
+#define REG_GPIO_INT_LEVEL3			0x0094
+
+#define AIROHA_NUM_PINS				64
+#define AIROHA_PIN_BANK_SIZE			(AIROHA_NUM_PINS / 2)
+#define AIROHA_REG_GPIOCTRL_NUM_PIN		(AIROHA_NUM_PINS / 4)
+
+#define PINCTRL_PIN_GROUP(id, table)					\
+	PINCTRL_PINGROUP(id, table##_pins, ARRAY_SIZE(table##_pins))
+
+#define PINCTRL_FUNC_DESC(id, table)					\
+	{								\
+		.desc = PINCTRL_PINFUNCTION(id, table##_groups,	\
+					    ARRAY_SIZE(table##_groups)),\
+		.groups = table##_func_group,				\
+		.group_size = ARRAY_SIZE(table##_func_group),		\
+	}
+
+#define PINCTRL_CONF_DESC(p, offset, mask)				\
+	{								\
+		.pin = p,						\
+		.reg = { offset, mask },				\
+	}
+
+struct airoha_pinctrl_reg {
+	u32 offset;
+	u32 mask;
+};
+
+enum airoha_pinctrl_mux_func {
+	AIROHA_FUNC_MUX,
+	AIROHA_FUNC_PWM_MUX,
+	AIROHA_FUNC_PWM_EXT_MUX,
+};
+
+struct airoha_pinctrl_func_group {
+	const char *name;
+	struct {
+		enum airoha_pinctrl_mux_func mux;
+		u32 offset;
+		u32 mask;
+		u32 val;
+	} regmap[2];
+	int regmap_size;
+};
+
+struct airoha_pinctrl_func {
+	const struct pinfunction desc;
+	const struct airoha_pinctrl_func_group *groups;
+	u8 group_size;
+};
+
+struct airoha_pinctrl_conf {
+	u32 pin;
+	struct airoha_pinctrl_reg reg;
+};
+
+struct airoha_pinctrl_gpiochip {
+	struct gpio_chip chip;
+
+	/* gpio */
+	const u32 *data;
+	const u32 *dir;
+	const u32 *out;
+	/* irq */
+	const u32 *status;
+	const u32 *level;
+	const u32 *edge;
+};
+
+struct airoha_pinctrl_confs_info {
+	const struct airoha_pinctrl_conf *confs;
+	unsigned int num_confs;
+};
+
+enum airoha_pinctrl_confs_type {
+	AIROHA_PINCTRL_CONFS_PULLUP,
+	AIROHA_PINCTRL_CONFS_PULLDOWN,
+	AIROHA_PINCTRL_CONFS_DRIVE_E2,
+	AIROHA_PINCTRL_CONFS_DRIVE_E4,
+	AIROHA_PINCTRL_CONFS_PCIE_RST_OD,
+
+	AIROHA_PINCTRL_CONFS_MAX,
+};
+
+struct airoha_pinctrl {
+	struct pinctrl_dev *ctrl;
+
+	struct pinctrl_desc desc;
+	const struct pingroup *grps;
+	const struct airoha_pinctrl_func *funcs;
+	const struct airoha_pinctrl_confs_info *confs_info;
+
+	struct regmap *chip_scu;
+	struct regmap *regmap;
+
+	struct airoha_pinctrl_gpiochip gpiochip;
+};
+
+struct airoha_pinctrl_match_data {
+	const struct pinctrl_pin_desc *pins;
+	const unsigned int num_pins;
+	const struct pingroup *grps;
+	const unsigned int num_grps;
+	const struct airoha_pinctrl_func *funcs;
+	const unsigned int num_funcs;
+	const struct airoha_pinctrl_confs_info confs_info[AIROHA_PINCTRL_CONFS_MAX];
+};
+
+#endif
diff --git a/drivers/pinctrl/airoha/pinctrl-airoha.c b/drivers/pinctrl/airoha/pinctrl-airoha.c
index 65447d7e5965a..f42631afc05d3 100644
--- a/drivers/pinctrl/airoha/pinctrl-airoha.c
+++ b/drivers/pinctrl/airoha/pinctrl-airoha.c
@@ -5,47 +5,7 @@
  * Author: Markus Gothe <markus.gothe@genexis.eu>
  */
 
-#include <dt-bindings/pinctrl/mt65xx.h>
-#include <linux/bitfield.h>
-#include <linux/bits.h>
-#include <linux/cleanup.h>
-#include <linux/gpio/driver.h>
-#include <linux/interrupt.h>
-#include <linux/io.h>
-#include <linux/irq.h>
-#include <linux/irqdomain.h>
-#include <linux/mfd/syscon.h>
-#include <linux/of.h>
-#include <linux/of_irq.h>
-#include <linux/of_platform.h>
-#include <linux/pinctrl/consumer.h>
-#include <linux/pinctrl/pinctrl.h>
-#include <linux/pinctrl/pinconf.h>
-#include <linux/pinctrl/pinconf-generic.h>
-#include <linux/pinctrl/pinmux.h>
-#include <linux/platform_device.h>
-#include <linux/regmap.h>
-
-#include "../core.h"
-#include "../pinconf.h"
-#include "../pinmux.h"
-
-#define PINCTRL_PIN_GROUP(id, table)					\
-	PINCTRL_PINGROUP(id, table##_pins, ARRAY_SIZE(table##_pins))
-
-#define PINCTRL_FUNC_DESC(id, table)					\
-	{								\
-		.desc = PINCTRL_PINFUNCTION(id, table##_groups,	\
-					    ARRAY_SIZE(table##_groups)),\
-		.groups = table##_func_group,				\
-		.group_size = ARRAY_SIZE(table##_func_group),		\
-	}
-
-#define PINCTRL_CONF_DESC(p, offset, mask)				\
-	{								\
-		.pin = p,						\
-		.reg = { offset, mask },				\
-	}
+#include "airoha-common.h"
 
 /* MUX */
 #define REG_GPIO_2ND_I2C_MODE			0x0214
@@ -230,6 +190,8 @@
 #define REG_GPIO_INT_LEVEL			0x0010
 #define REG_GPIO_OE				0x0014
 #define REG_GPIO_CTRL1				0x0020
+#define REG_GPIO_CTRL2				0x0060
+#define REG_GPIO_CTRL3				0x0064
 
 /* PWM MODE CONF */
 #define REG_GPIO_FLASH_MODE_CFG			0x0034
@@ -250,9 +212,6 @@
 #define GPIO1_FLASH_MODE_CFG			BIT(1)
 #define GPIO0_FLASH_MODE_CFG			BIT(0)
 
-#define REG_GPIO_CTRL2				0x0060
-#define REG_GPIO_CTRL3				0x0064
-
 /* PWM MODE CONF EXT */
 #define REG_GPIO_FLASH_MODE_CFG_EXT		0x0068
 #define GPIO51_FLASH_MODE_CFG			BIT(31)
@@ -298,9 +257,145 @@
 #define REG_GPIO_INT_LEVEL2			0x0090
 #define REG_GPIO_INT_LEVEL3			0x0094
 
-#define AIROHA_NUM_PINS				64
-#define AIROHA_PIN_BANK_SIZE			(AIROHA_NUM_PINS / 2)
-#define AIROHA_REG_GPIOCTRL_NUM_PIN		(AIROHA_NUM_PINS / 4)
+#define AIROHA_PINCTRL_GPIO(gpio, mux_val)			\
+	{							\
+		.name = (gpio),					\
+		.regmap[0] = {					\
+			AIROHA_FUNC_MUX,			\
+			REG_GPIO_PON_MODE,			\
+			(mux_val),				\
+			(mux_val)				\
+		},						\
+		.regmap_size = 1,				\
+	}
+
+#define AIROHA_PINCTRL_GPIO_EXT(gpio, mux_val, smux_val)	\
+	{							\
+		.name = (gpio),					\
+		.regmap[0] = {					\
+			AIROHA_FUNC_PWM_EXT_MUX,		\
+			REG_GPIO_FLASH_MODE_CFG_EXT,		\
+			(mux_val),				\
+			0					\
+		},						\
+		.regmap[1] = {					\
+			AIROHA_FUNC_MUX,			\
+			REG_GPIO_PON_MODE,			\
+			(smux_val),				\
+			(smux_val)				\
+		},						\
+		.regmap_size = 2,				\
+	}
+
+/* PWM */
+#define AIROHA_PINCTRL_PWM(gpio, mux_val)		\
+	{						\
+		.name = (gpio),				\
+		.regmap[0] = {				\
+			AIROHA_FUNC_PWM_MUX,		\
+			REG_GPIO_FLASH_MODE_CFG,	\
+			(mux_val),			\
+			(mux_val)			\
+		},					\
+		.regmap_size = 1,			\
+	}
+
+#define AIROHA_PINCTRL_PWM_EXT(gpio, mux_val)		\
+	{						\
+		.name = (gpio),				\
+		.regmap[0] = {				\
+			AIROHA_FUNC_PWM_EXT_MUX,	\
+			REG_GPIO_FLASH_MODE_CFG_EXT,	\
+			(mux_val),			\
+			(mux_val)			\
+		},					\
+		.regmap_size = 1,			\
+	}
+
+#define AIROHA_PINCTRL_PWM_EXT_SEC(gpio, mux_val, smux_val)	\
+	{							\
+		.name = (gpio),					\
+		.regmap[0] = {					\
+			AIROHA_FUNC_PWM_EXT_MUX,		\
+			REG_GPIO_FLASH_MODE_CFG_EXT,		\
+			(mux_val),				\
+			(mux_val)				\
+		},						\
+		.regmap[1] = {					\
+			AIROHA_FUNC_MUX,			\
+			REG_GPIO_PON_MODE,			\
+			(smux_val),				\
+			(smux_val)				\
+		},						\
+		.regmap_size = 2,				\
+	}
+
+#define AIROHA_PINCTRL_PHY_LED0(gpio, mux_val, map_mask, map_val)	\
+	{								\
+		.name = (gpio),						\
+		.regmap[0] = {						\
+			AIROHA_FUNC_MUX,				\
+			REG_GPIO_2ND_I2C_MODE,				\
+			(mux_val),					\
+			(mux_val),					\
+		},							\
+		.regmap[1] = {						\
+			AIROHA_FUNC_MUX,				\
+			REG_LAN_LED0_MAPPING,				\
+			(map_mask),					\
+			(map_val),					\
+		},							\
+		.regmap_size = 2,					\
+	}
+
+#define AIROHA_PINCTRL_PHY_LED1(gpio, mux_val, map_mask, map_val)	\
+	{								\
+		.name = (gpio),						\
+		.regmap[0] = {						\
+			AIROHA_FUNC_MUX,				\
+			REG_GPIO_2ND_I2C_MODE,				\
+			(mux_val),					\
+			(mux_val),					\
+		},							\
+		.regmap[1] = {						\
+			AIROHA_FUNC_MUX,				\
+			REG_LAN_LED1_MAPPING,				\
+			(map_mask),					\
+			(map_val),					\
+		},							\
+		.regmap_size = 2,					\
+	}
+
+#define airoha_pinctrl_get_pullup_conf(pinctrl, pin, val)			\
+	airoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_PULLUP,		\
+				(pin), (val))
+#define airoha_pinctrl_get_pulldown_conf(pinctrl, pin, val)			\
+	airoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_PULLDOWN,	\
+				(pin), (val))
+#define airoha_pinctrl_get_drive_e2_conf(pinctrl, pin, val)			\
+	airoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_DRIVE_E2,	\
+				(pin), (val))
+#define airoha_pinctrl_get_drive_e4_conf(pinctrl, pin, val)			\
+	airoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_DRIVE_E4,	\
+				(pin), (val))
+#define airoha_pinctrl_get_pcie_rst_od_conf(pinctrl, pin, val)			\
+	airoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_PCIE_RST_OD,	\
+				(pin), (val))
+#define airoha_pinctrl_set_pullup_conf(pinctrl, pin, val)			\
+	airoha_pinctrl_set_conf((pinctrl), AIROHA_PINCTRL_CONFS_PULLUP,		\
+				(pin), (val))
+#define airoha_pinctrl_set_pulldown_conf(pinctrl, pin, val)			\
+	airoha_pinctrl_set_conf((pinctrl), AIROHA_PINCTRL_CONFS_PULLDOWN,	\
+				(pin), (val))
+#define airoha_pinctrl_set_drive_e2_conf(pinctrl, pin, val)			\
+	airoha_pinctrl_set_conf((pinctrl), AIROHA_PINCTRL_CONFS_DRIVE_E2,	\
+				(pin), (val))
+#define airoha_pinctrl_set_drive_e4_conf(pinctrl, pin, val)			\
+	airoha_pinctrl_set_conf((pinctrl), AIROHA_PINCTRL_CONFS_DRIVE_E4,	\
+				(pin), (val))
+#define airoha_pinctrl_set_pcie_rst_od_conf(pinctrl, pin, val)			\
+	airoha_pinctrl_set_conf((pinctrl), AIROHA_PINCTRL_CONFS_PCIE_RST_OD,	\
+				(pin), (val))
 
 static const u32 gpio_data_regs[] = {
 	REG_GPIO_DATA,
@@ -338,91 +433,6 @@ static const u32 irq_edge_regs[] = {
 	REG_GPIO_INT_EDGE3
 };
 
-struct airoha_pinctrl_reg {
-	u32 offset;
-	u32 mask;
-};
-
-enum airoha_pinctrl_mux_func {
-	AIROHA_FUNC_MUX,
-	AIROHA_FUNC_PWM_MUX,
-	AIROHA_FUNC_PWM_EXT_MUX,
-};
-
-struct airoha_pinctrl_func_group {
-	const char *name;
-	struct {
-		enum airoha_pinctrl_mux_func mux;
-		u32 offset;
-		u32 mask;
-		u32 val;
-	} regmap[2];
-	int regmap_size;
-};
-
-struct airoha_pinctrl_func {
-	const struct pinfunction desc;
-	const struct airoha_pinctrl_func_group *groups;
-	u8 group_size;
-};
-
-struct airoha_pinctrl_conf {
-	u32 pin;
-	struct airoha_pinctrl_reg reg;
-};
-
-struct airoha_pinctrl_gpiochip {
-	struct gpio_chip chip;
-
-	/* gpio */
-	const u32 *data;
-	const u32 *dir;
-	const u32 *out;
-	/* irq */
-	const u32 *status;
-	const u32 *level;
-	const u32 *edge;
-};
-
-struct airoha_pinctrl_confs_info {
-	const struct airoha_pinctrl_conf *confs;
-	unsigned int num_confs;
-};
-
-enum airoha_pinctrl_confs_type {
-	AIROHA_PINCTRL_CONFS_PULLUP,
-	AIROHA_PINCTRL_CONFS_PULLDOWN,
-	AIROHA_PINCTRL_CONFS_DRIVE_E2,
-	AIROHA_PINCTRL_CONFS_DRIVE_E4,
-	AIROHA_PINCTRL_CONFS_PCIE_RST_OD,
-
-	AIROHA_PINCTRL_CONFS_MAX,
-};
-
-struct airoha_pinctrl {
-	struct pinctrl_dev *ctrl;
-
-	struct pinctrl_desc desc;
-	const struct pingroup *grps;
-	const struct airoha_pinctrl_func *funcs;
-	const struct airoha_pinctrl_confs_info *confs_info;
-
-	struct regmap *chip_scu;
-	struct regmap *regmap;
-
-	struct airoha_pinctrl_gpiochip gpiochip;
-};
-
-struct airoha_pinctrl_match_data {
-	const struct pinctrl_pin_desc *pins;
-	const unsigned int num_pins;
-	const struct pingroup *grps;
-	const unsigned int num_grps;
-	const struct airoha_pinctrl_func *funcs;
-	const unsigned int num_funcs;
-	const struct airoha_pinctrl_confs_info confs_info[AIROHA_PINCTRL_CONFS_MAX];
-};
-
 static struct pinctrl_pin_desc en7581_pinctrl_pins[] = {
 	PINCTRL_PIN(0, "uart1_txd"),
 	PINCTRL_PIN(1, "uart1_rxd"),
@@ -1437,36 +1447,6 @@ static const struct airoha_pinctrl_func_group pnand_func_group[] = {
 	},
 };
 
-#define AIROHA_PINCTRL_GPIO(gpio, mux_val)			\
-	{							\
-		.name = (gpio),					\
-		.regmap[0] = {					\
-			AIROHA_FUNC_MUX,			\
-			REG_GPIO_PON_MODE,			\
-			(mux_val),				\
-			(mux_val)				\
-		},						\
-		.regmap_size = 1,				\
-	}
-
-#define AIROHA_PINCTRL_GPIO_EXT(gpio, mux_val, smux_val)	\
-	{							\
-		.name = (gpio),					\
-		.regmap[0] = {					\
-			AIROHA_FUNC_PWM_EXT_MUX,		\
-			REG_GPIO_FLASH_MODE_CFG_EXT,		\
-			(mux_val),				\
-			0					\
-		},						\
-		.regmap[1] = {					\
-			AIROHA_FUNC_MUX,			\
-			REG_GPIO_PON_MODE,			\
-			(smux_val),				\
-			(smux_val)				\
-		},						\
-		.regmap_size = 2,				\
-	}
-
 static const struct airoha_pinctrl_func_group gpio_func_group[] = {
 	AIROHA_PINCTRL_GPIO_EXT("gpio47", GPIO47_FLASH_MODE_CFG,
 				GPIO_PCIE_RESET0_MASK),
@@ -1559,49 +1539,6 @@ static const struct airoha_pinctrl_func_group an7583_pcie_reset_func_group[] = {
 	},
 };
 
-/* PWM */
-#define AIROHA_PINCTRL_PWM(gpio, mux_val)		\
-	{						\
-		.name = (gpio),				\
-		.regmap[0] = {				\
-			AIROHA_FUNC_PWM_MUX,		\
-			REG_GPIO_FLASH_MODE_CFG,	\
-			(mux_val),			\
-			(mux_val)			\
-		},					\
-		.regmap_size = 1,			\
-	}						\
-
-#define AIROHA_PINCTRL_PWM_EXT(gpio, mux_val)		\
-	{						\
-		.name = (gpio),				\
-		.regmap[0] = {				\
-			AIROHA_FUNC_PWM_EXT_MUX,	\
-			REG_GPIO_FLASH_MODE_CFG_EXT,	\
-			(mux_val),			\
-			(mux_val)			\
-		},					\
-		.regmap_size = 1,			\
-	}						\
-
-#define AIROHA_PINCTRL_PWM_EXT_SEC(gpio, mux_val, smux_val)	\
-	{							\
-		.name = (gpio),					\
-		.regmap[0] = {					\
-			AIROHA_FUNC_PWM_EXT_MUX,		\
-			REG_GPIO_FLASH_MODE_CFG_EXT,		\
-			(mux_val),				\
-			(mux_val)				\
-		},						\
-		.regmap[1] = {					\
-			AIROHA_FUNC_MUX,			\
-			REG_GPIO_PON_MODE,			\
-			(smux_val),				\
-			(smux_val)				\
-		},						\
-		.regmap_size = 2,				\
-	}
-
 static const struct airoha_pinctrl_func_group pwm_func_group[] = {
 	AIROHA_PINCTRL_PWM("gpio0", GPIO0_FLASH_MODE_CFG),
 	AIROHA_PINCTRL_PWM("gpio1", GPIO1_FLASH_MODE_CFG),
@@ -1718,42 +1655,6 @@ static const struct airoha_pinctrl_func_group an7583_pwm_func_group[] = {
 				   AN7583_MDC_0_GPIO_MODE_MASK),
 };
 
-#define AIROHA_PINCTRL_PHY_LED0(gpio, mux_val, map_mask, map_val)	\
-	{								\
-		.name = (gpio),						\
-		.regmap[0] = {						\
-			AIROHA_FUNC_MUX,				\
-			REG_GPIO_2ND_I2C_MODE,				\
-			(mux_val),					\
-			(mux_val),					\
-		},							\
-		.regmap[1] = {						\
-			AIROHA_FUNC_MUX,				\
-			REG_LAN_LED0_MAPPING,				\
-			(map_mask),					\
-			(map_val),					\
-		},							\
-		.regmap_size = 2,					\
-	}
-
-#define AIROHA_PINCTRL_PHY_LED1(gpio, mux_val, map_mask, map_val)	\
-	{								\
-		.name = (gpio),						\
-		.regmap[0] = {						\
-			AIROHA_FUNC_MUX,				\
-			REG_GPIO_2ND_I2C_MODE,				\
-			(mux_val),					\
-			(mux_val),					\
-		},							\
-		.regmap[1] = {						\
-			AIROHA_FUNC_MUX,				\
-			REG_LAN_LED1_MAPPING,				\
-			(map_mask),					\
-			(map_val),					\
-		},							\
-		.regmap_size = 2,					\
-	}
-
 static const struct airoha_pinctrl_func_group phy1_led0_func_group[] = {
 	AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK,
 				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),
@@ -2883,37 +2784,6 @@ static int airoha_pinctrl_set_conf(struct airoha_pinctrl *pinctrl,
 	return 0;
 }
 
-#define airoha_pinctrl_get_pullup_conf(pinctrl, pin, val)			\
-	airoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_PULLUP,		\
-				(pin), (val))
-#define airoha_pinctrl_get_pulldown_conf(pinctrl, pin, val)			\
-	airoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_PULLDOWN,	\
-				(pin), (val))
-#define airoha_pinctrl_get_drive_e2_conf(pinctrl, pin, val)			\
-	airoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_DRIVE_E2,	\
-				(pin), (val))
-#define airoha_pinctrl_get_drive_e4_conf(pinctrl, pin, val)			\
-	airoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_DRIVE_E4,	\
-				(pin), (val))
-#define airoha_pinctrl_get_pcie_rst_od_conf(pinctrl, pin, val)			\
-	airoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_PCIE_RST_OD,	\
-				(pin), (val))
-#define airoha_pinctrl_set_pullup_conf(pinctrl, pin, val)			\
-	airoha_pinctrl_set_conf((pinctrl), AIROHA_PINCTRL_CONFS_PULLUP,		\
-				(pin), (val))
-#define airoha_pinctrl_set_pulldown_conf(pinctrl, pin, val)			\
-	airoha_pinctrl_set_conf((pinctrl), AIROHA_PINCTRL_CONFS_PULLDOWN,	\
-				(pin), (val))
-#define airoha_pinctrl_set_drive_e2_conf(pinctrl, pin, val)			\
-	airoha_pinctrl_set_conf((pinctrl), AIROHA_PINCTRL_CONFS_DRIVE_E2,	\
-				(pin), (val))
-#define airoha_pinctrl_set_drive_e4_conf(pinctrl, pin, val)			\
-	airoha_pinctrl_set_conf((pinctrl), AIROHA_PINCTRL_CONFS_DRIVE_E4,	\
-				(pin), (val))
-#define airoha_pinctrl_set_pcie_rst_od_conf(pinctrl, pin, val)			\
-	airoha_pinctrl_set_conf((pinctrl), AIROHA_PINCTRL_CONFS_PCIE_RST_OD,	\
-				(pin), (val))
-
 static int airoha_pinconf_get_direction(struct pinctrl_dev *pctrl_dev, u32 p)
 {
 	struct airoha_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
-- 
2.53.0

Re: [PATCH v7 19/34] pinctrl: airoha: move common definitions to the separate header

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] The commit states its intent to move GPIO related register addresses to `airoha-common.h`, but it only copied them, failing to delete the original macro definitions from `pinctrl-airoha.c`.
--

--- Patch [19]: [PATCH v7 19/34] pinctrl: airoha: move common definitions to the separate header ---
commit e0116c883a65c06680c853edf3abcd0498eff60d
Author: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>

pinctrl: airoha: move common definitions to the separate header

Let's move the SoC independent definitions and declarations of structures
required for Airoha SoC-specific pinctrl drivers to a common header. Later
we'll have several SoC-specific drivers, so this step is necessary.

Also move GPIO related register addresses. It's not changed across en7523/
an7581/an7583 chips and will be used by common gpio code.

> diff --git a/drivers/pinctrl/airoha/airoha-common.h b/drivers/pinctrl/airoha/airoha-common.h
> new file mode 100644
> index 0000000000000..40d7e515c09eb
> --- /dev/null
> +++ b/drivers/pinctrl/airoha/airoha-common.h
[ ... ]
> +/* GPIOs */
> +#define REG_GPIO_CTRL				0x0000
> +#define REG_GPIO_DATA				0x0004
> +#define REG_GPIO_INT				0x0008
> +#define REG_GPIO_INT_EDGE			0x000c
> +#define REG_GPIO_INT_LEVEL			0x0010
> +#define REG_GPIO_OE				0x0014
> +#define REG_GPIO_CTRL1				0x0020
> +#define REG_GPIO_CTRL2				0x0060
> +#define REG_GPIO_CTRL3				0x0064

[ ... ]

> diff --git a/drivers/pinctrl/airoha/pinctrl-airoha.c b/drivers/pinctrl/airoha/pinctrl-airoha.c
> index 6d4b282c21eaf..7cbedb370c977 100644
> --- a/drivers/pinctrl/airoha/pinctrl-airoha.c
> +++ b/drivers/pinctrl/airoha/pinctrl-airoha.c
[ ... ]
> @@ -230,6 +190,8 @@
>  #define REG_GPIO_INT_LEVEL			0x0010
>  #define REG_GPIO_OE				0x0014
>  #define REG_GPIO_CTRL1				0x0020
> +#define REG_GPIO_CTRL2				0x0060
> +#define REG_GPIO_CTRL3				0x0064

[Severity: Low]
The commit message mentions moving the GPIO related register addresses to
airoha-common.h, but the original definitions were left in pinctrl-airoha.c.
Could these duplicate definitions be removed from pinctrl-airoha.c to
complete the move as stated in the commit message?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260727074234.3761170-1-mikhail.kshevetskiy@iopsys.eu?part=19

[PATCH v7 20/34] pinctrl: airoha: split driver on shared code and SoC specific drivers

[Mikhail Kshevetskiy]

Split combined an7581/an7583 source file on a
 * shared pinctrl code (pinctrl-airoha.c)
 * an7581 specific pinctrl driver (pinctrl-an7581.c)
 * an7583 specific pinctrl driver (pinctrl-an7583.c)

Ininialization code was adapted a bit to work properly for shared
and SoC specific cases.

Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
---
 drivers/pinctrl/airoha/Kconfig          |   24 +-
 drivers/pinctrl/airoha/Makefile         |    5 +
 drivers/pinctrl/airoha/airoha-common.h  |    5 +
 drivers/pinctrl/airoha/pinctrl-airoha.c | 2382 +----------------------
 drivers/pinctrl/airoha/pinctrl-an7581.c | 1486 ++++++++++++++
 drivers/pinctrl/airoha/pinctrl-an7583.c | 1456 ++++++++++++++
 6 files changed, 2984 insertions(+), 2374 deletions(-)
 create mode 100644 drivers/pinctrl/airoha/pinctrl-an7581.c
 create mode 100644 drivers/pinctrl/airoha/pinctrl-an7583.c

diff --git a/drivers/pinctrl/airoha/Kconfig b/drivers/pinctrl/airoha/Kconfig
index 03adaeae8fc3a..dae6608bc72dd 100644
--- a/drivers/pinctrl/airoha/Kconfig
+++ b/drivers/pinctrl/airoha/Kconfig
@@ -3,9 +3,9 @@ menu "Airoha pinctrl drivers"
 	depends on ARCH_AIROHA || COMPILE_TEST
 
 config PINCTRL_AIROHA
-	tristate "Airoha EN7581 pin control"
+	tristate "Airoha pin control"
 	depends on OF
-	depends on ARM64 || COMPILE_TEST
+	depends on ARCH_AIROHA || COMPILE_TEST
 	select PINMUX
 	select GENERIC_PINCONF
 	select GENERIC_PINCTRL_GROUPS
@@ -13,8 +13,26 @@ config PINCTRL_AIROHA
 	select GPIOLIB
 	select GPIOLIB_IRQCHIP
 	select REGMAP_MMIO
+	imply PINCTRL_AIROHA_AN7581
+	imply PINCTRL_AIROHA_AN7583
+	help
+	  Shared pin controller and gpio driver code for different
+	  Airoha SoCs.
+
+config PINCTRL_AIROHA_AN7581
+	tristate "AN7581 pinctrl"
+	depends on ARM64 || COMPILE_TEST
+	depends on PINCTRL_AIROHA
+	help
+	  Say yes here to support pin controller and gpio driver
+	  on Airoha AN7581, AN7566, AN7551 and other compatible SoCs.
+
+config PINCTRL_AIROHA_AN7583
+	tristate "AN7583 pinctrl"
+	depends on ARM64 || COMPILE_TEST
+	depends on PINCTRL_AIROHA
 	help
 	  Say yes here to support pin controller and gpio driver
-	  on Airoha EN7581 SoC.
+	  on Airoha AN7583, AN7553, AN7567 and other compatible SoCs.
 
 endmenu
diff --git a/drivers/pinctrl/airoha/Makefile b/drivers/pinctrl/airoha/Makefile
index a25b744dd7a8a..cfd68c45ae0f0 100644
--- a/drivers/pinctrl/airoha/Makefile
+++ b/drivers/pinctrl/airoha/Makefile
@@ -1,3 +1,8 @@
 # SPDX-License-Identifier: GPL-2.0
 
+# shared code
 obj-$(CONFIG_PINCTRL_AIROHA)		+= pinctrl-airoha.o
+
+# SoC drivers
+obj-$(CONFIG_PINCTRL_AIROHA_AN7581)	+= pinctrl-an7581.o
+obj-$(CONFIG_PINCTRL_AIROHA_AN7583)	+= pinctrl-an7583.o
diff --git a/drivers/pinctrl/airoha/airoha-common.h b/drivers/pinctrl/airoha/airoha-common.h
index 40d7e515c09eb..f73e90ca860f4 100644
--- a/drivers/pinctrl/airoha/airoha-common.h
+++ b/drivers/pinctrl/airoha/airoha-common.h
@@ -148,9 +148,12 @@ struct airoha_pinctrl {
 	struct regmap *regmap;
 
 	struct airoha_pinctrl_gpiochip gpiochip;
+	struct irq_chip gpio_irq_chip;
 };
 
 struct airoha_pinctrl_match_data {
+	const char *pinctrl_name;
+	struct module *pinctrl_owner;
 	const struct pinctrl_pin_desc *pins;
 	const unsigned int num_pins;
 	const struct pingroup *grps;
@@ -160,4 +163,6 @@ struct airoha_pinctrl_match_data {
 	const struct airoha_pinctrl_confs_info confs_info[AIROHA_PINCTRL_CONFS_MAX];
 };
 
+int airoha_pinctrl_probe(struct platform_device *pdev);
+
 #endif
diff --git a/drivers/pinctrl/airoha/pinctrl-airoha.c b/drivers/pinctrl/airoha/pinctrl-airoha.c
index f42631afc05d3..a46596eb1493b 100644
--- a/drivers/pinctrl/airoha/pinctrl-airoha.c
+++ b/drivers/pinctrl/airoha/pinctrl-airoha.c
@@ -7,365 +7,6 @@
 
 #include "airoha-common.h"
 
-/* MUX */
-#define REG_GPIO_2ND_I2C_MODE			0x0214
-#define GPIO_MDC_IO_MASTER_MODE_MASK		BIT(14)
-#define GPIO_I2C_MASTER_MODE_MODE		BIT(13)
-#define GPIO_I2S_MODE_MASK			BIT(12)
-#define GPIO_I2C_SLAVE_MODE_MODE		BIT(11)
-#define GPIO_LAN3_LED1_MODE_MASK		BIT(10)
-#define GPIO_LAN3_LED0_MODE_MASK		BIT(9)
-#define GPIO_LAN2_LED1_MODE_MASK		BIT(8)
-#define GPIO_LAN2_LED0_MODE_MASK		BIT(7)
-#define GPIO_LAN1_LED1_MODE_MASK		BIT(6)
-#define GPIO_LAN1_LED0_MODE_MASK		BIT(5)
-#define GPIO_LAN0_LED1_MODE_MASK		BIT(4)
-#define GPIO_LAN0_LED0_MODE_MASK		BIT(3)
-#define PON_TOD_1PPS_MODE_MASK			BIT(2)
-#define GSW_TOD_1PPS_MODE_MASK			BIT(1)
-#define GPIO_2ND_I2C_MODE_MASK			BIT(0)
-
-#define REG_GPIO_SPI_CS1_MODE			0x0218
-#define GPIO_PCM_SPI_CS4_MODE_MASK		BIT(21)
-#define GPIO_PCM_SPI_CS3_MODE_MASK		BIT(20)
-#define GPIO_PCM_SPI_CS2_MODE_P156_MASK		BIT(19)
-#define GPIO_PCM_SPI_CS2_MODE_P128_MASK		BIT(18)
-#define AN7583_GPIO_PCM_SPI_CS2_MODE_MASK	BIT(18)
-#define GPIO_PCM_SPI_CS1_MODE_MASK		BIT(17)
-#define GPIO_PCM_SPI_MODE_MASK			BIT(16)
-#define GPIO_PCM2_MODE_MASK			BIT(13)
-#define GPIO_PCM1_MODE_MASK			BIT(12)
-#define GPIO_PCM_INT_MODE_MASK			BIT(9)
-#define GPIO_PCM_RESET_MODE_MASK		BIT(8)
-#define GPIO_SPI_QUAD_MODE_MASK			BIT(4)
-#define GPIO_SPI_CS4_MODE_MASK			BIT(3)
-#define GPIO_SPI_CS3_MODE_MASK			BIT(2)
-#define GPIO_SPI_CS2_MODE_MASK			BIT(1)
-#define GPIO_SPI_CS1_MODE_MASK			BIT(0)
-
-#define REG_GPIO_PON_MODE			0x021c
-#define AN7583_MDIO_0_GPIO_MODE_MASK		BIT(26)
-#define AN7583_MDC_0_GPIO_MODE_MASK		BIT(25)
-#define AN7583_UART_RXD_GPIO_MODE_MASK		BIT(24)
-#define AN7583_UART_TXD_GPIO_MODE_MASK		BIT(23)
-#define AN7583_SPI_MISO_GPIO_MODE_MASK		BIT(22)
-#define AN7583_SPI_MOSI_GPIO_MODE_MASK		BIT(21)
-#define AN7583_SPI_CS_GPIO_MODE_MASK		BIT(20)
-#define AN7583_SPI_CLK_GPIO_MODE_MASK		BIT(19)
-#define AN7583_I2C1_SDA_GPIO_MODE_MASK		BIT(18)
-#define AN7583_I2C1_SCL_GPIO_MODE_MASK		BIT(17)
-#define AN7583_I2C0_SDA_GPIO_MODE_MASK		BIT(16)
-#define AN7583_I2C0_SCL_GPIO_MODE_MASK		BIT(15)
-#define GPIO_PARALLEL_NAND_MODE_MASK		BIT(14)
-#define GPIO_SGMII_MDIO_MODE_MASK		BIT(13)
-#define GPIO_PCIE_RESET2_MASK			BIT(12)
-#define SIPO_RCLK_MODE_MASK			BIT(11)
-#define GPIO_PCIE_RESET1_MASK			BIT(10)
-#define GPIO_PCIE_RESET0_MASK			BIT(9)
-#define GPIO_UART5_MODE_MASK			BIT(8)
-#define GPIO_UART4_MODE_MASK			BIT(7)
-#define GPIO_HSUART_CTS_RTS_MODE_MASK		BIT(6)
-#define GPIO_HSUART_MODE_MASK			BIT(5)
-#define GPIO_UART2_CTS_RTS_MODE_MASK		BIT(4)
-#define GPIO_UART2_MODE_MASK			BIT(3)
-#define GPIO_SIPO_MODE_MASK			BIT(2)
-#define GPIO_EMMC_MODE_MASK			BIT(1)
-#define GPIO_PON_MODE_MASK			BIT(0)
-
-#define REG_NPU_UART_EN				0x0224
-#define JTAG_UDI_EN_MASK			BIT(4)
-#define JTAG_DFD_EN_MASK			BIT(3)
-
-#define REG_FORCE_GPIO_EN			0x0228
-#define FORCE_GPIO_EN(n)			BIT(n)
-
-/* LED MAP */
-#define REG_LAN_LED0_MAPPING			0x027c
-#define REG_LAN_LED1_MAPPING			0x0280
-
-#define LAN4_LED_MAPPING_MASK			GENMASK(18, 16)
-#define LAN4_PHY_LED_MAP(_n)			FIELD_PREP_CONST(LAN4_LED_MAPPING_MASK, (_n))
-
-#define LAN3_LED_MAPPING_MASK			GENMASK(14, 12)
-#define LAN3_PHY_LED_MAP(_n)			FIELD_PREP_CONST(LAN3_LED_MAPPING_MASK, (_n))
-
-#define LAN2_LED_MAPPING_MASK			GENMASK(10, 8)
-#define LAN2_PHY_LED_MAP(_n)			FIELD_PREP_CONST(LAN2_LED_MAPPING_MASK, (_n))
-
-#define LAN1_LED_MAPPING_MASK			GENMASK(6, 4)
-#define LAN1_PHY_LED_MAP(_n)			FIELD_PREP_CONST(LAN1_LED_MAPPING_MASK, (_n))
-
-#define LAN0_LED_MAPPING_MASK			GENMASK(2, 0)
-#define LAN0_PHY_LED_MAP(_n)			FIELD_PREP_CONST(LAN0_LED_MAPPING_MASK, (_n))
-
-/* CONF */
-#define REG_I2C_SDA_E2				0x001c
-#define AN7583_I2C1_SCL_E2_MASK			BIT(16)
-#define AN7583_I2C1_SDA_E2_MASK			BIT(15)
-#define SPI_MISO_E2_MASK			BIT(14)
-#define SPI_MOSI_E2_MASK			BIT(13)
-#define SPI_CLK_E2_MASK				BIT(12)
-#define SPI_CS0_E2_MASK				BIT(11)
-#define PCIE2_RESET_E2_MASK			BIT(10)
-#define PCIE1_RESET_E2_MASK			BIT(9)
-#define PCIE0_RESET_E2_MASK			BIT(8)
-#define AN7583_MDIO_0_E2_MASK			BIT(5)
-#define AN7583_MDC_0_E2_MASK			BIT(4)
-#define UART1_RXD_E2_MASK			BIT(3)
-#define UART1_TXD_E2_MASK			BIT(2)
-#define I2C_SCL_E2_MASK				BIT(1)
-#define I2C_SDA_E2_MASK				BIT(0)
-
-#define REG_I2C_SDA_E4				0x0020
-#define AN7583_I2C1_SCL_E4_MASK			BIT(16)
-#define AN7583_I2C1_SDA_E4_MASK			BIT(15)
-#define SPI_MISO_E4_MASK			BIT(14)
-#define SPI_MOSI_E4_MASK			BIT(13)
-#define SPI_CLK_E4_MASK				BIT(12)
-#define SPI_CS0_E4_MASK				BIT(11)
-#define PCIE2_RESET_E4_MASK			BIT(10)
-#define PCIE1_RESET_E4_MASK			BIT(9)
-#define PCIE0_RESET_E4_MASK			BIT(8)
-#define AN7583_MDIO_0_E4_MASK			BIT(5)
-#define AN7583_MDC_0_E4_MASK			BIT(4)
-#define UART1_RXD_E4_MASK			BIT(3)
-#define UART1_TXD_E4_MASK			BIT(2)
-#define I2C_SCL_E4_MASK				BIT(1)
-#define I2C_SDA_E4_MASK				BIT(0)
-
-#define REG_GPIO_L_E2				0x0024
-#define REG_GPIO_L_E4				0x0028
-#define REG_GPIO_H_E2				0x002c
-#define REG_GPIO_H_E4				0x0030
-
-#define REG_I2C_SDA_PU				0x0044
-#define AN7583_I2C1_SCL_PU_MASK			BIT(16)
-#define AN7583_I2C1_SDA_PU_MASK			BIT(15)
-#define SPI_MISO_PU_MASK			BIT(14)
-#define SPI_MOSI_PU_MASK			BIT(13)
-#define SPI_CLK_PU_MASK				BIT(12)
-#define SPI_CS0_PU_MASK				BIT(11)
-#define PCIE2_RESET_PU_MASK			BIT(10)
-#define PCIE1_RESET_PU_MASK			BIT(9)
-#define PCIE0_RESET_PU_MASK			BIT(8)
-#define AN7583_MDIO_0_PU_MASK			BIT(5)
-#define AN7583_MDC_0_PU_MASK			BIT(4)
-#define UART1_RXD_PU_MASK			BIT(3)
-#define UART1_TXD_PU_MASK			BIT(2)
-#define I2C_SCL_PU_MASK				BIT(1)
-#define I2C_SDA_PU_MASK				BIT(0)
-
-#define REG_I2C_SDA_PD				0x0048
-#define AN7583_I2C1_SCL_PD_MASK			BIT(16)
-#define AN7583_I2C1_SDA_PD_MASK			BIT(15)
-#define SPI_MISO_PD_MASK			BIT(14)
-#define SPI_MOSI_PD_MASK			BIT(13)
-#define SPI_CLK_PD_MASK				BIT(12)
-#define SPI_CS0_PD_MASK				BIT(11)
-#define PCIE2_RESET_PD_MASK			BIT(10)
-#define PCIE1_RESET_PD_MASK			BIT(9)
-#define PCIE0_RESET_PD_MASK			BIT(8)
-#define AN7583_MDIO_0_PD_MASK			BIT(5)
-#define AN7583_MDC_0_PD_MASK			BIT(4)
-#define UART1_RXD_PD_MASK			BIT(3)
-#define UART1_TXD_PD_MASK			BIT(2)
-#define I2C_SCL_PD_MASK				BIT(1)
-#define I2C_SDA_PD_MASK				BIT(0)
-
-#define REG_GPIO_L_PU				0x004c
-#define REG_GPIO_L_PD				0x0050
-#define REG_GPIO_H_PU				0x0054
-#define REG_GPIO_H_PD				0x0058
-
-#define REG_PCIE_RESET_OD			0x018c
-#define PCIE2_RESET_OD_MASK			BIT(2)
-#define PCIE1_RESET_OD_MASK			BIT(1)
-#define PCIE0_RESET_OD_MASK			BIT(0)
-
-/* GPIOs */
-#define REG_GPIO_CTRL				0x0000
-#define REG_GPIO_DATA				0x0004
-#define REG_GPIO_INT				0x0008
-#define REG_GPIO_INT_EDGE			0x000c
-#define REG_GPIO_INT_LEVEL			0x0010
-#define REG_GPIO_OE				0x0014
-#define REG_GPIO_CTRL1				0x0020
-#define REG_GPIO_CTRL2				0x0060
-#define REG_GPIO_CTRL3				0x0064
-
-/* PWM MODE CONF */
-#define REG_GPIO_FLASH_MODE_CFG			0x0034
-#define GPIO15_FLASH_MODE_CFG			BIT(15)
-#define GPIO14_FLASH_MODE_CFG			BIT(14)
-#define GPIO13_FLASH_MODE_CFG			BIT(13)
-#define GPIO12_FLASH_MODE_CFG			BIT(12)
-#define GPIO11_FLASH_MODE_CFG			BIT(11)
-#define GPIO10_FLASH_MODE_CFG			BIT(10)
-#define GPIO9_FLASH_MODE_CFG			BIT(9)
-#define GPIO8_FLASH_MODE_CFG			BIT(8)
-#define GPIO7_FLASH_MODE_CFG			BIT(7)
-#define GPIO6_FLASH_MODE_CFG			BIT(6)
-#define GPIO5_FLASH_MODE_CFG			BIT(5)
-#define GPIO4_FLASH_MODE_CFG			BIT(4)
-#define GPIO3_FLASH_MODE_CFG			BIT(3)
-#define GPIO2_FLASH_MODE_CFG			BIT(2)
-#define GPIO1_FLASH_MODE_CFG			BIT(1)
-#define GPIO0_FLASH_MODE_CFG			BIT(0)
-
-/* PWM MODE CONF EXT */
-#define REG_GPIO_FLASH_MODE_CFG_EXT		0x0068
-#define GPIO51_FLASH_MODE_CFG			BIT(31)
-#define GPIO50_FLASH_MODE_CFG			BIT(30)
-#define GPIO49_FLASH_MODE_CFG			BIT(29)
-#define GPIO48_FLASH_MODE_CFG			BIT(28)
-#define GPIO47_FLASH_MODE_CFG			BIT(27)
-#define GPIO46_FLASH_MODE_CFG			BIT(26)
-#define GPIO45_FLASH_MODE_CFG			BIT(25)
-#define GPIO44_FLASH_MODE_CFG			BIT(24)
-#define GPIO43_FLASH_MODE_CFG			BIT(23)
-#define GPIO42_FLASH_MODE_CFG			BIT(22)
-#define GPIO41_FLASH_MODE_CFG			BIT(21)
-#define GPIO40_FLASH_MODE_CFG			BIT(20)
-#define GPIO39_FLASH_MODE_CFG			BIT(19)
-#define GPIO38_FLASH_MODE_CFG			BIT(18)
-#define GPIO37_FLASH_MODE_CFG			BIT(17)
-#define GPIO36_FLASH_MODE_CFG			BIT(16)
-#define GPIO31_FLASH_MODE_CFG			BIT(15)
-#define GPIO30_FLASH_MODE_CFG			BIT(14)
-#define GPIO29_FLASH_MODE_CFG			BIT(13)
-#define GPIO28_FLASH_MODE_CFG			BIT(12)
-#define GPIO27_FLASH_MODE_CFG			BIT(11)
-#define GPIO26_FLASH_MODE_CFG			BIT(10)
-#define GPIO25_FLASH_MODE_CFG			BIT(9)
-#define GPIO24_FLASH_MODE_CFG			BIT(8)
-#define GPIO23_FLASH_MODE_CFG			BIT(7)
-#define GPIO22_FLASH_MODE_CFG			BIT(6)
-#define GPIO21_FLASH_MODE_CFG			BIT(5)
-#define GPIO20_FLASH_MODE_CFG			BIT(4)
-#define GPIO19_FLASH_MODE_CFG			BIT(3)
-#define GPIO18_FLASH_MODE_CFG			BIT(2)
-#define GPIO17_FLASH_MODE_CFG			BIT(1)
-#define GPIO16_FLASH_MODE_CFG			BIT(0)
-
-#define REG_GPIO_DATA1				0x0070
-#define REG_GPIO_OE1				0x0078
-#define REG_GPIO_INT1				0x007c
-#define REG_GPIO_INT_EDGE1			0x0080
-#define REG_GPIO_INT_EDGE2			0x0084
-#define REG_GPIO_INT_EDGE3			0x0088
-#define REG_GPIO_INT_LEVEL1			0x008c
-#define REG_GPIO_INT_LEVEL2			0x0090
-#define REG_GPIO_INT_LEVEL3			0x0094
-
-#define AIROHA_PINCTRL_GPIO(gpio, mux_val)			\
-	{							\
-		.name = (gpio),					\
-		.regmap[0] = {					\
-			AIROHA_FUNC_MUX,			\
-			REG_GPIO_PON_MODE,			\
-			(mux_val),				\
-			(mux_val)				\
-		},						\
-		.regmap_size = 1,				\
-	}
-
-#define AIROHA_PINCTRL_GPIO_EXT(gpio, mux_val, smux_val)	\
-	{							\
-		.name = (gpio),					\
-		.regmap[0] = {					\
-			AIROHA_FUNC_PWM_EXT_MUX,		\
-			REG_GPIO_FLASH_MODE_CFG_EXT,		\
-			(mux_val),				\
-			0					\
-		},						\
-		.regmap[1] = {					\
-			AIROHA_FUNC_MUX,			\
-			REG_GPIO_PON_MODE,			\
-			(smux_val),				\
-			(smux_val)				\
-		},						\
-		.regmap_size = 2,				\
-	}
-
-/* PWM */
-#define AIROHA_PINCTRL_PWM(gpio, mux_val)		\
-	{						\
-		.name = (gpio),				\
-		.regmap[0] = {				\
-			AIROHA_FUNC_PWM_MUX,		\
-			REG_GPIO_FLASH_MODE_CFG,	\
-			(mux_val),			\
-			(mux_val)			\
-		},					\
-		.regmap_size = 1,			\
-	}
-
-#define AIROHA_PINCTRL_PWM_EXT(gpio, mux_val)		\
-	{						\
-		.name = (gpio),				\
-		.regmap[0] = {				\
-			AIROHA_FUNC_PWM_EXT_MUX,	\
-			REG_GPIO_FLASH_MODE_CFG_EXT,	\
-			(mux_val),			\
-			(mux_val)			\
-		},					\
-		.regmap_size = 1,			\
-	}
-
-#define AIROHA_PINCTRL_PWM_EXT_SEC(gpio, mux_val, smux_val)	\
-	{							\
-		.name = (gpio),					\
-		.regmap[0] = {					\
-			AIROHA_FUNC_PWM_EXT_MUX,		\
-			REG_GPIO_FLASH_MODE_CFG_EXT,		\
-			(mux_val),				\
-			(mux_val)				\
-		},						\
-		.regmap[1] = {					\
-			AIROHA_FUNC_MUX,			\
-			REG_GPIO_PON_MODE,			\
-			(smux_val),				\
-			(smux_val)				\
-		},						\
-		.regmap_size = 2,				\
-	}
-
-#define AIROHA_PINCTRL_PHY_LED0(gpio, mux_val, map_mask, map_val)	\
-	{								\
-		.name = (gpio),						\
-		.regmap[0] = {						\
-			AIROHA_FUNC_MUX,				\
-			REG_GPIO_2ND_I2C_MODE,				\
-			(mux_val),					\
-			(mux_val),					\
-		},							\
-		.regmap[1] = {						\
-			AIROHA_FUNC_MUX,				\
-			REG_LAN_LED0_MAPPING,				\
-			(map_mask),					\
-			(map_val),					\
-		},							\
-		.regmap_size = 2,					\
-	}
-
-#define AIROHA_PINCTRL_PHY_LED1(gpio, mux_val, map_mask, map_val)	\
-	{								\
-		.name = (gpio),						\
-		.regmap[0] = {						\
-			AIROHA_FUNC_MUX,				\
-			REG_GPIO_2ND_I2C_MODE,				\
-			(mux_val),					\
-			(mux_val),					\
-		},							\
-		.regmap[1] = {						\
-			AIROHA_FUNC_MUX,				\
-			REG_LAN_LED1_MAPPING,				\
-			(map_mask),					\
-			(map_val),					\
-		},							\
-		.regmap_size = 2,					\
-	}
-
 #define airoha_pinctrl_get_pullup_conf(pinctrl, pin, val)			\
 	airoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_PULLUP,		\
 				(pin), (val))
@@ -433,1935 +74,6 @@ static const u32 irq_edge_regs[] = {
 	REG_GPIO_INT_EDGE3
 };
 
-static struct pinctrl_pin_desc en7581_pinctrl_pins[] = {
-	PINCTRL_PIN(0, "uart1_txd"),
-	PINCTRL_PIN(1, "uart1_rxd"),
-	PINCTRL_PIN(2, "i2c_scl"),
-	PINCTRL_PIN(3, "i2c_sda"),
-	PINCTRL_PIN(4, "spi_cs0"),
-	PINCTRL_PIN(5, "spi_clk"),
-	PINCTRL_PIN(6, "spi_mosi"),
-	PINCTRL_PIN(7, "spi_miso"),
-	PINCTRL_PIN(13, "gpio0"),
-	PINCTRL_PIN(14, "gpio1"),
-	PINCTRL_PIN(15, "gpio2"),
-	PINCTRL_PIN(16, "gpio3"),
-	PINCTRL_PIN(17, "gpio4"),
-	PINCTRL_PIN(18, "gpio5"),
-	PINCTRL_PIN(19, "gpio6"),
-	PINCTRL_PIN(20, "gpio7"),
-	PINCTRL_PIN(21, "gpio8"),
-	PINCTRL_PIN(22, "gpio9"),
-	PINCTRL_PIN(23, "gpio10"),
-	PINCTRL_PIN(24, "gpio11"),
-	PINCTRL_PIN(25, "gpio12"),
-	PINCTRL_PIN(26, "gpio13"),
-	PINCTRL_PIN(27, "gpio14"),
-	PINCTRL_PIN(28, "gpio15"),
-	PINCTRL_PIN(29, "gpio16"),
-	PINCTRL_PIN(30, "gpio17"),
-	PINCTRL_PIN(31, "gpio18"),
-	PINCTRL_PIN(32, "gpio19"),
-	PINCTRL_PIN(33, "gpio20"),
-	PINCTRL_PIN(34, "gpio21"),
-	PINCTRL_PIN(35, "gpio22"),
-	PINCTRL_PIN(36, "gpio23"),
-	PINCTRL_PIN(37, "gpio24"),
-	PINCTRL_PIN(38, "gpio25"),
-	PINCTRL_PIN(39, "gpio26"),
-	PINCTRL_PIN(40, "gpio27"),
-	PINCTRL_PIN(41, "gpio28"),
-	PINCTRL_PIN(42, "gpio29"),
-	PINCTRL_PIN(43, "gpio30"),
-	PINCTRL_PIN(44, "gpio31"),
-	PINCTRL_PIN(45, "gpio32"),
-	PINCTRL_PIN(46, "gpio33"),
-	PINCTRL_PIN(47, "gpio34"),
-	PINCTRL_PIN(48, "gpio35"),
-	PINCTRL_PIN(49, "gpio36"),
-	PINCTRL_PIN(50, "gpio37"),
-	PINCTRL_PIN(51, "gpio38"),
-	PINCTRL_PIN(52, "gpio39"),
-	PINCTRL_PIN(53, "gpio40"),
-	PINCTRL_PIN(54, "gpio41"),
-	PINCTRL_PIN(55, "gpio42"),
-	PINCTRL_PIN(56, "gpio43"),
-	PINCTRL_PIN(57, "gpio44"),
-	PINCTRL_PIN(58, "gpio45"),
-	PINCTRL_PIN(59, "gpio46"),
-	PINCTRL_PIN(60, "pcie_reset0"),
-	PINCTRL_PIN(61, "pcie_reset1"),
-	PINCTRL_PIN(62, "pcie_reset2"),
-};
-
-static const int en7581_pon_pins[] = { 49, 50, 51, 52, 53, 54 };
-static const int en7581_pon_tod_1pps_pins[] = { 46 };
-static const int en7581_gsw_tod_1pps_pins[] = { 46 };
-static const int en7581_sipo_pins[] = { 16, 17 };
-static const int en7581_sipo_rclk_pins[] = { 16, 17, 43 };
-static const int en7581_mdio_pins[] = { 14, 15 };
-static const int en7581_uart2_pins[] = { 48, 55 };
-static const int en7581_uart2_cts_rts_pins[] = { 46, 47 };
-static const int en7581_hsuart_pins[] = { 28, 29 };
-static const int en7581_hsuart_cts_rts_pins[] = { 26, 27 };
-static const int en7581_uart4_pins[] = { 38, 39 };
-static const int en7581_uart5_pins[] = { 18, 19 };
-static const int en7581_i2c0_pins[] = { 2, 3 };
-static const int en7581_i2c1_pins[] = { 14, 15 };
-static const int en7581_jtag_udi_pins[] = { 16, 17, 18, 19, 20 };
-static const int en7581_jtag_dfd_pins[] = { 16, 17, 18, 19, 20 };
-static const int en7581_i2s_pins[] = { 26, 27, 28, 29 };
-static const int en7581_pcm1_pins[] = { 22, 23, 24, 25 };
-static const int en7581_pcm2_pins[] = { 18, 19, 20, 21 };
-static const int en7581_spi_quad_pins[] = { 32, 33 };
-static const int en7581_spi_pins[] = { 4, 5, 6, 7 };
-static const int en7581_spi_cs1_pins[] = { 34 };
-static const int en7581_pcm_spi_pins[] = { 18, 19, 20, 21, 22, 23, 24, 25 };
-static const int en7581_pcm_spi_int_pins[] = { 14 };
-static const int en7581_pcm_spi_rst_pins[] = { 15 };
-static const int en7581_pcm_spi_cs1_pins[] = { 43 };
-static const int en7581_pcm_spi_cs2_pins[] = { 40 };
-static const int en7581_pcm_spi_cs2_p128_pins[] = { 40 };
-static const int en7581_pcm_spi_cs2_p156_pins[] = { 40 };
-static const int en7581_pcm_spi_cs3_pins[] = { 41 };
-static const int en7581_pcm_spi_cs4_pins[] = { 42 };
-static const int en7581_emmc_pins[] = { 4, 5, 6, 30, 31, 32, 33, 34, 35, 36, 37 };
-static const int en7581_pnand_pins[] = { 4, 5, 6, 7, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42 };
-static const int en7581_gpio0_pins[] = { 13 };
-static const int en7581_gpio1_pins[] = { 14 };
-static const int en7581_gpio2_pins[] = { 15 };
-static const int en7581_gpio3_pins[] = { 16 };
-static const int en7581_gpio4_pins[] = { 17 };
-static const int en7581_gpio5_pins[] = { 18 };
-static const int en7581_gpio6_pins[] = { 19 };
-static const int en7581_gpio7_pins[] = { 20 };
-static const int en7581_gpio8_pins[] = { 21 };
-static const int en7581_gpio9_pins[] = { 22 };
-static const int en7581_gpio10_pins[] = { 23 };
-static const int en7581_gpio11_pins[] = { 24 };
-static const int en7581_gpio12_pins[] = { 25 };
-static const int en7581_gpio13_pins[] = { 26 };
-static const int en7581_gpio14_pins[] = { 27 };
-static const int en7581_gpio15_pins[] = { 28 };
-static const int en7581_gpio16_pins[] = { 29 };
-static const int en7581_gpio17_pins[] = { 30 };
-static const int en7581_gpio18_pins[] = { 31 };
-static const int en7581_gpio19_pins[] = { 32 };
-static const int en7581_gpio20_pins[] = { 33 };
-static const int en7581_gpio21_pins[] = { 34 };
-static const int en7581_gpio22_pins[] = { 35 };
-static const int en7581_gpio23_pins[] = { 36 };
-static const int en7581_gpio24_pins[] = { 37 };
-static const int en7581_gpio25_pins[] = { 38 };
-static const int en7581_gpio26_pins[] = { 39 };
-static const int en7581_gpio27_pins[] = { 40 };
-static const int en7581_gpio28_pins[] = { 41 };
-static const int en7581_gpio29_pins[] = { 42 };
-static const int en7581_gpio30_pins[] = { 43 };
-static const int en7581_gpio31_pins[] = { 44 };
-static const int en7581_gpio32_pins[] = { 45 };
-static const int en7581_gpio33_pins[] = { 46 };
-static const int en7581_gpio34_pins[] = { 47 };
-static const int en7581_gpio35_pins[] = { 48 };
-static const int en7581_gpio36_pins[] = { 49 };
-static const int en7581_gpio37_pins[] = { 50 };
-static const int en7581_gpio38_pins[] = { 51 };
-static const int en7581_gpio39_pins[] = { 52 };
-static const int en7581_gpio40_pins[] = { 53 };
-static const int en7581_gpio41_pins[] = { 54 };
-static const int en7581_gpio42_pins[] = { 55 };
-static const int en7581_gpio43_pins[] = { 56 };
-static const int en7581_gpio44_pins[] = { 57 };
-static const int en7581_gpio45_pins[] = { 58 };
-static const int en7581_gpio46_pins[] = { 59 };
-static const int en7581_gpio47_pins[] = { 60 };
-static const int en7581_gpio48_pins[] = { 61 };
-static const int en7581_gpio49_pins[] = { 62 };
-static const int en7581_pcie_reset0_pins[] = { 60 };
-static const int en7581_pcie_reset1_pins[] = { 61 };
-static const int en7581_pcie_reset2_pins[] = { 62 };
-
-static const struct pingroup en7581_pinctrl_groups[] = {
-	PINCTRL_PIN_GROUP("pon", en7581_pon),
-	PINCTRL_PIN_GROUP("pon_tod_1pps", en7581_pon_tod_1pps),
-	PINCTRL_PIN_GROUP("gsw_tod_1pps", en7581_gsw_tod_1pps),
-	PINCTRL_PIN_GROUP("sipo", en7581_sipo),
-	PINCTRL_PIN_GROUP("sipo_rclk", en7581_sipo_rclk),
-	PINCTRL_PIN_GROUP("mdio", en7581_mdio),
-	PINCTRL_PIN_GROUP("uart2", en7581_uart2),
-	PINCTRL_PIN_GROUP("uart2_cts_rts", en7581_uart2_cts_rts),
-	PINCTRL_PIN_GROUP("hsuart", en7581_hsuart),
-	PINCTRL_PIN_GROUP("hsuart_cts_rts", en7581_hsuart_cts_rts),
-	PINCTRL_PIN_GROUP("uart4", en7581_uart4),
-	PINCTRL_PIN_GROUP("uart5", en7581_uart5),
-	PINCTRL_PIN_GROUP("i2c0", en7581_i2c0),
-	PINCTRL_PIN_GROUP("i2c1", en7581_i2c1),
-	PINCTRL_PIN_GROUP("jtag_udi", en7581_jtag_udi),
-	PINCTRL_PIN_GROUP("jtag_dfd", en7581_jtag_dfd),
-	PINCTRL_PIN_GROUP("i2s", en7581_i2s),
-	PINCTRL_PIN_GROUP("pcm1", en7581_pcm1),
-	PINCTRL_PIN_GROUP("pcm2", en7581_pcm2),
-	PINCTRL_PIN_GROUP("spi", en7581_spi),
-	PINCTRL_PIN_GROUP("spi_quad", en7581_spi_quad),
-	PINCTRL_PIN_GROUP("spi_cs1", en7581_spi_cs1),
-	PINCTRL_PIN_GROUP("pcm_spi", en7581_pcm_spi),
-	PINCTRL_PIN_GROUP("pcm_spi_int", en7581_pcm_spi_int),
-	PINCTRL_PIN_GROUP("pcm_spi_rst", en7581_pcm_spi_rst),
-	PINCTRL_PIN_GROUP("pcm_spi_cs1", en7581_pcm_spi_cs1),
-	PINCTRL_PIN_GROUP("pcm_spi_cs2_p128", en7581_pcm_spi_cs2_p128),
-	PINCTRL_PIN_GROUP("pcm_spi_cs2_p156", en7581_pcm_spi_cs2_p156),
-	PINCTRL_PIN_GROUP("pcm_spi_cs2", en7581_pcm_spi_cs2),
-	PINCTRL_PIN_GROUP("pcm_spi_cs3", en7581_pcm_spi_cs3),
-	PINCTRL_PIN_GROUP("pcm_spi_cs4", en7581_pcm_spi_cs4),
-	PINCTRL_PIN_GROUP("emmc", en7581_emmc),
-	PINCTRL_PIN_GROUP("pnand", en7581_pnand),
-	PINCTRL_PIN_GROUP("gpio0", en7581_gpio0),
-	PINCTRL_PIN_GROUP("gpio1", en7581_gpio1),
-	PINCTRL_PIN_GROUP("gpio2", en7581_gpio2),
-	PINCTRL_PIN_GROUP("gpio3", en7581_gpio3),
-	PINCTRL_PIN_GROUP("gpio4", en7581_gpio4),
-	PINCTRL_PIN_GROUP("gpio5", en7581_gpio5),
-	PINCTRL_PIN_GROUP("gpio6", en7581_gpio6),
-	PINCTRL_PIN_GROUP("gpio7", en7581_gpio7),
-	PINCTRL_PIN_GROUP("gpio8", en7581_gpio8),
-	PINCTRL_PIN_GROUP("gpio9", en7581_gpio9),
-	PINCTRL_PIN_GROUP("gpio10", en7581_gpio10),
-	PINCTRL_PIN_GROUP("gpio11", en7581_gpio11),
-	PINCTRL_PIN_GROUP("gpio12", en7581_gpio12),
-	PINCTRL_PIN_GROUP("gpio13", en7581_gpio13),
-	PINCTRL_PIN_GROUP("gpio14", en7581_gpio14),
-	PINCTRL_PIN_GROUP("gpio15", en7581_gpio15),
-	PINCTRL_PIN_GROUP("gpio16", en7581_gpio16),
-	PINCTRL_PIN_GROUP("gpio17", en7581_gpio17),
-	PINCTRL_PIN_GROUP("gpio18", en7581_gpio18),
-	PINCTRL_PIN_GROUP("gpio19", en7581_gpio19),
-	PINCTRL_PIN_GROUP("gpio20", en7581_gpio20),
-	PINCTRL_PIN_GROUP("gpio21", en7581_gpio21),
-	PINCTRL_PIN_GROUP("gpio22", en7581_gpio22),
-	PINCTRL_PIN_GROUP("gpio23", en7581_gpio23),
-	PINCTRL_PIN_GROUP("gpio24", en7581_gpio24),
-	PINCTRL_PIN_GROUP("gpio25", en7581_gpio25),
-	PINCTRL_PIN_GROUP("gpio26", en7581_gpio26),
-	PINCTRL_PIN_GROUP("gpio27", en7581_gpio27),
-	PINCTRL_PIN_GROUP("gpio28", en7581_gpio28),
-	PINCTRL_PIN_GROUP("gpio29", en7581_gpio29),
-	PINCTRL_PIN_GROUP("gpio30", en7581_gpio30),
-	PINCTRL_PIN_GROUP("gpio31", en7581_gpio31),
-	PINCTRL_PIN_GROUP("gpio32", en7581_gpio32),
-	PINCTRL_PIN_GROUP("gpio33", en7581_gpio33),
-	PINCTRL_PIN_GROUP("gpio34", en7581_gpio34),
-	PINCTRL_PIN_GROUP("gpio35", en7581_gpio35),
-	PINCTRL_PIN_GROUP("gpio36", en7581_gpio36),
-	PINCTRL_PIN_GROUP("gpio37", en7581_gpio37),
-	PINCTRL_PIN_GROUP("gpio38", en7581_gpio38),
-	PINCTRL_PIN_GROUP("gpio39", en7581_gpio39),
-	PINCTRL_PIN_GROUP("gpio40", en7581_gpio40),
-	PINCTRL_PIN_GROUP("gpio41", en7581_gpio41),
-	PINCTRL_PIN_GROUP("gpio42", en7581_gpio42),
-	PINCTRL_PIN_GROUP("gpio43", en7581_gpio43),
-	PINCTRL_PIN_GROUP("gpio44", en7581_gpio44),
-	PINCTRL_PIN_GROUP("gpio45", en7581_gpio45),
-	PINCTRL_PIN_GROUP("gpio46", en7581_gpio46),
-	PINCTRL_PIN_GROUP("gpio47", en7581_gpio47),
-	PINCTRL_PIN_GROUP("gpio48", en7581_gpio48),
-	PINCTRL_PIN_GROUP("gpio49", en7581_gpio49),
-	PINCTRL_PIN_GROUP("pcie_reset0", en7581_pcie_reset0),
-	PINCTRL_PIN_GROUP("pcie_reset1", en7581_pcie_reset1),
-	PINCTRL_PIN_GROUP("pcie_reset2", en7581_pcie_reset2),
-};
-
-static struct pinctrl_pin_desc an7583_pinctrl_pins[] = {
-	PINCTRL_PIN(2, "gpio0"),
-	PINCTRL_PIN(3, "gpio1"),
-	PINCTRL_PIN(4, "gpio2"),
-	PINCTRL_PIN(5, "gpio3"),
-	PINCTRL_PIN(6, "gpio4"),
-	PINCTRL_PIN(7, "gpio5"),
-	PINCTRL_PIN(8, "gpio6"),
-	PINCTRL_PIN(9, "gpio7"),
-	PINCTRL_PIN(10, "gpio8"),
-	PINCTRL_PIN(11, "gpio9"),
-	PINCTRL_PIN(12, "gpio10"),
-	PINCTRL_PIN(13, "gpio11"),
-	PINCTRL_PIN(14, "gpio12"),
-	PINCTRL_PIN(15, "gpio13"),
-	PINCTRL_PIN(16, "gpio14"),
-	PINCTRL_PIN(17, "gpio15"),
-	PINCTRL_PIN(18, "gpio16"),
-	PINCTRL_PIN(19, "gpio17"),
-	PINCTRL_PIN(20, "gpio18"),
-	PINCTRL_PIN(21, "gpio19"),
-	PINCTRL_PIN(22, "gpio20"),
-	PINCTRL_PIN(23, "gpio21"),
-	PINCTRL_PIN(24, "gpio22"),
-	PINCTRL_PIN(25, "gpio23"),
-	PINCTRL_PIN(26, "gpio24"),
-	PINCTRL_PIN(27, "gpio25"),
-	PINCTRL_PIN(28, "gpio26"),
-	PINCTRL_PIN(29, "gpio27"),
-	PINCTRL_PIN(30, "gpio28"),
-	PINCTRL_PIN(31, "gpio29"),
-	PINCTRL_PIN(32, "gpio30"),
-	PINCTRL_PIN(33, "gpio31"),
-	PINCTRL_PIN(34, "gpio32"),
-	PINCTRL_PIN(35, "gpio33"),
-	PINCTRL_PIN(36, "gpio34"),
-	PINCTRL_PIN(37, "gpio35"),
-	PINCTRL_PIN(38, "gpio36"),
-	PINCTRL_PIN(39, "gpio37"),
-	PINCTRL_PIN(40, "gpio38"),
-	PINCTRL_PIN(41, "i2c0_scl"),
-	PINCTRL_PIN(42, "i2c0_sda"),
-	PINCTRL_PIN(43, "i2c1_scl"),
-	PINCTRL_PIN(44, "i2c1_sda"),
-	PINCTRL_PIN(45, "spi_clk"),
-	PINCTRL_PIN(46, "spi_cs"),
-	PINCTRL_PIN(47, "spi_mosi"),
-	PINCTRL_PIN(48, "spi_miso"),
-	PINCTRL_PIN(49, "uart_txd"),
-	PINCTRL_PIN(50, "uart_rxd"),
-	PINCTRL_PIN(51, "pcie_reset0"),
-	PINCTRL_PIN(52, "pcie_reset1"),
-	PINCTRL_PIN(53, "mdc_0"),
-	PINCTRL_PIN(54, "mdio_0"),
-};
-
-static const int an7583_pon_pins[] = { 15, 16, 17, 18, 19, 20 };
-static const int an7583_pon_tod_1pps_pins[] = { 32 };
-static const int an7583_gsw_tod_1pps_pins[] = { 32 };
-static const int an7583_sipo_pins[] = { 34, 35 };
-static const int an7583_sipo_rclk_pins[] = { 34, 35, 33 };
-static const int an7583_mdio_pins[] = { 43, 44 };
-static const int an7583_uart2_pins[] = { 34, 35 };
-static const int an7583_uart2_cts_rts_pins[] = { 32, 33 };
-static const int an7583_hsuart_pins[] = { 30, 31 };
-static const int an7583_hsuart_cts_rts_pins[] = { 28, 29 };
-static const int an7583_npu_uart_pins[] = { 7, 8 };
-static const int an7583_uart4_pins[] = { 7, 8 };
-static const int an7583_uart5_pins[] = { 23, 24 };
-static const int an7583_i2c0_pins[] = { 41, 42 };
-static const int an7583_i2c1_pins[] = { 43, 44 };
-static const int an7583_jtag_udi_pins[] = { 23, 24, 22, 25, 26 };
-static const int an7583_jtag_dfd_pins[] = { 23, 24, 22, 25, 26 };
-static const int an7583_pcm1_pins[] = { 10, 11, 12, 13, 14 };
-static const int an7583_pcm2_pins[] = { 28, 29, 30, 31, 24 };
-static const int an7583_spi_pins[] = { 28, 29, 30, 31 };
-static const int an7583_spi_quad_pins[] = { 25, 26 };
-static const int an7583_spi_cs1_pins[] = { 27 };
-static const int an7583_pcm_spi_pins[] = { 28, 29, 30, 31, 10, 11, 12, 13 };
-static const int an7583_pcm_spi_rst_pins[] = { 14 };
-static const int an7583_pcm_spi_cs1_pins[] = { 24 };
-static const int an7583_emmc_pins[] = { 7, 8, 9, 22, 23, 24, 25, 26, 45, 46, 47 };
-static const int an7583_pnand_pins[] = { 7, 8, 9, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 45, 46, 47, 48 };
-static const int an7583_gpio0_pins[] = { 2 };
-static const int an7583_gpio1_pins[] = { 3 };
-static const int an7583_gpio2_pins[] = { 4 };
-static const int an7583_gpio3_pins[] = { 5 };
-static const int an7583_gpio4_pins[] = { 6 };
-static const int an7583_gpio5_pins[] = { 7 };
-static const int an7583_gpio6_pins[] = { 8 };
-static const int an7583_gpio7_pins[] = { 9 };
-static const int an7583_gpio8_pins[] = { 10 };
-static const int an7583_gpio9_pins[] = { 11 };
-static const int an7583_gpio10_pins[] = { 12 };
-static const int an7583_gpio11_pins[] = { 13 };
-static const int an7583_gpio12_pins[] = { 14 };
-static const int an7583_gpio13_pins[] = { 15 };
-static const int an7583_gpio14_pins[] = { 16 };
-static const int an7583_gpio15_pins[] = { 17 };
-static const int an7583_gpio16_pins[] = { 18 };
-static const int an7583_gpio17_pins[] = { 19 };
-static const int an7583_gpio18_pins[] = { 20 };
-static const int an7583_gpio19_pins[] = { 21 };
-static const int an7583_gpio20_pins[] = { 22 };
-static const int an7583_gpio21_pins[] = { 23 };
-static const int an7583_gpio22_pins[] = { 24 };
-static const int an7583_gpio23_pins[] = { 25 };
-static const int an7583_gpio24_pins[] = { 26 };
-static const int an7583_gpio25_pins[] = { 27 };
-static const int an7583_gpio26_pins[] = { 28 };
-static const int an7583_gpio27_pins[] = { 29 };
-static const int an7583_gpio28_pins[] = { 30 };
-static const int an7583_gpio29_pins[] = { 31 };
-static const int an7583_gpio30_pins[] = { 32 };
-static const int an7583_gpio31_pins[] = { 33 };
-static const int an7583_gpio32_pins[] = { 34 };
-static const int an7583_gpio33_pins[] = { 35 };
-static const int an7583_gpio34_pins[] = { 36 };
-static const int an7583_gpio35_pins[] = { 37 };
-static const int an7583_gpio36_pins[] = { 38 };
-static const int an7583_gpio37_pins[] = { 39 };
-static const int an7583_gpio38_pins[] = { 40 };
-static const int an7583_gpio39_pins[] = { 41 };
-static const int an7583_gpio40_pins[] = { 42 };
-static const int an7583_gpio41_pins[] = { 43 };
-static const int an7583_gpio42_pins[] = { 44 };
-static const int an7583_gpio43_pins[] = { 45 };
-static const int an7583_gpio44_pins[] = { 46 };
-static const int an7583_gpio45_pins[] = { 47 };
-static const int an7583_gpio46_pins[] = { 48 };
-static const int an7583_gpio47_pins[] = { 49 };
-static const int an7583_gpio48_pins[] = { 50 };
-static const int an7583_gpio49_pins[] = { 51 };
-static const int an7583_gpio50_pins[] = { 52 };
-static const int an7583_gpio51_pins[] = { 53 };
-static const int an7583_gpio52_pins[] = { 54 };
-static const int an7583_pcie_reset0_pins[] = { 51 };
-static const int an7583_pcie_reset1_pins[] = { 52 };
-
-static const struct pingroup an7583_pinctrl_groups[] = {
-	PINCTRL_PIN_GROUP("pon", an7583_pon),
-	PINCTRL_PIN_GROUP("pon_tod_1pps", an7583_pon_tod_1pps),
-	PINCTRL_PIN_GROUP("gsw_tod_1pps", an7583_gsw_tod_1pps),
-	PINCTRL_PIN_GROUP("sipo", an7583_sipo),
-	PINCTRL_PIN_GROUP("sipo_rclk", an7583_sipo_rclk),
-	PINCTRL_PIN_GROUP("mdio", an7583_mdio),
-	PINCTRL_PIN_GROUP("uart2", an7583_uart2),
-	PINCTRL_PIN_GROUP("uart2_cts_rts", an7583_uart2_cts_rts),
-	PINCTRL_PIN_GROUP("hsuart", an7583_hsuart),
-	PINCTRL_PIN_GROUP("hsuart_cts_rts", an7583_hsuart_cts_rts),
-	PINCTRL_PIN_GROUP("npu_uart", an7583_npu_uart),
-	PINCTRL_PIN_GROUP("uart4", an7583_uart4),
-	PINCTRL_PIN_GROUP("uart5", an7583_uart5),
-	PINCTRL_PIN_GROUP("i2c0", an7583_i2c0),
-	PINCTRL_PIN_GROUP("i2c1", an7583_i2c1),
-	PINCTRL_PIN_GROUP("jtag_udi", an7583_jtag_udi),
-	PINCTRL_PIN_GROUP("jtag_dfd", an7583_jtag_dfd),
-	PINCTRL_PIN_GROUP("pcm1", an7583_pcm1),
-	PINCTRL_PIN_GROUP("pcm2", an7583_pcm2),
-	PINCTRL_PIN_GROUP("spi", an7583_spi),
-	PINCTRL_PIN_GROUP("spi_quad", an7583_spi_quad),
-	PINCTRL_PIN_GROUP("spi_cs1", an7583_spi_cs1),
-	PINCTRL_PIN_GROUP("pcm_spi", an7583_pcm_spi),
-	PINCTRL_PIN_GROUP("pcm_spi_rst", an7583_pcm_spi_rst),
-	PINCTRL_PIN_GROUP("pcm_spi_cs1", an7583_pcm_spi_cs1),
-	PINCTRL_PIN_GROUP("emmc", an7583_emmc),
-	PINCTRL_PIN_GROUP("pnand", an7583_pnand),
-	PINCTRL_PIN_GROUP("gpio0", an7583_gpio0),
-	PINCTRL_PIN_GROUP("gpio1", an7583_gpio1),
-	PINCTRL_PIN_GROUP("gpio2", an7583_gpio2),
-	PINCTRL_PIN_GROUP("gpio3", an7583_gpio3),
-	PINCTRL_PIN_GROUP("gpio4", an7583_gpio4),
-	PINCTRL_PIN_GROUP("gpio5", an7583_gpio5),
-	PINCTRL_PIN_GROUP("gpio6", an7583_gpio6),
-	PINCTRL_PIN_GROUP("gpio7", an7583_gpio7),
-	PINCTRL_PIN_GROUP("gpio8", an7583_gpio8),
-	PINCTRL_PIN_GROUP("gpio9", an7583_gpio9),
-	PINCTRL_PIN_GROUP("gpio10", an7583_gpio10),
-	PINCTRL_PIN_GROUP("gpio11", an7583_gpio11),
-	PINCTRL_PIN_GROUP("gpio12", an7583_gpio12),
-	PINCTRL_PIN_GROUP("gpio13", an7583_gpio13),
-	PINCTRL_PIN_GROUP("gpio14", an7583_gpio14),
-	PINCTRL_PIN_GROUP("gpio15", an7583_gpio15),
-	PINCTRL_PIN_GROUP("gpio16", an7583_gpio16),
-	PINCTRL_PIN_GROUP("gpio17", an7583_gpio17),
-	PINCTRL_PIN_GROUP("gpio18", an7583_gpio18),
-	PINCTRL_PIN_GROUP("gpio19", an7583_gpio19),
-	PINCTRL_PIN_GROUP("gpio20", an7583_gpio20),
-	PINCTRL_PIN_GROUP("gpio21", an7583_gpio21),
-	PINCTRL_PIN_GROUP("gpio22", an7583_gpio22),
-	PINCTRL_PIN_GROUP("gpio23", an7583_gpio23),
-	PINCTRL_PIN_GROUP("gpio24", an7583_gpio24),
-	PINCTRL_PIN_GROUP("gpio25", an7583_gpio25),
-	PINCTRL_PIN_GROUP("gpio26", an7583_gpio26),
-	PINCTRL_PIN_GROUP("gpio27", an7583_gpio27),
-	PINCTRL_PIN_GROUP("gpio28", an7583_gpio28),
-	PINCTRL_PIN_GROUP("gpio29", an7583_gpio29),
-	PINCTRL_PIN_GROUP("gpio30", an7583_gpio30),
-	PINCTRL_PIN_GROUP("gpio31", an7583_gpio31),
-	PINCTRL_PIN_GROUP("gpio32", an7583_gpio32),
-	PINCTRL_PIN_GROUP("gpio33", an7583_gpio33),
-	PINCTRL_PIN_GROUP("gpio34", an7583_gpio34),
-	PINCTRL_PIN_GROUP("gpio35", an7583_gpio35),
-	PINCTRL_PIN_GROUP("gpio36", an7583_gpio36),
-	PINCTRL_PIN_GROUP("gpio37", an7583_gpio37),
-	PINCTRL_PIN_GROUP("gpio38", an7583_gpio38),
-	PINCTRL_PIN_GROUP("gpio39", an7583_gpio39),
-	PINCTRL_PIN_GROUP("gpio40", an7583_gpio40),
-	PINCTRL_PIN_GROUP("gpio41", an7583_gpio41),
-	PINCTRL_PIN_GROUP("gpio42", an7583_gpio42),
-	PINCTRL_PIN_GROUP("gpio43", an7583_gpio43),
-	PINCTRL_PIN_GROUP("gpio44", an7583_gpio44),
-	PINCTRL_PIN_GROUP("gpio45", an7583_gpio45),
-	PINCTRL_PIN_GROUP("gpio46", an7583_gpio46),
-	PINCTRL_PIN_GROUP("gpio47", an7583_gpio47),
-	PINCTRL_PIN_GROUP("gpio48", an7583_gpio48),
-	PINCTRL_PIN_GROUP("gpio49", an7583_gpio49),
-	PINCTRL_PIN_GROUP("gpio50", an7583_gpio50),
-	PINCTRL_PIN_GROUP("gpio51", an7583_gpio51),
-	PINCTRL_PIN_GROUP("gpio52", an7583_gpio52),
-	PINCTRL_PIN_GROUP("pcie_reset0", an7583_pcie_reset0),
-	PINCTRL_PIN_GROUP("pcie_reset1", an7583_pcie_reset1),
-};
-
-static const char *const pon_groups[] = { "pon" };
-static const char *const tod_1pps_groups[] = { "pon_tod_1pps", "gsw_tod_1pps" };
-static const char *const sipo_groups[] = { "sipo", "sipo_rclk" };
-static const char *const mdio_groups[] = { "mdio" };
-static const char *const an7583_mdio_groups[] = { "mdio" };
-static const char *const uart_groups[] = { "uart2", "uart2_cts_rts", "hsuart",
-					   "hsuart_cts_rts", "uart4",
-					   "uart5" };
-static const char *const i2c_groups[] = { "i2c1" };
-static const char *const jtag_groups[] = { "jtag_udi", "jtag_dfd" };
-static const char *const pcm_groups[] = { "pcm1", "pcm2" };
-static const char *const spi_groups[] = { "spi_quad", "spi_cs1" };
-static const char *const pcm_spi_groups[] = { "pcm_spi", "pcm_spi_int",
-					      "pcm_spi_rst", "pcm_spi_cs1",
-					      "pcm_spi_cs2_p156",
-					      "pcm_spi_cs2_p128",
-					      "pcm_spi_cs3", "pcm_spi_cs4" };
-static const char *const an7583_pcm_spi_groups[] = { "pcm_spi",
-						     "pcm_spi_rst", "pcm_spi_cs1" };
-static const char *const i2s_groups[] = { "i2s" };
-static const char *const emmc_groups[] = { "emmc" };
-static const char *const pnand_groups[] = { "pnand" };
-static const char *const gpio_groups[] = { "gpio47", "gpio48", "gpio49" };
-static const char *const pcie_reset_groups[] = { "pcie_reset0", "pcie_reset1",
-						 "pcie_reset2" };
-static const char *const an7583_gpio_groups[] = { "gpio39", "gpio40", "gpio41",
-						  "gpio42", "gpio43", "gpio44",
-						  "gpio45", "gpio46", "gpio47",
-						  "gpio48", "gpio49", "gpio50",
-						  "gpio51", "gpio52" };
-static const char *const an7583_pcie_reset_groups[] = { "pcie_reset0", "pcie_reset1" };
-static const char *const pwm_groups[] = { "gpio0", "gpio1",
-					  "gpio2", "gpio3",
-					  "gpio4", "gpio5",
-					  "gpio6", "gpio7",
-					  "gpio8", "gpio9",
-					  "gpio10", "gpio11",
-					  "gpio12", "gpio13",
-					  "gpio14", "gpio15",
-					  "gpio16", "gpio17",
-					  "gpio18", "gpio19",
-					  "gpio20", "gpio21",
-					  "gpio22", "gpio23",
-					  "gpio24", "gpio25",
-					  "gpio26", "gpio27",
-					  "gpio28", "gpio29",
-					  "gpio30", "gpio31",
-					  "gpio36", "gpio37",
-					  "gpio38", "gpio39",
-					  "gpio40", "gpio41",
-					  "gpio42", "gpio43",
-					  "gpio44", "gpio45",
-					  "gpio46", "gpio47",
-					  "gpio48", "gpio49" };
-static const char *const an7583_pwm_groups[] = { "gpio0", "gpio1",
-						 "gpio2", "gpio3",
-						 "gpio4", "gpio5",
-						 "gpio6", "gpio7",
-						 "gpio8", "gpio9",
-						 "gpio10", "gpio11",
-						 "gpio12", "gpio13",
-						 "gpio14", "gpio15",
-						 "gpio16", "gpio17",
-						 "gpio18", "gpio19",
-						 "gpio20", "gpio21",
-						 "gpio22", "gpio23",
-						 "gpio24", "gpio25",
-						 "gpio26", "gpio27",
-						 "gpio28", "gpio29",
-						 "gpio30", "gpio31",
-						 "gpio36", "gpio37",
-						 "gpio38", "gpio39",
-						 "gpio40", "gpio41",
-						 "gpio42", "gpio43",
-						 "gpio44", "gpio45",
-						 "gpio46", "gpio47",
-						 "gpio48", "gpio49",
-						 "gpio50", "gpio51" };
-static const char *const phy1_led0_groups[] = { "gpio33", "gpio34",
-						"gpio35", "gpio42" };
-static const char *const phy2_led0_groups[] = { "gpio33", "gpio34",
-						"gpio35", "gpio42" };
-static const char *const phy3_led0_groups[] = { "gpio33", "gpio34",
-						"gpio35", "gpio42" };
-static const char *const phy4_led0_groups[] = { "gpio33", "gpio34",
-						"gpio35", "gpio42" };
-static const char *const phy1_led1_groups[] = { "gpio43", "gpio44",
-						"gpio45", "gpio46" };
-static const char *const phy2_led1_groups[] = { "gpio43", "gpio44",
-						"gpio45", "gpio46" };
-static const char *const phy3_led1_groups[] = { "gpio43", "gpio44",
-						"gpio45", "gpio46" };
-static const char *const phy4_led1_groups[] = { "gpio43", "gpio44",
-						"gpio45", "gpio46" };
-static const char *const an7583_phy1_led0_groups[] = { "gpio1", "gpio2",
-							"gpio3", "gpio4" };
-static const char *const an7583_phy2_led0_groups[] = { "gpio1", "gpio2",
-							"gpio3", "gpio4" };
-static const char *const an7583_phy3_led0_groups[] = { "gpio1", "gpio2",
-							"gpio3", "gpio4" };
-static const char *const an7583_phy4_led0_groups[] = { "gpio1", "gpio2",
-							"gpio3", "gpio4" };
-static const char *const an7583_phy1_led1_groups[] = { "gpio8", "gpio9",
-							"gpio10", "gpio11" };
-static const char *const an7583_phy2_led1_groups[] = { "gpio8", "gpio9",
-							"gpio10", "gpio11" };
-static const char *const an7583_phy3_led1_groups[] = { "gpio8", "gpio9",
-							"gpio10", "gpio11" };
-static const char *const an7583_phy4_led1_groups[] = { "gpio8", "gpio9",
-							"gpio10", "gpio11" };
-
-static const struct airoha_pinctrl_func_group pon_func_group[] = {
-	{
-		.name = "pon",
-		.regmap[0] = {
-			AIROHA_FUNC_MUX,
-			REG_GPIO_PON_MODE,
-			GPIO_PON_MODE_MASK,
-			GPIO_PON_MODE_MASK
-		},
-		.regmap_size = 1,
-	},
-};
-
-static const struct airoha_pinctrl_func_group tod_1pps_func_group[] = {
-	{
-		.name = "pon_tod_1pps",
-		.regmap[0] = {
-			AIROHA_FUNC_MUX,
-			REG_GPIO_2ND_I2C_MODE,
-			PON_TOD_1PPS_MODE_MASK,
-			PON_TOD_1PPS_MODE_MASK
-		},
-		.regmap_size = 1,
-	}, {
-		.name = "gsw_tod_1pps",
-		.regmap[0] = {
-			AIROHA_FUNC_MUX,
-			REG_GPIO_2ND_I2C_MODE,
-			GSW_TOD_1PPS_MODE_MASK,
-			GSW_TOD_1PPS_MODE_MASK
-		},
-		.regmap_size = 1,
-	},
-};
-
-static const struct airoha_pinctrl_func_group sipo_func_group[] = {
-	{
-		.name = "sipo",
-		.regmap[0] = {
-			AIROHA_FUNC_MUX,
-			REG_GPIO_PON_MODE,
-			GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK,
-			GPIO_SIPO_MODE_MASK
-		},
-		.regmap_size = 1,
-	}, {
-		.name = "sipo_rclk",
-		.regmap[0] = {
-			AIROHA_FUNC_MUX,
-			REG_GPIO_PON_MODE,
-			GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK,
-			GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK
-		},
-		.regmap_size = 1,
-	},
-};
-
-static const struct airoha_pinctrl_func_group mdio_func_group[] = {
-	{
-		.name = "mdio",
-		.regmap[0] = {
-			AIROHA_FUNC_MUX,
-			REG_GPIO_2ND_I2C_MODE,
-			GPIO_MDC_IO_MASTER_MODE_MASK,
-			GPIO_MDC_IO_MASTER_MODE_MASK
-		},
-		.regmap[1] = {
-			AIROHA_FUNC_MUX,
-			REG_FORCE_GPIO_EN,
-			FORCE_GPIO_EN(1) | FORCE_GPIO_EN(2),
-			FORCE_GPIO_EN(1) | FORCE_GPIO_EN(2)
-		},
-		.regmap_size = 2,
-	},
-};
-
-static const struct airoha_pinctrl_func_group an7583_mdio_func_group[] = {
-	{
-		.name = "mdio",
-		.regmap[0] = {
-			AIROHA_FUNC_MUX,
-			REG_GPIO_PON_MODE,
-			GPIO_SGMII_MDIO_MODE_MASK,
-			GPIO_SGMII_MDIO_MODE_MASK
-		},
-		.regmap[1] = {
-			AIROHA_FUNC_MUX,
-			REG_GPIO_SPI_CS1_MODE,
-			GPIO_MDC_IO_MASTER_MODE_MASK,
-			GPIO_MDC_IO_MASTER_MODE_MASK
-		},
-		.regmap_size = 2,
-	},
-};
-
-static const struct airoha_pinctrl_func_group uart_func_group[] = {
-	{
-		.name = "uart2",
-		.regmap[0] = {
-			AIROHA_FUNC_MUX,
-			REG_GPIO_PON_MODE,
-			GPIO_UART2_MODE_MASK,
-			GPIO_UART2_MODE_MASK
-		},
-		.regmap_size = 1,
-	}, {
-		.name = "uart2_cts_rts",
-		.regmap[0] = {
-			AIROHA_FUNC_MUX,
-			REG_GPIO_PON_MODE,
-			GPIO_UART2_MODE_MASK | GPIO_UART2_CTS_RTS_MODE_MASK,
-			GPIO_UART2_MODE_MASK | GPIO_UART2_CTS_RTS_MODE_MASK
-		},
-		.regmap_size = 1,
-	}, {
-		.name = "hsuart",
-		.regmap[0] = {
-			AIROHA_FUNC_MUX,
-			REG_GPIO_PON_MODE,
-			GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK,
-			GPIO_HSUART_MODE_MASK
-		},
-		.regmap_size = 1,
-	},
-	{
-		.name = "hsuart_cts_rts",
-		.regmap[0] = {
-			AIROHA_FUNC_MUX,
-			REG_GPIO_PON_MODE,
-			GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK,
-			GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK
-		},
-		.regmap_size = 1,
-	}, {
-		.name = "uart4",
-		.regmap[0] = {
-			AIROHA_FUNC_MUX,
-			REG_GPIO_PON_MODE,
-			GPIO_UART4_MODE_MASK,
-			GPIO_UART4_MODE_MASK
-		},
-		.regmap_size = 1,
-	}, {
-		.name = "uart5",
-		.regmap[0] = {
-			AIROHA_FUNC_MUX,
-			REG_GPIO_PON_MODE,
-			GPIO_UART5_MODE_MASK,
-			GPIO_UART5_MODE_MASK
-		},
-		.regmap_size = 1,
-	},
-};
-
-static const struct airoha_pinctrl_func_group i2c_func_group[] = {
-	{
-		.name = "i2c1",
-		.regmap[0] = {
-			AIROHA_FUNC_MUX,
-			REG_GPIO_2ND_I2C_MODE,
-			GPIO_2ND_I2C_MODE_MASK,
-			GPIO_2ND_I2C_MODE_MASK
-		},
-		.regmap_size = 1,
-	},
-};
-
-static const struct airoha_pinctrl_func_group jtag_func_group[] = {
-	{
-		.name = "jtag_udi",
-		.regmap[0] = {
-			AIROHA_FUNC_MUX,
-			REG_NPU_UART_EN,
-			JTAG_UDI_EN_MASK,
-			JTAG_UDI_EN_MASK
-		},
-		.regmap_size = 1,
-	}, {
-		.name = "jtag_dfd",
-		.regmap[0] = {
-			AIROHA_FUNC_MUX,
-			REG_NPU_UART_EN,
-			JTAG_DFD_EN_MASK,
-			JTAG_DFD_EN_MASK
-		},
-		.regmap_size = 1,
-	},
-};
-
-static const struct airoha_pinctrl_func_group pcm_func_group[] = {
-	{
-		.name = "pcm1",
-		.regmap[0] = {
-			AIROHA_FUNC_MUX,
-			REG_GPIO_SPI_CS1_MODE,
-			GPIO_PCM1_MODE_MASK,
-			GPIO_PCM1_MODE_MASK
-		},
-		.regmap_size = 1,
-	}, {
-		.name = "pcm2",
-		.regmap[0] = {
-			AIROHA_FUNC_MUX,
-			REG_GPIO_SPI_CS1_MODE,
-			GPIO_PCM2_MODE_MASK,
-			GPIO_PCM2_MODE_MASK
-		},
-		.regmap_size = 1,
-	},
-};
-
-static const struct airoha_pinctrl_func_group spi_func_group[] = {
-	{
-		.name = "spi_quad",
-		.regmap[0] = {
-			AIROHA_FUNC_MUX,
-			REG_GPIO_SPI_CS1_MODE,
-			GPIO_SPI_QUAD_MODE_MASK,
-			GPIO_SPI_QUAD_MODE_MASK
-		},
-		.regmap_size = 1,
-	}, {
-		.name = "spi_cs1",
-		.regmap[0] = {
-			AIROHA_FUNC_MUX,
-			REG_GPIO_SPI_CS1_MODE,
-			GPIO_SPI_CS1_MODE_MASK,
-			GPIO_SPI_CS1_MODE_MASK
-		},
-		.regmap_size = 1,
-	}, {
-		.name = "spi_cs2",
-		.regmap[0] = {
-			AIROHA_FUNC_MUX,
-			REG_GPIO_SPI_CS1_MODE,
-			GPIO_SPI_CS2_MODE_MASK,
-			GPIO_SPI_CS2_MODE_MASK
-		},
-		.regmap_size = 1,
-	}, {
-		.name = "spi_cs3",
-		.regmap[0] = {
-			AIROHA_FUNC_MUX,
-			REG_GPIO_SPI_CS1_MODE,
-			GPIO_SPI_CS3_MODE_MASK,
-			GPIO_SPI_CS3_MODE_MASK
-		},
-		.regmap_size = 1,
-	}, {
-		.name = "spi_cs4",
-		.regmap[0] = {
-			AIROHA_FUNC_MUX,
-			REG_GPIO_SPI_CS1_MODE,
-			GPIO_SPI_CS4_MODE_MASK,
-			GPIO_SPI_CS4_MODE_MASK
-		},
-		.regmap_size = 1,
-	},
-};
-
-static const struct airoha_pinctrl_func_group pcm_spi_func_group[] = {
-	{
-		.name = "pcm_spi",
-		.regmap[0] = {
-			AIROHA_FUNC_MUX,
-			REG_GPIO_SPI_CS1_MODE,
-			GPIO_PCM_SPI_MODE_MASK,
-			GPIO_PCM_SPI_MODE_MASK
-		},
-		.regmap_size = 1,
-	}, {
-		.name = "pcm_spi_int",
-		.regmap[0] = {
-			AIROHA_FUNC_MUX,
-			REG_GPIO_SPI_CS1_MODE,
-			GPIO_PCM_INT_MODE_MASK,
-			GPIO_PCM_INT_MODE_MASK
-		},
-		.regmap_size = 1,
-	}, {
-		.name = "pcm_spi_rst",
-		.regmap[0] = {
-			AIROHA_FUNC_MUX,
-			REG_GPIO_SPI_CS1_MODE,
-			GPIO_PCM_RESET_MODE_MASK,
-			GPIO_PCM_RESET_MODE_MASK
-		},
-		.regmap_size = 1,
-	}, {
-		.name = "pcm_spi_cs1",
-		.regmap[0] = {
-			AIROHA_FUNC_MUX,
-			REG_GPIO_SPI_CS1_MODE,
-			GPIO_PCM_SPI_CS1_MODE_MASK,
-			GPIO_PCM_SPI_CS1_MODE_MASK
-		},
-		.regmap_size = 1,
-	}, {
-		.name = "pcm_spi_cs2_p128",
-		.regmap[0] = {
-			AIROHA_FUNC_MUX,
-			REG_GPIO_SPI_CS1_MODE,
-			GPIO_PCM_SPI_CS2_MODE_P128_MASK,
-			GPIO_PCM_SPI_CS2_MODE_P128_MASK
-		},
-		.regmap_size = 1,
-	}, {
-		.name = "pcm_spi_cs2_p156",
-		.regmap[0] = {
-			AIROHA_FUNC_MUX,
-			REG_GPIO_SPI_CS1_MODE,
-			GPIO_PCM_SPI_CS2_MODE_P156_MASK,
-			GPIO_PCM_SPI_CS2_MODE_P156_MASK
-		},
-		.regmap_size = 1,
-	}, {
-		.name = "pcm_spi_cs3",
-		.regmap[0] = {
-			AIROHA_FUNC_MUX,
-			REG_GPIO_SPI_CS1_MODE,
-			GPIO_PCM_SPI_CS3_MODE_MASK,
-			GPIO_PCM_SPI_CS3_MODE_MASK
-		},
-		.regmap_size = 1,
-	}, {
-		.name = "pcm_spi_cs4",
-		.regmap[0] = {
-			AIROHA_FUNC_MUX,
-			REG_GPIO_SPI_CS1_MODE,
-			GPIO_PCM_SPI_CS4_MODE_MASK,
-			GPIO_PCM_SPI_CS4_MODE_MASK
-		},
-		.regmap_size = 1,
-	},
-};
-
-static const struct airoha_pinctrl_func_group an7583_pcm_spi_func_group[] = {
-	{
-		.name = "pcm_spi",
-		.regmap[0] = {
-			AIROHA_FUNC_MUX,
-			REG_GPIO_SPI_CS1_MODE,
-			GPIO_PCM_SPI_MODE_MASK,
-			GPIO_PCM_SPI_MODE_MASK
-		},
-		.regmap_size = 1,
-	}, {
-		.name = "pcm_spi_int",
-		.regmap[0] = {
-			AIROHA_FUNC_MUX,
-			REG_GPIO_SPI_CS1_MODE,
-			GPIO_PCM_INT_MODE_MASK,
-			GPIO_PCM_INT_MODE_MASK
-		},
-		.regmap_size = 1,
-	}, {
-		.name = "pcm_spi_rst",
-		.regmap[0] = {
-			AIROHA_FUNC_MUX,
-			REG_GPIO_SPI_CS1_MODE,
-			GPIO_PCM_RESET_MODE_MASK,
-			GPIO_PCM_RESET_MODE_MASK
-		},
-		.regmap_size = 1,
-	}, {
-		.name = "pcm_spi_cs1",
-		.regmap[0] = {
-			AIROHA_FUNC_MUX,
-			REG_GPIO_SPI_CS1_MODE,
-			GPIO_PCM_SPI_CS1_MODE_MASK,
-			GPIO_PCM_SPI_CS1_MODE_MASK
-		},
-		.regmap_size = 1,
-	}, {
-		.name = "pcm_spi_cs2",
-		.regmap[0] = {
-			AIROHA_FUNC_MUX,
-			REG_GPIO_SPI_CS1_MODE,
-			AN7583_GPIO_PCM_SPI_CS2_MODE_MASK,
-			AN7583_GPIO_PCM_SPI_CS2_MODE_MASK
-		},
-		.regmap_size = 1,
-	}, {
-		.name = "pcm_spi_cs3",
-		.regmap[0] = {
-			AIROHA_FUNC_MUX,
-			REG_GPIO_SPI_CS1_MODE,
-			GPIO_PCM_SPI_CS3_MODE_MASK,
-			GPIO_PCM_SPI_CS3_MODE_MASK
-		},
-		.regmap_size = 1,
-	}, {
-		.name = "pcm_spi_cs4",
-		.regmap[0] = {
-			AIROHA_FUNC_MUX,
-			REG_GPIO_SPI_CS1_MODE,
-			GPIO_PCM_SPI_CS4_MODE_MASK,
-			GPIO_PCM_SPI_CS4_MODE_MASK
-		},
-		.regmap_size = 1,
-	},
-};
-
-static const struct airoha_pinctrl_func_group i2s_func_group[] = {
-	{
-		.name = "i2s",
-		.regmap[0] = {
-			AIROHA_FUNC_MUX,
-			REG_GPIO_2ND_I2C_MODE,
-			GPIO_I2S_MODE_MASK,
-			GPIO_I2S_MODE_MASK
-		},
-		.regmap_size = 1,
-	},
-};
-
-static const struct airoha_pinctrl_func_group emmc_func_group[] = {
-	{
-		.name = "emmc",
-		.regmap[0] = {
-			AIROHA_FUNC_MUX,
-			REG_GPIO_PON_MODE,
-			GPIO_EMMC_MODE_MASK,
-			GPIO_EMMC_MODE_MASK
-		},
-		.regmap_size = 1,
-	},
-};
-
-static const struct airoha_pinctrl_func_group pnand_func_group[] = {
-	{
-		.name = "pnand",
-		.regmap[0] = {
-			AIROHA_FUNC_MUX,
-			REG_GPIO_PON_MODE,
-			GPIO_PARALLEL_NAND_MODE_MASK,
-			GPIO_PARALLEL_NAND_MODE_MASK
-		},
-		.regmap_size = 1,
-	},
-};
-
-static const struct airoha_pinctrl_func_group gpio_func_group[] = {
-	AIROHA_PINCTRL_GPIO_EXT("gpio47", GPIO47_FLASH_MODE_CFG,
-				GPIO_PCIE_RESET0_MASK),
-	AIROHA_PINCTRL_GPIO_EXT("gpio48", GPIO48_FLASH_MODE_CFG,
-				GPIO_PCIE_RESET1_MASK),
-	AIROHA_PINCTRL_GPIO_EXT("gpio49", GPIO49_FLASH_MODE_CFG,
-				GPIO_PCIE_RESET2_MASK),
-};
-
-static const struct airoha_pinctrl_func_group pcie_reset_func_group[] = {
-	{
-		.name = "pcie_reset0",
-		.regmap[0] = {
-			AIROHA_FUNC_MUX,
-			REG_GPIO_PON_MODE,
-			GPIO_PCIE_RESET0_MASK,
-			0
-		},
-		.regmap_size = 1,
-	}, {
-		.name = "pcie_reset1",
-		.regmap[0] = {
-			AIROHA_FUNC_MUX,
-			REG_GPIO_PON_MODE,
-			GPIO_PCIE_RESET1_MASK,
-			0
-		},
-		.regmap_size = 1,
-	}, {
-		.name = "pcie_reset2",
-		.regmap[0] = {
-			AIROHA_FUNC_MUX,
-			REG_GPIO_PON_MODE,
-			GPIO_PCIE_RESET2_MASK,
-			0
-		},
-		.regmap_size = 1,
-	},
-};
-
-static const struct airoha_pinctrl_func_group an7583_gpio_func_group[] = {
-	AIROHA_PINCTRL_GPIO_EXT("gpio39", GPIO39_FLASH_MODE_CFG,
-				AN7583_I2C0_SCL_GPIO_MODE_MASK),
-	AIROHA_PINCTRL_GPIO_EXT("gpio40", GPIO40_FLASH_MODE_CFG,
-				AN7583_I2C0_SDA_GPIO_MODE_MASK),
-	AIROHA_PINCTRL_GPIO_EXT("gpio41", GPIO41_FLASH_MODE_CFG,
-				AN7583_I2C1_SCL_GPIO_MODE_MASK),
-	AIROHA_PINCTRL_GPIO_EXT("gpio42", GPIO42_FLASH_MODE_CFG,
-				AN7583_I2C1_SDA_GPIO_MODE_MASK),
-	AIROHA_PINCTRL_GPIO_EXT("gpio43", GPIO43_FLASH_MODE_CFG,
-				AN7583_SPI_CLK_GPIO_MODE_MASK),
-	AIROHA_PINCTRL_GPIO_EXT("gpio44", GPIO44_FLASH_MODE_CFG,
-				AN7583_SPI_CS_GPIO_MODE_MASK),
-	AIROHA_PINCTRL_GPIO_EXT("gpio45", GPIO45_FLASH_MODE_CFG,
-				AN7583_SPI_MOSI_GPIO_MODE_MASK),
-	AIROHA_PINCTRL_GPIO_EXT("gpio46", GPIO46_FLASH_MODE_CFG,
-				AN7583_SPI_MISO_GPIO_MODE_MASK),
-	AIROHA_PINCTRL_GPIO_EXT("gpio47", GPIO47_FLASH_MODE_CFG,
-				AN7583_UART_TXD_GPIO_MODE_MASK),
-	AIROHA_PINCTRL_GPIO_EXT("gpio48", GPIO48_FLASH_MODE_CFG,
-				AN7583_UART_RXD_GPIO_MODE_MASK),
-	AIROHA_PINCTRL_GPIO_EXT("gpio49", GPIO49_FLASH_MODE_CFG,
-				GPIO_PCIE_RESET0_MASK),
-	AIROHA_PINCTRL_GPIO_EXT("gpio50", GPIO50_FLASH_MODE_CFG,
-				GPIO_PCIE_RESET1_MASK),
-	AIROHA_PINCTRL_GPIO_EXT("gpio51", GPIO51_FLASH_MODE_CFG,
-				AN7583_MDC_0_GPIO_MODE_MASK),
-	AIROHA_PINCTRL_GPIO("gpio52", AN7583_MDIO_0_GPIO_MODE_MASK),
-};
-
-static const struct airoha_pinctrl_func_group an7583_pcie_reset_func_group[] = {
-	{
-		.name = "pcie_reset0",
-		.regmap[0] = {
-			AIROHA_FUNC_MUX,
-			REG_GPIO_PON_MODE,
-			GPIO_PCIE_RESET0_MASK,
-			0
-		},
-		.regmap_size = 1,
-	}, {
-		.name = "pcie_reset1",
-		.regmap[0] = {
-			AIROHA_FUNC_MUX,
-			REG_GPIO_PON_MODE,
-			GPIO_PCIE_RESET1_MASK,
-			0
-		},
-		.regmap_size = 1,
-	},
-};
-
-static const struct airoha_pinctrl_func_group pwm_func_group[] = {
-	AIROHA_PINCTRL_PWM("gpio0", GPIO0_FLASH_MODE_CFG),
-	AIROHA_PINCTRL_PWM("gpio1", GPIO1_FLASH_MODE_CFG),
-	AIROHA_PINCTRL_PWM("gpio2", GPIO2_FLASH_MODE_CFG),
-	AIROHA_PINCTRL_PWM("gpio3", GPIO3_FLASH_MODE_CFG),
-	AIROHA_PINCTRL_PWM("gpio4", GPIO4_FLASH_MODE_CFG),
-	AIROHA_PINCTRL_PWM("gpio5", GPIO5_FLASH_MODE_CFG),
-	AIROHA_PINCTRL_PWM("gpio6", GPIO6_FLASH_MODE_CFG),
-	AIROHA_PINCTRL_PWM("gpio7", GPIO7_FLASH_MODE_CFG),
-	AIROHA_PINCTRL_PWM("gpio8", GPIO8_FLASH_MODE_CFG),
-	AIROHA_PINCTRL_PWM("gpio9", GPIO9_FLASH_MODE_CFG),
-	AIROHA_PINCTRL_PWM("gpio10", GPIO10_FLASH_MODE_CFG),
-	AIROHA_PINCTRL_PWM("gpio11", GPIO11_FLASH_MODE_CFG),
-	AIROHA_PINCTRL_PWM("gpio12", GPIO12_FLASH_MODE_CFG),
-	AIROHA_PINCTRL_PWM("gpio13", GPIO13_FLASH_MODE_CFG),
-	AIROHA_PINCTRL_PWM("gpio14", GPIO14_FLASH_MODE_CFG),
-	AIROHA_PINCTRL_PWM("gpio15", GPIO15_FLASH_MODE_CFG),
-	AIROHA_PINCTRL_PWM_EXT("gpio16", GPIO16_FLASH_MODE_CFG),
-	AIROHA_PINCTRL_PWM_EXT("gpio17", GPIO17_FLASH_MODE_CFG),
-	AIROHA_PINCTRL_PWM_EXT("gpio18", GPIO18_FLASH_MODE_CFG),
-	AIROHA_PINCTRL_PWM_EXT("gpio19", GPIO19_FLASH_MODE_CFG),
-	AIROHA_PINCTRL_PWM_EXT("gpio20", GPIO20_FLASH_MODE_CFG),
-	AIROHA_PINCTRL_PWM_EXT("gpio21", GPIO21_FLASH_MODE_CFG),
-	AIROHA_PINCTRL_PWM_EXT("gpio22", GPIO22_FLASH_MODE_CFG),
-	AIROHA_PINCTRL_PWM_EXT("gpio23", GPIO23_FLASH_MODE_CFG),
-	AIROHA_PINCTRL_PWM_EXT("gpio24", GPIO24_FLASH_MODE_CFG),
-	AIROHA_PINCTRL_PWM_EXT("gpio25", GPIO25_FLASH_MODE_CFG),
-	AIROHA_PINCTRL_PWM_EXT("gpio26", GPIO26_FLASH_MODE_CFG),
-	AIROHA_PINCTRL_PWM_EXT("gpio27", GPIO27_FLASH_MODE_CFG),
-	AIROHA_PINCTRL_PWM_EXT("gpio28", GPIO28_FLASH_MODE_CFG),
-	AIROHA_PINCTRL_PWM_EXT("gpio29", GPIO29_FLASH_MODE_CFG),
-	AIROHA_PINCTRL_PWM_EXT("gpio30", GPIO30_FLASH_MODE_CFG),
-	AIROHA_PINCTRL_PWM_EXT("gpio31", GPIO31_FLASH_MODE_CFG),
-	AIROHA_PINCTRL_PWM_EXT("gpio36", GPIO36_FLASH_MODE_CFG),
-	AIROHA_PINCTRL_PWM_EXT("gpio37", GPIO37_FLASH_MODE_CFG),
-	AIROHA_PINCTRL_PWM_EXT("gpio38", GPIO38_FLASH_MODE_CFG),
-	AIROHA_PINCTRL_PWM_EXT("gpio39", GPIO39_FLASH_MODE_CFG),
-	AIROHA_PINCTRL_PWM_EXT("gpio40", GPIO40_FLASH_MODE_CFG),
-	AIROHA_PINCTRL_PWM_EXT("gpio41", GPIO41_FLASH_MODE_CFG),
-	AIROHA_PINCTRL_PWM_EXT("gpio42", GPIO42_FLASH_MODE_CFG),
-	AIROHA_PINCTRL_PWM_EXT("gpio43", GPIO43_FLASH_MODE_CFG),
-	AIROHA_PINCTRL_PWM_EXT("gpio44", GPIO44_FLASH_MODE_CFG),
-	AIROHA_PINCTRL_PWM_EXT("gpio45", GPIO45_FLASH_MODE_CFG),
-	AIROHA_PINCTRL_PWM_EXT("gpio46", GPIO46_FLASH_MODE_CFG),
-	AIROHA_PINCTRL_PWM_EXT_SEC("gpio47", GPIO47_FLASH_MODE_CFG,
-				   GPIO_PCIE_RESET0_MASK),
-	AIROHA_PINCTRL_PWM_EXT_SEC("gpio48", GPIO48_FLASH_MODE_CFG,
-				   GPIO_PCIE_RESET1_MASK),
-	AIROHA_PINCTRL_PWM_EXT_SEC("gpio49", GPIO49_FLASH_MODE_CFG,
-				   GPIO_PCIE_RESET2_MASK),
-};
-
-static const struct airoha_pinctrl_func_group an7583_pwm_func_group[] = {
-	AIROHA_PINCTRL_PWM("gpio0", GPIO0_FLASH_MODE_CFG),
-	AIROHA_PINCTRL_PWM("gpio1", GPIO1_FLASH_MODE_CFG),
-	AIROHA_PINCTRL_PWM("gpio2", GPIO2_FLASH_MODE_CFG),
-	AIROHA_PINCTRL_PWM("gpio3", GPIO3_FLASH_MODE_CFG),
-	AIROHA_PINCTRL_PWM("gpio4", GPIO4_FLASH_MODE_CFG),
-	AIROHA_PINCTRL_PWM("gpio5", GPIO5_FLASH_MODE_CFG),
-	AIROHA_PINCTRL_PWM("gpio6", GPIO6_FLASH_MODE_CFG),
-	AIROHA_PINCTRL_PWM("gpio7", GPIO7_FLASH_MODE_CFG),
-	AIROHA_PINCTRL_PWM("gpio8", GPIO8_FLASH_MODE_CFG),
-	AIROHA_PINCTRL_PWM("gpio9", GPIO9_FLASH_MODE_CFG),
-	AIROHA_PINCTRL_PWM("gpio10", GPIO10_FLASH_MODE_CFG),
-	AIROHA_PINCTRL_PWM("gpio11", GPIO11_FLASH_MODE_CFG),
-	AIROHA_PINCTRL_PWM("gpio12", GPIO12_FLASH_MODE_CFG),
-	AIROHA_PINCTRL_PWM("gpio13", GPIO13_FLASH_MODE_CFG),
-	AIROHA_PINCTRL_PWM("gpio14", GPIO14_FLASH_MODE_CFG),
-	AIROHA_PINCTRL_PWM("gpio15", GPIO15_FLASH_MODE_CFG),
-	AIROHA_PINCTRL_PWM_EXT("gpio16", GPIO16_FLASH_MODE_CFG),
-	AIROHA_PINCTRL_PWM_EXT("gpio17", GPIO17_FLASH_MODE_CFG),
-	AIROHA_PINCTRL_PWM_EXT("gpio18", GPIO18_FLASH_MODE_CFG),
-	AIROHA_PINCTRL_PWM_EXT("gpio19", GPIO19_FLASH_MODE_CFG),
-	AIROHA_PINCTRL_PWM_EXT("gpio20", GPIO20_FLASH_MODE_CFG),
-	AIROHA_PINCTRL_PWM_EXT("gpio21", GPIO21_FLASH_MODE_CFG),
-	AIROHA_PINCTRL_PWM_EXT("gpio22", GPIO22_FLASH_MODE_CFG),
-	AIROHA_PINCTRL_PWM_EXT("gpio23", GPIO23_FLASH_MODE_CFG),
-	AIROHA_PINCTRL_PWM_EXT("gpio24", GPIO24_FLASH_MODE_CFG),
-	AIROHA_PINCTRL_PWM_EXT("gpio25", GPIO25_FLASH_MODE_CFG),
-	AIROHA_PINCTRL_PWM_EXT("gpio26", GPIO26_FLASH_MODE_CFG),
-	AIROHA_PINCTRL_PWM_EXT("gpio27", GPIO27_FLASH_MODE_CFG),
-	AIROHA_PINCTRL_PWM_EXT("gpio28", GPIO28_FLASH_MODE_CFG),
-	AIROHA_PINCTRL_PWM_EXT("gpio29", GPIO29_FLASH_MODE_CFG),
-	AIROHA_PINCTRL_PWM_EXT("gpio30", GPIO30_FLASH_MODE_CFG),
-	AIROHA_PINCTRL_PWM_EXT("gpio31", GPIO31_FLASH_MODE_CFG),
-	AIROHA_PINCTRL_PWM_EXT("gpio36", GPIO36_FLASH_MODE_CFG),
-	AIROHA_PINCTRL_PWM_EXT("gpio37", GPIO37_FLASH_MODE_CFG),
-	AIROHA_PINCTRL_PWM_EXT("gpio38", GPIO38_FLASH_MODE_CFG),
-	AIROHA_PINCTRL_PWM_EXT_SEC("gpio39", GPIO39_FLASH_MODE_CFG,
-				   AN7583_I2C0_SCL_GPIO_MODE_MASK),
-	AIROHA_PINCTRL_PWM_EXT_SEC("gpio40", GPIO40_FLASH_MODE_CFG,
-				   AN7583_I2C0_SDA_GPIO_MODE_MASK),
-	AIROHA_PINCTRL_PWM_EXT_SEC("gpio41", GPIO41_FLASH_MODE_CFG,
-				   AN7583_I2C1_SCL_GPIO_MODE_MASK),
-	AIROHA_PINCTRL_PWM_EXT_SEC("gpio42", GPIO42_FLASH_MODE_CFG,
-				   AN7583_I2C1_SDA_GPIO_MODE_MASK),
-	AIROHA_PINCTRL_PWM_EXT_SEC("gpio43", GPIO43_FLASH_MODE_CFG,
-				   AN7583_SPI_CLK_GPIO_MODE_MASK),
-	AIROHA_PINCTRL_PWM_EXT_SEC("gpio44", GPIO44_FLASH_MODE_CFG,
-				   AN7583_SPI_CS_GPIO_MODE_MASK),
-	AIROHA_PINCTRL_PWM_EXT_SEC("gpio45", GPIO45_FLASH_MODE_CFG,
-				   AN7583_SPI_MOSI_GPIO_MODE_MASK),
-	AIROHA_PINCTRL_PWM_EXT_SEC("gpio46", GPIO46_FLASH_MODE_CFG,
-				   AN7583_SPI_MISO_GPIO_MODE_MASK),
-	AIROHA_PINCTRL_PWM_EXT_SEC("gpio47", GPIO47_FLASH_MODE_CFG,
-				   AN7583_UART_TXD_GPIO_MODE_MASK),
-	AIROHA_PINCTRL_PWM_EXT_SEC("gpio48", GPIO48_FLASH_MODE_CFG,
-				   AN7583_UART_RXD_GPIO_MODE_MASK),
-	AIROHA_PINCTRL_PWM_EXT_SEC("gpio49", GPIO49_FLASH_MODE_CFG,
-				   GPIO_PCIE_RESET0_MASK),
-	AIROHA_PINCTRL_PWM_EXT_SEC("gpio50", GPIO50_FLASH_MODE_CFG,
-				   GPIO_PCIE_RESET1_MASK),
-	AIROHA_PINCTRL_PWM_EXT_SEC("gpio51", GPIO51_FLASH_MODE_CFG,
-				   AN7583_MDC_0_GPIO_MODE_MASK),
-};
-
-static const struct airoha_pinctrl_func_group phy1_led0_func_group[] = {
-	AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK,
-				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),
-	AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK,
-				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)),
-	AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK,
-				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)),
-	AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK,
-				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),
-};
-
-static const struct airoha_pinctrl_func_group phy2_led0_func_group[] = {
-	AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK,
-				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),
-	AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK,
-				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)),
-	AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK,
-				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)),
-	AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK,
-				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),
-};
-
-static const struct airoha_pinctrl_func_group phy3_led0_func_group[] = {
-	AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK,
-				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
-	AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK,
-				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),
-	AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK,
-				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),
-	AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK,
-				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
-};
-
-static const struct airoha_pinctrl_func_group phy4_led0_func_group[] = {
-	AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK,
-				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)),
-	AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK,
-				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)),
-	AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK,
-				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)),
-	AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK,
-				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)),
-};
-
-static const struct airoha_pinctrl_func_group phy1_led1_func_group[] = {
-	AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK,
-				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),
-	AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK,
-				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)),
-	AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK,
-				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)),
-	AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK,
-				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),
-};
-
-static const struct airoha_pinctrl_func_group phy2_led1_func_group[] = {
-	AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK,
-				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),
-	AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK,
-				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)),
-	AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK,
-				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)),
-	AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK,
-				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),
-};
-
-static const struct airoha_pinctrl_func_group phy3_led1_func_group[] = {
-	AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK,
-				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
-	AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK,
-				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),
-	AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK,
-				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),
-	AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK,
-				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
-};
-
-static const struct airoha_pinctrl_func_group phy4_led1_func_group[] = {
-	AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK,
-				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)),
-	AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK,
-				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)),
-	AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK,
-				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)),
-	AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK,
-				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)),
-};
-
-static const struct airoha_pinctrl_func_group an7583_phy1_led0_func_group[] = {
-	AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK,
-				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),
-	AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK,
-				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)),
-	AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK,
-				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)),
-	AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK,
-				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),
-};
-
-static const struct airoha_pinctrl_func_group an7583_phy2_led0_func_group[] = {
-	AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK,
-				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),
-	AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK,
-				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)),
-	AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK,
-				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)),
-	AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK,
-				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),
-};
-
-static const struct airoha_pinctrl_func_group an7583_phy3_led0_func_group[] = {
-	AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK,
-				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
-	AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK,
-				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),
-	AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK,
-				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),
-	AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK,
-				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
-};
-
-static const struct airoha_pinctrl_func_group an7583_phy4_led0_func_group[] = {
-	AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK,
-				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)),
-	AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK,
-				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)),
-	AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK,
-				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)),
-	AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK,
-				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)),
-};
-
-static const struct airoha_pinctrl_func_group an7583_phy1_led1_func_group[] = {
-	AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK,
-				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),
-	AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK,
-				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)),
-	AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK,
-				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)),
-	AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK,
-				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),
-};
-
-static const struct airoha_pinctrl_func_group an7583_phy2_led1_func_group[] = {
-	AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK,
-				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),
-	AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK,
-				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)),
-	AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK,
-				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)),
-	AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK,
-				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),
-};
-
-static const struct airoha_pinctrl_func_group an7583_phy3_led1_func_group[] = {
-	AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK,
-				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
-	AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK,
-				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),
-	AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK,
-				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),
-	AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK,
-				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
-};
-
-static const struct airoha_pinctrl_func_group an7583_phy4_led1_func_group[] = {
-	AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK,
-				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)),
-	AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK,
-				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)),
-	AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK,
-				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)),
-	AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK,
-				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)),
-};
-
-static const struct airoha_pinctrl_func en7581_pinctrl_funcs[] = {
-	PINCTRL_FUNC_DESC("pon", pon),
-	PINCTRL_FUNC_DESC("tod_1pps", tod_1pps),
-	PINCTRL_FUNC_DESC("sipo", sipo),
-	PINCTRL_FUNC_DESC("mdio", mdio),
-	PINCTRL_FUNC_DESC("uart", uart),
-	PINCTRL_FUNC_DESC("i2c", i2c),
-	PINCTRL_FUNC_DESC("jtag", jtag),
-	PINCTRL_FUNC_DESC("pcm", pcm),
-	PINCTRL_FUNC_DESC("spi", spi),
-	PINCTRL_FUNC_DESC("pcm_spi", pcm_spi),
-	PINCTRL_FUNC_DESC("i2s", i2s),
-	PINCTRL_FUNC_DESC("emmc", emmc),
-	PINCTRL_FUNC_DESC("pnand", pnand),
-	PINCTRL_FUNC_DESC("gpio", gpio),
-	PINCTRL_FUNC_DESC("pcie_reset", pcie_reset),
-	PINCTRL_FUNC_DESC("pwm", pwm),
-	PINCTRL_FUNC_DESC("phy1_led0", phy1_led0),
-	PINCTRL_FUNC_DESC("phy2_led0", phy2_led0),
-	PINCTRL_FUNC_DESC("phy3_led0", phy3_led0),
-	PINCTRL_FUNC_DESC("phy4_led0", phy4_led0),
-	PINCTRL_FUNC_DESC("phy1_led1", phy1_led1),
-	PINCTRL_FUNC_DESC("phy2_led1", phy2_led1),
-	PINCTRL_FUNC_DESC("phy3_led1", phy3_led1),
-	PINCTRL_FUNC_DESC("phy4_led1", phy4_led1),
-};
-
-static const struct airoha_pinctrl_func an7583_pinctrl_funcs[] = {
-	PINCTRL_FUNC_DESC("pon", pon),
-	PINCTRL_FUNC_DESC("tod_1pps", tod_1pps),
-	PINCTRL_FUNC_DESC("sipo", sipo),
-	PINCTRL_FUNC_DESC("mdio", an7583_mdio),
-	PINCTRL_FUNC_DESC("uart", uart),
-	PINCTRL_FUNC_DESC("jtag", jtag),
-	PINCTRL_FUNC_DESC("pcm", pcm),
-	PINCTRL_FUNC_DESC("spi", spi),
-	PINCTRL_FUNC_DESC("pcm_spi", an7583_pcm_spi),
-	PINCTRL_FUNC_DESC("emmc", emmc),
-	PINCTRL_FUNC_DESC("pnand", pnand),
-	PINCTRL_FUNC_DESC("gpio", an7583_gpio),
-	PINCTRL_FUNC_DESC("pcie_reset", an7583_pcie_reset),
-	PINCTRL_FUNC_DESC("pwm", an7583_pwm),
-	PINCTRL_FUNC_DESC("phy1_led0", an7583_phy1_led0),
-	PINCTRL_FUNC_DESC("phy2_led0", an7583_phy2_led0),
-	PINCTRL_FUNC_DESC("phy3_led0", an7583_phy3_led0),
-	PINCTRL_FUNC_DESC("phy4_led0", an7583_phy4_led0),
-	PINCTRL_FUNC_DESC("phy1_led1", an7583_phy1_led1),
-	PINCTRL_FUNC_DESC("phy2_led1", an7583_phy2_led1),
-	PINCTRL_FUNC_DESC("phy3_led1", an7583_phy3_led1),
-	PINCTRL_FUNC_DESC("phy4_led1", an7583_phy4_led1),
-};
-
-static const struct airoha_pinctrl_conf en7581_pinctrl_pullup_conf[] = {
-	PINCTRL_CONF_DESC(0, REG_I2C_SDA_PU, UART1_TXD_PU_MASK),
-	PINCTRL_CONF_DESC(1, REG_I2C_SDA_PU, UART1_RXD_PU_MASK),
-	PINCTRL_CONF_DESC(2, REG_I2C_SDA_PU, I2C_SDA_PU_MASK),
-	PINCTRL_CONF_DESC(3, REG_I2C_SDA_PU, I2C_SCL_PU_MASK),
-	PINCTRL_CONF_DESC(4, REG_I2C_SDA_PU, SPI_CS0_PU_MASK),
-	PINCTRL_CONF_DESC(5, REG_I2C_SDA_PU, SPI_CLK_PU_MASK),
-	PINCTRL_CONF_DESC(6, REG_I2C_SDA_PU, SPI_MOSI_PU_MASK),
-	PINCTRL_CONF_DESC(7, REG_I2C_SDA_PU, SPI_MISO_PU_MASK),
-	PINCTRL_CONF_DESC(13, REG_GPIO_L_PU, BIT(0)),
-	PINCTRL_CONF_DESC(14, REG_GPIO_L_PU, BIT(1)),
-	PINCTRL_CONF_DESC(15, REG_GPIO_L_PU, BIT(2)),
-	PINCTRL_CONF_DESC(16, REG_GPIO_L_PU, BIT(3)),
-	PINCTRL_CONF_DESC(17, REG_GPIO_L_PU, BIT(4)),
-	PINCTRL_CONF_DESC(18, REG_GPIO_L_PU, BIT(5)),
-	PINCTRL_CONF_DESC(19, REG_GPIO_L_PU, BIT(6)),
-	PINCTRL_CONF_DESC(20, REG_GPIO_L_PU, BIT(7)),
-	PINCTRL_CONF_DESC(21, REG_GPIO_L_PU, BIT(8)),
-	PINCTRL_CONF_DESC(22, REG_GPIO_L_PU, BIT(9)),
-	PINCTRL_CONF_DESC(23, REG_GPIO_L_PU, BIT(10)),
-	PINCTRL_CONF_DESC(24, REG_GPIO_L_PU, BIT(11)),
-	PINCTRL_CONF_DESC(25, REG_GPIO_L_PU, BIT(12)),
-	PINCTRL_CONF_DESC(26, REG_GPIO_L_PU, BIT(13)),
-	PINCTRL_CONF_DESC(27, REG_GPIO_L_PU, BIT(14)),
-	PINCTRL_CONF_DESC(28, REG_GPIO_L_PU, BIT(15)),
-	PINCTRL_CONF_DESC(29, REG_GPIO_L_PU, BIT(16)),
-	PINCTRL_CONF_DESC(30, REG_GPIO_L_PU, BIT(17)),
-	PINCTRL_CONF_DESC(31, REG_GPIO_L_PU, BIT(18)),
-	PINCTRL_CONF_DESC(32, REG_GPIO_L_PU, BIT(19)),
-	PINCTRL_CONF_DESC(33, REG_GPIO_L_PU, BIT(20)),
-	PINCTRL_CONF_DESC(34, REG_GPIO_L_PU, BIT(21)),
-	PINCTRL_CONF_DESC(35, REG_GPIO_L_PU, BIT(22)),
-	PINCTRL_CONF_DESC(36, REG_GPIO_L_PU, BIT(23)),
-	PINCTRL_CONF_DESC(37, REG_GPIO_L_PU, BIT(24)),
-	PINCTRL_CONF_DESC(38, REG_GPIO_L_PU, BIT(25)),
-	PINCTRL_CONF_DESC(39, REG_GPIO_L_PU, BIT(26)),
-	PINCTRL_CONF_DESC(40, REG_GPIO_L_PU, BIT(27)),
-	PINCTRL_CONF_DESC(41, REG_GPIO_L_PU, BIT(28)),
-	PINCTRL_CONF_DESC(42, REG_GPIO_L_PU, BIT(29)),
-	PINCTRL_CONF_DESC(43, REG_GPIO_L_PU, BIT(30)),
-	PINCTRL_CONF_DESC(44, REG_GPIO_L_PU, BIT(31)),
-	PINCTRL_CONF_DESC(45, REG_GPIO_H_PU, BIT(0)),
-	PINCTRL_CONF_DESC(46, REG_GPIO_H_PU, BIT(1)),
-	PINCTRL_CONF_DESC(47, REG_GPIO_H_PU, BIT(2)),
-	PINCTRL_CONF_DESC(48, REG_GPIO_H_PU, BIT(3)),
-	PINCTRL_CONF_DESC(49, REG_GPIO_H_PU, BIT(4)),
-	PINCTRL_CONF_DESC(50, REG_GPIO_H_PU, BIT(5)),
-	PINCTRL_CONF_DESC(51, REG_GPIO_H_PU, BIT(6)),
-	PINCTRL_CONF_DESC(52, REG_GPIO_H_PU, BIT(7)),
-	PINCTRL_CONF_DESC(53, REG_GPIO_H_PU, BIT(8)),
-	PINCTRL_CONF_DESC(54, REG_GPIO_H_PU, BIT(9)),
-	PINCTRL_CONF_DESC(55, REG_GPIO_H_PU, BIT(10)),
-	PINCTRL_CONF_DESC(56, REG_GPIO_H_PU, BIT(11)),
-	PINCTRL_CONF_DESC(57, REG_GPIO_H_PU, BIT(12)),
-	PINCTRL_CONF_DESC(58, REG_GPIO_H_PU, BIT(13)),
-	PINCTRL_CONF_DESC(59, REG_GPIO_H_PU, BIT(14)),
-	PINCTRL_CONF_DESC(60, REG_I2C_SDA_PU, PCIE0_RESET_PU_MASK),
-	PINCTRL_CONF_DESC(61, REG_I2C_SDA_PU, PCIE1_RESET_PU_MASK),
-	PINCTRL_CONF_DESC(62, REG_I2C_SDA_PU, PCIE2_RESET_PU_MASK),
-};
-
-static const struct airoha_pinctrl_conf an7583_pinctrl_pullup_conf[] = {
-	PINCTRL_CONF_DESC(2, REG_GPIO_L_PU, BIT(0)),
-	PINCTRL_CONF_DESC(3, REG_GPIO_L_PU, BIT(1)),
-	PINCTRL_CONF_DESC(4, REG_GPIO_L_PU, BIT(2)),
-	PINCTRL_CONF_DESC(5, REG_GPIO_L_PU, BIT(3)),
-	PINCTRL_CONF_DESC(6, REG_GPIO_L_PU, BIT(4)),
-	PINCTRL_CONF_DESC(7, REG_GPIO_L_PU, BIT(5)),
-	PINCTRL_CONF_DESC(8, REG_GPIO_L_PU, BIT(6)),
-	PINCTRL_CONF_DESC(9, REG_GPIO_L_PU, BIT(7)),
-	PINCTRL_CONF_DESC(10, REG_GPIO_L_PU, BIT(8)),
-	PINCTRL_CONF_DESC(11, REG_GPIO_L_PU, BIT(9)),
-	PINCTRL_CONF_DESC(12, REG_GPIO_L_PU, BIT(10)),
-	PINCTRL_CONF_DESC(13, REG_GPIO_L_PU, BIT(11)),
-	PINCTRL_CONF_DESC(14, REG_GPIO_L_PU, BIT(12)),
-	PINCTRL_CONF_DESC(15, REG_GPIO_L_PU, BIT(13)),
-	PINCTRL_CONF_DESC(16, REG_GPIO_L_PU, BIT(14)),
-	PINCTRL_CONF_DESC(17, REG_GPIO_L_PU, BIT(15)),
-	PINCTRL_CONF_DESC(18, REG_GPIO_L_PU, BIT(16)),
-	PINCTRL_CONF_DESC(19, REG_GPIO_L_PU, BIT(17)),
-	PINCTRL_CONF_DESC(20, REG_GPIO_L_PU, BIT(18)),
-	PINCTRL_CONF_DESC(21, REG_GPIO_L_PU, BIT(19)),
-	PINCTRL_CONF_DESC(22, REG_GPIO_L_PU, BIT(20)),
-	PINCTRL_CONF_DESC(23, REG_GPIO_L_PU, BIT(21)),
-	PINCTRL_CONF_DESC(24, REG_GPIO_L_PU, BIT(22)),
-	PINCTRL_CONF_DESC(25, REG_GPIO_L_PU, BIT(23)),
-	PINCTRL_CONF_DESC(26, REG_GPIO_L_PU, BIT(24)),
-	PINCTRL_CONF_DESC(27, REG_GPIO_L_PU, BIT(25)),
-	PINCTRL_CONF_DESC(28, REG_GPIO_L_PU, BIT(26)),
-	PINCTRL_CONF_DESC(29, REG_GPIO_L_PU, BIT(27)),
-	PINCTRL_CONF_DESC(30, REG_GPIO_L_PU, BIT(28)),
-	PINCTRL_CONF_DESC(31, REG_GPIO_L_PU, BIT(29)),
-	PINCTRL_CONF_DESC(32, REG_GPIO_L_PU, BIT(30)),
-	PINCTRL_CONF_DESC(33, REG_GPIO_L_PU, BIT(31)),
-	PINCTRL_CONF_DESC(34, REG_GPIO_H_PU, BIT(0)),
-	PINCTRL_CONF_DESC(35, REG_GPIO_H_PU, BIT(1)),
-	PINCTRL_CONF_DESC(36, REG_GPIO_H_PU, BIT(2)),
-	PINCTRL_CONF_DESC(37, REG_GPIO_H_PU, BIT(3)),
-	PINCTRL_CONF_DESC(38, REG_GPIO_H_PU, BIT(4)),
-	PINCTRL_CONF_DESC(39, REG_GPIO_H_PU, BIT(5)),
-	PINCTRL_CONF_DESC(40, REG_GPIO_H_PU, BIT(6)),
-	PINCTRL_CONF_DESC(41, REG_I2C_SDA_PU, I2C_SCL_PU_MASK),
-	PINCTRL_CONF_DESC(42, REG_I2C_SDA_PU, I2C_SDA_PU_MASK),
-	PINCTRL_CONF_DESC(43, REG_I2C_SDA_PU, AN7583_I2C1_SCL_PU_MASK),
-	PINCTRL_CONF_DESC(44, REG_I2C_SDA_PU, AN7583_I2C1_SDA_PU_MASK),
-	PINCTRL_CONF_DESC(45, REG_I2C_SDA_PU, SPI_CLK_PU_MASK),
-	PINCTRL_CONF_DESC(46, REG_I2C_SDA_PU, SPI_CS0_PU_MASK),
-	PINCTRL_CONF_DESC(47, REG_I2C_SDA_PU, SPI_MOSI_PU_MASK),
-	PINCTRL_CONF_DESC(48, REG_I2C_SDA_PU, SPI_MISO_PU_MASK),
-	PINCTRL_CONF_DESC(49, REG_I2C_SDA_PU, UART1_TXD_PU_MASK),
-	PINCTRL_CONF_DESC(50, REG_I2C_SDA_PU, UART1_RXD_PU_MASK),
-	PINCTRL_CONF_DESC(51, REG_I2C_SDA_PU, PCIE0_RESET_PU_MASK),
-	PINCTRL_CONF_DESC(52, REG_I2C_SDA_PU, PCIE1_RESET_PU_MASK),
-	PINCTRL_CONF_DESC(53, REG_I2C_SDA_PU, AN7583_MDC_0_PU_MASK),
-	PINCTRL_CONF_DESC(54, REG_I2C_SDA_PU, AN7583_MDIO_0_PU_MASK),
-};
-
-static const struct airoha_pinctrl_conf en7581_pinctrl_pulldown_conf[] = {
-	PINCTRL_CONF_DESC(0, REG_I2C_SDA_PD, UART1_TXD_PD_MASK),
-	PINCTRL_CONF_DESC(1, REG_I2C_SDA_PD, UART1_RXD_PD_MASK),
-	PINCTRL_CONF_DESC(2, REG_I2C_SDA_PD, I2C_SDA_PD_MASK),
-	PINCTRL_CONF_DESC(3, REG_I2C_SDA_PD, I2C_SCL_PD_MASK),
-	PINCTRL_CONF_DESC(4, REG_I2C_SDA_PD, SPI_CS0_PD_MASK),
-	PINCTRL_CONF_DESC(5, REG_I2C_SDA_PD, SPI_CLK_PD_MASK),
-	PINCTRL_CONF_DESC(6, REG_I2C_SDA_PD, SPI_MOSI_PD_MASK),
-	PINCTRL_CONF_DESC(7, REG_I2C_SDA_PD, SPI_MISO_PD_MASK),
-	PINCTRL_CONF_DESC(13, REG_GPIO_L_PD, BIT(0)),
-	PINCTRL_CONF_DESC(14, REG_GPIO_L_PD, BIT(1)),
-	PINCTRL_CONF_DESC(15, REG_GPIO_L_PD, BIT(2)),
-	PINCTRL_CONF_DESC(16, REG_GPIO_L_PD, BIT(3)),
-	PINCTRL_CONF_DESC(17, REG_GPIO_L_PD, BIT(4)),
-	PINCTRL_CONF_DESC(18, REG_GPIO_L_PD, BIT(5)),
-	PINCTRL_CONF_DESC(19, REG_GPIO_L_PD, BIT(6)),
-	PINCTRL_CONF_DESC(20, REG_GPIO_L_PD, BIT(7)),
-	PINCTRL_CONF_DESC(21, REG_GPIO_L_PD, BIT(8)),
-	PINCTRL_CONF_DESC(22, REG_GPIO_L_PD, BIT(9)),
-	PINCTRL_CONF_DESC(23, REG_GPIO_L_PD, BIT(10)),
-	PINCTRL_CONF_DESC(24, REG_GPIO_L_PD, BIT(11)),
-	PINCTRL_CONF_DESC(25, REG_GPIO_L_PD, BIT(12)),
-	PINCTRL_CONF_DESC(26, REG_GPIO_L_PD, BIT(13)),
-	PINCTRL_CONF_DESC(27, REG_GPIO_L_PD, BIT(14)),
-	PINCTRL_CONF_DESC(28, REG_GPIO_L_PD, BIT(15)),
-	PINCTRL_CONF_DESC(29, REG_GPIO_L_PD, BIT(16)),
-	PINCTRL_CONF_DESC(30, REG_GPIO_L_PD, BIT(17)),
-	PINCTRL_CONF_DESC(31, REG_GPIO_L_PD, BIT(18)),
-	PINCTRL_CONF_DESC(32, REG_GPIO_L_PD, BIT(19)),
-	PINCTRL_CONF_DESC(33, REG_GPIO_L_PD, BIT(20)),
-	PINCTRL_CONF_DESC(34, REG_GPIO_L_PD, BIT(21)),
-	PINCTRL_CONF_DESC(35, REG_GPIO_L_PD, BIT(22)),
-	PINCTRL_CONF_DESC(36, REG_GPIO_L_PD, BIT(23)),
-	PINCTRL_CONF_DESC(37, REG_GPIO_L_PD, BIT(24)),
-	PINCTRL_CONF_DESC(38, REG_GPIO_L_PD, BIT(25)),
-	PINCTRL_CONF_DESC(39, REG_GPIO_L_PD, BIT(26)),
-	PINCTRL_CONF_DESC(40, REG_GPIO_L_PD, BIT(27)),
-	PINCTRL_CONF_DESC(41, REG_GPIO_L_PD, BIT(28)),
-	PINCTRL_CONF_DESC(42, REG_GPIO_L_PD, BIT(29)),
-	PINCTRL_CONF_DESC(43, REG_GPIO_L_PD, BIT(30)),
-	PINCTRL_CONF_DESC(44, REG_GPIO_L_PD, BIT(31)),
-	PINCTRL_CONF_DESC(45, REG_GPIO_H_PD, BIT(0)),
-	PINCTRL_CONF_DESC(46, REG_GPIO_H_PD, BIT(1)),
-	PINCTRL_CONF_DESC(47, REG_GPIO_H_PD, BIT(2)),
-	PINCTRL_CONF_DESC(48, REG_GPIO_H_PD, BIT(3)),
-	PINCTRL_CONF_DESC(49, REG_GPIO_H_PD, BIT(4)),
-	PINCTRL_CONF_DESC(50, REG_GPIO_H_PD, BIT(5)),
-	PINCTRL_CONF_DESC(51, REG_GPIO_H_PD, BIT(6)),
-	PINCTRL_CONF_DESC(52, REG_GPIO_H_PD, BIT(7)),
-	PINCTRL_CONF_DESC(53, REG_GPIO_H_PD, BIT(8)),
-	PINCTRL_CONF_DESC(54, REG_GPIO_H_PD, BIT(9)),
-	PINCTRL_CONF_DESC(55, REG_GPIO_H_PD, BIT(10)),
-	PINCTRL_CONF_DESC(56, REG_GPIO_H_PD, BIT(11)),
-	PINCTRL_CONF_DESC(57, REG_GPIO_H_PD, BIT(12)),
-	PINCTRL_CONF_DESC(58, REG_GPIO_H_PD, BIT(13)),
-	PINCTRL_CONF_DESC(59, REG_GPIO_H_PD, BIT(14)),
-	PINCTRL_CONF_DESC(60, REG_I2C_SDA_PD, PCIE0_RESET_PD_MASK),
-	PINCTRL_CONF_DESC(61, REG_I2C_SDA_PD, PCIE1_RESET_PD_MASK),
-	PINCTRL_CONF_DESC(62, REG_I2C_SDA_PD, PCIE2_RESET_PD_MASK),
-};
-
-static const struct airoha_pinctrl_conf an7583_pinctrl_pulldown_conf[] = {
-	PINCTRL_CONF_DESC(2, REG_GPIO_L_PD, BIT(0)),
-	PINCTRL_CONF_DESC(3, REG_GPIO_L_PD, BIT(1)),
-	PINCTRL_CONF_DESC(4, REG_GPIO_L_PD, BIT(2)),
-	PINCTRL_CONF_DESC(5, REG_GPIO_L_PD, BIT(3)),
-	PINCTRL_CONF_DESC(6, REG_GPIO_L_PD, BIT(4)),
-	PINCTRL_CONF_DESC(7, REG_GPIO_L_PD, BIT(5)),
-	PINCTRL_CONF_DESC(8, REG_GPIO_L_PD, BIT(6)),
-	PINCTRL_CONF_DESC(9, REG_GPIO_L_PD, BIT(7)),
-	PINCTRL_CONF_DESC(10, REG_GPIO_L_PD, BIT(8)),
-	PINCTRL_CONF_DESC(11, REG_GPIO_L_PD, BIT(9)),
-	PINCTRL_CONF_DESC(12, REG_GPIO_L_PD, BIT(10)),
-	PINCTRL_CONF_DESC(13, REG_GPIO_L_PD, BIT(11)),
-	PINCTRL_CONF_DESC(14, REG_GPIO_L_PD, BIT(12)),
-	PINCTRL_CONF_DESC(15, REG_GPIO_L_PD, BIT(13)),
-	PINCTRL_CONF_DESC(16, REG_GPIO_L_PD, BIT(14)),
-	PINCTRL_CONF_DESC(17, REG_GPIO_L_PD, BIT(15)),
-	PINCTRL_CONF_DESC(18, REG_GPIO_L_PD, BIT(16)),
-	PINCTRL_CONF_DESC(19, REG_GPIO_L_PD, BIT(17)),
-	PINCTRL_CONF_DESC(20, REG_GPIO_L_PD, BIT(18)),
-	PINCTRL_CONF_DESC(21, REG_GPIO_L_PD, BIT(19)),
-	PINCTRL_CONF_DESC(22, REG_GPIO_L_PD, BIT(20)),
-	PINCTRL_CONF_DESC(23, REG_GPIO_L_PD, BIT(21)),
-	PINCTRL_CONF_DESC(24, REG_GPIO_L_PD, BIT(22)),
-	PINCTRL_CONF_DESC(25, REG_GPIO_L_PD, BIT(23)),
-	PINCTRL_CONF_DESC(26, REG_GPIO_L_PD, BIT(24)),
-	PINCTRL_CONF_DESC(27, REG_GPIO_L_PD, BIT(25)),
-	PINCTRL_CONF_DESC(28, REG_GPIO_L_PD, BIT(26)),
-	PINCTRL_CONF_DESC(29, REG_GPIO_L_PD, BIT(27)),
-	PINCTRL_CONF_DESC(30, REG_GPIO_L_PD, BIT(28)),
-	PINCTRL_CONF_DESC(31, REG_GPIO_L_PD, BIT(29)),
-	PINCTRL_CONF_DESC(32, REG_GPIO_L_PD, BIT(30)),
-	PINCTRL_CONF_DESC(33, REG_GPIO_L_PD, BIT(31)),
-	PINCTRL_CONF_DESC(34, REG_GPIO_H_PD, BIT(0)),
-	PINCTRL_CONF_DESC(35, REG_GPIO_H_PD, BIT(1)),
-	PINCTRL_CONF_DESC(36, REG_GPIO_H_PD, BIT(2)),
-	PINCTRL_CONF_DESC(37, REG_GPIO_H_PD, BIT(3)),
-	PINCTRL_CONF_DESC(38, REG_GPIO_H_PD, BIT(4)),
-	PINCTRL_CONF_DESC(39, REG_GPIO_H_PD, BIT(5)),
-	PINCTRL_CONF_DESC(40, REG_GPIO_H_PD, BIT(6)),
-	PINCTRL_CONF_DESC(41, REG_I2C_SDA_PD, I2C_SCL_PD_MASK),
-	PINCTRL_CONF_DESC(42, REG_I2C_SDA_PD, I2C_SDA_PD_MASK),
-	PINCTRL_CONF_DESC(43, REG_I2C_SDA_PD, AN7583_I2C1_SCL_PD_MASK),
-	PINCTRL_CONF_DESC(44, REG_I2C_SDA_PD, AN7583_I2C1_SDA_PD_MASK),
-	PINCTRL_CONF_DESC(45, REG_I2C_SDA_PD, SPI_CLK_PD_MASK),
-	PINCTRL_CONF_DESC(46, REG_I2C_SDA_PD, SPI_CS0_PD_MASK),
-	PINCTRL_CONF_DESC(47, REG_I2C_SDA_PD, SPI_MOSI_PD_MASK),
-	PINCTRL_CONF_DESC(48, REG_I2C_SDA_PD, SPI_MISO_PD_MASK),
-	PINCTRL_CONF_DESC(49, REG_I2C_SDA_PD, UART1_TXD_PD_MASK),
-	PINCTRL_CONF_DESC(50, REG_I2C_SDA_PD, UART1_RXD_PD_MASK),
-	PINCTRL_CONF_DESC(51, REG_I2C_SDA_PD, PCIE0_RESET_PD_MASK),
-	PINCTRL_CONF_DESC(52, REG_I2C_SDA_PD, PCIE1_RESET_PD_MASK),
-	PINCTRL_CONF_DESC(53, REG_I2C_SDA_PD, AN7583_MDC_0_PD_MASK),
-	PINCTRL_CONF_DESC(54, REG_I2C_SDA_PD, AN7583_MDIO_0_PD_MASK),
-};
-
-static const struct airoha_pinctrl_conf en7581_pinctrl_drive_e2_conf[] = {
-	PINCTRL_CONF_DESC(0, REG_I2C_SDA_E2, UART1_TXD_E2_MASK),
-	PINCTRL_CONF_DESC(1, REG_I2C_SDA_E2, UART1_RXD_E2_MASK),
-	PINCTRL_CONF_DESC(2, REG_I2C_SDA_E2, I2C_SDA_E2_MASK),
-	PINCTRL_CONF_DESC(3, REG_I2C_SDA_E2, I2C_SCL_E2_MASK),
-	PINCTRL_CONF_DESC(4, REG_I2C_SDA_E2, SPI_CS0_E2_MASK),
-	PINCTRL_CONF_DESC(5, REG_I2C_SDA_E2, SPI_CLK_E2_MASK),
-	PINCTRL_CONF_DESC(6, REG_I2C_SDA_E2, SPI_MOSI_E2_MASK),
-	PINCTRL_CONF_DESC(7, REG_I2C_SDA_E2, SPI_MISO_E2_MASK),
-	PINCTRL_CONF_DESC(13, REG_GPIO_L_E2, BIT(0)),
-	PINCTRL_CONF_DESC(14, REG_GPIO_L_E2, BIT(1)),
-	PINCTRL_CONF_DESC(15, REG_GPIO_L_E2, BIT(2)),
-	PINCTRL_CONF_DESC(16, REG_GPIO_L_E2, BIT(3)),
-	PINCTRL_CONF_DESC(17, REG_GPIO_L_E2, BIT(4)),
-	PINCTRL_CONF_DESC(18, REG_GPIO_L_E2, BIT(5)),
-	PINCTRL_CONF_DESC(19, REG_GPIO_L_E2, BIT(6)),
-	PINCTRL_CONF_DESC(20, REG_GPIO_L_E2, BIT(7)),
-	PINCTRL_CONF_DESC(21, REG_GPIO_L_E2, BIT(8)),
-	PINCTRL_CONF_DESC(22, REG_GPIO_L_E2, BIT(9)),
-	PINCTRL_CONF_DESC(23, REG_GPIO_L_E2, BIT(10)),
-	PINCTRL_CONF_DESC(24, REG_GPIO_L_E2, BIT(11)),
-	PINCTRL_CONF_DESC(25, REG_GPIO_L_E2, BIT(12)),
-	PINCTRL_CONF_DESC(26, REG_GPIO_L_E2, BIT(13)),
-	PINCTRL_CONF_DESC(27, REG_GPIO_L_E2, BIT(14)),
-	PINCTRL_CONF_DESC(28, REG_GPIO_L_E2, BIT(15)),
-	PINCTRL_CONF_DESC(29, REG_GPIO_L_E2, BIT(16)),
-	PINCTRL_CONF_DESC(30, REG_GPIO_L_E2, BIT(17)),
-	PINCTRL_CONF_DESC(31, REG_GPIO_L_E2, BIT(18)),
-	PINCTRL_CONF_DESC(32, REG_GPIO_L_E2, BIT(19)),
-	PINCTRL_CONF_DESC(33, REG_GPIO_L_E2, BIT(20)),
-	PINCTRL_CONF_DESC(34, REG_GPIO_L_E2, BIT(21)),
-	PINCTRL_CONF_DESC(35, REG_GPIO_L_E2, BIT(22)),
-	PINCTRL_CONF_DESC(36, REG_GPIO_L_E2, BIT(23)),
-	PINCTRL_CONF_DESC(37, REG_GPIO_L_E2, BIT(24)),
-	PINCTRL_CONF_DESC(38, REG_GPIO_L_E2, BIT(25)),
-	PINCTRL_CONF_DESC(39, REG_GPIO_L_E2, BIT(26)),
-	PINCTRL_CONF_DESC(40, REG_GPIO_L_E2, BIT(27)),
-	PINCTRL_CONF_DESC(41, REG_GPIO_L_E2, BIT(28)),
-	PINCTRL_CONF_DESC(42, REG_GPIO_L_E2, BIT(29)),
-	PINCTRL_CONF_DESC(43, REG_GPIO_L_E2, BIT(30)),
-	PINCTRL_CONF_DESC(44, REG_GPIO_L_E2, BIT(31)),
-	PINCTRL_CONF_DESC(45, REG_GPIO_H_E2, BIT(0)),
-	PINCTRL_CONF_DESC(46, REG_GPIO_H_E2, BIT(1)),
-	PINCTRL_CONF_DESC(47, REG_GPIO_H_E2, BIT(2)),
-	PINCTRL_CONF_DESC(48, REG_GPIO_H_E2, BIT(3)),
-	PINCTRL_CONF_DESC(49, REG_GPIO_H_E2, BIT(4)),
-	PINCTRL_CONF_DESC(50, REG_GPIO_H_E2, BIT(5)),
-	PINCTRL_CONF_DESC(51, REG_GPIO_H_E2, BIT(6)),
-	PINCTRL_CONF_DESC(52, REG_GPIO_H_E2, BIT(7)),
-	PINCTRL_CONF_DESC(53, REG_GPIO_H_E2, BIT(8)),
-	PINCTRL_CONF_DESC(54, REG_GPIO_H_E2, BIT(9)),
-	PINCTRL_CONF_DESC(55, REG_GPIO_H_E2, BIT(10)),
-	PINCTRL_CONF_DESC(56, REG_GPIO_H_E2, BIT(11)),
-	PINCTRL_CONF_DESC(57, REG_GPIO_H_E2, BIT(12)),
-	PINCTRL_CONF_DESC(58, REG_GPIO_H_E2, BIT(13)),
-	PINCTRL_CONF_DESC(59, REG_GPIO_H_E2, BIT(14)),
-	PINCTRL_CONF_DESC(60, REG_I2C_SDA_E2, PCIE0_RESET_E2_MASK),
-	PINCTRL_CONF_DESC(61, REG_I2C_SDA_E2, PCIE1_RESET_E2_MASK),
-	PINCTRL_CONF_DESC(62, REG_I2C_SDA_E2, PCIE2_RESET_E2_MASK),
-};
-
-static const struct airoha_pinctrl_conf an7583_pinctrl_drive_e2_conf[] = {
-	PINCTRL_CONF_DESC(2, REG_GPIO_L_E2, BIT(0)),
-	PINCTRL_CONF_DESC(3, REG_GPIO_L_E2, BIT(1)),
-	PINCTRL_CONF_DESC(4, REG_GPIO_L_E2, BIT(2)),
-	PINCTRL_CONF_DESC(5, REG_GPIO_L_E2, BIT(3)),
-	PINCTRL_CONF_DESC(6, REG_GPIO_L_E2, BIT(4)),
-	PINCTRL_CONF_DESC(7, REG_GPIO_L_E2, BIT(5)),
-	PINCTRL_CONF_DESC(8, REG_GPIO_L_E2, BIT(6)),
-	PINCTRL_CONF_DESC(9, REG_GPIO_L_E2, BIT(7)),
-	PINCTRL_CONF_DESC(10, REG_GPIO_L_E2, BIT(8)),
-	PINCTRL_CONF_DESC(11, REG_GPIO_L_E2, BIT(9)),
-	PINCTRL_CONF_DESC(12, REG_GPIO_L_E2, BIT(10)),
-	PINCTRL_CONF_DESC(13, REG_GPIO_L_E2, BIT(11)),
-	PINCTRL_CONF_DESC(14, REG_GPIO_L_E2, BIT(12)),
-	PINCTRL_CONF_DESC(15, REG_GPIO_L_E2, BIT(13)),
-	PINCTRL_CONF_DESC(16, REG_GPIO_L_E2, BIT(14)),
-	PINCTRL_CONF_DESC(17, REG_GPIO_L_E2, BIT(15)),
-	PINCTRL_CONF_DESC(18, REG_GPIO_L_E2, BIT(16)),
-	PINCTRL_CONF_DESC(19, REG_GPIO_L_E2, BIT(17)),
-	PINCTRL_CONF_DESC(20, REG_GPIO_L_E2, BIT(18)),
-	PINCTRL_CONF_DESC(21, REG_GPIO_L_E2, BIT(19)),
-	PINCTRL_CONF_DESC(22, REG_GPIO_L_E2, BIT(20)),
-	PINCTRL_CONF_DESC(23, REG_GPIO_L_E2, BIT(21)),
-	PINCTRL_CONF_DESC(24, REG_GPIO_L_E2, BIT(22)),
-	PINCTRL_CONF_DESC(25, REG_GPIO_L_E2, BIT(23)),
-	PINCTRL_CONF_DESC(26, REG_GPIO_L_E2, BIT(24)),
-	PINCTRL_CONF_DESC(27, REG_GPIO_L_E2, BIT(25)),
-	PINCTRL_CONF_DESC(28, REG_GPIO_L_E2, BIT(26)),
-	PINCTRL_CONF_DESC(29, REG_GPIO_L_E2, BIT(27)),
-	PINCTRL_CONF_DESC(30, REG_GPIO_L_E2, BIT(28)),
-	PINCTRL_CONF_DESC(31, REG_GPIO_L_E2, BIT(29)),
-	PINCTRL_CONF_DESC(32, REG_GPIO_L_E2, BIT(30)),
-	PINCTRL_CONF_DESC(33, REG_GPIO_L_E2, BIT(31)),
-	PINCTRL_CONF_DESC(34, REG_GPIO_H_E2, BIT(0)),
-	PINCTRL_CONF_DESC(35, REG_GPIO_H_E2, BIT(1)),
-	PINCTRL_CONF_DESC(36, REG_GPIO_H_E2, BIT(2)),
-	PINCTRL_CONF_DESC(37, REG_GPIO_H_E2, BIT(3)),
-	PINCTRL_CONF_DESC(38, REG_GPIO_H_E2, BIT(4)),
-	PINCTRL_CONF_DESC(39, REG_GPIO_H_E2, BIT(5)),
-	PINCTRL_CONF_DESC(40, REG_GPIO_H_E2, BIT(6)),
-	PINCTRL_CONF_DESC(41, REG_I2C_SDA_E2, I2C_SCL_E2_MASK),
-	PINCTRL_CONF_DESC(42, REG_I2C_SDA_E2, I2C_SDA_E2_MASK),
-	PINCTRL_CONF_DESC(43, REG_I2C_SDA_E2, AN7583_I2C1_SCL_E2_MASK),
-	PINCTRL_CONF_DESC(44, REG_I2C_SDA_E2, AN7583_I2C1_SDA_E2_MASK),
-	PINCTRL_CONF_DESC(45, REG_I2C_SDA_E2, SPI_CLK_E2_MASK),
-	PINCTRL_CONF_DESC(46, REG_I2C_SDA_E2, SPI_CS0_E2_MASK),
-	PINCTRL_CONF_DESC(47, REG_I2C_SDA_E2, SPI_MOSI_E2_MASK),
-	PINCTRL_CONF_DESC(48, REG_I2C_SDA_E2, SPI_MISO_E2_MASK),
-	PINCTRL_CONF_DESC(49, REG_I2C_SDA_E2, UART1_TXD_E2_MASK),
-	PINCTRL_CONF_DESC(50, REG_I2C_SDA_E2, UART1_RXD_E2_MASK),
-	PINCTRL_CONF_DESC(51, REG_I2C_SDA_E2, PCIE0_RESET_E2_MASK),
-	PINCTRL_CONF_DESC(52, REG_I2C_SDA_E2, PCIE1_RESET_E2_MASK),
-	PINCTRL_CONF_DESC(53, REG_I2C_SDA_E2, AN7583_MDC_0_E2_MASK),
-	PINCTRL_CONF_DESC(54, REG_I2C_SDA_E2, AN7583_MDIO_0_E2_MASK),
-};
-
-static const struct airoha_pinctrl_conf en7581_pinctrl_drive_e4_conf[] = {
-	PINCTRL_CONF_DESC(0, REG_I2C_SDA_E4, UART1_TXD_E4_MASK),
-	PINCTRL_CONF_DESC(1, REG_I2C_SDA_E4, UART1_RXD_E4_MASK),
-	PINCTRL_CONF_DESC(2, REG_I2C_SDA_E4, I2C_SDA_E4_MASK),
-	PINCTRL_CONF_DESC(3, REG_I2C_SDA_E4, I2C_SCL_E4_MASK),
-	PINCTRL_CONF_DESC(4, REG_I2C_SDA_E4, SPI_CS0_E4_MASK),
-	PINCTRL_CONF_DESC(5, REG_I2C_SDA_E4, SPI_CLK_E4_MASK),
-	PINCTRL_CONF_DESC(6, REG_I2C_SDA_E4, SPI_MOSI_E4_MASK),
-	PINCTRL_CONF_DESC(7, REG_I2C_SDA_E4, SPI_MISO_E4_MASK),
-	PINCTRL_CONF_DESC(13, REG_GPIO_L_E4, BIT(0)),
-	PINCTRL_CONF_DESC(14, REG_GPIO_L_E4, BIT(1)),
-	PINCTRL_CONF_DESC(15, REG_GPIO_L_E4, BIT(2)),
-	PINCTRL_CONF_DESC(16, REG_GPIO_L_E4, BIT(3)),
-	PINCTRL_CONF_DESC(17, REG_GPIO_L_E4, BIT(4)),
-	PINCTRL_CONF_DESC(18, REG_GPIO_L_E4, BIT(5)),
-	PINCTRL_CONF_DESC(19, REG_GPIO_L_E4, BIT(6)),
-	PINCTRL_CONF_DESC(20, REG_GPIO_L_E4, BIT(7)),
-	PINCTRL_CONF_DESC(21, REG_GPIO_L_E4, BIT(8)),
-	PINCTRL_CONF_DESC(22, REG_GPIO_L_E4, BIT(9)),
-	PINCTRL_CONF_DESC(23, REG_GPIO_L_E4, BIT(10)),
-	PINCTRL_CONF_DESC(24, REG_GPIO_L_E4, BIT(11)),
-	PINCTRL_CONF_DESC(25, REG_GPIO_L_E4, BIT(12)),
-	PINCTRL_CONF_DESC(26, REG_GPIO_L_E4, BIT(13)),
-	PINCTRL_CONF_DESC(27, REG_GPIO_L_E4, BIT(14)),
-	PINCTRL_CONF_DESC(28, REG_GPIO_L_E4, BIT(15)),
-	PINCTRL_CONF_DESC(29, REG_GPIO_L_E4, BIT(16)),
-	PINCTRL_CONF_DESC(30, REG_GPIO_L_E4, BIT(17)),
-	PINCTRL_CONF_DESC(31, REG_GPIO_L_E4, BIT(18)),
-	PINCTRL_CONF_DESC(32, REG_GPIO_L_E4, BIT(19)),
-	PINCTRL_CONF_DESC(33, REG_GPIO_L_E4, BIT(20)),
-	PINCTRL_CONF_DESC(34, REG_GPIO_L_E4, BIT(21)),
-	PINCTRL_CONF_DESC(35, REG_GPIO_L_E4, BIT(22)),
-	PINCTRL_CONF_DESC(36, REG_GPIO_L_E4, BIT(23)),
-	PINCTRL_CONF_DESC(37, REG_GPIO_L_E4, BIT(24)),
-	PINCTRL_CONF_DESC(38, REG_GPIO_L_E4, BIT(25)),
-	PINCTRL_CONF_DESC(39, REG_GPIO_L_E4, BIT(26)),
-	PINCTRL_CONF_DESC(40, REG_GPIO_L_E4, BIT(27)),
-	PINCTRL_CONF_DESC(41, REG_GPIO_L_E4, BIT(28)),
-	PINCTRL_CONF_DESC(42, REG_GPIO_L_E4, BIT(29)),
-	PINCTRL_CONF_DESC(43, REG_GPIO_L_E4, BIT(30)),
-	PINCTRL_CONF_DESC(44, REG_GPIO_L_E4, BIT(31)),
-	PINCTRL_CONF_DESC(45, REG_GPIO_H_E4, BIT(0)),
-	PINCTRL_CONF_DESC(46, REG_GPIO_H_E4, BIT(1)),
-	PINCTRL_CONF_DESC(47, REG_GPIO_H_E4, BIT(2)),
-	PINCTRL_CONF_DESC(48, REG_GPIO_H_E4, BIT(3)),
-	PINCTRL_CONF_DESC(49, REG_GPIO_H_E4, BIT(4)),
-	PINCTRL_CONF_DESC(50, REG_GPIO_H_E4, BIT(5)),
-	PINCTRL_CONF_DESC(51, REG_GPIO_H_E4, BIT(6)),
-	PINCTRL_CONF_DESC(52, REG_GPIO_H_E4, BIT(7)),
-	PINCTRL_CONF_DESC(53, REG_GPIO_H_E4, BIT(8)),
-	PINCTRL_CONF_DESC(54, REG_GPIO_H_E4, BIT(9)),
-	PINCTRL_CONF_DESC(55, REG_GPIO_H_E4, BIT(10)),
-	PINCTRL_CONF_DESC(56, REG_GPIO_H_E4, BIT(11)),
-	PINCTRL_CONF_DESC(57, REG_GPIO_H_E4, BIT(12)),
-	PINCTRL_CONF_DESC(58, REG_GPIO_H_E4, BIT(13)),
-	PINCTRL_CONF_DESC(59, REG_GPIO_H_E4, BIT(14)),
-	PINCTRL_CONF_DESC(60, REG_I2C_SDA_E4, PCIE0_RESET_E4_MASK),
-	PINCTRL_CONF_DESC(61, REG_I2C_SDA_E4, PCIE1_RESET_E4_MASK),
-	PINCTRL_CONF_DESC(62, REG_I2C_SDA_E4, PCIE2_RESET_E4_MASK),
-};
-
-static const struct airoha_pinctrl_conf an7583_pinctrl_drive_e4_conf[] = {
-	PINCTRL_CONF_DESC(2, REG_GPIO_L_E4, BIT(0)),
-	PINCTRL_CONF_DESC(3, REG_GPIO_L_E4, BIT(1)),
-	PINCTRL_CONF_DESC(4, REG_GPIO_L_E4, BIT(2)),
-	PINCTRL_CONF_DESC(5, REG_GPIO_L_E4, BIT(3)),
-	PINCTRL_CONF_DESC(6, REG_GPIO_L_E4, BIT(4)),
-	PINCTRL_CONF_DESC(7, REG_GPIO_L_E4, BIT(5)),
-	PINCTRL_CONF_DESC(8, REG_GPIO_L_E4, BIT(6)),
-	PINCTRL_CONF_DESC(9, REG_GPIO_L_E4, BIT(7)),
-	PINCTRL_CONF_DESC(10, REG_GPIO_L_E4, BIT(8)),
-	PINCTRL_CONF_DESC(11, REG_GPIO_L_E4, BIT(9)),
-	PINCTRL_CONF_DESC(12, REG_GPIO_L_E4, BIT(10)),
-	PINCTRL_CONF_DESC(13, REG_GPIO_L_E4, BIT(11)),
-	PINCTRL_CONF_DESC(14, REG_GPIO_L_E4, BIT(12)),
-	PINCTRL_CONF_DESC(15, REG_GPIO_L_E4, BIT(13)),
-	PINCTRL_CONF_DESC(16, REG_GPIO_L_E4, BIT(14)),
-	PINCTRL_CONF_DESC(17, REG_GPIO_L_E4, BIT(15)),
-	PINCTRL_CONF_DESC(18, REG_GPIO_L_E4, BIT(16)),
-	PINCTRL_CONF_DESC(19, REG_GPIO_L_E4, BIT(17)),
-	PINCTRL_CONF_DESC(20, REG_GPIO_L_E4, BIT(18)),
-	PINCTRL_CONF_DESC(21, REG_GPIO_L_E4, BIT(19)),
-	PINCTRL_CONF_DESC(22, REG_GPIO_L_E4, BIT(20)),
-	PINCTRL_CONF_DESC(23, REG_GPIO_L_E4, BIT(21)),
-	PINCTRL_CONF_DESC(24, REG_GPIO_L_E4, BIT(22)),
-	PINCTRL_CONF_DESC(25, REG_GPIO_L_E4, BIT(23)),
-	PINCTRL_CONF_DESC(26, REG_GPIO_L_E4, BIT(24)),
-	PINCTRL_CONF_DESC(27, REG_GPIO_L_E4, BIT(25)),
-	PINCTRL_CONF_DESC(28, REG_GPIO_L_E4, BIT(26)),
-	PINCTRL_CONF_DESC(29, REG_GPIO_L_E4, BIT(27)),
-	PINCTRL_CONF_DESC(30, REG_GPIO_L_E4, BIT(28)),
-	PINCTRL_CONF_DESC(31, REG_GPIO_L_E4, BIT(29)),
-	PINCTRL_CONF_DESC(32, REG_GPIO_L_E4, BIT(30)),
-	PINCTRL_CONF_DESC(33, REG_GPIO_L_E4, BIT(31)),
-	PINCTRL_CONF_DESC(34, REG_GPIO_H_E4, BIT(0)),
-	PINCTRL_CONF_DESC(35, REG_GPIO_H_E4, BIT(1)),
-	PINCTRL_CONF_DESC(36, REG_GPIO_H_E4, BIT(2)),
-	PINCTRL_CONF_DESC(37, REG_GPIO_H_E4, BIT(3)),
-	PINCTRL_CONF_DESC(38, REG_GPIO_H_E4, BIT(4)),
-	PINCTRL_CONF_DESC(39, REG_GPIO_H_E4, BIT(5)),
-	PINCTRL_CONF_DESC(40, REG_GPIO_H_E4, BIT(6)),
-	PINCTRL_CONF_DESC(41, REG_I2C_SDA_E4, I2C_SCL_E4_MASK),
-	PINCTRL_CONF_DESC(42, REG_I2C_SDA_E4, I2C_SDA_E4_MASK),
-	PINCTRL_CONF_DESC(43, REG_I2C_SDA_E4, AN7583_I2C1_SCL_E4_MASK),
-	PINCTRL_CONF_DESC(44, REG_I2C_SDA_E4, AN7583_I2C1_SDA_E4_MASK),
-	PINCTRL_CONF_DESC(45, REG_I2C_SDA_E4, SPI_CLK_E4_MASK),
-	PINCTRL_CONF_DESC(46, REG_I2C_SDA_E4, SPI_CS0_E4_MASK),
-	PINCTRL_CONF_DESC(47, REG_I2C_SDA_E4, SPI_MOSI_E4_MASK),
-	PINCTRL_CONF_DESC(48, REG_I2C_SDA_E4, SPI_MISO_E4_MASK),
-	PINCTRL_CONF_DESC(49, REG_I2C_SDA_E4, UART1_TXD_E4_MASK),
-	PINCTRL_CONF_DESC(50, REG_I2C_SDA_E4, UART1_RXD_E4_MASK),
-	PINCTRL_CONF_DESC(51, REG_I2C_SDA_E4, PCIE0_RESET_E4_MASK),
-	PINCTRL_CONF_DESC(52, REG_I2C_SDA_E4, PCIE1_RESET_E4_MASK),
-	PINCTRL_CONF_DESC(53, REG_I2C_SDA_E4, AN7583_MDC_0_E4_MASK),
-	PINCTRL_CONF_DESC(54, REG_I2C_SDA_E4, AN7583_MDIO_0_E4_MASK),
-};
-
-static const struct airoha_pinctrl_conf en7581_pinctrl_pcie_rst_od_conf[] = {
-	PINCTRL_CONF_DESC(60, REG_PCIE_RESET_OD, PCIE0_RESET_OD_MASK),
-	PINCTRL_CONF_DESC(61, REG_PCIE_RESET_OD, PCIE1_RESET_OD_MASK),
-	PINCTRL_CONF_DESC(62, REG_PCIE_RESET_OD, PCIE2_RESET_OD_MASK),
-};
-
-static const struct airoha_pinctrl_conf an7583_pinctrl_pcie_rst_od_conf[] = {
-	PINCTRL_CONF_DESC(51, REG_PCIE_RESET_OD, PCIE0_RESET_OD_MASK),
-	PINCTRL_CONF_DESC(52, REG_PCIE_RESET_OD, PCIE1_RESET_OD_MASK),
-};
-
 static int airoha_convert_pin_to_reg_offset(struct pinctrl_dev *pctrl_dev,
 					    struct pinctrl_gpio_range *range,
 					    int pin)
@@ -2606,6 +318,7 @@ static int airoha_pinctrl_add_gpiochip(struct airoha_pinctrl *pinctrl,
 					struct platform_device *pdev)
 {
 	struct airoha_pinctrl_gpiochip *chip = &pinctrl->gpiochip;
+	struct irq_chip *irq_chip = &pinctrl->gpio_irq_chip;
 	struct gpio_chip *gc = &chip->chip;
 	struct gpio_irq_chip *girq = &gc->irq;
 	struct device *dev = &pdev->dev;
@@ -2630,9 +343,11 @@ static int airoha_pinctrl_add_gpiochip(struct airoha_pinctrl *pinctrl,
 	gc->base = -1;
 	gc->ngpio = AIROHA_NUM_PINS;
 
+	memcpy(irq_chip, &airoha_gpio_irq_chip, sizeof(struct irq_chip));
+
 	girq->default_type = IRQ_TYPE_NONE;
 	girq->handler = handle_bad_irq;
-	gpio_irq_chip_set_chip(girq, &airoha_gpio_irq_chip);
+	gpio_irq_chip_set_chip(girq, irq_chip);
 
 	irq = platform_get_irq(pdev, 0);
 	if (irq < 0)
@@ -3011,7 +726,7 @@ static const struct pinctrl_ops airoha_pctlops = {
 	.dt_free_map = pinconf_generic_dt_free_map,
 };
 
-static int airoha_pinctrl_probe(struct platform_device *pdev)
+int airoha_pinctrl_probe(struct platform_device *pdev)
 {
 	const struct airoha_pinctrl_match_data *data;
 	struct device *dev = &pdev->dev;
@@ -3020,6 +735,8 @@ static int airoha_pinctrl_probe(struct platform_device *pdev)
 	int err, i;
 
 	data = device_get_match_data(dev);
+	if (!data)
+		return -EINVAL;
 
 	pinctrl = devm_kzalloc(dev, sizeof(*pinctrl), GFP_KERNEL);
 	if (!pinctrl)
@@ -3036,8 +753,8 @@ static int airoha_pinctrl_probe(struct platform_device *pdev)
 	pinctrl->chip_scu = map;
 
 	/* Init pinctrl desc struct */
-	pinctrl->desc.name = KBUILD_MODNAME;
-	pinctrl->desc.owner = THIS_MODULE;
+	pinctrl->desc.name = data->pinctrl_name;
+	pinctrl->desc.owner = data->pinctrl_owner;
 	pinctrl->desc.pctlops = &airoha_pctlops;
 	pinctrl->desc.pmxops = &airoha_pmxops;
 	pinctrl->desc.confops = &airoha_confops;
@@ -3089,87 +806,10 @@ static int airoha_pinctrl_probe(struct platform_device *pdev)
 	/* build gpio-chip */
 	return airoha_pinctrl_add_gpiochip(pinctrl, pdev);
 }
-
-static const struct airoha_pinctrl_match_data en7581_pinctrl_match_data = {
-	.pins = en7581_pinctrl_pins,
-	.num_pins = ARRAY_SIZE(en7581_pinctrl_pins),
-	.grps = en7581_pinctrl_groups,
-	.num_grps = ARRAY_SIZE(en7581_pinctrl_groups),
-	.funcs = en7581_pinctrl_funcs,
-	.num_funcs = ARRAY_SIZE(en7581_pinctrl_funcs),
-	.confs_info = {
-		[AIROHA_PINCTRL_CONFS_PULLUP] = {
-			.confs = en7581_pinctrl_pullup_conf,
-			.num_confs = ARRAY_SIZE(en7581_pinctrl_pullup_conf),
-		},
-		[AIROHA_PINCTRL_CONFS_PULLDOWN] = {
-			.confs = en7581_pinctrl_pulldown_conf,
-			.num_confs = ARRAY_SIZE(en7581_pinctrl_pulldown_conf),
-		},
-		[AIROHA_PINCTRL_CONFS_DRIVE_E2] = {
-			.confs = en7581_pinctrl_drive_e2_conf,
-			.num_confs = ARRAY_SIZE(en7581_pinctrl_drive_e2_conf),
-		},
-		[AIROHA_PINCTRL_CONFS_DRIVE_E4] = {
-			.confs = en7581_pinctrl_drive_e4_conf,
-			.num_confs = ARRAY_SIZE(en7581_pinctrl_drive_e4_conf),
-		},
-		[AIROHA_PINCTRL_CONFS_PCIE_RST_OD] = {
-			.confs = en7581_pinctrl_pcie_rst_od_conf,
-			.num_confs = ARRAY_SIZE(en7581_pinctrl_pcie_rst_od_conf),
-		},
-	},
-};
-
-static const struct airoha_pinctrl_match_data an7583_pinctrl_match_data = {
-	.pins = an7583_pinctrl_pins,
-	.num_pins = ARRAY_SIZE(an7583_pinctrl_pins),
-	.grps = an7583_pinctrl_groups,
-	.num_grps = ARRAY_SIZE(an7583_pinctrl_groups),
-	.funcs = an7583_pinctrl_funcs,
-	.num_funcs = ARRAY_SIZE(an7583_pinctrl_funcs),
-	.confs_info = {
-		[AIROHA_PINCTRL_CONFS_PULLUP] = {
-			.confs = an7583_pinctrl_pullup_conf,
-			.num_confs = ARRAY_SIZE(an7583_pinctrl_pullup_conf),
-		},
-		[AIROHA_PINCTRL_CONFS_PULLDOWN] = {
-			.confs = an7583_pinctrl_pulldown_conf,
-			.num_confs = ARRAY_SIZE(an7583_pinctrl_pulldown_conf),
-		},
-		[AIROHA_PINCTRL_CONFS_DRIVE_E2] = {
-			.confs = an7583_pinctrl_drive_e2_conf,
-			.num_confs = ARRAY_SIZE(an7583_pinctrl_drive_e2_conf),
-		},
-		[AIROHA_PINCTRL_CONFS_DRIVE_E4] = {
-			.confs = an7583_pinctrl_drive_e4_conf,
-			.num_confs = ARRAY_SIZE(an7583_pinctrl_drive_e4_conf),
-		},
-		[AIROHA_PINCTRL_CONFS_PCIE_RST_OD] = {
-			.confs = an7583_pinctrl_pcie_rst_od_conf,
-			.num_confs = ARRAY_SIZE(an7583_pinctrl_pcie_rst_od_conf),
-		},
-	},
-};
-
-static const struct of_device_id airoha_pinctrl_of_match[] = {
-	{ .compatible = "airoha,en7581-pinctrl", .data = &en7581_pinctrl_match_data },
-	{ .compatible = "airoha,an7583-pinctrl", .data = &an7583_pinctrl_match_data },
-	{ /* sentinel */ }
-};
-MODULE_DEVICE_TABLE(of, airoha_pinctrl_of_match);
-
-static struct platform_driver airoha_pinctrl_driver = {
-	.probe = airoha_pinctrl_probe,
-	.driver = {
-		.name = "pinctrl-airoha",
-		.of_match_table = airoha_pinctrl_of_match,
-	},
-};
-module_platform_driver(airoha_pinctrl_driver);
+EXPORT_SYMBOL_GPL(airoha_pinctrl_probe);
 
 MODULE_LICENSE("GPL");
 MODULE_AUTHOR("Lorenzo Bianconi <lorenzo@kernel.org>");
 MODULE_AUTHOR("Benjamin Larsson <benjamin.larsson@genexis.eu>");
 MODULE_AUTHOR("Markus Gothe <markus.gothe@genexis.eu>");
-MODULE_DESCRIPTION("Pinctrl driver for Airoha SoC");
+MODULE_DESCRIPTION("Pinctrl common driver for Airoha SoC");
diff --git a/drivers/pinctrl/airoha/pinctrl-an7581.c b/drivers/pinctrl/airoha/pinctrl-an7581.c
new file mode 100644
index 0000000000000..522b35bbaa121
--- /dev/null
+++ b/drivers/pinctrl/airoha/pinctrl-an7581.c
@@ -0,0 +1,1486 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Author: Lorenzo Bianconi <lorenzo@kernel.org>
+ * Author: Benjamin Larsson <benjamin.larsson@genexis.eu>
+ * Author: Markus Gothe <markus.gothe@genexis.eu>
+ */
+
+#include "airoha-common.h"
+
+/* MUX */
+#define REG_GPIO_2ND_I2C_MODE			0x0214
+#define GPIO_MDC_IO_MASTER_MODE_MASK		BIT(14)
+#define GPIO_I2C_MASTER_MODE_MODE		BIT(13)
+#define GPIO_I2S_MODE_MASK			BIT(12)
+#define GPIO_I2C_SLAVE_MODE_MODE		BIT(11)
+#define GPIO_LAN3_LED1_MODE_MASK		BIT(10)
+#define GPIO_LAN3_LED0_MODE_MASK		BIT(9)
+#define GPIO_LAN2_LED1_MODE_MASK		BIT(8)
+#define GPIO_LAN2_LED0_MODE_MASK		BIT(7)
+#define GPIO_LAN1_LED1_MODE_MASK		BIT(6)
+#define GPIO_LAN1_LED0_MODE_MASK		BIT(5)
+#define GPIO_LAN0_LED1_MODE_MASK		BIT(4)
+#define GPIO_LAN0_LED0_MODE_MASK		BIT(3)
+#define PON_TOD_1PPS_MODE_MASK			BIT(2)
+#define GSW_TOD_1PPS_MODE_MASK			BIT(1)
+#define GPIO_2ND_I2C_MODE_MASK			BIT(0)
+
+#define REG_GPIO_SPI_CS1_MODE			0x0218
+#define GPIO_PCM_SPI_CS4_MODE_MASK		BIT(21)
+#define GPIO_PCM_SPI_CS3_MODE_MASK		BIT(20)
+#define GPIO_PCM_SPI_CS2_MODE_P156_MASK		BIT(19)
+#define GPIO_PCM_SPI_CS2_MODE_P128_MASK		BIT(18)
+#define GPIO_PCM_SPI_CS1_MODE_MASK		BIT(17)
+#define GPIO_PCM_SPI_MODE_MASK			BIT(16)
+#define GPIO_PCM2_MODE_MASK			BIT(13)
+#define GPIO_PCM1_MODE_MASK			BIT(12)
+#define GPIO_PCM_INT_MODE_MASK			BIT(9)
+#define GPIO_PCM_RESET_MODE_MASK		BIT(8)
+#define GPIO_SPI_QUAD_MODE_MASK			BIT(4)
+#define GPIO_SPI_CS4_MODE_MASK			BIT(3)
+#define GPIO_SPI_CS3_MODE_MASK			BIT(2)
+#define GPIO_SPI_CS2_MODE_MASK			BIT(1)
+#define GPIO_SPI_CS1_MODE_MASK			BIT(0)
+
+#define REG_GPIO_PON_MODE			0x021c
+#define GPIO_PARALLEL_NAND_MODE_MASK		BIT(14)
+#define GPIO_SGMII_MDIO_MODE_MASK		BIT(13)
+#define GPIO_PCIE_RESET2_MASK			BIT(12)
+#define SIPO_RCLK_MODE_MASK			BIT(11)
+#define GPIO_PCIE_RESET1_MASK			BIT(10)
+#define GPIO_PCIE_RESET0_MASK			BIT(9)
+#define GPIO_UART5_MODE_MASK			BIT(8)
+#define GPIO_UART4_MODE_MASK			BIT(7)
+#define GPIO_HSUART_CTS_RTS_MODE_MASK		BIT(6)
+#define GPIO_HSUART_MODE_MASK			BIT(5)
+#define GPIO_UART2_CTS_RTS_MODE_MASK		BIT(4)
+#define GPIO_UART2_MODE_MASK			BIT(3)
+#define GPIO_SIPO_MODE_MASK			BIT(2)
+#define GPIO_EMMC_MODE_MASK			BIT(1)
+#define GPIO_PON_MODE_MASK			BIT(0)
+
+#define REG_NPU_UART_EN				0x0224
+#define JTAG_UDI_EN_MASK			BIT(4)
+#define JTAG_DFD_EN_MASK			BIT(3)
+
+#define REG_FORCE_GPIO_EN			0x0228
+#define FORCE_GPIO_EN(n)			BIT(n)
+
+/* LED MAP */
+#define REG_LAN_LED0_MAPPING			0x027c
+#define REG_LAN_LED1_MAPPING			0x0280
+
+#define LAN4_LED_MAPPING_MASK			GENMASK(18, 16)
+#define LAN4_PHY_LED_MAP(_n)			FIELD_PREP_CONST(LAN4_LED_MAPPING_MASK, (_n))
+
+#define LAN3_LED_MAPPING_MASK			GENMASK(14, 12)
+#define LAN3_PHY_LED_MAP(_n)			FIELD_PREP_CONST(LAN3_LED_MAPPING_MASK, (_n))
+
+#define LAN2_LED_MAPPING_MASK			GENMASK(10, 8)
+#define LAN2_PHY_LED_MAP(_n)			FIELD_PREP_CONST(LAN2_LED_MAPPING_MASK, (_n))
+
+#define LAN1_LED_MAPPING_MASK			GENMASK(6, 4)
+#define LAN1_PHY_LED_MAP(_n)			FIELD_PREP_CONST(LAN1_LED_MAPPING_MASK, (_n))
+
+#define LAN0_LED_MAPPING_MASK			GENMASK(2, 0)
+#define LAN0_PHY_LED_MAP(_n)			FIELD_PREP_CONST(LAN0_LED_MAPPING_MASK, (_n))
+
+/* CONF */
+#define REG_I2C_SDA_E2				0x001c
+#define SPI_MISO_E2_MASK			BIT(14)
+#define SPI_MOSI_E2_MASK			BIT(13)
+#define SPI_CLK_E2_MASK				BIT(12)
+#define SPI_CS0_E2_MASK				BIT(11)
+#define PCIE2_RESET_E2_MASK			BIT(10)
+#define PCIE1_RESET_E2_MASK			BIT(9)
+#define PCIE0_RESET_E2_MASK			BIT(8)
+#define UART1_RXD_E2_MASK			BIT(3)
+#define UART1_TXD_E2_MASK			BIT(2)
+#define I2C_SCL_E2_MASK				BIT(1)
+#define I2C_SDA_E2_MASK				BIT(0)
+
+#define REG_I2C_SDA_E4				0x0020
+#define SPI_MISO_E4_MASK			BIT(14)
+#define SPI_MOSI_E4_MASK			BIT(13)
+#define SPI_CLK_E4_MASK				BIT(12)
+#define SPI_CS0_E4_MASK				BIT(11)
+#define PCIE2_RESET_E4_MASK			BIT(10)
+#define PCIE1_RESET_E4_MASK			BIT(9)
+#define PCIE0_RESET_E4_MASK			BIT(8)
+#define UART1_RXD_E4_MASK			BIT(3)
+#define UART1_TXD_E4_MASK			BIT(2)
+#define I2C_SCL_E4_MASK				BIT(1)
+#define I2C_SDA_E4_MASK				BIT(0)
+
+#define REG_GPIO_L_E2				0x0024
+#define REG_GPIO_L_E4				0x0028
+#define REG_GPIO_H_E2				0x002c
+#define REG_GPIO_H_E4				0x0030
+
+#define REG_I2C_SDA_PU				0x0044
+#define SPI_MISO_PU_MASK			BIT(14)
+#define SPI_MOSI_PU_MASK			BIT(13)
+#define SPI_CLK_PU_MASK				BIT(12)
+#define SPI_CS0_PU_MASK				BIT(11)
+#define PCIE2_RESET_PU_MASK			BIT(10)
+#define PCIE1_RESET_PU_MASK			BIT(9)
+#define PCIE0_RESET_PU_MASK			BIT(8)
+#define UART1_RXD_PU_MASK			BIT(3)
+#define UART1_TXD_PU_MASK			BIT(2)
+#define I2C_SCL_PU_MASK				BIT(1)
+#define I2C_SDA_PU_MASK				BIT(0)
+
+#define REG_I2C_SDA_PD				0x0048
+#define SPI_MISO_PD_MASK			BIT(14)
+#define SPI_MOSI_PD_MASK			BIT(13)
+#define SPI_CLK_PD_MASK				BIT(12)
+#define SPI_CS0_PD_MASK				BIT(11)
+#define PCIE2_RESET_PD_MASK			BIT(10)
+#define PCIE1_RESET_PD_MASK			BIT(9)
+#define PCIE0_RESET_PD_MASK			BIT(8)
+#define UART1_RXD_PD_MASK			BIT(3)
+#define UART1_TXD_PD_MASK			BIT(2)
+#define I2C_SCL_PD_MASK				BIT(1)
+#define I2C_SDA_PD_MASK				BIT(0)
+
+#define REG_GPIO_L_PU				0x004c
+#define REG_GPIO_L_PD				0x0050
+#define REG_GPIO_H_PU				0x0054
+#define REG_GPIO_H_PD				0x0058
+
+#define REG_PCIE_RESET_OD			0x018c
+#define PCIE2_RESET_OD_MASK			BIT(2)
+#define PCIE1_RESET_OD_MASK			BIT(1)
+#define PCIE0_RESET_OD_MASK			BIT(0)
+
+/* PWM MODE CONF */
+#define REG_GPIO_FLASH_MODE_CFG			0x0034
+#define GPIO15_FLASH_MODE_CFG			BIT(15)
+#define GPIO14_FLASH_MODE_CFG			BIT(14)
+#define GPIO13_FLASH_MODE_CFG			BIT(13)
+#define GPIO12_FLASH_MODE_CFG			BIT(12)
+#define GPIO11_FLASH_MODE_CFG			BIT(11)
+#define GPIO10_FLASH_MODE_CFG			BIT(10)
+#define GPIO9_FLASH_MODE_CFG			BIT(9)
+#define GPIO8_FLASH_MODE_CFG			BIT(8)
+#define GPIO7_FLASH_MODE_CFG			BIT(7)
+#define GPIO6_FLASH_MODE_CFG			BIT(6)
+#define GPIO5_FLASH_MODE_CFG			BIT(5)
+#define GPIO4_FLASH_MODE_CFG			BIT(4)
+#define GPIO3_FLASH_MODE_CFG			BIT(3)
+#define GPIO2_FLASH_MODE_CFG			BIT(2)
+#define GPIO1_FLASH_MODE_CFG			BIT(1)
+#define GPIO0_FLASH_MODE_CFG			BIT(0)
+
+/* PWM MODE CONF EXT */
+#define REG_GPIO_FLASH_MODE_CFG_EXT		0x0068
+#define GPIO51_FLASH_MODE_CFG			BIT(31)
+#define GPIO50_FLASH_MODE_CFG			BIT(30)
+#define GPIO49_FLASH_MODE_CFG			BIT(29)
+#define GPIO48_FLASH_MODE_CFG			BIT(28)
+#define GPIO47_FLASH_MODE_CFG			BIT(27)
+#define GPIO46_FLASH_MODE_CFG			BIT(26)
+#define GPIO45_FLASH_MODE_CFG			BIT(25)
+#define GPIO44_FLASH_MODE_CFG			BIT(24)
+#define GPIO43_FLASH_MODE_CFG			BIT(23)
+#define GPIO42_FLASH_MODE_CFG			BIT(22)
+#define GPIO41_FLASH_MODE_CFG			BIT(21)
+#define GPIO40_FLASH_MODE_CFG			BIT(20)
+#define GPIO39_FLASH_MODE_CFG			BIT(19)
+#define GPIO38_FLASH_MODE_CFG			BIT(18)
+#define GPIO37_FLASH_MODE_CFG			BIT(17)
+#define GPIO36_FLASH_MODE_CFG			BIT(16)
+#define GPIO31_FLASH_MODE_CFG			BIT(15)
+#define GPIO30_FLASH_MODE_CFG			BIT(14)
+#define GPIO29_FLASH_MODE_CFG			BIT(13)
+#define GPIO28_FLASH_MODE_CFG			BIT(12)
+#define GPIO27_FLASH_MODE_CFG			BIT(11)
+#define GPIO26_FLASH_MODE_CFG			BIT(10)
+#define GPIO25_FLASH_MODE_CFG			BIT(9)
+#define GPIO24_FLASH_MODE_CFG			BIT(8)
+#define GPIO23_FLASH_MODE_CFG			BIT(7)
+#define GPIO22_FLASH_MODE_CFG			BIT(6)
+#define GPIO21_FLASH_MODE_CFG			BIT(5)
+#define GPIO20_FLASH_MODE_CFG			BIT(4)
+#define GPIO19_FLASH_MODE_CFG			BIT(3)
+#define GPIO18_FLASH_MODE_CFG			BIT(2)
+#define GPIO17_FLASH_MODE_CFG			BIT(1)
+#define GPIO16_FLASH_MODE_CFG			BIT(0)
+
+#define AIROHA_PINCTRL_GPIO(gpio, mux_val)			\
+	{							\
+		.name = (gpio),					\
+		.regmap[0] = {					\
+			AIROHA_FUNC_MUX,			\
+			REG_GPIO_PON_MODE,			\
+			(mux_val),				\
+			(mux_val)				\
+		},						\
+		.regmap_size = 1,				\
+	}
+
+#define AIROHA_PINCTRL_GPIO_EXT(gpio, mux_val, smux_val)	\
+	{							\
+		.name = (gpio),					\
+		.regmap[0] = {					\
+			AIROHA_FUNC_PWM_EXT_MUX,		\
+			REG_GPIO_FLASH_MODE_CFG_EXT,		\
+			(mux_val),				\
+			0					\
+		},						\
+		.regmap[1] = {					\
+			AIROHA_FUNC_MUX,			\
+			REG_GPIO_PON_MODE,			\
+			(smux_val),				\
+			(smux_val)				\
+		},						\
+		.regmap_size = 2,				\
+	}
+
+/* PWM */
+#define AIROHA_PINCTRL_PWM(gpio, mux_val)			\
+	{							\
+		.name = (gpio),					\
+		.regmap[0] = {					\
+			AIROHA_FUNC_PWM_MUX,			\
+			REG_GPIO_FLASH_MODE_CFG,		\
+			(mux_val),				\
+			(mux_val)				\
+		},						\
+		.regmap_size = 1,				\
+	}
+
+#define AIROHA_PINCTRL_PWM_EXT(gpio, mux_val)			\
+	{							\
+		.name = (gpio),					\
+		.regmap[0] = {					\
+			AIROHA_FUNC_PWM_EXT_MUX,		\
+			REG_GPIO_FLASH_MODE_CFG_EXT,		\
+			(mux_val),				\
+			(mux_val)				\
+		},						\
+		.regmap_size = 1,				\
+	}
+
+#define AIROHA_PINCTRL_PWM_EXT_SEC(gpio, mux_val, smux_val)	\
+	{							\
+		.name = (gpio),					\
+		.regmap[0] = {					\
+			AIROHA_FUNC_PWM_EXT_MUX,		\
+			REG_GPIO_FLASH_MODE_CFG_EXT,		\
+			(mux_val),				\
+			(mux_val)				\
+		},						\
+		.regmap[1] = {					\
+			AIROHA_FUNC_MUX,			\
+			REG_GPIO_PON_MODE,			\
+			(smux_val),				\
+			(smux_val)				\
+		},						\
+		.regmap_size = 2,				\
+	}
+
+#define AIROHA_PINCTRL_PHY_LED0(gpio, mux_val, map_mask, map_val)	\
+	{								\
+		.name = (gpio),						\
+		.regmap[0] = {						\
+			AIROHA_FUNC_MUX,				\
+			REG_GPIO_2ND_I2C_MODE,				\
+			(mux_val),					\
+			(mux_val),					\
+		},							\
+		.regmap[1] = {						\
+			AIROHA_FUNC_MUX,				\
+			REG_LAN_LED0_MAPPING,				\
+			(map_mask),					\
+			(map_val),					\
+		},							\
+		.regmap_size = 2,					\
+	}
+
+#define AIROHA_PINCTRL_PHY_LED1(gpio, mux_val, map_mask, map_val)	\
+	{								\
+		.name = (gpio),						\
+		.regmap[0] = {						\
+			AIROHA_FUNC_MUX,				\
+			REG_GPIO_2ND_I2C_MODE,				\
+			(mux_val),					\
+			(mux_val),					\
+		},							\
+		.regmap[1] = {						\
+			AIROHA_FUNC_MUX,				\
+			REG_LAN_LED1_MAPPING,				\
+			(map_mask),					\
+			(map_val),					\
+		},							\
+		.regmap_size = 2,					\
+	}
+
+static struct pinctrl_pin_desc en7581_pinctrl_pins[] = {
+	PINCTRL_PIN(0, "uart1_txd"),
+	PINCTRL_PIN(1, "uart1_rxd"),
+	PINCTRL_PIN(2, "i2c_scl"),
+	PINCTRL_PIN(3, "i2c_sda"),
+	PINCTRL_PIN(4, "spi_cs0"),
+	PINCTRL_PIN(5, "spi_clk"),
+	PINCTRL_PIN(6, "spi_mosi"),
+	PINCTRL_PIN(7, "spi_miso"),
+	PINCTRL_PIN(13, "gpio0"),
+	PINCTRL_PIN(14, "gpio1"),
+	PINCTRL_PIN(15, "gpio2"),
+	PINCTRL_PIN(16, "gpio3"),
+	PINCTRL_PIN(17, "gpio4"),
+	PINCTRL_PIN(18, "gpio5"),
+	PINCTRL_PIN(19, "gpio6"),
+	PINCTRL_PIN(20, "gpio7"),
+	PINCTRL_PIN(21, "gpio8"),
+	PINCTRL_PIN(22, "gpio9"),
+	PINCTRL_PIN(23, "gpio10"),
+	PINCTRL_PIN(24, "gpio11"),
+	PINCTRL_PIN(25, "gpio12"),
+	PINCTRL_PIN(26, "gpio13"),
+	PINCTRL_PIN(27, "gpio14"),
+	PINCTRL_PIN(28, "gpio15"),
+	PINCTRL_PIN(29, "gpio16"),
+	PINCTRL_PIN(30, "gpio17"),
+	PINCTRL_PIN(31, "gpio18"),
+	PINCTRL_PIN(32, "gpio19"),
+	PINCTRL_PIN(33, "gpio20"),
+	PINCTRL_PIN(34, "gpio21"),
+	PINCTRL_PIN(35, "gpio22"),
+	PINCTRL_PIN(36, "gpio23"),
+	PINCTRL_PIN(37, "gpio24"),
+	PINCTRL_PIN(38, "gpio25"),
+	PINCTRL_PIN(39, "gpio26"),
+	PINCTRL_PIN(40, "gpio27"),
+	PINCTRL_PIN(41, "gpio28"),
+	PINCTRL_PIN(42, "gpio29"),
+	PINCTRL_PIN(43, "gpio30"),
+	PINCTRL_PIN(44, "gpio31"),
+	PINCTRL_PIN(45, "gpio32"),
+	PINCTRL_PIN(46, "gpio33"),
+	PINCTRL_PIN(47, "gpio34"),
+	PINCTRL_PIN(48, "gpio35"),
+	PINCTRL_PIN(49, "gpio36"),
+	PINCTRL_PIN(50, "gpio37"),
+	PINCTRL_PIN(51, "gpio38"),
+	PINCTRL_PIN(52, "gpio39"),
+	PINCTRL_PIN(53, "gpio40"),
+	PINCTRL_PIN(54, "gpio41"),
+	PINCTRL_PIN(55, "gpio42"),
+	PINCTRL_PIN(56, "gpio43"),
+	PINCTRL_PIN(57, "gpio44"),
+	PINCTRL_PIN(58, "gpio45"),
+	PINCTRL_PIN(59, "gpio46"),
+	PINCTRL_PIN(60, "pcie_reset0"),
+	PINCTRL_PIN(61, "pcie_reset1"),
+	PINCTRL_PIN(62, "pcie_reset2"),
+};
+
+static const int en7581_pon_pins[] = { 49, 50, 51, 52, 53, 54 };
+static const int en7581_pon_tod_1pps_pins[] = { 46 };
+static const int en7581_gsw_tod_1pps_pins[] = { 46 };
+static const int en7581_sipo_pins[] = { 16, 17 };
+static const int en7581_sipo_rclk_pins[] = { 16, 17, 43 };
+static const int en7581_mdio_pins[] = { 14, 15 };
+static const int en7581_uart2_pins[] = { 48, 55 };
+static const int en7581_uart2_cts_rts_pins[] = { 46, 47 };
+static const int en7581_hsuart_pins[] = { 28, 29 };
+static const int en7581_hsuart_cts_rts_pins[] = { 26, 27 };
+static const int en7581_uart4_pins[] = { 38, 39 };
+static const int en7581_uart5_pins[] = { 18, 19 };
+static const int en7581_i2c0_pins[] = { 2, 3 };
+static const int en7581_i2c1_pins[] = { 14, 15 };
+static const int en7581_jtag_udi_pins[] = { 16, 17, 18, 19, 20 };
+static const int en7581_jtag_dfd_pins[] = { 16, 17, 18, 19, 20 };
+static const int en7581_i2s_pins[] = { 26, 27, 28, 29 };
+static const int en7581_pcm1_pins[] = { 22, 23, 24, 25 };
+static const int en7581_pcm2_pins[] = { 18, 19, 20, 21 };
+static const int en7581_spi_quad_pins[] = { 32, 33 };
+static const int en7581_spi_pins[] = { 4, 5, 6, 7 };
+static const int en7581_spi_cs1_pins[] = { 34 };
+static const int en7581_pcm_spi_pins[] = { 18, 19, 20, 21, 22, 23, 24, 25 };
+static const int en7581_pcm_spi_int_pins[] = { 14 };
+static const int en7581_pcm_spi_rst_pins[] = { 15 };
+static const int en7581_pcm_spi_cs1_pins[] = { 43 };
+static const int en7581_pcm_spi_cs2_pins[] = { 40 };
+static const int en7581_pcm_spi_cs2_p128_pins[] = { 40 };
+static const int en7581_pcm_spi_cs2_p156_pins[] = { 40 };
+static const int en7581_pcm_spi_cs3_pins[] = { 41 };
+static const int en7581_pcm_spi_cs4_pins[] = { 42 };
+static const int en7581_emmc_pins[] = {
+	4, 5, 6, 30, 31, 32, 33, 34, 35, 36, 37
+};
+static const int en7581_pnand_pins[] = {
+	4, 5, 6, 7, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42
+};
+static const int en7581_gpio0_pins[] = { 13 };
+static const int en7581_gpio1_pins[] = { 14 };
+static const int en7581_gpio2_pins[] = { 15 };
+static const int en7581_gpio3_pins[] = { 16 };
+static const int en7581_gpio4_pins[] = { 17 };
+static const int en7581_gpio5_pins[] = { 18 };
+static const int en7581_gpio6_pins[] = { 19 };
+static const int en7581_gpio7_pins[] = { 20 };
+static const int en7581_gpio8_pins[] = { 21 };
+static const int en7581_gpio9_pins[] = { 22 };
+static const int en7581_gpio10_pins[] = { 23 };
+static const int en7581_gpio11_pins[] = { 24 };
+static const int en7581_gpio12_pins[] = { 25 };
+static const int en7581_gpio13_pins[] = { 26 };
+static const int en7581_gpio14_pins[] = { 27 };
+static const int en7581_gpio15_pins[] = { 28 };
+static const int en7581_gpio16_pins[] = { 29 };
+static const int en7581_gpio17_pins[] = { 30 };
+static const int en7581_gpio18_pins[] = { 31 };
+static const int en7581_gpio19_pins[] = { 32 };
+static const int en7581_gpio20_pins[] = { 33 };
+static const int en7581_gpio21_pins[] = { 34 };
+static const int en7581_gpio22_pins[] = { 35 };
+static const int en7581_gpio23_pins[] = { 36 };
+static const int en7581_gpio24_pins[] = { 37 };
+static const int en7581_gpio25_pins[] = { 38 };
+static const int en7581_gpio26_pins[] = { 39 };
+static const int en7581_gpio27_pins[] = { 40 };
+static const int en7581_gpio28_pins[] = { 41 };
+static const int en7581_gpio29_pins[] = { 42 };
+static const int en7581_gpio30_pins[] = { 43 };
+static const int en7581_gpio31_pins[] = { 44 };
+static const int en7581_gpio32_pins[] = { 45 };
+static const int en7581_gpio33_pins[] = { 46 };
+static const int en7581_gpio34_pins[] = { 47 };
+static const int en7581_gpio35_pins[] = { 48 };
+static const int en7581_gpio36_pins[] = { 49 };
+static const int en7581_gpio37_pins[] = { 50 };
+static const int en7581_gpio38_pins[] = { 51 };
+static const int en7581_gpio39_pins[] = { 52 };
+static const int en7581_gpio40_pins[] = { 53 };
+static const int en7581_gpio41_pins[] = { 54 };
+static const int en7581_gpio42_pins[] = { 55 };
+static const int en7581_gpio43_pins[] = { 56 };
+static const int en7581_gpio44_pins[] = { 57 };
+static const int en7581_gpio45_pins[] = { 58 };
+static const int en7581_gpio46_pins[] = { 59 };
+static const int en7581_gpio47_pins[] = { 60 };
+static const int en7581_gpio48_pins[] = { 61 };
+static const int en7581_gpio49_pins[] = { 62 };
+static const int en7581_pcie_reset0_pins[] = { 60 };
+static const int en7581_pcie_reset1_pins[] = { 61 };
+static const int en7581_pcie_reset2_pins[] = { 62 };
+
+static const struct pingroup en7581_pinctrl_groups[] = {
+	PINCTRL_PIN_GROUP("pon", en7581_pon),
+	PINCTRL_PIN_GROUP("pon_tod_1pps", en7581_pon_tod_1pps),
+	PINCTRL_PIN_GROUP("gsw_tod_1pps", en7581_gsw_tod_1pps),
+	PINCTRL_PIN_GROUP("sipo", en7581_sipo),
+	PINCTRL_PIN_GROUP("sipo_rclk", en7581_sipo_rclk),
+	PINCTRL_PIN_GROUP("mdio", en7581_mdio),
+	PINCTRL_PIN_GROUP("uart2", en7581_uart2),
+	PINCTRL_PIN_GROUP("uart2_cts_rts", en7581_uart2_cts_rts),
+	PINCTRL_PIN_GROUP("hsuart", en7581_hsuart),
+	PINCTRL_PIN_GROUP("hsuart_cts_rts", en7581_hsuart_cts_rts),
+	PINCTRL_PIN_GROUP("uart4", en7581_uart4),
+	PINCTRL_PIN_GROUP("uart5", en7581_uart5),
+	PINCTRL_PIN_GROUP("i2c0", en7581_i2c0),
+	PINCTRL_PIN_GROUP("i2c1", en7581_i2c1),
+	PINCTRL_PIN_GROUP("jtag_udi", en7581_jtag_udi),
+	PINCTRL_PIN_GROUP("jtag_dfd", en7581_jtag_dfd),
+	PINCTRL_PIN_GROUP("i2s", en7581_i2s),
+	PINCTRL_PIN_GROUP("pcm1", en7581_pcm1),
+	PINCTRL_PIN_GROUP("pcm2", en7581_pcm2),
+	PINCTRL_PIN_GROUP("spi", en7581_spi),
+	PINCTRL_PIN_GROUP("spi_quad", en7581_spi_quad),
+	PINCTRL_PIN_GROUP("spi_cs1", en7581_spi_cs1),
+	PINCTRL_PIN_GROUP("pcm_spi", en7581_pcm_spi),
+	PINCTRL_PIN_GROUP("pcm_spi_int", en7581_pcm_spi_int),
+	PINCTRL_PIN_GROUP("pcm_spi_rst", en7581_pcm_spi_rst),
+	PINCTRL_PIN_GROUP("pcm_spi_cs1", en7581_pcm_spi_cs1),
+	PINCTRL_PIN_GROUP("pcm_spi_cs2_p128", en7581_pcm_spi_cs2_p128),
+	PINCTRL_PIN_GROUP("pcm_spi_cs2_p156", en7581_pcm_spi_cs2_p156),
+	PINCTRL_PIN_GROUP("pcm_spi_cs2", en7581_pcm_spi_cs2),
+	PINCTRL_PIN_GROUP("pcm_spi_cs3", en7581_pcm_spi_cs3),
+	PINCTRL_PIN_GROUP("pcm_spi_cs4", en7581_pcm_spi_cs4),
+	PINCTRL_PIN_GROUP("emmc", en7581_emmc),
+	PINCTRL_PIN_GROUP("pnand", en7581_pnand),
+	PINCTRL_PIN_GROUP("gpio0", en7581_gpio0),
+	PINCTRL_PIN_GROUP("gpio1", en7581_gpio1),
+	PINCTRL_PIN_GROUP("gpio2", en7581_gpio2),
+	PINCTRL_PIN_GROUP("gpio3", en7581_gpio3),
+	PINCTRL_PIN_GROUP("gpio4", en7581_gpio4),
+	PINCTRL_PIN_GROUP("gpio5", en7581_gpio5),
+	PINCTRL_PIN_GROUP("gpio6", en7581_gpio6),
+	PINCTRL_PIN_GROUP("gpio7", en7581_gpio7),
+	PINCTRL_PIN_GROUP("gpio8", en7581_gpio8),
+	PINCTRL_PIN_GROUP("gpio9", en7581_gpio9),
+	PINCTRL_PIN_GROUP("gpio10", en7581_gpio10),
+	PINCTRL_PIN_GROUP("gpio11", en7581_gpio11),
+	PINCTRL_PIN_GROUP("gpio12", en7581_gpio12),
+	PINCTRL_PIN_GROUP("gpio13", en7581_gpio13),
+	PINCTRL_PIN_GROUP("gpio14", en7581_gpio14),
+	PINCTRL_PIN_GROUP("gpio15", en7581_gpio15),
+	PINCTRL_PIN_GROUP("gpio16", en7581_gpio16),
+	PINCTRL_PIN_GROUP("gpio17", en7581_gpio17),
+	PINCTRL_PIN_GROUP("gpio18", en7581_gpio18),
+	PINCTRL_PIN_GROUP("gpio19", en7581_gpio19),
+	PINCTRL_PIN_GROUP("gpio20", en7581_gpio20),
+	PINCTRL_PIN_GROUP("gpio21", en7581_gpio21),
+	PINCTRL_PIN_GROUP("gpio22", en7581_gpio22),
+	PINCTRL_PIN_GROUP("gpio23", en7581_gpio23),
+	PINCTRL_PIN_GROUP("gpio24", en7581_gpio24),
+	PINCTRL_PIN_GROUP("gpio25", en7581_gpio25),
+	PINCTRL_PIN_GROUP("gpio26", en7581_gpio26),
+	PINCTRL_PIN_GROUP("gpio27", en7581_gpio27),
+	PINCTRL_PIN_GROUP("gpio28", en7581_gpio28),
+	PINCTRL_PIN_GROUP("gpio29", en7581_gpio29),
+	PINCTRL_PIN_GROUP("gpio30", en7581_gpio30),
+	PINCTRL_PIN_GROUP("gpio31", en7581_gpio31),
+	PINCTRL_PIN_GROUP("gpio32", en7581_gpio32),
+	PINCTRL_PIN_GROUP("gpio33", en7581_gpio33),
+	PINCTRL_PIN_GROUP("gpio34", en7581_gpio34),
+	PINCTRL_PIN_GROUP("gpio35", en7581_gpio35),
+	PINCTRL_PIN_GROUP("gpio36", en7581_gpio36),
+	PINCTRL_PIN_GROUP("gpio37", en7581_gpio37),
+	PINCTRL_PIN_GROUP("gpio38", en7581_gpio38),
+	PINCTRL_PIN_GROUP("gpio39", en7581_gpio39),
+	PINCTRL_PIN_GROUP("gpio40", en7581_gpio40),
+	PINCTRL_PIN_GROUP("gpio41", en7581_gpio41),
+	PINCTRL_PIN_GROUP("gpio42", en7581_gpio42),
+	PINCTRL_PIN_GROUP("gpio43", en7581_gpio43),
+	PINCTRL_PIN_GROUP("gpio44", en7581_gpio44),
+	PINCTRL_PIN_GROUP("gpio45", en7581_gpio45),
+	PINCTRL_PIN_GROUP("gpio46", en7581_gpio46),
+	PINCTRL_PIN_GROUP("gpio47", en7581_gpio47),
+	PINCTRL_PIN_GROUP("gpio48", en7581_gpio48),
+	PINCTRL_PIN_GROUP("gpio49", en7581_gpio49),
+	PINCTRL_PIN_GROUP("pcie_reset0", en7581_pcie_reset0),
+	PINCTRL_PIN_GROUP("pcie_reset1", en7581_pcie_reset1),
+	PINCTRL_PIN_GROUP("pcie_reset2", en7581_pcie_reset2),
+};
+
+static const char *const pon_groups[] = { "pon" };
+static const char *const tod_1pps_groups[] = {
+	"pon_tod_1pps", "gsw_tod_1pps"
+};
+static const char *const sipo_groups[] = { "sipo", "sipo_rclk" };
+static const char *const mdio_groups[] = { "mdio" };
+static const char *const uart_groups[] = {
+	"uart2", "uart2_cts_rts", "hsuart", "hsuart_cts_rts",
+	"uart4", "uart5"
+};
+static const char *const i2c_groups[] = { "i2c1" };
+static const char *const jtag_groups[] = { "jtag_udi", "jtag_dfd" };
+static const char *const pcm_groups[] = { "pcm1", "pcm2" };
+static const char *const spi_groups[] = { "spi_quad", "spi_cs1" };
+static const char *const pcm_spi_groups[] = {
+	"pcm_spi", "pcm_spi_int", "pcm_spi_rst", "pcm_spi_cs1",
+	"pcm_spi_cs2_p156", "pcm_spi_cs2_p128", "pcm_spi_cs3",
+	"pcm_spi_cs4"
+};
+static const char *const i2s_groups[] = { "i2s" };
+static const char *const emmc_groups[] = { "emmc" };
+static const char *const pnand_groups[] = { "pnand" };
+static const char *const gpio_groups[] = { "gpio47", "gpio48", "gpio49" };
+static const char *const pcie_reset_groups[] = {
+	"pcie_reset0", "pcie_reset1", "pcie_reset2"
+};
+static const char *const pwm_groups[] = {
+	"gpio0",  "gpio1",  "gpio2",  "gpio3",  "gpio4",  "gpio5",
+	"gpio6",  "gpio7",  "gpio8",  "gpio9",  "gpio10", "gpio11",
+	"gpio12", "gpio13", "gpio14", "gpio15", "gpio16", "gpio17",
+	"gpio18", "gpio19", "gpio20", "gpio21", "gpio22", "gpio23",
+	"gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29",
+	"gpio30", "gpio31", "gpio36", "gpio37", "gpio38", "gpio39",
+	"gpio40", "gpio41", "gpio42", "gpio43", "gpio44", "gpio45",
+	"gpio46", "gpio47", "gpio48", "gpio49"
+};
+static const char *const phy1_led0_groups[] = {
+	"gpio33", "gpio34", "gpio35", "gpio42"
+};
+static const char *const phy2_led0_groups[] = {
+	"gpio33", "gpio34", "gpio35", "gpio42"
+};
+static const char *const phy3_led0_groups[] = {
+	"gpio33", "gpio34", "gpio35", "gpio42"
+};
+static const char *const phy4_led0_groups[] = {
+	"gpio33", "gpio34", "gpio35", "gpio42"
+};
+static const char *const phy1_led1_groups[] = {
+	"gpio43", "gpio44", "gpio45", "gpio46"
+};
+static const char *const phy2_led1_groups[] = {
+	"gpio43", "gpio44", "gpio45", "gpio46"
+};
+static const char *const phy3_led1_groups[] = {
+	"gpio43", "gpio44", "gpio45", "gpio46"
+};
+static const char *const phy4_led1_groups[] = {
+	"gpio43", "gpio44", "gpio45", "gpio46"
+};
+
+static const struct airoha_pinctrl_func_group pon_func_group[] = {
+	{
+		.name = "pon",
+		.regmap[0] = {
+			AIROHA_FUNC_MUX,
+			REG_GPIO_PON_MODE,
+			GPIO_PON_MODE_MASK,
+			GPIO_PON_MODE_MASK
+		},
+		.regmap_size = 1,
+	},
+};
+
+static const struct airoha_pinctrl_func_group tod_1pps_func_group[] = {
+	{
+		.name = "pon_tod_1pps",
+		.regmap[0] = {
+			AIROHA_FUNC_MUX,
+			REG_GPIO_2ND_I2C_MODE,
+			PON_TOD_1PPS_MODE_MASK,
+			PON_TOD_1PPS_MODE_MASK
+		},
+		.regmap_size = 1,
+	}, {
+		.name = "gsw_tod_1pps",
+		.regmap[0] = {
+			AIROHA_FUNC_MUX,
+			REG_GPIO_2ND_I2C_MODE,
+			GSW_TOD_1PPS_MODE_MASK,
+			GSW_TOD_1PPS_MODE_MASK
+		},
+		.regmap_size = 1,
+	},
+};
+
+static const struct airoha_pinctrl_func_group sipo_func_group[] = {
+	{
+		.name = "sipo",
+		.regmap[0] = {
+			AIROHA_FUNC_MUX,
+			REG_GPIO_PON_MODE,
+			GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK,
+			GPIO_SIPO_MODE_MASK
+		},
+		.regmap_size = 1,
+	}, {
+		.name = "sipo_rclk",
+		.regmap[0] = {
+			AIROHA_FUNC_MUX,
+			REG_GPIO_PON_MODE,
+			GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK,
+			GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK
+		},
+		.regmap_size = 1,
+	},
+};
+
+static const struct airoha_pinctrl_func_group mdio_func_group[] = {
+	{
+		.name = "mdio",
+		.regmap[0] = {
+			AIROHA_FUNC_MUX,
+			REG_GPIO_2ND_I2C_MODE,
+			GPIO_MDC_IO_MASTER_MODE_MASK,
+			GPIO_MDC_IO_MASTER_MODE_MASK
+		},
+		.regmap[1] = {
+			AIROHA_FUNC_MUX,
+			REG_FORCE_GPIO_EN,
+			FORCE_GPIO_EN(1) | FORCE_GPIO_EN(2),
+			FORCE_GPIO_EN(1) | FORCE_GPIO_EN(2)
+		},
+		.regmap_size = 2,
+	},
+};
+
+static const struct airoha_pinctrl_func_group uart_func_group[] = {
+	{
+		.name = "uart2",
+		.regmap[0] = {
+			AIROHA_FUNC_MUX,
+			REG_GPIO_PON_MODE,
+			GPIO_UART2_MODE_MASK,
+			GPIO_UART2_MODE_MASK
+		},
+		.regmap_size = 1,
+	}, {
+		.name = "uart2_cts_rts",
+		.regmap[0] = {
+			AIROHA_FUNC_MUX,
+			REG_GPIO_PON_MODE,
+			GPIO_UART2_MODE_MASK | GPIO_UART2_CTS_RTS_MODE_MASK,
+			GPIO_UART2_MODE_MASK | GPIO_UART2_CTS_RTS_MODE_MASK
+		},
+		.regmap_size = 1,
+	}, {
+		.name = "hsuart",
+		.regmap[0] = {
+			AIROHA_FUNC_MUX,
+			REG_GPIO_PON_MODE,
+			GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK,
+			GPIO_HSUART_MODE_MASK
+		},
+		.regmap_size = 1,
+	},
+	{
+		.name = "hsuart_cts_rts",
+		.regmap[0] = {
+			AIROHA_FUNC_MUX,
+			REG_GPIO_PON_MODE,
+			GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK,
+			GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK
+		},
+		.regmap_size = 1,
+	}, {
+		.name = "uart4",
+		.regmap[0] = {
+			AIROHA_FUNC_MUX,
+			REG_GPIO_PON_MODE,
+			GPIO_UART4_MODE_MASK,
+			GPIO_UART4_MODE_MASK
+		},
+		.regmap_size = 1,
+	}, {
+		.name = "uart5",
+		.regmap[0] = {
+			AIROHA_FUNC_MUX,
+			REG_GPIO_PON_MODE,
+			GPIO_UART5_MODE_MASK,
+			GPIO_UART5_MODE_MASK
+		},
+		.regmap_size = 1,
+	},
+};
+
+static const struct airoha_pinctrl_func_group i2c_func_group[] = {
+	{
+		.name = "i2c1",
+		.regmap[0] = {
+			AIROHA_FUNC_MUX,
+			REG_GPIO_2ND_I2C_MODE,
+			GPIO_2ND_I2C_MODE_MASK,
+			GPIO_2ND_I2C_MODE_MASK
+		},
+		.regmap_size = 1,
+	},
+};
+
+static const struct airoha_pinctrl_func_group jtag_func_group[] = {
+	{
+		.name = "jtag_udi",
+		.regmap[0] = {
+			AIROHA_FUNC_MUX,
+			REG_NPU_UART_EN,
+			JTAG_UDI_EN_MASK,
+			JTAG_UDI_EN_MASK
+		},
+		.regmap_size = 1,
+	}, {
+		.name = "jtag_dfd",
+		.regmap[0] = {
+			AIROHA_FUNC_MUX,
+			REG_NPU_UART_EN,
+			JTAG_DFD_EN_MASK,
+			JTAG_DFD_EN_MASK
+		},
+		.regmap_size = 1,
+	},
+};
+
+static const struct airoha_pinctrl_func_group pcm_func_group[] = {
+	{
+		.name = "pcm1",
+		.regmap[0] = {
+			AIROHA_FUNC_MUX,
+			REG_GPIO_SPI_CS1_MODE,
+			GPIO_PCM1_MODE_MASK,
+			GPIO_PCM1_MODE_MASK
+		},
+		.regmap_size = 1,
+	}, {
+		.name = "pcm2",
+		.regmap[0] = {
+			AIROHA_FUNC_MUX,
+			REG_GPIO_SPI_CS1_MODE,
+			GPIO_PCM2_MODE_MASK,
+			GPIO_PCM2_MODE_MASK
+		},
+		.regmap_size = 1,
+	},
+};
+
+static const struct airoha_pinctrl_func_group spi_func_group[] = {
+	{
+		.name = "spi_quad",
+		.regmap[0] = {
+			AIROHA_FUNC_MUX,
+			REG_GPIO_SPI_CS1_MODE,
+			GPIO_SPI_QUAD_MODE_MASK,
+			GPIO_SPI_QUAD_MODE_MASK
+		},
+		.regmap_size = 1,
+	}, {
+		.name = "spi_cs1",
+		.regmap[0] = {
+			AIROHA_FUNC_MUX,
+			REG_GPIO_SPI_CS1_MODE,
+			GPIO_SPI_CS1_MODE_MASK,
+			GPIO_SPI_CS1_MODE_MASK
+		},
+		.regmap_size = 1,
+	}, {
+		.name = "spi_cs2",
+		.regmap[0] = {
+			AIROHA_FUNC_MUX,
+			REG_GPIO_SPI_CS1_MODE,
+			GPIO_SPI_CS2_MODE_MASK,
+			GPIO_SPI_CS2_MODE_MASK
+		},
+		.regmap_size = 1,
+	}, {
+		.name = "spi_cs3",
+		.regmap[0] = {
+			AIROHA_FUNC_MUX,
+			REG_GPIO_SPI_CS1_MODE,
+			GPIO_SPI_CS3_MODE_MASK,
+			GPIO_SPI_CS3_MODE_MASK
+		},
+		.regmap_size = 1,
+	}, {
+		.name = "spi_cs4",
+		.regmap[0] = {
+			AIROHA_FUNC_MUX,
+			REG_GPIO_SPI_CS1_MODE,
+			GPIO_SPI_CS4_MODE_MASK,
+			GPIO_SPI_CS4_MODE_MASK
+		},
+		.regmap_size = 1,
+	},
+};
+
+static const struct airoha_pinctrl_func_group pcm_spi_func_group[] = {
+	{
+		.name = "pcm_spi",
+		.regmap[0] = {
+			AIROHA_FUNC_MUX,
+			REG_GPIO_SPI_CS1_MODE,
+			GPIO_PCM_SPI_MODE_MASK,
+			GPIO_PCM_SPI_MODE_MASK
+		},
+		.regmap_size = 1,
+	}, {
+		.name = "pcm_spi_int",
+		.regmap[0] = {
+			AIROHA_FUNC_MUX,
+			REG_GPIO_SPI_CS1_MODE,
+			GPIO_PCM_INT_MODE_MASK,
+			GPIO_PCM_INT_MODE_MASK
+		},
+		.regmap_size = 1,
+	}, {
+		.name = "pcm_spi_rst",
+		.regmap[0] = {
+			AIROHA_FUNC_MUX,
+			REG_GPIO_SPI_CS1_MODE,
+			GPIO_PCM_RESET_MODE_MASK,
+			GPIO_PCM_RESET_MODE_MASK
+		},
+		.regmap_size = 1,
+	}, {
+		.name = "pcm_spi_cs1",
+		.regmap[0] = {
+			AIROHA_FUNC_MUX,
+			REG_GPIO_SPI_CS1_MODE,
+			GPIO_PCM_SPI_CS1_MODE_MASK,
+			GPIO_PCM_SPI_CS1_MODE_MASK
+		},
+		.regmap_size = 1,
+	}, {
+		.name = "pcm_spi_cs2_p128",
+		.regmap[0] = {
+			AIROHA_FUNC_MUX,
+			REG_GPIO_SPI_CS1_MODE,
+			GPIO_PCM_SPI_CS2_MODE_P128_MASK,
+			GPIO_PCM_SPI_CS2_MODE_P128_MASK
+		},
+		.regmap_size = 1,
+	}, {
+		.name = "pcm_spi_cs2_p156",
+		.regmap[0] = {
+			AIROHA_FUNC_MUX,
+			REG_GPIO_SPI_CS1_MODE,
+			GPIO_PCM_SPI_CS2_MODE_P156_MASK,
+			GPIO_PCM_SPI_CS2_MODE_P156_MASK
+		},
+		.regmap_size = 1,
+	}, {
+		.name = "pcm_spi_cs3",
+		.regmap[0] = {
+			AIROHA_FUNC_MUX,
+			REG_GPIO_SPI_CS1_MODE,
+			GPIO_PCM_SPI_CS3_MODE_MASK,
+			GPIO_PCM_SPI_CS3_MODE_MASK
+		},
+		.regmap_size = 1,
+	}, {
+		.name = "pcm_spi_cs4",
+		.regmap[0] = {
+			AIROHA_FUNC_MUX,
+			REG_GPIO_SPI_CS1_MODE,
+			GPIO_PCM_SPI_CS4_MODE_MASK,
+			GPIO_PCM_SPI_CS4_MODE_MASK
+		},
+		.regmap_size = 1,
+	},
+};
+
+static const struct airoha_pinctrl_func_group i2s_func_group[] = {
+	{
+		.name = "i2s",
+		.regmap[0] = {
+			AIROHA_FUNC_MUX,
+			REG_GPIO_2ND_I2C_MODE,
+			GPIO_I2S_MODE_MASK,
+			GPIO_I2S_MODE_MASK
+		},
+		.regmap_size = 1,
+	},
+};
+
+static const struct airoha_pinctrl_func_group emmc_func_group[] = {
+	{
+		.name = "emmc",
+		.regmap[0] = {
+			AIROHA_FUNC_MUX,
+			REG_GPIO_PON_MODE,
+			GPIO_EMMC_MODE_MASK,
+			GPIO_EMMC_MODE_MASK
+		},
+		.regmap_size = 1,
+	},
+};
+
+static const struct airoha_pinctrl_func_group pnand_func_group[] = {
+	{
+		.name = "pnand",
+		.regmap[0] = {
+			AIROHA_FUNC_MUX,
+			REG_GPIO_PON_MODE,
+			GPIO_PARALLEL_NAND_MODE_MASK,
+			GPIO_PARALLEL_NAND_MODE_MASK
+		},
+		.regmap_size = 1,
+	},
+};
+
+static const struct airoha_pinctrl_func_group gpio_func_group[] = {
+	AIROHA_PINCTRL_GPIO_EXT("gpio47", GPIO47_FLASH_MODE_CFG,
+				GPIO_PCIE_RESET0_MASK),
+	AIROHA_PINCTRL_GPIO_EXT("gpio48", GPIO48_FLASH_MODE_CFG,
+				GPIO_PCIE_RESET1_MASK),
+	AIROHA_PINCTRL_GPIO_EXT("gpio49", GPIO49_FLASH_MODE_CFG,
+				GPIO_PCIE_RESET2_MASK),
+};
+
+static const struct airoha_pinctrl_func_group pcie_reset_func_group[] = {
+	{
+		.name = "pcie_reset0",
+		.regmap[0] = {
+			AIROHA_FUNC_MUX,
+			REG_GPIO_PON_MODE,
+			GPIO_PCIE_RESET0_MASK,
+			0
+		},
+		.regmap_size = 1,
+	}, {
+		.name = "pcie_reset1",
+		.regmap[0] = {
+			AIROHA_FUNC_MUX,
+			REG_GPIO_PON_MODE,
+			GPIO_PCIE_RESET1_MASK,
+			0
+		},
+		.regmap_size = 1,
+	}, {
+		.name = "pcie_reset2",
+		.regmap[0] = {
+			AIROHA_FUNC_MUX,
+			REG_GPIO_PON_MODE,
+			GPIO_PCIE_RESET2_MASK,
+			0
+		},
+		.regmap_size = 1,
+	},
+};
+
+static const struct airoha_pinctrl_func_group pwm_func_group[] = {
+	AIROHA_PINCTRL_PWM("gpio0", GPIO0_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM("gpio1", GPIO1_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM("gpio2", GPIO2_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM("gpio3", GPIO3_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM("gpio4", GPIO4_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM("gpio5", GPIO5_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM("gpio6", GPIO6_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM("gpio7", GPIO7_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM("gpio8", GPIO8_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM("gpio9", GPIO9_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM("gpio10", GPIO10_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM("gpio11", GPIO11_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM("gpio12", GPIO12_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM("gpio13", GPIO13_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM("gpio14", GPIO14_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM("gpio15", GPIO15_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM_EXT("gpio16", GPIO16_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM_EXT("gpio17", GPIO17_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM_EXT("gpio18", GPIO18_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM_EXT("gpio19", GPIO19_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM_EXT("gpio20", GPIO20_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM_EXT("gpio21", GPIO21_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM_EXT("gpio22", GPIO22_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM_EXT("gpio23", GPIO23_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM_EXT("gpio24", GPIO24_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM_EXT("gpio25", GPIO25_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM_EXT("gpio26", GPIO26_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM_EXT("gpio27", GPIO27_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM_EXT("gpio28", GPIO28_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM_EXT("gpio29", GPIO29_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM_EXT("gpio30", GPIO30_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM_EXT("gpio31", GPIO31_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM_EXT("gpio36", GPIO36_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM_EXT("gpio37", GPIO37_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM_EXT("gpio38", GPIO38_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM_EXT("gpio39", GPIO39_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM_EXT("gpio40", GPIO40_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM_EXT("gpio41", GPIO41_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM_EXT("gpio42", GPIO42_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM_EXT("gpio43", GPIO43_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM_EXT("gpio44", GPIO44_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM_EXT("gpio45", GPIO45_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM_EXT("gpio46", GPIO46_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM_EXT_SEC("gpio47", GPIO47_FLASH_MODE_CFG,
+				   GPIO_PCIE_RESET0_MASK),
+	AIROHA_PINCTRL_PWM_EXT_SEC("gpio48", GPIO48_FLASH_MODE_CFG,
+				   GPIO_PCIE_RESET1_MASK),
+	AIROHA_PINCTRL_PWM_EXT_SEC("gpio49", GPIO49_FLASH_MODE_CFG,
+				   GPIO_PCIE_RESET2_MASK),
+};
+
+static const struct airoha_pinctrl_func_group phy1_led0_func_group[] = {
+	AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK,
+				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),
+	AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK,
+				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)),
+	AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK,
+				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)),
+	AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK,
+				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),
+};
+
+static const struct airoha_pinctrl_func_group phy2_led0_func_group[] = {
+	AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK,
+				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),
+	AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK,
+				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)),
+	AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK,
+				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)),
+	AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK,
+				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),
+};
+
+static const struct airoha_pinctrl_func_group phy3_led0_func_group[] = {
+	AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK,
+				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
+	AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK,
+				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),
+	AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK,
+				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),
+	AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK,
+				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
+};
+
+static const struct airoha_pinctrl_func_group phy4_led0_func_group[] = {
+	AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK,
+				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)),
+	AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK,
+				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)),
+	AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK,
+				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)),
+	AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK,
+				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)),
+};
+
+static const struct airoha_pinctrl_func_group phy1_led1_func_group[] = {
+	AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK,
+				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),
+	AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK,
+				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)),
+	AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK,
+				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)),
+	AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK,
+				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),
+};
+
+static const struct airoha_pinctrl_func_group phy2_led1_func_group[] = {
+	AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK,
+				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),
+	AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK,
+				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)),
+	AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK,
+				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)),
+	AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK,
+				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),
+};
+
+static const struct airoha_pinctrl_func_group phy3_led1_func_group[] = {
+	AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK,
+				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
+	AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK,
+				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),
+	AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK,
+				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),
+	AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK,
+				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
+};
+
+static const struct airoha_pinctrl_func_group phy4_led1_func_group[] = {
+	AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK,
+				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)),
+	AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK,
+				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)),
+	AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK,
+				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)),
+	AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK,
+				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)),
+};
+
+static const struct airoha_pinctrl_func en7581_pinctrl_funcs[] = {
+	PINCTRL_FUNC_DESC("pon", pon),
+	PINCTRL_FUNC_DESC("tod_1pps", tod_1pps),
+	PINCTRL_FUNC_DESC("sipo", sipo),
+	PINCTRL_FUNC_DESC("mdio", mdio),
+	PINCTRL_FUNC_DESC("uart", uart),
+	PINCTRL_FUNC_DESC("i2c", i2c),
+	PINCTRL_FUNC_DESC("jtag", jtag),
+	PINCTRL_FUNC_DESC("pcm", pcm),
+	PINCTRL_FUNC_DESC("spi", spi),
+	PINCTRL_FUNC_DESC("pcm_spi", pcm_spi),
+	PINCTRL_FUNC_DESC("i2s", i2s),
+	PINCTRL_FUNC_DESC("emmc", emmc),
+	PINCTRL_FUNC_DESC("pnand", pnand),
+	PINCTRL_FUNC_DESC("gpio", gpio),
+	PINCTRL_FUNC_DESC("pcie_reset", pcie_reset),
+	PINCTRL_FUNC_DESC("pwm", pwm),
+	PINCTRL_FUNC_DESC("phy1_led0", phy1_led0),
+	PINCTRL_FUNC_DESC("phy2_led0", phy2_led0),
+	PINCTRL_FUNC_DESC("phy3_led0", phy3_led0),
+	PINCTRL_FUNC_DESC("phy4_led0", phy4_led0),
+	PINCTRL_FUNC_DESC("phy1_led1", phy1_led1),
+	PINCTRL_FUNC_DESC("phy2_led1", phy2_led1),
+	PINCTRL_FUNC_DESC("phy3_led1", phy3_led1),
+	PINCTRL_FUNC_DESC("phy4_led1", phy4_led1),
+};
+
+static const struct airoha_pinctrl_conf en7581_pinctrl_pullup_conf[] = {
+	PINCTRL_CONF_DESC(0, REG_I2C_SDA_PU, UART1_TXD_PU_MASK),
+	PINCTRL_CONF_DESC(1, REG_I2C_SDA_PU, UART1_RXD_PU_MASK),
+	PINCTRL_CONF_DESC(2, REG_I2C_SDA_PU, I2C_SDA_PU_MASK),
+	PINCTRL_CONF_DESC(3, REG_I2C_SDA_PU, I2C_SCL_PU_MASK),
+	PINCTRL_CONF_DESC(4, REG_I2C_SDA_PU, SPI_CS0_PU_MASK),
+	PINCTRL_CONF_DESC(5, REG_I2C_SDA_PU, SPI_CLK_PU_MASK),
+	PINCTRL_CONF_DESC(6, REG_I2C_SDA_PU, SPI_MOSI_PU_MASK),
+	PINCTRL_CONF_DESC(7, REG_I2C_SDA_PU, SPI_MISO_PU_MASK),
+	PINCTRL_CONF_DESC(13, REG_GPIO_L_PU, BIT(0)),
+	PINCTRL_CONF_DESC(14, REG_GPIO_L_PU, BIT(1)),
+	PINCTRL_CONF_DESC(15, REG_GPIO_L_PU, BIT(2)),
+	PINCTRL_CONF_DESC(16, REG_GPIO_L_PU, BIT(3)),
+	PINCTRL_CONF_DESC(17, REG_GPIO_L_PU, BIT(4)),
+	PINCTRL_CONF_DESC(18, REG_GPIO_L_PU, BIT(5)),
+	PINCTRL_CONF_DESC(19, REG_GPIO_L_PU, BIT(6)),
+	PINCTRL_CONF_DESC(20, REG_GPIO_L_PU, BIT(7)),
+	PINCTRL_CONF_DESC(21, REG_GPIO_L_PU, BIT(8)),
+	PINCTRL_CONF_DESC(22, REG_GPIO_L_PU, BIT(9)),
+	PINCTRL_CONF_DESC(23, REG_GPIO_L_PU, BIT(10)),
+	PINCTRL_CONF_DESC(24, REG_GPIO_L_PU, BIT(11)),
+	PINCTRL_CONF_DESC(25, REG_GPIO_L_PU, BIT(12)),
+	PINCTRL_CONF_DESC(26, REG_GPIO_L_PU, BIT(13)),
+	PINCTRL_CONF_DESC(27, REG_GPIO_L_PU, BIT(14)),
+	PINCTRL_CONF_DESC(28, REG_GPIO_L_PU, BIT(15)),
+	PINCTRL_CONF_DESC(29, REG_GPIO_L_PU, BIT(16)),
+	PINCTRL_CONF_DESC(30, REG_GPIO_L_PU, BIT(17)),
+	PINCTRL_CONF_DESC(31, REG_GPIO_L_PU, BIT(18)),
+	PINCTRL_CONF_DESC(32, REG_GPIO_L_PU, BIT(19)),
+	PINCTRL_CONF_DESC(33, REG_GPIO_L_PU, BIT(20)),
+	PINCTRL_CONF_DESC(34, REG_GPIO_L_PU, BIT(21)),
+	PINCTRL_CONF_DESC(35, REG_GPIO_L_PU, BIT(22)),
+	PINCTRL_CONF_DESC(36, REG_GPIO_L_PU, BIT(23)),
+	PINCTRL_CONF_DESC(37, REG_GPIO_L_PU, BIT(24)),
+	PINCTRL_CONF_DESC(38, REG_GPIO_L_PU, BIT(25)),
+	PINCTRL_CONF_DESC(39, REG_GPIO_L_PU, BIT(26)),
+	PINCTRL_CONF_DESC(40, REG_GPIO_L_PU, BIT(27)),
+	PINCTRL_CONF_DESC(41, REG_GPIO_L_PU, BIT(28)),
+	PINCTRL_CONF_DESC(42, REG_GPIO_L_PU, BIT(29)),
+	PINCTRL_CONF_DESC(43, REG_GPIO_L_PU, BIT(30)),
+	PINCTRL_CONF_DESC(44, REG_GPIO_L_PU, BIT(31)),
+	PINCTRL_CONF_DESC(45, REG_GPIO_H_PU, BIT(0)),
+	PINCTRL_CONF_DESC(46, REG_GPIO_H_PU, BIT(1)),
+	PINCTRL_CONF_DESC(47, REG_GPIO_H_PU, BIT(2)),
+	PINCTRL_CONF_DESC(48, REG_GPIO_H_PU, BIT(3)),
+	PINCTRL_CONF_DESC(49, REG_GPIO_H_PU, BIT(4)),
+	PINCTRL_CONF_DESC(50, REG_GPIO_H_PU, BIT(5)),
+	PINCTRL_CONF_DESC(51, REG_GPIO_H_PU, BIT(6)),
+	PINCTRL_CONF_DESC(52, REG_GPIO_H_PU, BIT(7)),
+	PINCTRL_CONF_DESC(53, REG_GPIO_H_PU, BIT(8)),
+	PINCTRL_CONF_DESC(54, REG_GPIO_H_PU, BIT(9)),
+	PINCTRL_CONF_DESC(55, REG_GPIO_H_PU, BIT(10)),
+	PINCTRL_CONF_DESC(56, REG_GPIO_H_PU, BIT(11)),
+	PINCTRL_CONF_DESC(57, REG_GPIO_H_PU, BIT(12)),
+	PINCTRL_CONF_DESC(58, REG_GPIO_H_PU, BIT(13)),
+	PINCTRL_CONF_DESC(59, REG_GPIO_H_PU, BIT(14)),
+	PINCTRL_CONF_DESC(60, REG_I2C_SDA_PU, PCIE0_RESET_PU_MASK),
+	PINCTRL_CONF_DESC(61, REG_I2C_SDA_PU, PCIE1_RESET_PU_MASK),
+	PINCTRL_CONF_DESC(62, REG_I2C_SDA_PU, PCIE2_RESET_PU_MASK),
+};
+
+static const struct airoha_pinctrl_conf en7581_pinctrl_pulldown_conf[] = {
+	PINCTRL_CONF_DESC(0, REG_I2C_SDA_PD, UART1_TXD_PD_MASK),
+	PINCTRL_CONF_DESC(1, REG_I2C_SDA_PD, UART1_RXD_PD_MASK),
+	PINCTRL_CONF_DESC(2, REG_I2C_SDA_PD, I2C_SDA_PD_MASK),
+	PINCTRL_CONF_DESC(3, REG_I2C_SDA_PD, I2C_SCL_PD_MASK),
+	PINCTRL_CONF_DESC(4, REG_I2C_SDA_PD, SPI_CS0_PD_MASK),
+	PINCTRL_CONF_DESC(5, REG_I2C_SDA_PD, SPI_CLK_PD_MASK),
+	PINCTRL_CONF_DESC(6, REG_I2C_SDA_PD, SPI_MOSI_PD_MASK),
+	PINCTRL_CONF_DESC(7, REG_I2C_SDA_PD, SPI_MISO_PD_MASK),
+	PINCTRL_CONF_DESC(13, REG_GPIO_L_PD, BIT(0)),
+	PINCTRL_CONF_DESC(14, REG_GPIO_L_PD, BIT(1)),
+	PINCTRL_CONF_DESC(15, REG_GPIO_L_PD, BIT(2)),
+	PINCTRL_CONF_DESC(16, REG_GPIO_L_PD, BIT(3)),
+	PINCTRL_CONF_DESC(17, REG_GPIO_L_PD, BIT(4)),
+	PINCTRL_CONF_DESC(18, REG_GPIO_L_PD, BIT(5)),
+	PINCTRL_CONF_DESC(19, REG_GPIO_L_PD, BIT(6)),
+	PINCTRL_CONF_DESC(20, REG_GPIO_L_PD, BIT(7)),
+	PINCTRL_CONF_DESC(21, REG_GPIO_L_PD, BIT(8)),
+	PINCTRL_CONF_DESC(22, REG_GPIO_L_PD, BIT(9)),
+	PINCTRL_CONF_DESC(23, REG_GPIO_L_PD, BIT(10)),
+	PINCTRL_CONF_DESC(24, REG_GPIO_L_PD, BIT(11)),
+	PINCTRL_CONF_DESC(25, REG_GPIO_L_PD, BIT(12)),
+	PINCTRL_CONF_DESC(26, REG_GPIO_L_PD, BIT(13)),
+	PINCTRL_CONF_DESC(27, REG_GPIO_L_PD, BIT(14)),
+	PINCTRL_CONF_DESC(28, REG_GPIO_L_PD, BIT(15)),
+	PINCTRL_CONF_DESC(29, REG_GPIO_L_PD, BIT(16)),
+	PINCTRL_CONF_DESC(30, REG_GPIO_L_PD, BIT(17)),
+	PINCTRL_CONF_DESC(31, REG_GPIO_L_PD, BIT(18)),
+	PINCTRL_CONF_DESC(32, REG_GPIO_L_PD, BIT(19)),
+	PINCTRL_CONF_DESC(33, REG_GPIO_L_PD, BIT(20)),
+	PINCTRL_CONF_DESC(34, REG_GPIO_L_PD, BIT(21)),
+	PINCTRL_CONF_DESC(35, REG_GPIO_L_PD, BIT(22)),
+	PINCTRL_CONF_DESC(36, REG_GPIO_L_PD, BIT(23)),
+	PINCTRL_CONF_DESC(37, REG_GPIO_L_PD, BIT(24)),
+	PINCTRL_CONF_DESC(38, REG_GPIO_L_PD, BIT(25)),
+	PINCTRL_CONF_DESC(39, REG_GPIO_L_PD, BIT(26)),
+	PINCTRL_CONF_DESC(40, REG_GPIO_L_PD, BIT(27)),
+	PINCTRL_CONF_DESC(41, REG_GPIO_L_PD, BIT(28)),
+	PINCTRL_CONF_DESC(42, REG_GPIO_L_PD, BIT(29)),
+	PINCTRL_CONF_DESC(43, REG_GPIO_L_PD, BIT(30)),
+	PINCTRL_CONF_DESC(44, REG_GPIO_L_PD, BIT(31)),
+	PINCTRL_CONF_DESC(45, REG_GPIO_H_PD, BIT(0)),
+	PINCTRL_CONF_DESC(46, REG_GPIO_H_PD, BIT(1)),
+	PINCTRL_CONF_DESC(47, REG_GPIO_H_PD, BIT(2)),
+	PINCTRL_CONF_DESC(48, REG_GPIO_H_PD, BIT(3)),
+	PINCTRL_CONF_DESC(49, REG_GPIO_H_PD, BIT(4)),
+	PINCTRL_CONF_DESC(50, REG_GPIO_H_PD, BIT(5)),
+	PINCTRL_CONF_DESC(51, REG_GPIO_H_PD, BIT(6)),
+	PINCTRL_CONF_DESC(52, REG_GPIO_H_PD, BIT(7)),
+	PINCTRL_CONF_DESC(53, REG_GPIO_H_PD, BIT(8)),
+	PINCTRL_CONF_DESC(54, REG_GPIO_H_PD, BIT(9)),
+	PINCTRL_CONF_DESC(55, REG_GPIO_H_PD, BIT(10)),
+	PINCTRL_CONF_DESC(56, REG_GPIO_H_PD, BIT(11)),
+	PINCTRL_CONF_DESC(57, REG_GPIO_H_PD, BIT(12)),
+	PINCTRL_CONF_DESC(58, REG_GPIO_H_PD, BIT(13)),
+	PINCTRL_CONF_DESC(59, REG_GPIO_H_PD, BIT(14)),
+	PINCTRL_CONF_DESC(60, REG_I2C_SDA_PD, PCIE0_RESET_PD_MASK),
+	PINCTRL_CONF_DESC(61, REG_I2C_SDA_PD, PCIE1_RESET_PD_MASK),
+	PINCTRL_CONF_DESC(62, REG_I2C_SDA_PD, PCIE2_RESET_PD_MASK),
+};
+
+static const struct airoha_pinctrl_conf en7581_pinctrl_drive_e2_conf[] = {
+	PINCTRL_CONF_DESC(0, REG_I2C_SDA_E2, UART1_TXD_E2_MASK),
+	PINCTRL_CONF_DESC(1, REG_I2C_SDA_E2, UART1_RXD_E2_MASK),
+	PINCTRL_CONF_DESC(2, REG_I2C_SDA_E2, I2C_SDA_E2_MASK),
+	PINCTRL_CONF_DESC(3, REG_I2C_SDA_E2, I2C_SCL_E2_MASK),
+	PINCTRL_CONF_DESC(4, REG_I2C_SDA_E2, SPI_CS0_E2_MASK),
+	PINCTRL_CONF_DESC(5, REG_I2C_SDA_E2, SPI_CLK_E2_MASK),
+	PINCTRL_CONF_DESC(6, REG_I2C_SDA_E2, SPI_MOSI_E2_MASK),
+	PINCTRL_CONF_DESC(7, REG_I2C_SDA_E2, SPI_MISO_E2_MASK),
+	PINCTRL_CONF_DESC(13, REG_GPIO_L_E2, BIT(0)),
+	PINCTRL_CONF_DESC(14, REG_GPIO_L_E2, BIT(1)),
+	PINCTRL_CONF_DESC(15, REG_GPIO_L_E2, BIT(2)),
+	PINCTRL_CONF_DESC(16, REG_GPIO_L_E2, BIT(3)),
+	PINCTRL_CONF_DESC(17, REG_GPIO_L_E2, BIT(4)),
+	PINCTRL_CONF_DESC(18, REG_GPIO_L_E2, BIT(5)),
+	PINCTRL_CONF_DESC(19, REG_GPIO_L_E2, BIT(6)),
+	PINCTRL_CONF_DESC(20, REG_GPIO_L_E2, BIT(7)),
+	PINCTRL_CONF_DESC(21, REG_GPIO_L_E2, BIT(8)),
+	PINCTRL_CONF_DESC(22, REG_GPIO_L_E2, BIT(9)),
+	PINCTRL_CONF_DESC(23, REG_GPIO_L_E2, BIT(10)),
+	PINCTRL_CONF_DESC(24, REG_GPIO_L_E2, BIT(11)),
+	PINCTRL_CONF_DESC(25, REG_GPIO_L_E2, BIT(12)),
+	PINCTRL_CONF_DESC(26, REG_GPIO_L_E2, BIT(13)),
+	PINCTRL_CONF_DESC(27, REG_GPIO_L_E2, BIT(14)),
+	PINCTRL_CONF_DESC(28, REG_GPIO_L_E2, BIT(15)),
+	PINCTRL_CONF_DESC(29, REG_GPIO_L_E2, BIT(16)),
+	PINCTRL_CONF_DESC(30, REG_GPIO_L_E2, BIT(17)),
+	PINCTRL_CONF_DESC(31, REG_GPIO_L_E2, BIT(18)),
+	PINCTRL_CONF_DESC(32, REG_GPIO_L_E2, BIT(19)),
+	PINCTRL_CONF_DESC(33, REG_GPIO_L_E2, BIT(20)),
+	PINCTRL_CONF_DESC(34, REG_GPIO_L_E2, BIT(21)),
+	PINCTRL_CONF_DESC(35, REG_GPIO_L_E2, BIT(22)),
+	PINCTRL_CONF_DESC(36, REG_GPIO_L_E2, BIT(23)),
+	PINCTRL_CONF_DESC(37, REG_GPIO_L_E2, BIT(24)),
+	PINCTRL_CONF_DESC(38, REG_GPIO_L_E2, BIT(25)),
+	PINCTRL_CONF_DESC(39, REG_GPIO_L_E2, BIT(26)),
+	PINCTRL_CONF_DESC(40, REG_GPIO_L_E2, BIT(27)),
+	PINCTRL_CONF_DESC(41, REG_GPIO_L_E2, BIT(28)),
+	PINCTRL_CONF_DESC(42, REG_GPIO_L_E2, BIT(29)),
+	PINCTRL_CONF_DESC(43, REG_GPIO_L_E2, BIT(30)),
+	PINCTRL_CONF_DESC(44, REG_GPIO_L_E2, BIT(31)),
+	PINCTRL_CONF_DESC(45, REG_GPIO_H_E2, BIT(0)),
+	PINCTRL_CONF_DESC(46, REG_GPIO_H_E2, BIT(1)),
+	PINCTRL_CONF_DESC(47, REG_GPIO_H_E2, BIT(2)),
+	PINCTRL_CONF_DESC(48, REG_GPIO_H_E2, BIT(3)),
+	PINCTRL_CONF_DESC(49, REG_GPIO_H_E2, BIT(4)),
+	PINCTRL_CONF_DESC(50, REG_GPIO_H_E2, BIT(5)),
+	PINCTRL_CONF_DESC(51, REG_GPIO_H_E2, BIT(6)),
+	PINCTRL_CONF_DESC(52, REG_GPIO_H_E2, BIT(7)),
+	PINCTRL_CONF_DESC(53, REG_GPIO_H_E2, BIT(8)),
+	PINCTRL_CONF_DESC(54, REG_GPIO_H_E2, BIT(9)),
+	PINCTRL_CONF_DESC(55, REG_GPIO_H_E2, BIT(10)),
+	PINCTRL_CONF_DESC(56, REG_GPIO_H_E2, BIT(11)),
+	PINCTRL_CONF_DESC(57, REG_GPIO_H_E2, BIT(12)),
+	PINCTRL_CONF_DESC(58, REG_GPIO_H_E2, BIT(13)),
+	PINCTRL_CONF_DESC(59, REG_GPIO_H_E2, BIT(14)),
+	PINCTRL_CONF_DESC(60, REG_I2C_SDA_E2, PCIE0_RESET_E2_MASK),
+	PINCTRL_CONF_DESC(61, REG_I2C_SDA_E2, PCIE1_RESET_E2_MASK),
+	PINCTRL_CONF_DESC(62, REG_I2C_SDA_E2, PCIE2_RESET_E2_MASK),
+};
+
+static const struct airoha_pinctrl_conf en7581_pinctrl_drive_e4_conf[] = {
+	PINCTRL_CONF_DESC(0, REG_I2C_SDA_E4, UART1_TXD_E4_MASK),
+	PINCTRL_CONF_DESC(1, REG_I2C_SDA_E4, UART1_RXD_E4_MASK),
+	PINCTRL_CONF_DESC(2, REG_I2C_SDA_E4, I2C_SDA_E4_MASK),
+	PINCTRL_CONF_DESC(3, REG_I2C_SDA_E4, I2C_SCL_E4_MASK),
+	PINCTRL_CONF_DESC(4, REG_I2C_SDA_E4, SPI_CS0_E4_MASK),
+	PINCTRL_CONF_DESC(5, REG_I2C_SDA_E4, SPI_CLK_E4_MASK),
+	PINCTRL_CONF_DESC(6, REG_I2C_SDA_E4, SPI_MOSI_E4_MASK),
+	PINCTRL_CONF_DESC(7, REG_I2C_SDA_E4, SPI_MISO_E4_MASK),
+	PINCTRL_CONF_DESC(13, REG_GPIO_L_E4, BIT(0)),
+	PINCTRL_CONF_DESC(14, REG_GPIO_L_E4, BIT(1)),
+	PINCTRL_CONF_DESC(15, REG_GPIO_L_E4, BIT(2)),
+	PINCTRL_CONF_DESC(16, REG_GPIO_L_E4, BIT(3)),
+	PINCTRL_CONF_DESC(17, REG_GPIO_L_E4, BIT(4)),
+	PINCTRL_CONF_DESC(18, REG_GPIO_L_E4, BIT(5)),
+	PINCTRL_CONF_DESC(19, REG_GPIO_L_E4, BIT(6)),
+	PINCTRL_CONF_DESC(20, REG_GPIO_L_E4, BIT(7)),
+	PINCTRL_CONF_DESC(21, REG_GPIO_L_E4, BIT(8)),
+	PINCTRL_CONF_DESC(22, REG_GPIO_L_E4, BIT(9)),
+	PINCTRL_CONF_DESC(23, REG_GPIO_L_E4, BIT(10)),
+	PINCTRL_CONF_DESC(24, REG_GPIO_L_E4, BIT(11)),
+	PINCTRL_CONF_DESC(25, REG_GPIO_L_E4, BIT(12)),
+	PINCTRL_CONF_DESC(26, REG_GPIO_L_E4, BIT(13)),
+	PINCTRL_CONF_DESC(27, REG_GPIO_L_E4, BIT(14)),
+	PINCTRL_CONF_DESC(28, REG_GPIO_L_E4, BIT(15)),
+	PINCTRL_CONF_DESC(29, REG_GPIO_L_E4, BIT(16)),
+	PINCTRL_CONF_DESC(30, REG_GPIO_L_E4, BIT(17)),
+	PINCTRL_CONF_DESC(31, REG_GPIO_L_E4, BIT(18)),
+	PINCTRL_CONF_DESC(32, REG_GPIO_L_E4, BIT(19)),
+	PINCTRL_CONF_DESC(33, REG_GPIO_L_E4, BIT(20)),
+	PINCTRL_CONF_DESC(34, REG_GPIO_L_E4, BIT(21)),
+	PINCTRL_CONF_DESC(35, REG_GPIO_L_E4, BIT(22)),
+	PINCTRL_CONF_DESC(36, REG_GPIO_L_E4, BIT(23)),
+	PINCTRL_CONF_DESC(37, REG_GPIO_L_E4, BIT(24)),
+	PINCTRL_CONF_DESC(38, REG_GPIO_L_E4, BIT(25)),
+	PINCTRL_CONF_DESC(39, REG_GPIO_L_E4, BIT(26)),
+	PINCTRL_CONF_DESC(40, REG_GPIO_L_E4, BIT(27)),
+	PINCTRL_CONF_DESC(41, REG_GPIO_L_E4, BIT(28)),
+	PINCTRL_CONF_DESC(42, REG_GPIO_L_E4, BIT(29)),
+	PINCTRL_CONF_DESC(43, REG_GPIO_L_E4, BIT(30)),
+	PINCTRL_CONF_DESC(44, REG_GPIO_L_E4, BIT(31)),
+	PINCTRL_CONF_DESC(45, REG_GPIO_H_E4, BIT(0)),
+	PINCTRL_CONF_DESC(46, REG_GPIO_H_E4, BIT(1)),
+	PINCTRL_CONF_DESC(47, REG_GPIO_H_E4, BIT(2)),
+	PINCTRL_CONF_DESC(48, REG_GPIO_H_E4, BIT(3)),
+	PINCTRL_CONF_DESC(49, REG_GPIO_H_E4, BIT(4)),
+	PINCTRL_CONF_DESC(50, REG_GPIO_H_E4, BIT(5)),
+	PINCTRL_CONF_DESC(51, REG_GPIO_H_E4, BIT(6)),
+	PINCTRL_CONF_DESC(52, REG_GPIO_H_E4, BIT(7)),
+	PINCTRL_CONF_DESC(53, REG_GPIO_H_E4, BIT(8)),
+	PINCTRL_CONF_DESC(54, REG_GPIO_H_E4, BIT(9)),
+	PINCTRL_CONF_DESC(55, REG_GPIO_H_E4, BIT(10)),
+	PINCTRL_CONF_DESC(56, REG_GPIO_H_E4, BIT(11)),
+	PINCTRL_CONF_DESC(57, REG_GPIO_H_E4, BIT(12)),
+	PINCTRL_CONF_DESC(58, REG_GPIO_H_E4, BIT(13)),
+	PINCTRL_CONF_DESC(59, REG_GPIO_H_E4, BIT(14)),
+	PINCTRL_CONF_DESC(60, REG_I2C_SDA_E4, PCIE0_RESET_E4_MASK),
+	PINCTRL_CONF_DESC(61, REG_I2C_SDA_E4, PCIE1_RESET_E4_MASK),
+	PINCTRL_CONF_DESC(62, REG_I2C_SDA_E4, PCIE2_RESET_E4_MASK),
+};
+
+static const struct airoha_pinctrl_conf en7581_pinctrl_pcie_rst_od_conf[] = {
+	PINCTRL_CONF_DESC(60, REG_PCIE_RESET_OD, PCIE0_RESET_OD_MASK),
+	PINCTRL_CONF_DESC(61, REG_PCIE_RESET_OD, PCIE1_RESET_OD_MASK),
+	PINCTRL_CONF_DESC(62, REG_PCIE_RESET_OD, PCIE2_RESET_OD_MASK),
+};
+
+static const struct airoha_pinctrl_match_data en7581_pinctrl_match_data = {
+	.pinctrl_name = KBUILD_MODNAME,
+	.pinctrl_owner = THIS_MODULE,
+	.pins = en7581_pinctrl_pins,
+	.num_pins = ARRAY_SIZE(en7581_pinctrl_pins),
+	.grps = en7581_pinctrl_groups,
+	.num_grps = ARRAY_SIZE(en7581_pinctrl_groups),
+	.funcs = en7581_pinctrl_funcs,
+	.num_funcs = ARRAY_SIZE(en7581_pinctrl_funcs),
+	.confs_info = {
+		[AIROHA_PINCTRL_CONFS_PULLUP] = {
+			.confs = en7581_pinctrl_pullup_conf,
+			.num_confs = ARRAY_SIZE(en7581_pinctrl_pullup_conf),
+		},
+		[AIROHA_PINCTRL_CONFS_PULLDOWN] = {
+			.confs = en7581_pinctrl_pulldown_conf,
+			.num_confs = ARRAY_SIZE(en7581_pinctrl_pulldown_conf),
+		},
+		[AIROHA_PINCTRL_CONFS_DRIVE_E2] = {
+			.confs = en7581_pinctrl_drive_e2_conf,
+			.num_confs = ARRAY_SIZE(en7581_pinctrl_drive_e2_conf),
+		},
+		[AIROHA_PINCTRL_CONFS_DRIVE_E4] = {
+			.confs = en7581_pinctrl_drive_e4_conf,
+			.num_confs = ARRAY_SIZE(en7581_pinctrl_drive_e4_conf),
+		},
+		[AIROHA_PINCTRL_CONFS_PCIE_RST_OD] = {
+			.confs = en7581_pinctrl_pcie_rst_od_conf,
+			.num_confs = ARRAY_SIZE(en7581_pinctrl_pcie_rst_od_conf),
+		},
+	},
+};
+
+static const struct of_device_id airoha_pinctrl_of_match[] = {
+	{ .compatible = "airoha,en7581-pinctrl", .data = &en7581_pinctrl_match_data },
+	{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, airoha_pinctrl_of_match);
+
+static struct platform_driver airoha_pinctrl_driver = {
+	.probe = airoha_pinctrl_probe,
+	.driver = {
+		.name = "pinctrl-airoha-an7581",
+		.of_match_table = airoha_pinctrl_of_match,
+	},
+};
+module_platform_driver(airoha_pinctrl_driver);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Lorenzo Bianconi <lorenzo@kernel.org>");
+MODULE_AUTHOR("Benjamin Larsson <benjamin.larsson@genexis.eu>");
+MODULE_AUTHOR("Markus Gothe <markus.gothe@genexis.eu>");
+MODULE_DESCRIPTION("Pinctrl driver for Airoha AN7581 SoC");
diff --git a/drivers/pinctrl/airoha/pinctrl-an7583.c b/drivers/pinctrl/airoha/pinctrl-an7583.c
new file mode 100644
index 0000000000000..b9d8dd94de5f0
--- /dev/null
+++ b/drivers/pinctrl/airoha/pinctrl-an7583.c
@@ -0,0 +1,1456 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Author: Lorenzo Bianconi <lorenzo@kernel.org>
+ * Author: Benjamin Larsson <benjamin.larsson@genexis.eu>
+ * Author: Markus Gothe <markus.gothe@genexis.eu>
+ */
+
+#include "airoha-common.h"
+
+/* MUX */
+#define REG_GPIO_2ND_I2C_MODE			0x0214
+#define GPIO_LAN3_LED1_MODE_MASK		BIT(10)
+#define GPIO_LAN3_LED0_MODE_MASK		BIT(9)
+#define GPIO_LAN2_LED1_MODE_MASK		BIT(8)
+#define GPIO_LAN2_LED0_MODE_MASK		BIT(7)
+#define GPIO_LAN1_LED1_MODE_MASK		BIT(6)
+#define GPIO_LAN1_LED0_MODE_MASK		BIT(5)
+#define GPIO_LAN0_LED1_MODE_MASK		BIT(4)
+#define GPIO_LAN0_LED0_MODE_MASK		BIT(3)
+#define PON_TOD_1PPS_MODE_MASK			BIT(2)
+#define GSW_TOD_1PPS_MODE_MASK			BIT(1)
+
+#define REG_GPIO_SPI_CS1_MODE			0x0218
+#define GPIO_MDC_IO_MASTER_MODE_MASK		BIT(22)
+#define GPIO_PCM_SPI_CS4_MODE_MASK		BIT(21)
+#define GPIO_PCM_SPI_CS3_MODE_MASK		BIT(20)
+#define AN7583_GPIO_PCM_SPI_CS2_MODE_MASK	BIT(18)
+#define GPIO_PCM_SPI_CS1_MODE_MASK		BIT(17)
+#define GPIO_PCM_SPI_MODE_MASK			BIT(16)
+#define GPIO_PCM2_MODE_MASK			BIT(13)
+#define GPIO_PCM1_MODE_MASK			BIT(12)
+#define GPIO_PCM_INT_MODE_MASK			BIT(9)
+#define GPIO_PCM_RESET_MODE_MASK		BIT(8)
+#define GPIO_SPI_QUAD_MODE_MASK			BIT(4)
+#define GPIO_SPI_CS4_MODE_MASK			BIT(3)
+#define GPIO_SPI_CS3_MODE_MASK			BIT(2)
+#define GPIO_SPI_CS2_MODE_MASK			BIT(1)
+#define GPIO_SPI_CS1_MODE_MASK			BIT(0)
+
+#define REG_GPIO_PON_MODE			0x021c
+#define AN7583_MDIO_0_GPIO_MODE_MASK		BIT(26)
+#define AN7583_MDC_0_GPIO_MODE_MASK		BIT(25)
+#define AN7583_UART_RXD_GPIO_MODE_MASK		BIT(24)
+#define AN7583_UART_TXD_GPIO_MODE_MASK		BIT(23)
+#define AN7583_SPI_MISO_GPIO_MODE_MASK		BIT(22)
+#define AN7583_SPI_MOSI_GPIO_MODE_MASK		BIT(21)
+#define AN7583_SPI_CS_GPIO_MODE_MASK		BIT(20)
+#define AN7583_SPI_CLK_GPIO_MODE_MASK		BIT(19)
+#define AN7583_I2C1_SDA_GPIO_MODE_MASK		BIT(18)
+#define AN7583_I2C1_SCL_GPIO_MODE_MASK		BIT(17)
+#define AN7583_I2C0_SDA_GPIO_MODE_MASK		BIT(16)
+#define AN7583_I2C0_SCL_GPIO_MODE_MASK		BIT(15)
+#define GPIO_PARALLEL_NAND_MODE_MASK		BIT(14)
+#define GPIO_SGMII_MDIO_MODE_MASK		BIT(13)
+#define SIPO_RCLK_MODE_MASK			BIT(11)
+#define GPIO_PCIE_RESET1_MASK			BIT(10)
+#define GPIO_PCIE_RESET0_MASK			BIT(9)
+#define GPIO_UART5_MODE_MASK			BIT(8)
+#define GPIO_UART4_MODE_MASK			BIT(7)
+#define GPIO_HSUART_CTS_RTS_MODE_MASK		BIT(6)
+#define GPIO_HSUART_MODE_MASK			BIT(5)
+#define GPIO_UART2_CTS_RTS_MODE_MASK		BIT(4)
+#define GPIO_UART2_MODE_MASK			BIT(3)
+#define GPIO_SIPO_MODE_MASK			BIT(2)
+#define GPIO_EMMC_MODE_MASK			BIT(1)
+#define GPIO_PON_MODE_MASK			BIT(0)
+
+#define REG_NPU_UART_EN				0x0224
+#define JTAG_UDI_EN_MASK			BIT(4)
+#define JTAG_DFD_EN_MASK			BIT(3)
+
+#define REG_FORCE_GPIO_EN			0x0228
+#define FORCE_GPIO_EN(n)			BIT(n)
+
+/* LED MAP */
+#define REG_LAN_LED0_MAPPING			0x027c
+#define REG_LAN_LED1_MAPPING			0x0280
+
+#define LAN4_LED_MAPPING_MASK			GENMASK(18, 16)
+#define LAN4_PHY_LED_MAP(_n)			FIELD_PREP_CONST(LAN4_LED_MAPPING_MASK, (_n))
+
+#define LAN3_LED_MAPPING_MASK			GENMASK(14, 12)
+#define LAN3_PHY_LED_MAP(_n)			FIELD_PREP_CONST(LAN3_LED_MAPPING_MASK, (_n))
+
+#define LAN2_LED_MAPPING_MASK			GENMASK(10, 8)
+#define LAN2_PHY_LED_MAP(_n)			FIELD_PREP_CONST(LAN2_LED_MAPPING_MASK, (_n))
+
+#define LAN1_LED_MAPPING_MASK			GENMASK(6, 4)
+#define LAN1_PHY_LED_MAP(_n)			FIELD_PREP_CONST(LAN1_LED_MAPPING_MASK, (_n))
+
+#define LAN0_LED_MAPPING_MASK			GENMASK(2, 0)
+#define LAN0_PHY_LED_MAP(_n)			FIELD_PREP_CONST(LAN0_LED_MAPPING_MASK, (_n))
+
+/* CONF */
+#define REG_I2C_SDA_E2				0x001c
+#define AN7583_I2C1_SCL_E2_MASK			BIT(16)
+#define AN7583_I2C1_SDA_E2_MASK			BIT(15)
+#define SPI_MISO_E2_MASK			BIT(14)
+#define SPI_MOSI_E2_MASK			BIT(13)
+#define SPI_CLK_E2_MASK				BIT(12)
+#define SPI_CS0_E2_MASK				BIT(11)
+#define PCIE1_RESET_E2_MASK			BIT(9)
+#define PCIE0_RESET_E2_MASK			BIT(8)
+#define AN7583_MDIO_0_E2_MASK			BIT(5)
+#define AN7583_MDC_0_E2_MASK			BIT(4)
+#define UART1_RXD_E2_MASK			BIT(3)
+#define UART1_TXD_E2_MASK			BIT(2)
+#define I2C_SCL_E2_MASK				BIT(1)
+#define I2C_SDA_E2_MASK				BIT(0)
+
+#define REG_I2C_SDA_E4				0x0020
+#define AN7583_I2C1_SCL_E4_MASK			BIT(16)
+#define AN7583_I2C1_SDA_E4_MASK			BIT(15)
+#define SPI_MISO_E4_MASK			BIT(14)
+#define SPI_MOSI_E4_MASK			BIT(13)
+#define SPI_CLK_E4_MASK				BIT(12)
+#define SPI_CS0_E4_MASK				BIT(11)
+#define PCIE1_RESET_E4_MASK			BIT(9)
+#define PCIE0_RESET_E4_MASK			BIT(8)
+#define AN7583_MDIO_0_E4_MASK			BIT(5)
+#define AN7583_MDC_0_E4_MASK			BIT(4)
+#define UART1_RXD_E4_MASK			BIT(3)
+#define UART1_TXD_E4_MASK			BIT(2)
+#define I2C_SCL_E4_MASK				BIT(1)
+#define I2C_SDA_E4_MASK				BIT(0)
+
+#define REG_GPIO_L_E2				0x0024
+#define REG_GPIO_L_E4				0x0028
+#define REG_GPIO_H_E2				0x002c
+#define REG_GPIO_H_E4				0x0030
+
+#define REG_I2C_SDA_PU				0x0044
+#define AN7583_I2C1_SCL_PU_MASK			BIT(16)
+#define AN7583_I2C1_SDA_PU_MASK			BIT(15)
+#define SPI_MISO_PU_MASK			BIT(14)
+#define SPI_MOSI_PU_MASK			BIT(13)
+#define SPI_CLK_PU_MASK				BIT(12)
+#define SPI_CS0_PU_MASK				BIT(11)
+#define PCIE1_RESET_PU_MASK			BIT(9)
+#define PCIE0_RESET_PU_MASK			BIT(8)
+#define AN7583_MDIO_0_PU_MASK			BIT(5)
+#define AN7583_MDC_0_PU_MASK			BIT(4)
+#define UART1_RXD_PU_MASK			BIT(3)
+#define UART1_TXD_PU_MASK			BIT(2)
+#define I2C_SCL_PU_MASK				BIT(1)
+#define I2C_SDA_PU_MASK				BIT(0)
+
+#define REG_I2C_SDA_PD				0x0048
+#define AN7583_I2C1_SCL_PD_MASK			BIT(16)
+#define AN7583_I2C1_SDA_PD_MASK			BIT(15)
+#define SPI_MISO_PD_MASK			BIT(14)
+#define SPI_MOSI_PD_MASK			BIT(13)
+#define SPI_CLK_PD_MASK				BIT(12)
+#define SPI_CS0_PD_MASK				BIT(11)
+#define PCIE1_RESET_PD_MASK			BIT(9)
+#define PCIE0_RESET_PD_MASK			BIT(8)
+#define AN7583_MDIO_0_PD_MASK			BIT(5)
+#define AN7583_MDC_0_PD_MASK			BIT(4)
+#define UART1_RXD_PD_MASK			BIT(3)
+#define UART1_TXD_PD_MASK			BIT(2)
+#define I2C_SCL_PD_MASK				BIT(1)
+#define I2C_SDA_PD_MASK				BIT(0)
+
+#define REG_GPIO_L_PU				0x004c
+#define REG_GPIO_L_PD				0x0050
+#define REG_GPIO_H_PU				0x0054
+#define REG_GPIO_H_PD				0x0058
+
+#define REG_PCIE_RESET_OD			0x018c
+#define PCIE1_RESET_OD_MASK			BIT(1)
+#define PCIE0_RESET_OD_MASK			BIT(0)
+
+/* PWM MODE CONF */
+#define REG_GPIO_FLASH_MODE_CFG			0x0034
+#define GPIO15_FLASH_MODE_CFG			BIT(15)
+#define GPIO14_FLASH_MODE_CFG			BIT(14)
+#define GPIO13_FLASH_MODE_CFG			BIT(13)
+#define GPIO12_FLASH_MODE_CFG			BIT(12)
+#define GPIO11_FLASH_MODE_CFG			BIT(11)
+#define GPIO10_FLASH_MODE_CFG			BIT(10)
+#define GPIO9_FLASH_MODE_CFG			BIT(9)
+#define GPIO8_FLASH_MODE_CFG			BIT(8)
+#define GPIO7_FLASH_MODE_CFG			BIT(7)
+#define GPIO6_FLASH_MODE_CFG			BIT(6)
+#define GPIO5_FLASH_MODE_CFG			BIT(5)
+#define GPIO4_FLASH_MODE_CFG			BIT(4)
+#define GPIO3_FLASH_MODE_CFG			BIT(3)
+#define GPIO2_FLASH_MODE_CFG			BIT(2)
+#define GPIO1_FLASH_MODE_CFG			BIT(1)
+#define GPIO0_FLASH_MODE_CFG			BIT(0)
+
+/* PWM MODE CONF EXT */
+#define REG_GPIO_FLASH_MODE_CFG_EXT		0x0068
+#define GPIO51_FLASH_MODE_CFG			BIT(31)
+#define GPIO50_FLASH_MODE_CFG			BIT(30)
+#define GPIO49_FLASH_MODE_CFG			BIT(29)
+#define GPIO48_FLASH_MODE_CFG			BIT(28)
+#define GPIO47_FLASH_MODE_CFG			BIT(27)
+#define GPIO46_FLASH_MODE_CFG			BIT(26)
+#define GPIO45_FLASH_MODE_CFG			BIT(25)
+#define GPIO44_FLASH_MODE_CFG			BIT(24)
+#define GPIO43_FLASH_MODE_CFG			BIT(23)
+#define GPIO42_FLASH_MODE_CFG			BIT(22)
+#define GPIO41_FLASH_MODE_CFG			BIT(21)
+#define GPIO40_FLASH_MODE_CFG			BIT(20)
+#define GPIO39_FLASH_MODE_CFG			BIT(19)
+#define GPIO38_FLASH_MODE_CFG			BIT(18)
+#define GPIO37_FLASH_MODE_CFG			BIT(17)
+#define GPIO36_FLASH_MODE_CFG			BIT(16)
+#define GPIO31_FLASH_MODE_CFG			BIT(15)
+#define GPIO30_FLASH_MODE_CFG			BIT(14)
+#define GPIO29_FLASH_MODE_CFG			BIT(13)
+#define GPIO28_FLASH_MODE_CFG			BIT(12)
+#define GPIO27_FLASH_MODE_CFG			BIT(11)
+#define GPIO26_FLASH_MODE_CFG			BIT(10)
+#define GPIO25_FLASH_MODE_CFG			BIT(9)
+#define GPIO24_FLASH_MODE_CFG			BIT(8)
+#define GPIO23_FLASH_MODE_CFG			BIT(7)
+#define GPIO22_FLASH_MODE_CFG			BIT(6)
+#define GPIO21_FLASH_MODE_CFG			BIT(5)
+#define GPIO20_FLASH_MODE_CFG			BIT(4)
+#define GPIO19_FLASH_MODE_CFG			BIT(3)
+#define GPIO18_FLASH_MODE_CFG			BIT(2)
+#define GPIO17_FLASH_MODE_CFG			BIT(1)
+#define GPIO16_FLASH_MODE_CFG			BIT(0)
+
+#define AIROHA_PINCTRL_GPIO(gpio, mux_val)			\
+	{							\
+		.name = (gpio),					\
+		.regmap[0] = {					\
+			AIROHA_FUNC_MUX,			\
+			REG_GPIO_PON_MODE,			\
+			(mux_val),				\
+			(mux_val)				\
+		},						\
+		.regmap_size = 1,				\
+	}
+
+#define AIROHA_PINCTRL_GPIO_EXT(gpio, mux_val, smux_val)	\
+	{							\
+		.name = (gpio),					\
+		.regmap[0] = {					\
+			AIROHA_FUNC_PWM_EXT_MUX,		\
+			REG_GPIO_FLASH_MODE_CFG_EXT,		\
+			(mux_val),				\
+			0					\
+		},						\
+		.regmap[1] = {					\
+			AIROHA_FUNC_MUX,			\
+			REG_GPIO_PON_MODE,			\
+			(smux_val),				\
+			(smux_val)				\
+		},						\
+		.regmap_size = 2,				\
+	}
+
+/* PWM */
+#define AIROHA_PINCTRL_PWM(gpio, mux_val)			\
+	{							\
+		.name = (gpio),					\
+		.regmap[0] = {					\
+			AIROHA_FUNC_PWM_MUX,			\
+			REG_GPIO_FLASH_MODE_CFG,		\
+			(mux_val),				\
+			(mux_val)				\
+		},						\
+		.regmap_size = 1,				\
+	}
+
+#define AIROHA_PINCTRL_PWM_EXT(gpio, mux_val)			\
+	{							\
+		.name = (gpio),					\
+		.regmap[0] = {					\
+			AIROHA_FUNC_PWM_EXT_MUX,		\
+			REG_GPIO_FLASH_MODE_CFG_EXT,		\
+			(mux_val),				\
+			(mux_val)				\
+		},						\
+		.regmap_size = 1,				\
+	}
+
+#define AIROHA_PINCTRL_PWM_EXT_SEC(gpio, mux_val, smux_val)	\
+	{							\
+		.name = (gpio),					\
+		.regmap[0] = {					\
+			AIROHA_FUNC_PWM_EXT_MUX,		\
+			REG_GPIO_FLASH_MODE_CFG_EXT,		\
+			(mux_val),				\
+			(mux_val)				\
+		},						\
+		.regmap[1] = {					\
+			AIROHA_FUNC_MUX,			\
+			REG_GPIO_PON_MODE,			\
+			(smux_val),				\
+			(smux_val)				\
+		},						\
+		.regmap_size = 2,				\
+	}
+
+#define AIROHA_PINCTRL_PHY_LED0(gpio, mux_val, map_mask, map_val)	\
+	{								\
+		.name = (gpio),						\
+		.regmap[0] = {						\
+			AIROHA_FUNC_MUX,				\
+			REG_GPIO_2ND_I2C_MODE,				\
+			(mux_val),					\
+			(mux_val),					\
+		},							\
+		.regmap[1] = {						\
+			AIROHA_FUNC_MUX,				\
+			REG_LAN_LED0_MAPPING,				\
+			(map_mask),					\
+			(map_val),					\
+		},							\
+		.regmap_size = 2,					\
+	}
+
+#define AIROHA_PINCTRL_PHY_LED1(gpio, mux_val, map_mask, map_val)	\
+	{								\
+		.name = (gpio),						\
+		.regmap[0] = {						\
+			AIROHA_FUNC_MUX,				\
+			REG_GPIO_2ND_I2C_MODE,				\
+			(mux_val),					\
+			(mux_val),					\
+		},							\
+		.regmap[1] = {						\
+			AIROHA_FUNC_MUX,				\
+			REG_LAN_LED1_MAPPING,				\
+			(map_mask),					\
+			(map_val),					\
+		},							\
+		.regmap_size = 2,					\
+	}
+
+static struct pinctrl_pin_desc an7583_pinctrl_pins[] = {
+	PINCTRL_PIN(2, "gpio0"),
+	PINCTRL_PIN(3, "gpio1"),
+	PINCTRL_PIN(4, "gpio2"),
+	PINCTRL_PIN(5, "gpio3"),
+	PINCTRL_PIN(6, "gpio4"),
+	PINCTRL_PIN(7, "gpio5"),
+	PINCTRL_PIN(8, "gpio6"),
+	PINCTRL_PIN(9, "gpio7"),
+	PINCTRL_PIN(10, "gpio8"),
+	PINCTRL_PIN(11, "gpio9"),
+	PINCTRL_PIN(12, "gpio10"),
+	PINCTRL_PIN(13, "gpio11"),
+	PINCTRL_PIN(14, "gpio12"),
+	PINCTRL_PIN(15, "gpio13"),
+	PINCTRL_PIN(16, "gpio14"),
+	PINCTRL_PIN(17, "gpio15"),
+	PINCTRL_PIN(18, "gpio16"),
+	PINCTRL_PIN(19, "gpio17"),
+	PINCTRL_PIN(20, "gpio18"),
+	PINCTRL_PIN(21, "gpio19"),
+	PINCTRL_PIN(22, "gpio20"),
+	PINCTRL_PIN(23, "gpio21"),
+	PINCTRL_PIN(24, "gpio22"),
+	PINCTRL_PIN(25, "gpio23"),
+	PINCTRL_PIN(26, "gpio24"),
+	PINCTRL_PIN(27, "gpio25"),
+	PINCTRL_PIN(28, "gpio26"),
+	PINCTRL_PIN(29, "gpio27"),
+	PINCTRL_PIN(30, "gpio28"),
+	PINCTRL_PIN(31, "gpio29"),
+	PINCTRL_PIN(32, "gpio30"),
+	PINCTRL_PIN(33, "gpio31"),
+	PINCTRL_PIN(34, "gpio32"),
+	PINCTRL_PIN(35, "gpio33"),
+	PINCTRL_PIN(36, "gpio34"),
+	PINCTRL_PIN(37, "gpio35"),
+	PINCTRL_PIN(38, "gpio36"),
+	PINCTRL_PIN(39, "gpio37"),
+	PINCTRL_PIN(40, "gpio38"),
+	PINCTRL_PIN(41, "i2c0_scl"),
+	PINCTRL_PIN(42, "i2c0_sda"),
+	PINCTRL_PIN(43, "i2c1_scl"),
+	PINCTRL_PIN(44, "i2c1_sda"),
+	PINCTRL_PIN(45, "spi_clk"),
+	PINCTRL_PIN(46, "spi_cs"),
+	PINCTRL_PIN(47, "spi_mosi"),
+	PINCTRL_PIN(48, "spi_miso"),
+	PINCTRL_PIN(49, "uart_txd"),
+	PINCTRL_PIN(50, "uart_rxd"),
+	PINCTRL_PIN(51, "pcie_reset0"),
+	PINCTRL_PIN(52, "pcie_reset1"),
+	PINCTRL_PIN(53, "mdc_0"),
+	PINCTRL_PIN(54, "mdio_0"),
+};
+
+static const int an7583_pon_pins[] = { 15, 16, 17, 18, 19, 20 };
+static const int an7583_pon_tod_1pps_pins[] = { 32 };
+static const int an7583_gsw_tod_1pps_pins[] = { 32 };
+static const int an7583_sipo_pins[] = { 34, 35 };
+static const int an7583_sipo_rclk_pins[] = { 34, 35, 33 };
+static const int an7583_mdio_pins[] = { 43, 44 };
+static const int an7583_uart2_pins[] = { 34, 35 };
+static const int an7583_uart2_cts_rts_pins[] = { 32, 33 };
+static const int an7583_hsuart_pins[] = { 30, 31 };
+static const int an7583_hsuart_cts_rts_pins[] = { 28, 29 };
+static const int an7583_npu_uart_pins[] = { 7, 8 };
+static const int an7583_uart4_pins[] = { 7, 8 };
+static const int an7583_uart5_pins[] = { 23, 24 };
+static const int an7583_i2c0_pins[] = { 41, 42 };
+static const int an7583_i2c1_pins[] = { 43, 44 };
+static const int an7583_jtag_udi_pins[] = { 23, 24, 22, 25, 26 };
+static const int an7583_jtag_dfd_pins[] = { 23, 24, 22, 25, 26 };
+static const int an7583_pcm1_pins[] = { 10, 11, 12, 13, 14 };
+static const int an7583_pcm2_pins[] = { 28, 29, 30, 31, 24 };
+static const int an7583_spi_pins[] = { 28, 29, 30, 31 };
+static const int an7583_spi_quad_pins[] = { 25, 26 };
+static const int an7583_spi_cs1_pins[] = { 27 };
+static const int an7583_pcm_spi_pins[] = { 28, 29, 30, 31, 10, 11, 12, 13 };
+static const int an7583_pcm_spi_rst_pins[] = { 14 };
+static const int an7583_pcm_spi_cs1_pins[] = { 24 };
+static const int an7583_emmc_pins[] = {
+	7, 8, 9, 22, 23, 24, 25, 26, 45, 46, 47
+};
+static const int an7583_pnand_pins[] = {
+	7, 8, 9, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 45, 46, 47, 48
+};
+static const int an7583_gpio0_pins[] = { 2 };
+static const int an7583_gpio1_pins[] = { 3 };
+static const int an7583_gpio2_pins[] = { 4 };
+static const int an7583_gpio3_pins[] = { 5 };
+static const int an7583_gpio4_pins[] = { 6 };
+static const int an7583_gpio5_pins[] = { 7 };
+static const int an7583_gpio6_pins[] = { 8 };
+static const int an7583_gpio7_pins[] = { 9 };
+static const int an7583_gpio8_pins[] = { 10 };
+static const int an7583_gpio9_pins[] = { 11 };
+static const int an7583_gpio10_pins[] = { 12 };
+static const int an7583_gpio11_pins[] = { 13 };
+static const int an7583_gpio12_pins[] = { 14 };
+static const int an7583_gpio13_pins[] = { 15 };
+static const int an7583_gpio14_pins[] = { 16 };
+static const int an7583_gpio15_pins[] = { 17 };
+static const int an7583_gpio16_pins[] = { 18 };
+static const int an7583_gpio17_pins[] = { 19 };
+static const int an7583_gpio18_pins[] = { 20 };
+static const int an7583_gpio19_pins[] = { 21 };
+static const int an7583_gpio20_pins[] = { 22 };
+static const int an7583_gpio21_pins[] = { 23 };
+static const int an7583_gpio22_pins[] = { 24 };
+static const int an7583_gpio23_pins[] = { 25 };
+static const int an7583_gpio24_pins[] = { 26 };
+static const int an7583_gpio25_pins[] = { 27 };
+static const int an7583_gpio26_pins[] = { 28 };
+static const int an7583_gpio27_pins[] = { 29 };
+static const int an7583_gpio28_pins[] = { 30 };
+static const int an7583_gpio29_pins[] = { 31 };
+static const int an7583_gpio30_pins[] = { 32 };
+static const int an7583_gpio31_pins[] = { 33 };
+static const int an7583_gpio32_pins[] = { 34 };
+static const int an7583_gpio33_pins[] = { 35 };
+static const int an7583_gpio34_pins[] = { 36 };
+static const int an7583_gpio35_pins[] = { 37 };
+static const int an7583_gpio36_pins[] = { 38 };
+static const int an7583_gpio37_pins[] = { 39 };
+static const int an7583_gpio38_pins[] = { 40 };
+static const int an7583_gpio39_pins[] = { 41 };
+static const int an7583_gpio40_pins[] = { 42 };
+static const int an7583_gpio41_pins[] = { 43 };
+static const int an7583_gpio42_pins[] = { 44 };
+static const int an7583_gpio43_pins[] = { 45 };
+static const int an7583_gpio44_pins[] = { 46 };
+static const int an7583_gpio45_pins[] = { 47 };
+static const int an7583_gpio46_pins[] = { 48 };
+static const int an7583_gpio47_pins[] = { 49 };
+static const int an7583_gpio48_pins[] = { 50 };
+static const int an7583_gpio49_pins[] = { 51 };
+static const int an7583_gpio50_pins[] = { 52 };
+static const int an7583_gpio51_pins[] = { 53 };
+static const int an7583_gpio52_pins[] = { 54 };
+static const int an7583_pcie_reset0_pins[] = { 51 };
+static const int an7583_pcie_reset1_pins[] = { 52 };
+
+static const struct pingroup an7583_pinctrl_groups[] = {
+	PINCTRL_PIN_GROUP("pon", an7583_pon),
+	PINCTRL_PIN_GROUP("pon_tod_1pps", an7583_pon_tod_1pps),
+	PINCTRL_PIN_GROUP("gsw_tod_1pps", an7583_gsw_tod_1pps),
+	PINCTRL_PIN_GROUP("sipo", an7583_sipo),
+	PINCTRL_PIN_GROUP("sipo_rclk", an7583_sipo_rclk),
+	PINCTRL_PIN_GROUP("mdio", an7583_mdio),
+	PINCTRL_PIN_GROUP("uart2", an7583_uart2),
+	PINCTRL_PIN_GROUP("uart2_cts_rts", an7583_uart2_cts_rts),
+	PINCTRL_PIN_GROUP("hsuart", an7583_hsuart),
+	PINCTRL_PIN_GROUP("hsuart_cts_rts", an7583_hsuart_cts_rts),
+	PINCTRL_PIN_GROUP("npu_uart", an7583_npu_uart),
+	PINCTRL_PIN_GROUP("uart4", an7583_uart4),
+	PINCTRL_PIN_GROUP("uart5", an7583_uart5),
+	PINCTRL_PIN_GROUP("i2c0", an7583_i2c0),
+	PINCTRL_PIN_GROUP("i2c1", an7583_i2c1),
+	PINCTRL_PIN_GROUP("jtag_udi", an7583_jtag_udi),
+	PINCTRL_PIN_GROUP("jtag_dfd", an7583_jtag_dfd),
+	PINCTRL_PIN_GROUP("pcm1", an7583_pcm1),
+	PINCTRL_PIN_GROUP("pcm2", an7583_pcm2),
+	PINCTRL_PIN_GROUP("spi", an7583_spi),
+	PINCTRL_PIN_GROUP("spi_quad", an7583_spi_quad),
+	PINCTRL_PIN_GROUP("spi_cs1", an7583_spi_cs1),
+	PINCTRL_PIN_GROUP("pcm_spi", an7583_pcm_spi),
+	PINCTRL_PIN_GROUP("pcm_spi_rst", an7583_pcm_spi_rst),
+	PINCTRL_PIN_GROUP("pcm_spi_cs1", an7583_pcm_spi_cs1),
+	PINCTRL_PIN_GROUP("emmc", an7583_emmc),
+	PINCTRL_PIN_GROUP("pnand", an7583_pnand),
+	PINCTRL_PIN_GROUP("gpio0", an7583_gpio0),
+	PINCTRL_PIN_GROUP("gpio1", an7583_gpio1),
+	PINCTRL_PIN_GROUP("gpio2", an7583_gpio2),
+	PINCTRL_PIN_GROUP("gpio3", an7583_gpio3),
+	PINCTRL_PIN_GROUP("gpio4", an7583_gpio4),
+	PINCTRL_PIN_GROUP("gpio5", an7583_gpio5),
+	PINCTRL_PIN_GROUP("gpio6", an7583_gpio6),
+	PINCTRL_PIN_GROUP("gpio7", an7583_gpio7),
+	PINCTRL_PIN_GROUP("gpio8", an7583_gpio8),
+	PINCTRL_PIN_GROUP("gpio9", an7583_gpio9),
+	PINCTRL_PIN_GROUP("gpio10", an7583_gpio10),
+	PINCTRL_PIN_GROUP("gpio11", an7583_gpio11),
+	PINCTRL_PIN_GROUP("gpio12", an7583_gpio12),
+	PINCTRL_PIN_GROUP("gpio13", an7583_gpio13),
+	PINCTRL_PIN_GROUP("gpio14", an7583_gpio14),
+	PINCTRL_PIN_GROUP("gpio15", an7583_gpio15),
+	PINCTRL_PIN_GROUP("gpio16", an7583_gpio16),
+	PINCTRL_PIN_GROUP("gpio17", an7583_gpio17),
+	PINCTRL_PIN_GROUP("gpio18", an7583_gpio18),
+	PINCTRL_PIN_GROUP("gpio19", an7583_gpio19),
+	PINCTRL_PIN_GROUP("gpio20", an7583_gpio20),
+	PINCTRL_PIN_GROUP("gpio21", an7583_gpio21),
+	PINCTRL_PIN_GROUP("gpio22", an7583_gpio22),
+	PINCTRL_PIN_GROUP("gpio23", an7583_gpio23),
+	PINCTRL_PIN_GROUP("gpio24", an7583_gpio24),
+	PINCTRL_PIN_GROUP("gpio25", an7583_gpio25),
+	PINCTRL_PIN_GROUP("gpio26", an7583_gpio26),
+	PINCTRL_PIN_GROUP("gpio27", an7583_gpio27),
+	PINCTRL_PIN_GROUP("gpio28", an7583_gpio28),
+	PINCTRL_PIN_GROUP("gpio29", an7583_gpio29),
+	PINCTRL_PIN_GROUP("gpio30", an7583_gpio30),
+	PINCTRL_PIN_GROUP("gpio31", an7583_gpio31),
+	PINCTRL_PIN_GROUP("gpio32", an7583_gpio32),
+	PINCTRL_PIN_GROUP("gpio33", an7583_gpio33),
+	PINCTRL_PIN_GROUP("gpio34", an7583_gpio34),
+	PINCTRL_PIN_GROUP("gpio35", an7583_gpio35),
+	PINCTRL_PIN_GROUP("gpio36", an7583_gpio36),
+	PINCTRL_PIN_GROUP("gpio37", an7583_gpio37),
+	PINCTRL_PIN_GROUP("gpio38", an7583_gpio38),
+	PINCTRL_PIN_GROUP("gpio39", an7583_gpio39),
+	PINCTRL_PIN_GROUP("gpio40", an7583_gpio40),
+	PINCTRL_PIN_GROUP("gpio41", an7583_gpio41),
+	PINCTRL_PIN_GROUP("gpio42", an7583_gpio42),
+	PINCTRL_PIN_GROUP("gpio43", an7583_gpio43),
+	PINCTRL_PIN_GROUP("gpio44", an7583_gpio44),
+	PINCTRL_PIN_GROUP("gpio45", an7583_gpio45),
+	PINCTRL_PIN_GROUP("gpio46", an7583_gpio46),
+	PINCTRL_PIN_GROUP("gpio47", an7583_gpio47),
+	PINCTRL_PIN_GROUP("gpio48", an7583_gpio48),
+	PINCTRL_PIN_GROUP("gpio49", an7583_gpio49),
+	PINCTRL_PIN_GROUP("gpio50", an7583_gpio50),
+	PINCTRL_PIN_GROUP("gpio51", an7583_gpio51),
+	PINCTRL_PIN_GROUP("gpio52", an7583_gpio52),
+	PINCTRL_PIN_GROUP("pcie_reset0", an7583_pcie_reset0),
+	PINCTRL_PIN_GROUP("pcie_reset1", an7583_pcie_reset1),
+};
+
+static const char *const pon_groups[] = { "pon" };
+static const char *const tod_1pps_groups[] = {
+	"pon_tod_1pps", "gsw_tod_1pps"
+};
+static const char *const sipo_groups[] = { "sipo", "sipo_rclk" };
+static const char *const an7583_mdio_groups[] = { "mdio" };
+static const char *const uart_groups[] = {
+	"uart2", "uart2_cts_rts", "hsuart", "hsuart_cts_rts",
+	"uart4", "uart5"
+};
+static const char *const jtag_groups[] = { "jtag_udi", "jtag_dfd" };
+static const char *const pcm_groups[] = { "pcm1", "pcm2" };
+static const char *const spi_groups[] = { "spi_quad", "spi_cs1" };
+static const char *const an7583_pcm_spi_groups[] = {
+	"pcm_spi", "pcm_spi_rst", "pcm_spi_cs1"
+};
+static const char *const emmc_groups[] = { "emmc" };
+static const char *const pnand_groups[] = { "pnand" };
+static const char *const an7583_gpio_groups[] = {
+	"gpio39", "gpio40", "gpio41", "gpio42", "gpio43",
+	"gpio44", "gpio45", "gpio46", "gpio47", "gpio48",
+	"gpio49", "gpio50", "gpio51", "gpio52"
+};
+static const char *const an7583_pcie_reset_groups[] = {
+	"pcie_reset0", "pcie_reset1"
+};
+static const char *const an7583_pwm_groups[] = {
+	"gpio0",  "gpio1",  "gpio2",  "gpio3",  "gpio4",  "gpio5",
+	"gpio6",  "gpio7",  "gpio8",  "gpio9",  "gpio10", "gpio11",
+	"gpio12", "gpio13", "gpio14", "gpio15", "gpio16", "gpio17",
+	"gpio18", "gpio19", "gpio20", "gpio21", "gpio22", "gpio23",
+	"gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29",
+	"gpio30", "gpio31", "gpio36", "gpio37", "gpio38", "gpio39",
+	"gpio40", "gpio41", "gpio42", "gpio43", "gpio44", "gpio45",
+	"gpio46", "gpio47", "gpio48", "gpio49", "gpio50", "gpio51"
+};
+static const char *const an7583_phy1_led0_groups[] = {
+	"gpio1", "gpio2", "gpio3", "gpio4"
+};
+static const char *const an7583_phy2_led0_groups[] = {
+	"gpio1", "gpio2", "gpio3", "gpio4"
+};
+static const char *const an7583_phy3_led0_groups[] = {
+	"gpio1", "gpio2", "gpio3", "gpio4"
+};
+static const char *const an7583_phy4_led0_groups[] = {
+	"gpio1", "gpio2", "gpio3", "gpio4"
+};
+static const char *const an7583_phy1_led1_groups[] = {
+	"gpio8", "gpio9", "gpio10", "gpio11"
+};
+static const char *const an7583_phy2_led1_groups[] = {
+	"gpio8", "gpio9", "gpio10", "gpio11"
+};
+static const char *const an7583_phy3_led1_groups[] = {
+	"gpio8", "gpio9", "gpio10", "gpio11"
+};
+static const char *const an7583_phy4_led1_groups[] = {
+	"gpio8", "gpio9", "gpio10", "gpio11"
+};
+
+static const struct airoha_pinctrl_func_group pon_func_group[] = {
+	{
+		.name = "pon",
+		.regmap[0] = {
+			AIROHA_FUNC_MUX,
+			REG_GPIO_PON_MODE,
+			GPIO_PON_MODE_MASK,
+			GPIO_PON_MODE_MASK
+		},
+		.regmap_size = 1,
+	},
+};
+
+static const struct airoha_pinctrl_func_group tod_1pps_func_group[] = {
+	{
+		.name = "pon_tod_1pps",
+		.regmap[0] = {
+			AIROHA_FUNC_MUX,
+			REG_GPIO_2ND_I2C_MODE,
+			PON_TOD_1PPS_MODE_MASK,
+			PON_TOD_1PPS_MODE_MASK
+		},
+		.regmap_size = 1,
+	}, {
+		.name = "gsw_tod_1pps",
+		.regmap[0] = {
+			AIROHA_FUNC_MUX,
+			REG_GPIO_2ND_I2C_MODE,
+			GSW_TOD_1PPS_MODE_MASK,
+			GSW_TOD_1PPS_MODE_MASK
+		},
+		.regmap_size = 1,
+	},
+};
+
+static const struct airoha_pinctrl_func_group sipo_func_group[] = {
+	{
+		.name = "sipo",
+		.regmap[0] = {
+			AIROHA_FUNC_MUX,
+			REG_GPIO_PON_MODE,
+			GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK,
+			GPIO_SIPO_MODE_MASK
+		},
+		.regmap_size = 1,
+	}, {
+		.name = "sipo_rclk",
+		.regmap[0] = {
+			AIROHA_FUNC_MUX,
+			REG_GPIO_PON_MODE,
+			GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK,
+			GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK
+		},
+		.regmap_size = 1,
+	},
+};
+
+static const struct airoha_pinctrl_func_group an7583_mdio_func_group[] = {
+	{
+		.name = "mdio",
+		.regmap[0] = {
+			AIROHA_FUNC_MUX,
+			REG_GPIO_PON_MODE,
+			GPIO_SGMII_MDIO_MODE_MASK,
+			GPIO_SGMII_MDIO_MODE_MASK
+		},
+		.regmap[1] = {
+			AIROHA_FUNC_MUX,
+			REG_GPIO_SPI_CS1_MODE,
+			GPIO_MDC_IO_MASTER_MODE_MASK,
+			GPIO_MDC_IO_MASTER_MODE_MASK
+		},
+		.regmap_size = 2,
+	},
+};
+
+static const struct airoha_pinctrl_func_group uart_func_group[] = {
+	{
+		.name = "uart2",
+		.regmap[0] = {
+			AIROHA_FUNC_MUX,
+			REG_GPIO_PON_MODE,
+			GPIO_UART2_MODE_MASK,
+			GPIO_UART2_MODE_MASK
+		},
+		.regmap_size = 1,
+	}, {
+		.name = "uart2_cts_rts",
+		.regmap[0] = {
+			AIROHA_FUNC_MUX,
+			REG_GPIO_PON_MODE,
+			GPIO_UART2_MODE_MASK | GPIO_UART2_CTS_RTS_MODE_MASK,
+			GPIO_UART2_MODE_MASK | GPIO_UART2_CTS_RTS_MODE_MASK
+		},
+		.regmap_size = 1,
+	}, {
+		.name = "hsuart",
+		.regmap[0] = {
+			AIROHA_FUNC_MUX,
+			REG_GPIO_PON_MODE,
+			GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK,
+			GPIO_HSUART_MODE_MASK
+		},
+		.regmap_size = 1,
+	},
+	{
+		.name = "hsuart_cts_rts",
+		.regmap[0] = {
+			AIROHA_FUNC_MUX,
+			REG_GPIO_PON_MODE,
+			GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK,
+			GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK
+		},
+		.regmap_size = 1,
+	}, {
+		.name = "uart4",
+		.regmap[0] = {
+			AIROHA_FUNC_MUX,
+			REG_GPIO_PON_MODE,
+			GPIO_UART4_MODE_MASK,
+			GPIO_UART4_MODE_MASK
+		},
+		.regmap_size = 1,
+	}, {
+		.name = "uart5",
+		.regmap[0] = {
+			AIROHA_FUNC_MUX,
+			REG_GPIO_PON_MODE,
+			GPIO_UART5_MODE_MASK,
+			GPIO_UART5_MODE_MASK
+		},
+		.regmap_size = 1,
+	},
+};
+
+static const struct airoha_pinctrl_func_group jtag_func_group[] = {
+	{
+		.name = "jtag_udi",
+		.regmap[0] = {
+			AIROHA_FUNC_MUX,
+			REG_NPU_UART_EN,
+			JTAG_UDI_EN_MASK,
+			JTAG_UDI_EN_MASK
+		},
+		.regmap_size = 1,
+	}, {
+		.name = "jtag_dfd",
+		.regmap[0] = {
+			AIROHA_FUNC_MUX,
+			REG_NPU_UART_EN,
+			JTAG_DFD_EN_MASK,
+			JTAG_DFD_EN_MASK
+		},
+		.regmap_size = 1,
+	},
+};
+
+static const struct airoha_pinctrl_func_group pcm_func_group[] = {
+	{
+		.name = "pcm1",
+		.regmap[0] = {
+			AIROHA_FUNC_MUX,
+			REG_GPIO_SPI_CS1_MODE,
+			GPIO_PCM1_MODE_MASK,
+			GPIO_PCM1_MODE_MASK
+		},
+		.regmap_size = 1,
+	}, {
+		.name = "pcm2",
+		.regmap[0] = {
+			AIROHA_FUNC_MUX,
+			REG_GPIO_SPI_CS1_MODE,
+			GPIO_PCM2_MODE_MASK,
+			GPIO_PCM2_MODE_MASK
+		},
+		.regmap_size = 1,
+	},
+};
+
+static const struct airoha_pinctrl_func_group spi_func_group[] = {
+	{
+		.name = "spi_quad",
+		.regmap[0] = {
+			AIROHA_FUNC_MUX,
+			REG_GPIO_SPI_CS1_MODE,
+			GPIO_SPI_QUAD_MODE_MASK,
+			GPIO_SPI_QUAD_MODE_MASK
+		},
+		.regmap_size = 1,
+	}, {
+		.name = "spi_cs1",
+		.regmap[0] = {
+			AIROHA_FUNC_MUX,
+			REG_GPIO_SPI_CS1_MODE,
+			GPIO_SPI_CS1_MODE_MASK,
+			GPIO_SPI_CS1_MODE_MASK
+		},
+		.regmap_size = 1,
+	}, {
+		.name = "spi_cs2",
+		.regmap[0] = {
+			AIROHA_FUNC_MUX,
+			REG_GPIO_SPI_CS1_MODE,
+			GPIO_SPI_CS2_MODE_MASK,
+			GPIO_SPI_CS2_MODE_MASK
+		},
+		.regmap_size = 1,
+	}, {
+		.name = "spi_cs3",
+		.regmap[0] = {
+			AIROHA_FUNC_MUX,
+			REG_GPIO_SPI_CS1_MODE,
+			GPIO_SPI_CS3_MODE_MASK,
+			GPIO_SPI_CS3_MODE_MASK
+		},
+		.regmap_size = 1,
+	}, {
+		.name = "spi_cs4",
+		.regmap[0] = {
+			AIROHA_FUNC_MUX,
+			REG_GPIO_SPI_CS1_MODE,
+			GPIO_SPI_CS4_MODE_MASK,
+			GPIO_SPI_CS4_MODE_MASK
+		},
+		.regmap_size = 1,
+	},
+};
+
+static const struct airoha_pinctrl_func_group an7583_pcm_spi_func_group[] = {
+	{
+		.name = "pcm_spi",
+		.regmap[0] = {
+			AIROHA_FUNC_MUX,
+			REG_GPIO_SPI_CS1_MODE,
+			GPIO_PCM_SPI_MODE_MASK,
+			GPIO_PCM_SPI_MODE_MASK
+		},
+		.regmap_size = 1,
+	}, {
+		.name = "pcm_spi_int",
+		.regmap[0] = {
+			AIROHA_FUNC_MUX,
+			REG_GPIO_SPI_CS1_MODE,
+			GPIO_PCM_INT_MODE_MASK,
+			GPIO_PCM_INT_MODE_MASK
+		},
+		.regmap_size = 1,
+	}, {
+		.name = "pcm_spi_rst",
+		.regmap[0] = {
+			AIROHA_FUNC_MUX,
+			REG_GPIO_SPI_CS1_MODE,
+			GPIO_PCM_RESET_MODE_MASK,
+			GPIO_PCM_RESET_MODE_MASK
+		},
+		.regmap_size = 1,
+	}, {
+		.name = "pcm_spi_cs1",
+		.regmap[0] = {
+			AIROHA_FUNC_MUX,
+			REG_GPIO_SPI_CS1_MODE,
+			GPIO_PCM_SPI_CS1_MODE_MASK,
+			GPIO_PCM_SPI_CS1_MODE_MASK
+		},
+		.regmap_size = 1,
+	}, {
+		.name = "pcm_spi_cs2",
+		.regmap[0] = {
+			AIROHA_FUNC_MUX,
+			REG_GPIO_SPI_CS1_MODE,
+			AN7583_GPIO_PCM_SPI_CS2_MODE_MASK,
+			AN7583_GPIO_PCM_SPI_CS2_MODE_MASK
+		},
+		.regmap_size = 1,
+	}, {
+		.name = "pcm_spi_cs3",
+		.regmap[0] = {
+			AIROHA_FUNC_MUX,
+			REG_GPIO_SPI_CS1_MODE,
+			GPIO_PCM_SPI_CS3_MODE_MASK,
+			GPIO_PCM_SPI_CS3_MODE_MASK
+		},
+		.regmap_size = 1,
+	}, {
+		.name = "pcm_spi_cs4",
+		.regmap[0] = {
+			AIROHA_FUNC_MUX,
+			REG_GPIO_SPI_CS1_MODE,
+			GPIO_PCM_SPI_CS4_MODE_MASK,
+			GPIO_PCM_SPI_CS4_MODE_MASK
+		},
+		.regmap_size = 1,
+	},
+};
+
+static const struct airoha_pinctrl_func_group emmc_func_group[] = {
+	{
+		.name = "emmc",
+		.regmap[0] = {
+			AIROHA_FUNC_MUX,
+			REG_GPIO_PON_MODE,
+			GPIO_EMMC_MODE_MASK,
+			GPIO_EMMC_MODE_MASK
+		},
+		.regmap_size = 1,
+	},
+};
+
+static const struct airoha_pinctrl_func_group pnand_func_group[] = {
+	{
+		.name = "pnand",
+		.regmap[0] = {
+			AIROHA_FUNC_MUX,
+			REG_GPIO_PON_MODE,
+			GPIO_PARALLEL_NAND_MODE_MASK,
+			GPIO_PARALLEL_NAND_MODE_MASK
+		},
+		.regmap_size = 1,
+	},
+};
+
+static const struct airoha_pinctrl_func_group an7583_gpio_func_group[] = {
+	AIROHA_PINCTRL_GPIO_EXT("gpio39", GPIO39_FLASH_MODE_CFG,
+				AN7583_I2C0_SCL_GPIO_MODE_MASK),
+	AIROHA_PINCTRL_GPIO_EXT("gpio40", GPIO40_FLASH_MODE_CFG,
+				AN7583_I2C0_SDA_GPIO_MODE_MASK),
+	AIROHA_PINCTRL_GPIO_EXT("gpio41", GPIO41_FLASH_MODE_CFG,
+				AN7583_I2C1_SCL_GPIO_MODE_MASK),
+	AIROHA_PINCTRL_GPIO_EXT("gpio42", GPIO42_FLASH_MODE_CFG,
+				AN7583_I2C1_SDA_GPIO_MODE_MASK),
+	AIROHA_PINCTRL_GPIO_EXT("gpio43", GPIO43_FLASH_MODE_CFG,
+				AN7583_SPI_CLK_GPIO_MODE_MASK),
+	AIROHA_PINCTRL_GPIO_EXT("gpio44", GPIO44_FLASH_MODE_CFG,
+				AN7583_SPI_CS_GPIO_MODE_MASK),
+	AIROHA_PINCTRL_GPIO_EXT("gpio45", GPIO45_FLASH_MODE_CFG,
+				AN7583_SPI_MOSI_GPIO_MODE_MASK),
+	AIROHA_PINCTRL_GPIO_EXT("gpio46", GPIO46_FLASH_MODE_CFG,
+				AN7583_SPI_MISO_GPIO_MODE_MASK),
+	AIROHA_PINCTRL_GPIO_EXT("gpio47", GPIO47_FLASH_MODE_CFG,
+				AN7583_UART_TXD_GPIO_MODE_MASK),
+	AIROHA_PINCTRL_GPIO_EXT("gpio48", GPIO48_FLASH_MODE_CFG,
+				AN7583_UART_RXD_GPIO_MODE_MASK),
+	AIROHA_PINCTRL_GPIO_EXT("gpio49", GPIO49_FLASH_MODE_CFG,
+				GPIO_PCIE_RESET0_MASK),
+	AIROHA_PINCTRL_GPIO_EXT("gpio50", GPIO50_FLASH_MODE_CFG,
+				GPIO_PCIE_RESET1_MASK),
+	AIROHA_PINCTRL_GPIO_EXT("gpio51", GPIO51_FLASH_MODE_CFG,
+				AN7583_MDC_0_GPIO_MODE_MASK),
+	AIROHA_PINCTRL_GPIO("gpio52", AN7583_MDIO_0_GPIO_MODE_MASK),
+};
+
+static const struct airoha_pinctrl_func_group an7583_pcie_reset_func_group[] = {
+	{
+		.name = "pcie_reset0",
+		.regmap[0] = {
+			AIROHA_FUNC_MUX,
+			REG_GPIO_PON_MODE,
+			GPIO_PCIE_RESET0_MASK,
+			0
+		},
+		.regmap_size = 1,
+	}, {
+		.name = "pcie_reset1",
+		.regmap[0] = {
+			AIROHA_FUNC_MUX,
+			REG_GPIO_PON_MODE,
+			GPIO_PCIE_RESET1_MASK,
+			0
+		},
+		.regmap_size = 1,
+	},
+};
+
+static const struct airoha_pinctrl_func_group an7583_pwm_func_group[] = {
+	AIROHA_PINCTRL_PWM("gpio0", GPIO0_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM("gpio1", GPIO1_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM("gpio2", GPIO2_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM("gpio3", GPIO3_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM("gpio4", GPIO4_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM("gpio5", GPIO5_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM("gpio6", GPIO6_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM("gpio7", GPIO7_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM("gpio8", GPIO8_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM("gpio9", GPIO9_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM("gpio10", GPIO10_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM("gpio11", GPIO11_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM("gpio12", GPIO12_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM("gpio13", GPIO13_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM("gpio14", GPIO14_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM("gpio15", GPIO15_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM_EXT("gpio16", GPIO16_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM_EXT("gpio17", GPIO17_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM_EXT("gpio18", GPIO18_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM_EXT("gpio19", GPIO19_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM_EXT("gpio20", GPIO20_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM_EXT("gpio21", GPIO21_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM_EXT("gpio22", GPIO22_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM_EXT("gpio23", GPIO23_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM_EXT("gpio24", GPIO24_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM_EXT("gpio25", GPIO25_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM_EXT("gpio26", GPIO26_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM_EXT("gpio27", GPIO27_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM_EXT("gpio28", GPIO28_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM_EXT("gpio29", GPIO29_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM_EXT("gpio30", GPIO30_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM_EXT("gpio31", GPIO31_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM_EXT("gpio36", GPIO36_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM_EXT("gpio37", GPIO37_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM_EXT("gpio38", GPIO38_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM_EXT_SEC("gpio39", GPIO39_FLASH_MODE_CFG,
+				   AN7583_I2C0_SCL_GPIO_MODE_MASK),
+	AIROHA_PINCTRL_PWM_EXT_SEC("gpio40", GPIO40_FLASH_MODE_CFG,
+				   AN7583_I2C0_SDA_GPIO_MODE_MASK),
+	AIROHA_PINCTRL_PWM_EXT_SEC("gpio41", GPIO41_FLASH_MODE_CFG,
+				   AN7583_I2C1_SCL_GPIO_MODE_MASK),
+	AIROHA_PINCTRL_PWM_EXT_SEC("gpio42", GPIO42_FLASH_MODE_CFG,
+				   AN7583_I2C1_SDA_GPIO_MODE_MASK),
+	AIROHA_PINCTRL_PWM_EXT_SEC("gpio43", GPIO43_FLASH_MODE_CFG,
+				   AN7583_SPI_CLK_GPIO_MODE_MASK),
+	AIROHA_PINCTRL_PWM_EXT_SEC("gpio44", GPIO44_FLASH_MODE_CFG,
+				   AN7583_SPI_CS_GPIO_MODE_MASK),
+	AIROHA_PINCTRL_PWM_EXT_SEC("gpio45", GPIO45_FLASH_MODE_CFG,
+				   AN7583_SPI_MOSI_GPIO_MODE_MASK),
+	AIROHA_PINCTRL_PWM_EXT_SEC("gpio46", GPIO46_FLASH_MODE_CFG,
+				   AN7583_SPI_MISO_GPIO_MODE_MASK),
+	AIROHA_PINCTRL_PWM_EXT_SEC("gpio47", GPIO47_FLASH_MODE_CFG,
+				   AN7583_UART_TXD_GPIO_MODE_MASK),
+	AIROHA_PINCTRL_PWM_EXT_SEC("gpio48", GPIO48_FLASH_MODE_CFG,
+				   AN7583_UART_RXD_GPIO_MODE_MASK),
+	AIROHA_PINCTRL_PWM_EXT_SEC("gpio49", GPIO49_FLASH_MODE_CFG,
+				   GPIO_PCIE_RESET0_MASK),
+	AIROHA_PINCTRL_PWM_EXT_SEC("gpio50", GPIO50_FLASH_MODE_CFG,
+				   GPIO_PCIE_RESET1_MASK),
+	AIROHA_PINCTRL_PWM_EXT_SEC("gpio51", GPIO51_FLASH_MODE_CFG,
+				   AN7583_MDC_0_GPIO_MODE_MASK),
+};
+
+static const struct airoha_pinctrl_func_group an7583_phy1_led0_func_group[] = {
+	AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK,
+				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),
+	AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK,
+				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)),
+	AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK,
+				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)),
+	AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK,
+				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),
+};
+
+static const struct airoha_pinctrl_func_group an7583_phy2_led0_func_group[] = {
+	AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK,
+				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),
+	AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK,
+				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)),
+	AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK,
+				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)),
+	AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK,
+				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),
+};
+
+static const struct airoha_pinctrl_func_group an7583_phy3_led0_func_group[] = {
+	AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK,
+				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
+	AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK,
+				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),
+	AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK,
+				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),
+	AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK,
+				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
+};
+
+static const struct airoha_pinctrl_func_group an7583_phy4_led0_func_group[] = {
+	AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK,
+				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)),
+	AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK,
+				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)),
+	AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK,
+				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)),
+	AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK,
+				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)),
+};
+
+static const struct airoha_pinctrl_func_group an7583_phy1_led1_func_group[] = {
+	AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK,
+				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),
+	AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK,
+				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)),
+	AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK,
+				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)),
+	AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK,
+				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),
+};
+
+static const struct airoha_pinctrl_func_group an7583_phy2_led1_func_group[] = {
+	AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK,
+				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),
+	AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK,
+				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)),
+	AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK,
+				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)),
+	AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK,
+				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),
+};
+
+static const struct airoha_pinctrl_func_group an7583_phy3_led1_func_group[] = {
+	AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK,
+				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
+	AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK,
+				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),
+	AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK,
+				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),
+	AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK,
+				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
+};
+
+static const struct airoha_pinctrl_func_group an7583_phy4_led1_func_group[] = {
+	AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK,
+				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)),
+	AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK,
+				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)),
+	AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK,
+				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)),
+	AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK,
+				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)),
+};
+
+static const struct airoha_pinctrl_func an7583_pinctrl_funcs[] = {
+	PINCTRL_FUNC_DESC("pon", pon),
+	PINCTRL_FUNC_DESC("tod_1pps", tod_1pps),
+	PINCTRL_FUNC_DESC("sipo", sipo),
+	PINCTRL_FUNC_DESC("mdio", an7583_mdio),
+	PINCTRL_FUNC_DESC("uart", uart),
+	PINCTRL_FUNC_DESC("jtag", jtag),
+	PINCTRL_FUNC_DESC("pcm", pcm),
+	PINCTRL_FUNC_DESC("spi", spi),
+	PINCTRL_FUNC_DESC("pcm_spi", an7583_pcm_spi),
+	PINCTRL_FUNC_DESC("emmc", emmc),
+	PINCTRL_FUNC_DESC("pnand", pnand),
+	PINCTRL_FUNC_DESC("gpio", an7583_gpio),
+	PINCTRL_FUNC_DESC("pcie_reset", an7583_pcie_reset),
+	PINCTRL_FUNC_DESC("pwm", an7583_pwm),
+	PINCTRL_FUNC_DESC("phy1_led0", an7583_phy1_led0),
+	PINCTRL_FUNC_DESC("phy2_led0", an7583_phy2_led0),
+	PINCTRL_FUNC_DESC("phy3_led0", an7583_phy3_led0),
+	PINCTRL_FUNC_DESC("phy4_led0", an7583_phy4_led0),
+	PINCTRL_FUNC_DESC("phy1_led1", an7583_phy1_led1),
+	PINCTRL_FUNC_DESC("phy2_led1", an7583_phy2_led1),
+	PINCTRL_FUNC_DESC("phy3_led1", an7583_phy3_led1),
+	PINCTRL_FUNC_DESC("phy4_led1", an7583_phy4_led1),
+};
+
+static const struct airoha_pinctrl_conf an7583_pinctrl_pullup_conf[] = {
+	PINCTRL_CONF_DESC(2, REG_GPIO_L_PU, BIT(0)),
+	PINCTRL_CONF_DESC(3, REG_GPIO_L_PU, BIT(1)),
+	PINCTRL_CONF_DESC(4, REG_GPIO_L_PU, BIT(2)),
+	PINCTRL_CONF_DESC(5, REG_GPIO_L_PU, BIT(3)),
+	PINCTRL_CONF_DESC(6, REG_GPIO_L_PU, BIT(4)),
+	PINCTRL_CONF_DESC(7, REG_GPIO_L_PU, BIT(5)),
+	PINCTRL_CONF_DESC(8, REG_GPIO_L_PU, BIT(6)),
+	PINCTRL_CONF_DESC(9, REG_GPIO_L_PU, BIT(7)),
+	PINCTRL_CONF_DESC(10, REG_GPIO_L_PU, BIT(8)),
+	PINCTRL_CONF_DESC(11, REG_GPIO_L_PU, BIT(9)),
+	PINCTRL_CONF_DESC(12, REG_GPIO_L_PU, BIT(10)),
+	PINCTRL_CONF_DESC(13, REG_GPIO_L_PU, BIT(11)),
+	PINCTRL_CONF_DESC(14, REG_GPIO_L_PU, BIT(12)),
+	PINCTRL_CONF_DESC(15, REG_GPIO_L_PU, BIT(13)),
+	PINCTRL_CONF_DESC(16, REG_GPIO_L_PU, BIT(14)),
+	PINCTRL_CONF_DESC(17, REG_GPIO_L_PU, BIT(15)),
+	PINCTRL_CONF_DESC(18, REG_GPIO_L_PU, BIT(16)),
+	PINCTRL_CONF_DESC(19, REG_GPIO_L_PU, BIT(17)),
+	PINCTRL_CONF_DESC(20, REG_GPIO_L_PU, BIT(18)),
+	PINCTRL_CONF_DESC(21, REG_GPIO_L_PU, BIT(19)),
+	PINCTRL_CONF_DESC(22, REG_GPIO_L_PU, BIT(20)),
+	PINCTRL_CONF_DESC(23, REG_GPIO_L_PU, BIT(21)),
+	PINCTRL_CONF_DESC(24, REG_GPIO_L_PU, BIT(22)),
+	PINCTRL_CONF_DESC(25, REG_GPIO_L_PU, BIT(23)),
+	PINCTRL_CONF_DESC(26, REG_GPIO_L_PU, BIT(24)),
+	PINCTRL_CONF_DESC(27, REG_GPIO_L_PU, BIT(25)),
+	PINCTRL_CONF_DESC(28, REG_GPIO_L_PU, BIT(26)),
+	PINCTRL_CONF_DESC(29, REG_GPIO_L_PU, BIT(27)),
+	PINCTRL_CONF_DESC(30, REG_GPIO_L_PU, BIT(28)),
+	PINCTRL_CONF_DESC(31, REG_GPIO_L_PU, BIT(29)),
+	PINCTRL_CONF_DESC(32, REG_GPIO_L_PU, BIT(30)),
+	PINCTRL_CONF_DESC(33, REG_GPIO_L_PU, BIT(31)),
+	PINCTRL_CONF_DESC(34, REG_GPIO_H_PU, BIT(0)),
+	PINCTRL_CONF_DESC(35, REG_GPIO_H_PU, BIT(1)),
+	PINCTRL_CONF_DESC(36, REG_GPIO_H_PU, BIT(2)),
+	PINCTRL_CONF_DESC(37, REG_GPIO_H_PU, BIT(3)),
+	PINCTRL_CONF_DESC(38, REG_GPIO_H_PU, BIT(4)),
+	PINCTRL_CONF_DESC(39, REG_GPIO_H_PU, BIT(5)),
+	PINCTRL_CONF_DESC(40, REG_GPIO_H_PU, BIT(6)),
+	PINCTRL_CONF_DESC(41, REG_I2C_SDA_PU, I2C_SCL_PU_MASK),
+	PINCTRL_CONF_DESC(42, REG_I2C_SDA_PU, I2C_SDA_PU_MASK),
+	PINCTRL_CONF_DESC(43, REG_I2C_SDA_PU, AN7583_I2C1_SCL_PU_MASK),
+	PINCTRL_CONF_DESC(44, REG_I2C_SDA_PU, AN7583_I2C1_SDA_PU_MASK),
+	PINCTRL_CONF_DESC(45, REG_I2C_SDA_PU, SPI_CLK_PU_MASK),
+	PINCTRL_CONF_DESC(46, REG_I2C_SDA_PU, SPI_CS0_PU_MASK),
+	PINCTRL_CONF_DESC(47, REG_I2C_SDA_PU, SPI_MOSI_PU_MASK),
+	PINCTRL_CONF_DESC(48, REG_I2C_SDA_PU, SPI_MISO_PU_MASK),
+	PINCTRL_CONF_DESC(49, REG_I2C_SDA_PU, UART1_TXD_PU_MASK),
+	PINCTRL_CONF_DESC(50, REG_I2C_SDA_PU, UART1_RXD_PU_MASK),
+	PINCTRL_CONF_DESC(51, REG_I2C_SDA_PU, PCIE0_RESET_PU_MASK),
+	PINCTRL_CONF_DESC(52, REG_I2C_SDA_PU, PCIE1_RESET_PU_MASK),
+	PINCTRL_CONF_DESC(53, REG_I2C_SDA_PU, AN7583_MDC_0_PU_MASK),
+	PINCTRL_CONF_DESC(54, REG_I2C_SDA_PU, AN7583_MDIO_0_PU_MASK),
+};
+
+static const struct airoha_pinctrl_conf an7583_pinctrl_pulldown_conf[] = {
+	PINCTRL_CONF_DESC(2, REG_GPIO_L_PD, BIT(0)),
+	PINCTRL_CONF_DESC(3, REG_GPIO_L_PD, BIT(1)),
+	PINCTRL_CONF_DESC(4, REG_GPIO_L_PD, BIT(2)),
+	PINCTRL_CONF_DESC(5, REG_GPIO_L_PD, BIT(3)),
+	PINCTRL_CONF_DESC(6, REG_GPIO_L_PD, BIT(4)),
+	PINCTRL_CONF_DESC(7, REG_GPIO_L_PD, BIT(5)),
+	PINCTRL_CONF_DESC(8, REG_GPIO_L_PD, BIT(6)),
+	PINCTRL_CONF_DESC(9, REG_GPIO_L_PD, BIT(7)),
+	PINCTRL_CONF_DESC(10, REG_GPIO_L_PD, BIT(8)),
+	PINCTRL_CONF_DESC(11, REG_GPIO_L_PD, BIT(9)),
+	PINCTRL_CONF_DESC(12, REG_GPIO_L_PD, BIT(10)),
+	PINCTRL_CONF_DESC(13, REG_GPIO_L_PD, BIT(11)),
+	PINCTRL_CONF_DESC(14, REG_GPIO_L_PD, BIT(12)),
+	PINCTRL_CONF_DESC(15, REG_GPIO_L_PD, BIT(13)),
+	PINCTRL_CONF_DESC(16, REG_GPIO_L_PD, BIT(14)),
+	PINCTRL_CONF_DESC(17, REG_GPIO_L_PD, BIT(15)),
+	PINCTRL_CONF_DESC(18, REG_GPIO_L_PD, BIT(16)),
+	PINCTRL_CONF_DESC(19, REG_GPIO_L_PD, BIT(17)),
+	PINCTRL_CONF_DESC(20, REG_GPIO_L_PD, BIT(18)),
+	PINCTRL_CONF_DESC(21, REG_GPIO_L_PD, BIT(19)),
+	PINCTRL_CONF_DESC(22, REG_GPIO_L_PD, BIT(20)),
+	PINCTRL_CONF_DESC(23, REG_GPIO_L_PD, BIT(21)),
+	PINCTRL_CONF_DESC(24, REG_GPIO_L_PD, BIT(22)),
+	PINCTRL_CONF_DESC(25, REG_GPIO_L_PD, BIT(23)),
+	PINCTRL_CONF_DESC(26, REG_GPIO_L_PD, BIT(24)),
+	PINCTRL_CONF_DESC(27, REG_GPIO_L_PD, BIT(25)),
+	PINCTRL_CONF_DESC(28, REG_GPIO_L_PD, BIT(26)),
+	PINCTRL_CONF_DESC(29, REG_GPIO_L_PD, BIT(27)),
+	PINCTRL_CONF_DESC(30, REG_GPIO_L_PD, BIT(28)),
+	PINCTRL_CONF_DESC(31, REG_GPIO_L_PD, BIT(29)),
+	PINCTRL_CONF_DESC(32, REG_GPIO_L_PD, BIT(30)),
+	PINCTRL_CONF_DESC(33, REG_GPIO_L_PD, BIT(31)),
+	PINCTRL_CONF_DESC(34, REG_GPIO_H_PD, BIT(0)),
+	PINCTRL_CONF_DESC(35, REG_GPIO_H_PD, BIT(1)),
+	PINCTRL_CONF_DESC(36, REG_GPIO_H_PD, BIT(2)),
+	PINCTRL_CONF_DESC(37, REG_GPIO_H_PD, BIT(3)),
+	PINCTRL_CONF_DESC(38, REG_GPIO_H_PD, BIT(4)),
+	PINCTRL_CONF_DESC(39, REG_GPIO_H_PD, BIT(5)),
+	PINCTRL_CONF_DESC(40, REG_GPIO_H_PD, BIT(6)),
+	PINCTRL_CONF_DESC(41, REG_I2C_SDA_PD, I2C_SCL_PD_MASK),
+	PINCTRL_CONF_DESC(42, REG_I2C_SDA_PD, I2C_SDA_PD_MASK),
+	PINCTRL_CONF_DESC(43, REG_I2C_SDA_PD, AN7583_I2C1_SCL_PD_MASK),
+	PINCTRL_CONF_DESC(44, REG_I2C_SDA_PD, AN7583_I2C1_SDA_PD_MASK),
+	PINCTRL_CONF_DESC(45, REG_I2C_SDA_PD, SPI_CLK_PD_MASK),
+	PINCTRL_CONF_DESC(46, REG_I2C_SDA_PD, SPI_CS0_PD_MASK),
+	PINCTRL_CONF_DESC(47, REG_I2C_SDA_PD, SPI_MOSI_PD_MASK),
+	PINCTRL_CONF_DESC(48, REG_I2C_SDA_PD, SPI_MISO_PD_MASK),
+	PINCTRL_CONF_DESC(49, REG_I2C_SDA_PD, UART1_TXD_PD_MASK),
+	PINCTRL_CONF_DESC(50, REG_I2C_SDA_PD, UART1_RXD_PD_MASK),
+	PINCTRL_CONF_DESC(51, REG_I2C_SDA_PD, PCIE0_RESET_PD_MASK),
+	PINCTRL_CONF_DESC(52, REG_I2C_SDA_PD, PCIE1_RESET_PD_MASK),
+	PINCTRL_CONF_DESC(53, REG_I2C_SDA_PD, AN7583_MDC_0_PD_MASK),
+	PINCTRL_CONF_DESC(54, REG_I2C_SDA_PD, AN7583_MDIO_0_PD_MASK),
+};
+
+static const struct airoha_pinctrl_conf an7583_pinctrl_drive_e2_conf[] = {
+	PINCTRL_CONF_DESC(2, REG_GPIO_L_E2, BIT(0)),
+	PINCTRL_CONF_DESC(3, REG_GPIO_L_E2, BIT(1)),
+	PINCTRL_CONF_DESC(4, REG_GPIO_L_E2, BIT(2)),
+	PINCTRL_CONF_DESC(5, REG_GPIO_L_E2, BIT(3)),
+	PINCTRL_CONF_DESC(6, REG_GPIO_L_E2, BIT(4)),
+	PINCTRL_CONF_DESC(7, REG_GPIO_L_E2, BIT(5)),
+	PINCTRL_CONF_DESC(8, REG_GPIO_L_E2, BIT(6)),
+	PINCTRL_CONF_DESC(9, REG_GPIO_L_E2, BIT(7)),
+	PINCTRL_CONF_DESC(10, REG_GPIO_L_E2, BIT(8)),
+	PINCTRL_CONF_DESC(11, REG_GPIO_L_E2, BIT(9)),
+	PINCTRL_CONF_DESC(12, REG_GPIO_L_E2, BIT(10)),
+	PINCTRL_CONF_DESC(13, REG_GPIO_L_E2, BIT(11)),
+	PINCTRL_CONF_DESC(14, REG_GPIO_L_E2, BIT(12)),
+	PINCTRL_CONF_DESC(15, REG_GPIO_L_E2, BIT(13)),
+	PINCTRL_CONF_DESC(16, REG_GPIO_L_E2, BIT(14)),
+	PINCTRL_CONF_DESC(17, REG_GPIO_L_E2, BIT(15)),
+	PINCTRL_CONF_DESC(18, REG_GPIO_L_E2, BIT(16)),
+	PINCTRL_CONF_DESC(19, REG_GPIO_L_E2, BIT(17)),
+	PINCTRL_CONF_DESC(20, REG_GPIO_L_E2, BIT(18)),
+	PINCTRL_CONF_DESC(21, REG_GPIO_L_E2, BIT(19)),
+	PINCTRL_CONF_DESC(22, REG_GPIO_L_E2, BIT(20)),
+	PINCTRL_CONF_DESC(23, REG_GPIO_L_E2, BIT(21)),
+	PINCTRL_CONF_DESC(24, REG_GPIO_L_E2, BIT(22)),
+	PINCTRL_CONF_DESC(25, REG_GPIO_L_E2, BIT(23)),
+	PINCTRL_CONF_DESC(26, REG_GPIO_L_E2, BIT(24)),
+	PINCTRL_CONF_DESC(27, REG_GPIO_L_E2, BIT(25)),
+	PINCTRL_CONF_DESC(28, REG_GPIO_L_E2, BIT(26)),
+	PINCTRL_CONF_DESC(29, REG_GPIO_L_E2, BIT(27)),
+	PINCTRL_CONF_DESC(30, REG_GPIO_L_E2, BIT(28)),
+	PINCTRL_CONF_DESC(31, REG_GPIO_L_E2, BIT(29)),
+	PINCTRL_CONF_DESC(32, REG_GPIO_L_E2, BIT(30)),
+	PINCTRL_CONF_DESC(33, REG_GPIO_L_E2, BIT(31)),
+	PINCTRL_CONF_DESC(34, REG_GPIO_H_E2, BIT(0)),
+	PINCTRL_CONF_DESC(35, REG_GPIO_H_E2, BIT(1)),
+	PINCTRL_CONF_DESC(36, REG_GPIO_H_E2, BIT(2)),
+	PINCTRL_CONF_DESC(37, REG_GPIO_H_E2, BIT(3)),
+	PINCTRL_CONF_DESC(38, REG_GPIO_H_E2, BIT(4)),
+	PINCTRL_CONF_DESC(39, REG_GPIO_H_E2, BIT(5)),
+	PINCTRL_CONF_DESC(40, REG_GPIO_H_E2, BIT(6)),
+	PINCTRL_CONF_DESC(41, REG_I2C_SDA_E2, I2C_SCL_E2_MASK),
+	PINCTRL_CONF_DESC(42, REG_I2C_SDA_E2, I2C_SDA_E2_MASK),
+	PINCTRL_CONF_DESC(43, REG_I2C_SDA_E2, AN7583_I2C1_SCL_E2_MASK),
+	PINCTRL_CONF_DESC(44, REG_I2C_SDA_E2, AN7583_I2C1_SDA_E2_MASK),
+	PINCTRL_CONF_DESC(45, REG_I2C_SDA_E2, SPI_CLK_E2_MASK),
+	PINCTRL_CONF_DESC(46, REG_I2C_SDA_E2, SPI_CS0_E2_MASK),
+	PINCTRL_CONF_DESC(47, REG_I2C_SDA_E2, SPI_MOSI_E2_MASK),
+	PINCTRL_CONF_DESC(48, REG_I2C_SDA_E2, SPI_MISO_E2_MASK),
+	PINCTRL_CONF_DESC(49, REG_I2C_SDA_E2, UART1_TXD_E2_MASK),
+	PINCTRL_CONF_DESC(50, REG_I2C_SDA_E2, UART1_RXD_E2_MASK),
+	PINCTRL_CONF_DESC(51, REG_I2C_SDA_E2, PCIE0_RESET_E2_MASK),
+	PINCTRL_CONF_DESC(52, REG_I2C_SDA_E2, PCIE1_RESET_E2_MASK),
+	PINCTRL_CONF_DESC(53, REG_I2C_SDA_E2, AN7583_MDC_0_E2_MASK),
+	PINCTRL_CONF_DESC(54, REG_I2C_SDA_E2, AN7583_MDIO_0_E2_MASK),
+};
+
+static const struct airoha_pinctrl_conf an7583_pinctrl_drive_e4_conf[] = {
+	PINCTRL_CONF_DESC(2, REG_GPIO_L_E4, BIT(0)),
+	PINCTRL_CONF_DESC(3, REG_GPIO_L_E4, BIT(1)),
+	PINCTRL_CONF_DESC(4, REG_GPIO_L_E4, BIT(2)),
+	PINCTRL_CONF_DESC(5, REG_GPIO_L_E4, BIT(3)),
+	PINCTRL_CONF_DESC(6, REG_GPIO_L_E4, BIT(4)),
+	PINCTRL_CONF_DESC(7, REG_GPIO_L_E4, BIT(5)),
+	PINCTRL_CONF_DESC(8, REG_GPIO_L_E4, BIT(6)),
+	PINCTRL_CONF_DESC(9, REG_GPIO_L_E4, BIT(7)),
+	PINCTRL_CONF_DESC(10, REG_GPIO_L_E4, BIT(8)),
+	PINCTRL_CONF_DESC(11, REG_GPIO_L_E4, BIT(9)),
+	PINCTRL_CONF_DESC(12, REG_GPIO_L_E4, BIT(10)),
+	PINCTRL_CONF_DESC(13, REG_GPIO_L_E4, BIT(11)),
+	PINCTRL_CONF_DESC(14, REG_GPIO_L_E4, BIT(12)),
+	PINCTRL_CONF_DESC(15, REG_GPIO_L_E4, BIT(13)),
+	PINCTRL_CONF_DESC(16, REG_GPIO_L_E4, BIT(14)),
+	PINCTRL_CONF_DESC(17, REG_GPIO_L_E4, BIT(15)),
+	PINCTRL_CONF_DESC(18, REG_GPIO_L_E4, BIT(16)),
+	PINCTRL_CONF_DESC(19, REG_GPIO_L_E4, BIT(17)),
+	PINCTRL_CONF_DESC(20, REG_GPIO_L_E4, BIT(18)),
+	PINCTRL_CONF_DESC(21, REG_GPIO_L_E4, BIT(19)),
+	PINCTRL_CONF_DESC(22, REG_GPIO_L_E4, BIT(20)),
+	PINCTRL_CONF_DESC(23, REG_GPIO_L_E4, BIT(21)),
+	PINCTRL_CONF_DESC(24, REG_GPIO_L_E4, BIT(22)),
+	PINCTRL_CONF_DESC(25, REG_GPIO_L_E4, BIT(23)),
+	PINCTRL_CONF_DESC(26, REG_GPIO_L_E4, BIT(24)),
+	PINCTRL_CONF_DESC(27, REG_GPIO_L_E4, BIT(25)),
+	PINCTRL_CONF_DESC(28, REG_GPIO_L_E4, BIT(26)),
+	PINCTRL_CONF_DESC(29, REG_GPIO_L_E4, BIT(27)),
+	PINCTRL_CONF_DESC(30, REG_GPIO_L_E4, BIT(28)),
+	PINCTRL_CONF_DESC(31, REG_GPIO_L_E4, BIT(29)),
+	PINCTRL_CONF_DESC(32, REG_GPIO_L_E4, BIT(30)),
+	PINCTRL_CONF_DESC(33, REG_GPIO_L_E4, BIT(31)),
+	PINCTRL_CONF_DESC(34, REG_GPIO_H_E4, BIT(0)),
+	PINCTRL_CONF_DESC(35, REG_GPIO_H_E4, BIT(1)),
+	PINCTRL_CONF_DESC(36, REG_GPIO_H_E4, BIT(2)),
+	PINCTRL_CONF_DESC(37, REG_GPIO_H_E4, BIT(3)),
+	PINCTRL_CONF_DESC(38, REG_GPIO_H_E4, BIT(4)),
+	PINCTRL_CONF_DESC(39, REG_GPIO_H_E4, BIT(5)),
+	PINCTRL_CONF_DESC(40, REG_GPIO_H_E4, BIT(6)),
+	PINCTRL_CONF_DESC(41, REG_I2C_SDA_E4, I2C_SCL_E4_MASK),
+	PINCTRL_CONF_DESC(42, REG_I2C_SDA_E4, I2C_SDA_E4_MASK),
+	PINCTRL_CONF_DESC(43, REG_I2C_SDA_E4, AN7583_I2C1_SCL_E4_MASK),
+	PINCTRL_CONF_DESC(44, REG_I2C_SDA_E4, AN7583_I2C1_SDA_E4_MASK),
+	PINCTRL_CONF_DESC(45, REG_I2C_SDA_E4, SPI_CLK_E4_MASK),
+	PINCTRL_CONF_DESC(46, REG_I2C_SDA_E4, SPI_CS0_E4_MASK),
+	PINCTRL_CONF_DESC(47, REG_I2C_SDA_E4, SPI_MOSI_E4_MASK),
+	PINCTRL_CONF_DESC(48, REG_I2C_SDA_E4, SPI_MISO_E4_MASK),
+	PINCTRL_CONF_DESC(49, REG_I2C_SDA_E4, UART1_TXD_E4_MASK),
+	PINCTRL_CONF_DESC(50, REG_I2C_SDA_E4, UART1_RXD_E4_MASK),
+	PINCTRL_CONF_DESC(51, REG_I2C_SDA_E4, PCIE0_RESET_E4_MASK),
+	PINCTRL_CONF_DESC(52, REG_I2C_SDA_E4, PCIE1_RESET_E4_MASK),
+	PINCTRL_CONF_DESC(53, REG_I2C_SDA_E4, AN7583_MDC_0_E4_MASK),
+	PINCTRL_CONF_DESC(54, REG_I2C_SDA_E4, AN7583_MDIO_0_E4_MASK),
+};
+
+static const struct airoha_pinctrl_conf an7583_pinctrl_pcie_rst_od_conf[] = {
+	PINCTRL_CONF_DESC(51, REG_PCIE_RESET_OD, PCIE0_RESET_OD_MASK),
+	PINCTRL_CONF_DESC(52, REG_PCIE_RESET_OD, PCIE1_RESET_OD_MASK),
+};
+
+static const struct airoha_pinctrl_match_data an7583_pinctrl_match_data = {
+	.pinctrl_name = KBUILD_MODNAME,
+	.pinctrl_owner = THIS_MODULE,
+	.pins = an7583_pinctrl_pins,
+	.num_pins = ARRAY_SIZE(an7583_pinctrl_pins),
+	.grps = an7583_pinctrl_groups,
+	.num_grps = ARRAY_SIZE(an7583_pinctrl_groups),
+	.funcs = an7583_pinctrl_funcs,
+	.num_funcs = ARRAY_SIZE(an7583_pinctrl_funcs),
+	.confs_info = {
+		[AIROHA_PINCTRL_CONFS_PULLUP] = {
+			.confs = an7583_pinctrl_pullup_conf,
+			.num_confs = ARRAY_SIZE(an7583_pinctrl_pullup_conf),
+		},
+		[AIROHA_PINCTRL_CONFS_PULLDOWN] = {
+			.confs = an7583_pinctrl_pulldown_conf,
+			.num_confs = ARRAY_SIZE(an7583_pinctrl_pulldown_conf),
+		},
+		[AIROHA_PINCTRL_CONFS_DRIVE_E2] = {
+			.confs = an7583_pinctrl_drive_e2_conf,
+			.num_confs = ARRAY_SIZE(an7583_pinctrl_drive_e2_conf),
+		},
+		[AIROHA_PINCTRL_CONFS_DRIVE_E4] = {
+			.confs = an7583_pinctrl_drive_e4_conf,
+			.num_confs = ARRAY_SIZE(an7583_pinctrl_drive_e4_conf),
+		},
+		[AIROHA_PINCTRL_CONFS_PCIE_RST_OD] = {
+			.confs = an7583_pinctrl_pcie_rst_od_conf,
+			.num_confs = ARRAY_SIZE(an7583_pinctrl_pcie_rst_od_conf),
+		},
+	},
+};
+
+static const struct of_device_id airoha_pinctrl_of_match[] = {
+	{ .compatible = "airoha,an7583-pinctrl", .data = &an7583_pinctrl_match_data },
+	{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, airoha_pinctrl_of_match);
+
+static struct platform_driver airoha_pinctrl_driver = {
+	.probe = airoha_pinctrl_probe,
+	.driver = {
+		.name = "pinctrl-airoha-an7583",
+		.of_match_table = airoha_pinctrl_of_match,
+	},
+};
+module_platform_driver(airoha_pinctrl_driver);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Lorenzo Bianconi <lorenzo@kernel.org>");
+MODULE_AUTHOR("Benjamin Larsson <benjamin.larsson@genexis.eu>");
+MODULE_AUTHOR("Markus Gothe <markus.gothe@genexis.eu>");
+MODULE_DESCRIPTION("Pinctrl driver for Airoha AN7583 SoC");
-- 
2.53.0

Re: [PATCH v7 20/34] pinctrl: airoha: split driver on shared code and SoC specific drivers

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider:

New issues:
- [High] The trailing explicit status clear after executing `generic_handle_domain_irq()` double-ACKs edge-triggered interrupts, silencing subsequent pending edge events.
- [Medium] The driver dynamically copies an immutable `irq_chip` structure into per-instance memory, defeating the purpose of the `IRQCHIP_IMMUTABLE` flag.

Pre-existing issues:
- [High] Incorrect devres teardown ordering causes a Use-After-Free of `girq->domain` on driver unbind and a race condition during probe.
--

--- Patch [20]: [PATCH v7 20/34] pinctrl: airoha: split driver on shared code and SoC specific drivers ---
commit cead269156cfbd3a10c51e662e4e2740e945e387
Author: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>

pinctrl: airoha: split driver on shared code and SoC specific drivers
    
Split combined an7581/an7583 source file on a
 * shared pinctrl code (pinctrl-airoha.c)
 * an7581 specific pinctrl driver (pinctrl-an7581.c)
 * an7583 specific pinctrl driver (pinctrl-an7583.c)

Ininialization code was adapted a bit to work properly for shared
and SoC specific cases.

> diff --git a/drivers/pinctrl/airoha/airoha-common.h b/drivers/pinctrl/airoha/airoha-common.h
> --- a/drivers/pinctrl/airoha/airoha-common.h
> +++ b/drivers/pinctrl/airoha/airoha-common.h
> @@ -148,9 +148,12 @@ struct airoha_pinctrl {
>  	struct regmap *regmap;
>  
>  	struct airoha_pinctrl_gpiochip gpiochip;
> +	struct irq_chip gpio_irq_chip;
>  };

[ ... ]

> diff --git a/drivers/pinctrl/airoha/pinctrl-airoha.c b/drivers/pinctrl/airoha/pinctrl-airoha.c
> --- a/drivers/pinctrl/airoha/pinctrl-airoha.c
> +++ b/drivers/pinctrl/airoha/pinctrl-airoha.c
> @@ -2630,9 +343,11 @@ static int airoha_pinctrl_add_gpiochip(struct airoha_pinctrl *pinctrl,
>  	gc->base = -1;
>  	gc->ngpio = AIROHA_NUM_PINS;
>  
> +	memcpy(irq_chip, &airoha_gpio_irq_chip, sizeof(struct irq_chip));
> +
>  	girq->default_type = IRQ_TYPE_NONE;
>  	girq->handler = handle_bad_irq;
> -	gpio_irq_chip_set_chip(girq, &airoha_gpio_irq_chip);
> +	gpio_irq_chip_set_chip(girq, irq_chip);

[Severity: Medium]
Does copying the immutable airoha_gpio_irq_chip into per-instance memory
bypass the protections of the IRQCHIP_IMMUTABLE flag?

The core kernel contract expects a static const irq_chip to be passed to
gpio_irq_chip_set_chip(). Here, the driver dynamically copies it into the
mutable pinctrl->gpio_irq_chip and registers that instead.

[Severity: High]
This is a pre-existing issue, but can the devres teardown order here cause
a use-after-free of the IRQ domain?

In airoha_pinctrl_add_gpiochip(), devm_request_irq() is called before
devm_gpiochip_add_data():

    err = devm_request_irq(dev, irq, airoha_irq_handler, IRQF_SHARED,
                           dev_name(dev), pinctrl);

On driver unbind, devres will execute gpiochip_remove() first (which
destroys girq->domain), and only then call free_irq(). If the shared parent
IRQ fires during this window, airoha_irq_handler() will dereference the
freed girq->domain when calling generic_handle_domain_irq().

It could also fire during probe before the domain is fully initialized.

[Severity: High]
Can the trailing status clear in airoha_irq_handler() lead to lost
edge-triggered interrupts?

Looking at airoha_irq_handler() in drivers/pinctrl/airoha/pinctrl-airoha.c:

    generic_handle_domain_irq(girq->domain, offset);
    regmap_write(pinctrl->regmap, pinctrl->gpiochip.status[i], BIT(irq));
        
This patch series updates edge-triggered interrupts to use handle_edge_irq,
which already ACKs the interrupt upfront via the .irq_ack callback. This
allows the hardware to latch new edge events while the handler runs.
However, the explicit regmap_write() after generic_handle_domain_irq()
double-ACKs the interrupt, potentially clearing any new edge events that
arrived during processing.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260727074234.3761170-1-mikhail.kshevetskiy@iopsys.eu?part=20

Re: [PATCH v7 20/34] pinctrl: airoha: split driver on shared code and SoC specific drivers

[Lorenzo Bianconi]

[-- Attachment #1: Type: text/plain, Size: 221364 bytes --]

> Split combined an7581/an7583 source file on a
>  * shared pinctrl code (pinctrl-airoha.c)
>  * an7581 specific pinctrl driver (pinctrl-an7581.c)
>  * an7583 specific pinctrl driver (pinctrl-an7583.c)

I do not think we can have 7581 and 7583 chips at the same time on a given
board so I guess we can avoid creating a dedicated module for the common code.
I guess we can just create a library we can compile in. What do yout think?

Regards,
Lorenzo

> 
> Ininialization code was adapted a bit to work properly for shared
> and SoC specific cases.
> 
> Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
> ---
>  drivers/pinctrl/airoha/Kconfig          |   24 +-
>  drivers/pinctrl/airoha/Makefile         |    5 +
>  drivers/pinctrl/airoha/airoha-common.h  |    5 +
>  drivers/pinctrl/airoha/pinctrl-airoha.c | 2382 +----------------------
>  drivers/pinctrl/airoha/pinctrl-an7581.c | 1486 ++++++++++++++
>  drivers/pinctrl/airoha/pinctrl-an7583.c | 1456 ++++++++++++++
>  6 files changed, 2984 insertions(+), 2374 deletions(-)
>  create mode 100644 drivers/pinctrl/airoha/pinctrl-an7581.c
>  create mode 100644 drivers/pinctrl/airoha/pinctrl-an7583.c
> 
> diff --git a/drivers/pinctrl/airoha/Kconfig b/drivers/pinctrl/airoha/Kconfig
> index 03adaeae8fc3a..dae6608bc72dd 100644
> --- a/drivers/pinctrl/airoha/Kconfig
> +++ b/drivers/pinctrl/airoha/Kconfig
> @@ -3,9 +3,9 @@ menu "Airoha pinctrl drivers"
>  	depends on ARCH_AIROHA || COMPILE_TEST
>  
>  config PINCTRL_AIROHA
> -	tristate "Airoha EN7581 pin control"
> +	tristate "Airoha pin control"
>  	depends on OF
> -	depends on ARM64 || COMPILE_TEST
> +	depends on ARCH_AIROHA || COMPILE_TEST
>  	select PINMUX
>  	select GENERIC_PINCONF
>  	select GENERIC_PINCTRL_GROUPS
> @@ -13,8 +13,26 @@ config PINCTRL_AIROHA
>  	select GPIOLIB
>  	select GPIOLIB_IRQCHIP
>  	select REGMAP_MMIO
> +	imply PINCTRL_AIROHA_AN7581
> +	imply PINCTRL_AIROHA_AN7583
> +	help
> +	  Shared pin controller and gpio driver code for different
> +	  Airoha SoCs.
> +
> +config PINCTRL_AIROHA_AN7581
> +	tristate "AN7581 pinctrl"
> +	depends on ARM64 || COMPILE_TEST
> +	depends on PINCTRL_AIROHA
> +	help
> +	  Say yes here to support pin controller and gpio driver
> +	  on Airoha AN7581, AN7566, AN7551 and other compatible SoCs.
> +
> +config PINCTRL_AIROHA_AN7583
> +	tristate "AN7583 pinctrl"
> +	depends on ARM64 || COMPILE_TEST
> +	depends on PINCTRL_AIROHA
>  	help
>  	  Say yes here to support pin controller and gpio driver
> -	  on Airoha EN7581 SoC.
> +	  on Airoha AN7583, AN7553, AN7567 and other compatible SoCs.
>  
>  endmenu
> diff --git a/drivers/pinctrl/airoha/Makefile b/drivers/pinctrl/airoha/Makefile
> index a25b744dd7a8a..cfd68c45ae0f0 100644
> --- a/drivers/pinctrl/airoha/Makefile
> +++ b/drivers/pinctrl/airoha/Makefile
> @@ -1,3 +1,8 @@
>  # SPDX-License-Identifier: GPL-2.0
>  
> +# shared code
>  obj-$(CONFIG_PINCTRL_AIROHA)		+= pinctrl-airoha.o
> +
> +# SoC drivers
> +obj-$(CONFIG_PINCTRL_AIROHA_AN7581)	+= pinctrl-an7581.o
> +obj-$(CONFIG_PINCTRL_AIROHA_AN7583)	+= pinctrl-an7583.o
> diff --git a/drivers/pinctrl/airoha/airoha-common.h b/drivers/pinctrl/airoha/airoha-common.h
> index 40d7e515c09eb..f73e90ca860f4 100644
> --- a/drivers/pinctrl/airoha/airoha-common.h
> +++ b/drivers/pinctrl/airoha/airoha-common.h
> @@ -148,9 +148,12 @@ struct airoha_pinctrl {
>  	struct regmap *regmap;
>  
>  	struct airoha_pinctrl_gpiochip gpiochip;
> +	struct irq_chip gpio_irq_chip;
>  };
>  
>  struct airoha_pinctrl_match_data {
> +	const char *pinctrl_name;
> +	struct module *pinctrl_owner;
>  	const struct pinctrl_pin_desc *pins;
>  	const unsigned int num_pins;
>  	const struct pingroup *grps;
> @@ -160,4 +163,6 @@ struct airoha_pinctrl_match_data {
>  	const struct airoha_pinctrl_confs_info confs_info[AIROHA_PINCTRL_CONFS_MAX];
>  };
>  
> +int airoha_pinctrl_probe(struct platform_device *pdev);
> +
>  #endif
> diff --git a/drivers/pinctrl/airoha/pinctrl-airoha.c b/drivers/pinctrl/airoha/pinctrl-airoha.c
> index f42631afc05d3..a46596eb1493b 100644
> --- a/drivers/pinctrl/airoha/pinctrl-airoha.c
> +++ b/drivers/pinctrl/airoha/pinctrl-airoha.c
> @@ -7,365 +7,6 @@
>  
>  #include "airoha-common.h"
>  
> -/* MUX */
> -#define REG_GPIO_2ND_I2C_MODE			0x0214
> -#define GPIO_MDC_IO_MASTER_MODE_MASK		BIT(14)
> -#define GPIO_I2C_MASTER_MODE_MODE		BIT(13)
> -#define GPIO_I2S_MODE_MASK			BIT(12)
> -#define GPIO_I2C_SLAVE_MODE_MODE		BIT(11)
> -#define GPIO_LAN3_LED1_MODE_MASK		BIT(10)
> -#define GPIO_LAN3_LED0_MODE_MASK		BIT(9)
> -#define GPIO_LAN2_LED1_MODE_MASK		BIT(8)
> -#define GPIO_LAN2_LED0_MODE_MASK		BIT(7)
> -#define GPIO_LAN1_LED1_MODE_MASK		BIT(6)
> -#define GPIO_LAN1_LED0_MODE_MASK		BIT(5)
> -#define GPIO_LAN0_LED1_MODE_MASK		BIT(4)
> -#define GPIO_LAN0_LED0_MODE_MASK		BIT(3)
> -#define PON_TOD_1PPS_MODE_MASK			BIT(2)
> -#define GSW_TOD_1PPS_MODE_MASK			BIT(1)
> -#define GPIO_2ND_I2C_MODE_MASK			BIT(0)
> -
> -#define REG_GPIO_SPI_CS1_MODE			0x0218
> -#define GPIO_PCM_SPI_CS4_MODE_MASK		BIT(21)
> -#define GPIO_PCM_SPI_CS3_MODE_MASK		BIT(20)
> -#define GPIO_PCM_SPI_CS2_MODE_P156_MASK		BIT(19)
> -#define GPIO_PCM_SPI_CS2_MODE_P128_MASK		BIT(18)
> -#define AN7583_GPIO_PCM_SPI_CS2_MODE_MASK	BIT(18)
> -#define GPIO_PCM_SPI_CS1_MODE_MASK		BIT(17)
> -#define GPIO_PCM_SPI_MODE_MASK			BIT(16)
> -#define GPIO_PCM2_MODE_MASK			BIT(13)
> -#define GPIO_PCM1_MODE_MASK			BIT(12)
> -#define GPIO_PCM_INT_MODE_MASK			BIT(9)
> -#define GPIO_PCM_RESET_MODE_MASK		BIT(8)
> -#define GPIO_SPI_QUAD_MODE_MASK			BIT(4)
> -#define GPIO_SPI_CS4_MODE_MASK			BIT(3)
> -#define GPIO_SPI_CS3_MODE_MASK			BIT(2)
> -#define GPIO_SPI_CS2_MODE_MASK			BIT(1)
> -#define GPIO_SPI_CS1_MODE_MASK			BIT(0)
> -
> -#define REG_GPIO_PON_MODE			0x021c
> -#define AN7583_MDIO_0_GPIO_MODE_MASK		BIT(26)
> -#define AN7583_MDC_0_GPIO_MODE_MASK		BIT(25)
> -#define AN7583_UART_RXD_GPIO_MODE_MASK		BIT(24)
> -#define AN7583_UART_TXD_GPIO_MODE_MASK		BIT(23)
> -#define AN7583_SPI_MISO_GPIO_MODE_MASK		BIT(22)
> -#define AN7583_SPI_MOSI_GPIO_MODE_MASK		BIT(21)
> -#define AN7583_SPI_CS_GPIO_MODE_MASK		BIT(20)
> -#define AN7583_SPI_CLK_GPIO_MODE_MASK		BIT(19)
> -#define AN7583_I2C1_SDA_GPIO_MODE_MASK		BIT(18)
> -#define AN7583_I2C1_SCL_GPIO_MODE_MASK		BIT(17)
> -#define AN7583_I2C0_SDA_GPIO_MODE_MASK		BIT(16)
> -#define AN7583_I2C0_SCL_GPIO_MODE_MASK		BIT(15)
> -#define GPIO_PARALLEL_NAND_MODE_MASK		BIT(14)
> -#define GPIO_SGMII_MDIO_MODE_MASK		BIT(13)
> -#define GPIO_PCIE_RESET2_MASK			BIT(12)
> -#define SIPO_RCLK_MODE_MASK			BIT(11)
> -#define GPIO_PCIE_RESET1_MASK			BIT(10)
> -#define GPIO_PCIE_RESET0_MASK			BIT(9)
> -#define GPIO_UART5_MODE_MASK			BIT(8)
> -#define GPIO_UART4_MODE_MASK			BIT(7)
> -#define GPIO_HSUART_CTS_RTS_MODE_MASK		BIT(6)
> -#define GPIO_HSUART_MODE_MASK			BIT(5)
> -#define GPIO_UART2_CTS_RTS_MODE_MASK		BIT(4)
> -#define GPIO_UART2_MODE_MASK			BIT(3)
> -#define GPIO_SIPO_MODE_MASK			BIT(2)
> -#define GPIO_EMMC_MODE_MASK			BIT(1)
> -#define GPIO_PON_MODE_MASK			BIT(0)
> -
> -#define REG_NPU_UART_EN				0x0224
> -#define JTAG_UDI_EN_MASK			BIT(4)
> -#define JTAG_DFD_EN_MASK			BIT(3)
> -
> -#define REG_FORCE_GPIO_EN			0x0228
> -#define FORCE_GPIO_EN(n)			BIT(n)
> -
> -/* LED MAP */
> -#define REG_LAN_LED0_MAPPING			0x027c
> -#define REG_LAN_LED1_MAPPING			0x0280
> -
> -#define LAN4_LED_MAPPING_MASK			GENMASK(18, 16)
> -#define LAN4_PHY_LED_MAP(_n)			FIELD_PREP_CONST(LAN4_LED_MAPPING_MASK, (_n))
> -
> -#define LAN3_LED_MAPPING_MASK			GENMASK(14, 12)
> -#define LAN3_PHY_LED_MAP(_n)			FIELD_PREP_CONST(LAN3_LED_MAPPING_MASK, (_n))
> -
> -#define LAN2_LED_MAPPING_MASK			GENMASK(10, 8)
> -#define LAN2_PHY_LED_MAP(_n)			FIELD_PREP_CONST(LAN2_LED_MAPPING_MASK, (_n))
> -
> -#define LAN1_LED_MAPPING_MASK			GENMASK(6, 4)
> -#define LAN1_PHY_LED_MAP(_n)			FIELD_PREP_CONST(LAN1_LED_MAPPING_MASK, (_n))
> -
> -#define LAN0_LED_MAPPING_MASK			GENMASK(2, 0)
> -#define LAN0_PHY_LED_MAP(_n)			FIELD_PREP_CONST(LAN0_LED_MAPPING_MASK, (_n))
> -
> -/* CONF */
> -#define REG_I2C_SDA_E2				0x001c
> -#define AN7583_I2C1_SCL_E2_MASK			BIT(16)
> -#define AN7583_I2C1_SDA_E2_MASK			BIT(15)
> -#define SPI_MISO_E2_MASK			BIT(14)
> -#define SPI_MOSI_E2_MASK			BIT(13)
> -#define SPI_CLK_E2_MASK				BIT(12)
> -#define SPI_CS0_E2_MASK				BIT(11)
> -#define PCIE2_RESET_E2_MASK			BIT(10)
> -#define PCIE1_RESET_E2_MASK			BIT(9)
> -#define PCIE0_RESET_E2_MASK			BIT(8)
> -#define AN7583_MDIO_0_E2_MASK			BIT(5)
> -#define AN7583_MDC_0_E2_MASK			BIT(4)
> -#define UART1_RXD_E2_MASK			BIT(3)
> -#define UART1_TXD_E2_MASK			BIT(2)
> -#define I2C_SCL_E2_MASK				BIT(1)
> -#define I2C_SDA_E2_MASK				BIT(0)
> -
> -#define REG_I2C_SDA_E4				0x0020
> -#define AN7583_I2C1_SCL_E4_MASK			BIT(16)
> -#define AN7583_I2C1_SDA_E4_MASK			BIT(15)
> -#define SPI_MISO_E4_MASK			BIT(14)
> -#define SPI_MOSI_E4_MASK			BIT(13)
> -#define SPI_CLK_E4_MASK				BIT(12)
> -#define SPI_CS0_E4_MASK				BIT(11)
> -#define PCIE2_RESET_E4_MASK			BIT(10)
> -#define PCIE1_RESET_E4_MASK			BIT(9)
> -#define PCIE0_RESET_E4_MASK			BIT(8)
> -#define AN7583_MDIO_0_E4_MASK			BIT(5)
> -#define AN7583_MDC_0_E4_MASK			BIT(4)
> -#define UART1_RXD_E4_MASK			BIT(3)
> -#define UART1_TXD_E4_MASK			BIT(2)
> -#define I2C_SCL_E4_MASK				BIT(1)
> -#define I2C_SDA_E4_MASK				BIT(0)
> -
> -#define REG_GPIO_L_E2				0x0024
> -#define REG_GPIO_L_E4				0x0028
> -#define REG_GPIO_H_E2				0x002c
> -#define REG_GPIO_H_E4				0x0030
> -
> -#define REG_I2C_SDA_PU				0x0044
> -#define AN7583_I2C1_SCL_PU_MASK			BIT(16)
> -#define AN7583_I2C1_SDA_PU_MASK			BIT(15)
> -#define SPI_MISO_PU_MASK			BIT(14)
> -#define SPI_MOSI_PU_MASK			BIT(13)
> -#define SPI_CLK_PU_MASK				BIT(12)
> -#define SPI_CS0_PU_MASK				BIT(11)
> -#define PCIE2_RESET_PU_MASK			BIT(10)
> -#define PCIE1_RESET_PU_MASK			BIT(9)
> -#define PCIE0_RESET_PU_MASK			BIT(8)
> -#define AN7583_MDIO_0_PU_MASK			BIT(5)
> -#define AN7583_MDC_0_PU_MASK			BIT(4)
> -#define UART1_RXD_PU_MASK			BIT(3)
> -#define UART1_TXD_PU_MASK			BIT(2)
> -#define I2C_SCL_PU_MASK				BIT(1)
> -#define I2C_SDA_PU_MASK				BIT(0)
> -
> -#define REG_I2C_SDA_PD				0x0048
> -#define AN7583_I2C1_SCL_PD_MASK			BIT(16)
> -#define AN7583_I2C1_SDA_PD_MASK			BIT(15)
> -#define SPI_MISO_PD_MASK			BIT(14)
> -#define SPI_MOSI_PD_MASK			BIT(13)
> -#define SPI_CLK_PD_MASK				BIT(12)
> -#define SPI_CS0_PD_MASK				BIT(11)
> -#define PCIE2_RESET_PD_MASK			BIT(10)
> -#define PCIE1_RESET_PD_MASK			BIT(9)
> -#define PCIE0_RESET_PD_MASK			BIT(8)
> -#define AN7583_MDIO_0_PD_MASK			BIT(5)
> -#define AN7583_MDC_0_PD_MASK			BIT(4)
> -#define UART1_RXD_PD_MASK			BIT(3)
> -#define UART1_TXD_PD_MASK			BIT(2)
> -#define I2C_SCL_PD_MASK				BIT(1)
> -#define I2C_SDA_PD_MASK				BIT(0)
> -
> -#define REG_GPIO_L_PU				0x004c
> -#define REG_GPIO_L_PD				0x0050
> -#define REG_GPIO_H_PU				0x0054
> -#define REG_GPIO_H_PD				0x0058
> -
> -#define REG_PCIE_RESET_OD			0x018c
> -#define PCIE2_RESET_OD_MASK			BIT(2)
> -#define PCIE1_RESET_OD_MASK			BIT(1)
> -#define PCIE0_RESET_OD_MASK			BIT(0)
> -
> -/* GPIOs */
> -#define REG_GPIO_CTRL				0x0000
> -#define REG_GPIO_DATA				0x0004
> -#define REG_GPIO_INT				0x0008
> -#define REG_GPIO_INT_EDGE			0x000c
> -#define REG_GPIO_INT_LEVEL			0x0010
> -#define REG_GPIO_OE				0x0014
> -#define REG_GPIO_CTRL1				0x0020
> -#define REG_GPIO_CTRL2				0x0060
> -#define REG_GPIO_CTRL3				0x0064
> -
> -/* PWM MODE CONF */
> -#define REG_GPIO_FLASH_MODE_CFG			0x0034
> -#define GPIO15_FLASH_MODE_CFG			BIT(15)
> -#define GPIO14_FLASH_MODE_CFG			BIT(14)
> -#define GPIO13_FLASH_MODE_CFG			BIT(13)
> -#define GPIO12_FLASH_MODE_CFG			BIT(12)
> -#define GPIO11_FLASH_MODE_CFG			BIT(11)
> -#define GPIO10_FLASH_MODE_CFG			BIT(10)
> -#define GPIO9_FLASH_MODE_CFG			BIT(9)
> -#define GPIO8_FLASH_MODE_CFG			BIT(8)
> -#define GPIO7_FLASH_MODE_CFG			BIT(7)
> -#define GPIO6_FLASH_MODE_CFG			BIT(6)
> -#define GPIO5_FLASH_MODE_CFG			BIT(5)
> -#define GPIO4_FLASH_MODE_CFG			BIT(4)
> -#define GPIO3_FLASH_MODE_CFG			BIT(3)
> -#define GPIO2_FLASH_MODE_CFG			BIT(2)
> -#define GPIO1_FLASH_MODE_CFG			BIT(1)
> -#define GPIO0_FLASH_MODE_CFG			BIT(0)
> -
> -/* PWM MODE CONF EXT */
> -#define REG_GPIO_FLASH_MODE_CFG_EXT		0x0068
> -#define GPIO51_FLASH_MODE_CFG			BIT(31)
> -#define GPIO50_FLASH_MODE_CFG			BIT(30)
> -#define GPIO49_FLASH_MODE_CFG			BIT(29)
> -#define GPIO48_FLASH_MODE_CFG			BIT(28)
> -#define GPIO47_FLASH_MODE_CFG			BIT(27)
> -#define GPIO46_FLASH_MODE_CFG			BIT(26)
> -#define GPIO45_FLASH_MODE_CFG			BIT(25)
> -#define GPIO44_FLASH_MODE_CFG			BIT(24)
> -#define GPIO43_FLASH_MODE_CFG			BIT(23)
> -#define GPIO42_FLASH_MODE_CFG			BIT(22)
> -#define GPIO41_FLASH_MODE_CFG			BIT(21)
> -#define GPIO40_FLASH_MODE_CFG			BIT(20)
> -#define GPIO39_FLASH_MODE_CFG			BIT(19)
> -#define GPIO38_FLASH_MODE_CFG			BIT(18)
> -#define GPIO37_FLASH_MODE_CFG			BIT(17)
> -#define GPIO36_FLASH_MODE_CFG			BIT(16)
> -#define GPIO31_FLASH_MODE_CFG			BIT(15)
> -#define GPIO30_FLASH_MODE_CFG			BIT(14)
> -#define GPIO29_FLASH_MODE_CFG			BIT(13)
> -#define GPIO28_FLASH_MODE_CFG			BIT(12)
> -#define GPIO27_FLASH_MODE_CFG			BIT(11)
> -#define GPIO26_FLASH_MODE_CFG			BIT(10)
> -#define GPIO25_FLASH_MODE_CFG			BIT(9)
> -#define GPIO24_FLASH_MODE_CFG			BIT(8)
> -#define GPIO23_FLASH_MODE_CFG			BIT(7)
> -#define GPIO22_FLASH_MODE_CFG			BIT(6)
> -#define GPIO21_FLASH_MODE_CFG			BIT(5)
> -#define GPIO20_FLASH_MODE_CFG			BIT(4)
> -#define GPIO19_FLASH_MODE_CFG			BIT(3)
> -#define GPIO18_FLASH_MODE_CFG			BIT(2)
> -#define GPIO17_FLASH_MODE_CFG			BIT(1)
> -#define GPIO16_FLASH_MODE_CFG			BIT(0)
> -
> -#define REG_GPIO_DATA1				0x0070
> -#define REG_GPIO_OE1				0x0078
> -#define REG_GPIO_INT1				0x007c
> -#define REG_GPIO_INT_EDGE1			0x0080
> -#define REG_GPIO_INT_EDGE2			0x0084
> -#define REG_GPIO_INT_EDGE3			0x0088
> -#define REG_GPIO_INT_LEVEL1			0x008c
> -#define REG_GPIO_INT_LEVEL2			0x0090
> -#define REG_GPIO_INT_LEVEL3			0x0094
> -
> -#define AIROHA_PINCTRL_GPIO(gpio, mux_val)			\
> -	{							\
> -		.name = (gpio),					\
> -		.regmap[0] = {					\
> -			AIROHA_FUNC_MUX,			\
> -			REG_GPIO_PON_MODE,			\
> -			(mux_val),				\
> -			(mux_val)				\
> -		},						\
> -		.regmap_size = 1,				\
> -	}
> -
> -#define AIROHA_PINCTRL_GPIO_EXT(gpio, mux_val, smux_val)	\
> -	{							\
> -		.name = (gpio),					\
> -		.regmap[0] = {					\
> -			AIROHA_FUNC_PWM_EXT_MUX,		\
> -			REG_GPIO_FLASH_MODE_CFG_EXT,		\
> -			(mux_val),				\
> -			0					\
> -		},						\
> -		.regmap[1] = {					\
> -			AIROHA_FUNC_MUX,			\
> -			REG_GPIO_PON_MODE,			\
> -			(smux_val),				\
> -			(smux_val)				\
> -		},						\
> -		.regmap_size = 2,				\
> -	}
> -
> -/* PWM */
> -#define AIROHA_PINCTRL_PWM(gpio, mux_val)		\
> -	{						\
> -		.name = (gpio),				\
> -		.regmap[0] = {				\
> -			AIROHA_FUNC_PWM_MUX,		\
> -			REG_GPIO_FLASH_MODE_CFG,	\
> -			(mux_val),			\
> -			(mux_val)			\
> -		},					\
> -		.regmap_size = 1,			\
> -	}
> -
> -#define AIROHA_PINCTRL_PWM_EXT(gpio, mux_val)		\
> -	{						\
> -		.name = (gpio),				\
> -		.regmap[0] = {				\
> -			AIROHA_FUNC_PWM_EXT_MUX,	\
> -			REG_GPIO_FLASH_MODE_CFG_EXT,	\
> -			(mux_val),			\
> -			(mux_val)			\
> -		},					\
> -		.regmap_size = 1,			\
> -	}
> -
> -#define AIROHA_PINCTRL_PWM_EXT_SEC(gpio, mux_val, smux_val)	\
> -	{							\
> -		.name = (gpio),					\
> -		.regmap[0] = {					\
> -			AIROHA_FUNC_PWM_EXT_MUX,		\
> -			REG_GPIO_FLASH_MODE_CFG_EXT,		\
> -			(mux_val),				\
> -			(mux_val)				\
> -		},						\
> -		.regmap[1] = {					\
> -			AIROHA_FUNC_MUX,			\
> -			REG_GPIO_PON_MODE,			\
> -			(smux_val),				\
> -			(smux_val)				\
> -		},						\
> -		.regmap_size = 2,				\
> -	}
> -
> -#define AIROHA_PINCTRL_PHY_LED0(gpio, mux_val, map_mask, map_val)	\
> -	{								\
> -		.name = (gpio),						\
> -		.regmap[0] = {						\
> -			AIROHA_FUNC_MUX,				\
> -			REG_GPIO_2ND_I2C_MODE,				\
> -			(mux_val),					\
> -			(mux_val),					\
> -		},							\
> -		.regmap[1] = {						\
> -			AIROHA_FUNC_MUX,				\
> -			REG_LAN_LED0_MAPPING,				\
> -			(map_mask),					\
> -			(map_val),					\
> -		},							\
> -		.regmap_size = 2,					\
> -	}
> -
> -#define AIROHA_PINCTRL_PHY_LED1(gpio, mux_val, map_mask, map_val)	\
> -	{								\
> -		.name = (gpio),						\
> -		.regmap[0] = {						\
> -			AIROHA_FUNC_MUX,				\
> -			REG_GPIO_2ND_I2C_MODE,				\
> -			(mux_val),					\
> -			(mux_val),					\
> -		},							\
> -		.regmap[1] = {						\
> -			AIROHA_FUNC_MUX,				\
> -			REG_LAN_LED1_MAPPING,				\
> -			(map_mask),					\
> -			(map_val),					\
> -		},							\
> -		.regmap_size = 2,					\
> -	}
> -
>  #define airoha_pinctrl_get_pullup_conf(pinctrl, pin, val)			\
>  	airoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_PULLUP,		\
>  				(pin), (val))
> @@ -433,1935 +74,6 @@ static const u32 irq_edge_regs[] = {
>  	REG_GPIO_INT_EDGE3
>  };
>  
> -static struct pinctrl_pin_desc en7581_pinctrl_pins[] = {
> -	PINCTRL_PIN(0, "uart1_txd"),
> -	PINCTRL_PIN(1, "uart1_rxd"),
> -	PINCTRL_PIN(2, "i2c_scl"),
> -	PINCTRL_PIN(3, "i2c_sda"),
> -	PINCTRL_PIN(4, "spi_cs0"),
> -	PINCTRL_PIN(5, "spi_clk"),
> -	PINCTRL_PIN(6, "spi_mosi"),
> -	PINCTRL_PIN(7, "spi_miso"),
> -	PINCTRL_PIN(13, "gpio0"),
> -	PINCTRL_PIN(14, "gpio1"),
> -	PINCTRL_PIN(15, "gpio2"),
> -	PINCTRL_PIN(16, "gpio3"),
> -	PINCTRL_PIN(17, "gpio4"),
> -	PINCTRL_PIN(18, "gpio5"),
> -	PINCTRL_PIN(19, "gpio6"),
> -	PINCTRL_PIN(20, "gpio7"),
> -	PINCTRL_PIN(21, "gpio8"),
> -	PINCTRL_PIN(22, "gpio9"),
> -	PINCTRL_PIN(23, "gpio10"),
> -	PINCTRL_PIN(24, "gpio11"),
> -	PINCTRL_PIN(25, "gpio12"),
> -	PINCTRL_PIN(26, "gpio13"),
> -	PINCTRL_PIN(27, "gpio14"),
> -	PINCTRL_PIN(28, "gpio15"),
> -	PINCTRL_PIN(29, "gpio16"),
> -	PINCTRL_PIN(30, "gpio17"),
> -	PINCTRL_PIN(31, "gpio18"),
> -	PINCTRL_PIN(32, "gpio19"),
> -	PINCTRL_PIN(33, "gpio20"),
> -	PINCTRL_PIN(34, "gpio21"),
> -	PINCTRL_PIN(35, "gpio22"),
> -	PINCTRL_PIN(36, "gpio23"),
> -	PINCTRL_PIN(37, "gpio24"),
> -	PINCTRL_PIN(38, "gpio25"),
> -	PINCTRL_PIN(39, "gpio26"),
> -	PINCTRL_PIN(40, "gpio27"),
> -	PINCTRL_PIN(41, "gpio28"),
> -	PINCTRL_PIN(42, "gpio29"),
> -	PINCTRL_PIN(43, "gpio30"),
> -	PINCTRL_PIN(44, "gpio31"),
> -	PINCTRL_PIN(45, "gpio32"),
> -	PINCTRL_PIN(46, "gpio33"),
> -	PINCTRL_PIN(47, "gpio34"),
> -	PINCTRL_PIN(48, "gpio35"),
> -	PINCTRL_PIN(49, "gpio36"),
> -	PINCTRL_PIN(50, "gpio37"),
> -	PINCTRL_PIN(51, "gpio38"),
> -	PINCTRL_PIN(52, "gpio39"),
> -	PINCTRL_PIN(53, "gpio40"),
> -	PINCTRL_PIN(54, "gpio41"),
> -	PINCTRL_PIN(55, "gpio42"),
> -	PINCTRL_PIN(56, "gpio43"),
> -	PINCTRL_PIN(57, "gpio44"),
> -	PINCTRL_PIN(58, "gpio45"),
> -	PINCTRL_PIN(59, "gpio46"),
> -	PINCTRL_PIN(60, "pcie_reset0"),
> -	PINCTRL_PIN(61, "pcie_reset1"),
> -	PINCTRL_PIN(62, "pcie_reset2"),
> -};
> -
> -static const int en7581_pon_pins[] = { 49, 50, 51, 52, 53, 54 };
> -static const int en7581_pon_tod_1pps_pins[] = { 46 };
> -static const int en7581_gsw_tod_1pps_pins[] = { 46 };
> -static const int en7581_sipo_pins[] = { 16, 17 };
> -static const int en7581_sipo_rclk_pins[] = { 16, 17, 43 };
> -static const int en7581_mdio_pins[] = { 14, 15 };
> -static const int en7581_uart2_pins[] = { 48, 55 };
> -static const int en7581_uart2_cts_rts_pins[] = { 46, 47 };
> -static const int en7581_hsuart_pins[] = { 28, 29 };
> -static const int en7581_hsuart_cts_rts_pins[] = { 26, 27 };
> -static const int en7581_uart4_pins[] = { 38, 39 };
> -static const int en7581_uart5_pins[] = { 18, 19 };
> -static const int en7581_i2c0_pins[] = { 2, 3 };
> -static const int en7581_i2c1_pins[] = { 14, 15 };
> -static const int en7581_jtag_udi_pins[] = { 16, 17, 18, 19, 20 };
> -static const int en7581_jtag_dfd_pins[] = { 16, 17, 18, 19, 20 };
> -static const int en7581_i2s_pins[] = { 26, 27, 28, 29 };
> -static const int en7581_pcm1_pins[] = { 22, 23, 24, 25 };
> -static const int en7581_pcm2_pins[] = { 18, 19, 20, 21 };
> -static const int en7581_spi_quad_pins[] = { 32, 33 };
> -static const int en7581_spi_pins[] = { 4, 5, 6, 7 };
> -static const int en7581_spi_cs1_pins[] = { 34 };
> -static const int en7581_pcm_spi_pins[] = { 18, 19, 20, 21, 22, 23, 24, 25 };
> -static const int en7581_pcm_spi_int_pins[] = { 14 };
> -static const int en7581_pcm_spi_rst_pins[] = { 15 };
> -static const int en7581_pcm_spi_cs1_pins[] = { 43 };
> -static const int en7581_pcm_spi_cs2_pins[] = { 40 };
> -static const int en7581_pcm_spi_cs2_p128_pins[] = { 40 };
> -static const int en7581_pcm_spi_cs2_p156_pins[] = { 40 };
> -static const int en7581_pcm_spi_cs3_pins[] = { 41 };
> -static const int en7581_pcm_spi_cs4_pins[] = { 42 };
> -static const int en7581_emmc_pins[] = { 4, 5, 6, 30, 31, 32, 33, 34, 35, 36, 37 };
> -static const int en7581_pnand_pins[] = { 4, 5, 6, 7, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42 };
> -static const int en7581_gpio0_pins[] = { 13 };
> -static const int en7581_gpio1_pins[] = { 14 };
> -static const int en7581_gpio2_pins[] = { 15 };
> -static const int en7581_gpio3_pins[] = { 16 };
> -static const int en7581_gpio4_pins[] = { 17 };
> -static const int en7581_gpio5_pins[] = { 18 };
> -static const int en7581_gpio6_pins[] = { 19 };
> -static const int en7581_gpio7_pins[] = { 20 };
> -static const int en7581_gpio8_pins[] = { 21 };
> -static const int en7581_gpio9_pins[] = { 22 };
> -static const int en7581_gpio10_pins[] = { 23 };
> -static const int en7581_gpio11_pins[] = { 24 };
> -static const int en7581_gpio12_pins[] = { 25 };
> -static const int en7581_gpio13_pins[] = { 26 };
> -static const int en7581_gpio14_pins[] = { 27 };
> -static const int en7581_gpio15_pins[] = { 28 };
> -static const int en7581_gpio16_pins[] = { 29 };
> -static const int en7581_gpio17_pins[] = { 30 };
> -static const int en7581_gpio18_pins[] = { 31 };
> -static const int en7581_gpio19_pins[] = { 32 };
> -static const int en7581_gpio20_pins[] = { 33 };
> -static const int en7581_gpio21_pins[] = { 34 };
> -static const int en7581_gpio22_pins[] = { 35 };
> -static const int en7581_gpio23_pins[] = { 36 };
> -static const int en7581_gpio24_pins[] = { 37 };
> -static const int en7581_gpio25_pins[] = { 38 };
> -static const int en7581_gpio26_pins[] = { 39 };
> -static const int en7581_gpio27_pins[] = { 40 };
> -static const int en7581_gpio28_pins[] = { 41 };
> -static const int en7581_gpio29_pins[] = { 42 };
> -static const int en7581_gpio30_pins[] = { 43 };
> -static const int en7581_gpio31_pins[] = { 44 };
> -static const int en7581_gpio32_pins[] = { 45 };
> -static const int en7581_gpio33_pins[] = { 46 };
> -static const int en7581_gpio34_pins[] = { 47 };
> -static const int en7581_gpio35_pins[] = { 48 };
> -static const int en7581_gpio36_pins[] = { 49 };
> -static const int en7581_gpio37_pins[] = { 50 };
> -static const int en7581_gpio38_pins[] = { 51 };
> -static const int en7581_gpio39_pins[] = { 52 };
> -static const int en7581_gpio40_pins[] = { 53 };
> -static const int en7581_gpio41_pins[] = { 54 };
> -static const int en7581_gpio42_pins[] = { 55 };
> -static const int en7581_gpio43_pins[] = { 56 };
> -static const int en7581_gpio44_pins[] = { 57 };
> -static const int en7581_gpio45_pins[] = { 58 };
> -static const int en7581_gpio46_pins[] = { 59 };
> -static const int en7581_gpio47_pins[] = { 60 };
> -static const int en7581_gpio48_pins[] = { 61 };
> -static const int en7581_gpio49_pins[] = { 62 };
> -static const int en7581_pcie_reset0_pins[] = { 60 };
> -static const int en7581_pcie_reset1_pins[] = { 61 };
> -static const int en7581_pcie_reset2_pins[] = { 62 };
> -
> -static const struct pingroup en7581_pinctrl_groups[] = {
> -	PINCTRL_PIN_GROUP("pon", en7581_pon),
> -	PINCTRL_PIN_GROUP("pon_tod_1pps", en7581_pon_tod_1pps),
> -	PINCTRL_PIN_GROUP("gsw_tod_1pps", en7581_gsw_tod_1pps),
> -	PINCTRL_PIN_GROUP("sipo", en7581_sipo),
> -	PINCTRL_PIN_GROUP("sipo_rclk", en7581_sipo_rclk),
> -	PINCTRL_PIN_GROUP("mdio", en7581_mdio),
> -	PINCTRL_PIN_GROUP("uart2", en7581_uart2),
> -	PINCTRL_PIN_GROUP("uart2_cts_rts", en7581_uart2_cts_rts),
> -	PINCTRL_PIN_GROUP("hsuart", en7581_hsuart),
> -	PINCTRL_PIN_GROUP("hsuart_cts_rts", en7581_hsuart_cts_rts),
> -	PINCTRL_PIN_GROUP("uart4", en7581_uart4),
> -	PINCTRL_PIN_GROUP("uart5", en7581_uart5),
> -	PINCTRL_PIN_GROUP("i2c0", en7581_i2c0),
> -	PINCTRL_PIN_GROUP("i2c1", en7581_i2c1),
> -	PINCTRL_PIN_GROUP("jtag_udi", en7581_jtag_udi),
> -	PINCTRL_PIN_GROUP("jtag_dfd", en7581_jtag_dfd),
> -	PINCTRL_PIN_GROUP("i2s", en7581_i2s),
> -	PINCTRL_PIN_GROUP("pcm1", en7581_pcm1),
> -	PINCTRL_PIN_GROUP("pcm2", en7581_pcm2),
> -	PINCTRL_PIN_GROUP("spi", en7581_spi),
> -	PINCTRL_PIN_GROUP("spi_quad", en7581_spi_quad),
> -	PINCTRL_PIN_GROUP("spi_cs1", en7581_spi_cs1),
> -	PINCTRL_PIN_GROUP("pcm_spi", en7581_pcm_spi),
> -	PINCTRL_PIN_GROUP("pcm_spi_int", en7581_pcm_spi_int),
> -	PINCTRL_PIN_GROUP("pcm_spi_rst", en7581_pcm_spi_rst),
> -	PINCTRL_PIN_GROUP("pcm_spi_cs1", en7581_pcm_spi_cs1),
> -	PINCTRL_PIN_GROUP("pcm_spi_cs2_p128", en7581_pcm_spi_cs2_p128),
> -	PINCTRL_PIN_GROUP("pcm_spi_cs2_p156", en7581_pcm_spi_cs2_p156),
> -	PINCTRL_PIN_GROUP("pcm_spi_cs2", en7581_pcm_spi_cs2),
> -	PINCTRL_PIN_GROUP("pcm_spi_cs3", en7581_pcm_spi_cs3),
> -	PINCTRL_PIN_GROUP("pcm_spi_cs4", en7581_pcm_spi_cs4),
> -	PINCTRL_PIN_GROUP("emmc", en7581_emmc),
> -	PINCTRL_PIN_GROUP("pnand", en7581_pnand),
> -	PINCTRL_PIN_GROUP("gpio0", en7581_gpio0),
> -	PINCTRL_PIN_GROUP("gpio1", en7581_gpio1),
> -	PINCTRL_PIN_GROUP("gpio2", en7581_gpio2),
> -	PINCTRL_PIN_GROUP("gpio3", en7581_gpio3),
> -	PINCTRL_PIN_GROUP("gpio4", en7581_gpio4),
> -	PINCTRL_PIN_GROUP("gpio5", en7581_gpio5),
> -	PINCTRL_PIN_GROUP("gpio6", en7581_gpio6),
> -	PINCTRL_PIN_GROUP("gpio7", en7581_gpio7),
> -	PINCTRL_PIN_GROUP("gpio8", en7581_gpio8),
> -	PINCTRL_PIN_GROUP("gpio9", en7581_gpio9),
> -	PINCTRL_PIN_GROUP("gpio10", en7581_gpio10),
> -	PINCTRL_PIN_GROUP("gpio11", en7581_gpio11),
> -	PINCTRL_PIN_GROUP("gpio12", en7581_gpio12),
> -	PINCTRL_PIN_GROUP("gpio13", en7581_gpio13),
> -	PINCTRL_PIN_GROUP("gpio14", en7581_gpio14),
> -	PINCTRL_PIN_GROUP("gpio15", en7581_gpio15),
> -	PINCTRL_PIN_GROUP("gpio16", en7581_gpio16),
> -	PINCTRL_PIN_GROUP("gpio17", en7581_gpio17),
> -	PINCTRL_PIN_GROUP("gpio18", en7581_gpio18),
> -	PINCTRL_PIN_GROUP("gpio19", en7581_gpio19),
> -	PINCTRL_PIN_GROUP("gpio20", en7581_gpio20),
> -	PINCTRL_PIN_GROUP("gpio21", en7581_gpio21),
> -	PINCTRL_PIN_GROUP("gpio22", en7581_gpio22),
> -	PINCTRL_PIN_GROUP("gpio23", en7581_gpio23),
> -	PINCTRL_PIN_GROUP("gpio24", en7581_gpio24),
> -	PINCTRL_PIN_GROUP("gpio25", en7581_gpio25),
> -	PINCTRL_PIN_GROUP("gpio26", en7581_gpio26),
> -	PINCTRL_PIN_GROUP("gpio27", en7581_gpio27),
> -	PINCTRL_PIN_GROUP("gpio28", en7581_gpio28),
> -	PINCTRL_PIN_GROUP("gpio29", en7581_gpio29),
> -	PINCTRL_PIN_GROUP("gpio30", en7581_gpio30),
> -	PINCTRL_PIN_GROUP("gpio31", en7581_gpio31),
> -	PINCTRL_PIN_GROUP("gpio32", en7581_gpio32),
> -	PINCTRL_PIN_GROUP("gpio33", en7581_gpio33),
> -	PINCTRL_PIN_GROUP("gpio34", en7581_gpio34),
> -	PINCTRL_PIN_GROUP("gpio35", en7581_gpio35),
> -	PINCTRL_PIN_GROUP("gpio36", en7581_gpio36),
> -	PINCTRL_PIN_GROUP("gpio37", en7581_gpio37),
> -	PINCTRL_PIN_GROUP("gpio38", en7581_gpio38),
> -	PINCTRL_PIN_GROUP("gpio39", en7581_gpio39),
> -	PINCTRL_PIN_GROUP("gpio40", en7581_gpio40),
> -	PINCTRL_PIN_GROUP("gpio41", en7581_gpio41),
> -	PINCTRL_PIN_GROUP("gpio42", en7581_gpio42),
> -	PINCTRL_PIN_GROUP("gpio43", en7581_gpio43),
> -	PINCTRL_PIN_GROUP("gpio44", en7581_gpio44),
> -	PINCTRL_PIN_GROUP("gpio45", en7581_gpio45),
> -	PINCTRL_PIN_GROUP("gpio46", en7581_gpio46),
> -	PINCTRL_PIN_GROUP("gpio47", en7581_gpio47),
> -	PINCTRL_PIN_GROUP("gpio48", en7581_gpio48),
> -	PINCTRL_PIN_GROUP("gpio49", en7581_gpio49),
> -	PINCTRL_PIN_GROUP("pcie_reset0", en7581_pcie_reset0),
> -	PINCTRL_PIN_GROUP("pcie_reset1", en7581_pcie_reset1),
> -	PINCTRL_PIN_GROUP("pcie_reset2", en7581_pcie_reset2),
> -};
> -
> -static struct pinctrl_pin_desc an7583_pinctrl_pins[] = {
> -	PINCTRL_PIN(2, "gpio0"),
> -	PINCTRL_PIN(3, "gpio1"),
> -	PINCTRL_PIN(4, "gpio2"),
> -	PINCTRL_PIN(5, "gpio3"),
> -	PINCTRL_PIN(6, "gpio4"),
> -	PINCTRL_PIN(7, "gpio5"),
> -	PINCTRL_PIN(8, "gpio6"),
> -	PINCTRL_PIN(9, "gpio7"),
> -	PINCTRL_PIN(10, "gpio8"),
> -	PINCTRL_PIN(11, "gpio9"),
> -	PINCTRL_PIN(12, "gpio10"),
> -	PINCTRL_PIN(13, "gpio11"),
> -	PINCTRL_PIN(14, "gpio12"),
> -	PINCTRL_PIN(15, "gpio13"),
> -	PINCTRL_PIN(16, "gpio14"),
> -	PINCTRL_PIN(17, "gpio15"),
> -	PINCTRL_PIN(18, "gpio16"),
> -	PINCTRL_PIN(19, "gpio17"),
> -	PINCTRL_PIN(20, "gpio18"),
> -	PINCTRL_PIN(21, "gpio19"),
> -	PINCTRL_PIN(22, "gpio20"),
> -	PINCTRL_PIN(23, "gpio21"),
> -	PINCTRL_PIN(24, "gpio22"),
> -	PINCTRL_PIN(25, "gpio23"),
> -	PINCTRL_PIN(26, "gpio24"),
> -	PINCTRL_PIN(27, "gpio25"),
> -	PINCTRL_PIN(28, "gpio26"),
> -	PINCTRL_PIN(29, "gpio27"),
> -	PINCTRL_PIN(30, "gpio28"),
> -	PINCTRL_PIN(31, "gpio29"),
> -	PINCTRL_PIN(32, "gpio30"),
> -	PINCTRL_PIN(33, "gpio31"),
> -	PINCTRL_PIN(34, "gpio32"),
> -	PINCTRL_PIN(35, "gpio33"),
> -	PINCTRL_PIN(36, "gpio34"),
> -	PINCTRL_PIN(37, "gpio35"),
> -	PINCTRL_PIN(38, "gpio36"),
> -	PINCTRL_PIN(39, "gpio37"),
> -	PINCTRL_PIN(40, "gpio38"),
> -	PINCTRL_PIN(41, "i2c0_scl"),
> -	PINCTRL_PIN(42, "i2c0_sda"),
> -	PINCTRL_PIN(43, "i2c1_scl"),
> -	PINCTRL_PIN(44, "i2c1_sda"),
> -	PINCTRL_PIN(45, "spi_clk"),
> -	PINCTRL_PIN(46, "spi_cs"),
> -	PINCTRL_PIN(47, "spi_mosi"),
> -	PINCTRL_PIN(48, "spi_miso"),
> -	PINCTRL_PIN(49, "uart_txd"),
> -	PINCTRL_PIN(50, "uart_rxd"),
> -	PINCTRL_PIN(51, "pcie_reset0"),
> -	PINCTRL_PIN(52, "pcie_reset1"),
> -	PINCTRL_PIN(53, "mdc_0"),
> -	PINCTRL_PIN(54, "mdio_0"),
> -};
> -
> -static const int an7583_pon_pins[] = { 15, 16, 17, 18, 19, 20 };
> -static const int an7583_pon_tod_1pps_pins[] = { 32 };
> -static const int an7583_gsw_tod_1pps_pins[] = { 32 };
> -static const int an7583_sipo_pins[] = { 34, 35 };
> -static const int an7583_sipo_rclk_pins[] = { 34, 35, 33 };
> -static const int an7583_mdio_pins[] = { 43, 44 };
> -static const int an7583_uart2_pins[] = { 34, 35 };
> -static const int an7583_uart2_cts_rts_pins[] = { 32, 33 };
> -static const int an7583_hsuart_pins[] = { 30, 31 };
> -static const int an7583_hsuart_cts_rts_pins[] = { 28, 29 };
> -static const int an7583_npu_uart_pins[] = { 7, 8 };
> -static const int an7583_uart4_pins[] = { 7, 8 };
> -static const int an7583_uart5_pins[] = { 23, 24 };
> -static const int an7583_i2c0_pins[] = { 41, 42 };
> -static const int an7583_i2c1_pins[] = { 43, 44 };
> -static const int an7583_jtag_udi_pins[] = { 23, 24, 22, 25, 26 };
> -static const int an7583_jtag_dfd_pins[] = { 23, 24, 22, 25, 26 };
> -static const int an7583_pcm1_pins[] = { 10, 11, 12, 13, 14 };
> -static const int an7583_pcm2_pins[] = { 28, 29, 30, 31, 24 };
> -static const int an7583_spi_pins[] = { 28, 29, 30, 31 };
> -static const int an7583_spi_quad_pins[] = { 25, 26 };
> -static const int an7583_spi_cs1_pins[] = { 27 };
> -static const int an7583_pcm_spi_pins[] = { 28, 29, 30, 31, 10, 11, 12, 13 };
> -static const int an7583_pcm_spi_rst_pins[] = { 14 };
> -static const int an7583_pcm_spi_cs1_pins[] = { 24 };
> -static const int an7583_emmc_pins[] = { 7, 8, 9, 22, 23, 24, 25, 26, 45, 46, 47 };
> -static const int an7583_pnand_pins[] = { 7, 8, 9, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 45, 46, 47, 48 };
> -static const int an7583_gpio0_pins[] = { 2 };
> -static const int an7583_gpio1_pins[] = { 3 };
> -static const int an7583_gpio2_pins[] = { 4 };
> -static const int an7583_gpio3_pins[] = { 5 };
> -static const int an7583_gpio4_pins[] = { 6 };
> -static const int an7583_gpio5_pins[] = { 7 };
> -static const int an7583_gpio6_pins[] = { 8 };
> -static const int an7583_gpio7_pins[] = { 9 };
> -static const int an7583_gpio8_pins[] = { 10 };
> -static const int an7583_gpio9_pins[] = { 11 };
> -static const int an7583_gpio10_pins[] = { 12 };
> -static const int an7583_gpio11_pins[] = { 13 };
> -static const int an7583_gpio12_pins[] = { 14 };
> -static const int an7583_gpio13_pins[] = { 15 };
> -static const int an7583_gpio14_pins[] = { 16 };
> -static const int an7583_gpio15_pins[] = { 17 };
> -static const int an7583_gpio16_pins[] = { 18 };
> -static const int an7583_gpio17_pins[] = { 19 };
> -static const int an7583_gpio18_pins[] = { 20 };
> -static const int an7583_gpio19_pins[] = { 21 };
> -static const int an7583_gpio20_pins[] = { 22 };
> -static const int an7583_gpio21_pins[] = { 23 };
> -static const int an7583_gpio22_pins[] = { 24 };
> -static const int an7583_gpio23_pins[] = { 25 };
> -static const int an7583_gpio24_pins[] = { 26 };
> -static const int an7583_gpio25_pins[] = { 27 };
> -static const int an7583_gpio26_pins[] = { 28 };
> -static const int an7583_gpio27_pins[] = { 29 };
> -static const int an7583_gpio28_pins[] = { 30 };
> -static const int an7583_gpio29_pins[] = { 31 };
> -static const int an7583_gpio30_pins[] = { 32 };
> -static const int an7583_gpio31_pins[] = { 33 };
> -static const int an7583_gpio32_pins[] = { 34 };
> -static const int an7583_gpio33_pins[] = { 35 };
> -static const int an7583_gpio34_pins[] = { 36 };
> -static const int an7583_gpio35_pins[] = { 37 };
> -static const int an7583_gpio36_pins[] = { 38 };
> -static const int an7583_gpio37_pins[] = { 39 };
> -static const int an7583_gpio38_pins[] = { 40 };
> -static const int an7583_gpio39_pins[] = { 41 };
> -static const int an7583_gpio40_pins[] = { 42 };
> -static const int an7583_gpio41_pins[] = { 43 };
> -static const int an7583_gpio42_pins[] = { 44 };
> -static const int an7583_gpio43_pins[] = { 45 };
> -static const int an7583_gpio44_pins[] = { 46 };
> -static const int an7583_gpio45_pins[] = { 47 };
> -static const int an7583_gpio46_pins[] = { 48 };
> -static const int an7583_gpio47_pins[] = { 49 };
> -static const int an7583_gpio48_pins[] = { 50 };
> -static const int an7583_gpio49_pins[] = { 51 };
> -static const int an7583_gpio50_pins[] = { 52 };
> -static const int an7583_gpio51_pins[] = { 53 };
> -static const int an7583_gpio52_pins[] = { 54 };
> -static const int an7583_pcie_reset0_pins[] = { 51 };
> -static const int an7583_pcie_reset1_pins[] = { 52 };
> -
> -static const struct pingroup an7583_pinctrl_groups[] = {
> -	PINCTRL_PIN_GROUP("pon", an7583_pon),
> -	PINCTRL_PIN_GROUP("pon_tod_1pps", an7583_pon_tod_1pps),
> -	PINCTRL_PIN_GROUP("gsw_tod_1pps", an7583_gsw_tod_1pps),
> -	PINCTRL_PIN_GROUP("sipo", an7583_sipo),
> -	PINCTRL_PIN_GROUP("sipo_rclk", an7583_sipo_rclk),
> -	PINCTRL_PIN_GROUP("mdio", an7583_mdio),
> -	PINCTRL_PIN_GROUP("uart2", an7583_uart2),
> -	PINCTRL_PIN_GROUP("uart2_cts_rts", an7583_uart2_cts_rts),
> -	PINCTRL_PIN_GROUP("hsuart", an7583_hsuart),
> -	PINCTRL_PIN_GROUP("hsuart_cts_rts", an7583_hsuart_cts_rts),
> -	PINCTRL_PIN_GROUP("npu_uart", an7583_npu_uart),
> -	PINCTRL_PIN_GROUP("uart4", an7583_uart4),
> -	PINCTRL_PIN_GROUP("uart5", an7583_uart5),
> -	PINCTRL_PIN_GROUP("i2c0", an7583_i2c0),
> -	PINCTRL_PIN_GROUP("i2c1", an7583_i2c1),
> -	PINCTRL_PIN_GROUP("jtag_udi", an7583_jtag_udi),
> -	PINCTRL_PIN_GROUP("jtag_dfd", an7583_jtag_dfd),
> -	PINCTRL_PIN_GROUP("pcm1", an7583_pcm1),
> -	PINCTRL_PIN_GROUP("pcm2", an7583_pcm2),
> -	PINCTRL_PIN_GROUP("spi", an7583_spi),
> -	PINCTRL_PIN_GROUP("spi_quad", an7583_spi_quad),
> -	PINCTRL_PIN_GROUP("spi_cs1", an7583_spi_cs1),
> -	PINCTRL_PIN_GROUP("pcm_spi", an7583_pcm_spi),
> -	PINCTRL_PIN_GROUP("pcm_spi_rst", an7583_pcm_spi_rst),
> -	PINCTRL_PIN_GROUP("pcm_spi_cs1", an7583_pcm_spi_cs1),
> -	PINCTRL_PIN_GROUP("emmc", an7583_emmc),
> -	PINCTRL_PIN_GROUP("pnand", an7583_pnand),
> -	PINCTRL_PIN_GROUP("gpio0", an7583_gpio0),
> -	PINCTRL_PIN_GROUP("gpio1", an7583_gpio1),
> -	PINCTRL_PIN_GROUP("gpio2", an7583_gpio2),
> -	PINCTRL_PIN_GROUP("gpio3", an7583_gpio3),
> -	PINCTRL_PIN_GROUP("gpio4", an7583_gpio4),
> -	PINCTRL_PIN_GROUP("gpio5", an7583_gpio5),
> -	PINCTRL_PIN_GROUP("gpio6", an7583_gpio6),
> -	PINCTRL_PIN_GROUP("gpio7", an7583_gpio7),
> -	PINCTRL_PIN_GROUP("gpio8", an7583_gpio8),
> -	PINCTRL_PIN_GROUP("gpio9", an7583_gpio9),
> -	PINCTRL_PIN_GROUP("gpio10", an7583_gpio10),
> -	PINCTRL_PIN_GROUP("gpio11", an7583_gpio11),
> -	PINCTRL_PIN_GROUP("gpio12", an7583_gpio12),
> -	PINCTRL_PIN_GROUP("gpio13", an7583_gpio13),
> -	PINCTRL_PIN_GROUP("gpio14", an7583_gpio14),
> -	PINCTRL_PIN_GROUP("gpio15", an7583_gpio15),
> -	PINCTRL_PIN_GROUP("gpio16", an7583_gpio16),
> -	PINCTRL_PIN_GROUP("gpio17", an7583_gpio17),
> -	PINCTRL_PIN_GROUP("gpio18", an7583_gpio18),
> -	PINCTRL_PIN_GROUP("gpio19", an7583_gpio19),
> -	PINCTRL_PIN_GROUP("gpio20", an7583_gpio20),
> -	PINCTRL_PIN_GROUP("gpio21", an7583_gpio21),
> -	PINCTRL_PIN_GROUP("gpio22", an7583_gpio22),
> -	PINCTRL_PIN_GROUP("gpio23", an7583_gpio23),
> -	PINCTRL_PIN_GROUP("gpio24", an7583_gpio24),
> -	PINCTRL_PIN_GROUP("gpio25", an7583_gpio25),
> -	PINCTRL_PIN_GROUP("gpio26", an7583_gpio26),
> -	PINCTRL_PIN_GROUP("gpio27", an7583_gpio27),
> -	PINCTRL_PIN_GROUP("gpio28", an7583_gpio28),
> -	PINCTRL_PIN_GROUP("gpio29", an7583_gpio29),
> -	PINCTRL_PIN_GROUP("gpio30", an7583_gpio30),
> -	PINCTRL_PIN_GROUP("gpio31", an7583_gpio31),
> -	PINCTRL_PIN_GROUP("gpio32", an7583_gpio32),
> -	PINCTRL_PIN_GROUP("gpio33", an7583_gpio33),
> -	PINCTRL_PIN_GROUP("gpio34", an7583_gpio34),
> -	PINCTRL_PIN_GROUP("gpio35", an7583_gpio35),
> -	PINCTRL_PIN_GROUP("gpio36", an7583_gpio36),
> -	PINCTRL_PIN_GROUP("gpio37", an7583_gpio37),
> -	PINCTRL_PIN_GROUP("gpio38", an7583_gpio38),
> -	PINCTRL_PIN_GROUP("gpio39", an7583_gpio39),
> -	PINCTRL_PIN_GROUP("gpio40", an7583_gpio40),
> -	PINCTRL_PIN_GROUP("gpio41", an7583_gpio41),
> -	PINCTRL_PIN_GROUP("gpio42", an7583_gpio42),
> -	PINCTRL_PIN_GROUP("gpio43", an7583_gpio43),
> -	PINCTRL_PIN_GROUP("gpio44", an7583_gpio44),
> -	PINCTRL_PIN_GROUP("gpio45", an7583_gpio45),
> -	PINCTRL_PIN_GROUP("gpio46", an7583_gpio46),
> -	PINCTRL_PIN_GROUP("gpio47", an7583_gpio47),
> -	PINCTRL_PIN_GROUP("gpio48", an7583_gpio48),
> -	PINCTRL_PIN_GROUP("gpio49", an7583_gpio49),
> -	PINCTRL_PIN_GROUP("gpio50", an7583_gpio50),
> -	PINCTRL_PIN_GROUP("gpio51", an7583_gpio51),
> -	PINCTRL_PIN_GROUP("gpio52", an7583_gpio52),
> -	PINCTRL_PIN_GROUP("pcie_reset0", an7583_pcie_reset0),
> -	PINCTRL_PIN_GROUP("pcie_reset1", an7583_pcie_reset1),
> -};
> -
> -static const char *const pon_groups[] = { "pon" };
> -static const char *const tod_1pps_groups[] = { "pon_tod_1pps", "gsw_tod_1pps" };
> -static const char *const sipo_groups[] = { "sipo", "sipo_rclk" };
> -static const char *const mdio_groups[] = { "mdio" };
> -static const char *const an7583_mdio_groups[] = { "mdio" };
> -static const char *const uart_groups[] = { "uart2", "uart2_cts_rts", "hsuart",
> -					   "hsuart_cts_rts", "uart4",
> -					   "uart5" };
> -static const char *const i2c_groups[] = { "i2c1" };
> -static const char *const jtag_groups[] = { "jtag_udi", "jtag_dfd" };
> -static const char *const pcm_groups[] = { "pcm1", "pcm2" };
> -static const char *const spi_groups[] = { "spi_quad", "spi_cs1" };
> -static const char *const pcm_spi_groups[] = { "pcm_spi", "pcm_spi_int",
> -					      "pcm_spi_rst", "pcm_spi_cs1",
> -					      "pcm_spi_cs2_p156",
> -					      "pcm_spi_cs2_p128",
> -					      "pcm_spi_cs3", "pcm_spi_cs4" };
> -static const char *const an7583_pcm_spi_groups[] = { "pcm_spi",
> -						     "pcm_spi_rst", "pcm_spi_cs1" };
> -static const char *const i2s_groups[] = { "i2s" };
> -static const char *const emmc_groups[] = { "emmc" };
> -static const char *const pnand_groups[] = { "pnand" };
> -static const char *const gpio_groups[] = { "gpio47", "gpio48", "gpio49" };
> -static const char *const pcie_reset_groups[] = { "pcie_reset0", "pcie_reset1",
> -						 "pcie_reset2" };
> -static const char *const an7583_gpio_groups[] = { "gpio39", "gpio40", "gpio41",
> -						  "gpio42", "gpio43", "gpio44",
> -						  "gpio45", "gpio46", "gpio47",
> -						  "gpio48", "gpio49", "gpio50",
> -						  "gpio51", "gpio52" };
> -static const char *const an7583_pcie_reset_groups[] = { "pcie_reset0", "pcie_reset1" };
> -static const char *const pwm_groups[] = { "gpio0", "gpio1",
> -					  "gpio2", "gpio3",
> -					  "gpio4", "gpio5",
> -					  "gpio6", "gpio7",
> -					  "gpio8", "gpio9",
> -					  "gpio10", "gpio11",
> -					  "gpio12", "gpio13",
> -					  "gpio14", "gpio15",
> -					  "gpio16", "gpio17",
> -					  "gpio18", "gpio19",
> -					  "gpio20", "gpio21",
> -					  "gpio22", "gpio23",
> -					  "gpio24", "gpio25",
> -					  "gpio26", "gpio27",
> -					  "gpio28", "gpio29",
> -					  "gpio30", "gpio31",
> -					  "gpio36", "gpio37",
> -					  "gpio38", "gpio39",
> -					  "gpio40", "gpio41",
> -					  "gpio42", "gpio43",
> -					  "gpio44", "gpio45",
> -					  "gpio46", "gpio47",
> -					  "gpio48", "gpio49" };
> -static const char *const an7583_pwm_groups[] = { "gpio0", "gpio1",
> -						 "gpio2", "gpio3",
> -						 "gpio4", "gpio5",
> -						 "gpio6", "gpio7",
> -						 "gpio8", "gpio9",
> -						 "gpio10", "gpio11",
> -						 "gpio12", "gpio13",
> -						 "gpio14", "gpio15",
> -						 "gpio16", "gpio17",
> -						 "gpio18", "gpio19",
> -						 "gpio20", "gpio21",
> -						 "gpio22", "gpio23",
> -						 "gpio24", "gpio25",
> -						 "gpio26", "gpio27",
> -						 "gpio28", "gpio29",
> -						 "gpio30", "gpio31",
> -						 "gpio36", "gpio37",
> -						 "gpio38", "gpio39",
> -						 "gpio40", "gpio41",
> -						 "gpio42", "gpio43",
> -						 "gpio44", "gpio45",
> -						 "gpio46", "gpio47",
> -						 "gpio48", "gpio49",
> -						 "gpio50", "gpio51" };
> -static const char *const phy1_led0_groups[] = { "gpio33", "gpio34",
> -						"gpio35", "gpio42" };
> -static const char *const phy2_led0_groups[] = { "gpio33", "gpio34",
> -						"gpio35", "gpio42" };
> -static const char *const phy3_led0_groups[] = { "gpio33", "gpio34",
> -						"gpio35", "gpio42" };
> -static const char *const phy4_led0_groups[] = { "gpio33", "gpio34",
> -						"gpio35", "gpio42" };
> -static const char *const phy1_led1_groups[] = { "gpio43", "gpio44",
> -						"gpio45", "gpio46" };
> -static const char *const phy2_led1_groups[] = { "gpio43", "gpio44",
> -						"gpio45", "gpio46" };
> -static const char *const phy3_led1_groups[] = { "gpio43", "gpio44",
> -						"gpio45", "gpio46" };
> -static const char *const phy4_led1_groups[] = { "gpio43", "gpio44",
> -						"gpio45", "gpio46" };
> -static const char *const an7583_phy1_led0_groups[] = { "gpio1", "gpio2",
> -							"gpio3", "gpio4" };
> -static const char *const an7583_phy2_led0_groups[] = { "gpio1", "gpio2",
> -							"gpio3", "gpio4" };
> -static const char *const an7583_phy3_led0_groups[] = { "gpio1", "gpio2",
> -							"gpio3", "gpio4" };
> -static const char *const an7583_phy4_led0_groups[] = { "gpio1", "gpio2",
> -							"gpio3", "gpio4" };
> -static const char *const an7583_phy1_led1_groups[] = { "gpio8", "gpio9",
> -							"gpio10", "gpio11" };
> -static const char *const an7583_phy2_led1_groups[] = { "gpio8", "gpio9",
> -							"gpio10", "gpio11" };
> -static const char *const an7583_phy3_led1_groups[] = { "gpio8", "gpio9",
> -							"gpio10", "gpio11" };
> -static const char *const an7583_phy4_led1_groups[] = { "gpio8", "gpio9",
> -							"gpio10", "gpio11" };
> -
> -static const struct airoha_pinctrl_func_group pon_func_group[] = {
> -	{
> -		.name = "pon",
> -		.regmap[0] = {
> -			AIROHA_FUNC_MUX,
> -			REG_GPIO_PON_MODE,
> -			GPIO_PON_MODE_MASK,
> -			GPIO_PON_MODE_MASK
> -		},
> -		.regmap_size = 1,
> -	},
> -};
> -
> -static const struct airoha_pinctrl_func_group tod_1pps_func_group[] = {
> -	{
> -		.name = "pon_tod_1pps",
> -		.regmap[0] = {
> -			AIROHA_FUNC_MUX,
> -			REG_GPIO_2ND_I2C_MODE,
> -			PON_TOD_1PPS_MODE_MASK,
> -			PON_TOD_1PPS_MODE_MASK
> -		},
> -		.regmap_size = 1,
> -	}, {
> -		.name = "gsw_tod_1pps",
> -		.regmap[0] = {
> -			AIROHA_FUNC_MUX,
> -			REG_GPIO_2ND_I2C_MODE,
> -			GSW_TOD_1PPS_MODE_MASK,
> -			GSW_TOD_1PPS_MODE_MASK
> -		},
> -		.regmap_size = 1,
> -	},
> -};
> -
> -static const struct airoha_pinctrl_func_group sipo_func_group[] = {
> -	{
> -		.name = "sipo",
> -		.regmap[0] = {
> -			AIROHA_FUNC_MUX,
> -			REG_GPIO_PON_MODE,
> -			GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK,
> -			GPIO_SIPO_MODE_MASK
> -		},
> -		.regmap_size = 1,
> -	}, {
> -		.name = "sipo_rclk",
> -		.regmap[0] = {
> -			AIROHA_FUNC_MUX,
> -			REG_GPIO_PON_MODE,
> -			GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK,
> -			GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK
> -		},
> -		.regmap_size = 1,
> -	},
> -};
> -
> -static const struct airoha_pinctrl_func_group mdio_func_group[] = {
> -	{
> -		.name = "mdio",
> -		.regmap[0] = {
> -			AIROHA_FUNC_MUX,
> -			REG_GPIO_2ND_I2C_MODE,
> -			GPIO_MDC_IO_MASTER_MODE_MASK,
> -			GPIO_MDC_IO_MASTER_MODE_MASK
> -		},
> -		.regmap[1] = {
> -			AIROHA_FUNC_MUX,
> -			REG_FORCE_GPIO_EN,
> -			FORCE_GPIO_EN(1) | FORCE_GPIO_EN(2),
> -			FORCE_GPIO_EN(1) | FORCE_GPIO_EN(2)
> -		},
> -		.regmap_size = 2,
> -	},
> -};
> -
> -static const struct airoha_pinctrl_func_group an7583_mdio_func_group[] = {
> -	{
> -		.name = "mdio",
> -		.regmap[0] = {
> -			AIROHA_FUNC_MUX,
> -			REG_GPIO_PON_MODE,
> -			GPIO_SGMII_MDIO_MODE_MASK,
> -			GPIO_SGMII_MDIO_MODE_MASK
> -		},
> -		.regmap[1] = {
> -			AIROHA_FUNC_MUX,
> -			REG_GPIO_SPI_CS1_MODE,
> -			GPIO_MDC_IO_MASTER_MODE_MASK,
> -			GPIO_MDC_IO_MASTER_MODE_MASK
> -		},
> -		.regmap_size = 2,
> -	},
> -};
> -
> -static const struct airoha_pinctrl_func_group uart_func_group[] = {
> -	{
> -		.name = "uart2",
> -		.regmap[0] = {
> -			AIROHA_FUNC_MUX,
> -			REG_GPIO_PON_MODE,
> -			GPIO_UART2_MODE_MASK,
> -			GPIO_UART2_MODE_MASK
> -		},
> -		.regmap_size = 1,
> -	}, {
> -		.name = "uart2_cts_rts",
> -		.regmap[0] = {
> -			AIROHA_FUNC_MUX,
> -			REG_GPIO_PON_MODE,
> -			GPIO_UART2_MODE_MASK | GPIO_UART2_CTS_RTS_MODE_MASK,
> -			GPIO_UART2_MODE_MASK | GPIO_UART2_CTS_RTS_MODE_MASK
> -		},
> -		.regmap_size = 1,
> -	}, {
> -		.name = "hsuart",
> -		.regmap[0] = {
> -			AIROHA_FUNC_MUX,
> -			REG_GPIO_PON_MODE,
> -			GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK,
> -			GPIO_HSUART_MODE_MASK
> -		},
> -		.regmap_size = 1,
> -	},
> -	{
> -		.name = "hsuart_cts_rts",
> -		.regmap[0] = {
> -			AIROHA_FUNC_MUX,
> -			REG_GPIO_PON_MODE,
> -			GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK,
> -			GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK
> -		},
> -		.regmap_size = 1,
> -	}, {
> -		.name = "uart4",
> -		.regmap[0] = {
> -			AIROHA_FUNC_MUX,
> -			REG_GPIO_PON_MODE,
> -			GPIO_UART4_MODE_MASK,
> -			GPIO_UART4_MODE_MASK
> -		},
> -		.regmap_size = 1,
> -	}, {
> -		.name = "uart5",
> -		.regmap[0] = {
> -			AIROHA_FUNC_MUX,
> -			REG_GPIO_PON_MODE,
> -			GPIO_UART5_MODE_MASK,
> -			GPIO_UART5_MODE_MASK
> -		},
> -		.regmap_size = 1,
> -	},
> -};
> -
> -static const struct airoha_pinctrl_func_group i2c_func_group[] = {
> -	{
> -		.name = "i2c1",
> -		.regmap[0] = {
> -			AIROHA_FUNC_MUX,
> -			REG_GPIO_2ND_I2C_MODE,
> -			GPIO_2ND_I2C_MODE_MASK,
> -			GPIO_2ND_I2C_MODE_MASK
> -		},
> -		.regmap_size = 1,
> -	},
> -};
> -
> -static const struct airoha_pinctrl_func_group jtag_func_group[] = {
> -	{
> -		.name = "jtag_udi",
> -		.regmap[0] = {
> -			AIROHA_FUNC_MUX,
> -			REG_NPU_UART_EN,
> -			JTAG_UDI_EN_MASK,
> -			JTAG_UDI_EN_MASK
> -		},
> -		.regmap_size = 1,
> -	}, {
> -		.name = "jtag_dfd",
> -		.regmap[0] = {
> -			AIROHA_FUNC_MUX,
> -			REG_NPU_UART_EN,
> -			JTAG_DFD_EN_MASK,
> -			JTAG_DFD_EN_MASK
> -		},
> -		.regmap_size = 1,
> -	},
> -};
> -
> -static const struct airoha_pinctrl_func_group pcm_func_group[] = {
> -	{
> -		.name = "pcm1",
> -		.regmap[0] = {
> -			AIROHA_FUNC_MUX,
> -			REG_GPIO_SPI_CS1_MODE,
> -			GPIO_PCM1_MODE_MASK,
> -			GPIO_PCM1_MODE_MASK
> -		},
> -		.regmap_size = 1,
> -	}, {
> -		.name = "pcm2",
> -		.regmap[0] = {
> -			AIROHA_FUNC_MUX,
> -			REG_GPIO_SPI_CS1_MODE,
> -			GPIO_PCM2_MODE_MASK,
> -			GPIO_PCM2_MODE_MASK
> -		},
> -		.regmap_size = 1,
> -	},
> -};
> -
> -static const struct airoha_pinctrl_func_group spi_func_group[] = {
> -	{
> -		.name = "spi_quad",
> -		.regmap[0] = {
> -			AIROHA_FUNC_MUX,
> -			REG_GPIO_SPI_CS1_MODE,
> -			GPIO_SPI_QUAD_MODE_MASK,
> -			GPIO_SPI_QUAD_MODE_MASK
> -		},
> -		.regmap_size = 1,
> -	}, {
> -		.name = "spi_cs1",
> -		.regmap[0] = {
> -			AIROHA_FUNC_MUX,
> -			REG_GPIO_SPI_CS1_MODE,
> -			GPIO_SPI_CS1_MODE_MASK,
> -			GPIO_SPI_CS1_MODE_MASK
> -		},
> -		.regmap_size = 1,
> -	}, {
> -		.name = "spi_cs2",
> -		.regmap[0] = {
> -			AIROHA_FUNC_MUX,
> -			REG_GPIO_SPI_CS1_MODE,
> -			GPIO_SPI_CS2_MODE_MASK,
> -			GPIO_SPI_CS2_MODE_MASK
> -		},
> -		.regmap_size = 1,
> -	}, {
> -		.name = "spi_cs3",
> -		.regmap[0] = {
> -			AIROHA_FUNC_MUX,
> -			REG_GPIO_SPI_CS1_MODE,
> -			GPIO_SPI_CS3_MODE_MASK,
> -			GPIO_SPI_CS3_MODE_MASK
> -		},
> -		.regmap_size = 1,
> -	}, {
> -		.name = "spi_cs4",
> -		.regmap[0] = {
> -			AIROHA_FUNC_MUX,
> -			REG_GPIO_SPI_CS1_MODE,
> -			GPIO_SPI_CS4_MODE_MASK,
> -			GPIO_SPI_CS4_MODE_MASK
> -		},
> -		.regmap_size = 1,
> -	},
> -};
> -
> -static const struct airoha_pinctrl_func_group pcm_spi_func_group[] = {
> -	{
> -		.name = "pcm_spi",
> -		.regmap[0] = {
> -			AIROHA_FUNC_MUX,
> -			REG_GPIO_SPI_CS1_MODE,
> -			GPIO_PCM_SPI_MODE_MASK,
> -			GPIO_PCM_SPI_MODE_MASK
> -		},
> -		.regmap_size = 1,
> -	}, {
> -		.name = "pcm_spi_int",
> -		.regmap[0] = {
> -			AIROHA_FUNC_MUX,
> -			REG_GPIO_SPI_CS1_MODE,
> -			GPIO_PCM_INT_MODE_MASK,
> -			GPIO_PCM_INT_MODE_MASK
> -		},
> -		.regmap_size = 1,
> -	}, {
> -		.name = "pcm_spi_rst",
> -		.regmap[0] = {
> -			AIROHA_FUNC_MUX,
> -			REG_GPIO_SPI_CS1_MODE,
> -			GPIO_PCM_RESET_MODE_MASK,
> -			GPIO_PCM_RESET_MODE_MASK
> -		},
> -		.regmap_size = 1,
> -	}, {
> -		.name = "pcm_spi_cs1",
> -		.regmap[0] = {
> -			AIROHA_FUNC_MUX,
> -			REG_GPIO_SPI_CS1_MODE,
> -			GPIO_PCM_SPI_CS1_MODE_MASK,
> -			GPIO_PCM_SPI_CS1_MODE_MASK
> -		},
> -		.regmap_size = 1,
> -	}, {
> -		.name = "pcm_spi_cs2_p128",
> -		.regmap[0] = {
> -			AIROHA_FUNC_MUX,
> -			REG_GPIO_SPI_CS1_MODE,
> -			GPIO_PCM_SPI_CS2_MODE_P128_MASK,
> -			GPIO_PCM_SPI_CS2_MODE_P128_MASK
> -		},
> -		.regmap_size = 1,
> -	}, {
> -		.name = "pcm_spi_cs2_p156",
> -		.regmap[0] = {
> -			AIROHA_FUNC_MUX,
> -			REG_GPIO_SPI_CS1_MODE,
> -			GPIO_PCM_SPI_CS2_MODE_P156_MASK,
> -			GPIO_PCM_SPI_CS2_MODE_P156_MASK
> -		},
> -		.regmap_size = 1,
> -	}, {
> -		.name = "pcm_spi_cs3",
> -		.regmap[0] = {
> -			AIROHA_FUNC_MUX,
> -			REG_GPIO_SPI_CS1_MODE,
> -			GPIO_PCM_SPI_CS3_MODE_MASK,
> -			GPIO_PCM_SPI_CS3_MODE_MASK
> -		},
> -		.regmap_size = 1,
> -	}, {
> -		.name = "pcm_spi_cs4",
> -		.regmap[0] = {
> -			AIROHA_FUNC_MUX,
> -			REG_GPIO_SPI_CS1_MODE,
> -			GPIO_PCM_SPI_CS4_MODE_MASK,
> -			GPIO_PCM_SPI_CS4_MODE_MASK
> -		},
> -		.regmap_size = 1,
> -	},
> -};
> -
> -static const struct airoha_pinctrl_func_group an7583_pcm_spi_func_group[] = {
> -	{
> -		.name = "pcm_spi",
> -		.regmap[0] = {
> -			AIROHA_FUNC_MUX,
> -			REG_GPIO_SPI_CS1_MODE,
> -			GPIO_PCM_SPI_MODE_MASK,
> -			GPIO_PCM_SPI_MODE_MASK
> -		},
> -		.regmap_size = 1,
> -	}, {
> -		.name = "pcm_spi_int",
> -		.regmap[0] = {
> -			AIROHA_FUNC_MUX,
> -			REG_GPIO_SPI_CS1_MODE,
> -			GPIO_PCM_INT_MODE_MASK,
> -			GPIO_PCM_INT_MODE_MASK
> -		},
> -		.regmap_size = 1,
> -	}, {
> -		.name = "pcm_spi_rst",
> -		.regmap[0] = {
> -			AIROHA_FUNC_MUX,
> -			REG_GPIO_SPI_CS1_MODE,
> -			GPIO_PCM_RESET_MODE_MASK,
> -			GPIO_PCM_RESET_MODE_MASK
> -		},
> -		.regmap_size = 1,
> -	}, {
> -		.name = "pcm_spi_cs1",
> -		.regmap[0] = {
> -			AIROHA_FUNC_MUX,
> -			REG_GPIO_SPI_CS1_MODE,
> -			GPIO_PCM_SPI_CS1_MODE_MASK,
> -			GPIO_PCM_SPI_CS1_MODE_MASK
> -		},
> -		.regmap_size = 1,
> -	}, {
> -		.name = "pcm_spi_cs2",
> -		.regmap[0] = {
> -			AIROHA_FUNC_MUX,
> -			REG_GPIO_SPI_CS1_MODE,
> -			AN7583_GPIO_PCM_SPI_CS2_MODE_MASK,
> -			AN7583_GPIO_PCM_SPI_CS2_MODE_MASK
> -		},
> -		.regmap_size = 1,
> -	}, {
> -		.name = "pcm_spi_cs3",
> -		.regmap[0] = {
> -			AIROHA_FUNC_MUX,
> -			REG_GPIO_SPI_CS1_MODE,
> -			GPIO_PCM_SPI_CS3_MODE_MASK,
> -			GPIO_PCM_SPI_CS3_MODE_MASK
> -		},
> -		.regmap_size = 1,
> -	}, {
> -		.name = "pcm_spi_cs4",
> -		.regmap[0] = {
> -			AIROHA_FUNC_MUX,
> -			REG_GPIO_SPI_CS1_MODE,
> -			GPIO_PCM_SPI_CS4_MODE_MASK,
> -			GPIO_PCM_SPI_CS4_MODE_MASK
> -		},
> -		.regmap_size = 1,
> -	},
> -};
> -
> -static const struct airoha_pinctrl_func_group i2s_func_group[] = {
> -	{
> -		.name = "i2s",
> -		.regmap[0] = {
> -			AIROHA_FUNC_MUX,
> -			REG_GPIO_2ND_I2C_MODE,
> -			GPIO_I2S_MODE_MASK,
> -			GPIO_I2S_MODE_MASK
> -		},
> -		.regmap_size = 1,
> -	},
> -};
> -
> -static const struct airoha_pinctrl_func_group emmc_func_group[] = {
> -	{
> -		.name = "emmc",
> -		.regmap[0] = {
> -			AIROHA_FUNC_MUX,
> -			REG_GPIO_PON_MODE,
> -			GPIO_EMMC_MODE_MASK,
> -			GPIO_EMMC_MODE_MASK
> -		},
> -		.regmap_size = 1,
> -	},
> -};
> -
> -static const struct airoha_pinctrl_func_group pnand_func_group[] = {
> -	{
> -		.name = "pnand",
> -		.regmap[0] = {
> -			AIROHA_FUNC_MUX,
> -			REG_GPIO_PON_MODE,
> -			GPIO_PARALLEL_NAND_MODE_MASK,
> -			GPIO_PARALLEL_NAND_MODE_MASK
> -		},
> -		.regmap_size = 1,
> -	},
> -};
> -
> -static const struct airoha_pinctrl_func_group gpio_func_group[] = {
> -	AIROHA_PINCTRL_GPIO_EXT("gpio47", GPIO47_FLASH_MODE_CFG,
> -				GPIO_PCIE_RESET0_MASK),
> -	AIROHA_PINCTRL_GPIO_EXT("gpio48", GPIO48_FLASH_MODE_CFG,
> -				GPIO_PCIE_RESET1_MASK),
> -	AIROHA_PINCTRL_GPIO_EXT("gpio49", GPIO49_FLASH_MODE_CFG,
> -				GPIO_PCIE_RESET2_MASK),
> -};
> -
> -static const struct airoha_pinctrl_func_group pcie_reset_func_group[] = {
> -	{
> -		.name = "pcie_reset0",
> -		.regmap[0] = {
> -			AIROHA_FUNC_MUX,
> -			REG_GPIO_PON_MODE,
> -			GPIO_PCIE_RESET0_MASK,
> -			0
> -		},
> -		.regmap_size = 1,
> -	}, {
> -		.name = "pcie_reset1",
> -		.regmap[0] = {
> -			AIROHA_FUNC_MUX,
> -			REG_GPIO_PON_MODE,
> -			GPIO_PCIE_RESET1_MASK,
> -			0
> -		},
> -		.regmap_size = 1,
> -	}, {
> -		.name = "pcie_reset2",
> -		.regmap[0] = {
> -			AIROHA_FUNC_MUX,
> -			REG_GPIO_PON_MODE,
> -			GPIO_PCIE_RESET2_MASK,
> -			0
> -		},
> -		.regmap_size = 1,
> -	},
> -};
> -
> -static const struct airoha_pinctrl_func_group an7583_gpio_func_group[] = {
> -	AIROHA_PINCTRL_GPIO_EXT("gpio39", GPIO39_FLASH_MODE_CFG,
> -				AN7583_I2C0_SCL_GPIO_MODE_MASK),
> -	AIROHA_PINCTRL_GPIO_EXT("gpio40", GPIO40_FLASH_MODE_CFG,
> -				AN7583_I2C0_SDA_GPIO_MODE_MASK),
> -	AIROHA_PINCTRL_GPIO_EXT("gpio41", GPIO41_FLASH_MODE_CFG,
> -				AN7583_I2C1_SCL_GPIO_MODE_MASK),
> -	AIROHA_PINCTRL_GPIO_EXT("gpio42", GPIO42_FLASH_MODE_CFG,
> -				AN7583_I2C1_SDA_GPIO_MODE_MASK),
> -	AIROHA_PINCTRL_GPIO_EXT("gpio43", GPIO43_FLASH_MODE_CFG,
> -				AN7583_SPI_CLK_GPIO_MODE_MASK),
> -	AIROHA_PINCTRL_GPIO_EXT("gpio44", GPIO44_FLASH_MODE_CFG,
> -				AN7583_SPI_CS_GPIO_MODE_MASK),
> -	AIROHA_PINCTRL_GPIO_EXT("gpio45", GPIO45_FLASH_MODE_CFG,
> -				AN7583_SPI_MOSI_GPIO_MODE_MASK),
> -	AIROHA_PINCTRL_GPIO_EXT("gpio46", GPIO46_FLASH_MODE_CFG,
> -				AN7583_SPI_MISO_GPIO_MODE_MASK),
> -	AIROHA_PINCTRL_GPIO_EXT("gpio47", GPIO47_FLASH_MODE_CFG,
> -				AN7583_UART_TXD_GPIO_MODE_MASK),
> -	AIROHA_PINCTRL_GPIO_EXT("gpio48", GPIO48_FLASH_MODE_CFG,
> -				AN7583_UART_RXD_GPIO_MODE_MASK),
> -	AIROHA_PINCTRL_GPIO_EXT("gpio49", GPIO49_FLASH_MODE_CFG,
> -				GPIO_PCIE_RESET0_MASK),
> -	AIROHA_PINCTRL_GPIO_EXT("gpio50", GPIO50_FLASH_MODE_CFG,
> -				GPIO_PCIE_RESET1_MASK),
> -	AIROHA_PINCTRL_GPIO_EXT("gpio51", GPIO51_FLASH_MODE_CFG,
> -				AN7583_MDC_0_GPIO_MODE_MASK),
> -	AIROHA_PINCTRL_GPIO("gpio52", AN7583_MDIO_0_GPIO_MODE_MASK),
> -};
> -
> -static const struct airoha_pinctrl_func_group an7583_pcie_reset_func_group[] = {
> -	{
> -		.name = "pcie_reset0",
> -		.regmap[0] = {
> -			AIROHA_FUNC_MUX,
> -			REG_GPIO_PON_MODE,
> -			GPIO_PCIE_RESET0_MASK,
> -			0
> -		},
> -		.regmap_size = 1,
> -	}, {
> -		.name = "pcie_reset1",
> -		.regmap[0] = {
> -			AIROHA_FUNC_MUX,
> -			REG_GPIO_PON_MODE,
> -			GPIO_PCIE_RESET1_MASK,
> -			0
> -		},
> -		.regmap_size = 1,
> -	},
> -};
> -
> -static const struct airoha_pinctrl_func_group pwm_func_group[] = {
> -	AIROHA_PINCTRL_PWM("gpio0", GPIO0_FLASH_MODE_CFG),
> -	AIROHA_PINCTRL_PWM("gpio1", GPIO1_FLASH_MODE_CFG),
> -	AIROHA_PINCTRL_PWM("gpio2", GPIO2_FLASH_MODE_CFG),
> -	AIROHA_PINCTRL_PWM("gpio3", GPIO3_FLASH_MODE_CFG),
> -	AIROHA_PINCTRL_PWM("gpio4", GPIO4_FLASH_MODE_CFG),
> -	AIROHA_PINCTRL_PWM("gpio5", GPIO5_FLASH_MODE_CFG),
> -	AIROHA_PINCTRL_PWM("gpio6", GPIO6_FLASH_MODE_CFG),
> -	AIROHA_PINCTRL_PWM("gpio7", GPIO7_FLASH_MODE_CFG),
> -	AIROHA_PINCTRL_PWM("gpio8", GPIO8_FLASH_MODE_CFG),
> -	AIROHA_PINCTRL_PWM("gpio9", GPIO9_FLASH_MODE_CFG),
> -	AIROHA_PINCTRL_PWM("gpio10", GPIO10_FLASH_MODE_CFG),
> -	AIROHA_PINCTRL_PWM("gpio11", GPIO11_FLASH_MODE_CFG),
> -	AIROHA_PINCTRL_PWM("gpio12", GPIO12_FLASH_MODE_CFG),
> -	AIROHA_PINCTRL_PWM("gpio13", GPIO13_FLASH_MODE_CFG),
> -	AIROHA_PINCTRL_PWM("gpio14", GPIO14_FLASH_MODE_CFG),
> -	AIROHA_PINCTRL_PWM("gpio15", GPIO15_FLASH_MODE_CFG),
> -	AIROHA_PINCTRL_PWM_EXT("gpio16", GPIO16_FLASH_MODE_CFG),
> -	AIROHA_PINCTRL_PWM_EXT("gpio17", GPIO17_FLASH_MODE_CFG),
> -	AIROHA_PINCTRL_PWM_EXT("gpio18", GPIO18_FLASH_MODE_CFG),
> -	AIROHA_PINCTRL_PWM_EXT("gpio19", GPIO19_FLASH_MODE_CFG),
> -	AIROHA_PINCTRL_PWM_EXT("gpio20", GPIO20_FLASH_MODE_CFG),
> -	AIROHA_PINCTRL_PWM_EXT("gpio21", GPIO21_FLASH_MODE_CFG),
> -	AIROHA_PINCTRL_PWM_EXT("gpio22", GPIO22_FLASH_MODE_CFG),
> -	AIROHA_PINCTRL_PWM_EXT("gpio23", GPIO23_FLASH_MODE_CFG),
> -	AIROHA_PINCTRL_PWM_EXT("gpio24", GPIO24_FLASH_MODE_CFG),
> -	AIROHA_PINCTRL_PWM_EXT("gpio25", GPIO25_FLASH_MODE_CFG),
> -	AIROHA_PINCTRL_PWM_EXT("gpio26", GPIO26_FLASH_MODE_CFG),
> -	AIROHA_PINCTRL_PWM_EXT("gpio27", GPIO27_FLASH_MODE_CFG),
> -	AIROHA_PINCTRL_PWM_EXT("gpio28", GPIO28_FLASH_MODE_CFG),
> -	AIROHA_PINCTRL_PWM_EXT("gpio29", GPIO29_FLASH_MODE_CFG),
> -	AIROHA_PINCTRL_PWM_EXT("gpio30", GPIO30_FLASH_MODE_CFG),
> -	AIROHA_PINCTRL_PWM_EXT("gpio31", GPIO31_FLASH_MODE_CFG),
> -	AIROHA_PINCTRL_PWM_EXT("gpio36", GPIO36_FLASH_MODE_CFG),
> -	AIROHA_PINCTRL_PWM_EXT("gpio37", GPIO37_FLASH_MODE_CFG),
> -	AIROHA_PINCTRL_PWM_EXT("gpio38", GPIO38_FLASH_MODE_CFG),
> -	AIROHA_PINCTRL_PWM_EXT("gpio39", GPIO39_FLASH_MODE_CFG),
> -	AIROHA_PINCTRL_PWM_EXT("gpio40", GPIO40_FLASH_MODE_CFG),
> -	AIROHA_PINCTRL_PWM_EXT("gpio41", GPIO41_FLASH_MODE_CFG),
> -	AIROHA_PINCTRL_PWM_EXT("gpio42", GPIO42_FLASH_MODE_CFG),
> -	AIROHA_PINCTRL_PWM_EXT("gpio43", GPIO43_FLASH_MODE_CFG),
> -	AIROHA_PINCTRL_PWM_EXT("gpio44", GPIO44_FLASH_MODE_CFG),
> -	AIROHA_PINCTRL_PWM_EXT("gpio45", GPIO45_FLASH_MODE_CFG),
> -	AIROHA_PINCTRL_PWM_EXT("gpio46", GPIO46_FLASH_MODE_CFG),
> -	AIROHA_PINCTRL_PWM_EXT_SEC("gpio47", GPIO47_FLASH_MODE_CFG,
> -				   GPIO_PCIE_RESET0_MASK),
> -	AIROHA_PINCTRL_PWM_EXT_SEC("gpio48", GPIO48_FLASH_MODE_CFG,
> -				   GPIO_PCIE_RESET1_MASK),
> -	AIROHA_PINCTRL_PWM_EXT_SEC("gpio49", GPIO49_FLASH_MODE_CFG,
> -				   GPIO_PCIE_RESET2_MASK),
> -};
> -
> -static const struct airoha_pinctrl_func_group an7583_pwm_func_group[] = {
> -	AIROHA_PINCTRL_PWM("gpio0", GPIO0_FLASH_MODE_CFG),
> -	AIROHA_PINCTRL_PWM("gpio1", GPIO1_FLASH_MODE_CFG),
> -	AIROHA_PINCTRL_PWM("gpio2", GPIO2_FLASH_MODE_CFG),
> -	AIROHA_PINCTRL_PWM("gpio3", GPIO3_FLASH_MODE_CFG),
> -	AIROHA_PINCTRL_PWM("gpio4", GPIO4_FLASH_MODE_CFG),
> -	AIROHA_PINCTRL_PWM("gpio5", GPIO5_FLASH_MODE_CFG),
> -	AIROHA_PINCTRL_PWM("gpio6", GPIO6_FLASH_MODE_CFG),
> -	AIROHA_PINCTRL_PWM("gpio7", GPIO7_FLASH_MODE_CFG),
> -	AIROHA_PINCTRL_PWM("gpio8", GPIO8_FLASH_MODE_CFG),
> -	AIROHA_PINCTRL_PWM("gpio9", GPIO9_FLASH_MODE_CFG),
> -	AIROHA_PINCTRL_PWM("gpio10", GPIO10_FLASH_MODE_CFG),
> -	AIROHA_PINCTRL_PWM("gpio11", GPIO11_FLASH_MODE_CFG),
> -	AIROHA_PINCTRL_PWM("gpio12", GPIO12_FLASH_MODE_CFG),
> -	AIROHA_PINCTRL_PWM("gpio13", GPIO13_FLASH_MODE_CFG),
> -	AIROHA_PINCTRL_PWM("gpio14", GPIO14_FLASH_MODE_CFG),
> -	AIROHA_PINCTRL_PWM("gpio15", GPIO15_FLASH_MODE_CFG),
> -	AIROHA_PINCTRL_PWM_EXT("gpio16", GPIO16_FLASH_MODE_CFG),
> -	AIROHA_PINCTRL_PWM_EXT("gpio17", GPIO17_FLASH_MODE_CFG),
> -	AIROHA_PINCTRL_PWM_EXT("gpio18", GPIO18_FLASH_MODE_CFG),
> -	AIROHA_PINCTRL_PWM_EXT("gpio19", GPIO19_FLASH_MODE_CFG),
> -	AIROHA_PINCTRL_PWM_EXT("gpio20", GPIO20_FLASH_MODE_CFG),
> -	AIROHA_PINCTRL_PWM_EXT("gpio21", GPIO21_FLASH_MODE_CFG),
> -	AIROHA_PINCTRL_PWM_EXT("gpio22", GPIO22_FLASH_MODE_CFG),
> -	AIROHA_PINCTRL_PWM_EXT("gpio23", GPIO23_FLASH_MODE_CFG),
> -	AIROHA_PINCTRL_PWM_EXT("gpio24", GPIO24_FLASH_MODE_CFG),
> -	AIROHA_PINCTRL_PWM_EXT("gpio25", GPIO25_FLASH_MODE_CFG),
> -	AIROHA_PINCTRL_PWM_EXT("gpio26", GPIO26_FLASH_MODE_CFG),
> -	AIROHA_PINCTRL_PWM_EXT("gpio27", GPIO27_FLASH_MODE_CFG),
> -	AIROHA_PINCTRL_PWM_EXT("gpio28", GPIO28_FLASH_MODE_CFG),
> -	AIROHA_PINCTRL_PWM_EXT("gpio29", GPIO29_FLASH_MODE_CFG),
> -	AIROHA_PINCTRL_PWM_EXT("gpio30", GPIO30_FLASH_MODE_CFG),
> -	AIROHA_PINCTRL_PWM_EXT("gpio31", GPIO31_FLASH_MODE_CFG),
> -	AIROHA_PINCTRL_PWM_EXT("gpio36", GPIO36_FLASH_MODE_CFG),
> -	AIROHA_PINCTRL_PWM_EXT("gpio37", GPIO37_FLASH_MODE_CFG),
> -	AIROHA_PINCTRL_PWM_EXT("gpio38", GPIO38_FLASH_MODE_CFG),
> -	AIROHA_PINCTRL_PWM_EXT_SEC("gpio39", GPIO39_FLASH_MODE_CFG,
> -				   AN7583_I2C0_SCL_GPIO_MODE_MASK),
> -	AIROHA_PINCTRL_PWM_EXT_SEC("gpio40", GPIO40_FLASH_MODE_CFG,
> -				   AN7583_I2C0_SDA_GPIO_MODE_MASK),
> -	AIROHA_PINCTRL_PWM_EXT_SEC("gpio41", GPIO41_FLASH_MODE_CFG,
> -				   AN7583_I2C1_SCL_GPIO_MODE_MASK),
> -	AIROHA_PINCTRL_PWM_EXT_SEC("gpio42", GPIO42_FLASH_MODE_CFG,
> -				   AN7583_I2C1_SDA_GPIO_MODE_MASK),
> -	AIROHA_PINCTRL_PWM_EXT_SEC("gpio43", GPIO43_FLASH_MODE_CFG,
> -				   AN7583_SPI_CLK_GPIO_MODE_MASK),
> -	AIROHA_PINCTRL_PWM_EXT_SEC("gpio44", GPIO44_FLASH_MODE_CFG,
> -				   AN7583_SPI_CS_GPIO_MODE_MASK),
> -	AIROHA_PINCTRL_PWM_EXT_SEC("gpio45", GPIO45_FLASH_MODE_CFG,
> -				   AN7583_SPI_MOSI_GPIO_MODE_MASK),
> -	AIROHA_PINCTRL_PWM_EXT_SEC("gpio46", GPIO46_FLASH_MODE_CFG,
> -				   AN7583_SPI_MISO_GPIO_MODE_MASK),
> -	AIROHA_PINCTRL_PWM_EXT_SEC("gpio47", GPIO47_FLASH_MODE_CFG,
> -				   AN7583_UART_TXD_GPIO_MODE_MASK),
> -	AIROHA_PINCTRL_PWM_EXT_SEC("gpio48", GPIO48_FLASH_MODE_CFG,
> -				   AN7583_UART_RXD_GPIO_MODE_MASK),
> -	AIROHA_PINCTRL_PWM_EXT_SEC("gpio49", GPIO49_FLASH_MODE_CFG,
> -				   GPIO_PCIE_RESET0_MASK),
> -	AIROHA_PINCTRL_PWM_EXT_SEC("gpio50", GPIO50_FLASH_MODE_CFG,
> -				   GPIO_PCIE_RESET1_MASK),
> -	AIROHA_PINCTRL_PWM_EXT_SEC("gpio51", GPIO51_FLASH_MODE_CFG,
> -				   AN7583_MDC_0_GPIO_MODE_MASK),
> -};
> -
> -static const struct airoha_pinctrl_func_group phy1_led0_func_group[] = {
> -	AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK,
> -				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),
> -	AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK,
> -				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)),
> -	AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK,
> -				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)),
> -	AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK,
> -				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),
> -};
> -
> -static const struct airoha_pinctrl_func_group phy2_led0_func_group[] = {
> -	AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK,
> -				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),
> -	AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK,
> -				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)),
> -	AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK,
> -				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)),
> -	AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK,
> -				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),
> -};
> -
> -static const struct airoha_pinctrl_func_group phy3_led0_func_group[] = {
> -	AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK,
> -				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
> -	AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK,
> -				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),
> -	AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK,
> -				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),
> -	AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK,
> -				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
> -};
> -
> -static const struct airoha_pinctrl_func_group phy4_led0_func_group[] = {
> -	AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK,
> -				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)),
> -	AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK,
> -				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)),
> -	AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK,
> -				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)),
> -	AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK,
> -				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)),
> -};
> -
> -static const struct airoha_pinctrl_func_group phy1_led1_func_group[] = {
> -	AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK,
> -				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),
> -	AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK,
> -				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)),
> -	AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK,
> -				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)),
> -	AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK,
> -				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),
> -};
> -
> -static const struct airoha_pinctrl_func_group phy2_led1_func_group[] = {
> -	AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK,
> -				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),
> -	AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK,
> -				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)),
> -	AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK,
> -				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)),
> -	AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK,
> -				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),
> -};
> -
> -static const struct airoha_pinctrl_func_group phy3_led1_func_group[] = {
> -	AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK,
> -				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
> -	AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK,
> -				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),
> -	AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK,
> -				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),
> -	AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK,
> -				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
> -};
> -
> -static const struct airoha_pinctrl_func_group phy4_led1_func_group[] = {
> -	AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK,
> -				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)),
> -	AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK,
> -				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)),
> -	AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK,
> -				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)),
> -	AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK,
> -				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)),
> -};
> -
> -static const struct airoha_pinctrl_func_group an7583_phy1_led0_func_group[] = {
> -	AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK,
> -				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),
> -	AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK,
> -				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)),
> -	AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK,
> -				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)),
> -	AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK,
> -				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),
> -};
> -
> -static const struct airoha_pinctrl_func_group an7583_phy2_led0_func_group[] = {
> -	AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK,
> -				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),
> -	AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK,
> -				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)),
> -	AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK,
> -				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)),
> -	AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK,
> -				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),
> -};
> -
> -static const struct airoha_pinctrl_func_group an7583_phy3_led0_func_group[] = {
> -	AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK,
> -				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
> -	AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK,
> -				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),
> -	AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK,
> -				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),
> -	AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK,
> -				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
> -};
> -
> -static const struct airoha_pinctrl_func_group an7583_phy4_led0_func_group[] = {
> -	AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK,
> -				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)),
> -	AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK,
> -				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)),
> -	AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK,
> -				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)),
> -	AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK,
> -				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)),
> -};
> -
> -static const struct airoha_pinctrl_func_group an7583_phy1_led1_func_group[] = {
> -	AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK,
> -				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),
> -	AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK,
> -				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)),
> -	AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK,
> -				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)),
> -	AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK,
> -				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),
> -};
> -
> -static const struct airoha_pinctrl_func_group an7583_phy2_led1_func_group[] = {
> -	AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK,
> -				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),
> -	AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK,
> -				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)),
> -	AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK,
> -				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)),
> -	AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK,
> -				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),
> -};
> -
> -static const struct airoha_pinctrl_func_group an7583_phy3_led1_func_group[] = {
> -	AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK,
> -				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
> -	AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK,
> -				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),
> -	AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK,
> -				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),
> -	AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK,
> -				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
> -};
> -
> -static const struct airoha_pinctrl_func_group an7583_phy4_led1_func_group[] = {
> -	AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK,
> -				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)),
> -	AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK,
> -				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)),
> -	AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK,
> -				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)),
> -	AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK,
> -				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)),
> -};
> -
> -static const struct airoha_pinctrl_func en7581_pinctrl_funcs[] = {
> -	PINCTRL_FUNC_DESC("pon", pon),
> -	PINCTRL_FUNC_DESC("tod_1pps", tod_1pps),
> -	PINCTRL_FUNC_DESC("sipo", sipo),
> -	PINCTRL_FUNC_DESC("mdio", mdio),
> -	PINCTRL_FUNC_DESC("uart", uart),
> -	PINCTRL_FUNC_DESC("i2c", i2c),
> -	PINCTRL_FUNC_DESC("jtag", jtag),
> -	PINCTRL_FUNC_DESC("pcm", pcm),
> -	PINCTRL_FUNC_DESC("spi", spi),
> -	PINCTRL_FUNC_DESC("pcm_spi", pcm_spi),
> -	PINCTRL_FUNC_DESC("i2s", i2s),
> -	PINCTRL_FUNC_DESC("emmc", emmc),
> -	PINCTRL_FUNC_DESC("pnand", pnand),
> -	PINCTRL_FUNC_DESC("gpio", gpio),
> -	PINCTRL_FUNC_DESC("pcie_reset", pcie_reset),
> -	PINCTRL_FUNC_DESC("pwm", pwm),
> -	PINCTRL_FUNC_DESC("phy1_led0", phy1_led0),
> -	PINCTRL_FUNC_DESC("phy2_led0", phy2_led0),
> -	PINCTRL_FUNC_DESC("phy3_led0", phy3_led0),
> -	PINCTRL_FUNC_DESC("phy4_led0", phy4_led0),
> -	PINCTRL_FUNC_DESC("phy1_led1", phy1_led1),
> -	PINCTRL_FUNC_DESC("phy2_led1", phy2_led1),
> -	PINCTRL_FUNC_DESC("phy3_led1", phy3_led1),
> -	PINCTRL_FUNC_DESC("phy4_led1", phy4_led1),
> -};
> -
> -static const struct airoha_pinctrl_func an7583_pinctrl_funcs[] = {
> -	PINCTRL_FUNC_DESC("pon", pon),
> -	PINCTRL_FUNC_DESC("tod_1pps", tod_1pps),
> -	PINCTRL_FUNC_DESC("sipo", sipo),
> -	PINCTRL_FUNC_DESC("mdio", an7583_mdio),
> -	PINCTRL_FUNC_DESC("uart", uart),
> -	PINCTRL_FUNC_DESC("jtag", jtag),
> -	PINCTRL_FUNC_DESC("pcm", pcm),
> -	PINCTRL_FUNC_DESC("spi", spi),
> -	PINCTRL_FUNC_DESC("pcm_spi", an7583_pcm_spi),
> -	PINCTRL_FUNC_DESC("emmc", emmc),
> -	PINCTRL_FUNC_DESC("pnand", pnand),
> -	PINCTRL_FUNC_DESC("gpio", an7583_gpio),
> -	PINCTRL_FUNC_DESC("pcie_reset", an7583_pcie_reset),
> -	PINCTRL_FUNC_DESC("pwm", an7583_pwm),
> -	PINCTRL_FUNC_DESC("phy1_led0", an7583_phy1_led0),
> -	PINCTRL_FUNC_DESC("phy2_led0", an7583_phy2_led0),
> -	PINCTRL_FUNC_DESC("phy3_led0", an7583_phy3_led0),
> -	PINCTRL_FUNC_DESC("phy4_led0", an7583_phy4_led0),
> -	PINCTRL_FUNC_DESC("phy1_led1", an7583_phy1_led1),
> -	PINCTRL_FUNC_DESC("phy2_led1", an7583_phy2_led1),
> -	PINCTRL_FUNC_DESC("phy3_led1", an7583_phy3_led1),
> -	PINCTRL_FUNC_DESC("phy4_led1", an7583_phy4_led1),
> -};
> -
> -static const struct airoha_pinctrl_conf en7581_pinctrl_pullup_conf[] = {
> -	PINCTRL_CONF_DESC(0, REG_I2C_SDA_PU, UART1_TXD_PU_MASK),
> -	PINCTRL_CONF_DESC(1, REG_I2C_SDA_PU, UART1_RXD_PU_MASK),
> -	PINCTRL_CONF_DESC(2, REG_I2C_SDA_PU, I2C_SDA_PU_MASK),
> -	PINCTRL_CONF_DESC(3, REG_I2C_SDA_PU, I2C_SCL_PU_MASK),
> -	PINCTRL_CONF_DESC(4, REG_I2C_SDA_PU, SPI_CS0_PU_MASK),
> -	PINCTRL_CONF_DESC(5, REG_I2C_SDA_PU, SPI_CLK_PU_MASK),
> -	PINCTRL_CONF_DESC(6, REG_I2C_SDA_PU, SPI_MOSI_PU_MASK),
> -	PINCTRL_CONF_DESC(7, REG_I2C_SDA_PU, SPI_MISO_PU_MASK),
> -	PINCTRL_CONF_DESC(13, REG_GPIO_L_PU, BIT(0)),
> -	PINCTRL_CONF_DESC(14, REG_GPIO_L_PU, BIT(1)),
> -	PINCTRL_CONF_DESC(15, REG_GPIO_L_PU, BIT(2)),
> -	PINCTRL_CONF_DESC(16, REG_GPIO_L_PU, BIT(3)),
> -	PINCTRL_CONF_DESC(17, REG_GPIO_L_PU, BIT(4)),
> -	PINCTRL_CONF_DESC(18, REG_GPIO_L_PU, BIT(5)),
> -	PINCTRL_CONF_DESC(19, REG_GPIO_L_PU, BIT(6)),
> -	PINCTRL_CONF_DESC(20, REG_GPIO_L_PU, BIT(7)),
> -	PINCTRL_CONF_DESC(21, REG_GPIO_L_PU, BIT(8)),
> -	PINCTRL_CONF_DESC(22, REG_GPIO_L_PU, BIT(9)),
> -	PINCTRL_CONF_DESC(23, REG_GPIO_L_PU, BIT(10)),
> -	PINCTRL_CONF_DESC(24, REG_GPIO_L_PU, BIT(11)),
> -	PINCTRL_CONF_DESC(25, REG_GPIO_L_PU, BIT(12)),
> -	PINCTRL_CONF_DESC(26, REG_GPIO_L_PU, BIT(13)),
> -	PINCTRL_CONF_DESC(27, REG_GPIO_L_PU, BIT(14)),
> -	PINCTRL_CONF_DESC(28, REG_GPIO_L_PU, BIT(15)),
> -	PINCTRL_CONF_DESC(29, REG_GPIO_L_PU, BIT(16)),
> -	PINCTRL_CONF_DESC(30, REG_GPIO_L_PU, BIT(17)),
> -	PINCTRL_CONF_DESC(31, REG_GPIO_L_PU, BIT(18)),
> -	PINCTRL_CONF_DESC(32, REG_GPIO_L_PU, BIT(19)),
> -	PINCTRL_CONF_DESC(33, REG_GPIO_L_PU, BIT(20)),
> -	PINCTRL_CONF_DESC(34, REG_GPIO_L_PU, BIT(21)),
> -	PINCTRL_CONF_DESC(35, REG_GPIO_L_PU, BIT(22)),
> -	PINCTRL_CONF_DESC(36, REG_GPIO_L_PU, BIT(23)),
> -	PINCTRL_CONF_DESC(37, REG_GPIO_L_PU, BIT(24)),
> -	PINCTRL_CONF_DESC(38, REG_GPIO_L_PU, BIT(25)),
> -	PINCTRL_CONF_DESC(39, REG_GPIO_L_PU, BIT(26)),
> -	PINCTRL_CONF_DESC(40, REG_GPIO_L_PU, BIT(27)),
> -	PINCTRL_CONF_DESC(41, REG_GPIO_L_PU, BIT(28)),
> -	PINCTRL_CONF_DESC(42, REG_GPIO_L_PU, BIT(29)),
> -	PINCTRL_CONF_DESC(43, REG_GPIO_L_PU, BIT(30)),
> -	PINCTRL_CONF_DESC(44, REG_GPIO_L_PU, BIT(31)),
> -	PINCTRL_CONF_DESC(45, REG_GPIO_H_PU, BIT(0)),
> -	PINCTRL_CONF_DESC(46, REG_GPIO_H_PU, BIT(1)),
> -	PINCTRL_CONF_DESC(47, REG_GPIO_H_PU, BIT(2)),
> -	PINCTRL_CONF_DESC(48, REG_GPIO_H_PU, BIT(3)),
> -	PINCTRL_CONF_DESC(49, REG_GPIO_H_PU, BIT(4)),
> -	PINCTRL_CONF_DESC(50, REG_GPIO_H_PU, BIT(5)),
> -	PINCTRL_CONF_DESC(51, REG_GPIO_H_PU, BIT(6)),
> -	PINCTRL_CONF_DESC(52, REG_GPIO_H_PU, BIT(7)),
> -	PINCTRL_CONF_DESC(53, REG_GPIO_H_PU, BIT(8)),
> -	PINCTRL_CONF_DESC(54, REG_GPIO_H_PU, BIT(9)),
> -	PINCTRL_CONF_DESC(55, REG_GPIO_H_PU, BIT(10)),
> -	PINCTRL_CONF_DESC(56, REG_GPIO_H_PU, BIT(11)),
> -	PINCTRL_CONF_DESC(57, REG_GPIO_H_PU, BIT(12)),
> -	PINCTRL_CONF_DESC(58, REG_GPIO_H_PU, BIT(13)),
> -	PINCTRL_CONF_DESC(59, REG_GPIO_H_PU, BIT(14)),
> -	PINCTRL_CONF_DESC(60, REG_I2C_SDA_PU, PCIE0_RESET_PU_MASK),
> -	PINCTRL_CONF_DESC(61, REG_I2C_SDA_PU, PCIE1_RESET_PU_MASK),
> -	PINCTRL_CONF_DESC(62, REG_I2C_SDA_PU, PCIE2_RESET_PU_MASK),
> -};
> -
> -static const struct airoha_pinctrl_conf an7583_pinctrl_pullup_conf[] = {
> -	PINCTRL_CONF_DESC(2, REG_GPIO_L_PU, BIT(0)),
> -	PINCTRL_CONF_DESC(3, REG_GPIO_L_PU, BIT(1)),
> -	PINCTRL_CONF_DESC(4, REG_GPIO_L_PU, BIT(2)),
> -	PINCTRL_CONF_DESC(5, REG_GPIO_L_PU, BIT(3)),
> -	PINCTRL_CONF_DESC(6, REG_GPIO_L_PU, BIT(4)),
> -	PINCTRL_CONF_DESC(7, REG_GPIO_L_PU, BIT(5)),
> -	PINCTRL_CONF_DESC(8, REG_GPIO_L_PU, BIT(6)),
> -	PINCTRL_CONF_DESC(9, REG_GPIO_L_PU, BIT(7)),
> -	PINCTRL_CONF_DESC(10, REG_GPIO_L_PU, BIT(8)),
> -	PINCTRL_CONF_DESC(11, REG_GPIO_L_PU, BIT(9)),
> -	PINCTRL_CONF_DESC(12, REG_GPIO_L_PU, BIT(10)),
> -	PINCTRL_CONF_DESC(13, REG_GPIO_L_PU, BIT(11)),
> -	PINCTRL_CONF_DESC(14, REG_GPIO_L_PU, BIT(12)),
> -	PINCTRL_CONF_DESC(15, REG_GPIO_L_PU, BIT(13)),
> -	PINCTRL_CONF_DESC(16, REG_GPIO_L_PU, BIT(14)),
> -	PINCTRL_CONF_DESC(17, REG_GPIO_L_PU, BIT(15)),
> -	PINCTRL_CONF_DESC(18, REG_GPIO_L_PU, BIT(16)),
> -	PINCTRL_CONF_DESC(19, REG_GPIO_L_PU, BIT(17)),
> -	PINCTRL_CONF_DESC(20, REG_GPIO_L_PU, BIT(18)),
> -	PINCTRL_CONF_DESC(21, REG_GPIO_L_PU, BIT(19)),
> -	PINCTRL_CONF_DESC(22, REG_GPIO_L_PU, BIT(20)),
> -	PINCTRL_CONF_DESC(23, REG_GPIO_L_PU, BIT(21)),
> -	PINCTRL_CONF_DESC(24, REG_GPIO_L_PU, BIT(22)),
> -	PINCTRL_CONF_DESC(25, REG_GPIO_L_PU, BIT(23)),
> -	PINCTRL_CONF_DESC(26, REG_GPIO_L_PU, BIT(24)),
> -	PINCTRL_CONF_DESC(27, REG_GPIO_L_PU, BIT(25)),
> -	PINCTRL_CONF_DESC(28, REG_GPIO_L_PU, BIT(26)),
> -	PINCTRL_CONF_DESC(29, REG_GPIO_L_PU, BIT(27)),
> -	PINCTRL_CONF_DESC(30, REG_GPIO_L_PU, BIT(28)),
> -	PINCTRL_CONF_DESC(31, REG_GPIO_L_PU, BIT(29)),
> -	PINCTRL_CONF_DESC(32, REG_GPIO_L_PU, BIT(30)),
> -	PINCTRL_CONF_DESC(33, REG_GPIO_L_PU, BIT(31)),
> -	PINCTRL_CONF_DESC(34, REG_GPIO_H_PU, BIT(0)),
> -	PINCTRL_CONF_DESC(35, REG_GPIO_H_PU, BIT(1)),
> -	PINCTRL_CONF_DESC(36, REG_GPIO_H_PU, BIT(2)),
> -	PINCTRL_CONF_DESC(37, REG_GPIO_H_PU, BIT(3)),
> -	PINCTRL_CONF_DESC(38, REG_GPIO_H_PU, BIT(4)),
> -	PINCTRL_CONF_DESC(39, REG_GPIO_H_PU, BIT(5)),
> -	PINCTRL_CONF_DESC(40, REG_GPIO_H_PU, BIT(6)),
> -	PINCTRL_CONF_DESC(41, REG_I2C_SDA_PU, I2C_SCL_PU_MASK),
> -	PINCTRL_CONF_DESC(42, REG_I2C_SDA_PU, I2C_SDA_PU_MASK),
> -	PINCTRL_CONF_DESC(43, REG_I2C_SDA_PU, AN7583_I2C1_SCL_PU_MASK),
> -	PINCTRL_CONF_DESC(44, REG_I2C_SDA_PU, AN7583_I2C1_SDA_PU_MASK),
> -	PINCTRL_CONF_DESC(45, REG_I2C_SDA_PU, SPI_CLK_PU_MASK),
> -	PINCTRL_CONF_DESC(46, REG_I2C_SDA_PU, SPI_CS0_PU_MASK),
> -	PINCTRL_CONF_DESC(47, REG_I2C_SDA_PU, SPI_MOSI_PU_MASK),
> -	PINCTRL_CONF_DESC(48, REG_I2C_SDA_PU, SPI_MISO_PU_MASK),
> -	PINCTRL_CONF_DESC(49, REG_I2C_SDA_PU, UART1_TXD_PU_MASK),
> -	PINCTRL_CONF_DESC(50, REG_I2C_SDA_PU, UART1_RXD_PU_MASK),
> -	PINCTRL_CONF_DESC(51, REG_I2C_SDA_PU, PCIE0_RESET_PU_MASK),
> -	PINCTRL_CONF_DESC(52, REG_I2C_SDA_PU, PCIE1_RESET_PU_MASK),
> -	PINCTRL_CONF_DESC(53, REG_I2C_SDA_PU, AN7583_MDC_0_PU_MASK),
> -	PINCTRL_CONF_DESC(54, REG_I2C_SDA_PU, AN7583_MDIO_0_PU_MASK),
> -};
> -
> -static const struct airoha_pinctrl_conf en7581_pinctrl_pulldown_conf[] = {
> -	PINCTRL_CONF_DESC(0, REG_I2C_SDA_PD, UART1_TXD_PD_MASK),
> -	PINCTRL_CONF_DESC(1, REG_I2C_SDA_PD, UART1_RXD_PD_MASK),
> -	PINCTRL_CONF_DESC(2, REG_I2C_SDA_PD, I2C_SDA_PD_MASK),
> -	PINCTRL_CONF_DESC(3, REG_I2C_SDA_PD, I2C_SCL_PD_MASK),
> -	PINCTRL_CONF_DESC(4, REG_I2C_SDA_PD, SPI_CS0_PD_MASK),
> -	PINCTRL_CONF_DESC(5, REG_I2C_SDA_PD, SPI_CLK_PD_MASK),
> -	PINCTRL_CONF_DESC(6, REG_I2C_SDA_PD, SPI_MOSI_PD_MASK),
> -	PINCTRL_CONF_DESC(7, REG_I2C_SDA_PD, SPI_MISO_PD_MASK),
> -	PINCTRL_CONF_DESC(13, REG_GPIO_L_PD, BIT(0)),
> -	PINCTRL_CONF_DESC(14, REG_GPIO_L_PD, BIT(1)),
> -	PINCTRL_CONF_DESC(15, REG_GPIO_L_PD, BIT(2)),
> -	PINCTRL_CONF_DESC(16, REG_GPIO_L_PD, BIT(3)),
> -	PINCTRL_CONF_DESC(17, REG_GPIO_L_PD, BIT(4)),
> -	PINCTRL_CONF_DESC(18, REG_GPIO_L_PD, BIT(5)),
> -	PINCTRL_CONF_DESC(19, REG_GPIO_L_PD, BIT(6)),
> -	PINCTRL_CONF_DESC(20, REG_GPIO_L_PD, BIT(7)),
> -	PINCTRL_CONF_DESC(21, REG_GPIO_L_PD, BIT(8)),
> -	PINCTRL_CONF_DESC(22, REG_GPIO_L_PD, BIT(9)),
> -	PINCTRL_CONF_DESC(23, REG_GPIO_L_PD, BIT(10)),
> -	PINCTRL_CONF_DESC(24, REG_GPIO_L_PD, BIT(11)),
> -	PINCTRL_CONF_DESC(25, REG_GPIO_L_PD, BIT(12)),
> -	PINCTRL_CONF_DESC(26, REG_GPIO_L_PD, BIT(13)),
> -	PINCTRL_CONF_DESC(27, REG_GPIO_L_PD, BIT(14)),
> -	PINCTRL_CONF_DESC(28, REG_GPIO_L_PD, BIT(15)),
> -	PINCTRL_CONF_DESC(29, REG_GPIO_L_PD, BIT(16)),
> -	PINCTRL_CONF_DESC(30, REG_GPIO_L_PD, BIT(17)),
> -	PINCTRL_CONF_DESC(31, REG_GPIO_L_PD, BIT(18)),
> -	PINCTRL_CONF_DESC(32, REG_GPIO_L_PD, BIT(19)),
> -	PINCTRL_CONF_DESC(33, REG_GPIO_L_PD, BIT(20)),
> -	PINCTRL_CONF_DESC(34, REG_GPIO_L_PD, BIT(21)),
> -	PINCTRL_CONF_DESC(35, REG_GPIO_L_PD, BIT(22)),
> -	PINCTRL_CONF_DESC(36, REG_GPIO_L_PD, BIT(23)),
> -	PINCTRL_CONF_DESC(37, REG_GPIO_L_PD, BIT(24)),
> -	PINCTRL_CONF_DESC(38, REG_GPIO_L_PD, BIT(25)),
> -	PINCTRL_CONF_DESC(39, REG_GPIO_L_PD, BIT(26)),
> -	PINCTRL_CONF_DESC(40, REG_GPIO_L_PD, BIT(27)),
> -	PINCTRL_CONF_DESC(41, REG_GPIO_L_PD, BIT(28)),
> -	PINCTRL_CONF_DESC(42, REG_GPIO_L_PD, BIT(29)),
> -	PINCTRL_CONF_DESC(43, REG_GPIO_L_PD, BIT(30)),
> -	PINCTRL_CONF_DESC(44, REG_GPIO_L_PD, BIT(31)),
> -	PINCTRL_CONF_DESC(45, REG_GPIO_H_PD, BIT(0)),
> -	PINCTRL_CONF_DESC(46, REG_GPIO_H_PD, BIT(1)),
> -	PINCTRL_CONF_DESC(47, REG_GPIO_H_PD, BIT(2)),
> -	PINCTRL_CONF_DESC(48, REG_GPIO_H_PD, BIT(3)),
> -	PINCTRL_CONF_DESC(49, REG_GPIO_H_PD, BIT(4)),
> -	PINCTRL_CONF_DESC(50, REG_GPIO_H_PD, BIT(5)),
> -	PINCTRL_CONF_DESC(51, REG_GPIO_H_PD, BIT(6)),
> -	PINCTRL_CONF_DESC(52, REG_GPIO_H_PD, BIT(7)),
> -	PINCTRL_CONF_DESC(53, REG_GPIO_H_PD, BIT(8)),
> -	PINCTRL_CONF_DESC(54, REG_GPIO_H_PD, BIT(9)),
> -	PINCTRL_CONF_DESC(55, REG_GPIO_H_PD, BIT(10)),
> -	PINCTRL_CONF_DESC(56, REG_GPIO_H_PD, BIT(11)),
> -	PINCTRL_CONF_DESC(57, REG_GPIO_H_PD, BIT(12)),
> -	PINCTRL_CONF_DESC(58, REG_GPIO_H_PD, BIT(13)),
> -	PINCTRL_CONF_DESC(59, REG_GPIO_H_PD, BIT(14)),
> -	PINCTRL_CONF_DESC(60, REG_I2C_SDA_PD, PCIE0_RESET_PD_MASK),
> -	PINCTRL_CONF_DESC(61, REG_I2C_SDA_PD, PCIE1_RESET_PD_MASK),
> -	PINCTRL_CONF_DESC(62, REG_I2C_SDA_PD, PCIE2_RESET_PD_MASK),
> -};
> -
> -static const struct airoha_pinctrl_conf an7583_pinctrl_pulldown_conf[] = {
> -	PINCTRL_CONF_DESC(2, REG_GPIO_L_PD, BIT(0)),
> -	PINCTRL_CONF_DESC(3, REG_GPIO_L_PD, BIT(1)),
> -	PINCTRL_CONF_DESC(4, REG_GPIO_L_PD, BIT(2)),
> -	PINCTRL_CONF_DESC(5, REG_GPIO_L_PD, BIT(3)),
> -	PINCTRL_CONF_DESC(6, REG_GPIO_L_PD, BIT(4)),
> -	PINCTRL_CONF_DESC(7, REG_GPIO_L_PD, BIT(5)),
> -	PINCTRL_CONF_DESC(8, REG_GPIO_L_PD, BIT(6)),
> -	PINCTRL_CONF_DESC(9, REG_GPIO_L_PD, BIT(7)),
> -	PINCTRL_CONF_DESC(10, REG_GPIO_L_PD, BIT(8)),
> -	PINCTRL_CONF_DESC(11, REG_GPIO_L_PD, BIT(9)),
> -	PINCTRL_CONF_DESC(12, REG_GPIO_L_PD, BIT(10)),
> -	PINCTRL_CONF_DESC(13, REG_GPIO_L_PD, BIT(11)),
> -	PINCTRL_CONF_DESC(14, REG_GPIO_L_PD, BIT(12)),
> -	PINCTRL_CONF_DESC(15, REG_GPIO_L_PD, BIT(13)),
> -	PINCTRL_CONF_DESC(16, REG_GPIO_L_PD, BIT(14)),
> -	PINCTRL_CONF_DESC(17, REG_GPIO_L_PD, BIT(15)),
> -	PINCTRL_CONF_DESC(18, REG_GPIO_L_PD, BIT(16)),
> -	PINCTRL_CONF_DESC(19, REG_GPIO_L_PD, BIT(17)),
> -	PINCTRL_CONF_DESC(20, REG_GPIO_L_PD, BIT(18)),
> -	PINCTRL_CONF_DESC(21, REG_GPIO_L_PD, BIT(19)),
> -	PINCTRL_CONF_DESC(22, REG_GPIO_L_PD, BIT(20)),
> -	PINCTRL_CONF_DESC(23, REG_GPIO_L_PD, BIT(21)),
> -	PINCTRL_CONF_DESC(24, REG_GPIO_L_PD, BIT(22)),
> -	PINCTRL_CONF_DESC(25, REG_GPIO_L_PD, BIT(23)),
> -	PINCTRL_CONF_DESC(26, REG_GPIO_L_PD, BIT(24)),
> -	PINCTRL_CONF_DESC(27, REG_GPIO_L_PD, BIT(25)),
> -	PINCTRL_CONF_DESC(28, REG_GPIO_L_PD, BIT(26)),
> -	PINCTRL_CONF_DESC(29, REG_GPIO_L_PD, BIT(27)),
> -	PINCTRL_CONF_DESC(30, REG_GPIO_L_PD, BIT(28)),
> -	PINCTRL_CONF_DESC(31, REG_GPIO_L_PD, BIT(29)),
> -	PINCTRL_CONF_DESC(32, REG_GPIO_L_PD, BIT(30)),
> -	PINCTRL_CONF_DESC(33, REG_GPIO_L_PD, BIT(31)),
> -	PINCTRL_CONF_DESC(34, REG_GPIO_H_PD, BIT(0)),
> -	PINCTRL_CONF_DESC(35, REG_GPIO_H_PD, BIT(1)),
> -	PINCTRL_CONF_DESC(36, REG_GPIO_H_PD, BIT(2)),
> -	PINCTRL_CONF_DESC(37, REG_GPIO_H_PD, BIT(3)),
> -	PINCTRL_CONF_DESC(38, REG_GPIO_H_PD, BIT(4)),
> -	PINCTRL_CONF_DESC(39, REG_GPIO_H_PD, BIT(5)),
> -	PINCTRL_CONF_DESC(40, REG_GPIO_H_PD, BIT(6)),
> -	PINCTRL_CONF_DESC(41, REG_I2C_SDA_PD, I2C_SCL_PD_MASK),
> -	PINCTRL_CONF_DESC(42, REG_I2C_SDA_PD, I2C_SDA_PD_MASK),
> -	PINCTRL_CONF_DESC(43, REG_I2C_SDA_PD, AN7583_I2C1_SCL_PD_MASK),
> -	PINCTRL_CONF_DESC(44, REG_I2C_SDA_PD, AN7583_I2C1_SDA_PD_MASK),
> -	PINCTRL_CONF_DESC(45, REG_I2C_SDA_PD, SPI_CLK_PD_MASK),
> -	PINCTRL_CONF_DESC(46, REG_I2C_SDA_PD, SPI_CS0_PD_MASK),
> -	PINCTRL_CONF_DESC(47, REG_I2C_SDA_PD, SPI_MOSI_PD_MASK),
> -	PINCTRL_CONF_DESC(48, REG_I2C_SDA_PD, SPI_MISO_PD_MASK),
> -	PINCTRL_CONF_DESC(49, REG_I2C_SDA_PD, UART1_TXD_PD_MASK),
> -	PINCTRL_CONF_DESC(50, REG_I2C_SDA_PD, UART1_RXD_PD_MASK),
> -	PINCTRL_CONF_DESC(51, REG_I2C_SDA_PD, PCIE0_RESET_PD_MASK),
> -	PINCTRL_CONF_DESC(52, REG_I2C_SDA_PD, PCIE1_RESET_PD_MASK),
> -	PINCTRL_CONF_DESC(53, REG_I2C_SDA_PD, AN7583_MDC_0_PD_MASK),
> -	PINCTRL_CONF_DESC(54, REG_I2C_SDA_PD, AN7583_MDIO_0_PD_MASK),
> -};
> -
> -static const struct airoha_pinctrl_conf en7581_pinctrl_drive_e2_conf[] = {
> -	PINCTRL_CONF_DESC(0, REG_I2C_SDA_E2, UART1_TXD_E2_MASK),
> -	PINCTRL_CONF_DESC(1, REG_I2C_SDA_E2, UART1_RXD_E2_MASK),
> -	PINCTRL_CONF_DESC(2, REG_I2C_SDA_E2, I2C_SDA_E2_MASK),
> -	PINCTRL_CONF_DESC(3, REG_I2C_SDA_E2, I2C_SCL_E2_MASK),
> -	PINCTRL_CONF_DESC(4, REG_I2C_SDA_E2, SPI_CS0_E2_MASK),
> -	PINCTRL_CONF_DESC(5, REG_I2C_SDA_E2, SPI_CLK_E2_MASK),
> -	PINCTRL_CONF_DESC(6, REG_I2C_SDA_E2, SPI_MOSI_E2_MASK),
> -	PINCTRL_CONF_DESC(7, REG_I2C_SDA_E2, SPI_MISO_E2_MASK),
> -	PINCTRL_CONF_DESC(13, REG_GPIO_L_E2, BIT(0)),
> -	PINCTRL_CONF_DESC(14, REG_GPIO_L_E2, BIT(1)),
> -	PINCTRL_CONF_DESC(15, REG_GPIO_L_E2, BIT(2)),
> -	PINCTRL_CONF_DESC(16, REG_GPIO_L_E2, BIT(3)),
> -	PINCTRL_CONF_DESC(17, REG_GPIO_L_E2, BIT(4)),
> -	PINCTRL_CONF_DESC(18, REG_GPIO_L_E2, BIT(5)),
> -	PINCTRL_CONF_DESC(19, REG_GPIO_L_E2, BIT(6)),
> -	PINCTRL_CONF_DESC(20, REG_GPIO_L_E2, BIT(7)),
> -	PINCTRL_CONF_DESC(21, REG_GPIO_L_E2, BIT(8)),
> -	PINCTRL_CONF_DESC(22, REG_GPIO_L_E2, BIT(9)),
> -	PINCTRL_CONF_DESC(23, REG_GPIO_L_E2, BIT(10)),
> -	PINCTRL_CONF_DESC(24, REG_GPIO_L_E2, BIT(11)),
> -	PINCTRL_CONF_DESC(25, REG_GPIO_L_E2, BIT(12)),
> -	PINCTRL_CONF_DESC(26, REG_GPIO_L_E2, BIT(13)),
> -	PINCTRL_CONF_DESC(27, REG_GPIO_L_E2, BIT(14)),
> -	PINCTRL_CONF_DESC(28, REG_GPIO_L_E2, BIT(15)),
> -	PINCTRL_CONF_DESC(29, REG_GPIO_L_E2, BIT(16)),
> -	PINCTRL_CONF_DESC(30, REG_GPIO_L_E2, BIT(17)),
> -	PINCTRL_CONF_DESC(31, REG_GPIO_L_E2, BIT(18)),
> -	PINCTRL_CONF_DESC(32, REG_GPIO_L_E2, BIT(19)),
> -	PINCTRL_CONF_DESC(33, REG_GPIO_L_E2, BIT(20)),
> -	PINCTRL_CONF_DESC(34, REG_GPIO_L_E2, BIT(21)),
> -	PINCTRL_CONF_DESC(35, REG_GPIO_L_E2, BIT(22)),
> -	PINCTRL_CONF_DESC(36, REG_GPIO_L_E2, BIT(23)),
> -	PINCTRL_CONF_DESC(37, REG_GPIO_L_E2, BIT(24)),
> -	PINCTRL_CONF_DESC(38, REG_GPIO_L_E2, BIT(25)),
> -	PINCTRL_CONF_DESC(39, REG_GPIO_L_E2, BIT(26)),
> -	PINCTRL_CONF_DESC(40, REG_GPIO_L_E2, BIT(27)),
> -	PINCTRL_CONF_DESC(41, REG_GPIO_L_E2, BIT(28)),
> -	PINCTRL_CONF_DESC(42, REG_GPIO_L_E2, BIT(29)),
> -	PINCTRL_CONF_DESC(43, REG_GPIO_L_E2, BIT(30)),
> -	PINCTRL_CONF_DESC(44, REG_GPIO_L_E2, BIT(31)),
> -	PINCTRL_CONF_DESC(45, REG_GPIO_H_E2, BIT(0)),
> -	PINCTRL_CONF_DESC(46, REG_GPIO_H_E2, BIT(1)),
> -	PINCTRL_CONF_DESC(47, REG_GPIO_H_E2, BIT(2)),
> -	PINCTRL_CONF_DESC(48, REG_GPIO_H_E2, BIT(3)),
> -	PINCTRL_CONF_DESC(49, REG_GPIO_H_E2, BIT(4)),
> -	PINCTRL_CONF_DESC(50, REG_GPIO_H_E2, BIT(5)),
> -	PINCTRL_CONF_DESC(51, REG_GPIO_H_E2, BIT(6)),
> -	PINCTRL_CONF_DESC(52, REG_GPIO_H_E2, BIT(7)),
> -	PINCTRL_CONF_DESC(53, REG_GPIO_H_E2, BIT(8)),
> -	PINCTRL_CONF_DESC(54, REG_GPIO_H_E2, BIT(9)),
> -	PINCTRL_CONF_DESC(55, REG_GPIO_H_E2, BIT(10)),
> -	PINCTRL_CONF_DESC(56, REG_GPIO_H_E2, BIT(11)),
> -	PINCTRL_CONF_DESC(57, REG_GPIO_H_E2, BIT(12)),
> -	PINCTRL_CONF_DESC(58, REG_GPIO_H_E2, BIT(13)),
> -	PINCTRL_CONF_DESC(59, REG_GPIO_H_E2, BIT(14)),
> -	PINCTRL_CONF_DESC(60, REG_I2C_SDA_E2, PCIE0_RESET_E2_MASK),
> -	PINCTRL_CONF_DESC(61, REG_I2C_SDA_E2, PCIE1_RESET_E2_MASK),
> -	PINCTRL_CONF_DESC(62, REG_I2C_SDA_E2, PCIE2_RESET_E2_MASK),
> -};
> -
> -static const struct airoha_pinctrl_conf an7583_pinctrl_drive_e2_conf[] = {
> -	PINCTRL_CONF_DESC(2, REG_GPIO_L_E2, BIT(0)),
> -	PINCTRL_CONF_DESC(3, REG_GPIO_L_E2, BIT(1)),
> -	PINCTRL_CONF_DESC(4, REG_GPIO_L_E2, BIT(2)),
> -	PINCTRL_CONF_DESC(5, REG_GPIO_L_E2, BIT(3)),
> -	PINCTRL_CONF_DESC(6, REG_GPIO_L_E2, BIT(4)),
> -	PINCTRL_CONF_DESC(7, REG_GPIO_L_E2, BIT(5)),
> -	PINCTRL_CONF_DESC(8, REG_GPIO_L_E2, BIT(6)),
> -	PINCTRL_CONF_DESC(9, REG_GPIO_L_E2, BIT(7)),
> -	PINCTRL_CONF_DESC(10, REG_GPIO_L_E2, BIT(8)),
> -	PINCTRL_CONF_DESC(11, REG_GPIO_L_E2, BIT(9)),
> -	PINCTRL_CONF_DESC(12, REG_GPIO_L_E2, BIT(10)),
> -	PINCTRL_CONF_DESC(13, REG_GPIO_L_E2, BIT(11)),
> -	PINCTRL_CONF_DESC(14, REG_GPIO_L_E2, BIT(12)),
> -	PINCTRL_CONF_DESC(15, REG_GPIO_L_E2, BIT(13)),
> -	PINCTRL_CONF_DESC(16, REG_GPIO_L_E2, BIT(14)),
> -	PINCTRL_CONF_DESC(17, REG_GPIO_L_E2, BIT(15)),
> -	PINCTRL_CONF_DESC(18, REG_GPIO_L_E2, BIT(16)),
> -	PINCTRL_CONF_DESC(19, REG_GPIO_L_E2, BIT(17)),
> -	PINCTRL_CONF_DESC(20, REG_GPIO_L_E2, BIT(18)),
> -	PINCTRL_CONF_DESC(21, REG_GPIO_L_E2, BIT(19)),
> -	PINCTRL_CONF_DESC(22, REG_GPIO_L_E2, BIT(20)),
> -	PINCTRL_CONF_DESC(23, REG_GPIO_L_E2, BIT(21)),
> -	PINCTRL_CONF_DESC(24, REG_GPIO_L_E2, BIT(22)),
> -	PINCTRL_CONF_DESC(25, REG_GPIO_L_E2, BIT(23)),
> -	PINCTRL_CONF_DESC(26, REG_GPIO_L_E2, BIT(24)),
> -	PINCTRL_CONF_DESC(27, REG_GPIO_L_E2, BIT(25)),
> -	PINCTRL_CONF_DESC(28, REG_GPIO_L_E2, BIT(26)),
> -	PINCTRL_CONF_DESC(29, REG_GPIO_L_E2, BIT(27)),
> -	PINCTRL_CONF_DESC(30, REG_GPIO_L_E2, BIT(28)),
> -	PINCTRL_CONF_DESC(31, REG_GPIO_L_E2, BIT(29)),
> -	PINCTRL_CONF_DESC(32, REG_GPIO_L_E2, BIT(30)),
> -	PINCTRL_CONF_DESC(33, REG_GPIO_L_E2, BIT(31)),
> -	PINCTRL_CONF_DESC(34, REG_GPIO_H_E2, BIT(0)),
> -	PINCTRL_CONF_DESC(35, REG_GPIO_H_E2, BIT(1)),
> -	PINCTRL_CONF_DESC(36, REG_GPIO_H_E2, BIT(2)),
> -	PINCTRL_CONF_DESC(37, REG_GPIO_H_E2, BIT(3)),
> -	PINCTRL_CONF_DESC(38, REG_GPIO_H_E2, BIT(4)),
> -	PINCTRL_CONF_DESC(39, REG_GPIO_H_E2, BIT(5)),
> -	PINCTRL_CONF_DESC(40, REG_GPIO_H_E2, BIT(6)),
> -	PINCTRL_CONF_DESC(41, REG_I2C_SDA_E2, I2C_SCL_E2_MASK),
> -	PINCTRL_CONF_DESC(42, REG_I2C_SDA_E2, I2C_SDA_E2_MASK),
> -	PINCTRL_CONF_DESC(43, REG_I2C_SDA_E2, AN7583_I2C1_SCL_E2_MASK),
> -	PINCTRL_CONF_DESC(44, REG_I2C_SDA_E2, AN7583_I2C1_SDA_E2_MASK),
> -	PINCTRL_CONF_DESC(45, REG_I2C_SDA_E2, SPI_CLK_E2_MASK),
> -	PINCTRL_CONF_DESC(46, REG_I2C_SDA_E2, SPI_CS0_E2_MASK),
> -	PINCTRL_CONF_DESC(47, REG_I2C_SDA_E2, SPI_MOSI_E2_MASK),
> -	PINCTRL_CONF_DESC(48, REG_I2C_SDA_E2, SPI_MISO_E2_MASK),
> -	PINCTRL_CONF_DESC(49, REG_I2C_SDA_E2, UART1_TXD_E2_MASK),
> -	PINCTRL_CONF_DESC(50, REG_I2C_SDA_E2, UART1_RXD_E2_MASK),
> -	PINCTRL_CONF_DESC(51, REG_I2C_SDA_E2, PCIE0_RESET_E2_MASK),
> -	PINCTRL_CONF_DESC(52, REG_I2C_SDA_E2, PCIE1_RESET_E2_MASK),
> -	PINCTRL_CONF_DESC(53, REG_I2C_SDA_E2, AN7583_MDC_0_E2_MASK),
> -	PINCTRL_CONF_DESC(54, REG_I2C_SDA_E2, AN7583_MDIO_0_E2_MASK),
> -};
> -
> -static const struct airoha_pinctrl_conf en7581_pinctrl_drive_e4_conf[] = {
> -	PINCTRL_CONF_DESC(0, REG_I2C_SDA_E4, UART1_TXD_E4_MASK),
> -	PINCTRL_CONF_DESC(1, REG_I2C_SDA_E4, UART1_RXD_E4_MASK),
> -	PINCTRL_CONF_DESC(2, REG_I2C_SDA_E4, I2C_SDA_E4_MASK),
> -	PINCTRL_CONF_DESC(3, REG_I2C_SDA_E4, I2C_SCL_E4_MASK),
> -	PINCTRL_CONF_DESC(4, REG_I2C_SDA_E4, SPI_CS0_E4_MASK),
> -	PINCTRL_CONF_DESC(5, REG_I2C_SDA_E4, SPI_CLK_E4_MASK),
> -	PINCTRL_CONF_DESC(6, REG_I2C_SDA_E4, SPI_MOSI_E4_MASK),
> -	PINCTRL_CONF_DESC(7, REG_I2C_SDA_E4, SPI_MISO_E4_MASK),
> -	PINCTRL_CONF_DESC(13, REG_GPIO_L_E4, BIT(0)),
> -	PINCTRL_CONF_DESC(14, REG_GPIO_L_E4, BIT(1)),
> -	PINCTRL_CONF_DESC(15, REG_GPIO_L_E4, BIT(2)),
> -	PINCTRL_CONF_DESC(16, REG_GPIO_L_E4, BIT(3)),
> -	PINCTRL_CONF_DESC(17, REG_GPIO_L_E4, BIT(4)),
> -	PINCTRL_CONF_DESC(18, REG_GPIO_L_E4, BIT(5)),
> -	PINCTRL_CONF_DESC(19, REG_GPIO_L_E4, BIT(6)),
> -	PINCTRL_CONF_DESC(20, REG_GPIO_L_E4, BIT(7)),
> -	PINCTRL_CONF_DESC(21, REG_GPIO_L_E4, BIT(8)),
> -	PINCTRL_CONF_DESC(22, REG_GPIO_L_E4, BIT(9)),
> -	PINCTRL_CONF_DESC(23, REG_GPIO_L_E4, BIT(10)),
> -	PINCTRL_CONF_DESC(24, REG_GPIO_L_E4, BIT(11)),
> -	PINCTRL_CONF_DESC(25, REG_GPIO_L_E4, BIT(12)),
> -	PINCTRL_CONF_DESC(26, REG_GPIO_L_E4, BIT(13)),
> -	PINCTRL_CONF_DESC(27, REG_GPIO_L_E4, BIT(14)),
> -	PINCTRL_CONF_DESC(28, REG_GPIO_L_E4, BIT(15)),
> -	PINCTRL_CONF_DESC(29, REG_GPIO_L_E4, BIT(16)),
> -	PINCTRL_CONF_DESC(30, REG_GPIO_L_E4, BIT(17)),
> -	PINCTRL_CONF_DESC(31, REG_GPIO_L_E4, BIT(18)),
> -	PINCTRL_CONF_DESC(32, REG_GPIO_L_E4, BIT(19)),
> -	PINCTRL_CONF_DESC(33, REG_GPIO_L_E4, BIT(20)),
> -	PINCTRL_CONF_DESC(34, REG_GPIO_L_E4, BIT(21)),
> -	PINCTRL_CONF_DESC(35, REG_GPIO_L_E4, BIT(22)),
> -	PINCTRL_CONF_DESC(36, REG_GPIO_L_E4, BIT(23)),
> -	PINCTRL_CONF_DESC(37, REG_GPIO_L_E4, BIT(24)),
> -	PINCTRL_CONF_DESC(38, REG_GPIO_L_E4, BIT(25)),
> -	PINCTRL_CONF_DESC(39, REG_GPIO_L_E4, BIT(26)),
> -	PINCTRL_CONF_DESC(40, REG_GPIO_L_E4, BIT(27)),
> -	PINCTRL_CONF_DESC(41, REG_GPIO_L_E4, BIT(28)),
> -	PINCTRL_CONF_DESC(42, REG_GPIO_L_E4, BIT(29)),
> -	PINCTRL_CONF_DESC(43, REG_GPIO_L_E4, BIT(30)),
> -	PINCTRL_CONF_DESC(44, REG_GPIO_L_E4, BIT(31)),
> -	PINCTRL_CONF_DESC(45, REG_GPIO_H_E4, BIT(0)),
> -	PINCTRL_CONF_DESC(46, REG_GPIO_H_E4, BIT(1)),
> -	PINCTRL_CONF_DESC(47, REG_GPIO_H_E4, BIT(2)),
> -	PINCTRL_CONF_DESC(48, REG_GPIO_H_E4, BIT(3)),
> -	PINCTRL_CONF_DESC(49, REG_GPIO_H_E4, BIT(4)),
> -	PINCTRL_CONF_DESC(50, REG_GPIO_H_E4, BIT(5)),
> -	PINCTRL_CONF_DESC(51, REG_GPIO_H_E4, BIT(6)),
> -	PINCTRL_CONF_DESC(52, REG_GPIO_H_E4, BIT(7)),
> -	PINCTRL_CONF_DESC(53, REG_GPIO_H_E4, BIT(8)),
> -	PINCTRL_CONF_DESC(54, REG_GPIO_H_E4, BIT(9)),
> -	PINCTRL_CONF_DESC(55, REG_GPIO_H_E4, BIT(10)),
> -	PINCTRL_CONF_DESC(56, REG_GPIO_H_E4, BIT(11)),
> -	PINCTRL_CONF_DESC(57, REG_GPIO_H_E4, BIT(12)),
> -	PINCTRL_CONF_DESC(58, REG_GPIO_H_E4, BIT(13)),
> -	PINCTRL_CONF_DESC(59, REG_GPIO_H_E4, BIT(14)),
> -	PINCTRL_CONF_DESC(60, REG_I2C_SDA_E4, PCIE0_RESET_E4_MASK),
> -	PINCTRL_CONF_DESC(61, REG_I2C_SDA_E4, PCIE1_RESET_E4_MASK),
> -	PINCTRL_CONF_DESC(62, REG_I2C_SDA_E4, PCIE2_RESET_E4_MASK),
> -};
> -
> -static const struct airoha_pinctrl_conf an7583_pinctrl_drive_e4_conf[] = {
> -	PINCTRL_CONF_DESC(2, REG_GPIO_L_E4, BIT(0)),
> -	PINCTRL_CONF_DESC(3, REG_GPIO_L_E4, BIT(1)),
> -	PINCTRL_CONF_DESC(4, REG_GPIO_L_E4, BIT(2)),
> -	PINCTRL_CONF_DESC(5, REG_GPIO_L_E4, BIT(3)),
> -	PINCTRL_CONF_DESC(6, REG_GPIO_L_E4, BIT(4)),
> -	PINCTRL_CONF_DESC(7, REG_GPIO_L_E4, BIT(5)),
> -	PINCTRL_CONF_DESC(8, REG_GPIO_L_E4, BIT(6)),
> -	PINCTRL_CONF_DESC(9, REG_GPIO_L_E4, BIT(7)),
> -	PINCTRL_CONF_DESC(10, REG_GPIO_L_E4, BIT(8)),
> -	PINCTRL_CONF_DESC(11, REG_GPIO_L_E4, BIT(9)),
> -	PINCTRL_CONF_DESC(12, REG_GPIO_L_E4, BIT(10)),
> -	PINCTRL_CONF_DESC(13, REG_GPIO_L_E4, BIT(11)),
> -	PINCTRL_CONF_DESC(14, REG_GPIO_L_E4, BIT(12)),
> -	PINCTRL_CONF_DESC(15, REG_GPIO_L_E4, BIT(13)),
> -	PINCTRL_CONF_DESC(16, REG_GPIO_L_E4, BIT(14)),
> -	PINCTRL_CONF_DESC(17, REG_GPIO_L_E4, BIT(15)),
> -	PINCTRL_CONF_DESC(18, REG_GPIO_L_E4, BIT(16)),
> -	PINCTRL_CONF_DESC(19, REG_GPIO_L_E4, BIT(17)),
> -	PINCTRL_CONF_DESC(20, REG_GPIO_L_E4, BIT(18)),
> -	PINCTRL_CONF_DESC(21, REG_GPIO_L_E4, BIT(19)),
> -	PINCTRL_CONF_DESC(22, REG_GPIO_L_E4, BIT(20)),
> -	PINCTRL_CONF_DESC(23, REG_GPIO_L_E4, BIT(21)),
> -	PINCTRL_CONF_DESC(24, REG_GPIO_L_E4, BIT(22)),
> -	PINCTRL_CONF_DESC(25, REG_GPIO_L_E4, BIT(23)),
> -	PINCTRL_CONF_DESC(26, REG_GPIO_L_E4, BIT(24)),
> -	PINCTRL_CONF_DESC(27, REG_GPIO_L_E4, BIT(25)),
> -	PINCTRL_CONF_DESC(28, REG_GPIO_L_E4, BIT(26)),
> -	PINCTRL_CONF_DESC(29, REG_GPIO_L_E4, BIT(27)),
> -	PINCTRL_CONF_DESC(30, REG_GPIO_L_E4, BIT(28)),
> -	PINCTRL_CONF_DESC(31, REG_GPIO_L_E4, BIT(29)),
> -	PINCTRL_CONF_DESC(32, REG_GPIO_L_E4, BIT(30)),
> -	PINCTRL_CONF_DESC(33, REG_GPIO_L_E4, BIT(31)),
> -	PINCTRL_CONF_DESC(34, REG_GPIO_H_E4, BIT(0)),
> -	PINCTRL_CONF_DESC(35, REG_GPIO_H_E4, BIT(1)),
> -	PINCTRL_CONF_DESC(36, REG_GPIO_H_E4, BIT(2)),
> -	PINCTRL_CONF_DESC(37, REG_GPIO_H_E4, BIT(3)),
> -	PINCTRL_CONF_DESC(38, REG_GPIO_H_E4, BIT(4)),
> -	PINCTRL_CONF_DESC(39, REG_GPIO_H_E4, BIT(5)),
> -	PINCTRL_CONF_DESC(40, REG_GPIO_H_E4, BIT(6)),
> -	PINCTRL_CONF_DESC(41, REG_I2C_SDA_E4, I2C_SCL_E4_MASK),
> -	PINCTRL_CONF_DESC(42, REG_I2C_SDA_E4, I2C_SDA_E4_MASK),
> -	PINCTRL_CONF_DESC(43, REG_I2C_SDA_E4, AN7583_I2C1_SCL_E4_MASK),
> -	PINCTRL_CONF_DESC(44, REG_I2C_SDA_E4, AN7583_I2C1_SDA_E4_MASK),
> -	PINCTRL_CONF_DESC(45, REG_I2C_SDA_E4, SPI_CLK_E4_MASK),
> -	PINCTRL_CONF_DESC(46, REG_I2C_SDA_E4, SPI_CS0_E4_MASK),
> -	PINCTRL_CONF_DESC(47, REG_I2C_SDA_E4, SPI_MOSI_E4_MASK),
> -	PINCTRL_CONF_DESC(48, REG_I2C_SDA_E4, SPI_MISO_E4_MASK),
> -	PINCTRL_CONF_DESC(49, REG_I2C_SDA_E4, UART1_TXD_E4_MASK),
> -	PINCTRL_CONF_DESC(50, REG_I2C_SDA_E4, UART1_RXD_E4_MASK),
> -	PINCTRL_CONF_DESC(51, REG_I2C_SDA_E4, PCIE0_RESET_E4_MASK),
> -	PINCTRL_CONF_DESC(52, REG_I2C_SDA_E4, PCIE1_RESET_E4_MASK),
> -	PINCTRL_CONF_DESC(53, REG_I2C_SDA_E4, AN7583_MDC_0_E4_MASK),
> -	PINCTRL_CONF_DESC(54, REG_I2C_SDA_E4, AN7583_MDIO_0_E4_MASK),
> -};
> -
> -static const struct airoha_pinctrl_conf en7581_pinctrl_pcie_rst_od_conf[] = {
> -	PINCTRL_CONF_DESC(60, REG_PCIE_RESET_OD, PCIE0_RESET_OD_MASK),
> -	PINCTRL_CONF_DESC(61, REG_PCIE_RESET_OD, PCIE1_RESET_OD_MASK),
> -	PINCTRL_CONF_DESC(62, REG_PCIE_RESET_OD, PCIE2_RESET_OD_MASK),
> -};
> -
> -static const struct airoha_pinctrl_conf an7583_pinctrl_pcie_rst_od_conf[] = {
> -	PINCTRL_CONF_DESC(51, REG_PCIE_RESET_OD, PCIE0_RESET_OD_MASK),
> -	PINCTRL_CONF_DESC(52, REG_PCIE_RESET_OD, PCIE1_RESET_OD_MASK),
> -};
> -
>  static int airoha_convert_pin_to_reg_offset(struct pinctrl_dev *pctrl_dev,
>  					    struct pinctrl_gpio_range *range,
>  					    int pin)
> @@ -2606,6 +318,7 @@ static int airoha_pinctrl_add_gpiochip(struct airoha_pinctrl *pinctrl,
>  					struct platform_device *pdev)
>  {
>  	struct airoha_pinctrl_gpiochip *chip = &pinctrl->gpiochip;
> +	struct irq_chip *irq_chip = &pinctrl->gpio_irq_chip;
>  	struct gpio_chip *gc = &chip->chip;
>  	struct gpio_irq_chip *girq = &gc->irq;
>  	struct device *dev = &pdev->dev;
> @@ -2630,9 +343,11 @@ static int airoha_pinctrl_add_gpiochip(struct airoha_pinctrl *pinctrl,
>  	gc->base = -1;
>  	gc->ngpio = AIROHA_NUM_PINS;
>  
> +	memcpy(irq_chip, &airoha_gpio_irq_chip, sizeof(struct irq_chip));
> +
>  	girq->default_type = IRQ_TYPE_NONE;
>  	girq->handler = handle_bad_irq;
> -	gpio_irq_chip_set_chip(girq, &airoha_gpio_irq_chip);
> +	gpio_irq_chip_set_chip(girq, irq_chip);
>  
>  	irq = platform_get_irq(pdev, 0);
>  	if (irq < 0)
> @@ -3011,7 +726,7 @@ static const struct pinctrl_ops airoha_pctlops = {
>  	.dt_free_map = pinconf_generic_dt_free_map,
>  };
>  
> -static int airoha_pinctrl_probe(struct platform_device *pdev)
> +int airoha_pinctrl_probe(struct platform_device *pdev)
>  {
>  	const struct airoha_pinctrl_match_data *data;
>  	struct device *dev = &pdev->dev;
> @@ -3020,6 +735,8 @@ static int airoha_pinctrl_probe(struct platform_device *pdev)
>  	int err, i;
>  
>  	data = device_get_match_data(dev);
> +	if (!data)
> +		return -EINVAL;
>  
>  	pinctrl = devm_kzalloc(dev, sizeof(*pinctrl), GFP_KERNEL);
>  	if (!pinctrl)
> @@ -3036,8 +753,8 @@ static int airoha_pinctrl_probe(struct platform_device *pdev)
>  	pinctrl->chip_scu = map;
>  
>  	/* Init pinctrl desc struct */
> -	pinctrl->desc.name = KBUILD_MODNAME;
> -	pinctrl->desc.owner = THIS_MODULE;
> +	pinctrl->desc.name = data->pinctrl_name;
> +	pinctrl->desc.owner = data->pinctrl_owner;
>  	pinctrl->desc.pctlops = &airoha_pctlops;
>  	pinctrl->desc.pmxops = &airoha_pmxops;
>  	pinctrl->desc.confops = &airoha_confops;
> @@ -3089,87 +806,10 @@ static int airoha_pinctrl_probe(struct platform_device *pdev)
>  	/* build gpio-chip */
>  	return airoha_pinctrl_add_gpiochip(pinctrl, pdev);
>  }
> -
> -static const struct airoha_pinctrl_match_data en7581_pinctrl_match_data = {
> -	.pins = en7581_pinctrl_pins,
> -	.num_pins = ARRAY_SIZE(en7581_pinctrl_pins),
> -	.grps = en7581_pinctrl_groups,
> -	.num_grps = ARRAY_SIZE(en7581_pinctrl_groups),
> -	.funcs = en7581_pinctrl_funcs,
> -	.num_funcs = ARRAY_SIZE(en7581_pinctrl_funcs),
> -	.confs_info = {
> -		[AIROHA_PINCTRL_CONFS_PULLUP] = {
> -			.confs = en7581_pinctrl_pullup_conf,
> -			.num_confs = ARRAY_SIZE(en7581_pinctrl_pullup_conf),
> -		},
> -		[AIROHA_PINCTRL_CONFS_PULLDOWN] = {
> -			.confs = en7581_pinctrl_pulldown_conf,
> -			.num_confs = ARRAY_SIZE(en7581_pinctrl_pulldown_conf),
> -		},
> -		[AIROHA_PINCTRL_CONFS_DRIVE_E2] = {
> -			.confs = en7581_pinctrl_drive_e2_conf,
> -			.num_confs = ARRAY_SIZE(en7581_pinctrl_drive_e2_conf),
> -		},
> -		[AIROHA_PINCTRL_CONFS_DRIVE_E4] = {
> -			.confs = en7581_pinctrl_drive_e4_conf,
> -			.num_confs = ARRAY_SIZE(en7581_pinctrl_drive_e4_conf),
> -		},
> -		[AIROHA_PINCTRL_CONFS_PCIE_RST_OD] = {
> -			.confs = en7581_pinctrl_pcie_rst_od_conf,
> -			.num_confs = ARRAY_SIZE(en7581_pinctrl_pcie_rst_od_conf),
> -		},
> -	},
> -};
> -
> -static const struct airoha_pinctrl_match_data an7583_pinctrl_match_data = {
> -	.pins = an7583_pinctrl_pins,
> -	.num_pins = ARRAY_SIZE(an7583_pinctrl_pins),
> -	.grps = an7583_pinctrl_groups,
> -	.num_grps = ARRAY_SIZE(an7583_pinctrl_groups),
> -	.funcs = an7583_pinctrl_funcs,
> -	.num_funcs = ARRAY_SIZE(an7583_pinctrl_funcs),
> -	.confs_info = {
> -		[AIROHA_PINCTRL_CONFS_PULLUP] = {
> -			.confs = an7583_pinctrl_pullup_conf,
> -			.num_confs = ARRAY_SIZE(an7583_pinctrl_pullup_conf),
> -		},
> -		[AIROHA_PINCTRL_CONFS_PULLDOWN] = {
> -			.confs = an7583_pinctrl_pulldown_conf,
> -			.num_confs = ARRAY_SIZE(an7583_pinctrl_pulldown_conf),
> -		},
> -		[AIROHA_PINCTRL_CONFS_DRIVE_E2] = {
> -			.confs = an7583_pinctrl_drive_e2_conf,
> -			.num_confs = ARRAY_SIZE(an7583_pinctrl_drive_e2_conf),
> -		},
> -		[AIROHA_PINCTRL_CONFS_DRIVE_E4] = {
> -			.confs = an7583_pinctrl_drive_e4_conf,
> -			.num_confs = ARRAY_SIZE(an7583_pinctrl_drive_e4_conf),
> -		},
> -		[AIROHA_PINCTRL_CONFS_PCIE_RST_OD] = {
> -			.confs = an7583_pinctrl_pcie_rst_od_conf,
> -			.num_confs = ARRAY_SIZE(an7583_pinctrl_pcie_rst_od_conf),
> -		},
> -	},
> -};
> -
> -static const struct of_device_id airoha_pinctrl_of_match[] = {
> -	{ .compatible = "airoha,en7581-pinctrl", .data = &en7581_pinctrl_match_data },
> -	{ .compatible = "airoha,an7583-pinctrl", .data = &an7583_pinctrl_match_data },
> -	{ /* sentinel */ }
> -};
> -MODULE_DEVICE_TABLE(of, airoha_pinctrl_of_match);
> -
> -static struct platform_driver airoha_pinctrl_driver = {
> -	.probe = airoha_pinctrl_probe,
> -	.driver = {
> -		.name = "pinctrl-airoha",
> -		.of_match_table = airoha_pinctrl_of_match,
> -	},
> -};
> -module_platform_driver(airoha_pinctrl_driver);
> +EXPORT_SYMBOL_GPL(airoha_pinctrl_probe);
>  
>  MODULE_LICENSE("GPL");
>  MODULE_AUTHOR("Lorenzo Bianconi <lorenzo@kernel.org>");
>  MODULE_AUTHOR("Benjamin Larsson <benjamin.larsson@genexis.eu>");
>  MODULE_AUTHOR("Markus Gothe <markus.gothe@genexis.eu>");
> -MODULE_DESCRIPTION("Pinctrl driver for Airoha SoC");
> +MODULE_DESCRIPTION("Pinctrl common driver for Airoha SoC");
> diff --git a/drivers/pinctrl/airoha/pinctrl-an7581.c b/drivers/pinctrl/airoha/pinctrl-an7581.c
> new file mode 100644
> index 0000000000000..522b35bbaa121
> --- /dev/null
> +++ b/drivers/pinctrl/airoha/pinctrl-an7581.c
> @@ -0,0 +1,1486 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Author: Lorenzo Bianconi <lorenzo@kernel.org>
> + * Author: Benjamin Larsson <benjamin.larsson@genexis.eu>
> + * Author: Markus Gothe <markus.gothe@genexis.eu>
> + */
> +
> +#include "airoha-common.h"
> +
> +/* MUX */
> +#define REG_GPIO_2ND_I2C_MODE			0x0214
> +#define GPIO_MDC_IO_MASTER_MODE_MASK		BIT(14)
> +#define GPIO_I2C_MASTER_MODE_MODE		BIT(13)
> +#define GPIO_I2S_MODE_MASK			BIT(12)
> +#define GPIO_I2C_SLAVE_MODE_MODE		BIT(11)
> +#define GPIO_LAN3_LED1_MODE_MASK		BIT(10)
> +#define GPIO_LAN3_LED0_MODE_MASK		BIT(9)
> +#define GPIO_LAN2_LED1_MODE_MASK		BIT(8)
> +#define GPIO_LAN2_LED0_MODE_MASK		BIT(7)
> +#define GPIO_LAN1_LED1_MODE_MASK		BIT(6)
> +#define GPIO_LAN1_LED0_MODE_MASK		BIT(5)
> +#define GPIO_LAN0_LED1_MODE_MASK		BIT(4)
> +#define GPIO_LAN0_LED0_MODE_MASK		BIT(3)
> +#define PON_TOD_1PPS_MODE_MASK			BIT(2)
> +#define GSW_TOD_1PPS_MODE_MASK			BIT(1)
> +#define GPIO_2ND_I2C_MODE_MASK			BIT(0)
> +
> +#define REG_GPIO_SPI_CS1_MODE			0x0218
> +#define GPIO_PCM_SPI_CS4_MODE_MASK		BIT(21)
> +#define GPIO_PCM_SPI_CS3_MODE_MASK		BIT(20)
> +#define GPIO_PCM_SPI_CS2_MODE_P156_MASK		BIT(19)
> +#define GPIO_PCM_SPI_CS2_MODE_P128_MASK		BIT(18)
> +#define GPIO_PCM_SPI_CS1_MODE_MASK		BIT(17)
> +#define GPIO_PCM_SPI_MODE_MASK			BIT(16)
> +#define GPIO_PCM2_MODE_MASK			BIT(13)
> +#define GPIO_PCM1_MODE_MASK			BIT(12)
> +#define GPIO_PCM_INT_MODE_MASK			BIT(9)
> +#define GPIO_PCM_RESET_MODE_MASK		BIT(8)
> +#define GPIO_SPI_QUAD_MODE_MASK			BIT(4)
> +#define GPIO_SPI_CS4_MODE_MASK			BIT(3)
> +#define GPIO_SPI_CS3_MODE_MASK			BIT(2)
> +#define GPIO_SPI_CS2_MODE_MASK			BIT(1)
> +#define GPIO_SPI_CS1_MODE_MASK			BIT(0)
> +
> +#define REG_GPIO_PON_MODE			0x021c
> +#define GPIO_PARALLEL_NAND_MODE_MASK		BIT(14)
> +#define GPIO_SGMII_MDIO_MODE_MASK		BIT(13)
> +#define GPIO_PCIE_RESET2_MASK			BIT(12)
> +#define SIPO_RCLK_MODE_MASK			BIT(11)
> +#define GPIO_PCIE_RESET1_MASK			BIT(10)
> +#define GPIO_PCIE_RESET0_MASK			BIT(9)
> +#define GPIO_UART5_MODE_MASK			BIT(8)
> +#define GPIO_UART4_MODE_MASK			BIT(7)
> +#define GPIO_HSUART_CTS_RTS_MODE_MASK		BIT(6)
> +#define GPIO_HSUART_MODE_MASK			BIT(5)
> +#define GPIO_UART2_CTS_RTS_MODE_MASK		BIT(4)
> +#define GPIO_UART2_MODE_MASK			BIT(3)
> +#define GPIO_SIPO_MODE_MASK			BIT(2)
> +#define GPIO_EMMC_MODE_MASK			BIT(1)
> +#define GPIO_PON_MODE_MASK			BIT(0)
> +
> +#define REG_NPU_UART_EN				0x0224
> +#define JTAG_UDI_EN_MASK			BIT(4)
> +#define JTAG_DFD_EN_MASK			BIT(3)
> +
> +#define REG_FORCE_GPIO_EN			0x0228
> +#define FORCE_GPIO_EN(n)			BIT(n)
> +
> +/* LED MAP */
> +#define REG_LAN_LED0_MAPPING			0x027c
> +#define REG_LAN_LED1_MAPPING			0x0280
> +
> +#define LAN4_LED_MAPPING_MASK			GENMASK(18, 16)
> +#define LAN4_PHY_LED_MAP(_n)			FIELD_PREP_CONST(LAN4_LED_MAPPING_MASK, (_n))
> +
> +#define LAN3_LED_MAPPING_MASK			GENMASK(14, 12)
> +#define LAN3_PHY_LED_MAP(_n)			FIELD_PREP_CONST(LAN3_LED_MAPPING_MASK, (_n))
> +
> +#define LAN2_LED_MAPPING_MASK			GENMASK(10, 8)
> +#define LAN2_PHY_LED_MAP(_n)			FIELD_PREP_CONST(LAN2_LED_MAPPING_MASK, (_n))
> +
> +#define LAN1_LED_MAPPING_MASK			GENMASK(6, 4)
> +#define LAN1_PHY_LED_MAP(_n)			FIELD_PREP_CONST(LAN1_LED_MAPPING_MASK, (_n))
> +
> +#define LAN0_LED_MAPPING_MASK			GENMASK(2, 0)
> +#define LAN0_PHY_LED_MAP(_n)			FIELD_PREP_CONST(LAN0_LED_MAPPING_MASK, (_n))
> +
> +/* CONF */
> +#define REG_I2C_SDA_E2				0x001c
> +#define SPI_MISO_E2_MASK			BIT(14)
> +#define SPI_MOSI_E2_MASK			BIT(13)
> +#define SPI_CLK_E2_MASK				BIT(12)
> +#define SPI_CS0_E2_MASK				BIT(11)
> +#define PCIE2_RESET_E2_MASK			BIT(10)
> +#define PCIE1_RESET_E2_MASK			BIT(9)
> +#define PCIE0_RESET_E2_MASK			BIT(8)
> +#define UART1_RXD_E2_MASK			BIT(3)
> +#define UART1_TXD_E2_MASK			BIT(2)
> +#define I2C_SCL_E2_MASK				BIT(1)
> +#define I2C_SDA_E2_MASK				BIT(0)
> +
> +#define REG_I2C_SDA_E4				0x0020
> +#define SPI_MISO_E4_MASK			BIT(14)
> +#define SPI_MOSI_E4_MASK			BIT(13)
> +#define SPI_CLK_E4_MASK				BIT(12)
> +#define SPI_CS0_E4_MASK				BIT(11)
> +#define PCIE2_RESET_E4_MASK			BIT(10)
> +#define PCIE1_RESET_E4_MASK			BIT(9)
> +#define PCIE0_RESET_E4_MASK			BIT(8)
> +#define UART1_RXD_E4_MASK			BIT(3)
> +#define UART1_TXD_E4_MASK			BIT(2)
> +#define I2C_SCL_E4_MASK				BIT(1)
> +#define I2C_SDA_E4_MASK				BIT(0)
> +
> +#define REG_GPIO_L_E2				0x0024
> +#define REG_GPIO_L_E4				0x0028
> +#define REG_GPIO_H_E2				0x002c
> +#define REG_GPIO_H_E4				0x0030
> +
> +#define REG_I2C_SDA_PU				0x0044
> +#define SPI_MISO_PU_MASK			BIT(14)
> +#define SPI_MOSI_PU_MASK			BIT(13)
> +#define SPI_CLK_PU_MASK				BIT(12)
> +#define SPI_CS0_PU_MASK				BIT(11)
> +#define PCIE2_RESET_PU_MASK			BIT(10)
> +#define PCIE1_RESET_PU_MASK			BIT(9)
> +#define PCIE0_RESET_PU_MASK			BIT(8)
> +#define UART1_RXD_PU_MASK			BIT(3)
> +#define UART1_TXD_PU_MASK			BIT(2)
> +#define I2C_SCL_PU_MASK				BIT(1)
> +#define I2C_SDA_PU_MASK				BIT(0)
> +
> +#define REG_I2C_SDA_PD				0x0048
> +#define SPI_MISO_PD_MASK			BIT(14)
> +#define SPI_MOSI_PD_MASK			BIT(13)
> +#define SPI_CLK_PD_MASK				BIT(12)
> +#define SPI_CS0_PD_MASK				BIT(11)
> +#define PCIE2_RESET_PD_MASK			BIT(10)
> +#define PCIE1_RESET_PD_MASK			BIT(9)
> +#define PCIE0_RESET_PD_MASK			BIT(8)
> +#define UART1_RXD_PD_MASK			BIT(3)
> +#define UART1_TXD_PD_MASK			BIT(2)
> +#define I2C_SCL_PD_MASK				BIT(1)
> +#define I2C_SDA_PD_MASK				BIT(0)
> +
> +#define REG_GPIO_L_PU				0x004c
> +#define REG_GPIO_L_PD				0x0050
> +#define REG_GPIO_H_PU				0x0054
> +#define REG_GPIO_H_PD				0x0058
> +
> +#define REG_PCIE_RESET_OD			0x018c
> +#define PCIE2_RESET_OD_MASK			BIT(2)
> +#define PCIE1_RESET_OD_MASK			BIT(1)
> +#define PCIE0_RESET_OD_MASK			BIT(0)
> +
> +/* PWM MODE CONF */
> +#define REG_GPIO_FLASH_MODE_CFG			0x0034
> +#define GPIO15_FLASH_MODE_CFG			BIT(15)
> +#define GPIO14_FLASH_MODE_CFG			BIT(14)
> +#define GPIO13_FLASH_MODE_CFG			BIT(13)
> +#define GPIO12_FLASH_MODE_CFG			BIT(12)
> +#define GPIO11_FLASH_MODE_CFG			BIT(11)
> +#define GPIO10_FLASH_MODE_CFG			BIT(10)
> +#define GPIO9_FLASH_MODE_CFG			BIT(9)
> +#define GPIO8_FLASH_MODE_CFG			BIT(8)
> +#define GPIO7_FLASH_MODE_CFG			BIT(7)
> +#define GPIO6_FLASH_MODE_CFG			BIT(6)
> +#define GPIO5_FLASH_MODE_CFG			BIT(5)
> +#define GPIO4_FLASH_MODE_CFG			BIT(4)
> +#define GPIO3_FLASH_MODE_CFG			BIT(3)
> +#define GPIO2_FLASH_MODE_CFG			BIT(2)
> +#define GPIO1_FLASH_MODE_CFG			BIT(1)
> +#define GPIO0_FLASH_MODE_CFG			BIT(0)
> +
> +/* PWM MODE CONF EXT */
> +#define REG_GPIO_FLASH_MODE_CFG_EXT		0x0068
> +#define GPIO51_FLASH_MODE_CFG			BIT(31)
> +#define GPIO50_FLASH_MODE_CFG			BIT(30)
> +#define GPIO49_FLASH_MODE_CFG			BIT(29)
> +#define GPIO48_FLASH_MODE_CFG			BIT(28)
> +#define GPIO47_FLASH_MODE_CFG			BIT(27)
> +#define GPIO46_FLASH_MODE_CFG			BIT(26)
> +#define GPIO45_FLASH_MODE_CFG			BIT(25)
> +#define GPIO44_FLASH_MODE_CFG			BIT(24)
> +#define GPIO43_FLASH_MODE_CFG			BIT(23)
> +#define GPIO42_FLASH_MODE_CFG			BIT(22)
> +#define GPIO41_FLASH_MODE_CFG			BIT(21)
> +#define GPIO40_FLASH_MODE_CFG			BIT(20)
> +#define GPIO39_FLASH_MODE_CFG			BIT(19)
> +#define GPIO38_FLASH_MODE_CFG			BIT(18)
> +#define GPIO37_FLASH_MODE_CFG			BIT(17)
> +#define GPIO36_FLASH_MODE_CFG			BIT(16)
> +#define GPIO31_FLASH_MODE_CFG			BIT(15)
> +#define GPIO30_FLASH_MODE_CFG			BIT(14)
> +#define GPIO29_FLASH_MODE_CFG			BIT(13)
> +#define GPIO28_FLASH_MODE_CFG			BIT(12)
> +#define GPIO27_FLASH_MODE_CFG			BIT(11)
> +#define GPIO26_FLASH_MODE_CFG			BIT(10)
> +#define GPIO25_FLASH_MODE_CFG			BIT(9)
> +#define GPIO24_FLASH_MODE_CFG			BIT(8)
> +#define GPIO23_FLASH_MODE_CFG			BIT(7)
> +#define GPIO22_FLASH_MODE_CFG			BIT(6)
> +#define GPIO21_FLASH_MODE_CFG			BIT(5)
> +#define GPIO20_FLASH_MODE_CFG			BIT(4)
> +#define GPIO19_FLASH_MODE_CFG			BIT(3)
> +#define GPIO18_FLASH_MODE_CFG			BIT(2)
> +#define GPIO17_FLASH_MODE_CFG			BIT(1)
> +#define GPIO16_FLASH_MODE_CFG			BIT(0)
> +
> +#define AIROHA_PINCTRL_GPIO(gpio, mux_val)			\
> +	{							\
> +		.name = (gpio),					\
> +		.regmap[0] = {					\
> +			AIROHA_FUNC_MUX,			\
> +			REG_GPIO_PON_MODE,			\
> +			(mux_val),				\
> +			(mux_val)				\
> +		},						\
> +		.regmap_size = 1,				\
> +	}
> +
> +#define AIROHA_PINCTRL_GPIO_EXT(gpio, mux_val, smux_val)	\
> +	{							\
> +		.name = (gpio),					\
> +		.regmap[0] = {					\
> +			AIROHA_FUNC_PWM_EXT_MUX,		\
> +			REG_GPIO_FLASH_MODE_CFG_EXT,		\
> +			(mux_val),				\
> +			0					\
> +		},						\
> +		.regmap[1] = {					\
> +			AIROHA_FUNC_MUX,			\
> +			REG_GPIO_PON_MODE,			\
> +			(smux_val),				\
> +			(smux_val)				\
> +		},						\
> +		.regmap_size = 2,				\
> +	}
> +
> +/* PWM */
> +#define AIROHA_PINCTRL_PWM(gpio, mux_val)			\
> +	{							\
> +		.name = (gpio),					\
> +		.regmap[0] = {					\
> +			AIROHA_FUNC_PWM_MUX,			\
> +			REG_GPIO_FLASH_MODE_CFG,		\
> +			(mux_val),				\
> +			(mux_val)				\
> +		},						\
> +		.regmap_size = 1,				\
> +	}
> +
> +#define AIROHA_PINCTRL_PWM_EXT(gpio, mux_val)			\
> +	{							\
> +		.name = (gpio),					\
> +		.regmap[0] = {					\
> +			AIROHA_FUNC_PWM_EXT_MUX,		\
> +			REG_GPIO_FLASH_MODE_CFG_EXT,		\
> +			(mux_val),				\
> +			(mux_val)				\
> +		},						\
> +		.regmap_size = 1,				\
> +	}
> +
> +#define AIROHA_PINCTRL_PWM_EXT_SEC(gpio, mux_val, smux_val)	\
> +	{							\
> +		.name = (gpio),					\
> +		.regmap[0] = {					\
> +			AIROHA_FUNC_PWM_EXT_MUX,		\
> +			REG_GPIO_FLASH_MODE_CFG_EXT,		\
> +			(mux_val),				\
> +			(mux_val)				\
> +		},						\
> +		.regmap[1] = {					\
> +			AIROHA_FUNC_MUX,			\
> +			REG_GPIO_PON_MODE,			\
> +			(smux_val),				\
> +			(smux_val)				\
> +		},						\
> +		.regmap_size = 2,				\
> +	}
> +
> +#define AIROHA_PINCTRL_PHY_LED0(gpio, mux_val, map_mask, map_val)	\
> +	{								\
> +		.name = (gpio),						\
> +		.regmap[0] = {						\
> +			AIROHA_FUNC_MUX,				\
> +			REG_GPIO_2ND_I2C_MODE,				\
> +			(mux_val),					\
> +			(mux_val),					\
> +		},							\
> +		.regmap[1] = {						\
> +			AIROHA_FUNC_MUX,				\
> +			REG_LAN_LED0_MAPPING,				\
> +			(map_mask),					\
> +			(map_val),					\
> +		},							\
> +		.regmap_size = 2,					\
> +	}
> +
> +#define AIROHA_PINCTRL_PHY_LED1(gpio, mux_val, map_mask, map_val)	\
> +	{								\
> +		.name = (gpio),						\
> +		.regmap[0] = {						\
> +			AIROHA_FUNC_MUX,				\
> +			REG_GPIO_2ND_I2C_MODE,				\
> +			(mux_val),					\
> +			(mux_val),					\
> +		},							\
> +		.regmap[1] = {						\
> +			AIROHA_FUNC_MUX,				\
> +			REG_LAN_LED1_MAPPING,				\
> +			(map_mask),					\
> +			(map_val),					\
> +		},							\
> +		.regmap_size = 2,					\
> +	}
> +
> +static struct pinctrl_pin_desc en7581_pinctrl_pins[] = {
> +	PINCTRL_PIN(0, "uart1_txd"),
> +	PINCTRL_PIN(1, "uart1_rxd"),
> +	PINCTRL_PIN(2, "i2c_scl"),
> +	PINCTRL_PIN(3, "i2c_sda"),
> +	PINCTRL_PIN(4, "spi_cs0"),
> +	PINCTRL_PIN(5, "spi_clk"),
> +	PINCTRL_PIN(6, "spi_mosi"),
> +	PINCTRL_PIN(7, "spi_miso"),
> +	PINCTRL_PIN(13, "gpio0"),
> +	PINCTRL_PIN(14, "gpio1"),
> +	PINCTRL_PIN(15, "gpio2"),
> +	PINCTRL_PIN(16, "gpio3"),
> +	PINCTRL_PIN(17, "gpio4"),
> +	PINCTRL_PIN(18, "gpio5"),
> +	PINCTRL_PIN(19, "gpio6"),
> +	PINCTRL_PIN(20, "gpio7"),
> +	PINCTRL_PIN(21, "gpio8"),
> +	PINCTRL_PIN(22, "gpio9"),
> +	PINCTRL_PIN(23, "gpio10"),
> +	PINCTRL_PIN(24, "gpio11"),
> +	PINCTRL_PIN(25, "gpio12"),
> +	PINCTRL_PIN(26, "gpio13"),
> +	PINCTRL_PIN(27, "gpio14"),
> +	PINCTRL_PIN(28, "gpio15"),
> +	PINCTRL_PIN(29, "gpio16"),
> +	PINCTRL_PIN(30, "gpio17"),
> +	PINCTRL_PIN(31, "gpio18"),
> +	PINCTRL_PIN(32, "gpio19"),
> +	PINCTRL_PIN(33, "gpio20"),
> +	PINCTRL_PIN(34, "gpio21"),
> +	PINCTRL_PIN(35, "gpio22"),
> +	PINCTRL_PIN(36, "gpio23"),
> +	PINCTRL_PIN(37, "gpio24"),
> +	PINCTRL_PIN(38, "gpio25"),
> +	PINCTRL_PIN(39, "gpio26"),
> +	PINCTRL_PIN(40, "gpio27"),
> +	PINCTRL_PIN(41, "gpio28"),
> +	PINCTRL_PIN(42, "gpio29"),
> +	PINCTRL_PIN(43, "gpio30"),
> +	PINCTRL_PIN(44, "gpio31"),
> +	PINCTRL_PIN(45, "gpio32"),
> +	PINCTRL_PIN(46, "gpio33"),
> +	PINCTRL_PIN(47, "gpio34"),
> +	PINCTRL_PIN(48, "gpio35"),
> +	PINCTRL_PIN(49, "gpio36"),
> +	PINCTRL_PIN(50, "gpio37"),
> +	PINCTRL_PIN(51, "gpio38"),
> +	PINCTRL_PIN(52, "gpio39"),
> +	PINCTRL_PIN(53, "gpio40"),
> +	PINCTRL_PIN(54, "gpio41"),
> +	PINCTRL_PIN(55, "gpio42"),
> +	PINCTRL_PIN(56, "gpio43"),
> +	PINCTRL_PIN(57, "gpio44"),
> +	PINCTRL_PIN(58, "gpio45"),
> +	PINCTRL_PIN(59, "gpio46"),
> +	PINCTRL_PIN(60, "pcie_reset0"),
> +	PINCTRL_PIN(61, "pcie_reset1"),
> +	PINCTRL_PIN(62, "pcie_reset2"),
> +};
> +
> +static const int en7581_pon_pins[] = { 49, 50, 51, 52, 53, 54 };
> +static const int en7581_pon_tod_1pps_pins[] = { 46 };
> +static const int en7581_gsw_tod_1pps_pins[] = { 46 };
> +static const int en7581_sipo_pins[] = { 16, 17 };
> +static const int en7581_sipo_rclk_pins[] = { 16, 17, 43 };
> +static const int en7581_mdio_pins[] = { 14, 15 };
> +static const int en7581_uart2_pins[] = { 48, 55 };
> +static const int en7581_uart2_cts_rts_pins[] = { 46, 47 };
> +static const int en7581_hsuart_pins[] = { 28, 29 };
> +static const int en7581_hsuart_cts_rts_pins[] = { 26, 27 };
> +static const int en7581_uart4_pins[] = { 38, 39 };
> +static const int en7581_uart5_pins[] = { 18, 19 };
> +static const int en7581_i2c0_pins[] = { 2, 3 };
> +static const int en7581_i2c1_pins[] = { 14, 15 };
> +static const int en7581_jtag_udi_pins[] = { 16, 17, 18, 19, 20 };
> +static const int en7581_jtag_dfd_pins[] = { 16, 17, 18, 19, 20 };
> +static const int en7581_i2s_pins[] = { 26, 27, 28, 29 };
> +static const int en7581_pcm1_pins[] = { 22, 23, 24, 25 };
> +static const int en7581_pcm2_pins[] = { 18, 19, 20, 21 };
> +static const int en7581_spi_quad_pins[] = { 32, 33 };
> +static const int en7581_spi_pins[] = { 4, 5, 6, 7 };
> +static const int en7581_spi_cs1_pins[] = { 34 };
> +static const int en7581_pcm_spi_pins[] = { 18, 19, 20, 21, 22, 23, 24, 25 };
> +static const int en7581_pcm_spi_int_pins[] = { 14 };
> +static const int en7581_pcm_spi_rst_pins[] = { 15 };
> +static const int en7581_pcm_spi_cs1_pins[] = { 43 };
> +static const int en7581_pcm_spi_cs2_pins[] = { 40 };
> +static const int en7581_pcm_spi_cs2_p128_pins[] = { 40 };
> +static const int en7581_pcm_spi_cs2_p156_pins[] = { 40 };
> +static const int en7581_pcm_spi_cs3_pins[] = { 41 };
> +static const int en7581_pcm_spi_cs4_pins[] = { 42 };
> +static const int en7581_emmc_pins[] = {
> +	4, 5, 6, 30, 31, 32, 33, 34, 35, 36, 37
> +};
> +static const int en7581_pnand_pins[] = {
> +	4, 5, 6, 7, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42
> +};
> +static const int en7581_gpio0_pins[] = { 13 };
> +static const int en7581_gpio1_pins[] = { 14 };
> +static const int en7581_gpio2_pins[] = { 15 };
> +static const int en7581_gpio3_pins[] = { 16 };
> +static const int en7581_gpio4_pins[] = { 17 };
> +static const int en7581_gpio5_pins[] = { 18 };
> +static const int en7581_gpio6_pins[] = { 19 };
> +static const int en7581_gpio7_pins[] = { 20 };
> +static const int en7581_gpio8_pins[] = { 21 };
> +static const int en7581_gpio9_pins[] = { 22 };
> +static const int en7581_gpio10_pins[] = { 23 };
> +static const int en7581_gpio11_pins[] = { 24 };
> +static const int en7581_gpio12_pins[] = { 25 };
> +static const int en7581_gpio13_pins[] = { 26 };
> +static const int en7581_gpio14_pins[] = { 27 };
> +static const int en7581_gpio15_pins[] = { 28 };
> +static const int en7581_gpio16_pins[] = { 29 };
> +static const int en7581_gpio17_pins[] = { 30 };
> +static const int en7581_gpio18_pins[] = { 31 };
> +static const int en7581_gpio19_pins[] = { 32 };
> +static const int en7581_gpio20_pins[] = { 33 };
> +static const int en7581_gpio21_pins[] = { 34 };
> +static const int en7581_gpio22_pins[] = { 35 };
> +static const int en7581_gpio23_pins[] = { 36 };
> +static const int en7581_gpio24_pins[] = { 37 };
> +static const int en7581_gpio25_pins[] = { 38 };
> +static const int en7581_gpio26_pins[] = { 39 };
> +static const int en7581_gpio27_pins[] = { 40 };
> +static const int en7581_gpio28_pins[] = { 41 };
> +static const int en7581_gpio29_pins[] = { 42 };
> +static const int en7581_gpio30_pins[] = { 43 };
> +static const int en7581_gpio31_pins[] = { 44 };
> +static const int en7581_gpio32_pins[] = { 45 };
> +static const int en7581_gpio33_pins[] = { 46 };
> +static const int en7581_gpio34_pins[] = { 47 };
> +static const int en7581_gpio35_pins[] = { 48 };
> +static const int en7581_gpio36_pins[] = { 49 };
> +static const int en7581_gpio37_pins[] = { 50 };
> +static const int en7581_gpio38_pins[] = { 51 };
> +static const int en7581_gpio39_pins[] = { 52 };
> +static const int en7581_gpio40_pins[] = { 53 };
> +static const int en7581_gpio41_pins[] = { 54 };
> +static const int en7581_gpio42_pins[] = { 55 };
> +static const int en7581_gpio43_pins[] = { 56 };
> +static const int en7581_gpio44_pins[] = { 57 };
> +static const int en7581_gpio45_pins[] = { 58 };
> +static const int en7581_gpio46_pins[] = { 59 };
> +static const int en7581_gpio47_pins[] = { 60 };
> +static const int en7581_gpio48_pins[] = { 61 };
> +static const int en7581_gpio49_pins[] = { 62 };
> +static const int en7581_pcie_reset0_pins[] = { 60 };
> +static const int en7581_pcie_reset1_pins[] = { 61 };
> +static const int en7581_pcie_reset2_pins[] = { 62 };
> +
> +static const struct pingroup en7581_pinctrl_groups[] = {
> +	PINCTRL_PIN_GROUP("pon", en7581_pon),
> +	PINCTRL_PIN_GROUP("pon_tod_1pps", en7581_pon_tod_1pps),
> +	PINCTRL_PIN_GROUP("gsw_tod_1pps", en7581_gsw_tod_1pps),
> +	PINCTRL_PIN_GROUP("sipo", en7581_sipo),
> +	PINCTRL_PIN_GROUP("sipo_rclk", en7581_sipo_rclk),
> +	PINCTRL_PIN_GROUP("mdio", en7581_mdio),
> +	PINCTRL_PIN_GROUP("uart2", en7581_uart2),
> +	PINCTRL_PIN_GROUP("uart2_cts_rts", en7581_uart2_cts_rts),
> +	PINCTRL_PIN_GROUP("hsuart", en7581_hsuart),
> +	PINCTRL_PIN_GROUP("hsuart_cts_rts", en7581_hsuart_cts_rts),
> +	PINCTRL_PIN_GROUP("uart4", en7581_uart4),
> +	PINCTRL_PIN_GROUP("uart5", en7581_uart5),
> +	PINCTRL_PIN_GROUP("i2c0", en7581_i2c0),
> +	PINCTRL_PIN_GROUP("i2c1", en7581_i2c1),
> +	PINCTRL_PIN_GROUP("jtag_udi", en7581_jtag_udi),
> +	PINCTRL_PIN_GROUP("jtag_dfd", en7581_jtag_dfd),
> +	PINCTRL_PIN_GROUP("i2s", en7581_i2s),
> +	PINCTRL_PIN_GROUP("pcm1", en7581_pcm1),
> +	PINCTRL_PIN_GROUP("pcm2", en7581_pcm2),
> +	PINCTRL_PIN_GROUP("spi", en7581_spi),
> +	PINCTRL_PIN_GROUP("spi_quad", en7581_spi_quad),
> +	PINCTRL_PIN_GROUP("spi_cs1", en7581_spi_cs1),
> +	PINCTRL_PIN_GROUP("pcm_spi", en7581_pcm_spi),
> +	PINCTRL_PIN_GROUP("pcm_spi_int", en7581_pcm_spi_int),
> +	PINCTRL_PIN_GROUP("pcm_spi_rst", en7581_pcm_spi_rst),
> +	PINCTRL_PIN_GROUP("pcm_spi_cs1", en7581_pcm_spi_cs1),
> +	PINCTRL_PIN_GROUP("pcm_spi_cs2_p128", en7581_pcm_spi_cs2_p128),
> +	PINCTRL_PIN_GROUP("pcm_spi_cs2_p156", en7581_pcm_spi_cs2_p156),
> +	PINCTRL_PIN_GROUP("pcm_spi_cs2", en7581_pcm_spi_cs2),
> +	PINCTRL_PIN_GROUP("pcm_spi_cs3", en7581_pcm_spi_cs3),
> +	PINCTRL_PIN_GROUP("pcm_spi_cs4", en7581_pcm_spi_cs4),
> +	PINCTRL_PIN_GROUP("emmc", en7581_emmc),
> +	PINCTRL_PIN_GROUP("pnand", en7581_pnand),
> +	PINCTRL_PIN_GROUP("gpio0", en7581_gpio0),
> +	PINCTRL_PIN_GROUP("gpio1", en7581_gpio1),
> +	PINCTRL_PIN_GROUP("gpio2", en7581_gpio2),
> +	PINCTRL_PIN_GROUP("gpio3", en7581_gpio3),
> +	PINCTRL_PIN_GROUP("gpio4", en7581_gpio4),
> +	PINCTRL_PIN_GROUP("gpio5", en7581_gpio5),
> +	PINCTRL_PIN_GROUP("gpio6", en7581_gpio6),
> +	PINCTRL_PIN_GROUP("gpio7", en7581_gpio7),
> +	PINCTRL_PIN_GROUP("gpio8", en7581_gpio8),
> +	PINCTRL_PIN_GROUP("gpio9", en7581_gpio9),
> +	PINCTRL_PIN_GROUP("gpio10", en7581_gpio10),
> +	PINCTRL_PIN_GROUP("gpio11", en7581_gpio11),
> +	PINCTRL_PIN_GROUP("gpio12", en7581_gpio12),
> +	PINCTRL_PIN_GROUP("gpio13", en7581_gpio13),
> +	PINCTRL_PIN_GROUP("gpio14", en7581_gpio14),
> +	PINCTRL_PIN_GROUP("gpio15", en7581_gpio15),
> +	PINCTRL_PIN_GROUP("gpio16", en7581_gpio16),
> +	PINCTRL_PIN_GROUP("gpio17", en7581_gpio17),
> +	PINCTRL_PIN_GROUP("gpio18", en7581_gpio18),
> +	PINCTRL_PIN_GROUP("gpio19", en7581_gpio19),
> +	PINCTRL_PIN_GROUP("gpio20", en7581_gpio20),
> +	PINCTRL_PIN_GROUP("gpio21", en7581_gpio21),
> +	PINCTRL_PIN_GROUP("gpio22", en7581_gpio22),
> +	PINCTRL_PIN_GROUP("gpio23", en7581_gpio23),
> +	PINCTRL_PIN_GROUP("gpio24", en7581_gpio24),
> +	PINCTRL_PIN_GROUP("gpio25", en7581_gpio25),
> +	PINCTRL_PIN_GROUP("gpio26", en7581_gpio26),
> +	PINCTRL_PIN_GROUP("gpio27", en7581_gpio27),
> +	PINCTRL_PIN_GROUP("gpio28", en7581_gpio28),
> +	PINCTRL_PIN_GROUP("gpio29", en7581_gpio29),
> +	PINCTRL_PIN_GROUP("gpio30", en7581_gpio30),
> +	PINCTRL_PIN_GROUP("gpio31", en7581_gpio31),
> +	PINCTRL_PIN_GROUP("gpio32", en7581_gpio32),
> +	PINCTRL_PIN_GROUP("gpio33", en7581_gpio33),
> +	PINCTRL_PIN_GROUP("gpio34", en7581_gpio34),
> +	PINCTRL_PIN_GROUP("gpio35", en7581_gpio35),
> +	PINCTRL_PIN_GROUP("gpio36", en7581_gpio36),
> +	PINCTRL_PIN_GROUP("gpio37", en7581_gpio37),
> +	PINCTRL_PIN_GROUP("gpio38", en7581_gpio38),
> +	PINCTRL_PIN_GROUP("gpio39", en7581_gpio39),
> +	PINCTRL_PIN_GROUP("gpio40", en7581_gpio40),
> +	PINCTRL_PIN_GROUP("gpio41", en7581_gpio41),
> +	PINCTRL_PIN_GROUP("gpio42", en7581_gpio42),
> +	PINCTRL_PIN_GROUP("gpio43", en7581_gpio43),
> +	PINCTRL_PIN_GROUP("gpio44", en7581_gpio44),
> +	PINCTRL_PIN_GROUP("gpio45", en7581_gpio45),
> +	PINCTRL_PIN_GROUP("gpio46", en7581_gpio46),
> +	PINCTRL_PIN_GROUP("gpio47", en7581_gpio47),
> +	PINCTRL_PIN_GROUP("gpio48", en7581_gpio48),
> +	PINCTRL_PIN_GROUP("gpio49", en7581_gpio49),
> +	PINCTRL_PIN_GROUP("pcie_reset0", en7581_pcie_reset0),
> +	PINCTRL_PIN_GROUP("pcie_reset1", en7581_pcie_reset1),
> +	PINCTRL_PIN_GROUP("pcie_reset2", en7581_pcie_reset2),
> +};
> +
> +static const char *const pon_groups[] = { "pon" };
> +static const char *const tod_1pps_groups[] = {
> +	"pon_tod_1pps", "gsw_tod_1pps"
> +};
> +static const char *const sipo_groups[] = { "sipo", "sipo_rclk" };
> +static const char *const mdio_groups[] = { "mdio" };
> +static const char *const uart_groups[] = {
> +	"uart2", "uart2_cts_rts", "hsuart", "hsuart_cts_rts",
> +	"uart4", "uart5"
> +};
> +static const char *const i2c_groups[] = { "i2c1" };
> +static const char *const jtag_groups[] = { "jtag_udi", "jtag_dfd" };
> +static const char *const pcm_groups[] = { "pcm1", "pcm2" };
> +static const char *const spi_groups[] = { "spi_quad", "spi_cs1" };
> +static const char *const pcm_spi_groups[] = {
> +	"pcm_spi", "pcm_spi_int", "pcm_spi_rst", "pcm_spi_cs1",
> +	"pcm_spi_cs2_p156", "pcm_spi_cs2_p128", "pcm_spi_cs3",
> +	"pcm_spi_cs4"
> +};
> +static const char *const i2s_groups[] = { "i2s" };
> +static const char *const emmc_groups[] = { "emmc" };
> +static const char *const pnand_groups[] = { "pnand" };
> +static const char *const gpio_groups[] = { "gpio47", "gpio48", "gpio49" };
> +static const char *const pcie_reset_groups[] = {
> +	"pcie_reset0", "pcie_reset1", "pcie_reset2"
> +};
> +static const char *const pwm_groups[] = {
> +	"gpio0",  "gpio1",  "gpio2",  "gpio3",  "gpio4",  "gpio5",
> +	"gpio6",  "gpio7",  "gpio8",  "gpio9",  "gpio10", "gpio11",
> +	"gpio12", "gpio13", "gpio14", "gpio15", "gpio16", "gpio17",
> +	"gpio18", "gpio19", "gpio20", "gpio21", "gpio22", "gpio23",
> +	"gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29",
> +	"gpio30", "gpio31", "gpio36", "gpio37", "gpio38", "gpio39",
> +	"gpio40", "gpio41", "gpio42", "gpio43", "gpio44", "gpio45",
> +	"gpio46", "gpio47", "gpio48", "gpio49"
> +};
> +static const char *const phy1_led0_groups[] = {
> +	"gpio33", "gpio34", "gpio35", "gpio42"
> +};
> +static const char *const phy2_led0_groups[] = {
> +	"gpio33", "gpio34", "gpio35", "gpio42"
> +};
> +static const char *const phy3_led0_groups[] = {
> +	"gpio33", "gpio34", "gpio35", "gpio42"
> +};
> +static const char *const phy4_led0_groups[] = {
> +	"gpio33", "gpio34", "gpio35", "gpio42"
> +};
> +static const char *const phy1_led1_groups[] = {
> +	"gpio43", "gpio44", "gpio45", "gpio46"
> +};
> +static const char *const phy2_led1_groups[] = {
> +	"gpio43", "gpio44", "gpio45", "gpio46"
> +};
> +static const char *const phy3_led1_groups[] = {
> +	"gpio43", "gpio44", "gpio45", "gpio46"
> +};
> +static const char *const phy4_led1_groups[] = {
> +	"gpio43", "gpio44", "gpio45", "gpio46"
> +};
> +
> +static const struct airoha_pinctrl_func_group pon_func_group[] = {
> +	{
> +		.name = "pon",
> +		.regmap[0] = {
> +			AIROHA_FUNC_MUX,
> +			REG_GPIO_PON_MODE,
> +			GPIO_PON_MODE_MASK,
> +			GPIO_PON_MODE_MASK
> +		},
> +		.regmap_size = 1,
> +	},
> +};
> +
> +static const struct airoha_pinctrl_func_group tod_1pps_func_group[] = {
> +	{
> +		.name = "pon_tod_1pps",
> +		.regmap[0] = {
> +			AIROHA_FUNC_MUX,
> +			REG_GPIO_2ND_I2C_MODE,
> +			PON_TOD_1PPS_MODE_MASK,
> +			PON_TOD_1PPS_MODE_MASK
> +		},
> +		.regmap_size = 1,
> +	}, {
> +		.name = "gsw_tod_1pps",
> +		.regmap[0] = {
> +			AIROHA_FUNC_MUX,
> +			REG_GPIO_2ND_I2C_MODE,
> +			GSW_TOD_1PPS_MODE_MASK,
> +			GSW_TOD_1PPS_MODE_MASK
> +		},
> +		.regmap_size = 1,
> +	},
> +};
> +
> +static const struct airoha_pinctrl_func_group sipo_func_group[] = {
> +	{
> +		.name = "sipo",
> +		.regmap[0] = {
> +			AIROHA_FUNC_MUX,
> +			REG_GPIO_PON_MODE,
> +			GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK,
> +			GPIO_SIPO_MODE_MASK
> +		},
> +		.regmap_size = 1,
> +	}, {
> +		.name = "sipo_rclk",
> +		.regmap[0] = {
> +			AIROHA_FUNC_MUX,
> +			REG_GPIO_PON_MODE,
> +			GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK,
> +			GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK
> +		},
> +		.regmap_size = 1,
> +	},
> +};
> +
> +static const struct airoha_pinctrl_func_group mdio_func_group[] = {
> +	{
> +		.name = "mdio",
> +		.regmap[0] = {
> +			AIROHA_FUNC_MUX,
> +			REG_GPIO_2ND_I2C_MODE,
> +			GPIO_MDC_IO_MASTER_MODE_MASK,
> +			GPIO_MDC_IO_MASTER_MODE_MASK
> +		},
> +		.regmap[1] = {
> +			AIROHA_FUNC_MUX,
> +			REG_FORCE_GPIO_EN,
> +			FORCE_GPIO_EN(1) | FORCE_GPIO_EN(2),
> +			FORCE_GPIO_EN(1) | FORCE_GPIO_EN(2)
> +		},
> +		.regmap_size = 2,
> +	},
> +};
> +
> +static const struct airoha_pinctrl_func_group uart_func_group[] = {
> +	{
> +		.name = "uart2",
> +		.regmap[0] = {
> +			AIROHA_FUNC_MUX,
> +			REG_GPIO_PON_MODE,
> +			GPIO_UART2_MODE_MASK,
> +			GPIO_UART2_MODE_MASK
> +		},
> +		.regmap_size = 1,
> +	}, {
> +		.name = "uart2_cts_rts",
> +		.regmap[0] = {
> +			AIROHA_FUNC_MUX,
> +			REG_GPIO_PON_MODE,
> +			GPIO_UART2_MODE_MASK | GPIO_UART2_CTS_RTS_MODE_MASK,
> +			GPIO_UART2_MODE_MASK | GPIO_UART2_CTS_RTS_MODE_MASK
> +		},
> +		.regmap_size = 1,
> +	}, {
> +		.name = "hsuart",
> +		.regmap[0] = {
> +			AIROHA_FUNC_MUX,
> +			REG_GPIO_PON_MODE,
> +			GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK,
> +			GPIO_HSUART_MODE_MASK
> +		},
> +		.regmap_size = 1,
> +	},
> +	{
> +		.name = "hsuart_cts_rts",
> +		.regmap[0] = {
> +			AIROHA_FUNC_MUX,
> +			REG_GPIO_PON_MODE,
> +			GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK,
> +			GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK
> +		},
> +		.regmap_size = 1,
> +	}, {
> +		.name = "uart4",
> +		.regmap[0] = {
> +			AIROHA_FUNC_MUX,
> +			REG_GPIO_PON_MODE,
> +			GPIO_UART4_MODE_MASK,
> +			GPIO_UART4_MODE_MASK
> +		},
> +		.regmap_size = 1,
> +	}, {
> +		.name = "uart5",
> +		.regmap[0] = {
> +			AIROHA_FUNC_MUX,
> +			REG_GPIO_PON_MODE,
> +			GPIO_UART5_MODE_MASK,
> +			GPIO_UART5_MODE_MASK
> +		},
> +		.regmap_size = 1,
> +	},
> +};
> +
> +static const struct airoha_pinctrl_func_group i2c_func_group[] = {
> +	{
> +		.name = "i2c1",
> +		.regmap[0] = {
> +			AIROHA_FUNC_MUX,
> +			REG_GPIO_2ND_I2C_MODE,
> +			GPIO_2ND_I2C_MODE_MASK,
> +			GPIO_2ND_I2C_MODE_MASK
> +		},
> +		.regmap_size = 1,
> +	},
> +};
> +
> +static const struct airoha_pinctrl_func_group jtag_func_group[] = {
> +	{
> +		.name = "jtag_udi",
> +		.regmap[0] = {
> +			AIROHA_FUNC_MUX,
> +			REG_NPU_UART_EN,
> +			JTAG_UDI_EN_MASK,
> +			JTAG_UDI_EN_MASK
> +		},
> +		.regmap_size = 1,
> +	}, {
> +		.name = "jtag_dfd",
> +		.regmap[0] = {
> +			AIROHA_FUNC_MUX,
> +			REG_NPU_UART_EN,
> +			JTAG_DFD_EN_MASK,
> +			JTAG_DFD_EN_MASK
> +		},
> +		.regmap_size = 1,
> +	},
> +};
> +
> +static const struct airoha_pinctrl_func_group pcm_func_group[] = {
> +	{
> +		.name = "pcm1",
> +		.regmap[0] = {
> +			AIROHA_FUNC_MUX,
> +			REG_GPIO_SPI_CS1_MODE,
> +			GPIO_PCM1_MODE_MASK,
> +			GPIO_PCM1_MODE_MASK
> +		},
> +		.regmap_size = 1,
> +	}, {
> +		.name = "pcm2",
> +		.regmap[0] = {
> +			AIROHA_FUNC_MUX,
> +			REG_GPIO_SPI_CS1_MODE,
> +			GPIO_PCM2_MODE_MASK,
> +			GPIO_PCM2_MODE_MASK
> +		},
> +		.regmap_size = 1,
> +	},
> +};
> +
> +static const struct airoha_pinctrl_func_group spi_func_group[] = {
> +	{
> +		.name = "spi_quad",
> +		.regmap[0] = {
> +			AIROHA_FUNC_MUX,
> +			REG_GPIO_SPI_CS1_MODE,
> +			GPIO_SPI_QUAD_MODE_MASK,
> +			GPIO_SPI_QUAD_MODE_MASK
> +		},
> +		.regmap_size = 1,
> +	}, {
> +		.name = "spi_cs1",
> +		.regmap[0] = {
> +			AIROHA_FUNC_MUX,
> +			REG_GPIO_SPI_CS1_MODE,
> +			GPIO_SPI_CS1_MODE_MASK,
> +			GPIO_SPI_CS1_MODE_MASK
> +		},
> +		.regmap_size = 1,
> +	}, {
> +		.name = "spi_cs2",
> +		.regmap[0] = {
> +			AIROHA_FUNC_MUX,
> +			REG_GPIO_SPI_CS1_MODE,
> +			GPIO_SPI_CS2_MODE_MASK,
> +			GPIO_SPI_CS2_MODE_MASK
> +		},
> +		.regmap_size = 1,
> +	}, {
> +		.name = "spi_cs3",
> +		.regmap[0] = {
> +			AIROHA_FUNC_MUX,
> +			REG_GPIO_SPI_CS1_MODE,
> +			GPIO_SPI_CS3_MODE_MASK,
> +			GPIO_SPI_CS3_MODE_MASK
> +		},
> +		.regmap_size = 1,
> +	}, {
> +		.name = "spi_cs4",
> +		.regmap[0] = {
> +			AIROHA_FUNC_MUX,
> +			REG_GPIO_SPI_CS1_MODE,
> +			GPIO_SPI_CS4_MODE_MASK,
> +			GPIO_SPI_CS4_MODE_MASK
> +		},
> +		.regmap_size = 1,
> +	},
> +};
> +
> +static const struct airoha_pinctrl_func_group pcm_spi_func_group[] = {
> +	{
> +		.name = "pcm_spi",
> +		.regmap[0] = {
> +			AIROHA_FUNC_MUX,
> +			REG_GPIO_SPI_CS1_MODE,
> +			GPIO_PCM_SPI_MODE_MASK,
> +			GPIO_PCM_SPI_MODE_MASK
> +		},
> +		.regmap_size = 1,
> +	}, {
> +		.name = "pcm_spi_int",
> +		.regmap[0] = {
> +			AIROHA_FUNC_MUX,
> +			REG_GPIO_SPI_CS1_MODE,
> +			GPIO_PCM_INT_MODE_MASK,
> +			GPIO_PCM_INT_MODE_MASK
> +		},
> +		.regmap_size = 1,
> +	}, {
> +		.name = "pcm_spi_rst",
> +		.regmap[0] = {
> +			AIROHA_FUNC_MUX,
> +			REG_GPIO_SPI_CS1_MODE,
> +			GPIO_PCM_RESET_MODE_MASK,
> +			GPIO_PCM_RESET_MODE_MASK
> +		},
> +		.regmap_size = 1,
> +	}, {
> +		.name = "pcm_spi_cs1",
> +		.regmap[0] = {
> +			AIROHA_FUNC_MUX,
> +			REG_GPIO_SPI_CS1_MODE,
> +			GPIO_PCM_SPI_CS1_MODE_MASK,
> +			GPIO_PCM_SPI_CS1_MODE_MASK
> +		},
> +		.regmap_size = 1,
> +	}, {
> +		.name = "pcm_spi_cs2_p128",
> +		.regmap[0] = {
> +			AIROHA_FUNC_MUX,
> +			REG_GPIO_SPI_CS1_MODE,
> +			GPIO_PCM_SPI_CS2_MODE_P128_MASK,
> +			GPIO_PCM_SPI_CS2_MODE_P128_MASK
> +		},
> +		.regmap_size = 1,
> +	}, {
> +		.name = "pcm_spi_cs2_p156",
> +		.regmap[0] = {
> +			AIROHA_FUNC_MUX,
> +			REG_GPIO_SPI_CS1_MODE,
> +			GPIO_PCM_SPI_CS2_MODE_P156_MASK,
> +			GPIO_PCM_SPI_CS2_MODE_P156_MASK
> +		},
> +		.regmap_size = 1,
> +	}, {
> +		.name = "pcm_spi_cs3",
> +		.regmap[0] = {
> +			AIROHA_FUNC_MUX,
> +			REG_GPIO_SPI_CS1_MODE,
> +			GPIO_PCM_SPI_CS3_MODE_MASK,
> +			GPIO_PCM_SPI_CS3_MODE_MASK
> +		},
> +		.regmap_size = 1,
> +	}, {
> +		.name = "pcm_spi_cs4",
> +		.regmap[0] = {
> +			AIROHA_FUNC_MUX,
> +			REG_GPIO_SPI_CS1_MODE,
> +			GPIO_PCM_SPI_CS4_MODE_MASK,
> +			GPIO_PCM_SPI_CS4_MODE_MASK
> +		},
> +		.regmap_size = 1,
> +	},
> +};
> +
> +static const struct airoha_pinctrl_func_group i2s_func_group[] = {
> +	{
> +		.name = "i2s",
> +		.regmap[0] = {
> +			AIROHA_FUNC_MUX,
> +			REG_GPIO_2ND_I2C_MODE,
> +			GPIO_I2S_MODE_MASK,
> +			GPIO_I2S_MODE_MASK
> +		},
> +		.regmap_size = 1,
> +	},
> +};
> +
> +static const struct airoha_pinctrl_func_group emmc_func_group[] = {
> +	{
> +		.name = "emmc",
> +		.regmap[0] = {
> +			AIROHA_FUNC_MUX,
> +			REG_GPIO_PON_MODE,
> +			GPIO_EMMC_MODE_MASK,
> +			GPIO_EMMC_MODE_MASK
> +		},
> +		.regmap_size = 1,
> +	},
> +};
> +
> +static const struct airoha_pinctrl_func_group pnand_func_group[] = {
> +	{
> +		.name = "pnand",
> +		.regmap[0] = {
> +			AIROHA_FUNC_MUX,
> +			REG_GPIO_PON_MODE,
> +			GPIO_PARALLEL_NAND_MODE_MASK,
> +			GPIO_PARALLEL_NAND_MODE_MASK
> +		},
> +		.regmap_size = 1,
> +	},
> +};
> +
> +static const struct airoha_pinctrl_func_group gpio_func_group[] = {
> +	AIROHA_PINCTRL_GPIO_EXT("gpio47", GPIO47_FLASH_MODE_CFG,
> +				GPIO_PCIE_RESET0_MASK),
> +	AIROHA_PINCTRL_GPIO_EXT("gpio48", GPIO48_FLASH_MODE_CFG,
> +				GPIO_PCIE_RESET1_MASK),
> +	AIROHA_PINCTRL_GPIO_EXT("gpio49", GPIO49_FLASH_MODE_CFG,
> +				GPIO_PCIE_RESET2_MASK),
> +};
> +
> +static const struct airoha_pinctrl_func_group pcie_reset_func_group[] = {
> +	{
> +		.name = "pcie_reset0",
> +		.regmap[0] = {
> +			AIROHA_FUNC_MUX,
> +			REG_GPIO_PON_MODE,
> +			GPIO_PCIE_RESET0_MASK,
> +			0
> +		},
> +		.regmap_size = 1,
> +	}, {
> +		.name = "pcie_reset1",
> +		.regmap[0] = {
> +			AIROHA_FUNC_MUX,
> +			REG_GPIO_PON_MODE,
> +			GPIO_PCIE_RESET1_MASK,
> +			0
> +		},
> +		.regmap_size = 1,
> +	}, {
> +		.name = "pcie_reset2",
> +		.regmap[0] = {
> +			AIROHA_FUNC_MUX,
> +			REG_GPIO_PON_MODE,
> +			GPIO_PCIE_RESET2_MASK,
> +			0
> +		},
> +		.regmap_size = 1,
> +	},
> +};
> +
> +static const struct airoha_pinctrl_func_group pwm_func_group[] = {
> +	AIROHA_PINCTRL_PWM("gpio0", GPIO0_FLASH_MODE_CFG),
> +	AIROHA_PINCTRL_PWM("gpio1", GPIO1_FLASH_MODE_CFG),
> +	AIROHA_PINCTRL_PWM("gpio2", GPIO2_FLASH_MODE_CFG),
> +	AIROHA_PINCTRL_PWM("gpio3", GPIO3_FLASH_MODE_CFG),
> +	AIROHA_PINCTRL_PWM("gpio4", GPIO4_FLASH_MODE_CFG),
> +	AIROHA_PINCTRL_PWM("gpio5", GPIO5_FLASH_MODE_CFG),
> +	AIROHA_PINCTRL_PWM("gpio6", GPIO6_FLASH_MODE_CFG),
> +	AIROHA_PINCTRL_PWM("gpio7", GPIO7_FLASH_MODE_CFG),
> +	AIROHA_PINCTRL_PWM("gpio8", GPIO8_FLASH_MODE_CFG),
> +	AIROHA_PINCTRL_PWM("gpio9", GPIO9_FLASH_MODE_CFG),
> +	AIROHA_PINCTRL_PWM("gpio10", GPIO10_FLASH_MODE_CFG),
> +	AIROHA_PINCTRL_PWM("gpio11", GPIO11_FLASH_MODE_CFG),
> +	AIROHA_PINCTRL_PWM("gpio12", GPIO12_FLASH_MODE_CFG),
> +	AIROHA_PINCTRL_PWM("gpio13", GPIO13_FLASH_MODE_CFG),
> +	AIROHA_PINCTRL_PWM("gpio14", GPIO14_FLASH_MODE_CFG),
> +	AIROHA_PINCTRL_PWM("gpio15", GPIO15_FLASH_MODE_CFG),
> +	AIROHA_PINCTRL_PWM_EXT("gpio16", GPIO16_FLASH_MODE_CFG),
> +	AIROHA_PINCTRL_PWM_EXT("gpio17", GPIO17_FLASH_MODE_CFG),
> +	AIROHA_PINCTRL_PWM_EXT("gpio18", GPIO18_FLASH_MODE_CFG),
> +	AIROHA_PINCTRL_PWM_EXT("gpio19", GPIO19_FLASH_MODE_CFG),
> +	AIROHA_PINCTRL_PWM_EXT("gpio20", GPIO20_FLASH_MODE_CFG),
> +	AIROHA_PINCTRL_PWM_EXT("gpio21", GPIO21_FLASH_MODE_CFG),
> +	AIROHA_PINCTRL_PWM_EXT("gpio22", GPIO22_FLASH_MODE_CFG),
> +	AIROHA_PINCTRL_PWM_EXT("gpio23", GPIO23_FLASH_MODE_CFG),
> +	AIROHA_PINCTRL_PWM_EXT("gpio24", GPIO24_FLASH_MODE_CFG),
> +	AIROHA_PINCTRL_PWM_EXT("gpio25", GPIO25_FLASH_MODE_CFG),
> +	AIROHA_PINCTRL_PWM_EXT("gpio26", GPIO26_FLASH_MODE_CFG),
> +	AIROHA_PINCTRL_PWM_EXT("gpio27", GPIO27_FLASH_MODE_CFG),
> +	AIROHA_PINCTRL_PWM_EXT("gpio28", GPIO28_FLASH_MODE_CFG),
> +	AIROHA_PINCTRL_PWM_EXT("gpio29", GPIO29_FLASH_MODE_CFG),
> +	AIROHA_PINCTRL_PWM_EXT("gpio30", GPIO30_FLASH_MODE_CFG),
> +	AIROHA_PINCTRL_PWM_EXT("gpio31", GPIO31_FLASH_MODE_CFG),
> +	AIROHA_PINCTRL_PWM_EXT("gpio36", GPIO36_FLASH_MODE_CFG),
> +	AIROHA_PINCTRL_PWM_EXT("gpio37", GPIO37_FLASH_MODE_CFG),
> +	AIROHA_PINCTRL_PWM_EXT("gpio38", GPIO38_FLASH_MODE_CFG),
> +	AIROHA_PINCTRL_PWM_EXT("gpio39", GPIO39_FLASH_MODE_CFG),
> +	AIROHA_PINCTRL_PWM_EXT("gpio40", GPIO40_FLASH_MODE_CFG),
> +	AIROHA_PINCTRL_PWM_EXT("gpio41", GPIO41_FLASH_MODE_CFG),
> +	AIROHA_PINCTRL_PWM_EXT("gpio42", GPIO42_FLASH_MODE_CFG),
> +	AIROHA_PINCTRL_PWM_EXT("gpio43", GPIO43_FLASH_MODE_CFG),
> +	AIROHA_PINCTRL_PWM_EXT("gpio44", GPIO44_FLASH_MODE_CFG),
> +	AIROHA_PINCTRL_PWM_EXT("gpio45", GPIO45_FLASH_MODE_CFG),
> +	AIROHA_PINCTRL_PWM_EXT("gpio46", GPIO46_FLASH_MODE_CFG),
> +	AIROHA_PINCTRL_PWM_EXT_SEC("gpio47", GPIO47_FLASH_MODE_CFG,
> +				   GPIO_PCIE_RESET0_MASK),
> +	AIROHA_PINCTRL_PWM_EXT_SEC("gpio48", GPIO48_FLASH_MODE_CFG,
> +				   GPIO_PCIE_RESET1_MASK),
> +	AIROHA_PINCTRL_PWM_EXT_SEC("gpio49", GPIO49_FLASH_MODE_CFG,
> +				   GPIO_PCIE_RESET2_MASK),
> +};
> +
> +static const struct airoha_pinctrl_func_group phy1_led0_func_group[] = {
> +	AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK,
> +				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),
> +	AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK,
> +				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)),
> +	AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK,
> +				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)),
> +	AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK,
> +				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),
> +};
> +
> +static const struct airoha_pinctrl_func_group phy2_led0_func_group[] = {
> +	AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK,
> +				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),
> +	AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK,
> +				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)),
> +	AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK,
> +				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)),
> +	AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK,
> +				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),
> +};
> +
> +static const struct airoha_pinctrl_func_group phy3_led0_func_group[] = {
> +	AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK,
> +				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
> +	AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK,
> +				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),
> +	AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK,
> +				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),
> +	AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK,
> +				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
> +};
> +
> +static const struct airoha_pinctrl_func_group phy4_led0_func_group[] = {
> +	AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK,
> +				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)),
> +	AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK,
> +				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)),
> +	AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK,
> +				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)),
> +	AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK,
> +				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)),
> +};
> +
> +static const struct airoha_pinctrl_func_group phy1_led1_func_group[] = {
> +	AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK,
> +				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),
> +	AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK,
> +				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)),
> +	AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK,
> +				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)),
> +	AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK,
> +				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),
> +};
> +
> +static const struct airoha_pinctrl_func_group phy2_led1_func_group[] = {
> +	AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK,
> +				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),
> +	AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK,
> +				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)),
> +	AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK,
> +				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)),
> +	AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK,
> +				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),
> +};
> +
> +static const struct airoha_pinctrl_func_group phy3_led1_func_group[] = {
> +	AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK,
> +				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
> +	AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK,
> +				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),
> +	AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK,
> +				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),
> +	AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK,
> +				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
> +};
> +
> +static const struct airoha_pinctrl_func_group phy4_led1_func_group[] = {
> +	AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK,
> +				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)),
> +	AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK,
> +				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)),
> +	AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK,
> +				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)),
> +	AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK,
> +				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)),
> +};
> +
> +static const struct airoha_pinctrl_func en7581_pinctrl_funcs[] = {
> +	PINCTRL_FUNC_DESC("pon", pon),
> +	PINCTRL_FUNC_DESC("tod_1pps", tod_1pps),
> +	PINCTRL_FUNC_DESC("sipo", sipo),
> +	PINCTRL_FUNC_DESC("mdio", mdio),
> +	PINCTRL_FUNC_DESC("uart", uart),
> +	PINCTRL_FUNC_DESC("i2c", i2c),
> +	PINCTRL_FUNC_DESC("jtag", jtag),
> +	PINCTRL_FUNC_DESC("pcm", pcm),
> +	PINCTRL_FUNC_DESC("spi", spi),
> +	PINCTRL_FUNC_DESC("pcm_spi", pcm_spi),
> +	PINCTRL_FUNC_DESC("i2s", i2s),
> +	PINCTRL_FUNC_DESC("emmc", emmc),
> +	PINCTRL_FUNC_DESC("pnand", pnand),
> +	PINCTRL_FUNC_DESC("gpio", gpio),
> +	PINCTRL_FUNC_DESC("pcie_reset", pcie_reset),
> +	PINCTRL_FUNC_DESC("pwm", pwm),
> +	PINCTRL_FUNC_DESC("phy1_led0", phy1_led0),
> +	PINCTRL_FUNC_DESC("phy2_led0", phy2_led0),
> +	PINCTRL_FUNC_DESC("phy3_led0", phy3_led0),
> +	PINCTRL_FUNC_DESC("phy4_led0", phy4_led0),
> +	PINCTRL_FUNC_DESC("phy1_led1", phy1_led1),
> +	PINCTRL_FUNC_DESC("phy2_led1", phy2_led1),
> +	PINCTRL_FUNC_DESC("phy3_led1", phy3_led1),
> +	PINCTRL_FUNC_DESC("phy4_led1", phy4_led1),
> +};
> +
> +static const struct airoha_pinctrl_conf en7581_pinctrl_pullup_conf[] = {
> +	PINCTRL_CONF_DESC(0, REG_I2C_SDA_PU, UART1_TXD_PU_MASK),
> +	PINCTRL_CONF_DESC(1, REG_I2C_SDA_PU, UART1_RXD_PU_MASK),
> +	PINCTRL_CONF_DESC(2, REG_I2C_SDA_PU, I2C_SDA_PU_MASK),
> +	PINCTRL_CONF_DESC(3, REG_I2C_SDA_PU, I2C_SCL_PU_MASK),
> +	PINCTRL_CONF_DESC(4, REG_I2C_SDA_PU, SPI_CS0_PU_MASK),
> +	PINCTRL_CONF_DESC(5, REG_I2C_SDA_PU, SPI_CLK_PU_MASK),
> +	PINCTRL_CONF_DESC(6, REG_I2C_SDA_PU, SPI_MOSI_PU_MASK),
> +	PINCTRL_CONF_DESC(7, REG_I2C_SDA_PU, SPI_MISO_PU_MASK),
> +	PINCTRL_CONF_DESC(13, REG_GPIO_L_PU, BIT(0)),
> +	PINCTRL_CONF_DESC(14, REG_GPIO_L_PU, BIT(1)),
> +	PINCTRL_CONF_DESC(15, REG_GPIO_L_PU, BIT(2)),
> +	PINCTRL_CONF_DESC(16, REG_GPIO_L_PU, BIT(3)),
> +	PINCTRL_CONF_DESC(17, REG_GPIO_L_PU, BIT(4)),
> +	PINCTRL_CONF_DESC(18, REG_GPIO_L_PU, BIT(5)),
> +	PINCTRL_CONF_DESC(19, REG_GPIO_L_PU, BIT(6)),
> +	PINCTRL_CONF_DESC(20, REG_GPIO_L_PU, BIT(7)),
> +	PINCTRL_CONF_DESC(21, REG_GPIO_L_PU, BIT(8)),
> +	PINCTRL_CONF_DESC(22, REG_GPIO_L_PU, BIT(9)),
> +	PINCTRL_CONF_DESC(23, REG_GPIO_L_PU, BIT(10)),
> +	PINCTRL_CONF_DESC(24, REG_GPIO_L_PU, BIT(11)),
> +	PINCTRL_CONF_DESC(25, REG_GPIO_L_PU, BIT(12)),
> +	PINCTRL_CONF_DESC(26, REG_GPIO_L_PU, BIT(13)),
> +	PINCTRL_CONF_DESC(27, REG_GPIO_L_PU, BIT(14)),
> +	PINCTRL_CONF_DESC(28, REG_GPIO_L_PU, BIT(15)),
> +	PINCTRL_CONF_DESC(29, REG_GPIO_L_PU, BIT(16)),
> +	PINCTRL_CONF_DESC(30, REG_GPIO_L_PU, BIT(17)),
> +	PINCTRL_CONF_DESC(31, REG_GPIO_L_PU, BIT(18)),
> +	PINCTRL_CONF_DESC(32, REG_GPIO_L_PU, BIT(19)),
> +	PINCTRL_CONF_DESC(33, REG_GPIO_L_PU, BIT(20)),
> +	PINCTRL_CONF_DESC(34, REG_GPIO_L_PU, BIT(21)),
> +	PINCTRL_CONF_DESC(35, REG_GPIO_L_PU, BIT(22)),
> +	PINCTRL_CONF_DESC(36, REG_GPIO_L_PU, BIT(23)),
> +	PINCTRL_CONF_DESC(37, REG_GPIO_L_PU, BIT(24)),
> +	PINCTRL_CONF_DESC(38, REG_GPIO_L_PU, BIT(25)),
> +	PINCTRL_CONF_DESC(39, REG_GPIO_L_PU, BIT(26)),
> +	PINCTRL_CONF_DESC(40, REG_GPIO_L_PU, BIT(27)),
> +	PINCTRL_CONF_DESC(41, REG_GPIO_L_PU, BIT(28)),
> +	PINCTRL_CONF_DESC(42, REG_GPIO_L_PU, BIT(29)),
> +	PINCTRL_CONF_DESC(43, REG_GPIO_L_PU, BIT(30)),
> +	PINCTRL_CONF_DESC(44, REG_GPIO_L_PU, BIT(31)),
> +	PINCTRL_CONF_DESC(45, REG_GPIO_H_PU, BIT(0)),
> +	PINCTRL_CONF_DESC(46, REG_GPIO_H_PU, BIT(1)),
> +	PINCTRL_CONF_DESC(47, REG_GPIO_H_PU, BIT(2)),
> +	PINCTRL_CONF_DESC(48, REG_GPIO_H_PU, BIT(3)),
> +	PINCTRL_CONF_DESC(49, REG_GPIO_H_PU, BIT(4)),
> +	PINCTRL_CONF_DESC(50, REG_GPIO_H_PU, BIT(5)),
> +	PINCTRL_CONF_DESC(51, REG_GPIO_H_PU, BIT(6)),
> +	PINCTRL_CONF_DESC(52, REG_GPIO_H_PU, BIT(7)),
> +	PINCTRL_CONF_DESC(53, REG_GPIO_H_PU, BIT(8)),
> +	PINCTRL_CONF_DESC(54, REG_GPIO_H_PU, BIT(9)),
> +	PINCTRL_CONF_DESC(55, REG_GPIO_H_PU, BIT(10)),
> +	PINCTRL_CONF_DESC(56, REG_GPIO_H_PU, BIT(11)),
> +	PINCTRL_CONF_DESC(57, REG_GPIO_H_PU, BIT(12)),
> +	PINCTRL_CONF_DESC(58, REG_GPIO_H_PU, BIT(13)),
> +	PINCTRL_CONF_DESC(59, REG_GPIO_H_PU, BIT(14)),
> +	PINCTRL_CONF_DESC(60, REG_I2C_SDA_PU, PCIE0_RESET_PU_MASK),
> +	PINCTRL_CONF_DESC(61, REG_I2C_SDA_PU, PCIE1_RESET_PU_MASK),
> +	PINCTRL_CONF_DESC(62, REG_I2C_SDA_PU, PCIE2_RESET_PU_MASK),
> +};
> +
> +static const struct airoha_pinctrl_conf en7581_pinctrl_pulldown_conf[] = {
> +	PINCTRL_CONF_DESC(0, REG_I2C_SDA_PD, UART1_TXD_PD_MASK),
> +	PINCTRL_CONF_DESC(1, REG_I2C_SDA_PD, UART1_RXD_PD_MASK),
> +	PINCTRL_CONF_DESC(2, REG_I2C_SDA_PD, I2C_SDA_PD_MASK),
> +	PINCTRL_CONF_DESC(3, REG_I2C_SDA_PD, I2C_SCL_PD_MASK),
> +	PINCTRL_CONF_DESC(4, REG_I2C_SDA_PD, SPI_CS0_PD_MASK),
> +	PINCTRL_CONF_DESC(5, REG_I2C_SDA_PD, SPI_CLK_PD_MASK),
> +	PINCTRL_CONF_DESC(6, REG_I2C_SDA_PD, SPI_MOSI_PD_MASK),
> +	PINCTRL_CONF_DESC(7, REG_I2C_SDA_PD, SPI_MISO_PD_MASK),
> +	PINCTRL_CONF_DESC(13, REG_GPIO_L_PD, BIT(0)),
> +	PINCTRL_CONF_DESC(14, REG_GPIO_L_PD, BIT(1)),
> +	PINCTRL_CONF_DESC(15, REG_GPIO_L_PD, BIT(2)),
> +	PINCTRL_CONF_DESC(16, REG_GPIO_L_PD, BIT(3)),
> +	PINCTRL_CONF_DESC(17, REG_GPIO_L_PD, BIT(4)),
> +	PINCTRL_CONF_DESC(18, REG_GPIO_L_PD, BIT(5)),
> +	PINCTRL_CONF_DESC(19, REG_GPIO_L_PD, BIT(6)),
> +	PINCTRL_CONF_DESC(20, REG_GPIO_L_PD, BIT(7)),
> +	PINCTRL_CONF_DESC(21, REG_GPIO_L_PD, BIT(8)),
> +	PINCTRL_CONF_DESC(22, REG_GPIO_L_PD, BIT(9)),
> +	PINCTRL_CONF_DESC(23, REG_GPIO_L_PD, BIT(10)),
> +	PINCTRL_CONF_DESC(24, REG_GPIO_L_PD, BIT(11)),
> +	PINCTRL_CONF_DESC(25, REG_GPIO_L_PD, BIT(12)),
> +	PINCTRL_CONF_DESC(26, REG_GPIO_L_PD, BIT(13)),
> +	PINCTRL_CONF_DESC(27, REG_GPIO_L_PD, BIT(14)),
> +	PINCTRL_CONF_DESC(28, REG_GPIO_L_PD, BIT(15)),
> +	PINCTRL_CONF_DESC(29, REG_GPIO_L_PD, BIT(16)),
> +	PINCTRL_CONF_DESC(30, REG_GPIO_L_PD, BIT(17)),
> +	PINCTRL_CONF_DESC(31, REG_GPIO_L_PD, BIT(18)),
> +	PINCTRL_CONF_DESC(32, REG_GPIO_L_PD, BIT(19)),
> +	PINCTRL_CONF_DESC(33, REG_GPIO_L_PD, BIT(20)),
> +	PINCTRL_CONF_DESC(34, REG_GPIO_L_PD, BIT(21)),
> +	PINCTRL_CONF_DESC(35, REG_GPIO_L_PD, BIT(22)),
> +	PINCTRL_CONF_DESC(36, REG_GPIO_L_PD, BIT(23)),
> +	PINCTRL_CONF_DESC(37, REG_GPIO_L_PD, BIT(24)),
> +	PINCTRL_CONF_DESC(38, REG_GPIO_L_PD, BIT(25)),
> +	PINCTRL_CONF_DESC(39, REG_GPIO_L_PD, BIT(26)),
> +	PINCTRL_CONF_DESC(40, REG_GPIO_L_PD, BIT(27)),
> +	PINCTRL_CONF_DESC(41, REG_GPIO_L_PD, BIT(28)),
> +	PINCTRL_CONF_DESC(42, REG_GPIO_L_PD, BIT(29)),
> +	PINCTRL_CONF_DESC(43, REG_GPIO_L_PD, BIT(30)),
> +	PINCTRL_CONF_DESC(44, REG_GPIO_L_PD, BIT(31)),
> +	PINCTRL_CONF_DESC(45, REG_GPIO_H_PD, BIT(0)),
> +	PINCTRL_CONF_DESC(46, REG_GPIO_H_PD, BIT(1)),
> +	PINCTRL_CONF_DESC(47, REG_GPIO_H_PD, BIT(2)),
> +	PINCTRL_CONF_DESC(48, REG_GPIO_H_PD, BIT(3)),
> +	PINCTRL_CONF_DESC(49, REG_GPIO_H_PD, BIT(4)),
> +	PINCTRL_CONF_DESC(50, REG_GPIO_H_PD, BIT(5)),
> +	PINCTRL_CONF_DESC(51, REG_GPIO_H_PD, BIT(6)),
> +	PINCTRL_CONF_DESC(52, REG_GPIO_H_PD, BIT(7)),
> +	PINCTRL_CONF_DESC(53, REG_GPIO_H_PD, BIT(8)),
> +	PINCTRL_CONF_DESC(54, REG_GPIO_H_PD, BIT(9)),
> +	PINCTRL_CONF_DESC(55, REG_GPIO_H_PD, BIT(10)),
> +	PINCTRL_CONF_DESC(56, REG_GPIO_H_PD, BIT(11)),
> +	PINCTRL_CONF_DESC(57, REG_GPIO_H_PD, BIT(12)),
> +	PINCTRL_CONF_DESC(58, REG_GPIO_H_PD, BIT(13)),
> +	PINCTRL_CONF_DESC(59, REG_GPIO_H_PD, BIT(14)),
> +	PINCTRL_CONF_DESC(60, REG_I2C_SDA_PD, PCIE0_RESET_PD_MASK),
> +	PINCTRL_CONF_DESC(61, REG_I2C_SDA_PD, PCIE1_RESET_PD_MASK),
> +	PINCTRL_CONF_DESC(62, REG_I2C_SDA_PD, PCIE2_RESET_PD_MASK),
> +};
> +
> +static const struct airoha_pinctrl_conf en7581_pinctrl_drive_e2_conf[] = {
> +	PINCTRL_CONF_DESC(0, REG_I2C_SDA_E2, UART1_TXD_E2_MASK),
> +	PINCTRL_CONF_DESC(1, REG_I2C_SDA_E2, UART1_RXD_E2_MASK),
> +	PINCTRL_CONF_DESC(2, REG_I2C_SDA_E2, I2C_SDA_E2_MASK),
> +	PINCTRL_CONF_DESC(3, REG_I2C_SDA_E2, I2C_SCL_E2_MASK),
> +	PINCTRL_CONF_DESC(4, REG_I2C_SDA_E2, SPI_CS0_E2_MASK),
> +	PINCTRL_CONF_DESC(5, REG_I2C_SDA_E2, SPI_CLK_E2_MASK),
> +	PINCTRL_CONF_DESC(6, REG_I2C_SDA_E2, SPI_MOSI_E2_MASK),
> +	PINCTRL_CONF_DESC(7, REG_I2C_SDA_E2, SPI_MISO_E2_MASK),
> +	PINCTRL_CONF_DESC(13, REG_GPIO_L_E2, BIT(0)),
> +	PINCTRL_CONF_DESC(14, REG_GPIO_L_E2, BIT(1)),
> +	PINCTRL_CONF_DESC(15, REG_GPIO_L_E2, BIT(2)),
> +	PINCTRL_CONF_DESC(16, REG_GPIO_L_E2, BIT(3)),
> +	PINCTRL_CONF_DESC(17, REG_GPIO_L_E2, BIT(4)),
> +	PINCTRL_CONF_DESC(18, REG_GPIO_L_E2, BIT(5)),
> +	PINCTRL_CONF_DESC(19, REG_GPIO_L_E2, BIT(6)),
> +	PINCTRL_CONF_DESC(20, REG_GPIO_L_E2, BIT(7)),
> +	PINCTRL_CONF_DESC(21, REG_GPIO_L_E2, BIT(8)),
> +	PINCTRL_CONF_DESC(22, REG_GPIO_L_E2, BIT(9)),
> +	PINCTRL_CONF_DESC(23, REG_GPIO_L_E2, BIT(10)),
> +	PINCTRL_CONF_DESC(24, REG_GPIO_L_E2, BIT(11)),
> +	PINCTRL_CONF_DESC(25, REG_GPIO_L_E2, BIT(12)),
> +	PINCTRL_CONF_DESC(26, REG_GPIO_L_E2, BIT(13)),
> +	PINCTRL_CONF_DESC(27, REG_GPIO_L_E2, BIT(14)),
> +	PINCTRL_CONF_DESC(28, REG_GPIO_L_E2, BIT(15)),
> +	PINCTRL_CONF_DESC(29, REG_GPIO_L_E2, BIT(16)),
> +	PINCTRL_CONF_DESC(30, REG_GPIO_L_E2, BIT(17)),
> +	PINCTRL_CONF_DESC(31, REG_GPIO_L_E2, BIT(18)),
> +	PINCTRL_CONF_DESC(32, REG_GPIO_L_E2, BIT(19)),
> +	PINCTRL_CONF_DESC(33, REG_GPIO_L_E2, BIT(20)),
> +	PINCTRL_CONF_DESC(34, REG_GPIO_L_E2, BIT(21)),
> +	PINCTRL_CONF_DESC(35, REG_GPIO_L_E2, BIT(22)),
> +	PINCTRL_CONF_DESC(36, REG_GPIO_L_E2, BIT(23)),
> +	PINCTRL_CONF_DESC(37, REG_GPIO_L_E2, BIT(24)),
> +	PINCTRL_CONF_DESC(38, REG_GPIO_L_E2, BIT(25)),
> +	PINCTRL_CONF_DESC(39, REG_GPIO_L_E2, BIT(26)),
> +	PINCTRL_CONF_DESC(40, REG_GPIO_L_E2, BIT(27)),
> +	PINCTRL_CONF_DESC(41, REG_GPIO_L_E2, BIT(28)),
> +	PINCTRL_CONF_DESC(42, REG_GPIO_L_E2, BIT(29)),
> +	PINCTRL_CONF_DESC(43, REG_GPIO_L_E2, BIT(30)),
> +	PINCTRL_CONF_DESC(44, REG_GPIO_L_E2, BIT(31)),
> +	PINCTRL_CONF_DESC(45, REG_GPIO_H_E2, BIT(0)),
> +	PINCTRL_CONF_DESC(46, REG_GPIO_H_E2, BIT(1)),
> +	PINCTRL_CONF_DESC(47, REG_GPIO_H_E2, BIT(2)),
> +	PINCTRL_CONF_DESC(48, REG_GPIO_H_E2, BIT(3)),
> +	PINCTRL_CONF_DESC(49, REG_GPIO_H_E2, BIT(4)),
> +	PINCTRL_CONF_DESC(50, REG_GPIO_H_E2, BIT(5)),
> +	PINCTRL_CONF_DESC(51, REG_GPIO_H_E2, BIT(6)),
> +	PINCTRL_CONF_DESC(52, REG_GPIO_H_E2, BIT(7)),
> +	PINCTRL_CONF_DESC(53, REG_GPIO_H_E2, BIT(8)),
> +	PINCTRL_CONF_DESC(54, REG_GPIO_H_E2, BIT(9)),
> +	PINCTRL_CONF_DESC(55, REG_GPIO_H_E2, BIT(10)),
> +	PINCTRL_CONF_DESC(56, REG_GPIO_H_E2, BIT(11)),
> +	PINCTRL_CONF_DESC(57, REG_GPIO_H_E2, BIT(12)),
> +	PINCTRL_CONF_DESC(58, REG_GPIO_H_E2, BIT(13)),
> +	PINCTRL_CONF_DESC(59, REG_GPIO_H_E2, BIT(14)),
> +	PINCTRL_CONF_DESC(60, REG_I2C_SDA_E2, PCIE0_RESET_E2_MASK),
> +	PINCTRL_CONF_DESC(61, REG_I2C_SDA_E2, PCIE1_RESET_E2_MASK),
> +	PINCTRL_CONF_DESC(62, REG_I2C_SDA_E2, PCIE2_RESET_E2_MASK),
> +};
> +
> +static const struct airoha_pinctrl_conf en7581_pinctrl_drive_e4_conf[] = {
> +	PINCTRL_CONF_DESC(0, REG_I2C_SDA_E4, UART1_TXD_E4_MASK),
> +	PINCTRL_CONF_DESC(1, REG_I2C_SDA_E4, UART1_RXD_E4_MASK),
> +	PINCTRL_CONF_DESC(2, REG_I2C_SDA_E4, I2C_SDA_E4_MASK),
> +	PINCTRL_CONF_DESC(3, REG_I2C_SDA_E4, I2C_SCL_E4_MASK),
> +	PINCTRL_CONF_DESC(4, REG_I2C_SDA_E4, SPI_CS0_E4_MASK),
> +	PINCTRL_CONF_DESC(5, REG_I2C_SDA_E4, SPI_CLK_E4_MASK),
> +	PINCTRL_CONF_DESC(6, REG_I2C_SDA_E4, SPI_MOSI_E4_MASK),
> +	PINCTRL_CONF_DESC(7, REG_I2C_SDA_E4, SPI_MISO_E4_MASK),
> +	PINCTRL_CONF_DESC(13, REG_GPIO_L_E4, BIT(0)),
> +	PINCTRL_CONF_DESC(14, REG_GPIO_L_E4, BIT(1)),
> +	PINCTRL_CONF_DESC(15, REG_GPIO_L_E4, BIT(2)),
> +	PINCTRL_CONF_DESC(16, REG_GPIO_L_E4, BIT(3)),
> +	PINCTRL_CONF_DESC(17, REG_GPIO_L_E4, BIT(4)),
> +	PINCTRL_CONF_DESC(18, REG_GPIO_L_E4, BIT(5)),
> +	PINCTRL_CONF_DESC(19, REG_GPIO_L_E4, BIT(6)),
> +	PINCTRL_CONF_DESC(20, REG_GPIO_L_E4, BIT(7)),
> +	PINCTRL_CONF_DESC(21, REG_GPIO_L_E4, BIT(8)),
> +	PINCTRL_CONF_DESC(22, REG_GPIO_L_E4, BIT(9)),
> +	PINCTRL_CONF_DESC(23, REG_GPIO_L_E4, BIT(10)),
> +	PINCTRL_CONF_DESC(24, REG_GPIO_L_E4, BIT(11)),
> +	PINCTRL_CONF_DESC(25, REG_GPIO_L_E4, BIT(12)),
> +	PINCTRL_CONF_DESC(26, REG_GPIO_L_E4, BIT(13)),
> +	PINCTRL_CONF_DESC(27, REG_GPIO_L_E4, BIT(14)),
> +	PINCTRL_CONF_DESC(28, REG_GPIO_L_E4, BIT(15)),
> +	PINCTRL_CONF_DESC(29, REG_GPIO_L_E4, BIT(16)),
> +	PINCTRL_CONF_DESC(30, REG_GPIO_L_E4, BIT(17)),
> +	PINCTRL_CONF_DESC(31, REG_GPIO_L_E4, BIT(18)),
> +	PINCTRL_CONF_DESC(32, REG_GPIO_L_E4, BIT(19)),
> +	PINCTRL_CONF_DESC(33, REG_GPIO_L_E4, BIT(20)),
> +	PINCTRL_CONF_DESC(34, REG_GPIO_L_E4, BIT(21)),
> +	PINCTRL_CONF_DESC(35, REG_GPIO_L_E4, BIT(22)),
> +	PINCTRL_CONF_DESC(36, REG_GPIO_L_E4, BIT(23)),
> +	PINCTRL_CONF_DESC(37, REG_GPIO_L_E4, BIT(24)),
> +	PINCTRL_CONF_DESC(38, REG_GPIO_L_E4, BIT(25)),
> +	PINCTRL_CONF_DESC(39, REG_GPIO_L_E4, BIT(26)),
> +	PINCTRL_CONF_DESC(40, REG_GPIO_L_E4, BIT(27)),
> +	PINCTRL_CONF_DESC(41, REG_GPIO_L_E4, BIT(28)),
> +	PINCTRL_CONF_DESC(42, REG_GPIO_L_E4, BIT(29)),
> +	PINCTRL_CONF_DESC(43, REG_GPIO_L_E4, BIT(30)),
> +	PINCTRL_CONF_DESC(44, REG_GPIO_L_E4, BIT(31)),
> +	PINCTRL_CONF_DESC(45, REG_GPIO_H_E4, BIT(0)),
> +	PINCTRL_CONF_DESC(46, REG_GPIO_H_E4, BIT(1)),
> +	PINCTRL_CONF_DESC(47, REG_GPIO_H_E4, BIT(2)),
> +	PINCTRL_CONF_DESC(48, REG_GPIO_H_E4, BIT(3)),
> +	PINCTRL_CONF_DESC(49, REG_GPIO_H_E4, BIT(4)),
> +	PINCTRL_CONF_DESC(50, REG_GPIO_H_E4, BIT(5)),
> +	PINCTRL_CONF_DESC(51, REG_GPIO_H_E4, BIT(6)),
> +	PINCTRL_CONF_DESC(52, REG_GPIO_H_E4, BIT(7)),
> +	PINCTRL_CONF_DESC(53, REG_GPIO_H_E4, BIT(8)),
> +	PINCTRL_CONF_DESC(54, REG_GPIO_H_E4, BIT(9)),
> +	PINCTRL_CONF_DESC(55, REG_GPIO_H_E4, BIT(10)),
> +	PINCTRL_CONF_DESC(56, REG_GPIO_H_E4, BIT(11)),
> +	PINCTRL_CONF_DESC(57, REG_GPIO_H_E4, BIT(12)),
> +	PINCTRL_CONF_DESC(58, REG_GPIO_H_E4, BIT(13)),
> +	PINCTRL_CONF_DESC(59, REG_GPIO_H_E4, BIT(14)),
> +	PINCTRL_CONF_DESC(60, REG_I2C_SDA_E4, PCIE0_RESET_E4_MASK),
> +	PINCTRL_CONF_DESC(61, REG_I2C_SDA_E4, PCIE1_RESET_E4_MASK),
> +	PINCTRL_CONF_DESC(62, REG_I2C_SDA_E4, PCIE2_RESET_E4_MASK),
> +};
> +
> +static const struct airoha_pinctrl_conf en7581_pinctrl_pcie_rst_od_conf[] = {
> +	PINCTRL_CONF_DESC(60, REG_PCIE_RESET_OD, PCIE0_RESET_OD_MASK),
> +	PINCTRL_CONF_DESC(61, REG_PCIE_RESET_OD, PCIE1_RESET_OD_MASK),
> +	PINCTRL_CONF_DESC(62, REG_PCIE_RESET_OD, PCIE2_RESET_OD_MASK),
> +};
> +
> +static const struct airoha_pinctrl_match_data en7581_pinctrl_match_data = {
> +	.pinctrl_name = KBUILD_MODNAME,
> +	.pinctrl_owner = THIS_MODULE,
> +	.pins = en7581_pinctrl_pins,
> +	.num_pins = ARRAY_SIZE(en7581_pinctrl_pins),
> +	.grps = en7581_pinctrl_groups,
> +	.num_grps = ARRAY_SIZE(en7581_pinctrl_groups),
> +	.funcs = en7581_pinctrl_funcs,
> +	.num_funcs = ARRAY_SIZE(en7581_pinctrl_funcs),
> +	.confs_info = {
> +		[AIROHA_PINCTRL_CONFS_PULLUP] = {
> +			.confs = en7581_pinctrl_pullup_conf,
> +			.num_confs = ARRAY_SIZE(en7581_pinctrl_pullup_conf),
> +		},
> +		[AIROHA_PINCTRL_CONFS_PULLDOWN] = {
> +			.confs = en7581_pinctrl_pulldown_conf,
> +			.num_confs = ARRAY_SIZE(en7581_pinctrl_pulldown_conf),
> +		},
> +		[AIROHA_PINCTRL_CONFS_DRIVE_E2] = {
> +			.confs = en7581_pinctrl_drive_e2_conf,
> +			.num_confs = ARRAY_SIZE(en7581_pinctrl_drive_e2_conf),
> +		},
> +		[AIROHA_PINCTRL_CONFS_DRIVE_E4] = {
> +			.confs = en7581_pinctrl_drive_e4_conf,
> +			.num_confs = ARRAY_SIZE(en7581_pinctrl_drive_e4_conf),
> +		},
> +		[AIROHA_PINCTRL_CONFS_PCIE_RST_OD] = {
> +			.confs = en7581_pinctrl_pcie_rst_od_conf,
> +			.num_confs = ARRAY_SIZE(en7581_pinctrl_pcie_rst_od_conf),
> +		},
> +	},
> +};
> +
> +static const struct of_device_id airoha_pinctrl_of_match[] = {
> +	{ .compatible = "airoha,en7581-pinctrl", .data = &en7581_pinctrl_match_data },
> +	{ /* sentinel */ }
> +};
> +MODULE_DEVICE_TABLE(of, airoha_pinctrl_of_match);
> +
> +static struct platform_driver airoha_pinctrl_driver = {
> +	.probe = airoha_pinctrl_probe,
> +	.driver = {
> +		.name = "pinctrl-airoha-an7581",
> +		.of_match_table = airoha_pinctrl_of_match,
> +	},
> +};
> +module_platform_driver(airoha_pinctrl_driver);
> +
> +MODULE_LICENSE("GPL");
> +MODULE_AUTHOR("Lorenzo Bianconi <lorenzo@kernel.org>");
> +MODULE_AUTHOR("Benjamin Larsson <benjamin.larsson@genexis.eu>");
> +MODULE_AUTHOR("Markus Gothe <markus.gothe@genexis.eu>");
> +MODULE_DESCRIPTION("Pinctrl driver for Airoha AN7581 SoC");
> diff --git a/drivers/pinctrl/airoha/pinctrl-an7583.c b/drivers/pinctrl/airoha/pinctrl-an7583.c
> new file mode 100644
> index 0000000000000..b9d8dd94de5f0
> --- /dev/null
> +++ b/drivers/pinctrl/airoha/pinctrl-an7583.c
> @@ -0,0 +1,1456 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Author: Lorenzo Bianconi <lorenzo@kernel.org>
> + * Author: Benjamin Larsson <benjamin.larsson@genexis.eu>
> + * Author: Markus Gothe <markus.gothe@genexis.eu>
> + */
> +
> +#include "airoha-common.h"
> +
> +/* MUX */
> +#define REG_GPIO_2ND_I2C_MODE			0x0214
> +#define GPIO_LAN3_LED1_MODE_MASK		BIT(10)
> +#define GPIO_LAN3_LED0_MODE_MASK		BIT(9)
> +#define GPIO_LAN2_LED1_MODE_MASK		BIT(8)
> +#define GPIO_LAN2_LED0_MODE_MASK		BIT(7)
> +#define GPIO_LAN1_LED1_MODE_MASK		BIT(6)
> +#define GPIO_LAN1_LED0_MODE_MASK		BIT(5)
> +#define GPIO_LAN0_LED1_MODE_MASK		BIT(4)
> +#define GPIO_LAN0_LED0_MODE_MASK		BIT(3)
> +#define PON_TOD_1PPS_MODE_MASK			BIT(2)
> +#define GSW_TOD_1PPS_MODE_MASK			BIT(1)
> +
> +#define REG_GPIO_SPI_CS1_MODE			0x0218
> +#define GPIO_MDC_IO_MASTER_MODE_MASK		BIT(22)
> +#define GPIO_PCM_SPI_CS4_MODE_MASK		BIT(21)
> +#define GPIO_PCM_SPI_CS3_MODE_MASK		BIT(20)
> +#define AN7583_GPIO_PCM_SPI_CS2_MODE_MASK	BIT(18)
> +#define GPIO_PCM_SPI_CS1_MODE_MASK		BIT(17)
> +#define GPIO_PCM_SPI_MODE_MASK			BIT(16)
> +#define GPIO_PCM2_MODE_MASK			BIT(13)
> +#define GPIO_PCM1_MODE_MASK			BIT(12)
> +#define GPIO_PCM_INT_MODE_MASK			BIT(9)
> +#define GPIO_PCM_RESET_MODE_MASK		BIT(8)
> +#define GPIO_SPI_QUAD_MODE_MASK			BIT(4)
> +#define GPIO_SPI_CS4_MODE_MASK			BIT(3)
> +#define GPIO_SPI_CS3_MODE_MASK			BIT(2)
> +#define GPIO_SPI_CS2_MODE_MASK			BIT(1)
> +#define GPIO_SPI_CS1_MODE_MASK			BIT(0)
> +
> +#define REG_GPIO_PON_MODE			0x021c
> +#define AN7583_MDIO_0_GPIO_MODE_MASK		BIT(26)
> +#define AN7583_MDC_0_GPIO_MODE_MASK		BIT(25)
> +#define AN7583_UART_RXD_GPIO_MODE_MASK		BIT(24)
> +#define AN7583_UART_TXD_GPIO_MODE_MASK		BIT(23)
> +#define AN7583_SPI_MISO_GPIO_MODE_MASK		BIT(22)
> +#define AN7583_SPI_MOSI_GPIO_MODE_MASK		BIT(21)
> +#define AN7583_SPI_CS_GPIO_MODE_MASK		BIT(20)
> +#define AN7583_SPI_CLK_GPIO_MODE_MASK		BIT(19)
> +#define AN7583_I2C1_SDA_GPIO_MODE_MASK		BIT(18)
> +#define AN7583_I2C1_SCL_GPIO_MODE_MASK		BIT(17)
> +#define AN7583_I2C0_SDA_GPIO_MODE_MASK		BIT(16)
> +#define AN7583_I2C0_SCL_GPIO_MODE_MASK		BIT(15)
> +#define GPIO_PARALLEL_NAND_MODE_MASK		BIT(14)
> +#define GPIO_SGMII_MDIO_MODE_MASK		BIT(13)
> +#define SIPO_RCLK_MODE_MASK			BIT(11)
> +#define GPIO_PCIE_RESET1_MASK			BIT(10)
> +#define GPIO_PCIE_RESET0_MASK			BIT(9)
> +#define GPIO_UART5_MODE_MASK			BIT(8)
> +#define GPIO_UART4_MODE_MASK			BIT(7)
> +#define GPIO_HSUART_CTS_RTS_MODE_MASK		BIT(6)
> +#define GPIO_HSUART_MODE_MASK			BIT(5)
> +#define GPIO_UART2_CTS_RTS_MODE_MASK		BIT(4)
> +#define GPIO_UART2_MODE_MASK			BIT(3)
> +#define GPIO_SIPO_MODE_MASK			BIT(2)
> +#define GPIO_EMMC_MODE_MASK			BIT(1)
> +#define GPIO_PON_MODE_MASK			BIT(0)
> +
> +#define REG_NPU_UART_EN				0x0224
> +#define JTAG_UDI_EN_MASK			BIT(4)
> +#define JTAG_DFD_EN_MASK			BIT(3)
> +
> +#define REG_FORCE_GPIO_EN			0x0228
> +#define FORCE_GPIO_EN(n)			BIT(n)
> +
> +/* LED MAP */
> +#define REG_LAN_LED0_MAPPING			0x027c
> +#define REG_LAN_LED1_MAPPING			0x0280
> +
> +#define LAN4_LED_MAPPING_MASK			GENMASK(18, 16)
> +#define LAN4_PHY_LED_MAP(_n)			FIELD_PREP_CONST(LAN4_LED_MAPPING_MASK, (_n))
> +
> +#define LAN3_LED_MAPPING_MASK			GENMASK(14, 12)
> +#define LAN3_PHY_LED_MAP(_n)			FIELD_PREP_CONST(LAN3_LED_MAPPING_MASK, (_n))
> +
> +#define LAN2_LED_MAPPING_MASK			GENMASK(10, 8)
> +#define LAN2_PHY_LED_MAP(_n)			FIELD_PREP_CONST(LAN2_LED_MAPPING_MASK, (_n))
> +
> +#define LAN1_LED_MAPPING_MASK			GENMASK(6, 4)
> +#define LAN1_PHY_LED_MAP(_n)			FIELD_PREP_CONST(LAN1_LED_MAPPING_MASK, (_n))
> +
> +#define LAN0_LED_MAPPING_MASK			GENMASK(2, 0)
> +#define LAN0_PHY_LED_MAP(_n)			FIELD_PREP_CONST(LAN0_LED_MAPPING_MASK, (_n))
> +
> +/* CONF */
> +#define REG_I2C_SDA_E2				0x001c
> +#define AN7583_I2C1_SCL_E2_MASK			BIT(16)
> +#define AN7583_I2C1_SDA_E2_MASK			BIT(15)
> +#define SPI_MISO_E2_MASK			BIT(14)
> +#define SPI_MOSI_E2_MASK			BIT(13)
> +#define SPI_CLK_E2_MASK				BIT(12)
> +#define SPI_CS0_E2_MASK				BIT(11)
> +#define PCIE1_RESET_E2_MASK			BIT(9)
> +#define PCIE0_RESET_E2_MASK			BIT(8)
> +#define AN7583_MDIO_0_E2_MASK			BIT(5)
> +#define AN7583_MDC_0_E2_MASK			BIT(4)
> +#define UART1_RXD_E2_MASK			BIT(3)
> +#define UART1_TXD_E2_MASK			BIT(2)
> +#define I2C_SCL_E2_MASK				BIT(1)
> +#define I2C_SDA_E2_MASK				BIT(0)
> +
> +#define REG_I2C_SDA_E4				0x0020
> +#define AN7583_I2C1_SCL_E4_MASK			BIT(16)
> +#define AN7583_I2C1_SDA_E4_MASK			BIT(15)
> +#define SPI_MISO_E4_MASK			BIT(14)
> +#define SPI_MOSI_E4_MASK			BIT(13)
> +#define SPI_CLK_E4_MASK				BIT(12)
> +#define SPI_CS0_E4_MASK				BIT(11)
> +#define PCIE1_RESET_E4_MASK			BIT(9)
> +#define PCIE0_RESET_E4_MASK			BIT(8)
> +#define AN7583_MDIO_0_E4_MASK			BIT(5)
> +#define AN7583_MDC_0_E4_MASK			BIT(4)
> +#define UART1_RXD_E4_MASK			BIT(3)
> +#define UART1_TXD_E4_MASK			BIT(2)
> +#define I2C_SCL_E4_MASK				BIT(1)
> +#define I2C_SDA_E4_MASK				BIT(0)
> +
> +#define REG_GPIO_L_E2				0x0024
> +#define REG_GPIO_L_E4				0x0028
> +#define REG_GPIO_H_E2				0x002c
> +#define REG_GPIO_H_E4				0x0030
> +
> +#define REG_I2C_SDA_PU				0x0044
> +#define AN7583_I2C1_SCL_PU_MASK			BIT(16)
> +#define AN7583_I2C1_SDA_PU_MASK			BIT(15)
> +#define SPI_MISO_PU_MASK			BIT(14)
> +#define SPI_MOSI_PU_MASK			BIT(13)
> +#define SPI_CLK_PU_MASK				BIT(12)
> +#define SPI_CS0_PU_MASK				BIT(11)
> +#define PCIE1_RESET_PU_MASK			BIT(9)
> +#define PCIE0_RESET_PU_MASK			BIT(8)
> +#define AN7583_MDIO_0_PU_MASK			BIT(5)
> +#define AN7583_MDC_0_PU_MASK			BIT(4)
> +#define UART1_RXD_PU_MASK			BIT(3)
> +#define UART1_TXD_PU_MASK			BIT(2)
> +#define I2C_SCL_PU_MASK				BIT(1)
> +#define I2C_SDA_PU_MASK				BIT(0)
> +
> +#define REG_I2C_SDA_PD				0x0048
> +#define AN7583_I2C1_SCL_PD_MASK			BIT(16)
> +#define AN7583_I2C1_SDA_PD_MASK			BIT(15)
> +#define SPI_MISO_PD_MASK			BIT(14)
> +#define SPI_MOSI_PD_MASK			BIT(13)
> +#define SPI_CLK_PD_MASK				BIT(12)
> +#define SPI_CS0_PD_MASK				BIT(11)
> +#define PCIE1_RESET_PD_MASK			BIT(9)
> +#define PCIE0_RESET_PD_MASK			BIT(8)
> +#define AN7583_MDIO_0_PD_MASK			BIT(5)
> +#define AN7583_MDC_0_PD_MASK			BIT(4)
> +#define UART1_RXD_PD_MASK			BIT(3)
> +#define UART1_TXD_PD_MASK			BIT(2)
> +#define I2C_SCL_PD_MASK				BIT(1)
> +#define I2C_SDA_PD_MASK				BIT(0)
> +
> +#define REG_GPIO_L_PU				0x004c
> +#define REG_GPIO_L_PD				0x0050
> +#define REG_GPIO_H_PU				0x0054
> +#define REG_GPIO_H_PD				0x0058
> +
> +#define REG_PCIE_RESET_OD			0x018c
> +#define PCIE1_RESET_OD_MASK			BIT(1)
> +#define PCIE0_RESET_OD_MASK			BIT(0)
> +
> +/* PWM MODE CONF */
> +#define REG_GPIO_FLASH_MODE_CFG			0x0034
> +#define GPIO15_FLASH_MODE_CFG			BIT(15)
> +#define GPIO14_FLASH_MODE_CFG			BIT(14)
> +#define GPIO13_FLASH_MODE_CFG			BIT(13)
> +#define GPIO12_FLASH_MODE_CFG			BIT(12)
> +#define GPIO11_FLASH_MODE_CFG			BIT(11)
> +#define GPIO10_FLASH_MODE_CFG			BIT(10)
> +#define GPIO9_FLASH_MODE_CFG			BIT(9)
> +#define GPIO8_FLASH_MODE_CFG			BIT(8)
> +#define GPIO7_FLASH_MODE_CFG			BIT(7)
> +#define GPIO6_FLASH_MODE_CFG			BIT(6)
> +#define GPIO5_FLASH_MODE_CFG			BIT(5)
> +#define GPIO4_FLASH_MODE_CFG			BIT(4)
> +#define GPIO3_FLASH_MODE_CFG			BIT(3)
> +#define GPIO2_FLASH_MODE_CFG			BIT(2)
> +#define GPIO1_FLASH_MODE_CFG			BIT(1)
> +#define GPIO0_FLASH_MODE_CFG			BIT(0)
> +
> +/* PWM MODE CONF EXT */
> +#define REG_GPIO_FLASH_MODE_CFG_EXT		0x0068
> +#define GPIO51_FLASH_MODE_CFG			BIT(31)
> +#define GPIO50_FLASH_MODE_CFG			BIT(30)
> +#define GPIO49_FLASH_MODE_CFG			BIT(29)
> +#define GPIO48_FLASH_MODE_CFG			BIT(28)
> +#define GPIO47_FLASH_MODE_CFG			BIT(27)
> +#define GPIO46_FLASH_MODE_CFG			BIT(26)
> +#define GPIO45_FLASH_MODE_CFG			BIT(25)
> +#define GPIO44_FLASH_MODE_CFG			BIT(24)
> +#define GPIO43_FLASH_MODE_CFG			BIT(23)
> +#define GPIO42_FLASH_MODE_CFG			BIT(22)
> +#define GPIO41_FLASH_MODE_CFG			BIT(21)
> +#define GPIO40_FLASH_MODE_CFG			BIT(20)
> +#define GPIO39_FLASH_MODE_CFG			BIT(19)
> +#define GPIO38_FLASH_MODE_CFG			BIT(18)
> +#define GPIO37_FLASH_MODE_CFG			BIT(17)
> +#define GPIO36_FLASH_MODE_CFG			BIT(16)
> +#define GPIO31_FLASH_MODE_CFG			BIT(15)
> +#define GPIO30_FLASH_MODE_CFG			BIT(14)
> +#define GPIO29_FLASH_MODE_CFG			BIT(13)
> +#define GPIO28_FLASH_MODE_CFG			BIT(12)
> +#define GPIO27_FLASH_MODE_CFG			BIT(11)
> +#define GPIO26_FLASH_MODE_CFG			BIT(10)
> +#define GPIO25_FLASH_MODE_CFG			BIT(9)
> +#define GPIO24_FLASH_MODE_CFG			BIT(8)
> +#define GPIO23_FLASH_MODE_CFG			BIT(7)
> +#define GPIO22_FLASH_MODE_CFG			BIT(6)
> +#define GPIO21_FLASH_MODE_CFG			BIT(5)
> +#define GPIO20_FLASH_MODE_CFG			BIT(4)
> +#define GPIO19_FLASH_MODE_CFG			BIT(3)
> +#define GPIO18_FLASH_MODE_CFG			BIT(2)
> +#define GPIO17_FLASH_MODE_CFG			BIT(1)
> +#define GPIO16_FLASH_MODE_CFG			BIT(0)
> +
> +#define AIROHA_PINCTRL_GPIO(gpio, mux_val)			\
> +	{							\
> +		.name = (gpio),					\
> +		.regmap[0] = {					\
> +			AIROHA_FUNC_MUX,			\
> +			REG_GPIO_PON_MODE,			\
> +			(mux_val),				\
> +			(mux_val)				\
> +		},						\
> +		.regmap_size = 1,				\
> +	}
> +
> +#define AIROHA_PINCTRL_GPIO_EXT(gpio, mux_val, smux_val)	\
> +	{							\
> +		.name = (gpio),					\
> +		.regmap[0] = {					\
> +			AIROHA_FUNC_PWM_EXT_MUX,		\
> +			REG_GPIO_FLASH_MODE_CFG_EXT,		\
> +			(mux_val),				\
> +			0					\
> +		},						\
> +		.regmap[1] = {					\
> +			AIROHA_FUNC_MUX,			\
> +			REG_GPIO_PON_MODE,			\
> +			(smux_val),				\
> +			(smux_val)				\
> +		},						\
> +		.regmap_size = 2,				\
> +	}
> +
> +/* PWM */
> +#define AIROHA_PINCTRL_PWM(gpio, mux_val)			\
> +	{							\
> +		.name = (gpio),					\
> +		.regmap[0] = {					\
> +			AIROHA_FUNC_PWM_MUX,			\
> +			REG_GPIO_FLASH_MODE_CFG,		\
> +			(mux_val),				\
> +			(mux_val)				\
> +		},						\
> +		.regmap_size = 1,				\
> +	}
> +
> +#define AIROHA_PINCTRL_PWM_EXT(gpio, mux_val)			\
> +	{							\
> +		.name = (gpio),					\
> +		.regmap[0] = {					\
> +			AIROHA_FUNC_PWM_EXT_MUX,		\
> +			REG_GPIO_FLASH_MODE_CFG_EXT,		\
> +			(mux_val),				\
> +			(mux_val)				\
> +		},						\
> +		.regmap_size = 1,				\
> +	}
> +
> +#define AIROHA_PINCTRL_PWM_EXT_SEC(gpio, mux_val, smux_val)	\
> +	{							\
> +		.name = (gpio),					\
> +		.regmap[0] = {					\
> +			AIROHA_FUNC_PWM_EXT_MUX,		\
> +			REG_GPIO_FLASH_MODE_CFG_EXT,		\
> +			(mux_val),				\
> +			(mux_val)				\
> +		},						\
> +		.regmap[1] = {					\
> +			AIROHA_FUNC_MUX,			\
> +			REG_GPIO_PON_MODE,			\
> +			(smux_val),				\
> +			(smux_val)				\
> +		},						\
> +		.regmap_size = 2,				\
> +	}
> +
> +#define AIROHA_PINCTRL_PHY_LED0(gpio, mux_val, map_mask, map_val)	\
> +	{								\
> +		.name = (gpio),						\
> +		.regmap[0] = {						\
> +			AIROHA_FUNC_MUX,				\
> +			REG_GPIO_2ND_I2C_MODE,				\
> +			(mux_val),					\
> +			(mux_val),					\
> +		},							\
> +		.regmap[1] = {						\
> +			AIROHA_FUNC_MUX,				\
> +			REG_LAN_LED0_MAPPING,				\
> +			(map_mask),					\
> +			(map_val),					\
> +		},							\
> +		.regmap_size = 2,					\
> +	}
> +
> +#define AIROHA_PINCTRL_PHY_LED1(gpio, mux_val, map_mask, map_val)	\
> +	{								\
> +		.name = (gpio),						\
> +		.regmap[0] = {						\
> +			AIROHA_FUNC_MUX,				\
> +			REG_GPIO_2ND_I2C_MODE,				\
> +			(mux_val),					\
> +			(mux_val),					\
> +		},							\
> +		.regmap[1] = {						\
> +			AIROHA_FUNC_MUX,				\
> +			REG_LAN_LED1_MAPPING,				\
> +			(map_mask),					\
> +			(map_val),					\
> +		},							\
> +		.regmap_size = 2,					\
> +	}
> +
> +static struct pinctrl_pin_desc an7583_pinctrl_pins[] = {
> +	PINCTRL_PIN(2, "gpio0"),
> +	PINCTRL_PIN(3, "gpio1"),
> +	PINCTRL_PIN(4, "gpio2"),
> +	PINCTRL_PIN(5, "gpio3"),
> +	PINCTRL_PIN(6, "gpio4"),
> +	PINCTRL_PIN(7, "gpio5"),
> +	PINCTRL_PIN(8, "gpio6"),
> +	PINCTRL_PIN(9, "gpio7"),
> +	PINCTRL_PIN(10, "gpio8"),
> +	PINCTRL_PIN(11, "gpio9"),
> +	PINCTRL_PIN(12, "gpio10"),
> +	PINCTRL_PIN(13, "gpio11"),
> +	PINCTRL_PIN(14, "gpio12"),
> +	PINCTRL_PIN(15, "gpio13"),
> +	PINCTRL_PIN(16, "gpio14"),
> +	PINCTRL_PIN(17, "gpio15"),
> +	PINCTRL_PIN(18, "gpio16"),
> +	PINCTRL_PIN(19, "gpio17"),
> +	PINCTRL_PIN(20, "gpio18"),
> +	PINCTRL_PIN(21, "gpio19"),
> +	PINCTRL_PIN(22, "gpio20"),
> +	PINCTRL_PIN(23, "gpio21"),
> +	PINCTRL_PIN(24, "gpio22"),
> +	PINCTRL_PIN(25, "gpio23"),
> +	PINCTRL_PIN(26, "gpio24"),
> +	PINCTRL_PIN(27, "gpio25"),
> +	PINCTRL_PIN(28, "gpio26"),
> +	PINCTRL_PIN(29, "gpio27"),
> +	PINCTRL_PIN(30, "gpio28"),
> +	PINCTRL_PIN(31, "gpio29"),
> +	PINCTRL_PIN(32, "gpio30"),
> +	PINCTRL_PIN(33, "gpio31"),
> +	PINCTRL_PIN(34, "gpio32"),
> +	PINCTRL_PIN(35, "gpio33"),
> +	PINCTRL_PIN(36, "gpio34"),
> +	PINCTRL_PIN(37, "gpio35"),
> +	PINCTRL_PIN(38, "gpio36"),
> +	PINCTRL_PIN(39, "gpio37"),
> +	PINCTRL_PIN(40, "gpio38"),
> +	PINCTRL_PIN(41, "i2c0_scl"),
> +	PINCTRL_PIN(42, "i2c0_sda"),
> +	PINCTRL_PIN(43, "i2c1_scl"),
> +	PINCTRL_PIN(44, "i2c1_sda"),
> +	PINCTRL_PIN(45, "spi_clk"),
> +	PINCTRL_PIN(46, "spi_cs"),
> +	PINCTRL_PIN(47, "spi_mosi"),
> +	PINCTRL_PIN(48, "spi_miso"),
> +	PINCTRL_PIN(49, "uart_txd"),
> +	PINCTRL_PIN(50, "uart_rxd"),
> +	PINCTRL_PIN(51, "pcie_reset0"),
> +	PINCTRL_PIN(52, "pcie_reset1"),
> +	PINCTRL_PIN(53, "mdc_0"),
> +	PINCTRL_PIN(54, "mdio_0"),
> +};
> +
> +static const int an7583_pon_pins[] = { 15, 16, 17, 18, 19, 20 };
> +static const int an7583_pon_tod_1pps_pins[] = { 32 };
> +static const int an7583_gsw_tod_1pps_pins[] = { 32 };
> +static const int an7583_sipo_pins[] = { 34, 35 };
> +static const int an7583_sipo_rclk_pins[] = { 34, 35, 33 };
> +static const int an7583_mdio_pins[] = { 43, 44 };
> +static const int an7583_uart2_pins[] = { 34, 35 };
> +static const int an7583_uart2_cts_rts_pins[] = { 32, 33 };
> +static const int an7583_hsuart_pins[] = { 30, 31 };
> +static const int an7583_hsuart_cts_rts_pins[] = { 28, 29 };
> +static const int an7583_npu_uart_pins[] = { 7, 8 };
> +static const int an7583_uart4_pins[] = { 7, 8 };
> +static const int an7583_uart5_pins[] = { 23, 24 };
> +static const int an7583_i2c0_pins[] = { 41, 42 };
> +static const int an7583_i2c1_pins[] = { 43, 44 };
> +static const int an7583_jtag_udi_pins[] = { 23, 24, 22, 25, 26 };
> +static const int an7583_jtag_dfd_pins[] = { 23, 24, 22, 25, 26 };
> +static const int an7583_pcm1_pins[] = { 10, 11, 12, 13, 14 };
> +static const int an7583_pcm2_pins[] = { 28, 29, 30, 31, 24 };
> +static const int an7583_spi_pins[] = { 28, 29, 30, 31 };
> +static const int an7583_spi_quad_pins[] = { 25, 26 };
> +static const int an7583_spi_cs1_pins[] = { 27 };
> +static const int an7583_pcm_spi_pins[] = { 28, 29, 30, 31, 10, 11, 12, 13 };
> +static const int an7583_pcm_spi_rst_pins[] = { 14 };
> +static const int an7583_pcm_spi_cs1_pins[] = { 24 };
> +static const int an7583_emmc_pins[] = {
> +	7, 8, 9, 22, 23, 24, 25, 26, 45, 46, 47
> +};
> +static const int an7583_pnand_pins[] = {
> +	7, 8, 9, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 45, 46, 47, 48
> +};
> +static const int an7583_gpio0_pins[] = { 2 };
> +static const int an7583_gpio1_pins[] = { 3 };
> +static const int an7583_gpio2_pins[] = { 4 };
> +static const int an7583_gpio3_pins[] = { 5 };
> +static const int an7583_gpio4_pins[] = { 6 };
> +static const int an7583_gpio5_pins[] = { 7 };
> +static const int an7583_gpio6_pins[] = { 8 };
> +static const int an7583_gpio7_pins[] = { 9 };
> +static const int an7583_gpio8_pins[] = { 10 };
> +static const int an7583_gpio9_pins[] = { 11 };
> +static const int an7583_gpio10_pins[] = { 12 };
> +static const int an7583_gpio11_pins[] = { 13 };
> +static const int an7583_gpio12_pins[] = { 14 };
> +static const int an7583_gpio13_pins[] = { 15 };
> +static const int an7583_gpio14_pins[] = { 16 };
> +static const int an7583_gpio15_pins[] = { 17 };
> +static const int an7583_gpio16_pins[] = { 18 };
> +static const int an7583_gpio17_pins[] = { 19 };
> +static const int an7583_gpio18_pins[] = { 20 };
> +static const int an7583_gpio19_pins[] = { 21 };
> +static const int an7583_gpio20_pins[] = { 22 };
> +static const int an7583_gpio21_pins[] = { 23 };
> +static const int an7583_gpio22_pins[] = { 24 };
> +static const int an7583_gpio23_pins[] = { 25 };
> +static const int an7583_gpio24_pins[] = { 26 };
> +static const int an7583_gpio25_pins[] = { 27 };
> +static const int an7583_gpio26_pins[] = { 28 };
> +static const int an7583_gpio27_pins[] = { 29 };
> +static const int an7583_gpio28_pins[] = { 30 };
> +static const int an7583_gpio29_pins[] = { 31 };
> +static const int an7583_gpio30_pins[] = { 32 };
> +static const int an7583_gpio31_pins[] = { 33 };
> +static const int an7583_gpio32_pins[] = { 34 };
> +static const int an7583_gpio33_pins[] = { 35 };
> +static const int an7583_gpio34_pins[] = { 36 };
> +static const int an7583_gpio35_pins[] = { 37 };
> +static const int an7583_gpio36_pins[] = { 38 };
> +static const int an7583_gpio37_pins[] = { 39 };
> +static const int an7583_gpio38_pins[] = { 40 };
> +static const int an7583_gpio39_pins[] = { 41 };
> +static const int an7583_gpio40_pins[] = { 42 };
> +static const int an7583_gpio41_pins[] = { 43 };
> +static const int an7583_gpio42_pins[] = { 44 };
> +static const int an7583_gpio43_pins[] = { 45 };
> +static const int an7583_gpio44_pins[] = { 46 };
> +static const int an7583_gpio45_pins[] = { 47 };
> +static const int an7583_gpio46_pins[] = { 48 };
> +static const int an7583_gpio47_pins[] = { 49 };
> +static const int an7583_gpio48_pins[] = { 50 };
> +static const int an7583_gpio49_pins[] = { 51 };
> +static const int an7583_gpio50_pins[] = { 52 };
> +static const int an7583_gpio51_pins[] = { 53 };
> +static const int an7583_gpio52_pins[] = { 54 };
> +static const int an7583_pcie_reset0_pins[] = { 51 };
> +static const int an7583_pcie_reset1_pins[] = { 52 };
> +
> +static const struct pingroup an7583_pinctrl_groups[] = {
> +	PINCTRL_PIN_GROUP("pon", an7583_pon),
> +	PINCTRL_PIN_GROUP("pon_tod_1pps", an7583_pon_tod_1pps),
> +	PINCTRL_PIN_GROUP("gsw_tod_1pps", an7583_gsw_tod_1pps),
> +	PINCTRL_PIN_GROUP("sipo", an7583_sipo),
> +	PINCTRL_PIN_GROUP("sipo_rclk", an7583_sipo_rclk),
> +	PINCTRL_PIN_GROUP("mdio", an7583_mdio),
> +	PINCTRL_PIN_GROUP("uart2", an7583_uart2),
> +	PINCTRL_PIN_GROUP("uart2_cts_rts", an7583_uart2_cts_rts),
> +	PINCTRL_PIN_GROUP("hsuart", an7583_hsuart),
> +	PINCTRL_PIN_GROUP("hsuart_cts_rts", an7583_hsuart_cts_rts),
> +	PINCTRL_PIN_GROUP("npu_uart", an7583_npu_uart),
> +	PINCTRL_PIN_GROUP("uart4", an7583_uart4),
> +	PINCTRL_PIN_GROUP("uart5", an7583_uart5),
> +	PINCTRL_PIN_GROUP("i2c0", an7583_i2c0),
> +	PINCTRL_PIN_GROUP("i2c1", an7583_i2c1),
> +	PINCTRL_PIN_GROUP("jtag_udi", an7583_jtag_udi),
> +	PINCTRL_PIN_GROUP("jtag_dfd", an7583_jtag_dfd),
> +	PINCTRL_PIN_GROUP("pcm1", an7583_pcm1),
> +	PINCTRL_PIN_GROUP("pcm2", an7583_pcm2),
> +	PINCTRL_PIN_GROUP("spi", an7583_spi),
> +	PINCTRL_PIN_GROUP("spi_quad", an7583_spi_quad),
> +	PINCTRL_PIN_GROUP("spi_cs1", an7583_spi_cs1),
> +	PINCTRL_PIN_GROUP("pcm_spi", an7583_pcm_spi),
> +	PINCTRL_PIN_GROUP("pcm_spi_rst", an7583_pcm_spi_rst),
> +	PINCTRL_PIN_GROUP("pcm_spi_cs1", an7583_pcm_spi_cs1),
> +	PINCTRL_PIN_GROUP("emmc", an7583_emmc),
> +	PINCTRL_PIN_GROUP("pnand", an7583_pnand),
> +	PINCTRL_PIN_GROUP("gpio0", an7583_gpio0),
> +	PINCTRL_PIN_GROUP("gpio1", an7583_gpio1),
> +	PINCTRL_PIN_GROUP("gpio2", an7583_gpio2),
> +	PINCTRL_PIN_GROUP("gpio3", an7583_gpio3),
> +	PINCTRL_PIN_GROUP("gpio4", an7583_gpio4),
> +	PINCTRL_PIN_GROUP("gpio5", an7583_gpio5),
> +	PINCTRL_PIN_GROUP("gpio6", an7583_gpio6),
> +	PINCTRL_PIN_GROUP("gpio7", an7583_gpio7),
> +	PINCTRL_PIN_GROUP("gpio8", an7583_gpio8),
> +	PINCTRL_PIN_GROUP("gpio9", an7583_gpio9),
> +	PINCTRL_PIN_GROUP("gpio10", an7583_gpio10),
> +	PINCTRL_PIN_GROUP("gpio11", an7583_gpio11),
> +	PINCTRL_PIN_GROUP("gpio12", an7583_gpio12),
> +	PINCTRL_PIN_GROUP("gpio13", an7583_gpio13),
> +	PINCTRL_PIN_GROUP("gpio14", an7583_gpio14),
> +	PINCTRL_PIN_GROUP("gpio15", an7583_gpio15),
> +	PINCTRL_PIN_GROUP("gpio16", an7583_gpio16),
> +	PINCTRL_PIN_GROUP("gpio17", an7583_gpio17),
> +	PINCTRL_PIN_GROUP("gpio18", an7583_gpio18),
> +	PINCTRL_PIN_GROUP("gpio19", an7583_gpio19),
> +	PINCTRL_PIN_GROUP("gpio20", an7583_gpio20),
> +	PINCTRL_PIN_GROUP("gpio21", an7583_gpio21),
> +	PINCTRL_PIN_GROUP("gpio22", an7583_gpio22),
> +	PINCTRL_PIN_GROUP("gpio23", an7583_gpio23),
> +	PINCTRL_PIN_GROUP("gpio24", an7583_gpio24),
> +	PINCTRL_PIN_GROUP("gpio25", an7583_gpio25),
> +	PINCTRL_PIN_GROUP("gpio26", an7583_gpio26),
> +	PINCTRL_PIN_GROUP("gpio27", an7583_gpio27),
> +	PINCTRL_PIN_GROUP("gpio28", an7583_gpio28),
> +	PINCTRL_PIN_GROUP("gpio29", an7583_gpio29),
> +	PINCTRL_PIN_GROUP("gpio30", an7583_gpio30),
> +	PINCTRL_PIN_GROUP("gpio31", an7583_gpio31),
> +	PINCTRL_PIN_GROUP("gpio32", an7583_gpio32),
> +	PINCTRL_PIN_GROUP("gpio33", an7583_gpio33),
> +	PINCTRL_PIN_GROUP("gpio34", an7583_gpio34),
> +	PINCTRL_PIN_GROUP("gpio35", an7583_gpio35),
> +	PINCTRL_PIN_GROUP("gpio36", an7583_gpio36),
> +	PINCTRL_PIN_GROUP("gpio37", an7583_gpio37),
> +	PINCTRL_PIN_GROUP("gpio38", an7583_gpio38),
> +	PINCTRL_PIN_GROUP("gpio39", an7583_gpio39),
> +	PINCTRL_PIN_GROUP("gpio40", an7583_gpio40),
> +	PINCTRL_PIN_GROUP("gpio41", an7583_gpio41),
> +	PINCTRL_PIN_GROUP("gpio42", an7583_gpio42),
> +	PINCTRL_PIN_GROUP("gpio43", an7583_gpio43),
> +	PINCTRL_PIN_GROUP("gpio44", an7583_gpio44),
> +	PINCTRL_PIN_GROUP("gpio45", an7583_gpio45),
> +	PINCTRL_PIN_GROUP("gpio46", an7583_gpio46),
> +	PINCTRL_PIN_GROUP("gpio47", an7583_gpio47),
> +	PINCTRL_PIN_GROUP("gpio48", an7583_gpio48),
> +	PINCTRL_PIN_GROUP("gpio49", an7583_gpio49),
> +	PINCTRL_PIN_GROUP("gpio50", an7583_gpio50),
> +	PINCTRL_PIN_GROUP("gpio51", an7583_gpio51),
> +	PINCTRL_PIN_GROUP("gpio52", an7583_gpio52),
> +	PINCTRL_PIN_GROUP("pcie_reset0", an7583_pcie_reset0),
> +	PINCTRL_PIN_GROUP("pcie_reset1", an7583_pcie_reset1),
> +};
> +
> +static const char *const pon_groups[] = { "pon" };
> +static const char *const tod_1pps_groups[] = {
> +	"pon_tod_1pps", "gsw_tod_1pps"
> +};
> +static const char *const sipo_groups[] = { "sipo", "sipo_rclk" };
> +static const char *const an7583_mdio_groups[] = { "mdio" };
> +static const char *const uart_groups[] = {
> +	"uart2", "uart2_cts_rts", "hsuart", "hsuart_cts_rts",
> +	"uart4", "uart5"
> +};
> +static const char *const jtag_groups[] = { "jtag_udi", "jtag_dfd" };
> +static const char *const pcm_groups[] = { "pcm1", "pcm2" };
> +static const char *const spi_groups[] = { "spi_quad", "spi_cs1" };
> +static const char *const an7583_pcm_spi_groups[] = {
> +	"pcm_spi", "pcm_spi_rst", "pcm_spi_cs1"
> +};
> +static const char *const emmc_groups[] = { "emmc" };
> +static const char *const pnand_groups[] = { "pnand" };
> +static const char *const an7583_gpio_groups[] = {
> +	"gpio39", "gpio40", "gpio41", "gpio42", "gpio43",
> +	"gpio44", "gpio45", "gpio46", "gpio47", "gpio48",
> +	"gpio49", "gpio50", "gpio51", "gpio52"
> +};
> +static const char *const an7583_pcie_reset_groups[] = {
> +	"pcie_reset0", "pcie_reset1"
> +};
> +static const char *const an7583_pwm_groups[] = {
> +	"gpio0",  "gpio1",  "gpio2",  "gpio3",  "gpio4",  "gpio5",
> +	"gpio6",  "gpio7",  "gpio8",  "gpio9",  "gpio10", "gpio11",
> +	"gpio12", "gpio13", "gpio14", "gpio15", "gpio16", "gpio17",
> +	"gpio18", "gpio19", "gpio20", "gpio21", "gpio22", "gpio23",
> +	"gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29",
> +	"gpio30", "gpio31", "gpio36", "gpio37", "gpio38", "gpio39",
> +	"gpio40", "gpio41", "gpio42", "gpio43", "gpio44", "gpio45",
> +	"gpio46", "gpio47", "gpio48", "gpio49", "gpio50", "gpio51"
> +};
> +static const char *const an7583_phy1_led0_groups[] = {
> +	"gpio1", "gpio2", "gpio3", "gpio4"
> +};
> +static const char *const an7583_phy2_led0_groups[] = {
> +	"gpio1", "gpio2", "gpio3", "gpio4"
> +};
> +static const char *const an7583_phy3_led0_groups[] = {
> +	"gpio1", "gpio2", "gpio3", "gpio4"
> +};
> +static const char *const an7583_phy4_led0_groups[] = {
> +	"gpio1", "gpio2", "gpio3", "gpio4"
> +};
> +static const char *const an7583_phy1_led1_groups[] = {
> +	"gpio8", "gpio9", "gpio10", "gpio11"
> +};
> +static const char *const an7583_phy2_led1_groups[] = {
> +	"gpio8", "gpio9", "gpio10", "gpio11"
> +};
> +static const char *const an7583_phy3_led1_groups[] = {
> +	"gpio8", "gpio9", "gpio10", "gpio11"
> +};
> +static const char *const an7583_phy4_led1_groups[] = {
> +	"gpio8", "gpio9", "gpio10", "gpio11"
> +};
> +
> +static const struct airoha_pinctrl_func_group pon_func_group[] = {
> +	{
> +		.name = "pon",
> +		.regmap[0] = {
> +			AIROHA_FUNC_MUX,
> +			REG_GPIO_PON_MODE,
> +			GPIO_PON_MODE_MASK,
> +			GPIO_PON_MODE_MASK
> +		},
> +		.regmap_size = 1,
> +	},
> +};
> +
> +static const struct airoha_pinctrl_func_group tod_1pps_func_group[] = {
> +	{
> +		.name = "pon_tod_1pps",
> +		.regmap[0] = {
> +			AIROHA_FUNC_MUX,
> +			REG_GPIO_2ND_I2C_MODE,
> +			PON_TOD_1PPS_MODE_MASK,
> +			PON_TOD_1PPS_MODE_MASK
> +		},
> +		.regmap_size = 1,
> +	}, {
> +		.name = "gsw_tod_1pps",
> +		.regmap[0] = {
> +			AIROHA_FUNC_MUX,
> +			REG_GPIO_2ND_I2C_MODE,
> +			GSW_TOD_1PPS_MODE_MASK,
> +			GSW_TOD_1PPS_MODE_MASK
> +		},
> +		.regmap_size = 1,
> +	},
> +};
> +
> +static const struct airoha_pinctrl_func_group sipo_func_group[] = {
> +	{
> +		.name = "sipo",
> +		.regmap[0] = {
> +			AIROHA_FUNC_MUX,
> +			REG_GPIO_PON_MODE,
> +			GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK,
> +			GPIO_SIPO_MODE_MASK
> +		},
> +		.regmap_size = 1,
> +	}, {
> +		.name = "sipo_rclk",
> +		.regmap[0] = {
> +			AIROHA_FUNC_MUX,
> +			REG_GPIO_PON_MODE,
> +			GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK,
> +			GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK
> +		},
> +		.regmap_size = 1,
> +	},
> +};
> +
> +static const struct airoha_pinctrl_func_group an7583_mdio_func_group[] = {
> +	{
> +		.name = "mdio",
> +		.regmap[0] = {
> +			AIROHA_FUNC_MUX,
> +			REG_GPIO_PON_MODE,
> +			GPIO_SGMII_MDIO_MODE_MASK,
> +			GPIO_SGMII_MDIO_MODE_MASK
> +		},
> +		.regmap[1] = {
> +			AIROHA_FUNC_MUX,
> +			REG_GPIO_SPI_CS1_MODE,
> +			GPIO_MDC_IO_MASTER_MODE_MASK,
> +			GPIO_MDC_IO_MASTER_MODE_MASK
> +		},
> +		.regmap_size = 2,
> +	},
> +};
> +
> +static const struct airoha_pinctrl_func_group uart_func_group[] = {
> +	{
> +		.name = "uart2",
> +		.regmap[0] = {
> +			AIROHA_FUNC_MUX,
> +			REG_GPIO_PON_MODE,
> +			GPIO_UART2_MODE_MASK,
> +			GPIO_UART2_MODE_MASK
> +		},
> +		.regmap_size = 1,
> +	}, {
> +		.name = "uart2_cts_rts",
> +		.regmap[0] = {
> +			AIROHA_FUNC_MUX,
> +			REG_GPIO_PON_MODE,
> +			GPIO_UART2_MODE_MASK | GPIO_UART2_CTS_RTS_MODE_MASK,
> +			GPIO_UART2_MODE_MASK | GPIO_UART2_CTS_RTS_MODE_MASK
> +		},
> +		.regmap_size = 1,
> +	}, {
> +		.name = "hsuart",
> +		.regmap[0] = {
> +			AIROHA_FUNC_MUX,
> +			REG_GPIO_PON_MODE,
> +			GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK,
> +			GPIO_HSUART_MODE_MASK
> +		},
> +		.regmap_size = 1,
> +	},
> +	{
> +		.name = "hsuart_cts_rts",
> +		.regmap[0] = {
> +			AIROHA_FUNC_MUX,
> +			REG_GPIO_PON_MODE,
> +			GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK,
> +			GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK
> +		},
> +		.regmap_size = 1,
> +	}, {
> +		.name = "uart4",
> +		.regmap[0] = {
> +			AIROHA_FUNC_MUX,
> +			REG_GPIO_PON_MODE,
> +			GPIO_UART4_MODE_MASK,
> +			GPIO_UART4_MODE_MASK
> +		},
> +		.regmap_size = 1,
> +	}, {
> +		.name = "uart5",
> +		.regmap[0] = {
> +			AIROHA_FUNC_MUX,
> +			REG_GPIO_PON_MODE,
> +			GPIO_UART5_MODE_MASK,
> +			GPIO_UART5_MODE_MASK
> +		},
> +		.regmap_size = 1,
> +	},
> +};
> +
> +static const struct airoha_pinctrl_func_group jtag_func_group[] = {
> +	{
> +		.name = "jtag_udi",
> +		.regmap[0] = {
> +			AIROHA_FUNC_MUX,
> +			REG_NPU_UART_EN,
> +			JTAG_UDI_EN_MASK,
> +			JTAG_UDI_EN_MASK
> +		},
> +		.regmap_size = 1,
> +	}, {
> +		.name = "jtag_dfd",
> +		.regmap[0] = {
> +			AIROHA_FUNC_MUX,
> +			REG_NPU_UART_EN,
> +			JTAG_DFD_EN_MASK,
> +			JTAG_DFD_EN_MASK
> +		},
> +		.regmap_size = 1,
> +	},
> +};
> +
> +static const struct airoha_pinctrl_func_group pcm_func_group[] = {
> +	{
> +		.name = "pcm1",
> +		.regmap[0] = {
> +			AIROHA_FUNC_MUX,
> +			REG_GPIO_SPI_CS1_MODE,
> +			GPIO_PCM1_MODE_MASK,
> +			GPIO_PCM1_MODE_MASK
> +		},
> +		.regmap_size = 1,
> +	}, {
> +		.name = "pcm2",
> +		.regmap[0] = {
> +			AIROHA_FUNC_MUX,
> +			REG_GPIO_SPI_CS1_MODE,
> +			GPIO_PCM2_MODE_MASK,
> +			GPIO_PCM2_MODE_MASK
> +		},
> +		.regmap_size = 1,
> +	},
> +};
> +
> +static const struct airoha_pinctrl_func_group spi_func_group[] = {
> +	{
> +		.name = "spi_quad",
> +		.regmap[0] = {
> +			AIROHA_FUNC_MUX,
> +			REG_GPIO_SPI_CS1_MODE,
> +			GPIO_SPI_QUAD_MODE_MASK,
> +			GPIO_SPI_QUAD_MODE_MASK
> +		},
> +		.regmap_size = 1,
> +	}, {
> +		.name = "spi_cs1",
> +		.regmap[0] = {
> +			AIROHA_FUNC_MUX,
> +			REG_GPIO_SPI_CS1_MODE,
> +			GPIO_SPI_CS1_MODE_MASK,
> +			GPIO_SPI_CS1_MODE_MASK
> +		},
> +		.regmap_size = 1,
> +	}, {
> +		.name = "spi_cs2",
> +		.regmap[0] = {
> +			AIROHA_FUNC_MUX,
> +			REG_GPIO_SPI_CS1_MODE,
> +			GPIO_SPI_CS2_MODE_MASK,
> +			GPIO_SPI_CS2_MODE_MASK
> +		},
> +		.regmap_size = 1,
> +	}, {
> +		.name = "spi_cs3",
> +		.regmap[0] = {
> +			AIROHA_FUNC_MUX,
> +			REG_GPIO_SPI_CS1_MODE,
> +			GPIO_SPI_CS3_MODE_MASK,
> +			GPIO_SPI_CS3_MODE_MASK
> +		},
> +		.regmap_size = 1,
> +	}, {
> +		.name = "spi_cs4",
> +		.regmap[0] = {
> +			AIROHA_FUNC_MUX,
> +			REG_GPIO_SPI_CS1_MODE,
> +			GPIO_SPI_CS4_MODE_MASK,
> +			GPIO_SPI_CS4_MODE_MASK
> +		},
> +		.regmap_size = 1,
> +	},
> +};
> +
> +static const struct airoha_pinctrl_func_group an7583_pcm_spi_func_group[] = {
> +	{
> +		.name = "pcm_spi",
> +		.regmap[0] = {
> +			AIROHA_FUNC_MUX,
> +			REG_GPIO_SPI_CS1_MODE,
> +			GPIO_PCM_SPI_MODE_MASK,
> +			GPIO_PCM_SPI_MODE_MASK
> +		},
> +		.regmap_size = 1,
> +	}, {
> +		.name = "pcm_spi_int",
> +		.regmap[0] = {
> +			AIROHA_FUNC_MUX,
> +			REG_GPIO_SPI_CS1_MODE,
> +			GPIO_PCM_INT_MODE_MASK,
> +			GPIO_PCM_INT_MODE_MASK
> +		},
> +		.regmap_size = 1,
> +	}, {
> +		.name = "pcm_spi_rst",
> +		.regmap[0] = {
> +			AIROHA_FUNC_MUX,
> +			REG_GPIO_SPI_CS1_MODE,
> +			GPIO_PCM_RESET_MODE_MASK,
> +			GPIO_PCM_RESET_MODE_MASK
> +		},
> +		.regmap_size = 1,
> +	}, {
> +		.name = "pcm_spi_cs1",
> +		.regmap[0] = {
> +			AIROHA_FUNC_MUX,
> +			REG_GPIO_SPI_CS1_MODE,
> +			GPIO_PCM_SPI_CS1_MODE_MASK,
> +			GPIO_PCM_SPI_CS1_MODE_MASK
> +		},
> +		.regmap_size = 1,
> +	}, {
> +		.name = "pcm_spi_cs2",
> +		.regmap[0] = {
> +			AIROHA_FUNC_MUX,
> +			REG_GPIO_SPI_CS1_MODE,
> +			AN7583_GPIO_PCM_SPI_CS2_MODE_MASK,
> +			AN7583_GPIO_PCM_SPI_CS2_MODE_MASK
> +		},
> +		.regmap_size = 1,
> +	}, {
> +		.name = "pcm_spi_cs3",
> +		.regmap[0] = {
> +			AIROHA_FUNC_MUX,
> +			REG_GPIO_SPI_CS1_MODE,
> +			GPIO_PCM_SPI_CS3_MODE_MASK,
> +			GPIO_PCM_SPI_CS3_MODE_MASK
> +		},
> +		.regmap_size = 1,
> +	}, {
> +		.name = "pcm_spi_cs4",
> +		.regmap[0] = {
> +			AIROHA_FUNC_MUX,
> +			REG_GPIO_SPI_CS1_MODE,
> +			GPIO_PCM_SPI_CS4_MODE_MASK,
> +			GPIO_PCM_SPI_CS4_MODE_MASK
> +		},
> +		.regmap_size = 1,
> +	},
> +};
> +
> +static const struct airoha_pinctrl_func_group emmc_func_group[] = {
> +	{
> +		.name = "emmc",
> +		.regmap[0] = {
> +			AIROHA_FUNC_MUX,
> +			REG_GPIO_PON_MODE,
> +			GPIO_EMMC_MODE_MASK,
> +			GPIO_EMMC_MODE_MASK
> +		},
> +		.regmap_size = 1,
> +	},
> +};
> +
> +static const struct airoha_pinctrl_func_group pnand_func_group[] = {
> +	{
> +		.name = "pnand",
> +		.regmap[0] = {
> +			AIROHA_FUNC_MUX,
> +			REG_GPIO_PON_MODE,
> +			GPIO_PARALLEL_NAND_MODE_MASK,
> +			GPIO_PARALLEL_NAND_MODE_MASK
> +		},
> +		.regmap_size = 1,
> +	},
> +};
> +
> +static const struct airoha_pinctrl_func_group an7583_gpio_func_group[] = {
> +	AIROHA_PINCTRL_GPIO_EXT("gpio39", GPIO39_FLASH_MODE_CFG,
> +				AN7583_I2C0_SCL_GPIO_MODE_MASK),
> +	AIROHA_PINCTRL_GPIO_EXT("gpio40", GPIO40_FLASH_MODE_CFG,
> +				AN7583_I2C0_SDA_GPIO_MODE_MASK),
> +	AIROHA_PINCTRL_GPIO_EXT("gpio41", GPIO41_FLASH_MODE_CFG,
> +				AN7583_I2C1_SCL_GPIO_MODE_MASK),
> +	AIROHA_PINCTRL_GPIO_EXT("gpio42", GPIO42_FLASH_MODE_CFG,
> +				AN7583_I2C1_SDA_GPIO_MODE_MASK),
> +	AIROHA_PINCTRL_GPIO_EXT("gpio43", GPIO43_FLASH_MODE_CFG,
> +				AN7583_SPI_CLK_GPIO_MODE_MASK),
> +	AIROHA_PINCTRL_GPIO_EXT("gpio44", GPIO44_FLASH_MODE_CFG,
> +				AN7583_SPI_CS_GPIO_MODE_MASK),
> +	AIROHA_PINCTRL_GPIO_EXT("gpio45", GPIO45_FLASH_MODE_CFG,
> +				AN7583_SPI_MOSI_GPIO_MODE_MASK),
> +	AIROHA_PINCTRL_GPIO_EXT("gpio46", GPIO46_FLASH_MODE_CFG,
> +				AN7583_SPI_MISO_GPIO_MODE_MASK),
> +	AIROHA_PINCTRL_GPIO_EXT("gpio47", GPIO47_FLASH_MODE_CFG,
> +				AN7583_UART_TXD_GPIO_MODE_MASK),
> +	AIROHA_PINCTRL_GPIO_EXT("gpio48", GPIO48_FLASH_MODE_CFG,
> +				AN7583_UART_RXD_GPIO_MODE_MASK),
> +	AIROHA_PINCTRL_GPIO_EXT("gpio49", GPIO49_FLASH_MODE_CFG,
> +				GPIO_PCIE_RESET0_MASK),
> +	AIROHA_PINCTRL_GPIO_EXT("gpio50", GPIO50_FLASH_MODE_CFG,
> +				GPIO_PCIE_RESET1_MASK),
> +	AIROHA_PINCTRL_GPIO_EXT("gpio51", GPIO51_FLASH_MODE_CFG,
> +				AN7583_MDC_0_GPIO_MODE_MASK),
> +	AIROHA_PINCTRL_GPIO("gpio52", AN7583_MDIO_0_GPIO_MODE_MASK),
> +};
> +
> +static const struct airoha_pinctrl_func_group an7583_pcie_reset_func_group[] = {
> +	{
> +		.name = "pcie_reset0",
> +		.regmap[0] = {
> +			AIROHA_FUNC_MUX,
> +			REG_GPIO_PON_MODE,
> +			GPIO_PCIE_RESET0_MASK,
> +			0
> +		},
> +		.regmap_size = 1,
> +	}, {
> +		.name = "pcie_reset1",
> +		.regmap[0] = {
> +			AIROHA_FUNC_MUX,
> +			REG_GPIO_PON_MODE,
> +			GPIO_PCIE_RESET1_MASK,
> +			0
> +		},
> +		.regmap_size = 1,
> +	},
> +};
> +
> +static const struct airoha_pinctrl_func_group an7583_pwm_func_group[] = {
> +	AIROHA_PINCTRL_PWM("gpio0", GPIO0_FLASH_MODE_CFG),
> +	AIROHA_PINCTRL_PWM("gpio1", GPIO1_FLASH_MODE_CFG),
> +	AIROHA_PINCTRL_PWM("gpio2", GPIO2_FLASH_MODE_CFG),
> +	AIROHA_PINCTRL_PWM("gpio3", GPIO3_FLASH_MODE_CFG),
> +	AIROHA_PINCTRL_PWM("gpio4", GPIO4_FLASH_MODE_CFG),
> +	AIROHA_PINCTRL_PWM("gpio5", GPIO5_FLASH_MODE_CFG),
> +	AIROHA_PINCTRL_PWM("gpio6", GPIO6_FLASH_MODE_CFG),
> +	AIROHA_PINCTRL_PWM("gpio7", GPIO7_FLASH_MODE_CFG),
> +	AIROHA_PINCTRL_PWM("gpio8", GPIO8_FLASH_MODE_CFG),
> +	AIROHA_PINCTRL_PWM("gpio9", GPIO9_FLASH_MODE_CFG),
> +	AIROHA_PINCTRL_PWM("gpio10", GPIO10_FLASH_MODE_CFG),
> +	AIROHA_PINCTRL_PWM("gpio11", GPIO11_FLASH_MODE_CFG),
> +	AIROHA_PINCTRL_PWM("gpio12", GPIO12_FLASH_MODE_CFG),
> +	AIROHA_PINCTRL_PWM("gpio13", GPIO13_FLASH_MODE_CFG),
> +	AIROHA_PINCTRL_PWM("gpio14", GPIO14_FLASH_MODE_CFG),
> +	AIROHA_PINCTRL_PWM("gpio15", GPIO15_FLASH_MODE_CFG),
> +	AIROHA_PINCTRL_PWM_EXT("gpio16", GPIO16_FLASH_MODE_CFG),
> +	AIROHA_PINCTRL_PWM_EXT("gpio17", GPIO17_FLASH_MODE_CFG),
> +	AIROHA_PINCTRL_PWM_EXT("gpio18", GPIO18_FLASH_MODE_CFG),
> +	AIROHA_PINCTRL_PWM_EXT("gpio19", GPIO19_FLASH_MODE_CFG),
> +	AIROHA_PINCTRL_PWM_EXT("gpio20", GPIO20_FLASH_MODE_CFG),
> +	AIROHA_PINCTRL_PWM_EXT("gpio21", GPIO21_FLASH_MODE_CFG),
> +	AIROHA_PINCTRL_PWM_EXT("gpio22", GPIO22_FLASH_MODE_CFG),
> +	AIROHA_PINCTRL_PWM_EXT("gpio23", GPIO23_FLASH_MODE_CFG),
> +	AIROHA_PINCTRL_PWM_EXT("gpio24", GPIO24_FLASH_MODE_CFG),
> +	AIROHA_PINCTRL_PWM_EXT("gpio25", GPIO25_FLASH_MODE_CFG),
> +	AIROHA_PINCTRL_PWM_EXT("gpio26", GPIO26_FLASH_MODE_CFG),
> +	AIROHA_PINCTRL_PWM_EXT("gpio27", GPIO27_FLASH_MODE_CFG),
> +	AIROHA_PINCTRL_PWM_EXT("gpio28", GPIO28_FLASH_MODE_CFG),
> +	AIROHA_PINCTRL_PWM_EXT("gpio29", GPIO29_FLASH_MODE_CFG),
> +	AIROHA_PINCTRL_PWM_EXT("gpio30", GPIO30_FLASH_MODE_CFG),
> +	AIROHA_PINCTRL_PWM_EXT("gpio31", GPIO31_FLASH_MODE_CFG),
> +	AIROHA_PINCTRL_PWM_EXT("gpio36", GPIO36_FLASH_MODE_CFG),
> +	AIROHA_PINCTRL_PWM_EXT("gpio37", GPIO37_FLASH_MODE_CFG),
> +	AIROHA_PINCTRL_PWM_EXT("gpio38", GPIO38_FLASH_MODE_CFG),
> +	AIROHA_PINCTRL_PWM_EXT_SEC("gpio39", GPIO39_FLASH_MODE_CFG,
> +				   AN7583_I2C0_SCL_GPIO_MODE_MASK),
> +	AIROHA_PINCTRL_PWM_EXT_SEC("gpio40", GPIO40_FLASH_MODE_CFG,
> +				   AN7583_I2C0_SDA_GPIO_MODE_MASK),
> +	AIROHA_PINCTRL_PWM_EXT_SEC("gpio41", GPIO41_FLASH_MODE_CFG,
> +				   AN7583_I2C1_SCL_GPIO_MODE_MASK),
> +	AIROHA_PINCTRL_PWM_EXT_SEC("gpio42", GPIO42_FLASH_MODE_CFG,
> +				   AN7583_I2C1_SDA_GPIO_MODE_MASK),
> +	AIROHA_PINCTRL_PWM_EXT_SEC("gpio43", GPIO43_FLASH_MODE_CFG,
> +				   AN7583_SPI_CLK_GPIO_MODE_MASK),
> +	AIROHA_PINCTRL_PWM_EXT_SEC("gpio44", GPIO44_FLASH_MODE_CFG,
> +				   AN7583_SPI_CS_GPIO_MODE_MASK),
> +	AIROHA_PINCTRL_PWM_EXT_SEC("gpio45", GPIO45_FLASH_MODE_CFG,
> +				   AN7583_SPI_MOSI_GPIO_MODE_MASK),
> +	AIROHA_PINCTRL_PWM_EXT_SEC("gpio46", GPIO46_FLASH_MODE_CFG,
> +				   AN7583_SPI_MISO_GPIO_MODE_MASK),
> +	AIROHA_PINCTRL_PWM_EXT_SEC("gpio47", GPIO47_FLASH_MODE_CFG,
> +				   AN7583_UART_TXD_GPIO_MODE_MASK),
> +	AIROHA_PINCTRL_PWM_EXT_SEC("gpio48", GPIO48_FLASH_MODE_CFG,
> +				   AN7583_UART_RXD_GPIO_MODE_MASK),
> +	AIROHA_PINCTRL_PWM_EXT_SEC("gpio49", GPIO49_FLASH_MODE_CFG,
> +				   GPIO_PCIE_RESET0_MASK),
> +	AIROHA_PINCTRL_PWM_EXT_SEC("gpio50", GPIO50_FLASH_MODE_CFG,
> +				   GPIO_PCIE_RESET1_MASK),
> +	AIROHA_PINCTRL_PWM_EXT_SEC("gpio51", GPIO51_FLASH_MODE_CFG,
> +				   AN7583_MDC_0_GPIO_MODE_MASK),
> +};
> +
> +static const struct airoha_pinctrl_func_group an7583_phy1_led0_func_group[] = {
> +	AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK,
> +				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),
> +	AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK,
> +				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)),
> +	AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK,
> +				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)),
> +	AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK,
> +				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),
> +};
> +
> +static const struct airoha_pinctrl_func_group an7583_phy2_led0_func_group[] = {
> +	AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK,
> +				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),
> +	AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK,
> +				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)),
> +	AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK,
> +				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)),
> +	AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK,
> +				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),
> +};
> +
> +static const struct airoha_pinctrl_func_group an7583_phy3_led0_func_group[] = {
> +	AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK,
> +				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
> +	AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK,
> +				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),
> +	AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK,
> +				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),
> +	AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK,
> +				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
> +};
> +
> +static const struct airoha_pinctrl_func_group an7583_phy4_led0_func_group[] = {
> +	AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK,
> +				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)),
> +	AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK,
> +				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)),
> +	AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK,
> +				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)),
> +	AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK,
> +				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)),
> +};
> +
> +static const struct airoha_pinctrl_func_group an7583_phy1_led1_func_group[] = {
> +	AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK,
> +				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),
> +	AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK,
> +				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)),
> +	AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK,
> +				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)),
> +	AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK,
> +				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),
> +};
> +
> +static const struct airoha_pinctrl_func_group an7583_phy2_led1_func_group[] = {
> +	AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK,
> +				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),
> +	AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK,
> +				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)),
> +	AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK,
> +				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)),
> +	AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK,
> +				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),
> +};
> +
> +static const struct airoha_pinctrl_func_group an7583_phy3_led1_func_group[] = {
> +	AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK,
> +				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
> +	AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK,
> +				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),
> +	AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK,
> +				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),
> +	AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK,
> +				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
> +};
> +
> +static const struct airoha_pinctrl_func_group an7583_phy4_led1_func_group[] = {
> +	AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK,
> +				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)),
> +	AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK,
> +				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)),
> +	AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK,
> +				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)),
> +	AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK,
> +				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)),
> +};
> +
> +static const struct airoha_pinctrl_func an7583_pinctrl_funcs[] = {
> +	PINCTRL_FUNC_DESC("pon", pon),
> +	PINCTRL_FUNC_DESC("tod_1pps", tod_1pps),
> +	PINCTRL_FUNC_DESC("sipo", sipo),
> +	PINCTRL_FUNC_DESC("mdio", an7583_mdio),
> +	PINCTRL_FUNC_DESC("uart", uart),
> +	PINCTRL_FUNC_DESC("jtag", jtag),
> +	PINCTRL_FUNC_DESC("pcm", pcm),
> +	PINCTRL_FUNC_DESC("spi", spi),
> +	PINCTRL_FUNC_DESC("pcm_spi", an7583_pcm_spi),
> +	PINCTRL_FUNC_DESC("emmc", emmc),
> +	PINCTRL_FUNC_DESC("pnand", pnand),
> +	PINCTRL_FUNC_DESC("gpio", an7583_gpio),
> +	PINCTRL_FUNC_DESC("pcie_reset", an7583_pcie_reset),
> +	PINCTRL_FUNC_DESC("pwm", an7583_pwm),
> +	PINCTRL_FUNC_DESC("phy1_led0", an7583_phy1_led0),
> +	PINCTRL_FUNC_DESC("phy2_led0", an7583_phy2_led0),
> +	PINCTRL_FUNC_DESC("phy3_led0", an7583_phy3_led0),
> +	PINCTRL_FUNC_DESC("phy4_led0", an7583_phy4_led0),
> +	PINCTRL_FUNC_DESC("phy1_led1", an7583_phy1_led1),
> +	PINCTRL_FUNC_DESC("phy2_led1", an7583_phy2_led1),
> +	PINCTRL_FUNC_DESC("phy3_led1", an7583_phy3_led1),
> +	PINCTRL_FUNC_DESC("phy4_led1", an7583_phy4_led1),
> +};
> +
> +static const struct airoha_pinctrl_conf an7583_pinctrl_pullup_conf[] = {
> +	PINCTRL_CONF_DESC(2, REG_GPIO_L_PU, BIT(0)),
> +	PINCTRL_CONF_DESC(3, REG_GPIO_L_PU, BIT(1)),
> +	PINCTRL_CONF_DESC(4, REG_GPIO_L_PU, BIT(2)),
> +	PINCTRL_CONF_DESC(5, REG_GPIO_L_PU, BIT(3)),
> +	PINCTRL_CONF_DESC(6, REG_GPIO_L_PU, BIT(4)),
> +	PINCTRL_CONF_DESC(7, REG_GPIO_L_PU, BIT(5)),
> +	PINCTRL_CONF_DESC(8, REG_GPIO_L_PU, BIT(6)),
> +	PINCTRL_CONF_DESC(9, REG_GPIO_L_PU, BIT(7)),
> +	PINCTRL_CONF_DESC(10, REG_GPIO_L_PU, BIT(8)),
> +	PINCTRL_CONF_DESC(11, REG_GPIO_L_PU, BIT(9)),
> +	PINCTRL_CONF_DESC(12, REG_GPIO_L_PU, BIT(10)),
> +	PINCTRL_CONF_DESC(13, REG_GPIO_L_PU, BIT(11)),
> +	PINCTRL_CONF_DESC(14, REG_GPIO_L_PU, BIT(12)),
> +	PINCTRL_CONF_DESC(15, REG_GPIO_L_PU, BIT(13)),
> +	PINCTRL_CONF_DESC(16, REG_GPIO_L_PU, BIT(14)),
> +	PINCTRL_CONF_DESC(17, REG_GPIO_L_PU, BIT(15)),
> +	PINCTRL_CONF_DESC(18, REG_GPIO_L_PU, BIT(16)),
> +	PINCTRL_CONF_DESC(19, REG_GPIO_L_PU, BIT(17)),
> +	PINCTRL_CONF_DESC(20, REG_GPIO_L_PU, BIT(18)),
> +	PINCTRL_CONF_DESC(21, REG_GPIO_L_PU, BIT(19)),
> +	PINCTRL_CONF_DESC(22, REG_GPIO_L_PU, BIT(20)),
> +	PINCTRL_CONF_DESC(23, REG_GPIO_L_PU, BIT(21)),
> +	PINCTRL_CONF_DESC(24, REG_GPIO_L_PU, BIT(22)),
> +	PINCTRL_CONF_DESC(25, REG_GPIO_L_PU, BIT(23)),
> +	PINCTRL_CONF_DESC(26, REG_GPIO_L_PU, BIT(24)),
> +	PINCTRL_CONF_DESC(27, REG_GPIO_L_PU, BIT(25)),
> +	PINCTRL_CONF_DESC(28, REG_GPIO_L_PU, BIT(26)),
> +	PINCTRL_CONF_DESC(29, REG_GPIO_L_PU, BIT(27)),
> +	PINCTRL_CONF_DESC(30, REG_GPIO_L_PU, BIT(28)),
> +	PINCTRL_CONF_DESC(31, REG_GPIO_L_PU, BIT(29)),
> +	PINCTRL_CONF_DESC(32, REG_GPIO_L_PU, BIT(30)),
> +	PINCTRL_CONF_DESC(33, REG_GPIO_L_PU, BIT(31)),
> +	PINCTRL_CONF_DESC(34, REG_GPIO_H_PU, BIT(0)),
> +	PINCTRL_CONF_DESC(35, REG_GPIO_H_PU, BIT(1)),
> +	PINCTRL_CONF_DESC(36, REG_GPIO_H_PU, BIT(2)),
> +	PINCTRL_CONF_DESC(37, REG_GPIO_H_PU, BIT(3)),
> +	PINCTRL_CONF_DESC(38, REG_GPIO_H_PU, BIT(4)),
> +	PINCTRL_CONF_DESC(39, REG_GPIO_H_PU, BIT(5)),
> +	PINCTRL_CONF_DESC(40, REG_GPIO_H_PU, BIT(6)),
> +	PINCTRL_CONF_DESC(41, REG_I2C_SDA_PU, I2C_SCL_PU_MASK),
> +	PINCTRL_CONF_DESC(42, REG_I2C_SDA_PU, I2C_SDA_PU_MASK),
> +	PINCTRL_CONF_DESC(43, REG_I2C_SDA_PU, AN7583_I2C1_SCL_PU_MASK),
> +	PINCTRL_CONF_DESC(44, REG_I2C_SDA_PU, AN7583_I2C1_SDA_PU_MASK),
> +	PINCTRL_CONF_DESC(45, REG_I2C_SDA_PU, SPI_CLK_PU_MASK),
> +	PINCTRL_CONF_DESC(46, REG_I2C_SDA_PU, SPI_CS0_PU_MASK),
> +	PINCTRL_CONF_DESC(47, REG_I2C_SDA_PU, SPI_MOSI_PU_MASK),
> +	PINCTRL_CONF_DESC(48, REG_I2C_SDA_PU, SPI_MISO_PU_MASK),
> +	PINCTRL_CONF_DESC(49, REG_I2C_SDA_PU, UART1_TXD_PU_MASK),
> +	PINCTRL_CONF_DESC(50, REG_I2C_SDA_PU, UART1_RXD_PU_MASK),
> +	PINCTRL_CONF_DESC(51, REG_I2C_SDA_PU, PCIE0_RESET_PU_MASK),
> +	PINCTRL_CONF_DESC(52, REG_I2C_SDA_PU, PCIE1_RESET_PU_MASK),
> +	PINCTRL_CONF_DESC(53, REG_I2C_SDA_PU, AN7583_MDC_0_PU_MASK),
> +	PINCTRL_CONF_DESC(54, REG_I2C_SDA_PU, AN7583_MDIO_0_PU_MASK),
> +};
> +
> +static const struct airoha_pinctrl_conf an7583_pinctrl_pulldown_conf[] = {
> +	PINCTRL_CONF_DESC(2, REG_GPIO_L_PD, BIT(0)),
> +	PINCTRL_CONF_DESC(3, REG_GPIO_L_PD, BIT(1)),
> +	PINCTRL_CONF_DESC(4, REG_GPIO_L_PD, BIT(2)),
> +	PINCTRL_CONF_DESC(5, REG_GPIO_L_PD, BIT(3)),
> +	PINCTRL_CONF_DESC(6, REG_GPIO_L_PD, BIT(4)),
> +	PINCTRL_CONF_DESC(7, REG_GPIO_L_PD, BIT(5)),
> +	PINCTRL_CONF_DESC(8, REG_GPIO_L_PD, BIT(6)),
> +	PINCTRL_CONF_DESC(9, REG_GPIO_L_PD, BIT(7)),
> +	PINCTRL_CONF_DESC(10, REG_GPIO_L_PD, BIT(8)),
> +	PINCTRL_CONF_DESC(11, REG_GPIO_L_PD, BIT(9)),
> +	PINCTRL_CONF_DESC(12, REG_GPIO_L_PD, BIT(10)),
> +	PINCTRL_CONF_DESC(13, REG_GPIO_L_PD, BIT(11)),
> +	PINCTRL_CONF_DESC(14, REG_GPIO_L_PD, BIT(12)),
> +	PINCTRL_CONF_DESC(15, REG_GPIO_L_PD, BIT(13)),
> +	PINCTRL_CONF_DESC(16, REG_GPIO_L_PD, BIT(14)),
> +	PINCTRL_CONF_DESC(17, REG_GPIO_L_PD, BIT(15)),
> +	PINCTRL_CONF_DESC(18, REG_GPIO_L_PD, BIT(16)),
> +	PINCTRL_CONF_DESC(19, REG_GPIO_L_PD, BIT(17)),
> +	PINCTRL_CONF_DESC(20, REG_GPIO_L_PD, BIT(18)),
> +	PINCTRL_CONF_DESC(21, REG_GPIO_L_PD, BIT(19)),
> +	PINCTRL_CONF_DESC(22, REG_GPIO_L_PD, BIT(20)),
> +	PINCTRL_CONF_DESC(23, REG_GPIO_L_PD, BIT(21)),
> +	PINCTRL_CONF_DESC(24, REG_GPIO_L_PD, BIT(22)),
> +	PINCTRL_CONF_DESC(25, REG_GPIO_L_PD, BIT(23)),
> +	PINCTRL_CONF_DESC(26, REG_GPIO_L_PD, BIT(24)),
> +	PINCTRL_CONF_DESC(27, REG_GPIO_L_PD, BIT(25)),
> +	PINCTRL_CONF_DESC(28, REG_GPIO_L_PD, BIT(26)),
> +	PINCTRL_CONF_DESC(29, REG_GPIO_L_PD, BIT(27)),
> +	PINCTRL_CONF_DESC(30, REG_GPIO_L_PD, BIT(28)),
> +	PINCTRL_CONF_DESC(31, REG_GPIO_L_PD, BIT(29)),
> +	PINCTRL_CONF_DESC(32, REG_GPIO_L_PD, BIT(30)),
> +	PINCTRL_CONF_DESC(33, REG_GPIO_L_PD, BIT(31)),
> +	PINCTRL_CONF_DESC(34, REG_GPIO_H_PD, BIT(0)),
> +	PINCTRL_CONF_DESC(35, REG_GPIO_H_PD, BIT(1)),
> +	PINCTRL_CONF_DESC(36, REG_GPIO_H_PD, BIT(2)),
> +	PINCTRL_CONF_DESC(37, REG_GPIO_H_PD, BIT(3)),
> +	PINCTRL_CONF_DESC(38, REG_GPIO_H_PD, BIT(4)),
> +	PINCTRL_CONF_DESC(39, REG_GPIO_H_PD, BIT(5)),
> +	PINCTRL_CONF_DESC(40, REG_GPIO_H_PD, BIT(6)),
> +	PINCTRL_CONF_DESC(41, REG_I2C_SDA_PD, I2C_SCL_PD_MASK),
> +	PINCTRL_CONF_DESC(42, REG_I2C_SDA_PD, I2C_SDA_PD_MASK),
> +	PINCTRL_CONF_DESC(43, REG_I2C_SDA_PD, AN7583_I2C1_SCL_PD_MASK),
> +	PINCTRL_CONF_DESC(44, REG_I2C_SDA_PD, AN7583_I2C1_SDA_PD_MASK),
> +	PINCTRL_CONF_DESC(45, REG_I2C_SDA_PD, SPI_CLK_PD_MASK),
> +	PINCTRL_CONF_DESC(46, REG_I2C_SDA_PD, SPI_CS0_PD_MASK),
> +	PINCTRL_CONF_DESC(47, REG_I2C_SDA_PD, SPI_MOSI_PD_MASK),
> +	PINCTRL_CONF_DESC(48, REG_I2C_SDA_PD, SPI_MISO_PD_MASK),
> +	PINCTRL_CONF_DESC(49, REG_I2C_SDA_PD, UART1_TXD_PD_MASK),
> +	PINCTRL_CONF_DESC(50, REG_I2C_SDA_PD, UART1_RXD_PD_MASK),
> +	PINCTRL_CONF_DESC(51, REG_I2C_SDA_PD, PCIE0_RESET_PD_MASK),
> +	PINCTRL_CONF_DESC(52, REG_I2C_SDA_PD, PCIE1_RESET_PD_MASK),
> +	PINCTRL_CONF_DESC(53, REG_I2C_SDA_PD, AN7583_MDC_0_PD_MASK),
> +	PINCTRL_CONF_DESC(54, REG_I2C_SDA_PD, AN7583_MDIO_0_PD_MASK),
> +};
> +
> +static const struct airoha_pinctrl_conf an7583_pinctrl_drive_e2_conf[] = {
> +	PINCTRL_CONF_DESC(2, REG_GPIO_L_E2, BIT(0)),
> +	PINCTRL_CONF_DESC(3, REG_GPIO_L_E2, BIT(1)),
> +	PINCTRL_CONF_DESC(4, REG_GPIO_L_E2, BIT(2)),
> +	PINCTRL_CONF_DESC(5, REG_GPIO_L_E2, BIT(3)),
> +	PINCTRL_CONF_DESC(6, REG_GPIO_L_E2, BIT(4)),
> +	PINCTRL_CONF_DESC(7, REG_GPIO_L_E2, BIT(5)),
> +	PINCTRL_CONF_DESC(8, REG_GPIO_L_E2, BIT(6)),
> +	PINCTRL_CONF_DESC(9, REG_GPIO_L_E2, BIT(7)),
> +	PINCTRL_CONF_DESC(10, REG_GPIO_L_E2, BIT(8)),
> +	PINCTRL_CONF_DESC(11, REG_GPIO_L_E2, BIT(9)),
> +	PINCTRL_CONF_DESC(12, REG_GPIO_L_E2, BIT(10)),
> +	PINCTRL_CONF_DESC(13, REG_GPIO_L_E2, BIT(11)),
> +	PINCTRL_CONF_DESC(14, REG_GPIO_L_E2, BIT(12)),
> +	PINCTRL_CONF_DESC(15, REG_GPIO_L_E2, BIT(13)),
> +	PINCTRL_CONF_DESC(16, REG_GPIO_L_E2, BIT(14)),
> +	PINCTRL_CONF_DESC(17, REG_GPIO_L_E2, BIT(15)),
> +	PINCTRL_CONF_DESC(18, REG_GPIO_L_E2, BIT(16)),
> +	PINCTRL_CONF_DESC(19, REG_GPIO_L_E2, BIT(17)),
> +	PINCTRL_CONF_DESC(20, REG_GPIO_L_E2, BIT(18)),
> +	PINCTRL_CONF_DESC(21, REG_GPIO_L_E2, BIT(19)),
> +	PINCTRL_CONF_DESC(22, REG_GPIO_L_E2, BIT(20)),
> +	PINCTRL_CONF_DESC(23, REG_GPIO_L_E2, BIT(21)),
> +	PINCTRL_CONF_DESC(24, REG_GPIO_L_E2, BIT(22)),
> +	PINCTRL_CONF_DESC(25, REG_GPIO_L_E2, BIT(23)),
> +	PINCTRL_CONF_DESC(26, REG_GPIO_L_E2, BIT(24)),
> +	PINCTRL_CONF_DESC(27, REG_GPIO_L_E2, BIT(25)),
> +	PINCTRL_CONF_DESC(28, REG_GPIO_L_E2, BIT(26)),
> +	PINCTRL_CONF_DESC(29, REG_GPIO_L_E2, BIT(27)),
> +	PINCTRL_CONF_DESC(30, REG_GPIO_L_E2, BIT(28)),
> +	PINCTRL_CONF_DESC(31, REG_GPIO_L_E2, BIT(29)),
> +	PINCTRL_CONF_DESC(32, REG_GPIO_L_E2, BIT(30)),
> +	PINCTRL_CONF_DESC(33, REG_GPIO_L_E2, BIT(31)),
> +	PINCTRL_CONF_DESC(34, REG_GPIO_H_E2, BIT(0)),
> +	PINCTRL_CONF_DESC(35, REG_GPIO_H_E2, BIT(1)),
> +	PINCTRL_CONF_DESC(36, REG_GPIO_H_E2, BIT(2)),
> +	PINCTRL_CONF_DESC(37, REG_GPIO_H_E2, BIT(3)),
> +	PINCTRL_CONF_DESC(38, REG_GPIO_H_E2, BIT(4)),
> +	PINCTRL_CONF_DESC(39, REG_GPIO_H_E2, BIT(5)),
> +	PINCTRL_CONF_DESC(40, REG_GPIO_H_E2, BIT(6)),
> +	PINCTRL_CONF_DESC(41, REG_I2C_SDA_E2, I2C_SCL_E2_MASK),
> +	PINCTRL_CONF_DESC(42, REG_I2C_SDA_E2, I2C_SDA_E2_MASK),
> +	PINCTRL_CONF_DESC(43, REG_I2C_SDA_E2, AN7583_I2C1_SCL_E2_MASK),
> +	PINCTRL_CONF_DESC(44, REG_I2C_SDA_E2, AN7583_I2C1_SDA_E2_MASK),
> +	PINCTRL_CONF_DESC(45, REG_I2C_SDA_E2, SPI_CLK_E2_MASK),
> +	PINCTRL_CONF_DESC(46, REG_I2C_SDA_E2, SPI_CS0_E2_MASK),
> +	PINCTRL_CONF_DESC(47, REG_I2C_SDA_E2, SPI_MOSI_E2_MASK),
> +	PINCTRL_CONF_DESC(48, REG_I2C_SDA_E2, SPI_MISO_E2_MASK),
> +	PINCTRL_CONF_DESC(49, REG_I2C_SDA_E2, UART1_TXD_E2_MASK),
> +	PINCTRL_CONF_DESC(50, REG_I2C_SDA_E2, UART1_RXD_E2_MASK),
> +	PINCTRL_CONF_DESC(51, REG_I2C_SDA_E2, PCIE0_RESET_E2_MASK),
> +	PINCTRL_CONF_DESC(52, REG_I2C_SDA_E2, PCIE1_RESET_E2_MASK),
> +	PINCTRL_CONF_DESC(53, REG_I2C_SDA_E2, AN7583_MDC_0_E2_MASK),
> +	PINCTRL_CONF_DESC(54, REG_I2C_SDA_E2, AN7583_MDIO_0_E2_MASK),
> +};
> +
> +static const struct airoha_pinctrl_conf an7583_pinctrl_drive_e4_conf[] = {
> +	PINCTRL_CONF_DESC(2, REG_GPIO_L_E4, BIT(0)),
> +	PINCTRL_CONF_DESC(3, REG_GPIO_L_E4, BIT(1)),
> +	PINCTRL_CONF_DESC(4, REG_GPIO_L_E4, BIT(2)),
> +	PINCTRL_CONF_DESC(5, REG_GPIO_L_E4, BIT(3)),
> +	PINCTRL_CONF_DESC(6, REG_GPIO_L_E4, BIT(4)),
> +	PINCTRL_CONF_DESC(7, REG_GPIO_L_E4, BIT(5)),
> +	PINCTRL_CONF_DESC(8, REG_GPIO_L_E4, BIT(6)),
> +	PINCTRL_CONF_DESC(9, REG_GPIO_L_E4, BIT(7)),
> +	PINCTRL_CONF_DESC(10, REG_GPIO_L_E4, BIT(8)),
> +	PINCTRL_CONF_DESC(11, REG_GPIO_L_E4, BIT(9)),
> +	PINCTRL_CONF_DESC(12, REG_GPIO_L_E4, BIT(10)),
> +	PINCTRL_CONF_DESC(13, REG_GPIO_L_E4, BIT(11)),
> +	PINCTRL_CONF_DESC(14, REG_GPIO_L_E4, BIT(12)),
> +	PINCTRL_CONF_DESC(15, REG_GPIO_L_E4, BIT(13)),
> +	PINCTRL_CONF_DESC(16, REG_GPIO_L_E4, BIT(14)),
> +	PINCTRL_CONF_DESC(17, REG_GPIO_L_E4, BIT(15)),
> +	PINCTRL_CONF_DESC(18, REG_GPIO_L_E4, BIT(16)),
> +	PINCTRL_CONF_DESC(19, REG_GPIO_L_E4, BIT(17)),
> +	PINCTRL_CONF_DESC(20, REG_GPIO_L_E4, BIT(18)),
> +	PINCTRL_CONF_DESC(21, REG_GPIO_L_E4, BIT(19)),
> +	PINCTRL_CONF_DESC(22, REG_GPIO_L_E4, BIT(20)),
> +	PINCTRL_CONF_DESC(23, REG_GPIO_L_E4, BIT(21)),
> +	PINCTRL_CONF_DESC(24, REG_GPIO_L_E4, BIT(22)),
> +	PINCTRL_CONF_DESC(25, REG_GPIO_L_E4, BIT(23)),
> +	PINCTRL_CONF_DESC(26, REG_GPIO_L_E4, BIT(24)),
> +	PINCTRL_CONF_DESC(27, REG_GPIO_L_E4, BIT(25)),
> +	PINCTRL_CONF_DESC(28, REG_GPIO_L_E4, BIT(26)),
> +	PINCTRL_CONF_DESC(29, REG_GPIO_L_E4, BIT(27)),
> +	PINCTRL_CONF_DESC(30, REG_GPIO_L_E4, BIT(28)),
> +	PINCTRL_CONF_DESC(31, REG_GPIO_L_E4, BIT(29)),
> +	PINCTRL_CONF_DESC(32, REG_GPIO_L_E4, BIT(30)),
> +	PINCTRL_CONF_DESC(33, REG_GPIO_L_E4, BIT(31)),
> +	PINCTRL_CONF_DESC(34, REG_GPIO_H_E4, BIT(0)),
> +	PINCTRL_CONF_DESC(35, REG_GPIO_H_E4, BIT(1)),
> +	PINCTRL_CONF_DESC(36, REG_GPIO_H_E4, BIT(2)),
> +	PINCTRL_CONF_DESC(37, REG_GPIO_H_E4, BIT(3)),
> +	PINCTRL_CONF_DESC(38, REG_GPIO_H_E4, BIT(4)),
> +	PINCTRL_CONF_DESC(39, REG_GPIO_H_E4, BIT(5)),
> +	PINCTRL_CONF_DESC(40, REG_GPIO_H_E4, BIT(6)),
> +	PINCTRL_CONF_DESC(41, REG_I2C_SDA_E4, I2C_SCL_E4_MASK),
> +	PINCTRL_CONF_DESC(42, REG_I2C_SDA_E4, I2C_SDA_E4_MASK),
> +	PINCTRL_CONF_DESC(43, REG_I2C_SDA_E4, AN7583_I2C1_SCL_E4_MASK),
> +	PINCTRL_CONF_DESC(44, REG_I2C_SDA_E4, AN7583_I2C1_SDA_E4_MASK),
> +	PINCTRL_CONF_DESC(45, REG_I2C_SDA_E4, SPI_CLK_E4_MASK),
> +	PINCTRL_CONF_DESC(46, REG_I2C_SDA_E4, SPI_CS0_E4_MASK),
> +	PINCTRL_CONF_DESC(47, REG_I2C_SDA_E4, SPI_MOSI_E4_MASK),
> +	PINCTRL_CONF_DESC(48, REG_I2C_SDA_E4, SPI_MISO_E4_MASK),
> +	PINCTRL_CONF_DESC(49, REG_I2C_SDA_E4, UART1_TXD_E4_MASK),
> +	PINCTRL_CONF_DESC(50, REG_I2C_SDA_E4, UART1_RXD_E4_MASK),
> +	PINCTRL_CONF_DESC(51, REG_I2C_SDA_E4, PCIE0_RESET_E4_MASK),
> +	PINCTRL_CONF_DESC(52, REG_I2C_SDA_E4, PCIE1_RESET_E4_MASK),
> +	PINCTRL_CONF_DESC(53, REG_I2C_SDA_E4, AN7583_MDC_0_E4_MASK),
> +	PINCTRL_CONF_DESC(54, REG_I2C_SDA_E4, AN7583_MDIO_0_E4_MASK),
> +};
> +
> +static const struct airoha_pinctrl_conf an7583_pinctrl_pcie_rst_od_conf[] = {
> +	PINCTRL_CONF_DESC(51, REG_PCIE_RESET_OD, PCIE0_RESET_OD_MASK),
> +	PINCTRL_CONF_DESC(52, REG_PCIE_RESET_OD, PCIE1_RESET_OD_MASK),
> +};
> +
> +static const struct airoha_pinctrl_match_data an7583_pinctrl_match_data = {
> +	.pinctrl_name = KBUILD_MODNAME,
> +	.pinctrl_owner = THIS_MODULE,
> +	.pins = an7583_pinctrl_pins,
> +	.num_pins = ARRAY_SIZE(an7583_pinctrl_pins),
> +	.grps = an7583_pinctrl_groups,
> +	.num_grps = ARRAY_SIZE(an7583_pinctrl_groups),
> +	.funcs = an7583_pinctrl_funcs,
> +	.num_funcs = ARRAY_SIZE(an7583_pinctrl_funcs),
> +	.confs_info = {
> +		[AIROHA_PINCTRL_CONFS_PULLUP] = {
> +			.confs = an7583_pinctrl_pullup_conf,
> +			.num_confs = ARRAY_SIZE(an7583_pinctrl_pullup_conf),
> +		},
> +		[AIROHA_PINCTRL_CONFS_PULLDOWN] = {
> +			.confs = an7583_pinctrl_pulldown_conf,
> +			.num_confs = ARRAY_SIZE(an7583_pinctrl_pulldown_conf),
> +		},
> +		[AIROHA_PINCTRL_CONFS_DRIVE_E2] = {
> +			.confs = an7583_pinctrl_drive_e2_conf,
> +			.num_confs = ARRAY_SIZE(an7583_pinctrl_drive_e2_conf),
> +		},
> +		[AIROHA_PINCTRL_CONFS_DRIVE_E4] = {
> +			.confs = an7583_pinctrl_drive_e4_conf,
> +			.num_confs = ARRAY_SIZE(an7583_pinctrl_drive_e4_conf),
> +		},
> +		[AIROHA_PINCTRL_CONFS_PCIE_RST_OD] = {
> +			.confs = an7583_pinctrl_pcie_rst_od_conf,
> +			.num_confs = ARRAY_SIZE(an7583_pinctrl_pcie_rst_od_conf),
> +		},
> +	},
> +};
> +
> +static const struct of_device_id airoha_pinctrl_of_match[] = {
> +	{ .compatible = "airoha,an7583-pinctrl", .data = &an7583_pinctrl_match_data },
> +	{ /* sentinel */ }
> +};
> +MODULE_DEVICE_TABLE(of, airoha_pinctrl_of_match);
> +
> +static struct platform_driver airoha_pinctrl_driver = {
> +	.probe = airoha_pinctrl_probe,
> +	.driver = {
> +		.name = "pinctrl-airoha-an7583",
> +		.of_match_table = airoha_pinctrl_of_match,
> +	},
> +};
> +module_platform_driver(airoha_pinctrl_driver);
> +
> +MODULE_LICENSE("GPL");
> +MODULE_AUTHOR("Lorenzo Bianconi <lorenzo@kernel.org>");
> +MODULE_AUTHOR("Benjamin Larsson <benjamin.larsson@genexis.eu>");
> +MODULE_AUTHOR("Markus Gothe <markus.gothe@genexis.eu>");
> +MODULE_DESCRIPTION("Pinctrl driver for Airoha AN7583 SoC");
> -- 
> 2.53.0
> 

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Re: [PATCH v7 20/34] pinctrl: airoha: split driver on shared code and SoC specific drivers

[Mikhail Kshevetskiy]

On 7/27/26 12:14, Lorenzo Bianconi wrote:
>> Split combined an7581/an7583 source file on a
>>  * shared pinctrl code (pinctrl-airoha.c)
>>  * an7581 specific pinctrl driver (pinctrl-an7581.c)
>>  * an7583 specific pinctrl driver (pinctrl-an7583.c)
> I do not think we can have 7581 and 7583 chips at the same time on a given
> board so I guess we can avoid creating a dedicated module for the common code.
> I guess we can just create a library we can compile in. What do yout think?
>
> Regards,
> Lorenzo
Hm, how do you suggest to implement it? In the generic kernel case  we
should not
load airoha pinctrl library if we are booting from non airoha board. 
>
>> Ininialization code was adapted a bit to work properly for shared
>> and SoC specific cases.
>>
>> Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
>> ---
>>  drivers/pinctrl/airoha/Kconfig          |   24 +-
>>  drivers/pinctrl/airoha/Makefile         |    5 +
>>  drivers/pinctrl/airoha/airoha-common.h  |    5 +
>>  drivers/pinctrl/airoha/pinctrl-airoha.c | 2382 +----------------------
>>  drivers/pinctrl/airoha/pinctrl-an7581.c | 1486 ++++++++++++++
>>  drivers/pinctrl/airoha/pinctrl-an7583.c | 1456 ++++++++++++++
>>  6 files changed, 2984 insertions(+), 2374 deletions(-)
>>  create mode 100644 drivers/pinctrl/airoha/pinctrl-an7581.c
>>  create mode 100644 drivers/pinctrl/airoha/pinctrl-an7583.c
>>
>> diff --git a/drivers/pinctrl/airoha/Kconfig b/drivers/pinctrl/airoha/Kconfig
>> index 03adaeae8fc3a..dae6608bc72dd 100644
>> --- a/drivers/pinctrl/airoha/Kconfig
>> +++ b/drivers/pinctrl/airoha/Kconfig
>> @@ -3,9 +3,9 @@ menu "Airoha pinctrl drivers"
>>  	depends on ARCH_AIROHA || COMPILE_TEST
>>  
>>  config PINCTRL_AIROHA
>> -	tristate "Airoha EN7581 pin control"
>> +	tristate "Airoha pin control"
>>  	depends on OF
>> -	depends on ARM64 || COMPILE_TEST
>> +	depends on ARCH_AIROHA || COMPILE_TEST
>>  	select PINMUX
>>  	select GENERIC_PINCONF
>>  	select GENERIC_PINCTRL_GROUPS
>> @@ -13,8 +13,26 @@ config PINCTRL_AIROHA
>>  	select GPIOLIB
>>  	select GPIOLIB_IRQCHIP
>>  	select REGMAP_MMIO
>> +	imply PINCTRL_AIROHA_AN7581
>> +	imply PINCTRL_AIROHA_AN7583
>> +	help
>> +	  Shared pin controller and gpio driver code for different
>> +	  Airoha SoCs.
>> +
>> +config PINCTRL_AIROHA_AN7581
>> +	tristate "AN7581 pinctrl"
>> +	depends on ARM64 || COMPILE_TEST
>> +	depends on PINCTRL_AIROHA
>> +	help
>> +	  Say yes here to support pin controller and gpio driver
>> +	  on Airoha AN7581, AN7566, AN7551 and other compatible SoCs.
>> +
>> +config PINCTRL_AIROHA_AN7583
>> +	tristate "AN7583 pinctrl"
>> +	depends on ARM64 || COMPILE_TEST
>> +	depends on PINCTRL_AIROHA
>>  	help
>>  	  Say yes here to support pin controller and gpio driver
>> -	  on Airoha EN7581 SoC.
>> +	  on Airoha AN7583, AN7553, AN7567 and other compatible SoCs.
>>  
>>  endmenu
>> diff --git a/drivers/pinctrl/airoha/Makefile b/drivers/pinctrl/airoha/Makefile
>> index a25b744dd7a8a..cfd68c45ae0f0 100644
>> --- a/drivers/pinctrl/airoha/Makefile
>> +++ b/drivers/pinctrl/airoha/Makefile
>> @@ -1,3 +1,8 @@
>>  # SPDX-License-Identifier: GPL-2.0
>>  
>> +# shared code
>>  obj-$(CONFIG_PINCTRL_AIROHA)		+= pinctrl-airoha.o
>> +
>> +# SoC drivers
>> +obj-$(CONFIG_PINCTRL_AIROHA_AN7581)	+= pinctrl-an7581.o
>> +obj-$(CONFIG_PINCTRL_AIROHA_AN7583)	+= pinctrl-an7583.o
>> diff --git a/drivers/pinctrl/airoha/airoha-common.h b/drivers/pinctrl/airoha/airoha-common.h
>> index 40d7e515c09eb..f73e90ca860f4 100644
>> --- a/drivers/pinctrl/airoha/airoha-common.h
>> +++ b/drivers/pinctrl/airoha/airoha-common.h
>> @@ -148,9 +148,12 @@ struct airoha_pinctrl {
>>  	struct regmap *regmap;
>>  
>>  	struct airoha_pinctrl_gpiochip gpiochip;
>> +	struct irq_chip gpio_irq_chip;
>>  };
>>  
>>  struct airoha_pinctrl_match_data {
>> +	const char *pinctrl_name;
>> +	struct module *pinctrl_owner;
>>  	const struct pinctrl_pin_desc *pins;
>>  	const unsigned int num_pins;
>>  	const struct pingroup *grps;
>> @@ -160,4 +163,6 @@ struct airoha_pinctrl_match_data {
>>  	const struct airoha_pinctrl_confs_info confs_info[AIROHA_PINCTRL_CONFS_MAX];
>>  };
>>  
>> +int airoha_pinctrl_probe(struct platform_device *pdev);
>> +
>>  #endif
>> diff --git a/drivers/pinctrl/airoha/pinctrl-airoha.c b/drivers/pinctrl/airoha/pinctrl-airoha.c
>> index f42631afc05d3..a46596eb1493b 100644
>> --- a/drivers/pinctrl/airoha/pinctrl-airoha.c
>> +++ b/drivers/pinctrl/airoha/pinctrl-airoha.c
>> @@ -7,365 +7,6 @@
>>  
>>  #include "airoha-common.h"
>>  
>> -/* MUX */
>> -#define REG_GPIO_2ND_I2C_MODE			0x0214
>> -#define GPIO_MDC_IO_MASTER_MODE_MASK		BIT(14)
>> -#define GPIO_I2C_MASTER_MODE_MODE		BIT(13)
>> -#define GPIO_I2S_MODE_MASK			BIT(12)
>> -#define GPIO_I2C_SLAVE_MODE_MODE		BIT(11)
>> -#define GPIO_LAN3_LED1_MODE_MASK		BIT(10)
>> -#define GPIO_LAN3_LED0_MODE_MASK		BIT(9)
>> -#define GPIO_LAN2_LED1_MODE_MASK		BIT(8)
>> -#define GPIO_LAN2_LED0_MODE_MASK		BIT(7)
>> -#define GPIO_LAN1_LED1_MODE_MASK		BIT(6)
>> -#define GPIO_LAN1_LED0_MODE_MASK		BIT(5)
>> -#define GPIO_LAN0_LED1_MODE_MASK		BIT(4)
>> -#define GPIO_LAN0_LED0_MODE_MASK		BIT(3)
>> -#define PON_TOD_1PPS_MODE_MASK			BIT(2)
>> -#define GSW_TOD_1PPS_MODE_MASK			BIT(1)
>> -#define GPIO_2ND_I2C_MODE_MASK			BIT(0)
>> -
>> -#define REG_GPIO_SPI_CS1_MODE			0x0218
>> -#define GPIO_PCM_SPI_CS4_MODE_MASK		BIT(21)
>> -#define GPIO_PCM_SPI_CS3_MODE_MASK		BIT(20)
>> -#define GPIO_PCM_SPI_CS2_MODE_P156_MASK		BIT(19)
>> -#define GPIO_PCM_SPI_CS2_MODE_P128_MASK		BIT(18)
>> -#define AN7583_GPIO_PCM_SPI_CS2_MODE_MASK	BIT(18)
>> -#define GPIO_PCM_SPI_CS1_MODE_MASK		BIT(17)
>> -#define GPIO_PCM_SPI_MODE_MASK			BIT(16)
>> -#define GPIO_PCM2_MODE_MASK			BIT(13)
>> -#define GPIO_PCM1_MODE_MASK			BIT(12)
>> -#define GPIO_PCM_INT_MODE_MASK			BIT(9)
>> -#define GPIO_PCM_RESET_MODE_MASK		BIT(8)
>> -#define GPIO_SPI_QUAD_MODE_MASK			BIT(4)
>> -#define GPIO_SPI_CS4_MODE_MASK			BIT(3)
>> -#define GPIO_SPI_CS3_MODE_MASK			BIT(2)
>> -#define GPIO_SPI_CS2_MODE_MASK			BIT(1)
>> -#define GPIO_SPI_CS1_MODE_MASK			BIT(0)
>> -
>> -#define REG_GPIO_PON_MODE			0x021c
>> -#define AN7583_MDIO_0_GPIO_MODE_MASK		BIT(26)
>> -#define AN7583_MDC_0_GPIO_MODE_MASK		BIT(25)
>> -#define AN7583_UART_RXD_GPIO_MODE_MASK		BIT(24)
>> -#define AN7583_UART_TXD_GPIO_MODE_MASK		BIT(23)
>> -#define AN7583_SPI_MISO_GPIO_MODE_MASK		BIT(22)
>> -#define AN7583_SPI_MOSI_GPIO_MODE_MASK		BIT(21)
>> -#define AN7583_SPI_CS_GPIO_MODE_MASK		BIT(20)
>> -#define AN7583_SPI_CLK_GPIO_MODE_MASK		BIT(19)
>> -#define AN7583_I2C1_SDA_GPIO_MODE_MASK		BIT(18)
>> -#define AN7583_I2C1_SCL_GPIO_MODE_MASK		BIT(17)
>> -#define AN7583_I2C0_SDA_GPIO_MODE_MASK		BIT(16)
>> -#define AN7583_I2C0_SCL_GPIO_MODE_MASK		BIT(15)
>> -#define GPIO_PARALLEL_NAND_MODE_MASK		BIT(14)
>> -#define GPIO_SGMII_MDIO_MODE_MASK		BIT(13)
>> -#define GPIO_PCIE_RESET2_MASK			BIT(12)
>> -#define SIPO_RCLK_MODE_MASK			BIT(11)
>> -#define GPIO_PCIE_RESET1_MASK			BIT(10)
>> -#define GPIO_PCIE_RESET0_MASK			BIT(9)
>> -#define GPIO_UART5_MODE_MASK			BIT(8)
>> -#define GPIO_UART4_MODE_MASK			BIT(7)
>> -#define GPIO_HSUART_CTS_RTS_MODE_MASK		BIT(6)
>> -#define GPIO_HSUART_MODE_MASK			BIT(5)
>> -#define GPIO_UART2_CTS_RTS_MODE_MASK		BIT(4)
>> -#define GPIO_UART2_MODE_MASK			BIT(3)
>> -#define GPIO_SIPO_MODE_MASK			BIT(2)
>> -#define GPIO_EMMC_MODE_MASK			BIT(1)
>> -#define GPIO_PON_MODE_MASK			BIT(0)
>> -
>> -#define REG_NPU_UART_EN				0x0224
>> -#define JTAG_UDI_EN_MASK			BIT(4)
>> -#define JTAG_DFD_EN_MASK			BIT(3)
>> -
>> -#define REG_FORCE_GPIO_EN			0x0228
>> -#define FORCE_GPIO_EN(n)			BIT(n)
>> -
>> -/* LED MAP */
>> -#define REG_LAN_LED0_MAPPING			0x027c
>> -#define REG_LAN_LED1_MAPPING			0x0280
>> -
>> -#define LAN4_LED_MAPPING_MASK			GENMASK(18, 16)
>> -#define LAN4_PHY_LED_MAP(_n)			FIELD_PREP_CONST(LAN4_LED_MAPPING_MASK, (_n))
>> -
>> -#define LAN3_LED_MAPPING_MASK			GENMASK(14, 12)
>> -#define LAN3_PHY_LED_MAP(_n)			FIELD_PREP_CONST(LAN3_LED_MAPPING_MASK, (_n))
>> -
>> -#define LAN2_LED_MAPPING_MASK			GENMASK(10, 8)
>> -#define LAN2_PHY_LED_MAP(_n)			FIELD_PREP_CONST(LAN2_LED_MAPPING_MASK, (_n))
>> -
>> -#define LAN1_LED_MAPPING_MASK			GENMASK(6, 4)
>> -#define LAN1_PHY_LED_MAP(_n)			FIELD_PREP_CONST(LAN1_LED_MAPPING_MASK, (_n))
>> -
>> -#define LAN0_LED_MAPPING_MASK			GENMASK(2, 0)
>> -#define LAN0_PHY_LED_MAP(_n)			FIELD_PREP_CONST(LAN0_LED_MAPPING_MASK, (_n))
>> -
>> -/* CONF */
>> -#define REG_I2C_SDA_E2				0x001c
>> -#define AN7583_I2C1_SCL_E2_MASK			BIT(16)
>> -#define AN7583_I2C1_SDA_E2_MASK			BIT(15)
>> -#define SPI_MISO_E2_MASK			BIT(14)
>> -#define SPI_MOSI_E2_MASK			BIT(13)
>> -#define SPI_CLK_E2_MASK				BIT(12)
>> -#define SPI_CS0_E2_MASK				BIT(11)
>> -#define PCIE2_RESET_E2_MASK			BIT(10)
>> -#define PCIE1_RESET_E2_MASK			BIT(9)
>> -#define PCIE0_RESET_E2_MASK			BIT(8)
>> -#define AN7583_MDIO_0_E2_MASK			BIT(5)
>> -#define AN7583_MDC_0_E2_MASK			BIT(4)
>> -#define UART1_RXD_E2_MASK			BIT(3)
>> -#define UART1_TXD_E2_MASK			BIT(2)
>> -#define I2C_SCL_E2_MASK				BIT(1)
>> -#define I2C_SDA_E2_MASK				BIT(0)
>> -
>> -#define REG_I2C_SDA_E4				0x0020
>> -#define AN7583_I2C1_SCL_E4_MASK			BIT(16)
>> -#define AN7583_I2C1_SDA_E4_MASK			BIT(15)
>> -#define SPI_MISO_E4_MASK			BIT(14)
>> -#define SPI_MOSI_E4_MASK			BIT(13)
>> -#define SPI_CLK_E4_MASK				BIT(12)
>> -#define SPI_CS0_E4_MASK				BIT(11)
>> -#define PCIE2_RESET_E4_MASK			BIT(10)
>> -#define PCIE1_RESET_E4_MASK			BIT(9)
>> -#define PCIE0_RESET_E4_MASK			BIT(8)
>> -#define AN7583_MDIO_0_E4_MASK			BIT(5)
>> -#define AN7583_MDC_0_E4_MASK			BIT(4)
>> -#define UART1_RXD_E4_MASK			BIT(3)
>> -#define UART1_TXD_E4_MASK			BIT(2)
>> -#define I2C_SCL_E4_MASK				BIT(1)
>> -#define I2C_SDA_E4_MASK				BIT(0)
>> -
>> -#define REG_GPIO_L_E2				0x0024
>> -#define REG_GPIO_L_E4				0x0028
>> -#define REG_GPIO_H_E2				0x002c
>> -#define REG_GPIO_H_E4				0x0030
>> -
>> -#define REG_I2C_SDA_PU				0x0044
>> -#define AN7583_I2C1_SCL_PU_MASK			BIT(16)
>> -#define AN7583_I2C1_SDA_PU_MASK			BIT(15)
>> -#define SPI_MISO_PU_MASK			BIT(14)
>> -#define SPI_MOSI_PU_MASK			BIT(13)
>> -#define SPI_CLK_PU_MASK				BIT(12)
>> -#define SPI_CS0_PU_MASK				BIT(11)
>> -#define PCIE2_RESET_PU_MASK			BIT(10)
>> -#define PCIE1_RESET_PU_MASK			BIT(9)
>> -#define PCIE0_RESET_PU_MASK			BIT(8)
>> -#define AN7583_MDIO_0_PU_MASK			BIT(5)
>> -#define AN7583_MDC_0_PU_MASK			BIT(4)
>> -#define UART1_RXD_PU_MASK			BIT(3)
>> -#define UART1_TXD_PU_MASK			BIT(2)
>> -#define I2C_SCL_PU_MASK				BIT(1)
>> -#define I2C_SDA_PU_MASK				BIT(0)
>> -
>> -#define REG_I2C_SDA_PD				0x0048
>> -#define AN7583_I2C1_SCL_PD_MASK			BIT(16)
>> -#define AN7583_I2C1_SDA_PD_MASK			BIT(15)
>> -#define SPI_MISO_PD_MASK			BIT(14)
>> -#define SPI_MOSI_PD_MASK			BIT(13)
>> -#define SPI_CLK_PD_MASK				BIT(12)
>> -#define SPI_CS0_PD_MASK				BIT(11)
>> -#define PCIE2_RESET_PD_MASK			BIT(10)
>> -#define PCIE1_RESET_PD_MASK			BIT(9)
>> -#define PCIE0_RESET_PD_MASK			BIT(8)
>> -#define AN7583_MDIO_0_PD_MASK			BIT(5)
>> -#define AN7583_MDC_0_PD_MASK			BIT(4)
>> -#define UART1_RXD_PD_MASK			BIT(3)
>> -#define UART1_TXD_PD_MASK			BIT(2)
>> -#define I2C_SCL_PD_MASK				BIT(1)
>> -#define I2C_SDA_PD_MASK				BIT(0)
>> -
>> -#define REG_GPIO_L_PU				0x004c
>> -#define REG_GPIO_L_PD				0x0050
>> -#define REG_GPIO_H_PU				0x0054
>> -#define REG_GPIO_H_PD				0x0058
>> -
>> -#define REG_PCIE_RESET_OD			0x018c
>> -#define PCIE2_RESET_OD_MASK			BIT(2)
>> -#define PCIE1_RESET_OD_MASK			BIT(1)
>> -#define PCIE0_RESET_OD_MASK			BIT(0)
>> -
>> -/* GPIOs */
>> -#define REG_GPIO_CTRL				0x0000
>> -#define REG_GPIO_DATA				0x0004
>> -#define REG_GPIO_INT				0x0008
>> -#define REG_GPIO_INT_EDGE			0x000c
>> -#define REG_GPIO_INT_LEVEL			0x0010
>> -#define REG_GPIO_OE				0x0014
>> -#define REG_GPIO_CTRL1				0x0020
>> -#define REG_GPIO_CTRL2				0x0060
>> -#define REG_GPIO_CTRL3				0x0064
>> -
>> -/* PWM MODE CONF */
>> -#define REG_GPIO_FLASH_MODE_CFG			0x0034
>> -#define GPIO15_FLASH_MODE_CFG			BIT(15)
>> -#define GPIO14_FLASH_MODE_CFG			BIT(14)
>> -#define GPIO13_FLASH_MODE_CFG			BIT(13)
>> -#define GPIO12_FLASH_MODE_CFG			BIT(12)
>> -#define GPIO11_FLASH_MODE_CFG			BIT(11)
>> -#define GPIO10_FLASH_MODE_CFG			BIT(10)
>> -#define GPIO9_FLASH_MODE_CFG			BIT(9)
>> -#define GPIO8_FLASH_MODE_CFG			BIT(8)
>> -#define GPIO7_FLASH_MODE_CFG			BIT(7)
>> -#define GPIO6_FLASH_MODE_CFG			BIT(6)
>> -#define GPIO5_FLASH_MODE_CFG			BIT(5)
>> -#define GPIO4_FLASH_MODE_CFG			BIT(4)
>> -#define GPIO3_FLASH_MODE_CFG			BIT(3)
>> -#define GPIO2_FLASH_MODE_CFG			BIT(2)
>> -#define GPIO1_FLASH_MODE_CFG			BIT(1)
>> -#define GPIO0_FLASH_MODE_CFG			BIT(0)
>> -
>> -/* PWM MODE CONF EXT */
>> -#define REG_GPIO_FLASH_MODE_CFG_EXT		0x0068
>> -#define GPIO51_FLASH_MODE_CFG			BIT(31)
>> -#define GPIO50_FLASH_MODE_CFG			BIT(30)
>> -#define GPIO49_FLASH_MODE_CFG			BIT(29)
>> -#define GPIO48_FLASH_MODE_CFG			BIT(28)
>> -#define GPIO47_FLASH_MODE_CFG			BIT(27)
>> -#define GPIO46_FLASH_MODE_CFG			BIT(26)
>> -#define GPIO45_FLASH_MODE_CFG			BIT(25)
>> -#define GPIO44_FLASH_MODE_CFG			BIT(24)
>> -#define GPIO43_FLASH_MODE_CFG			BIT(23)
>> -#define GPIO42_FLASH_MODE_CFG			BIT(22)
>> -#define GPIO41_FLASH_MODE_CFG			BIT(21)
>> -#define GPIO40_FLASH_MODE_CFG			BIT(20)
>> -#define GPIO39_FLASH_MODE_CFG			BIT(19)
>> -#define GPIO38_FLASH_MODE_CFG			BIT(18)
>> -#define GPIO37_FLASH_MODE_CFG			BIT(17)
>> -#define GPIO36_FLASH_MODE_CFG			BIT(16)
>> -#define GPIO31_FLASH_MODE_CFG			BIT(15)
>> -#define GPIO30_FLASH_MODE_CFG			BIT(14)
>> -#define GPIO29_FLASH_MODE_CFG			BIT(13)
>> -#define GPIO28_FLASH_MODE_CFG			BIT(12)
>> -#define GPIO27_FLASH_MODE_CFG			BIT(11)
>> -#define GPIO26_FLASH_MODE_CFG			BIT(10)
>> -#define GPIO25_FLASH_MODE_CFG			BIT(9)
>> -#define GPIO24_FLASH_MODE_CFG			BIT(8)
>> -#define GPIO23_FLASH_MODE_CFG			BIT(7)
>> -#define GPIO22_FLASH_MODE_CFG			BIT(6)
>> -#define GPIO21_FLASH_MODE_CFG			BIT(5)
>> -#define GPIO20_FLASH_MODE_CFG			BIT(4)
>> -#define GPIO19_FLASH_MODE_CFG			BIT(3)
>> -#define GPIO18_FLASH_MODE_CFG			BIT(2)
>> -#define GPIO17_FLASH_MODE_CFG			BIT(1)
>> -#define GPIO16_FLASH_MODE_CFG			BIT(0)
>> -
>> -#define REG_GPIO_DATA1				0x0070
>> -#define REG_GPIO_OE1				0x0078
>> -#define REG_GPIO_INT1				0x007c
>> -#define REG_GPIO_INT_EDGE1			0x0080
>> -#define REG_GPIO_INT_EDGE2			0x0084
>> -#define REG_GPIO_INT_EDGE3			0x0088
>> -#define REG_GPIO_INT_LEVEL1			0x008c
>> -#define REG_GPIO_INT_LEVEL2			0x0090
>> -#define REG_GPIO_INT_LEVEL3			0x0094
>> -
>> -#define AIROHA_PINCTRL_GPIO(gpio, mux_val)			\
>> -	{							\
>> -		.name = (gpio),					\
>> -		.regmap[0] = {					\
>> -			AIROHA_FUNC_MUX,			\
>> -			REG_GPIO_PON_MODE,			\
>> -			(mux_val),				\
>> -			(mux_val)				\
>> -		},						\
>> -		.regmap_size = 1,				\
>> -	}
>> -
>> -#define AIROHA_PINCTRL_GPIO_EXT(gpio, mux_val, smux_val)	\
>> -	{							\
>> -		.name = (gpio),					\
>> -		.regmap[0] = {					\
>> -			AIROHA_FUNC_PWM_EXT_MUX,		\
>> -			REG_GPIO_FLASH_MODE_CFG_EXT,		\
>> -			(mux_val),				\
>> -			0					\
>> -		},						\
>> -		.regmap[1] = {					\
>> -			AIROHA_FUNC_MUX,			\
>> -			REG_GPIO_PON_MODE,			\
>> -			(smux_val),				\
>> -			(smux_val)				\
>> -		},						\
>> -		.regmap_size = 2,				\
>> -	}
>> -
>> -/* PWM */
>> -#define AIROHA_PINCTRL_PWM(gpio, mux_val)		\
>> -	{						\
>> -		.name = (gpio),				\
>> -		.regmap[0] = {				\
>> -			AIROHA_FUNC_PWM_MUX,		\
>> -			REG_GPIO_FLASH_MODE_CFG,	\
>> -			(mux_val),			\
>> -			(mux_val)			\
>> -		},					\
>> -		.regmap_size = 1,			\
>> -	}
>> -
>> -#define AIROHA_PINCTRL_PWM_EXT(gpio, mux_val)		\
>> -	{						\
>> -		.name = (gpio),				\
>> -		.regmap[0] = {				\
>> -			AIROHA_FUNC_PWM_EXT_MUX,	\
>> -			REG_GPIO_FLASH_MODE_CFG_EXT,	\
>> -			(mux_val),			\
>> -			(mux_val)			\
>> -		},					\
>> -		.regmap_size = 1,			\
>> -	}
>> -
>> -#define AIROHA_PINCTRL_PWM_EXT_SEC(gpio, mux_val, smux_val)	\
>> -	{							\
>> -		.name = (gpio),					\
>> -		.regmap[0] = {					\
>> -			AIROHA_FUNC_PWM_EXT_MUX,		\
>> -			REG_GPIO_FLASH_MODE_CFG_EXT,		\
>> -			(mux_val),				\
>> -			(mux_val)				\
>> -		},						\
>> -		.regmap[1] = {					\
>> -			AIROHA_FUNC_MUX,			\
>> -			REG_GPIO_PON_MODE,			\
>> -			(smux_val),				\
>> -			(smux_val)				\
>> -		},						\
>> -		.regmap_size = 2,				\
>> -	}
>> -
>> -#define AIROHA_PINCTRL_PHY_LED0(gpio, mux_val, map_mask, map_val)	\
>> -	{								\
>> -		.name = (gpio),						\
>> -		.regmap[0] = {						\
>> -			AIROHA_FUNC_MUX,				\
>> -			REG_GPIO_2ND_I2C_MODE,				\
>> -			(mux_val),					\
>> -			(mux_val),					\
>> -		},							\
>> -		.regmap[1] = {						\
>> -			AIROHA_FUNC_MUX,				\
>> -			REG_LAN_LED0_MAPPING,				\
>> -			(map_mask),					\
>> -			(map_val),					\
>> -		},							\
>> -		.regmap_size = 2,					\
>> -	}
>> -
>> -#define AIROHA_PINCTRL_PHY_LED1(gpio, mux_val, map_mask, map_val)	\
>> -	{								\
>> -		.name = (gpio),						\
>> -		.regmap[0] = {						\
>> -			AIROHA_FUNC_MUX,				\
>> -			REG_GPIO_2ND_I2C_MODE,				\
>> -			(mux_val),					\
>> -			(mux_val),					\
>> -		},							\
>> -		.regmap[1] = {						\
>> -			AIROHA_FUNC_MUX,				\
>> -			REG_LAN_LED1_MAPPING,				\
>> -			(map_mask),					\
>> -			(map_val),					\
>> -		},							\
>> -		.regmap_size = 2,					\
>> -	}
>> -
>>  #define airoha_pinctrl_get_pullup_conf(pinctrl, pin, val)			\
>>  	airoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_PULLUP,		\
>>  				(pin), (val))
>> @@ -433,1935 +74,6 @@ static const u32 irq_edge_regs[] = {
>>  	REG_GPIO_INT_EDGE3
>>  };
>>  
>> -static struct pinctrl_pin_desc en7581_pinctrl_pins[] = {
>> -	PINCTRL_PIN(0, "uart1_txd"),
>> -	PINCTRL_PIN(1, "uart1_rxd"),
>> -	PINCTRL_PIN(2, "i2c_scl"),
>> -	PINCTRL_PIN(3, "i2c_sda"),
>> -	PINCTRL_PIN(4, "spi_cs0"),
>> -	PINCTRL_PIN(5, "spi_clk"),
>> -	PINCTRL_PIN(6, "spi_mosi"),
>> -	PINCTRL_PIN(7, "spi_miso"),
>> -	PINCTRL_PIN(13, "gpio0"),
>> -	PINCTRL_PIN(14, "gpio1"),
>> -	PINCTRL_PIN(15, "gpio2"),
>> -	PINCTRL_PIN(16, "gpio3"),
>> -	PINCTRL_PIN(17, "gpio4"),
>> -	PINCTRL_PIN(18, "gpio5"),
>> -	PINCTRL_PIN(19, "gpio6"),
>> -	PINCTRL_PIN(20, "gpio7"),
>> -	PINCTRL_PIN(21, "gpio8"),
>> -	PINCTRL_PIN(22, "gpio9"),
>> -	PINCTRL_PIN(23, "gpio10"),
>> -	PINCTRL_PIN(24, "gpio11"),
>> -	PINCTRL_PIN(25, "gpio12"),
>> -	PINCTRL_PIN(26, "gpio13"),
>> -	PINCTRL_PIN(27, "gpio14"),
>> -	PINCTRL_PIN(28, "gpio15"),
>> -	PINCTRL_PIN(29, "gpio16"),
>> -	PINCTRL_PIN(30, "gpio17"),
>> -	PINCTRL_PIN(31, "gpio18"),
>> -	PINCTRL_PIN(32, "gpio19"),
>> -	PINCTRL_PIN(33, "gpio20"),
>> -	PINCTRL_PIN(34, "gpio21"),
>> -	PINCTRL_PIN(35, "gpio22"),
>> -	PINCTRL_PIN(36, "gpio23"),
>> -	PINCTRL_PIN(37, "gpio24"),
>> -	PINCTRL_PIN(38, "gpio25"),
>> -	PINCTRL_PIN(39, "gpio26"),
>> -	PINCTRL_PIN(40, "gpio27"),
>> -	PINCTRL_PIN(41, "gpio28"),
>> -	PINCTRL_PIN(42, "gpio29"),
>> -	PINCTRL_PIN(43, "gpio30"),
>> -	PINCTRL_PIN(44, "gpio31"),
>> -	PINCTRL_PIN(45, "gpio32"),
>> -	PINCTRL_PIN(46, "gpio33"),
>> -	PINCTRL_PIN(47, "gpio34"),
>> -	PINCTRL_PIN(48, "gpio35"),
>> -	PINCTRL_PIN(49, "gpio36"),
>> -	PINCTRL_PIN(50, "gpio37"),
>> -	PINCTRL_PIN(51, "gpio38"),
>> -	PINCTRL_PIN(52, "gpio39"),
>> -	PINCTRL_PIN(53, "gpio40"),
>> -	PINCTRL_PIN(54, "gpio41"),
>> -	PINCTRL_PIN(55, "gpio42"),
>> -	PINCTRL_PIN(56, "gpio43"),
>> -	PINCTRL_PIN(57, "gpio44"),
>> -	PINCTRL_PIN(58, "gpio45"),
>> -	PINCTRL_PIN(59, "gpio46"),
>> -	PINCTRL_PIN(60, "pcie_reset0"),
>> -	PINCTRL_PIN(61, "pcie_reset1"),
>> -	PINCTRL_PIN(62, "pcie_reset2"),
>> -};
>> -
>> -static const int en7581_pon_pins[] = { 49, 50, 51, 52, 53, 54 };
>> -static const int en7581_pon_tod_1pps_pins[] = { 46 };
>> -static const int en7581_gsw_tod_1pps_pins[] = { 46 };
>> -static const int en7581_sipo_pins[] = { 16, 17 };
>> -static const int en7581_sipo_rclk_pins[] = { 16, 17, 43 };
>> -static const int en7581_mdio_pins[] = { 14, 15 };
>> -static const int en7581_uart2_pins[] = { 48, 55 };
>> -static const int en7581_uart2_cts_rts_pins[] = { 46, 47 };
>> -static const int en7581_hsuart_pins[] = { 28, 29 };
>> -static const int en7581_hsuart_cts_rts_pins[] = { 26, 27 };
>> -static const int en7581_uart4_pins[] = { 38, 39 };
>> -static const int en7581_uart5_pins[] = { 18, 19 };
>> -static const int en7581_i2c0_pins[] = { 2, 3 };
>> -static const int en7581_i2c1_pins[] = { 14, 15 };
>> -static const int en7581_jtag_udi_pins[] = { 16, 17, 18, 19, 20 };
>> -static const int en7581_jtag_dfd_pins[] = { 16, 17, 18, 19, 20 };
>> -static const int en7581_i2s_pins[] = { 26, 27, 28, 29 };
>> -static const int en7581_pcm1_pins[] = { 22, 23, 24, 25 };
>> -static const int en7581_pcm2_pins[] = { 18, 19, 20, 21 };
>> -static const int en7581_spi_quad_pins[] = { 32, 33 };
>> -static const int en7581_spi_pins[] = { 4, 5, 6, 7 };
>> -static const int en7581_spi_cs1_pins[] = { 34 };
>> -static const int en7581_pcm_spi_pins[] = { 18, 19, 20, 21, 22, 23, 24, 25 };
>> -static const int en7581_pcm_spi_int_pins[] = { 14 };
>> -static const int en7581_pcm_spi_rst_pins[] = { 15 };
>> -static const int en7581_pcm_spi_cs1_pins[] = { 43 };
>> -static const int en7581_pcm_spi_cs2_pins[] = { 40 };
>> -static const int en7581_pcm_spi_cs2_p128_pins[] = { 40 };
>> -static const int en7581_pcm_spi_cs2_p156_pins[] = { 40 };
>> -static const int en7581_pcm_spi_cs3_pins[] = { 41 };
>> -static const int en7581_pcm_spi_cs4_pins[] = { 42 };
>> -static const int en7581_emmc_pins[] = { 4, 5, 6, 30, 31, 32, 33, 34, 35, 36, 37 };
>> -static const int en7581_pnand_pins[] = { 4, 5, 6, 7, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42 };
>> -static const int en7581_gpio0_pins[] = { 13 };
>> -static const int en7581_gpio1_pins[] = { 14 };
>> -static const int en7581_gpio2_pins[] = { 15 };
>> -static const int en7581_gpio3_pins[] = { 16 };
>> -static const int en7581_gpio4_pins[] = { 17 };
>> -static const int en7581_gpio5_pins[] = { 18 };
>> -static const int en7581_gpio6_pins[] = { 19 };
>> -static const int en7581_gpio7_pins[] = { 20 };
>> -static const int en7581_gpio8_pins[] = { 21 };
>> -static const int en7581_gpio9_pins[] = { 22 };
>> -static const int en7581_gpio10_pins[] = { 23 };
>> -static const int en7581_gpio11_pins[] = { 24 };
>> -static const int en7581_gpio12_pins[] = { 25 };
>> -static const int en7581_gpio13_pins[] = { 26 };
>> -static const int en7581_gpio14_pins[] = { 27 };
>> -static const int en7581_gpio15_pins[] = { 28 };
>> -static const int en7581_gpio16_pins[] = { 29 };
>> -static const int en7581_gpio17_pins[] = { 30 };
>> -static const int en7581_gpio18_pins[] = { 31 };
>> -static const int en7581_gpio19_pins[] = { 32 };
>> -static const int en7581_gpio20_pins[] = { 33 };
>> -static const int en7581_gpio21_pins[] = { 34 };
>> -static const int en7581_gpio22_pins[] = { 35 };
>> -static const int en7581_gpio23_pins[] = { 36 };
>> -static const int en7581_gpio24_pins[] = { 37 };
>> -static const int en7581_gpio25_pins[] = { 38 };
>> -static const int en7581_gpio26_pins[] = { 39 };
>> -static const int en7581_gpio27_pins[] = { 40 };
>> -static const int en7581_gpio28_pins[] = { 41 };
>> -static const int en7581_gpio29_pins[] = { 42 };
>> -static const int en7581_gpio30_pins[] = { 43 };
>> -static const int en7581_gpio31_pins[] = { 44 };
>> -static const int en7581_gpio32_pins[] = { 45 };
>> -static const int en7581_gpio33_pins[] = { 46 };
>> -static const int en7581_gpio34_pins[] = { 47 };
>> -static const int en7581_gpio35_pins[] = { 48 };
>> -static const int en7581_gpio36_pins[] = { 49 };
>> -static const int en7581_gpio37_pins[] = { 50 };
>> -static const int en7581_gpio38_pins[] = { 51 };
>> -static const int en7581_gpio39_pins[] = { 52 };
>> -static const int en7581_gpio40_pins[] = { 53 };
>> -static const int en7581_gpio41_pins[] = { 54 };
>> -static const int en7581_gpio42_pins[] = { 55 };
>> -static const int en7581_gpio43_pins[] = { 56 };
>> -static const int en7581_gpio44_pins[] = { 57 };
>> -static const int en7581_gpio45_pins[] = { 58 };
>> -static const int en7581_gpio46_pins[] = { 59 };
>> -static const int en7581_gpio47_pins[] = { 60 };
>> -static const int en7581_gpio48_pins[] = { 61 };
>> -static const int en7581_gpio49_pins[] = { 62 };
>> -static const int en7581_pcie_reset0_pins[] = { 60 };
>> -static const int en7581_pcie_reset1_pins[] = { 61 };
>> -static const int en7581_pcie_reset2_pins[] = { 62 };
>> -
>> -static const struct pingroup en7581_pinctrl_groups[] = {
>> -	PINCTRL_PIN_GROUP("pon", en7581_pon),
>> -	PINCTRL_PIN_GROUP("pon_tod_1pps", en7581_pon_tod_1pps),
>> -	PINCTRL_PIN_GROUP("gsw_tod_1pps", en7581_gsw_tod_1pps),
>> -	PINCTRL_PIN_GROUP("sipo", en7581_sipo),
>> -	PINCTRL_PIN_GROUP("sipo_rclk", en7581_sipo_rclk),
>> -	PINCTRL_PIN_GROUP("mdio", en7581_mdio),
>> -	PINCTRL_PIN_GROUP("uart2", en7581_uart2),
>> -	PINCTRL_PIN_GROUP("uart2_cts_rts", en7581_uart2_cts_rts),
>> -	PINCTRL_PIN_GROUP("hsuart", en7581_hsuart),
>> -	PINCTRL_PIN_GROUP("hsuart_cts_rts", en7581_hsuart_cts_rts),
>> -	PINCTRL_PIN_GROUP("uart4", en7581_uart4),
>> -	PINCTRL_PIN_GROUP("uart5", en7581_uart5),
>> -	PINCTRL_PIN_GROUP("i2c0", en7581_i2c0),
>> -	PINCTRL_PIN_GROUP("i2c1", en7581_i2c1),
>> -	PINCTRL_PIN_GROUP("jtag_udi", en7581_jtag_udi),
>> -	PINCTRL_PIN_GROUP("jtag_dfd", en7581_jtag_dfd),
>> -	PINCTRL_PIN_GROUP("i2s", en7581_i2s),
>> -	PINCTRL_PIN_GROUP("pcm1", en7581_pcm1),
>> -	PINCTRL_PIN_GROUP("pcm2", en7581_pcm2),
>> -	PINCTRL_PIN_GROUP("spi", en7581_spi),
>> -	PINCTRL_PIN_GROUP("spi_quad", en7581_spi_quad),
>> -	PINCTRL_PIN_GROUP("spi_cs1", en7581_spi_cs1),
>> -	PINCTRL_PIN_GROUP("pcm_spi", en7581_pcm_spi),
>> -	PINCTRL_PIN_GROUP("pcm_spi_int", en7581_pcm_spi_int),
>> -	PINCTRL_PIN_GROUP("pcm_spi_rst", en7581_pcm_spi_rst),
>> -	PINCTRL_PIN_GROUP("pcm_spi_cs1", en7581_pcm_spi_cs1),
>> -	PINCTRL_PIN_GROUP("pcm_spi_cs2_p128", en7581_pcm_spi_cs2_p128),
>> -	PINCTRL_PIN_GROUP("pcm_spi_cs2_p156", en7581_pcm_spi_cs2_p156),
>> -	PINCTRL_PIN_GROUP("pcm_spi_cs2", en7581_pcm_spi_cs2),
>> -	PINCTRL_PIN_GROUP("pcm_spi_cs3", en7581_pcm_spi_cs3),
>> -	PINCTRL_PIN_GROUP("pcm_spi_cs4", en7581_pcm_spi_cs4),
>> -	PINCTRL_PIN_GROUP("emmc", en7581_emmc),
>> -	PINCTRL_PIN_GROUP("pnand", en7581_pnand),
>> -	PINCTRL_PIN_GROUP("gpio0", en7581_gpio0),
>> -	PINCTRL_PIN_GROUP("gpio1", en7581_gpio1),
>> -	PINCTRL_PIN_GROUP("gpio2", en7581_gpio2),
>> -	PINCTRL_PIN_GROUP("gpio3", en7581_gpio3),
>> -	PINCTRL_PIN_GROUP("gpio4", en7581_gpio4),
>> -	PINCTRL_PIN_GROUP("gpio5", en7581_gpio5),
>> -	PINCTRL_PIN_GROUP("gpio6", en7581_gpio6),
>> -	PINCTRL_PIN_GROUP("gpio7", en7581_gpio7),
>> -	PINCTRL_PIN_GROUP("gpio8", en7581_gpio8),
>> -	PINCTRL_PIN_GROUP("gpio9", en7581_gpio9),
>> -	PINCTRL_PIN_GROUP("gpio10", en7581_gpio10),
>> -	PINCTRL_PIN_GROUP("gpio11", en7581_gpio11),
>> -	PINCTRL_PIN_GROUP("gpio12", en7581_gpio12),
>> -	PINCTRL_PIN_GROUP("gpio13", en7581_gpio13),
>> -	PINCTRL_PIN_GROUP("gpio14", en7581_gpio14),
>> -	PINCTRL_PIN_GROUP("gpio15", en7581_gpio15),
>> -	PINCTRL_PIN_GROUP("gpio16", en7581_gpio16),
>> -	PINCTRL_PIN_GROUP("gpio17", en7581_gpio17),
>> -	PINCTRL_PIN_GROUP("gpio18", en7581_gpio18),
>> -	PINCTRL_PIN_GROUP("gpio19", en7581_gpio19),
>> -	PINCTRL_PIN_GROUP("gpio20", en7581_gpio20),
>> -	PINCTRL_PIN_GROUP("gpio21", en7581_gpio21),
>> -	PINCTRL_PIN_GROUP("gpio22", en7581_gpio22),
>> -	PINCTRL_PIN_GROUP("gpio23", en7581_gpio23),
>> -	PINCTRL_PIN_GROUP("gpio24", en7581_gpio24),
>> -	PINCTRL_PIN_GROUP("gpio25", en7581_gpio25),
>> -	PINCTRL_PIN_GROUP("gpio26", en7581_gpio26),
>> -	PINCTRL_PIN_GROUP("gpio27", en7581_gpio27),
>> -	PINCTRL_PIN_GROUP("gpio28", en7581_gpio28),
>> -	PINCTRL_PIN_GROUP("gpio29", en7581_gpio29),
>> -	PINCTRL_PIN_GROUP("gpio30", en7581_gpio30),
>> -	PINCTRL_PIN_GROUP("gpio31", en7581_gpio31),
>> -	PINCTRL_PIN_GROUP("gpio32", en7581_gpio32),
>> -	PINCTRL_PIN_GROUP("gpio33", en7581_gpio33),
>> -	PINCTRL_PIN_GROUP("gpio34", en7581_gpio34),
>> -	PINCTRL_PIN_GROUP("gpio35", en7581_gpio35),
>> -	PINCTRL_PIN_GROUP("gpio36", en7581_gpio36),
>> -	PINCTRL_PIN_GROUP("gpio37", en7581_gpio37),
>> -	PINCTRL_PIN_GROUP("gpio38", en7581_gpio38),
>> -	PINCTRL_PIN_GROUP("gpio39", en7581_gpio39),
>> -	PINCTRL_PIN_GROUP("gpio40", en7581_gpio40),
>> -	PINCTRL_PIN_GROUP("gpio41", en7581_gpio41),
>> -	PINCTRL_PIN_GROUP("gpio42", en7581_gpio42),
>> -	PINCTRL_PIN_GROUP("gpio43", en7581_gpio43),
>> -	PINCTRL_PIN_GROUP("gpio44", en7581_gpio44),
>> -	PINCTRL_PIN_GROUP("gpio45", en7581_gpio45),
>> -	PINCTRL_PIN_GROUP("gpio46", en7581_gpio46),
>> -	PINCTRL_PIN_GROUP("gpio47", en7581_gpio47),
>> -	PINCTRL_PIN_GROUP("gpio48", en7581_gpio48),
>> -	PINCTRL_PIN_GROUP("gpio49", en7581_gpio49),
>> -	PINCTRL_PIN_GROUP("pcie_reset0", en7581_pcie_reset0),
>> -	PINCTRL_PIN_GROUP("pcie_reset1", en7581_pcie_reset1),
>> -	PINCTRL_PIN_GROUP("pcie_reset2", en7581_pcie_reset2),
>> -};
>> -
>> -static struct pinctrl_pin_desc an7583_pinctrl_pins[] = {
>> -	PINCTRL_PIN(2, "gpio0"),
>> -	PINCTRL_PIN(3, "gpio1"),
>> -	PINCTRL_PIN(4, "gpio2"),
>> -	PINCTRL_PIN(5, "gpio3"),
>> -	PINCTRL_PIN(6, "gpio4"),
>> -	PINCTRL_PIN(7, "gpio5"),
>> -	PINCTRL_PIN(8, "gpio6"),
>> -	PINCTRL_PIN(9, "gpio7"),
>> -	PINCTRL_PIN(10, "gpio8"),
>> -	PINCTRL_PIN(11, "gpio9"),
>> -	PINCTRL_PIN(12, "gpio10"),
>> -	PINCTRL_PIN(13, "gpio11"),
>> -	PINCTRL_PIN(14, "gpio12"),
>> -	PINCTRL_PIN(15, "gpio13"),
>> -	PINCTRL_PIN(16, "gpio14"),
>> -	PINCTRL_PIN(17, "gpio15"),
>> -	PINCTRL_PIN(18, "gpio16"),
>> -	PINCTRL_PIN(19, "gpio17"),
>> -	PINCTRL_PIN(20, "gpio18"),
>> -	PINCTRL_PIN(21, "gpio19"),
>> -	PINCTRL_PIN(22, "gpio20"),
>> -	PINCTRL_PIN(23, "gpio21"),
>> -	PINCTRL_PIN(24, "gpio22"),
>> -	PINCTRL_PIN(25, "gpio23"),
>> -	PINCTRL_PIN(26, "gpio24"),
>> -	PINCTRL_PIN(27, "gpio25"),
>> -	PINCTRL_PIN(28, "gpio26"),
>> -	PINCTRL_PIN(29, "gpio27"),
>> -	PINCTRL_PIN(30, "gpio28"),
>> -	PINCTRL_PIN(31, "gpio29"),
>> -	PINCTRL_PIN(32, "gpio30"),
>> -	PINCTRL_PIN(33, "gpio31"),
>> -	PINCTRL_PIN(34, "gpio32"),
>> -	PINCTRL_PIN(35, "gpio33"),
>> -	PINCTRL_PIN(36, "gpio34"),
>> -	PINCTRL_PIN(37, "gpio35"),
>> -	PINCTRL_PIN(38, "gpio36"),
>> -	PINCTRL_PIN(39, "gpio37"),
>> -	PINCTRL_PIN(40, "gpio38"),
>> -	PINCTRL_PIN(41, "i2c0_scl"),
>> -	PINCTRL_PIN(42, "i2c0_sda"),
>> -	PINCTRL_PIN(43, "i2c1_scl"),
>> -	PINCTRL_PIN(44, "i2c1_sda"),
>> -	PINCTRL_PIN(45, "spi_clk"),
>> -	PINCTRL_PIN(46, "spi_cs"),
>> -	PINCTRL_PIN(47, "spi_mosi"),
>> -	PINCTRL_PIN(48, "spi_miso"),
>> -	PINCTRL_PIN(49, "uart_txd"),
>> -	PINCTRL_PIN(50, "uart_rxd"),
>> -	PINCTRL_PIN(51, "pcie_reset0"),
>> -	PINCTRL_PIN(52, "pcie_reset1"),
>> -	PINCTRL_PIN(53, "mdc_0"),
>> -	PINCTRL_PIN(54, "mdio_0"),
>> -};
>> -
>> -static const int an7583_pon_pins[] = { 15, 16, 17, 18, 19, 20 };
>> -static const int an7583_pon_tod_1pps_pins[] = { 32 };
>> -static const int an7583_gsw_tod_1pps_pins[] = { 32 };
>> -static const int an7583_sipo_pins[] = { 34, 35 };
>> -static const int an7583_sipo_rclk_pins[] = { 34, 35, 33 };
>> -static const int an7583_mdio_pins[] = { 43, 44 };
>> -static const int an7583_uart2_pins[] = { 34, 35 };
>> -static const int an7583_uart2_cts_rts_pins[] = { 32, 33 };
>> -static const int an7583_hsuart_pins[] = { 30, 31 };
>> -static const int an7583_hsuart_cts_rts_pins[] = { 28, 29 };
>> -static const int an7583_npu_uart_pins[] = { 7, 8 };
>> -static const int an7583_uart4_pins[] = { 7, 8 };
>> -static const int an7583_uart5_pins[] = { 23, 24 };
>> -static const int an7583_i2c0_pins[] = { 41, 42 };
>> -static const int an7583_i2c1_pins[] = { 43, 44 };
>> -static const int an7583_jtag_udi_pins[] = { 23, 24, 22, 25, 26 };
>> -static const int an7583_jtag_dfd_pins[] = { 23, 24, 22, 25, 26 };
>> -static const int an7583_pcm1_pins[] = { 10, 11, 12, 13, 14 };
>> -static const int an7583_pcm2_pins[] = { 28, 29, 30, 31, 24 };
>> -static const int an7583_spi_pins[] = { 28, 29, 30, 31 };
>> -static const int an7583_spi_quad_pins[] = { 25, 26 };
>> -static const int an7583_spi_cs1_pins[] = { 27 };
>> -static const int an7583_pcm_spi_pins[] = { 28, 29, 30, 31, 10, 11, 12, 13 };
>> -static const int an7583_pcm_spi_rst_pins[] = { 14 };
>> -static const int an7583_pcm_spi_cs1_pins[] = { 24 };
>> -static const int an7583_emmc_pins[] = { 7, 8, 9, 22, 23, 24, 25, 26, 45, 46, 47 };
>> -static const int an7583_pnand_pins[] = { 7, 8, 9, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 45, 46, 47, 48 };
>> -static const int an7583_gpio0_pins[] = { 2 };
>> -static const int an7583_gpio1_pins[] = { 3 };
>> -static const int an7583_gpio2_pins[] = { 4 };
>> -static const int an7583_gpio3_pins[] = { 5 };
>> -static const int an7583_gpio4_pins[] = { 6 };
>> -static const int an7583_gpio5_pins[] = { 7 };
>> -static const int an7583_gpio6_pins[] = { 8 };
>> -static const int an7583_gpio7_pins[] = { 9 };
>> -static const int an7583_gpio8_pins[] = { 10 };
>> -static const int an7583_gpio9_pins[] = { 11 };
>> -static const int an7583_gpio10_pins[] = { 12 };
>> -static const int an7583_gpio11_pins[] = { 13 };
>> -static const int an7583_gpio12_pins[] = { 14 };
>> -static const int an7583_gpio13_pins[] = { 15 };
>> -static const int an7583_gpio14_pins[] = { 16 };
>> -static const int an7583_gpio15_pins[] = { 17 };
>> -static const int an7583_gpio16_pins[] = { 18 };
>> -static const int an7583_gpio17_pins[] = { 19 };
>> -static const int an7583_gpio18_pins[] = { 20 };
>> -static const int an7583_gpio19_pins[] = { 21 };
>> -static const int an7583_gpio20_pins[] = { 22 };
>> -static const int an7583_gpio21_pins[] = { 23 };
>> -static const int an7583_gpio22_pins[] = { 24 };
>> -static const int an7583_gpio23_pins[] = { 25 };
>> -static const int an7583_gpio24_pins[] = { 26 };
>> -static const int an7583_gpio25_pins[] = { 27 };
>> -static const int an7583_gpio26_pins[] = { 28 };
>> -static const int an7583_gpio27_pins[] = { 29 };
>> -static const int an7583_gpio28_pins[] = { 30 };
>> -static const int an7583_gpio29_pins[] = { 31 };
>> -static const int an7583_gpio30_pins[] = { 32 };
>> -static const int an7583_gpio31_pins[] = { 33 };
>> -static const int an7583_gpio32_pins[] = { 34 };
>> -static const int an7583_gpio33_pins[] = { 35 };
>> -static const int an7583_gpio34_pins[] = { 36 };
>> -static const int an7583_gpio35_pins[] = { 37 };
>> -static const int an7583_gpio36_pins[] = { 38 };
>> -static const int an7583_gpio37_pins[] = { 39 };
>> -static const int an7583_gpio38_pins[] = { 40 };
>> -static const int an7583_gpio39_pins[] = { 41 };
>> -static const int an7583_gpio40_pins[] = { 42 };
>> -static const int an7583_gpio41_pins[] = { 43 };
>> -static const int an7583_gpio42_pins[] = { 44 };
>> -static const int an7583_gpio43_pins[] = { 45 };
>> -static const int an7583_gpio44_pins[] = { 46 };
>> -static const int an7583_gpio45_pins[] = { 47 };
>> -static const int an7583_gpio46_pins[] = { 48 };
>> -static const int an7583_gpio47_pins[] = { 49 };
>> -static const int an7583_gpio48_pins[] = { 50 };
>> -static const int an7583_gpio49_pins[] = { 51 };
>> -static const int an7583_gpio50_pins[] = { 52 };
>> -static const int an7583_gpio51_pins[] = { 53 };
>> -static const int an7583_gpio52_pins[] = { 54 };
>> -static const int an7583_pcie_reset0_pins[] = { 51 };
>> -static const int an7583_pcie_reset1_pins[] = { 52 };
>> -
>> -static const struct pingroup an7583_pinctrl_groups[] = {
>> -	PINCTRL_PIN_GROUP("pon", an7583_pon),
>> -	PINCTRL_PIN_GROUP("pon_tod_1pps", an7583_pon_tod_1pps),
>> -	PINCTRL_PIN_GROUP("gsw_tod_1pps", an7583_gsw_tod_1pps),
>> -	PINCTRL_PIN_GROUP("sipo", an7583_sipo),
>> -	PINCTRL_PIN_GROUP("sipo_rclk", an7583_sipo_rclk),
>> -	PINCTRL_PIN_GROUP("mdio", an7583_mdio),
>> -	PINCTRL_PIN_GROUP("uart2", an7583_uart2),
>> -	PINCTRL_PIN_GROUP("uart2_cts_rts", an7583_uart2_cts_rts),
>> -	PINCTRL_PIN_GROUP("hsuart", an7583_hsuart),
>> -	PINCTRL_PIN_GROUP("hsuart_cts_rts", an7583_hsuart_cts_rts),
>> -	PINCTRL_PIN_GROUP("npu_uart", an7583_npu_uart),
>> -	PINCTRL_PIN_GROUP("uart4", an7583_uart4),
>> -	PINCTRL_PIN_GROUP("uart5", an7583_uart5),
>> -	PINCTRL_PIN_GROUP("i2c0", an7583_i2c0),
>> -	PINCTRL_PIN_GROUP("i2c1", an7583_i2c1),
>> -	PINCTRL_PIN_GROUP("jtag_udi", an7583_jtag_udi),
>> -	PINCTRL_PIN_GROUP("jtag_dfd", an7583_jtag_dfd),
>> -	PINCTRL_PIN_GROUP("pcm1", an7583_pcm1),
>> -	PINCTRL_PIN_GROUP("pcm2", an7583_pcm2),
>> -	PINCTRL_PIN_GROUP("spi", an7583_spi),
>> -	PINCTRL_PIN_GROUP("spi_quad", an7583_spi_quad),
>> -	PINCTRL_PIN_GROUP("spi_cs1", an7583_spi_cs1),
>> -	PINCTRL_PIN_GROUP("pcm_spi", an7583_pcm_spi),
>> -	PINCTRL_PIN_GROUP("pcm_spi_rst", an7583_pcm_spi_rst),
>> -	PINCTRL_PIN_GROUP("pcm_spi_cs1", an7583_pcm_spi_cs1),
>> -	PINCTRL_PIN_GROUP("emmc", an7583_emmc),
>> -	PINCTRL_PIN_GROUP("pnand", an7583_pnand),
>> -	PINCTRL_PIN_GROUP("gpio0", an7583_gpio0),
>> -	PINCTRL_PIN_GROUP("gpio1", an7583_gpio1),
>> -	PINCTRL_PIN_GROUP("gpio2", an7583_gpio2),
>> -	PINCTRL_PIN_GROUP("gpio3", an7583_gpio3),
>> -	PINCTRL_PIN_GROUP("gpio4", an7583_gpio4),
>> -	PINCTRL_PIN_GROUP("gpio5", an7583_gpio5),
>> -	PINCTRL_PIN_GROUP("gpio6", an7583_gpio6),
>> -	PINCTRL_PIN_GROUP("gpio7", an7583_gpio7),
>> -	PINCTRL_PIN_GROUP("gpio8", an7583_gpio8),
>> -	PINCTRL_PIN_GROUP("gpio9", an7583_gpio9),
>> -	PINCTRL_PIN_GROUP("gpio10", an7583_gpio10),
>> -	PINCTRL_PIN_GROUP("gpio11", an7583_gpio11),
>> -	PINCTRL_PIN_GROUP("gpio12", an7583_gpio12),
>> -	PINCTRL_PIN_GROUP("gpio13", an7583_gpio13),
>> -	PINCTRL_PIN_GROUP("gpio14", an7583_gpio14),
>> -	PINCTRL_PIN_GROUP("gpio15", an7583_gpio15),
>> -	PINCTRL_PIN_GROUP("gpio16", an7583_gpio16),
>> -	PINCTRL_PIN_GROUP("gpio17", an7583_gpio17),
>> -	PINCTRL_PIN_GROUP("gpio18", an7583_gpio18),
>> -	PINCTRL_PIN_GROUP("gpio19", an7583_gpio19),
>> -	PINCTRL_PIN_GROUP("gpio20", an7583_gpio20),
>> -	PINCTRL_PIN_GROUP("gpio21", an7583_gpio21),
>> -	PINCTRL_PIN_GROUP("gpio22", an7583_gpio22),
>> -	PINCTRL_PIN_GROUP("gpio23", an7583_gpio23),
>> -	PINCTRL_PIN_GROUP("gpio24", an7583_gpio24),
>> -	PINCTRL_PIN_GROUP("gpio25", an7583_gpio25),
>> -	PINCTRL_PIN_GROUP("gpio26", an7583_gpio26),
>> -	PINCTRL_PIN_GROUP("gpio27", an7583_gpio27),
>> -	PINCTRL_PIN_GROUP("gpio28", an7583_gpio28),
>> -	PINCTRL_PIN_GROUP("gpio29", an7583_gpio29),
>> -	PINCTRL_PIN_GROUP("gpio30", an7583_gpio30),
>> -	PINCTRL_PIN_GROUP("gpio31", an7583_gpio31),
>> -	PINCTRL_PIN_GROUP("gpio32", an7583_gpio32),
>> -	PINCTRL_PIN_GROUP("gpio33", an7583_gpio33),
>> -	PINCTRL_PIN_GROUP("gpio34", an7583_gpio34),
>> -	PINCTRL_PIN_GROUP("gpio35", an7583_gpio35),
>> -	PINCTRL_PIN_GROUP("gpio36", an7583_gpio36),
>> -	PINCTRL_PIN_GROUP("gpio37", an7583_gpio37),
>> -	PINCTRL_PIN_GROUP("gpio38", an7583_gpio38),
>> -	PINCTRL_PIN_GROUP("gpio39", an7583_gpio39),
>> -	PINCTRL_PIN_GROUP("gpio40", an7583_gpio40),
>> -	PINCTRL_PIN_GROUP("gpio41", an7583_gpio41),
>> -	PINCTRL_PIN_GROUP("gpio42", an7583_gpio42),
>> -	PINCTRL_PIN_GROUP("gpio43", an7583_gpio43),
>> -	PINCTRL_PIN_GROUP("gpio44", an7583_gpio44),
>> -	PINCTRL_PIN_GROUP("gpio45", an7583_gpio45),
>> -	PINCTRL_PIN_GROUP("gpio46", an7583_gpio46),
>> -	PINCTRL_PIN_GROUP("gpio47", an7583_gpio47),
>> -	PINCTRL_PIN_GROUP("gpio48", an7583_gpio48),
>> -	PINCTRL_PIN_GROUP("gpio49", an7583_gpio49),
>> -	PINCTRL_PIN_GROUP("gpio50", an7583_gpio50),
>> -	PINCTRL_PIN_GROUP("gpio51", an7583_gpio51),
>> -	PINCTRL_PIN_GROUP("gpio52", an7583_gpio52),
>> -	PINCTRL_PIN_GROUP("pcie_reset0", an7583_pcie_reset0),
>> -	PINCTRL_PIN_GROUP("pcie_reset1", an7583_pcie_reset1),
>> -};
>> -
>> -static const char *const pon_groups[] = { "pon" };
>> -static const char *const tod_1pps_groups[] = { "pon_tod_1pps", "gsw_tod_1pps" };
>> -static const char *const sipo_groups[] = { "sipo", "sipo_rclk" };
>> -static const char *const mdio_groups[] = { "mdio" };
>> -static const char *const an7583_mdio_groups[] = { "mdio" };
>> -static const char *const uart_groups[] = { "uart2", "uart2_cts_rts", "hsuart",
>> -					   "hsuart_cts_rts", "uart4",
>> -					   "uart5" };
>> -static const char *const i2c_groups[] = { "i2c1" };
>> -static const char *const jtag_groups[] = { "jtag_udi", "jtag_dfd" };
>> -static const char *const pcm_groups[] = { "pcm1", "pcm2" };
>> -static const char *const spi_groups[] = { "spi_quad", "spi_cs1" };
>> -static const char *const pcm_spi_groups[] = { "pcm_spi", "pcm_spi_int",
>> -					      "pcm_spi_rst", "pcm_spi_cs1",
>> -					      "pcm_spi_cs2_p156",
>> -					      "pcm_spi_cs2_p128",
>> -					      "pcm_spi_cs3", "pcm_spi_cs4" };
>> -static const char *const an7583_pcm_spi_groups[] = { "pcm_spi",
>> -						     "pcm_spi_rst", "pcm_spi_cs1" };
>> -static const char *const i2s_groups[] = { "i2s" };
>> -static const char *const emmc_groups[] = { "emmc" };
>> -static const char *const pnand_groups[] = { "pnand" };
>> -static const char *const gpio_groups[] = { "gpio47", "gpio48", "gpio49" };
>> -static const char *const pcie_reset_groups[] = { "pcie_reset0", "pcie_reset1",
>> -						 "pcie_reset2" };
>> -static const char *const an7583_gpio_groups[] = { "gpio39", "gpio40", "gpio41",
>> -						  "gpio42", "gpio43", "gpio44",
>> -						  "gpio45", "gpio46", "gpio47",
>> -						  "gpio48", "gpio49", "gpio50",
>> -						  "gpio51", "gpio52" };
>> -static const char *const an7583_pcie_reset_groups[] = { "pcie_reset0", "pcie_reset1" };
>> -static const char *const pwm_groups[] = { "gpio0", "gpio1",
>> -					  "gpio2", "gpio3",
>> -					  "gpio4", "gpio5",
>> -					  "gpio6", "gpio7",
>> -					  "gpio8", "gpio9",
>> -					  "gpio10", "gpio11",
>> -					  "gpio12", "gpio13",
>> -					  "gpio14", "gpio15",
>> -					  "gpio16", "gpio17",
>> -					  "gpio18", "gpio19",
>> -					  "gpio20", "gpio21",
>> -					  "gpio22", "gpio23",
>> -					  "gpio24", "gpio25",
>> -					  "gpio26", "gpio27",
>> -					  "gpio28", "gpio29",
>> -					  "gpio30", "gpio31",
>> -					  "gpio36", "gpio37",
>> -					  "gpio38", "gpio39",
>> -					  "gpio40", "gpio41",
>> -					  "gpio42", "gpio43",
>> -					  "gpio44", "gpio45",
>> -					  "gpio46", "gpio47",
>> -					  "gpio48", "gpio49" };
>> -static const char *const an7583_pwm_groups[] = { "gpio0", "gpio1",
>> -						 "gpio2", "gpio3",
>> -						 "gpio4", "gpio5",
>> -						 "gpio6", "gpio7",
>> -						 "gpio8", "gpio9",
>> -						 "gpio10", "gpio11",
>> -						 "gpio12", "gpio13",
>> -						 "gpio14", "gpio15",
>> -						 "gpio16", "gpio17",
>> -						 "gpio18", "gpio19",
>> -						 "gpio20", "gpio21",
>> -						 "gpio22", "gpio23",
>> -						 "gpio24", "gpio25",
>> -						 "gpio26", "gpio27",
>> -						 "gpio28", "gpio29",
>> -						 "gpio30", "gpio31",
>> -						 "gpio36", "gpio37",
>> -						 "gpio38", "gpio39",
>> -						 "gpio40", "gpio41",
>> -						 "gpio42", "gpio43",
>> -						 "gpio44", "gpio45",
>> -						 "gpio46", "gpio47",
>> -						 "gpio48", "gpio49",
>> -						 "gpio50", "gpio51" };
>> -static const char *const phy1_led0_groups[] = { "gpio33", "gpio34",
>> -						"gpio35", "gpio42" };
>> -static const char *const phy2_led0_groups[] = { "gpio33", "gpio34",
>> -						"gpio35", "gpio42" };
>> -static const char *const phy3_led0_groups[] = { "gpio33", "gpio34",
>> -						"gpio35", "gpio42" };
>> -static const char *const phy4_led0_groups[] = { "gpio33", "gpio34",
>> -						"gpio35", "gpio42" };
>> -static const char *const phy1_led1_groups[] = { "gpio43", "gpio44",
>> -						"gpio45", "gpio46" };
>> -static const char *const phy2_led1_groups[] = { "gpio43", "gpio44",
>> -						"gpio45", "gpio46" };
>> -static const char *const phy3_led1_groups[] = { "gpio43", "gpio44",
>> -						"gpio45", "gpio46" };
>> -static const char *const phy4_led1_groups[] = { "gpio43", "gpio44",
>> -						"gpio45", "gpio46" };
>> -static const char *const an7583_phy1_led0_groups[] = { "gpio1", "gpio2",
>> -							"gpio3", "gpio4" };
>> -static const char *const an7583_phy2_led0_groups[] = { "gpio1", "gpio2",
>> -							"gpio3", "gpio4" };
>> -static const char *const an7583_phy3_led0_groups[] = { "gpio1", "gpio2",
>> -							"gpio3", "gpio4" };
>> -static const char *const an7583_phy4_led0_groups[] = { "gpio1", "gpio2",
>> -							"gpio3", "gpio4" };
>> -static const char *const an7583_phy1_led1_groups[] = { "gpio8", "gpio9",
>> -							"gpio10", "gpio11" };
>> -static const char *const an7583_phy2_led1_groups[] = { "gpio8", "gpio9",
>> -							"gpio10", "gpio11" };
>> -static const char *const an7583_phy3_led1_groups[] = { "gpio8", "gpio9",
>> -							"gpio10", "gpio11" };
>> -static const char *const an7583_phy4_led1_groups[] = { "gpio8", "gpio9",
>> -							"gpio10", "gpio11" };
>> -
>> -static const struct airoha_pinctrl_func_group pon_func_group[] = {
>> -	{
>> -		.name = "pon",
>> -		.regmap[0] = {
>> -			AIROHA_FUNC_MUX,
>> -			REG_GPIO_PON_MODE,
>> -			GPIO_PON_MODE_MASK,
>> -			GPIO_PON_MODE_MASK
>> -		},
>> -		.regmap_size = 1,
>> -	},
>> -};
>> -
>> -static const struct airoha_pinctrl_func_group tod_1pps_func_group[] = {
>> -	{
>> -		.name = "pon_tod_1pps",
>> -		.regmap[0] = {
>> -			AIROHA_FUNC_MUX,
>> -			REG_GPIO_2ND_I2C_MODE,
>> -			PON_TOD_1PPS_MODE_MASK,
>> -			PON_TOD_1PPS_MODE_MASK
>> -		},
>> -		.regmap_size = 1,
>> -	}, {
>> -		.name = "gsw_tod_1pps",
>> -		.regmap[0] = {
>> -			AIROHA_FUNC_MUX,
>> -			REG_GPIO_2ND_I2C_MODE,
>> -			GSW_TOD_1PPS_MODE_MASK,
>> -			GSW_TOD_1PPS_MODE_MASK
>> -		},
>> -		.regmap_size = 1,
>> -	},
>> -};
>> -
>> -static const struct airoha_pinctrl_func_group sipo_func_group[] = {
>> -	{
>> -		.name = "sipo",
>> -		.regmap[0] = {
>> -			AIROHA_FUNC_MUX,
>> -			REG_GPIO_PON_MODE,
>> -			GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK,
>> -			GPIO_SIPO_MODE_MASK
>> -		},
>> -		.regmap_size = 1,
>> -	}, {
>> -		.name = "sipo_rclk",
>> -		.regmap[0] = {
>> -			AIROHA_FUNC_MUX,
>> -			REG_GPIO_PON_MODE,
>> -			GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK,
>> -			GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK
>> -		},
>> -		.regmap_size = 1,
>> -	},
>> -};
>> -
>> -static const struct airoha_pinctrl_func_group mdio_func_group[] = {
>> -	{
>> -		.name = "mdio",
>> -		.regmap[0] = {
>> -			AIROHA_FUNC_MUX,
>> -			REG_GPIO_2ND_I2C_MODE,
>> -			GPIO_MDC_IO_MASTER_MODE_MASK,
>> -			GPIO_MDC_IO_MASTER_MODE_MASK
>> -		},
>> -		.regmap[1] = {
>> -			AIROHA_FUNC_MUX,
>> -			REG_FORCE_GPIO_EN,
>> -			FORCE_GPIO_EN(1) | FORCE_GPIO_EN(2),
>> -			FORCE_GPIO_EN(1) | FORCE_GPIO_EN(2)
>> -		},
>> -		.regmap_size = 2,
>> -	},
>> -};
>> -
>> -static const struct airoha_pinctrl_func_group an7583_mdio_func_group[] = {
>> -	{
>> -		.name = "mdio",
>> -		.regmap[0] = {
>> -			AIROHA_FUNC_MUX,
>> -			REG_GPIO_PON_MODE,
>> -			GPIO_SGMII_MDIO_MODE_MASK,
>> -			GPIO_SGMII_MDIO_MODE_MASK
>> -		},
>> -		.regmap[1] = {
>> -			AIROHA_FUNC_MUX,
>> -			REG_GPIO_SPI_CS1_MODE,
>> -			GPIO_MDC_IO_MASTER_MODE_MASK,
>> -			GPIO_MDC_IO_MASTER_MODE_MASK
>> -		},
>> -		.regmap_size = 2,
>> -	},
>> -};
>> -
>> -static const struct airoha_pinctrl_func_group uart_func_group[] = {
>> -	{
>> -		.name = "uart2",
>> -		.regmap[0] = {
>> -			AIROHA_FUNC_MUX,
>> -			REG_GPIO_PON_MODE,
>> -			GPIO_UART2_MODE_MASK,
>> -			GPIO_UART2_MODE_MASK
>> -		},
>> -		.regmap_size = 1,
>> -	}, {
>> -		.name = "uart2_cts_rts",
>> -		.regmap[0] = {
>> -			AIROHA_FUNC_MUX,
>> -			REG_GPIO_PON_MODE,
>> -			GPIO_UART2_MODE_MASK | GPIO_UART2_CTS_RTS_MODE_MASK,
>> -			GPIO_UART2_MODE_MASK | GPIO_UART2_CTS_RTS_MODE_MASK
>> -		},
>> -		.regmap_size = 1,
>> -	}, {
>> -		.name = "hsuart",
>> -		.regmap[0] = {
>> -			AIROHA_FUNC_MUX,
>> -			REG_GPIO_PON_MODE,
>> -			GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK,
>> -			GPIO_HSUART_MODE_MASK
>> -		},
>> -		.regmap_size = 1,
>> -	},
>> -	{
>> -		.name = "hsuart_cts_rts",
>> -		.regmap[0] = {
>> -			AIROHA_FUNC_MUX,
>> -			REG_GPIO_PON_MODE,
>> -			GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK,
>> -			GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK
>> -		},
>> -		.regmap_size = 1,
>> -	}, {
>> -		.name = "uart4",
>> -		.regmap[0] = {
>> -			AIROHA_FUNC_MUX,
>> -			REG_GPIO_PON_MODE,
>> -			GPIO_UART4_MODE_MASK,
>> -			GPIO_UART4_MODE_MASK
>> -		},
>> -		.regmap_size = 1,
>> -	}, {
>> -		.name = "uart5",
>> -		.regmap[0] = {
>> -			AIROHA_FUNC_MUX,
>> -			REG_GPIO_PON_MODE,
>> -			GPIO_UART5_MODE_MASK,
>> -			GPIO_UART5_MODE_MASK
>> -		},
>> -		.regmap_size = 1,
>> -	},
>> -};
>> -
>> -static const struct airoha_pinctrl_func_group i2c_func_group[] = {
>> -	{
>> -		.name = "i2c1",
>> -		.regmap[0] = {
>> -			AIROHA_FUNC_MUX,
>> -			REG_GPIO_2ND_I2C_MODE,
>> -			GPIO_2ND_I2C_MODE_MASK,
>> -			GPIO_2ND_I2C_MODE_MASK
>> -		},
>> -		.regmap_size = 1,
>> -	},
>> -};
>> -
>> -static const struct airoha_pinctrl_func_group jtag_func_group[] = {
>> -	{
>> -		.name = "jtag_udi",
>> -		.regmap[0] = {
>> -			AIROHA_FUNC_MUX,
>> -			REG_NPU_UART_EN,
>> -			JTAG_UDI_EN_MASK,
>> -			JTAG_UDI_EN_MASK
>> -		},
>> -		.regmap_size = 1,
>> -	}, {
>> -		.name = "jtag_dfd",
>> -		.regmap[0] = {
>> -			AIROHA_FUNC_MUX,
>> -			REG_NPU_UART_EN,
>> -			JTAG_DFD_EN_MASK,
>> -			JTAG_DFD_EN_MASK
>> -		},
>> -		.regmap_size = 1,
>> -	},
>> -};
>> -
>> -static const struct airoha_pinctrl_func_group pcm_func_group[] = {
>> -	{
>> -		.name = "pcm1",
>> -		.regmap[0] = {
>> -			AIROHA_FUNC_MUX,
>> -			REG_GPIO_SPI_CS1_MODE,
>> -			GPIO_PCM1_MODE_MASK,
>> -			GPIO_PCM1_MODE_MASK
>> -		},
>> -		.regmap_size = 1,
>> -	}, {
>> -		.name = "pcm2",
>> -		.regmap[0] = {
>> -			AIROHA_FUNC_MUX,
>> -			REG_GPIO_SPI_CS1_MODE,
>> -			GPIO_PCM2_MODE_MASK,
>> -			GPIO_PCM2_MODE_MASK
>> -		},
>> -		.regmap_size = 1,
>> -	},
>> -};
>> -
>> -static const struct airoha_pinctrl_func_group spi_func_group[] = {
>> -	{
>> -		.name = "spi_quad",
>> -		.regmap[0] = {
>> -			AIROHA_FUNC_MUX,
>> -			REG_GPIO_SPI_CS1_MODE,
>> -			GPIO_SPI_QUAD_MODE_MASK,
>> -			GPIO_SPI_QUAD_MODE_MASK
>> -		},
>> -		.regmap_size = 1,
>> -	}, {
>> -		.name = "spi_cs1",
>> -		.regmap[0] = {
>> -			AIROHA_FUNC_MUX,
>> -			REG_GPIO_SPI_CS1_MODE,
>> -			GPIO_SPI_CS1_MODE_MASK,
>> -			GPIO_SPI_CS1_MODE_MASK
>> -		},
>> -		.regmap_size = 1,
>> -	}, {
>> -		.name = "spi_cs2",
>> -		.regmap[0] = {
>> -			AIROHA_FUNC_MUX,
>> -			REG_GPIO_SPI_CS1_MODE,
>> -			GPIO_SPI_CS2_MODE_MASK,
>> -			GPIO_SPI_CS2_MODE_MASK
>> -		},
>> -		.regmap_size = 1,
>> -	}, {
>> -		.name = "spi_cs3",
>> -		.regmap[0] = {
>> -			AIROHA_FUNC_MUX,
>> -			REG_GPIO_SPI_CS1_MODE,
>> -			GPIO_SPI_CS3_MODE_MASK,
>> -			GPIO_SPI_CS3_MODE_MASK
>> -		},
>> -		.regmap_size = 1,
>> -	}, {
>> -		.name = "spi_cs4",
>> -		.regmap[0] = {
>> -			AIROHA_FUNC_MUX,
>> -			REG_GPIO_SPI_CS1_MODE,
>> -			GPIO_SPI_CS4_MODE_MASK,
>> -			GPIO_SPI_CS4_MODE_MASK
>> -		},
>> -		.regmap_size = 1,
>> -	},
>> -};
>> -
>> -static const struct airoha_pinctrl_func_group pcm_spi_func_group[] = {
>> -	{
>> -		.name = "pcm_spi",
>> -		.regmap[0] = {
>> -			AIROHA_FUNC_MUX,
>> -			REG_GPIO_SPI_CS1_MODE,
>> -			GPIO_PCM_SPI_MODE_MASK,
>> -			GPIO_PCM_SPI_MODE_MASK
>> -		},
>> -		.regmap_size = 1,
>> -	}, {
>> -		.name = "pcm_spi_int",
>> -		.regmap[0] = {
>> -			AIROHA_FUNC_MUX,
>> -			REG_GPIO_SPI_CS1_MODE,
>> -			GPIO_PCM_INT_MODE_MASK,
>> -			GPIO_PCM_INT_MODE_MASK
>> -		},
>> -		.regmap_size = 1,
>> -	}, {
>> -		.name = "pcm_spi_rst",
>> -		.regmap[0] = {
>> -			AIROHA_FUNC_MUX,
>> -			REG_GPIO_SPI_CS1_MODE,
>> -			GPIO_PCM_RESET_MODE_MASK,
>> -			GPIO_PCM_RESET_MODE_MASK
>> -		},
>> -		.regmap_size = 1,
>> -	}, {
>> -		.name = "pcm_spi_cs1",
>> -		.regmap[0] = {
>> -			AIROHA_FUNC_MUX,
>> -			REG_GPIO_SPI_CS1_MODE,
>> -			GPIO_PCM_SPI_CS1_MODE_MASK,
>> -			GPIO_PCM_SPI_CS1_MODE_MASK
>> -		},
>> -		.regmap_size = 1,
>> -	}, {
>> -		.name = "pcm_spi_cs2_p128",
>> -		.regmap[0] = {
>> -			AIROHA_FUNC_MUX,
>> -			REG_GPIO_SPI_CS1_MODE,
>> -			GPIO_PCM_SPI_CS2_MODE_P128_MASK,
>> -			GPIO_PCM_SPI_CS2_MODE_P128_MASK
>> -		},
>> -		.regmap_size = 1,
>> -	}, {
>> -		.name = "pcm_spi_cs2_p156",
>> -		.regmap[0] = {
>> -			AIROHA_FUNC_MUX,
>> -			REG_GPIO_SPI_CS1_MODE,
>> -			GPIO_PCM_SPI_CS2_MODE_P156_MASK,
>> -			GPIO_PCM_SPI_CS2_MODE_P156_MASK
>> -		},
>> -		.regmap_size = 1,
>> -	}, {
>> -		.name = "pcm_spi_cs3",
>> -		.regmap[0] = {
>> -			AIROHA_FUNC_MUX,
>> -			REG_GPIO_SPI_CS1_MODE,
>> -			GPIO_PCM_SPI_CS3_MODE_MASK,
>> -			GPIO_PCM_SPI_CS3_MODE_MASK
>> -		},
>> -		.regmap_size = 1,
>> -	}, {
>> -		.name = "pcm_spi_cs4",
>> -		.regmap[0] = {
>> -			AIROHA_FUNC_MUX,
>> -			REG_GPIO_SPI_CS1_MODE,
>> -			GPIO_PCM_SPI_CS4_MODE_MASK,
>> -			GPIO_PCM_SPI_CS4_MODE_MASK
>> -		},
>> -		.regmap_size = 1,
>> -	},
>> -};
>> -
>> -static const struct airoha_pinctrl_func_group an7583_pcm_spi_func_group[] = {
>> -	{
>> -		.name = "pcm_spi",
>> -		.regmap[0] = {
>> -			AIROHA_FUNC_MUX,
>> -			REG_GPIO_SPI_CS1_MODE,
>> -			GPIO_PCM_SPI_MODE_MASK,
>> -			GPIO_PCM_SPI_MODE_MASK
>> -		},
>> -		.regmap_size = 1,
>> -	}, {
>> -		.name = "pcm_spi_int",
>> -		.regmap[0] = {
>> -			AIROHA_FUNC_MUX,
>> -			REG_GPIO_SPI_CS1_MODE,
>> -			GPIO_PCM_INT_MODE_MASK,
>> -			GPIO_PCM_INT_MODE_MASK
>> -		},
>> -		.regmap_size = 1,
>> -	}, {
>> -		.name = "pcm_spi_rst",
>> -		.regmap[0] = {
>> -			AIROHA_FUNC_MUX,
>> -			REG_GPIO_SPI_CS1_MODE,
>> -			GPIO_PCM_RESET_MODE_MASK,
>> -			GPIO_PCM_RESET_MODE_MASK
>> -		},
>> -		.regmap_size = 1,
>> -	}, {
>> -		.name = "pcm_spi_cs1",
>> -		.regmap[0] = {
>> -			AIROHA_FUNC_MUX,
>> -			REG_GPIO_SPI_CS1_MODE,
>> -			GPIO_PCM_SPI_CS1_MODE_MASK,
>> -			GPIO_PCM_SPI_CS1_MODE_MASK
>> -		},
>> -		.regmap_size = 1,
>> -	}, {
>> -		.name = "pcm_spi_cs2",
>> -		.regmap[0] = {
>> -			AIROHA_FUNC_MUX,
>> -			REG_GPIO_SPI_CS1_MODE,
>> -			AN7583_GPIO_PCM_SPI_CS2_MODE_MASK,
>> -			AN7583_GPIO_PCM_SPI_CS2_MODE_MASK
>> -		},
>> -		.regmap_size = 1,
>> -	}, {
>> -		.name = "pcm_spi_cs3",
>> -		.regmap[0] = {
>> -			AIROHA_FUNC_MUX,
>> -			REG_GPIO_SPI_CS1_MODE,
>> -			GPIO_PCM_SPI_CS3_MODE_MASK,
>> -			GPIO_PCM_SPI_CS3_MODE_MASK
>> -		},
>> -		.regmap_size = 1,
>> -	}, {
>> -		.name = "pcm_spi_cs4",
>> -		.regmap[0] = {
>> -			AIROHA_FUNC_MUX,
>> -			REG_GPIO_SPI_CS1_MODE,
>> -			GPIO_PCM_SPI_CS4_MODE_MASK,
>> -			GPIO_PCM_SPI_CS4_MODE_MASK
>> -		},
>> -		.regmap_size = 1,
>> -	},
>> -};
>> -
>> -static const struct airoha_pinctrl_func_group i2s_func_group[] = {
>> -	{
>> -		.name = "i2s",
>> -		.regmap[0] = {
>> -			AIROHA_FUNC_MUX,
>> -			REG_GPIO_2ND_I2C_MODE,
>> -			GPIO_I2S_MODE_MASK,
>> -			GPIO_I2S_MODE_MASK
>> -		},
>> -		.regmap_size = 1,
>> -	},
>> -};
>> -
>> -static const struct airoha_pinctrl_func_group emmc_func_group[] = {
>> -	{
>> -		.name = "emmc",
>> -		.regmap[0] = {
>> -			AIROHA_FUNC_MUX,
>> -			REG_GPIO_PON_MODE,
>> -			GPIO_EMMC_MODE_MASK,
>> -			GPIO_EMMC_MODE_MASK
>> -		},
>> -		.regmap_size = 1,
>> -	},
>> -};
>> -
>> -static const struct airoha_pinctrl_func_group pnand_func_group[] = {
>> -	{
>> -		.name = "pnand",
>> -		.regmap[0] = {
>> -			AIROHA_FUNC_MUX,
>> -			REG_GPIO_PON_MODE,
>> -			GPIO_PARALLEL_NAND_MODE_MASK,
>> -			GPIO_PARALLEL_NAND_MODE_MASK
>> -		},
>> -		.regmap_size = 1,
>> -	},
>> -};
>> -
>> -static const struct airoha_pinctrl_func_group gpio_func_group[] = {
>> -	AIROHA_PINCTRL_GPIO_EXT("gpio47", GPIO47_FLASH_MODE_CFG,
>> -				GPIO_PCIE_RESET0_MASK),
>> -	AIROHA_PINCTRL_GPIO_EXT("gpio48", GPIO48_FLASH_MODE_CFG,
>> -				GPIO_PCIE_RESET1_MASK),
>> -	AIROHA_PINCTRL_GPIO_EXT("gpio49", GPIO49_FLASH_MODE_CFG,
>> -				GPIO_PCIE_RESET2_MASK),
>> -};
>> -
>> -static const struct airoha_pinctrl_func_group pcie_reset_func_group[] = {
>> -	{
>> -		.name = "pcie_reset0",
>> -		.regmap[0] = {
>> -			AIROHA_FUNC_MUX,
>> -			REG_GPIO_PON_MODE,
>> -			GPIO_PCIE_RESET0_MASK,
>> -			0
>> -		},
>> -		.regmap_size = 1,
>> -	}, {
>> -		.name = "pcie_reset1",
>> -		.regmap[0] = {
>> -			AIROHA_FUNC_MUX,
>> -			REG_GPIO_PON_MODE,
>> -			GPIO_PCIE_RESET1_MASK,
>> -			0
>> -		},
>> -		.regmap_size = 1,
>> -	}, {
>> -		.name = "pcie_reset2",
>> -		.regmap[0] = {
>> -			AIROHA_FUNC_MUX,
>> -			REG_GPIO_PON_MODE,
>> -			GPIO_PCIE_RESET2_MASK,
>> -			0
>> -		},
>> -		.regmap_size = 1,
>> -	},
>> -};
>> -
>> -static const struct airoha_pinctrl_func_group an7583_gpio_func_group[] = {
>> -	AIROHA_PINCTRL_GPIO_EXT("gpio39", GPIO39_FLASH_MODE_CFG,
>> -				AN7583_I2C0_SCL_GPIO_MODE_MASK),
>> -	AIROHA_PINCTRL_GPIO_EXT("gpio40", GPIO40_FLASH_MODE_CFG,
>> -				AN7583_I2C0_SDA_GPIO_MODE_MASK),
>> -	AIROHA_PINCTRL_GPIO_EXT("gpio41", GPIO41_FLASH_MODE_CFG,
>> -				AN7583_I2C1_SCL_GPIO_MODE_MASK),
>> -	AIROHA_PINCTRL_GPIO_EXT("gpio42", GPIO42_FLASH_MODE_CFG,
>> -				AN7583_I2C1_SDA_GPIO_MODE_MASK),
>> -	AIROHA_PINCTRL_GPIO_EXT("gpio43", GPIO43_FLASH_MODE_CFG,
>> -				AN7583_SPI_CLK_GPIO_MODE_MASK),
>> -	AIROHA_PINCTRL_GPIO_EXT("gpio44", GPIO44_FLASH_MODE_CFG,
>> -				AN7583_SPI_CS_GPIO_MODE_MASK),
>> -	AIROHA_PINCTRL_GPIO_EXT("gpio45", GPIO45_FLASH_MODE_CFG,
>> -				AN7583_SPI_MOSI_GPIO_MODE_MASK),
>> -	AIROHA_PINCTRL_GPIO_EXT("gpio46", GPIO46_FLASH_MODE_CFG,
>> -				AN7583_SPI_MISO_GPIO_MODE_MASK),
>> -	AIROHA_PINCTRL_GPIO_EXT("gpio47", GPIO47_FLASH_MODE_CFG,
>> -				AN7583_UART_TXD_GPIO_MODE_MASK),
>> -	AIROHA_PINCTRL_GPIO_EXT("gpio48", GPIO48_FLASH_MODE_CFG,
>> -				AN7583_UART_RXD_GPIO_MODE_MASK),
>> -	AIROHA_PINCTRL_GPIO_EXT("gpio49", GPIO49_FLASH_MODE_CFG,
>> -				GPIO_PCIE_RESET0_MASK),
>> -	AIROHA_PINCTRL_GPIO_EXT("gpio50", GPIO50_FLASH_MODE_CFG,
>> -				GPIO_PCIE_RESET1_MASK),
>> -	AIROHA_PINCTRL_GPIO_EXT("gpio51", GPIO51_FLASH_MODE_CFG,
>> -				AN7583_MDC_0_GPIO_MODE_MASK),
>> -	AIROHA_PINCTRL_GPIO("gpio52", AN7583_MDIO_0_GPIO_MODE_MASK),
>> -};
>> -
>> -static const struct airoha_pinctrl_func_group an7583_pcie_reset_func_group[] = {
>> -	{
>> -		.name = "pcie_reset0",
>> -		.regmap[0] = {
>> -			AIROHA_FUNC_MUX,
>> -			REG_GPIO_PON_MODE,
>> -			GPIO_PCIE_RESET0_MASK,
>> -			0
>> -		},
>> -		.regmap_size = 1,
>> -	}, {
>> -		.name = "pcie_reset1",
>> -		.regmap[0] = {
>> -			AIROHA_FUNC_MUX,
>> -			REG_GPIO_PON_MODE,
>> -			GPIO_PCIE_RESET1_MASK,
>> -			0
>> -		},
>> -		.regmap_size = 1,
>> -	},
>> -};
>> -
>> -static const struct airoha_pinctrl_func_group pwm_func_group[] = {
>> -	AIROHA_PINCTRL_PWM("gpio0", GPIO0_FLASH_MODE_CFG),
>> -	AIROHA_PINCTRL_PWM("gpio1", GPIO1_FLASH_MODE_CFG),
>> -	AIROHA_PINCTRL_PWM("gpio2", GPIO2_FLASH_MODE_CFG),
>> -	AIROHA_PINCTRL_PWM("gpio3", GPIO3_FLASH_MODE_CFG),
>> -	AIROHA_PINCTRL_PWM("gpio4", GPIO4_FLASH_MODE_CFG),
>> -	AIROHA_PINCTRL_PWM("gpio5", GPIO5_FLASH_MODE_CFG),
>> -	AIROHA_PINCTRL_PWM("gpio6", GPIO6_FLASH_MODE_CFG),
>> -	AIROHA_PINCTRL_PWM("gpio7", GPIO7_FLASH_MODE_CFG),
>> -	AIROHA_PINCTRL_PWM("gpio8", GPIO8_FLASH_MODE_CFG),
>> -	AIROHA_PINCTRL_PWM("gpio9", GPIO9_FLASH_MODE_CFG),
>> -	AIROHA_PINCTRL_PWM("gpio10", GPIO10_FLASH_MODE_CFG),
>> -	AIROHA_PINCTRL_PWM("gpio11", GPIO11_FLASH_MODE_CFG),
>> -	AIROHA_PINCTRL_PWM("gpio12", GPIO12_FLASH_MODE_CFG),
>> -	AIROHA_PINCTRL_PWM("gpio13", GPIO13_FLASH_MODE_CFG),
>> -	AIROHA_PINCTRL_PWM("gpio14", GPIO14_FLASH_MODE_CFG),
>> -	AIROHA_PINCTRL_PWM("gpio15", GPIO15_FLASH_MODE_CFG),
>> -	AIROHA_PINCTRL_PWM_EXT("gpio16", GPIO16_FLASH_MODE_CFG),
>> -	AIROHA_PINCTRL_PWM_EXT("gpio17", GPIO17_FLASH_MODE_CFG),
>> -	AIROHA_PINCTRL_PWM_EXT("gpio18", GPIO18_FLASH_MODE_CFG),
>> -	AIROHA_PINCTRL_PWM_EXT("gpio19", GPIO19_FLASH_MODE_CFG),
>> -	AIROHA_PINCTRL_PWM_EXT("gpio20", GPIO20_FLASH_MODE_CFG),
>> -	AIROHA_PINCTRL_PWM_EXT("gpio21", GPIO21_FLASH_MODE_CFG),
>> -	AIROHA_PINCTRL_PWM_EXT("gpio22", GPIO22_FLASH_MODE_CFG),
>> -	AIROHA_PINCTRL_PWM_EXT("gpio23", GPIO23_FLASH_MODE_CFG),
>> -	AIROHA_PINCTRL_PWM_EXT("gpio24", GPIO24_FLASH_MODE_CFG),
>> -	AIROHA_PINCTRL_PWM_EXT("gpio25", GPIO25_FLASH_MODE_CFG),
>> -	AIROHA_PINCTRL_PWM_EXT("gpio26", GPIO26_FLASH_MODE_CFG),
>> -	AIROHA_PINCTRL_PWM_EXT("gpio27", GPIO27_FLASH_MODE_CFG),
>> -	AIROHA_PINCTRL_PWM_EXT("gpio28", GPIO28_FLASH_MODE_CFG),
>> -	AIROHA_PINCTRL_PWM_EXT("gpio29", GPIO29_FLASH_MODE_CFG),
>> -	AIROHA_PINCTRL_PWM_EXT("gpio30", GPIO30_FLASH_MODE_CFG),
>> -	AIROHA_PINCTRL_PWM_EXT("gpio31", GPIO31_FLASH_MODE_CFG),
>> -	AIROHA_PINCTRL_PWM_EXT("gpio36", GPIO36_FLASH_MODE_CFG),
>> -	AIROHA_PINCTRL_PWM_EXT("gpio37", GPIO37_FLASH_MODE_CFG),
>> -	AIROHA_PINCTRL_PWM_EXT("gpio38", GPIO38_FLASH_MODE_CFG),
>> -	AIROHA_PINCTRL_PWM_EXT("gpio39", GPIO39_FLASH_MODE_CFG),
>> -	AIROHA_PINCTRL_PWM_EXT("gpio40", GPIO40_FLASH_MODE_CFG),
>> -	AIROHA_PINCTRL_PWM_EXT("gpio41", GPIO41_FLASH_MODE_CFG),
>> -	AIROHA_PINCTRL_PWM_EXT("gpio42", GPIO42_FLASH_MODE_CFG),
>> -	AIROHA_PINCTRL_PWM_EXT("gpio43", GPIO43_FLASH_MODE_CFG),
>> -	AIROHA_PINCTRL_PWM_EXT("gpio44", GPIO44_FLASH_MODE_CFG),
>> -	AIROHA_PINCTRL_PWM_EXT("gpio45", GPIO45_FLASH_MODE_CFG),
>> -	AIROHA_PINCTRL_PWM_EXT("gpio46", GPIO46_FLASH_MODE_CFG),
>> -	AIROHA_PINCTRL_PWM_EXT_SEC("gpio47", GPIO47_FLASH_MODE_CFG,
>> -				   GPIO_PCIE_RESET0_MASK),
>> -	AIROHA_PINCTRL_PWM_EXT_SEC("gpio48", GPIO48_FLASH_MODE_CFG,
>> -				   GPIO_PCIE_RESET1_MASK),
>> -	AIROHA_PINCTRL_PWM_EXT_SEC("gpio49", GPIO49_FLASH_MODE_CFG,
>> -				   GPIO_PCIE_RESET2_MASK),
>> -};
>> -
>> -static const struct airoha_pinctrl_func_group an7583_pwm_func_group[] = {
>> -	AIROHA_PINCTRL_PWM("gpio0", GPIO0_FLASH_MODE_CFG),
>> -	AIROHA_PINCTRL_PWM("gpio1", GPIO1_FLASH_MODE_CFG),
>> -	AIROHA_PINCTRL_PWM("gpio2", GPIO2_FLASH_MODE_CFG),
>> -	AIROHA_PINCTRL_PWM("gpio3", GPIO3_FLASH_MODE_CFG),
>> -	AIROHA_PINCTRL_PWM("gpio4", GPIO4_FLASH_MODE_CFG),
>> -	AIROHA_PINCTRL_PWM("gpio5", GPIO5_FLASH_MODE_CFG),
>> -	AIROHA_PINCTRL_PWM("gpio6", GPIO6_FLASH_MODE_CFG),
>> -	AIROHA_PINCTRL_PWM("gpio7", GPIO7_FLASH_MODE_CFG),
>> -	AIROHA_PINCTRL_PWM("gpio8", GPIO8_FLASH_MODE_CFG),
>> -	AIROHA_PINCTRL_PWM("gpio9", GPIO9_FLASH_MODE_CFG),
>> -	AIROHA_PINCTRL_PWM("gpio10", GPIO10_FLASH_MODE_CFG),
>> -	AIROHA_PINCTRL_PWM("gpio11", GPIO11_FLASH_MODE_CFG),
>> -	AIROHA_PINCTRL_PWM("gpio12", GPIO12_FLASH_MODE_CFG),
>> -	AIROHA_PINCTRL_PWM("gpio13", GPIO13_FLASH_MODE_CFG),
>> -	AIROHA_PINCTRL_PWM("gpio14", GPIO14_FLASH_MODE_CFG),
>> -	AIROHA_PINCTRL_PWM("gpio15", GPIO15_FLASH_MODE_CFG),
>> -	AIROHA_PINCTRL_PWM_EXT("gpio16", GPIO16_FLASH_MODE_CFG),
>> -	AIROHA_PINCTRL_PWM_EXT("gpio17", GPIO17_FLASH_MODE_CFG),
>> -	AIROHA_PINCTRL_PWM_EXT("gpio18", GPIO18_FLASH_MODE_CFG),
>> -	AIROHA_PINCTRL_PWM_EXT("gpio19", GPIO19_FLASH_MODE_CFG),
>> -	AIROHA_PINCTRL_PWM_EXT("gpio20", GPIO20_FLASH_MODE_CFG),
>> -	AIROHA_PINCTRL_PWM_EXT("gpio21", GPIO21_FLASH_MODE_CFG),
>> -	AIROHA_PINCTRL_PWM_EXT("gpio22", GPIO22_FLASH_MODE_CFG),
>> -	AIROHA_PINCTRL_PWM_EXT("gpio23", GPIO23_FLASH_MODE_CFG),
>> -	AIROHA_PINCTRL_PWM_EXT("gpio24", GPIO24_FLASH_MODE_CFG),
>> -	AIROHA_PINCTRL_PWM_EXT("gpio25", GPIO25_FLASH_MODE_CFG),
>> -	AIROHA_PINCTRL_PWM_EXT("gpio26", GPIO26_FLASH_MODE_CFG),
>> -	AIROHA_PINCTRL_PWM_EXT("gpio27", GPIO27_FLASH_MODE_CFG),
>> -	AIROHA_PINCTRL_PWM_EXT("gpio28", GPIO28_FLASH_MODE_CFG),
>> -	AIROHA_PINCTRL_PWM_EXT("gpio29", GPIO29_FLASH_MODE_CFG),
>> -	AIROHA_PINCTRL_PWM_EXT("gpio30", GPIO30_FLASH_MODE_CFG),
>> -	AIROHA_PINCTRL_PWM_EXT("gpio31", GPIO31_FLASH_MODE_CFG),
>> -	AIROHA_PINCTRL_PWM_EXT("gpio36", GPIO36_FLASH_MODE_CFG),
>> -	AIROHA_PINCTRL_PWM_EXT("gpio37", GPIO37_FLASH_MODE_CFG),
>> -	AIROHA_PINCTRL_PWM_EXT("gpio38", GPIO38_FLASH_MODE_CFG),
>> -	AIROHA_PINCTRL_PWM_EXT_SEC("gpio39", GPIO39_FLASH_MODE_CFG,
>> -				   AN7583_I2C0_SCL_GPIO_MODE_MASK),
>> -	AIROHA_PINCTRL_PWM_EXT_SEC("gpio40", GPIO40_FLASH_MODE_CFG,
>> -				   AN7583_I2C0_SDA_GPIO_MODE_MASK),
>> -	AIROHA_PINCTRL_PWM_EXT_SEC("gpio41", GPIO41_FLASH_MODE_CFG,
>> -				   AN7583_I2C1_SCL_GPIO_MODE_MASK),
>> -	AIROHA_PINCTRL_PWM_EXT_SEC("gpio42", GPIO42_FLASH_MODE_CFG,
>> -				   AN7583_I2C1_SDA_GPIO_MODE_MASK),
>> -	AIROHA_PINCTRL_PWM_EXT_SEC("gpio43", GPIO43_FLASH_MODE_CFG,
>> -				   AN7583_SPI_CLK_GPIO_MODE_MASK),
>> -	AIROHA_PINCTRL_PWM_EXT_SEC("gpio44", GPIO44_FLASH_MODE_CFG,
>> -				   AN7583_SPI_CS_GPIO_MODE_MASK),
>> -	AIROHA_PINCTRL_PWM_EXT_SEC("gpio45", GPIO45_FLASH_MODE_CFG,
>> -				   AN7583_SPI_MOSI_GPIO_MODE_MASK),
>> -	AIROHA_PINCTRL_PWM_EXT_SEC("gpio46", GPIO46_FLASH_MODE_CFG,
>> -				   AN7583_SPI_MISO_GPIO_MODE_MASK),
>> -	AIROHA_PINCTRL_PWM_EXT_SEC("gpio47", GPIO47_FLASH_MODE_CFG,
>> -				   AN7583_UART_TXD_GPIO_MODE_MASK),
>> -	AIROHA_PINCTRL_PWM_EXT_SEC("gpio48", GPIO48_FLASH_MODE_CFG,
>> -				   AN7583_UART_RXD_GPIO_MODE_MASK),
>> -	AIROHA_PINCTRL_PWM_EXT_SEC("gpio49", GPIO49_FLASH_MODE_CFG,
>> -				   GPIO_PCIE_RESET0_MASK),
>> -	AIROHA_PINCTRL_PWM_EXT_SEC("gpio50", GPIO50_FLASH_MODE_CFG,
>> -				   GPIO_PCIE_RESET1_MASK),
>> -	AIROHA_PINCTRL_PWM_EXT_SEC("gpio51", GPIO51_FLASH_MODE_CFG,
>> -				   AN7583_MDC_0_GPIO_MODE_MASK),
>> -};
>> -
>> -static const struct airoha_pinctrl_func_group phy1_led0_func_group[] = {
>> -	AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK,
>> -				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),
>> -	AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK,
>> -				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)),
>> -	AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK,
>> -				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)),
>> -	AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK,
>> -				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),
>> -};
>> -
>> -static const struct airoha_pinctrl_func_group phy2_led0_func_group[] = {
>> -	AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK,
>> -				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),
>> -	AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK,
>> -				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)),
>> -	AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK,
>> -				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)),
>> -	AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK,
>> -				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),
>> -};
>> -
>> -static const struct airoha_pinctrl_func_group phy3_led0_func_group[] = {
>> -	AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK,
>> -				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
>> -	AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK,
>> -				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),
>> -	AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK,
>> -				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),
>> -	AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK,
>> -				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
>> -};
>> -
>> -static const struct airoha_pinctrl_func_group phy4_led0_func_group[] = {
>> -	AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK,
>> -				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)),
>> -	AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK,
>> -				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)),
>> -	AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK,
>> -				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)),
>> -	AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK,
>> -				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)),
>> -};
>> -
>> -static const struct airoha_pinctrl_func_group phy1_led1_func_group[] = {
>> -	AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK,
>> -				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),
>> -	AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK,
>> -				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)),
>> -	AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK,
>> -				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)),
>> -	AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK,
>> -				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),
>> -};
>> -
>> -static const struct airoha_pinctrl_func_group phy2_led1_func_group[] = {
>> -	AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK,
>> -				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),
>> -	AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK,
>> -				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)),
>> -	AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK,
>> -				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)),
>> -	AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK,
>> -				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),
>> -};
>> -
>> -static const struct airoha_pinctrl_func_group phy3_led1_func_group[] = {
>> -	AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK,
>> -				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
>> -	AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK,
>> -				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),
>> -	AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK,
>> -				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),
>> -	AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK,
>> -				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
>> -};
>> -
>> -static const struct airoha_pinctrl_func_group phy4_led1_func_group[] = {
>> -	AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK,
>> -				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)),
>> -	AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK,
>> -				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)),
>> -	AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK,
>> -				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)),
>> -	AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK,
>> -				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)),
>> -};
>> -
>> -static const struct airoha_pinctrl_func_group an7583_phy1_led0_func_group[] = {
>> -	AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK,
>> -				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),
>> -	AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK,
>> -				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)),
>> -	AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK,
>> -				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)),
>> -	AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK,
>> -				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),
>> -};
>> -
>> -static const struct airoha_pinctrl_func_group an7583_phy2_led0_func_group[] = {
>> -	AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK,
>> -				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),
>> -	AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK,
>> -				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)),
>> -	AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK,
>> -				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)),
>> -	AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK,
>> -				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),
>> -};
>> -
>> -static const struct airoha_pinctrl_func_group an7583_phy3_led0_func_group[] = {
>> -	AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK,
>> -				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
>> -	AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK,
>> -				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),
>> -	AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK,
>> -				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),
>> -	AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK,
>> -				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
>> -};
>> -
>> -static const struct airoha_pinctrl_func_group an7583_phy4_led0_func_group[] = {
>> -	AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK,
>> -				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)),
>> -	AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK,
>> -				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)),
>> -	AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK,
>> -				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)),
>> -	AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK,
>> -				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)),
>> -};
>> -
>> -static const struct airoha_pinctrl_func_group an7583_phy1_led1_func_group[] = {
>> -	AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK,
>> -				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),
>> -	AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK,
>> -				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)),
>> -	AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK,
>> -				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)),
>> -	AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK,
>> -				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),
>> -};
>> -
>> -static const struct airoha_pinctrl_func_group an7583_phy2_led1_func_group[] = {
>> -	AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK,
>> -				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),
>> -	AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK,
>> -				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)),
>> -	AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK,
>> -				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)),
>> -	AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK,
>> -				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),
>> -};
>> -
>> -static const struct airoha_pinctrl_func_group an7583_phy3_led1_func_group[] = {
>> -	AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK,
>> -				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
>> -	AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK,
>> -				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),
>> -	AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK,
>> -				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),
>> -	AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK,
>> -				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
>> -};
>> -
>> -static const struct airoha_pinctrl_func_group an7583_phy4_led1_func_group[] = {
>> -	AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK,
>> -				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)),
>> -	AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK,
>> -				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)),
>> -	AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK,
>> -				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)),
>> -	AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK,
>> -				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)),
>> -};
>> -
>> -static const struct airoha_pinctrl_func en7581_pinctrl_funcs[] = {
>> -	PINCTRL_FUNC_DESC("pon", pon),
>> -	PINCTRL_FUNC_DESC("tod_1pps", tod_1pps),
>> -	PINCTRL_FUNC_DESC("sipo", sipo),
>> -	PINCTRL_FUNC_DESC("mdio", mdio),
>> -	PINCTRL_FUNC_DESC("uart", uart),
>> -	PINCTRL_FUNC_DESC("i2c", i2c),
>> -	PINCTRL_FUNC_DESC("jtag", jtag),
>> -	PINCTRL_FUNC_DESC("pcm", pcm),
>> -	PINCTRL_FUNC_DESC("spi", spi),
>> -	PINCTRL_FUNC_DESC("pcm_spi", pcm_spi),
>> -	PINCTRL_FUNC_DESC("i2s", i2s),
>> -	PINCTRL_FUNC_DESC("emmc", emmc),
>> -	PINCTRL_FUNC_DESC("pnand", pnand),
>> -	PINCTRL_FUNC_DESC("gpio", gpio),
>> -	PINCTRL_FUNC_DESC("pcie_reset", pcie_reset),
>> -	PINCTRL_FUNC_DESC("pwm", pwm),
>> -	PINCTRL_FUNC_DESC("phy1_led0", phy1_led0),
>> -	PINCTRL_FUNC_DESC("phy2_led0", phy2_led0),
>> -	PINCTRL_FUNC_DESC("phy3_led0", phy3_led0),
>> -	PINCTRL_FUNC_DESC("phy4_led0", phy4_led0),
>> -	PINCTRL_FUNC_DESC("phy1_led1", phy1_led1),
>> -	PINCTRL_FUNC_DESC("phy2_led1", phy2_led1),
>> -	PINCTRL_FUNC_DESC("phy3_led1", phy3_led1),
>> -	PINCTRL_FUNC_DESC("phy4_led1", phy4_led1),
>> -};
>> -
>> -static const struct airoha_pinctrl_func an7583_pinctrl_funcs[] = {
>> -	PINCTRL_FUNC_DESC("pon", pon),
>> -	PINCTRL_FUNC_DESC("tod_1pps", tod_1pps),
>> -	PINCTRL_FUNC_DESC("sipo", sipo),
>> -	PINCTRL_FUNC_DESC("mdio", an7583_mdio),
>> -	PINCTRL_FUNC_DESC("uart", uart),
>> -	PINCTRL_FUNC_DESC("jtag", jtag),
>> -	PINCTRL_FUNC_DESC("pcm", pcm),
>> -	PINCTRL_FUNC_DESC("spi", spi),
>> -	PINCTRL_FUNC_DESC("pcm_spi", an7583_pcm_spi),
>> -	PINCTRL_FUNC_DESC("emmc", emmc),
>> -	PINCTRL_FUNC_DESC("pnand", pnand),
>> -	PINCTRL_FUNC_DESC("gpio", an7583_gpio),
>> -	PINCTRL_FUNC_DESC("pcie_reset", an7583_pcie_reset),
>> -	PINCTRL_FUNC_DESC("pwm", an7583_pwm),
>> -	PINCTRL_FUNC_DESC("phy1_led0", an7583_phy1_led0),
>> -	PINCTRL_FUNC_DESC("phy2_led0", an7583_phy2_led0),
>> -	PINCTRL_FUNC_DESC("phy3_led0", an7583_phy3_led0),
>> -	PINCTRL_FUNC_DESC("phy4_led0", an7583_phy4_led0),
>> -	PINCTRL_FUNC_DESC("phy1_led1", an7583_phy1_led1),
>> -	PINCTRL_FUNC_DESC("phy2_led1", an7583_phy2_led1),
>> -	PINCTRL_FUNC_DESC("phy3_led1", an7583_phy3_led1),
>> -	PINCTRL_FUNC_DESC("phy4_led1", an7583_phy4_led1),
>> -};
>> -
>> -static const struct airoha_pinctrl_conf en7581_pinctrl_pullup_conf[] = {
>> -	PINCTRL_CONF_DESC(0, REG_I2C_SDA_PU, UART1_TXD_PU_MASK),
>> -	PINCTRL_CONF_DESC(1, REG_I2C_SDA_PU, UART1_RXD_PU_MASK),
>> -	PINCTRL_CONF_DESC(2, REG_I2C_SDA_PU, I2C_SDA_PU_MASK),
>> -	PINCTRL_CONF_DESC(3, REG_I2C_SDA_PU, I2C_SCL_PU_MASK),
>> -	PINCTRL_CONF_DESC(4, REG_I2C_SDA_PU, SPI_CS0_PU_MASK),
>> -	PINCTRL_CONF_DESC(5, REG_I2C_SDA_PU, SPI_CLK_PU_MASK),
>> -	PINCTRL_CONF_DESC(6, REG_I2C_SDA_PU, SPI_MOSI_PU_MASK),
>> -	PINCTRL_CONF_DESC(7, REG_I2C_SDA_PU, SPI_MISO_PU_MASK),
>> -	PINCTRL_CONF_DESC(13, REG_GPIO_L_PU, BIT(0)),
>> -	PINCTRL_CONF_DESC(14, REG_GPIO_L_PU, BIT(1)),
>> -	PINCTRL_CONF_DESC(15, REG_GPIO_L_PU, BIT(2)),
>> -	PINCTRL_CONF_DESC(16, REG_GPIO_L_PU, BIT(3)),
>> -	PINCTRL_CONF_DESC(17, REG_GPIO_L_PU, BIT(4)),
>> -	PINCTRL_CONF_DESC(18, REG_GPIO_L_PU, BIT(5)),
>> -	PINCTRL_CONF_DESC(19, REG_GPIO_L_PU, BIT(6)),
>> -	PINCTRL_CONF_DESC(20, REG_GPIO_L_PU, BIT(7)),
>> -	PINCTRL_CONF_DESC(21, REG_GPIO_L_PU, BIT(8)),
>> -	PINCTRL_CONF_DESC(22, REG_GPIO_L_PU, BIT(9)),
>> -	PINCTRL_CONF_DESC(23, REG_GPIO_L_PU, BIT(10)),
>> -	PINCTRL_CONF_DESC(24, REG_GPIO_L_PU, BIT(11)),
>> -	PINCTRL_CONF_DESC(25, REG_GPIO_L_PU, BIT(12)),
>> -	PINCTRL_CONF_DESC(26, REG_GPIO_L_PU, BIT(13)),
>> -	PINCTRL_CONF_DESC(27, REG_GPIO_L_PU, BIT(14)),
>> -	PINCTRL_CONF_DESC(28, REG_GPIO_L_PU, BIT(15)),
>> -	PINCTRL_CONF_DESC(29, REG_GPIO_L_PU, BIT(16)),
>> -	PINCTRL_CONF_DESC(30, REG_GPIO_L_PU, BIT(17)),
>> -	PINCTRL_CONF_DESC(31, REG_GPIO_L_PU, BIT(18)),
>> -	PINCTRL_CONF_DESC(32, REG_GPIO_L_PU, BIT(19)),
>> -	PINCTRL_CONF_DESC(33, REG_GPIO_L_PU, BIT(20)),
>> -	PINCTRL_CONF_DESC(34, REG_GPIO_L_PU, BIT(21)),
>> -	PINCTRL_CONF_DESC(35, REG_GPIO_L_PU, BIT(22)),
>> -	PINCTRL_CONF_DESC(36, REG_GPIO_L_PU, BIT(23)),
>> -	PINCTRL_CONF_DESC(37, REG_GPIO_L_PU, BIT(24)),
>> -	PINCTRL_CONF_DESC(38, REG_GPIO_L_PU, BIT(25)),
>> -	PINCTRL_CONF_DESC(39, REG_GPIO_L_PU, BIT(26)),
>> -	PINCTRL_CONF_DESC(40, REG_GPIO_L_PU, BIT(27)),
>> -	PINCTRL_CONF_DESC(41, REG_GPIO_L_PU, BIT(28)),
>> -	PINCTRL_CONF_DESC(42, REG_GPIO_L_PU, BIT(29)),
>> -	PINCTRL_CONF_DESC(43, REG_GPIO_L_PU, BIT(30)),
>> -	PINCTRL_CONF_DESC(44, REG_GPIO_L_PU, BIT(31)),
>> -	PINCTRL_CONF_DESC(45, REG_GPIO_H_PU, BIT(0)),
>> -	PINCTRL_CONF_DESC(46, REG_GPIO_H_PU, BIT(1)),
>> -	PINCTRL_CONF_DESC(47, REG_GPIO_H_PU, BIT(2)),
>> -	PINCTRL_CONF_DESC(48, REG_GPIO_H_PU, BIT(3)),
>> -	PINCTRL_CONF_DESC(49, REG_GPIO_H_PU, BIT(4)),
>> -	PINCTRL_CONF_DESC(50, REG_GPIO_H_PU, BIT(5)),
>> -	PINCTRL_CONF_DESC(51, REG_GPIO_H_PU, BIT(6)),
>> -	PINCTRL_CONF_DESC(52, REG_GPIO_H_PU, BIT(7)),
>> -	PINCTRL_CONF_DESC(53, REG_GPIO_H_PU, BIT(8)),
>> -	PINCTRL_CONF_DESC(54, REG_GPIO_H_PU, BIT(9)),
>> -	PINCTRL_CONF_DESC(55, REG_GPIO_H_PU, BIT(10)),
>> -	PINCTRL_CONF_DESC(56, REG_GPIO_H_PU, BIT(11)),
>> -	PINCTRL_CONF_DESC(57, REG_GPIO_H_PU, BIT(12)),
>> -	PINCTRL_CONF_DESC(58, REG_GPIO_H_PU, BIT(13)),
>> -	PINCTRL_CONF_DESC(59, REG_GPIO_H_PU, BIT(14)),
>> -	PINCTRL_CONF_DESC(60, REG_I2C_SDA_PU, PCIE0_RESET_PU_MASK),
>> -	PINCTRL_CONF_DESC(61, REG_I2C_SDA_PU, PCIE1_RESET_PU_MASK),
>> -	PINCTRL_CONF_DESC(62, REG_I2C_SDA_PU, PCIE2_RESET_PU_MASK),
>> -};
>> -
>> -static const struct airoha_pinctrl_conf an7583_pinctrl_pullup_conf[] = {
>> -	PINCTRL_CONF_DESC(2, REG_GPIO_L_PU, BIT(0)),
>> -	PINCTRL_CONF_DESC(3, REG_GPIO_L_PU, BIT(1)),
>> -	PINCTRL_CONF_DESC(4, REG_GPIO_L_PU, BIT(2)),
>> -	PINCTRL_CONF_DESC(5, REG_GPIO_L_PU, BIT(3)),
>> -	PINCTRL_CONF_DESC(6, REG_GPIO_L_PU, BIT(4)),
>> -	PINCTRL_CONF_DESC(7, REG_GPIO_L_PU, BIT(5)),
>> -	PINCTRL_CONF_DESC(8, REG_GPIO_L_PU, BIT(6)),
>> -	PINCTRL_CONF_DESC(9, REG_GPIO_L_PU, BIT(7)),
>> -	PINCTRL_CONF_DESC(10, REG_GPIO_L_PU, BIT(8)),
>> -	PINCTRL_CONF_DESC(11, REG_GPIO_L_PU, BIT(9)),
>> -	PINCTRL_CONF_DESC(12, REG_GPIO_L_PU, BIT(10)),
>> -	PINCTRL_CONF_DESC(13, REG_GPIO_L_PU, BIT(11)),
>> -	PINCTRL_CONF_DESC(14, REG_GPIO_L_PU, BIT(12)),
>> -	PINCTRL_CONF_DESC(15, REG_GPIO_L_PU, BIT(13)),
>> -	PINCTRL_CONF_DESC(16, REG_GPIO_L_PU, BIT(14)),
>> -	PINCTRL_CONF_DESC(17, REG_GPIO_L_PU, BIT(15)),
>> -	PINCTRL_CONF_DESC(18, REG_GPIO_L_PU, BIT(16)),
>> -	PINCTRL_CONF_DESC(19, REG_GPIO_L_PU, BIT(17)),
>> -	PINCTRL_CONF_DESC(20, REG_GPIO_L_PU, BIT(18)),
>> -	PINCTRL_CONF_DESC(21, REG_GPIO_L_PU, BIT(19)),
>> -	PINCTRL_CONF_DESC(22, REG_GPIO_L_PU, BIT(20)),
>> -	PINCTRL_CONF_DESC(23, REG_GPIO_L_PU, BIT(21)),
>> -	PINCTRL_CONF_DESC(24, REG_GPIO_L_PU, BIT(22)),
>> -	PINCTRL_CONF_DESC(25, REG_GPIO_L_PU, BIT(23)),
>> -	PINCTRL_CONF_DESC(26, REG_GPIO_L_PU, BIT(24)),
>> -	PINCTRL_CONF_DESC(27, REG_GPIO_L_PU, BIT(25)),
>> -	PINCTRL_CONF_DESC(28, REG_GPIO_L_PU, BIT(26)),
>> -	PINCTRL_CONF_DESC(29, REG_GPIO_L_PU, BIT(27)),
>> -	PINCTRL_CONF_DESC(30, REG_GPIO_L_PU, BIT(28)),
>> -	PINCTRL_CONF_DESC(31, REG_GPIO_L_PU, BIT(29)),
>> -	PINCTRL_CONF_DESC(32, REG_GPIO_L_PU, BIT(30)),
>> -	PINCTRL_CONF_DESC(33, REG_GPIO_L_PU, BIT(31)),
>> -	PINCTRL_CONF_DESC(34, REG_GPIO_H_PU, BIT(0)),
>> -	PINCTRL_CONF_DESC(35, REG_GPIO_H_PU, BIT(1)),
>> -	PINCTRL_CONF_DESC(36, REG_GPIO_H_PU, BIT(2)),
>> -	PINCTRL_CONF_DESC(37, REG_GPIO_H_PU, BIT(3)),
>> -	PINCTRL_CONF_DESC(38, REG_GPIO_H_PU, BIT(4)),
>> -	PINCTRL_CONF_DESC(39, REG_GPIO_H_PU, BIT(5)),
>> -	PINCTRL_CONF_DESC(40, REG_GPIO_H_PU, BIT(6)),
>> -	PINCTRL_CONF_DESC(41, REG_I2C_SDA_PU, I2C_SCL_PU_MASK),
>> -	PINCTRL_CONF_DESC(42, REG_I2C_SDA_PU, I2C_SDA_PU_MASK),
>> -	PINCTRL_CONF_DESC(43, REG_I2C_SDA_PU, AN7583_I2C1_SCL_PU_MASK),
>> -	PINCTRL_CONF_DESC(44, REG_I2C_SDA_PU, AN7583_I2C1_SDA_PU_MASK),
>> -	PINCTRL_CONF_DESC(45, REG_I2C_SDA_PU, SPI_CLK_PU_MASK),
>> -	PINCTRL_CONF_DESC(46, REG_I2C_SDA_PU, SPI_CS0_PU_MASK),
>> -	PINCTRL_CONF_DESC(47, REG_I2C_SDA_PU, SPI_MOSI_PU_MASK),
>> -	PINCTRL_CONF_DESC(48, REG_I2C_SDA_PU, SPI_MISO_PU_MASK),
>> -	PINCTRL_CONF_DESC(49, REG_I2C_SDA_PU, UART1_TXD_PU_MASK),
>> -	PINCTRL_CONF_DESC(50, REG_I2C_SDA_PU, UART1_RXD_PU_MASK),
>> -	PINCTRL_CONF_DESC(51, REG_I2C_SDA_PU, PCIE0_RESET_PU_MASK),
>> -	PINCTRL_CONF_DESC(52, REG_I2C_SDA_PU, PCIE1_RESET_PU_MASK),
>> -	PINCTRL_CONF_DESC(53, REG_I2C_SDA_PU, AN7583_MDC_0_PU_MASK),
>> -	PINCTRL_CONF_DESC(54, REG_I2C_SDA_PU, AN7583_MDIO_0_PU_MASK),
>> -};
>> -
>> -static const struct airoha_pinctrl_conf en7581_pinctrl_pulldown_conf[] = {
>> -	PINCTRL_CONF_DESC(0, REG_I2C_SDA_PD, UART1_TXD_PD_MASK),
>> -	PINCTRL_CONF_DESC(1, REG_I2C_SDA_PD, UART1_RXD_PD_MASK),
>> -	PINCTRL_CONF_DESC(2, REG_I2C_SDA_PD, I2C_SDA_PD_MASK),
>> -	PINCTRL_CONF_DESC(3, REG_I2C_SDA_PD, I2C_SCL_PD_MASK),
>> -	PINCTRL_CONF_DESC(4, REG_I2C_SDA_PD, SPI_CS0_PD_MASK),
>> -	PINCTRL_CONF_DESC(5, REG_I2C_SDA_PD, SPI_CLK_PD_MASK),
>> -	PINCTRL_CONF_DESC(6, REG_I2C_SDA_PD, SPI_MOSI_PD_MASK),
>> -	PINCTRL_CONF_DESC(7, REG_I2C_SDA_PD, SPI_MISO_PD_MASK),
>> -	PINCTRL_CONF_DESC(13, REG_GPIO_L_PD, BIT(0)),
>> -	PINCTRL_CONF_DESC(14, REG_GPIO_L_PD, BIT(1)),
>> -	PINCTRL_CONF_DESC(15, REG_GPIO_L_PD, BIT(2)),
>> -	PINCTRL_CONF_DESC(16, REG_GPIO_L_PD, BIT(3)),
>> -	PINCTRL_CONF_DESC(17, REG_GPIO_L_PD, BIT(4)),
>> -	PINCTRL_CONF_DESC(18, REG_GPIO_L_PD, BIT(5)),
>> -	PINCTRL_CONF_DESC(19, REG_GPIO_L_PD, BIT(6)),
>> -	PINCTRL_CONF_DESC(20, REG_GPIO_L_PD, BIT(7)),
>> -	PINCTRL_CONF_DESC(21, REG_GPIO_L_PD, BIT(8)),
>> -	PINCTRL_CONF_DESC(22, REG_GPIO_L_PD, BIT(9)),
>> -	PINCTRL_CONF_DESC(23, REG_GPIO_L_PD, BIT(10)),
>> -	PINCTRL_CONF_DESC(24, REG_GPIO_L_PD, BIT(11)),
>> -	PINCTRL_CONF_DESC(25, REG_GPIO_L_PD, BIT(12)),
>> -	PINCTRL_CONF_DESC(26, REG_GPIO_L_PD, BIT(13)),
>> -	PINCTRL_CONF_DESC(27, REG_GPIO_L_PD, BIT(14)),
>> -	PINCTRL_CONF_DESC(28, REG_GPIO_L_PD, BIT(15)),
>> -	PINCTRL_CONF_DESC(29, REG_GPIO_L_PD, BIT(16)),
>> -	PINCTRL_CONF_DESC(30, REG_GPIO_L_PD, BIT(17)),
>> -	PINCTRL_CONF_DESC(31, REG_GPIO_L_PD, BIT(18)),
>> -	PINCTRL_CONF_DESC(32, REG_GPIO_L_PD, BIT(19)),
>> -	PINCTRL_CONF_DESC(33, REG_GPIO_L_PD, BIT(20)),
>> -	PINCTRL_CONF_DESC(34, REG_GPIO_L_PD, BIT(21)),
>> -	PINCTRL_CONF_DESC(35, REG_GPIO_L_PD, BIT(22)),
>> -	PINCTRL_CONF_DESC(36, REG_GPIO_L_PD, BIT(23)),
>> -	PINCTRL_CONF_DESC(37, REG_GPIO_L_PD, BIT(24)),
>> -	PINCTRL_CONF_DESC(38, REG_GPIO_L_PD, BIT(25)),
>> -	PINCTRL_CONF_DESC(39, REG_GPIO_L_PD, BIT(26)),
>> -	PINCTRL_CONF_DESC(40, REG_GPIO_L_PD, BIT(27)),
>> -	PINCTRL_CONF_DESC(41, REG_GPIO_L_PD, BIT(28)),
>> -	PINCTRL_CONF_DESC(42, REG_GPIO_L_PD, BIT(29)),
>> -	PINCTRL_CONF_DESC(43, REG_GPIO_L_PD, BIT(30)),
>> -	PINCTRL_CONF_DESC(44, REG_GPIO_L_PD, BIT(31)),
>> -	PINCTRL_CONF_DESC(45, REG_GPIO_H_PD, BIT(0)),
>> -	PINCTRL_CONF_DESC(46, REG_GPIO_H_PD, BIT(1)),
>> -	PINCTRL_CONF_DESC(47, REG_GPIO_H_PD, BIT(2)),
>> -	PINCTRL_CONF_DESC(48, REG_GPIO_H_PD, BIT(3)),
>> -	PINCTRL_CONF_DESC(49, REG_GPIO_H_PD, BIT(4)),
>> -	PINCTRL_CONF_DESC(50, REG_GPIO_H_PD, BIT(5)),
>> -	PINCTRL_CONF_DESC(51, REG_GPIO_H_PD, BIT(6)),
>> -	PINCTRL_CONF_DESC(52, REG_GPIO_H_PD, BIT(7)),
>> -	PINCTRL_CONF_DESC(53, REG_GPIO_H_PD, BIT(8)),
>> -	PINCTRL_CONF_DESC(54, REG_GPIO_H_PD, BIT(9)),
>> -	PINCTRL_CONF_DESC(55, REG_GPIO_H_PD, BIT(10)),
>> -	PINCTRL_CONF_DESC(56, REG_GPIO_H_PD, BIT(11)),
>> -	PINCTRL_CONF_DESC(57, REG_GPIO_H_PD, BIT(12)),
>> -	PINCTRL_CONF_DESC(58, REG_GPIO_H_PD, BIT(13)),
>> -	PINCTRL_CONF_DESC(59, REG_GPIO_H_PD, BIT(14)),
>> -	PINCTRL_CONF_DESC(60, REG_I2C_SDA_PD, PCIE0_RESET_PD_MASK),
>> -	PINCTRL_CONF_DESC(61, REG_I2C_SDA_PD, PCIE1_RESET_PD_MASK),
>> -	PINCTRL_CONF_DESC(62, REG_I2C_SDA_PD, PCIE2_RESET_PD_MASK),
>> -};
>> -
>> -static const struct airoha_pinctrl_conf an7583_pinctrl_pulldown_conf[] = {
>> -	PINCTRL_CONF_DESC(2, REG_GPIO_L_PD, BIT(0)),
>> -	PINCTRL_CONF_DESC(3, REG_GPIO_L_PD, BIT(1)),
>> -	PINCTRL_CONF_DESC(4, REG_GPIO_L_PD, BIT(2)),
>> -	PINCTRL_CONF_DESC(5, REG_GPIO_L_PD, BIT(3)),
>> -	PINCTRL_CONF_DESC(6, REG_GPIO_L_PD, BIT(4)),
>> -	PINCTRL_CONF_DESC(7, REG_GPIO_L_PD, BIT(5)),
>> -	PINCTRL_CONF_DESC(8, REG_GPIO_L_PD, BIT(6)),
>> -	PINCTRL_CONF_DESC(9, REG_GPIO_L_PD, BIT(7)),
>> -	PINCTRL_CONF_DESC(10, REG_GPIO_L_PD, BIT(8)),
>> -	PINCTRL_CONF_DESC(11, REG_GPIO_L_PD, BIT(9)),
>> -	PINCTRL_CONF_DESC(12, REG_GPIO_L_PD, BIT(10)),
>> -	PINCTRL_CONF_DESC(13, REG_GPIO_L_PD, BIT(11)),
>> -	PINCTRL_CONF_DESC(14, REG_GPIO_L_PD, BIT(12)),
>> -	PINCTRL_CONF_DESC(15, REG_GPIO_L_PD, BIT(13)),
>> -	PINCTRL_CONF_DESC(16, REG_GPIO_L_PD, BIT(14)),
>> -	PINCTRL_CONF_DESC(17, REG_GPIO_L_PD, BIT(15)),
>> -	PINCTRL_CONF_DESC(18, REG_GPIO_L_PD, BIT(16)),
>> -	PINCTRL_CONF_DESC(19, REG_GPIO_L_PD, BIT(17)),
>> -	PINCTRL_CONF_DESC(20, REG_GPIO_L_PD, BIT(18)),
>> -	PINCTRL_CONF_DESC(21, REG_GPIO_L_PD, BIT(19)),
>> -	PINCTRL_CONF_DESC(22, REG_GPIO_L_PD, BIT(20)),
>> -	PINCTRL_CONF_DESC(23, REG_GPIO_L_PD, BIT(21)),
>> -	PINCTRL_CONF_DESC(24, REG_GPIO_L_PD, BIT(22)),
>> -	PINCTRL_CONF_DESC(25, REG_GPIO_L_PD, BIT(23)),
>> -	PINCTRL_CONF_DESC(26, REG_GPIO_L_PD, BIT(24)),
>> -	PINCTRL_CONF_DESC(27, REG_GPIO_L_PD, BIT(25)),
>> -	PINCTRL_CONF_DESC(28, REG_GPIO_L_PD, BIT(26)),
>> -	PINCTRL_CONF_DESC(29, REG_GPIO_L_PD, BIT(27)),
>> -	PINCTRL_CONF_DESC(30, REG_GPIO_L_PD, BIT(28)),
>> -	PINCTRL_CONF_DESC(31, REG_GPIO_L_PD, BIT(29)),
>> -	PINCTRL_CONF_DESC(32, REG_GPIO_L_PD, BIT(30)),
>> -	PINCTRL_CONF_DESC(33, REG_GPIO_L_PD, BIT(31)),
>> -	PINCTRL_CONF_DESC(34, REG_GPIO_H_PD, BIT(0)),
>> -	PINCTRL_CONF_DESC(35, REG_GPIO_H_PD, BIT(1)),
>> -	PINCTRL_CONF_DESC(36, REG_GPIO_H_PD, BIT(2)),
>> -	PINCTRL_CONF_DESC(37, REG_GPIO_H_PD, BIT(3)),
>> -	PINCTRL_CONF_DESC(38, REG_GPIO_H_PD, BIT(4)),
>> -	PINCTRL_CONF_DESC(39, REG_GPIO_H_PD, BIT(5)),
>> -	PINCTRL_CONF_DESC(40, REG_GPIO_H_PD, BIT(6)),
>> -	PINCTRL_CONF_DESC(41, REG_I2C_SDA_PD, I2C_SCL_PD_MASK),
>> -	PINCTRL_CONF_DESC(42, REG_I2C_SDA_PD, I2C_SDA_PD_MASK),
>> -	PINCTRL_CONF_DESC(43, REG_I2C_SDA_PD, AN7583_I2C1_SCL_PD_MASK),
>> -	PINCTRL_CONF_DESC(44, REG_I2C_SDA_PD, AN7583_I2C1_SDA_PD_MASK),
>> -	PINCTRL_CONF_DESC(45, REG_I2C_SDA_PD, SPI_CLK_PD_MASK),
>> -	PINCTRL_CONF_DESC(46, REG_I2C_SDA_PD, SPI_CS0_PD_MASK),
>> -	PINCTRL_CONF_DESC(47, REG_I2C_SDA_PD, SPI_MOSI_PD_MASK),
>> -	PINCTRL_CONF_DESC(48, REG_I2C_SDA_PD, SPI_MISO_PD_MASK),
>> -	PINCTRL_CONF_DESC(49, REG_I2C_SDA_PD, UART1_TXD_PD_MASK),
>> -	PINCTRL_CONF_DESC(50, REG_I2C_SDA_PD, UART1_RXD_PD_MASK),
>> -	PINCTRL_CONF_DESC(51, REG_I2C_SDA_PD, PCIE0_RESET_PD_MASK),
>> -	PINCTRL_CONF_DESC(52, REG_I2C_SDA_PD, PCIE1_RESET_PD_MASK),
>> -	PINCTRL_CONF_DESC(53, REG_I2C_SDA_PD, AN7583_MDC_0_PD_MASK),
>> -	PINCTRL_CONF_DESC(54, REG_I2C_SDA_PD, AN7583_MDIO_0_PD_MASK),
>> -};
>> -
>> -static const struct airoha_pinctrl_conf en7581_pinctrl_drive_e2_conf[] = {
>> -	PINCTRL_CONF_DESC(0, REG_I2C_SDA_E2, UART1_TXD_E2_MASK),
>> -	PINCTRL_CONF_DESC(1, REG_I2C_SDA_E2, UART1_RXD_E2_MASK),
>> -	PINCTRL_CONF_DESC(2, REG_I2C_SDA_E2, I2C_SDA_E2_MASK),
>> -	PINCTRL_CONF_DESC(3, REG_I2C_SDA_E2, I2C_SCL_E2_MASK),
>> -	PINCTRL_CONF_DESC(4, REG_I2C_SDA_E2, SPI_CS0_E2_MASK),
>> -	PINCTRL_CONF_DESC(5, REG_I2C_SDA_E2, SPI_CLK_E2_MASK),
>> -	PINCTRL_CONF_DESC(6, REG_I2C_SDA_E2, SPI_MOSI_E2_MASK),
>> -	PINCTRL_CONF_DESC(7, REG_I2C_SDA_E2, SPI_MISO_E2_MASK),
>> -	PINCTRL_CONF_DESC(13, REG_GPIO_L_E2, BIT(0)),
>> -	PINCTRL_CONF_DESC(14, REG_GPIO_L_E2, BIT(1)),
>> -	PINCTRL_CONF_DESC(15, REG_GPIO_L_E2, BIT(2)),
>> -	PINCTRL_CONF_DESC(16, REG_GPIO_L_E2, BIT(3)),
>> -	PINCTRL_CONF_DESC(17, REG_GPIO_L_E2, BIT(4)),
>> -	PINCTRL_CONF_DESC(18, REG_GPIO_L_E2, BIT(5)),
>> -	PINCTRL_CONF_DESC(19, REG_GPIO_L_E2, BIT(6)),
>> -	PINCTRL_CONF_DESC(20, REG_GPIO_L_E2, BIT(7)),
>> -	PINCTRL_CONF_DESC(21, REG_GPIO_L_E2, BIT(8)),
>> -	PINCTRL_CONF_DESC(22, REG_GPIO_L_E2, BIT(9)),
>> -	PINCTRL_CONF_DESC(23, REG_GPIO_L_E2, BIT(10)),
>> -	PINCTRL_CONF_DESC(24, REG_GPIO_L_E2, BIT(11)),
>> -	PINCTRL_CONF_DESC(25, REG_GPIO_L_E2, BIT(12)),
>> -	PINCTRL_CONF_DESC(26, REG_GPIO_L_E2, BIT(13)),
>> -	PINCTRL_CONF_DESC(27, REG_GPIO_L_E2, BIT(14)),
>> -	PINCTRL_CONF_DESC(28, REG_GPIO_L_E2, BIT(15)),
>> -	PINCTRL_CONF_DESC(29, REG_GPIO_L_E2, BIT(16)),
>> -	PINCTRL_CONF_DESC(30, REG_GPIO_L_E2, BIT(17)),
>> -	PINCTRL_CONF_DESC(31, REG_GPIO_L_E2, BIT(18)),
>> -	PINCTRL_CONF_DESC(32, REG_GPIO_L_E2, BIT(19)),
>> -	PINCTRL_CONF_DESC(33, REG_GPIO_L_E2, BIT(20)),
>> -	PINCTRL_CONF_DESC(34, REG_GPIO_L_E2, BIT(21)),
>> -	PINCTRL_CONF_DESC(35, REG_GPIO_L_E2, BIT(22)),
>> -	PINCTRL_CONF_DESC(36, REG_GPIO_L_E2, BIT(23)),
>> -	PINCTRL_CONF_DESC(37, REG_GPIO_L_E2, BIT(24)),
>> -	PINCTRL_CONF_DESC(38, REG_GPIO_L_E2, BIT(25)),
>> -	PINCTRL_CONF_DESC(39, REG_GPIO_L_E2, BIT(26)),
>> -	PINCTRL_CONF_DESC(40, REG_GPIO_L_E2, BIT(27)),
>> -	PINCTRL_CONF_DESC(41, REG_GPIO_L_E2, BIT(28)),
>> -	PINCTRL_CONF_DESC(42, REG_GPIO_L_E2, BIT(29)),
>> -	PINCTRL_CONF_DESC(43, REG_GPIO_L_E2, BIT(30)),
>> -	PINCTRL_CONF_DESC(44, REG_GPIO_L_E2, BIT(31)),
>> -	PINCTRL_CONF_DESC(45, REG_GPIO_H_E2, BIT(0)),
>> -	PINCTRL_CONF_DESC(46, REG_GPIO_H_E2, BIT(1)),
>> -	PINCTRL_CONF_DESC(47, REG_GPIO_H_E2, BIT(2)),
>> -	PINCTRL_CONF_DESC(48, REG_GPIO_H_E2, BIT(3)),
>> -	PINCTRL_CONF_DESC(49, REG_GPIO_H_E2, BIT(4)),
>> -	PINCTRL_CONF_DESC(50, REG_GPIO_H_E2, BIT(5)),
>> -	PINCTRL_CONF_DESC(51, REG_GPIO_H_E2, BIT(6)),
>> -	PINCTRL_CONF_DESC(52, REG_GPIO_H_E2, BIT(7)),
>> -	PINCTRL_CONF_DESC(53, REG_GPIO_H_E2, BIT(8)),
>> -	PINCTRL_CONF_DESC(54, REG_GPIO_H_E2, BIT(9)),
>> -	PINCTRL_CONF_DESC(55, REG_GPIO_H_E2, BIT(10)),
>> -	PINCTRL_CONF_DESC(56, REG_GPIO_H_E2, BIT(11)),
>> -	PINCTRL_CONF_DESC(57, REG_GPIO_H_E2, BIT(12)),
>> -	PINCTRL_CONF_DESC(58, REG_GPIO_H_E2, BIT(13)),
>> -	PINCTRL_CONF_DESC(59, REG_GPIO_H_E2, BIT(14)),
>> -	PINCTRL_CONF_DESC(60, REG_I2C_SDA_E2, PCIE0_RESET_E2_MASK),
>> -	PINCTRL_CONF_DESC(61, REG_I2C_SDA_E2, PCIE1_RESET_E2_MASK),
>> -	PINCTRL_CONF_DESC(62, REG_I2C_SDA_E2, PCIE2_RESET_E2_MASK),
>> -};
>> -
>> -static const struct airoha_pinctrl_conf an7583_pinctrl_drive_e2_conf[] = {
>> -	PINCTRL_CONF_DESC(2, REG_GPIO_L_E2, BIT(0)),
>> -	PINCTRL_CONF_DESC(3, REG_GPIO_L_E2, BIT(1)),
>> -	PINCTRL_CONF_DESC(4, REG_GPIO_L_E2, BIT(2)),
>> -	PINCTRL_CONF_DESC(5, REG_GPIO_L_E2, BIT(3)),
>> -	PINCTRL_CONF_DESC(6, REG_GPIO_L_E2, BIT(4)),
>> -	PINCTRL_CONF_DESC(7, REG_GPIO_L_E2, BIT(5)),
>> -	PINCTRL_CONF_DESC(8, REG_GPIO_L_E2, BIT(6)),
>> -	PINCTRL_CONF_DESC(9, REG_GPIO_L_E2, BIT(7)),
>> -	PINCTRL_CONF_DESC(10, REG_GPIO_L_E2, BIT(8)),
>> -	PINCTRL_CONF_DESC(11, REG_GPIO_L_E2, BIT(9)),
>> -	PINCTRL_CONF_DESC(12, REG_GPIO_L_E2, BIT(10)),
>> -	PINCTRL_CONF_DESC(13, REG_GPIO_L_E2, BIT(11)),
>> -	PINCTRL_CONF_DESC(14, REG_GPIO_L_E2, BIT(12)),
>> -	PINCTRL_CONF_DESC(15, REG_GPIO_L_E2, BIT(13)),
>> -	PINCTRL_CONF_DESC(16, REG_GPIO_L_E2, BIT(14)),
>> -	PINCTRL_CONF_DESC(17, REG_GPIO_L_E2, BIT(15)),
>> -	PINCTRL_CONF_DESC(18, REG_GPIO_L_E2, BIT(16)),
>> -	PINCTRL_CONF_DESC(19, REG_GPIO_L_E2, BIT(17)),
>> -	PINCTRL_CONF_DESC(20, REG_GPIO_L_E2, BIT(18)),
>> -	PINCTRL_CONF_DESC(21, REG_GPIO_L_E2, BIT(19)),
>> -	PINCTRL_CONF_DESC(22, REG_GPIO_L_E2, BIT(20)),
>> -	PINCTRL_CONF_DESC(23, REG_GPIO_L_E2, BIT(21)),
>> -	PINCTRL_CONF_DESC(24, REG_GPIO_L_E2, BIT(22)),
>> -	PINCTRL_CONF_DESC(25, REG_GPIO_L_E2, BIT(23)),
>> -	PINCTRL_CONF_DESC(26, REG_GPIO_L_E2, BIT(24)),
>> -	PINCTRL_CONF_DESC(27, REG_GPIO_L_E2, BIT(25)),
>> -	PINCTRL_CONF_DESC(28, REG_GPIO_L_E2, BIT(26)),
>> -	PINCTRL_CONF_DESC(29, REG_GPIO_L_E2, BIT(27)),
>> -	PINCTRL_CONF_DESC(30, REG_GPIO_L_E2, BIT(28)),
>> -	PINCTRL_CONF_DESC(31, REG_GPIO_L_E2, BIT(29)),
>> -	PINCTRL_CONF_DESC(32, REG_GPIO_L_E2, BIT(30)),
>> -	PINCTRL_CONF_DESC(33, REG_GPIO_L_E2, BIT(31)),
>> -	PINCTRL_CONF_DESC(34, REG_GPIO_H_E2, BIT(0)),
>> -	PINCTRL_CONF_DESC(35, REG_GPIO_H_E2, BIT(1)),
>> -	PINCTRL_CONF_DESC(36, REG_GPIO_H_E2, BIT(2)),
>> -	PINCTRL_CONF_DESC(37, REG_GPIO_H_E2, BIT(3)),
>> -	PINCTRL_CONF_DESC(38, REG_GPIO_H_E2, BIT(4)),
>> -	PINCTRL_CONF_DESC(39, REG_GPIO_H_E2, BIT(5)),
>> -	PINCTRL_CONF_DESC(40, REG_GPIO_H_E2, BIT(6)),
>> -	PINCTRL_CONF_DESC(41, REG_I2C_SDA_E2, I2C_SCL_E2_MASK),
>> -	PINCTRL_CONF_DESC(42, REG_I2C_SDA_E2, I2C_SDA_E2_MASK),
>> -	PINCTRL_CONF_DESC(43, REG_I2C_SDA_E2, AN7583_I2C1_SCL_E2_MASK),
>> -	PINCTRL_CONF_DESC(44, REG_I2C_SDA_E2, AN7583_I2C1_SDA_E2_MASK),
>> -	PINCTRL_CONF_DESC(45, REG_I2C_SDA_E2, SPI_CLK_E2_MASK),
>> -	PINCTRL_CONF_DESC(46, REG_I2C_SDA_E2, SPI_CS0_E2_MASK),
>> -	PINCTRL_CONF_DESC(47, REG_I2C_SDA_E2, SPI_MOSI_E2_MASK),
>> -	PINCTRL_CONF_DESC(48, REG_I2C_SDA_E2, SPI_MISO_E2_MASK),
>> -	PINCTRL_CONF_DESC(49, REG_I2C_SDA_E2, UART1_TXD_E2_MASK),
>> -	PINCTRL_CONF_DESC(50, REG_I2C_SDA_E2, UART1_RXD_E2_MASK),
>> -	PINCTRL_CONF_DESC(51, REG_I2C_SDA_E2, PCIE0_RESET_E2_MASK),
>> -	PINCTRL_CONF_DESC(52, REG_I2C_SDA_E2, PCIE1_RESET_E2_MASK),
>> -	PINCTRL_CONF_DESC(53, REG_I2C_SDA_E2, AN7583_MDC_0_E2_MASK),
>> -	PINCTRL_CONF_DESC(54, REG_I2C_SDA_E2, AN7583_MDIO_0_E2_MASK),
>> -};
>> -
>> -static const struct airoha_pinctrl_conf en7581_pinctrl_drive_e4_conf[] = {
>> -	PINCTRL_CONF_DESC(0, REG_I2C_SDA_E4, UART1_TXD_E4_MASK),
>> -	PINCTRL_CONF_DESC(1, REG_I2C_SDA_E4, UART1_RXD_E4_MASK),
>> -	PINCTRL_CONF_DESC(2, REG_I2C_SDA_E4, I2C_SDA_E4_MASK),
>> -	PINCTRL_CONF_DESC(3, REG_I2C_SDA_E4, I2C_SCL_E4_MASK),
>> -	PINCTRL_CONF_DESC(4, REG_I2C_SDA_E4, SPI_CS0_E4_MASK),
>> -	PINCTRL_CONF_DESC(5, REG_I2C_SDA_E4, SPI_CLK_E4_MASK),
>> -	PINCTRL_CONF_DESC(6, REG_I2C_SDA_E4, SPI_MOSI_E4_MASK),
>> -	PINCTRL_CONF_DESC(7, REG_I2C_SDA_E4, SPI_MISO_E4_MASK),
>> -	PINCTRL_CONF_DESC(13, REG_GPIO_L_E4, BIT(0)),
>> -	PINCTRL_CONF_DESC(14, REG_GPIO_L_E4, BIT(1)),
>> -	PINCTRL_CONF_DESC(15, REG_GPIO_L_E4, BIT(2)),
>> -	PINCTRL_CONF_DESC(16, REG_GPIO_L_E4, BIT(3)),
>> -	PINCTRL_CONF_DESC(17, REG_GPIO_L_E4, BIT(4)),
>> -	PINCTRL_CONF_DESC(18, REG_GPIO_L_E4, BIT(5)),
>> -	PINCTRL_CONF_DESC(19, REG_GPIO_L_E4, BIT(6)),
>> -	PINCTRL_CONF_DESC(20, REG_GPIO_L_E4, BIT(7)),
>> -	PINCTRL_CONF_DESC(21, REG_GPIO_L_E4, BIT(8)),
>> -	PINCTRL_CONF_DESC(22, REG_GPIO_L_E4, BIT(9)),
>> -	PINCTRL_CONF_DESC(23, REG_GPIO_L_E4, BIT(10)),
>> -	PINCTRL_CONF_DESC(24, REG_GPIO_L_E4, BIT(11)),
>> -	PINCTRL_CONF_DESC(25, REG_GPIO_L_E4, BIT(12)),
>> -	PINCTRL_CONF_DESC(26, REG_GPIO_L_E4, BIT(13)),
>> -	PINCTRL_CONF_DESC(27, REG_GPIO_L_E4, BIT(14)),
>> -	PINCTRL_CONF_DESC(28, REG_GPIO_L_E4, BIT(15)),
>> -	PINCTRL_CONF_DESC(29, REG_GPIO_L_E4, BIT(16)),
>> -	PINCTRL_CONF_DESC(30, REG_GPIO_L_E4, BIT(17)),
>> -	PINCTRL_CONF_DESC(31, REG_GPIO_L_E4, BIT(18)),
>> -	PINCTRL_CONF_DESC(32, REG_GPIO_L_E4, BIT(19)),
>> -	PINCTRL_CONF_DESC(33, REG_GPIO_L_E4, BIT(20)),
>> -	PINCTRL_CONF_DESC(34, REG_GPIO_L_E4, BIT(21)),
>> -	PINCTRL_CONF_DESC(35, REG_GPIO_L_E4, BIT(22)),
>> -	PINCTRL_CONF_DESC(36, REG_GPIO_L_E4, BIT(23)),
>> -	PINCTRL_CONF_DESC(37, REG_GPIO_L_E4, BIT(24)),
>> -	PINCTRL_CONF_DESC(38, REG_GPIO_L_E4, BIT(25)),
>> -	PINCTRL_CONF_DESC(39, REG_GPIO_L_E4, BIT(26)),
>> -	PINCTRL_CONF_DESC(40, REG_GPIO_L_E4, BIT(27)),
>> -	PINCTRL_CONF_DESC(41, REG_GPIO_L_E4, BIT(28)),
>> -	PINCTRL_CONF_DESC(42, REG_GPIO_L_E4, BIT(29)),
>> -	PINCTRL_CONF_DESC(43, REG_GPIO_L_E4, BIT(30)),
>> -	PINCTRL_CONF_DESC(44, REG_GPIO_L_E4, BIT(31)),
>> -	PINCTRL_CONF_DESC(45, REG_GPIO_H_E4, BIT(0)),
>> -	PINCTRL_CONF_DESC(46, REG_GPIO_H_E4, BIT(1)),
>> -	PINCTRL_CONF_DESC(47, REG_GPIO_H_E4, BIT(2)),
>> -	PINCTRL_CONF_DESC(48, REG_GPIO_H_E4, BIT(3)),
>> -	PINCTRL_CONF_DESC(49, REG_GPIO_H_E4, BIT(4)),
>> -	PINCTRL_CONF_DESC(50, REG_GPIO_H_E4, BIT(5)),
>> -	PINCTRL_CONF_DESC(51, REG_GPIO_H_E4, BIT(6)),
>> -	PINCTRL_CONF_DESC(52, REG_GPIO_H_E4, BIT(7)),
>> -	PINCTRL_CONF_DESC(53, REG_GPIO_H_E4, BIT(8)),
>> -	PINCTRL_CONF_DESC(54, REG_GPIO_H_E4, BIT(9)),
>> -	PINCTRL_CONF_DESC(55, REG_GPIO_H_E4, BIT(10)),
>> -	PINCTRL_CONF_DESC(56, REG_GPIO_H_E4, BIT(11)),
>> -	PINCTRL_CONF_DESC(57, REG_GPIO_H_E4, BIT(12)),
>> -	PINCTRL_CONF_DESC(58, REG_GPIO_H_E4, BIT(13)),
>> -	PINCTRL_CONF_DESC(59, REG_GPIO_H_E4, BIT(14)),
>> -	PINCTRL_CONF_DESC(60, REG_I2C_SDA_E4, PCIE0_RESET_E4_MASK),
>> -	PINCTRL_CONF_DESC(61, REG_I2C_SDA_E4, PCIE1_RESET_E4_MASK),
>> -	PINCTRL_CONF_DESC(62, REG_I2C_SDA_E4, PCIE2_RESET_E4_MASK),
>> -};
>> -
>> -static const struct airoha_pinctrl_conf an7583_pinctrl_drive_e4_conf[] = {
>> -	PINCTRL_CONF_DESC(2, REG_GPIO_L_E4, BIT(0)),
>> -	PINCTRL_CONF_DESC(3, REG_GPIO_L_E4, BIT(1)),
>> -	PINCTRL_CONF_DESC(4, REG_GPIO_L_E4, BIT(2)),
>> -	PINCTRL_CONF_DESC(5, REG_GPIO_L_E4, BIT(3)),
>> -	PINCTRL_CONF_DESC(6, REG_GPIO_L_E4, BIT(4)),
>> -	PINCTRL_CONF_DESC(7, REG_GPIO_L_E4, BIT(5)),
>> -	PINCTRL_CONF_DESC(8, REG_GPIO_L_E4, BIT(6)),
>> -	PINCTRL_CONF_DESC(9, REG_GPIO_L_E4, BIT(7)),
>> -	PINCTRL_CONF_DESC(10, REG_GPIO_L_E4, BIT(8)),
>> -	PINCTRL_CONF_DESC(11, REG_GPIO_L_E4, BIT(9)),
>> -	PINCTRL_CONF_DESC(12, REG_GPIO_L_E4, BIT(10)),
>> -	PINCTRL_CONF_DESC(13, REG_GPIO_L_E4, BIT(11)),
>> -	PINCTRL_CONF_DESC(14, REG_GPIO_L_E4, BIT(12)),
>> -	PINCTRL_CONF_DESC(15, REG_GPIO_L_E4, BIT(13)),
>> -	PINCTRL_CONF_DESC(16, REG_GPIO_L_E4, BIT(14)),
>> -	PINCTRL_CONF_DESC(17, REG_GPIO_L_E4, BIT(15)),
>> -	PINCTRL_CONF_DESC(18, REG_GPIO_L_E4, BIT(16)),
>> -	PINCTRL_CONF_DESC(19, REG_GPIO_L_E4, BIT(17)),
>> -	PINCTRL_CONF_DESC(20, REG_GPIO_L_E4, BIT(18)),
>> -	PINCTRL_CONF_DESC(21, REG_GPIO_L_E4, BIT(19)),
>> -	PINCTRL_CONF_DESC(22, REG_GPIO_L_E4, BIT(20)),
>> -	PINCTRL_CONF_DESC(23, REG_GPIO_L_E4, BIT(21)),
>> -	PINCTRL_CONF_DESC(24, REG_GPIO_L_E4, BIT(22)),
>> -	PINCTRL_CONF_DESC(25, REG_GPIO_L_E4, BIT(23)),
>> -	PINCTRL_CONF_DESC(26, REG_GPIO_L_E4, BIT(24)),
>> -	PINCTRL_CONF_DESC(27, REG_GPIO_L_E4, BIT(25)),
>> -	PINCTRL_CONF_DESC(28, REG_GPIO_L_E4, BIT(26)),
>> -	PINCTRL_CONF_DESC(29, REG_GPIO_L_E4, BIT(27)),
>> -	PINCTRL_CONF_DESC(30, REG_GPIO_L_E4, BIT(28)),
>> -	PINCTRL_CONF_DESC(31, REG_GPIO_L_E4, BIT(29)),
>> -	PINCTRL_CONF_DESC(32, REG_GPIO_L_E4, BIT(30)),
>> -	PINCTRL_CONF_DESC(33, REG_GPIO_L_E4, BIT(31)),
>> -	PINCTRL_CONF_DESC(34, REG_GPIO_H_E4, BIT(0)),
>> -	PINCTRL_CONF_DESC(35, REG_GPIO_H_E4, BIT(1)),
>> -	PINCTRL_CONF_DESC(36, REG_GPIO_H_E4, BIT(2)),
>> -	PINCTRL_CONF_DESC(37, REG_GPIO_H_E4, BIT(3)),
>> -	PINCTRL_CONF_DESC(38, REG_GPIO_H_E4, BIT(4)),
>> -	PINCTRL_CONF_DESC(39, REG_GPIO_H_E4, BIT(5)),
>> -	PINCTRL_CONF_DESC(40, REG_GPIO_H_E4, BIT(6)),
>> -	PINCTRL_CONF_DESC(41, REG_I2C_SDA_E4, I2C_SCL_E4_MASK),
>> -	PINCTRL_CONF_DESC(42, REG_I2C_SDA_E4, I2C_SDA_E4_MASK),
>> -	PINCTRL_CONF_DESC(43, REG_I2C_SDA_E4, AN7583_I2C1_SCL_E4_MASK),
>> -	PINCTRL_CONF_DESC(44, REG_I2C_SDA_E4, AN7583_I2C1_SDA_E4_MASK),
>> -	PINCTRL_CONF_DESC(45, REG_I2C_SDA_E4, SPI_CLK_E4_MASK),
>> -	PINCTRL_CONF_DESC(46, REG_I2C_SDA_E4, SPI_CS0_E4_MASK),
>> -	PINCTRL_CONF_DESC(47, REG_I2C_SDA_E4, SPI_MOSI_E4_MASK),
>> -	PINCTRL_CONF_DESC(48, REG_I2C_SDA_E4, SPI_MISO_E4_MASK),
>> -	PINCTRL_CONF_DESC(49, REG_I2C_SDA_E4, UART1_TXD_E4_MASK),
>> -	PINCTRL_CONF_DESC(50, REG_I2C_SDA_E4, UART1_RXD_E4_MASK),
>> -	PINCTRL_CONF_DESC(51, REG_I2C_SDA_E4, PCIE0_RESET_E4_MASK),
>> -	PINCTRL_CONF_DESC(52, REG_I2C_SDA_E4, PCIE1_RESET_E4_MASK),
>> -	PINCTRL_CONF_DESC(53, REG_I2C_SDA_E4, AN7583_MDC_0_E4_MASK),
>> -	PINCTRL_CONF_DESC(54, REG_I2C_SDA_E4, AN7583_MDIO_0_E4_MASK),
>> -};
>> -
>> -static const struct airoha_pinctrl_conf en7581_pinctrl_pcie_rst_od_conf[] = {
>> -	PINCTRL_CONF_DESC(60, REG_PCIE_RESET_OD, PCIE0_RESET_OD_MASK),
>> -	PINCTRL_CONF_DESC(61, REG_PCIE_RESET_OD, PCIE1_RESET_OD_MASK),
>> -	PINCTRL_CONF_DESC(62, REG_PCIE_RESET_OD, PCIE2_RESET_OD_MASK),
>> -};
>> -
>> -static const struct airoha_pinctrl_conf an7583_pinctrl_pcie_rst_od_conf[] = {
>> -	PINCTRL_CONF_DESC(51, REG_PCIE_RESET_OD, PCIE0_RESET_OD_MASK),
>> -	PINCTRL_CONF_DESC(52, REG_PCIE_RESET_OD, PCIE1_RESET_OD_MASK),
>> -};
>> -
>>  static int airoha_convert_pin_to_reg_offset(struct pinctrl_dev *pctrl_dev,
>>  					    struct pinctrl_gpio_range *range,
>>  					    int pin)
>> @@ -2606,6 +318,7 @@ static int airoha_pinctrl_add_gpiochip(struct airoha_pinctrl *pinctrl,
>>  					struct platform_device *pdev)
>>  {
>>  	struct airoha_pinctrl_gpiochip *chip = &pinctrl->gpiochip;
>> +	struct irq_chip *irq_chip = &pinctrl->gpio_irq_chip;
>>  	struct gpio_chip *gc = &chip->chip;
>>  	struct gpio_irq_chip *girq = &gc->irq;
>>  	struct device *dev = &pdev->dev;
>> @@ -2630,9 +343,11 @@ static int airoha_pinctrl_add_gpiochip(struct airoha_pinctrl *pinctrl,
>>  	gc->base = -1;
>>  	gc->ngpio = AIROHA_NUM_PINS;
>>  
>> +	memcpy(irq_chip, &airoha_gpio_irq_chip, sizeof(struct irq_chip));
>> +
>>  	girq->default_type = IRQ_TYPE_NONE;
>>  	girq->handler = handle_bad_irq;
>> -	gpio_irq_chip_set_chip(girq, &airoha_gpio_irq_chip);
>> +	gpio_irq_chip_set_chip(girq, irq_chip);
>>  
>>  	irq = platform_get_irq(pdev, 0);
>>  	if (irq < 0)
>> @@ -3011,7 +726,7 @@ static const struct pinctrl_ops airoha_pctlops = {
>>  	.dt_free_map = pinconf_generic_dt_free_map,
>>  };
>>  
>> -static int airoha_pinctrl_probe(struct platform_device *pdev)
>> +int airoha_pinctrl_probe(struct platform_device *pdev)
>>  {
>>  	const struct airoha_pinctrl_match_data *data;
>>  	struct device *dev = &pdev->dev;
>> @@ -3020,6 +735,8 @@ static int airoha_pinctrl_probe(struct platform_device *pdev)
>>  	int err, i;
>>  
>>  	data = device_get_match_data(dev);
>> +	if (!data)
>> +		return -EINVAL;
>>  
>>  	pinctrl = devm_kzalloc(dev, sizeof(*pinctrl), GFP_KERNEL);
>>  	if (!pinctrl)
>> @@ -3036,8 +753,8 @@ static int airoha_pinctrl_probe(struct platform_device *pdev)
>>  	pinctrl->chip_scu = map;
>>  
>>  	/* Init pinctrl desc struct */
>> -	pinctrl->desc.name = KBUILD_MODNAME;
>> -	pinctrl->desc.owner = THIS_MODULE;
>> +	pinctrl->desc.name = data->pinctrl_name;
>> +	pinctrl->desc.owner = data->pinctrl_owner;
>>  	pinctrl->desc.pctlops = &airoha_pctlops;
>>  	pinctrl->desc.pmxops = &airoha_pmxops;
>>  	pinctrl->desc.confops = &airoha_confops;
>> @@ -3089,87 +806,10 @@ static int airoha_pinctrl_probe(struct platform_device *pdev)
>>  	/* build gpio-chip */
>>  	return airoha_pinctrl_add_gpiochip(pinctrl, pdev);
>>  }
>> -
>> -static const struct airoha_pinctrl_match_data en7581_pinctrl_match_data = {
>> -	.pins = en7581_pinctrl_pins,
>> -	.num_pins = ARRAY_SIZE(en7581_pinctrl_pins),
>> -	.grps = en7581_pinctrl_groups,
>> -	.num_grps = ARRAY_SIZE(en7581_pinctrl_groups),
>> -	.funcs = en7581_pinctrl_funcs,
>> -	.num_funcs = ARRAY_SIZE(en7581_pinctrl_funcs),
>> -	.confs_info = {
>> -		[AIROHA_PINCTRL_CONFS_PULLUP] = {
>> -			.confs = en7581_pinctrl_pullup_conf,
>> -			.num_confs = ARRAY_SIZE(en7581_pinctrl_pullup_conf),
>> -		},
>> -		[AIROHA_PINCTRL_CONFS_PULLDOWN] = {
>> -			.confs = en7581_pinctrl_pulldown_conf,
>> -			.num_confs = ARRAY_SIZE(en7581_pinctrl_pulldown_conf),
>> -		},
>> -		[AIROHA_PINCTRL_CONFS_DRIVE_E2] = {
>> -			.confs = en7581_pinctrl_drive_e2_conf,
>> -			.num_confs = ARRAY_SIZE(en7581_pinctrl_drive_e2_conf),
>> -		},
>> -		[AIROHA_PINCTRL_CONFS_DRIVE_E4] = {
>> -			.confs = en7581_pinctrl_drive_e4_conf,
>> -			.num_confs = ARRAY_SIZE(en7581_pinctrl_drive_e4_conf),
>> -		},
>> -		[AIROHA_PINCTRL_CONFS_PCIE_RST_OD] = {
>> -			.confs = en7581_pinctrl_pcie_rst_od_conf,
>> -			.num_confs = ARRAY_SIZE(en7581_pinctrl_pcie_rst_od_conf),
>> -		},
>> -	},
>> -};
>> -
>> -static const struct airoha_pinctrl_match_data an7583_pinctrl_match_data = {
>> -	.pins = an7583_pinctrl_pins,
>> -	.num_pins = ARRAY_SIZE(an7583_pinctrl_pins),
>> -	.grps = an7583_pinctrl_groups,
>> -	.num_grps = ARRAY_SIZE(an7583_pinctrl_groups),
>> -	.funcs = an7583_pinctrl_funcs,
>> -	.num_funcs = ARRAY_SIZE(an7583_pinctrl_funcs),
>> -	.confs_info = {
>> -		[AIROHA_PINCTRL_CONFS_PULLUP] = {
>> -			.confs = an7583_pinctrl_pullup_conf,
>> -			.num_confs = ARRAY_SIZE(an7583_pinctrl_pullup_conf),
>> -		},
>> -		[AIROHA_PINCTRL_CONFS_PULLDOWN] = {
>> -			.confs = an7583_pinctrl_pulldown_conf,
>> -			.num_confs = ARRAY_SIZE(an7583_pinctrl_pulldown_conf),
>> -		},
>> -		[AIROHA_PINCTRL_CONFS_DRIVE_E2] = {
>> -			.confs = an7583_pinctrl_drive_e2_conf,
>> -			.num_confs = ARRAY_SIZE(an7583_pinctrl_drive_e2_conf),
>> -		},
>> -		[AIROHA_PINCTRL_CONFS_DRIVE_E4] = {
>> -			.confs = an7583_pinctrl_drive_e4_conf,
>> -			.num_confs = ARRAY_SIZE(an7583_pinctrl_drive_e4_conf),
>> -		},
>> -		[AIROHA_PINCTRL_CONFS_PCIE_RST_OD] = {
>> -			.confs = an7583_pinctrl_pcie_rst_od_conf,
>> -			.num_confs = ARRAY_SIZE(an7583_pinctrl_pcie_rst_od_conf),
>> -		},
>> -	},
>> -};
>> -
>> -static const struct of_device_id airoha_pinctrl_of_match[] = {
>> -	{ .compatible = "airoha,en7581-pinctrl", .data = &en7581_pinctrl_match_data },
>> -	{ .compatible = "airoha,an7583-pinctrl", .data = &an7583_pinctrl_match_data },
>> -	{ /* sentinel */ }
>> -};
>> -MODULE_DEVICE_TABLE(of, airoha_pinctrl_of_match);
>> -
>> -static struct platform_driver airoha_pinctrl_driver = {
>> -	.probe = airoha_pinctrl_probe,
>> -	.driver = {
>> -		.name = "pinctrl-airoha",
>> -		.of_match_table = airoha_pinctrl_of_match,
>> -	},
>> -};
>> -module_platform_driver(airoha_pinctrl_driver);
>> +EXPORT_SYMBOL_GPL(airoha_pinctrl_probe);
>>  
>>  MODULE_LICENSE("GPL");
>>  MODULE_AUTHOR("Lorenzo Bianconi <lorenzo@kernel.org>");
>>  MODULE_AUTHOR("Benjamin Larsson <benjamin.larsson@genexis.eu>");
>>  MODULE_AUTHOR("Markus Gothe <markus.gothe@genexis.eu>");
>> -MODULE_DESCRIPTION("Pinctrl driver for Airoha SoC");
>> +MODULE_DESCRIPTION("Pinctrl common driver for Airoha SoC");
>> diff --git a/drivers/pinctrl/airoha/pinctrl-an7581.c b/drivers/pinctrl/airoha/pinctrl-an7581.c
>> new file mode 100644
>> index 0000000000000..522b35bbaa121
>> --- /dev/null
>> +++ b/drivers/pinctrl/airoha/pinctrl-an7581.c
>> @@ -0,0 +1,1486 @@
>> +// SPDX-License-Identifier: GPL-2.0-only
>> +/*
>> + * Author: Lorenzo Bianconi <lorenzo@kernel.org>
>> + * Author: Benjamin Larsson <benjamin.larsson@genexis.eu>
>> + * Author: Markus Gothe <markus.gothe@genexis.eu>
>> + */
>> +
>> +#include "airoha-common.h"
>> +
>> +/* MUX */
>> +#define REG_GPIO_2ND_I2C_MODE			0x0214
>> +#define GPIO_MDC_IO_MASTER_MODE_MASK		BIT(14)
>> +#define GPIO_I2C_MASTER_MODE_MODE		BIT(13)
>> +#define GPIO_I2S_MODE_MASK			BIT(12)
>> +#define GPIO_I2C_SLAVE_MODE_MODE		BIT(11)
>> +#define GPIO_LAN3_LED1_MODE_MASK		BIT(10)
>> +#define GPIO_LAN3_LED0_MODE_MASK		BIT(9)
>> +#define GPIO_LAN2_LED1_MODE_MASK		BIT(8)
>> +#define GPIO_LAN2_LED0_MODE_MASK		BIT(7)
>> +#define GPIO_LAN1_LED1_MODE_MASK		BIT(6)
>> +#define GPIO_LAN1_LED0_MODE_MASK		BIT(5)
>> +#define GPIO_LAN0_LED1_MODE_MASK		BIT(4)
>> +#define GPIO_LAN0_LED0_MODE_MASK		BIT(3)
>> +#define PON_TOD_1PPS_MODE_MASK			BIT(2)
>> +#define GSW_TOD_1PPS_MODE_MASK			BIT(1)
>> +#define GPIO_2ND_I2C_MODE_MASK			BIT(0)
>> +
>> +#define REG_GPIO_SPI_CS1_MODE			0x0218
>> +#define GPIO_PCM_SPI_CS4_MODE_MASK		BIT(21)
>> +#define GPIO_PCM_SPI_CS3_MODE_MASK		BIT(20)
>> +#define GPIO_PCM_SPI_CS2_MODE_P156_MASK		BIT(19)
>> +#define GPIO_PCM_SPI_CS2_MODE_P128_MASK		BIT(18)
>> +#define GPIO_PCM_SPI_CS1_MODE_MASK		BIT(17)
>> +#define GPIO_PCM_SPI_MODE_MASK			BIT(16)
>> +#define GPIO_PCM2_MODE_MASK			BIT(13)
>> +#define GPIO_PCM1_MODE_MASK			BIT(12)
>> +#define GPIO_PCM_INT_MODE_MASK			BIT(9)
>> +#define GPIO_PCM_RESET_MODE_MASK		BIT(8)
>> +#define GPIO_SPI_QUAD_MODE_MASK			BIT(4)
>> +#define GPIO_SPI_CS4_MODE_MASK			BIT(3)
>> +#define GPIO_SPI_CS3_MODE_MASK			BIT(2)
>> +#define GPIO_SPI_CS2_MODE_MASK			BIT(1)
>> +#define GPIO_SPI_CS1_MODE_MASK			BIT(0)
>> +
>> +#define REG_GPIO_PON_MODE			0x021c
>> +#define GPIO_PARALLEL_NAND_MODE_MASK		BIT(14)
>> +#define GPIO_SGMII_MDIO_MODE_MASK		BIT(13)
>> +#define GPIO_PCIE_RESET2_MASK			BIT(12)
>> +#define SIPO_RCLK_MODE_MASK			BIT(11)
>> +#define GPIO_PCIE_RESET1_MASK			BIT(10)
>> +#define GPIO_PCIE_RESET0_MASK			BIT(9)
>> +#define GPIO_UART5_MODE_MASK			BIT(8)
>> +#define GPIO_UART4_MODE_MASK			BIT(7)
>> +#define GPIO_HSUART_CTS_RTS_MODE_MASK		BIT(6)
>> +#define GPIO_HSUART_MODE_MASK			BIT(5)
>> +#define GPIO_UART2_CTS_RTS_MODE_MASK		BIT(4)
>> +#define GPIO_UART2_MODE_MASK			BIT(3)
>> +#define GPIO_SIPO_MODE_MASK			BIT(2)
>> +#define GPIO_EMMC_MODE_MASK			BIT(1)
>> +#define GPIO_PON_MODE_MASK			BIT(0)
>> +
>> +#define REG_NPU_UART_EN				0x0224
>> +#define JTAG_UDI_EN_MASK			BIT(4)
>> +#define JTAG_DFD_EN_MASK			BIT(3)
>> +
>> +#define REG_FORCE_GPIO_EN			0x0228
>> +#define FORCE_GPIO_EN(n)			BIT(n)
>> +
>> +/* LED MAP */
>> +#define REG_LAN_LED0_MAPPING			0x027c
>> +#define REG_LAN_LED1_MAPPING			0x0280
>> +
>> +#define LAN4_LED_MAPPING_MASK			GENMASK(18, 16)
>> +#define LAN4_PHY_LED_MAP(_n)			FIELD_PREP_CONST(LAN4_LED_MAPPING_MASK, (_n))
>> +
>> +#define LAN3_LED_MAPPING_MASK			GENMASK(14, 12)
>> +#define LAN3_PHY_LED_MAP(_n)			FIELD_PREP_CONST(LAN3_LED_MAPPING_MASK, (_n))
>> +
>> +#define LAN2_LED_MAPPING_MASK			GENMASK(10, 8)
>> +#define LAN2_PHY_LED_MAP(_n)			FIELD_PREP_CONST(LAN2_LED_MAPPING_MASK, (_n))
>> +
>> +#define LAN1_LED_MAPPING_MASK			GENMASK(6, 4)
>> +#define LAN1_PHY_LED_MAP(_n)			FIELD_PREP_CONST(LAN1_LED_MAPPING_MASK, (_n))
>> +
>> +#define LAN0_LED_MAPPING_MASK			GENMASK(2, 0)
>> +#define LAN0_PHY_LED_MAP(_n)			FIELD_PREP_CONST(LAN0_LED_MAPPING_MASK, (_n))
>> +
>> +/* CONF */
>> +#define REG_I2C_SDA_E2				0x001c
>> +#define SPI_MISO_E2_MASK			BIT(14)
>> +#define SPI_MOSI_E2_MASK			BIT(13)
>> +#define SPI_CLK_E2_MASK				BIT(12)
>> +#define SPI_CS0_E2_MASK				BIT(11)
>> +#define PCIE2_RESET_E2_MASK			BIT(10)
>> +#define PCIE1_RESET_E2_MASK			BIT(9)
>> +#define PCIE0_RESET_E2_MASK			BIT(8)
>> +#define UART1_RXD_E2_MASK			BIT(3)
>> +#define UART1_TXD_E2_MASK			BIT(2)
>> +#define I2C_SCL_E2_MASK				BIT(1)
>> +#define I2C_SDA_E2_MASK				BIT(0)
>> +
>> +#define REG_I2C_SDA_E4				0x0020
>> +#define SPI_MISO_E4_MASK			BIT(14)
>> +#define SPI_MOSI_E4_MASK			BIT(13)
>> +#define SPI_CLK_E4_MASK				BIT(12)
>> +#define SPI_CS0_E4_MASK				BIT(11)
>> +#define PCIE2_RESET_E4_MASK			BIT(10)
>> +#define PCIE1_RESET_E4_MASK			BIT(9)
>> +#define PCIE0_RESET_E4_MASK			BIT(8)
>> +#define UART1_RXD_E4_MASK			BIT(3)
>> +#define UART1_TXD_E4_MASK			BIT(2)
>> +#define I2C_SCL_E4_MASK				BIT(1)
>> +#define I2C_SDA_E4_MASK				BIT(0)
>> +
>> +#define REG_GPIO_L_E2				0x0024
>> +#define REG_GPIO_L_E4				0x0028
>> +#define REG_GPIO_H_E2				0x002c
>> +#define REG_GPIO_H_E4				0x0030
>> +
>> +#define REG_I2C_SDA_PU				0x0044
>> +#define SPI_MISO_PU_MASK			BIT(14)
>> +#define SPI_MOSI_PU_MASK			BIT(13)
>> +#define SPI_CLK_PU_MASK				BIT(12)
>> +#define SPI_CS0_PU_MASK				BIT(11)
>> +#define PCIE2_RESET_PU_MASK			BIT(10)
>> +#define PCIE1_RESET_PU_MASK			BIT(9)
>> +#define PCIE0_RESET_PU_MASK			BIT(8)
>> +#define UART1_RXD_PU_MASK			BIT(3)
>> +#define UART1_TXD_PU_MASK			BIT(2)
>> +#define I2C_SCL_PU_MASK				BIT(1)
>> +#define I2C_SDA_PU_MASK				BIT(0)
>> +
>> +#define REG_I2C_SDA_PD				0x0048
>> +#define SPI_MISO_PD_MASK			BIT(14)
>> +#define SPI_MOSI_PD_MASK			BIT(13)
>> +#define SPI_CLK_PD_MASK				BIT(12)
>> +#define SPI_CS0_PD_MASK				BIT(11)
>> +#define PCIE2_RESET_PD_MASK			BIT(10)
>> +#define PCIE1_RESET_PD_MASK			BIT(9)
>> +#define PCIE0_RESET_PD_MASK			BIT(8)
>> +#define UART1_RXD_PD_MASK			BIT(3)
>> +#define UART1_TXD_PD_MASK			BIT(2)
>> +#define I2C_SCL_PD_MASK				BIT(1)
>> +#define I2C_SDA_PD_MASK				BIT(0)
>> +
>> +#define REG_GPIO_L_PU				0x004c
>> +#define REG_GPIO_L_PD				0x0050
>> +#define REG_GPIO_H_PU				0x0054
>> +#define REG_GPIO_H_PD				0x0058
>> +
>> +#define REG_PCIE_RESET_OD			0x018c
>> +#define PCIE2_RESET_OD_MASK			BIT(2)
>> +#define PCIE1_RESET_OD_MASK			BIT(1)
>> +#define PCIE0_RESET_OD_MASK			BIT(0)
>> +
>> +/* PWM MODE CONF */
>> +#define REG_GPIO_FLASH_MODE_CFG			0x0034
>> +#define GPIO15_FLASH_MODE_CFG			BIT(15)
>> +#define GPIO14_FLASH_MODE_CFG			BIT(14)
>> +#define GPIO13_FLASH_MODE_CFG			BIT(13)
>> +#define GPIO12_FLASH_MODE_CFG			BIT(12)
>> +#define GPIO11_FLASH_MODE_CFG			BIT(11)
>> +#define GPIO10_FLASH_MODE_CFG			BIT(10)
>> +#define GPIO9_FLASH_MODE_CFG			BIT(9)
>> +#define GPIO8_FLASH_MODE_CFG			BIT(8)
>> +#define GPIO7_FLASH_MODE_CFG			BIT(7)
>> +#define GPIO6_FLASH_MODE_CFG			BIT(6)
>> +#define GPIO5_FLASH_MODE_CFG			BIT(5)
>> +#define GPIO4_FLASH_MODE_CFG			BIT(4)
>> +#define GPIO3_FLASH_MODE_CFG			BIT(3)
>> +#define GPIO2_FLASH_MODE_CFG			BIT(2)
>> +#define GPIO1_FLASH_MODE_CFG			BIT(1)
>> +#define GPIO0_FLASH_MODE_CFG			BIT(0)
>> +
>> +/* PWM MODE CONF EXT */
>> +#define REG_GPIO_FLASH_MODE_CFG_EXT		0x0068
>> +#define GPIO51_FLASH_MODE_CFG			BIT(31)
>> +#define GPIO50_FLASH_MODE_CFG			BIT(30)
>> +#define GPIO49_FLASH_MODE_CFG			BIT(29)
>> +#define GPIO48_FLASH_MODE_CFG			BIT(28)
>> +#define GPIO47_FLASH_MODE_CFG			BIT(27)
>> +#define GPIO46_FLASH_MODE_CFG			BIT(26)
>> +#define GPIO45_FLASH_MODE_CFG			BIT(25)
>> +#define GPIO44_FLASH_MODE_CFG			BIT(24)
>> +#define GPIO43_FLASH_MODE_CFG			BIT(23)
>> +#define GPIO42_FLASH_MODE_CFG			BIT(22)
>> +#define GPIO41_FLASH_MODE_CFG			BIT(21)
>> +#define GPIO40_FLASH_MODE_CFG			BIT(20)
>> +#define GPIO39_FLASH_MODE_CFG			BIT(19)
>> +#define GPIO38_FLASH_MODE_CFG			BIT(18)
>> +#define GPIO37_FLASH_MODE_CFG			BIT(17)
>> +#define GPIO36_FLASH_MODE_CFG			BIT(16)
>> +#define GPIO31_FLASH_MODE_CFG			BIT(15)
>> +#define GPIO30_FLASH_MODE_CFG			BIT(14)
>> +#define GPIO29_FLASH_MODE_CFG			BIT(13)
>> +#define GPIO28_FLASH_MODE_CFG			BIT(12)
>> +#define GPIO27_FLASH_MODE_CFG			BIT(11)
>> +#define GPIO26_FLASH_MODE_CFG			BIT(10)
>> +#define GPIO25_FLASH_MODE_CFG			BIT(9)
>> +#define GPIO24_FLASH_MODE_CFG			BIT(8)
>> +#define GPIO23_FLASH_MODE_CFG			BIT(7)
>> +#define GPIO22_FLASH_MODE_CFG			BIT(6)
>> +#define GPIO21_FLASH_MODE_CFG			BIT(5)
>> +#define GPIO20_FLASH_MODE_CFG			BIT(4)
>> +#define GPIO19_FLASH_MODE_CFG			BIT(3)
>> +#define GPIO18_FLASH_MODE_CFG			BIT(2)
>> +#define GPIO17_FLASH_MODE_CFG			BIT(1)
>> +#define GPIO16_FLASH_MODE_CFG			BIT(0)
>> +
>> +#define AIROHA_PINCTRL_GPIO(gpio, mux_val)			\
>> +	{							\
>> +		.name = (gpio),					\
>> +		.regmap[0] = {					\
>> +			AIROHA_FUNC_MUX,			\
>> +			REG_GPIO_PON_MODE,			\
>> +			(mux_val),				\
>> +			(mux_val)				\
>> +		},						\
>> +		.regmap_size = 1,				\
>> +	}
>> +
>> +#define AIROHA_PINCTRL_GPIO_EXT(gpio, mux_val, smux_val)	\
>> +	{							\
>> +		.name = (gpio),					\
>> +		.regmap[0] = {					\
>> +			AIROHA_FUNC_PWM_EXT_MUX,		\
>> +			REG_GPIO_FLASH_MODE_CFG_EXT,		\
>> +			(mux_val),				\
>> +			0					\
>> +		},						\
>> +		.regmap[1] = {					\
>> +			AIROHA_FUNC_MUX,			\
>> +			REG_GPIO_PON_MODE,			\
>> +			(smux_val),				\
>> +			(smux_val)				\
>> +		},						\
>> +		.regmap_size = 2,				\
>> +	}
>> +
>> +/* PWM */
>> +#define AIROHA_PINCTRL_PWM(gpio, mux_val)			\
>> +	{							\
>> +		.name = (gpio),					\
>> +		.regmap[0] = {					\
>> +			AIROHA_FUNC_PWM_MUX,			\
>> +			REG_GPIO_FLASH_MODE_CFG,		\
>> +			(mux_val),				\
>> +			(mux_val)				\
>> +		},						\
>> +		.regmap_size = 1,				\
>> +	}
>> +
>> +#define AIROHA_PINCTRL_PWM_EXT(gpio, mux_val)			\
>> +	{							\
>> +		.name = (gpio),					\
>> +		.regmap[0] = {					\
>> +			AIROHA_FUNC_PWM_EXT_MUX,		\
>> +			REG_GPIO_FLASH_MODE_CFG_EXT,		\
>> +			(mux_val),				\
>> +			(mux_val)				\
>> +		},						\
>> +		.regmap_size = 1,				\
>> +	}
>> +
>> +#define AIROHA_PINCTRL_PWM_EXT_SEC(gpio, mux_val, smux_val)	\
>> +	{							\
>> +		.name = (gpio),					\
>> +		.regmap[0] = {					\
>> +			AIROHA_FUNC_PWM_EXT_MUX,		\
>> +			REG_GPIO_FLASH_MODE_CFG_EXT,		\
>> +			(mux_val),				\
>> +			(mux_val)				\
>> +		},						\
>> +		.regmap[1] = {					\
>> +			AIROHA_FUNC_MUX,			\
>> +			REG_GPIO_PON_MODE,			\
>> +			(smux_val),				\
>> +			(smux_val)				\
>> +		},						\
>> +		.regmap_size = 2,				\
>> +	}
>> +
>> +#define AIROHA_PINCTRL_PHY_LED0(gpio, mux_val, map_mask, map_val)	\
>> +	{								\
>> +		.name = (gpio),						\
>> +		.regmap[0] = {						\
>> +			AIROHA_FUNC_MUX,				\
>> +			REG_GPIO_2ND_I2C_MODE,				\
>> +			(mux_val),					\
>> +			(mux_val),					\
>> +		},							\
>> +		.regmap[1] = {						\
>> +			AIROHA_FUNC_MUX,				\
>> +			REG_LAN_LED0_MAPPING,				\
>> +			(map_mask),					\
>> +			(map_val),					\
>> +		},							\
>> +		.regmap_size = 2,					\
>> +	}
>> +
>> +#define AIROHA_PINCTRL_PHY_LED1(gpio, mux_val, map_mask, map_val)	\
>> +	{								\
>> +		.name = (gpio),						\
>> +		.regmap[0] = {						\
>> +			AIROHA_FUNC_MUX,				\
>> +			REG_GPIO_2ND_I2C_MODE,				\
>> +			(mux_val),					\
>> +			(mux_val),					\
>> +		},							\
>> +		.regmap[1] = {						\
>> +			AIROHA_FUNC_MUX,				\
>> +			REG_LAN_LED1_MAPPING,				\
>> +			(map_mask),					\
>> +			(map_val),					\
>> +		},							\
>> +		.regmap_size = 2,					\
>> +	}
>> +
>> +static struct pinctrl_pin_desc en7581_pinctrl_pins[] = {
>> +	PINCTRL_PIN(0, "uart1_txd"),
>> +	PINCTRL_PIN(1, "uart1_rxd"),
>> +	PINCTRL_PIN(2, "i2c_scl"),
>> +	PINCTRL_PIN(3, "i2c_sda"),
>> +	PINCTRL_PIN(4, "spi_cs0"),
>> +	PINCTRL_PIN(5, "spi_clk"),
>> +	PINCTRL_PIN(6, "spi_mosi"),
>> +	PINCTRL_PIN(7, "spi_miso"),
>> +	PINCTRL_PIN(13, "gpio0"),
>> +	PINCTRL_PIN(14, "gpio1"),
>> +	PINCTRL_PIN(15, "gpio2"),
>> +	PINCTRL_PIN(16, "gpio3"),
>> +	PINCTRL_PIN(17, "gpio4"),
>> +	PINCTRL_PIN(18, "gpio5"),
>> +	PINCTRL_PIN(19, "gpio6"),
>> +	PINCTRL_PIN(20, "gpio7"),
>> +	PINCTRL_PIN(21, "gpio8"),
>> +	PINCTRL_PIN(22, "gpio9"),
>> +	PINCTRL_PIN(23, "gpio10"),
>> +	PINCTRL_PIN(24, "gpio11"),
>> +	PINCTRL_PIN(25, "gpio12"),
>> +	PINCTRL_PIN(26, "gpio13"),
>> +	PINCTRL_PIN(27, "gpio14"),
>> +	PINCTRL_PIN(28, "gpio15"),
>> +	PINCTRL_PIN(29, "gpio16"),
>> +	PINCTRL_PIN(30, "gpio17"),
>> +	PINCTRL_PIN(31, "gpio18"),
>> +	PINCTRL_PIN(32, "gpio19"),
>> +	PINCTRL_PIN(33, "gpio20"),
>> +	PINCTRL_PIN(34, "gpio21"),
>> +	PINCTRL_PIN(35, "gpio22"),
>> +	PINCTRL_PIN(36, "gpio23"),
>> +	PINCTRL_PIN(37, "gpio24"),
>> +	PINCTRL_PIN(38, "gpio25"),
>> +	PINCTRL_PIN(39, "gpio26"),
>> +	PINCTRL_PIN(40, "gpio27"),
>> +	PINCTRL_PIN(41, "gpio28"),
>> +	PINCTRL_PIN(42, "gpio29"),
>> +	PINCTRL_PIN(43, "gpio30"),
>> +	PINCTRL_PIN(44, "gpio31"),
>> +	PINCTRL_PIN(45, "gpio32"),
>> +	PINCTRL_PIN(46, "gpio33"),
>> +	PINCTRL_PIN(47, "gpio34"),
>> +	PINCTRL_PIN(48, "gpio35"),
>> +	PINCTRL_PIN(49, "gpio36"),
>> +	PINCTRL_PIN(50, "gpio37"),
>> +	PINCTRL_PIN(51, "gpio38"),
>> +	PINCTRL_PIN(52, "gpio39"),
>> +	PINCTRL_PIN(53, "gpio40"),
>> +	PINCTRL_PIN(54, "gpio41"),
>> +	PINCTRL_PIN(55, "gpio42"),
>> +	PINCTRL_PIN(56, "gpio43"),
>> +	PINCTRL_PIN(57, "gpio44"),
>> +	PINCTRL_PIN(58, "gpio45"),
>> +	PINCTRL_PIN(59, "gpio46"),
>> +	PINCTRL_PIN(60, "pcie_reset0"),
>> +	PINCTRL_PIN(61, "pcie_reset1"),
>> +	PINCTRL_PIN(62, "pcie_reset2"),
>> +};
>> +
>> +static const int en7581_pon_pins[] = { 49, 50, 51, 52, 53, 54 };
>> +static const int en7581_pon_tod_1pps_pins[] = { 46 };
>> +static const int en7581_gsw_tod_1pps_pins[] = { 46 };
>> +static const int en7581_sipo_pins[] = { 16, 17 };
>> +static const int en7581_sipo_rclk_pins[] = { 16, 17, 43 };
>> +static const int en7581_mdio_pins[] = { 14, 15 };
>> +static const int en7581_uart2_pins[] = { 48, 55 };
>> +static const int en7581_uart2_cts_rts_pins[] = { 46, 47 };
>> +static const int en7581_hsuart_pins[] = { 28, 29 };
>> +static const int en7581_hsuart_cts_rts_pins[] = { 26, 27 };
>> +static const int en7581_uart4_pins[] = { 38, 39 };
>> +static const int en7581_uart5_pins[] = { 18, 19 };
>> +static const int en7581_i2c0_pins[] = { 2, 3 };
>> +static const int en7581_i2c1_pins[] = { 14, 15 };
>> +static const int en7581_jtag_udi_pins[] = { 16, 17, 18, 19, 20 };
>> +static const int en7581_jtag_dfd_pins[] = { 16, 17, 18, 19, 20 };
>> +static const int en7581_i2s_pins[] = { 26, 27, 28, 29 };
>> +static const int en7581_pcm1_pins[] = { 22, 23, 24, 25 };
>> +static const int en7581_pcm2_pins[] = { 18, 19, 20, 21 };
>> +static const int en7581_spi_quad_pins[] = { 32, 33 };
>> +static const int en7581_spi_pins[] = { 4, 5, 6, 7 };
>> +static const int en7581_spi_cs1_pins[] = { 34 };
>> +static const int en7581_pcm_spi_pins[] = { 18, 19, 20, 21, 22, 23, 24, 25 };
>> +static const int en7581_pcm_spi_int_pins[] = { 14 };
>> +static const int en7581_pcm_spi_rst_pins[] = { 15 };
>> +static const int en7581_pcm_spi_cs1_pins[] = { 43 };
>> +static const int en7581_pcm_spi_cs2_pins[] = { 40 };
>> +static const int en7581_pcm_spi_cs2_p128_pins[] = { 40 };
>> +static const int en7581_pcm_spi_cs2_p156_pins[] = { 40 };
>> +static const int en7581_pcm_spi_cs3_pins[] = { 41 };
>> +static const int en7581_pcm_spi_cs4_pins[] = { 42 };
>> +static const int en7581_emmc_pins[] = {
>> +	4, 5, 6, 30, 31, 32, 33, 34, 35, 36, 37
>> +};
>> +static const int en7581_pnand_pins[] = {
>> +	4, 5, 6, 7, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42
>> +};
>> +static const int en7581_gpio0_pins[] = { 13 };
>> +static const int en7581_gpio1_pins[] = { 14 };
>> +static const int en7581_gpio2_pins[] = { 15 };
>> +static const int en7581_gpio3_pins[] = { 16 };
>> +static const int en7581_gpio4_pins[] = { 17 };
>> +static const int en7581_gpio5_pins[] = { 18 };
>> +static const int en7581_gpio6_pins[] = { 19 };
>> +static const int en7581_gpio7_pins[] = { 20 };
>> +static const int en7581_gpio8_pins[] = { 21 };
>> +static const int en7581_gpio9_pins[] = { 22 };
>> +static const int en7581_gpio10_pins[] = { 23 };
>> +static const int en7581_gpio11_pins[] = { 24 };
>> +static const int en7581_gpio12_pins[] = { 25 };
>> +static const int en7581_gpio13_pins[] = { 26 };
>> +static const int en7581_gpio14_pins[] = { 27 };
>> +static const int en7581_gpio15_pins[] = { 28 };
>> +static const int en7581_gpio16_pins[] = { 29 };
>> +static const int en7581_gpio17_pins[] = { 30 };
>> +static const int en7581_gpio18_pins[] = { 31 };
>> +static const int en7581_gpio19_pins[] = { 32 };
>> +static const int en7581_gpio20_pins[] = { 33 };
>> +static const int en7581_gpio21_pins[] = { 34 };
>> +static const int en7581_gpio22_pins[] = { 35 };
>> +static const int en7581_gpio23_pins[] = { 36 };
>> +static const int en7581_gpio24_pins[] = { 37 };
>> +static const int en7581_gpio25_pins[] = { 38 };
>> +static const int en7581_gpio26_pins[] = { 39 };
>> +static const int en7581_gpio27_pins[] = { 40 };
>> +static const int en7581_gpio28_pins[] = { 41 };
>> +static const int en7581_gpio29_pins[] = { 42 };
>> +static const int en7581_gpio30_pins[] = { 43 };
>> +static const int en7581_gpio31_pins[] = { 44 };
>> +static const int en7581_gpio32_pins[] = { 45 };
>> +static const int en7581_gpio33_pins[] = { 46 };
>> +static const int en7581_gpio34_pins[] = { 47 };
>> +static const int en7581_gpio35_pins[] = { 48 };
>> +static const int en7581_gpio36_pins[] = { 49 };
>> +static const int en7581_gpio37_pins[] = { 50 };
>> +static const int en7581_gpio38_pins[] = { 51 };
>> +static const int en7581_gpio39_pins[] = { 52 };
>> +static const int en7581_gpio40_pins[] = { 53 };
>> +static const int en7581_gpio41_pins[] = { 54 };
>> +static const int en7581_gpio42_pins[] = { 55 };
>> +static const int en7581_gpio43_pins[] = { 56 };
>> +static const int en7581_gpio44_pins[] = { 57 };
>> +static const int en7581_gpio45_pins[] = { 58 };
>> +static const int en7581_gpio46_pins[] = { 59 };
>> +static const int en7581_gpio47_pins[] = { 60 };
>> +static const int en7581_gpio48_pins[] = { 61 };
>> +static const int en7581_gpio49_pins[] = { 62 };
>> +static const int en7581_pcie_reset0_pins[] = { 60 };
>> +static const int en7581_pcie_reset1_pins[] = { 61 };
>> +static const int en7581_pcie_reset2_pins[] = { 62 };
>> +
>> +static const struct pingroup en7581_pinctrl_groups[] = {
>> +	PINCTRL_PIN_GROUP("pon", en7581_pon),
>> +	PINCTRL_PIN_GROUP("pon_tod_1pps", en7581_pon_tod_1pps),
>> +	PINCTRL_PIN_GROUP("gsw_tod_1pps", en7581_gsw_tod_1pps),
>> +	PINCTRL_PIN_GROUP("sipo", en7581_sipo),
>> +	PINCTRL_PIN_GROUP("sipo_rclk", en7581_sipo_rclk),
>> +	PINCTRL_PIN_GROUP("mdio", en7581_mdio),
>> +	PINCTRL_PIN_GROUP("uart2", en7581_uart2),
>> +	PINCTRL_PIN_GROUP("uart2_cts_rts", en7581_uart2_cts_rts),
>> +	PINCTRL_PIN_GROUP("hsuart", en7581_hsuart),
>> +	PINCTRL_PIN_GROUP("hsuart_cts_rts", en7581_hsuart_cts_rts),
>> +	PINCTRL_PIN_GROUP("uart4", en7581_uart4),
>> +	PINCTRL_PIN_GROUP("uart5", en7581_uart5),
>> +	PINCTRL_PIN_GROUP("i2c0", en7581_i2c0),
>> +	PINCTRL_PIN_GROUP("i2c1", en7581_i2c1),
>> +	PINCTRL_PIN_GROUP("jtag_udi", en7581_jtag_udi),
>> +	PINCTRL_PIN_GROUP("jtag_dfd", en7581_jtag_dfd),
>> +	PINCTRL_PIN_GROUP("i2s", en7581_i2s),
>> +	PINCTRL_PIN_GROUP("pcm1", en7581_pcm1),
>> +	PINCTRL_PIN_GROUP("pcm2", en7581_pcm2),
>> +	PINCTRL_PIN_GROUP("spi", en7581_spi),
>> +	PINCTRL_PIN_GROUP("spi_quad", en7581_spi_quad),
>> +	PINCTRL_PIN_GROUP("spi_cs1", en7581_spi_cs1),
>> +	PINCTRL_PIN_GROUP("pcm_spi", en7581_pcm_spi),
>> +	PINCTRL_PIN_GROUP("pcm_spi_int", en7581_pcm_spi_int),
>> +	PINCTRL_PIN_GROUP("pcm_spi_rst", en7581_pcm_spi_rst),
>> +	PINCTRL_PIN_GROUP("pcm_spi_cs1", en7581_pcm_spi_cs1),
>> +	PINCTRL_PIN_GROUP("pcm_spi_cs2_p128", en7581_pcm_spi_cs2_p128),
>> +	PINCTRL_PIN_GROUP("pcm_spi_cs2_p156", en7581_pcm_spi_cs2_p156),
>> +	PINCTRL_PIN_GROUP("pcm_spi_cs2", en7581_pcm_spi_cs2),
>> +	PINCTRL_PIN_GROUP("pcm_spi_cs3", en7581_pcm_spi_cs3),
>> +	PINCTRL_PIN_GROUP("pcm_spi_cs4", en7581_pcm_spi_cs4),
>> +	PINCTRL_PIN_GROUP("emmc", en7581_emmc),
>> +	PINCTRL_PIN_GROUP("pnand", en7581_pnand),
>> +	PINCTRL_PIN_GROUP("gpio0", en7581_gpio0),
>> +	PINCTRL_PIN_GROUP("gpio1", en7581_gpio1),
>> +	PINCTRL_PIN_GROUP("gpio2", en7581_gpio2),
>> +	PINCTRL_PIN_GROUP("gpio3", en7581_gpio3),
>> +	PINCTRL_PIN_GROUP("gpio4", en7581_gpio4),
>> +	PINCTRL_PIN_GROUP("gpio5", en7581_gpio5),
>> +	PINCTRL_PIN_GROUP("gpio6", en7581_gpio6),
>> +	PINCTRL_PIN_GROUP("gpio7", en7581_gpio7),
>> +	PINCTRL_PIN_GROUP("gpio8", en7581_gpio8),
>> +	PINCTRL_PIN_GROUP("gpio9", en7581_gpio9),
>> +	PINCTRL_PIN_GROUP("gpio10", en7581_gpio10),
>> +	PINCTRL_PIN_GROUP("gpio11", en7581_gpio11),
>> +	PINCTRL_PIN_GROUP("gpio12", en7581_gpio12),
>> +	PINCTRL_PIN_GROUP("gpio13", en7581_gpio13),
>> +	PINCTRL_PIN_GROUP("gpio14", en7581_gpio14),
>> +	PINCTRL_PIN_GROUP("gpio15", en7581_gpio15),
>> +	PINCTRL_PIN_GROUP("gpio16", en7581_gpio16),
>> +	PINCTRL_PIN_GROUP("gpio17", en7581_gpio17),
>> +	PINCTRL_PIN_GROUP("gpio18", en7581_gpio18),
>> +	PINCTRL_PIN_GROUP("gpio19", en7581_gpio19),
>> +	PINCTRL_PIN_GROUP("gpio20", en7581_gpio20),
>> +	PINCTRL_PIN_GROUP("gpio21", en7581_gpio21),
>> +	PINCTRL_PIN_GROUP("gpio22", en7581_gpio22),
>> +	PINCTRL_PIN_GROUP("gpio23", en7581_gpio23),
>> +	PINCTRL_PIN_GROUP("gpio24", en7581_gpio24),
>> +	PINCTRL_PIN_GROUP("gpio25", en7581_gpio25),
>> +	PINCTRL_PIN_GROUP("gpio26", en7581_gpio26),
>> +	PINCTRL_PIN_GROUP("gpio27", en7581_gpio27),
>> +	PINCTRL_PIN_GROUP("gpio28", en7581_gpio28),
>> +	PINCTRL_PIN_GROUP("gpio29", en7581_gpio29),
>> +	PINCTRL_PIN_GROUP("gpio30", en7581_gpio30),
>> +	PINCTRL_PIN_GROUP("gpio31", en7581_gpio31),
>> +	PINCTRL_PIN_GROUP("gpio32", en7581_gpio32),
>> +	PINCTRL_PIN_GROUP("gpio33", en7581_gpio33),
>> +	PINCTRL_PIN_GROUP("gpio34", en7581_gpio34),
>> +	PINCTRL_PIN_GROUP("gpio35", en7581_gpio35),
>> +	PINCTRL_PIN_GROUP("gpio36", en7581_gpio36),
>> +	PINCTRL_PIN_GROUP("gpio37", en7581_gpio37),
>> +	PINCTRL_PIN_GROUP("gpio38", en7581_gpio38),
>> +	PINCTRL_PIN_GROUP("gpio39", en7581_gpio39),
>> +	PINCTRL_PIN_GROUP("gpio40", en7581_gpio40),
>> +	PINCTRL_PIN_GROUP("gpio41", en7581_gpio41),
>> +	PINCTRL_PIN_GROUP("gpio42", en7581_gpio42),
>> +	PINCTRL_PIN_GROUP("gpio43", en7581_gpio43),
>> +	PINCTRL_PIN_GROUP("gpio44", en7581_gpio44),
>> +	PINCTRL_PIN_GROUP("gpio45", en7581_gpio45),
>> +	PINCTRL_PIN_GROUP("gpio46", en7581_gpio46),
>> +	PINCTRL_PIN_GROUP("gpio47", en7581_gpio47),
>> +	PINCTRL_PIN_GROUP("gpio48", en7581_gpio48),
>> +	PINCTRL_PIN_GROUP("gpio49", en7581_gpio49),
>> +	PINCTRL_PIN_GROUP("pcie_reset0", en7581_pcie_reset0),
>> +	PINCTRL_PIN_GROUP("pcie_reset1", en7581_pcie_reset1),
>> +	PINCTRL_PIN_GROUP("pcie_reset2", en7581_pcie_reset2),
>> +};
>> +
>> +static const char *const pon_groups[] = { "pon" };
>> +static const char *const tod_1pps_groups[] = {
>> +	"pon_tod_1pps", "gsw_tod_1pps"
>> +};
>> +static const char *const sipo_groups[] = { "sipo", "sipo_rclk" };
>> +static const char *const mdio_groups[] = { "mdio" };
>> +static const char *const uart_groups[] = {
>> +	"uart2", "uart2_cts_rts", "hsuart", "hsuart_cts_rts",
>> +	"uart4", "uart5"
>> +};
>> +static const char *const i2c_groups[] = { "i2c1" };
>> +static const char *const jtag_groups[] = { "jtag_udi", "jtag_dfd" };
>> +static const char *const pcm_groups[] = { "pcm1", "pcm2" };
>> +static const char *const spi_groups[] = { "spi_quad", "spi_cs1" };
>> +static const char *const pcm_spi_groups[] = {
>> +	"pcm_spi", "pcm_spi_int", "pcm_spi_rst", "pcm_spi_cs1",
>> +	"pcm_spi_cs2_p156", "pcm_spi_cs2_p128", "pcm_spi_cs3",
>> +	"pcm_spi_cs4"
>> +};
>> +static const char *const i2s_groups[] = { "i2s" };
>> +static const char *const emmc_groups[] = { "emmc" };
>> +static const char *const pnand_groups[] = { "pnand" };
>> +static const char *const gpio_groups[] = { "gpio47", "gpio48", "gpio49" };
>> +static const char *const pcie_reset_groups[] = {
>> +	"pcie_reset0", "pcie_reset1", "pcie_reset2"
>> +};
>> +static const char *const pwm_groups[] = {
>> +	"gpio0",  "gpio1",  "gpio2",  "gpio3",  "gpio4",  "gpio5",
>> +	"gpio6",  "gpio7",  "gpio8",  "gpio9",  "gpio10", "gpio11",
>> +	"gpio12", "gpio13", "gpio14", "gpio15", "gpio16", "gpio17",
>> +	"gpio18", "gpio19", "gpio20", "gpio21", "gpio22", "gpio23",
>> +	"gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29",
>> +	"gpio30", "gpio31", "gpio36", "gpio37", "gpio38", "gpio39",
>> +	"gpio40", "gpio41", "gpio42", "gpio43", "gpio44", "gpio45",
>> +	"gpio46", "gpio47", "gpio48", "gpio49"
>> +};
>> +static const char *const phy1_led0_groups[] = {
>> +	"gpio33", "gpio34", "gpio35", "gpio42"
>> +};
>> +static const char *const phy2_led0_groups[] = {
>> +	"gpio33", "gpio34", "gpio35", "gpio42"
>> +};
>> +static const char *const phy3_led0_groups[] = {
>> +	"gpio33", "gpio34", "gpio35", "gpio42"
>> +};
>> +static const char *const phy4_led0_groups[] = {
>> +	"gpio33", "gpio34", "gpio35", "gpio42"
>> +};
>> +static const char *const phy1_led1_groups[] = {
>> +	"gpio43", "gpio44", "gpio45", "gpio46"
>> +};
>> +static const char *const phy2_led1_groups[] = {
>> +	"gpio43", "gpio44", "gpio45", "gpio46"
>> +};
>> +static const char *const phy3_led1_groups[] = {
>> +	"gpio43", "gpio44", "gpio45", "gpio46"
>> +};
>> +static const char *const phy4_led1_groups[] = {
>> +	"gpio43", "gpio44", "gpio45", "gpio46"
>> +};
>> +
>> +static const struct airoha_pinctrl_func_group pon_func_group[] = {
>> +	{
>> +		.name = "pon",
>> +		.regmap[0] = {
>> +			AIROHA_FUNC_MUX,
>> +			REG_GPIO_PON_MODE,
>> +			GPIO_PON_MODE_MASK,
>> +			GPIO_PON_MODE_MASK
>> +		},
>> +		.regmap_size = 1,
>> +	},
>> +};
>> +
>> +static const struct airoha_pinctrl_func_group tod_1pps_func_group[] = {
>> +	{
>> +		.name = "pon_tod_1pps",
>> +		.regmap[0] = {
>> +			AIROHA_FUNC_MUX,
>> +			REG_GPIO_2ND_I2C_MODE,
>> +			PON_TOD_1PPS_MODE_MASK,
>> +			PON_TOD_1PPS_MODE_MASK
>> +		},
>> +		.regmap_size = 1,
>> +	}, {
>> +		.name = "gsw_tod_1pps",
>> +		.regmap[0] = {
>> +			AIROHA_FUNC_MUX,
>> +			REG_GPIO_2ND_I2C_MODE,
>> +			GSW_TOD_1PPS_MODE_MASK,
>> +			GSW_TOD_1PPS_MODE_MASK
>> +		},
>> +		.regmap_size = 1,
>> +	},
>> +};
>> +
>> +static const struct airoha_pinctrl_func_group sipo_func_group[] = {
>> +	{
>> +		.name = "sipo",
>> +		.regmap[0] = {
>> +			AIROHA_FUNC_MUX,
>> +			REG_GPIO_PON_MODE,
>> +			GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK,
>> +			GPIO_SIPO_MODE_MASK
>> +		},
>> +		.regmap_size = 1,
>> +	}, {
>> +		.name = "sipo_rclk",
>> +		.regmap[0] = {
>> +			AIROHA_FUNC_MUX,
>> +			REG_GPIO_PON_MODE,
>> +			GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK,
>> +			GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK
>> +		},
>> +		.regmap_size = 1,
>> +	},
>> +};
>> +
>> +static const struct airoha_pinctrl_func_group mdio_func_group[] = {
>> +	{
>> +		.name = "mdio",
>> +		.regmap[0] = {
>> +			AIROHA_FUNC_MUX,
>> +			REG_GPIO_2ND_I2C_MODE,
>> +			GPIO_MDC_IO_MASTER_MODE_MASK,
>> +			GPIO_MDC_IO_MASTER_MODE_MASK
>> +		},
>> +		.regmap[1] = {
>> +			AIROHA_FUNC_MUX,
>> +			REG_FORCE_GPIO_EN,
>> +			FORCE_GPIO_EN(1) | FORCE_GPIO_EN(2),
>> +			FORCE_GPIO_EN(1) | FORCE_GPIO_EN(2)
>> +		},
>> +		.regmap_size = 2,
>> +	},
>> +};
>> +
>> +static const struct airoha_pinctrl_func_group uart_func_group[] = {
>> +	{
>> +		.name = "uart2",
>> +		.regmap[0] = {
>> +			AIROHA_FUNC_MUX,
>> +			REG_GPIO_PON_MODE,
>> +			GPIO_UART2_MODE_MASK,
>> +			GPIO_UART2_MODE_MASK
>> +		},
>> +		.regmap_size = 1,
>> +	}, {
>> +		.name = "uart2_cts_rts",
>> +		.regmap[0] = {
>> +			AIROHA_FUNC_MUX,
>> +			REG_GPIO_PON_MODE,
>> +			GPIO_UART2_MODE_MASK | GPIO_UART2_CTS_RTS_MODE_MASK,
>> +			GPIO_UART2_MODE_MASK | GPIO_UART2_CTS_RTS_MODE_MASK
>> +		},
>> +		.regmap_size = 1,
>> +	}, {
>> +		.name = "hsuart",
>> +		.regmap[0] = {
>> +			AIROHA_FUNC_MUX,
>> +			REG_GPIO_PON_MODE,
>> +			GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK,
>> +			GPIO_HSUART_MODE_MASK
>> +		},
>> +		.regmap_size = 1,
>> +	},
>> +	{
>> +		.name = "hsuart_cts_rts",
>> +		.regmap[0] = {
>> +			AIROHA_FUNC_MUX,
>> +			REG_GPIO_PON_MODE,
>> +			GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK,
>> +			GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK
>> +		},
>> +		.regmap_size = 1,
>> +	}, {
>> +		.name = "uart4",
>> +		.regmap[0] = {
>> +			AIROHA_FUNC_MUX,
>> +			REG_GPIO_PON_MODE,
>> +			GPIO_UART4_MODE_MASK,
>> +			GPIO_UART4_MODE_MASK
>> +		},
>> +		.regmap_size = 1,
>> +	}, {
>> +		.name = "uart5",
>> +		.regmap[0] = {
>> +			AIROHA_FUNC_MUX,
>> +			REG_GPIO_PON_MODE,
>> +			GPIO_UART5_MODE_MASK,
>> +			GPIO_UART5_MODE_MASK
>> +		},
>> +		.regmap_size = 1,
>> +	},
>> +};
>> +
>> +static const struct airoha_pinctrl_func_group i2c_func_group[] = {
>> +	{
>> +		.name = "i2c1",
>> +		.regmap[0] = {
>> +			AIROHA_FUNC_MUX,
>> +			REG_GPIO_2ND_I2C_MODE,
>> +			GPIO_2ND_I2C_MODE_MASK,
>> +			GPIO_2ND_I2C_MODE_MASK
>> +		},
>> +		.regmap_size = 1,
>> +	},
>> +};
>> +
>> +static const struct airoha_pinctrl_func_group jtag_func_group[] = {
>> +	{
>> +		.name = "jtag_udi",
>> +		.regmap[0] = {
>> +			AIROHA_FUNC_MUX,
>> +			REG_NPU_UART_EN,
>> +			JTAG_UDI_EN_MASK,
>> +			JTAG_UDI_EN_MASK
>> +		},
>> +		.regmap_size = 1,
>> +	}, {
>> +		.name = "jtag_dfd",
>> +		.regmap[0] = {
>> +			AIROHA_FUNC_MUX,
>> +			REG_NPU_UART_EN,
>> +			JTAG_DFD_EN_MASK,
>> +			JTAG_DFD_EN_MASK
>> +		},
>> +		.regmap_size = 1,
>> +	},
>> +};
>> +
>> +static const struct airoha_pinctrl_func_group pcm_func_group[] = {
>> +	{
>> +		.name = "pcm1",
>> +		.regmap[0] = {
>> +			AIROHA_FUNC_MUX,
>> +			REG_GPIO_SPI_CS1_MODE,
>> +			GPIO_PCM1_MODE_MASK,
>> +			GPIO_PCM1_MODE_MASK
>> +		},
>> +		.regmap_size = 1,
>> +	}, {
>> +		.name = "pcm2",
>> +		.regmap[0] = {
>> +			AIROHA_FUNC_MUX,
>> +			REG_GPIO_SPI_CS1_MODE,
>> +			GPIO_PCM2_MODE_MASK,
>> +			GPIO_PCM2_MODE_MASK
>> +		},
>> +		.regmap_size = 1,
>> +	},
>> +};
>> +
>> +static const struct airoha_pinctrl_func_group spi_func_group[] = {
>> +	{
>> +		.name = "spi_quad",
>> +		.regmap[0] = {
>> +			AIROHA_FUNC_MUX,
>> +			REG_GPIO_SPI_CS1_MODE,
>> +			GPIO_SPI_QUAD_MODE_MASK,
>> +			GPIO_SPI_QUAD_MODE_MASK
>> +		},
>> +		.regmap_size = 1,
>> +	}, {
>> +		.name = "spi_cs1",
>> +		.regmap[0] = {
>> +			AIROHA_FUNC_MUX,
>> +			REG_GPIO_SPI_CS1_MODE,
>> +			GPIO_SPI_CS1_MODE_MASK,
>> +			GPIO_SPI_CS1_MODE_MASK
>> +		},
>> +		.regmap_size = 1,
>> +	}, {
>> +		.name = "spi_cs2",
>> +		.regmap[0] = {
>> +			AIROHA_FUNC_MUX,
>> +			REG_GPIO_SPI_CS1_MODE,
>> +			GPIO_SPI_CS2_MODE_MASK,
>> +			GPIO_SPI_CS2_MODE_MASK
>> +		},
>> +		.regmap_size = 1,
>> +	}, {
>> +		.name = "spi_cs3",
>> +		.regmap[0] = {
>> +			AIROHA_FUNC_MUX,
>> +			REG_GPIO_SPI_CS1_MODE,
>> +			GPIO_SPI_CS3_MODE_MASK,
>> +			GPIO_SPI_CS3_MODE_MASK
>> +		},
>> +		.regmap_size = 1,
>> +	}, {
>> +		.name = "spi_cs4",
>> +		.regmap[0] = {
>> +			AIROHA_FUNC_MUX,
>> +			REG_GPIO_SPI_CS1_MODE,
>> +			GPIO_SPI_CS4_MODE_MASK,
>> +			GPIO_SPI_CS4_MODE_MASK
>> +		},
>> +		.regmap_size = 1,
>> +	},
>> +};
>> +
>> +static const struct airoha_pinctrl_func_group pcm_spi_func_group[] = {
>> +	{
>> +		.name = "pcm_spi",
>> +		.regmap[0] = {
>> +			AIROHA_FUNC_MUX,
>> +			REG_GPIO_SPI_CS1_MODE,
>> +			GPIO_PCM_SPI_MODE_MASK,
>> +			GPIO_PCM_SPI_MODE_MASK
>> +		},
>> +		.regmap_size = 1,
>> +	}, {
>> +		.name = "pcm_spi_int",
>> +		.regmap[0] = {
>> +			AIROHA_FUNC_MUX,
>> +			REG_GPIO_SPI_CS1_MODE,
>> +			GPIO_PCM_INT_MODE_MASK,
>> +			GPIO_PCM_INT_MODE_MASK
>> +		},
>> +		.regmap_size = 1,
>> +	}, {
>> +		.name = "pcm_spi_rst",
>> +		.regmap[0] = {
>> +			AIROHA_FUNC_MUX,
>> +			REG_GPIO_SPI_CS1_MODE,
>> +			GPIO_PCM_RESET_MODE_MASK,
>> +			GPIO_PCM_RESET_MODE_MASK
>> +		},
>> +		.regmap_size = 1,
>> +	}, {
>> +		.name = "pcm_spi_cs1",
>> +		.regmap[0] = {
>> +			AIROHA_FUNC_MUX,
>> +			REG_GPIO_SPI_CS1_MODE,
>> +			GPIO_PCM_SPI_CS1_MODE_MASK,
>> +			GPIO_PCM_SPI_CS1_MODE_MASK
>> +		},
>> +		.regmap_size = 1,
>> +	}, {
>> +		.name = "pcm_spi_cs2_p128",
>> +		.regmap[0] = {
>> +			AIROHA_FUNC_MUX,
>> +			REG_GPIO_SPI_CS1_MODE,
>> +			GPIO_PCM_SPI_CS2_MODE_P128_MASK,
>> +			GPIO_PCM_SPI_CS2_MODE_P128_MASK
>> +		},
>> +		.regmap_size = 1,
>> +	}, {
>> +		.name = "pcm_spi_cs2_p156",
>> +		.regmap[0] = {
>> +			AIROHA_FUNC_MUX,
>> +			REG_GPIO_SPI_CS1_MODE,
>> +			GPIO_PCM_SPI_CS2_MODE_P156_MASK,
>> +			GPIO_PCM_SPI_CS2_MODE_P156_MASK
>> +		},
>> +		.regmap_size = 1,
>> +	}, {
>> +		.name = "pcm_spi_cs3",
>> +		.regmap[0] = {
>> +			AIROHA_FUNC_MUX,
>> +			REG_GPIO_SPI_CS1_MODE,
>> +			GPIO_PCM_SPI_CS3_MODE_MASK,
>> +			GPIO_PCM_SPI_CS3_MODE_MASK
>> +		},
>> +		.regmap_size = 1,
>> +	}, {
>> +		.name = "pcm_spi_cs4",
>> +		.regmap[0] = {
>> +			AIROHA_FUNC_MUX,
>> +			REG_GPIO_SPI_CS1_MODE,
>> +			GPIO_PCM_SPI_CS4_MODE_MASK,
>> +			GPIO_PCM_SPI_CS4_MODE_MASK
>> +		},
>> +		.regmap_size = 1,
>> +	},
>> +};
>> +
>> +static const struct airoha_pinctrl_func_group i2s_func_group[] = {
>> +	{
>> +		.name = "i2s",
>> +		.regmap[0] = {
>> +			AIROHA_FUNC_MUX,
>> +			REG_GPIO_2ND_I2C_MODE,
>> +			GPIO_I2S_MODE_MASK,
>> +			GPIO_I2S_MODE_MASK
>> +		},
>> +		.regmap_size = 1,
>> +	},
>> +};
>> +
>> +static const struct airoha_pinctrl_func_group emmc_func_group[] = {
>> +	{
>> +		.name = "emmc",
>> +		.regmap[0] = {
>> +			AIROHA_FUNC_MUX,
>> +			REG_GPIO_PON_MODE,
>> +			GPIO_EMMC_MODE_MASK,
>> +			GPIO_EMMC_MODE_MASK
>> +		},
>> +		.regmap_size = 1,
>> +	},
>> +};
>> +
>> +static const struct airoha_pinctrl_func_group pnand_func_group[] = {
>> +	{
>> +		.name = "pnand",
>> +		.regmap[0] = {
>> +			AIROHA_FUNC_MUX,
>> +			REG_GPIO_PON_MODE,
>> +			GPIO_PARALLEL_NAND_MODE_MASK,
>> +			GPIO_PARALLEL_NAND_MODE_MASK
>> +		},
>> +		.regmap_size = 1,
>> +	},
>> +};
>> +
>> +static const struct airoha_pinctrl_func_group gpio_func_group[] = {
>> +	AIROHA_PINCTRL_GPIO_EXT("gpio47", GPIO47_FLASH_MODE_CFG,
>> +				GPIO_PCIE_RESET0_MASK),
>> +	AIROHA_PINCTRL_GPIO_EXT("gpio48", GPIO48_FLASH_MODE_CFG,
>> +				GPIO_PCIE_RESET1_MASK),
>> +	AIROHA_PINCTRL_GPIO_EXT("gpio49", GPIO49_FLASH_MODE_CFG,
>> +				GPIO_PCIE_RESET2_MASK),
>> +};
>> +
>> +static const struct airoha_pinctrl_func_group pcie_reset_func_group[] = {
>> +	{
>> +		.name = "pcie_reset0",
>> +		.regmap[0] = {
>> +			AIROHA_FUNC_MUX,
>> +			REG_GPIO_PON_MODE,
>> +			GPIO_PCIE_RESET0_MASK,
>> +			0
>> +		},
>> +		.regmap_size = 1,
>> +	}, {
>> +		.name = "pcie_reset1",
>> +		.regmap[0] = {
>> +			AIROHA_FUNC_MUX,
>> +			REG_GPIO_PON_MODE,
>> +			GPIO_PCIE_RESET1_MASK,
>> +			0
>> +		},
>> +		.regmap_size = 1,
>> +	}, {
>> +		.name = "pcie_reset2",
>> +		.regmap[0] = {
>> +			AIROHA_FUNC_MUX,
>> +			REG_GPIO_PON_MODE,
>> +			GPIO_PCIE_RESET2_MASK,
>> +			0
>> +		},
>> +		.regmap_size = 1,
>> +	},
>> +};
>> +
>> +static const struct airoha_pinctrl_func_group pwm_func_group[] = {
>> +	AIROHA_PINCTRL_PWM("gpio0", GPIO0_FLASH_MODE_CFG),
>> +	AIROHA_PINCTRL_PWM("gpio1", GPIO1_FLASH_MODE_CFG),
>> +	AIROHA_PINCTRL_PWM("gpio2", GPIO2_FLASH_MODE_CFG),
>> +	AIROHA_PINCTRL_PWM("gpio3", GPIO3_FLASH_MODE_CFG),
>> +	AIROHA_PINCTRL_PWM("gpio4", GPIO4_FLASH_MODE_CFG),
>> +	AIROHA_PINCTRL_PWM("gpio5", GPIO5_FLASH_MODE_CFG),
>> +	AIROHA_PINCTRL_PWM("gpio6", GPIO6_FLASH_MODE_CFG),
>> +	AIROHA_PINCTRL_PWM("gpio7", GPIO7_FLASH_MODE_CFG),
>> +	AIROHA_PINCTRL_PWM("gpio8", GPIO8_FLASH_MODE_CFG),
>> +	AIROHA_PINCTRL_PWM("gpio9", GPIO9_FLASH_MODE_CFG),
>> +	AIROHA_PINCTRL_PWM("gpio10", GPIO10_FLASH_MODE_CFG),
>> +	AIROHA_PINCTRL_PWM("gpio11", GPIO11_FLASH_MODE_CFG),
>> +	AIROHA_PINCTRL_PWM("gpio12", GPIO12_FLASH_MODE_CFG),
>> +	AIROHA_PINCTRL_PWM("gpio13", GPIO13_FLASH_MODE_CFG),
>> +	AIROHA_PINCTRL_PWM("gpio14", GPIO14_FLASH_MODE_CFG),
>> +	AIROHA_PINCTRL_PWM("gpio15", GPIO15_FLASH_MODE_CFG),
>> +	AIROHA_PINCTRL_PWM_EXT("gpio16", GPIO16_FLASH_MODE_CFG),
>> +	AIROHA_PINCTRL_PWM_EXT("gpio17", GPIO17_FLASH_MODE_CFG),
>> +	AIROHA_PINCTRL_PWM_EXT("gpio18", GPIO18_FLASH_MODE_CFG),
>> +	AIROHA_PINCTRL_PWM_EXT("gpio19", GPIO19_FLASH_MODE_CFG),
>> +	AIROHA_PINCTRL_PWM_EXT("gpio20", GPIO20_FLASH_MODE_CFG),
>> +	AIROHA_PINCTRL_PWM_EXT("gpio21", GPIO21_FLASH_MODE_CFG),
>> +	AIROHA_PINCTRL_PWM_EXT("gpio22", GPIO22_FLASH_MODE_CFG),
>> +	AIROHA_PINCTRL_PWM_EXT("gpio23", GPIO23_FLASH_MODE_CFG),
>> +	AIROHA_PINCTRL_PWM_EXT("gpio24", GPIO24_FLASH_MODE_CFG),
>> +	AIROHA_PINCTRL_PWM_EXT("gpio25", GPIO25_FLASH_MODE_CFG),
>> +	AIROHA_PINCTRL_PWM_EXT("gpio26", GPIO26_FLASH_MODE_CFG),
>> +	AIROHA_PINCTRL_PWM_EXT("gpio27", GPIO27_FLASH_MODE_CFG),
>> +	AIROHA_PINCTRL_PWM_EXT("gpio28", GPIO28_FLASH_MODE_CFG),
>> +	AIROHA_PINCTRL_PWM_EXT("gpio29", GPIO29_FLASH_MODE_CFG),
>> +	AIROHA_PINCTRL_PWM_EXT("gpio30", GPIO30_FLASH_MODE_CFG),
>> +	AIROHA_PINCTRL_PWM_EXT("gpio31", GPIO31_FLASH_MODE_CFG),
>> +	AIROHA_PINCTRL_PWM_EXT("gpio36", GPIO36_FLASH_MODE_CFG),
>> +	AIROHA_PINCTRL_PWM_EXT("gpio37", GPIO37_FLASH_MODE_CFG),
>> +	AIROHA_PINCTRL_PWM_EXT("gpio38", GPIO38_FLASH_MODE_CFG),
>> +	AIROHA_PINCTRL_PWM_EXT("gpio39", GPIO39_FLASH_MODE_CFG),
>> +	AIROHA_PINCTRL_PWM_EXT("gpio40", GPIO40_FLASH_MODE_CFG),
>> +	AIROHA_PINCTRL_PWM_EXT("gpio41", GPIO41_FLASH_MODE_CFG),
>> +	AIROHA_PINCTRL_PWM_EXT("gpio42", GPIO42_FLASH_MODE_CFG),
>> +	AIROHA_PINCTRL_PWM_EXT("gpio43", GPIO43_FLASH_MODE_CFG),
>> +	AIROHA_PINCTRL_PWM_EXT("gpio44", GPIO44_FLASH_MODE_CFG),
>> +	AIROHA_PINCTRL_PWM_EXT("gpio45", GPIO45_FLASH_MODE_CFG),
>> +	AIROHA_PINCTRL_PWM_EXT("gpio46", GPIO46_FLASH_MODE_CFG),
>> +	AIROHA_PINCTRL_PWM_EXT_SEC("gpio47", GPIO47_FLASH_MODE_CFG,
>> +				   GPIO_PCIE_RESET0_MASK),
>> +	AIROHA_PINCTRL_PWM_EXT_SEC("gpio48", GPIO48_FLASH_MODE_CFG,
>> +				   GPIO_PCIE_RESET1_MASK),
>> +	AIROHA_PINCTRL_PWM_EXT_SEC("gpio49", GPIO49_FLASH_MODE_CFG,
>> +				   GPIO_PCIE_RESET2_MASK),
>> +};
>> +
>> +static const struct airoha_pinctrl_func_group phy1_led0_func_group[] = {
>> +	AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK,
>> +				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),
>> +	AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK,
>> +				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)),
>> +	AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK,
>> +				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)),
>> +	AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK,
>> +				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),
>> +};
>> +
>> +static const struct airoha_pinctrl_func_group phy2_led0_func_group[] = {
>> +	AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK,
>> +				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),
>> +	AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK,
>> +				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)),
>> +	AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK,
>> +				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)),
>> +	AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK,
>> +				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),
>> +};
>> +
>> +static const struct airoha_pinctrl_func_group phy3_led0_func_group[] = {
>> +	AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK,
>> +				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
>> +	AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK,
>> +				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),
>> +	AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK,
>> +				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),
>> +	AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK,
>> +				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
>> +};
>> +
>> +static const struct airoha_pinctrl_func_group phy4_led0_func_group[] = {
>> +	AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK,
>> +				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)),
>> +	AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK,
>> +				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)),
>> +	AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK,
>> +				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)),
>> +	AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK,
>> +				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)),
>> +};
>> +
>> +static const struct airoha_pinctrl_func_group phy1_led1_func_group[] = {
>> +	AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK,
>> +				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),
>> +	AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK,
>> +				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)),
>> +	AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK,
>> +				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)),
>> +	AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK,
>> +				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),
>> +};
>> +
>> +static const struct airoha_pinctrl_func_group phy2_led1_func_group[] = {
>> +	AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK,
>> +				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),
>> +	AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK,
>> +				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)),
>> +	AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK,
>> +				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)),
>> +	AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK,
>> +				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),
>> +};
>> +
>> +static const struct airoha_pinctrl_func_group phy3_led1_func_group[] = {
>> +	AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK,
>> +				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
>> +	AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK,
>> +				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),
>> +	AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK,
>> +				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),
>> +	AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK,
>> +				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
>> +};
>> +
>> +static const struct airoha_pinctrl_func_group phy4_led1_func_group[] = {
>> +	AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK,
>> +				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)),
>> +	AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK,
>> +				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)),
>> +	AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK,
>> +				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)),
>> +	AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK,
>> +				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)),
>> +};
>> +
>> +static const struct airoha_pinctrl_func en7581_pinctrl_funcs[] = {
>> +	PINCTRL_FUNC_DESC("pon", pon),
>> +	PINCTRL_FUNC_DESC("tod_1pps", tod_1pps),
>> +	PINCTRL_FUNC_DESC("sipo", sipo),
>> +	PINCTRL_FUNC_DESC("mdio", mdio),
>> +	PINCTRL_FUNC_DESC("uart", uart),
>> +	PINCTRL_FUNC_DESC("i2c", i2c),
>> +	PINCTRL_FUNC_DESC("jtag", jtag),
>> +	PINCTRL_FUNC_DESC("pcm", pcm),
>> +	PINCTRL_FUNC_DESC("spi", spi),
>> +	PINCTRL_FUNC_DESC("pcm_spi", pcm_spi),
>> +	PINCTRL_FUNC_DESC("i2s", i2s),
>> +	PINCTRL_FUNC_DESC("emmc", emmc),
>> +	PINCTRL_FUNC_DESC("pnand", pnand),
>> +	PINCTRL_FUNC_DESC("gpio", gpio),
>> +	PINCTRL_FUNC_DESC("pcie_reset", pcie_reset),
>> +	PINCTRL_FUNC_DESC("pwm", pwm),
>> +	PINCTRL_FUNC_DESC("phy1_led0", phy1_led0),
>> +	PINCTRL_FUNC_DESC("phy2_led0", phy2_led0),
>> +	PINCTRL_FUNC_DESC("phy3_led0", phy3_led0),
>> +	PINCTRL_FUNC_DESC("phy4_led0", phy4_led0),
>> +	PINCTRL_FUNC_DESC("phy1_led1", phy1_led1),
>> +	PINCTRL_FUNC_DESC("phy2_led1", phy2_led1),
>> +	PINCTRL_FUNC_DESC("phy3_led1", phy3_led1),
>> +	PINCTRL_FUNC_DESC("phy4_led1", phy4_led1),
>> +};
>> +
>> +static const struct airoha_pinctrl_conf en7581_pinctrl_pullup_conf[] = {
>> +	PINCTRL_CONF_DESC(0, REG_I2C_SDA_PU, UART1_TXD_PU_MASK),
>> +	PINCTRL_CONF_DESC(1, REG_I2C_SDA_PU, UART1_RXD_PU_MASK),
>> +	PINCTRL_CONF_DESC(2, REG_I2C_SDA_PU, I2C_SDA_PU_MASK),
>> +	PINCTRL_CONF_DESC(3, REG_I2C_SDA_PU, I2C_SCL_PU_MASK),
>> +	PINCTRL_CONF_DESC(4, REG_I2C_SDA_PU, SPI_CS0_PU_MASK),
>> +	PINCTRL_CONF_DESC(5, REG_I2C_SDA_PU, SPI_CLK_PU_MASK),
>> +	PINCTRL_CONF_DESC(6, REG_I2C_SDA_PU, SPI_MOSI_PU_MASK),
>> +	PINCTRL_CONF_DESC(7, REG_I2C_SDA_PU, SPI_MISO_PU_MASK),
>> +	PINCTRL_CONF_DESC(13, REG_GPIO_L_PU, BIT(0)),
>> +	PINCTRL_CONF_DESC(14, REG_GPIO_L_PU, BIT(1)),
>> +	PINCTRL_CONF_DESC(15, REG_GPIO_L_PU, BIT(2)),
>> +	PINCTRL_CONF_DESC(16, REG_GPIO_L_PU, BIT(3)),
>> +	PINCTRL_CONF_DESC(17, REG_GPIO_L_PU, BIT(4)),
>> +	PINCTRL_CONF_DESC(18, REG_GPIO_L_PU, BIT(5)),
>> +	PINCTRL_CONF_DESC(19, REG_GPIO_L_PU, BIT(6)),
>> +	PINCTRL_CONF_DESC(20, REG_GPIO_L_PU, BIT(7)),
>> +	PINCTRL_CONF_DESC(21, REG_GPIO_L_PU, BIT(8)),
>> +	PINCTRL_CONF_DESC(22, REG_GPIO_L_PU, BIT(9)),
>> +	PINCTRL_CONF_DESC(23, REG_GPIO_L_PU, BIT(10)),
>> +	PINCTRL_CONF_DESC(24, REG_GPIO_L_PU, BIT(11)),
>> +	PINCTRL_CONF_DESC(25, REG_GPIO_L_PU, BIT(12)),
>> +	PINCTRL_CONF_DESC(26, REG_GPIO_L_PU, BIT(13)),
>> +	PINCTRL_CONF_DESC(27, REG_GPIO_L_PU, BIT(14)),
>> +	PINCTRL_CONF_DESC(28, REG_GPIO_L_PU, BIT(15)),
>> +	PINCTRL_CONF_DESC(29, REG_GPIO_L_PU, BIT(16)),
>> +	PINCTRL_CONF_DESC(30, REG_GPIO_L_PU, BIT(17)),
>> +	PINCTRL_CONF_DESC(31, REG_GPIO_L_PU, BIT(18)),
>> +	PINCTRL_CONF_DESC(32, REG_GPIO_L_PU, BIT(19)),
>> +	PINCTRL_CONF_DESC(33, REG_GPIO_L_PU, BIT(20)),
>> +	PINCTRL_CONF_DESC(34, REG_GPIO_L_PU, BIT(21)),
>> +	PINCTRL_CONF_DESC(35, REG_GPIO_L_PU, BIT(22)),
>> +	PINCTRL_CONF_DESC(36, REG_GPIO_L_PU, BIT(23)),
>> +	PINCTRL_CONF_DESC(37, REG_GPIO_L_PU, BIT(24)),
>> +	PINCTRL_CONF_DESC(38, REG_GPIO_L_PU, BIT(25)),
>> +	PINCTRL_CONF_DESC(39, REG_GPIO_L_PU, BIT(26)),
>> +	PINCTRL_CONF_DESC(40, REG_GPIO_L_PU, BIT(27)),
>> +	PINCTRL_CONF_DESC(41, REG_GPIO_L_PU, BIT(28)),
>> +	PINCTRL_CONF_DESC(42, REG_GPIO_L_PU, BIT(29)),
>> +	PINCTRL_CONF_DESC(43, REG_GPIO_L_PU, BIT(30)),
>> +	PINCTRL_CONF_DESC(44, REG_GPIO_L_PU, BIT(31)),
>> +	PINCTRL_CONF_DESC(45, REG_GPIO_H_PU, BIT(0)),
>> +	PINCTRL_CONF_DESC(46, REG_GPIO_H_PU, BIT(1)),
>> +	PINCTRL_CONF_DESC(47, REG_GPIO_H_PU, BIT(2)),
>> +	PINCTRL_CONF_DESC(48, REG_GPIO_H_PU, BIT(3)),
>> +	PINCTRL_CONF_DESC(49, REG_GPIO_H_PU, BIT(4)),
>> +	PINCTRL_CONF_DESC(50, REG_GPIO_H_PU, BIT(5)),
>> +	PINCTRL_CONF_DESC(51, REG_GPIO_H_PU, BIT(6)),
>> +	PINCTRL_CONF_DESC(52, REG_GPIO_H_PU, BIT(7)),
>> +	PINCTRL_CONF_DESC(53, REG_GPIO_H_PU, BIT(8)),
>> +	PINCTRL_CONF_DESC(54, REG_GPIO_H_PU, BIT(9)),
>> +	PINCTRL_CONF_DESC(55, REG_GPIO_H_PU, BIT(10)),
>> +	PINCTRL_CONF_DESC(56, REG_GPIO_H_PU, BIT(11)),
>> +	PINCTRL_CONF_DESC(57, REG_GPIO_H_PU, BIT(12)),
>> +	PINCTRL_CONF_DESC(58, REG_GPIO_H_PU, BIT(13)),
>> +	PINCTRL_CONF_DESC(59, REG_GPIO_H_PU, BIT(14)),
>> +	PINCTRL_CONF_DESC(60, REG_I2C_SDA_PU, PCIE0_RESET_PU_MASK),
>> +	PINCTRL_CONF_DESC(61, REG_I2C_SDA_PU, PCIE1_RESET_PU_MASK),
>> +	PINCTRL_CONF_DESC(62, REG_I2C_SDA_PU, PCIE2_RESET_PU_MASK),
>> +};
>> +
>> +static const struct airoha_pinctrl_conf en7581_pinctrl_pulldown_conf[] = {
>> +	PINCTRL_CONF_DESC(0, REG_I2C_SDA_PD, UART1_TXD_PD_MASK),
>> +	PINCTRL_CONF_DESC(1, REG_I2C_SDA_PD, UART1_RXD_PD_MASK),
>> +	PINCTRL_CONF_DESC(2, REG_I2C_SDA_PD, I2C_SDA_PD_MASK),
>> +	PINCTRL_CONF_DESC(3, REG_I2C_SDA_PD, I2C_SCL_PD_MASK),
>> +	PINCTRL_CONF_DESC(4, REG_I2C_SDA_PD, SPI_CS0_PD_MASK),
>> +	PINCTRL_CONF_DESC(5, REG_I2C_SDA_PD, SPI_CLK_PD_MASK),
>> +	PINCTRL_CONF_DESC(6, REG_I2C_SDA_PD, SPI_MOSI_PD_MASK),
>> +	PINCTRL_CONF_DESC(7, REG_I2C_SDA_PD, SPI_MISO_PD_MASK),
>> +	PINCTRL_CONF_DESC(13, REG_GPIO_L_PD, BIT(0)),
>> +	PINCTRL_CONF_DESC(14, REG_GPIO_L_PD, BIT(1)),
>> +	PINCTRL_CONF_DESC(15, REG_GPIO_L_PD, BIT(2)),
>> +	PINCTRL_CONF_DESC(16, REG_GPIO_L_PD, BIT(3)),
>> +	PINCTRL_CONF_DESC(17, REG_GPIO_L_PD, BIT(4)),
>> +	PINCTRL_CONF_DESC(18, REG_GPIO_L_PD, BIT(5)),
>> +	PINCTRL_CONF_DESC(19, REG_GPIO_L_PD, BIT(6)),
>> +	PINCTRL_CONF_DESC(20, REG_GPIO_L_PD, BIT(7)),
>> +	PINCTRL_CONF_DESC(21, REG_GPIO_L_PD, BIT(8)),
>> +	PINCTRL_CONF_DESC(22, REG_GPIO_L_PD, BIT(9)),
>> +	PINCTRL_CONF_DESC(23, REG_GPIO_L_PD, BIT(10)),
>> +	PINCTRL_CONF_DESC(24, REG_GPIO_L_PD, BIT(11)),
>> +	PINCTRL_CONF_DESC(25, REG_GPIO_L_PD, BIT(12)),
>> +	PINCTRL_CONF_DESC(26, REG_GPIO_L_PD, BIT(13)),
>> +	PINCTRL_CONF_DESC(27, REG_GPIO_L_PD, BIT(14)),
>> +	PINCTRL_CONF_DESC(28, REG_GPIO_L_PD, BIT(15)),
>> +	PINCTRL_CONF_DESC(29, REG_GPIO_L_PD, BIT(16)),
>> +	PINCTRL_CONF_DESC(30, REG_GPIO_L_PD, BIT(17)),
>> +	PINCTRL_CONF_DESC(31, REG_GPIO_L_PD, BIT(18)),
>> +	PINCTRL_CONF_DESC(32, REG_GPIO_L_PD, BIT(19)),
>> +	PINCTRL_CONF_DESC(33, REG_GPIO_L_PD, BIT(20)),
>> +	PINCTRL_CONF_DESC(34, REG_GPIO_L_PD, BIT(21)),
>> +	PINCTRL_CONF_DESC(35, REG_GPIO_L_PD, BIT(22)),
>> +	PINCTRL_CONF_DESC(36, REG_GPIO_L_PD, BIT(23)),
>> +	PINCTRL_CONF_DESC(37, REG_GPIO_L_PD, BIT(24)),
>> +	PINCTRL_CONF_DESC(38, REG_GPIO_L_PD, BIT(25)),
>> +	PINCTRL_CONF_DESC(39, REG_GPIO_L_PD, BIT(26)),
>> +	PINCTRL_CONF_DESC(40, REG_GPIO_L_PD, BIT(27)),
>> +	PINCTRL_CONF_DESC(41, REG_GPIO_L_PD, BIT(28)),
>> +	PINCTRL_CONF_DESC(42, REG_GPIO_L_PD, BIT(29)),
>> +	PINCTRL_CONF_DESC(43, REG_GPIO_L_PD, BIT(30)),
>> +	PINCTRL_CONF_DESC(44, REG_GPIO_L_PD, BIT(31)),
>> +	PINCTRL_CONF_DESC(45, REG_GPIO_H_PD, BIT(0)),
>> +	PINCTRL_CONF_DESC(46, REG_GPIO_H_PD, BIT(1)),
>> +	PINCTRL_CONF_DESC(47, REG_GPIO_H_PD, BIT(2)),
>> +	PINCTRL_CONF_DESC(48, REG_GPIO_H_PD, BIT(3)),
>> +	PINCTRL_CONF_DESC(49, REG_GPIO_H_PD, BIT(4)),
>> +	PINCTRL_CONF_DESC(50, REG_GPIO_H_PD, BIT(5)),
>> +	PINCTRL_CONF_DESC(51, REG_GPIO_H_PD, BIT(6)),
>> +	PINCTRL_CONF_DESC(52, REG_GPIO_H_PD, BIT(7)),
>> +	PINCTRL_CONF_DESC(53, REG_GPIO_H_PD, BIT(8)),
>> +	PINCTRL_CONF_DESC(54, REG_GPIO_H_PD, BIT(9)),
>> +	PINCTRL_CONF_DESC(55, REG_GPIO_H_PD, BIT(10)),
>> +	PINCTRL_CONF_DESC(56, REG_GPIO_H_PD, BIT(11)),
>> +	PINCTRL_CONF_DESC(57, REG_GPIO_H_PD, BIT(12)),
>> +	PINCTRL_CONF_DESC(58, REG_GPIO_H_PD, BIT(13)),
>> +	PINCTRL_CONF_DESC(59, REG_GPIO_H_PD, BIT(14)),
>> +	PINCTRL_CONF_DESC(60, REG_I2C_SDA_PD, PCIE0_RESET_PD_MASK),
>> +	PINCTRL_CONF_DESC(61, REG_I2C_SDA_PD, PCIE1_RESET_PD_MASK),
>> +	PINCTRL_CONF_DESC(62, REG_I2C_SDA_PD, PCIE2_RESET_PD_MASK),
>> +};
>> +
>> +static const struct airoha_pinctrl_conf en7581_pinctrl_drive_e2_conf[] = {
>> +	PINCTRL_CONF_DESC(0, REG_I2C_SDA_E2, UART1_TXD_E2_MASK),
>> +	PINCTRL_CONF_DESC(1, REG_I2C_SDA_E2, UART1_RXD_E2_MASK),
>> +	PINCTRL_CONF_DESC(2, REG_I2C_SDA_E2, I2C_SDA_E2_MASK),
>> +	PINCTRL_CONF_DESC(3, REG_I2C_SDA_E2, I2C_SCL_E2_MASK),
>> +	PINCTRL_CONF_DESC(4, REG_I2C_SDA_E2, SPI_CS0_E2_MASK),
>> +	PINCTRL_CONF_DESC(5, REG_I2C_SDA_E2, SPI_CLK_E2_MASK),
>> +	PINCTRL_CONF_DESC(6, REG_I2C_SDA_E2, SPI_MOSI_E2_MASK),
>> +	PINCTRL_CONF_DESC(7, REG_I2C_SDA_E2, SPI_MISO_E2_MASK),
>> +	PINCTRL_CONF_DESC(13, REG_GPIO_L_E2, BIT(0)),
>> +	PINCTRL_CONF_DESC(14, REG_GPIO_L_E2, BIT(1)),
>> +	PINCTRL_CONF_DESC(15, REG_GPIO_L_E2, BIT(2)),
>> +	PINCTRL_CONF_DESC(16, REG_GPIO_L_E2, BIT(3)),
>> +	PINCTRL_CONF_DESC(17, REG_GPIO_L_E2, BIT(4)),
>> +	PINCTRL_CONF_DESC(18, REG_GPIO_L_E2, BIT(5)),
>> +	PINCTRL_CONF_DESC(19, REG_GPIO_L_E2, BIT(6)),
>> +	PINCTRL_CONF_DESC(20, REG_GPIO_L_E2, BIT(7)),
>> +	PINCTRL_CONF_DESC(21, REG_GPIO_L_E2, BIT(8)),
>> +	PINCTRL_CONF_DESC(22, REG_GPIO_L_E2, BIT(9)),
>> +	PINCTRL_CONF_DESC(23, REG_GPIO_L_E2, BIT(10)),
>> +	PINCTRL_CONF_DESC(24, REG_GPIO_L_E2, BIT(11)),
>> +	PINCTRL_CONF_DESC(25, REG_GPIO_L_E2, BIT(12)),
>> +	PINCTRL_CONF_DESC(26, REG_GPIO_L_E2, BIT(13)),
>> +	PINCTRL_CONF_DESC(27, REG_GPIO_L_E2, BIT(14)),
>> +	PINCTRL_CONF_DESC(28, REG_GPIO_L_E2, BIT(15)),
>> +	PINCTRL_CONF_DESC(29, REG_GPIO_L_E2, BIT(16)),
>> +	PINCTRL_CONF_DESC(30, REG_GPIO_L_E2, BIT(17)),
>> +	PINCTRL_CONF_DESC(31, REG_GPIO_L_E2, BIT(18)),
>> +	PINCTRL_CONF_DESC(32, REG_GPIO_L_E2, BIT(19)),
>> +	PINCTRL_CONF_DESC(33, REG_GPIO_L_E2, BIT(20)),
>> +	PINCTRL_CONF_DESC(34, REG_GPIO_L_E2, BIT(21)),
>> +	PINCTRL_CONF_DESC(35, REG_GPIO_L_E2, BIT(22)),
>> +	PINCTRL_CONF_DESC(36, REG_GPIO_L_E2, BIT(23)),
>> +	PINCTRL_CONF_DESC(37, REG_GPIO_L_E2, BIT(24)),
>> +	PINCTRL_CONF_DESC(38, REG_GPIO_L_E2, BIT(25)),
>> +	PINCTRL_CONF_DESC(39, REG_GPIO_L_E2, BIT(26)),
>> +	PINCTRL_CONF_DESC(40, REG_GPIO_L_E2, BIT(27)),
>> +	PINCTRL_CONF_DESC(41, REG_GPIO_L_E2, BIT(28)),
>> +	PINCTRL_CONF_DESC(42, REG_GPIO_L_E2, BIT(29)),
>> +	PINCTRL_CONF_DESC(43, REG_GPIO_L_E2, BIT(30)),
>> +	PINCTRL_CONF_DESC(44, REG_GPIO_L_E2, BIT(31)),
>> +	PINCTRL_CONF_DESC(45, REG_GPIO_H_E2, BIT(0)),
>> +	PINCTRL_CONF_DESC(46, REG_GPIO_H_E2, BIT(1)),
>> +	PINCTRL_CONF_DESC(47, REG_GPIO_H_E2, BIT(2)),
>> +	PINCTRL_CONF_DESC(48, REG_GPIO_H_E2, BIT(3)),
>> +	PINCTRL_CONF_DESC(49, REG_GPIO_H_E2, BIT(4)),
>> +	PINCTRL_CONF_DESC(50, REG_GPIO_H_E2, BIT(5)),
>> +	PINCTRL_CONF_DESC(51, REG_GPIO_H_E2, BIT(6)),
>> +	PINCTRL_CONF_DESC(52, REG_GPIO_H_E2, BIT(7)),
>> +	PINCTRL_CONF_DESC(53, REG_GPIO_H_E2, BIT(8)),
>> +	PINCTRL_CONF_DESC(54, REG_GPIO_H_E2, BIT(9)),
>> +	PINCTRL_CONF_DESC(55, REG_GPIO_H_E2, BIT(10)),
>> +	PINCTRL_CONF_DESC(56, REG_GPIO_H_E2, BIT(11)),
>> +	PINCTRL_CONF_DESC(57, REG_GPIO_H_E2, BIT(12)),
>> +	PINCTRL_CONF_DESC(58, REG_GPIO_H_E2, BIT(13)),
>> +	PINCTRL_CONF_DESC(59, REG_GPIO_H_E2, BIT(14)),
>> +	PINCTRL_CONF_DESC(60, REG_I2C_SDA_E2, PCIE0_RESET_E2_MASK),
>> +	PINCTRL_CONF_DESC(61, REG_I2C_SDA_E2, PCIE1_RESET_E2_MASK),
>> +	PINCTRL_CONF_DESC(62, REG_I2C_SDA_E2, PCIE2_RESET_E2_MASK),
>> +};
>> +
>> +static const struct airoha_pinctrl_conf en7581_pinctrl_drive_e4_conf[] = {
>> +	PINCTRL_CONF_DESC(0, REG_I2C_SDA_E4, UART1_TXD_E4_MASK),
>> +	PINCTRL_CONF_DESC(1, REG_I2C_SDA_E4, UART1_RXD_E4_MASK),
>> +	PINCTRL_CONF_DESC(2, REG_I2C_SDA_E4, I2C_SDA_E4_MASK),
>> +	PINCTRL_CONF_DESC(3, REG_I2C_SDA_E4, I2C_SCL_E4_MASK),
>> +	PINCTRL_CONF_DESC(4, REG_I2C_SDA_E4, SPI_CS0_E4_MASK),
>> +	PINCTRL_CONF_DESC(5, REG_I2C_SDA_E4, SPI_CLK_E4_MASK),
>> +	PINCTRL_CONF_DESC(6, REG_I2C_SDA_E4, SPI_MOSI_E4_MASK),
>> +	PINCTRL_CONF_DESC(7, REG_I2C_SDA_E4, SPI_MISO_E4_MASK),
>> +	PINCTRL_CONF_DESC(13, REG_GPIO_L_E4, BIT(0)),
>> +	PINCTRL_CONF_DESC(14, REG_GPIO_L_E4, BIT(1)),
>> +	PINCTRL_CONF_DESC(15, REG_GPIO_L_E4, BIT(2)),
>> +	PINCTRL_CONF_DESC(16, REG_GPIO_L_E4, BIT(3)),
>> +	PINCTRL_CONF_DESC(17, REG_GPIO_L_E4, BIT(4)),
>> +	PINCTRL_CONF_DESC(18, REG_GPIO_L_E4, BIT(5)),
>> +	PINCTRL_CONF_DESC(19, REG_GPIO_L_E4, BIT(6)),
>> +	PINCTRL_CONF_DESC(20, REG_GPIO_L_E4, BIT(7)),
>> +	PINCTRL_CONF_DESC(21, REG_GPIO_L_E4, BIT(8)),
>> +	PINCTRL_CONF_DESC(22, REG_GPIO_L_E4, BIT(9)),
>> +	PINCTRL_CONF_DESC(23, REG_GPIO_L_E4, BIT(10)),
>> +	PINCTRL_CONF_DESC(24, REG_GPIO_L_E4, BIT(11)),
>> +	PINCTRL_CONF_DESC(25, REG_GPIO_L_E4, BIT(12)),
>> +	PINCTRL_CONF_DESC(26, REG_GPIO_L_E4, BIT(13)),
>> +	PINCTRL_CONF_DESC(27, REG_GPIO_L_E4, BIT(14)),
>> +	PINCTRL_CONF_DESC(28, REG_GPIO_L_E4, BIT(15)),
>> +	PINCTRL_CONF_DESC(29, REG_GPIO_L_E4, BIT(16)),
>> +	PINCTRL_CONF_DESC(30, REG_GPIO_L_E4, BIT(17)),
>> +	PINCTRL_CONF_DESC(31, REG_GPIO_L_E4, BIT(18)),
>> +	PINCTRL_CONF_DESC(32, REG_GPIO_L_E4, BIT(19)),
>> +	PINCTRL_CONF_DESC(33, REG_GPIO_L_E4, BIT(20)),
>> +	PINCTRL_CONF_DESC(34, REG_GPIO_L_E4, BIT(21)),
>> +	PINCTRL_CONF_DESC(35, REG_GPIO_L_E4, BIT(22)),
>> +	PINCTRL_CONF_DESC(36, REG_GPIO_L_E4, BIT(23)),
>> +	PINCTRL_CONF_DESC(37, REG_GPIO_L_E4, BIT(24)),
>> +	PINCTRL_CONF_DESC(38, REG_GPIO_L_E4, BIT(25)),
>> +	PINCTRL_CONF_DESC(39, REG_GPIO_L_E4, BIT(26)),
>> +	PINCTRL_CONF_DESC(40, REG_GPIO_L_E4, BIT(27)),
>> +	PINCTRL_CONF_DESC(41, REG_GPIO_L_E4, BIT(28)),
>> +	PINCTRL_CONF_DESC(42, REG_GPIO_L_E4, BIT(29)),
>> +	PINCTRL_CONF_DESC(43, REG_GPIO_L_E4, BIT(30)),
>> +	PINCTRL_CONF_DESC(44, REG_GPIO_L_E4, BIT(31)),
>> +	PINCTRL_CONF_DESC(45, REG_GPIO_H_E4, BIT(0)),
>> +	PINCTRL_CONF_DESC(46, REG_GPIO_H_E4, BIT(1)),
>> +	PINCTRL_CONF_DESC(47, REG_GPIO_H_E4, BIT(2)),
>> +	PINCTRL_CONF_DESC(48, REG_GPIO_H_E4, BIT(3)),
>> +	PINCTRL_CONF_DESC(49, REG_GPIO_H_E4, BIT(4)),
>> +	PINCTRL_CONF_DESC(50, REG_GPIO_H_E4, BIT(5)),
>> +	PINCTRL_CONF_DESC(51, REG_GPIO_H_E4, BIT(6)),
>> +	PINCTRL_CONF_DESC(52, REG_GPIO_H_E4, BIT(7)),
>> +	PINCTRL_CONF_DESC(53, REG_GPIO_H_E4, BIT(8)),
>> +	PINCTRL_CONF_DESC(54, REG_GPIO_H_E4, BIT(9)),
>> +	PINCTRL_CONF_DESC(55, REG_GPIO_H_E4, BIT(10)),
>> +	PINCTRL_CONF_DESC(56, REG_GPIO_H_E4, BIT(11)),
>> +	PINCTRL_CONF_DESC(57, REG_GPIO_H_E4, BIT(12)),
>> +	PINCTRL_CONF_DESC(58, REG_GPIO_H_E4, BIT(13)),
>> +	PINCTRL_CONF_DESC(59, REG_GPIO_H_E4, BIT(14)),
>> +	PINCTRL_CONF_DESC(60, REG_I2C_SDA_E4, PCIE0_RESET_E4_MASK),
>> +	PINCTRL_CONF_DESC(61, REG_I2C_SDA_E4, PCIE1_RESET_E4_MASK),
>> +	PINCTRL_CONF_DESC(62, REG_I2C_SDA_E4, PCIE2_RESET_E4_MASK),
>> +};
>> +
>> +static const struct airoha_pinctrl_conf en7581_pinctrl_pcie_rst_od_conf[] = {
>> +	PINCTRL_CONF_DESC(60, REG_PCIE_RESET_OD, PCIE0_RESET_OD_MASK),
>> +	PINCTRL_CONF_DESC(61, REG_PCIE_RESET_OD, PCIE1_RESET_OD_MASK),
>> +	PINCTRL_CONF_DESC(62, REG_PCIE_RESET_OD, PCIE2_RESET_OD_MASK),
>> +};
>> +
>> +static const struct airoha_pinctrl_match_data en7581_pinctrl_match_data = {
>> +	.pinctrl_name = KBUILD_MODNAME,
>> +	.pinctrl_owner = THIS_MODULE,
>> +	.pins = en7581_pinctrl_pins,
>> +	.num_pins = ARRAY_SIZE(en7581_pinctrl_pins),
>> +	.grps = en7581_pinctrl_groups,
>> +	.num_grps = ARRAY_SIZE(en7581_pinctrl_groups),
>> +	.funcs = en7581_pinctrl_funcs,
>> +	.num_funcs = ARRAY_SIZE(en7581_pinctrl_funcs),
>> +	.confs_info = {
>> +		[AIROHA_PINCTRL_CONFS_PULLUP] = {
>> +			.confs = en7581_pinctrl_pullup_conf,
>> +			.num_confs = ARRAY_SIZE(en7581_pinctrl_pullup_conf),
>> +		},
>> +		[AIROHA_PINCTRL_CONFS_PULLDOWN] = {
>> +			.confs = en7581_pinctrl_pulldown_conf,
>> +			.num_confs = ARRAY_SIZE(en7581_pinctrl_pulldown_conf),
>> +		},
>> +		[AIROHA_PINCTRL_CONFS_DRIVE_E2] = {
>> +			.confs = en7581_pinctrl_drive_e2_conf,
>> +			.num_confs = ARRAY_SIZE(en7581_pinctrl_drive_e2_conf),
>> +		},
>> +		[AIROHA_PINCTRL_CONFS_DRIVE_E4] = {
>> +			.confs = en7581_pinctrl_drive_e4_conf,
>> +			.num_confs = ARRAY_SIZE(en7581_pinctrl_drive_e4_conf),
>> +		},
>> +		[AIROHA_PINCTRL_CONFS_PCIE_RST_OD] = {
>> +			.confs = en7581_pinctrl_pcie_rst_od_conf,
>> +			.num_confs = ARRAY_SIZE(en7581_pinctrl_pcie_rst_od_conf),
>> +		},
>> +	},
>> +};
>> +
>> +static const struct of_device_id airoha_pinctrl_of_match[] = {
>> +	{ .compatible = "airoha,en7581-pinctrl", .data = &en7581_pinctrl_match_data },
>> +	{ /* sentinel */ }
>> +};
>> +MODULE_DEVICE_TABLE(of, airoha_pinctrl_of_match);
>> +
>> +static struct platform_driver airoha_pinctrl_driver = {
>> +	.probe = airoha_pinctrl_probe,
>> +	.driver = {
>> +		.name = "pinctrl-airoha-an7581",
>> +		.of_match_table = airoha_pinctrl_of_match,
>> +	},
>> +};
>> +module_platform_driver(airoha_pinctrl_driver);
>> +
>> +MODULE_LICENSE("GPL");
>> +MODULE_AUTHOR("Lorenzo Bianconi <lorenzo@kernel.org>");
>> +MODULE_AUTHOR("Benjamin Larsson <benjamin.larsson@genexis.eu>");
>> +MODULE_AUTHOR("Markus Gothe <markus.gothe@genexis.eu>");
>> +MODULE_DESCRIPTION("Pinctrl driver for Airoha AN7581 SoC");
>> diff --git a/drivers/pinctrl/airoha/pinctrl-an7583.c b/drivers/pinctrl/airoha/pinctrl-an7583.c
>> new file mode 100644
>> index 0000000000000..b9d8dd94de5f0
>> --- /dev/null
>> +++ b/drivers/pinctrl/airoha/pinctrl-an7583.c
>> @@ -0,0 +1,1456 @@
>> +// SPDX-License-Identifier: GPL-2.0-only
>> +/*
>> + * Author: Lorenzo Bianconi <lorenzo@kernel.org>
>> + * Author: Benjamin Larsson <benjamin.larsson@genexis.eu>
>> + * Author: Markus Gothe <markus.gothe@genexis.eu>
>> + */
>> +
>> +#include "airoha-common.h"
>> +
>> +/* MUX */
>> +#define REG_GPIO_2ND_I2C_MODE			0x0214
>> +#define GPIO_LAN3_LED1_MODE_MASK		BIT(10)
>> +#define GPIO_LAN3_LED0_MODE_MASK		BIT(9)
>> +#define GPIO_LAN2_LED1_MODE_MASK		BIT(8)
>> +#define GPIO_LAN2_LED0_MODE_MASK		BIT(7)
>> +#define GPIO_LAN1_LED1_MODE_MASK		BIT(6)
>> +#define GPIO_LAN1_LED0_MODE_MASK		BIT(5)
>> +#define GPIO_LAN0_LED1_MODE_MASK		BIT(4)
>> +#define GPIO_LAN0_LED0_MODE_MASK		BIT(3)
>> +#define PON_TOD_1PPS_MODE_MASK			BIT(2)
>> +#define GSW_TOD_1PPS_MODE_MASK			BIT(1)
>> +
>> +#define REG_GPIO_SPI_CS1_MODE			0x0218
>> +#define GPIO_MDC_IO_MASTER_MODE_MASK		BIT(22)
>> +#define GPIO_PCM_SPI_CS4_MODE_MASK		BIT(21)
>> +#define GPIO_PCM_SPI_CS3_MODE_MASK		BIT(20)
>> +#define AN7583_GPIO_PCM_SPI_CS2_MODE_MASK	BIT(18)
>> +#define GPIO_PCM_SPI_CS1_MODE_MASK		BIT(17)
>> +#define GPIO_PCM_SPI_MODE_MASK			BIT(16)
>> +#define GPIO_PCM2_MODE_MASK			BIT(13)
>> +#define GPIO_PCM1_MODE_MASK			BIT(12)
>> +#define GPIO_PCM_INT_MODE_MASK			BIT(9)
>> +#define GPIO_PCM_RESET_MODE_MASK		BIT(8)
>> +#define GPIO_SPI_QUAD_MODE_MASK			BIT(4)
>> +#define GPIO_SPI_CS4_MODE_MASK			BIT(3)
>> +#define GPIO_SPI_CS3_MODE_MASK			BIT(2)
>> +#define GPIO_SPI_CS2_MODE_MASK			BIT(1)
>> +#define GPIO_SPI_CS1_MODE_MASK			BIT(0)
>> +
>> +#define REG_GPIO_PON_MODE			0x021c
>> +#define AN7583_MDIO_0_GPIO_MODE_MASK		BIT(26)
>> +#define AN7583_MDC_0_GPIO_MODE_MASK		BIT(25)
>> +#define AN7583_UART_RXD_GPIO_MODE_MASK		BIT(24)
>> +#define AN7583_UART_TXD_GPIO_MODE_MASK		BIT(23)
>> +#define AN7583_SPI_MISO_GPIO_MODE_MASK		BIT(22)
>> +#define AN7583_SPI_MOSI_GPIO_MODE_MASK		BIT(21)
>> +#define AN7583_SPI_CS_GPIO_MODE_MASK		BIT(20)
>> +#define AN7583_SPI_CLK_GPIO_MODE_MASK		BIT(19)
>> +#define AN7583_I2C1_SDA_GPIO_MODE_MASK		BIT(18)
>> +#define AN7583_I2C1_SCL_GPIO_MODE_MASK		BIT(17)
>> +#define AN7583_I2C0_SDA_GPIO_MODE_MASK		BIT(16)
>> +#define AN7583_I2C0_SCL_GPIO_MODE_MASK		BIT(15)
>> +#define GPIO_PARALLEL_NAND_MODE_MASK		BIT(14)
>> +#define GPIO_SGMII_MDIO_MODE_MASK		BIT(13)
>> +#define SIPO_RCLK_MODE_MASK			BIT(11)
>> +#define GPIO_PCIE_RESET1_MASK			BIT(10)
>> +#define GPIO_PCIE_RESET0_MASK			BIT(9)
>> +#define GPIO_UART5_MODE_MASK			BIT(8)
>> +#define GPIO_UART4_MODE_MASK			BIT(7)
>> +#define GPIO_HSUART_CTS_RTS_MODE_MASK		BIT(6)
>> +#define GPIO_HSUART_MODE_MASK			BIT(5)
>> +#define GPIO_UART2_CTS_RTS_MODE_MASK		BIT(4)
>> +#define GPIO_UART2_MODE_MASK			BIT(3)
>> +#define GPIO_SIPO_MODE_MASK			BIT(2)
>> +#define GPIO_EMMC_MODE_MASK			BIT(1)
>> +#define GPIO_PON_MODE_MASK			BIT(0)
>> +
>> +#define REG_NPU_UART_EN				0x0224
>> +#define JTAG_UDI_EN_MASK			BIT(4)
>> +#define JTAG_DFD_EN_MASK			BIT(3)
>> +
>> +#define REG_FORCE_GPIO_EN			0x0228
>> +#define FORCE_GPIO_EN(n)			BIT(n)
>> +
>> +/* LED MAP */
>> +#define REG_LAN_LED0_MAPPING			0x027c
>> +#define REG_LAN_LED1_MAPPING			0x0280
>> +
>> +#define LAN4_LED_MAPPING_MASK			GENMASK(18, 16)
>> +#define LAN4_PHY_LED_MAP(_n)			FIELD_PREP_CONST(LAN4_LED_MAPPING_MASK, (_n))
>> +
>> +#define LAN3_LED_MAPPING_MASK			GENMASK(14, 12)
>> +#define LAN3_PHY_LED_MAP(_n)			FIELD_PREP_CONST(LAN3_LED_MAPPING_MASK, (_n))
>> +
>> +#define LAN2_LED_MAPPING_MASK			GENMASK(10, 8)
>> +#define LAN2_PHY_LED_MAP(_n)			FIELD_PREP_CONST(LAN2_LED_MAPPING_MASK, (_n))
>> +
>> +#define LAN1_LED_MAPPING_MASK			GENMASK(6, 4)
>> +#define LAN1_PHY_LED_MAP(_n)			FIELD_PREP_CONST(LAN1_LED_MAPPING_MASK, (_n))
>> +
>> +#define LAN0_LED_MAPPING_MASK			GENMASK(2, 0)
>> +#define LAN0_PHY_LED_MAP(_n)			FIELD_PREP_CONST(LAN0_LED_MAPPING_MASK, (_n))
>> +
>> +/* CONF */
>> +#define REG_I2C_SDA_E2				0x001c
>> +#define AN7583_I2C1_SCL_E2_MASK			BIT(16)
>> +#define AN7583_I2C1_SDA_E2_MASK			BIT(15)
>> +#define SPI_MISO_E2_MASK			BIT(14)
>> +#define SPI_MOSI_E2_MASK			BIT(13)
>> +#define SPI_CLK_E2_MASK				BIT(12)
>> +#define SPI_CS0_E2_MASK				BIT(11)
>> +#define PCIE1_RESET_E2_MASK			BIT(9)
>> +#define PCIE0_RESET_E2_MASK			BIT(8)
>> +#define AN7583_MDIO_0_E2_MASK			BIT(5)
>> +#define AN7583_MDC_0_E2_MASK			BIT(4)
>> +#define UART1_RXD_E2_MASK			BIT(3)
>> +#define UART1_TXD_E2_MASK			BIT(2)
>> +#define I2C_SCL_E2_MASK				BIT(1)
>> +#define I2C_SDA_E2_MASK				BIT(0)
>> +
>> +#define REG_I2C_SDA_E4				0x0020
>> +#define AN7583_I2C1_SCL_E4_MASK			BIT(16)
>> +#define AN7583_I2C1_SDA_E4_MASK			BIT(15)
>> +#define SPI_MISO_E4_MASK			BIT(14)
>> +#define SPI_MOSI_E4_MASK			BIT(13)
>> +#define SPI_CLK_E4_MASK				BIT(12)
>> +#define SPI_CS0_E4_MASK				BIT(11)
>> +#define PCIE1_RESET_E4_MASK			BIT(9)
>> +#define PCIE0_RESET_E4_MASK			BIT(8)
>> +#define AN7583_MDIO_0_E4_MASK			BIT(5)
>> +#define AN7583_MDC_0_E4_MASK			BIT(4)
>> +#define UART1_RXD_E4_MASK			BIT(3)
>> +#define UART1_TXD_E4_MASK			BIT(2)
>> +#define I2C_SCL_E4_MASK				BIT(1)
>> +#define I2C_SDA_E4_MASK				BIT(0)
>> +
>> +#define REG_GPIO_L_E2				0x0024
>> +#define REG_GPIO_L_E4				0x0028
>> +#define REG_GPIO_H_E2				0x002c
>> +#define REG_GPIO_H_E4				0x0030
>> +
>> +#define REG_I2C_SDA_PU				0x0044
>> +#define AN7583_I2C1_SCL_PU_MASK			BIT(16)
>> +#define AN7583_I2C1_SDA_PU_MASK			BIT(15)
>> +#define SPI_MISO_PU_MASK			BIT(14)
>> +#define SPI_MOSI_PU_MASK			BIT(13)
>> +#define SPI_CLK_PU_MASK				BIT(12)
>> +#define SPI_CS0_PU_MASK				BIT(11)
>> +#define PCIE1_RESET_PU_MASK			BIT(9)
>> +#define PCIE0_RESET_PU_MASK			BIT(8)
>> +#define AN7583_MDIO_0_PU_MASK			BIT(5)
>> +#define AN7583_MDC_0_PU_MASK			BIT(4)
>> +#define UART1_RXD_PU_MASK			BIT(3)
>> +#define UART1_TXD_PU_MASK			BIT(2)
>> +#define I2C_SCL_PU_MASK				BIT(1)
>> +#define I2C_SDA_PU_MASK				BIT(0)
>> +
>> +#define REG_I2C_SDA_PD				0x0048
>> +#define AN7583_I2C1_SCL_PD_MASK			BIT(16)
>> +#define AN7583_I2C1_SDA_PD_MASK			BIT(15)
>> +#define SPI_MISO_PD_MASK			BIT(14)
>> +#define SPI_MOSI_PD_MASK			BIT(13)
>> +#define SPI_CLK_PD_MASK				BIT(12)
>> +#define SPI_CS0_PD_MASK				BIT(11)
>> +#define PCIE1_RESET_PD_MASK			BIT(9)
>> +#define PCIE0_RESET_PD_MASK			BIT(8)
>> +#define AN7583_MDIO_0_PD_MASK			BIT(5)
>> +#define AN7583_MDC_0_PD_MASK			BIT(4)
>> +#define UART1_RXD_PD_MASK			BIT(3)
>> +#define UART1_TXD_PD_MASK			BIT(2)
>> +#define I2C_SCL_PD_MASK				BIT(1)
>> +#define I2C_SDA_PD_MASK				BIT(0)
>> +
>> +#define REG_GPIO_L_PU				0x004c
>> +#define REG_GPIO_L_PD				0x0050
>> +#define REG_GPIO_H_PU				0x0054
>> +#define REG_GPIO_H_PD				0x0058
>> +
>> +#define REG_PCIE_RESET_OD			0x018c
>> +#define PCIE1_RESET_OD_MASK			BIT(1)
>> +#define PCIE0_RESET_OD_MASK			BIT(0)
>> +
>> +/* PWM MODE CONF */
>> +#define REG_GPIO_FLASH_MODE_CFG			0x0034
>> +#define GPIO15_FLASH_MODE_CFG			BIT(15)
>> +#define GPIO14_FLASH_MODE_CFG			BIT(14)
>> +#define GPIO13_FLASH_MODE_CFG			BIT(13)
>> +#define GPIO12_FLASH_MODE_CFG			BIT(12)
>> +#define GPIO11_FLASH_MODE_CFG			BIT(11)
>> +#define GPIO10_FLASH_MODE_CFG			BIT(10)
>> +#define GPIO9_FLASH_MODE_CFG			BIT(9)
>> +#define GPIO8_FLASH_MODE_CFG			BIT(8)
>> +#define GPIO7_FLASH_MODE_CFG			BIT(7)
>> +#define GPIO6_FLASH_MODE_CFG			BIT(6)
>> +#define GPIO5_FLASH_MODE_CFG			BIT(5)
>> +#define GPIO4_FLASH_MODE_CFG			BIT(4)
>> +#define GPIO3_FLASH_MODE_CFG			BIT(3)
>> +#define GPIO2_FLASH_MODE_CFG			BIT(2)
>> +#define GPIO1_FLASH_MODE_CFG			BIT(1)
>> +#define GPIO0_FLASH_MODE_CFG			BIT(0)
>> +
>> +/* PWM MODE CONF EXT */
>> +#define REG_GPIO_FLASH_MODE_CFG_EXT		0x0068
>> +#define GPIO51_FLASH_MODE_CFG			BIT(31)
>> +#define GPIO50_FLASH_MODE_CFG			BIT(30)
>> +#define GPIO49_FLASH_MODE_CFG			BIT(29)
>> +#define GPIO48_FLASH_MODE_CFG			BIT(28)
>> +#define GPIO47_FLASH_MODE_CFG			BIT(27)
>> +#define GPIO46_FLASH_MODE_CFG			BIT(26)
>> +#define GPIO45_FLASH_MODE_CFG			BIT(25)
>> +#define GPIO44_FLASH_MODE_CFG			BIT(24)
>> +#define GPIO43_FLASH_MODE_CFG			BIT(23)
>> +#define GPIO42_FLASH_MODE_CFG			BIT(22)
>> +#define GPIO41_FLASH_MODE_CFG			BIT(21)
>> +#define GPIO40_FLASH_MODE_CFG			BIT(20)
>> +#define GPIO39_FLASH_MODE_CFG			BIT(19)
>> +#define GPIO38_FLASH_MODE_CFG			BIT(18)
>> +#define GPIO37_FLASH_MODE_CFG			BIT(17)
>> +#define GPIO36_FLASH_MODE_CFG			BIT(16)
>> +#define GPIO31_FLASH_MODE_CFG			BIT(15)
>> +#define GPIO30_FLASH_MODE_CFG			BIT(14)
>> +#define GPIO29_FLASH_MODE_CFG			BIT(13)
>> +#define GPIO28_FLASH_MODE_CFG			BIT(12)
>> +#define GPIO27_FLASH_MODE_CFG			BIT(11)
>> +#define GPIO26_FLASH_MODE_CFG			BIT(10)
>> +#define GPIO25_FLASH_MODE_CFG			BIT(9)
>> +#define GPIO24_FLASH_MODE_CFG			BIT(8)
>> +#define GPIO23_FLASH_MODE_CFG			BIT(7)
>> +#define GPIO22_FLASH_MODE_CFG			BIT(6)
>> +#define GPIO21_FLASH_MODE_CFG			BIT(5)
>> +#define GPIO20_FLASH_MODE_CFG			BIT(4)
>> +#define GPIO19_FLASH_MODE_CFG			BIT(3)
>> +#define GPIO18_FLASH_MODE_CFG			BIT(2)
>> +#define GPIO17_FLASH_MODE_CFG			BIT(1)
>> +#define GPIO16_FLASH_MODE_CFG			BIT(0)
>> +
>> +#define AIROHA_PINCTRL_GPIO(gpio, mux_val)			\
>> +	{							\
>> +		.name = (gpio),					\
>> +		.regmap[0] = {					\
>> +			AIROHA_FUNC_MUX,			\
>> +			REG_GPIO_PON_MODE,			\
>> +			(mux_val),				\
>> +			(mux_val)				\
>> +		},						\
>> +		.regmap_size = 1,				\
>> +	}
>> +
>> +#define AIROHA_PINCTRL_GPIO_EXT(gpio, mux_val, smux_val)	\
>> +	{							\
>> +		.name = (gpio),					\
>> +		.regmap[0] = {					\
>> +			AIROHA_FUNC_PWM_EXT_MUX,		\
>> +			REG_GPIO_FLASH_MODE_CFG_EXT,		\
>> +			(mux_val),				\
>> +			0					\
>> +		},						\
>> +		.regmap[1] = {					\
>> +			AIROHA_FUNC_MUX,			\
>> +			REG_GPIO_PON_MODE,			\
>> +			(smux_val),				\
>> +			(smux_val)				\
>> +		},						\
>> +		.regmap_size = 2,				\
>> +	}
>> +
>> +/* PWM */
>> +#define AIROHA_PINCTRL_PWM(gpio, mux_val)			\
>> +	{							\
>> +		.name = (gpio),					\
>> +		.regmap[0] = {					\
>> +			AIROHA_FUNC_PWM_MUX,			\
>> +			REG_GPIO_FLASH_MODE_CFG,		\
>> +			(mux_val),				\
>> +			(mux_val)				\
>> +		},						\
>> +		.regmap_size = 1,				\
>> +	}
>> +
>> +#define AIROHA_PINCTRL_PWM_EXT(gpio, mux_val)			\
>> +	{							\
>> +		.name = (gpio),					\
>> +		.regmap[0] = {					\
>> +			AIROHA_FUNC_PWM_EXT_MUX,		\
>> +			REG_GPIO_FLASH_MODE_CFG_EXT,		\
>> +			(mux_val),				\
>> +			(mux_val)				\
>> +		},						\
>> +		.regmap_size = 1,				\
>> +	}
>> +
>> +#define AIROHA_PINCTRL_PWM_EXT_SEC(gpio, mux_val, smux_val)	\
>> +	{							\
>> +		.name = (gpio),					\
>> +		.regmap[0] = {					\
>> +			AIROHA_FUNC_PWM_EXT_MUX,		\
>> +			REG_GPIO_FLASH_MODE_CFG_EXT,		\
>> +			(mux_val),				\
>> +			(mux_val)				\
>> +		},						\
>> +		.regmap[1] = {					\
>> +			AIROHA_FUNC_MUX,			\
>> +			REG_GPIO_PON_MODE,			\
>> +			(smux_val),				\
>> +			(smux_val)				\
>> +		},						\
>> +		.regmap_size = 2,				\
>> +	}
>> +
>> +#define AIROHA_PINCTRL_PHY_LED0(gpio, mux_val, map_mask, map_val)	\
>> +	{								\
>> +		.name = (gpio),						\
>> +		.regmap[0] = {						\
>> +			AIROHA_FUNC_MUX,				\
>> +			REG_GPIO_2ND_I2C_MODE,				\
>> +			(mux_val),					\
>> +			(mux_val),					\
>> +		},							\
>> +		.regmap[1] = {						\
>> +			AIROHA_FUNC_MUX,				\
>> +			REG_LAN_LED0_MAPPING,				\
>> +			(map_mask),					\
>> +			(map_val),					\
>> +		},							\
>> +		.regmap_size = 2,					\
>> +	}
>> +
>> +#define AIROHA_PINCTRL_PHY_LED1(gpio, mux_val, map_mask, map_val)	\
>> +	{								\
>> +		.name = (gpio),						\
>> +		.regmap[0] = {						\
>> +			AIROHA_FUNC_MUX,				\
>> +			REG_GPIO_2ND_I2C_MODE,				\
>> +			(mux_val),					\
>> +			(mux_val),					\
>> +		},							\
>> +		.regmap[1] = {						\
>> +			AIROHA_FUNC_MUX,				\
>> +			REG_LAN_LED1_MAPPING,				\
>> +			(map_mask),					\
>> +			(map_val),					\
>> +		},							\
>> +		.regmap_size = 2,					\
>> +	}
>> +
>> +static struct pinctrl_pin_desc an7583_pinctrl_pins[] = {
>> +	PINCTRL_PIN(2, "gpio0"),
>> +	PINCTRL_PIN(3, "gpio1"),
>> +	PINCTRL_PIN(4, "gpio2"),
>> +	PINCTRL_PIN(5, "gpio3"),
>> +	PINCTRL_PIN(6, "gpio4"),
>> +	PINCTRL_PIN(7, "gpio5"),
>> +	PINCTRL_PIN(8, "gpio6"),
>> +	PINCTRL_PIN(9, "gpio7"),
>> +	PINCTRL_PIN(10, "gpio8"),
>> +	PINCTRL_PIN(11, "gpio9"),
>> +	PINCTRL_PIN(12, "gpio10"),
>> +	PINCTRL_PIN(13, "gpio11"),
>> +	PINCTRL_PIN(14, "gpio12"),
>> +	PINCTRL_PIN(15, "gpio13"),
>> +	PINCTRL_PIN(16, "gpio14"),
>> +	PINCTRL_PIN(17, "gpio15"),
>> +	PINCTRL_PIN(18, "gpio16"),
>> +	PINCTRL_PIN(19, "gpio17"),
>> +	PINCTRL_PIN(20, "gpio18"),
>> +	PINCTRL_PIN(21, "gpio19"),
>> +	PINCTRL_PIN(22, "gpio20"),
>> +	PINCTRL_PIN(23, "gpio21"),
>> +	PINCTRL_PIN(24, "gpio22"),
>> +	PINCTRL_PIN(25, "gpio23"),
>> +	PINCTRL_PIN(26, "gpio24"),
>> +	PINCTRL_PIN(27, "gpio25"),
>> +	PINCTRL_PIN(28, "gpio26"),
>> +	PINCTRL_PIN(29, "gpio27"),
>> +	PINCTRL_PIN(30, "gpio28"),
>> +	PINCTRL_PIN(31, "gpio29"),
>> +	PINCTRL_PIN(32, "gpio30"),
>> +	PINCTRL_PIN(33, "gpio31"),
>> +	PINCTRL_PIN(34, "gpio32"),
>> +	PINCTRL_PIN(35, "gpio33"),
>> +	PINCTRL_PIN(36, "gpio34"),
>> +	PINCTRL_PIN(37, "gpio35"),
>> +	PINCTRL_PIN(38, "gpio36"),
>> +	PINCTRL_PIN(39, "gpio37"),
>> +	PINCTRL_PIN(40, "gpio38"),
>> +	PINCTRL_PIN(41, "i2c0_scl"),
>> +	PINCTRL_PIN(42, "i2c0_sda"),
>> +	PINCTRL_PIN(43, "i2c1_scl"),
>> +	PINCTRL_PIN(44, "i2c1_sda"),
>> +	PINCTRL_PIN(45, "spi_clk"),
>> +	PINCTRL_PIN(46, "spi_cs"),
>> +	PINCTRL_PIN(47, "spi_mosi"),
>> +	PINCTRL_PIN(48, "spi_miso"),
>> +	PINCTRL_PIN(49, "uart_txd"),
>> +	PINCTRL_PIN(50, "uart_rxd"),
>> +	PINCTRL_PIN(51, "pcie_reset0"),
>> +	PINCTRL_PIN(52, "pcie_reset1"),
>> +	PINCTRL_PIN(53, "mdc_0"),
>> +	PINCTRL_PIN(54, "mdio_0"),
>> +};
>> +
>> +static const int an7583_pon_pins[] = { 15, 16, 17, 18, 19, 20 };
>> +static const int an7583_pon_tod_1pps_pins[] = { 32 };
>> +static const int an7583_gsw_tod_1pps_pins[] = { 32 };
>> +static const int an7583_sipo_pins[] = { 34, 35 };
>> +static const int an7583_sipo_rclk_pins[] = { 34, 35, 33 };
>> +static const int an7583_mdio_pins[] = { 43, 44 };
>> +static const int an7583_uart2_pins[] = { 34, 35 };
>> +static const int an7583_uart2_cts_rts_pins[] = { 32, 33 };
>> +static const int an7583_hsuart_pins[] = { 30, 31 };
>> +static const int an7583_hsuart_cts_rts_pins[] = { 28, 29 };
>> +static const int an7583_npu_uart_pins[] = { 7, 8 };
>> +static const int an7583_uart4_pins[] = { 7, 8 };
>> +static const int an7583_uart5_pins[] = { 23, 24 };
>> +static const int an7583_i2c0_pins[] = { 41, 42 };
>> +static const int an7583_i2c1_pins[] = { 43, 44 };
>> +static const int an7583_jtag_udi_pins[] = { 23, 24, 22, 25, 26 };
>> +static const int an7583_jtag_dfd_pins[] = { 23, 24, 22, 25, 26 };
>> +static const int an7583_pcm1_pins[] = { 10, 11, 12, 13, 14 };
>> +static const int an7583_pcm2_pins[] = { 28, 29, 30, 31, 24 };
>> +static const int an7583_spi_pins[] = { 28, 29, 30, 31 };
>> +static const int an7583_spi_quad_pins[] = { 25, 26 };
>> +static const int an7583_spi_cs1_pins[] = { 27 };
>> +static const int an7583_pcm_spi_pins[] = { 28, 29, 30, 31, 10, 11, 12, 13 };
>> +static const int an7583_pcm_spi_rst_pins[] = { 14 };
>> +static const int an7583_pcm_spi_cs1_pins[] = { 24 };
>> +static const int an7583_emmc_pins[] = {
>> +	7, 8, 9, 22, 23, 24, 25, 26, 45, 46, 47
>> +};
>> +static const int an7583_pnand_pins[] = {
>> +	7, 8, 9, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 45, 46, 47, 48
>> +};
>> +static const int an7583_gpio0_pins[] = { 2 };
>> +static const int an7583_gpio1_pins[] = { 3 };
>> +static const int an7583_gpio2_pins[] = { 4 };
>> +static const int an7583_gpio3_pins[] = { 5 };
>> +static const int an7583_gpio4_pins[] = { 6 };
>> +static const int an7583_gpio5_pins[] = { 7 };
>> +static const int an7583_gpio6_pins[] = { 8 };
>> +static const int an7583_gpio7_pins[] = { 9 };
>> +static const int an7583_gpio8_pins[] = { 10 };
>> +static const int an7583_gpio9_pins[] = { 11 };
>> +static const int an7583_gpio10_pins[] = { 12 };
>> +static const int an7583_gpio11_pins[] = { 13 };
>> +static const int an7583_gpio12_pins[] = { 14 };
>> +static const int an7583_gpio13_pins[] = { 15 };
>> +static const int an7583_gpio14_pins[] = { 16 };
>> +static const int an7583_gpio15_pins[] = { 17 };
>> +static const int an7583_gpio16_pins[] = { 18 };
>> +static const int an7583_gpio17_pins[] = { 19 };
>> +static const int an7583_gpio18_pins[] = { 20 };
>> +static const int an7583_gpio19_pins[] = { 21 };
>> +static const int an7583_gpio20_pins[] = { 22 };
>> +static const int an7583_gpio21_pins[] = { 23 };
>> +static const int an7583_gpio22_pins[] = { 24 };
>> +static const int an7583_gpio23_pins[] = { 25 };
>> +static const int an7583_gpio24_pins[] = { 26 };
>> +static const int an7583_gpio25_pins[] = { 27 };
>> +static const int an7583_gpio26_pins[] = { 28 };
>> +static const int an7583_gpio27_pins[] = { 29 };
>> +static const int an7583_gpio28_pins[] = { 30 };
>> +static const int an7583_gpio29_pins[] = { 31 };
>> +static const int an7583_gpio30_pins[] = { 32 };
>> +static const int an7583_gpio31_pins[] = { 33 };
>> +static const int an7583_gpio32_pins[] = { 34 };
>> +static const int an7583_gpio33_pins[] = { 35 };
>> +static const int an7583_gpio34_pins[] = { 36 };
>> +static const int an7583_gpio35_pins[] = { 37 };
>> +static const int an7583_gpio36_pins[] = { 38 };
>> +static const int an7583_gpio37_pins[] = { 39 };
>> +static const int an7583_gpio38_pins[] = { 40 };
>> +static const int an7583_gpio39_pins[] = { 41 };
>> +static const int an7583_gpio40_pins[] = { 42 };
>> +static const int an7583_gpio41_pins[] = { 43 };
>> +static const int an7583_gpio42_pins[] = { 44 };
>> +static const int an7583_gpio43_pins[] = { 45 };
>> +static const int an7583_gpio44_pins[] = { 46 };
>> +static const int an7583_gpio45_pins[] = { 47 };
>> +static const int an7583_gpio46_pins[] = { 48 };
>> +static const int an7583_gpio47_pins[] = { 49 };
>> +static const int an7583_gpio48_pins[] = { 50 };
>> +static const int an7583_gpio49_pins[] = { 51 };
>> +static const int an7583_gpio50_pins[] = { 52 };
>> +static const int an7583_gpio51_pins[] = { 53 };
>> +static const int an7583_gpio52_pins[] = { 54 };
>> +static const int an7583_pcie_reset0_pins[] = { 51 };
>> +static const int an7583_pcie_reset1_pins[] = { 52 };
>> +
>> +static const struct pingroup an7583_pinctrl_groups[] = {
>> +	PINCTRL_PIN_GROUP("pon", an7583_pon),
>> +	PINCTRL_PIN_GROUP("pon_tod_1pps", an7583_pon_tod_1pps),
>> +	PINCTRL_PIN_GROUP("gsw_tod_1pps", an7583_gsw_tod_1pps),
>> +	PINCTRL_PIN_GROUP("sipo", an7583_sipo),
>> +	PINCTRL_PIN_GROUP("sipo_rclk", an7583_sipo_rclk),
>> +	PINCTRL_PIN_GROUP("mdio", an7583_mdio),
>> +	PINCTRL_PIN_GROUP("uart2", an7583_uart2),
>> +	PINCTRL_PIN_GROUP("uart2_cts_rts", an7583_uart2_cts_rts),
>> +	PINCTRL_PIN_GROUP("hsuart", an7583_hsuart),
>> +	PINCTRL_PIN_GROUP("hsuart_cts_rts", an7583_hsuart_cts_rts),
>> +	PINCTRL_PIN_GROUP("npu_uart", an7583_npu_uart),
>> +	PINCTRL_PIN_GROUP("uart4", an7583_uart4),
>> +	PINCTRL_PIN_GROUP("uart5", an7583_uart5),
>> +	PINCTRL_PIN_GROUP("i2c0", an7583_i2c0),
>> +	PINCTRL_PIN_GROUP("i2c1", an7583_i2c1),
>> +	PINCTRL_PIN_GROUP("jtag_udi", an7583_jtag_udi),
>> +	PINCTRL_PIN_GROUP("jtag_dfd", an7583_jtag_dfd),
>> +	PINCTRL_PIN_GROUP("pcm1", an7583_pcm1),
>> +	PINCTRL_PIN_GROUP("pcm2", an7583_pcm2),
>> +	PINCTRL_PIN_GROUP("spi", an7583_spi),
>> +	PINCTRL_PIN_GROUP("spi_quad", an7583_spi_quad),
>> +	PINCTRL_PIN_GROUP("spi_cs1", an7583_spi_cs1),
>> +	PINCTRL_PIN_GROUP("pcm_spi", an7583_pcm_spi),
>> +	PINCTRL_PIN_GROUP("pcm_spi_rst", an7583_pcm_spi_rst),
>> +	PINCTRL_PIN_GROUP("pcm_spi_cs1", an7583_pcm_spi_cs1),
>> +	PINCTRL_PIN_GROUP("emmc", an7583_emmc),
>> +	PINCTRL_PIN_GROUP("pnand", an7583_pnand),
>> +	PINCTRL_PIN_GROUP("gpio0", an7583_gpio0),
>> +	PINCTRL_PIN_GROUP("gpio1", an7583_gpio1),
>> +	PINCTRL_PIN_GROUP("gpio2", an7583_gpio2),
>> +	PINCTRL_PIN_GROUP("gpio3", an7583_gpio3),
>> +	PINCTRL_PIN_GROUP("gpio4", an7583_gpio4),
>> +	PINCTRL_PIN_GROUP("gpio5", an7583_gpio5),
>> +	PINCTRL_PIN_GROUP("gpio6", an7583_gpio6),
>> +	PINCTRL_PIN_GROUP("gpio7", an7583_gpio7),
>> +	PINCTRL_PIN_GROUP("gpio8", an7583_gpio8),
>> +	PINCTRL_PIN_GROUP("gpio9", an7583_gpio9),
>> +	PINCTRL_PIN_GROUP("gpio10", an7583_gpio10),
>> +	PINCTRL_PIN_GROUP("gpio11", an7583_gpio11),
>> +	PINCTRL_PIN_GROUP("gpio12", an7583_gpio12),
>> +	PINCTRL_PIN_GROUP("gpio13", an7583_gpio13),
>> +	PINCTRL_PIN_GROUP("gpio14", an7583_gpio14),
>> +	PINCTRL_PIN_GROUP("gpio15", an7583_gpio15),
>> +	PINCTRL_PIN_GROUP("gpio16", an7583_gpio16),
>> +	PINCTRL_PIN_GROUP("gpio17", an7583_gpio17),
>> +	PINCTRL_PIN_GROUP("gpio18", an7583_gpio18),
>> +	PINCTRL_PIN_GROUP("gpio19", an7583_gpio19),
>> +	PINCTRL_PIN_GROUP("gpio20", an7583_gpio20),
>> +	PINCTRL_PIN_GROUP("gpio21", an7583_gpio21),
>> +	PINCTRL_PIN_GROUP("gpio22", an7583_gpio22),
>> +	PINCTRL_PIN_GROUP("gpio23", an7583_gpio23),
>> +	PINCTRL_PIN_GROUP("gpio24", an7583_gpio24),
>> +	PINCTRL_PIN_GROUP("gpio25", an7583_gpio25),
>> +	PINCTRL_PIN_GROUP("gpio26", an7583_gpio26),
>> +	PINCTRL_PIN_GROUP("gpio27", an7583_gpio27),
>> +	PINCTRL_PIN_GROUP("gpio28", an7583_gpio28),
>> +	PINCTRL_PIN_GROUP("gpio29", an7583_gpio29),
>> +	PINCTRL_PIN_GROUP("gpio30", an7583_gpio30),
>> +	PINCTRL_PIN_GROUP("gpio31", an7583_gpio31),
>> +	PINCTRL_PIN_GROUP("gpio32", an7583_gpio32),
>> +	PINCTRL_PIN_GROUP("gpio33", an7583_gpio33),
>> +	PINCTRL_PIN_GROUP("gpio34", an7583_gpio34),
>> +	PINCTRL_PIN_GROUP("gpio35", an7583_gpio35),
>> +	PINCTRL_PIN_GROUP("gpio36", an7583_gpio36),
>> +	PINCTRL_PIN_GROUP("gpio37", an7583_gpio37),
>> +	PINCTRL_PIN_GROUP("gpio38", an7583_gpio38),
>> +	PINCTRL_PIN_GROUP("gpio39", an7583_gpio39),
>> +	PINCTRL_PIN_GROUP("gpio40", an7583_gpio40),
>> +	PINCTRL_PIN_GROUP("gpio41", an7583_gpio41),
>> +	PINCTRL_PIN_GROUP("gpio42", an7583_gpio42),
>> +	PINCTRL_PIN_GROUP("gpio43", an7583_gpio43),
>> +	PINCTRL_PIN_GROUP("gpio44", an7583_gpio44),
>> +	PINCTRL_PIN_GROUP("gpio45", an7583_gpio45),
>> +	PINCTRL_PIN_GROUP("gpio46", an7583_gpio46),
>> +	PINCTRL_PIN_GROUP("gpio47", an7583_gpio47),
>> +	PINCTRL_PIN_GROUP("gpio48", an7583_gpio48),
>> +	PINCTRL_PIN_GROUP("gpio49", an7583_gpio49),
>> +	PINCTRL_PIN_GROUP("gpio50", an7583_gpio50),
>> +	PINCTRL_PIN_GROUP("gpio51", an7583_gpio51),
>> +	PINCTRL_PIN_GROUP("gpio52", an7583_gpio52),
>> +	PINCTRL_PIN_GROUP("pcie_reset0", an7583_pcie_reset0),
>> +	PINCTRL_PIN_GROUP("pcie_reset1", an7583_pcie_reset1),
>> +};
>> +
>> +static const char *const pon_groups[] = { "pon" };
>> +static const char *const tod_1pps_groups[] = {
>> +	"pon_tod_1pps", "gsw_tod_1pps"
>> +};
>> +static const char *const sipo_groups[] = { "sipo", "sipo_rclk" };
>> +static const char *const an7583_mdio_groups[] = { "mdio" };
>> +static const char *const uart_groups[] = {
>> +	"uart2", "uart2_cts_rts", "hsuart", "hsuart_cts_rts",
>> +	"uart4", "uart5"
>> +};
>> +static const char *const jtag_groups[] = { "jtag_udi", "jtag_dfd" };
>> +static const char *const pcm_groups[] = { "pcm1", "pcm2" };
>> +static const char *const spi_groups[] = { "spi_quad", "spi_cs1" };
>> +static const char *const an7583_pcm_spi_groups[] = {
>> +	"pcm_spi", "pcm_spi_rst", "pcm_spi_cs1"
>> +};
>> +static const char *const emmc_groups[] = { "emmc" };
>> +static const char *const pnand_groups[] = { "pnand" };
>> +static const char *const an7583_gpio_groups[] = {
>> +	"gpio39", "gpio40", "gpio41", "gpio42", "gpio43",
>> +	"gpio44", "gpio45", "gpio46", "gpio47", "gpio48",
>> +	"gpio49", "gpio50", "gpio51", "gpio52"
>> +};
>> +static const char *const an7583_pcie_reset_groups[] = {
>> +	"pcie_reset0", "pcie_reset1"
>> +};
>> +static const char *const an7583_pwm_groups[] = {
>> +	"gpio0",  "gpio1",  "gpio2",  "gpio3",  "gpio4",  "gpio5",
>> +	"gpio6",  "gpio7",  "gpio8",  "gpio9",  "gpio10", "gpio11",
>> +	"gpio12", "gpio13", "gpio14", "gpio15", "gpio16", "gpio17",
>> +	"gpio18", "gpio19", "gpio20", "gpio21", "gpio22", "gpio23",
>> +	"gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29",
>> +	"gpio30", "gpio31", "gpio36", "gpio37", "gpio38", "gpio39",
>> +	"gpio40", "gpio41", "gpio42", "gpio43", "gpio44", "gpio45",
>> +	"gpio46", "gpio47", "gpio48", "gpio49", "gpio50", "gpio51"
>> +};
>> +static const char *const an7583_phy1_led0_groups[] = {
>> +	"gpio1", "gpio2", "gpio3", "gpio4"
>> +};
>> +static const char *const an7583_phy2_led0_groups[] = {
>> +	"gpio1", "gpio2", "gpio3", "gpio4"
>> +};
>> +static const char *const an7583_phy3_led0_groups[] = {
>> +	"gpio1", "gpio2", "gpio3", "gpio4"
>> +};
>> +static const char *const an7583_phy4_led0_groups[] = {
>> +	"gpio1", "gpio2", "gpio3", "gpio4"
>> +};
>> +static const char *const an7583_phy1_led1_groups[] = {
>> +	"gpio8", "gpio9", "gpio10", "gpio11"
>> +};
>> +static const char *const an7583_phy2_led1_groups[] = {
>> +	"gpio8", "gpio9", "gpio10", "gpio11"
>> +};
>> +static const char *const an7583_phy3_led1_groups[] = {
>> +	"gpio8", "gpio9", "gpio10", "gpio11"
>> +};
>> +static const char *const an7583_phy4_led1_groups[] = {
>> +	"gpio8", "gpio9", "gpio10", "gpio11"
>> +};
>> +
>> +static const struct airoha_pinctrl_func_group pon_func_group[] = {
>> +	{
>> +		.name = "pon",
>> +		.regmap[0] = {
>> +			AIROHA_FUNC_MUX,
>> +			REG_GPIO_PON_MODE,
>> +			GPIO_PON_MODE_MASK,
>> +			GPIO_PON_MODE_MASK
>> +		},
>> +		.regmap_size = 1,
>> +	},
>> +};
>> +
>> +static const struct airoha_pinctrl_func_group tod_1pps_func_group[] = {
>> +	{
>> +		.name = "pon_tod_1pps",
>> +		.regmap[0] = {
>> +			AIROHA_FUNC_MUX,
>> +			REG_GPIO_2ND_I2C_MODE,
>> +			PON_TOD_1PPS_MODE_MASK,
>> +			PON_TOD_1PPS_MODE_MASK
>> +		},
>> +		.regmap_size = 1,
>> +	}, {
>> +		.name = "gsw_tod_1pps",
>> +		.regmap[0] = {
>> +			AIROHA_FUNC_MUX,
>> +			REG_GPIO_2ND_I2C_MODE,
>> +			GSW_TOD_1PPS_MODE_MASK,
>> +			GSW_TOD_1PPS_MODE_MASK
>> +		},
>> +		.regmap_size = 1,
>> +	},
>> +};
>> +
>> +static const struct airoha_pinctrl_func_group sipo_func_group[] = {
>> +	{
>> +		.name = "sipo",
>> +		.regmap[0] = {
>> +			AIROHA_FUNC_MUX,
>> +			REG_GPIO_PON_MODE,
>> +			GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK,
>> +			GPIO_SIPO_MODE_MASK
>> +		},
>> +		.regmap_size = 1,
>> +	}, {
>> +		.name = "sipo_rclk",
>> +		.regmap[0] = {
>> +			AIROHA_FUNC_MUX,
>> +			REG_GPIO_PON_MODE,
>> +			GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK,
>> +			GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK
>> +		},
>> +		.regmap_size = 1,
>> +	},
>> +};
>> +
>> +static const struct airoha_pinctrl_func_group an7583_mdio_func_group[] = {
>> +	{
>> +		.name = "mdio",
>> +		.regmap[0] = {
>> +			AIROHA_FUNC_MUX,
>> +			REG_GPIO_PON_MODE,
>> +			GPIO_SGMII_MDIO_MODE_MASK,
>> +			GPIO_SGMII_MDIO_MODE_MASK
>> +		},
>> +		.regmap[1] = {
>> +			AIROHA_FUNC_MUX,
>> +			REG_GPIO_SPI_CS1_MODE,
>> +			GPIO_MDC_IO_MASTER_MODE_MASK,
>> +			GPIO_MDC_IO_MASTER_MODE_MASK
>> +		},
>> +		.regmap_size = 2,
>> +	},
>> +};
>> +
>> +static const struct airoha_pinctrl_func_group uart_func_group[] = {
>> +	{
>> +		.name = "uart2",
>> +		.regmap[0] = {
>> +			AIROHA_FUNC_MUX,
>> +			REG_GPIO_PON_MODE,
>> +			GPIO_UART2_MODE_MASK,
>> +			GPIO_UART2_MODE_MASK
>> +		},
>> +		.regmap_size = 1,
>> +	}, {
>> +		.name = "uart2_cts_rts",
>> +		.regmap[0] = {
>> +			AIROHA_FUNC_MUX,
>> +			REG_GPIO_PON_MODE,
>> +			GPIO_UART2_MODE_MASK | GPIO_UART2_CTS_RTS_MODE_MASK,
>> +			GPIO_UART2_MODE_MASK | GPIO_UART2_CTS_RTS_MODE_MASK
>> +		},
>> +		.regmap_size = 1,
>> +	}, {
>> +		.name = "hsuart",
>> +		.regmap[0] = {
>> +			AIROHA_FUNC_MUX,
>> +			REG_GPIO_PON_MODE,
>> +			GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK,
>> +			GPIO_HSUART_MODE_MASK
>> +		},
>> +		.regmap_size = 1,
>> +	},
>> +	{
>> +		.name = "hsuart_cts_rts",
>> +		.regmap[0] = {
>> +			AIROHA_FUNC_MUX,
>> +			REG_GPIO_PON_MODE,
>> +			GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK,
>> +			GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK
>> +		},
>> +		.regmap_size = 1,
>> +	}, {
>> +		.name = "uart4",
>> +		.regmap[0] = {
>> +			AIROHA_FUNC_MUX,
>> +			REG_GPIO_PON_MODE,
>> +			GPIO_UART4_MODE_MASK,
>> +			GPIO_UART4_MODE_MASK
>> +		},
>> +		.regmap_size = 1,
>> +	}, {
>> +		.name = "uart5",
>> +		.regmap[0] = {
>> +			AIROHA_FUNC_MUX,
>> +			REG_GPIO_PON_MODE,
>> +			GPIO_UART5_MODE_MASK,
>> +			GPIO_UART5_MODE_MASK
>> +		},
>> +		.regmap_size = 1,
>> +	},
>> +};
>> +
>> +static const struct airoha_pinctrl_func_group jtag_func_group[] = {
>> +	{
>> +		.name = "jtag_udi",
>> +		.regmap[0] = {
>> +			AIROHA_FUNC_MUX,
>> +			REG_NPU_UART_EN,
>> +			JTAG_UDI_EN_MASK,
>> +			JTAG_UDI_EN_MASK
>> +		},
>> +		.regmap_size = 1,
>> +	}, {
>> +		.name = "jtag_dfd",
>> +		.regmap[0] = {
>> +			AIROHA_FUNC_MUX,
>> +			REG_NPU_UART_EN,
>> +			JTAG_DFD_EN_MASK,
>> +			JTAG_DFD_EN_MASK
>> +		},
>> +		.regmap_size = 1,
>> +	},
>> +};
>> +
>> +static const struct airoha_pinctrl_func_group pcm_func_group[] = {
>> +	{
>> +		.name = "pcm1",
>> +		.regmap[0] = {
>> +			AIROHA_FUNC_MUX,
>> +			REG_GPIO_SPI_CS1_MODE,
>> +			GPIO_PCM1_MODE_MASK,
>> +			GPIO_PCM1_MODE_MASK
>> +		},
>> +		.regmap_size = 1,
>> +	}, {
>> +		.name = "pcm2",
>> +		.regmap[0] = {
>> +			AIROHA_FUNC_MUX,
>> +			REG_GPIO_SPI_CS1_MODE,
>> +			GPIO_PCM2_MODE_MASK,
>> +			GPIO_PCM2_MODE_MASK
>> +		},
>> +		.regmap_size = 1,
>> +	},
>> +};
>> +
>> +static const struct airoha_pinctrl_func_group spi_func_group[] = {
>> +	{
>> +		.name = "spi_quad",
>> +		.regmap[0] = {
>> +			AIROHA_FUNC_MUX,
>> +			REG_GPIO_SPI_CS1_MODE,
>> +			GPIO_SPI_QUAD_MODE_MASK,
>> +			GPIO_SPI_QUAD_MODE_MASK
>> +		},
>> +		.regmap_size = 1,
>> +	}, {
>> +		.name = "spi_cs1",
>> +		.regmap[0] = {
>> +			AIROHA_FUNC_MUX,
>> +			REG_GPIO_SPI_CS1_MODE,
>> +			GPIO_SPI_CS1_MODE_MASK,
>> +			GPIO_SPI_CS1_MODE_MASK
>> +		},
>> +		.regmap_size = 1,
>> +	}, {
>> +		.name = "spi_cs2",
>> +		.regmap[0] = {
>> +			AIROHA_FUNC_MUX,
>> +			REG_GPIO_SPI_CS1_MODE,
>> +			GPIO_SPI_CS2_MODE_MASK,
>> +			GPIO_SPI_CS2_MODE_MASK
>> +		},
>> +		.regmap_size = 1,
>> +	}, {
>> +		.name = "spi_cs3",
>> +		.regmap[0] = {
>> +			AIROHA_FUNC_MUX,
>> +			REG_GPIO_SPI_CS1_MODE,
>> +			GPIO_SPI_CS3_MODE_MASK,
>> +			GPIO_SPI_CS3_MODE_MASK
>> +		},
>> +		.regmap_size = 1,
>> +	}, {
>> +		.name = "spi_cs4",
>> +		.regmap[0] = {
>> +			AIROHA_FUNC_MUX,
>> +			REG_GPIO_SPI_CS1_MODE,
>> +			GPIO_SPI_CS4_MODE_MASK,
>> +			GPIO_SPI_CS4_MODE_MASK
>> +		},
>> +		.regmap_size = 1,
>> +	},
>> +};
>> +
>> +static const struct airoha_pinctrl_func_group an7583_pcm_spi_func_group[] = {
>> +	{
>> +		.name = "pcm_spi",
>> +		.regmap[0] = {
>> +			AIROHA_FUNC_MUX,
>> +			REG_GPIO_SPI_CS1_MODE,
>> +			GPIO_PCM_SPI_MODE_MASK,
>> +			GPIO_PCM_SPI_MODE_MASK
>> +		},
>> +		.regmap_size = 1,
>> +	}, {
>> +		.name = "pcm_spi_int",
>> +		.regmap[0] = {
>> +			AIROHA_FUNC_MUX,
>> +			REG_GPIO_SPI_CS1_MODE,
>> +			GPIO_PCM_INT_MODE_MASK,
>> +			GPIO_PCM_INT_MODE_MASK
>> +		},
>> +		.regmap_size = 1,
>> +	}, {
>> +		.name = "pcm_spi_rst",
>> +		.regmap[0] = {
>> +			AIROHA_FUNC_MUX,
>> +			REG_GPIO_SPI_CS1_MODE,
>> +			GPIO_PCM_RESET_MODE_MASK,
>> +			GPIO_PCM_RESET_MODE_MASK
>> +		},
>> +		.regmap_size = 1,
>> +	}, {
>> +		.name = "pcm_spi_cs1",
>> +		.regmap[0] = {
>> +			AIROHA_FUNC_MUX,
>> +			REG_GPIO_SPI_CS1_MODE,
>> +			GPIO_PCM_SPI_CS1_MODE_MASK,
>> +			GPIO_PCM_SPI_CS1_MODE_MASK
>> +		},
>> +		.regmap_size = 1,
>> +	}, {
>> +		.name = "pcm_spi_cs2",
>> +		.regmap[0] = {
>> +			AIROHA_FUNC_MUX,
>> +			REG_GPIO_SPI_CS1_MODE,
>> +			AN7583_GPIO_PCM_SPI_CS2_MODE_MASK,
>> +			AN7583_GPIO_PCM_SPI_CS2_MODE_MASK
>> +		},
>> +		.regmap_size = 1,
>> +	}, {
>> +		.name = "pcm_spi_cs3",
>> +		.regmap[0] = {
>> +			AIROHA_FUNC_MUX,
>> +			REG_GPIO_SPI_CS1_MODE,
>> +			GPIO_PCM_SPI_CS3_MODE_MASK,
>> +			GPIO_PCM_SPI_CS3_MODE_MASK
>> +		},
>> +		.regmap_size = 1,
>> +	}, {
>> +		.name = "pcm_spi_cs4",
>> +		.regmap[0] = {
>> +			AIROHA_FUNC_MUX,
>> +			REG_GPIO_SPI_CS1_MODE,
>> +			GPIO_PCM_SPI_CS4_MODE_MASK,
>> +			GPIO_PCM_SPI_CS4_MODE_MASK
>> +		},
>> +		.regmap_size = 1,
>> +	},
>> +};
>> +
>> +static const struct airoha_pinctrl_func_group emmc_func_group[] = {
>> +	{
>> +		.name = "emmc",
>> +		.regmap[0] = {
>> +			AIROHA_FUNC_MUX,
>> +			REG_GPIO_PON_MODE,
>> +			GPIO_EMMC_MODE_MASK,
>> +			GPIO_EMMC_MODE_MASK
>> +		},
>> +		.regmap_size = 1,
>> +	},
>> +};
>> +
>> +static const struct airoha_pinctrl_func_group pnand_func_group[] = {
>> +	{
>> +		.name = "pnand",
>> +		.regmap[0] = {
>> +			AIROHA_FUNC_MUX,
>> +			REG_GPIO_PON_MODE,
>> +			GPIO_PARALLEL_NAND_MODE_MASK,
>> +			GPIO_PARALLEL_NAND_MODE_MASK
>> +		},
>> +		.regmap_size = 1,
>> +	},
>> +};
>> +
>> +static const struct airoha_pinctrl_func_group an7583_gpio_func_group[] = {
>> +	AIROHA_PINCTRL_GPIO_EXT("gpio39", GPIO39_FLASH_MODE_CFG,
>> +				AN7583_I2C0_SCL_GPIO_MODE_MASK),
>> +	AIROHA_PINCTRL_GPIO_EXT("gpio40", GPIO40_FLASH_MODE_CFG,
>> +				AN7583_I2C0_SDA_GPIO_MODE_MASK),
>> +	AIROHA_PINCTRL_GPIO_EXT("gpio41", GPIO41_FLASH_MODE_CFG,
>> +				AN7583_I2C1_SCL_GPIO_MODE_MASK),
>> +	AIROHA_PINCTRL_GPIO_EXT("gpio42", GPIO42_FLASH_MODE_CFG,
>> +				AN7583_I2C1_SDA_GPIO_MODE_MASK),
>> +	AIROHA_PINCTRL_GPIO_EXT("gpio43", GPIO43_FLASH_MODE_CFG,
>> +				AN7583_SPI_CLK_GPIO_MODE_MASK),
>> +	AIROHA_PINCTRL_GPIO_EXT("gpio44", GPIO44_FLASH_MODE_CFG,
>> +				AN7583_SPI_CS_GPIO_MODE_MASK),
>> +	AIROHA_PINCTRL_GPIO_EXT("gpio45", GPIO45_FLASH_MODE_CFG,
>> +				AN7583_SPI_MOSI_GPIO_MODE_MASK),
>> +	AIROHA_PINCTRL_GPIO_EXT("gpio46", GPIO46_FLASH_MODE_CFG,
>> +				AN7583_SPI_MISO_GPIO_MODE_MASK),
>> +	AIROHA_PINCTRL_GPIO_EXT("gpio47", GPIO47_FLASH_MODE_CFG,
>> +				AN7583_UART_TXD_GPIO_MODE_MASK),
>> +	AIROHA_PINCTRL_GPIO_EXT("gpio48", GPIO48_FLASH_MODE_CFG,
>> +				AN7583_UART_RXD_GPIO_MODE_MASK),
>> +	AIROHA_PINCTRL_GPIO_EXT("gpio49", GPIO49_FLASH_MODE_CFG,
>> +				GPIO_PCIE_RESET0_MASK),
>> +	AIROHA_PINCTRL_GPIO_EXT("gpio50", GPIO50_FLASH_MODE_CFG,
>> +				GPIO_PCIE_RESET1_MASK),
>> +	AIROHA_PINCTRL_GPIO_EXT("gpio51", GPIO51_FLASH_MODE_CFG,
>> +				AN7583_MDC_0_GPIO_MODE_MASK),
>> +	AIROHA_PINCTRL_GPIO("gpio52", AN7583_MDIO_0_GPIO_MODE_MASK),
>> +};
>> +
>> +static const struct airoha_pinctrl_func_group an7583_pcie_reset_func_group[] = {
>> +	{
>> +		.name = "pcie_reset0",
>> +		.regmap[0] = {
>> +			AIROHA_FUNC_MUX,
>> +			REG_GPIO_PON_MODE,
>> +			GPIO_PCIE_RESET0_MASK,
>> +			0
>> +		},
>> +		.regmap_size = 1,
>> +	}, {
>> +		.name = "pcie_reset1",
>> +		.regmap[0] = {
>> +			AIROHA_FUNC_MUX,
>> +			REG_GPIO_PON_MODE,
>> +			GPIO_PCIE_RESET1_MASK,
>> +			0
>> +		},
>> +		.regmap_size = 1,
>> +	},
>> +};
>> +
>> +static const struct airoha_pinctrl_func_group an7583_pwm_func_group[] = {
>> +	AIROHA_PINCTRL_PWM("gpio0", GPIO0_FLASH_MODE_CFG),
>> +	AIROHA_PINCTRL_PWM("gpio1", GPIO1_FLASH_MODE_CFG),
>> +	AIROHA_PINCTRL_PWM("gpio2", GPIO2_FLASH_MODE_CFG),
>> +	AIROHA_PINCTRL_PWM("gpio3", GPIO3_FLASH_MODE_CFG),
>> +	AIROHA_PINCTRL_PWM("gpio4", GPIO4_FLASH_MODE_CFG),
>> +	AIROHA_PINCTRL_PWM("gpio5", GPIO5_FLASH_MODE_CFG),
>> +	AIROHA_PINCTRL_PWM("gpio6", GPIO6_FLASH_MODE_CFG),
>> +	AIROHA_PINCTRL_PWM("gpio7", GPIO7_FLASH_MODE_CFG),
>> +	AIROHA_PINCTRL_PWM("gpio8", GPIO8_FLASH_MODE_CFG),
>> +	AIROHA_PINCTRL_PWM("gpio9", GPIO9_FLASH_MODE_CFG),
>> +	AIROHA_PINCTRL_PWM("gpio10", GPIO10_FLASH_MODE_CFG),
>> +	AIROHA_PINCTRL_PWM("gpio11", GPIO11_FLASH_MODE_CFG),
>> +	AIROHA_PINCTRL_PWM("gpio12", GPIO12_FLASH_MODE_CFG),
>> +	AIROHA_PINCTRL_PWM("gpio13", GPIO13_FLASH_MODE_CFG),
>> +	AIROHA_PINCTRL_PWM("gpio14", GPIO14_FLASH_MODE_CFG),
>> +	AIROHA_PINCTRL_PWM("gpio15", GPIO15_FLASH_MODE_CFG),
>> +	AIROHA_PINCTRL_PWM_EXT("gpio16", GPIO16_FLASH_MODE_CFG),
>> +	AIROHA_PINCTRL_PWM_EXT("gpio17", GPIO17_FLASH_MODE_CFG),
>> +	AIROHA_PINCTRL_PWM_EXT("gpio18", GPIO18_FLASH_MODE_CFG),
>> +	AIROHA_PINCTRL_PWM_EXT("gpio19", GPIO19_FLASH_MODE_CFG),
>> +	AIROHA_PINCTRL_PWM_EXT("gpio20", GPIO20_FLASH_MODE_CFG),
>> +	AIROHA_PINCTRL_PWM_EXT("gpio21", GPIO21_FLASH_MODE_CFG),
>> +	AIROHA_PINCTRL_PWM_EXT("gpio22", GPIO22_FLASH_MODE_CFG),
>> +	AIROHA_PINCTRL_PWM_EXT("gpio23", GPIO23_FLASH_MODE_CFG),
>> +	AIROHA_PINCTRL_PWM_EXT("gpio24", GPIO24_FLASH_MODE_CFG),
>> +	AIROHA_PINCTRL_PWM_EXT("gpio25", GPIO25_FLASH_MODE_CFG),
>> +	AIROHA_PINCTRL_PWM_EXT("gpio26", GPIO26_FLASH_MODE_CFG),
>> +	AIROHA_PINCTRL_PWM_EXT("gpio27", GPIO27_FLASH_MODE_CFG),
>> +	AIROHA_PINCTRL_PWM_EXT("gpio28", GPIO28_FLASH_MODE_CFG),
>> +	AIROHA_PINCTRL_PWM_EXT("gpio29", GPIO29_FLASH_MODE_CFG),
>> +	AIROHA_PINCTRL_PWM_EXT("gpio30", GPIO30_FLASH_MODE_CFG),
>> +	AIROHA_PINCTRL_PWM_EXT("gpio31", GPIO31_FLASH_MODE_CFG),
>> +	AIROHA_PINCTRL_PWM_EXT("gpio36", GPIO36_FLASH_MODE_CFG),
>> +	AIROHA_PINCTRL_PWM_EXT("gpio37", GPIO37_FLASH_MODE_CFG),
>> +	AIROHA_PINCTRL_PWM_EXT("gpio38", GPIO38_FLASH_MODE_CFG),
>> +	AIROHA_PINCTRL_PWM_EXT_SEC("gpio39", GPIO39_FLASH_MODE_CFG,
>> +				   AN7583_I2C0_SCL_GPIO_MODE_MASK),
>> +	AIROHA_PINCTRL_PWM_EXT_SEC("gpio40", GPIO40_FLASH_MODE_CFG,
>> +				   AN7583_I2C0_SDA_GPIO_MODE_MASK),
>> +	AIROHA_PINCTRL_PWM_EXT_SEC("gpio41", GPIO41_FLASH_MODE_CFG,
>> +				   AN7583_I2C1_SCL_GPIO_MODE_MASK),
>> +	AIROHA_PINCTRL_PWM_EXT_SEC("gpio42", GPIO42_FLASH_MODE_CFG,
>> +				   AN7583_I2C1_SDA_GPIO_MODE_MASK),
>> +	AIROHA_PINCTRL_PWM_EXT_SEC("gpio43", GPIO43_FLASH_MODE_CFG,
>> +				   AN7583_SPI_CLK_GPIO_MODE_MASK),
>> +	AIROHA_PINCTRL_PWM_EXT_SEC("gpio44", GPIO44_FLASH_MODE_CFG,
>> +				   AN7583_SPI_CS_GPIO_MODE_MASK),
>> +	AIROHA_PINCTRL_PWM_EXT_SEC("gpio45", GPIO45_FLASH_MODE_CFG,
>> +				   AN7583_SPI_MOSI_GPIO_MODE_MASK),
>> +	AIROHA_PINCTRL_PWM_EXT_SEC("gpio46", GPIO46_FLASH_MODE_CFG,
>> +				   AN7583_SPI_MISO_GPIO_MODE_MASK),
>> +	AIROHA_PINCTRL_PWM_EXT_SEC("gpio47", GPIO47_FLASH_MODE_CFG,
>> +				   AN7583_UART_TXD_GPIO_MODE_MASK),
>> +	AIROHA_PINCTRL_PWM_EXT_SEC("gpio48", GPIO48_FLASH_MODE_CFG,
>> +				   AN7583_UART_RXD_GPIO_MODE_MASK),
>> +	AIROHA_PINCTRL_PWM_EXT_SEC("gpio49", GPIO49_FLASH_MODE_CFG,
>> +				   GPIO_PCIE_RESET0_MASK),
>> +	AIROHA_PINCTRL_PWM_EXT_SEC("gpio50", GPIO50_FLASH_MODE_CFG,
>> +				   GPIO_PCIE_RESET1_MASK),
>> +	AIROHA_PINCTRL_PWM_EXT_SEC("gpio51", GPIO51_FLASH_MODE_CFG,
>> +				   AN7583_MDC_0_GPIO_MODE_MASK),
>> +};
>> +
>> +static const struct airoha_pinctrl_func_group an7583_phy1_led0_func_group[] = {
>> +	AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK,
>> +				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),
>> +	AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK,
>> +				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)),
>> +	AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK,
>> +				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)),
>> +	AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK,
>> +				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),
>> +};
>> +
>> +static const struct airoha_pinctrl_func_group an7583_phy2_led0_func_group[] = {
>> +	AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK,
>> +				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),
>> +	AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK,
>> +				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)),
>> +	AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK,
>> +				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)),
>> +	AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK,
>> +				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),
>> +};
>> +
>> +static const struct airoha_pinctrl_func_group an7583_phy3_led0_func_group[] = {
>> +	AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK,
>> +				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
>> +	AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK,
>> +				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),
>> +	AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK,
>> +				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),
>> +	AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK,
>> +				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
>> +};
>> +
>> +static const struct airoha_pinctrl_func_group an7583_phy4_led0_func_group[] = {
>> +	AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK,
>> +				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)),
>> +	AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK,
>> +				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)),
>> +	AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK,
>> +				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)),
>> +	AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK,
>> +				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)),
>> +};
>> +
>> +static const struct airoha_pinctrl_func_group an7583_phy1_led1_func_group[] = {
>> +	AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK,
>> +				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),
>> +	AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK,
>> +				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)),
>> +	AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK,
>> +				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)),
>> +	AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK,
>> +				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),
>> +};
>> +
>> +static const struct airoha_pinctrl_func_group an7583_phy2_led1_func_group[] = {
>> +	AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK,
>> +				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),
>> +	AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK,
>> +				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)),
>> +	AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK,
>> +				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)),
>> +	AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK,
>> +				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),
>> +};
>> +
>> +static const struct airoha_pinctrl_func_group an7583_phy3_led1_func_group[] = {
>> +	AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK,
>> +				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
>> +	AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK,
>> +				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),
>> +	AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK,
>> +				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),
>> +	AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK,
>> +				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
>> +};
>> +
>> +static const struct airoha_pinctrl_func_group an7583_phy4_led1_func_group[] = {
>> +	AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK,
>> +				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)),
>> +	AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK,
>> +				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)),
>> +	AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK,
>> +				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)),
>> +	AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK,
>> +				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)),
>> +};
>> +
>> +static const struct airoha_pinctrl_func an7583_pinctrl_funcs[] = {
>> +	PINCTRL_FUNC_DESC("pon", pon),
>> +	PINCTRL_FUNC_DESC("tod_1pps", tod_1pps),
>> +	PINCTRL_FUNC_DESC("sipo", sipo),
>> +	PINCTRL_FUNC_DESC("mdio", an7583_mdio),
>> +	PINCTRL_FUNC_DESC("uart", uart),
>> +	PINCTRL_FUNC_DESC("jtag", jtag),
>> +	PINCTRL_FUNC_DESC("pcm", pcm),
>> +	PINCTRL_FUNC_DESC("spi", spi),
>> +	PINCTRL_FUNC_DESC("pcm_spi", an7583_pcm_spi),
>> +	PINCTRL_FUNC_DESC("emmc", emmc),
>> +	PINCTRL_FUNC_DESC("pnand", pnand),
>> +	PINCTRL_FUNC_DESC("gpio", an7583_gpio),
>> +	PINCTRL_FUNC_DESC("pcie_reset", an7583_pcie_reset),
>> +	PINCTRL_FUNC_DESC("pwm", an7583_pwm),
>> +	PINCTRL_FUNC_DESC("phy1_led0", an7583_phy1_led0),
>> +	PINCTRL_FUNC_DESC("phy2_led0", an7583_phy2_led0),
>> +	PINCTRL_FUNC_DESC("phy3_led0", an7583_phy3_led0),
>> +	PINCTRL_FUNC_DESC("phy4_led0", an7583_phy4_led0),
>> +	PINCTRL_FUNC_DESC("phy1_led1", an7583_phy1_led1),
>> +	PINCTRL_FUNC_DESC("phy2_led1", an7583_phy2_led1),
>> +	PINCTRL_FUNC_DESC("phy3_led1", an7583_phy3_led1),
>> +	PINCTRL_FUNC_DESC("phy4_led1", an7583_phy4_led1),
>> +};
>> +
>> +static const struct airoha_pinctrl_conf an7583_pinctrl_pullup_conf[] = {
>> +	PINCTRL_CONF_DESC(2, REG_GPIO_L_PU, BIT(0)),
>> +	PINCTRL_CONF_DESC(3, REG_GPIO_L_PU, BIT(1)),
>> +	PINCTRL_CONF_DESC(4, REG_GPIO_L_PU, BIT(2)),
>> +	PINCTRL_CONF_DESC(5, REG_GPIO_L_PU, BIT(3)),
>> +	PINCTRL_CONF_DESC(6, REG_GPIO_L_PU, BIT(4)),
>> +	PINCTRL_CONF_DESC(7, REG_GPIO_L_PU, BIT(5)),
>> +	PINCTRL_CONF_DESC(8, REG_GPIO_L_PU, BIT(6)),
>> +	PINCTRL_CONF_DESC(9, REG_GPIO_L_PU, BIT(7)),
>> +	PINCTRL_CONF_DESC(10, REG_GPIO_L_PU, BIT(8)),
>> +	PINCTRL_CONF_DESC(11, REG_GPIO_L_PU, BIT(9)),
>> +	PINCTRL_CONF_DESC(12, REG_GPIO_L_PU, BIT(10)),
>> +	PINCTRL_CONF_DESC(13, REG_GPIO_L_PU, BIT(11)),
>> +	PINCTRL_CONF_DESC(14, REG_GPIO_L_PU, BIT(12)),
>> +	PINCTRL_CONF_DESC(15, REG_GPIO_L_PU, BIT(13)),
>> +	PINCTRL_CONF_DESC(16, REG_GPIO_L_PU, BIT(14)),
>> +	PINCTRL_CONF_DESC(17, REG_GPIO_L_PU, BIT(15)),
>> +	PINCTRL_CONF_DESC(18, REG_GPIO_L_PU, BIT(16)),
>> +	PINCTRL_CONF_DESC(19, REG_GPIO_L_PU, BIT(17)),
>> +	PINCTRL_CONF_DESC(20, REG_GPIO_L_PU, BIT(18)),
>> +	PINCTRL_CONF_DESC(21, REG_GPIO_L_PU, BIT(19)),
>> +	PINCTRL_CONF_DESC(22, REG_GPIO_L_PU, BIT(20)),
>> +	PINCTRL_CONF_DESC(23, REG_GPIO_L_PU, BIT(21)),
>> +	PINCTRL_CONF_DESC(24, REG_GPIO_L_PU, BIT(22)),
>> +	PINCTRL_CONF_DESC(25, REG_GPIO_L_PU, BIT(23)),
>> +	PINCTRL_CONF_DESC(26, REG_GPIO_L_PU, BIT(24)),
>> +	PINCTRL_CONF_DESC(27, REG_GPIO_L_PU, BIT(25)),
>> +	PINCTRL_CONF_DESC(28, REG_GPIO_L_PU, BIT(26)),
>> +	PINCTRL_CONF_DESC(29, REG_GPIO_L_PU, BIT(27)),
>> +	PINCTRL_CONF_DESC(30, REG_GPIO_L_PU, BIT(28)),
>> +	PINCTRL_CONF_DESC(31, REG_GPIO_L_PU, BIT(29)),
>> +	PINCTRL_CONF_DESC(32, REG_GPIO_L_PU, BIT(30)),
>> +	PINCTRL_CONF_DESC(33, REG_GPIO_L_PU, BIT(31)),
>> +	PINCTRL_CONF_DESC(34, REG_GPIO_H_PU, BIT(0)),
>> +	PINCTRL_CONF_DESC(35, REG_GPIO_H_PU, BIT(1)),
>> +	PINCTRL_CONF_DESC(36, REG_GPIO_H_PU, BIT(2)),
>> +	PINCTRL_CONF_DESC(37, REG_GPIO_H_PU, BIT(3)),
>> +	PINCTRL_CONF_DESC(38, REG_GPIO_H_PU, BIT(4)),
>> +	PINCTRL_CONF_DESC(39, REG_GPIO_H_PU, BIT(5)),
>> +	PINCTRL_CONF_DESC(40, REG_GPIO_H_PU, BIT(6)),
>> +	PINCTRL_CONF_DESC(41, REG_I2C_SDA_PU, I2C_SCL_PU_MASK),
>> +	PINCTRL_CONF_DESC(42, REG_I2C_SDA_PU, I2C_SDA_PU_MASK),
>> +	PINCTRL_CONF_DESC(43, REG_I2C_SDA_PU, AN7583_I2C1_SCL_PU_MASK),
>> +	PINCTRL_CONF_DESC(44, REG_I2C_SDA_PU, AN7583_I2C1_SDA_PU_MASK),
>> +	PINCTRL_CONF_DESC(45, REG_I2C_SDA_PU, SPI_CLK_PU_MASK),
>> +	PINCTRL_CONF_DESC(46, REG_I2C_SDA_PU, SPI_CS0_PU_MASK),
>> +	PINCTRL_CONF_DESC(47, REG_I2C_SDA_PU, SPI_MOSI_PU_MASK),
>> +	PINCTRL_CONF_DESC(48, REG_I2C_SDA_PU, SPI_MISO_PU_MASK),
>> +	PINCTRL_CONF_DESC(49, REG_I2C_SDA_PU, UART1_TXD_PU_MASK),
>> +	PINCTRL_CONF_DESC(50, REG_I2C_SDA_PU, UART1_RXD_PU_MASK),
>> +	PINCTRL_CONF_DESC(51, REG_I2C_SDA_PU, PCIE0_RESET_PU_MASK),
>> +	PINCTRL_CONF_DESC(52, REG_I2C_SDA_PU, PCIE1_RESET_PU_MASK),
>> +	PINCTRL_CONF_DESC(53, REG_I2C_SDA_PU, AN7583_MDC_0_PU_MASK),
>> +	PINCTRL_CONF_DESC(54, REG_I2C_SDA_PU, AN7583_MDIO_0_PU_MASK),
>> +};
>> +
>> +static const struct airoha_pinctrl_conf an7583_pinctrl_pulldown_conf[] = {
>> +	PINCTRL_CONF_DESC(2, REG_GPIO_L_PD, BIT(0)),
>> +	PINCTRL_CONF_DESC(3, REG_GPIO_L_PD, BIT(1)),
>> +	PINCTRL_CONF_DESC(4, REG_GPIO_L_PD, BIT(2)),
>> +	PINCTRL_CONF_DESC(5, REG_GPIO_L_PD, BIT(3)),
>> +	PINCTRL_CONF_DESC(6, REG_GPIO_L_PD, BIT(4)),
>> +	PINCTRL_CONF_DESC(7, REG_GPIO_L_PD, BIT(5)),
>> +	PINCTRL_CONF_DESC(8, REG_GPIO_L_PD, BIT(6)),
>> +	PINCTRL_CONF_DESC(9, REG_GPIO_L_PD, BIT(7)),
>> +	PINCTRL_CONF_DESC(10, REG_GPIO_L_PD, BIT(8)),
>> +	PINCTRL_CONF_DESC(11, REG_GPIO_L_PD, BIT(9)),
>> +	PINCTRL_CONF_DESC(12, REG_GPIO_L_PD, BIT(10)),
>> +	PINCTRL_CONF_DESC(13, REG_GPIO_L_PD, BIT(11)),
>> +	PINCTRL_CONF_DESC(14, REG_GPIO_L_PD, BIT(12)),
>> +	PINCTRL_CONF_DESC(15, REG_GPIO_L_PD, BIT(13)),
>> +	PINCTRL_CONF_DESC(16, REG_GPIO_L_PD, BIT(14)),
>> +	PINCTRL_CONF_DESC(17, REG_GPIO_L_PD, BIT(15)),
>> +	PINCTRL_CONF_DESC(18, REG_GPIO_L_PD, BIT(16)),
>> +	PINCTRL_CONF_DESC(19, REG_GPIO_L_PD, BIT(17)),
>> +	PINCTRL_CONF_DESC(20, REG_GPIO_L_PD, BIT(18)),
>> +	PINCTRL_CONF_DESC(21, REG_GPIO_L_PD, BIT(19)),
>> +	PINCTRL_CONF_DESC(22, REG_GPIO_L_PD, BIT(20)),
>> +	PINCTRL_CONF_DESC(23, REG_GPIO_L_PD, BIT(21)),
>> +	PINCTRL_CONF_DESC(24, REG_GPIO_L_PD, BIT(22)),
>> +	PINCTRL_CONF_DESC(25, REG_GPIO_L_PD, BIT(23)),
>> +	PINCTRL_CONF_DESC(26, REG_GPIO_L_PD, BIT(24)),
>> +	PINCTRL_CONF_DESC(27, REG_GPIO_L_PD, BIT(25)),
>> +	PINCTRL_CONF_DESC(28, REG_GPIO_L_PD, BIT(26)),
>> +	PINCTRL_CONF_DESC(29, REG_GPIO_L_PD, BIT(27)),
>> +	PINCTRL_CONF_DESC(30, REG_GPIO_L_PD, BIT(28)),
>> +	PINCTRL_CONF_DESC(31, REG_GPIO_L_PD, BIT(29)),
>> +	PINCTRL_CONF_DESC(32, REG_GPIO_L_PD, BIT(30)),
>> +	PINCTRL_CONF_DESC(33, REG_GPIO_L_PD, BIT(31)),
>> +	PINCTRL_CONF_DESC(34, REG_GPIO_H_PD, BIT(0)),
>> +	PINCTRL_CONF_DESC(35, REG_GPIO_H_PD, BIT(1)),
>> +	PINCTRL_CONF_DESC(36, REG_GPIO_H_PD, BIT(2)),
>> +	PINCTRL_CONF_DESC(37, REG_GPIO_H_PD, BIT(3)),
>> +	PINCTRL_CONF_DESC(38, REG_GPIO_H_PD, BIT(4)),
>> +	PINCTRL_CONF_DESC(39, REG_GPIO_H_PD, BIT(5)),
>> +	PINCTRL_CONF_DESC(40, REG_GPIO_H_PD, BIT(6)),
>> +	PINCTRL_CONF_DESC(41, REG_I2C_SDA_PD, I2C_SCL_PD_MASK),
>> +	PINCTRL_CONF_DESC(42, REG_I2C_SDA_PD, I2C_SDA_PD_MASK),
>> +	PINCTRL_CONF_DESC(43, REG_I2C_SDA_PD, AN7583_I2C1_SCL_PD_MASK),
>> +	PINCTRL_CONF_DESC(44, REG_I2C_SDA_PD, AN7583_I2C1_SDA_PD_MASK),
>> +	PINCTRL_CONF_DESC(45, REG_I2C_SDA_PD, SPI_CLK_PD_MASK),
>> +	PINCTRL_CONF_DESC(46, REG_I2C_SDA_PD, SPI_CS0_PD_MASK),
>> +	PINCTRL_CONF_DESC(47, REG_I2C_SDA_PD, SPI_MOSI_PD_MASK),
>> +	PINCTRL_CONF_DESC(48, REG_I2C_SDA_PD, SPI_MISO_PD_MASK),
>> +	PINCTRL_CONF_DESC(49, REG_I2C_SDA_PD, UART1_TXD_PD_MASK),
>> +	PINCTRL_CONF_DESC(50, REG_I2C_SDA_PD, UART1_RXD_PD_MASK),
>> +	PINCTRL_CONF_DESC(51, REG_I2C_SDA_PD, PCIE0_RESET_PD_MASK),
>> +	PINCTRL_CONF_DESC(52, REG_I2C_SDA_PD, PCIE1_RESET_PD_MASK),
>> +	PINCTRL_CONF_DESC(53, REG_I2C_SDA_PD, AN7583_MDC_0_PD_MASK),
>> +	PINCTRL_CONF_DESC(54, REG_I2C_SDA_PD, AN7583_MDIO_0_PD_MASK),
>> +};
>> +
>> +static const struct airoha_pinctrl_conf an7583_pinctrl_drive_e2_conf[] = {
>> +	PINCTRL_CONF_DESC(2, REG_GPIO_L_E2, BIT(0)),
>> +	PINCTRL_CONF_DESC(3, REG_GPIO_L_E2, BIT(1)),
>> +	PINCTRL_CONF_DESC(4, REG_GPIO_L_E2, BIT(2)),
>> +	PINCTRL_CONF_DESC(5, REG_GPIO_L_E2, BIT(3)),
>> +	PINCTRL_CONF_DESC(6, REG_GPIO_L_E2, BIT(4)),
>> +	PINCTRL_CONF_DESC(7, REG_GPIO_L_E2, BIT(5)),
>> +	PINCTRL_CONF_DESC(8, REG_GPIO_L_E2, BIT(6)),
>> +	PINCTRL_CONF_DESC(9, REG_GPIO_L_E2, BIT(7)),
>> +	PINCTRL_CONF_DESC(10, REG_GPIO_L_E2, BIT(8)),
>> +	PINCTRL_CONF_DESC(11, REG_GPIO_L_E2, BIT(9)),
>> +	PINCTRL_CONF_DESC(12, REG_GPIO_L_E2, BIT(10)),
>> +	PINCTRL_CONF_DESC(13, REG_GPIO_L_E2, BIT(11)),
>> +	PINCTRL_CONF_DESC(14, REG_GPIO_L_E2, BIT(12)),
>> +	PINCTRL_CONF_DESC(15, REG_GPIO_L_E2, BIT(13)),
>> +	PINCTRL_CONF_DESC(16, REG_GPIO_L_E2, BIT(14)),
>> +	PINCTRL_CONF_DESC(17, REG_GPIO_L_E2, BIT(15)),
>> +	PINCTRL_CONF_DESC(18, REG_GPIO_L_E2, BIT(16)),
>> +	PINCTRL_CONF_DESC(19, REG_GPIO_L_E2, BIT(17)),
>> +	PINCTRL_CONF_DESC(20, REG_GPIO_L_E2, BIT(18)),
>> +	PINCTRL_CONF_DESC(21, REG_GPIO_L_E2, BIT(19)),
>> +	PINCTRL_CONF_DESC(22, REG_GPIO_L_E2, BIT(20)),
>> +	PINCTRL_CONF_DESC(23, REG_GPIO_L_E2, BIT(21)),
>> +	PINCTRL_CONF_DESC(24, REG_GPIO_L_E2, BIT(22)),
>> +	PINCTRL_CONF_DESC(25, REG_GPIO_L_E2, BIT(23)),
>> +	PINCTRL_CONF_DESC(26, REG_GPIO_L_E2, BIT(24)),
>> +	PINCTRL_CONF_DESC(27, REG_GPIO_L_E2, BIT(25)),
>> +	PINCTRL_CONF_DESC(28, REG_GPIO_L_E2, BIT(26)),
>> +	PINCTRL_CONF_DESC(29, REG_GPIO_L_E2, BIT(27)),
>> +	PINCTRL_CONF_DESC(30, REG_GPIO_L_E2, BIT(28)),
>> +	PINCTRL_CONF_DESC(31, REG_GPIO_L_E2, BIT(29)),
>> +	PINCTRL_CONF_DESC(32, REG_GPIO_L_E2, BIT(30)),
>> +	PINCTRL_CONF_DESC(33, REG_GPIO_L_E2, BIT(31)),
>> +	PINCTRL_CONF_DESC(34, REG_GPIO_H_E2, BIT(0)),
>> +	PINCTRL_CONF_DESC(35, REG_GPIO_H_E2, BIT(1)),
>> +	PINCTRL_CONF_DESC(36, REG_GPIO_H_E2, BIT(2)),
>> +	PINCTRL_CONF_DESC(37, REG_GPIO_H_E2, BIT(3)),
>> +	PINCTRL_CONF_DESC(38, REG_GPIO_H_E2, BIT(4)),
>> +	PINCTRL_CONF_DESC(39, REG_GPIO_H_E2, BIT(5)),
>> +	PINCTRL_CONF_DESC(40, REG_GPIO_H_E2, BIT(6)),
>> +	PINCTRL_CONF_DESC(41, REG_I2C_SDA_E2, I2C_SCL_E2_MASK),
>> +	PINCTRL_CONF_DESC(42, REG_I2C_SDA_E2, I2C_SDA_E2_MASK),
>> +	PINCTRL_CONF_DESC(43, REG_I2C_SDA_E2, AN7583_I2C1_SCL_E2_MASK),
>> +	PINCTRL_CONF_DESC(44, REG_I2C_SDA_E2, AN7583_I2C1_SDA_E2_MASK),
>> +	PINCTRL_CONF_DESC(45, REG_I2C_SDA_E2, SPI_CLK_E2_MASK),
>> +	PINCTRL_CONF_DESC(46, REG_I2C_SDA_E2, SPI_CS0_E2_MASK),
>> +	PINCTRL_CONF_DESC(47, REG_I2C_SDA_E2, SPI_MOSI_E2_MASK),
>> +	PINCTRL_CONF_DESC(48, REG_I2C_SDA_E2, SPI_MISO_E2_MASK),
>> +	PINCTRL_CONF_DESC(49, REG_I2C_SDA_E2, UART1_TXD_E2_MASK),
>> +	PINCTRL_CONF_DESC(50, REG_I2C_SDA_E2, UART1_RXD_E2_MASK),
>> +	PINCTRL_CONF_DESC(51, REG_I2C_SDA_E2, PCIE0_RESET_E2_MASK),
>> +	PINCTRL_CONF_DESC(52, REG_I2C_SDA_E2, PCIE1_RESET_E2_MASK),
>> +	PINCTRL_CONF_DESC(53, REG_I2C_SDA_E2, AN7583_MDC_0_E2_MASK),
>> +	PINCTRL_CONF_DESC(54, REG_I2C_SDA_E2, AN7583_MDIO_0_E2_MASK),
>> +};
>> +
>> +static const struct airoha_pinctrl_conf an7583_pinctrl_drive_e4_conf[] = {
>> +	PINCTRL_CONF_DESC(2, REG_GPIO_L_E4, BIT(0)),
>> +	PINCTRL_CONF_DESC(3, REG_GPIO_L_E4, BIT(1)),
>> +	PINCTRL_CONF_DESC(4, REG_GPIO_L_E4, BIT(2)),
>> +	PINCTRL_CONF_DESC(5, REG_GPIO_L_E4, BIT(3)),
>> +	PINCTRL_CONF_DESC(6, REG_GPIO_L_E4, BIT(4)),
>> +	PINCTRL_CONF_DESC(7, REG_GPIO_L_E4, BIT(5)),
>> +	PINCTRL_CONF_DESC(8, REG_GPIO_L_E4, BIT(6)),
>> +	PINCTRL_CONF_DESC(9, REG_GPIO_L_E4, BIT(7)),
>> +	PINCTRL_CONF_DESC(10, REG_GPIO_L_E4, BIT(8)),
>> +	PINCTRL_CONF_DESC(11, REG_GPIO_L_E4, BIT(9)),
>> +	PINCTRL_CONF_DESC(12, REG_GPIO_L_E4, BIT(10)),
>> +	PINCTRL_CONF_DESC(13, REG_GPIO_L_E4, BIT(11)),
>> +	PINCTRL_CONF_DESC(14, REG_GPIO_L_E4, BIT(12)),
>> +	PINCTRL_CONF_DESC(15, REG_GPIO_L_E4, BIT(13)),
>> +	PINCTRL_CONF_DESC(16, REG_GPIO_L_E4, BIT(14)),
>> +	PINCTRL_CONF_DESC(17, REG_GPIO_L_E4, BIT(15)),
>> +	PINCTRL_CONF_DESC(18, REG_GPIO_L_E4, BIT(16)),
>> +	PINCTRL_CONF_DESC(19, REG_GPIO_L_E4, BIT(17)),
>> +	PINCTRL_CONF_DESC(20, REG_GPIO_L_E4, BIT(18)),
>> +	PINCTRL_CONF_DESC(21, REG_GPIO_L_E4, BIT(19)),
>> +	PINCTRL_CONF_DESC(22, REG_GPIO_L_E4, BIT(20)),
>> +	PINCTRL_CONF_DESC(23, REG_GPIO_L_E4, BIT(21)),
>> +	PINCTRL_CONF_DESC(24, REG_GPIO_L_E4, BIT(22)),
>> +	PINCTRL_CONF_DESC(25, REG_GPIO_L_E4, BIT(23)),
>> +	PINCTRL_CONF_DESC(26, REG_GPIO_L_E4, BIT(24)),
>> +	PINCTRL_CONF_DESC(27, REG_GPIO_L_E4, BIT(25)),
>> +	PINCTRL_CONF_DESC(28, REG_GPIO_L_E4, BIT(26)),
>> +	PINCTRL_CONF_DESC(29, REG_GPIO_L_E4, BIT(27)),
>> +	PINCTRL_CONF_DESC(30, REG_GPIO_L_E4, BIT(28)),
>> +	PINCTRL_CONF_DESC(31, REG_GPIO_L_E4, BIT(29)),
>> +	PINCTRL_CONF_DESC(32, REG_GPIO_L_E4, BIT(30)),
>> +	PINCTRL_CONF_DESC(33, REG_GPIO_L_E4, BIT(31)),
>> +	PINCTRL_CONF_DESC(34, REG_GPIO_H_E4, BIT(0)),
>> +	PINCTRL_CONF_DESC(35, REG_GPIO_H_E4, BIT(1)),
>> +	PINCTRL_CONF_DESC(36, REG_GPIO_H_E4, BIT(2)),
>> +	PINCTRL_CONF_DESC(37, REG_GPIO_H_E4, BIT(3)),
>> +	PINCTRL_CONF_DESC(38, REG_GPIO_H_E4, BIT(4)),
>> +	PINCTRL_CONF_DESC(39, REG_GPIO_H_E4, BIT(5)),
>> +	PINCTRL_CONF_DESC(40, REG_GPIO_H_E4, BIT(6)),
>> +	PINCTRL_CONF_DESC(41, REG_I2C_SDA_E4, I2C_SCL_E4_MASK),
>> +	PINCTRL_CONF_DESC(42, REG_I2C_SDA_E4, I2C_SDA_E4_MASK),
>> +	PINCTRL_CONF_DESC(43, REG_I2C_SDA_E4, AN7583_I2C1_SCL_E4_MASK),
>> +	PINCTRL_CONF_DESC(44, REG_I2C_SDA_E4, AN7583_I2C1_SDA_E4_MASK),
>> +	PINCTRL_CONF_DESC(45, REG_I2C_SDA_E4, SPI_CLK_E4_MASK),
>> +	PINCTRL_CONF_DESC(46, REG_I2C_SDA_E4, SPI_CS0_E4_MASK),
>> +	PINCTRL_CONF_DESC(47, REG_I2C_SDA_E4, SPI_MOSI_E4_MASK),
>> +	PINCTRL_CONF_DESC(48, REG_I2C_SDA_E4, SPI_MISO_E4_MASK),
>> +	PINCTRL_CONF_DESC(49, REG_I2C_SDA_E4, UART1_TXD_E4_MASK),
>> +	PINCTRL_CONF_DESC(50, REG_I2C_SDA_E4, UART1_RXD_E4_MASK),
>> +	PINCTRL_CONF_DESC(51, REG_I2C_SDA_E4, PCIE0_RESET_E4_MASK),
>> +	PINCTRL_CONF_DESC(52, REG_I2C_SDA_E4, PCIE1_RESET_E4_MASK),
>> +	PINCTRL_CONF_DESC(53, REG_I2C_SDA_E4, AN7583_MDC_0_E4_MASK),
>> +	PINCTRL_CONF_DESC(54, REG_I2C_SDA_E4, AN7583_MDIO_0_E4_MASK),
>> +};
>> +
>> +static const struct airoha_pinctrl_conf an7583_pinctrl_pcie_rst_od_conf[] = {
>> +	PINCTRL_CONF_DESC(51, REG_PCIE_RESET_OD, PCIE0_RESET_OD_MASK),
>> +	PINCTRL_CONF_DESC(52, REG_PCIE_RESET_OD, PCIE1_RESET_OD_MASK),
>> +};
>> +
>> +static const struct airoha_pinctrl_match_data an7583_pinctrl_match_data = {
>> +	.pinctrl_name = KBUILD_MODNAME,
>> +	.pinctrl_owner = THIS_MODULE,
>> +	.pins = an7583_pinctrl_pins,
>> +	.num_pins = ARRAY_SIZE(an7583_pinctrl_pins),
>> +	.grps = an7583_pinctrl_groups,
>> +	.num_grps = ARRAY_SIZE(an7583_pinctrl_groups),
>> +	.funcs = an7583_pinctrl_funcs,
>> +	.num_funcs = ARRAY_SIZE(an7583_pinctrl_funcs),
>> +	.confs_info = {
>> +		[AIROHA_PINCTRL_CONFS_PULLUP] = {
>> +			.confs = an7583_pinctrl_pullup_conf,
>> +			.num_confs = ARRAY_SIZE(an7583_pinctrl_pullup_conf),
>> +		},
>> +		[AIROHA_PINCTRL_CONFS_PULLDOWN] = {
>> +			.confs = an7583_pinctrl_pulldown_conf,
>> +			.num_confs = ARRAY_SIZE(an7583_pinctrl_pulldown_conf),
>> +		},
>> +		[AIROHA_PINCTRL_CONFS_DRIVE_E2] = {
>> +			.confs = an7583_pinctrl_drive_e2_conf,
>> +			.num_confs = ARRAY_SIZE(an7583_pinctrl_drive_e2_conf),
>> +		},
>> +		[AIROHA_PINCTRL_CONFS_DRIVE_E4] = {
>> +			.confs = an7583_pinctrl_drive_e4_conf,
>> +			.num_confs = ARRAY_SIZE(an7583_pinctrl_drive_e4_conf),
>> +		},
>> +		[AIROHA_PINCTRL_CONFS_PCIE_RST_OD] = {
>> +			.confs = an7583_pinctrl_pcie_rst_od_conf,
>> +			.num_confs = ARRAY_SIZE(an7583_pinctrl_pcie_rst_od_conf),
>> +		},
>> +	},
>> +};
>> +
>> +static const struct of_device_id airoha_pinctrl_of_match[] = {
>> +	{ .compatible = "airoha,an7583-pinctrl", .data = &an7583_pinctrl_match_data },
>> +	{ /* sentinel */ }
>> +};
>> +MODULE_DEVICE_TABLE(of, airoha_pinctrl_of_match);
>> +
>> +static struct platform_driver airoha_pinctrl_driver = {
>> +	.probe = airoha_pinctrl_probe,
>> +	.driver = {
>> +		.name = "pinctrl-airoha-an7583",
>> +		.of_match_table = airoha_pinctrl_of_match,
>> +	},
>> +};
>> +module_platform_driver(airoha_pinctrl_driver);
>> +
>> +MODULE_LICENSE("GPL");
>> +MODULE_AUTHOR("Lorenzo Bianconi <lorenzo@kernel.org>");
>> +MODULE_AUTHOR("Benjamin Larsson <benjamin.larsson@genexis.eu>");
>> +MODULE_AUTHOR("Markus Gothe <markus.gothe@genexis.eu>");
>> +MODULE_DESCRIPTION("Pinctrl driver for Airoha AN7583 SoC");
>> -- 
>> 2.53.0
>>

Re: [PATCH v7 20/34] pinctrl: airoha: split driver on shared code and SoC specific drivers

[Lorenzo Bianconi]

[-- Attachment #1: Type: text/plain, Size: 238212 bytes --]

> 
> On 7/27/26 12:14, Lorenzo Bianconi wrote:
> >> Split combined an7581/an7583 source file on a
> >>  * shared pinctrl code (pinctrl-airoha.c)
> >>  * an7581 specific pinctrl driver (pinctrl-an7581.c)
> >>  * an7583 specific pinctrl driver (pinctrl-an7583.c)
> > I do not think we can have 7581 and 7583 chips at the same time on a given
> > board so I guess we can avoid creating a dedicated module for the common code.
> > I guess we can just create a library we can compile in. What do yout think?
> >
> > Regards,
> > Lorenzo
> Hm, how do you suggest to implement it? In the generic kernel case  we
> should not
> load airoha pinctrl library if we are booting from non airoha board. 

I mean just compile the code in en7581 or an7583 modules without a dedicated
module.

Regards,
Lorenzo

> >
> >> Ininialization code was adapted a bit to work properly for shared
> >> and SoC specific cases.
> >>
> >> Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
> >> ---
> >>  drivers/pinctrl/airoha/Kconfig          |   24 +-
> >>  drivers/pinctrl/airoha/Makefile         |    5 +
> >>  drivers/pinctrl/airoha/airoha-common.h  |    5 +
> >>  drivers/pinctrl/airoha/pinctrl-airoha.c | 2382 +----------------------
> >>  drivers/pinctrl/airoha/pinctrl-an7581.c | 1486 ++++++++++++++
> >>  drivers/pinctrl/airoha/pinctrl-an7583.c | 1456 ++++++++++++++
> >>  6 files changed, 2984 insertions(+), 2374 deletions(-)
> >>  create mode 100644 drivers/pinctrl/airoha/pinctrl-an7581.c
> >>  create mode 100644 drivers/pinctrl/airoha/pinctrl-an7583.c
> >>
> >> diff --git a/drivers/pinctrl/airoha/Kconfig b/drivers/pinctrl/airoha/Kconfig
> >> index 03adaeae8fc3a..dae6608bc72dd 100644
> >> --- a/drivers/pinctrl/airoha/Kconfig
> >> +++ b/drivers/pinctrl/airoha/Kconfig
> >> @@ -3,9 +3,9 @@ menu "Airoha pinctrl drivers"
> >>  	depends on ARCH_AIROHA || COMPILE_TEST
> >>  
> >>  config PINCTRL_AIROHA
> >> -	tristate "Airoha EN7581 pin control"
> >> +	tristate "Airoha pin control"
> >>  	depends on OF
> >> -	depends on ARM64 || COMPILE_TEST
> >> +	depends on ARCH_AIROHA || COMPILE_TEST
> >>  	select PINMUX
> >>  	select GENERIC_PINCONF
> >>  	select GENERIC_PINCTRL_GROUPS
> >> @@ -13,8 +13,26 @@ config PINCTRL_AIROHA
> >>  	select GPIOLIB
> >>  	select GPIOLIB_IRQCHIP
> >>  	select REGMAP_MMIO
> >> +	imply PINCTRL_AIROHA_AN7581
> >> +	imply PINCTRL_AIROHA_AN7583
> >> +	help
> >> +	  Shared pin controller and gpio driver code for different
> >> +	  Airoha SoCs.
> >> +
> >> +config PINCTRL_AIROHA_AN7581
> >> +	tristate "AN7581 pinctrl"
> >> +	depends on ARM64 || COMPILE_TEST
> >> +	depends on PINCTRL_AIROHA
> >> +	help
> >> +	  Say yes here to support pin controller and gpio driver
> >> +	  on Airoha AN7581, AN7566, AN7551 and other compatible SoCs.
> >> +
> >> +config PINCTRL_AIROHA_AN7583
> >> +	tristate "AN7583 pinctrl"
> >> +	depends on ARM64 || COMPILE_TEST
> >> +	depends on PINCTRL_AIROHA
> >>  	help
> >>  	  Say yes here to support pin controller and gpio driver
> >> -	  on Airoha EN7581 SoC.
> >> +	  on Airoha AN7583, AN7553, AN7567 and other compatible SoCs.
> >>  
> >>  endmenu
> >> diff --git a/drivers/pinctrl/airoha/Makefile b/drivers/pinctrl/airoha/Makefile
> >> index a25b744dd7a8a..cfd68c45ae0f0 100644
> >> --- a/drivers/pinctrl/airoha/Makefile
> >> +++ b/drivers/pinctrl/airoha/Makefile
> >> @@ -1,3 +1,8 @@
> >>  # SPDX-License-Identifier: GPL-2.0
> >>  
> >> +# shared code
> >>  obj-$(CONFIG_PINCTRL_AIROHA)		+= pinctrl-airoha.o
> >> +
> >> +# SoC drivers
> >> +obj-$(CONFIG_PINCTRL_AIROHA_AN7581)	+= pinctrl-an7581.o
> >> +obj-$(CONFIG_PINCTRL_AIROHA_AN7583)	+= pinctrl-an7583.o
> >> diff --git a/drivers/pinctrl/airoha/airoha-common.h b/drivers/pinctrl/airoha/airoha-common.h
> >> index 40d7e515c09eb..f73e90ca860f4 100644
> >> --- a/drivers/pinctrl/airoha/airoha-common.h
> >> +++ b/drivers/pinctrl/airoha/airoha-common.h
> >> @@ -148,9 +148,12 @@ struct airoha_pinctrl {
> >>  	struct regmap *regmap;
> >>  
> >>  	struct airoha_pinctrl_gpiochip gpiochip;
> >> +	struct irq_chip gpio_irq_chip;
> >>  };
> >>  
> >>  struct airoha_pinctrl_match_data {
> >> +	const char *pinctrl_name;
> >> +	struct module *pinctrl_owner;
> >>  	const struct pinctrl_pin_desc *pins;
> >>  	const unsigned int num_pins;
> >>  	const struct pingroup *grps;
> >> @@ -160,4 +163,6 @@ struct airoha_pinctrl_match_data {
> >>  	const struct airoha_pinctrl_confs_info confs_info[AIROHA_PINCTRL_CONFS_MAX];
> >>  };
> >>  
> >> +int airoha_pinctrl_probe(struct platform_device *pdev);
> >> +
> >>  #endif
> >> diff --git a/drivers/pinctrl/airoha/pinctrl-airoha.c b/drivers/pinctrl/airoha/pinctrl-airoha.c
> >> index f42631afc05d3..a46596eb1493b 100644
> >> --- a/drivers/pinctrl/airoha/pinctrl-airoha.c
> >> +++ b/drivers/pinctrl/airoha/pinctrl-airoha.c
> >> @@ -7,365 +7,6 @@
> >>  
> >>  #include "airoha-common.h"
> >>  
> >> -/* MUX */
> >> -#define REG_GPIO_2ND_I2C_MODE			0x0214
> >> -#define GPIO_MDC_IO_MASTER_MODE_MASK		BIT(14)
> >> -#define GPIO_I2C_MASTER_MODE_MODE		BIT(13)
> >> -#define GPIO_I2S_MODE_MASK			BIT(12)
> >> -#define GPIO_I2C_SLAVE_MODE_MODE		BIT(11)
> >> -#define GPIO_LAN3_LED1_MODE_MASK		BIT(10)
> >> -#define GPIO_LAN3_LED0_MODE_MASK		BIT(9)
> >> -#define GPIO_LAN2_LED1_MODE_MASK		BIT(8)
> >> -#define GPIO_LAN2_LED0_MODE_MASK		BIT(7)
> >> -#define GPIO_LAN1_LED1_MODE_MASK		BIT(6)
> >> -#define GPIO_LAN1_LED0_MODE_MASK		BIT(5)
> >> -#define GPIO_LAN0_LED1_MODE_MASK		BIT(4)
> >> -#define GPIO_LAN0_LED0_MODE_MASK		BIT(3)
> >> -#define PON_TOD_1PPS_MODE_MASK			BIT(2)
> >> -#define GSW_TOD_1PPS_MODE_MASK			BIT(1)
> >> -#define GPIO_2ND_I2C_MODE_MASK			BIT(0)
> >> -
> >> -#define REG_GPIO_SPI_CS1_MODE			0x0218
> >> -#define GPIO_PCM_SPI_CS4_MODE_MASK		BIT(21)
> >> -#define GPIO_PCM_SPI_CS3_MODE_MASK		BIT(20)
> >> -#define GPIO_PCM_SPI_CS2_MODE_P156_MASK		BIT(19)
> >> -#define GPIO_PCM_SPI_CS2_MODE_P128_MASK		BIT(18)
> >> -#define AN7583_GPIO_PCM_SPI_CS2_MODE_MASK	BIT(18)
> >> -#define GPIO_PCM_SPI_CS1_MODE_MASK		BIT(17)
> >> -#define GPIO_PCM_SPI_MODE_MASK			BIT(16)
> >> -#define GPIO_PCM2_MODE_MASK			BIT(13)
> >> -#define GPIO_PCM1_MODE_MASK			BIT(12)
> >> -#define GPIO_PCM_INT_MODE_MASK			BIT(9)
> >> -#define GPIO_PCM_RESET_MODE_MASK		BIT(8)
> >> -#define GPIO_SPI_QUAD_MODE_MASK			BIT(4)
> >> -#define GPIO_SPI_CS4_MODE_MASK			BIT(3)
> >> -#define GPIO_SPI_CS3_MODE_MASK			BIT(2)
> >> -#define GPIO_SPI_CS2_MODE_MASK			BIT(1)
> >> -#define GPIO_SPI_CS1_MODE_MASK			BIT(0)
> >> -
> >> -#define REG_GPIO_PON_MODE			0x021c
> >> -#define AN7583_MDIO_0_GPIO_MODE_MASK		BIT(26)
> >> -#define AN7583_MDC_0_GPIO_MODE_MASK		BIT(25)
> >> -#define AN7583_UART_RXD_GPIO_MODE_MASK		BIT(24)
> >> -#define AN7583_UART_TXD_GPIO_MODE_MASK		BIT(23)
> >> -#define AN7583_SPI_MISO_GPIO_MODE_MASK		BIT(22)
> >> -#define AN7583_SPI_MOSI_GPIO_MODE_MASK		BIT(21)
> >> -#define AN7583_SPI_CS_GPIO_MODE_MASK		BIT(20)
> >> -#define AN7583_SPI_CLK_GPIO_MODE_MASK		BIT(19)
> >> -#define AN7583_I2C1_SDA_GPIO_MODE_MASK		BIT(18)
> >> -#define AN7583_I2C1_SCL_GPIO_MODE_MASK		BIT(17)
> >> -#define AN7583_I2C0_SDA_GPIO_MODE_MASK		BIT(16)
> >> -#define AN7583_I2C0_SCL_GPIO_MODE_MASK		BIT(15)
> >> -#define GPIO_PARALLEL_NAND_MODE_MASK		BIT(14)
> >> -#define GPIO_SGMII_MDIO_MODE_MASK		BIT(13)
> >> -#define GPIO_PCIE_RESET2_MASK			BIT(12)
> >> -#define SIPO_RCLK_MODE_MASK			BIT(11)
> >> -#define GPIO_PCIE_RESET1_MASK			BIT(10)
> >> -#define GPIO_PCIE_RESET0_MASK			BIT(9)
> >> -#define GPIO_UART5_MODE_MASK			BIT(8)
> >> -#define GPIO_UART4_MODE_MASK			BIT(7)
> >> -#define GPIO_HSUART_CTS_RTS_MODE_MASK		BIT(6)
> >> -#define GPIO_HSUART_MODE_MASK			BIT(5)
> >> -#define GPIO_UART2_CTS_RTS_MODE_MASK		BIT(4)
> >> -#define GPIO_UART2_MODE_MASK			BIT(3)
> >> -#define GPIO_SIPO_MODE_MASK			BIT(2)
> >> -#define GPIO_EMMC_MODE_MASK			BIT(1)
> >> -#define GPIO_PON_MODE_MASK			BIT(0)
> >> -
> >> -#define REG_NPU_UART_EN				0x0224
> >> -#define JTAG_UDI_EN_MASK			BIT(4)
> >> -#define JTAG_DFD_EN_MASK			BIT(3)
> >> -
> >> -#define REG_FORCE_GPIO_EN			0x0228
> >> -#define FORCE_GPIO_EN(n)			BIT(n)
> >> -
> >> -/* LED MAP */
> >> -#define REG_LAN_LED0_MAPPING			0x027c
> >> -#define REG_LAN_LED1_MAPPING			0x0280
> >> -
> >> -#define LAN4_LED_MAPPING_MASK			GENMASK(18, 16)
> >> -#define LAN4_PHY_LED_MAP(_n)			FIELD_PREP_CONST(LAN4_LED_MAPPING_MASK, (_n))
> >> -
> >> -#define LAN3_LED_MAPPING_MASK			GENMASK(14, 12)
> >> -#define LAN3_PHY_LED_MAP(_n)			FIELD_PREP_CONST(LAN3_LED_MAPPING_MASK, (_n))
> >> -
> >> -#define LAN2_LED_MAPPING_MASK			GENMASK(10, 8)
> >> -#define LAN2_PHY_LED_MAP(_n)			FIELD_PREP_CONST(LAN2_LED_MAPPING_MASK, (_n))
> >> -
> >> -#define LAN1_LED_MAPPING_MASK			GENMASK(6, 4)
> >> -#define LAN1_PHY_LED_MAP(_n)			FIELD_PREP_CONST(LAN1_LED_MAPPING_MASK, (_n))
> >> -
> >> -#define LAN0_LED_MAPPING_MASK			GENMASK(2, 0)
> >> -#define LAN0_PHY_LED_MAP(_n)			FIELD_PREP_CONST(LAN0_LED_MAPPING_MASK, (_n))
> >> -
> >> -/* CONF */
> >> -#define REG_I2C_SDA_E2				0x001c
> >> -#define AN7583_I2C1_SCL_E2_MASK			BIT(16)
> >> -#define AN7583_I2C1_SDA_E2_MASK			BIT(15)
> >> -#define SPI_MISO_E2_MASK			BIT(14)
> >> -#define SPI_MOSI_E2_MASK			BIT(13)
> >> -#define SPI_CLK_E2_MASK				BIT(12)
> >> -#define SPI_CS0_E2_MASK				BIT(11)
> >> -#define PCIE2_RESET_E2_MASK			BIT(10)
> >> -#define PCIE1_RESET_E2_MASK			BIT(9)
> >> -#define PCIE0_RESET_E2_MASK			BIT(8)
> >> -#define AN7583_MDIO_0_E2_MASK			BIT(5)
> >> -#define AN7583_MDC_0_E2_MASK			BIT(4)
> >> -#define UART1_RXD_E2_MASK			BIT(3)
> >> -#define UART1_TXD_E2_MASK			BIT(2)
> >> -#define I2C_SCL_E2_MASK				BIT(1)
> >> -#define I2C_SDA_E2_MASK				BIT(0)
> >> -
> >> -#define REG_I2C_SDA_E4				0x0020
> >> -#define AN7583_I2C1_SCL_E4_MASK			BIT(16)
> >> -#define AN7583_I2C1_SDA_E4_MASK			BIT(15)
> >> -#define SPI_MISO_E4_MASK			BIT(14)
> >> -#define SPI_MOSI_E4_MASK			BIT(13)
> >> -#define SPI_CLK_E4_MASK				BIT(12)
> >> -#define SPI_CS0_E4_MASK				BIT(11)
> >> -#define PCIE2_RESET_E4_MASK			BIT(10)
> >> -#define PCIE1_RESET_E4_MASK			BIT(9)
> >> -#define PCIE0_RESET_E4_MASK			BIT(8)
> >> -#define AN7583_MDIO_0_E4_MASK			BIT(5)
> >> -#define AN7583_MDC_0_E4_MASK			BIT(4)
> >> -#define UART1_RXD_E4_MASK			BIT(3)
> >> -#define UART1_TXD_E4_MASK			BIT(2)
> >> -#define I2C_SCL_E4_MASK				BIT(1)
> >> -#define I2C_SDA_E4_MASK				BIT(0)
> >> -
> >> -#define REG_GPIO_L_E2				0x0024
> >> -#define REG_GPIO_L_E4				0x0028
> >> -#define REG_GPIO_H_E2				0x002c
> >> -#define REG_GPIO_H_E4				0x0030
> >> -
> >> -#define REG_I2C_SDA_PU				0x0044
> >> -#define AN7583_I2C1_SCL_PU_MASK			BIT(16)
> >> -#define AN7583_I2C1_SDA_PU_MASK			BIT(15)
> >> -#define SPI_MISO_PU_MASK			BIT(14)
> >> -#define SPI_MOSI_PU_MASK			BIT(13)
> >> -#define SPI_CLK_PU_MASK				BIT(12)
> >> -#define SPI_CS0_PU_MASK				BIT(11)
> >> -#define PCIE2_RESET_PU_MASK			BIT(10)
> >> -#define PCIE1_RESET_PU_MASK			BIT(9)
> >> -#define PCIE0_RESET_PU_MASK			BIT(8)
> >> -#define AN7583_MDIO_0_PU_MASK			BIT(5)
> >> -#define AN7583_MDC_0_PU_MASK			BIT(4)
> >> -#define UART1_RXD_PU_MASK			BIT(3)
> >> -#define UART1_TXD_PU_MASK			BIT(2)
> >> -#define I2C_SCL_PU_MASK				BIT(1)
> >> -#define I2C_SDA_PU_MASK				BIT(0)
> >> -
> >> -#define REG_I2C_SDA_PD				0x0048
> >> -#define AN7583_I2C1_SCL_PD_MASK			BIT(16)
> >> -#define AN7583_I2C1_SDA_PD_MASK			BIT(15)
> >> -#define SPI_MISO_PD_MASK			BIT(14)
> >> -#define SPI_MOSI_PD_MASK			BIT(13)
> >> -#define SPI_CLK_PD_MASK				BIT(12)
> >> -#define SPI_CS0_PD_MASK				BIT(11)
> >> -#define PCIE2_RESET_PD_MASK			BIT(10)
> >> -#define PCIE1_RESET_PD_MASK			BIT(9)
> >> -#define PCIE0_RESET_PD_MASK			BIT(8)
> >> -#define AN7583_MDIO_0_PD_MASK			BIT(5)
> >> -#define AN7583_MDC_0_PD_MASK			BIT(4)
> >> -#define UART1_RXD_PD_MASK			BIT(3)
> >> -#define UART1_TXD_PD_MASK			BIT(2)
> >> -#define I2C_SCL_PD_MASK				BIT(1)
> >> -#define I2C_SDA_PD_MASK				BIT(0)
> >> -
> >> -#define REG_GPIO_L_PU				0x004c
> >> -#define REG_GPIO_L_PD				0x0050
> >> -#define REG_GPIO_H_PU				0x0054
> >> -#define REG_GPIO_H_PD				0x0058
> >> -
> >> -#define REG_PCIE_RESET_OD			0x018c
> >> -#define PCIE2_RESET_OD_MASK			BIT(2)
> >> -#define PCIE1_RESET_OD_MASK			BIT(1)
> >> -#define PCIE0_RESET_OD_MASK			BIT(0)
> >> -
> >> -/* GPIOs */
> >> -#define REG_GPIO_CTRL				0x0000
> >> -#define REG_GPIO_DATA				0x0004
> >> -#define REG_GPIO_INT				0x0008
> >> -#define REG_GPIO_INT_EDGE			0x000c
> >> -#define REG_GPIO_INT_LEVEL			0x0010
> >> -#define REG_GPIO_OE				0x0014
> >> -#define REG_GPIO_CTRL1				0x0020
> >> -#define REG_GPIO_CTRL2				0x0060
> >> -#define REG_GPIO_CTRL3				0x0064
> >> -
> >> -/* PWM MODE CONF */
> >> -#define REG_GPIO_FLASH_MODE_CFG			0x0034
> >> -#define GPIO15_FLASH_MODE_CFG			BIT(15)
> >> -#define GPIO14_FLASH_MODE_CFG			BIT(14)
> >> -#define GPIO13_FLASH_MODE_CFG			BIT(13)
> >> -#define GPIO12_FLASH_MODE_CFG			BIT(12)
> >> -#define GPIO11_FLASH_MODE_CFG			BIT(11)
> >> -#define GPIO10_FLASH_MODE_CFG			BIT(10)
> >> -#define GPIO9_FLASH_MODE_CFG			BIT(9)
> >> -#define GPIO8_FLASH_MODE_CFG			BIT(8)
> >> -#define GPIO7_FLASH_MODE_CFG			BIT(7)
> >> -#define GPIO6_FLASH_MODE_CFG			BIT(6)
> >> -#define GPIO5_FLASH_MODE_CFG			BIT(5)
> >> -#define GPIO4_FLASH_MODE_CFG			BIT(4)
> >> -#define GPIO3_FLASH_MODE_CFG			BIT(3)
> >> -#define GPIO2_FLASH_MODE_CFG			BIT(2)
> >> -#define GPIO1_FLASH_MODE_CFG			BIT(1)
> >> -#define GPIO0_FLASH_MODE_CFG			BIT(0)
> >> -
> >> -/* PWM MODE CONF EXT */
> >> -#define REG_GPIO_FLASH_MODE_CFG_EXT		0x0068
> >> -#define GPIO51_FLASH_MODE_CFG			BIT(31)
> >> -#define GPIO50_FLASH_MODE_CFG			BIT(30)
> >> -#define GPIO49_FLASH_MODE_CFG			BIT(29)
> >> -#define GPIO48_FLASH_MODE_CFG			BIT(28)
> >> -#define GPIO47_FLASH_MODE_CFG			BIT(27)
> >> -#define GPIO46_FLASH_MODE_CFG			BIT(26)
> >> -#define GPIO45_FLASH_MODE_CFG			BIT(25)
> >> -#define GPIO44_FLASH_MODE_CFG			BIT(24)
> >> -#define GPIO43_FLASH_MODE_CFG			BIT(23)
> >> -#define GPIO42_FLASH_MODE_CFG			BIT(22)
> >> -#define GPIO41_FLASH_MODE_CFG			BIT(21)
> >> -#define GPIO40_FLASH_MODE_CFG			BIT(20)
> >> -#define GPIO39_FLASH_MODE_CFG			BIT(19)
> >> -#define GPIO38_FLASH_MODE_CFG			BIT(18)
> >> -#define GPIO37_FLASH_MODE_CFG			BIT(17)
> >> -#define GPIO36_FLASH_MODE_CFG			BIT(16)
> >> -#define GPIO31_FLASH_MODE_CFG			BIT(15)
> >> -#define GPIO30_FLASH_MODE_CFG			BIT(14)
> >> -#define GPIO29_FLASH_MODE_CFG			BIT(13)
> >> -#define GPIO28_FLASH_MODE_CFG			BIT(12)
> >> -#define GPIO27_FLASH_MODE_CFG			BIT(11)
> >> -#define GPIO26_FLASH_MODE_CFG			BIT(10)
> >> -#define GPIO25_FLASH_MODE_CFG			BIT(9)
> >> -#define GPIO24_FLASH_MODE_CFG			BIT(8)
> >> -#define GPIO23_FLASH_MODE_CFG			BIT(7)
> >> -#define GPIO22_FLASH_MODE_CFG			BIT(6)
> >> -#define GPIO21_FLASH_MODE_CFG			BIT(5)
> >> -#define GPIO20_FLASH_MODE_CFG			BIT(4)
> >> -#define GPIO19_FLASH_MODE_CFG			BIT(3)
> >> -#define GPIO18_FLASH_MODE_CFG			BIT(2)
> >> -#define GPIO17_FLASH_MODE_CFG			BIT(1)
> >> -#define GPIO16_FLASH_MODE_CFG			BIT(0)
> >> -
> >> -#define REG_GPIO_DATA1				0x0070
> >> -#define REG_GPIO_OE1				0x0078
> >> -#define REG_GPIO_INT1				0x007c
> >> -#define REG_GPIO_INT_EDGE1			0x0080
> >> -#define REG_GPIO_INT_EDGE2			0x0084
> >> -#define REG_GPIO_INT_EDGE3			0x0088
> >> -#define REG_GPIO_INT_LEVEL1			0x008c
> >> -#define REG_GPIO_INT_LEVEL2			0x0090
> >> -#define REG_GPIO_INT_LEVEL3			0x0094
> >> -
> >> -#define AIROHA_PINCTRL_GPIO(gpio, mux_val)			\
> >> -	{							\
> >> -		.name = (gpio),					\
> >> -		.regmap[0] = {					\
> >> -			AIROHA_FUNC_MUX,			\
> >> -			REG_GPIO_PON_MODE,			\
> >> -			(mux_val),				\
> >> -			(mux_val)				\
> >> -		},						\
> >> -		.regmap_size = 1,				\
> >> -	}
> >> -
> >> -#define AIROHA_PINCTRL_GPIO_EXT(gpio, mux_val, smux_val)	\
> >> -	{							\
> >> -		.name = (gpio),					\
> >> -		.regmap[0] = {					\
> >> -			AIROHA_FUNC_PWM_EXT_MUX,		\
> >> -			REG_GPIO_FLASH_MODE_CFG_EXT,		\
> >> -			(mux_val),				\
> >> -			0					\
> >> -		},						\
> >> -		.regmap[1] = {					\
> >> -			AIROHA_FUNC_MUX,			\
> >> -			REG_GPIO_PON_MODE,			\
> >> -			(smux_val),				\
> >> -			(smux_val)				\
> >> -		},						\
> >> -		.regmap_size = 2,				\
> >> -	}
> >> -
> >> -/* PWM */
> >> -#define AIROHA_PINCTRL_PWM(gpio, mux_val)		\
> >> -	{						\
> >> -		.name = (gpio),				\
> >> -		.regmap[0] = {				\
> >> -			AIROHA_FUNC_PWM_MUX,		\
> >> -			REG_GPIO_FLASH_MODE_CFG,	\
> >> -			(mux_val),			\
> >> -			(mux_val)			\
> >> -		},					\
> >> -		.regmap_size = 1,			\
> >> -	}
> >> -
> >> -#define AIROHA_PINCTRL_PWM_EXT(gpio, mux_val)		\
> >> -	{						\
> >> -		.name = (gpio),				\
> >> -		.regmap[0] = {				\
> >> -			AIROHA_FUNC_PWM_EXT_MUX,	\
> >> -			REG_GPIO_FLASH_MODE_CFG_EXT,	\
> >> -			(mux_val),			\
> >> -			(mux_val)			\
> >> -		},					\
> >> -		.regmap_size = 1,			\
> >> -	}
> >> -
> >> -#define AIROHA_PINCTRL_PWM_EXT_SEC(gpio, mux_val, smux_val)	\
> >> -	{							\
> >> -		.name = (gpio),					\
> >> -		.regmap[0] = {					\
> >> -			AIROHA_FUNC_PWM_EXT_MUX,		\
> >> -			REG_GPIO_FLASH_MODE_CFG_EXT,		\
> >> -			(mux_val),				\
> >> -			(mux_val)				\
> >> -		},						\
> >> -		.regmap[1] = {					\
> >> -			AIROHA_FUNC_MUX,			\
> >> -			REG_GPIO_PON_MODE,			\
> >> -			(smux_val),				\
> >> -			(smux_val)				\
> >> -		},						\
> >> -		.regmap_size = 2,				\
> >> -	}
> >> -
> >> -#define AIROHA_PINCTRL_PHY_LED0(gpio, mux_val, map_mask, map_val)	\
> >> -	{								\
> >> -		.name = (gpio),						\
> >> -		.regmap[0] = {						\
> >> -			AIROHA_FUNC_MUX,				\
> >> -			REG_GPIO_2ND_I2C_MODE,				\
> >> -			(mux_val),					\
> >> -			(mux_val),					\
> >> -		},							\
> >> -		.regmap[1] = {						\
> >> -			AIROHA_FUNC_MUX,				\
> >> -			REG_LAN_LED0_MAPPING,				\
> >> -			(map_mask),					\
> >> -			(map_val),					\
> >> -		},							\
> >> -		.regmap_size = 2,					\
> >> -	}
> >> -
> >> -#define AIROHA_PINCTRL_PHY_LED1(gpio, mux_val, map_mask, map_val)	\
> >> -	{								\
> >> -		.name = (gpio),						\
> >> -		.regmap[0] = {						\
> >> -			AIROHA_FUNC_MUX,				\
> >> -			REG_GPIO_2ND_I2C_MODE,				\
> >> -			(mux_val),					\
> >> -			(mux_val),					\
> >> -		},							\
> >> -		.regmap[1] = {						\
> >> -			AIROHA_FUNC_MUX,				\
> >> -			REG_LAN_LED1_MAPPING,				\
> >> -			(map_mask),					\
> >> -			(map_val),					\
> >> -		},							\
> >> -		.regmap_size = 2,					\
> >> -	}
> >> -
> >>  #define airoha_pinctrl_get_pullup_conf(pinctrl, pin, val)			\
> >>  	airoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_PULLUP,		\
> >>  				(pin), (val))
> >> @@ -433,1935 +74,6 @@ static const u32 irq_edge_regs[] = {
> >>  	REG_GPIO_INT_EDGE3
> >>  };
> >>  
> >> -static struct pinctrl_pin_desc en7581_pinctrl_pins[] = {
> >> -	PINCTRL_PIN(0, "uart1_txd"),
> >> -	PINCTRL_PIN(1, "uart1_rxd"),
> >> -	PINCTRL_PIN(2, "i2c_scl"),
> >> -	PINCTRL_PIN(3, "i2c_sda"),
> >> -	PINCTRL_PIN(4, "spi_cs0"),
> >> -	PINCTRL_PIN(5, "spi_clk"),
> >> -	PINCTRL_PIN(6, "spi_mosi"),
> >> -	PINCTRL_PIN(7, "spi_miso"),
> >> -	PINCTRL_PIN(13, "gpio0"),
> >> -	PINCTRL_PIN(14, "gpio1"),
> >> -	PINCTRL_PIN(15, "gpio2"),
> >> -	PINCTRL_PIN(16, "gpio3"),
> >> -	PINCTRL_PIN(17, "gpio4"),
> >> -	PINCTRL_PIN(18, "gpio5"),
> >> -	PINCTRL_PIN(19, "gpio6"),
> >> -	PINCTRL_PIN(20, "gpio7"),
> >> -	PINCTRL_PIN(21, "gpio8"),
> >> -	PINCTRL_PIN(22, "gpio9"),
> >> -	PINCTRL_PIN(23, "gpio10"),
> >> -	PINCTRL_PIN(24, "gpio11"),
> >> -	PINCTRL_PIN(25, "gpio12"),
> >> -	PINCTRL_PIN(26, "gpio13"),
> >> -	PINCTRL_PIN(27, "gpio14"),
> >> -	PINCTRL_PIN(28, "gpio15"),
> >> -	PINCTRL_PIN(29, "gpio16"),
> >> -	PINCTRL_PIN(30, "gpio17"),
> >> -	PINCTRL_PIN(31, "gpio18"),
> >> -	PINCTRL_PIN(32, "gpio19"),
> >> -	PINCTRL_PIN(33, "gpio20"),
> >> -	PINCTRL_PIN(34, "gpio21"),
> >> -	PINCTRL_PIN(35, "gpio22"),
> >> -	PINCTRL_PIN(36, "gpio23"),
> >> -	PINCTRL_PIN(37, "gpio24"),
> >> -	PINCTRL_PIN(38, "gpio25"),
> >> -	PINCTRL_PIN(39, "gpio26"),
> >> -	PINCTRL_PIN(40, "gpio27"),
> >> -	PINCTRL_PIN(41, "gpio28"),
> >> -	PINCTRL_PIN(42, "gpio29"),
> >> -	PINCTRL_PIN(43, "gpio30"),
> >> -	PINCTRL_PIN(44, "gpio31"),
> >> -	PINCTRL_PIN(45, "gpio32"),
> >> -	PINCTRL_PIN(46, "gpio33"),
> >> -	PINCTRL_PIN(47, "gpio34"),
> >> -	PINCTRL_PIN(48, "gpio35"),
> >> -	PINCTRL_PIN(49, "gpio36"),
> >> -	PINCTRL_PIN(50, "gpio37"),
> >> -	PINCTRL_PIN(51, "gpio38"),
> >> -	PINCTRL_PIN(52, "gpio39"),
> >> -	PINCTRL_PIN(53, "gpio40"),
> >> -	PINCTRL_PIN(54, "gpio41"),
> >> -	PINCTRL_PIN(55, "gpio42"),
> >> -	PINCTRL_PIN(56, "gpio43"),
> >> -	PINCTRL_PIN(57, "gpio44"),
> >> -	PINCTRL_PIN(58, "gpio45"),
> >> -	PINCTRL_PIN(59, "gpio46"),
> >> -	PINCTRL_PIN(60, "pcie_reset0"),
> >> -	PINCTRL_PIN(61, "pcie_reset1"),
> >> -	PINCTRL_PIN(62, "pcie_reset2"),
> >> -};
> >> -
> >> -static const int en7581_pon_pins[] = { 49, 50, 51, 52, 53, 54 };
> >> -static const int en7581_pon_tod_1pps_pins[] = { 46 };
> >> -static const int en7581_gsw_tod_1pps_pins[] = { 46 };
> >> -static const int en7581_sipo_pins[] = { 16, 17 };
> >> -static const int en7581_sipo_rclk_pins[] = { 16, 17, 43 };
> >> -static const int en7581_mdio_pins[] = { 14, 15 };
> >> -static const int en7581_uart2_pins[] = { 48, 55 };
> >> -static const int en7581_uart2_cts_rts_pins[] = { 46, 47 };
> >> -static const int en7581_hsuart_pins[] = { 28, 29 };
> >> -static const int en7581_hsuart_cts_rts_pins[] = { 26, 27 };
> >> -static const int en7581_uart4_pins[] = { 38, 39 };
> >> -static const int en7581_uart5_pins[] = { 18, 19 };
> >> -static const int en7581_i2c0_pins[] = { 2, 3 };
> >> -static const int en7581_i2c1_pins[] = { 14, 15 };
> >> -static const int en7581_jtag_udi_pins[] = { 16, 17, 18, 19, 20 };
> >> -static const int en7581_jtag_dfd_pins[] = { 16, 17, 18, 19, 20 };
> >> -static const int en7581_i2s_pins[] = { 26, 27, 28, 29 };
> >> -static const int en7581_pcm1_pins[] = { 22, 23, 24, 25 };
> >> -static const int en7581_pcm2_pins[] = { 18, 19, 20, 21 };
> >> -static const int en7581_spi_quad_pins[] = { 32, 33 };
> >> -static const int en7581_spi_pins[] = { 4, 5, 6, 7 };
> >> -static const int en7581_spi_cs1_pins[] = { 34 };
> >> -static const int en7581_pcm_spi_pins[] = { 18, 19, 20, 21, 22, 23, 24, 25 };
> >> -static const int en7581_pcm_spi_int_pins[] = { 14 };
> >> -static const int en7581_pcm_spi_rst_pins[] = { 15 };
> >> -static const int en7581_pcm_spi_cs1_pins[] = { 43 };
> >> -static const int en7581_pcm_spi_cs2_pins[] = { 40 };
> >> -static const int en7581_pcm_spi_cs2_p128_pins[] = { 40 };
> >> -static const int en7581_pcm_spi_cs2_p156_pins[] = { 40 };
> >> -static const int en7581_pcm_spi_cs3_pins[] = { 41 };
> >> -static const int en7581_pcm_spi_cs4_pins[] = { 42 };
> >> -static const int en7581_emmc_pins[] = { 4, 5, 6, 30, 31, 32, 33, 34, 35, 36, 37 };
> >> -static const int en7581_pnand_pins[] = { 4, 5, 6, 7, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42 };
> >> -static const int en7581_gpio0_pins[] = { 13 };
> >> -static const int en7581_gpio1_pins[] = { 14 };
> >> -static const int en7581_gpio2_pins[] = { 15 };
> >> -static const int en7581_gpio3_pins[] = { 16 };
> >> -static const int en7581_gpio4_pins[] = { 17 };
> >> -static const int en7581_gpio5_pins[] = { 18 };
> >> -static const int en7581_gpio6_pins[] = { 19 };
> >> -static const int en7581_gpio7_pins[] = { 20 };
> >> -static const int en7581_gpio8_pins[] = { 21 };
> >> -static const int en7581_gpio9_pins[] = { 22 };
> >> -static const int en7581_gpio10_pins[] = { 23 };
> >> -static const int en7581_gpio11_pins[] = { 24 };
> >> -static const int en7581_gpio12_pins[] = { 25 };
> >> -static const int en7581_gpio13_pins[] = { 26 };
> >> -static const int en7581_gpio14_pins[] = { 27 };
> >> -static const int en7581_gpio15_pins[] = { 28 };
> >> -static const int en7581_gpio16_pins[] = { 29 };
> >> -static const int en7581_gpio17_pins[] = { 30 };
> >> -static const int en7581_gpio18_pins[] = { 31 };
> >> -static const int en7581_gpio19_pins[] = { 32 };
> >> -static const int en7581_gpio20_pins[] = { 33 };
> >> -static const int en7581_gpio21_pins[] = { 34 };
> >> -static const int en7581_gpio22_pins[] = { 35 };
> >> -static const int en7581_gpio23_pins[] = { 36 };
> >> -static const int en7581_gpio24_pins[] = { 37 };
> >> -static const int en7581_gpio25_pins[] = { 38 };
> >> -static const int en7581_gpio26_pins[] = { 39 };
> >> -static const int en7581_gpio27_pins[] = { 40 };
> >> -static const int en7581_gpio28_pins[] = { 41 };
> >> -static const int en7581_gpio29_pins[] = { 42 };
> >> -static const int en7581_gpio30_pins[] = { 43 };
> >> -static const int en7581_gpio31_pins[] = { 44 };
> >> -static const int en7581_gpio32_pins[] = { 45 };
> >> -static const int en7581_gpio33_pins[] = { 46 };
> >> -static const int en7581_gpio34_pins[] = { 47 };
> >> -static const int en7581_gpio35_pins[] = { 48 };
> >> -static const int en7581_gpio36_pins[] = { 49 };
> >> -static const int en7581_gpio37_pins[] = { 50 };
> >> -static const int en7581_gpio38_pins[] = { 51 };
> >> -static const int en7581_gpio39_pins[] = { 52 };
> >> -static const int en7581_gpio40_pins[] = { 53 };
> >> -static const int en7581_gpio41_pins[] = { 54 };
> >> -static const int en7581_gpio42_pins[] = { 55 };
> >> -static const int en7581_gpio43_pins[] = { 56 };
> >> -static const int en7581_gpio44_pins[] = { 57 };
> >> -static const int en7581_gpio45_pins[] = { 58 };
> >> -static const int en7581_gpio46_pins[] = { 59 };
> >> -static const int en7581_gpio47_pins[] = { 60 };
> >> -static const int en7581_gpio48_pins[] = { 61 };
> >> -static const int en7581_gpio49_pins[] = { 62 };
> >> -static const int en7581_pcie_reset0_pins[] = { 60 };
> >> -static const int en7581_pcie_reset1_pins[] = { 61 };
> >> -static const int en7581_pcie_reset2_pins[] = { 62 };
> >> -
> >> -static const struct pingroup en7581_pinctrl_groups[] = {
> >> -	PINCTRL_PIN_GROUP("pon", en7581_pon),
> >> -	PINCTRL_PIN_GROUP("pon_tod_1pps", en7581_pon_tod_1pps),
> >> -	PINCTRL_PIN_GROUP("gsw_tod_1pps", en7581_gsw_tod_1pps),
> >> -	PINCTRL_PIN_GROUP("sipo", en7581_sipo),
> >> -	PINCTRL_PIN_GROUP("sipo_rclk", en7581_sipo_rclk),
> >> -	PINCTRL_PIN_GROUP("mdio", en7581_mdio),
> >> -	PINCTRL_PIN_GROUP("uart2", en7581_uart2),
> >> -	PINCTRL_PIN_GROUP("uart2_cts_rts", en7581_uart2_cts_rts),
> >> -	PINCTRL_PIN_GROUP("hsuart", en7581_hsuart),
> >> -	PINCTRL_PIN_GROUP("hsuart_cts_rts", en7581_hsuart_cts_rts),
> >> -	PINCTRL_PIN_GROUP("uart4", en7581_uart4),
> >> -	PINCTRL_PIN_GROUP("uart5", en7581_uart5),
> >> -	PINCTRL_PIN_GROUP("i2c0", en7581_i2c0),
> >> -	PINCTRL_PIN_GROUP("i2c1", en7581_i2c1),
> >> -	PINCTRL_PIN_GROUP("jtag_udi", en7581_jtag_udi),
> >> -	PINCTRL_PIN_GROUP("jtag_dfd", en7581_jtag_dfd),
> >> -	PINCTRL_PIN_GROUP("i2s", en7581_i2s),
> >> -	PINCTRL_PIN_GROUP("pcm1", en7581_pcm1),
> >> -	PINCTRL_PIN_GROUP("pcm2", en7581_pcm2),
> >> -	PINCTRL_PIN_GROUP("spi", en7581_spi),
> >> -	PINCTRL_PIN_GROUP("spi_quad", en7581_spi_quad),
> >> -	PINCTRL_PIN_GROUP("spi_cs1", en7581_spi_cs1),
> >> -	PINCTRL_PIN_GROUP("pcm_spi", en7581_pcm_spi),
> >> -	PINCTRL_PIN_GROUP("pcm_spi_int", en7581_pcm_spi_int),
> >> -	PINCTRL_PIN_GROUP("pcm_spi_rst", en7581_pcm_spi_rst),
> >> -	PINCTRL_PIN_GROUP("pcm_spi_cs1", en7581_pcm_spi_cs1),
> >> -	PINCTRL_PIN_GROUP("pcm_spi_cs2_p128", en7581_pcm_spi_cs2_p128),
> >> -	PINCTRL_PIN_GROUP("pcm_spi_cs2_p156", en7581_pcm_spi_cs2_p156),
> >> -	PINCTRL_PIN_GROUP("pcm_spi_cs2", en7581_pcm_spi_cs2),
> >> -	PINCTRL_PIN_GROUP("pcm_spi_cs3", en7581_pcm_spi_cs3),
> >> -	PINCTRL_PIN_GROUP("pcm_spi_cs4", en7581_pcm_spi_cs4),
> >> -	PINCTRL_PIN_GROUP("emmc", en7581_emmc),
> >> -	PINCTRL_PIN_GROUP("pnand", en7581_pnand),
> >> -	PINCTRL_PIN_GROUP("gpio0", en7581_gpio0),
> >> -	PINCTRL_PIN_GROUP("gpio1", en7581_gpio1),
> >> -	PINCTRL_PIN_GROUP("gpio2", en7581_gpio2),
> >> -	PINCTRL_PIN_GROUP("gpio3", en7581_gpio3),
> >> -	PINCTRL_PIN_GROUP("gpio4", en7581_gpio4),
> >> -	PINCTRL_PIN_GROUP("gpio5", en7581_gpio5),
> >> -	PINCTRL_PIN_GROUP("gpio6", en7581_gpio6),
> >> -	PINCTRL_PIN_GROUP("gpio7", en7581_gpio7),
> >> -	PINCTRL_PIN_GROUP("gpio8", en7581_gpio8),
> >> -	PINCTRL_PIN_GROUP("gpio9", en7581_gpio9),
> >> -	PINCTRL_PIN_GROUP("gpio10", en7581_gpio10),
> >> -	PINCTRL_PIN_GROUP("gpio11", en7581_gpio11),
> >> -	PINCTRL_PIN_GROUP("gpio12", en7581_gpio12),
> >> -	PINCTRL_PIN_GROUP("gpio13", en7581_gpio13),
> >> -	PINCTRL_PIN_GROUP("gpio14", en7581_gpio14),
> >> -	PINCTRL_PIN_GROUP("gpio15", en7581_gpio15),
> >> -	PINCTRL_PIN_GROUP("gpio16", en7581_gpio16),
> >> -	PINCTRL_PIN_GROUP("gpio17", en7581_gpio17),
> >> -	PINCTRL_PIN_GROUP("gpio18", en7581_gpio18),
> >> -	PINCTRL_PIN_GROUP("gpio19", en7581_gpio19),
> >> -	PINCTRL_PIN_GROUP("gpio20", en7581_gpio20),
> >> -	PINCTRL_PIN_GROUP("gpio21", en7581_gpio21),
> >> -	PINCTRL_PIN_GROUP("gpio22", en7581_gpio22),
> >> -	PINCTRL_PIN_GROUP("gpio23", en7581_gpio23),
> >> -	PINCTRL_PIN_GROUP("gpio24", en7581_gpio24),
> >> -	PINCTRL_PIN_GROUP("gpio25", en7581_gpio25),
> >> -	PINCTRL_PIN_GROUP("gpio26", en7581_gpio26),
> >> -	PINCTRL_PIN_GROUP("gpio27", en7581_gpio27),
> >> -	PINCTRL_PIN_GROUP("gpio28", en7581_gpio28),
> >> -	PINCTRL_PIN_GROUP("gpio29", en7581_gpio29),
> >> -	PINCTRL_PIN_GROUP("gpio30", en7581_gpio30),
> >> -	PINCTRL_PIN_GROUP("gpio31", en7581_gpio31),
> >> -	PINCTRL_PIN_GROUP("gpio32", en7581_gpio32),
> >> -	PINCTRL_PIN_GROUP("gpio33", en7581_gpio33),
> >> -	PINCTRL_PIN_GROUP("gpio34", en7581_gpio34),
> >> -	PINCTRL_PIN_GROUP("gpio35", en7581_gpio35),
> >> -	PINCTRL_PIN_GROUP("gpio36", en7581_gpio36),
> >> -	PINCTRL_PIN_GROUP("gpio37", en7581_gpio37),
> >> -	PINCTRL_PIN_GROUP("gpio38", en7581_gpio38),
> >> -	PINCTRL_PIN_GROUP("gpio39", en7581_gpio39),
> >> -	PINCTRL_PIN_GROUP("gpio40", en7581_gpio40),
> >> -	PINCTRL_PIN_GROUP("gpio41", en7581_gpio41),
> >> -	PINCTRL_PIN_GROUP("gpio42", en7581_gpio42),
> >> -	PINCTRL_PIN_GROUP("gpio43", en7581_gpio43),
> >> -	PINCTRL_PIN_GROUP("gpio44", en7581_gpio44),
> >> -	PINCTRL_PIN_GROUP("gpio45", en7581_gpio45),
> >> -	PINCTRL_PIN_GROUP("gpio46", en7581_gpio46),
> >> -	PINCTRL_PIN_GROUP("gpio47", en7581_gpio47),
> >> -	PINCTRL_PIN_GROUP("gpio48", en7581_gpio48),
> >> -	PINCTRL_PIN_GROUP("gpio49", en7581_gpio49),
> >> -	PINCTRL_PIN_GROUP("pcie_reset0", en7581_pcie_reset0),
> >> -	PINCTRL_PIN_GROUP("pcie_reset1", en7581_pcie_reset1),
> >> -	PINCTRL_PIN_GROUP("pcie_reset2", en7581_pcie_reset2),
> >> -};
> >> -
> >> -static struct pinctrl_pin_desc an7583_pinctrl_pins[] = {
> >> -	PINCTRL_PIN(2, "gpio0"),
> >> -	PINCTRL_PIN(3, "gpio1"),
> >> -	PINCTRL_PIN(4, "gpio2"),
> >> -	PINCTRL_PIN(5, "gpio3"),
> >> -	PINCTRL_PIN(6, "gpio4"),
> >> -	PINCTRL_PIN(7, "gpio5"),
> >> -	PINCTRL_PIN(8, "gpio6"),
> >> -	PINCTRL_PIN(9, "gpio7"),
> >> -	PINCTRL_PIN(10, "gpio8"),
> >> -	PINCTRL_PIN(11, "gpio9"),
> >> -	PINCTRL_PIN(12, "gpio10"),
> >> -	PINCTRL_PIN(13, "gpio11"),
> >> -	PINCTRL_PIN(14, "gpio12"),
> >> -	PINCTRL_PIN(15, "gpio13"),
> >> -	PINCTRL_PIN(16, "gpio14"),
> >> -	PINCTRL_PIN(17, "gpio15"),
> >> -	PINCTRL_PIN(18, "gpio16"),
> >> -	PINCTRL_PIN(19, "gpio17"),
> >> -	PINCTRL_PIN(20, "gpio18"),
> >> -	PINCTRL_PIN(21, "gpio19"),
> >> -	PINCTRL_PIN(22, "gpio20"),
> >> -	PINCTRL_PIN(23, "gpio21"),
> >> -	PINCTRL_PIN(24, "gpio22"),
> >> -	PINCTRL_PIN(25, "gpio23"),
> >> -	PINCTRL_PIN(26, "gpio24"),
> >> -	PINCTRL_PIN(27, "gpio25"),
> >> -	PINCTRL_PIN(28, "gpio26"),
> >> -	PINCTRL_PIN(29, "gpio27"),
> >> -	PINCTRL_PIN(30, "gpio28"),
> >> -	PINCTRL_PIN(31, "gpio29"),
> >> -	PINCTRL_PIN(32, "gpio30"),
> >> -	PINCTRL_PIN(33, "gpio31"),
> >> -	PINCTRL_PIN(34, "gpio32"),
> >> -	PINCTRL_PIN(35, "gpio33"),
> >> -	PINCTRL_PIN(36, "gpio34"),
> >> -	PINCTRL_PIN(37, "gpio35"),
> >> -	PINCTRL_PIN(38, "gpio36"),
> >> -	PINCTRL_PIN(39, "gpio37"),
> >> -	PINCTRL_PIN(40, "gpio38"),
> >> -	PINCTRL_PIN(41, "i2c0_scl"),
> >> -	PINCTRL_PIN(42, "i2c0_sda"),
> >> -	PINCTRL_PIN(43, "i2c1_scl"),
> >> -	PINCTRL_PIN(44, "i2c1_sda"),
> >> -	PINCTRL_PIN(45, "spi_clk"),
> >> -	PINCTRL_PIN(46, "spi_cs"),
> >> -	PINCTRL_PIN(47, "spi_mosi"),
> >> -	PINCTRL_PIN(48, "spi_miso"),
> >> -	PINCTRL_PIN(49, "uart_txd"),
> >> -	PINCTRL_PIN(50, "uart_rxd"),
> >> -	PINCTRL_PIN(51, "pcie_reset0"),
> >> -	PINCTRL_PIN(52, "pcie_reset1"),
> >> -	PINCTRL_PIN(53, "mdc_0"),
> >> -	PINCTRL_PIN(54, "mdio_0"),
> >> -};
> >> -
> >> -static const int an7583_pon_pins[] = { 15, 16, 17, 18, 19, 20 };
> >> -static const int an7583_pon_tod_1pps_pins[] = { 32 };
> >> -static const int an7583_gsw_tod_1pps_pins[] = { 32 };
> >> -static const int an7583_sipo_pins[] = { 34, 35 };
> >> -static const int an7583_sipo_rclk_pins[] = { 34, 35, 33 };
> >> -static const int an7583_mdio_pins[] = { 43, 44 };
> >> -static const int an7583_uart2_pins[] = { 34, 35 };
> >> -static const int an7583_uart2_cts_rts_pins[] = { 32, 33 };
> >> -static const int an7583_hsuart_pins[] = { 30, 31 };
> >> -static const int an7583_hsuart_cts_rts_pins[] = { 28, 29 };
> >> -static const int an7583_npu_uart_pins[] = { 7, 8 };
> >> -static const int an7583_uart4_pins[] = { 7, 8 };
> >> -static const int an7583_uart5_pins[] = { 23, 24 };
> >> -static const int an7583_i2c0_pins[] = { 41, 42 };
> >> -static const int an7583_i2c1_pins[] = { 43, 44 };
> >> -static const int an7583_jtag_udi_pins[] = { 23, 24, 22, 25, 26 };
> >> -static const int an7583_jtag_dfd_pins[] = { 23, 24, 22, 25, 26 };
> >> -static const int an7583_pcm1_pins[] = { 10, 11, 12, 13, 14 };
> >> -static const int an7583_pcm2_pins[] = { 28, 29, 30, 31, 24 };
> >> -static const int an7583_spi_pins[] = { 28, 29, 30, 31 };
> >> -static const int an7583_spi_quad_pins[] = { 25, 26 };
> >> -static const int an7583_spi_cs1_pins[] = { 27 };
> >> -static const int an7583_pcm_spi_pins[] = { 28, 29, 30, 31, 10, 11, 12, 13 };
> >> -static const int an7583_pcm_spi_rst_pins[] = { 14 };
> >> -static const int an7583_pcm_spi_cs1_pins[] = { 24 };
> >> -static const int an7583_emmc_pins[] = { 7, 8, 9, 22, 23, 24, 25, 26, 45, 46, 47 };
> >> -static const int an7583_pnand_pins[] = { 7, 8, 9, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 45, 46, 47, 48 };
> >> -static const int an7583_gpio0_pins[] = { 2 };
> >> -static const int an7583_gpio1_pins[] = { 3 };
> >> -static const int an7583_gpio2_pins[] = { 4 };
> >> -static const int an7583_gpio3_pins[] = { 5 };
> >> -static const int an7583_gpio4_pins[] = { 6 };
> >> -static const int an7583_gpio5_pins[] = { 7 };
> >> -static const int an7583_gpio6_pins[] = { 8 };
> >> -static const int an7583_gpio7_pins[] = { 9 };
> >> -static const int an7583_gpio8_pins[] = { 10 };
> >> -static const int an7583_gpio9_pins[] = { 11 };
> >> -static const int an7583_gpio10_pins[] = { 12 };
> >> -static const int an7583_gpio11_pins[] = { 13 };
> >> -static const int an7583_gpio12_pins[] = { 14 };
> >> -static const int an7583_gpio13_pins[] = { 15 };
> >> -static const int an7583_gpio14_pins[] = { 16 };
> >> -static const int an7583_gpio15_pins[] = { 17 };
> >> -static const int an7583_gpio16_pins[] = { 18 };
> >> -static const int an7583_gpio17_pins[] = { 19 };
> >> -static const int an7583_gpio18_pins[] = { 20 };
> >> -static const int an7583_gpio19_pins[] = { 21 };
> >> -static const int an7583_gpio20_pins[] = { 22 };
> >> -static const int an7583_gpio21_pins[] = { 23 };
> >> -static const int an7583_gpio22_pins[] = { 24 };
> >> -static const int an7583_gpio23_pins[] = { 25 };
> >> -static const int an7583_gpio24_pins[] = { 26 };
> >> -static const int an7583_gpio25_pins[] = { 27 };
> >> -static const int an7583_gpio26_pins[] = { 28 };
> >> -static const int an7583_gpio27_pins[] = { 29 };
> >> -static const int an7583_gpio28_pins[] = { 30 };
> >> -static const int an7583_gpio29_pins[] = { 31 };
> >> -static const int an7583_gpio30_pins[] = { 32 };
> >> -static const int an7583_gpio31_pins[] = { 33 };
> >> -static const int an7583_gpio32_pins[] = { 34 };
> >> -static const int an7583_gpio33_pins[] = { 35 };
> >> -static const int an7583_gpio34_pins[] = { 36 };
> >> -static const int an7583_gpio35_pins[] = { 37 };
> >> -static const int an7583_gpio36_pins[] = { 38 };
> >> -static const int an7583_gpio37_pins[] = { 39 };
> >> -static const int an7583_gpio38_pins[] = { 40 };
> >> -static const int an7583_gpio39_pins[] = { 41 };
> >> -static const int an7583_gpio40_pins[] = { 42 };
> >> -static const int an7583_gpio41_pins[] = { 43 };
> >> -static const int an7583_gpio42_pins[] = { 44 };
> >> -static const int an7583_gpio43_pins[] = { 45 };
> >> -static const int an7583_gpio44_pins[] = { 46 };
> >> -static const int an7583_gpio45_pins[] = { 47 };
> >> -static const int an7583_gpio46_pins[] = { 48 };
> >> -static const int an7583_gpio47_pins[] = { 49 };
> >> -static const int an7583_gpio48_pins[] = { 50 };
> >> -static const int an7583_gpio49_pins[] = { 51 };
> >> -static const int an7583_gpio50_pins[] = { 52 };
> >> -static const int an7583_gpio51_pins[] = { 53 };
> >> -static const int an7583_gpio52_pins[] = { 54 };
> >> -static const int an7583_pcie_reset0_pins[] = { 51 };
> >> -static const int an7583_pcie_reset1_pins[] = { 52 };
> >> -
> >> -static const struct pingroup an7583_pinctrl_groups[] = {
> >> -	PINCTRL_PIN_GROUP("pon", an7583_pon),
> >> -	PINCTRL_PIN_GROUP("pon_tod_1pps", an7583_pon_tod_1pps),
> >> -	PINCTRL_PIN_GROUP("gsw_tod_1pps", an7583_gsw_tod_1pps),
> >> -	PINCTRL_PIN_GROUP("sipo", an7583_sipo),
> >> -	PINCTRL_PIN_GROUP("sipo_rclk", an7583_sipo_rclk),
> >> -	PINCTRL_PIN_GROUP("mdio", an7583_mdio),
> >> -	PINCTRL_PIN_GROUP("uart2", an7583_uart2),
> >> -	PINCTRL_PIN_GROUP("uart2_cts_rts", an7583_uart2_cts_rts),
> >> -	PINCTRL_PIN_GROUP("hsuart", an7583_hsuart),
> >> -	PINCTRL_PIN_GROUP("hsuart_cts_rts", an7583_hsuart_cts_rts),
> >> -	PINCTRL_PIN_GROUP("npu_uart", an7583_npu_uart),
> >> -	PINCTRL_PIN_GROUP("uart4", an7583_uart4),
> >> -	PINCTRL_PIN_GROUP("uart5", an7583_uart5),
> >> -	PINCTRL_PIN_GROUP("i2c0", an7583_i2c0),
> >> -	PINCTRL_PIN_GROUP("i2c1", an7583_i2c1),
> >> -	PINCTRL_PIN_GROUP("jtag_udi", an7583_jtag_udi),
> >> -	PINCTRL_PIN_GROUP("jtag_dfd", an7583_jtag_dfd),
> >> -	PINCTRL_PIN_GROUP("pcm1", an7583_pcm1),
> >> -	PINCTRL_PIN_GROUP("pcm2", an7583_pcm2),
> >> -	PINCTRL_PIN_GROUP("spi", an7583_spi),
> >> -	PINCTRL_PIN_GROUP("spi_quad", an7583_spi_quad),
> >> -	PINCTRL_PIN_GROUP("spi_cs1", an7583_spi_cs1),
> >> -	PINCTRL_PIN_GROUP("pcm_spi", an7583_pcm_spi),
> >> -	PINCTRL_PIN_GROUP("pcm_spi_rst", an7583_pcm_spi_rst),
> >> -	PINCTRL_PIN_GROUP("pcm_spi_cs1", an7583_pcm_spi_cs1),
> >> -	PINCTRL_PIN_GROUP("emmc", an7583_emmc),
> >> -	PINCTRL_PIN_GROUP("pnand", an7583_pnand),
> >> -	PINCTRL_PIN_GROUP("gpio0", an7583_gpio0),
> >> -	PINCTRL_PIN_GROUP("gpio1", an7583_gpio1),
> >> -	PINCTRL_PIN_GROUP("gpio2", an7583_gpio2),
> >> -	PINCTRL_PIN_GROUP("gpio3", an7583_gpio3),
> >> -	PINCTRL_PIN_GROUP("gpio4", an7583_gpio4),
> >> -	PINCTRL_PIN_GROUP("gpio5", an7583_gpio5),
> >> -	PINCTRL_PIN_GROUP("gpio6", an7583_gpio6),
> >> -	PINCTRL_PIN_GROUP("gpio7", an7583_gpio7),
> >> -	PINCTRL_PIN_GROUP("gpio8", an7583_gpio8),
> >> -	PINCTRL_PIN_GROUP("gpio9", an7583_gpio9),
> >> -	PINCTRL_PIN_GROUP("gpio10", an7583_gpio10),
> >> -	PINCTRL_PIN_GROUP("gpio11", an7583_gpio11),
> >> -	PINCTRL_PIN_GROUP("gpio12", an7583_gpio12),
> >> -	PINCTRL_PIN_GROUP("gpio13", an7583_gpio13),
> >> -	PINCTRL_PIN_GROUP("gpio14", an7583_gpio14),
> >> -	PINCTRL_PIN_GROUP("gpio15", an7583_gpio15),
> >> -	PINCTRL_PIN_GROUP("gpio16", an7583_gpio16),
> >> -	PINCTRL_PIN_GROUP("gpio17", an7583_gpio17),
> >> -	PINCTRL_PIN_GROUP("gpio18", an7583_gpio18),
> >> -	PINCTRL_PIN_GROUP("gpio19", an7583_gpio19),
> >> -	PINCTRL_PIN_GROUP("gpio20", an7583_gpio20),
> >> -	PINCTRL_PIN_GROUP("gpio21", an7583_gpio21),
> >> -	PINCTRL_PIN_GROUP("gpio22", an7583_gpio22),
> >> -	PINCTRL_PIN_GROUP("gpio23", an7583_gpio23),
> >> -	PINCTRL_PIN_GROUP("gpio24", an7583_gpio24),
> >> -	PINCTRL_PIN_GROUP("gpio25", an7583_gpio25),
> >> -	PINCTRL_PIN_GROUP("gpio26", an7583_gpio26),
> >> -	PINCTRL_PIN_GROUP("gpio27", an7583_gpio27),
> >> -	PINCTRL_PIN_GROUP("gpio28", an7583_gpio28),
> >> -	PINCTRL_PIN_GROUP("gpio29", an7583_gpio29),
> >> -	PINCTRL_PIN_GROUP("gpio30", an7583_gpio30),
> >> -	PINCTRL_PIN_GROUP("gpio31", an7583_gpio31),
> >> -	PINCTRL_PIN_GROUP("gpio32", an7583_gpio32),
> >> -	PINCTRL_PIN_GROUP("gpio33", an7583_gpio33),
> >> -	PINCTRL_PIN_GROUP("gpio34", an7583_gpio34),
> >> -	PINCTRL_PIN_GROUP("gpio35", an7583_gpio35),
> >> -	PINCTRL_PIN_GROUP("gpio36", an7583_gpio36),
> >> -	PINCTRL_PIN_GROUP("gpio37", an7583_gpio37),
> >> -	PINCTRL_PIN_GROUP("gpio38", an7583_gpio38),
> >> -	PINCTRL_PIN_GROUP("gpio39", an7583_gpio39),
> >> -	PINCTRL_PIN_GROUP("gpio40", an7583_gpio40),
> >> -	PINCTRL_PIN_GROUP("gpio41", an7583_gpio41),
> >> -	PINCTRL_PIN_GROUP("gpio42", an7583_gpio42),
> >> -	PINCTRL_PIN_GROUP("gpio43", an7583_gpio43),
> >> -	PINCTRL_PIN_GROUP("gpio44", an7583_gpio44),
> >> -	PINCTRL_PIN_GROUP("gpio45", an7583_gpio45),
> >> -	PINCTRL_PIN_GROUP("gpio46", an7583_gpio46),
> >> -	PINCTRL_PIN_GROUP("gpio47", an7583_gpio47),
> >> -	PINCTRL_PIN_GROUP("gpio48", an7583_gpio48),
> >> -	PINCTRL_PIN_GROUP("gpio49", an7583_gpio49),
> >> -	PINCTRL_PIN_GROUP("gpio50", an7583_gpio50),
> >> -	PINCTRL_PIN_GROUP("gpio51", an7583_gpio51),
> >> -	PINCTRL_PIN_GROUP("gpio52", an7583_gpio52),
> >> -	PINCTRL_PIN_GROUP("pcie_reset0", an7583_pcie_reset0),
> >> -	PINCTRL_PIN_GROUP("pcie_reset1", an7583_pcie_reset1),
> >> -};
> >> -
> >> -static const char *const pon_groups[] = { "pon" };
> >> -static const char *const tod_1pps_groups[] = { "pon_tod_1pps", "gsw_tod_1pps" };
> >> -static const char *const sipo_groups[] = { "sipo", "sipo_rclk" };
> >> -static const char *const mdio_groups[] = { "mdio" };
> >> -static const char *const an7583_mdio_groups[] = { "mdio" };
> >> -static const char *const uart_groups[] = { "uart2", "uart2_cts_rts", "hsuart",
> >> -					   "hsuart_cts_rts", "uart4",
> >> -					   "uart5" };
> >> -static const char *const i2c_groups[] = { "i2c1" };
> >> -static const char *const jtag_groups[] = { "jtag_udi", "jtag_dfd" };
> >> -static const char *const pcm_groups[] = { "pcm1", "pcm2" };
> >> -static const char *const spi_groups[] = { "spi_quad", "spi_cs1" };
> >> -static const char *const pcm_spi_groups[] = { "pcm_spi", "pcm_spi_int",
> >> -					      "pcm_spi_rst", "pcm_spi_cs1",
> >> -					      "pcm_spi_cs2_p156",
> >> -					      "pcm_spi_cs2_p128",
> >> -					      "pcm_spi_cs3", "pcm_spi_cs4" };
> >> -static const char *const an7583_pcm_spi_groups[] = { "pcm_spi",
> >> -						     "pcm_spi_rst", "pcm_spi_cs1" };
> >> -static const char *const i2s_groups[] = { "i2s" };
> >> -static const char *const emmc_groups[] = { "emmc" };
> >> -static const char *const pnand_groups[] = { "pnand" };
> >> -static const char *const gpio_groups[] = { "gpio47", "gpio48", "gpio49" };
> >> -static const char *const pcie_reset_groups[] = { "pcie_reset0", "pcie_reset1",
> >> -						 "pcie_reset2" };
> >> -static const char *const an7583_gpio_groups[] = { "gpio39", "gpio40", "gpio41",
> >> -						  "gpio42", "gpio43", "gpio44",
> >> -						  "gpio45", "gpio46", "gpio47",
> >> -						  "gpio48", "gpio49", "gpio50",
> >> -						  "gpio51", "gpio52" };
> >> -static const char *const an7583_pcie_reset_groups[] = { "pcie_reset0", "pcie_reset1" };
> >> -static const char *const pwm_groups[] = { "gpio0", "gpio1",
> >> -					  "gpio2", "gpio3",
> >> -					  "gpio4", "gpio5",
> >> -					  "gpio6", "gpio7",
> >> -					  "gpio8", "gpio9",
> >> -					  "gpio10", "gpio11",
> >> -					  "gpio12", "gpio13",
> >> -					  "gpio14", "gpio15",
> >> -					  "gpio16", "gpio17",
> >> -					  "gpio18", "gpio19",
> >> -					  "gpio20", "gpio21",
> >> -					  "gpio22", "gpio23",
> >> -					  "gpio24", "gpio25",
> >> -					  "gpio26", "gpio27",
> >> -					  "gpio28", "gpio29",
> >> -					  "gpio30", "gpio31",
> >> -					  "gpio36", "gpio37",
> >> -					  "gpio38", "gpio39",
> >> -					  "gpio40", "gpio41",
> >> -					  "gpio42", "gpio43",
> >> -					  "gpio44", "gpio45",
> >> -					  "gpio46", "gpio47",
> >> -					  "gpio48", "gpio49" };
> >> -static const char *const an7583_pwm_groups[] = { "gpio0", "gpio1",
> >> -						 "gpio2", "gpio3",
> >> -						 "gpio4", "gpio5",
> >> -						 "gpio6", "gpio7",
> >> -						 "gpio8", "gpio9",
> >> -						 "gpio10", "gpio11",
> >> -						 "gpio12", "gpio13",
> >> -						 "gpio14", "gpio15",
> >> -						 "gpio16", "gpio17",
> >> -						 "gpio18", "gpio19",
> >> -						 "gpio20", "gpio21",
> >> -						 "gpio22", "gpio23",
> >> -						 "gpio24", "gpio25",
> >> -						 "gpio26", "gpio27",
> >> -						 "gpio28", "gpio29",
> >> -						 "gpio30", "gpio31",
> >> -						 "gpio36", "gpio37",
> >> -						 "gpio38", "gpio39",
> >> -						 "gpio40", "gpio41",
> >> -						 "gpio42", "gpio43",
> >> -						 "gpio44", "gpio45",
> >> -						 "gpio46", "gpio47",
> >> -						 "gpio48", "gpio49",
> >> -						 "gpio50", "gpio51" };
> >> -static const char *const phy1_led0_groups[] = { "gpio33", "gpio34",
> >> -						"gpio35", "gpio42" };
> >> -static const char *const phy2_led0_groups[] = { "gpio33", "gpio34",
> >> -						"gpio35", "gpio42" };
> >> -static const char *const phy3_led0_groups[] = { "gpio33", "gpio34",
> >> -						"gpio35", "gpio42" };
> >> -static const char *const phy4_led0_groups[] = { "gpio33", "gpio34",
> >> -						"gpio35", "gpio42" };
> >> -static const char *const phy1_led1_groups[] = { "gpio43", "gpio44",
> >> -						"gpio45", "gpio46" };
> >> -static const char *const phy2_led1_groups[] = { "gpio43", "gpio44",
> >> -						"gpio45", "gpio46" };
> >> -static const char *const phy3_led1_groups[] = { "gpio43", "gpio44",
> >> -						"gpio45", "gpio46" };
> >> -static const char *const phy4_led1_groups[] = { "gpio43", "gpio44",
> >> -						"gpio45", "gpio46" };
> >> -static const char *const an7583_phy1_led0_groups[] = { "gpio1", "gpio2",
> >> -							"gpio3", "gpio4" };
> >> -static const char *const an7583_phy2_led0_groups[] = { "gpio1", "gpio2",
> >> -							"gpio3", "gpio4" };
> >> -static const char *const an7583_phy3_led0_groups[] = { "gpio1", "gpio2",
> >> -							"gpio3", "gpio4" };
> >> -static const char *const an7583_phy4_led0_groups[] = { "gpio1", "gpio2",
> >> -							"gpio3", "gpio4" };
> >> -static const char *const an7583_phy1_led1_groups[] = { "gpio8", "gpio9",
> >> -							"gpio10", "gpio11" };
> >> -static const char *const an7583_phy2_led1_groups[] = { "gpio8", "gpio9",
> >> -							"gpio10", "gpio11" };
> >> -static const char *const an7583_phy3_led1_groups[] = { "gpio8", "gpio9",
> >> -							"gpio10", "gpio11" };
> >> -static const char *const an7583_phy4_led1_groups[] = { "gpio8", "gpio9",
> >> -							"gpio10", "gpio11" };
> >> -
> >> -static const struct airoha_pinctrl_func_group pon_func_group[] = {
> >> -	{
> >> -		.name = "pon",
> >> -		.regmap[0] = {
> >> -			AIROHA_FUNC_MUX,
> >> -			REG_GPIO_PON_MODE,
> >> -			GPIO_PON_MODE_MASK,
> >> -			GPIO_PON_MODE_MASK
> >> -		},
> >> -		.regmap_size = 1,
> >> -	},
> >> -};
> >> -
> >> -static const struct airoha_pinctrl_func_group tod_1pps_func_group[] = {
> >> -	{
> >> -		.name = "pon_tod_1pps",
> >> -		.regmap[0] = {
> >> -			AIROHA_FUNC_MUX,
> >> -			REG_GPIO_2ND_I2C_MODE,
> >> -			PON_TOD_1PPS_MODE_MASK,
> >> -			PON_TOD_1PPS_MODE_MASK
> >> -		},
> >> -		.regmap_size = 1,
> >> -	}, {
> >> -		.name = "gsw_tod_1pps",
> >> -		.regmap[0] = {
> >> -			AIROHA_FUNC_MUX,
> >> -			REG_GPIO_2ND_I2C_MODE,
> >> -			GSW_TOD_1PPS_MODE_MASK,
> >> -			GSW_TOD_1PPS_MODE_MASK
> >> -		},
> >> -		.regmap_size = 1,
> >> -	},
> >> -};
> >> -
> >> -static const struct airoha_pinctrl_func_group sipo_func_group[] = {
> >> -	{
> >> -		.name = "sipo",
> >> -		.regmap[0] = {
> >> -			AIROHA_FUNC_MUX,
> >> -			REG_GPIO_PON_MODE,
> >> -			GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK,
> >> -			GPIO_SIPO_MODE_MASK
> >> -		},
> >> -		.regmap_size = 1,
> >> -	}, {
> >> -		.name = "sipo_rclk",
> >> -		.regmap[0] = {
> >> -			AIROHA_FUNC_MUX,
> >> -			REG_GPIO_PON_MODE,
> >> -			GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK,
> >> -			GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK
> >> -		},
> >> -		.regmap_size = 1,
> >> -	},
> >> -};
> >> -
> >> -static const struct airoha_pinctrl_func_group mdio_func_group[] = {
> >> -	{
> >> -		.name = "mdio",
> >> -		.regmap[0] = {
> >> -			AIROHA_FUNC_MUX,
> >> -			REG_GPIO_2ND_I2C_MODE,
> >> -			GPIO_MDC_IO_MASTER_MODE_MASK,
> >> -			GPIO_MDC_IO_MASTER_MODE_MASK
> >> -		},
> >> -		.regmap[1] = {
> >> -			AIROHA_FUNC_MUX,
> >> -			REG_FORCE_GPIO_EN,
> >> -			FORCE_GPIO_EN(1) | FORCE_GPIO_EN(2),
> >> -			FORCE_GPIO_EN(1) | FORCE_GPIO_EN(2)
> >> -		},
> >> -		.regmap_size = 2,
> >> -	},
> >> -};
> >> -
> >> -static const struct airoha_pinctrl_func_group an7583_mdio_func_group[] = {
> >> -	{
> >> -		.name = "mdio",
> >> -		.regmap[0] = {
> >> -			AIROHA_FUNC_MUX,
> >> -			REG_GPIO_PON_MODE,
> >> -			GPIO_SGMII_MDIO_MODE_MASK,
> >> -			GPIO_SGMII_MDIO_MODE_MASK
> >> -		},
> >> -		.regmap[1] = {
> >> -			AIROHA_FUNC_MUX,
> >> -			REG_GPIO_SPI_CS1_MODE,
> >> -			GPIO_MDC_IO_MASTER_MODE_MASK,
> >> -			GPIO_MDC_IO_MASTER_MODE_MASK
> >> -		},
> >> -		.regmap_size = 2,
> >> -	},
> >> -};
> >> -
> >> -static const struct airoha_pinctrl_func_group uart_func_group[] = {
> >> -	{
> >> -		.name = "uart2",
> >> -		.regmap[0] = {
> >> -			AIROHA_FUNC_MUX,
> >> -			REG_GPIO_PON_MODE,
> >> -			GPIO_UART2_MODE_MASK,
> >> -			GPIO_UART2_MODE_MASK
> >> -		},
> >> -		.regmap_size = 1,
> >> -	}, {
> >> -		.name = "uart2_cts_rts",
> >> -		.regmap[0] = {
> >> -			AIROHA_FUNC_MUX,
> >> -			REG_GPIO_PON_MODE,
> >> -			GPIO_UART2_MODE_MASK | GPIO_UART2_CTS_RTS_MODE_MASK,
> >> -			GPIO_UART2_MODE_MASK | GPIO_UART2_CTS_RTS_MODE_MASK
> >> -		},
> >> -		.regmap_size = 1,
> >> -	}, {
> >> -		.name = "hsuart",
> >> -		.regmap[0] = {
> >> -			AIROHA_FUNC_MUX,
> >> -			REG_GPIO_PON_MODE,
> >> -			GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK,
> >> -			GPIO_HSUART_MODE_MASK
> >> -		},
> >> -		.regmap_size = 1,
> >> -	},
> >> -	{
> >> -		.name = "hsuart_cts_rts",
> >> -		.regmap[0] = {
> >> -			AIROHA_FUNC_MUX,
> >> -			REG_GPIO_PON_MODE,
> >> -			GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK,
> >> -			GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK
> >> -		},
> >> -		.regmap_size = 1,
> >> -	}, {
> >> -		.name = "uart4",
> >> -		.regmap[0] = {
> >> -			AIROHA_FUNC_MUX,
> >> -			REG_GPIO_PON_MODE,
> >> -			GPIO_UART4_MODE_MASK,
> >> -			GPIO_UART4_MODE_MASK
> >> -		},
> >> -		.regmap_size = 1,
> >> -	}, {
> >> -		.name = "uart5",
> >> -		.regmap[0] = {
> >> -			AIROHA_FUNC_MUX,
> >> -			REG_GPIO_PON_MODE,
> >> -			GPIO_UART5_MODE_MASK,
> >> -			GPIO_UART5_MODE_MASK
> >> -		},
> >> -		.regmap_size = 1,
> >> -	},
> >> -};
> >> -
> >> -static const struct airoha_pinctrl_func_group i2c_func_group[] = {
> >> -	{
> >> -		.name = "i2c1",
> >> -		.regmap[0] = {
> >> -			AIROHA_FUNC_MUX,
> >> -			REG_GPIO_2ND_I2C_MODE,
> >> -			GPIO_2ND_I2C_MODE_MASK,
> >> -			GPIO_2ND_I2C_MODE_MASK
> >> -		},
> >> -		.regmap_size = 1,
> >> -	},
> >> -};
> >> -
> >> -static const struct airoha_pinctrl_func_group jtag_func_group[] = {
> >> -	{
> >> -		.name = "jtag_udi",
> >> -		.regmap[0] = {
> >> -			AIROHA_FUNC_MUX,
> >> -			REG_NPU_UART_EN,
> >> -			JTAG_UDI_EN_MASK,
> >> -			JTAG_UDI_EN_MASK
> >> -		},
> >> -		.regmap_size = 1,
> >> -	}, {
> >> -		.name = "jtag_dfd",
> >> -		.regmap[0] = {
> >> -			AIROHA_FUNC_MUX,
> >> -			REG_NPU_UART_EN,
> >> -			JTAG_DFD_EN_MASK,
> >> -			JTAG_DFD_EN_MASK
> >> -		},
> >> -		.regmap_size = 1,
> >> -	},
> >> -};
> >> -
> >> -static const struct airoha_pinctrl_func_group pcm_func_group[] = {
> >> -	{
> >> -		.name = "pcm1",
> >> -		.regmap[0] = {
> >> -			AIROHA_FUNC_MUX,
> >> -			REG_GPIO_SPI_CS1_MODE,
> >> -			GPIO_PCM1_MODE_MASK,
> >> -			GPIO_PCM1_MODE_MASK
> >> -		},
> >> -		.regmap_size = 1,
> >> -	}, {
> >> -		.name = "pcm2",
> >> -		.regmap[0] = {
> >> -			AIROHA_FUNC_MUX,
> >> -			REG_GPIO_SPI_CS1_MODE,
> >> -			GPIO_PCM2_MODE_MASK,
> >> -			GPIO_PCM2_MODE_MASK
> >> -		},
> >> -		.regmap_size = 1,
> >> -	},
> >> -};
> >> -
> >> -static const struct airoha_pinctrl_func_group spi_func_group[] = {
> >> -	{
> >> -		.name = "spi_quad",
> >> -		.regmap[0] = {
> >> -			AIROHA_FUNC_MUX,
> >> -			REG_GPIO_SPI_CS1_MODE,
> >> -			GPIO_SPI_QUAD_MODE_MASK,
> >> -			GPIO_SPI_QUAD_MODE_MASK
> >> -		},
> >> -		.regmap_size = 1,
> >> -	}, {
> >> -		.name = "spi_cs1",
> >> -		.regmap[0] = {
> >> -			AIROHA_FUNC_MUX,
> >> -			REG_GPIO_SPI_CS1_MODE,
> >> -			GPIO_SPI_CS1_MODE_MASK,
> >> -			GPIO_SPI_CS1_MODE_MASK
> >> -		},
> >> -		.regmap_size = 1,
> >> -	}, {
> >> -		.name = "spi_cs2",
> >> -		.regmap[0] = {
> >> -			AIROHA_FUNC_MUX,
> >> -			REG_GPIO_SPI_CS1_MODE,
> >> -			GPIO_SPI_CS2_MODE_MASK,
> >> -			GPIO_SPI_CS2_MODE_MASK
> >> -		},
> >> -		.regmap_size = 1,
> >> -	}, {
> >> -		.name = "spi_cs3",
> >> -		.regmap[0] = {
> >> -			AIROHA_FUNC_MUX,
> >> -			REG_GPIO_SPI_CS1_MODE,
> >> -			GPIO_SPI_CS3_MODE_MASK,
> >> -			GPIO_SPI_CS3_MODE_MASK
> >> -		},
> >> -		.regmap_size = 1,
> >> -	}, {
> >> -		.name = "spi_cs4",
> >> -		.regmap[0] = {
> >> -			AIROHA_FUNC_MUX,
> >> -			REG_GPIO_SPI_CS1_MODE,
> >> -			GPIO_SPI_CS4_MODE_MASK,
> >> -			GPIO_SPI_CS4_MODE_MASK
> >> -		},
> >> -		.regmap_size = 1,
> >> -	},
> >> -};
> >> -
> >> -static const struct airoha_pinctrl_func_group pcm_spi_func_group[] = {
> >> -	{
> >> -		.name = "pcm_spi",
> >> -		.regmap[0] = {
> >> -			AIROHA_FUNC_MUX,
> >> -			REG_GPIO_SPI_CS1_MODE,
> >> -			GPIO_PCM_SPI_MODE_MASK,
> >> -			GPIO_PCM_SPI_MODE_MASK
> >> -		},
> >> -		.regmap_size = 1,
> >> -	}, {
> >> -		.name = "pcm_spi_int",
> >> -		.regmap[0] = {
> >> -			AIROHA_FUNC_MUX,
> >> -			REG_GPIO_SPI_CS1_MODE,
> >> -			GPIO_PCM_INT_MODE_MASK,
> >> -			GPIO_PCM_INT_MODE_MASK
> >> -		},
> >> -		.regmap_size = 1,
> >> -	}, {
> >> -		.name = "pcm_spi_rst",
> >> -		.regmap[0] = {
> >> -			AIROHA_FUNC_MUX,
> >> -			REG_GPIO_SPI_CS1_MODE,
> >> -			GPIO_PCM_RESET_MODE_MASK,
> >> -			GPIO_PCM_RESET_MODE_MASK
> >> -		},
> >> -		.regmap_size = 1,
> >> -	}, {
> >> -		.name = "pcm_spi_cs1",
> >> -		.regmap[0] = {
> >> -			AIROHA_FUNC_MUX,
> >> -			REG_GPIO_SPI_CS1_MODE,
> >> -			GPIO_PCM_SPI_CS1_MODE_MASK,
> >> -			GPIO_PCM_SPI_CS1_MODE_MASK
> >> -		},
> >> -		.regmap_size = 1,
> >> -	}, {
> >> -		.name = "pcm_spi_cs2_p128",
> >> -		.regmap[0] = {
> >> -			AIROHA_FUNC_MUX,
> >> -			REG_GPIO_SPI_CS1_MODE,
> >> -			GPIO_PCM_SPI_CS2_MODE_P128_MASK,
> >> -			GPIO_PCM_SPI_CS2_MODE_P128_MASK
> >> -		},
> >> -		.regmap_size = 1,
> >> -	}, {
> >> -		.name = "pcm_spi_cs2_p156",
> >> -		.regmap[0] = {
> >> -			AIROHA_FUNC_MUX,
> >> -			REG_GPIO_SPI_CS1_MODE,
> >> -			GPIO_PCM_SPI_CS2_MODE_P156_MASK,
> >> -			GPIO_PCM_SPI_CS2_MODE_P156_MASK
> >> -		},
> >> -		.regmap_size = 1,
> >> -	}, {
> >> -		.name = "pcm_spi_cs3",
> >> -		.regmap[0] = {
> >> -			AIROHA_FUNC_MUX,
> >> -			REG_GPIO_SPI_CS1_MODE,
> >> -			GPIO_PCM_SPI_CS3_MODE_MASK,
> >> -			GPIO_PCM_SPI_CS3_MODE_MASK
> >> -		},
> >> -		.regmap_size = 1,
> >> -	}, {
> >> -		.name = "pcm_spi_cs4",
> >> -		.regmap[0] = {
> >> -			AIROHA_FUNC_MUX,
> >> -			REG_GPIO_SPI_CS1_MODE,
> >> -			GPIO_PCM_SPI_CS4_MODE_MASK,
> >> -			GPIO_PCM_SPI_CS4_MODE_MASK
> >> -		},
> >> -		.regmap_size = 1,
> >> -	},
> >> -};
> >> -
> >> -static const struct airoha_pinctrl_func_group an7583_pcm_spi_func_group[] = {
> >> -	{
> >> -		.name = "pcm_spi",
> >> -		.regmap[0] = {
> >> -			AIROHA_FUNC_MUX,
> >> -			REG_GPIO_SPI_CS1_MODE,
> >> -			GPIO_PCM_SPI_MODE_MASK,
> >> -			GPIO_PCM_SPI_MODE_MASK
> >> -		},
> >> -		.regmap_size = 1,
> >> -	}, {
> >> -		.name = "pcm_spi_int",
> >> -		.regmap[0] = {
> >> -			AIROHA_FUNC_MUX,
> >> -			REG_GPIO_SPI_CS1_MODE,
> >> -			GPIO_PCM_INT_MODE_MASK,
> >> -			GPIO_PCM_INT_MODE_MASK
> >> -		},
> >> -		.regmap_size = 1,
> >> -	}, {
> >> -		.name = "pcm_spi_rst",
> >> -		.regmap[0] = {
> >> -			AIROHA_FUNC_MUX,
> >> -			REG_GPIO_SPI_CS1_MODE,
> >> -			GPIO_PCM_RESET_MODE_MASK,
> >> -			GPIO_PCM_RESET_MODE_MASK
> >> -		},
> >> -		.regmap_size = 1,
> >> -	}, {
> >> -		.name = "pcm_spi_cs1",
> >> -		.regmap[0] = {
> >> -			AIROHA_FUNC_MUX,
> >> -			REG_GPIO_SPI_CS1_MODE,
> >> -			GPIO_PCM_SPI_CS1_MODE_MASK,
> >> -			GPIO_PCM_SPI_CS1_MODE_MASK
> >> -		},
> >> -		.regmap_size = 1,
> >> -	}, {
> >> -		.name = "pcm_spi_cs2",
> >> -		.regmap[0] = {
> >> -			AIROHA_FUNC_MUX,
> >> -			REG_GPIO_SPI_CS1_MODE,
> >> -			AN7583_GPIO_PCM_SPI_CS2_MODE_MASK,
> >> -			AN7583_GPIO_PCM_SPI_CS2_MODE_MASK
> >> -		},
> >> -		.regmap_size = 1,
> >> -	}, {
> >> -		.name = "pcm_spi_cs3",
> >> -		.regmap[0] = {
> >> -			AIROHA_FUNC_MUX,
> >> -			REG_GPIO_SPI_CS1_MODE,
> >> -			GPIO_PCM_SPI_CS3_MODE_MASK,
> >> -			GPIO_PCM_SPI_CS3_MODE_MASK
> >> -		},
> >> -		.regmap_size = 1,
> >> -	}, {
> >> -		.name = "pcm_spi_cs4",
> >> -		.regmap[0] = {
> >> -			AIROHA_FUNC_MUX,
> >> -			REG_GPIO_SPI_CS1_MODE,
> >> -			GPIO_PCM_SPI_CS4_MODE_MASK,
> >> -			GPIO_PCM_SPI_CS4_MODE_MASK
> >> -		},
> >> -		.regmap_size = 1,
> >> -	},
> >> -};
> >> -
> >> -static const struct airoha_pinctrl_func_group i2s_func_group[] = {
> >> -	{
> >> -		.name = "i2s",
> >> -		.regmap[0] = {
> >> -			AIROHA_FUNC_MUX,
> >> -			REG_GPIO_2ND_I2C_MODE,
> >> -			GPIO_I2S_MODE_MASK,
> >> -			GPIO_I2S_MODE_MASK
> >> -		},
> >> -		.regmap_size = 1,
> >> -	},
> >> -};
> >> -
> >> -static const struct airoha_pinctrl_func_group emmc_func_group[] = {
> >> -	{
> >> -		.name = "emmc",
> >> -		.regmap[0] = {
> >> -			AIROHA_FUNC_MUX,
> >> -			REG_GPIO_PON_MODE,
> >> -			GPIO_EMMC_MODE_MASK,
> >> -			GPIO_EMMC_MODE_MASK
> >> -		},
> >> -		.regmap_size = 1,
> >> -	},
> >> -};
> >> -
> >> -static const struct airoha_pinctrl_func_group pnand_func_group[] = {
> >> -	{
> >> -		.name = "pnand",
> >> -		.regmap[0] = {
> >> -			AIROHA_FUNC_MUX,
> >> -			REG_GPIO_PON_MODE,
> >> -			GPIO_PARALLEL_NAND_MODE_MASK,
> >> -			GPIO_PARALLEL_NAND_MODE_MASK
> >> -		},
> >> -		.regmap_size = 1,
> >> -	},
> >> -};
> >> -
> >> -static const struct airoha_pinctrl_func_group gpio_func_group[] = {
> >> -	AIROHA_PINCTRL_GPIO_EXT("gpio47", GPIO47_FLASH_MODE_CFG,
> >> -				GPIO_PCIE_RESET0_MASK),
> >> -	AIROHA_PINCTRL_GPIO_EXT("gpio48", GPIO48_FLASH_MODE_CFG,
> >> -				GPIO_PCIE_RESET1_MASK),
> >> -	AIROHA_PINCTRL_GPIO_EXT("gpio49", GPIO49_FLASH_MODE_CFG,
> >> -				GPIO_PCIE_RESET2_MASK),
> >> -};
> >> -
> >> -static const struct airoha_pinctrl_func_group pcie_reset_func_group[] = {
> >> -	{
> >> -		.name = "pcie_reset0",
> >> -		.regmap[0] = {
> >> -			AIROHA_FUNC_MUX,
> >> -			REG_GPIO_PON_MODE,
> >> -			GPIO_PCIE_RESET0_MASK,
> >> -			0
> >> -		},
> >> -		.regmap_size = 1,
> >> -	}, {
> >> -		.name = "pcie_reset1",
> >> -		.regmap[0] = {
> >> -			AIROHA_FUNC_MUX,
> >> -			REG_GPIO_PON_MODE,
> >> -			GPIO_PCIE_RESET1_MASK,
> >> -			0
> >> -		},
> >> -		.regmap_size = 1,
> >> -	}, {
> >> -		.name = "pcie_reset2",
> >> -		.regmap[0] = {
> >> -			AIROHA_FUNC_MUX,
> >> -			REG_GPIO_PON_MODE,
> >> -			GPIO_PCIE_RESET2_MASK,
> >> -			0
> >> -		},
> >> -		.regmap_size = 1,
> >> -	},
> >> -};
> >> -
> >> -static const struct airoha_pinctrl_func_group an7583_gpio_func_group[] = {
> >> -	AIROHA_PINCTRL_GPIO_EXT("gpio39", GPIO39_FLASH_MODE_CFG,
> >> -				AN7583_I2C0_SCL_GPIO_MODE_MASK),
> >> -	AIROHA_PINCTRL_GPIO_EXT("gpio40", GPIO40_FLASH_MODE_CFG,
> >> -				AN7583_I2C0_SDA_GPIO_MODE_MASK),
> >> -	AIROHA_PINCTRL_GPIO_EXT("gpio41", GPIO41_FLASH_MODE_CFG,
> >> -				AN7583_I2C1_SCL_GPIO_MODE_MASK),
> >> -	AIROHA_PINCTRL_GPIO_EXT("gpio42", GPIO42_FLASH_MODE_CFG,
> >> -				AN7583_I2C1_SDA_GPIO_MODE_MASK),
> >> -	AIROHA_PINCTRL_GPIO_EXT("gpio43", GPIO43_FLASH_MODE_CFG,
> >> -				AN7583_SPI_CLK_GPIO_MODE_MASK),
> >> -	AIROHA_PINCTRL_GPIO_EXT("gpio44", GPIO44_FLASH_MODE_CFG,
> >> -				AN7583_SPI_CS_GPIO_MODE_MASK),
> >> -	AIROHA_PINCTRL_GPIO_EXT("gpio45", GPIO45_FLASH_MODE_CFG,
> >> -				AN7583_SPI_MOSI_GPIO_MODE_MASK),
> >> -	AIROHA_PINCTRL_GPIO_EXT("gpio46", GPIO46_FLASH_MODE_CFG,
> >> -				AN7583_SPI_MISO_GPIO_MODE_MASK),
> >> -	AIROHA_PINCTRL_GPIO_EXT("gpio47", GPIO47_FLASH_MODE_CFG,
> >> -				AN7583_UART_TXD_GPIO_MODE_MASK),
> >> -	AIROHA_PINCTRL_GPIO_EXT("gpio48", GPIO48_FLASH_MODE_CFG,
> >> -				AN7583_UART_RXD_GPIO_MODE_MASK),
> >> -	AIROHA_PINCTRL_GPIO_EXT("gpio49", GPIO49_FLASH_MODE_CFG,
> >> -				GPIO_PCIE_RESET0_MASK),
> >> -	AIROHA_PINCTRL_GPIO_EXT("gpio50", GPIO50_FLASH_MODE_CFG,
> >> -				GPIO_PCIE_RESET1_MASK),
> >> -	AIROHA_PINCTRL_GPIO_EXT("gpio51", GPIO51_FLASH_MODE_CFG,
> >> -				AN7583_MDC_0_GPIO_MODE_MASK),
> >> -	AIROHA_PINCTRL_GPIO("gpio52", AN7583_MDIO_0_GPIO_MODE_MASK),
> >> -};
> >> -
> >> -static const struct airoha_pinctrl_func_group an7583_pcie_reset_func_group[] = {
> >> -	{
> >> -		.name = "pcie_reset0",
> >> -		.regmap[0] = {
> >> -			AIROHA_FUNC_MUX,
> >> -			REG_GPIO_PON_MODE,
> >> -			GPIO_PCIE_RESET0_MASK,
> >> -			0
> >> -		},
> >> -		.regmap_size = 1,
> >> -	}, {
> >> -		.name = "pcie_reset1",
> >> -		.regmap[0] = {
> >> -			AIROHA_FUNC_MUX,
> >> -			REG_GPIO_PON_MODE,
> >> -			GPIO_PCIE_RESET1_MASK,
> >> -			0
> >> -		},
> >> -		.regmap_size = 1,
> >> -	},
> >> -};
> >> -
> >> -static const struct airoha_pinctrl_func_group pwm_func_group[] = {
> >> -	AIROHA_PINCTRL_PWM("gpio0", GPIO0_FLASH_MODE_CFG),
> >> -	AIROHA_PINCTRL_PWM("gpio1", GPIO1_FLASH_MODE_CFG),
> >> -	AIROHA_PINCTRL_PWM("gpio2", GPIO2_FLASH_MODE_CFG),
> >> -	AIROHA_PINCTRL_PWM("gpio3", GPIO3_FLASH_MODE_CFG),
> >> -	AIROHA_PINCTRL_PWM("gpio4", GPIO4_FLASH_MODE_CFG),
> >> -	AIROHA_PINCTRL_PWM("gpio5", GPIO5_FLASH_MODE_CFG),
> >> -	AIROHA_PINCTRL_PWM("gpio6", GPIO6_FLASH_MODE_CFG),
> >> -	AIROHA_PINCTRL_PWM("gpio7", GPIO7_FLASH_MODE_CFG),
> >> -	AIROHA_PINCTRL_PWM("gpio8", GPIO8_FLASH_MODE_CFG),
> >> -	AIROHA_PINCTRL_PWM("gpio9", GPIO9_FLASH_MODE_CFG),
> >> -	AIROHA_PINCTRL_PWM("gpio10", GPIO10_FLASH_MODE_CFG),
> >> -	AIROHA_PINCTRL_PWM("gpio11", GPIO11_FLASH_MODE_CFG),
> >> -	AIROHA_PINCTRL_PWM("gpio12", GPIO12_FLASH_MODE_CFG),
> >> -	AIROHA_PINCTRL_PWM("gpio13", GPIO13_FLASH_MODE_CFG),
> >> -	AIROHA_PINCTRL_PWM("gpio14", GPIO14_FLASH_MODE_CFG),
> >> -	AIROHA_PINCTRL_PWM("gpio15", GPIO15_FLASH_MODE_CFG),
> >> -	AIROHA_PINCTRL_PWM_EXT("gpio16", GPIO16_FLASH_MODE_CFG),
> >> -	AIROHA_PINCTRL_PWM_EXT("gpio17", GPIO17_FLASH_MODE_CFG),
> >> -	AIROHA_PINCTRL_PWM_EXT("gpio18", GPIO18_FLASH_MODE_CFG),
> >> -	AIROHA_PINCTRL_PWM_EXT("gpio19", GPIO19_FLASH_MODE_CFG),
> >> -	AIROHA_PINCTRL_PWM_EXT("gpio20", GPIO20_FLASH_MODE_CFG),
> >> -	AIROHA_PINCTRL_PWM_EXT("gpio21", GPIO21_FLASH_MODE_CFG),
> >> -	AIROHA_PINCTRL_PWM_EXT("gpio22", GPIO22_FLASH_MODE_CFG),
> >> -	AIROHA_PINCTRL_PWM_EXT("gpio23", GPIO23_FLASH_MODE_CFG),
> >> -	AIROHA_PINCTRL_PWM_EXT("gpio24", GPIO24_FLASH_MODE_CFG),
> >> -	AIROHA_PINCTRL_PWM_EXT("gpio25", GPIO25_FLASH_MODE_CFG),
> >> -	AIROHA_PINCTRL_PWM_EXT("gpio26", GPIO26_FLASH_MODE_CFG),
> >> -	AIROHA_PINCTRL_PWM_EXT("gpio27", GPIO27_FLASH_MODE_CFG),
> >> -	AIROHA_PINCTRL_PWM_EXT("gpio28", GPIO28_FLASH_MODE_CFG),
> >> -	AIROHA_PINCTRL_PWM_EXT("gpio29", GPIO29_FLASH_MODE_CFG),
> >> -	AIROHA_PINCTRL_PWM_EXT("gpio30", GPIO30_FLASH_MODE_CFG),
> >> -	AIROHA_PINCTRL_PWM_EXT("gpio31", GPIO31_FLASH_MODE_CFG),
> >> -	AIROHA_PINCTRL_PWM_EXT("gpio36", GPIO36_FLASH_MODE_CFG),
> >> -	AIROHA_PINCTRL_PWM_EXT("gpio37", GPIO37_FLASH_MODE_CFG),
> >> -	AIROHA_PINCTRL_PWM_EXT("gpio38", GPIO38_FLASH_MODE_CFG),
> >> -	AIROHA_PINCTRL_PWM_EXT("gpio39", GPIO39_FLASH_MODE_CFG),
> >> -	AIROHA_PINCTRL_PWM_EXT("gpio40", GPIO40_FLASH_MODE_CFG),
> >> -	AIROHA_PINCTRL_PWM_EXT("gpio41", GPIO41_FLASH_MODE_CFG),
> >> -	AIROHA_PINCTRL_PWM_EXT("gpio42", GPIO42_FLASH_MODE_CFG),
> >> -	AIROHA_PINCTRL_PWM_EXT("gpio43", GPIO43_FLASH_MODE_CFG),
> >> -	AIROHA_PINCTRL_PWM_EXT("gpio44", GPIO44_FLASH_MODE_CFG),
> >> -	AIROHA_PINCTRL_PWM_EXT("gpio45", GPIO45_FLASH_MODE_CFG),
> >> -	AIROHA_PINCTRL_PWM_EXT("gpio46", GPIO46_FLASH_MODE_CFG),
> >> -	AIROHA_PINCTRL_PWM_EXT_SEC("gpio47", GPIO47_FLASH_MODE_CFG,
> >> -				   GPIO_PCIE_RESET0_MASK),
> >> -	AIROHA_PINCTRL_PWM_EXT_SEC("gpio48", GPIO48_FLASH_MODE_CFG,
> >> -				   GPIO_PCIE_RESET1_MASK),
> >> -	AIROHA_PINCTRL_PWM_EXT_SEC("gpio49", GPIO49_FLASH_MODE_CFG,
> >> -				   GPIO_PCIE_RESET2_MASK),
> >> -};
> >> -
> >> -static const struct airoha_pinctrl_func_group an7583_pwm_func_group[] = {
> >> -	AIROHA_PINCTRL_PWM("gpio0", GPIO0_FLASH_MODE_CFG),
> >> -	AIROHA_PINCTRL_PWM("gpio1", GPIO1_FLASH_MODE_CFG),
> >> -	AIROHA_PINCTRL_PWM("gpio2", GPIO2_FLASH_MODE_CFG),
> >> -	AIROHA_PINCTRL_PWM("gpio3", GPIO3_FLASH_MODE_CFG),
> >> -	AIROHA_PINCTRL_PWM("gpio4", GPIO4_FLASH_MODE_CFG),
> >> -	AIROHA_PINCTRL_PWM("gpio5", GPIO5_FLASH_MODE_CFG),
> >> -	AIROHA_PINCTRL_PWM("gpio6", GPIO6_FLASH_MODE_CFG),
> >> -	AIROHA_PINCTRL_PWM("gpio7", GPIO7_FLASH_MODE_CFG),
> >> -	AIROHA_PINCTRL_PWM("gpio8", GPIO8_FLASH_MODE_CFG),
> >> -	AIROHA_PINCTRL_PWM("gpio9", GPIO9_FLASH_MODE_CFG),
> >> -	AIROHA_PINCTRL_PWM("gpio10", GPIO10_FLASH_MODE_CFG),
> >> -	AIROHA_PINCTRL_PWM("gpio11", GPIO11_FLASH_MODE_CFG),
> >> -	AIROHA_PINCTRL_PWM("gpio12", GPIO12_FLASH_MODE_CFG),
> >> -	AIROHA_PINCTRL_PWM("gpio13", GPIO13_FLASH_MODE_CFG),
> >> -	AIROHA_PINCTRL_PWM("gpio14", GPIO14_FLASH_MODE_CFG),
> >> -	AIROHA_PINCTRL_PWM("gpio15", GPIO15_FLASH_MODE_CFG),
> >> -	AIROHA_PINCTRL_PWM_EXT("gpio16", GPIO16_FLASH_MODE_CFG),
> >> -	AIROHA_PINCTRL_PWM_EXT("gpio17", GPIO17_FLASH_MODE_CFG),
> >> -	AIROHA_PINCTRL_PWM_EXT("gpio18", GPIO18_FLASH_MODE_CFG),
> >> -	AIROHA_PINCTRL_PWM_EXT("gpio19", GPIO19_FLASH_MODE_CFG),
> >> -	AIROHA_PINCTRL_PWM_EXT("gpio20", GPIO20_FLASH_MODE_CFG),
> >> -	AIROHA_PINCTRL_PWM_EXT("gpio21", GPIO21_FLASH_MODE_CFG),
> >> -	AIROHA_PINCTRL_PWM_EXT("gpio22", GPIO22_FLASH_MODE_CFG),
> >> -	AIROHA_PINCTRL_PWM_EXT("gpio23", GPIO23_FLASH_MODE_CFG),
> >> -	AIROHA_PINCTRL_PWM_EXT("gpio24", GPIO24_FLASH_MODE_CFG),
> >> -	AIROHA_PINCTRL_PWM_EXT("gpio25", GPIO25_FLASH_MODE_CFG),
> >> -	AIROHA_PINCTRL_PWM_EXT("gpio26", GPIO26_FLASH_MODE_CFG),
> >> -	AIROHA_PINCTRL_PWM_EXT("gpio27", GPIO27_FLASH_MODE_CFG),
> >> -	AIROHA_PINCTRL_PWM_EXT("gpio28", GPIO28_FLASH_MODE_CFG),
> >> -	AIROHA_PINCTRL_PWM_EXT("gpio29", GPIO29_FLASH_MODE_CFG),
> >> -	AIROHA_PINCTRL_PWM_EXT("gpio30", GPIO30_FLASH_MODE_CFG),
> >> -	AIROHA_PINCTRL_PWM_EXT("gpio31", GPIO31_FLASH_MODE_CFG),
> >> -	AIROHA_PINCTRL_PWM_EXT("gpio36", GPIO36_FLASH_MODE_CFG),
> >> -	AIROHA_PINCTRL_PWM_EXT("gpio37", GPIO37_FLASH_MODE_CFG),
> >> -	AIROHA_PINCTRL_PWM_EXT("gpio38", GPIO38_FLASH_MODE_CFG),
> >> -	AIROHA_PINCTRL_PWM_EXT_SEC("gpio39", GPIO39_FLASH_MODE_CFG,
> >> -				   AN7583_I2C0_SCL_GPIO_MODE_MASK),
> >> -	AIROHA_PINCTRL_PWM_EXT_SEC("gpio40", GPIO40_FLASH_MODE_CFG,
> >> -				   AN7583_I2C0_SDA_GPIO_MODE_MASK),
> >> -	AIROHA_PINCTRL_PWM_EXT_SEC("gpio41", GPIO41_FLASH_MODE_CFG,
> >> -				   AN7583_I2C1_SCL_GPIO_MODE_MASK),
> >> -	AIROHA_PINCTRL_PWM_EXT_SEC("gpio42", GPIO42_FLASH_MODE_CFG,
> >> -				   AN7583_I2C1_SDA_GPIO_MODE_MASK),
> >> -	AIROHA_PINCTRL_PWM_EXT_SEC("gpio43", GPIO43_FLASH_MODE_CFG,
> >> -				   AN7583_SPI_CLK_GPIO_MODE_MASK),
> >> -	AIROHA_PINCTRL_PWM_EXT_SEC("gpio44", GPIO44_FLASH_MODE_CFG,
> >> -				   AN7583_SPI_CS_GPIO_MODE_MASK),
> >> -	AIROHA_PINCTRL_PWM_EXT_SEC("gpio45", GPIO45_FLASH_MODE_CFG,
> >> -				   AN7583_SPI_MOSI_GPIO_MODE_MASK),
> >> -	AIROHA_PINCTRL_PWM_EXT_SEC("gpio46", GPIO46_FLASH_MODE_CFG,
> >> -				   AN7583_SPI_MISO_GPIO_MODE_MASK),
> >> -	AIROHA_PINCTRL_PWM_EXT_SEC("gpio47", GPIO47_FLASH_MODE_CFG,
> >> -				   AN7583_UART_TXD_GPIO_MODE_MASK),
> >> -	AIROHA_PINCTRL_PWM_EXT_SEC("gpio48", GPIO48_FLASH_MODE_CFG,
> >> -				   AN7583_UART_RXD_GPIO_MODE_MASK),
> >> -	AIROHA_PINCTRL_PWM_EXT_SEC("gpio49", GPIO49_FLASH_MODE_CFG,
> >> -				   GPIO_PCIE_RESET0_MASK),
> >> -	AIROHA_PINCTRL_PWM_EXT_SEC("gpio50", GPIO50_FLASH_MODE_CFG,
> >> -				   GPIO_PCIE_RESET1_MASK),
> >> -	AIROHA_PINCTRL_PWM_EXT_SEC("gpio51", GPIO51_FLASH_MODE_CFG,
> >> -				   AN7583_MDC_0_GPIO_MODE_MASK),
> >> -};
> >> -
> >> -static const struct airoha_pinctrl_func_group phy1_led0_func_group[] = {
> >> -	AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK,
> >> -				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),
> >> -	AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK,
> >> -				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)),
> >> -	AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK,
> >> -				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)),
> >> -	AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK,
> >> -				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),
> >> -};
> >> -
> >> -static const struct airoha_pinctrl_func_group phy2_led0_func_group[] = {
> >> -	AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK,
> >> -				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),
> >> -	AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK,
> >> -				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)),
> >> -	AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK,
> >> -				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)),
> >> -	AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK,
> >> -				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),
> >> -};
> >> -
> >> -static const struct airoha_pinctrl_func_group phy3_led0_func_group[] = {
> >> -	AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK,
> >> -				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
> >> -	AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK,
> >> -				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),
> >> -	AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK,
> >> -				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),
> >> -	AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK,
> >> -				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
> >> -};
> >> -
> >> -static const struct airoha_pinctrl_func_group phy4_led0_func_group[] = {
> >> -	AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK,
> >> -				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)),
> >> -	AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK,
> >> -				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)),
> >> -	AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK,
> >> -				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)),
> >> -	AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK,
> >> -				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)),
> >> -};
> >> -
> >> -static const struct airoha_pinctrl_func_group phy1_led1_func_group[] = {
> >> -	AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK,
> >> -				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),
> >> -	AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK,
> >> -				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)),
> >> -	AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK,
> >> -				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)),
> >> -	AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK,
> >> -				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),
> >> -};
> >> -
> >> -static const struct airoha_pinctrl_func_group phy2_led1_func_group[] = {
> >> -	AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK,
> >> -				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),
> >> -	AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK,
> >> -				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)),
> >> -	AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK,
> >> -				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)),
> >> -	AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK,
> >> -				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),
> >> -};
> >> -
> >> -static const struct airoha_pinctrl_func_group phy3_led1_func_group[] = {
> >> -	AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK,
> >> -				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
> >> -	AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK,
> >> -				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),
> >> -	AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK,
> >> -				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),
> >> -	AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK,
> >> -				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
> >> -};
> >> -
> >> -static const struct airoha_pinctrl_func_group phy4_led1_func_group[] = {
> >> -	AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK,
> >> -				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)),
> >> -	AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK,
> >> -				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)),
> >> -	AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK,
> >> -				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)),
> >> -	AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK,
> >> -				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)),
> >> -};
> >> -
> >> -static const struct airoha_pinctrl_func_group an7583_phy1_led0_func_group[] = {
> >> -	AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK,
> >> -				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),
> >> -	AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK,
> >> -				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)),
> >> -	AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK,
> >> -				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)),
> >> -	AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK,
> >> -				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),
> >> -};
> >> -
> >> -static const struct airoha_pinctrl_func_group an7583_phy2_led0_func_group[] = {
> >> -	AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK,
> >> -				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),
> >> -	AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK,
> >> -				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)),
> >> -	AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK,
> >> -				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)),
> >> -	AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK,
> >> -				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),
> >> -};
> >> -
> >> -static const struct airoha_pinctrl_func_group an7583_phy3_led0_func_group[] = {
> >> -	AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK,
> >> -				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
> >> -	AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK,
> >> -				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),
> >> -	AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK,
> >> -				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),
> >> -	AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK,
> >> -				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
> >> -};
> >> -
> >> -static const struct airoha_pinctrl_func_group an7583_phy4_led0_func_group[] = {
> >> -	AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK,
> >> -				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)),
> >> -	AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK,
> >> -				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)),
> >> -	AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK,
> >> -				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)),
> >> -	AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK,
> >> -				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)),
> >> -};
> >> -
> >> -static const struct airoha_pinctrl_func_group an7583_phy1_led1_func_group[] = {
> >> -	AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK,
> >> -				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),
> >> -	AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK,
> >> -				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)),
> >> -	AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK,
> >> -				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)),
> >> -	AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK,
> >> -				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),
> >> -};
> >> -
> >> -static const struct airoha_pinctrl_func_group an7583_phy2_led1_func_group[] = {
> >> -	AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK,
> >> -				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),
> >> -	AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK,
> >> -				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)),
> >> -	AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK,
> >> -				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)),
> >> -	AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK,
> >> -				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),
> >> -};
> >> -
> >> -static const struct airoha_pinctrl_func_group an7583_phy3_led1_func_group[] = {
> >> -	AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK,
> >> -				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
> >> -	AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK,
> >> -				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),
> >> -	AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK,
> >> -				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),
> >> -	AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK,
> >> -				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
> >> -};
> >> -
> >> -static const struct airoha_pinctrl_func_group an7583_phy4_led1_func_group[] = {
> >> -	AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK,
> >> -				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)),
> >> -	AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK,
> >> -				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)),
> >> -	AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK,
> >> -				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)),
> >> -	AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK,
> >> -				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)),
> >> -};
> >> -
> >> -static const struct airoha_pinctrl_func en7581_pinctrl_funcs[] = {
> >> -	PINCTRL_FUNC_DESC("pon", pon),
> >> -	PINCTRL_FUNC_DESC("tod_1pps", tod_1pps),
> >> -	PINCTRL_FUNC_DESC("sipo", sipo),
> >> -	PINCTRL_FUNC_DESC("mdio", mdio),
> >> -	PINCTRL_FUNC_DESC("uart", uart),
> >> -	PINCTRL_FUNC_DESC("i2c", i2c),
> >> -	PINCTRL_FUNC_DESC("jtag", jtag),
> >> -	PINCTRL_FUNC_DESC("pcm", pcm),
> >> -	PINCTRL_FUNC_DESC("spi", spi),
> >> -	PINCTRL_FUNC_DESC("pcm_spi", pcm_spi),
> >> -	PINCTRL_FUNC_DESC("i2s", i2s),
> >> -	PINCTRL_FUNC_DESC("emmc", emmc),
> >> -	PINCTRL_FUNC_DESC("pnand", pnand),
> >> -	PINCTRL_FUNC_DESC("gpio", gpio),
> >> -	PINCTRL_FUNC_DESC("pcie_reset", pcie_reset),
> >> -	PINCTRL_FUNC_DESC("pwm", pwm),
> >> -	PINCTRL_FUNC_DESC("phy1_led0", phy1_led0),
> >> -	PINCTRL_FUNC_DESC("phy2_led0", phy2_led0),
> >> -	PINCTRL_FUNC_DESC("phy3_led0", phy3_led0),
> >> -	PINCTRL_FUNC_DESC("phy4_led0", phy4_led0),
> >> -	PINCTRL_FUNC_DESC("phy1_led1", phy1_led1),
> >> -	PINCTRL_FUNC_DESC("phy2_led1", phy2_led1),
> >> -	PINCTRL_FUNC_DESC("phy3_led1", phy3_led1),
> >> -	PINCTRL_FUNC_DESC("phy4_led1", phy4_led1),
> >> -};
> >> -
> >> -static const struct airoha_pinctrl_func an7583_pinctrl_funcs[] = {
> >> -	PINCTRL_FUNC_DESC("pon", pon),
> >> -	PINCTRL_FUNC_DESC("tod_1pps", tod_1pps),
> >> -	PINCTRL_FUNC_DESC("sipo", sipo),
> >> -	PINCTRL_FUNC_DESC("mdio", an7583_mdio),
> >> -	PINCTRL_FUNC_DESC("uart", uart),
> >> -	PINCTRL_FUNC_DESC("jtag", jtag),
> >> -	PINCTRL_FUNC_DESC("pcm", pcm),
> >> -	PINCTRL_FUNC_DESC("spi", spi),
> >> -	PINCTRL_FUNC_DESC("pcm_spi", an7583_pcm_spi),
> >> -	PINCTRL_FUNC_DESC("emmc", emmc),
> >> -	PINCTRL_FUNC_DESC("pnand", pnand),
> >> -	PINCTRL_FUNC_DESC("gpio", an7583_gpio),
> >> -	PINCTRL_FUNC_DESC("pcie_reset", an7583_pcie_reset),
> >> -	PINCTRL_FUNC_DESC("pwm", an7583_pwm),
> >> -	PINCTRL_FUNC_DESC("phy1_led0", an7583_phy1_led0),
> >> -	PINCTRL_FUNC_DESC("phy2_led0", an7583_phy2_led0),
> >> -	PINCTRL_FUNC_DESC("phy3_led0", an7583_phy3_led0),
> >> -	PINCTRL_FUNC_DESC("phy4_led0", an7583_phy4_led0),
> >> -	PINCTRL_FUNC_DESC("phy1_led1", an7583_phy1_led1),
> >> -	PINCTRL_FUNC_DESC("phy2_led1", an7583_phy2_led1),
> >> -	PINCTRL_FUNC_DESC("phy3_led1", an7583_phy3_led1),
> >> -	PINCTRL_FUNC_DESC("phy4_led1", an7583_phy4_led1),
> >> -};
> >> -
> >> -static const struct airoha_pinctrl_conf en7581_pinctrl_pullup_conf[] = {
> >> -	PINCTRL_CONF_DESC(0, REG_I2C_SDA_PU, UART1_TXD_PU_MASK),
> >> -	PINCTRL_CONF_DESC(1, REG_I2C_SDA_PU, UART1_RXD_PU_MASK),
> >> -	PINCTRL_CONF_DESC(2, REG_I2C_SDA_PU, I2C_SDA_PU_MASK),
> >> -	PINCTRL_CONF_DESC(3, REG_I2C_SDA_PU, I2C_SCL_PU_MASK),
> >> -	PINCTRL_CONF_DESC(4, REG_I2C_SDA_PU, SPI_CS0_PU_MASK),
> >> -	PINCTRL_CONF_DESC(5, REG_I2C_SDA_PU, SPI_CLK_PU_MASK),
> >> -	PINCTRL_CONF_DESC(6, REG_I2C_SDA_PU, SPI_MOSI_PU_MASK),
> >> -	PINCTRL_CONF_DESC(7, REG_I2C_SDA_PU, SPI_MISO_PU_MASK),
> >> -	PINCTRL_CONF_DESC(13, REG_GPIO_L_PU, BIT(0)),
> >> -	PINCTRL_CONF_DESC(14, REG_GPIO_L_PU, BIT(1)),
> >> -	PINCTRL_CONF_DESC(15, REG_GPIO_L_PU, BIT(2)),
> >> -	PINCTRL_CONF_DESC(16, REG_GPIO_L_PU, BIT(3)),
> >> -	PINCTRL_CONF_DESC(17, REG_GPIO_L_PU, BIT(4)),
> >> -	PINCTRL_CONF_DESC(18, REG_GPIO_L_PU, BIT(5)),
> >> -	PINCTRL_CONF_DESC(19, REG_GPIO_L_PU, BIT(6)),
> >> -	PINCTRL_CONF_DESC(20, REG_GPIO_L_PU, BIT(7)),
> >> -	PINCTRL_CONF_DESC(21, REG_GPIO_L_PU, BIT(8)),
> >> -	PINCTRL_CONF_DESC(22, REG_GPIO_L_PU, BIT(9)),
> >> -	PINCTRL_CONF_DESC(23, REG_GPIO_L_PU, BIT(10)),
> >> -	PINCTRL_CONF_DESC(24, REG_GPIO_L_PU, BIT(11)),
> >> -	PINCTRL_CONF_DESC(25, REG_GPIO_L_PU, BIT(12)),
> >> -	PINCTRL_CONF_DESC(26, REG_GPIO_L_PU, BIT(13)),
> >> -	PINCTRL_CONF_DESC(27, REG_GPIO_L_PU, BIT(14)),
> >> -	PINCTRL_CONF_DESC(28, REG_GPIO_L_PU, BIT(15)),
> >> -	PINCTRL_CONF_DESC(29, REG_GPIO_L_PU, BIT(16)),
> >> -	PINCTRL_CONF_DESC(30, REG_GPIO_L_PU, BIT(17)),
> >> -	PINCTRL_CONF_DESC(31, REG_GPIO_L_PU, BIT(18)),
> >> -	PINCTRL_CONF_DESC(32, REG_GPIO_L_PU, BIT(19)),
> >> -	PINCTRL_CONF_DESC(33, REG_GPIO_L_PU, BIT(20)),
> >> -	PINCTRL_CONF_DESC(34, REG_GPIO_L_PU, BIT(21)),
> >> -	PINCTRL_CONF_DESC(35, REG_GPIO_L_PU, BIT(22)),
> >> -	PINCTRL_CONF_DESC(36, REG_GPIO_L_PU, BIT(23)),
> >> -	PINCTRL_CONF_DESC(37, REG_GPIO_L_PU, BIT(24)),
> >> -	PINCTRL_CONF_DESC(38, REG_GPIO_L_PU, BIT(25)),
> >> -	PINCTRL_CONF_DESC(39, REG_GPIO_L_PU, BIT(26)),
> >> -	PINCTRL_CONF_DESC(40, REG_GPIO_L_PU, BIT(27)),
> >> -	PINCTRL_CONF_DESC(41, REG_GPIO_L_PU, BIT(28)),
> >> -	PINCTRL_CONF_DESC(42, REG_GPIO_L_PU, BIT(29)),
> >> -	PINCTRL_CONF_DESC(43, REG_GPIO_L_PU, BIT(30)),
> >> -	PINCTRL_CONF_DESC(44, REG_GPIO_L_PU, BIT(31)),
> >> -	PINCTRL_CONF_DESC(45, REG_GPIO_H_PU, BIT(0)),
> >> -	PINCTRL_CONF_DESC(46, REG_GPIO_H_PU, BIT(1)),
> >> -	PINCTRL_CONF_DESC(47, REG_GPIO_H_PU, BIT(2)),
> >> -	PINCTRL_CONF_DESC(48, REG_GPIO_H_PU, BIT(3)),
> >> -	PINCTRL_CONF_DESC(49, REG_GPIO_H_PU, BIT(4)),
> >> -	PINCTRL_CONF_DESC(50, REG_GPIO_H_PU, BIT(5)),
> >> -	PINCTRL_CONF_DESC(51, REG_GPIO_H_PU, BIT(6)),
> >> -	PINCTRL_CONF_DESC(52, REG_GPIO_H_PU, BIT(7)),
> >> -	PINCTRL_CONF_DESC(53, REG_GPIO_H_PU, BIT(8)),
> >> -	PINCTRL_CONF_DESC(54, REG_GPIO_H_PU, BIT(9)),
> >> -	PINCTRL_CONF_DESC(55, REG_GPIO_H_PU, BIT(10)),
> >> -	PINCTRL_CONF_DESC(56, REG_GPIO_H_PU, BIT(11)),
> >> -	PINCTRL_CONF_DESC(57, REG_GPIO_H_PU, BIT(12)),
> >> -	PINCTRL_CONF_DESC(58, REG_GPIO_H_PU, BIT(13)),
> >> -	PINCTRL_CONF_DESC(59, REG_GPIO_H_PU, BIT(14)),
> >> -	PINCTRL_CONF_DESC(60, REG_I2C_SDA_PU, PCIE0_RESET_PU_MASK),
> >> -	PINCTRL_CONF_DESC(61, REG_I2C_SDA_PU, PCIE1_RESET_PU_MASK),
> >> -	PINCTRL_CONF_DESC(62, REG_I2C_SDA_PU, PCIE2_RESET_PU_MASK),
> >> -};
> >> -
> >> -static const struct airoha_pinctrl_conf an7583_pinctrl_pullup_conf[] = {
> >> -	PINCTRL_CONF_DESC(2, REG_GPIO_L_PU, BIT(0)),
> >> -	PINCTRL_CONF_DESC(3, REG_GPIO_L_PU, BIT(1)),
> >> -	PINCTRL_CONF_DESC(4, REG_GPIO_L_PU, BIT(2)),
> >> -	PINCTRL_CONF_DESC(5, REG_GPIO_L_PU, BIT(3)),
> >> -	PINCTRL_CONF_DESC(6, REG_GPIO_L_PU, BIT(4)),
> >> -	PINCTRL_CONF_DESC(7, REG_GPIO_L_PU, BIT(5)),
> >> -	PINCTRL_CONF_DESC(8, REG_GPIO_L_PU, BIT(6)),
> >> -	PINCTRL_CONF_DESC(9, REG_GPIO_L_PU, BIT(7)),
> >> -	PINCTRL_CONF_DESC(10, REG_GPIO_L_PU, BIT(8)),
> >> -	PINCTRL_CONF_DESC(11, REG_GPIO_L_PU, BIT(9)),
> >> -	PINCTRL_CONF_DESC(12, REG_GPIO_L_PU, BIT(10)),
> >> -	PINCTRL_CONF_DESC(13, REG_GPIO_L_PU, BIT(11)),
> >> -	PINCTRL_CONF_DESC(14, REG_GPIO_L_PU, BIT(12)),
> >> -	PINCTRL_CONF_DESC(15, REG_GPIO_L_PU, BIT(13)),
> >> -	PINCTRL_CONF_DESC(16, REG_GPIO_L_PU, BIT(14)),
> >> -	PINCTRL_CONF_DESC(17, REG_GPIO_L_PU, BIT(15)),
> >> -	PINCTRL_CONF_DESC(18, REG_GPIO_L_PU, BIT(16)),
> >> -	PINCTRL_CONF_DESC(19, REG_GPIO_L_PU, BIT(17)),
> >> -	PINCTRL_CONF_DESC(20, REG_GPIO_L_PU, BIT(18)),
> >> -	PINCTRL_CONF_DESC(21, REG_GPIO_L_PU, BIT(19)),
> >> -	PINCTRL_CONF_DESC(22, REG_GPIO_L_PU, BIT(20)),
> >> -	PINCTRL_CONF_DESC(23, REG_GPIO_L_PU, BIT(21)),
> >> -	PINCTRL_CONF_DESC(24, REG_GPIO_L_PU, BIT(22)),
> >> -	PINCTRL_CONF_DESC(25, REG_GPIO_L_PU, BIT(23)),
> >> -	PINCTRL_CONF_DESC(26, REG_GPIO_L_PU, BIT(24)),
> >> -	PINCTRL_CONF_DESC(27, REG_GPIO_L_PU, BIT(25)),
> >> -	PINCTRL_CONF_DESC(28, REG_GPIO_L_PU, BIT(26)),
> >> -	PINCTRL_CONF_DESC(29, REG_GPIO_L_PU, BIT(27)),
> >> -	PINCTRL_CONF_DESC(30, REG_GPIO_L_PU, BIT(28)),
> >> -	PINCTRL_CONF_DESC(31, REG_GPIO_L_PU, BIT(29)),
> >> -	PINCTRL_CONF_DESC(32, REG_GPIO_L_PU, BIT(30)),
> >> -	PINCTRL_CONF_DESC(33, REG_GPIO_L_PU, BIT(31)),
> >> -	PINCTRL_CONF_DESC(34, REG_GPIO_H_PU, BIT(0)),
> >> -	PINCTRL_CONF_DESC(35, REG_GPIO_H_PU, BIT(1)),
> >> -	PINCTRL_CONF_DESC(36, REG_GPIO_H_PU, BIT(2)),
> >> -	PINCTRL_CONF_DESC(37, REG_GPIO_H_PU, BIT(3)),
> >> -	PINCTRL_CONF_DESC(38, REG_GPIO_H_PU, BIT(4)),
> >> -	PINCTRL_CONF_DESC(39, REG_GPIO_H_PU, BIT(5)),
> >> -	PINCTRL_CONF_DESC(40, REG_GPIO_H_PU, BIT(6)),
> >> -	PINCTRL_CONF_DESC(41, REG_I2C_SDA_PU, I2C_SCL_PU_MASK),
> >> -	PINCTRL_CONF_DESC(42, REG_I2C_SDA_PU, I2C_SDA_PU_MASK),
> >> -	PINCTRL_CONF_DESC(43, REG_I2C_SDA_PU, AN7583_I2C1_SCL_PU_MASK),
> >> -	PINCTRL_CONF_DESC(44, REG_I2C_SDA_PU, AN7583_I2C1_SDA_PU_MASK),
> >> -	PINCTRL_CONF_DESC(45, REG_I2C_SDA_PU, SPI_CLK_PU_MASK),
> >> -	PINCTRL_CONF_DESC(46, REG_I2C_SDA_PU, SPI_CS0_PU_MASK),
> >> -	PINCTRL_CONF_DESC(47, REG_I2C_SDA_PU, SPI_MOSI_PU_MASK),
> >> -	PINCTRL_CONF_DESC(48, REG_I2C_SDA_PU, SPI_MISO_PU_MASK),
> >> -	PINCTRL_CONF_DESC(49, REG_I2C_SDA_PU, UART1_TXD_PU_MASK),
> >> -	PINCTRL_CONF_DESC(50, REG_I2C_SDA_PU, UART1_RXD_PU_MASK),
> >> -	PINCTRL_CONF_DESC(51, REG_I2C_SDA_PU, PCIE0_RESET_PU_MASK),
> >> -	PINCTRL_CONF_DESC(52, REG_I2C_SDA_PU, PCIE1_RESET_PU_MASK),
> >> -	PINCTRL_CONF_DESC(53, REG_I2C_SDA_PU, AN7583_MDC_0_PU_MASK),
> >> -	PINCTRL_CONF_DESC(54, REG_I2C_SDA_PU, AN7583_MDIO_0_PU_MASK),
> >> -};
> >> -
> >> -static const struct airoha_pinctrl_conf en7581_pinctrl_pulldown_conf[] = {
> >> -	PINCTRL_CONF_DESC(0, REG_I2C_SDA_PD, UART1_TXD_PD_MASK),
> >> -	PINCTRL_CONF_DESC(1, REG_I2C_SDA_PD, UART1_RXD_PD_MASK),
> >> -	PINCTRL_CONF_DESC(2, REG_I2C_SDA_PD, I2C_SDA_PD_MASK),
> >> -	PINCTRL_CONF_DESC(3, REG_I2C_SDA_PD, I2C_SCL_PD_MASK),
> >> -	PINCTRL_CONF_DESC(4, REG_I2C_SDA_PD, SPI_CS0_PD_MASK),
> >> -	PINCTRL_CONF_DESC(5, REG_I2C_SDA_PD, SPI_CLK_PD_MASK),
> >> -	PINCTRL_CONF_DESC(6, REG_I2C_SDA_PD, SPI_MOSI_PD_MASK),
> >> -	PINCTRL_CONF_DESC(7, REG_I2C_SDA_PD, SPI_MISO_PD_MASK),
> >> -	PINCTRL_CONF_DESC(13, REG_GPIO_L_PD, BIT(0)),
> >> -	PINCTRL_CONF_DESC(14, REG_GPIO_L_PD, BIT(1)),
> >> -	PINCTRL_CONF_DESC(15, REG_GPIO_L_PD, BIT(2)),
> >> -	PINCTRL_CONF_DESC(16, REG_GPIO_L_PD, BIT(3)),
> >> -	PINCTRL_CONF_DESC(17, REG_GPIO_L_PD, BIT(4)),
> >> -	PINCTRL_CONF_DESC(18, REG_GPIO_L_PD, BIT(5)),
> >> -	PINCTRL_CONF_DESC(19, REG_GPIO_L_PD, BIT(6)),
> >> -	PINCTRL_CONF_DESC(20, REG_GPIO_L_PD, BIT(7)),
> >> -	PINCTRL_CONF_DESC(21, REG_GPIO_L_PD, BIT(8)),
> >> -	PINCTRL_CONF_DESC(22, REG_GPIO_L_PD, BIT(9)),
> >> -	PINCTRL_CONF_DESC(23, REG_GPIO_L_PD, BIT(10)),
> >> -	PINCTRL_CONF_DESC(24, REG_GPIO_L_PD, BIT(11)),
> >> -	PINCTRL_CONF_DESC(25, REG_GPIO_L_PD, BIT(12)),
> >> -	PINCTRL_CONF_DESC(26, REG_GPIO_L_PD, BIT(13)),
> >> -	PINCTRL_CONF_DESC(27, REG_GPIO_L_PD, BIT(14)),
> >> -	PINCTRL_CONF_DESC(28, REG_GPIO_L_PD, BIT(15)),
> >> -	PINCTRL_CONF_DESC(29, REG_GPIO_L_PD, BIT(16)),
> >> -	PINCTRL_CONF_DESC(30, REG_GPIO_L_PD, BIT(17)),
> >> -	PINCTRL_CONF_DESC(31, REG_GPIO_L_PD, BIT(18)),
> >> -	PINCTRL_CONF_DESC(32, REG_GPIO_L_PD, BIT(19)),
> >> -	PINCTRL_CONF_DESC(33, REG_GPIO_L_PD, BIT(20)),
> >> -	PINCTRL_CONF_DESC(34, REG_GPIO_L_PD, BIT(21)),
> >> -	PINCTRL_CONF_DESC(35, REG_GPIO_L_PD, BIT(22)),
> >> -	PINCTRL_CONF_DESC(36, REG_GPIO_L_PD, BIT(23)),
> >> -	PINCTRL_CONF_DESC(37, REG_GPIO_L_PD, BIT(24)),
> >> -	PINCTRL_CONF_DESC(38, REG_GPIO_L_PD, BIT(25)),
> >> -	PINCTRL_CONF_DESC(39, REG_GPIO_L_PD, BIT(26)),
> >> -	PINCTRL_CONF_DESC(40, REG_GPIO_L_PD, BIT(27)),
> >> -	PINCTRL_CONF_DESC(41, REG_GPIO_L_PD, BIT(28)),
> >> -	PINCTRL_CONF_DESC(42, REG_GPIO_L_PD, BIT(29)),
> >> -	PINCTRL_CONF_DESC(43, REG_GPIO_L_PD, BIT(30)),
> >> -	PINCTRL_CONF_DESC(44, REG_GPIO_L_PD, BIT(31)),
> >> -	PINCTRL_CONF_DESC(45, REG_GPIO_H_PD, BIT(0)),
> >> -	PINCTRL_CONF_DESC(46, REG_GPIO_H_PD, BIT(1)),
> >> -	PINCTRL_CONF_DESC(47, REG_GPIO_H_PD, BIT(2)),
> >> -	PINCTRL_CONF_DESC(48, REG_GPIO_H_PD, BIT(3)),
> >> -	PINCTRL_CONF_DESC(49, REG_GPIO_H_PD, BIT(4)),
> >> -	PINCTRL_CONF_DESC(50, REG_GPIO_H_PD, BIT(5)),
> >> -	PINCTRL_CONF_DESC(51, REG_GPIO_H_PD, BIT(6)),
> >> -	PINCTRL_CONF_DESC(52, REG_GPIO_H_PD, BIT(7)),
> >> -	PINCTRL_CONF_DESC(53, REG_GPIO_H_PD, BIT(8)),
> >> -	PINCTRL_CONF_DESC(54, REG_GPIO_H_PD, BIT(9)),
> >> -	PINCTRL_CONF_DESC(55, REG_GPIO_H_PD, BIT(10)),
> >> -	PINCTRL_CONF_DESC(56, REG_GPIO_H_PD, BIT(11)),
> >> -	PINCTRL_CONF_DESC(57, REG_GPIO_H_PD, BIT(12)),
> >> -	PINCTRL_CONF_DESC(58, REG_GPIO_H_PD, BIT(13)),
> >> -	PINCTRL_CONF_DESC(59, REG_GPIO_H_PD, BIT(14)),
> >> -	PINCTRL_CONF_DESC(60, REG_I2C_SDA_PD, PCIE0_RESET_PD_MASK),
> >> -	PINCTRL_CONF_DESC(61, REG_I2C_SDA_PD, PCIE1_RESET_PD_MASK),
> >> -	PINCTRL_CONF_DESC(62, REG_I2C_SDA_PD, PCIE2_RESET_PD_MASK),
> >> -};
> >> -
> >> -static const struct airoha_pinctrl_conf an7583_pinctrl_pulldown_conf[] = {
> >> -	PINCTRL_CONF_DESC(2, REG_GPIO_L_PD, BIT(0)),
> >> -	PINCTRL_CONF_DESC(3, REG_GPIO_L_PD, BIT(1)),
> >> -	PINCTRL_CONF_DESC(4, REG_GPIO_L_PD, BIT(2)),
> >> -	PINCTRL_CONF_DESC(5, REG_GPIO_L_PD, BIT(3)),
> >> -	PINCTRL_CONF_DESC(6, REG_GPIO_L_PD, BIT(4)),
> >> -	PINCTRL_CONF_DESC(7, REG_GPIO_L_PD, BIT(5)),
> >> -	PINCTRL_CONF_DESC(8, REG_GPIO_L_PD, BIT(6)),
> >> -	PINCTRL_CONF_DESC(9, REG_GPIO_L_PD, BIT(7)),
> >> -	PINCTRL_CONF_DESC(10, REG_GPIO_L_PD, BIT(8)),
> >> -	PINCTRL_CONF_DESC(11, REG_GPIO_L_PD, BIT(9)),
> >> -	PINCTRL_CONF_DESC(12, REG_GPIO_L_PD, BIT(10)),
> >> -	PINCTRL_CONF_DESC(13, REG_GPIO_L_PD, BIT(11)),
> >> -	PINCTRL_CONF_DESC(14, REG_GPIO_L_PD, BIT(12)),
> >> -	PINCTRL_CONF_DESC(15, REG_GPIO_L_PD, BIT(13)),
> >> -	PINCTRL_CONF_DESC(16, REG_GPIO_L_PD, BIT(14)),
> >> -	PINCTRL_CONF_DESC(17, REG_GPIO_L_PD, BIT(15)),
> >> -	PINCTRL_CONF_DESC(18, REG_GPIO_L_PD, BIT(16)),
> >> -	PINCTRL_CONF_DESC(19, REG_GPIO_L_PD, BIT(17)),
> >> -	PINCTRL_CONF_DESC(20, REG_GPIO_L_PD, BIT(18)),
> >> -	PINCTRL_CONF_DESC(21, REG_GPIO_L_PD, BIT(19)),
> >> -	PINCTRL_CONF_DESC(22, REG_GPIO_L_PD, BIT(20)),
> >> -	PINCTRL_CONF_DESC(23, REG_GPIO_L_PD, BIT(21)),
> >> -	PINCTRL_CONF_DESC(24, REG_GPIO_L_PD, BIT(22)),
> >> -	PINCTRL_CONF_DESC(25, REG_GPIO_L_PD, BIT(23)),
> >> -	PINCTRL_CONF_DESC(26, REG_GPIO_L_PD, BIT(24)),
> >> -	PINCTRL_CONF_DESC(27, REG_GPIO_L_PD, BIT(25)),
> >> -	PINCTRL_CONF_DESC(28, REG_GPIO_L_PD, BIT(26)),
> >> -	PINCTRL_CONF_DESC(29, REG_GPIO_L_PD, BIT(27)),
> >> -	PINCTRL_CONF_DESC(30, REG_GPIO_L_PD, BIT(28)),
> >> -	PINCTRL_CONF_DESC(31, REG_GPIO_L_PD, BIT(29)),
> >> -	PINCTRL_CONF_DESC(32, REG_GPIO_L_PD, BIT(30)),
> >> -	PINCTRL_CONF_DESC(33, REG_GPIO_L_PD, BIT(31)),
> >> -	PINCTRL_CONF_DESC(34, REG_GPIO_H_PD, BIT(0)),
> >> -	PINCTRL_CONF_DESC(35, REG_GPIO_H_PD, BIT(1)),
> >> -	PINCTRL_CONF_DESC(36, REG_GPIO_H_PD, BIT(2)),
> >> -	PINCTRL_CONF_DESC(37, REG_GPIO_H_PD, BIT(3)),
> >> -	PINCTRL_CONF_DESC(38, REG_GPIO_H_PD, BIT(4)),
> >> -	PINCTRL_CONF_DESC(39, REG_GPIO_H_PD, BIT(5)),
> >> -	PINCTRL_CONF_DESC(40, REG_GPIO_H_PD, BIT(6)),
> >> -	PINCTRL_CONF_DESC(41, REG_I2C_SDA_PD, I2C_SCL_PD_MASK),
> >> -	PINCTRL_CONF_DESC(42, REG_I2C_SDA_PD, I2C_SDA_PD_MASK),
> >> -	PINCTRL_CONF_DESC(43, REG_I2C_SDA_PD, AN7583_I2C1_SCL_PD_MASK),
> >> -	PINCTRL_CONF_DESC(44, REG_I2C_SDA_PD, AN7583_I2C1_SDA_PD_MASK),
> >> -	PINCTRL_CONF_DESC(45, REG_I2C_SDA_PD, SPI_CLK_PD_MASK),
> >> -	PINCTRL_CONF_DESC(46, REG_I2C_SDA_PD, SPI_CS0_PD_MASK),
> >> -	PINCTRL_CONF_DESC(47, REG_I2C_SDA_PD, SPI_MOSI_PD_MASK),
> >> -	PINCTRL_CONF_DESC(48, REG_I2C_SDA_PD, SPI_MISO_PD_MASK),
> >> -	PINCTRL_CONF_DESC(49, REG_I2C_SDA_PD, UART1_TXD_PD_MASK),
> >> -	PINCTRL_CONF_DESC(50, REG_I2C_SDA_PD, UART1_RXD_PD_MASK),
> >> -	PINCTRL_CONF_DESC(51, REG_I2C_SDA_PD, PCIE0_RESET_PD_MASK),
> >> -	PINCTRL_CONF_DESC(52, REG_I2C_SDA_PD, PCIE1_RESET_PD_MASK),
> >> -	PINCTRL_CONF_DESC(53, REG_I2C_SDA_PD, AN7583_MDC_0_PD_MASK),
> >> -	PINCTRL_CONF_DESC(54, REG_I2C_SDA_PD, AN7583_MDIO_0_PD_MASK),
> >> -};
> >> -
> >> -static const struct airoha_pinctrl_conf en7581_pinctrl_drive_e2_conf[] = {
> >> -	PINCTRL_CONF_DESC(0, REG_I2C_SDA_E2, UART1_TXD_E2_MASK),
> >> -	PINCTRL_CONF_DESC(1, REG_I2C_SDA_E2, UART1_RXD_E2_MASK),
> >> -	PINCTRL_CONF_DESC(2, REG_I2C_SDA_E2, I2C_SDA_E2_MASK),
> >> -	PINCTRL_CONF_DESC(3, REG_I2C_SDA_E2, I2C_SCL_E2_MASK),
> >> -	PINCTRL_CONF_DESC(4, REG_I2C_SDA_E2, SPI_CS0_E2_MASK),
> >> -	PINCTRL_CONF_DESC(5, REG_I2C_SDA_E2, SPI_CLK_E2_MASK),
> >> -	PINCTRL_CONF_DESC(6, REG_I2C_SDA_E2, SPI_MOSI_E2_MASK),
> >> -	PINCTRL_CONF_DESC(7, REG_I2C_SDA_E2, SPI_MISO_E2_MASK),
> >> -	PINCTRL_CONF_DESC(13, REG_GPIO_L_E2, BIT(0)),
> >> -	PINCTRL_CONF_DESC(14, REG_GPIO_L_E2, BIT(1)),
> >> -	PINCTRL_CONF_DESC(15, REG_GPIO_L_E2, BIT(2)),
> >> -	PINCTRL_CONF_DESC(16, REG_GPIO_L_E2, BIT(3)),
> >> -	PINCTRL_CONF_DESC(17, REG_GPIO_L_E2, BIT(4)),
> >> -	PINCTRL_CONF_DESC(18, REG_GPIO_L_E2, BIT(5)),
> >> -	PINCTRL_CONF_DESC(19, REG_GPIO_L_E2, BIT(6)),
> >> -	PINCTRL_CONF_DESC(20, REG_GPIO_L_E2, BIT(7)),
> >> -	PINCTRL_CONF_DESC(21, REG_GPIO_L_E2, BIT(8)),
> >> -	PINCTRL_CONF_DESC(22, REG_GPIO_L_E2, BIT(9)),
> >> -	PINCTRL_CONF_DESC(23, REG_GPIO_L_E2, BIT(10)),
> >> -	PINCTRL_CONF_DESC(24, REG_GPIO_L_E2, BIT(11)),
> >> -	PINCTRL_CONF_DESC(25, REG_GPIO_L_E2, BIT(12)),
> >> -	PINCTRL_CONF_DESC(26, REG_GPIO_L_E2, BIT(13)),
> >> -	PINCTRL_CONF_DESC(27, REG_GPIO_L_E2, BIT(14)),
> >> -	PINCTRL_CONF_DESC(28, REG_GPIO_L_E2, BIT(15)),
> >> -	PINCTRL_CONF_DESC(29, REG_GPIO_L_E2, BIT(16)),
> >> -	PINCTRL_CONF_DESC(30, REG_GPIO_L_E2, BIT(17)),
> >> -	PINCTRL_CONF_DESC(31, REG_GPIO_L_E2, BIT(18)),
> >> -	PINCTRL_CONF_DESC(32, REG_GPIO_L_E2, BIT(19)),
> >> -	PINCTRL_CONF_DESC(33, REG_GPIO_L_E2, BIT(20)),
> >> -	PINCTRL_CONF_DESC(34, REG_GPIO_L_E2, BIT(21)),
> >> -	PINCTRL_CONF_DESC(35, REG_GPIO_L_E2, BIT(22)),
> >> -	PINCTRL_CONF_DESC(36, REG_GPIO_L_E2, BIT(23)),
> >> -	PINCTRL_CONF_DESC(37, REG_GPIO_L_E2, BIT(24)),
> >> -	PINCTRL_CONF_DESC(38, REG_GPIO_L_E2, BIT(25)),
> >> -	PINCTRL_CONF_DESC(39, REG_GPIO_L_E2, BIT(26)),
> >> -	PINCTRL_CONF_DESC(40, REG_GPIO_L_E2, BIT(27)),
> >> -	PINCTRL_CONF_DESC(41, REG_GPIO_L_E2, BIT(28)),
> >> -	PINCTRL_CONF_DESC(42, REG_GPIO_L_E2, BIT(29)),
> >> -	PINCTRL_CONF_DESC(43, REG_GPIO_L_E2, BIT(30)),
> >> -	PINCTRL_CONF_DESC(44, REG_GPIO_L_E2, BIT(31)),
> >> -	PINCTRL_CONF_DESC(45, REG_GPIO_H_E2, BIT(0)),
> >> -	PINCTRL_CONF_DESC(46, REG_GPIO_H_E2, BIT(1)),
> >> -	PINCTRL_CONF_DESC(47, REG_GPIO_H_E2, BIT(2)),
> >> -	PINCTRL_CONF_DESC(48, REG_GPIO_H_E2, BIT(3)),
> >> -	PINCTRL_CONF_DESC(49, REG_GPIO_H_E2, BIT(4)),
> >> -	PINCTRL_CONF_DESC(50, REG_GPIO_H_E2, BIT(5)),
> >> -	PINCTRL_CONF_DESC(51, REG_GPIO_H_E2, BIT(6)),
> >> -	PINCTRL_CONF_DESC(52, REG_GPIO_H_E2, BIT(7)),
> >> -	PINCTRL_CONF_DESC(53, REG_GPIO_H_E2, BIT(8)),
> >> -	PINCTRL_CONF_DESC(54, REG_GPIO_H_E2, BIT(9)),
> >> -	PINCTRL_CONF_DESC(55, REG_GPIO_H_E2, BIT(10)),
> >> -	PINCTRL_CONF_DESC(56, REG_GPIO_H_E2, BIT(11)),
> >> -	PINCTRL_CONF_DESC(57, REG_GPIO_H_E2, BIT(12)),
> >> -	PINCTRL_CONF_DESC(58, REG_GPIO_H_E2, BIT(13)),
> >> -	PINCTRL_CONF_DESC(59, REG_GPIO_H_E2, BIT(14)),
> >> -	PINCTRL_CONF_DESC(60, REG_I2C_SDA_E2, PCIE0_RESET_E2_MASK),
> >> -	PINCTRL_CONF_DESC(61, REG_I2C_SDA_E2, PCIE1_RESET_E2_MASK),
> >> -	PINCTRL_CONF_DESC(62, REG_I2C_SDA_E2, PCIE2_RESET_E2_MASK),
> >> -};
> >> -
> >> -static const struct airoha_pinctrl_conf an7583_pinctrl_drive_e2_conf[] = {
> >> -	PINCTRL_CONF_DESC(2, REG_GPIO_L_E2, BIT(0)),
> >> -	PINCTRL_CONF_DESC(3, REG_GPIO_L_E2, BIT(1)),
> >> -	PINCTRL_CONF_DESC(4, REG_GPIO_L_E2, BIT(2)),
> >> -	PINCTRL_CONF_DESC(5, REG_GPIO_L_E2, BIT(3)),
> >> -	PINCTRL_CONF_DESC(6, REG_GPIO_L_E2, BIT(4)),
> >> -	PINCTRL_CONF_DESC(7, REG_GPIO_L_E2, BIT(5)),
> >> -	PINCTRL_CONF_DESC(8, REG_GPIO_L_E2, BIT(6)),
> >> -	PINCTRL_CONF_DESC(9, REG_GPIO_L_E2, BIT(7)),
> >> -	PINCTRL_CONF_DESC(10, REG_GPIO_L_E2, BIT(8)),
> >> -	PINCTRL_CONF_DESC(11, REG_GPIO_L_E2, BIT(9)),
> >> -	PINCTRL_CONF_DESC(12, REG_GPIO_L_E2, BIT(10)),
> >> -	PINCTRL_CONF_DESC(13, REG_GPIO_L_E2, BIT(11)),
> >> -	PINCTRL_CONF_DESC(14, REG_GPIO_L_E2, BIT(12)),
> >> -	PINCTRL_CONF_DESC(15, REG_GPIO_L_E2, BIT(13)),
> >> -	PINCTRL_CONF_DESC(16, REG_GPIO_L_E2, BIT(14)),
> >> -	PINCTRL_CONF_DESC(17, REG_GPIO_L_E2, BIT(15)),
> >> -	PINCTRL_CONF_DESC(18, REG_GPIO_L_E2, BIT(16)),
> >> -	PINCTRL_CONF_DESC(19, REG_GPIO_L_E2, BIT(17)),
> >> -	PINCTRL_CONF_DESC(20, REG_GPIO_L_E2, BIT(18)),
> >> -	PINCTRL_CONF_DESC(21, REG_GPIO_L_E2, BIT(19)),
> >> -	PINCTRL_CONF_DESC(22, REG_GPIO_L_E2, BIT(20)),
> >> -	PINCTRL_CONF_DESC(23, REG_GPIO_L_E2, BIT(21)),
> >> -	PINCTRL_CONF_DESC(24, REG_GPIO_L_E2, BIT(22)),
> >> -	PINCTRL_CONF_DESC(25, REG_GPIO_L_E2, BIT(23)),
> >> -	PINCTRL_CONF_DESC(26, REG_GPIO_L_E2, BIT(24)),
> >> -	PINCTRL_CONF_DESC(27, REG_GPIO_L_E2, BIT(25)),
> >> -	PINCTRL_CONF_DESC(28, REG_GPIO_L_E2, BIT(26)),
> >> -	PINCTRL_CONF_DESC(29, REG_GPIO_L_E2, BIT(27)),
> >> -	PINCTRL_CONF_DESC(30, REG_GPIO_L_E2, BIT(28)),
> >> -	PINCTRL_CONF_DESC(31, REG_GPIO_L_E2, BIT(29)),
> >> -	PINCTRL_CONF_DESC(32, REG_GPIO_L_E2, BIT(30)),
> >> -	PINCTRL_CONF_DESC(33, REG_GPIO_L_E2, BIT(31)),
> >> -	PINCTRL_CONF_DESC(34, REG_GPIO_H_E2, BIT(0)),
> >> -	PINCTRL_CONF_DESC(35, REG_GPIO_H_E2, BIT(1)),
> >> -	PINCTRL_CONF_DESC(36, REG_GPIO_H_E2, BIT(2)),
> >> -	PINCTRL_CONF_DESC(37, REG_GPIO_H_E2, BIT(3)),
> >> -	PINCTRL_CONF_DESC(38, REG_GPIO_H_E2, BIT(4)),
> >> -	PINCTRL_CONF_DESC(39, REG_GPIO_H_E2, BIT(5)),
> >> -	PINCTRL_CONF_DESC(40, REG_GPIO_H_E2, BIT(6)),
> >> -	PINCTRL_CONF_DESC(41, REG_I2C_SDA_E2, I2C_SCL_E2_MASK),
> >> -	PINCTRL_CONF_DESC(42, REG_I2C_SDA_E2, I2C_SDA_E2_MASK),
> >> -	PINCTRL_CONF_DESC(43, REG_I2C_SDA_E2, AN7583_I2C1_SCL_E2_MASK),
> >> -	PINCTRL_CONF_DESC(44, REG_I2C_SDA_E2, AN7583_I2C1_SDA_E2_MASK),
> >> -	PINCTRL_CONF_DESC(45, REG_I2C_SDA_E2, SPI_CLK_E2_MASK),
> >> -	PINCTRL_CONF_DESC(46, REG_I2C_SDA_E2, SPI_CS0_E2_MASK),
> >> -	PINCTRL_CONF_DESC(47, REG_I2C_SDA_E2, SPI_MOSI_E2_MASK),
> >> -	PINCTRL_CONF_DESC(48, REG_I2C_SDA_E2, SPI_MISO_E2_MASK),
> >> -	PINCTRL_CONF_DESC(49, REG_I2C_SDA_E2, UART1_TXD_E2_MASK),
> >> -	PINCTRL_CONF_DESC(50, REG_I2C_SDA_E2, UART1_RXD_E2_MASK),
> >> -	PINCTRL_CONF_DESC(51, REG_I2C_SDA_E2, PCIE0_RESET_E2_MASK),
> >> -	PINCTRL_CONF_DESC(52, REG_I2C_SDA_E2, PCIE1_RESET_E2_MASK),
> >> -	PINCTRL_CONF_DESC(53, REG_I2C_SDA_E2, AN7583_MDC_0_E2_MASK),
> >> -	PINCTRL_CONF_DESC(54, REG_I2C_SDA_E2, AN7583_MDIO_0_E2_MASK),
> >> -};
> >> -
> >> -static const struct airoha_pinctrl_conf en7581_pinctrl_drive_e4_conf[] = {
> >> -	PINCTRL_CONF_DESC(0, REG_I2C_SDA_E4, UART1_TXD_E4_MASK),
> >> -	PINCTRL_CONF_DESC(1, REG_I2C_SDA_E4, UART1_RXD_E4_MASK),
> >> -	PINCTRL_CONF_DESC(2, REG_I2C_SDA_E4, I2C_SDA_E4_MASK),
> >> -	PINCTRL_CONF_DESC(3, REG_I2C_SDA_E4, I2C_SCL_E4_MASK),
> >> -	PINCTRL_CONF_DESC(4, REG_I2C_SDA_E4, SPI_CS0_E4_MASK),
> >> -	PINCTRL_CONF_DESC(5, REG_I2C_SDA_E4, SPI_CLK_E4_MASK),
> >> -	PINCTRL_CONF_DESC(6, REG_I2C_SDA_E4, SPI_MOSI_E4_MASK),
> >> -	PINCTRL_CONF_DESC(7, REG_I2C_SDA_E4, SPI_MISO_E4_MASK),
> >> -	PINCTRL_CONF_DESC(13, REG_GPIO_L_E4, BIT(0)),
> >> -	PINCTRL_CONF_DESC(14, REG_GPIO_L_E4, BIT(1)),
> >> -	PINCTRL_CONF_DESC(15, REG_GPIO_L_E4, BIT(2)),
> >> -	PINCTRL_CONF_DESC(16, REG_GPIO_L_E4, BIT(3)),
> >> -	PINCTRL_CONF_DESC(17, REG_GPIO_L_E4, BIT(4)),
> >> -	PINCTRL_CONF_DESC(18, REG_GPIO_L_E4, BIT(5)),
> >> -	PINCTRL_CONF_DESC(19, REG_GPIO_L_E4, BIT(6)),
> >> -	PINCTRL_CONF_DESC(20, REG_GPIO_L_E4, BIT(7)),
> >> -	PINCTRL_CONF_DESC(21, REG_GPIO_L_E4, BIT(8)),
> >> -	PINCTRL_CONF_DESC(22, REG_GPIO_L_E4, BIT(9)),
> >> -	PINCTRL_CONF_DESC(23, REG_GPIO_L_E4, BIT(10)),
> >> -	PINCTRL_CONF_DESC(24, REG_GPIO_L_E4, BIT(11)),
> >> -	PINCTRL_CONF_DESC(25, REG_GPIO_L_E4, BIT(12)),
> >> -	PINCTRL_CONF_DESC(26, REG_GPIO_L_E4, BIT(13)),
> >> -	PINCTRL_CONF_DESC(27, REG_GPIO_L_E4, BIT(14)),
> >> -	PINCTRL_CONF_DESC(28, REG_GPIO_L_E4, BIT(15)),
> >> -	PINCTRL_CONF_DESC(29, REG_GPIO_L_E4, BIT(16)),
> >> -	PINCTRL_CONF_DESC(30, REG_GPIO_L_E4, BIT(17)),
> >> -	PINCTRL_CONF_DESC(31, REG_GPIO_L_E4, BIT(18)),
> >> -	PINCTRL_CONF_DESC(32, REG_GPIO_L_E4, BIT(19)),
> >> -	PINCTRL_CONF_DESC(33, REG_GPIO_L_E4, BIT(20)),
> >> -	PINCTRL_CONF_DESC(34, REG_GPIO_L_E4, BIT(21)),
> >> -	PINCTRL_CONF_DESC(35, REG_GPIO_L_E4, BIT(22)),
> >> -	PINCTRL_CONF_DESC(36, REG_GPIO_L_E4, BIT(23)),
> >> -	PINCTRL_CONF_DESC(37, REG_GPIO_L_E4, BIT(24)),
> >> -	PINCTRL_CONF_DESC(38, REG_GPIO_L_E4, BIT(25)),
> >> -	PINCTRL_CONF_DESC(39, REG_GPIO_L_E4, BIT(26)),
> >> -	PINCTRL_CONF_DESC(40, REG_GPIO_L_E4, BIT(27)),
> >> -	PINCTRL_CONF_DESC(41, REG_GPIO_L_E4, BIT(28)),
> >> -	PINCTRL_CONF_DESC(42, REG_GPIO_L_E4, BIT(29)),
> >> -	PINCTRL_CONF_DESC(43, REG_GPIO_L_E4, BIT(30)),
> >> -	PINCTRL_CONF_DESC(44, REG_GPIO_L_E4, BIT(31)),
> >> -	PINCTRL_CONF_DESC(45, REG_GPIO_H_E4, BIT(0)),
> >> -	PINCTRL_CONF_DESC(46, REG_GPIO_H_E4, BIT(1)),
> >> -	PINCTRL_CONF_DESC(47, REG_GPIO_H_E4, BIT(2)),
> >> -	PINCTRL_CONF_DESC(48, REG_GPIO_H_E4, BIT(3)),
> >> -	PINCTRL_CONF_DESC(49, REG_GPIO_H_E4, BIT(4)),
> >> -	PINCTRL_CONF_DESC(50, REG_GPIO_H_E4, BIT(5)),
> >> -	PINCTRL_CONF_DESC(51, REG_GPIO_H_E4, BIT(6)),
> >> -	PINCTRL_CONF_DESC(52, REG_GPIO_H_E4, BIT(7)),
> >> -	PINCTRL_CONF_DESC(53, REG_GPIO_H_E4, BIT(8)),
> >> -	PINCTRL_CONF_DESC(54, REG_GPIO_H_E4, BIT(9)),
> >> -	PINCTRL_CONF_DESC(55, REG_GPIO_H_E4, BIT(10)),
> >> -	PINCTRL_CONF_DESC(56, REG_GPIO_H_E4, BIT(11)),
> >> -	PINCTRL_CONF_DESC(57, REG_GPIO_H_E4, BIT(12)),
> >> -	PINCTRL_CONF_DESC(58, REG_GPIO_H_E4, BIT(13)),
> >> -	PINCTRL_CONF_DESC(59, REG_GPIO_H_E4, BIT(14)),
> >> -	PINCTRL_CONF_DESC(60, REG_I2C_SDA_E4, PCIE0_RESET_E4_MASK),
> >> -	PINCTRL_CONF_DESC(61, REG_I2C_SDA_E4, PCIE1_RESET_E4_MASK),
> >> -	PINCTRL_CONF_DESC(62, REG_I2C_SDA_E4, PCIE2_RESET_E4_MASK),
> >> -};
> >> -
> >> -static const struct airoha_pinctrl_conf an7583_pinctrl_drive_e4_conf[] = {
> >> -	PINCTRL_CONF_DESC(2, REG_GPIO_L_E4, BIT(0)),
> >> -	PINCTRL_CONF_DESC(3, REG_GPIO_L_E4, BIT(1)),
> >> -	PINCTRL_CONF_DESC(4, REG_GPIO_L_E4, BIT(2)),
> >> -	PINCTRL_CONF_DESC(5, REG_GPIO_L_E4, BIT(3)),
> >> -	PINCTRL_CONF_DESC(6, REG_GPIO_L_E4, BIT(4)),
> >> -	PINCTRL_CONF_DESC(7, REG_GPIO_L_E4, BIT(5)),
> >> -	PINCTRL_CONF_DESC(8, REG_GPIO_L_E4, BIT(6)),
> >> -	PINCTRL_CONF_DESC(9, REG_GPIO_L_E4, BIT(7)),
> >> -	PINCTRL_CONF_DESC(10, REG_GPIO_L_E4, BIT(8)),
> >> -	PINCTRL_CONF_DESC(11, REG_GPIO_L_E4, BIT(9)),
> >> -	PINCTRL_CONF_DESC(12, REG_GPIO_L_E4, BIT(10)),
> >> -	PINCTRL_CONF_DESC(13, REG_GPIO_L_E4, BIT(11)),
> >> -	PINCTRL_CONF_DESC(14, REG_GPIO_L_E4, BIT(12)),
> >> -	PINCTRL_CONF_DESC(15, REG_GPIO_L_E4, BIT(13)),
> >> -	PINCTRL_CONF_DESC(16, REG_GPIO_L_E4, BIT(14)),
> >> -	PINCTRL_CONF_DESC(17, REG_GPIO_L_E4, BIT(15)),
> >> -	PINCTRL_CONF_DESC(18, REG_GPIO_L_E4, BIT(16)),
> >> -	PINCTRL_CONF_DESC(19, REG_GPIO_L_E4, BIT(17)),
> >> -	PINCTRL_CONF_DESC(20, REG_GPIO_L_E4, BIT(18)),
> >> -	PINCTRL_CONF_DESC(21, REG_GPIO_L_E4, BIT(19)),
> >> -	PINCTRL_CONF_DESC(22, REG_GPIO_L_E4, BIT(20)),
> >> -	PINCTRL_CONF_DESC(23, REG_GPIO_L_E4, BIT(21)),
> >> -	PINCTRL_CONF_DESC(24, REG_GPIO_L_E4, BIT(22)),
> >> -	PINCTRL_CONF_DESC(25, REG_GPIO_L_E4, BIT(23)),
> >> -	PINCTRL_CONF_DESC(26, REG_GPIO_L_E4, BIT(24)),
> >> -	PINCTRL_CONF_DESC(27, REG_GPIO_L_E4, BIT(25)),
> >> -	PINCTRL_CONF_DESC(28, REG_GPIO_L_E4, BIT(26)),
> >> -	PINCTRL_CONF_DESC(29, REG_GPIO_L_E4, BIT(27)),
> >> -	PINCTRL_CONF_DESC(30, REG_GPIO_L_E4, BIT(28)),
> >> -	PINCTRL_CONF_DESC(31, REG_GPIO_L_E4, BIT(29)),
> >> -	PINCTRL_CONF_DESC(32, REG_GPIO_L_E4, BIT(30)),
> >> -	PINCTRL_CONF_DESC(33, REG_GPIO_L_E4, BIT(31)),
> >> -	PINCTRL_CONF_DESC(34, REG_GPIO_H_E4, BIT(0)),
> >> -	PINCTRL_CONF_DESC(35, REG_GPIO_H_E4, BIT(1)),
> >> -	PINCTRL_CONF_DESC(36, REG_GPIO_H_E4, BIT(2)),
> >> -	PINCTRL_CONF_DESC(37, REG_GPIO_H_E4, BIT(3)),
> >> -	PINCTRL_CONF_DESC(38, REG_GPIO_H_E4, BIT(4)),
> >> -	PINCTRL_CONF_DESC(39, REG_GPIO_H_E4, BIT(5)),
> >> -	PINCTRL_CONF_DESC(40, REG_GPIO_H_E4, BIT(6)),
> >> -	PINCTRL_CONF_DESC(41, REG_I2C_SDA_E4, I2C_SCL_E4_MASK),
> >> -	PINCTRL_CONF_DESC(42, REG_I2C_SDA_E4, I2C_SDA_E4_MASK),
> >> -	PINCTRL_CONF_DESC(43, REG_I2C_SDA_E4, AN7583_I2C1_SCL_E4_MASK),
> >> -	PINCTRL_CONF_DESC(44, REG_I2C_SDA_E4, AN7583_I2C1_SDA_E4_MASK),
> >> -	PINCTRL_CONF_DESC(45, REG_I2C_SDA_E4, SPI_CLK_E4_MASK),
> >> -	PINCTRL_CONF_DESC(46, REG_I2C_SDA_E4, SPI_CS0_E4_MASK),
> >> -	PINCTRL_CONF_DESC(47, REG_I2C_SDA_E4, SPI_MOSI_E4_MASK),
> >> -	PINCTRL_CONF_DESC(48, REG_I2C_SDA_E4, SPI_MISO_E4_MASK),
> >> -	PINCTRL_CONF_DESC(49, REG_I2C_SDA_E4, UART1_TXD_E4_MASK),
> >> -	PINCTRL_CONF_DESC(50, REG_I2C_SDA_E4, UART1_RXD_E4_MASK),
> >> -	PINCTRL_CONF_DESC(51, REG_I2C_SDA_E4, PCIE0_RESET_E4_MASK),
> >> -	PINCTRL_CONF_DESC(52, REG_I2C_SDA_E4, PCIE1_RESET_E4_MASK),
> >> -	PINCTRL_CONF_DESC(53, REG_I2C_SDA_E4, AN7583_MDC_0_E4_MASK),
> >> -	PINCTRL_CONF_DESC(54, REG_I2C_SDA_E4, AN7583_MDIO_0_E4_MASK),
> >> -};
> >> -
> >> -static const struct airoha_pinctrl_conf en7581_pinctrl_pcie_rst_od_conf[] = {
> >> -	PINCTRL_CONF_DESC(60, REG_PCIE_RESET_OD, PCIE0_RESET_OD_MASK),
> >> -	PINCTRL_CONF_DESC(61, REG_PCIE_RESET_OD, PCIE1_RESET_OD_MASK),
> >> -	PINCTRL_CONF_DESC(62, REG_PCIE_RESET_OD, PCIE2_RESET_OD_MASK),
> >> -};
> >> -
> >> -static const struct airoha_pinctrl_conf an7583_pinctrl_pcie_rst_od_conf[] = {
> >> -	PINCTRL_CONF_DESC(51, REG_PCIE_RESET_OD, PCIE0_RESET_OD_MASK),
> >> -	PINCTRL_CONF_DESC(52, REG_PCIE_RESET_OD, PCIE1_RESET_OD_MASK),
> >> -};
> >> -
> >>  static int airoha_convert_pin_to_reg_offset(struct pinctrl_dev *pctrl_dev,
> >>  					    struct pinctrl_gpio_range *range,
> >>  					    int pin)
> >> @@ -2606,6 +318,7 @@ static int airoha_pinctrl_add_gpiochip(struct airoha_pinctrl *pinctrl,
> >>  					struct platform_device *pdev)
> >>  {
> >>  	struct airoha_pinctrl_gpiochip *chip = &pinctrl->gpiochip;
> >> +	struct irq_chip *irq_chip = &pinctrl->gpio_irq_chip;
> >>  	struct gpio_chip *gc = &chip->chip;
> >>  	struct gpio_irq_chip *girq = &gc->irq;
> >>  	struct device *dev = &pdev->dev;
> >> @@ -2630,9 +343,11 @@ static int airoha_pinctrl_add_gpiochip(struct airoha_pinctrl *pinctrl,
> >>  	gc->base = -1;
> >>  	gc->ngpio = AIROHA_NUM_PINS;
> >>  
> >> +	memcpy(irq_chip, &airoha_gpio_irq_chip, sizeof(struct irq_chip));
> >> +
> >>  	girq->default_type = IRQ_TYPE_NONE;
> >>  	girq->handler = handle_bad_irq;
> >> -	gpio_irq_chip_set_chip(girq, &airoha_gpio_irq_chip);
> >> +	gpio_irq_chip_set_chip(girq, irq_chip);
> >>  
> >>  	irq = platform_get_irq(pdev, 0);
> >>  	if (irq < 0)
> >> @@ -3011,7 +726,7 @@ static const struct pinctrl_ops airoha_pctlops = {
> >>  	.dt_free_map = pinconf_generic_dt_free_map,
> >>  };
> >>  
> >> -static int airoha_pinctrl_probe(struct platform_device *pdev)
> >> +int airoha_pinctrl_probe(struct platform_device *pdev)
> >>  {
> >>  	const struct airoha_pinctrl_match_data *data;
> >>  	struct device *dev = &pdev->dev;
> >> @@ -3020,6 +735,8 @@ static int airoha_pinctrl_probe(struct platform_device *pdev)
> >>  	int err, i;
> >>  
> >>  	data = device_get_match_data(dev);
> >> +	if (!data)
> >> +		return -EINVAL;
> >>  
> >>  	pinctrl = devm_kzalloc(dev, sizeof(*pinctrl), GFP_KERNEL);
> >>  	if (!pinctrl)
> >> @@ -3036,8 +753,8 @@ static int airoha_pinctrl_probe(struct platform_device *pdev)
> >>  	pinctrl->chip_scu = map;
> >>  
> >>  	/* Init pinctrl desc struct */
> >> -	pinctrl->desc.name = KBUILD_MODNAME;
> >> -	pinctrl->desc.owner = THIS_MODULE;
> >> +	pinctrl->desc.name = data->pinctrl_name;
> >> +	pinctrl->desc.owner = data->pinctrl_owner;
> >>  	pinctrl->desc.pctlops = &airoha_pctlops;
> >>  	pinctrl->desc.pmxops = &airoha_pmxops;
> >>  	pinctrl->desc.confops = &airoha_confops;
> >> @@ -3089,87 +806,10 @@ static int airoha_pinctrl_probe(struct platform_device *pdev)
> >>  	/* build gpio-chip */
> >>  	return airoha_pinctrl_add_gpiochip(pinctrl, pdev);
> >>  }
> >> -
> >> -static const struct airoha_pinctrl_match_data en7581_pinctrl_match_data = {
> >> -	.pins = en7581_pinctrl_pins,
> >> -	.num_pins = ARRAY_SIZE(en7581_pinctrl_pins),
> >> -	.grps = en7581_pinctrl_groups,
> >> -	.num_grps = ARRAY_SIZE(en7581_pinctrl_groups),
> >> -	.funcs = en7581_pinctrl_funcs,
> >> -	.num_funcs = ARRAY_SIZE(en7581_pinctrl_funcs),
> >> -	.confs_info = {
> >> -		[AIROHA_PINCTRL_CONFS_PULLUP] = {
> >> -			.confs = en7581_pinctrl_pullup_conf,
> >> -			.num_confs = ARRAY_SIZE(en7581_pinctrl_pullup_conf),
> >> -		},
> >> -		[AIROHA_PINCTRL_CONFS_PULLDOWN] = {
> >> -			.confs = en7581_pinctrl_pulldown_conf,
> >> -			.num_confs = ARRAY_SIZE(en7581_pinctrl_pulldown_conf),
> >> -		},
> >> -		[AIROHA_PINCTRL_CONFS_DRIVE_E2] = {
> >> -			.confs = en7581_pinctrl_drive_e2_conf,
> >> -			.num_confs = ARRAY_SIZE(en7581_pinctrl_drive_e2_conf),
> >> -		},
> >> -		[AIROHA_PINCTRL_CONFS_DRIVE_E4] = {
> >> -			.confs = en7581_pinctrl_drive_e4_conf,
> >> -			.num_confs = ARRAY_SIZE(en7581_pinctrl_drive_e4_conf),
> >> -		},
> >> -		[AIROHA_PINCTRL_CONFS_PCIE_RST_OD] = {
> >> -			.confs = en7581_pinctrl_pcie_rst_od_conf,
> >> -			.num_confs = ARRAY_SIZE(en7581_pinctrl_pcie_rst_od_conf),
> >> -		},
> >> -	},
> >> -};
> >> -
> >> -static const struct airoha_pinctrl_match_data an7583_pinctrl_match_data = {
> >> -	.pins = an7583_pinctrl_pins,
> >> -	.num_pins = ARRAY_SIZE(an7583_pinctrl_pins),
> >> -	.grps = an7583_pinctrl_groups,
> >> -	.num_grps = ARRAY_SIZE(an7583_pinctrl_groups),
> >> -	.funcs = an7583_pinctrl_funcs,
> >> -	.num_funcs = ARRAY_SIZE(an7583_pinctrl_funcs),
> >> -	.confs_info = {
> >> -		[AIROHA_PINCTRL_CONFS_PULLUP] = {
> >> -			.confs = an7583_pinctrl_pullup_conf,
> >> -			.num_confs = ARRAY_SIZE(an7583_pinctrl_pullup_conf),
> >> -		},
> >> -		[AIROHA_PINCTRL_CONFS_PULLDOWN] = {
> >> -			.confs = an7583_pinctrl_pulldown_conf,
> >> -			.num_confs = ARRAY_SIZE(an7583_pinctrl_pulldown_conf),
> >> -		},
> >> -		[AIROHA_PINCTRL_CONFS_DRIVE_E2] = {
> >> -			.confs = an7583_pinctrl_drive_e2_conf,
> >> -			.num_confs = ARRAY_SIZE(an7583_pinctrl_drive_e2_conf),
> >> -		},
> >> -		[AIROHA_PINCTRL_CONFS_DRIVE_E4] = {
> >> -			.confs = an7583_pinctrl_drive_e4_conf,
> >> -			.num_confs = ARRAY_SIZE(an7583_pinctrl_drive_e4_conf),
> >> -		},
> >> -		[AIROHA_PINCTRL_CONFS_PCIE_RST_OD] = {
> >> -			.confs = an7583_pinctrl_pcie_rst_od_conf,
> >> -			.num_confs = ARRAY_SIZE(an7583_pinctrl_pcie_rst_od_conf),
> >> -		},
> >> -	},
> >> -};
> >> -
> >> -static const struct of_device_id airoha_pinctrl_of_match[] = {
> >> -	{ .compatible = "airoha,en7581-pinctrl", .data = &en7581_pinctrl_match_data },
> >> -	{ .compatible = "airoha,an7583-pinctrl", .data = &an7583_pinctrl_match_data },
> >> -	{ /* sentinel */ }
> >> -};
> >> -MODULE_DEVICE_TABLE(of, airoha_pinctrl_of_match);
> >> -
> >> -static struct platform_driver airoha_pinctrl_driver = {
> >> -	.probe = airoha_pinctrl_probe,
> >> -	.driver = {
> >> -		.name = "pinctrl-airoha",
> >> -		.of_match_table = airoha_pinctrl_of_match,
> >> -	},
> >> -};
> >> -module_platform_driver(airoha_pinctrl_driver);
> >> +EXPORT_SYMBOL_GPL(airoha_pinctrl_probe);
> >>  
> >>  MODULE_LICENSE("GPL");
> >>  MODULE_AUTHOR("Lorenzo Bianconi <lorenzo@kernel.org>");
> >>  MODULE_AUTHOR("Benjamin Larsson <benjamin.larsson@genexis.eu>");
> >>  MODULE_AUTHOR("Markus Gothe <markus.gothe@genexis.eu>");
> >> -MODULE_DESCRIPTION("Pinctrl driver for Airoha SoC");
> >> +MODULE_DESCRIPTION("Pinctrl common driver for Airoha SoC");
> >> diff --git a/drivers/pinctrl/airoha/pinctrl-an7581.c b/drivers/pinctrl/airoha/pinctrl-an7581.c
> >> new file mode 100644
> >> index 0000000000000..522b35bbaa121
> >> --- /dev/null
> >> +++ b/drivers/pinctrl/airoha/pinctrl-an7581.c
> >> @@ -0,0 +1,1486 @@
> >> +// SPDX-License-Identifier: GPL-2.0-only
> >> +/*
> >> + * Author: Lorenzo Bianconi <lorenzo@kernel.org>
> >> + * Author: Benjamin Larsson <benjamin.larsson@genexis.eu>
> >> + * Author: Markus Gothe <markus.gothe@genexis.eu>
> >> + */
> >> +
> >> +#include "airoha-common.h"
> >> +
> >> +/* MUX */
> >> +#define REG_GPIO_2ND_I2C_MODE			0x0214
> >> +#define GPIO_MDC_IO_MASTER_MODE_MASK		BIT(14)
> >> +#define GPIO_I2C_MASTER_MODE_MODE		BIT(13)
> >> +#define GPIO_I2S_MODE_MASK			BIT(12)
> >> +#define GPIO_I2C_SLAVE_MODE_MODE		BIT(11)
> >> +#define GPIO_LAN3_LED1_MODE_MASK		BIT(10)
> >> +#define GPIO_LAN3_LED0_MODE_MASK		BIT(9)
> >> +#define GPIO_LAN2_LED1_MODE_MASK		BIT(8)
> >> +#define GPIO_LAN2_LED0_MODE_MASK		BIT(7)
> >> +#define GPIO_LAN1_LED1_MODE_MASK		BIT(6)
> >> +#define GPIO_LAN1_LED0_MODE_MASK		BIT(5)
> >> +#define GPIO_LAN0_LED1_MODE_MASK		BIT(4)
> >> +#define GPIO_LAN0_LED0_MODE_MASK		BIT(3)
> >> +#define PON_TOD_1PPS_MODE_MASK			BIT(2)
> >> +#define GSW_TOD_1PPS_MODE_MASK			BIT(1)
> >> +#define GPIO_2ND_I2C_MODE_MASK			BIT(0)
> >> +
> >> +#define REG_GPIO_SPI_CS1_MODE			0x0218
> >> +#define GPIO_PCM_SPI_CS4_MODE_MASK		BIT(21)
> >> +#define GPIO_PCM_SPI_CS3_MODE_MASK		BIT(20)
> >> +#define GPIO_PCM_SPI_CS2_MODE_P156_MASK		BIT(19)
> >> +#define GPIO_PCM_SPI_CS2_MODE_P128_MASK		BIT(18)
> >> +#define GPIO_PCM_SPI_CS1_MODE_MASK		BIT(17)
> >> +#define GPIO_PCM_SPI_MODE_MASK			BIT(16)
> >> +#define GPIO_PCM2_MODE_MASK			BIT(13)
> >> +#define GPIO_PCM1_MODE_MASK			BIT(12)
> >> +#define GPIO_PCM_INT_MODE_MASK			BIT(9)
> >> +#define GPIO_PCM_RESET_MODE_MASK		BIT(8)
> >> +#define GPIO_SPI_QUAD_MODE_MASK			BIT(4)
> >> +#define GPIO_SPI_CS4_MODE_MASK			BIT(3)
> >> +#define GPIO_SPI_CS3_MODE_MASK			BIT(2)
> >> +#define GPIO_SPI_CS2_MODE_MASK			BIT(1)
> >> +#define GPIO_SPI_CS1_MODE_MASK			BIT(0)
> >> +
> >> +#define REG_GPIO_PON_MODE			0x021c
> >> +#define GPIO_PARALLEL_NAND_MODE_MASK		BIT(14)
> >> +#define GPIO_SGMII_MDIO_MODE_MASK		BIT(13)
> >> +#define GPIO_PCIE_RESET2_MASK			BIT(12)
> >> +#define SIPO_RCLK_MODE_MASK			BIT(11)
> >> +#define GPIO_PCIE_RESET1_MASK			BIT(10)
> >> +#define GPIO_PCIE_RESET0_MASK			BIT(9)
> >> +#define GPIO_UART5_MODE_MASK			BIT(8)
> >> +#define GPIO_UART4_MODE_MASK			BIT(7)
> >> +#define GPIO_HSUART_CTS_RTS_MODE_MASK		BIT(6)
> >> +#define GPIO_HSUART_MODE_MASK			BIT(5)
> >> +#define GPIO_UART2_CTS_RTS_MODE_MASK		BIT(4)
> >> +#define GPIO_UART2_MODE_MASK			BIT(3)
> >> +#define GPIO_SIPO_MODE_MASK			BIT(2)
> >> +#define GPIO_EMMC_MODE_MASK			BIT(1)
> >> +#define GPIO_PON_MODE_MASK			BIT(0)
> >> +
> >> +#define REG_NPU_UART_EN				0x0224
> >> +#define JTAG_UDI_EN_MASK			BIT(4)
> >> +#define JTAG_DFD_EN_MASK			BIT(3)
> >> +
> >> +#define REG_FORCE_GPIO_EN			0x0228
> >> +#define FORCE_GPIO_EN(n)			BIT(n)
> >> +
> >> +/* LED MAP */
> >> +#define REG_LAN_LED0_MAPPING			0x027c
> >> +#define REG_LAN_LED1_MAPPING			0x0280
> >> +
> >> +#define LAN4_LED_MAPPING_MASK			GENMASK(18, 16)
> >> +#define LAN4_PHY_LED_MAP(_n)			FIELD_PREP_CONST(LAN4_LED_MAPPING_MASK, (_n))
> >> +
> >> +#define LAN3_LED_MAPPING_MASK			GENMASK(14, 12)
> >> +#define LAN3_PHY_LED_MAP(_n)			FIELD_PREP_CONST(LAN3_LED_MAPPING_MASK, (_n))
> >> +
> >> +#define LAN2_LED_MAPPING_MASK			GENMASK(10, 8)
> >> +#define LAN2_PHY_LED_MAP(_n)			FIELD_PREP_CONST(LAN2_LED_MAPPING_MASK, (_n))
> >> +
> >> +#define LAN1_LED_MAPPING_MASK			GENMASK(6, 4)
> >> +#define LAN1_PHY_LED_MAP(_n)			FIELD_PREP_CONST(LAN1_LED_MAPPING_MASK, (_n))
> >> +
> >> +#define LAN0_LED_MAPPING_MASK			GENMASK(2, 0)
> >> +#define LAN0_PHY_LED_MAP(_n)			FIELD_PREP_CONST(LAN0_LED_MAPPING_MASK, (_n))
> >> +
> >> +/* CONF */
> >> +#define REG_I2C_SDA_E2				0x001c
> >> +#define SPI_MISO_E2_MASK			BIT(14)
> >> +#define SPI_MOSI_E2_MASK			BIT(13)
> >> +#define SPI_CLK_E2_MASK				BIT(12)
> >> +#define SPI_CS0_E2_MASK				BIT(11)
> >> +#define PCIE2_RESET_E2_MASK			BIT(10)
> >> +#define PCIE1_RESET_E2_MASK			BIT(9)
> >> +#define PCIE0_RESET_E2_MASK			BIT(8)
> >> +#define UART1_RXD_E2_MASK			BIT(3)
> >> +#define UART1_TXD_E2_MASK			BIT(2)
> >> +#define I2C_SCL_E2_MASK				BIT(1)
> >> +#define I2C_SDA_E2_MASK				BIT(0)
> >> +
> >> +#define REG_I2C_SDA_E4				0x0020
> >> +#define SPI_MISO_E4_MASK			BIT(14)
> >> +#define SPI_MOSI_E4_MASK			BIT(13)
> >> +#define SPI_CLK_E4_MASK				BIT(12)
> >> +#define SPI_CS0_E4_MASK				BIT(11)
> >> +#define PCIE2_RESET_E4_MASK			BIT(10)
> >> +#define PCIE1_RESET_E4_MASK			BIT(9)
> >> +#define PCIE0_RESET_E4_MASK			BIT(8)
> >> +#define UART1_RXD_E4_MASK			BIT(3)
> >> +#define UART1_TXD_E4_MASK			BIT(2)
> >> +#define I2C_SCL_E4_MASK				BIT(1)
> >> +#define I2C_SDA_E4_MASK				BIT(0)
> >> +
> >> +#define REG_GPIO_L_E2				0x0024
> >> +#define REG_GPIO_L_E4				0x0028
> >> +#define REG_GPIO_H_E2				0x002c
> >> +#define REG_GPIO_H_E4				0x0030
> >> +
> >> +#define REG_I2C_SDA_PU				0x0044
> >> +#define SPI_MISO_PU_MASK			BIT(14)
> >> +#define SPI_MOSI_PU_MASK			BIT(13)
> >> +#define SPI_CLK_PU_MASK				BIT(12)
> >> +#define SPI_CS0_PU_MASK				BIT(11)
> >> +#define PCIE2_RESET_PU_MASK			BIT(10)
> >> +#define PCIE1_RESET_PU_MASK			BIT(9)
> >> +#define PCIE0_RESET_PU_MASK			BIT(8)
> >> +#define UART1_RXD_PU_MASK			BIT(3)
> >> +#define UART1_TXD_PU_MASK			BIT(2)
> >> +#define I2C_SCL_PU_MASK				BIT(1)
> >> +#define I2C_SDA_PU_MASK				BIT(0)
> >> +
> >> +#define REG_I2C_SDA_PD				0x0048
> >> +#define SPI_MISO_PD_MASK			BIT(14)
> >> +#define SPI_MOSI_PD_MASK			BIT(13)
> >> +#define SPI_CLK_PD_MASK				BIT(12)
> >> +#define SPI_CS0_PD_MASK				BIT(11)
> >> +#define PCIE2_RESET_PD_MASK			BIT(10)
> >> +#define PCIE1_RESET_PD_MASK			BIT(9)
> >> +#define PCIE0_RESET_PD_MASK			BIT(8)
> >> +#define UART1_RXD_PD_MASK			BIT(3)
> >> +#define UART1_TXD_PD_MASK			BIT(2)
> >> +#define I2C_SCL_PD_MASK				BIT(1)
> >> +#define I2C_SDA_PD_MASK				BIT(0)
> >> +
> >> +#define REG_GPIO_L_PU				0x004c
> >> +#define REG_GPIO_L_PD				0x0050
> >> +#define REG_GPIO_H_PU				0x0054
> >> +#define REG_GPIO_H_PD				0x0058
> >> +
> >> +#define REG_PCIE_RESET_OD			0x018c
> >> +#define PCIE2_RESET_OD_MASK			BIT(2)
> >> +#define PCIE1_RESET_OD_MASK			BIT(1)
> >> +#define PCIE0_RESET_OD_MASK			BIT(0)
> >> +
> >> +/* PWM MODE CONF */
> >> +#define REG_GPIO_FLASH_MODE_CFG			0x0034
> >> +#define GPIO15_FLASH_MODE_CFG			BIT(15)
> >> +#define GPIO14_FLASH_MODE_CFG			BIT(14)
> >> +#define GPIO13_FLASH_MODE_CFG			BIT(13)
> >> +#define GPIO12_FLASH_MODE_CFG			BIT(12)
> >> +#define GPIO11_FLASH_MODE_CFG			BIT(11)
> >> +#define GPIO10_FLASH_MODE_CFG			BIT(10)
> >> +#define GPIO9_FLASH_MODE_CFG			BIT(9)
> >> +#define GPIO8_FLASH_MODE_CFG			BIT(8)
> >> +#define GPIO7_FLASH_MODE_CFG			BIT(7)
> >> +#define GPIO6_FLASH_MODE_CFG			BIT(6)
> >> +#define GPIO5_FLASH_MODE_CFG			BIT(5)
> >> +#define GPIO4_FLASH_MODE_CFG			BIT(4)
> >> +#define GPIO3_FLASH_MODE_CFG			BIT(3)
> >> +#define GPIO2_FLASH_MODE_CFG			BIT(2)
> >> +#define GPIO1_FLASH_MODE_CFG			BIT(1)
> >> +#define GPIO0_FLASH_MODE_CFG			BIT(0)
> >> +
> >> +/* PWM MODE CONF EXT */
> >> +#define REG_GPIO_FLASH_MODE_CFG_EXT		0x0068
> >> +#define GPIO51_FLASH_MODE_CFG			BIT(31)
> >> +#define GPIO50_FLASH_MODE_CFG			BIT(30)
> >> +#define GPIO49_FLASH_MODE_CFG			BIT(29)
> >> +#define GPIO48_FLASH_MODE_CFG			BIT(28)
> >> +#define GPIO47_FLASH_MODE_CFG			BIT(27)
> >> +#define GPIO46_FLASH_MODE_CFG			BIT(26)
> >> +#define GPIO45_FLASH_MODE_CFG			BIT(25)
> >> +#define GPIO44_FLASH_MODE_CFG			BIT(24)
> >> +#define GPIO43_FLASH_MODE_CFG			BIT(23)
> >> +#define GPIO42_FLASH_MODE_CFG			BIT(22)
> >> +#define GPIO41_FLASH_MODE_CFG			BIT(21)
> >> +#define GPIO40_FLASH_MODE_CFG			BIT(20)
> >> +#define GPIO39_FLASH_MODE_CFG			BIT(19)
> >> +#define GPIO38_FLASH_MODE_CFG			BIT(18)
> >> +#define GPIO37_FLASH_MODE_CFG			BIT(17)
> >> +#define GPIO36_FLASH_MODE_CFG			BIT(16)
> >> +#define GPIO31_FLASH_MODE_CFG			BIT(15)
> >> +#define GPIO30_FLASH_MODE_CFG			BIT(14)
> >> +#define GPIO29_FLASH_MODE_CFG			BIT(13)
> >> +#define GPIO28_FLASH_MODE_CFG			BIT(12)
> >> +#define GPIO27_FLASH_MODE_CFG			BIT(11)
> >> +#define GPIO26_FLASH_MODE_CFG			BIT(10)
> >> +#define GPIO25_FLASH_MODE_CFG			BIT(9)
> >> +#define GPIO24_FLASH_MODE_CFG			BIT(8)
> >> +#define GPIO23_FLASH_MODE_CFG			BIT(7)
> >> +#define GPIO22_FLASH_MODE_CFG			BIT(6)
> >> +#define GPIO21_FLASH_MODE_CFG			BIT(5)
> >> +#define GPIO20_FLASH_MODE_CFG			BIT(4)
> >> +#define GPIO19_FLASH_MODE_CFG			BIT(3)
> >> +#define GPIO18_FLASH_MODE_CFG			BIT(2)
> >> +#define GPIO17_FLASH_MODE_CFG			BIT(1)
> >> +#define GPIO16_FLASH_MODE_CFG			BIT(0)
> >> +
> >> +#define AIROHA_PINCTRL_GPIO(gpio, mux_val)			\
> >> +	{							\
> >> +		.name = (gpio),					\
> >> +		.regmap[0] = {					\
> >> +			AIROHA_FUNC_MUX,			\
> >> +			REG_GPIO_PON_MODE,			\
> >> +			(mux_val),				\
> >> +			(mux_val)				\
> >> +		},						\
> >> +		.regmap_size = 1,				\
> >> +	}
> >> +
> >> +#define AIROHA_PINCTRL_GPIO_EXT(gpio, mux_val, smux_val)	\
> >> +	{							\
> >> +		.name = (gpio),					\
> >> +		.regmap[0] = {					\
> >> +			AIROHA_FUNC_PWM_EXT_MUX,		\
> >> +			REG_GPIO_FLASH_MODE_CFG_EXT,		\
> >> +			(mux_val),				\
> >> +			0					\
> >> +		},						\
> >> +		.regmap[1] = {					\
> >> +			AIROHA_FUNC_MUX,			\
> >> +			REG_GPIO_PON_MODE,			\
> >> +			(smux_val),				\
> >> +			(smux_val)				\
> >> +		},						\
> >> +		.regmap_size = 2,				\
> >> +	}
> >> +
> >> +/* PWM */
> >> +#define AIROHA_PINCTRL_PWM(gpio, mux_val)			\
> >> +	{							\
> >> +		.name = (gpio),					\
> >> +		.regmap[0] = {					\
> >> +			AIROHA_FUNC_PWM_MUX,			\
> >> +			REG_GPIO_FLASH_MODE_CFG,		\
> >> +			(mux_val),				\
> >> +			(mux_val)				\
> >> +		},						\
> >> +		.regmap_size = 1,				\
> >> +	}
> >> +
> >> +#define AIROHA_PINCTRL_PWM_EXT(gpio, mux_val)			\
> >> +	{							\
> >> +		.name = (gpio),					\
> >> +		.regmap[0] = {					\
> >> +			AIROHA_FUNC_PWM_EXT_MUX,		\
> >> +			REG_GPIO_FLASH_MODE_CFG_EXT,		\
> >> +			(mux_val),				\
> >> +			(mux_val)				\
> >> +		},						\
> >> +		.regmap_size = 1,				\
> >> +	}
> >> +
> >> +#define AIROHA_PINCTRL_PWM_EXT_SEC(gpio, mux_val, smux_val)	\
> >> +	{							\
> >> +		.name = (gpio),					\
> >> +		.regmap[0] = {					\
> >> +			AIROHA_FUNC_PWM_EXT_MUX,		\
> >> +			REG_GPIO_FLASH_MODE_CFG_EXT,		\
> >> +			(mux_val),				\
> >> +			(mux_val)				\
> >> +		},						\
> >> +		.regmap[1] = {					\
> >> +			AIROHA_FUNC_MUX,			\
> >> +			REG_GPIO_PON_MODE,			\
> >> +			(smux_val),				\
> >> +			(smux_val)				\
> >> +		},						\
> >> +		.regmap_size = 2,				\
> >> +	}
> >> +
> >> +#define AIROHA_PINCTRL_PHY_LED0(gpio, mux_val, map_mask, map_val)	\
> >> +	{								\
> >> +		.name = (gpio),						\
> >> +		.regmap[0] = {						\
> >> +			AIROHA_FUNC_MUX,				\
> >> +			REG_GPIO_2ND_I2C_MODE,				\
> >> +			(mux_val),					\
> >> +			(mux_val),					\
> >> +		},							\
> >> +		.regmap[1] = {						\
> >> +			AIROHA_FUNC_MUX,				\
> >> +			REG_LAN_LED0_MAPPING,				\
> >> +			(map_mask),					\
> >> +			(map_val),					\
> >> +		},							\
> >> +		.regmap_size = 2,					\
> >> +	}
> >> +
> >> +#define AIROHA_PINCTRL_PHY_LED1(gpio, mux_val, map_mask, map_val)	\
> >> +	{								\
> >> +		.name = (gpio),						\
> >> +		.regmap[0] = {						\
> >> +			AIROHA_FUNC_MUX,				\
> >> +			REG_GPIO_2ND_I2C_MODE,				\
> >> +			(mux_val),					\
> >> +			(mux_val),					\
> >> +		},							\
> >> +		.regmap[1] = {						\
> >> +			AIROHA_FUNC_MUX,				\
> >> +			REG_LAN_LED1_MAPPING,				\
> >> +			(map_mask),					\
> >> +			(map_val),					\
> >> +		},							\
> >> +		.regmap_size = 2,					\
> >> +	}
> >> +
> >> +static struct pinctrl_pin_desc en7581_pinctrl_pins[] = {
> >> +	PINCTRL_PIN(0, "uart1_txd"),
> >> +	PINCTRL_PIN(1, "uart1_rxd"),
> >> +	PINCTRL_PIN(2, "i2c_scl"),
> >> +	PINCTRL_PIN(3, "i2c_sda"),
> >> +	PINCTRL_PIN(4, "spi_cs0"),
> >> +	PINCTRL_PIN(5, "spi_clk"),
> >> +	PINCTRL_PIN(6, "spi_mosi"),
> >> +	PINCTRL_PIN(7, "spi_miso"),
> >> +	PINCTRL_PIN(13, "gpio0"),
> >> +	PINCTRL_PIN(14, "gpio1"),
> >> +	PINCTRL_PIN(15, "gpio2"),
> >> +	PINCTRL_PIN(16, "gpio3"),
> >> +	PINCTRL_PIN(17, "gpio4"),
> >> +	PINCTRL_PIN(18, "gpio5"),
> >> +	PINCTRL_PIN(19, "gpio6"),
> >> +	PINCTRL_PIN(20, "gpio7"),
> >> +	PINCTRL_PIN(21, "gpio8"),
> >> +	PINCTRL_PIN(22, "gpio9"),
> >> +	PINCTRL_PIN(23, "gpio10"),
> >> +	PINCTRL_PIN(24, "gpio11"),
> >> +	PINCTRL_PIN(25, "gpio12"),
> >> +	PINCTRL_PIN(26, "gpio13"),
> >> +	PINCTRL_PIN(27, "gpio14"),
> >> +	PINCTRL_PIN(28, "gpio15"),
> >> +	PINCTRL_PIN(29, "gpio16"),
> >> +	PINCTRL_PIN(30, "gpio17"),
> >> +	PINCTRL_PIN(31, "gpio18"),
> >> +	PINCTRL_PIN(32, "gpio19"),
> >> +	PINCTRL_PIN(33, "gpio20"),
> >> +	PINCTRL_PIN(34, "gpio21"),
> >> +	PINCTRL_PIN(35, "gpio22"),
> >> +	PINCTRL_PIN(36, "gpio23"),
> >> +	PINCTRL_PIN(37, "gpio24"),
> >> +	PINCTRL_PIN(38, "gpio25"),
> >> +	PINCTRL_PIN(39, "gpio26"),
> >> +	PINCTRL_PIN(40, "gpio27"),
> >> +	PINCTRL_PIN(41, "gpio28"),
> >> +	PINCTRL_PIN(42, "gpio29"),
> >> +	PINCTRL_PIN(43, "gpio30"),
> >> +	PINCTRL_PIN(44, "gpio31"),
> >> +	PINCTRL_PIN(45, "gpio32"),
> >> +	PINCTRL_PIN(46, "gpio33"),
> >> +	PINCTRL_PIN(47, "gpio34"),
> >> +	PINCTRL_PIN(48, "gpio35"),
> >> +	PINCTRL_PIN(49, "gpio36"),
> >> +	PINCTRL_PIN(50, "gpio37"),
> >> +	PINCTRL_PIN(51, "gpio38"),
> >> +	PINCTRL_PIN(52, "gpio39"),
> >> +	PINCTRL_PIN(53, "gpio40"),
> >> +	PINCTRL_PIN(54, "gpio41"),
> >> +	PINCTRL_PIN(55, "gpio42"),
> >> +	PINCTRL_PIN(56, "gpio43"),
> >> +	PINCTRL_PIN(57, "gpio44"),
> >> +	PINCTRL_PIN(58, "gpio45"),
> >> +	PINCTRL_PIN(59, "gpio46"),
> >> +	PINCTRL_PIN(60, "pcie_reset0"),
> >> +	PINCTRL_PIN(61, "pcie_reset1"),
> >> +	PINCTRL_PIN(62, "pcie_reset2"),
> >> +};
> >> +
> >> +static const int en7581_pon_pins[] = { 49, 50, 51, 52, 53, 54 };
> >> +static const int en7581_pon_tod_1pps_pins[] = { 46 };
> >> +static const int en7581_gsw_tod_1pps_pins[] = { 46 };
> >> +static const int en7581_sipo_pins[] = { 16, 17 };
> >> +static const int en7581_sipo_rclk_pins[] = { 16, 17, 43 };
> >> +static const int en7581_mdio_pins[] = { 14, 15 };
> >> +static const int en7581_uart2_pins[] = { 48, 55 };
> >> +static const int en7581_uart2_cts_rts_pins[] = { 46, 47 };
> >> +static const int en7581_hsuart_pins[] = { 28, 29 };
> >> +static const int en7581_hsuart_cts_rts_pins[] = { 26, 27 };
> >> +static const int en7581_uart4_pins[] = { 38, 39 };
> >> +static const int en7581_uart5_pins[] = { 18, 19 };
> >> +static const int en7581_i2c0_pins[] = { 2, 3 };
> >> +static const int en7581_i2c1_pins[] = { 14, 15 };
> >> +static const int en7581_jtag_udi_pins[] = { 16, 17, 18, 19, 20 };
> >> +static const int en7581_jtag_dfd_pins[] = { 16, 17, 18, 19, 20 };
> >> +static const int en7581_i2s_pins[] = { 26, 27, 28, 29 };
> >> +static const int en7581_pcm1_pins[] = { 22, 23, 24, 25 };
> >> +static const int en7581_pcm2_pins[] = { 18, 19, 20, 21 };
> >> +static const int en7581_spi_quad_pins[] = { 32, 33 };
> >> +static const int en7581_spi_pins[] = { 4, 5, 6, 7 };
> >> +static const int en7581_spi_cs1_pins[] = { 34 };
> >> +static const int en7581_pcm_spi_pins[] = { 18, 19, 20, 21, 22, 23, 24, 25 };
> >> +static const int en7581_pcm_spi_int_pins[] = { 14 };
> >> +static const int en7581_pcm_spi_rst_pins[] = { 15 };
> >> +static const int en7581_pcm_spi_cs1_pins[] = { 43 };
> >> +static const int en7581_pcm_spi_cs2_pins[] = { 40 };
> >> +static const int en7581_pcm_spi_cs2_p128_pins[] = { 40 };
> >> +static const int en7581_pcm_spi_cs2_p156_pins[] = { 40 };
> >> +static const int en7581_pcm_spi_cs3_pins[] = { 41 };
> >> +static const int en7581_pcm_spi_cs4_pins[] = { 42 };
> >> +static const int en7581_emmc_pins[] = {
> >> +	4, 5, 6, 30, 31, 32, 33, 34, 35, 36, 37
> >> +};
> >> +static const int en7581_pnand_pins[] = {
> >> +	4, 5, 6, 7, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42
> >> +};
> >> +static const int en7581_gpio0_pins[] = { 13 };
> >> +static const int en7581_gpio1_pins[] = { 14 };
> >> +static const int en7581_gpio2_pins[] = { 15 };
> >> +static const int en7581_gpio3_pins[] = { 16 };
> >> +static const int en7581_gpio4_pins[] = { 17 };
> >> +static const int en7581_gpio5_pins[] = { 18 };
> >> +static const int en7581_gpio6_pins[] = { 19 };
> >> +static const int en7581_gpio7_pins[] = { 20 };
> >> +static const int en7581_gpio8_pins[] = { 21 };
> >> +static const int en7581_gpio9_pins[] = { 22 };
> >> +static const int en7581_gpio10_pins[] = { 23 };
> >> +static const int en7581_gpio11_pins[] = { 24 };
> >> +static const int en7581_gpio12_pins[] = { 25 };
> >> +static const int en7581_gpio13_pins[] = { 26 };
> >> +static const int en7581_gpio14_pins[] = { 27 };
> >> +static const int en7581_gpio15_pins[] = { 28 };
> >> +static const int en7581_gpio16_pins[] = { 29 };
> >> +static const int en7581_gpio17_pins[] = { 30 };
> >> +static const int en7581_gpio18_pins[] = { 31 };
> >> +static const int en7581_gpio19_pins[] = { 32 };
> >> +static const int en7581_gpio20_pins[] = { 33 };
> >> +static const int en7581_gpio21_pins[] = { 34 };
> >> +static const int en7581_gpio22_pins[] = { 35 };
> >> +static const int en7581_gpio23_pins[] = { 36 };
> >> +static const int en7581_gpio24_pins[] = { 37 };
> >> +static const int en7581_gpio25_pins[] = { 38 };
> >> +static const int en7581_gpio26_pins[] = { 39 };
> >> +static const int en7581_gpio27_pins[] = { 40 };
> >> +static const int en7581_gpio28_pins[] = { 41 };
> >> +static const int en7581_gpio29_pins[] = { 42 };
> >> +static const int en7581_gpio30_pins[] = { 43 };
> >> +static const int en7581_gpio31_pins[] = { 44 };
> >> +static const int en7581_gpio32_pins[] = { 45 };
> >> +static const int en7581_gpio33_pins[] = { 46 };
> >> +static const int en7581_gpio34_pins[] = { 47 };
> >> +static const int en7581_gpio35_pins[] = { 48 };
> >> +static const int en7581_gpio36_pins[] = { 49 };
> >> +static const int en7581_gpio37_pins[] = { 50 };
> >> +static const int en7581_gpio38_pins[] = { 51 };
> >> +static const int en7581_gpio39_pins[] = { 52 };
> >> +static const int en7581_gpio40_pins[] = { 53 };
> >> +static const int en7581_gpio41_pins[] = { 54 };
> >> +static const int en7581_gpio42_pins[] = { 55 };
> >> +static const int en7581_gpio43_pins[] = { 56 };
> >> +static const int en7581_gpio44_pins[] = { 57 };
> >> +static const int en7581_gpio45_pins[] = { 58 };
> >> +static const int en7581_gpio46_pins[] = { 59 };
> >> +static const int en7581_gpio47_pins[] = { 60 };
> >> +static const int en7581_gpio48_pins[] = { 61 };
> >> +static const int en7581_gpio49_pins[] = { 62 };
> >> +static const int en7581_pcie_reset0_pins[] = { 60 };
> >> +static const int en7581_pcie_reset1_pins[] = { 61 };
> >> +static const int en7581_pcie_reset2_pins[] = { 62 };
> >> +
> >> +static const struct pingroup en7581_pinctrl_groups[] = {
> >> +	PINCTRL_PIN_GROUP("pon", en7581_pon),
> >> +	PINCTRL_PIN_GROUP("pon_tod_1pps", en7581_pon_tod_1pps),
> >> +	PINCTRL_PIN_GROUP("gsw_tod_1pps", en7581_gsw_tod_1pps),
> >> +	PINCTRL_PIN_GROUP("sipo", en7581_sipo),
> >> +	PINCTRL_PIN_GROUP("sipo_rclk", en7581_sipo_rclk),
> >> +	PINCTRL_PIN_GROUP("mdio", en7581_mdio),
> >> +	PINCTRL_PIN_GROUP("uart2", en7581_uart2),
> >> +	PINCTRL_PIN_GROUP("uart2_cts_rts", en7581_uart2_cts_rts),
> >> +	PINCTRL_PIN_GROUP("hsuart", en7581_hsuart),
> >> +	PINCTRL_PIN_GROUP("hsuart_cts_rts", en7581_hsuart_cts_rts),
> >> +	PINCTRL_PIN_GROUP("uart4", en7581_uart4),
> >> +	PINCTRL_PIN_GROUP("uart5", en7581_uart5),
> >> +	PINCTRL_PIN_GROUP("i2c0", en7581_i2c0),
> >> +	PINCTRL_PIN_GROUP("i2c1", en7581_i2c1),
> >> +	PINCTRL_PIN_GROUP("jtag_udi", en7581_jtag_udi),
> >> +	PINCTRL_PIN_GROUP("jtag_dfd", en7581_jtag_dfd),
> >> +	PINCTRL_PIN_GROUP("i2s", en7581_i2s),
> >> +	PINCTRL_PIN_GROUP("pcm1", en7581_pcm1),
> >> +	PINCTRL_PIN_GROUP("pcm2", en7581_pcm2),
> >> +	PINCTRL_PIN_GROUP("spi", en7581_spi),
> >> +	PINCTRL_PIN_GROUP("spi_quad", en7581_spi_quad),
> >> +	PINCTRL_PIN_GROUP("spi_cs1", en7581_spi_cs1),
> >> +	PINCTRL_PIN_GROUP("pcm_spi", en7581_pcm_spi),
> >> +	PINCTRL_PIN_GROUP("pcm_spi_int", en7581_pcm_spi_int),
> >> +	PINCTRL_PIN_GROUP("pcm_spi_rst", en7581_pcm_spi_rst),
> >> +	PINCTRL_PIN_GROUP("pcm_spi_cs1", en7581_pcm_spi_cs1),
> >> +	PINCTRL_PIN_GROUP("pcm_spi_cs2_p128", en7581_pcm_spi_cs2_p128),
> >> +	PINCTRL_PIN_GROUP("pcm_spi_cs2_p156", en7581_pcm_spi_cs2_p156),
> >> +	PINCTRL_PIN_GROUP("pcm_spi_cs2", en7581_pcm_spi_cs2),
> >> +	PINCTRL_PIN_GROUP("pcm_spi_cs3", en7581_pcm_spi_cs3),
> >> +	PINCTRL_PIN_GROUP("pcm_spi_cs4", en7581_pcm_spi_cs4),
> >> +	PINCTRL_PIN_GROUP("emmc", en7581_emmc),
> >> +	PINCTRL_PIN_GROUP("pnand", en7581_pnand),
> >> +	PINCTRL_PIN_GROUP("gpio0", en7581_gpio0),
> >> +	PINCTRL_PIN_GROUP("gpio1", en7581_gpio1),
> >> +	PINCTRL_PIN_GROUP("gpio2", en7581_gpio2),
> >> +	PINCTRL_PIN_GROUP("gpio3", en7581_gpio3),
> >> +	PINCTRL_PIN_GROUP("gpio4", en7581_gpio4),
> >> +	PINCTRL_PIN_GROUP("gpio5", en7581_gpio5),
> >> +	PINCTRL_PIN_GROUP("gpio6", en7581_gpio6),
> >> +	PINCTRL_PIN_GROUP("gpio7", en7581_gpio7),
> >> +	PINCTRL_PIN_GROUP("gpio8", en7581_gpio8),
> >> +	PINCTRL_PIN_GROUP("gpio9", en7581_gpio9),
> >> +	PINCTRL_PIN_GROUP("gpio10", en7581_gpio10),
> >> +	PINCTRL_PIN_GROUP("gpio11", en7581_gpio11),
> >> +	PINCTRL_PIN_GROUP("gpio12", en7581_gpio12),
> >> +	PINCTRL_PIN_GROUP("gpio13", en7581_gpio13),
> >> +	PINCTRL_PIN_GROUP("gpio14", en7581_gpio14),
> >> +	PINCTRL_PIN_GROUP("gpio15", en7581_gpio15),
> >> +	PINCTRL_PIN_GROUP("gpio16", en7581_gpio16),
> >> +	PINCTRL_PIN_GROUP("gpio17", en7581_gpio17),
> >> +	PINCTRL_PIN_GROUP("gpio18", en7581_gpio18),
> >> +	PINCTRL_PIN_GROUP("gpio19", en7581_gpio19),
> >> +	PINCTRL_PIN_GROUP("gpio20", en7581_gpio20),
> >> +	PINCTRL_PIN_GROUP("gpio21", en7581_gpio21),
> >> +	PINCTRL_PIN_GROUP("gpio22", en7581_gpio22),
> >> +	PINCTRL_PIN_GROUP("gpio23", en7581_gpio23),
> >> +	PINCTRL_PIN_GROUP("gpio24", en7581_gpio24),
> >> +	PINCTRL_PIN_GROUP("gpio25", en7581_gpio25),
> >> +	PINCTRL_PIN_GROUP("gpio26", en7581_gpio26),
> >> +	PINCTRL_PIN_GROUP("gpio27", en7581_gpio27),
> >> +	PINCTRL_PIN_GROUP("gpio28", en7581_gpio28),
> >> +	PINCTRL_PIN_GROUP("gpio29", en7581_gpio29),
> >> +	PINCTRL_PIN_GROUP("gpio30", en7581_gpio30),
> >> +	PINCTRL_PIN_GROUP("gpio31", en7581_gpio31),
> >> +	PINCTRL_PIN_GROUP("gpio32", en7581_gpio32),
> >> +	PINCTRL_PIN_GROUP("gpio33", en7581_gpio33),
> >> +	PINCTRL_PIN_GROUP("gpio34", en7581_gpio34),
> >> +	PINCTRL_PIN_GROUP("gpio35", en7581_gpio35),
> >> +	PINCTRL_PIN_GROUP("gpio36", en7581_gpio36),
> >> +	PINCTRL_PIN_GROUP("gpio37", en7581_gpio37),
> >> +	PINCTRL_PIN_GROUP("gpio38", en7581_gpio38),
> >> +	PINCTRL_PIN_GROUP("gpio39", en7581_gpio39),
> >> +	PINCTRL_PIN_GROUP("gpio40", en7581_gpio40),
> >> +	PINCTRL_PIN_GROUP("gpio41", en7581_gpio41),
> >> +	PINCTRL_PIN_GROUP("gpio42", en7581_gpio42),
> >> +	PINCTRL_PIN_GROUP("gpio43", en7581_gpio43),
> >> +	PINCTRL_PIN_GROUP("gpio44", en7581_gpio44),
> >> +	PINCTRL_PIN_GROUP("gpio45", en7581_gpio45),
> >> +	PINCTRL_PIN_GROUP("gpio46", en7581_gpio46),
> >> +	PINCTRL_PIN_GROUP("gpio47", en7581_gpio47),
> >> +	PINCTRL_PIN_GROUP("gpio48", en7581_gpio48),
> >> +	PINCTRL_PIN_GROUP("gpio49", en7581_gpio49),
> >> +	PINCTRL_PIN_GROUP("pcie_reset0", en7581_pcie_reset0),
> >> +	PINCTRL_PIN_GROUP("pcie_reset1", en7581_pcie_reset1),
> >> +	PINCTRL_PIN_GROUP("pcie_reset2", en7581_pcie_reset2),
> >> +};
> >> +
> >> +static const char *const pon_groups[] = { "pon" };
> >> +static const char *const tod_1pps_groups[] = {
> >> +	"pon_tod_1pps", "gsw_tod_1pps"
> >> +};
> >> +static const char *const sipo_groups[] = { "sipo", "sipo_rclk" };
> >> +static const char *const mdio_groups[] = { "mdio" };
> >> +static const char *const uart_groups[] = {
> >> +	"uart2", "uart2_cts_rts", "hsuart", "hsuart_cts_rts",
> >> +	"uart4", "uart5"
> >> +};
> >> +static const char *const i2c_groups[] = { "i2c1" };
> >> +static const char *const jtag_groups[] = { "jtag_udi", "jtag_dfd" };
> >> +static const char *const pcm_groups[] = { "pcm1", "pcm2" };
> >> +static const char *const spi_groups[] = { "spi_quad", "spi_cs1" };
> >> +static const char *const pcm_spi_groups[] = {
> >> +	"pcm_spi", "pcm_spi_int", "pcm_spi_rst", "pcm_spi_cs1",
> >> +	"pcm_spi_cs2_p156", "pcm_spi_cs2_p128", "pcm_spi_cs3",
> >> +	"pcm_spi_cs4"
> >> +};
> >> +static const char *const i2s_groups[] = { "i2s" };
> >> +static const char *const emmc_groups[] = { "emmc" };
> >> +static const char *const pnand_groups[] = { "pnand" };
> >> +static const char *const gpio_groups[] = { "gpio47", "gpio48", "gpio49" };
> >> +static const char *const pcie_reset_groups[] = {
> >> +	"pcie_reset0", "pcie_reset1", "pcie_reset2"
> >> +};
> >> +static const char *const pwm_groups[] = {
> >> +	"gpio0",  "gpio1",  "gpio2",  "gpio3",  "gpio4",  "gpio5",
> >> +	"gpio6",  "gpio7",  "gpio8",  "gpio9",  "gpio10", "gpio11",
> >> +	"gpio12", "gpio13", "gpio14", "gpio15", "gpio16", "gpio17",
> >> +	"gpio18", "gpio19", "gpio20", "gpio21", "gpio22", "gpio23",
> >> +	"gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29",
> >> +	"gpio30", "gpio31", "gpio36", "gpio37", "gpio38", "gpio39",
> >> +	"gpio40", "gpio41", "gpio42", "gpio43", "gpio44", "gpio45",
> >> +	"gpio46", "gpio47", "gpio48", "gpio49"
> >> +};
> >> +static const char *const phy1_led0_groups[] = {
> >> +	"gpio33", "gpio34", "gpio35", "gpio42"
> >> +};
> >> +static const char *const phy2_led0_groups[] = {
> >> +	"gpio33", "gpio34", "gpio35", "gpio42"
> >> +};
> >> +static const char *const phy3_led0_groups[] = {
> >> +	"gpio33", "gpio34", "gpio35", "gpio42"
> >> +};
> >> +static const char *const phy4_led0_groups[] = {
> >> +	"gpio33", "gpio34", "gpio35", "gpio42"
> >> +};
> >> +static const char *const phy1_led1_groups[] = {
> >> +	"gpio43", "gpio44", "gpio45", "gpio46"
> >> +};
> >> +static const char *const phy2_led1_groups[] = {
> >> +	"gpio43", "gpio44", "gpio45", "gpio46"
> >> +};
> >> +static const char *const phy3_led1_groups[] = {
> >> +	"gpio43", "gpio44", "gpio45", "gpio46"
> >> +};
> >> +static const char *const phy4_led1_groups[] = {
> >> +	"gpio43", "gpio44", "gpio45", "gpio46"
> >> +};
> >> +
> >> +static const struct airoha_pinctrl_func_group pon_func_group[] = {
> >> +	{
> >> +		.name = "pon",
> >> +		.regmap[0] = {
> >> +			AIROHA_FUNC_MUX,
> >> +			REG_GPIO_PON_MODE,
> >> +			GPIO_PON_MODE_MASK,
> >> +			GPIO_PON_MODE_MASK
> >> +		},
> >> +		.regmap_size = 1,
> >> +	},
> >> +};
> >> +
> >> +static const struct airoha_pinctrl_func_group tod_1pps_func_group[] = {
> >> +	{
> >> +		.name = "pon_tod_1pps",
> >> +		.regmap[0] = {
> >> +			AIROHA_FUNC_MUX,
> >> +			REG_GPIO_2ND_I2C_MODE,
> >> +			PON_TOD_1PPS_MODE_MASK,
> >> +			PON_TOD_1PPS_MODE_MASK
> >> +		},
> >> +		.regmap_size = 1,
> >> +	}, {
> >> +		.name = "gsw_tod_1pps",
> >> +		.regmap[0] = {
> >> +			AIROHA_FUNC_MUX,
> >> +			REG_GPIO_2ND_I2C_MODE,
> >> +			GSW_TOD_1PPS_MODE_MASK,
> >> +			GSW_TOD_1PPS_MODE_MASK
> >> +		},
> >> +		.regmap_size = 1,
> >> +	},
> >> +};
> >> +
> >> +static const struct airoha_pinctrl_func_group sipo_func_group[] = {
> >> +	{
> >> +		.name = "sipo",
> >> +		.regmap[0] = {
> >> +			AIROHA_FUNC_MUX,
> >> +			REG_GPIO_PON_MODE,
> >> +			GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK,
> >> +			GPIO_SIPO_MODE_MASK
> >> +		},
> >> +		.regmap_size = 1,
> >> +	}, {
> >> +		.name = "sipo_rclk",
> >> +		.regmap[0] = {
> >> +			AIROHA_FUNC_MUX,
> >> +			REG_GPIO_PON_MODE,
> >> +			GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK,
> >> +			GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK
> >> +		},
> >> +		.regmap_size = 1,
> >> +	},
> >> +};
> >> +
> >> +static const struct airoha_pinctrl_func_group mdio_func_group[] = {
> >> +	{
> >> +		.name = "mdio",
> >> +		.regmap[0] = {
> >> +			AIROHA_FUNC_MUX,
> >> +			REG_GPIO_2ND_I2C_MODE,
> >> +			GPIO_MDC_IO_MASTER_MODE_MASK,
> >> +			GPIO_MDC_IO_MASTER_MODE_MASK
> >> +		},
> >> +		.regmap[1] = {
> >> +			AIROHA_FUNC_MUX,
> >> +			REG_FORCE_GPIO_EN,
> >> +			FORCE_GPIO_EN(1) | FORCE_GPIO_EN(2),
> >> +			FORCE_GPIO_EN(1) | FORCE_GPIO_EN(2)
> >> +		},
> >> +		.regmap_size = 2,
> >> +	},
> >> +};
> >> +
> >> +static const struct airoha_pinctrl_func_group uart_func_group[] = {
> >> +	{
> >> +		.name = "uart2",
> >> +		.regmap[0] = {
> >> +			AIROHA_FUNC_MUX,
> >> +			REG_GPIO_PON_MODE,
> >> +			GPIO_UART2_MODE_MASK,
> >> +			GPIO_UART2_MODE_MASK
> >> +		},
> >> +		.regmap_size = 1,
> >> +	}, {
> >> +		.name = "uart2_cts_rts",
> >> +		.regmap[0] = {
> >> +			AIROHA_FUNC_MUX,
> >> +			REG_GPIO_PON_MODE,
> >> +			GPIO_UART2_MODE_MASK | GPIO_UART2_CTS_RTS_MODE_MASK,
> >> +			GPIO_UART2_MODE_MASK | GPIO_UART2_CTS_RTS_MODE_MASK
> >> +		},
> >> +		.regmap_size = 1,
> >> +	}, {
> >> +		.name = "hsuart",
> >> +		.regmap[0] = {
> >> +			AIROHA_FUNC_MUX,
> >> +			REG_GPIO_PON_MODE,
> >> +			GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK,
> >> +			GPIO_HSUART_MODE_MASK
> >> +		},
> >> +		.regmap_size = 1,
> >> +	},
> >> +	{
> >> +		.name = "hsuart_cts_rts",
> >> +		.regmap[0] = {
> >> +			AIROHA_FUNC_MUX,
> >> +			REG_GPIO_PON_MODE,
> >> +			GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK,
> >> +			GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK
> >> +		},
> >> +		.regmap_size = 1,
> >> +	}, {
> >> +		.name = "uart4",
> >> +		.regmap[0] = {
> >> +			AIROHA_FUNC_MUX,
> >> +			REG_GPIO_PON_MODE,
> >> +			GPIO_UART4_MODE_MASK,
> >> +			GPIO_UART4_MODE_MASK
> >> +		},
> >> +		.regmap_size = 1,
> >> +	}, {
> >> +		.name = "uart5",
> >> +		.regmap[0] = {
> >> +			AIROHA_FUNC_MUX,
> >> +			REG_GPIO_PON_MODE,
> >> +			GPIO_UART5_MODE_MASK,
> >> +			GPIO_UART5_MODE_MASK
> >> +		},
> >> +		.regmap_size = 1,
> >> +	},
> >> +};
> >> +
> >> +static const struct airoha_pinctrl_func_group i2c_func_group[] = {
> >> +	{
> >> +		.name = "i2c1",
> >> +		.regmap[0] = {
> >> +			AIROHA_FUNC_MUX,
> >> +			REG_GPIO_2ND_I2C_MODE,
> >> +			GPIO_2ND_I2C_MODE_MASK,
> >> +			GPIO_2ND_I2C_MODE_MASK
> >> +		},
> >> +		.regmap_size = 1,
> >> +	},
> >> +};
> >> +
> >> +static const struct airoha_pinctrl_func_group jtag_func_group[] = {
> >> +	{
> >> +		.name = "jtag_udi",
> >> +		.regmap[0] = {
> >> +			AIROHA_FUNC_MUX,
> >> +			REG_NPU_UART_EN,
> >> +			JTAG_UDI_EN_MASK,
> >> +			JTAG_UDI_EN_MASK
> >> +		},
> >> +		.regmap_size = 1,
> >> +	}, {
> >> +		.name = "jtag_dfd",
> >> +		.regmap[0] = {
> >> +			AIROHA_FUNC_MUX,
> >> +			REG_NPU_UART_EN,
> >> +			JTAG_DFD_EN_MASK,
> >> +			JTAG_DFD_EN_MASK
> >> +		},
> >> +		.regmap_size = 1,
> >> +	},
> >> +};
> >> +
> >> +static const struct airoha_pinctrl_func_group pcm_func_group[] = {
> >> +	{
> >> +		.name = "pcm1",
> >> +		.regmap[0] = {
> >> +			AIROHA_FUNC_MUX,
> >> +			REG_GPIO_SPI_CS1_MODE,
> >> +			GPIO_PCM1_MODE_MASK,
> >> +			GPIO_PCM1_MODE_MASK
> >> +		},
> >> +		.regmap_size = 1,
> >> +	}, {
> >> +		.name = "pcm2",
> >> +		.regmap[0] = {
> >> +			AIROHA_FUNC_MUX,
> >> +			REG_GPIO_SPI_CS1_MODE,
> >> +			GPIO_PCM2_MODE_MASK,
> >> +			GPIO_PCM2_MODE_MASK
> >> +		},
> >> +		.regmap_size = 1,
> >> +	},
> >> +};
> >> +
> >> +static const struct airoha_pinctrl_func_group spi_func_group[] = {
> >> +	{
> >> +		.name = "spi_quad",
> >> +		.regmap[0] = {
> >> +			AIROHA_FUNC_MUX,
> >> +			REG_GPIO_SPI_CS1_MODE,
> >> +			GPIO_SPI_QUAD_MODE_MASK,
> >> +			GPIO_SPI_QUAD_MODE_MASK
> >> +		},
> >> +		.regmap_size = 1,
> >> +	}, {
> >> +		.name = "spi_cs1",
> >> +		.regmap[0] = {
> >> +			AIROHA_FUNC_MUX,
> >> +			REG_GPIO_SPI_CS1_MODE,
> >> +			GPIO_SPI_CS1_MODE_MASK,
> >> +			GPIO_SPI_CS1_MODE_MASK
> >> +		},
> >> +		.regmap_size = 1,
> >> +	}, {
> >> +		.name = "spi_cs2",
> >> +		.regmap[0] = {
> >> +			AIROHA_FUNC_MUX,
> >> +			REG_GPIO_SPI_CS1_MODE,
> >> +			GPIO_SPI_CS2_MODE_MASK,
> >> +			GPIO_SPI_CS2_MODE_MASK
> >> +		},
> >> +		.regmap_size = 1,
> >> +	}, {
> >> +		.name = "spi_cs3",
> >> +		.regmap[0] = {
> >> +			AIROHA_FUNC_MUX,
> >> +			REG_GPIO_SPI_CS1_MODE,
> >> +			GPIO_SPI_CS3_MODE_MASK,
> >> +			GPIO_SPI_CS3_MODE_MASK
> >> +		},
> >> +		.regmap_size = 1,
> >> +	}, {
> >> +		.name = "spi_cs4",
> >> +		.regmap[0] = {
> >> +			AIROHA_FUNC_MUX,
> >> +			REG_GPIO_SPI_CS1_MODE,
> >> +			GPIO_SPI_CS4_MODE_MASK,
> >> +			GPIO_SPI_CS4_MODE_MASK
> >> +		},
> >> +		.regmap_size = 1,
> >> +	},
> >> +};
> >> +
> >> +static const struct airoha_pinctrl_func_group pcm_spi_func_group[] = {
> >> +	{
> >> +		.name = "pcm_spi",
> >> +		.regmap[0] = {
> >> +			AIROHA_FUNC_MUX,
> >> +			REG_GPIO_SPI_CS1_MODE,
> >> +			GPIO_PCM_SPI_MODE_MASK,
> >> +			GPIO_PCM_SPI_MODE_MASK
> >> +		},
> >> +		.regmap_size = 1,
> >> +	}, {
> >> +		.name = "pcm_spi_int",
> >> +		.regmap[0] = {
> >> +			AIROHA_FUNC_MUX,
> >> +			REG_GPIO_SPI_CS1_MODE,
> >> +			GPIO_PCM_INT_MODE_MASK,
> >> +			GPIO_PCM_INT_MODE_MASK
> >> +		},
> >> +		.regmap_size = 1,
> >> +	}, {
> >> +		.name = "pcm_spi_rst",
> >> +		.regmap[0] = {
> >> +			AIROHA_FUNC_MUX,
> >> +			REG_GPIO_SPI_CS1_MODE,
> >> +			GPIO_PCM_RESET_MODE_MASK,
> >> +			GPIO_PCM_RESET_MODE_MASK
> >> +		},
> >> +		.regmap_size = 1,
> >> +	}, {
> >> +		.name = "pcm_spi_cs1",
> >> +		.regmap[0] = {
> >> +			AIROHA_FUNC_MUX,
> >> +			REG_GPIO_SPI_CS1_MODE,
> >> +			GPIO_PCM_SPI_CS1_MODE_MASK,
> >> +			GPIO_PCM_SPI_CS1_MODE_MASK
> >> +		},
> >> +		.regmap_size = 1,
> >> +	}, {
> >> +		.name = "pcm_spi_cs2_p128",
> >> +		.regmap[0] = {
> >> +			AIROHA_FUNC_MUX,
> >> +			REG_GPIO_SPI_CS1_MODE,
> >> +			GPIO_PCM_SPI_CS2_MODE_P128_MASK,
> >> +			GPIO_PCM_SPI_CS2_MODE_P128_MASK
> >> +		},
> >> +		.regmap_size = 1,
> >> +	}, {
> >> +		.name = "pcm_spi_cs2_p156",
> >> +		.regmap[0] = {
> >> +			AIROHA_FUNC_MUX,
> >> +			REG_GPIO_SPI_CS1_MODE,
> >> +			GPIO_PCM_SPI_CS2_MODE_P156_MASK,
> >> +			GPIO_PCM_SPI_CS2_MODE_P156_MASK
> >> +		},
> >> +		.regmap_size = 1,
> >> +	}, {
> >> +		.name = "pcm_spi_cs3",
> >> +		.regmap[0] = {
> >> +			AIROHA_FUNC_MUX,
> >> +			REG_GPIO_SPI_CS1_MODE,
> >> +			GPIO_PCM_SPI_CS3_MODE_MASK,
> >> +			GPIO_PCM_SPI_CS3_MODE_MASK
> >> +		},
> >> +		.regmap_size = 1,
> >> +	}, {
> >> +		.name = "pcm_spi_cs4",
> >> +		.regmap[0] = {
> >> +			AIROHA_FUNC_MUX,
> >> +			REG_GPIO_SPI_CS1_MODE,
> >> +			GPIO_PCM_SPI_CS4_MODE_MASK,
> >> +			GPIO_PCM_SPI_CS4_MODE_MASK
> >> +		},
> >> +		.regmap_size = 1,
> >> +	},
> >> +};
> >> +
> >> +static const struct airoha_pinctrl_func_group i2s_func_group[] = {
> >> +	{
> >> +		.name = "i2s",
> >> +		.regmap[0] = {
> >> +			AIROHA_FUNC_MUX,
> >> +			REG_GPIO_2ND_I2C_MODE,
> >> +			GPIO_I2S_MODE_MASK,
> >> +			GPIO_I2S_MODE_MASK
> >> +		},
> >> +		.regmap_size = 1,
> >> +	},
> >> +};
> >> +
> >> +static const struct airoha_pinctrl_func_group emmc_func_group[] = {
> >> +	{
> >> +		.name = "emmc",
> >> +		.regmap[0] = {
> >> +			AIROHA_FUNC_MUX,
> >> +			REG_GPIO_PON_MODE,
> >> +			GPIO_EMMC_MODE_MASK,
> >> +			GPIO_EMMC_MODE_MASK
> >> +		},
> >> +		.regmap_size = 1,
> >> +	},
> >> +};
> >> +
> >> +static const struct airoha_pinctrl_func_group pnand_func_group[] = {
> >> +	{
> >> +		.name = "pnand",
> >> +		.regmap[0] = {
> >> +			AIROHA_FUNC_MUX,
> >> +			REG_GPIO_PON_MODE,
> >> +			GPIO_PARALLEL_NAND_MODE_MASK,
> >> +			GPIO_PARALLEL_NAND_MODE_MASK
> >> +		},
> >> +		.regmap_size = 1,
> >> +	},
> >> +};
> >> +
> >> +static const struct airoha_pinctrl_func_group gpio_func_group[] = {
> >> +	AIROHA_PINCTRL_GPIO_EXT("gpio47", GPIO47_FLASH_MODE_CFG,
> >> +				GPIO_PCIE_RESET0_MASK),
> >> +	AIROHA_PINCTRL_GPIO_EXT("gpio48", GPIO48_FLASH_MODE_CFG,
> >> +				GPIO_PCIE_RESET1_MASK),
> >> +	AIROHA_PINCTRL_GPIO_EXT("gpio49", GPIO49_FLASH_MODE_CFG,
> >> +				GPIO_PCIE_RESET2_MASK),
> >> +};
> >> +
> >> +static const struct airoha_pinctrl_func_group pcie_reset_func_group[] = {
> >> +	{
> >> +		.name = "pcie_reset0",
> >> +		.regmap[0] = {
> >> +			AIROHA_FUNC_MUX,
> >> +			REG_GPIO_PON_MODE,
> >> +			GPIO_PCIE_RESET0_MASK,
> >> +			0
> >> +		},
> >> +		.regmap_size = 1,
> >> +	}, {
> >> +		.name = "pcie_reset1",
> >> +		.regmap[0] = {
> >> +			AIROHA_FUNC_MUX,
> >> +			REG_GPIO_PON_MODE,
> >> +			GPIO_PCIE_RESET1_MASK,
> >> +			0
> >> +		},
> >> +		.regmap_size = 1,
> >> +	}, {
> >> +		.name = "pcie_reset2",
> >> +		.regmap[0] = {
> >> +			AIROHA_FUNC_MUX,
> >> +			REG_GPIO_PON_MODE,
> >> +			GPIO_PCIE_RESET2_MASK,
> >> +			0
> >> +		},
> >> +		.regmap_size = 1,
> >> +	},
> >> +};
> >> +
> >> +static const struct airoha_pinctrl_func_group pwm_func_group[] = {
> >> +	AIROHA_PINCTRL_PWM("gpio0", GPIO0_FLASH_MODE_CFG),
> >> +	AIROHA_PINCTRL_PWM("gpio1", GPIO1_FLASH_MODE_CFG),
> >> +	AIROHA_PINCTRL_PWM("gpio2", GPIO2_FLASH_MODE_CFG),
> >> +	AIROHA_PINCTRL_PWM("gpio3", GPIO3_FLASH_MODE_CFG),
> >> +	AIROHA_PINCTRL_PWM("gpio4", GPIO4_FLASH_MODE_CFG),
> >> +	AIROHA_PINCTRL_PWM("gpio5", GPIO5_FLASH_MODE_CFG),
> >> +	AIROHA_PINCTRL_PWM("gpio6", GPIO6_FLASH_MODE_CFG),
> >> +	AIROHA_PINCTRL_PWM("gpio7", GPIO7_FLASH_MODE_CFG),
> >> +	AIROHA_PINCTRL_PWM("gpio8", GPIO8_FLASH_MODE_CFG),
> >> +	AIROHA_PINCTRL_PWM("gpio9", GPIO9_FLASH_MODE_CFG),
> >> +	AIROHA_PINCTRL_PWM("gpio10", GPIO10_FLASH_MODE_CFG),
> >> +	AIROHA_PINCTRL_PWM("gpio11", GPIO11_FLASH_MODE_CFG),
> >> +	AIROHA_PINCTRL_PWM("gpio12", GPIO12_FLASH_MODE_CFG),
> >> +	AIROHA_PINCTRL_PWM("gpio13", GPIO13_FLASH_MODE_CFG),
> >> +	AIROHA_PINCTRL_PWM("gpio14", GPIO14_FLASH_MODE_CFG),
> >> +	AIROHA_PINCTRL_PWM("gpio15", GPIO15_FLASH_MODE_CFG),
> >> +	AIROHA_PINCTRL_PWM_EXT("gpio16", GPIO16_FLASH_MODE_CFG),
> >> +	AIROHA_PINCTRL_PWM_EXT("gpio17", GPIO17_FLASH_MODE_CFG),
> >> +	AIROHA_PINCTRL_PWM_EXT("gpio18", GPIO18_FLASH_MODE_CFG),
> >> +	AIROHA_PINCTRL_PWM_EXT("gpio19", GPIO19_FLASH_MODE_CFG),
> >> +	AIROHA_PINCTRL_PWM_EXT("gpio20", GPIO20_FLASH_MODE_CFG),
> >> +	AIROHA_PINCTRL_PWM_EXT("gpio21", GPIO21_FLASH_MODE_CFG),
> >> +	AIROHA_PINCTRL_PWM_EXT("gpio22", GPIO22_FLASH_MODE_CFG),
> >> +	AIROHA_PINCTRL_PWM_EXT("gpio23", GPIO23_FLASH_MODE_CFG),
> >> +	AIROHA_PINCTRL_PWM_EXT("gpio24", GPIO24_FLASH_MODE_CFG),
> >> +	AIROHA_PINCTRL_PWM_EXT("gpio25", GPIO25_FLASH_MODE_CFG),
> >> +	AIROHA_PINCTRL_PWM_EXT("gpio26", GPIO26_FLASH_MODE_CFG),
> >> +	AIROHA_PINCTRL_PWM_EXT("gpio27", GPIO27_FLASH_MODE_CFG),
> >> +	AIROHA_PINCTRL_PWM_EXT("gpio28", GPIO28_FLASH_MODE_CFG),
> >> +	AIROHA_PINCTRL_PWM_EXT("gpio29", GPIO29_FLASH_MODE_CFG),
> >> +	AIROHA_PINCTRL_PWM_EXT("gpio30", GPIO30_FLASH_MODE_CFG),
> >> +	AIROHA_PINCTRL_PWM_EXT("gpio31", GPIO31_FLASH_MODE_CFG),
> >> +	AIROHA_PINCTRL_PWM_EXT("gpio36", GPIO36_FLASH_MODE_CFG),
> >> +	AIROHA_PINCTRL_PWM_EXT("gpio37", GPIO37_FLASH_MODE_CFG),
> >> +	AIROHA_PINCTRL_PWM_EXT("gpio38", GPIO38_FLASH_MODE_CFG),
> >> +	AIROHA_PINCTRL_PWM_EXT("gpio39", GPIO39_FLASH_MODE_CFG),
> >> +	AIROHA_PINCTRL_PWM_EXT("gpio40", GPIO40_FLASH_MODE_CFG),
> >> +	AIROHA_PINCTRL_PWM_EXT("gpio41", GPIO41_FLASH_MODE_CFG),
> >> +	AIROHA_PINCTRL_PWM_EXT("gpio42", GPIO42_FLASH_MODE_CFG),
> >> +	AIROHA_PINCTRL_PWM_EXT("gpio43", GPIO43_FLASH_MODE_CFG),
> >> +	AIROHA_PINCTRL_PWM_EXT("gpio44", GPIO44_FLASH_MODE_CFG),
> >> +	AIROHA_PINCTRL_PWM_EXT("gpio45", GPIO45_FLASH_MODE_CFG),
> >> +	AIROHA_PINCTRL_PWM_EXT("gpio46", GPIO46_FLASH_MODE_CFG),
> >> +	AIROHA_PINCTRL_PWM_EXT_SEC("gpio47", GPIO47_FLASH_MODE_CFG,
> >> +				   GPIO_PCIE_RESET0_MASK),
> >> +	AIROHA_PINCTRL_PWM_EXT_SEC("gpio48", GPIO48_FLASH_MODE_CFG,
> >> +				   GPIO_PCIE_RESET1_MASK),
> >> +	AIROHA_PINCTRL_PWM_EXT_SEC("gpio49", GPIO49_FLASH_MODE_CFG,
> >> +				   GPIO_PCIE_RESET2_MASK),
> >> +};
> >> +
> >> +static const struct airoha_pinctrl_func_group phy1_led0_func_group[] = {
> >> +	AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK,
> >> +				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),
> >> +	AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK,
> >> +				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)),
> >> +	AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK,
> >> +				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)),
> >> +	AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK,
> >> +				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),
> >> +};
> >> +
> >> +static const struct airoha_pinctrl_func_group phy2_led0_func_group[] = {
> >> +	AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK,
> >> +				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),
> >> +	AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK,
> >> +				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)),
> >> +	AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK,
> >> +				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)),
> >> +	AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK,
> >> +				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),
> >> +};
> >> +
> >> +static const struct airoha_pinctrl_func_group phy3_led0_func_group[] = {
> >> +	AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK,
> >> +				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
> >> +	AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK,
> >> +				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),
> >> +	AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK,
> >> +				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),
> >> +	AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK,
> >> +				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
> >> +};
> >> +
> >> +static const struct airoha_pinctrl_func_group phy4_led0_func_group[] = {
> >> +	AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK,
> >> +				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)),
> >> +	AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK,
> >> +				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)),
> >> +	AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK,
> >> +				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)),
> >> +	AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK,
> >> +				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)),
> >> +};
> >> +
> >> +static const struct airoha_pinctrl_func_group phy1_led1_func_group[] = {
> >> +	AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK,
> >> +				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),
> >> +	AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK,
> >> +				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)),
> >> +	AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK,
> >> +				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)),
> >> +	AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK,
> >> +				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),
> >> +};
> >> +
> >> +static const struct airoha_pinctrl_func_group phy2_led1_func_group[] = {
> >> +	AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK,
> >> +				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),
> >> +	AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK,
> >> +				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)),
> >> +	AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK,
> >> +				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)),
> >> +	AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK,
> >> +				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),
> >> +};
> >> +
> >> +static const struct airoha_pinctrl_func_group phy3_led1_func_group[] = {
> >> +	AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK,
> >> +				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
> >> +	AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK,
> >> +				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),
> >> +	AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK,
> >> +				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),
> >> +	AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK,
> >> +				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
> >> +};
> >> +
> >> +static const struct airoha_pinctrl_func_group phy4_led1_func_group[] = {
> >> +	AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK,
> >> +				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)),
> >> +	AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK,
> >> +				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)),
> >> +	AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK,
> >> +				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)),
> >> +	AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK,
> >> +				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)),
> >> +};
> >> +
> >> +static const struct airoha_pinctrl_func en7581_pinctrl_funcs[] = {
> >> +	PINCTRL_FUNC_DESC("pon", pon),
> >> +	PINCTRL_FUNC_DESC("tod_1pps", tod_1pps),
> >> +	PINCTRL_FUNC_DESC("sipo", sipo),
> >> +	PINCTRL_FUNC_DESC("mdio", mdio),
> >> +	PINCTRL_FUNC_DESC("uart", uart),
> >> +	PINCTRL_FUNC_DESC("i2c", i2c),
> >> +	PINCTRL_FUNC_DESC("jtag", jtag),
> >> +	PINCTRL_FUNC_DESC("pcm", pcm),
> >> +	PINCTRL_FUNC_DESC("spi", spi),
> >> +	PINCTRL_FUNC_DESC("pcm_spi", pcm_spi),
> >> +	PINCTRL_FUNC_DESC("i2s", i2s),
> >> +	PINCTRL_FUNC_DESC("emmc", emmc),
> >> +	PINCTRL_FUNC_DESC("pnand", pnand),
> >> +	PINCTRL_FUNC_DESC("gpio", gpio),
> >> +	PINCTRL_FUNC_DESC("pcie_reset", pcie_reset),
> >> +	PINCTRL_FUNC_DESC("pwm", pwm),
> >> +	PINCTRL_FUNC_DESC("phy1_led0", phy1_led0),
> >> +	PINCTRL_FUNC_DESC("phy2_led0", phy2_led0),
> >> +	PINCTRL_FUNC_DESC("phy3_led0", phy3_led0),
> >> +	PINCTRL_FUNC_DESC("phy4_led0", phy4_led0),
> >> +	PINCTRL_FUNC_DESC("phy1_led1", phy1_led1),
> >> +	PINCTRL_FUNC_DESC("phy2_led1", phy2_led1),
> >> +	PINCTRL_FUNC_DESC("phy3_led1", phy3_led1),
> >> +	PINCTRL_FUNC_DESC("phy4_led1", phy4_led1),
> >> +};
> >> +
> >> +static const struct airoha_pinctrl_conf en7581_pinctrl_pullup_conf[] = {
> >> +	PINCTRL_CONF_DESC(0, REG_I2C_SDA_PU, UART1_TXD_PU_MASK),
> >> +	PINCTRL_CONF_DESC(1, REG_I2C_SDA_PU, UART1_RXD_PU_MASK),
> >> +	PINCTRL_CONF_DESC(2, REG_I2C_SDA_PU, I2C_SDA_PU_MASK),
> >> +	PINCTRL_CONF_DESC(3, REG_I2C_SDA_PU, I2C_SCL_PU_MASK),
> >> +	PINCTRL_CONF_DESC(4, REG_I2C_SDA_PU, SPI_CS0_PU_MASK),
> >> +	PINCTRL_CONF_DESC(5, REG_I2C_SDA_PU, SPI_CLK_PU_MASK),
> >> +	PINCTRL_CONF_DESC(6, REG_I2C_SDA_PU, SPI_MOSI_PU_MASK),
> >> +	PINCTRL_CONF_DESC(7, REG_I2C_SDA_PU, SPI_MISO_PU_MASK),
> >> +	PINCTRL_CONF_DESC(13, REG_GPIO_L_PU, BIT(0)),
> >> +	PINCTRL_CONF_DESC(14, REG_GPIO_L_PU, BIT(1)),
> >> +	PINCTRL_CONF_DESC(15, REG_GPIO_L_PU, BIT(2)),
> >> +	PINCTRL_CONF_DESC(16, REG_GPIO_L_PU, BIT(3)),
> >> +	PINCTRL_CONF_DESC(17, REG_GPIO_L_PU, BIT(4)),
> >> +	PINCTRL_CONF_DESC(18, REG_GPIO_L_PU, BIT(5)),
> >> +	PINCTRL_CONF_DESC(19, REG_GPIO_L_PU, BIT(6)),
> >> +	PINCTRL_CONF_DESC(20, REG_GPIO_L_PU, BIT(7)),
> >> +	PINCTRL_CONF_DESC(21, REG_GPIO_L_PU, BIT(8)),
> >> +	PINCTRL_CONF_DESC(22, REG_GPIO_L_PU, BIT(9)),
> >> +	PINCTRL_CONF_DESC(23, REG_GPIO_L_PU, BIT(10)),
> >> +	PINCTRL_CONF_DESC(24, REG_GPIO_L_PU, BIT(11)),
> >> +	PINCTRL_CONF_DESC(25, REG_GPIO_L_PU, BIT(12)),
> >> +	PINCTRL_CONF_DESC(26, REG_GPIO_L_PU, BIT(13)),
> >> +	PINCTRL_CONF_DESC(27, REG_GPIO_L_PU, BIT(14)),
> >> +	PINCTRL_CONF_DESC(28, REG_GPIO_L_PU, BIT(15)),
> >> +	PINCTRL_CONF_DESC(29, REG_GPIO_L_PU, BIT(16)),
> >> +	PINCTRL_CONF_DESC(30, REG_GPIO_L_PU, BIT(17)),
> >> +	PINCTRL_CONF_DESC(31, REG_GPIO_L_PU, BIT(18)),
> >> +	PINCTRL_CONF_DESC(32, REG_GPIO_L_PU, BIT(19)),
> >> +	PINCTRL_CONF_DESC(33, REG_GPIO_L_PU, BIT(20)),
> >> +	PINCTRL_CONF_DESC(34, REG_GPIO_L_PU, BIT(21)),
> >> +	PINCTRL_CONF_DESC(35, REG_GPIO_L_PU, BIT(22)),
> >> +	PINCTRL_CONF_DESC(36, REG_GPIO_L_PU, BIT(23)),
> >> +	PINCTRL_CONF_DESC(37, REG_GPIO_L_PU, BIT(24)),
> >> +	PINCTRL_CONF_DESC(38, REG_GPIO_L_PU, BIT(25)),
> >> +	PINCTRL_CONF_DESC(39, REG_GPIO_L_PU, BIT(26)),
> >> +	PINCTRL_CONF_DESC(40, REG_GPIO_L_PU, BIT(27)),
> >> +	PINCTRL_CONF_DESC(41, REG_GPIO_L_PU, BIT(28)),
> >> +	PINCTRL_CONF_DESC(42, REG_GPIO_L_PU, BIT(29)),
> >> +	PINCTRL_CONF_DESC(43, REG_GPIO_L_PU, BIT(30)),
> >> +	PINCTRL_CONF_DESC(44, REG_GPIO_L_PU, BIT(31)),
> >> +	PINCTRL_CONF_DESC(45, REG_GPIO_H_PU, BIT(0)),
> >> +	PINCTRL_CONF_DESC(46, REG_GPIO_H_PU, BIT(1)),
> >> +	PINCTRL_CONF_DESC(47, REG_GPIO_H_PU, BIT(2)),
> >> +	PINCTRL_CONF_DESC(48, REG_GPIO_H_PU, BIT(3)),
> >> +	PINCTRL_CONF_DESC(49, REG_GPIO_H_PU, BIT(4)),
> >> +	PINCTRL_CONF_DESC(50, REG_GPIO_H_PU, BIT(5)),
> >> +	PINCTRL_CONF_DESC(51, REG_GPIO_H_PU, BIT(6)),
> >> +	PINCTRL_CONF_DESC(52, REG_GPIO_H_PU, BIT(7)),
> >> +	PINCTRL_CONF_DESC(53, REG_GPIO_H_PU, BIT(8)),
> >> +	PINCTRL_CONF_DESC(54, REG_GPIO_H_PU, BIT(9)),
> >> +	PINCTRL_CONF_DESC(55, REG_GPIO_H_PU, BIT(10)),
> >> +	PINCTRL_CONF_DESC(56, REG_GPIO_H_PU, BIT(11)),
> >> +	PINCTRL_CONF_DESC(57, REG_GPIO_H_PU, BIT(12)),
> >> +	PINCTRL_CONF_DESC(58, REG_GPIO_H_PU, BIT(13)),
> >> +	PINCTRL_CONF_DESC(59, REG_GPIO_H_PU, BIT(14)),
> >> +	PINCTRL_CONF_DESC(60, REG_I2C_SDA_PU, PCIE0_RESET_PU_MASK),
> >> +	PINCTRL_CONF_DESC(61, REG_I2C_SDA_PU, PCIE1_RESET_PU_MASK),
> >> +	PINCTRL_CONF_DESC(62, REG_I2C_SDA_PU, PCIE2_RESET_PU_MASK),
> >> +};
> >> +
> >> +static const struct airoha_pinctrl_conf en7581_pinctrl_pulldown_conf[] = {
> >> +	PINCTRL_CONF_DESC(0, REG_I2C_SDA_PD, UART1_TXD_PD_MASK),
> >> +	PINCTRL_CONF_DESC(1, REG_I2C_SDA_PD, UART1_RXD_PD_MASK),
> >> +	PINCTRL_CONF_DESC(2, REG_I2C_SDA_PD, I2C_SDA_PD_MASK),
> >> +	PINCTRL_CONF_DESC(3, REG_I2C_SDA_PD, I2C_SCL_PD_MASK),
> >> +	PINCTRL_CONF_DESC(4, REG_I2C_SDA_PD, SPI_CS0_PD_MASK),
> >> +	PINCTRL_CONF_DESC(5, REG_I2C_SDA_PD, SPI_CLK_PD_MASK),
> >> +	PINCTRL_CONF_DESC(6, REG_I2C_SDA_PD, SPI_MOSI_PD_MASK),
> >> +	PINCTRL_CONF_DESC(7, REG_I2C_SDA_PD, SPI_MISO_PD_MASK),
> >> +	PINCTRL_CONF_DESC(13, REG_GPIO_L_PD, BIT(0)),
> >> +	PINCTRL_CONF_DESC(14, REG_GPIO_L_PD, BIT(1)),
> >> +	PINCTRL_CONF_DESC(15, REG_GPIO_L_PD, BIT(2)),
> >> +	PINCTRL_CONF_DESC(16, REG_GPIO_L_PD, BIT(3)),
> >> +	PINCTRL_CONF_DESC(17, REG_GPIO_L_PD, BIT(4)),
> >> +	PINCTRL_CONF_DESC(18, REG_GPIO_L_PD, BIT(5)),
> >> +	PINCTRL_CONF_DESC(19, REG_GPIO_L_PD, BIT(6)),
> >> +	PINCTRL_CONF_DESC(20, REG_GPIO_L_PD, BIT(7)),
> >> +	PINCTRL_CONF_DESC(21, REG_GPIO_L_PD, BIT(8)),
> >> +	PINCTRL_CONF_DESC(22, REG_GPIO_L_PD, BIT(9)),
> >> +	PINCTRL_CONF_DESC(23, REG_GPIO_L_PD, BIT(10)),
> >> +	PINCTRL_CONF_DESC(24, REG_GPIO_L_PD, BIT(11)),
> >> +	PINCTRL_CONF_DESC(25, REG_GPIO_L_PD, BIT(12)),
> >> +	PINCTRL_CONF_DESC(26, REG_GPIO_L_PD, BIT(13)),
> >> +	PINCTRL_CONF_DESC(27, REG_GPIO_L_PD, BIT(14)),
> >> +	PINCTRL_CONF_DESC(28, REG_GPIO_L_PD, BIT(15)),
> >> +	PINCTRL_CONF_DESC(29, REG_GPIO_L_PD, BIT(16)),
> >> +	PINCTRL_CONF_DESC(30, REG_GPIO_L_PD, BIT(17)),
> >> +	PINCTRL_CONF_DESC(31, REG_GPIO_L_PD, BIT(18)),
> >> +	PINCTRL_CONF_DESC(32, REG_GPIO_L_PD, BIT(19)),
> >> +	PINCTRL_CONF_DESC(33, REG_GPIO_L_PD, BIT(20)),
> >> +	PINCTRL_CONF_DESC(34, REG_GPIO_L_PD, BIT(21)),
> >> +	PINCTRL_CONF_DESC(35, REG_GPIO_L_PD, BIT(22)),
> >> +	PINCTRL_CONF_DESC(36, REG_GPIO_L_PD, BIT(23)),
> >> +	PINCTRL_CONF_DESC(37, REG_GPIO_L_PD, BIT(24)),
> >> +	PINCTRL_CONF_DESC(38, REG_GPIO_L_PD, BIT(25)),
> >> +	PINCTRL_CONF_DESC(39, REG_GPIO_L_PD, BIT(26)),
> >> +	PINCTRL_CONF_DESC(40, REG_GPIO_L_PD, BIT(27)),
> >> +	PINCTRL_CONF_DESC(41, REG_GPIO_L_PD, BIT(28)),
> >> +	PINCTRL_CONF_DESC(42, REG_GPIO_L_PD, BIT(29)),
> >> +	PINCTRL_CONF_DESC(43, REG_GPIO_L_PD, BIT(30)),
> >> +	PINCTRL_CONF_DESC(44, REG_GPIO_L_PD, BIT(31)),
> >> +	PINCTRL_CONF_DESC(45, REG_GPIO_H_PD, BIT(0)),
> >> +	PINCTRL_CONF_DESC(46, REG_GPIO_H_PD, BIT(1)),
> >> +	PINCTRL_CONF_DESC(47, REG_GPIO_H_PD, BIT(2)),
> >> +	PINCTRL_CONF_DESC(48, REG_GPIO_H_PD, BIT(3)),
> >> +	PINCTRL_CONF_DESC(49, REG_GPIO_H_PD, BIT(4)),
> >> +	PINCTRL_CONF_DESC(50, REG_GPIO_H_PD, BIT(5)),
> >> +	PINCTRL_CONF_DESC(51, REG_GPIO_H_PD, BIT(6)),
> >> +	PINCTRL_CONF_DESC(52, REG_GPIO_H_PD, BIT(7)),
> >> +	PINCTRL_CONF_DESC(53, REG_GPIO_H_PD, BIT(8)),
> >> +	PINCTRL_CONF_DESC(54, REG_GPIO_H_PD, BIT(9)),
> >> +	PINCTRL_CONF_DESC(55, REG_GPIO_H_PD, BIT(10)),
> >> +	PINCTRL_CONF_DESC(56, REG_GPIO_H_PD, BIT(11)),
> >> +	PINCTRL_CONF_DESC(57, REG_GPIO_H_PD, BIT(12)),
> >> +	PINCTRL_CONF_DESC(58, REG_GPIO_H_PD, BIT(13)),
> >> +	PINCTRL_CONF_DESC(59, REG_GPIO_H_PD, BIT(14)),
> >> +	PINCTRL_CONF_DESC(60, REG_I2C_SDA_PD, PCIE0_RESET_PD_MASK),
> >> +	PINCTRL_CONF_DESC(61, REG_I2C_SDA_PD, PCIE1_RESET_PD_MASK),
> >> +	PINCTRL_CONF_DESC(62, REG_I2C_SDA_PD, PCIE2_RESET_PD_MASK),
> >> +};
> >> +
> >> +static const struct airoha_pinctrl_conf en7581_pinctrl_drive_e2_conf[] = {
> >> +	PINCTRL_CONF_DESC(0, REG_I2C_SDA_E2, UART1_TXD_E2_MASK),
> >> +	PINCTRL_CONF_DESC(1, REG_I2C_SDA_E2, UART1_RXD_E2_MASK),
> >> +	PINCTRL_CONF_DESC(2, REG_I2C_SDA_E2, I2C_SDA_E2_MASK),
> >> +	PINCTRL_CONF_DESC(3, REG_I2C_SDA_E2, I2C_SCL_E2_MASK),
> >> +	PINCTRL_CONF_DESC(4, REG_I2C_SDA_E2, SPI_CS0_E2_MASK),
> >> +	PINCTRL_CONF_DESC(5, REG_I2C_SDA_E2, SPI_CLK_E2_MASK),
> >> +	PINCTRL_CONF_DESC(6, REG_I2C_SDA_E2, SPI_MOSI_E2_MASK),
> >> +	PINCTRL_CONF_DESC(7, REG_I2C_SDA_E2, SPI_MISO_E2_MASK),
> >> +	PINCTRL_CONF_DESC(13, REG_GPIO_L_E2, BIT(0)),
> >> +	PINCTRL_CONF_DESC(14, REG_GPIO_L_E2, BIT(1)),
> >> +	PINCTRL_CONF_DESC(15, REG_GPIO_L_E2, BIT(2)),
> >> +	PINCTRL_CONF_DESC(16, REG_GPIO_L_E2, BIT(3)),
> >> +	PINCTRL_CONF_DESC(17, REG_GPIO_L_E2, BIT(4)),
> >> +	PINCTRL_CONF_DESC(18, REG_GPIO_L_E2, BIT(5)),
> >> +	PINCTRL_CONF_DESC(19, REG_GPIO_L_E2, BIT(6)),
> >> +	PINCTRL_CONF_DESC(20, REG_GPIO_L_E2, BIT(7)),
> >> +	PINCTRL_CONF_DESC(21, REG_GPIO_L_E2, BIT(8)),
> >> +	PINCTRL_CONF_DESC(22, REG_GPIO_L_E2, BIT(9)),
> >> +	PINCTRL_CONF_DESC(23, REG_GPIO_L_E2, BIT(10)),
> >> +	PINCTRL_CONF_DESC(24, REG_GPIO_L_E2, BIT(11)),
> >> +	PINCTRL_CONF_DESC(25, REG_GPIO_L_E2, BIT(12)),
> >> +	PINCTRL_CONF_DESC(26, REG_GPIO_L_E2, BIT(13)),
> >> +	PINCTRL_CONF_DESC(27, REG_GPIO_L_E2, BIT(14)),
> >> +	PINCTRL_CONF_DESC(28, REG_GPIO_L_E2, BIT(15)),
> >> +	PINCTRL_CONF_DESC(29, REG_GPIO_L_E2, BIT(16)),
> >> +	PINCTRL_CONF_DESC(30, REG_GPIO_L_E2, BIT(17)),
> >> +	PINCTRL_CONF_DESC(31, REG_GPIO_L_E2, BIT(18)),
> >> +	PINCTRL_CONF_DESC(32, REG_GPIO_L_E2, BIT(19)),
> >> +	PINCTRL_CONF_DESC(33, REG_GPIO_L_E2, BIT(20)),
> >> +	PINCTRL_CONF_DESC(34, REG_GPIO_L_E2, BIT(21)),
> >> +	PINCTRL_CONF_DESC(35, REG_GPIO_L_E2, BIT(22)),
> >> +	PINCTRL_CONF_DESC(36, REG_GPIO_L_E2, BIT(23)),
> >> +	PINCTRL_CONF_DESC(37, REG_GPIO_L_E2, BIT(24)),
> >> +	PINCTRL_CONF_DESC(38, REG_GPIO_L_E2, BIT(25)),
> >> +	PINCTRL_CONF_DESC(39, REG_GPIO_L_E2, BIT(26)),
> >> +	PINCTRL_CONF_DESC(40, REG_GPIO_L_E2, BIT(27)),
> >> +	PINCTRL_CONF_DESC(41, REG_GPIO_L_E2, BIT(28)),
> >> +	PINCTRL_CONF_DESC(42, REG_GPIO_L_E2, BIT(29)),
> >> +	PINCTRL_CONF_DESC(43, REG_GPIO_L_E2, BIT(30)),
> >> +	PINCTRL_CONF_DESC(44, REG_GPIO_L_E2, BIT(31)),
> >> +	PINCTRL_CONF_DESC(45, REG_GPIO_H_E2, BIT(0)),
> >> +	PINCTRL_CONF_DESC(46, REG_GPIO_H_E2, BIT(1)),
> >> +	PINCTRL_CONF_DESC(47, REG_GPIO_H_E2, BIT(2)),
> >> +	PINCTRL_CONF_DESC(48, REG_GPIO_H_E2, BIT(3)),
> >> +	PINCTRL_CONF_DESC(49, REG_GPIO_H_E2, BIT(4)),
> >> +	PINCTRL_CONF_DESC(50, REG_GPIO_H_E2, BIT(5)),
> >> +	PINCTRL_CONF_DESC(51, REG_GPIO_H_E2, BIT(6)),
> >> +	PINCTRL_CONF_DESC(52, REG_GPIO_H_E2, BIT(7)),
> >> +	PINCTRL_CONF_DESC(53, REG_GPIO_H_E2, BIT(8)),
> >> +	PINCTRL_CONF_DESC(54, REG_GPIO_H_E2, BIT(9)),
> >> +	PINCTRL_CONF_DESC(55, REG_GPIO_H_E2, BIT(10)),
> >> +	PINCTRL_CONF_DESC(56, REG_GPIO_H_E2, BIT(11)),
> >> +	PINCTRL_CONF_DESC(57, REG_GPIO_H_E2, BIT(12)),
> >> +	PINCTRL_CONF_DESC(58, REG_GPIO_H_E2, BIT(13)),
> >> +	PINCTRL_CONF_DESC(59, REG_GPIO_H_E2, BIT(14)),
> >> +	PINCTRL_CONF_DESC(60, REG_I2C_SDA_E2, PCIE0_RESET_E2_MASK),
> >> +	PINCTRL_CONF_DESC(61, REG_I2C_SDA_E2, PCIE1_RESET_E2_MASK),
> >> +	PINCTRL_CONF_DESC(62, REG_I2C_SDA_E2, PCIE2_RESET_E2_MASK),
> >> +};
> >> +
> >> +static const struct airoha_pinctrl_conf en7581_pinctrl_drive_e4_conf[] = {
> >> +	PINCTRL_CONF_DESC(0, REG_I2C_SDA_E4, UART1_TXD_E4_MASK),
> >> +	PINCTRL_CONF_DESC(1, REG_I2C_SDA_E4, UART1_RXD_E4_MASK),
> >> +	PINCTRL_CONF_DESC(2, REG_I2C_SDA_E4, I2C_SDA_E4_MASK),
> >> +	PINCTRL_CONF_DESC(3, REG_I2C_SDA_E4, I2C_SCL_E4_MASK),
> >> +	PINCTRL_CONF_DESC(4, REG_I2C_SDA_E4, SPI_CS0_E4_MASK),
> >> +	PINCTRL_CONF_DESC(5, REG_I2C_SDA_E4, SPI_CLK_E4_MASK),
> >> +	PINCTRL_CONF_DESC(6, REG_I2C_SDA_E4, SPI_MOSI_E4_MASK),
> >> +	PINCTRL_CONF_DESC(7, REG_I2C_SDA_E4, SPI_MISO_E4_MASK),
> >> +	PINCTRL_CONF_DESC(13, REG_GPIO_L_E4, BIT(0)),
> >> +	PINCTRL_CONF_DESC(14, REG_GPIO_L_E4, BIT(1)),
> >> +	PINCTRL_CONF_DESC(15, REG_GPIO_L_E4, BIT(2)),
> >> +	PINCTRL_CONF_DESC(16, REG_GPIO_L_E4, BIT(3)),
> >> +	PINCTRL_CONF_DESC(17, REG_GPIO_L_E4, BIT(4)),
> >> +	PINCTRL_CONF_DESC(18, REG_GPIO_L_E4, BIT(5)),
> >> +	PINCTRL_CONF_DESC(19, REG_GPIO_L_E4, BIT(6)),
> >> +	PINCTRL_CONF_DESC(20, REG_GPIO_L_E4, BIT(7)),
> >> +	PINCTRL_CONF_DESC(21, REG_GPIO_L_E4, BIT(8)),
> >> +	PINCTRL_CONF_DESC(22, REG_GPIO_L_E4, BIT(9)),
> >> +	PINCTRL_CONF_DESC(23, REG_GPIO_L_E4, BIT(10)),
> >> +	PINCTRL_CONF_DESC(24, REG_GPIO_L_E4, BIT(11)),
> >> +	PINCTRL_CONF_DESC(25, REG_GPIO_L_E4, BIT(12)),
> >> +	PINCTRL_CONF_DESC(26, REG_GPIO_L_E4, BIT(13)),
> >> +	PINCTRL_CONF_DESC(27, REG_GPIO_L_E4, BIT(14)),
> >> +	PINCTRL_CONF_DESC(28, REG_GPIO_L_E4, BIT(15)),
> >> +	PINCTRL_CONF_DESC(29, REG_GPIO_L_E4, BIT(16)),
> >> +	PINCTRL_CONF_DESC(30, REG_GPIO_L_E4, BIT(17)),
> >> +	PINCTRL_CONF_DESC(31, REG_GPIO_L_E4, BIT(18)),
> >> +	PINCTRL_CONF_DESC(32, REG_GPIO_L_E4, BIT(19)),
> >> +	PINCTRL_CONF_DESC(33, REG_GPIO_L_E4, BIT(20)),
> >> +	PINCTRL_CONF_DESC(34, REG_GPIO_L_E4, BIT(21)),
> >> +	PINCTRL_CONF_DESC(35, REG_GPIO_L_E4, BIT(22)),
> >> +	PINCTRL_CONF_DESC(36, REG_GPIO_L_E4, BIT(23)),
> >> +	PINCTRL_CONF_DESC(37, REG_GPIO_L_E4, BIT(24)),
> >> +	PINCTRL_CONF_DESC(38, REG_GPIO_L_E4, BIT(25)),
> >> +	PINCTRL_CONF_DESC(39, REG_GPIO_L_E4, BIT(26)),
> >> +	PINCTRL_CONF_DESC(40, REG_GPIO_L_E4, BIT(27)),
> >> +	PINCTRL_CONF_DESC(41, REG_GPIO_L_E4, BIT(28)),
> >> +	PINCTRL_CONF_DESC(42, REG_GPIO_L_E4, BIT(29)),
> >> +	PINCTRL_CONF_DESC(43, REG_GPIO_L_E4, BIT(30)),
> >> +	PINCTRL_CONF_DESC(44, REG_GPIO_L_E4, BIT(31)),
> >> +	PINCTRL_CONF_DESC(45, REG_GPIO_H_E4, BIT(0)),
> >> +	PINCTRL_CONF_DESC(46, REG_GPIO_H_E4, BIT(1)),
> >> +	PINCTRL_CONF_DESC(47, REG_GPIO_H_E4, BIT(2)),
> >> +	PINCTRL_CONF_DESC(48, REG_GPIO_H_E4, BIT(3)),
> >> +	PINCTRL_CONF_DESC(49, REG_GPIO_H_E4, BIT(4)),
> >> +	PINCTRL_CONF_DESC(50, REG_GPIO_H_E4, BIT(5)),
> >> +	PINCTRL_CONF_DESC(51, REG_GPIO_H_E4, BIT(6)),
> >> +	PINCTRL_CONF_DESC(52, REG_GPIO_H_E4, BIT(7)),
> >> +	PINCTRL_CONF_DESC(53, REG_GPIO_H_E4, BIT(8)),
> >> +	PINCTRL_CONF_DESC(54, REG_GPIO_H_E4, BIT(9)),
> >> +	PINCTRL_CONF_DESC(55, REG_GPIO_H_E4, BIT(10)),
> >> +	PINCTRL_CONF_DESC(56, REG_GPIO_H_E4, BIT(11)),
> >> +	PINCTRL_CONF_DESC(57, REG_GPIO_H_E4, BIT(12)),
> >> +	PINCTRL_CONF_DESC(58, REG_GPIO_H_E4, BIT(13)),
> >> +	PINCTRL_CONF_DESC(59, REG_GPIO_H_E4, BIT(14)),
> >> +	PINCTRL_CONF_DESC(60, REG_I2C_SDA_E4, PCIE0_RESET_E4_MASK),
> >> +	PINCTRL_CONF_DESC(61, REG_I2C_SDA_E4, PCIE1_RESET_E4_MASK),
> >> +	PINCTRL_CONF_DESC(62, REG_I2C_SDA_E4, PCIE2_RESET_E4_MASK),
> >> +};
> >> +
> >> +static const struct airoha_pinctrl_conf en7581_pinctrl_pcie_rst_od_conf[] = {
> >> +	PINCTRL_CONF_DESC(60, REG_PCIE_RESET_OD, PCIE0_RESET_OD_MASK),
> >> +	PINCTRL_CONF_DESC(61, REG_PCIE_RESET_OD, PCIE1_RESET_OD_MASK),
> >> +	PINCTRL_CONF_DESC(62, REG_PCIE_RESET_OD, PCIE2_RESET_OD_MASK),
> >> +};
> >> +
> >> +static const struct airoha_pinctrl_match_data en7581_pinctrl_match_data = {
> >> +	.pinctrl_name = KBUILD_MODNAME,
> >> +	.pinctrl_owner = THIS_MODULE,
> >> +	.pins = en7581_pinctrl_pins,
> >> +	.num_pins = ARRAY_SIZE(en7581_pinctrl_pins),
> >> +	.grps = en7581_pinctrl_groups,
> >> +	.num_grps = ARRAY_SIZE(en7581_pinctrl_groups),
> >> +	.funcs = en7581_pinctrl_funcs,
> >> +	.num_funcs = ARRAY_SIZE(en7581_pinctrl_funcs),
> >> +	.confs_info = {
> >> +		[AIROHA_PINCTRL_CONFS_PULLUP] = {
> >> +			.confs = en7581_pinctrl_pullup_conf,
> >> +			.num_confs = ARRAY_SIZE(en7581_pinctrl_pullup_conf),
> >> +		},
> >> +		[AIROHA_PINCTRL_CONFS_PULLDOWN] = {
> >> +			.confs = en7581_pinctrl_pulldown_conf,
> >> +			.num_confs = ARRAY_SIZE(en7581_pinctrl_pulldown_conf),
> >> +		},
> >> +		[AIROHA_PINCTRL_CONFS_DRIVE_E2] = {
> >> +			.confs = en7581_pinctrl_drive_e2_conf,
> >> +			.num_confs = ARRAY_SIZE(en7581_pinctrl_drive_e2_conf),
> >> +		},
> >> +		[AIROHA_PINCTRL_CONFS_DRIVE_E4] = {
> >> +			.confs = en7581_pinctrl_drive_e4_conf,
> >> +			.num_confs = ARRAY_SIZE(en7581_pinctrl_drive_e4_conf),
> >> +		},
> >> +		[AIROHA_PINCTRL_CONFS_PCIE_RST_OD] = {
> >> +			.confs = en7581_pinctrl_pcie_rst_od_conf,
> >> +			.num_confs = ARRAY_SIZE(en7581_pinctrl_pcie_rst_od_conf),
> >> +		},
> >> +	},
> >> +};
> >> +
> >> +static const struct of_device_id airoha_pinctrl_of_match[] = {
> >> +	{ .compatible = "airoha,en7581-pinctrl", .data = &en7581_pinctrl_match_data },
> >> +	{ /* sentinel */ }
> >> +};
> >> +MODULE_DEVICE_TABLE(of, airoha_pinctrl_of_match);
> >> +
> >> +static struct platform_driver airoha_pinctrl_driver = {
> >> +	.probe = airoha_pinctrl_probe,
> >> +	.driver = {
> >> +		.name = "pinctrl-airoha-an7581",
> >> +		.of_match_table = airoha_pinctrl_of_match,
> >> +	},
> >> +};
> >> +module_platform_driver(airoha_pinctrl_driver);
> >> +
> >> +MODULE_LICENSE("GPL");
> >> +MODULE_AUTHOR("Lorenzo Bianconi <lorenzo@kernel.org>");
> >> +MODULE_AUTHOR("Benjamin Larsson <benjamin.larsson@genexis.eu>");
> >> +MODULE_AUTHOR("Markus Gothe <markus.gothe@genexis.eu>");
> >> +MODULE_DESCRIPTION("Pinctrl driver for Airoha AN7581 SoC");
> >> diff --git a/drivers/pinctrl/airoha/pinctrl-an7583.c b/drivers/pinctrl/airoha/pinctrl-an7583.c
> >> new file mode 100644
> >> index 0000000000000..b9d8dd94de5f0
> >> --- /dev/null
> >> +++ b/drivers/pinctrl/airoha/pinctrl-an7583.c
> >> @@ -0,0 +1,1456 @@
> >> +// SPDX-License-Identifier: GPL-2.0-only
> >> +/*
> >> + * Author: Lorenzo Bianconi <lorenzo@kernel.org>
> >> + * Author: Benjamin Larsson <benjamin.larsson@genexis.eu>
> >> + * Author: Markus Gothe <markus.gothe@genexis.eu>
> >> + */
> >> +
> >> +#include "airoha-common.h"
> >> +
> >> +/* MUX */
> >> +#define REG_GPIO_2ND_I2C_MODE			0x0214
> >> +#define GPIO_LAN3_LED1_MODE_MASK		BIT(10)
> >> +#define GPIO_LAN3_LED0_MODE_MASK		BIT(9)
> >> +#define GPIO_LAN2_LED1_MODE_MASK		BIT(8)
> >> +#define GPIO_LAN2_LED0_MODE_MASK		BIT(7)
> >> +#define GPIO_LAN1_LED1_MODE_MASK		BIT(6)
> >> +#define GPIO_LAN1_LED0_MODE_MASK		BIT(5)
> >> +#define GPIO_LAN0_LED1_MODE_MASK		BIT(4)
> >> +#define GPIO_LAN0_LED0_MODE_MASK		BIT(3)
> >> +#define PON_TOD_1PPS_MODE_MASK			BIT(2)
> >> +#define GSW_TOD_1PPS_MODE_MASK			BIT(1)
> >> +
> >> +#define REG_GPIO_SPI_CS1_MODE			0x0218
> >> +#define GPIO_MDC_IO_MASTER_MODE_MASK		BIT(22)
> >> +#define GPIO_PCM_SPI_CS4_MODE_MASK		BIT(21)
> >> +#define GPIO_PCM_SPI_CS3_MODE_MASK		BIT(20)
> >> +#define AN7583_GPIO_PCM_SPI_CS2_MODE_MASK	BIT(18)
> >> +#define GPIO_PCM_SPI_CS1_MODE_MASK		BIT(17)
> >> +#define GPIO_PCM_SPI_MODE_MASK			BIT(16)
> >> +#define GPIO_PCM2_MODE_MASK			BIT(13)
> >> +#define GPIO_PCM1_MODE_MASK			BIT(12)
> >> +#define GPIO_PCM_INT_MODE_MASK			BIT(9)
> >> +#define GPIO_PCM_RESET_MODE_MASK		BIT(8)
> >> +#define GPIO_SPI_QUAD_MODE_MASK			BIT(4)
> >> +#define GPIO_SPI_CS4_MODE_MASK			BIT(3)
> >> +#define GPIO_SPI_CS3_MODE_MASK			BIT(2)
> >> +#define GPIO_SPI_CS2_MODE_MASK			BIT(1)
> >> +#define GPIO_SPI_CS1_MODE_MASK			BIT(0)
> >> +
> >> +#define REG_GPIO_PON_MODE			0x021c
> >> +#define AN7583_MDIO_0_GPIO_MODE_MASK		BIT(26)
> >> +#define AN7583_MDC_0_GPIO_MODE_MASK		BIT(25)
> >> +#define AN7583_UART_RXD_GPIO_MODE_MASK		BIT(24)
> >> +#define AN7583_UART_TXD_GPIO_MODE_MASK		BIT(23)
> >> +#define AN7583_SPI_MISO_GPIO_MODE_MASK		BIT(22)
> >> +#define AN7583_SPI_MOSI_GPIO_MODE_MASK		BIT(21)
> >> +#define AN7583_SPI_CS_GPIO_MODE_MASK		BIT(20)
> >> +#define AN7583_SPI_CLK_GPIO_MODE_MASK		BIT(19)
> >> +#define AN7583_I2C1_SDA_GPIO_MODE_MASK		BIT(18)
> >> +#define AN7583_I2C1_SCL_GPIO_MODE_MASK		BIT(17)
> >> +#define AN7583_I2C0_SDA_GPIO_MODE_MASK		BIT(16)
> >> +#define AN7583_I2C0_SCL_GPIO_MODE_MASK		BIT(15)
> >> +#define GPIO_PARALLEL_NAND_MODE_MASK		BIT(14)
> >> +#define GPIO_SGMII_MDIO_MODE_MASK		BIT(13)
> >> +#define SIPO_RCLK_MODE_MASK			BIT(11)
> >> +#define GPIO_PCIE_RESET1_MASK			BIT(10)
> >> +#define GPIO_PCIE_RESET0_MASK			BIT(9)
> >> +#define GPIO_UART5_MODE_MASK			BIT(8)
> >> +#define GPIO_UART4_MODE_MASK			BIT(7)
> >> +#define GPIO_HSUART_CTS_RTS_MODE_MASK		BIT(6)
> >> +#define GPIO_HSUART_MODE_MASK			BIT(5)
> >> +#define GPIO_UART2_CTS_RTS_MODE_MASK		BIT(4)
> >> +#define GPIO_UART2_MODE_MASK			BIT(3)
> >> +#define GPIO_SIPO_MODE_MASK			BIT(2)
> >> +#define GPIO_EMMC_MODE_MASK			BIT(1)
> >> +#define GPIO_PON_MODE_MASK			BIT(0)
> >> +
> >> +#define REG_NPU_UART_EN				0x0224
> >> +#define JTAG_UDI_EN_MASK			BIT(4)
> >> +#define JTAG_DFD_EN_MASK			BIT(3)
> >> +
> >> +#define REG_FORCE_GPIO_EN			0x0228
> >> +#define FORCE_GPIO_EN(n)			BIT(n)
> >> +
> >> +/* LED MAP */
> >> +#define REG_LAN_LED0_MAPPING			0x027c
> >> +#define REG_LAN_LED1_MAPPING			0x0280
> >> +
> >> +#define LAN4_LED_MAPPING_MASK			GENMASK(18, 16)
> >> +#define LAN4_PHY_LED_MAP(_n)			FIELD_PREP_CONST(LAN4_LED_MAPPING_MASK, (_n))
> >> +
> >> +#define LAN3_LED_MAPPING_MASK			GENMASK(14, 12)
> >> +#define LAN3_PHY_LED_MAP(_n)			FIELD_PREP_CONST(LAN3_LED_MAPPING_MASK, (_n))
> >> +
> >> +#define LAN2_LED_MAPPING_MASK			GENMASK(10, 8)
> >> +#define LAN2_PHY_LED_MAP(_n)			FIELD_PREP_CONST(LAN2_LED_MAPPING_MASK, (_n))
> >> +
> >> +#define LAN1_LED_MAPPING_MASK			GENMASK(6, 4)
> >> +#define LAN1_PHY_LED_MAP(_n)			FIELD_PREP_CONST(LAN1_LED_MAPPING_MASK, (_n))
> >> +
> >> +#define LAN0_LED_MAPPING_MASK			GENMASK(2, 0)
> >> +#define LAN0_PHY_LED_MAP(_n)			FIELD_PREP_CONST(LAN0_LED_MAPPING_MASK, (_n))
> >> +
> >> +/* CONF */
> >> +#define REG_I2C_SDA_E2				0x001c
> >> +#define AN7583_I2C1_SCL_E2_MASK			BIT(16)
> >> +#define AN7583_I2C1_SDA_E2_MASK			BIT(15)
> >> +#define SPI_MISO_E2_MASK			BIT(14)
> >> +#define SPI_MOSI_E2_MASK			BIT(13)
> >> +#define SPI_CLK_E2_MASK				BIT(12)
> >> +#define SPI_CS0_E2_MASK				BIT(11)
> >> +#define PCIE1_RESET_E2_MASK			BIT(9)
> >> +#define PCIE0_RESET_E2_MASK			BIT(8)
> >> +#define AN7583_MDIO_0_E2_MASK			BIT(5)
> >> +#define AN7583_MDC_0_E2_MASK			BIT(4)
> >> +#define UART1_RXD_E2_MASK			BIT(3)
> >> +#define UART1_TXD_E2_MASK			BIT(2)
> >> +#define I2C_SCL_E2_MASK				BIT(1)
> >> +#define I2C_SDA_E2_MASK				BIT(0)
> >> +
> >> +#define REG_I2C_SDA_E4				0x0020
> >> +#define AN7583_I2C1_SCL_E4_MASK			BIT(16)
> >> +#define AN7583_I2C1_SDA_E4_MASK			BIT(15)
> >> +#define SPI_MISO_E4_MASK			BIT(14)
> >> +#define SPI_MOSI_E4_MASK			BIT(13)
> >> +#define SPI_CLK_E4_MASK				BIT(12)
> >> +#define SPI_CS0_E4_MASK				BIT(11)
> >> +#define PCIE1_RESET_E4_MASK			BIT(9)
> >> +#define PCIE0_RESET_E4_MASK			BIT(8)
> >> +#define AN7583_MDIO_0_E4_MASK			BIT(5)
> >> +#define AN7583_MDC_0_E4_MASK			BIT(4)
> >> +#define UART1_RXD_E4_MASK			BIT(3)
> >> +#define UART1_TXD_E4_MASK			BIT(2)
> >> +#define I2C_SCL_E4_MASK				BIT(1)
> >> +#define I2C_SDA_E4_MASK				BIT(0)
> >> +
> >> +#define REG_GPIO_L_E2				0x0024
> >> +#define REG_GPIO_L_E4				0x0028
> >> +#define REG_GPIO_H_E2				0x002c
> >> +#define REG_GPIO_H_E4				0x0030
> >> +
> >> +#define REG_I2C_SDA_PU				0x0044
> >> +#define AN7583_I2C1_SCL_PU_MASK			BIT(16)
> >> +#define AN7583_I2C1_SDA_PU_MASK			BIT(15)
> >> +#define SPI_MISO_PU_MASK			BIT(14)
> >> +#define SPI_MOSI_PU_MASK			BIT(13)
> >> +#define SPI_CLK_PU_MASK				BIT(12)
> >> +#define SPI_CS0_PU_MASK				BIT(11)
> >> +#define PCIE1_RESET_PU_MASK			BIT(9)
> >> +#define PCIE0_RESET_PU_MASK			BIT(8)
> >> +#define AN7583_MDIO_0_PU_MASK			BIT(5)
> >> +#define AN7583_MDC_0_PU_MASK			BIT(4)
> >> +#define UART1_RXD_PU_MASK			BIT(3)
> >> +#define UART1_TXD_PU_MASK			BIT(2)
> >> +#define I2C_SCL_PU_MASK				BIT(1)
> >> +#define I2C_SDA_PU_MASK				BIT(0)
> >> +
> >> +#define REG_I2C_SDA_PD				0x0048
> >> +#define AN7583_I2C1_SCL_PD_MASK			BIT(16)
> >> +#define AN7583_I2C1_SDA_PD_MASK			BIT(15)
> >> +#define SPI_MISO_PD_MASK			BIT(14)
> >> +#define SPI_MOSI_PD_MASK			BIT(13)
> >> +#define SPI_CLK_PD_MASK				BIT(12)
> >> +#define SPI_CS0_PD_MASK				BIT(11)
> >> +#define PCIE1_RESET_PD_MASK			BIT(9)
> >> +#define PCIE0_RESET_PD_MASK			BIT(8)
> >> +#define AN7583_MDIO_0_PD_MASK			BIT(5)
> >> +#define AN7583_MDC_0_PD_MASK			BIT(4)
> >> +#define UART1_RXD_PD_MASK			BIT(3)
> >> +#define UART1_TXD_PD_MASK			BIT(2)
> >> +#define I2C_SCL_PD_MASK				BIT(1)
> >> +#define I2C_SDA_PD_MASK				BIT(0)
> >> +
> >> +#define REG_GPIO_L_PU				0x004c
> >> +#define REG_GPIO_L_PD				0x0050
> >> +#define REG_GPIO_H_PU				0x0054
> >> +#define REG_GPIO_H_PD				0x0058
> >> +
> >> +#define REG_PCIE_RESET_OD			0x018c
> >> +#define PCIE1_RESET_OD_MASK			BIT(1)
> >> +#define PCIE0_RESET_OD_MASK			BIT(0)
> >> +
> >> +/* PWM MODE CONF */
> >> +#define REG_GPIO_FLASH_MODE_CFG			0x0034
> >> +#define GPIO15_FLASH_MODE_CFG			BIT(15)
> >> +#define GPIO14_FLASH_MODE_CFG			BIT(14)
> >> +#define GPIO13_FLASH_MODE_CFG			BIT(13)
> >> +#define GPIO12_FLASH_MODE_CFG			BIT(12)
> >> +#define GPIO11_FLASH_MODE_CFG			BIT(11)
> >> +#define GPIO10_FLASH_MODE_CFG			BIT(10)
> >> +#define GPIO9_FLASH_MODE_CFG			BIT(9)
> >> +#define GPIO8_FLASH_MODE_CFG			BIT(8)
> >> +#define GPIO7_FLASH_MODE_CFG			BIT(7)
> >> +#define GPIO6_FLASH_MODE_CFG			BIT(6)
> >> +#define GPIO5_FLASH_MODE_CFG			BIT(5)
> >> +#define GPIO4_FLASH_MODE_CFG			BIT(4)
> >> +#define GPIO3_FLASH_MODE_CFG			BIT(3)
> >> +#define GPIO2_FLASH_MODE_CFG			BIT(2)
> >> +#define GPIO1_FLASH_MODE_CFG			BIT(1)
> >> +#define GPIO0_FLASH_MODE_CFG			BIT(0)
> >> +
> >> +/* PWM MODE CONF EXT */
> >> +#define REG_GPIO_FLASH_MODE_CFG_EXT		0x0068
> >> +#define GPIO51_FLASH_MODE_CFG			BIT(31)
> >> +#define GPIO50_FLASH_MODE_CFG			BIT(30)
> >> +#define GPIO49_FLASH_MODE_CFG			BIT(29)
> >> +#define GPIO48_FLASH_MODE_CFG			BIT(28)
> >> +#define GPIO47_FLASH_MODE_CFG			BIT(27)
> >> +#define GPIO46_FLASH_MODE_CFG			BIT(26)
> >> +#define GPIO45_FLASH_MODE_CFG			BIT(25)
> >> +#define GPIO44_FLASH_MODE_CFG			BIT(24)
> >> +#define GPIO43_FLASH_MODE_CFG			BIT(23)
> >> +#define GPIO42_FLASH_MODE_CFG			BIT(22)
> >> +#define GPIO41_FLASH_MODE_CFG			BIT(21)
> >> +#define GPIO40_FLASH_MODE_CFG			BIT(20)
> >> +#define GPIO39_FLASH_MODE_CFG			BIT(19)
> >> +#define GPIO38_FLASH_MODE_CFG			BIT(18)
> >> +#define GPIO37_FLASH_MODE_CFG			BIT(17)
> >> +#define GPIO36_FLASH_MODE_CFG			BIT(16)
> >> +#define GPIO31_FLASH_MODE_CFG			BIT(15)
> >> +#define GPIO30_FLASH_MODE_CFG			BIT(14)
> >> +#define GPIO29_FLASH_MODE_CFG			BIT(13)
> >> +#define GPIO28_FLASH_MODE_CFG			BIT(12)
> >> +#define GPIO27_FLASH_MODE_CFG			BIT(11)
> >> +#define GPIO26_FLASH_MODE_CFG			BIT(10)
> >> +#define GPIO25_FLASH_MODE_CFG			BIT(9)
> >> +#define GPIO24_FLASH_MODE_CFG			BIT(8)
> >> +#define GPIO23_FLASH_MODE_CFG			BIT(7)
> >> +#define GPIO22_FLASH_MODE_CFG			BIT(6)
> >> +#define GPIO21_FLASH_MODE_CFG			BIT(5)
> >> +#define GPIO20_FLASH_MODE_CFG			BIT(4)
> >> +#define GPIO19_FLASH_MODE_CFG			BIT(3)
> >> +#define GPIO18_FLASH_MODE_CFG			BIT(2)
> >> +#define GPIO17_FLASH_MODE_CFG			BIT(1)
> >> +#define GPIO16_FLASH_MODE_CFG			BIT(0)
> >> +
> >> +#define AIROHA_PINCTRL_GPIO(gpio, mux_val)			\
> >> +	{							\
> >> +		.name = (gpio),					\
> >> +		.regmap[0] = {					\
> >> +			AIROHA_FUNC_MUX,			\
> >> +			REG_GPIO_PON_MODE,			\
> >> +			(mux_val),				\
> >> +			(mux_val)				\
> >> +		},						\
> >> +		.regmap_size = 1,				\
> >> +	}
> >> +
> >> +#define AIROHA_PINCTRL_GPIO_EXT(gpio, mux_val, smux_val)	\
> >> +	{							\
> >> +		.name = (gpio),					\
> >> +		.regmap[0] = {					\
> >> +			AIROHA_FUNC_PWM_EXT_MUX,		\
> >> +			REG_GPIO_FLASH_MODE_CFG_EXT,		\
> >> +			(mux_val),				\
> >> +			0					\
> >> +		},						\
> >> +		.regmap[1] = {					\
> >> +			AIROHA_FUNC_MUX,			\
> >> +			REG_GPIO_PON_MODE,			\
> >> +			(smux_val),				\
> >> +			(smux_val)				\
> >> +		},						\
> >> +		.regmap_size = 2,				\
> >> +	}
> >> +
> >> +/* PWM */
> >> +#define AIROHA_PINCTRL_PWM(gpio, mux_val)			\
> >> +	{							\
> >> +		.name = (gpio),					\
> >> +		.regmap[0] = {					\
> >> +			AIROHA_FUNC_PWM_MUX,			\
> >> +			REG_GPIO_FLASH_MODE_CFG,		\
> >> +			(mux_val),				\
> >> +			(mux_val)				\
> >> +		},						\
> >> +		.regmap_size = 1,				\
> >> +	}
> >> +
> >> +#define AIROHA_PINCTRL_PWM_EXT(gpio, mux_val)			\
> >> +	{							\
> >> +		.name = (gpio),					\
> >> +		.regmap[0] = {					\
> >> +			AIROHA_FUNC_PWM_EXT_MUX,		\
> >> +			REG_GPIO_FLASH_MODE_CFG_EXT,		\
> >> +			(mux_val),				\
> >> +			(mux_val)				\
> >> +		},						\
> >> +		.regmap_size = 1,				\
> >> +	}
> >> +
> >> +#define AIROHA_PINCTRL_PWM_EXT_SEC(gpio, mux_val, smux_val)	\
> >> +	{							\
> >> +		.name = (gpio),					\
> >> +		.regmap[0] = {					\
> >> +			AIROHA_FUNC_PWM_EXT_MUX,		\
> >> +			REG_GPIO_FLASH_MODE_CFG_EXT,		\
> >> +			(mux_val),				\
> >> +			(mux_val)				\
> >> +		},						\
> >> +		.regmap[1] = {					\
> >> +			AIROHA_FUNC_MUX,			\
> >> +			REG_GPIO_PON_MODE,			\
> >> +			(smux_val),				\
> >> +			(smux_val)				\
> >> +		},						\
> >> +		.regmap_size = 2,				\
> >> +	}
> >> +
> >> +#define AIROHA_PINCTRL_PHY_LED0(gpio, mux_val, map_mask, map_val)	\
> >> +	{								\
> >> +		.name = (gpio),						\
> >> +		.regmap[0] = {						\
> >> +			AIROHA_FUNC_MUX,				\
> >> +			REG_GPIO_2ND_I2C_MODE,				\
> >> +			(mux_val),					\
> >> +			(mux_val),					\
> >> +		},							\
> >> +		.regmap[1] = {						\
> >> +			AIROHA_FUNC_MUX,				\
> >> +			REG_LAN_LED0_MAPPING,				\
> >> +			(map_mask),					\
> >> +			(map_val),					\
> >> +		},							\
> >> +		.regmap_size = 2,					\
> >> +	}
> >> +
> >> +#define AIROHA_PINCTRL_PHY_LED1(gpio, mux_val, map_mask, map_val)	\
> >> +	{								\
> >> +		.name = (gpio),						\
> >> +		.regmap[0] = {						\
> >> +			AIROHA_FUNC_MUX,				\
> >> +			REG_GPIO_2ND_I2C_MODE,				\
> >> +			(mux_val),					\
> >> +			(mux_val),					\
> >> +		},							\
> >> +		.regmap[1] = {						\
> >> +			AIROHA_FUNC_MUX,				\
> >> +			REG_LAN_LED1_MAPPING,				\
> >> +			(map_mask),					\
> >> +			(map_val),					\
> >> +		},							\
> >> +		.regmap_size = 2,					\
> >> +	}
> >> +
> >> +static struct pinctrl_pin_desc an7583_pinctrl_pins[] = {
> >> +	PINCTRL_PIN(2, "gpio0"),
> >> +	PINCTRL_PIN(3, "gpio1"),
> >> +	PINCTRL_PIN(4, "gpio2"),
> >> +	PINCTRL_PIN(5, "gpio3"),
> >> +	PINCTRL_PIN(6, "gpio4"),
> >> +	PINCTRL_PIN(7, "gpio5"),
> >> +	PINCTRL_PIN(8, "gpio6"),
> >> +	PINCTRL_PIN(9, "gpio7"),
> >> +	PINCTRL_PIN(10, "gpio8"),
> >> +	PINCTRL_PIN(11, "gpio9"),
> >> +	PINCTRL_PIN(12, "gpio10"),
> >> +	PINCTRL_PIN(13, "gpio11"),
> >> +	PINCTRL_PIN(14, "gpio12"),
> >> +	PINCTRL_PIN(15, "gpio13"),
> >> +	PINCTRL_PIN(16, "gpio14"),
> >> +	PINCTRL_PIN(17, "gpio15"),
> >> +	PINCTRL_PIN(18, "gpio16"),
> >> +	PINCTRL_PIN(19, "gpio17"),
> >> +	PINCTRL_PIN(20, "gpio18"),
> >> +	PINCTRL_PIN(21, "gpio19"),
> >> +	PINCTRL_PIN(22, "gpio20"),
> >> +	PINCTRL_PIN(23, "gpio21"),
> >> +	PINCTRL_PIN(24, "gpio22"),
> >> +	PINCTRL_PIN(25, "gpio23"),
> >> +	PINCTRL_PIN(26, "gpio24"),
> >> +	PINCTRL_PIN(27, "gpio25"),
> >> +	PINCTRL_PIN(28, "gpio26"),
> >> +	PINCTRL_PIN(29, "gpio27"),
> >> +	PINCTRL_PIN(30, "gpio28"),
> >> +	PINCTRL_PIN(31, "gpio29"),
> >> +	PINCTRL_PIN(32, "gpio30"),
> >> +	PINCTRL_PIN(33, "gpio31"),
> >> +	PINCTRL_PIN(34, "gpio32"),
> >> +	PINCTRL_PIN(35, "gpio33"),
> >> +	PINCTRL_PIN(36, "gpio34"),
> >> +	PINCTRL_PIN(37, "gpio35"),
> >> +	PINCTRL_PIN(38, "gpio36"),
> >> +	PINCTRL_PIN(39, "gpio37"),
> >> +	PINCTRL_PIN(40, "gpio38"),
> >> +	PINCTRL_PIN(41, "i2c0_scl"),
> >> +	PINCTRL_PIN(42, "i2c0_sda"),
> >> +	PINCTRL_PIN(43, "i2c1_scl"),
> >> +	PINCTRL_PIN(44, "i2c1_sda"),
> >> +	PINCTRL_PIN(45, "spi_clk"),
> >> +	PINCTRL_PIN(46, "spi_cs"),
> >> +	PINCTRL_PIN(47, "spi_mosi"),
> >> +	PINCTRL_PIN(48, "spi_miso"),
> >> +	PINCTRL_PIN(49, "uart_txd"),
> >> +	PINCTRL_PIN(50, "uart_rxd"),
> >> +	PINCTRL_PIN(51, "pcie_reset0"),
> >> +	PINCTRL_PIN(52, "pcie_reset1"),
> >> +	PINCTRL_PIN(53, "mdc_0"),
> >> +	PINCTRL_PIN(54, "mdio_0"),
> >> +};
> >> +
> >> +static const int an7583_pon_pins[] = { 15, 16, 17, 18, 19, 20 };
> >> +static const int an7583_pon_tod_1pps_pins[] = { 32 };
> >> +static const int an7583_gsw_tod_1pps_pins[] = { 32 };
> >> +static const int an7583_sipo_pins[] = { 34, 35 };
> >> +static const int an7583_sipo_rclk_pins[] = { 34, 35, 33 };
> >> +static const int an7583_mdio_pins[] = { 43, 44 };
> >> +static const int an7583_uart2_pins[] = { 34, 35 };
> >> +static const int an7583_uart2_cts_rts_pins[] = { 32, 33 };
> >> +static const int an7583_hsuart_pins[] = { 30, 31 };
> >> +static const int an7583_hsuart_cts_rts_pins[] = { 28, 29 };
> >> +static const int an7583_npu_uart_pins[] = { 7, 8 };
> >> +static const int an7583_uart4_pins[] = { 7, 8 };
> >> +static const int an7583_uart5_pins[] = { 23, 24 };
> >> +static const int an7583_i2c0_pins[] = { 41, 42 };
> >> +static const int an7583_i2c1_pins[] = { 43, 44 };
> >> +static const int an7583_jtag_udi_pins[] = { 23, 24, 22, 25, 26 };
> >> +static const int an7583_jtag_dfd_pins[] = { 23, 24, 22, 25, 26 };
> >> +static const int an7583_pcm1_pins[] = { 10, 11, 12, 13, 14 };
> >> +static const int an7583_pcm2_pins[] = { 28, 29, 30, 31, 24 };
> >> +static const int an7583_spi_pins[] = { 28, 29, 30, 31 };
> >> +static const int an7583_spi_quad_pins[] = { 25, 26 };
> >> +static const int an7583_spi_cs1_pins[] = { 27 };
> >> +static const int an7583_pcm_spi_pins[] = { 28, 29, 30, 31, 10, 11, 12, 13 };
> >> +static const int an7583_pcm_spi_rst_pins[] = { 14 };
> >> +static const int an7583_pcm_spi_cs1_pins[] = { 24 };
> >> +static const int an7583_emmc_pins[] = {
> >> +	7, 8, 9, 22, 23, 24, 25, 26, 45, 46, 47
> >> +};
> >> +static const int an7583_pnand_pins[] = {
> >> +	7, 8, 9, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 45, 46, 47, 48
> >> +};
> >> +static const int an7583_gpio0_pins[] = { 2 };
> >> +static const int an7583_gpio1_pins[] = { 3 };
> >> +static const int an7583_gpio2_pins[] = { 4 };
> >> +static const int an7583_gpio3_pins[] = { 5 };
> >> +static const int an7583_gpio4_pins[] = { 6 };
> >> +static const int an7583_gpio5_pins[] = { 7 };
> >> +static const int an7583_gpio6_pins[] = { 8 };
> >> +static const int an7583_gpio7_pins[] = { 9 };
> >> +static const int an7583_gpio8_pins[] = { 10 };
> >> +static const int an7583_gpio9_pins[] = { 11 };
> >> +static const int an7583_gpio10_pins[] = { 12 };
> >> +static const int an7583_gpio11_pins[] = { 13 };
> >> +static const int an7583_gpio12_pins[] = { 14 };
> >> +static const int an7583_gpio13_pins[] = { 15 };
> >> +static const int an7583_gpio14_pins[] = { 16 };
> >> +static const int an7583_gpio15_pins[] = { 17 };
> >> +static const int an7583_gpio16_pins[] = { 18 };
> >> +static const int an7583_gpio17_pins[] = { 19 };
> >> +static const int an7583_gpio18_pins[] = { 20 };
> >> +static const int an7583_gpio19_pins[] = { 21 };
> >> +static const int an7583_gpio20_pins[] = { 22 };
> >> +static const int an7583_gpio21_pins[] = { 23 };
> >> +static const int an7583_gpio22_pins[] = { 24 };
> >> +static const int an7583_gpio23_pins[] = { 25 };
> >> +static const int an7583_gpio24_pins[] = { 26 };
> >> +static const int an7583_gpio25_pins[] = { 27 };
> >> +static const int an7583_gpio26_pins[] = { 28 };
> >> +static const int an7583_gpio27_pins[] = { 29 };
> >> +static const int an7583_gpio28_pins[] = { 30 };
> >> +static const int an7583_gpio29_pins[] = { 31 };
> >> +static const int an7583_gpio30_pins[] = { 32 };
> >> +static const int an7583_gpio31_pins[] = { 33 };
> >> +static const int an7583_gpio32_pins[] = { 34 };
> >> +static const int an7583_gpio33_pins[] = { 35 };
> >> +static const int an7583_gpio34_pins[] = { 36 };
> >> +static const int an7583_gpio35_pins[] = { 37 };
> >> +static const int an7583_gpio36_pins[] = { 38 };
> >> +static const int an7583_gpio37_pins[] = { 39 };
> >> +static const int an7583_gpio38_pins[] = { 40 };
> >> +static const int an7583_gpio39_pins[] = { 41 };
> >> +static const int an7583_gpio40_pins[] = { 42 };
> >> +static const int an7583_gpio41_pins[] = { 43 };
> >> +static const int an7583_gpio42_pins[] = { 44 };
> >> +static const int an7583_gpio43_pins[] = { 45 };
> >> +static const int an7583_gpio44_pins[] = { 46 };
> >> +static const int an7583_gpio45_pins[] = { 47 };
> >> +static const int an7583_gpio46_pins[] = { 48 };
> >> +static const int an7583_gpio47_pins[] = { 49 };
> >> +static const int an7583_gpio48_pins[] = { 50 };
> >> +static const int an7583_gpio49_pins[] = { 51 };
> >> +static const int an7583_gpio50_pins[] = { 52 };
> >> +static const int an7583_gpio51_pins[] = { 53 };
> >> +static const int an7583_gpio52_pins[] = { 54 };
> >> +static const int an7583_pcie_reset0_pins[] = { 51 };
> >> +static const int an7583_pcie_reset1_pins[] = { 52 };
> >> +
> >> +static const struct pingroup an7583_pinctrl_groups[] = {
> >> +	PINCTRL_PIN_GROUP("pon", an7583_pon),
> >> +	PINCTRL_PIN_GROUP("pon_tod_1pps", an7583_pon_tod_1pps),
> >> +	PINCTRL_PIN_GROUP("gsw_tod_1pps", an7583_gsw_tod_1pps),
> >> +	PINCTRL_PIN_GROUP("sipo", an7583_sipo),
> >> +	PINCTRL_PIN_GROUP("sipo_rclk", an7583_sipo_rclk),
> >> +	PINCTRL_PIN_GROUP("mdio", an7583_mdio),
> >> +	PINCTRL_PIN_GROUP("uart2", an7583_uart2),
> >> +	PINCTRL_PIN_GROUP("uart2_cts_rts", an7583_uart2_cts_rts),
> >> +	PINCTRL_PIN_GROUP("hsuart", an7583_hsuart),
> >> +	PINCTRL_PIN_GROUP("hsuart_cts_rts", an7583_hsuart_cts_rts),
> >> +	PINCTRL_PIN_GROUP("npu_uart", an7583_npu_uart),
> >> +	PINCTRL_PIN_GROUP("uart4", an7583_uart4),
> >> +	PINCTRL_PIN_GROUP("uart5", an7583_uart5),
> >> +	PINCTRL_PIN_GROUP("i2c0", an7583_i2c0),
> >> +	PINCTRL_PIN_GROUP("i2c1", an7583_i2c1),
> >> +	PINCTRL_PIN_GROUP("jtag_udi", an7583_jtag_udi),
> >> +	PINCTRL_PIN_GROUP("jtag_dfd", an7583_jtag_dfd),
> >> +	PINCTRL_PIN_GROUP("pcm1", an7583_pcm1),
> >> +	PINCTRL_PIN_GROUP("pcm2", an7583_pcm2),
> >> +	PINCTRL_PIN_GROUP("spi", an7583_spi),
> >> +	PINCTRL_PIN_GROUP("spi_quad", an7583_spi_quad),
> >> +	PINCTRL_PIN_GROUP("spi_cs1", an7583_spi_cs1),
> >> +	PINCTRL_PIN_GROUP("pcm_spi", an7583_pcm_spi),
> >> +	PINCTRL_PIN_GROUP("pcm_spi_rst", an7583_pcm_spi_rst),
> >> +	PINCTRL_PIN_GROUP("pcm_spi_cs1", an7583_pcm_spi_cs1),
> >> +	PINCTRL_PIN_GROUP("emmc", an7583_emmc),
> >> +	PINCTRL_PIN_GROUP("pnand", an7583_pnand),
> >> +	PINCTRL_PIN_GROUP("gpio0", an7583_gpio0),
> >> +	PINCTRL_PIN_GROUP("gpio1", an7583_gpio1),
> >> +	PINCTRL_PIN_GROUP("gpio2", an7583_gpio2),
> >> +	PINCTRL_PIN_GROUP("gpio3", an7583_gpio3),
> >> +	PINCTRL_PIN_GROUP("gpio4", an7583_gpio4),
> >> +	PINCTRL_PIN_GROUP("gpio5", an7583_gpio5),
> >> +	PINCTRL_PIN_GROUP("gpio6", an7583_gpio6),
> >> +	PINCTRL_PIN_GROUP("gpio7", an7583_gpio7),
> >> +	PINCTRL_PIN_GROUP("gpio8", an7583_gpio8),
> >> +	PINCTRL_PIN_GROUP("gpio9", an7583_gpio9),
> >> +	PINCTRL_PIN_GROUP("gpio10", an7583_gpio10),
> >> +	PINCTRL_PIN_GROUP("gpio11", an7583_gpio11),
> >> +	PINCTRL_PIN_GROUP("gpio12", an7583_gpio12),
> >> +	PINCTRL_PIN_GROUP("gpio13", an7583_gpio13),
> >> +	PINCTRL_PIN_GROUP("gpio14", an7583_gpio14),
> >> +	PINCTRL_PIN_GROUP("gpio15", an7583_gpio15),
> >> +	PINCTRL_PIN_GROUP("gpio16", an7583_gpio16),
> >> +	PINCTRL_PIN_GROUP("gpio17", an7583_gpio17),
> >> +	PINCTRL_PIN_GROUP("gpio18", an7583_gpio18),
> >> +	PINCTRL_PIN_GROUP("gpio19", an7583_gpio19),
> >> +	PINCTRL_PIN_GROUP("gpio20", an7583_gpio20),
> >> +	PINCTRL_PIN_GROUP("gpio21", an7583_gpio21),
> >> +	PINCTRL_PIN_GROUP("gpio22", an7583_gpio22),
> >> +	PINCTRL_PIN_GROUP("gpio23", an7583_gpio23),
> >> +	PINCTRL_PIN_GROUP("gpio24", an7583_gpio24),
> >> +	PINCTRL_PIN_GROUP("gpio25", an7583_gpio25),
> >> +	PINCTRL_PIN_GROUP("gpio26", an7583_gpio26),
> >> +	PINCTRL_PIN_GROUP("gpio27", an7583_gpio27),
> >> +	PINCTRL_PIN_GROUP("gpio28", an7583_gpio28),
> >> +	PINCTRL_PIN_GROUP("gpio29", an7583_gpio29),
> >> +	PINCTRL_PIN_GROUP("gpio30", an7583_gpio30),
> >> +	PINCTRL_PIN_GROUP("gpio31", an7583_gpio31),
> >> +	PINCTRL_PIN_GROUP("gpio32", an7583_gpio32),
> >> +	PINCTRL_PIN_GROUP("gpio33", an7583_gpio33),
> >> +	PINCTRL_PIN_GROUP("gpio34", an7583_gpio34),
> >> +	PINCTRL_PIN_GROUP("gpio35", an7583_gpio35),
> >> +	PINCTRL_PIN_GROUP("gpio36", an7583_gpio36),
> >> +	PINCTRL_PIN_GROUP("gpio37", an7583_gpio37),
> >> +	PINCTRL_PIN_GROUP("gpio38", an7583_gpio38),
> >> +	PINCTRL_PIN_GROUP("gpio39", an7583_gpio39),
> >> +	PINCTRL_PIN_GROUP("gpio40", an7583_gpio40),
> >> +	PINCTRL_PIN_GROUP("gpio41", an7583_gpio41),
> >> +	PINCTRL_PIN_GROUP("gpio42", an7583_gpio42),
> >> +	PINCTRL_PIN_GROUP("gpio43", an7583_gpio43),
> >> +	PINCTRL_PIN_GROUP("gpio44", an7583_gpio44),
> >> +	PINCTRL_PIN_GROUP("gpio45", an7583_gpio45),
> >> +	PINCTRL_PIN_GROUP("gpio46", an7583_gpio46),
> >> +	PINCTRL_PIN_GROUP("gpio47", an7583_gpio47),
> >> +	PINCTRL_PIN_GROUP("gpio48", an7583_gpio48),
> >> +	PINCTRL_PIN_GROUP("gpio49", an7583_gpio49),
> >> +	PINCTRL_PIN_GROUP("gpio50", an7583_gpio50),
> >> +	PINCTRL_PIN_GROUP("gpio51", an7583_gpio51),
> >> +	PINCTRL_PIN_GROUP("gpio52", an7583_gpio52),
> >> +	PINCTRL_PIN_GROUP("pcie_reset0", an7583_pcie_reset0),
> >> +	PINCTRL_PIN_GROUP("pcie_reset1", an7583_pcie_reset1),
> >> +};
> >> +
> >> +static const char *const pon_groups[] = { "pon" };
> >> +static const char *const tod_1pps_groups[] = {
> >> +	"pon_tod_1pps", "gsw_tod_1pps"
> >> +};
> >> +static const char *const sipo_groups[] = { "sipo", "sipo_rclk" };
> >> +static const char *const an7583_mdio_groups[] = { "mdio" };
> >> +static const char *const uart_groups[] = {
> >> +	"uart2", "uart2_cts_rts", "hsuart", "hsuart_cts_rts",
> >> +	"uart4", "uart5"
> >> +};
> >> +static const char *const jtag_groups[] = { "jtag_udi", "jtag_dfd" };
> >> +static const char *const pcm_groups[] = { "pcm1", "pcm2" };
> >> +static const char *const spi_groups[] = { "spi_quad", "spi_cs1" };
> >> +static const char *const an7583_pcm_spi_groups[] = {
> >> +	"pcm_spi", "pcm_spi_rst", "pcm_spi_cs1"
> >> +};
> >> +static const char *const emmc_groups[] = { "emmc" };
> >> +static const char *const pnand_groups[] = { "pnand" };
> >> +static const char *const an7583_gpio_groups[] = {
> >> +	"gpio39", "gpio40", "gpio41", "gpio42", "gpio43",
> >> +	"gpio44", "gpio45", "gpio46", "gpio47", "gpio48",
> >> +	"gpio49", "gpio50", "gpio51", "gpio52"
> >> +};
> >> +static const char *const an7583_pcie_reset_groups[] = {
> >> +	"pcie_reset0", "pcie_reset1"
> >> +};
> >> +static const char *const an7583_pwm_groups[] = {
> >> +	"gpio0",  "gpio1",  "gpio2",  "gpio3",  "gpio4",  "gpio5",
> >> +	"gpio6",  "gpio7",  "gpio8",  "gpio9",  "gpio10", "gpio11",
> >> +	"gpio12", "gpio13", "gpio14", "gpio15", "gpio16", "gpio17",
> >> +	"gpio18", "gpio19", "gpio20", "gpio21", "gpio22", "gpio23",
> >> +	"gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29",
> >> +	"gpio30", "gpio31", "gpio36", "gpio37", "gpio38", "gpio39",
> >> +	"gpio40", "gpio41", "gpio42", "gpio43", "gpio44", "gpio45",
> >> +	"gpio46", "gpio47", "gpio48", "gpio49", "gpio50", "gpio51"
> >> +};
> >> +static const char *const an7583_phy1_led0_groups[] = {
> >> +	"gpio1", "gpio2", "gpio3", "gpio4"
> >> +};
> >> +static const char *const an7583_phy2_led0_groups[] = {
> >> +	"gpio1", "gpio2", "gpio3", "gpio4"
> >> +};
> >> +static const char *const an7583_phy3_led0_groups[] = {
> >> +	"gpio1", "gpio2", "gpio3", "gpio4"
> >> +};
> >> +static const char *const an7583_phy4_led0_groups[] = {
> >> +	"gpio1", "gpio2", "gpio3", "gpio4"
> >> +};
> >> +static const char *const an7583_phy1_led1_groups[] = {
> >> +	"gpio8", "gpio9", "gpio10", "gpio11"
> >> +};
> >> +static const char *const an7583_phy2_led1_groups[] = {
> >> +	"gpio8", "gpio9", "gpio10", "gpio11"
> >> +};
> >> +static const char *const an7583_phy3_led1_groups[] = {
> >> +	"gpio8", "gpio9", "gpio10", "gpio11"
> >> +};
> >> +static const char *const an7583_phy4_led1_groups[] = {
> >> +	"gpio8", "gpio9", "gpio10", "gpio11"
> >> +};
> >> +
> >> +static const struct airoha_pinctrl_func_group pon_func_group[] = {
> >> +	{
> >> +		.name = "pon",
> >> +		.regmap[0] = {
> >> +			AIROHA_FUNC_MUX,
> >> +			REG_GPIO_PON_MODE,
> >> +			GPIO_PON_MODE_MASK,
> >> +			GPIO_PON_MODE_MASK
> >> +		},
> >> +		.regmap_size = 1,
> >> +	},
> >> +};
> >> +
> >> +static const struct airoha_pinctrl_func_group tod_1pps_func_group[] = {
> >> +	{
> >> +		.name = "pon_tod_1pps",
> >> +		.regmap[0] = {
> >> +			AIROHA_FUNC_MUX,
> >> +			REG_GPIO_2ND_I2C_MODE,
> >> +			PON_TOD_1PPS_MODE_MASK,
> >> +			PON_TOD_1PPS_MODE_MASK
> >> +		},
> >> +		.regmap_size = 1,
> >> +	}, {
> >> +		.name = "gsw_tod_1pps",
> >> +		.regmap[0] = {
> >> +			AIROHA_FUNC_MUX,
> >> +			REG_GPIO_2ND_I2C_MODE,
> >> +			GSW_TOD_1PPS_MODE_MASK,
> >> +			GSW_TOD_1PPS_MODE_MASK
> >> +		},
> >> +		.regmap_size = 1,
> >> +	},
> >> +};
> >> +
> >> +static const struct airoha_pinctrl_func_group sipo_func_group[] = {
> >> +	{
> >> +		.name = "sipo",
> >> +		.regmap[0] = {
> >> +			AIROHA_FUNC_MUX,
> >> +			REG_GPIO_PON_MODE,
> >> +			GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK,
> >> +			GPIO_SIPO_MODE_MASK
> >> +		},
> >> +		.regmap_size = 1,
> >> +	}, {
> >> +		.name = "sipo_rclk",
> >> +		.regmap[0] = {
> >> +			AIROHA_FUNC_MUX,
> >> +			REG_GPIO_PON_MODE,
> >> +			GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK,
> >> +			GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK
> >> +		},
> >> +		.regmap_size = 1,
> >> +	},
> >> +};
> >> +
> >> +static const struct airoha_pinctrl_func_group an7583_mdio_func_group[] = {
> >> +	{
> >> +		.name = "mdio",
> >> +		.regmap[0] = {
> >> +			AIROHA_FUNC_MUX,
> >> +			REG_GPIO_PON_MODE,
> >> +			GPIO_SGMII_MDIO_MODE_MASK,
> >> +			GPIO_SGMII_MDIO_MODE_MASK
> >> +		},
> >> +		.regmap[1] = {
> >> +			AIROHA_FUNC_MUX,
> >> +			REG_GPIO_SPI_CS1_MODE,
> >> +			GPIO_MDC_IO_MASTER_MODE_MASK,
> >> +			GPIO_MDC_IO_MASTER_MODE_MASK
> >> +		},
> >> +		.regmap_size = 2,
> >> +	},
> >> +};
> >> +
> >> +static const struct airoha_pinctrl_func_group uart_func_group[] = {
> >> +	{
> >> +		.name = "uart2",
> >> +		.regmap[0] = {
> >> +			AIROHA_FUNC_MUX,
> >> +			REG_GPIO_PON_MODE,
> >> +			GPIO_UART2_MODE_MASK,
> >> +			GPIO_UART2_MODE_MASK
> >> +		},
> >> +		.regmap_size = 1,
> >> +	}, {
> >> +		.name = "uart2_cts_rts",
> >> +		.regmap[0] = {
> >> +			AIROHA_FUNC_MUX,
> >> +			REG_GPIO_PON_MODE,
> >> +			GPIO_UART2_MODE_MASK | GPIO_UART2_CTS_RTS_MODE_MASK,
> >> +			GPIO_UART2_MODE_MASK | GPIO_UART2_CTS_RTS_MODE_MASK
> >> +		},
> >> +		.regmap_size = 1,
> >> +	}, {
> >> +		.name = "hsuart",
> >> +		.regmap[0] = {
> >> +			AIROHA_FUNC_MUX,
> >> +			REG_GPIO_PON_MODE,
> >> +			GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK,
> >> +			GPIO_HSUART_MODE_MASK
> >> +		},
> >> +		.regmap_size = 1,
> >> +	},
> >> +	{
> >> +		.name = "hsuart_cts_rts",
> >> +		.regmap[0] = {
> >> +			AIROHA_FUNC_MUX,
> >> +			REG_GPIO_PON_MODE,
> >> +			GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK,
> >> +			GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK
> >> +		},
> >> +		.regmap_size = 1,
> >> +	}, {
> >> +		.name = "uart4",
> >> +		.regmap[0] = {
> >> +			AIROHA_FUNC_MUX,
> >> +			REG_GPIO_PON_MODE,
> >> +			GPIO_UART4_MODE_MASK,
> >> +			GPIO_UART4_MODE_MASK
> >> +		},
> >> +		.regmap_size = 1,
> >> +	}, {
> >> +		.name = "uart5",
> >> +		.regmap[0] = {
> >> +			AIROHA_FUNC_MUX,
> >> +			REG_GPIO_PON_MODE,
> >> +			GPIO_UART5_MODE_MASK,
> >> +			GPIO_UART5_MODE_MASK
> >> +		},
> >> +		.regmap_size = 1,
> >> +	},
> >> +};
> >> +
> >> +static const struct airoha_pinctrl_func_group jtag_func_group[] = {
> >> +	{
> >> +		.name = "jtag_udi",
> >> +		.regmap[0] = {
> >> +			AIROHA_FUNC_MUX,
> >> +			REG_NPU_UART_EN,
> >> +			JTAG_UDI_EN_MASK,
> >> +			JTAG_UDI_EN_MASK
> >> +		},
> >> +		.regmap_size = 1,
> >> +	}, {
> >> +		.name = "jtag_dfd",
> >> +		.regmap[0] = {
> >> +			AIROHA_FUNC_MUX,
> >> +			REG_NPU_UART_EN,
> >> +			JTAG_DFD_EN_MASK,
> >> +			JTAG_DFD_EN_MASK
> >> +		},
> >> +		.regmap_size = 1,
> >> +	},
> >> +};
> >> +
> >> +static const struct airoha_pinctrl_func_group pcm_func_group[] = {
> >> +	{
> >> +		.name = "pcm1",
> >> +		.regmap[0] = {
> >> +			AIROHA_FUNC_MUX,
> >> +			REG_GPIO_SPI_CS1_MODE,
> >> +			GPIO_PCM1_MODE_MASK,
> >> +			GPIO_PCM1_MODE_MASK
> >> +		},
> >> +		.regmap_size = 1,
> >> +	}, {
> >> +		.name = "pcm2",
> >> +		.regmap[0] = {
> >> +			AIROHA_FUNC_MUX,
> >> +			REG_GPIO_SPI_CS1_MODE,
> >> +			GPIO_PCM2_MODE_MASK,
> >> +			GPIO_PCM2_MODE_MASK
> >> +		},
> >> +		.regmap_size = 1,
> >> +	},
> >> +};
> >> +
> >> +static const struct airoha_pinctrl_func_group spi_func_group[] = {
> >> +	{
> >> +		.name = "spi_quad",
> >> +		.regmap[0] = {
> >> +			AIROHA_FUNC_MUX,
> >> +			REG_GPIO_SPI_CS1_MODE,
> >> +			GPIO_SPI_QUAD_MODE_MASK,
> >> +			GPIO_SPI_QUAD_MODE_MASK
> >> +		},
> >> +		.regmap_size = 1,
> >> +	}, {
> >> +		.name = "spi_cs1",
> >> +		.regmap[0] = {
> >> +			AIROHA_FUNC_MUX,
> >> +			REG_GPIO_SPI_CS1_MODE,
> >> +			GPIO_SPI_CS1_MODE_MASK,
> >> +			GPIO_SPI_CS1_MODE_MASK
> >> +		},
> >> +		.regmap_size = 1,
> >> +	}, {
> >> +		.name = "spi_cs2",
> >> +		.regmap[0] = {
> >> +			AIROHA_FUNC_MUX,
> >> +			REG_GPIO_SPI_CS1_MODE,
> >> +			GPIO_SPI_CS2_MODE_MASK,
> >> +			GPIO_SPI_CS2_MODE_MASK
> >> +		},
> >> +		.regmap_size = 1,
> >> +	}, {
> >> +		.name = "spi_cs3",
> >> +		.regmap[0] = {
> >> +			AIROHA_FUNC_MUX,
> >> +			REG_GPIO_SPI_CS1_MODE,
> >> +			GPIO_SPI_CS3_MODE_MASK,
> >> +			GPIO_SPI_CS3_MODE_MASK
> >> +		},
> >> +		.regmap_size = 1,
> >> +	}, {
> >> +		.name = "spi_cs4",
> >> +		.regmap[0] = {
> >> +			AIROHA_FUNC_MUX,
> >> +			REG_GPIO_SPI_CS1_MODE,
> >> +			GPIO_SPI_CS4_MODE_MASK,
> >> +			GPIO_SPI_CS4_MODE_MASK
> >> +		},
> >> +		.regmap_size = 1,
> >> +	},
> >> +};
> >> +
> >> +static const struct airoha_pinctrl_func_group an7583_pcm_spi_func_group[] = {
> >> +	{
> >> +		.name = "pcm_spi",
> >> +		.regmap[0] = {
> >> +			AIROHA_FUNC_MUX,
> >> +			REG_GPIO_SPI_CS1_MODE,
> >> +			GPIO_PCM_SPI_MODE_MASK,
> >> +			GPIO_PCM_SPI_MODE_MASK
> >> +		},
> >> +		.regmap_size = 1,
> >> +	}, {
> >> +		.name = "pcm_spi_int",
> >> +		.regmap[0] = {
> >> +			AIROHA_FUNC_MUX,
> >> +			REG_GPIO_SPI_CS1_MODE,
> >> +			GPIO_PCM_INT_MODE_MASK,
> >> +			GPIO_PCM_INT_MODE_MASK
> >> +		},
> >> +		.regmap_size = 1,
> >> +	}, {
> >> +		.name = "pcm_spi_rst",
> >> +		.regmap[0] = {
> >> +			AIROHA_FUNC_MUX,
> >> +			REG_GPIO_SPI_CS1_MODE,
> >> +			GPIO_PCM_RESET_MODE_MASK,
> >> +			GPIO_PCM_RESET_MODE_MASK
> >> +		},
> >> +		.regmap_size = 1,
> >> +	}, {
> >> +		.name = "pcm_spi_cs1",
> >> +		.regmap[0] = {
> >> +			AIROHA_FUNC_MUX,
> >> +			REG_GPIO_SPI_CS1_MODE,
> >> +			GPIO_PCM_SPI_CS1_MODE_MASK,
> >> +			GPIO_PCM_SPI_CS1_MODE_MASK
> >> +		},
> >> +		.regmap_size = 1,
> >> +	}, {
> >> +		.name = "pcm_spi_cs2",
> >> +		.regmap[0] = {
> >> +			AIROHA_FUNC_MUX,
> >> +			REG_GPIO_SPI_CS1_MODE,
> >> +			AN7583_GPIO_PCM_SPI_CS2_MODE_MASK,
> >> +			AN7583_GPIO_PCM_SPI_CS2_MODE_MASK
> >> +		},
> >> +		.regmap_size = 1,
> >> +	}, {
> >> +		.name = "pcm_spi_cs3",
> >> +		.regmap[0] = {
> >> +			AIROHA_FUNC_MUX,
> >> +			REG_GPIO_SPI_CS1_MODE,
> >> +			GPIO_PCM_SPI_CS3_MODE_MASK,
> >> +			GPIO_PCM_SPI_CS3_MODE_MASK
> >> +		},
> >> +		.regmap_size = 1,
> >> +	}, {
> >> +		.name = "pcm_spi_cs4",
> >> +		.regmap[0] = {
> >> +			AIROHA_FUNC_MUX,
> >> +			REG_GPIO_SPI_CS1_MODE,
> >> +			GPIO_PCM_SPI_CS4_MODE_MASK,
> >> +			GPIO_PCM_SPI_CS4_MODE_MASK
> >> +		},
> >> +		.regmap_size = 1,
> >> +	},
> >> +};
> >> +
> >> +static const struct airoha_pinctrl_func_group emmc_func_group[] = {
> >> +	{
> >> +		.name = "emmc",
> >> +		.regmap[0] = {
> >> +			AIROHA_FUNC_MUX,
> >> +			REG_GPIO_PON_MODE,
> >> +			GPIO_EMMC_MODE_MASK,
> >> +			GPIO_EMMC_MODE_MASK
> >> +		},
> >> +		.regmap_size = 1,
> >> +	},
> >> +};
> >> +
> >> +static const struct airoha_pinctrl_func_group pnand_func_group[] = {
> >> +	{
> >> +		.name = "pnand",
> >> +		.regmap[0] = {
> >> +			AIROHA_FUNC_MUX,
> >> +			REG_GPIO_PON_MODE,
> >> +			GPIO_PARALLEL_NAND_MODE_MASK,
> >> +			GPIO_PARALLEL_NAND_MODE_MASK
> >> +		},
> >> +		.regmap_size = 1,
> >> +	},
> >> +};
> >> +
> >> +static const struct airoha_pinctrl_func_group an7583_gpio_func_group[] = {
> >> +	AIROHA_PINCTRL_GPIO_EXT("gpio39", GPIO39_FLASH_MODE_CFG,
> >> +				AN7583_I2C0_SCL_GPIO_MODE_MASK),
> >> +	AIROHA_PINCTRL_GPIO_EXT("gpio40", GPIO40_FLASH_MODE_CFG,
> >> +				AN7583_I2C0_SDA_GPIO_MODE_MASK),
> >> +	AIROHA_PINCTRL_GPIO_EXT("gpio41", GPIO41_FLASH_MODE_CFG,
> >> +				AN7583_I2C1_SCL_GPIO_MODE_MASK),
> >> +	AIROHA_PINCTRL_GPIO_EXT("gpio42", GPIO42_FLASH_MODE_CFG,
> >> +				AN7583_I2C1_SDA_GPIO_MODE_MASK),
> >> +	AIROHA_PINCTRL_GPIO_EXT("gpio43", GPIO43_FLASH_MODE_CFG,
> >> +				AN7583_SPI_CLK_GPIO_MODE_MASK),
> >> +	AIROHA_PINCTRL_GPIO_EXT("gpio44", GPIO44_FLASH_MODE_CFG,
> >> +				AN7583_SPI_CS_GPIO_MODE_MASK),
> >> +	AIROHA_PINCTRL_GPIO_EXT("gpio45", GPIO45_FLASH_MODE_CFG,
> >> +				AN7583_SPI_MOSI_GPIO_MODE_MASK),
> >> +	AIROHA_PINCTRL_GPIO_EXT("gpio46", GPIO46_FLASH_MODE_CFG,
> >> +				AN7583_SPI_MISO_GPIO_MODE_MASK),
> >> +	AIROHA_PINCTRL_GPIO_EXT("gpio47", GPIO47_FLASH_MODE_CFG,
> >> +				AN7583_UART_TXD_GPIO_MODE_MASK),
> >> +	AIROHA_PINCTRL_GPIO_EXT("gpio48", GPIO48_FLASH_MODE_CFG,
> >> +				AN7583_UART_RXD_GPIO_MODE_MASK),
> >> +	AIROHA_PINCTRL_GPIO_EXT("gpio49", GPIO49_FLASH_MODE_CFG,
> >> +				GPIO_PCIE_RESET0_MASK),
> >> +	AIROHA_PINCTRL_GPIO_EXT("gpio50", GPIO50_FLASH_MODE_CFG,
> >> +				GPIO_PCIE_RESET1_MASK),
> >> +	AIROHA_PINCTRL_GPIO_EXT("gpio51", GPIO51_FLASH_MODE_CFG,
> >> +				AN7583_MDC_0_GPIO_MODE_MASK),
> >> +	AIROHA_PINCTRL_GPIO("gpio52", AN7583_MDIO_0_GPIO_MODE_MASK),
> >> +};
> >> +
> >> +static const struct airoha_pinctrl_func_group an7583_pcie_reset_func_group[] = {
> >> +	{
> >> +		.name = "pcie_reset0",
> >> +		.regmap[0] = {
> >> +			AIROHA_FUNC_MUX,
> >> +			REG_GPIO_PON_MODE,
> >> +			GPIO_PCIE_RESET0_MASK,
> >> +			0
> >> +		},
> >> +		.regmap_size = 1,
> >> +	}, {
> >> +		.name = "pcie_reset1",
> >> +		.regmap[0] = {
> >> +			AIROHA_FUNC_MUX,
> >> +			REG_GPIO_PON_MODE,
> >> +			GPIO_PCIE_RESET1_MASK,
> >> +			0
> >> +		},
> >> +		.regmap_size = 1,
> >> +	},
> >> +};
> >> +
> >> +static const struct airoha_pinctrl_func_group an7583_pwm_func_group[] = {
> >> +	AIROHA_PINCTRL_PWM("gpio0", GPIO0_FLASH_MODE_CFG),
> >> +	AIROHA_PINCTRL_PWM("gpio1", GPIO1_FLASH_MODE_CFG),
> >> +	AIROHA_PINCTRL_PWM("gpio2", GPIO2_FLASH_MODE_CFG),
> >> +	AIROHA_PINCTRL_PWM("gpio3", GPIO3_FLASH_MODE_CFG),
> >> +	AIROHA_PINCTRL_PWM("gpio4", GPIO4_FLASH_MODE_CFG),
> >> +	AIROHA_PINCTRL_PWM("gpio5", GPIO5_FLASH_MODE_CFG),
> >> +	AIROHA_PINCTRL_PWM("gpio6", GPIO6_FLASH_MODE_CFG),
> >> +	AIROHA_PINCTRL_PWM("gpio7", GPIO7_FLASH_MODE_CFG),
> >> +	AIROHA_PINCTRL_PWM("gpio8", GPIO8_FLASH_MODE_CFG),
> >> +	AIROHA_PINCTRL_PWM("gpio9", GPIO9_FLASH_MODE_CFG),
> >> +	AIROHA_PINCTRL_PWM("gpio10", GPIO10_FLASH_MODE_CFG),
> >> +	AIROHA_PINCTRL_PWM("gpio11", GPIO11_FLASH_MODE_CFG),
> >> +	AIROHA_PINCTRL_PWM("gpio12", GPIO12_FLASH_MODE_CFG),
> >> +	AIROHA_PINCTRL_PWM("gpio13", GPIO13_FLASH_MODE_CFG),
> >> +	AIROHA_PINCTRL_PWM("gpio14", GPIO14_FLASH_MODE_CFG),
> >> +	AIROHA_PINCTRL_PWM("gpio15", GPIO15_FLASH_MODE_CFG),
> >> +	AIROHA_PINCTRL_PWM_EXT("gpio16", GPIO16_FLASH_MODE_CFG),
> >> +	AIROHA_PINCTRL_PWM_EXT("gpio17", GPIO17_FLASH_MODE_CFG),
> >> +	AIROHA_PINCTRL_PWM_EXT("gpio18", GPIO18_FLASH_MODE_CFG),
> >> +	AIROHA_PINCTRL_PWM_EXT("gpio19", GPIO19_FLASH_MODE_CFG),
> >> +	AIROHA_PINCTRL_PWM_EXT("gpio20", GPIO20_FLASH_MODE_CFG),
> >> +	AIROHA_PINCTRL_PWM_EXT("gpio21", GPIO21_FLASH_MODE_CFG),
> >> +	AIROHA_PINCTRL_PWM_EXT("gpio22", GPIO22_FLASH_MODE_CFG),
> >> +	AIROHA_PINCTRL_PWM_EXT("gpio23", GPIO23_FLASH_MODE_CFG),
> >> +	AIROHA_PINCTRL_PWM_EXT("gpio24", GPIO24_FLASH_MODE_CFG),
> >> +	AIROHA_PINCTRL_PWM_EXT("gpio25", GPIO25_FLASH_MODE_CFG),
> >> +	AIROHA_PINCTRL_PWM_EXT("gpio26", GPIO26_FLASH_MODE_CFG),
> >> +	AIROHA_PINCTRL_PWM_EXT("gpio27", GPIO27_FLASH_MODE_CFG),
> >> +	AIROHA_PINCTRL_PWM_EXT("gpio28", GPIO28_FLASH_MODE_CFG),
> >> +	AIROHA_PINCTRL_PWM_EXT("gpio29", GPIO29_FLASH_MODE_CFG),
> >> +	AIROHA_PINCTRL_PWM_EXT("gpio30", GPIO30_FLASH_MODE_CFG),
> >> +	AIROHA_PINCTRL_PWM_EXT("gpio31", GPIO31_FLASH_MODE_CFG),
> >> +	AIROHA_PINCTRL_PWM_EXT("gpio36", GPIO36_FLASH_MODE_CFG),
> >> +	AIROHA_PINCTRL_PWM_EXT("gpio37", GPIO37_FLASH_MODE_CFG),
> >> +	AIROHA_PINCTRL_PWM_EXT("gpio38", GPIO38_FLASH_MODE_CFG),
> >> +	AIROHA_PINCTRL_PWM_EXT_SEC("gpio39", GPIO39_FLASH_MODE_CFG,
> >> +				   AN7583_I2C0_SCL_GPIO_MODE_MASK),
> >> +	AIROHA_PINCTRL_PWM_EXT_SEC("gpio40", GPIO40_FLASH_MODE_CFG,
> >> +				   AN7583_I2C0_SDA_GPIO_MODE_MASK),
> >> +	AIROHA_PINCTRL_PWM_EXT_SEC("gpio41", GPIO41_FLASH_MODE_CFG,
> >> +				   AN7583_I2C1_SCL_GPIO_MODE_MASK),
> >> +	AIROHA_PINCTRL_PWM_EXT_SEC("gpio42", GPIO42_FLASH_MODE_CFG,
> >> +				   AN7583_I2C1_SDA_GPIO_MODE_MASK),
> >> +	AIROHA_PINCTRL_PWM_EXT_SEC("gpio43", GPIO43_FLASH_MODE_CFG,
> >> +				   AN7583_SPI_CLK_GPIO_MODE_MASK),
> >> +	AIROHA_PINCTRL_PWM_EXT_SEC("gpio44", GPIO44_FLASH_MODE_CFG,
> >> +				   AN7583_SPI_CS_GPIO_MODE_MASK),
> >> +	AIROHA_PINCTRL_PWM_EXT_SEC("gpio45", GPIO45_FLASH_MODE_CFG,
> >> +				   AN7583_SPI_MOSI_GPIO_MODE_MASK),
> >> +	AIROHA_PINCTRL_PWM_EXT_SEC("gpio46", GPIO46_FLASH_MODE_CFG,
> >> +				   AN7583_SPI_MISO_GPIO_MODE_MASK),
> >> +	AIROHA_PINCTRL_PWM_EXT_SEC("gpio47", GPIO47_FLASH_MODE_CFG,
> >> +				   AN7583_UART_TXD_GPIO_MODE_MASK),
> >> +	AIROHA_PINCTRL_PWM_EXT_SEC("gpio48", GPIO48_FLASH_MODE_CFG,
> >> +				   AN7583_UART_RXD_GPIO_MODE_MASK),
> >> +	AIROHA_PINCTRL_PWM_EXT_SEC("gpio49", GPIO49_FLASH_MODE_CFG,
> >> +				   GPIO_PCIE_RESET0_MASK),
> >> +	AIROHA_PINCTRL_PWM_EXT_SEC("gpio50", GPIO50_FLASH_MODE_CFG,
> >> +				   GPIO_PCIE_RESET1_MASK),
> >> +	AIROHA_PINCTRL_PWM_EXT_SEC("gpio51", GPIO51_FLASH_MODE_CFG,
> >> +				   AN7583_MDC_0_GPIO_MODE_MASK),
> >> +};
> >> +
> >> +static const struct airoha_pinctrl_func_group an7583_phy1_led0_func_group[] = {
> >> +	AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK,
> >> +				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),
> >> +	AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK,
> >> +				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)),
> >> +	AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK,
> >> +				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)),
> >> +	AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK,
> >> +				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),
> >> +};
> >> +
> >> +static const struct airoha_pinctrl_func_group an7583_phy2_led0_func_group[] = {
> >> +	AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK,
> >> +				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),
> >> +	AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK,
> >> +				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)),
> >> +	AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK,
> >> +				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)),
> >> +	AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK,
> >> +				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),
> >> +};
> >> +
> >> +static const struct airoha_pinctrl_func_group an7583_phy3_led0_func_group[] = {
> >> +	AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK,
> >> +				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
> >> +	AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK,
> >> +				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),
> >> +	AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK,
> >> +				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),
> >> +	AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK,
> >> +				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
> >> +};
> >> +
> >> +static const struct airoha_pinctrl_func_group an7583_phy4_led0_func_group[] = {
> >> +	AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK,
> >> +				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)),
> >> +	AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK,
> >> +				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)),
> >> +	AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK,
> >> +				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)),
> >> +	AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK,
> >> +				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)),
> >> +};
> >> +
> >> +static const struct airoha_pinctrl_func_group an7583_phy1_led1_func_group[] = {
> >> +	AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK,
> >> +				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),
> >> +	AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK,
> >> +				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)),
> >> +	AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK,
> >> +				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)),
> >> +	AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK,
> >> +				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),
> >> +};
> >> +
> >> +static const struct airoha_pinctrl_func_group an7583_phy2_led1_func_group[] = {
> >> +	AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK,
> >> +				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),
> >> +	AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK,
> >> +				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)),
> >> +	AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK,
> >> +				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)),
> >> +	AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK,
> >> +				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),
> >> +};
> >> +
> >> +static const struct airoha_pinctrl_func_group an7583_phy3_led1_func_group[] = {
> >> +	AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK,
> >> +				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
> >> +	AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK,
> >> +				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),
> >> +	AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK,
> >> +				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),
> >> +	AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK,
> >> +				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
> >> +};
> >> +
> >> +static const struct airoha_pinctrl_func_group an7583_phy4_led1_func_group[] = {
> >> +	AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK,
> >> +				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)),
> >> +	AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK,
> >> +				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)),
> >> +	AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK,
> >> +				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)),
> >> +	AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK,
> >> +				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)),
> >> +};
> >> +
> >> +static const struct airoha_pinctrl_func an7583_pinctrl_funcs[] = {
> >> +	PINCTRL_FUNC_DESC("pon", pon),
> >> +	PINCTRL_FUNC_DESC("tod_1pps", tod_1pps),
> >> +	PINCTRL_FUNC_DESC("sipo", sipo),
> >> +	PINCTRL_FUNC_DESC("mdio", an7583_mdio),
> >> +	PINCTRL_FUNC_DESC("uart", uart),
> >> +	PINCTRL_FUNC_DESC("jtag", jtag),
> >> +	PINCTRL_FUNC_DESC("pcm", pcm),
> >> +	PINCTRL_FUNC_DESC("spi", spi),
> >> +	PINCTRL_FUNC_DESC("pcm_spi", an7583_pcm_spi),
> >> +	PINCTRL_FUNC_DESC("emmc", emmc),
> >> +	PINCTRL_FUNC_DESC("pnand", pnand),
> >> +	PINCTRL_FUNC_DESC("gpio", an7583_gpio),
> >> +	PINCTRL_FUNC_DESC("pcie_reset", an7583_pcie_reset),
> >> +	PINCTRL_FUNC_DESC("pwm", an7583_pwm),
> >> +	PINCTRL_FUNC_DESC("phy1_led0", an7583_phy1_led0),
> >> +	PINCTRL_FUNC_DESC("phy2_led0", an7583_phy2_led0),
> >> +	PINCTRL_FUNC_DESC("phy3_led0", an7583_phy3_led0),
> >> +	PINCTRL_FUNC_DESC("phy4_led0", an7583_phy4_led0),
> >> +	PINCTRL_FUNC_DESC("phy1_led1", an7583_phy1_led1),
> >> +	PINCTRL_FUNC_DESC("phy2_led1", an7583_phy2_led1),
> >> +	PINCTRL_FUNC_DESC("phy3_led1", an7583_phy3_led1),
> >> +	PINCTRL_FUNC_DESC("phy4_led1", an7583_phy4_led1),
> >> +};
> >> +
> >> +static const struct airoha_pinctrl_conf an7583_pinctrl_pullup_conf[] = {
> >> +	PINCTRL_CONF_DESC(2, REG_GPIO_L_PU, BIT(0)),
> >> +	PINCTRL_CONF_DESC(3, REG_GPIO_L_PU, BIT(1)),
> >> +	PINCTRL_CONF_DESC(4, REG_GPIO_L_PU, BIT(2)),
> >> +	PINCTRL_CONF_DESC(5, REG_GPIO_L_PU, BIT(3)),
> >> +	PINCTRL_CONF_DESC(6, REG_GPIO_L_PU, BIT(4)),
> >> +	PINCTRL_CONF_DESC(7, REG_GPIO_L_PU, BIT(5)),
> >> +	PINCTRL_CONF_DESC(8, REG_GPIO_L_PU, BIT(6)),
> >> +	PINCTRL_CONF_DESC(9, REG_GPIO_L_PU, BIT(7)),
> >> +	PINCTRL_CONF_DESC(10, REG_GPIO_L_PU, BIT(8)),
> >> +	PINCTRL_CONF_DESC(11, REG_GPIO_L_PU, BIT(9)),
> >> +	PINCTRL_CONF_DESC(12, REG_GPIO_L_PU, BIT(10)),
> >> +	PINCTRL_CONF_DESC(13, REG_GPIO_L_PU, BIT(11)),
> >> +	PINCTRL_CONF_DESC(14, REG_GPIO_L_PU, BIT(12)),
> >> +	PINCTRL_CONF_DESC(15, REG_GPIO_L_PU, BIT(13)),
> >> +	PINCTRL_CONF_DESC(16, REG_GPIO_L_PU, BIT(14)),
> >> +	PINCTRL_CONF_DESC(17, REG_GPIO_L_PU, BIT(15)),
> >> +	PINCTRL_CONF_DESC(18, REG_GPIO_L_PU, BIT(16)),
> >> +	PINCTRL_CONF_DESC(19, REG_GPIO_L_PU, BIT(17)),
> >> +	PINCTRL_CONF_DESC(20, REG_GPIO_L_PU, BIT(18)),
> >> +	PINCTRL_CONF_DESC(21, REG_GPIO_L_PU, BIT(19)),
> >> +	PINCTRL_CONF_DESC(22, REG_GPIO_L_PU, BIT(20)),
> >> +	PINCTRL_CONF_DESC(23, REG_GPIO_L_PU, BIT(21)),
> >> +	PINCTRL_CONF_DESC(24, REG_GPIO_L_PU, BIT(22)),
> >> +	PINCTRL_CONF_DESC(25, REG_GPIO_L_PU, BIT(23)),
> >> +	PINCTRL_CONF_DESC(26, REG_GPIO_L_PU, BIT(24)),
> >> +	PINCTRL_CONF_DESC(27, REG_GPIO_L_PU, BIT(25)),
> >> +	PINCTRL_CONF_DESC(28, REG_GPIO_L_PU, BIT(26)),
> >> +	PINCTRL_CONF_DESC(29, REG_GPIO_L_PU, BIT(27)),
> >> +	PINCTRL_CONF_DESC(30, REG_GPIO_L_PU, BIT(28)),
> >> +	PINCTRL_CONF_DESC(31, REG_GPIO_L_PU, BIT(29)),
> >> +	PINCTRL_CONF_DESC(32, REG_GPIO_L_PU, BIT(30)),
> >> +	PINCTRL_CONF_DESC(33, REG_GPIO_L_PU, BIT(31)),
> >> +	PINCTRL_CONF_DESC(34, REG_GPIO_H_PU, BIT(0)),
> >> +	PINCTRL_CONF_DESC(35, REG_GPIO_H_PU, BIT(1)),
> >> +	PINCTRL_CONF_DESC(36, REG_GPIO_H_PU, BIT(2)),
> >> +	PINCTRL_CONF_DESC(37, REG_GPIO_H_PU, BIT(3)),
> >> +	PINCTRL_CONF_DESC(38, REG_GPIO_H_PU, BIT(4)),
> >> +	PINCTRL_CONF_DESC(39, REG_GPIO_H_PU, BIT(5)),
> >> +	PINCTRL_CONF_DESC(40, REG_GPIO_H_PU, BIT(6)),
> >> +	PINCTRL_CONF_DESC(41, REG_I2C_SDA_PU, I2C_SCL_PU_MASK),
> >> +	PINCTRL_CONF_DESC(42, REG_I2C_SDA_PU, I2C_SDA_PU_MASK),
> >> +	PINCTRL_CONF_DESC(43, REG_I2C_SDA_PU, AN7583_I2C1_SCL_PU_MASK),
> >> +	PINCTRL_CONF_DESC(44, REG_I2C_SDA_PU, AN7583_I2C1_SDA_PU_MASK),
> >> +	PINCTRL_CONF_DESC(45, REG_I2C_SDA_PU, SPI_CLK_PU_MASK),
> >> +	PINCTRL_CONF_DESC(46, REG_I2C_SDA_PU, SPI_CS0_PU_MASK),
> >> +	PINCTRL_CONF_DESC(47, REG_I2C_SDA_PU, SPI_MOSI_PU_MASK),
> >> +	PINCTRL_CONF_DESC(48, REG_I2C_SDA_PU, SPI_MISO_PU_MASK),
> >> +	PINCTRL_CONF_DESC(49, REG_I2C_SDA_PU, UART1_TXD_PU_MASK),
> >> +	PINCTRL_CONF_DESC(50, REG_I2C_SDA_PU, UART1_RXD_PU_MASK),
> >> +	PINCTRL_CONF_DESC(51, REG_I2C_SDA_PU, PCIE0_RESET_PU_MASK),
> >> +	PINCTRL_CONF_DESC(52, REG_I2C_SDA_PU, PCIE1_RESET_PU_MASK),
> >> +	PINCTRL_CONF_DESC(53, REG_I2C_SDA_PU, AN7583_MDC_0_PU_MASK),
> >> +	PINCTRL_CONF_DESC(54, REG_I2C_SDA_PU, AN7583_MDIO_0_PU_MASK),
> >> +};
> >> +
> >> +static const struct airoha_pinctrl_conf an7583_pinctrl_pulldown_conf[] = {
> >> +	PINCTRL_CONF_DESC(2, REG_GPIO_L_PD, BIT(0)),
> >> +	PINCTRL_CONF_DESC(3, REG_GPIO_L_PD, BIT(1)),
> >> +	PINCTRL_CONF_DESC(4, REG_GPIO_L_PD, BIT(2)),
> >> +	PINCTRL_CONF_DESC(5, REG_GPIO_L_PD, BIT(3)),
> >> +	PINCTRL_CONF_DESC(6, REG_GPIO_L_PD, BIT(4)),
> >> +	PINCTRL_CONF_DESC(7, REG_GPIO_L_PD, BIT(5)),
> >> +	PINCTRL_CONF_DESC(8, REG_GPIO_L_PD, BIT(6)),
> >> +	PINCTRL_CONF_DESC(9, REG_GPIO_L_PD, BIT(7)),
> >> +	PINCTRL_CONF_DESC(10, REG_GPIO_L_PD, BIT(8)),
> >> +	PINCTRL_CONF_DESC(11, REG_GPIO_L_PD, BIT(9)),
> >> +	PINCTRL_CONF_DESC(12, REG_GPIO_L_PD, BIT(10)),
> >> +	PINCTRL_CONF_DESC(13, REG_GPIO_L_PD, BIT(11)),
> >> +	PINCTRL_CONF_DESC(14, REG_GPIO_L_PD, BIT(12)),
> >> +	PINCTRL_CONF_DESC(15, REG_GPIO_L_PD, BIT(13)),
> >> +	PINCTRL_CONF_DESC(16, REG_GPIO_L_PD, BIT(14)),
> >> +	PINCTRL_CONF_DESC(17, REG_GPIO_L_PD, BIT(15)),
> >> +	PINCTRL_CONF_DESC(18, REG_GPIO_L_PD, BIT(16)),
> >> +	PINCTRL_CONF_DESC(19, REG_GPIO_L_PD, BIT(17)),
> >> +	PINCTRL_CONF_DESC(20, REG_GPIO_L_PD, BIT(18)),
> >> +	PINCTRL_CONF_DESC(21, REG_GPIO_L_PD, BIT(19)),
> >> +	PINCTRL_CONF_DESC(22, REG_GPIO_L_PD, BIT(20)),
> >> +	PINCTRL_CONF_DESC(23, REG_GPIO_L_PD, BIT(21)),
> >> +	PINCTRL_CONF_DESC(24, REG_GPIO_L_PD, BIT(22)),
> >> +	PINCTRL_CONF_DESC(25, REG_GPIO_L_PD, BIT(23)),
> >> +	PINCTRL_CONF_DESC(26, REG_GPIO_L_PD, BIT(24)),
> >> +	PINCTRL_CONF_DESC(27, REG_GPIO_L_PD, BIT(25)),
> >> +	PINCTRL_CONF_DESC(28, REG_GPIO_L_PD, BIT(26)),
> >> +	PINCTRL_CONF_DESC(29, REG_GPIO_L_PD, BIT(27)),
> >> +	PINCTRL_CONF_DESC(30, REG_GPIO_L_PD, BIT(28)),
> >> +	PINCTRL_CONF_DESC(31, REG_GPIO_L_PD, BIT(29)),
> >> +	PINCTRL_CONF_DESC(32, REG_GPIO_L_PD, BIT(30)),
> >> +	PINCTRL_CONF_DESC(33, REG_GPIO_L_PD, BIT(31)),
> >> +	PINCTRL_CONF_DESC(34, REG_GPIO_H_PD, BIT(0)),
> >> +	PINCTRL_CONF_DESC(35, REG_GPIO_H_PD, BIT(1)),
> >> +	PINCTRL_CONF_DESC(36, REG_GPIO_H_PD, BIT(2)),
> >> +	PINCTRL_CONF_DESC(37, REG_GPIO_H_PD, BIT(3)),
> >> +	PINCTRL_CONF_DESC(38, REG_GPIO_H_PD, BIT(4)),
> >> +	PINCTRL_CONF_DESC(39, REG_GPIO_H_PD, BIT(5)),
> >> +	PINCTRL_CONF_DESC(40, REG_GPIO_H_PD, BIT(6)),
> >> +	PINCTRL_CONF_DESC(41, REG_I2C_SDA_PD, I2C_SCL_PD_MASK),
> >> +	PINCTRL_CONF_DESC(42, REG_I2C_SDA_PD, I2C_SDA_PD_MASK),
> >> +	PINCTRL_CONF_DESC(43, REG_I2C_SDA_PD, AN7583_I2C1_SCL_PD_MASK),
> >> +	PINCTRL_CONF_DESC(44, REG_I2C_SDA_PD, AN7583_I2C1_SDA_PD_MASK),
> >> +	PINCTRL_CONF_DESC(45, REG_I2C_SDA_PD, SPI_CLK_PD_MASK),
> >> +	PINCTRL_CONF_DESC(46, REG_I2C_SDA_PD, SPI_CS0_PD_MASK),
> >> +	PINCTRL_CONF_DESC(47, REG_I2C_SDA_PD, SPI_MOSI_PD_MASK),
> >> +	PINCTRL_CONF_DESC(48, REG_I2C_SDA_PD, SPI_MISO_PD_MASK),
> >> +	PINCTRL_CONF_DESC(49, REG_I2C_SDA_PD, UART1_TXD_PD_MASK),
> >> +	PINCTRL_CONF_DESC(50, REG_I2C_SDA_PD, UART1_RXD_PD_MASK),
> >> +	PINCTRL_CONF_DESC(51, REG_I2C_SDA_PD, PCIE0_RESET_PD_MASK),
> >> +	PINCTRL_CONF_DESC(52, REG_I2C_SDA_PD, PCIE1_RESET_PD_MASK),
> >> +	PINCTRL_CONF_DESC(53, REG_I2C_SDA_PD, AN7583_MDC_0_PD_MASK),
> >> +	PINCTRL_CONF_DESC(54, REG_I2C_SDA_PD, AN7583_MDIO_0_PD_MASK),
> >> +};
> >> +
> >> +static const struct airoha_pinctrl_conf an7583_pinctrl_drive_e2_conf[] = {
> >> +	PINCTRL_CONF_DESC(2, REG_GPIO_L_E2, BIT(0)),
> >> +	PINCTRL_CONF_DESC(3, REG_GPIO_L_E2, BIT(1)),
> >> +	PINCTRL_CONF_DESC(4, REG_GPIO_L_E2, BIT(2)),
> >> +	PINCTRL_CONF_DESC(5, REG_GPIO_L_E2, BIT(3)),
> >> +	PINCTRL_CONF_DESC(6, REG_GPIO_L_E2, BIT(4)),
> >> +	PINCTRL_CONF_DESC(7, REG_GPIO_L_E2, BIT(5)),
> >> +	PINCTRL_CONF_DESC(8, REG_GPIO_L_E2, BIT(6)),
> >> +	PINCTRL_CONF_DESC(9, REG_GPIO_L_E2, BIT(7)),
> >> +	PINCTRL_CONF_DESC(10, REG_GPIO_L_E2, BIT(8)),
> >> +	PINCTRL_CONF_DESC(11, REG_GPIO_L_E2, BIT(9)),
> >> +	PINCTRL_CONF_DESC(12, REG_GPIO_L_E2, BIT(10)),
> >> +	PINCTRL_CONF_DESC(13, REG_GPIO_L_E2, BIT(11)),
> >> +	PINCTRL_CONF_DESC(14, REG_GPIO_L_E2, BIT(12)),
> >> +	PINCTRL_CONF_DESC(15, REG_GPIO_L_E2, BIT(13)),
> >> +	PINCTRL_CONF_DESC(16, REG_GPIO_L_E2, BIT(14)),
> >> +	PINCTRL_CONF_DESC(17, REG_GPIO_L_E2, BIT(15)),
> >> +	PINCTRL_CONF_DESC(18, REG_GPIO_L_E2, BIT(16)),
> >> +	PINCTRL_CONF_DESC(19, REG_GPIO_L_E2, BIT(17)),
> >> +	PINCTRL_CONF_DESC(20, REG_GPIO_L_E2, BIT(18)),
> >> +	PINCTRL_CONF_DESC(21, REG_GPIO_L_E2, BIT(19)),
> >> +	PINCTRL_CONF_DESC(22, REG_GPIO_L_E2, BIT(20)),
> >> +	PINCTRL_CONF_DESC(23, REG_GPIO_L_E2, BIT(21)),
> >> +	PINCTRL_CONF_DESC(24, REG_GPIO_L_E2, BIT(22)),
> >> +	PINCTRL_CONF_DESC(25, REG_GPIO_L_E2, BIT(23)),
> >> +	PINCTRL_CONF_DESC(26, REG_GPIO_L_E2, BIT(24)),
> >> +	PINCTRL_CONF_DESC(27, REG_GPIO_L_E2, BIT(25)),
> >> +	PINCTRL_CONF_DESC(28, REG_GPIO_L_E2, BIT(26)),
> >> +	PINCTRL_CONF_DESC(29, REG_GPIO_L_E2, BIT(27)),
> >> +	PINCTRL_CONF_DESC(30, REG_GPIO_L_E2, BIT(28)),
> >> +	PINCTRL_CONF_DESC(31, REG_GPIO_L_E2, BIT(29)),
> >> +	PINCTRL_CONF_DESC(32, REG_GPIO_L_E2, BIT(30)),
> >> +	PINCTRL_CONF_DESC(33, REG_GPIO_L_E2, BIT(31)),
> >> +	PINCTRL_CONF_DESC(34, REG_GPIO_H_E2, BIT(0)),
> >> +	PINCTRL_CONF_DESC(35, REG_GPIO_H_E2, BIT(1)),
> >> +	PINCTRL_CONF_DESC(36, REG_GPIO_H_E2, BIT(2)),
> >> +	PINCTRL_CONF_DESC(37, REG_GPIO_H_E2, BIT(3)),
> >> +	PINCTRL_CONF_DESC(38, REG_GPIO_H_E2, BIT(4)),
> >> +	PINCTRL_CONF_DESC(39, REG_GPIO_H_E2, BIT(5)),
> >> +	PINCTRL_CONF_DESC(40, REG_GPIO_H_E2, BIT(6)),
> >> +	PINCTRL_CONF_DESC(41, REG_I2C_SDA_E2, I2C_SCL_E2_MASK),
> >> +	PINCTRL_CONF_DESC(42, REG_I2C_SDA_E2, I2C_SDA_E2_MASK),
> >> +	PINCTRL_CONF_DESC(43, REG_I2C_SDA_E2, AN7583_I2C1_SCL_E2_MASK),
> >> +	PINCTRL_CONF_DESC(44, REG_I2C_SDA_E2, AN7583_I2C1_SDA_E2_MASK),
> >> +	PINCTRL_CONF_DESC(45, REG_I2C_SDA_E2, SPI_CLK_E2_MASK),
> >> +	PINCTRL_CONF_DESC(46, REG_I2C_SDA_E2, SPI_CS0_E2_MASK),
> >> +	PINCTRL_CONF_DESC(47, REG_I2C_SDA_E2, SPI_MOSI_E2_MASK),
> >> +	PINCTRL_CONF_DESC(48, REG_I2C_SDA_E2, SPI_MISO_E2_MASK),
> >> +	PINCTRL_CONF_DESC(49, REG_I2C_SDA_E2, UART1_TXD_E2_MASK),
> >> +	PINCTRL_CONF_DESC(50, REG_I2C_SDA_E2, UART1_RXD_E2_MASK),
> >> +	PINCTRL_CONF_DESC(51, REG_I2C_SDA_E2, PCIE0_RESET_E2_MASK),
> >> +	PINCTRL_CONF_DESC(52, REG_I2C_SDA_E2, PCIE1_RESET_E2_MASK),
> >> +	PINCTRL_CONF_DESC(53, REG_I2C_SDA_E2, AN7583_MDC_0_E2_MASK),
> >> +	PINCTRL_CONF_DESC(54, REG_I2C_SDA_E2, AN7583_MDIO_0_E2_MASK),
> >> +};
> >> +
> >> +static const struct airoha_pinctrl_conf an7583_pinctrl_drive_e4_conf[] = {
> >> +	PINCTRL_CONF_DESC(2, REG_GPIO_L_E4, BIT(0)),
> >> +	PINCTRL_CONF_DESC(3, REG_GPIO_L_E4, BIT(1)),
> >> +	PINCTRL_CONF_DESC(4, REG_GPIO_L_E4, BIT(2)),
> >> +	PINCTRL_CONF_DESC(5, REG_GPIO_L_E4, BIT(3)),
> >> +	PINCTRL_CONF_DESC(6, REG_GPIO_L_E4, BIT(4)),
> >> +	PINCTRL_CONF_DESC(7, REG_GPIO_L_E4, BIT(5)),
> >> +	PINCTRL_CONF_DESC(8, REG_GPIO_L_E4, BIT(6)),
> >> +	PINCTRL_CONF_DESC(9, REG_GPIO_L_E4, BIT(7)),
> >> +	PINCTRL_CONF_DESC(10, REG_GPIO_L_E4, BIT(8)),
> >> +	PINCTRL_CONF_DESC(11, REG_GPIO_L_E4, BIT(9)),
> >> +	PINCTRL_CONF_DESC(12, REG_GPIO_L_E4, BIT(10)),
> >> +	PINCTRL_CONF_DESC(13, REG_GPIO_L_E4, BIT(11)),
> >> +	PINCTRL_CONF_DESC(14, REG_GPIO_L_E4, BIT(12)),
> >> +	PINCTRL_CONF_DESC(15, REG_GPIO_L_E4, BIT(13)),
> >> +	PINCTRL_CONF_DESC(16, REG_GPIO_L_E4, BIT(14)),
> >> +	PINCTRL_CONF_DESC(17, REG_GPIO_L_E4, BIT(15)),
> >> +	PINCTRL_CONF_DESC(18, REG_GPIO_L_E4, BIT(16)),
> >> +	PINCTRL_CONF_DESC(19, REG_GPIO_L_E4, BIT(17)),
> >> +	PINCTRL_CONF_DESC(20, REG_GPIO_L_E4, BIT(18)),
> >> +	PINCTRL_CONF_DESC(21, REG_GPIO_L_E4, BIT(19)),
> >> +	PINCTRL_CONF_DESC(22, REG_GPIO_L_E4, BIT(20)),
> >> +	PINCTRL_CONF_DESC(23, REG_GPIO_L_E4, BIT(21)),
> >> +	PINCTRL_CONF_DESC(24, REG_GPIO_L_E4, BIT(22)),
> >> +	PINCTRL_CONF_DESC(25, REG_GPIO_L_E4, BIT(23)),
> >> +	PINCTRL_CONF_DESC(26, REG_GPIO_L_E4, BIT(24)),
> >> +	PINCTRL_CONF_DESC(27, REG_GPIO_L_E4, BIT(25)),
> >> +	PINCTRL_CONF_DESC(28, REG_GPIO_L_E4, BIT(26)),
> >> +	PINCTRL_CONF_DESC(29, REG_GPIO_L_E4, BIT(27)),
> >> +	PINCTRL_CONF_DESC(30, REG_GPIO_L_E4, BIT(28)),
> >> +	PINCTRL_CONF_DESC(31, REG_GPIO_L_E4, BIT(29)),
> >> +	PINCTRL_CONF_DESC(32, REG_GPIO_L_E4, BIT(30)),
> >> +	PINCTRL_CONF_DESC(33, REG_GPIO_L_E4, BIT(31)),
> >> +	PINCTRL_CONF_DESC(34, REG_GPIO_H_E4, BIT(0)),
> >> +	PINCTRL_CONF_DESC(35, REG_GPIO_H_E4, BIT(1)),
> >> +	PINCTRL_CONF_DESC(36, REG_GPIO_H_E4, BIT(2)),
> >> +	PINCTRL_CONF_DESC(37, REG_GPIO_H_E4, BIT(3)),
> >> +	PINCTRL_CONF_DESC(38, REG_GPIO_H_E4, BIT(4)),
> >> +	PINCTRL_CONF_DESC(39, REG_GPIO_H_E4, BIT(5)),
> >> +	PINCTRL_CONF_DESC(40, REG_GPIO_H_E4, BIT(6)),
> >> +	PINCTRL_CONF_DESC(41, REG_I2C_SDA_E4, I2C_SCL_E4_MASK),
> >> +	PINCTRL_CONF_DESC(42, REG_I2C_SDA_E4, I2C_SDA_E4_MASK),
> >> +	PINCTRL_CONF_DESC(43, REG_I2C_SDA_E4, AN7583_I2C1_SCL_E4_MASK),
> >> +	PINCTRL_CONF_DESC(44, REG_I2C_SDA_E4, AN7583_I2C1_SDA_E4_MASK),
> >> +	PINCTRL_CONF_DESC(45, REG_I2C_SDA_E4, SPI_CLK_E4_MASK),
> >> +	PINCTRL_CONF_DESC(46, REG_I2C_SDA_E4, SPI_CS0_E4_MASK),
> >> +	PINCTRL_CONF_DESC(47, REG_I2C_SDA_E4, SPI_MOSI_E4_MASK),
> >> +	PINCTRL_CONF_DESC(48, REG_I2C_SDA_E4, SPI_MISO_E4_MASK),
> >> +	PINCTRL_CONF_DESC(49, REG_I2C_SDA_E4, UART1_TXD_E4_MASK),
> >> +	PINCTRL_CONF_DESC(50, REG_I2C_SDA_E4, UART1_RXD_E4_MASK),
> >> +	PINCTRL_CONF_DESC(51, REG_I2C_SDA_E4, PCIE0_RESET_E4_MASK),
> >> +	PINCTRL_CONF_DESC(52, REG_I2C_SDA_E4, PCIE1_RESET_E4_MASK),
> >> +	PINCTRL_CONF_DESC(53, REG_I2C_SDA_E4, AN7583_MDC_0_E4_MASK),
> >> +	PINCTRL_CONF_DESC(54, REG_I2C_SDA_E4, AN7583_MDIO_0_E4_MASK),
> >> +};
> >> +
> >> +static const struct airoha_pinctrl_conf an7583_pinctrl_pcie_rst_od_conf[] = {
> >> +	PINCTRL_CONF_DESC(51, REG_PCIE_RESET_OD, PCIE0_RESET_OD_MASK),
> >> +	PINCTRL_CONF_DESC(52, REG_PCIE_RESET_OD, PCIE1_RESET_OD_MASK),
> >> +};
> >> +
> >> +static const struct airoha_pinctrl_match_data an7583_pinctrl_match_data = {
> >> +	.pinctrl_name = KBUILD_MODNAME,
> >> +	.pinctrl_owner = THIS_MODULE,
> >> +	.pins = an7583_pinctrl_pins,
> >> +	.num_pins = ARRAY_SIZE(an7583_pinctrl_pins),
> >> +	.grps = an7583_pinctrl_groups,
> >> +	.num_grps = ARRAY_SIZE(an7583_pinctrl_groups),
> >> +	.funcs = an7583_pinctrl_funcs,
> >> +	.num_funcs = ARRAY_SIZE(an7583_pinctrl_funcs),
> >> +	.confs_info = {
> >> +		[AIROHA_PINCTRL_CONFS_PULLUP] = {
> >> +			.confs = an7583_pinctrl_pullup_conf,
> >> +			.num_confs = ARRAY_SIZE(an7583_pinctrl_pullup_conf),
> >> +		},
> >> +		[AIROHA_PINCTRL_CONFS_PULLDOWN] = {
> >> +			.confs = an7583_pinctrl_pulldown_conf,
> >> +			.num_confs = ARRAY_SIZE(an7583_pinctrl_pulldown_conf),
> >> +		},
> >> +		[AIROHA_PINCTRL_CONFS_DRIVE_E2] = {
> >> +			.confs = an7583_pinctrl_drive_e2_conf,
> >> +			.num_confs = ARRAY_SIZE(an7583_pinctrl_drive_e2_conf),
> >> +		},
> >> +		[AIROHA_PINCTRL_CONFS_DRIVE_E4] = {
> >> +			.confs = an7583_pinctrl_drive_e4_conf,
> >> +			.num_confs = ARRAY_SIZE(an7583_pinctrl_drive_e4_conf),
> >> +		},
> >> +		[AIROHA_PINCTRL_CONFS_PCIE_RST_OD] = {
> >> +			.confs = an7583_pinctrl_pcie_rst_od_conf,
> >> +			.num_confs = ARRAY_SIZE(an7583_pinctrl_pcie_rst_od_conf),
> >> +		},
> >> +	},
> >> +};
> >> +
> >> +static const struct of_device_id airoha_pinctrl_of_match[] = {
> >> +	{ .compatible = "airoha,an7583-pinctrl", .data = &an7583_pinctrl_match_data },
> >> +	{ /* sentinel */ }
> >> +};
> >> +MODULE_DEVICE_TABLE(of, airoha_pinctrl_of_match);
> >> +
> >> +static struct platform_driver airoha_pinctrl_driver = {
> >> +	.probe = airoha_pinctrl_probe,
> >> +	.driver = {
> >> +		.name = "pinctrl-airoha-an7583",
> >> +		.of_match_table = airoha_pinctrl_of_match,
> >> +	},
> >> +};
> >> +module_platform_driver(airoha_pinctrl_driver);
> >> +
> >> +MODULE_LICENSE("GPL");
> >> +MODULE_AUTHOR("Lorenzo Bianconi <lorenzo@kernel.org>");
> >> +MODULE_AUTHOR("Benjamin Larsson <benjamin.larsson@genexis.eu>");
> >> +MODULE_AUTHOR("Markus Gothe <markus.gothe@genexis.eu>");
> >> +MODULE_DESCRIPTION("Pinctrl driver for Airoha AN7583 SoC");
> >> -- 
> >> 2.53.0
> >>

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Re: [PATCH v7 20/34] pinctrl: airoha: split driver on shared code and SoC specific drivers

[Mikhail Kshevetskiy]

On 7/27/26 12:27, Lorenzo Bianconi wrote:
>> On 7/27/26 12:14, Lorenzo Bianconi wrote:
>>>> Split combined an7581/an7583 source file on a
>>>>  * shared pinctrl code (pinctrl-airoha.c)
>>>>  * an7581 specific pinctrl driver (pinctrl-an7581.c)
>>>>  * an7583 specific pinctrl driver (pinctrl-an7583.c)
>>> I do not think we can have 7581 and 7583 chips at the same time on a given
>>> board so I guess we can avoid creating a dedicated module for the common code.
>>> I guess we can just create a library we can compile in. What do yout think?
>>>
>>> Regards,
>>> Lorenzo
>> Hm, how do you suggest to implement it? In the generic kernel case  we
>> should not
>> load airoha pinctrl library if we are booting from non airoha board. 
> I mean just compile the code in en7581 or an7583 modules without a dedicated
> module.

so in the generic kernel case we will have 4 copies of shared code?


>
> Regards,
> Lorenzo
>
>>>> Ininialization code was adapted a bit to work properly for shared
>>>> and SoC specific cases.
>>>>
>>>> Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
>>>> ---
>>>>  drivers/pinctrl/airoha/Kconfig          |   24 +-
>>>>  drivers/pinctrl/airoha/Makefile         |    5 +
>>>>  drivers/pinctrl/airoha/airoha-common.h  |    5 +
>>>>  drivers/pinctrl/airoha/pinctrl-airoha.c | 2382 +----------------------
>>>>  drivers/pinctrl/airoha/pinctrl-an7581.c | 1486 ++++++++++++++
>>>>  drivers/pinctrl/airoha/pinctrl-an7583.c | 1456 ++++++++++++++
>>>>  6 files changed, 2984 insertions(+), 2374 deletions(-)
>>>>  create mode 100644 drivers/pinctrl/airoha/pinctrl-an7581.c
>>>>  create mode 100644 drivers/pinctrl/airoha/pinctrl-an7583.c
>>>>
>>>> diff --git a/drivers/pinctrl/airoha/Kconfig b/drivers/pinctrl/airoha/Kconfig
>>>> index 03adaeae8fc3a..dae6608bc72dd 100644
>>>> --- a/drivers/pinctrl/airoha/Kconfig
>>>> +++ b/drivers/pinctrl/airoha/Kconfig
>>>> @@ -3,9 +3,9 @@ menu "Airoha pinctrl drivers"
>>>>  	depends on ARCH_AIROHA || COMPILE_TEST
>>>>  
>>>>  config PINCTRL_AIROHA
>>>> -	tristate "Airoha EN7581 pin control"
>>>> +	tristate "Airoha pin control"
>>>>  	depends on OF
>>>> -	depends on ARM64 || COMPILE_TEST
>>>> +	depends on ARCH_AIROHA || COMPILE_TEST
>>>>  	select PINMUX
>>>>  	select GENERIC_PINCONF
>>>>  	select GENERIC_PINCTRL_GROUPS
>>>> @@ -13,8 +13,26 @@ config PINCTRL_AIROHA
>>>>  	select GPIOLIB
>>>>  	select GPIOLIB_IRQCHIP
>>>>  	select REGMAP_MMIO
>>>> +	imply PINCTRL_AIROHA_AN7581
>>>> +	imply PINCTRL_AIROHA_AN7583
>>>> +	help
>>>> +	  Shared pin controller and gpio driver code for different
>>>> +	  Airoha SoCs.
>>>> +
>>>> +config PINCTRL_AIROHA_AN7581
>>>> +	tristate "AN7581 pinctrl"
>>>> +	depends on ARM64 || COMPILE_TEST
>>>> +	depends on PINCTRL_AIROHA
>>>> +	help
>>>> +	  Say yes here to support pin controller and gpio driver
>>>> +	  on Airoha AN7581, AN7566, AN7551 and other compatible SoCs.
>>>> +
>>>> +config PINCTRL_AIROHA_AN7583
>>>> +	tristate "AN7583 pinctrl"
>>>> +	depends on ARM64 || COMPILE_TEST
>>>> +	depends on PINCTRL_AIROHA
>>>>  	help
>>>>  	  Say yes here to support pin controller and gpio driver
>>>> -	  on Airoha EN7581 SoC.
>>>> +	  on Airoha AN7583, AN7553, AN7567 and other compatible SoCs.
>>>>  
>>>>  endmenu
>>>> diff --git a/drivers/pinctrl/airoha/Makefile b/drivers/pinctrl/airoha/Makefile
>>>> index a25b744dd7a8a..cfd68c45ae0f0 100644
>>>> --- a/drivers/pinctrl/airoha/Makefile
>>>> +++ b/drivers/pinctrl/airoha/Makefile
>>>> @@ -1,3 +1,8 @@
>>>>  # SPDX-License-Identifier: GPL-2.0
>>>>  
>>>> +# shared code
>>>>  obj-$(CONFIG_PINCTRL_AIROHA)		+= pinctrl-airoha.o
>>>> +
>>>> +# SoC drivers
>>>> +obj-$(CONFIG_PINCTRL_AIROHA_AN7581)	+= pinctrl-an7581.o
>>>> +obj-$(CONFIG_PINCTRL_AIROHA_AN7583)	+= pinctrl-an7583.o
>>>> diff --git a/drivers/pinctrl/airoha/airoha-common.h b/drivers/pinctrl/airoha/airoha-common.h
>>>> index 40d7e515c09eb..f73e90ca860f4 100644
>>>> --- a/drivers/pinctrl/airoha/airoha-common.h
>>>> +++ b/drivers/pinctrl/airoha/airoha-common.h
>>>> @@ -148,9 +148,12 @@ struct airoha_pinctrl {
>>>>  	struct regmap *regmap;
>>>>  
>>>>  	struct airoha_pinctrl_gpiochip gpiochip;
>>>> +	struct irq_chip gpio_irq_chip;
>>>>  };
>>>>  
>>>>  struct airoha_pinctrl_match_data {
>>>> +	const char *pinctrl_name;
>>>> +	struct module *pinctrl_owner;
>>>>  	const struct pinctrl_pin_desc *pins;
>>>>  	const unsigned int num_pins;
>>>>  	const struct pingroup *grps;
>>>> @@ -160,4 +163,6 @@ struct airoha_pinctrl_match_data {
>>>>  	const struct airoha_pinctrl_confs_info confs_info[AIROHA_PINCTRL_CONFS_MAX];
>>>>  };
>>>>  
>>>> +int airoha_pinctrl_probe(struct platform_device *pdev);
>>>> +
>>>>  #endif
>>>> diff --git a/drivers/pinctrl/airoha/pinctrl-airoha.c b/drivers/pinctrl/airoha/pinctrl-airoha.c
>>>> index f42631afc05d3..a46596eb1493b 100644
>>>> --- a/drivers/pinctrl/airoha/pinctrl-airoha.c
>>>> +++ b/drivers/pinctrl/airoha/pinctrl-airoha.c
>>>> @@ -7,365 +7,6 @@
>>>>  
>>>>  #include "airoha-common.h"
>>>>  
>>>> -/* MUX */
>>>> -#define REG_GPIO_2ND_I2C_MODE			0x0214
>>>> -#define GPIO_MDC_IO_MASTER_MODE_MASK		BIT(14)
>>>> -#define GPIO_I2C_MASTER_MODE_MODE		BIT(13)
>>>> -#define GPIO_I2S_MODE_MASK			BIT(12)
>>>> -#define GPIO_I2C_SLAVE_MODE_MODE		BIT(11)
>>>> -#define GPIO_LAN3_LED1_MODE_MASK		BIT(10)
>>>> -#define GPIO_LAN3_LED0_MODE_MASK		BIT(9)
>>>> -#define GPIO_LAN2_LED1_MODE_MASK		BIT(8)
>>>> -#define GPIO_LAN2_LED0_MODE_MASK		BIT(7)
>>>> -#define GPIO_LAN1_LED1_MODE_MASK		BIT(6)
>>>> -#define GPIO_LAN1_LED0_MODE_MASK		BIT(5)
>>>> -#define GPIO_LAN0_LED1_MODE_MASK		BIT(4)
>>>> -#define GPIO_LAN0_LED0_MODE_MASK		BIT(3)
>>>> -#define PON_TOD_1PPS_MODE_MASK			BIT(2)
>>>> -#define GSW_TOD_1PPS_MODE_MASK			BIT(1)
>>>> -#define GPIO_2ND_I2C_MODE_MASK			BIT(0)
>>>> -
>>>> -#define REG_GPIO_SPI_CS1_MODE			0x0218
>>>> -#define GPIO_PCM_SPI_CS4_MODE_MASK		BIT(21)
>>>> -#define GPIO_PCM_SPI_CS3_MODE_MASK		BIT(20)
>>>> -#define GPIO_PCM_SPI_CS2_MODE_P156_MASK		BIT(19)
>>>> -#define GPIO_PCM_SPI_CS2_MODE_P128_MASK		BIT(18)
>>>> -#define AN7583_GPIO_PCM_SPI_CS2_MODE_MASK	BIT(18)
>>>> -#define GPIO_PCM_SPI_CS1_MODE_MASK		BIT(17)
>>>> -#define GPIO_PCM_SPI_MODE_MASK			BIT(16)
>>>> -#define GPIO_PCM2_MODE_MASK			BIT(13)
>>>> -#define GPIO_PCM1_MODE_MASK			BIT(12)
>>>> -#define GPIO_PCM_INT_MODE_MASK			BIT(9)
>>>> -#define GPIO_PCM_RESET_MODE_MASK		BIT(8)
>>>> -#define GPIO_SPI_QUAD_MODE_MASK			BIT(4)
>>>> -#define GPIO_SPI_CS4_MODE_MASK			BIT(3)
>>>> -#define GPIO_SPI_CS3_MODE_MASK			BIT(2)
>>>> -#define GPIO_SPI_CS2_MODE_MASK			BIT(1)
>>>> -#define GPIO_SPI_CS1_MODE_MASK			BIT(0)
>>>> -
>>>> -#define REG_GPIO_PON_MODE			0x021c
>>>> -#define AN7583_MDIO_0_GPIO_MODE_MASK		BIT(26)
>>>> -#define AN7583_MDC_0_GPIO_MODE_MASK		BIT(25)
>>>> -#define AN7583_UART_RXD_GPIO_MODE_MASK		BIT(24)
>>>> -#define AN7583_UART_TXD_GPIO_MODE_MASK		BIT(23)
>>>> -#define AN7583_SPI_MISO_GPIO_MODE_MASK		BIT(22)
>>>> -#define AN7583_SPI_MOSI_GPIO_MODE_MASK		BIT(21)
>>>> -#define AN7583_SPI_CS_GPIO_MODE_MASK		BIT(20)
>>>> -#define AN7583_SPI_CLK_GPIO_MODE_MASK		BIT(19)
>>>> -#define AN7583_I2C1_SDA_GPIO_MODE_MASK		BIT(18)
>>>> -#define AN7583_I2C1_SCL_GPIO_MODE_MASK		BIT(17)
>>>> -#define AN7583_I2C0_SDA_GPIO_MODE_MASK		BIT(16)
>>>> -#define AN7583_I2C0_SCL_GPIO_MODE_MASK		BIT(15)
>>>> -#define GPIO_PARALLEL_NAND_MODE_MASK		BIT(14)
>>>> -#define GPIO_SGMII_MDIO_MODE_MASK		BIT(13)
>>>> -#define GPIO_PCIE_RESET2_MASK			BIT(12)
>>>> -#define SIPO_RCLK_MODE_MASK			BIT(11)
>>>> -#define GPIO_PCIE_RESET1_MASK			BIT(10)
>>>> -#define GPIO_PCIE_RESET0_MASK			BIT(9)
>>>> -#define GPIO_UART5_MODE_MASK			BIT(8)
>>>> -#define GPIO_UART4_MODE_MASK			BIT(7)
>>>> -#define GPIO_HSUART_CTS_RTS_MODE_MASK		BIT(6)
>>>> -#define GPIO_HSUART_MODE_MASK			BIT(5)
>>>> -#define GPIO_UART2_CTS_RTS_MODE_MASK		BIT(4)
>>>> -#define GPIO_UART2_MODE_MASK			BIT(3)
>>>> -#define GPIO_SIPO_MODE_MASK			BIT(2)
>>>> -#define GPIO_EMMC_MODE_MASK			BIT(1)
>>>> -#define GPIO_PON_MODE_MASK			BIT(0)
>>>> -
>>>> -#define REG_NPU_UART_EN				0x0224
>>>> -#define JTAG_UDI_EN_MASK			BIT(4)
>>>> -#define JTAG_DFD_EN_MASK			BIT(3)
>>>> -
>>>> -#define REG_FORCE_GPIO_EN			0x0228
>>>> -#define FORCE_GPIO_EN(n)			BIT(n)
>>>> -
>>>> -/* LED MAP */
>>>> -#define REG_LAN_LED0_MAPPING			0x027c
>>>> -#define REG_LAN_LED1_MAPPING			0x0280
>>>> -
>>>> -#define LAN4_LED_MAPPING_MASK			GENMASK(18, 16)
>>>> -#define LAN4_PHY_LED_MAP(_n)			FIELD_PREP_CONST(LAN4_LED_MAPPING_MASK, (_n))
>>>> -
>>>> -#define LAN3_LED_MAPPING_MASK			GENMASK(14, 12)
>>>> -#define LAN3_PHY_LED_MAP(_n)			FIELD_PREP_CONST(LAN3_LED_MAPPING_MASK, (_n))
>>>> -
>>>> -#define LAN2_LED_MAPPING_MASK			GENMASK(10, 8)
>>>> -#define LAN2_PHY_LED_MAP(_n)			FIELD_PREP_CONST(LAN2_LED_MAPPING_MASK, (_n))
>>>> -
>>>> -#define LAN1_LED_MAPPING_MASK			GENMASK(6, 4)
>>>> -#define LAN1_PHY_LED_MAP(_n)			FIELD_PREP_CONST(LAN1_LED_MAPPING_MASK, (_n))
>>>> -
>>>> -#define LAN0_LED_MAPPING_MASK			GENMASK(2, 0)
>>>> -#define LAN0_PHY_LED_MAP(_n)			FIELD_PREP_CONST(LAN0_LED_MAPPING_MASK, (_n))
>>>> -
>>>> -/* CONF */
>>>> -#define REG_I2C_SDA_E2				0x001c
>>>> -#define AN7583_I2C1_SCL_E2_MASK			BIT(16)
>>>> -#define AN7583_I2C1_SDA_E2_MASK			BIT(15)
>>>> -#define SPI_MISO_E2_MASK			BIT(14)
>>>> -#define SPI_MOSI_E2_MASK			BIT(13)
>>>> -#define SPI_CLK_E2_MASK				BIT(12)
>>>> -#define SPI_CS0_E2_MASK				BIT(11)
>>>> -#define PCIE2_RESET_E2_MASK			BIT(10)
>>>> -#define PCIE1_RESET_E2_MASK			BIT(9)
>>>> -#define PCIE0_RESET_E2_MASK			BIT(8)
>>>> -#define AN7583_MDIO_0_E2_MASK			BIT(5)
>>>> -#define AN7583_MDC_0_E2_MASK			BIT(4)
>>>> -#define UART1_RXD_E2_MASK			BIT(3)
>>>> -#define UART1_TXD_E2_MASK			BIT(2)
>>>> -#define I2C_SCL_E2_MASK				BIT(1)
>>>> -#define I2C_SDA_E2_MASK				BIT(0)
>>>> -
>>>> -#define REG_I2C_SDA_E4				0x0020
>>>> -#define AN7583_I2C1_SCL_E4_MASK			BIT(16)
>>>> -#define AN7583_I2C1_SDA_E4_MASK			BIT(15)
>>>> -#define SPI_MISO_E4_MASK			BIT(14)
>>>> -#define SPI_MOSI_E4_MASK			BIT(13)
>>>> -#define SPI_CLK_E4_MASK				BIT(12)
>>>> -#define SPI_CS0_E4_MASK				BIT(11)
>>>> -#define PCIE2_RESET_E4_MASK			BIT(10)
>>>> -#define PCIE1_RESET_E4_MASK			BIT(9)
>>>> -#define PCIE0_RESET_E4_MASK			BIT(8)
>>>> -#define AN7583_MDIO_0_E4_MASK			BIT(5)
>>>> -#define AN7583_MDC_0_E4_MASK			BIT(4)
>>>> -#define UART1_RXD_E4_MASK			BIT(3)
>>>> -#define UART1_TXD_E4_MASK			BIT(2)
>>>> -#define I2C_SCL_E4_MASK				BIT(1)
>>>> -#define I2C_SDA_E4_MASK				BIT(0)
>>>> -
>>>> -#define REG_GPIO_L_E2				0x0024
>>>> -#define REG_GPIO_L_E4				0x0028
>>>> -#define REG_GPIO_H_E2				0x002c
>>>> -#define REG_GPIO_H_E4				0x0030
>>>> -
>>>> -#define REG_I2C_SDA_PU				0x0044
>>>> -#define AN7583_I2C1_SCL_PU_MASK			BIT(16)
>>>> -#define AN7583_I2C1_SDA_PU_MASK			BIT(15)
>>>> -#define SPI_MISO_PU_MASK			BIT(14)
>>>> -#define SPI_MOSI_PU_MASK			BIT(13)
>>>> -#define SPI_CLK_PU_MASK				BIT(12)
>>>> -#define SPI_CS0_PU_MASK				BIT(11)
>>>> -#define PCIE2_RESET_PU_MASK			BIT(10)
>>>> -#define PCIE1_RESET_PU_MASK			BIT(9)
>>>> -#define PCIE0_RESET_PU_MASK			BIT(8)
>>>> -#define AN7583_MDIO_0_PU_MASK			BIT(5)
>>>> -#define AN7583_MDC_0_PU_MASK			BIT(4)
>>>> -#define UART1_RXD_PU_MASK			BIT(3)
>>>> -#define UART1_TXD_PU_MASK			BIT(2)
>>>> -#define I2C_SCL_PU_MASK				BIT(1)
>>>> -#define I2C_SDA_PU_MASK				BIT(0)
>>>> -
>>>> -#define REG_I2C_SDA_PD				0x0048
>>>> -#define AN7583_I2C1_SCL_PD_MASK			BIT(16)
>>>> -#define AN7583_I2C1_SDA_PD_MASK			BIT(15)
>>>> -#define SPI_MISO_PD_MASK			BIT(14)
>>>> -#define SPI_MOSI_PD_MASK			BIT(13)
>>>> -#define SPI_CLK_PD_MASK				BIT(12)
>>>> -#define SPI_CS0_PD_MASK				BIT(11)
>>>> -#define PCIE2_RESET_PD_MASK			BIT(10)
>>>> -#define PCIE1_RESET_PD_MASK			BIT(9)
>>>> -#define PCIE0_RESET_PD_MASK			BIT(8)
>>>> -#define AN7583_MDIO_0_PD_MASK			BIT(5)
>>>> -#define AN7583_MDC_0_PD_MASK			BIT(4)
>>>> -#define UART1_RXD_PD_MASK			BIT(3)
>>>> -#define UART1_TXD_PD_MASK			BIT(2)
>>>> -#define I2C_SCL_PD_MASK				BIT(1)
>>>> -#define I2C_SDA_PD_MASK				BIT(0)
>>>> -
>>>> -#define REG_GPIO_L_PU				0x004c
>>>> -#define REG_GPIO_L_PD				0x0050
>>>> -#define REG_GPIO_H_PU				0x0054
>>>> -#define REG_GPIO_H_PD				0x0058
>>>> -
>>>> -#define REG_PCIE_RESET_OD			0x018c
>>>> -#define PCIE2_RESET_OD_MASK			BIT(2)
>>>> -#define PCIE1_RESET_OD_MASK			BIT(1)
>>>> -#define PCIE0_RESET_OD_MASK			BIT(0)
>>>> -
>>>> -/* GPIOs */
>>>> -#define REG_GPIO_CTRL				0x0000
>>>> -#define REG_GPIO_DATA				0x0004
>>>> -#define REG_GPIO_INT				0x0008
>>>> -#define REG_GPIO_INT_EDGE			0x000c
>>>> -#define REG_GPIO_INT_LEVEL			0x0010
>>>> -#define REG_GPIO_OE				0x0014
>>>> -#define REG_GPIO_CTRL1				0x0020
>>>> -#define REG_GPIO_CTRL2				0x0060
>>>> -#define REG_GPIO_CTRL3				0x0064
>>>> -
>>>> -/* PWM MODE CONF */
>>>> -#define REG_GPIO_FLASH_MODE_CFG			0x0034
>>>> -#define GPIO15_FLASH_MODE_CFG			BIT(15)
>>>> -#define GPIO14_FLASH_MODE_CFG			BIT(14)
>>>> -#define GPIO13_FLASH_MODE_CFG			BIT(13)
>>>> -#define GPIO12_FLASH_MODE_CFG			BIT(12)
>>>> -#define GPIO11_FLASH_MODE_CFG			BIT(11)
>>>> -#define GPIO10_FLASH_MODE_CFG			BIT(10)
>>>> -#define GPIO9_FLASH_MODE_CFG			BIT(9)
>>>> -#define GPIO8_FLASH_MODE_CFG			BIT(8)
>>>> -#define GPIO7_FLASH_MODE_CFG			BIT(7)
>>>> -#define GPIO6_FLASH_MODE_CFG			BIT(6)
>>>> -#define GPIO5_FLASH_MODE_CFG			BIT(5)
>>>> -#define GPIO4_FLASH_MODE_CFG			BIT(4)
>>>> -#define GPIO3_FLASH_MODE_CFG			BIT(3)
>>>> -#define GPIO2_FLASH_MODE_CFG			BIT(2)
>>>> -#define GPIO1_FLASH_MODE_CFG			BIT(1)
>>>> -#define GPIO0_FLASH_MODE_CFG			BIT(0)
>>>> -
>>>> -/* PWM MODE CONF EXT */
>>>> -#define REG_GPIO_FLASH_MODE_CFG_EXT		0x0068
>>>> -#define GPIO51_FLASH_MODE_CFG			BIT(31)
>>>> -#define GPIO50_FLASH_MODE_CFG			BIT(30)
>>>> -#define GPIO49_FLASH_MODE_CFG			BIT(29)
>>>> -#define GPIO48_FLASH_MODE_CFG			BIT(28)
>>>> -#define GPIO47_FLASH_MODE_CFG			BIT(27)
>>>> -#define GPIO46_FLASH_MODE_CFG			BIT(26)
>>>> -#define GPIO45_FLASH_MODE_CFG			BIT(25)
>>>> -#define GPIO44_FLASH_MODE_CFG			BIT(24)
>>>> -#define GPIO43_FLASH_MODE_CFG			BIT(23)
>>>> -#define GPIO42_FLASH_MODE_CFG			BIT(22)
>>>> -#define GPIO41_FLASH_MODE_CFG			BIT(21)
>>>> -#define GPIO40_FLASH_MODE_CFG			BIT(20)
>>>> -#define GPIO39_FLASH_MODE_CFG			BIT(19)
>>>> -#define GPIO38_FLASH_MODE_CFG			BIT(18)
>>>> -#define GPIO37_FLASH_MODE_CFG			BIT(17)
>>>> -#define GPIO36_FLASH_MODE_CFG			BIT(16)
>>>> -#define GPIO31_FLASH_MODE_CFG			BIT(15)
>>>> -#define GPIO30_FLASH_MODE_CFG			BIT(14)
>>>> -#define GPIO29_FLASH_MODE_CFG			BIT(13)
>>>> -#define GPIO28_FLASH_MODE_CFG			BIT(12)
>>>> -#define GPIO27_FLASH_MODE_CFG			BIT(11)
>>>> -#define GPIO26_FLASH_MODE_CFG			BIT(10)
>>>> -#define GPIO25_FLASH_MODE_CFG			BIT(9)
>>>> -#define GPIO24_FLASH_MODE_CFG			BIT(8)
>>>> -#define GPIO23_FLASH_MODE_CFG			BIT(7)
>>>> -#define GPIO22_FLASH_MODE_CFG			BIT(6)
>>>> -#define GPIO21_FLASH_MODE_CFG			BIT(5)
>>>> -#define GPIO20_FLASH_MODE_CFG			BIT(4)
>>>> -#define GPIO19_FLASH_MODE_CFG			BIT(3)
>>>> -#define GPIO18_FLASH_MODE_CFG			BIT(2)
>>>> -#define GPIO17_FLASH_MODE_CFG			BIT(1)
>>>> -#define GPIO16_FLASH_MODE_CFG			BIT(0)
>>>> -
>>>> -#define REG_GPIO_DATA1				0x0070
>>>> -#define REG_GPIO_OE1				0x0078
>>>> -#define REG_GPIO_INT1				0x007c
>>>> -#define REG_GPIO_INT_EDGE1			0x0080
>>>> -#define REG_GPIO_INT_EDGE2			0x0084
>>>> -#define REG_GPIO_INT_EDGE3			0x0088
>>>> -#define REG_GPIO_INT_LEVEL1			0x008c
>>>> -#define REG_GPIO_INT_LEVEL2			0x0090
>>>> -#define REG_GPIO_INT_LEVEL3			0x0094
>>>> -
>>>> -#define AIROHA_PINCTRL_GPIO(gpio, mux_val)			\
>>>> -	{							\
>>>> -		.name = (gpio),					\
>>>> -		.regmap[0] = {					\
>>>> -			AIROHA_FUNC_MUX,			\
>>>> -			REG_GPIO_PON_MODE,			\
>>>> -			(mux_val),				\
>>>> -			(mux_val)				\
>>>> -		},						\
>>>> -		.regmap_size = 1,				\
>>>> -	}
>>>> -
>>>> -#define AIROHA_PINCTRL_GPIO_EXT(gpio, mux_val, smux_val)	\
>>>> -	{							\
>>>> -		.name = (gpio),					\
>>>> -		.regmap[0] = {					\
>>>> -			AIROHA_FUNC_PWM_EXT_MUX,		\
>>>> -			REG_GPIO_FLASH_MODE_CFG_EXT,		\
>>>> -			(mux_val),				\
>>>> -			0					\
>>>> -		},						\
>>>> -		.regmap[1] = {					\
>>>> -			AIROHA_FUNC_MUX,			\
>>>> -			REG_GPIO_PON_MODE,			\
>>>> -			(smux_val),				\
>>>> -			(smux_val)				\
>>>> -		},						\
>>>> -		.regmap_size = 2,				\
>>>> -	}
>>>> -
>>>> -/* PWM */
>>>> -#define AIROHA_PINCTRL_PWM(gpio, mux_val)		\
>>>> -	{						\
>>>> -		.name = (gpio),				\
>>>> -		.regmap[0] = {				\
>>>> -			AIROHA_FUNC_PWM_MUX,		\
>>>> -			REG_GPIO_FLASH_MODE_CFG,	\
>>>> -			(mux_val),			\
>>>> -			(mux_val)			\
>>>> -		},					\
>>>> -		.regmap_size = 1,			\
>>>> -	}
>>>> -
>>>> -#define AIROHA_PINCTRL_PWM_EXT(gpio, mux_val)		\
>>>> -	{						\
>>>> -		.name = (gpio),				\
>>>> -		.regmap[0] = {				\
>>>> -			AIROHA_FUNC_PWM_EXT_MUX,	\
>>>> -			REG_GPIO_FLASH_MODE_CFG_EXT,	\
>>>> -			(mux_val),			\
>>>> -			(mux_val)			\
>>>> -		},					\
>>>> -		.regmap_size = 1,			\
>>>> -	}
>>>> -
>>>> -#define AIROHA_PINCTRL_PWM_EXT_SEC(gpio, mux_val, smux_val)	\
>>>> -	{							\
>>>> -		.name = (gpio),					\
>>>> -		.regmap[0] = {					\
>>>> -			AIROHA_FUNC_PWM_EXT_MUX,		\
>>>> -			REG_GPIO_FLASH_MODE_CFG_EXT,		\
>>>> -			(mux_val),				\
>>>> -			(mux_val)				\
>>>> -		},						\
>>>> -		.regmap[1] = {					\
>>>> -			AIROHA_FUNC_MUX,			\
>>>> -			REG_GPIO_PON_MODE,			\
>>>> -			(smux_val),				\
>>>> -			(smux_val)				\
>>>> -		},						\
>>>> -		.regmap_size = 2,				\
>>>> -	}
>>>> -
>>>> -#define AIROHA_PINCTRL_PHY_LED0(gpio, mux_val, map_mask, map_val)	\
>>>> -	{								\
>>>> -		.name = (gpio),						\
>>>> -		.regmap[0] = {						\
>>>> -			AIROHA_FUNC_MUX,				\
>>>> -			REG_GPIO_2ND_I2C_MODE,				\
>>>> -			(mux_val),					\
>>>> -			(mux_val),					\
>>>> -		},							\
>>>> -		.regmap[1] = {						\
>>>> -			AIROHA_FUNC_MUX,				\
>>>> -			REG_LAN_LED0_MAPPING,				\
>>>> -			(map_mask),					\
>>>> -			(map_val),					\
>>>> -		},							\
>>>> -		.regmap_size = 2,					\
>>>> -	}
>>>> -
>>>> -#define AIROHA_PINCTRL_PHY_LED1(gpio, mux_val, map_mask, map_val)	\
>>>> -	{								\
>>>> -		.name = (gpio),						\
>>>> -		.regmap[0] = {						\
>>>> -			AIROHA_FUNC_MUX,				\
>>>> -			REG_GPIO_2ND_I2C_MODE,				\
>>>> -			(mux_val),					\
>>>> -			(mux_val),					\
>>>> -		},							\
>>>> -		.regmap[1] = {						\
>>>> -			AIROHA_FUNC_MUX,				\
>>>> -			REG_LAN_LED1_MAPPING,				\
>>>> -			(map_mask),					\
>>>> -			(map_val),					\
>>>> -		},							\
>>>> -		.regmap_size = 2,					\
>>>> -	}
>>>> -
>>>>  #define airoha_pinctrl_get_pullup_conf(pinctrl, pin, val)			\
>>>>  	airoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_PULLUP,		\
>>>>  				(pin), (val))
>>>> @@ -433,1935 +74,6 @@ static const u32 irq_edge_regs[] = {
>>>>  	REG_GPIO_INT_EDGE3
>>>>  };
>>>>  
>>>> -static struct pinctrl_pin_desc en7581_pinctrl_pins[] = {
>>>> -	PINCTRL_PIN(0, "uart1_txd"),
>>>> -	PINCTRL_PIN(1, "uart1_rxd"),
>>>> -	PINCTRL_PIN(2, "i2c_scl"),
>>>> -	PINCTRL_PIN(3, "i2c_sda"),
>>>> -	PINCTRL_PIN(4, "spi_cs0"),
>>>> -	PINCTRL_PIN(5, "spi_clk"),
>>>> -	PINCTRL_PIN(6, "spi_mosi"),
>>>> -	PINCTRL_PIN(7, "spi_miso"),
>>>> -	PINCTRL_PIN(13, "gpio0"),
>>>> -	PINCTRL_PIN(14, "gpio1"),
>>>> -	PINCTRL_PIN(15, "gpio2"),
>>>> -	PINCTRL_PIN(16, "gpio3"),
>>>> -	PINCTRL_PIN(17, "gpio4"),
>>>> -	PINCTRL_PIN(18, "gpio5"),
>>>> -	PINCTRL_PIN(19, "gpio6"),
>>>> -	PINCTRL_PIN(20, "gpio7"),
>>>> -	PINCTRL_PIN(21, "gpio8"),
>>>> -	PINCTRL_PIN(22, "gpio9"),
>>>> -	PINCTRL_PIN(23, "gpio10"),
>>>> -	PINCTRL_PIN(24, "gpio11"),
>>>> -	PINCTRL_PIN(25, "gpio12"),
>>>> -	PINCTRL_PIN(26, "gpio13"),
>>>> -	PINCTRL_PIN(27, "gpio14"),
>>>> -	PINCTRL_PIN(28, "gpio15"),
>>>> -	PINCTRL_PIN(29, "gpio16"),
>>>> -	PINCTRL_PIN(30, "gpio17"),
>>>> -	PINCTRL_PIN(31, "gpio18"),
>>>> -	PINCTRL_PIN(32, "gpio19"),
>>>> -	PINCTRL_PIN(33, "gpio20"),
>>>> -	PINCTRL_PIN(34, "gpio21"),
>>>> -	PINCTRL_PIN(35, "gpio22"),
>>>> -	PINCTRL_PIN(36, "gpio23"),
>>>> -	PINCTRL_PIN(37, "gpio24"),
>>>> -	PINCTRL_PIN(38, "gpio25"),
>>>> -	PINCTRL_PIN(39, "gpio26"),
>>>> -	PINCTRL_PIN(40, "gpio27"),
>>>> -	PINCTRL_PIN(41, "gpio28"),
>>>> -	PINCTRL_PIN(42, "gpio29"),
>>>> -	PINCTRL_PIN(43, "gpio30"),
>>>> -	PINCTRL_PIN(44, "gpio31"),
>>>> -	PINCTRL_PIN(45, "gpio32"),
>>>> -	PINCTRL_PIN(46, "gpio33"),
>>>> -	PINCTRL_PIN(47, "gpio34"),
>>>> -	PINCTRL_PIN(48, "gpio35"),
>>>> -	PINCTRL_PIN(49, "gpio36"),
>>>> -	PINCTRL_PIN(50, "gpio37"),
>>>> -	PINCTRL_PIN(51, "gpio38"),
>>>> -	PINCTRL_PIN(52, "gpio39"),
>>>> -	PINCTRL_PIN(53, "gpio40"),
>>>> -	PINCTRL_PIN(54, "gpio41"),
>>>> -	PINCTRL_PIN(55, "gpio42"),
>>>> -	PINCTRL_PIN(56, "gpio43"),
>>>> -	PINCTRL_PIN(57, "gpio44"),
>>>> -	PINCTRL_PIN(58, "gpio45"),
>>>> -	PINCTRL_PIN(59, "gpio46"),
>>>> -	PINCTRL_PIN(60, "pcie_reset0"),
>>>> -	PINCTRL_PIN(61, "pcie_reset1"),
>>>> -	PINCTRL_PIN(62, "pcie_reset2"),
>>>> -};
>>>> -
>>>> -static const int en7581_pon_pins[] = { 49, 50, 51, 52, 53, 54 };
>>>> -static const int en7581_pon_tod_1pps_pins[] = { 46 };
>>>> -static const int en7581_gsw_tod_1pps_pins[] = { 46 };
>>>> -static const int en7581_sipo_pins[] = { 16, 17 };
>>>> -static const int en7581_sipo_rclk_pins[] = { 16, 17, 43 };
>>>> -static const int en7581_mdio_pins[] = { 14, 15 };
>>>> -static const int en7581_uart2_pins[] = { 48, 55 };
>>>> -static const int en7581_uart2_cts_rts_pins[] = { 46, 47 };
>>>> -static const int en7581_hsuart_pins[] = { 28, 29 };
>>>> -static const int en7581_hsuart_cts_rts_pins[] = { 26, 27 };
>>>> -static const int en7581_uart4_pins[] = { 38, 39 };
>>>> -static const int en7581_uart5_pins[] = { 18, 19 };
>>>> -static const int en7581_i2c0_pins[] = { 2, 3 };
>>>> -static const int en7581_i2c1_pins[] = { 14, 15 };
>>>> -static const int en7581_jtag_udi_pins[] = { 16, 17, 18, 19, 20 };
>>>> -static const int en7581_jtag_dfd_pins[] = { 16, 17, 18, 19, 20 };
>>>> -static const int en7581_i2s_pins[] = { 26, 27, 28, 29 };
>>>> -static const int en7581_pcm1_pins[] = { 22, 23, 24, 25 };
>>>> -static const int en7581_pcm2_pins[] = { 18, 19, 20, 21 };
>>>> -static const int en7581_spi_quad_pins[] = { 32, 33 };
>>>> -static const int en7581_spi_pins[] = { 4, 5, 6, 7 };
>>>> -static const int en7581_spi_cs1_pins[] = { 34 };
>>>> -static const int en7581_pcm_spi_pins[] = { 18, 19, 20, 21, 22, 23, 24, 25 };
>>>> -static const int en7581_pcm_spi_int_pins[] = { 14 };
>>>> -static const int en7581_pcm_spi_rst_pins[] = { 15 };
>>>> -static const int en7581_pcm_spi_cs1_pins[] = { 43 };
>>>> -static const int en7581_pcm_spi_cs2_pins[] = { 40 };
>>>> -static const int en7581_pcm_spi_cs2_p128_pins[] = { 40 };
>>>> -static const int en7581_pcm_spi_cs2_p156_pins[] = { 40 };
>>>> -static const int en7581_pcm_spi_cs3_pins[] = { 41 };
>>>> -static const int en7581_pcm_spi_cs4_pins[] = { 42 };
>>>> -static const int en7581_emmc_pins[] = { 4, 5, 6, 30, 31, 32, 33, 34, 35, 36, 37 };
>>>> -static const int en7581_pnand_pins[] = { 4, 5, 6, 7, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42 };
>>>> -static const int en7581_gpio0_pins[] = { 13 };
>>>> -static const int en7581_gpio1_pins[] = { 14 };
>>>> -static const int en7581_gpio2_pins[] = { 15 };
>>>> -static const int en7581_gpio3_pins[] = { 16 };
>>>> -static const int en7581_gpio4_pins[] = { 17 };
>>>> -static const int en7581_gpio5_pins[] = { 18 };
>>>> -static const int en7581_gpio6_pins[] = { 19 };
>>>> -static const int en7581_gpio7_pins[] = { 20 };
>>>> -static const int en7581_gpio8_pins[] = { 21 };
>>>> -static const int en7581_gpio9_pins[] = { 22 };
>>>> -static const int en7581_gpio10_pins[] = { 23 };
>>>> -static const int en7581_gpio11_pins[] = { 24 };
>>>> -static const int en7581_gpio12_pins[] = { 25 };
>>>> -static const int en7581_gpio13_pins[] = { 26 };
>>>> -static const int en7581_gpio14_pins[] = { 27 };
>>>> -static const int en7581_gpio15_pins[] = { 28 };
>>>> -static const int en7581_gpio16_pins[] = { 29 };
>>>> -static const int en7581_gpio17_pins[] = { 30 };
>>>> -static const int en7581_gpio18_pins[] = { 31 };
>>>> -static const int en7581_gpio19_pins[] = { 32 };
>>>> -static const int en7581_gpio20_pins[] = { 33 };
>>>> -static const int en7581_gpio21_pins[] = { 34 };
>>>> -static const int en7581_gpio22_pins[] = { 35 };
>>>> -static const int en7581_gpio23_pins[] = { 36 };
>>>> -static const int en7581_gpio24_pins[] = { 37 };
>>>> -static const int en7581_gpio25_pins[] = { 38 };
>>>> -static const int en7581_gpio26_pins[] = { 39 };
>>>> -static const int en7581_gpio27_pins[] = { 40 };
>>>> -static const int en7581_gpio28_pins[] = { 41 };
>>>> -static const int en7581_gpio29_pins[] = { 42 };
>>>> -static const int en7581_gpio30_pins[] = { 43 };
>>>> -static const int en7581_gpio31_pins[] = { 44 };
>>>> -static const int en7581_gpio32_pins[] = { 45 };
>>>> -static const int en7581_gpio33_pins[] = { 46 };
>>>> -static const int en7581_gpio34_pins[] = { 47 };
>>>> -static const int en7581_gpio35_pins[] = { 48 };
>>>> -static const int en7581_gpio36_pins[] = { 49 };
>>>> -static const int en7581_gpio37_pins[] = { 50 };
>>>> -static const int en7581_gpio38_pins[] = { 51 };
>>>> -static const int en7581_gpio39_pins[] = { 52 };
>>>> -static const int en7581_gpio40_pins[] = { 53 };
>>>> -static const int en7581_gpio41_pins[] = { 54 };
>>>> -static const int en7581_gpio42_pins[] = { 55 };
>>>> -static const int en7581_gpio43_pins[] = { 56 };
>>>> -static const int en7581_gpio44_pins[] = { 57 };
>>>> -static const int en7581_gpio45_pins[] = { 58 };
>>>> -static const int en7581_gpio46_pins[] = { 59 };
>>>> -static const int en7581_gpio47_pins[] = { 60 };
>>>> -static const int en7581_gpio48_pins[] = { 61 };
>>>> -static const int en7581_gpio49_pins[] = { 62 };
>>>> -static const int en7581_pcie_reset0_pins[] = { 60 };
>>>> -static const int en7581_pcie_reset1_pins[] = { 61 };
>>>> -static const int en7581_pcie_reset2_pins[] = { 62 };
>>>> -
>>>> -static const struct pingroup en7581_pinctrl_groups[] = {
>>>> -	PINCTRL_PIN_GROUP("pon", en7581_pon),
>>>> -	PINCTRL_PIN_GROUP("pon_tod_1pps", en7581_pon_tod_1pps),
>>>> -	PINCTRL_PIN_GROUP("gsw_tod_1pps", en7581_gsw_tod_1pps),
>>>> -	PINCTRL_PIN_GROUP("sipo", en7581_sipo),
>>>> -	PINCTRL_PIN_GROUP("sipo_rclk", en7581_sipo_rclk),
>>>> -	PINCTRL_PIN_GROUP("mdio", en7581_mdio),
>>>> -	PINCTRL_PIN_GROUP("uart2", en7581_uart2),
>>>> -	PINCTRL_PIN_GROUP("uart2_cts_rts", en7581_uart2_cts_rts),
>>>> -	PINCTRL_PIN_GROUP("hsuart", en7581_hsuart),
>>>> -	PINCTRL_PIN_GROUP("hsuart_cts_rts", en7581_hsuart_cts_rts),
>>>> -	PINCTRL_PIN_GROUP("uart4", en7581_uart4),
>>>> -	PINCTRL_PIN_GROUP("uart5", en7581_uart5),
>>>> -	PINCTRL_PIN_GROUP("i2c0", en7581_i2c0),
>>>> -	PINCTRL_PIN_GROUP("i2c1", en7581_i2c1),
>>>> -	PINCTRL_PIN_GROUP("jtag_udi", en7581_jtag_udi),
>>>> -	PINCTRL_PIN_GROUP("jtag_dfd", en7581_jtag_dfd),
>>>> -	PINCTRL_PIN_GROUP("i2s", en7581_i2s),
>>>> -	PINCTRL_PIN_GROUP("pcm1", en7581_pcm1),
>>>> -	PINCTRL_PIN_GROUP("pcm2", en7581_pcm2),
>>>> -	PINCTRL_PIN_GROUP("spi", en7581_spi),
>>>> -	PINCTRL_PIN_GROUP("spi_quad", en7581_spi_quad),
>>>> -	PINCTRL_PIN_GROUP("spi_cs1", en7581_spi_cs1),
>>>> -	PINCTRL_PIN_GROUP("pcm_spi", en7581_pcm_spi),
>>>> -	PINCTRL_PIN_GROUP("pcm_spi_int", en7581_pcm_spi_int),
>>>> -	PINCTRL_PIN_GROUP("pcm_spi_rst", en7581_pcm_spi_rst),
>>>> -	PINCTRL_PIN_GROUP("pcm_spi_cs1", en7581_pcm_spi_cs1),
>>>> -	PINCTRL_PIN_GROUP("pcm_spi_cs2_p128", en7581_pcm_spi_cs2_p128),
>>>> -	PINCTRL_PIN_GROUP("pcm_spi_cs2_p156", en7581_pcm_spi_cs2_p156),
>>>> -	PINCTRL_PIN_GROUP("pcm_spi_cs2", en7581_pcm_spi_cs2),
>>>> -	PINCTRL_PIN_GROUP("pcm_spi_cs3", en7581_pcm_spi_cs3),
>>>> -	PINCTRL_PIN_GROUP("pcm_spi_cs4", en7581_pcm_spi_cs4),
>>>> -	PINCTRL_PIN_GROUP("emmc", en7581_emmc),
>>>> -	PINCTRL_PIN_GROUP("pnand", en7581_pnand),
>>>> -	PINCTRL_PIN_GROUP("gpio0", en7581_gpio0),
>>>> -	PINCTRL_PIN_GROUP("gpio1", en7581_gpio1),
>>>> -	PINCTRL_PIN_GROUP("gpio2", en7581_gpio2),
>>>> -	PINCTRL_PIN_GROUP("gpio3", en7581_gpio3),
>>>> -	PINCTRL_PIN_GROUP("gpio4", en7581_gpio4),
>>>> -	PINCTRL_PIN_GROUP("gpio5", en7581_gpio5),
>>>> -	PINCTRL_PIN_GROUP("gpio6", en7581_gpio6),
>>>> -	PINCTRL_PIN_GROUP("gpio7", en7581_gpio7),
>>>> -	PINCTRL_PIN_GROUP("gpio8", en7581_gpio8),
>>>> -	PINCTRL_PIN_GROUP("gpio9", en7581_gpio9),
>>>> -	PINCTRL_PIN_GROUP("gpio10", en7581_gpio10),
>>>> -	PINCTRL_PIN_GROUP("gpio11", en7581_gpio11),
>>>> -	PINCTRL_PIN_GROUP("gpio12", en7581_gpio12),
>>>> -	PINCTRL_PIN_GROUP("gpio13", en7581_gpio13),
>>>> -	PINCTRL_PIN_GROUP("gpio14", en7581_gpio14),
>>>> -	PINCTRL_PIN_GROUP("gpio15", en7581_gpio15),
>>>> -	PINCTRL_PIN_GROUP("gpio16", en7581_gpio16),
>>>> -	PINCTRL_PIN_GROUP("gpio17", en7581_gpio17),
>>>> -	PINCTRL_PIN_GROUP("gpio18", en7581_gpio18),
>>>> -	PINCTRL_PIN_GROUP("gpio19", en7581_gpio19),
>>>> -	PINCTRL_PIN_GROUP("gpio20", en7581_gpio20),
>>>> -	PINCTRL_PIN_GROUP("gpio21", en7581_gpio21),
>>>> -	PINCTRL_PIN_GROUP("gpio22", en7581_gpio22),
>>>> -	PINCTRL_PIN_GROUP("gpio23", en7581_gpio23),
>>>> -	PINCTRL_PIN_GROUP("gpio24", en7581_gpio24),
>>>> -	PINCTRL_PIN_GROUP("gpio25", en7581_gpio25),
>>>> -	PINCTRL_PIN_GROUP("gpio26", en7581_gpio26),
>>>> -	PINCTRL_PIN_GROUP("gpio27", en7581_gpio27),
>>>> -	PINCTRL_PIN_GROUP("gpio28", en7581_gpio28),
>>>> -	PINCTRL_PIN_GROUP("gpio29", en7581_gpio29),
>>>> -	PINCTRL_PIN_GROUP("gpio30", en7581_gpio30),
>>>> -	PINCTRL_PIN_GROUP("gpio31", en7581_gpio31),
>>>> -	PINCTRL_PIN_GROUP("gpio32", en7581_gpio32),
>>>> -	PINCTRL_PIN_GROUP("gpio33", en7581_gpio33),
>>>> -	PINCTRL_PIN_GROUP("gpio34", en7581_gpio34),
>>>> -	PINCTRL_PIN_GROUP("gpio35", en7581_gpio35),
>>>> -	PINCTRL_PIN_GROUP("gpio36", en7581_gpio36),
>>>> -	PINCTRL_PIN_GROUP("gpio37", en7581_gpio37),
>>>> -	PINCTRL_PIN_GROUP("gpio38", en7581_gpio38),
>>>> -	PINCTRL_PIN_GROUP("gpio39", en7581_gpio39),
>>>> -	PINCTRL_PIN_GROUP("gpio40", en7581_gpio40),
>>>> -	PINCTRL_PIN_GROUP("gpio41", en7581_gpio41),
>>>> -	PINCTRL_PIN_GROUP("gpio42", en7581_gpio42),
>>>> -	PINCTRL_PIN_GROUP("gpio43", en7581_gpio43),
>>>> -	PINCTRL_PIN_GROUP("gpio44", en7581_gpio44),
>>>> -	PINCTRL_PIN_GROUP("gpio45", en7581_gpio45),
>>>> -	PINCTRL_PIN_GROUP("gpio46", en7581_gpio46),
>>>> -	PINCTRL_PIN_GROUP("gpio47", en7581_gpio47),
>>>> -	PINCTRL_PIN_GROUP("gpio48", en7581_gpio48),
>>>> -	PINCTRL_PIN_GROUP("gpio49", en7581_gpio49),
>>>> -	PINCTRL_PIN_GROUP("pcie_reset0", en7581_pcie_reset0),
>>>> -	PINCTRL_PIN_GROUP("pcie_reset1", en7581_pcie_reset1),
>>>> -	PINCTRL_PIN_GROUP("pcie_reset2", en7581_pcie_reset2),
>>>> -};
>>>> -
>>>> -static struct pinctrl_pin_desc an7583_pinctrl_pins[] = {
>>>> -	PINCTRL_PIN(2, "gpio0"),
>>>> -	PINCTRL_PIN(3, "gpio1"),
>>>> -	PINCTRL_PIN(4, "gpio2"),
>>>> -	PINCTRL_PIN(5, "gpio3"),
>>>> -	PINCTRL_PIN(6, "gpio4"),
>>>> -	PINCTRL_PIN(7, "gpio5"),
>>>> -	PINCTRL_PIN(8, "gpio6"),
>>>> -	PINCTRL_PIN(9, "gpio7"),
>>>> -	PINCTRL_PIN(10, "gpio8"),
>>>> -	PINCTRL_PIN(11, "gpio9"),
>>>> -	PINCTRL_PIN(12, "gpio10"),
>>>> -	PINCTRL_PIN(13, "gpio11"),
>>>> -	PINCTRL_PIN(14, "gpio12"),
>>>> -	PINCTRL_PIN(15, "gpio13"),
>>>> -	PINCTRL_PIN(16, "gpio14"),
>>>> -	PINCTRL_PIN(17, "gpio15"),
>>>> -	PINCTRL_PIN(18, "gpio16"),
>>>> -	PINCTRL_PIN(19, "gpio17"),
>>>> -	PINCTRL_PIN(20, "gpio18"),
>>>> -	PINCTRL_PIN(21, "gpio19"),
>>>> -	PINCTRL_PIN(22, "gpio20"),
>>>> -	PINCTRL_PIN(23, "gpio21"),
>>>> -	PINCTRL_PIN(24, "gpio22"),
>>>> -	PINCTRL_PIN(25, "gpio23"),
>>>> -	PINCTRL_PIN(26, "gpio24"),
>>>> -	PINCTRL_PIN(27, "gpio25"),
>>>> -	PINCTRL_PIN(28, "gpio26"),
>>>> -	PINCTRL_PIN(29, "gpio27"),
>>>> -	PINCTRL_PIN(30, "gpio28"),
>>>> -	PINCTRL_PIN(31, "gpio29"),
>>>> -	PINCTRL_PIN(32, "gpio30"),
>>>> -	PINCTRL_PIN(33, "gpio31"),
>>>> -	PINCTRL_PIN(34, "gpio32"),
>>>> -	PINCTRL_PIN(35, "gpio33"),
>>>> -	PINCTRL_PIN(36, "gpio34"),
>>>> -	PINCTRL_PIN(37, "gpio35"),
>>>> -	PINCTRL_PIN(38, "gpio36"),
>>>> -	PINCTRL_PIN(39, "gpio37"),
>>>> -	PINCTRL_PIN(40, "gpio38"),
>>>> -	PINCTRL_PIN(41, "i2c0_scl"),
>>>> -	PINCTRL_PIN(42, "i2c0_sda"),
>>>> -	PINCTRL_PIN(43, "i2c1_scl"),
>>>> -	PINCTRL_PIN(44, "i2c1_sda"),
>>>> -	PINCTRL_PIN(45, "spi_clk"),
>>>> -	PINCTRL_PIN(46, "spi_cs"),
>>>> -	PINCTRL_PIN(47, "spi_mosi"),
>>>> -	PINCTRL_PIN(48, "spi_miso"),
>>>> -	PINCTRL_PIN(49, "uart_txd"),
>>>> -	PINCTRL_PIN(50, "uart_rxd"),
>>>> -	PINCTRL_PIN(51, "pcie_reset0"),
>>>> -	PINCTRL_PIN(52, "pcie_reset1"),
>>>> -	PINCTRL_PIN(53, "mdc_0"),
>>>> -	PINCTRL_PIN(54, "mdio_0"),
>>>> -};
>>>> -
>>>> -static const int an7583_pon_pins[] = { 15, 16, 17, 18, 19, 20 };
>>>> -static const int an7583_pon_tod_1pps_pins[] = { 32 };
>>>> -static const int an7583_gsw_tod_1pps_pins[] = { 32 };
>>>> -static const int an7583_sipo_pins[] = { 34, 35 };
>>>> -static const int an7583_sipo_rclk_pins[] = { 34, 35, 33 };
>>>> -static const int an7583_mdio_pins[] = { 43, 44 };
>>>> -static const int an7583_uart2_pins[] = { 34, 35 };
>>>> -static const int an7583_uart2_cts_rts_pins[] = { 32, 33 };
>>>> -static const int an7583_hsuart_pins[] = { 30, 31 };
>>>> -static const int an7583_hsuart_cts_rts_pins[] = { 28, 29 };
>>>> -static const int an7583_npu_uart_pins[] = { 7, 8 };
>>>> -static const int an7583_uart4_pins[] = { 7, 8 };
>>>> -static const int an7583_uart5_pins[] = { 23, 24 };
>>>> -static const int an7583_i2c0_pins[] = { 41, 42 };
>>>> -static const int an7583_i2c1_pins[] = { 43, 44 };
>>>> -static const int an7583_jtag_udi_pins[] = { 23, 24, 22, 25, 26 };
>>>> -static const int an7583_jtag_dfd_pins[] = { 23, 24, 22, 25, 26 };
>>>> -static const int an7583_pcm1_pins[] = { 10, 11, 12, 13, 14 };
>>>> -static const int an7583_pcm2_pins[] = { 28, 29, 30, 31, 24 };
>>>> -static const int an7583_spi_pins[] = { 28, 29, 30, 31 };
>>>> -static const int an7583_spi_quad_pins[] = { 25, 26 };
>>>> -static const int an7583_spi_cs1_pins[] = { 27 };
>>>> -static const int an7583_pcm_spi_pins[] = { 28, 29, 30, 31, 10, 11, 12, 13 };
>>>> -static const int an7583_pcm_spi_rst_pins[] = { 14 };
>>>> -static const int an7583_pcm_spi_cs1_pins[] = { 24 };
>>>> -static const int an7583_emmc_pins[] = { 7, 8, 9, 22, 23, 24, 25, 26, 45, 46, 47 };
>>>> -static const int an7583_pnand_pins[] = { 7, 8, 9, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 45, 46, 47, 48 };
>>>> -static const int an7583_gpio0_pins[] = { 2 };
>>>> -static const int an7583_gpio1_pins[] = { 3 };
>>>> -static const int an7583_gpio2_pins[] = { 4 };
>>>> -static const int an7583_gpio3_pins[] = { 5 };
>>>> -static const int an7583_gpio4_pins[] = { 6 };
>>>> -static const int an7583_gpio5_pins[] = { 7 };
>>>> -static const int an7583_gpio6_pins[] = { 8 };
>>>> -static const int an7583_gpio7_pins[] = { 9 };
>>>> -static const int an7583_gpio8_pins[] = { 10 };
>>>> -static const int an7583_gpio9_pins[] = { 11 };
>>>> -static const int an7583_gpio10_pins[] = { 12 };
>>>> -static const int an7583_gpio11_pins[] = { 13 };
>>>> -static const int an7583_gpio12_pins[] = { 14 };
>>>> -static const int an7583_gpio13_pins[] = { 15 };
>>>> -static const int an7583_gpio14_pins[] = { 16 };
>>>> -static const int an7583_gpio15_pins[] = { 17 };
>>>> -static const int an7583_gpio16_pins[] = { 18 };
>>>> -static const int an7583_gpio17_pins[] = { 19 };
>>>> -static const int an7583_gpio18_pins[] = { 20 };
>>>> -static const int an7583_gpio19_pins[] = { 21 };
>>>> -static const int an7583_gpio20_pins[] = { 22 };
>>>> -static const int an7583_gpio21_pins[] = { 23 };
>>>> -static const int an7583_gpio22_pins[] = { 24 };
>>>> -static const int an7583_gpio23_pins[] = { 25 };
>>>> -static const int an7583_gpio24_pins[] = { 26 };
>>>> -static const int an7583_gpio25_pins[] = { 27 };
>>>> -static const int an7583_gpio26_pins[] = { 28 };
>>>> -static const int an7583_gpio27_pins[] = { 29 };
>>>> -static const int an7583_gpio28_pins[] = { 30 };
>>>> -static const int an7583_gpio29_pins[] = { 31 };
>>>> -static const int an7583_gpio30_pins[] = { 32 };
>>>> -static const int an7583_gpio31_pins[] = { 33 };
>>>> -static const int an7583_gpio32_pins[] = { 34 };
>>>> -static const int an7583_gpio33_pins[] = { 35 };
>>>> -static const int an7583_gpio34_pins[] = { 36 };
>>>> -static const int an7583_gpio35_pins[] = { 37 };
>>>> -static const int an7583_gpio36_pins[] = { 38 };
>>>> -static const int an7583_gpio37_pins[] = { 39 };
>>>> -static const int an7583_gpio38_pins[] = { 40 };
>>>> -static const int an7583_gpio39_pins[] = { 41 };
>>>> -static const int an7583_gpio40_pins[] = { 42 };
>>>> -static const int an7583_gpio41_pins[] = { 43 };
>>>> -static const int an7583_gpio42_pins[] = { 44 };
>>>> -static const int an7583_gpio43_pins[] = { 45 };
>>>> -static const int an7583_gpio44_pins[] = { 46 };
>>>> -static const int an7583_gpio45_pins[] = { 47 };
>>>> -static const int an7583_gpio46_pins[] = { 48 };
>>>> -static const int an7583_gpio47_pins[] = { 49 };
>>>> -static const int an7583_gpio48_pins[] = { 50 };
>>>> -static const int an7583_gpio49_pins[] = { 51 };
>>>> -static const int an7583_gpio50_pins[] = { 52 };
>>>> -static const int an7583_gpio51_pins[] = { 53 };
>>>> -static const int an7583_gpio52_pins[] = { 54 };
>>>> -static const int an7583_pcie_reset0_pins[] = { 51 };
>>>> -static const int an7583_pcie_reset1_pins[] = { 52 };
>>>> -
>>>> -static const struct pingroup an7583_pinctrl_groups[] = {
>>>> -	PINCTRL_PIN_GROUP("pon", an7583_pon),
>>>> -	PINCTRL_PIN_GROUP("pon_tod_1pps", an7583_pon_tod_1pps),
>>>> -	PINCTRL_PIN_GROUP("gsw_tod_1pps", an7583_gsw_tod_1pps),
>>>> -	PINCTRL_PIN_GROUP("sipo", an7583_sipo),
>>>> -	PINCTRL_PIN_GROUP("sipo_rclk", an7583_sipo_rclk),
>>>> -	PINCTRL_PIN_GROUP("mdio", an7583_mdio),
>>>> -	PINCTRL_PIN_GROUP("uart2", an7583_uart2),
>>>> -	PINCTRL_PIN_GROUP("uart2_cts_rts", an7583_uart2_cts_rts),
>>>> -	PINCTRL_PIN_GROUP("hsuart", an7583_hsuart),
>>>> -	PINCTRL_PIN_GROUP("hsuart_cts_rts", an7583_hsuart_cts_rts),
>>>> -	PINCTRL_PIN_GROUP("npu_uart", an7583_npu_uart),
>>>> -	PINCTRL_PIN_GROUP("uart4", an7583_uart4),
>>>> -	PINCTRL_PIN_GROUP("uart5", an7583_uart5),
>>>> -	PINCTRL_PIN_GROUP("i2c0", an7583_i2c0),
>>>> -	PINCTRL_PIN_GROUP("i2c1", an7583_i2c1),
>>>> -	PINCTRL_PIN_GROUP("jtag_udi", an7583_jtag_udi),
>>>> -	PINCTRL_PIN_GROUP("jtag_dfd", an7583_jtag_dfd),
>>>> -	PINCTRL_PIN_GROUP("pcm1", an7583_pcm1),
>>>> -	PINCTRL_PIN_GROUP("pcm2", an7583_pcm2),
>>>> -	PINCTRL_PIN_GROUP("spi", an7583_spi),
>>>> -	PINCTRL_PIN_GROUP("spi_quad", an7583_spi_quad),
>>>> -	PINCTRL_PIN_GROUP("spi_cs1", an7583_spi_cs1),
>>>> -	PINCTRL_PIN_GROUP("pcm_spi", an7583_pcm_spi),
>>>> -	PINCTRL_PIN_GROUP("pcm_spi_rst", an7583_pcm_spi_rst),
>>>> -	PINCTRL_PIN_GROUP("pcm_spi_cs1", an7583_pcm_spi_cs1),
>>>> -	PINCTRL_PIN_GROUP("emmc", an7583_emmc),
>>>> -	PINCTRL_PIN_GROUP("pnand", an7583_pnand),
>>>> -	PINCTRL_PIN_GROUP("gpio0", an7583_gpio0),
>>>> -	PINCTRL_PIN_GROUP("gpio1", an7583_gpio1),
>>>> -	PINCTRL_PIN_GROUP("gpio2", an7583_gpio2),
>>>> -	PINCTRL_PIN_GROUP("gpio3", an7583_gpio3),
>>>> -	PINCTRL_PIN_GROUP("gpio4", an7583_gpio4),
>>>> -	PINCTRL_PIN_GROUP("gpio5", an7583_gpio5),
>>>> -	PINCTRL_PIN_GROUP("gpio6", an7583_gpio6),
>>>> -	PINCTRL_PIN_GROUP("gpio7", an7583_gpio7),
>>>> -	PINCTRL_PIN_GROUP("gpio8", an7583_gpio8),
>>>> -	PINCTRL_PIN_GROUP("gpio9", an7583_gpio9),
>>>> -	PINCTRL_PIN_GROUP("gpio10", an7583_gpio10),
>>>> -	PINCTRL_PIN_GROUP("gpio11", an7583_gpio11),
>>>> -	PINCTRL_PIN_GROUP("gpio12", an7583_gpio12),
>>>> -	PINCTRL_PIN_GROUP("gpio13", an7583_gpio13),
>>>> -	PINCTRL_PIN_GROUP("gpio14", an7583_gpio14),
>>>> -	PINCTRL_PIN_GROUP("gpio15", an7583_gpio15),
>>>> -	PINCTRL_PIN_GROUP("gpio16", an7583_gpio16),
>>>> -	PINCTRL_PIN_GROUP("gpio17", an7583_gpio17),
>>>> -	PINCTRL_PIN_GROUP("gpio18", an7583_gpio18),
>>>> -	PINCTRL_PIN_GROUP("gpio19", an7583_gpio19),
>>>> -	PINCTRL_PIN_GROUP("gpio20", an7583_gpio20),
>>>> -	PINCTRL_PIN_GROUP("gpio21", an7583_gpio21),
>>>> -	PINCTRL_PIN_GROUP("gpio22", an7583_gpio22),
>>>> -	PINCTRL_PIN_GROUP("gpio23", an7583_gpio23),
>>>> -	PINCTRL_PIN_GROUP("gpio24", an7583_gpio24),
>>>> -	PINCTRL_PIN_GROUP("gpio25", an7583_gpio25),
>>>> -	PINCTRL_PIN_GROUP("gpio26", an7583_gpio26),
>>>> -	PINCTRL_PIN_GROUP("gpio27", an7583_gpio27),
>>>> -	PINCTRL_PIN_GROUP("gpio28", an7583_gpio28),
>>>> -	PINCTRL_PIN_GROUP("gpio29", an7583_gpio29),
>>>> -	PINCTRL_PIN_GROUP("gpio30", an7583_gpio30),
>>>> -	PINCTRL_PIN_GROUP("gpio31", an7583_gpio31),
>>>> -	PINCTRL_PIN_GROUP("gpio32", an7583_gpio32),
>>>> -	PINCTRL_PIN_GROUP("gpio33", an7583_gpio33),
>>>> -	PINCTRL_PIN_GROUP("gpio34", an7583_gpio34),
>>>> -	PINCTRL_PIN_GROUP("gpio35", an7583_gpio35),
>>>> -	PINCTRL_PIN_GROUP("gpio36", an7583_gpio36),
>>>> -	PINCTRL_PIN_GROUP("gpio37", an7583_gpio37),
>>>> -	PINCTRL_PIN_GROUP("gpio38", an7583_gpio38),
>>>> -	PINCTRL_PIN_GROUP("gpio39", an7583_gpio39),
>>>> -	PINCTRL_PIN_GROUP("gpio40", an7583_gpio40),
>>>> -	PINCTRL_PIN_GROUP("gpio41", an7583_gpio41),
>>>> -	PINCTRL_PIN_GROUP("gpio42", an7583_gpio42),
>>>> -	PINCTRL_PIN_GROUP("gpio43", an7583_gpio43),
>>>> -	PINCTRL_PIN_GROUP("gpio44", an7583_gpio44),
>>>> -	PINCTRL_PIN_GROUP("gpio45", an7583_gpio45),
>>>> -	PINCTRL_PIN_GROUP("gpio46", an7583_gpio46),
>>>> -	PINCTRL_PIN_GROUP("gpio47", an7583_gpio47),
>>>> -	PINCTRL_PIN_GROUP("gpio48", an7583_gpio48),
>>>> -	PINCTRL_PIN_GROUP("gpio49", an7583_gpio49),
>>>> -	PINCTRL_PIN_GROUP("gpio50", an7583_gpio50),
>>>> -	PINCTRL_PIN_GROUP("gpio51", an7583_gpio51),
>>>> -	PINCTRL_PIN_GROUP("gpio52", an7583_gpio52),
>>>> -	PINCTRL_PIN_GROUP("pcie_reset0", an7583_pcie_reset0),
>>>> -	PINCTRL_PIN_GROUP("pcie_reset1", an7583_pcie_reset1),
>>>> -};
>>>> -
>>>> -static const char *const pon_groups[] = { "pon" };
>>>> -static const char *const tod_1pps_groups[] = { "pon_tod_1pps", "gsw_tod_1pps" };
>>>> -static const char *const sipo_groups[] = { "sipo", "sipo_rclk" };
>>>> -static const char *const mdio_groups[] = { "mdio" };
>>>> -static const char *const an7583_mdio_groups[] = { "mdio" };
>>>> -static const char *const uart_groups[] = { "uart2", "uart2_cts_rts", "hsuart",
>>>> -					   "hsuart_cts_rts", "uart4",
>>>> -					   "uart5" };
>>>> -static const char *const i2c_groups[] = { "i2c1" };
>>>> -static const char *const jtag_groups[] = { "jtag_udi", "jtag_dfd" };
>>>> -static const char *const pcm_groups[] = { "pcm1", "pcm2" };
>>>> -static const char *const spi_groups[] = { "spi_quad", "spi_cs1" };
>>>> -static const char *const pcm_spi_groups[] = { "pcm_spi", "pcm_spi_int",
>>>> -					      "pcm_spi_rst", "pcm_spi_cs1",
>>>> -					      "pcm_spi_cs2_p156",
>>>> -					      "pcm_spi_cs2_p128",
>>>> -					      "pcm_spi_cs3", "pcm_spi_cs4" };
>>>> -static const char *const an7583_pcm_spi_groups[] = { "pcm_spi",
>>>> -						     "pcm_spi_rst", "pcm_spi_cs1" };
>>>> -static const char *const i2s_groups[] = { "i2s" };
>>>> -static const char *const emmc_groups[] = { "emmc" };
>>>> -static const char *const pnand_groups[] = { "pnand" };
>>>> -static const char *const gpio_groups[] = { "gpio47", "gpio48", "gpio49" };
>>>> -static const char *const pcie_reset_groups[] = { "pcie_reset0", "pcie_reset1",
>>>> -						 "pcie_reset2" };
>>>> -static const char *const an7583_gpio_groups[] = { "gpio39", "gpio40", "gpio41",
>>>> -						  "gpio42", "gpio43", "gpio44",
>>>> -						  "gpio45", "gpio46", "gpio47",
>>>> -						  "gpio48", "gpio49", "gpio50",
>>>> -						  "gpio51", "gpio52" };
>>>> -static const char *const an7583_pcie_reset_groups[] = { "pcie_reset0", "pcie_reset1" };
>>>> -static const char *const pwm_groups[] = { "gpio0", "gpio1",
>>>> -					  "gpio2", "gpio3",
>>>> -					  "gpio4", "gpio5",
>>>> -					  "gpio6", "gpio7",
>>>> -					  "gpio8", "gpio9",
>>>> -					  "gpio10", "gpio11",
>>>> -					  "gpio12", "gpio13",
>>>> -					  "gpio14", "gpio15",
>>>> -					  "gpio16", "gpio17",
>>>> -					  "gpio18", "gpio19",
>>>> -					  "gpio20", "gpio21",
>>>> -					  "gpio22", "gpio23",
>>>> -					  "gpio24", "gpio25",
>>>> -					  "gpio26", "gpio27",
>>>> -					  "gpio28", "gpio29",
>>>> -					  "gpio30", "gpio31",
>>>> -					  "gpio36", "gpio37",
>>>> -					  "gpio38", "gpio39",
>>>> -					  "gpio40", "gpio41",
>>>> -					  "gpio42", "gpio43",
>>>> -					  "gpio44", "gpio45",
>>>> -					  "gpio46", "gpio47",
>>>> -					  "gpio48", "gpio49" };
>>>> -static const char *const an7583_pwm_groups[] = { "gpio0", "gpio1",
>>>> -						 "gpio2", "gpio3",
>>>> -						 "gpio4", "gpio5",
>>>> -						 "gpio6", "gpio7",
>>>> -						 "gpio8", "gpio9",
>>>> -						 "gpio10", "gpio11",
>>>> -						 "gpio12", "gpio13",
>>>> -						 "gpio14", "gpio15",
>>>> -						 "gpio16", "gpio17",
>>>> -						 "gpio18", "gpio19",
>>>> -						 "gpio20", "gpio21",
>>>> -						 "gpio22", "gpio23",
>>>> -						 "gpio24", "gpio25",
>>>> -						 "gpio26", "gpio27",
>>>> -						 "gpio28", "gpio29",
>>>> -						 "gpio30", "gpio31",
>>>> -						 "gpio36", "gpio37",
>>>> -						 "gpio38", "gpio39",
>>>> -						 "gpio40", "gpio41",
>>>> -						 "gpio42", "gpio43",
>>>> -						 "gpio44", "gpio45",
>>>> -						 "gpio46", "gpio47",
>>>> -						 "gpio48", "gpio49",
>>>> -						 "gpio50", "gpio51" };
>>>> -static const char *const phy1_led0_groups[] = { "gpio33", "gpio34",
>>>> -						"gpio35", "gpio42" };
>>>> -static const char *const phy2_led0_groups[] = { "gpio33", "gpio34",
>>>> -						"gpio35", "gpio42" };
>>>> -static const char *const phy3_led0_groups[] = { "gpio33", "gpio34",
>>>> -						"gpio35", "gpio42" };
>>>> -static const char *const phy4_led0_groups[] = { "gpio33", "gpio34",
>>>> -						"gpio35", "gpio42" };
>>>> -static const char *const phy1_led1_groups[] = { "gpio43", "gpio44",
>>>> -						"gpio45", "gpio46" };
>>>> -static const char *const phy2_led1_groups[] = { "gpio43", "gpio44",
>>>> -						"gpio45", "gpio46" };
>>>> -static const char *const phy3_led1_groups[] = { "gpio43", "gpio44",
>>>> -						"gpio45", "gpio46" };
>>>> -static const char *const phy4_led1_groups[] = { "gpio43", "gpio44",
>>>> -						"gpio45", "gpio46" };
>>>> -static const char *const an7583_phy1_led0_groups[] = { "gpio1", "gpio2",
>>>> -							"gpio3", "gpio4" };
>>>> -static const char *const an7583_phy2_led0_groups[] = { "gpio1", "gpio2",
>>>> -							"gpio3", "gpio4" };
>>>> -static const char *const an7583_phy3_led0_groups[] = { "gpio1", "gpio2",
>>>> -							"gpio3", "gpio4" };
>>>> -static const char *const an7583_phy4_led0_groups[] = { "gpio1", "gpio2",
>>>> -							"gpio3", "gpio4" };
>>>> -static const char *const an7583_phy1_led1_groups[] = { "gpio8", "gpio9",
>>>> -							"gpio10", "gpio11" };
>>>> -static const char *const an7583_phy2_led1_groups[] = { "gpio8", "gpio9",
>>>> -							"gpio10", "gpio11" };
>>>> -static const char *const an7583_phy3_led1_groups[] = { "gpio8", "gpio9",
>>>> -							"gpio10", "gpio11" };
>>>> -static const char *const an7583_phy4_led1_groups[] = { "gpio8", "gpio9",
>>>> -							"gpio10", "gpio11" };
>>>> -
>>>> -static const struct airoha_pinctrl_func_group pon_func_group[] = {
>>>> -	{
>>>> -		.name = "pon",
>>>> -		.regmap[0] = {
>>>> -			AIROHA_FUNC_MUX,
>>>> -			REG_GPIO_PON_MODE,
>>>> -			GPIO_PON_MODE_MASK,
>>>> -			GPIO_PON_MODE_MASK
>>>> -		},
>>>> -		.regmap_size = 1,
>>>> -	},
>>>> -};
>>>> -
>>>> -static const struct airoha_pinctrl_func_group tod_1pps_func_group[] = {
>>>> -	{
>>>> -		.name = "pon_tod_1pps",
>>>> -		.regmap[0] = {
>>>> -			AIROHA_FUNC_MUX,
>>>> -			REG_GPIO_2ND_I2C_MODE,
>>>> -			PON_TOD_1PPS_MODE_MASK,
>>>> -			PON_TOD_1PPS_MODE_MASK
>>>> -		},
>>>> -		.regmap_size = 1,
>>>> -	}, {
>>>> -		.name = "gsw_tod_1pps",
>>>> -		.regmap[0] = {
>>>> -			AIROHA_FUNC_MUX,
>>>> -			REG_GPIO_2ND_I2C_MODE,
>>>> -			GSW_TOD_1PPS_MODE_MASK,
>>>> -			GSW_TOD_1PPS_MODE_MASK
>>>> -		},
>>>> -		.regmap_size = 1,
>>>> -	},
>>>> -};
>>>> -
>>>> -static const struct airoha_pinctrl_func_group sipo_func_group[] = {
>>>> -	{
>>>> -		.name = "sipo",
>>>> -		.regmap[0] = {
>>>> -			AIROHA_FUNC_MUX,
>>>> -			REG_GPIO_PON_MODE,
>>>> -			GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK,
>>>> -			GPIO_SIPO_MODE_MASK
>>>> -		},
>>>> -		.regmap_size = 1,
>>>> -	}, {
>>>> -		.name = "sipo_rclk",
>>>> -		.regmap[0] = {
>>>> -			AIROHA_FUNC_MUX,
>>>> -			REG_GPIO_PON_MODE,
>>>> -			GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK,
>>>> -			GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK
>>>> -		},
>>>> -		.regmap_size = 1,
>>>> -	},
>>>> -};
>>>> -
>>>> -static const struct airoha_pinctrl_func_group mdio_func_group[] = {
>>>> -	{
>>>> -		.name = "mdio",
>>>> -		.regmap[0] = {
>>>> -			AIROHA_FUNC_MUX,
>>>> -			REG_GPIO_2ND_I2C_MODE,
>>>> -			GPIO_MDC_IO_MASTER_MODE_MASK,
>>>> -			GPIO_MDC_IO_MASTER_MODE_MASK
>>>> -		},
>>>> -		.regmap[1] = {
>>>> -			AIROHA_FUNC_MUX,
>>>> -			REG_FORCE_GPIO_EN,
>>>> -			FORCE_GPIO_EN(1) | FORCE_GPIO_EN(2),
>>>> -			FORCE_GPIO_EN(1) | FORCE_GPIO_EN(2)
>>>> -		},
>>>> -		.regmap_size = 2,
>>>> -	},
>>>> -};
>>>> -
>>>> -static const struct airoha_pinctrl_func_group an7583_mdio_func_group[] = {
>>>> -	{
>>>> -		.name = "mdio",
>>>> -		.regmap[0] = {
>>>> -			AIROHA_FUNC_MUX,
>>>> -			REG_GPIO_PON_MODE,
>>>> -			GPIO_SGMII_MDIO_MODE_MASK,
>>>> -			GPIO_SGMII_MDIO_MODE_MASK
>>>> -		},
>>>> -		.regmap[1] = {
>>>> -			AIROHA_FUNC_MUX,
>>>> -			REG_GPIO_SPI_CS1_MODE,
>>>> -			GPIO_MDC_IO_MASTER_MODE_MASK,
>>>> -			GPIO_MDC_IO_MASTER_MODE_MASK
>>>> -		},
>>>> -		.regmap_size = 2,
>>>> -	},
>>>> -};
>>>> -
>>>> -static const struct airoha_pinctrl_func_group uart_func_group[] = {
>>>> -	{
>>>> -		.name = "uart2",
>>>> -		.regmap[0] = {
>>>> -			AIROHA_FUNC_MUX,
>>>> -			REG_GPIO_PON_MODE,
>>>> -			GPIO_UART2_MODE_MASK,
>>>> -			GPIO_UART2_MODE_MASK
>>>> -		},
>>>> -		.regmap_size = 1,
>>>> -	}, {
>>>> -		.name = "uart2_cts_rts",
>>>> -		.regmap[0] = {
>>>> -			AIROHA_FUNC_MUX,
>>>> -			REG_GPIO_PON_MODE,
>>>> -			GPIO_UART2_MODE_MASK | GPIO_UART2_CTS_RTS_MODE_MASK,
>>>> -			GPIO_UART2_MODE_MASK | GPIO_UART2_CTS_RTS_MODE_MASK
>>>> -		},
>>>> -		.regmap_size = 1,
>>>> -	}, {
>>>> -		.name = "hsuart",
>>>> -		.regmap[0] = {
>>>> -			AIROHA_FUNC_MUX,
>>>> -			REG_GPIO_PON_MODE,
>>>> -			GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK,
>>>> -			GPIO_HSUART_MODE_MASK
>>>> -		},
>>>> -		.regmap_size = 1,
>>>> -	},
>>>> -	{
>>>> -		.name = "hsuart_cts_rts",
>>>> -		.regmap[0] = {
>>>> -			AIROHA_FUNC_MUX,
>>>> -			REG_GPIO_PON_MODE,
>>>> -			GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK,
>>>> -			GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK
>>>> -		},
>>>> -		.regmap_size = 1,
>>>> -	}, {
>>>> -		.name = "uart4",
>>>> -		.regmap[0] = {
>>>> -			AIROHA_FUNC_MUX,
>>>> -			REG_GPIO_PON_MODE,
>>>> -			GPIO_UART4_MODE_MASK,
>>>> -			GPIO_UART4_MODE_MASK
>>>> -		},
>>>> -		.regmap_size = 1,
>>>> -	}, {
>>>> -		.name = "uart5",
>>>> -		.regmap[0] = {
>>>> -			AIROHA_FUNC_MUX,
>>>> -			REG_GPIO_PON_MODE,
>>>> -			GPIO_UART5_MODE_MASK,
>>>> -			GPIO_UART5_MODE_MASK
>>>> -		},
>>>> -		.regmap_size = 1,
>>>> -	},
>>>> -};
>>>> -
>>>> -static const struct airoha_pinctrl_func_group i2c_func_group[] = {
>>>> -	{
>>>> -		.name = "i2c1",
>>>> -		.regmap[0] = {
>>>> -			AIROHA_FUNC_MUX,
>>>> -			REG_GPIO_2ND_I2C_MODE,
>>>> -			GPIO_2ND_I2C_MODE_MASK,
>>>> -			GPIO_2ND_I2C_MODE_MASK
>>>> -		},
>>>> -		.regmap_size = 1,
>>>> -	},
>>>> -};
>>>> -
>>>> -static const struct airoha_pinctrl_func_group jtag_func_group[] = {
>>>> -	{
>>>> -		.name = "jtag_udi",
>>>> -		.regmap[0] = {
>>>> -			AIROHA_FUNC_MUX,
>>>> -			REG_NPU_UART_EN,
>>>> -			JTAG_UDI_EN_MASK,
>>>> -			JTAG_UDI_EN_MASK
>>>> -		},
>>>> -		.regmap_size = 1,
>>>> -	}, {
>>>> -		.name = "jtag_dfd",
>>>> -		.regmap[0] = {
>>>> -			AIROHA_FUNC_MUX,
>>>> -			REG_NPU_UART_EN,
>>>> -			JTAG_DFD_EN_MASK,
>>>> -			JTAG_DFD_EN_MASK
>>>> -		},
>>>> -		.regmap_size = 1,
>>>> -	},
>>>> -};
>>>> -
>>>> -static const struct airoha_pinctrl_func_group pcm_func_group[] = {
>>>> -	{
>>>> -		.name = "pcm1",
>>>> -		.regmap[0] = {
>>>> -			AIROHA_FUNC_MUX,
>>>> -			REG_GPIO_SPI_CS1_MODE,
>>>> -			GPIO_PCM1_MODE_MASK,
>>>> -			GPIO_PCM1_MODE_MASK
>>>> -		},
>>>> -		.regmap_size = 1,
>>>> -	}, {
>>>> -		.name = "pcm2",
>>>> -		.regmap[0] = {
>>>> -			AIROHA_FUNC_MUX,
>>>> -			REG_GPIO_SPI_CS1_MODE,
>>>> -			GPIO_PCM2_MODE_MASK,
>>>> -			GPIO_PCM2_MODE_MASK
>>>> -		},
>>>> -		.regmap_size = 1,
>>>> -	},
>>>> -};
>>>> -
>>>> -static const struct airoha_pinctrl_func_group spi_func_group[] = {
>>>> -	{
>>>> -		.name = "spi_quad",
>>>> -		.regmap[0] = {
>>>> -			AIROHA_FUNC_MUX,
>>>> -			REG_GPIO_SPI_CS1_MODE,
>>>> -			GPIO_SPI_QUAD_MODE_MASK,
>>>> -			GPIO_SPI_QUAD_MODE_MASK
>>>> -		},
>>>> -		.regmap_size = 1,
>>>> -	}, {
>>>> -		.name = "spi_cs1",
>>>> -		.regmap[0] = {
>>>> -			AIROHA_FUNC_MUX,
>>>> -			REG_GPIO_SPI_CS1_MODE,
>>>> -			GPIO_SPI_CS1_MODE_MASK,
>>>> -			GPIO_SPI_CS1_MODE_MASK
>>>> -		},
>>>> -		.regmap_size = 1,
>>>> -	}, {
>>>> -		.name = "spi_cs2",
>>>> -		.regmap[0] = {
>>>> -			AIROHA_FUNC_MUX,
>>>> -			REG_GPIO_SPI_CS1_MODE,
>>>> -			GPIO_SPI_CS2_MODE_MASK,
>>>> -			GPIO_SPI_CS2_MODE_MASK
>>>> -		},
>>>> -		.regmap_size = 1,
>>>> -	}, {
>>>> -		.name = "spi_cs3",
>>>> -		.regmap[0] = {
>>>> -			AIROHA_FUNC_MUX,
>>>> -			REG_GPIO_SPI_CS1_MODE,
>>>> -			GPIO_SPI_CS3_MODE_MASK,
>>>> -			GPIO_SPI_CS3_MODE_MASK
>>>> -		},
>>>> -		.regmap_size = 1,
>>>> -	}, {
>>>> -		.name = "spi_cs4",
>>>> -		.regmap[0] = {
>>>> -			AIROHA_FUNC_MUX,
>>>> -			REG_GPIO_SPI_CS1_MODE,
>>>> -			GPIO_SPI_CS4_MODE_MASK,
>>>> -			GPIO_SPI_CS4_MODE_MASK
>>>> -		},
>>>> -		.regmap_size = 1,
>>>> -	},
>>>> -};
>>>> -
>>>> -static const struct airoha_pinctrl_func_group pcm_spi_func_group[] = {
>>>> -	{
>>>> -		.name = "pcm_spi",
>>>> -		.regmap[0] = {
>>>> -			AIROHA_FUNC_MUX,
>>>> -			REG_GPIO_SPI_CS1_MODE,
>>>> -			GPIO_PCM_SPI_MODE_MASK,
>>>> -			GPIO_PCM_SPI_MODE_MASK
>>>> -		},
>>>> -		.regmap_size = 1,
>>>> -	}, {
>>>> -		.name = "pcm_spi_int",
>>>> -		.regmap[0] = {
>>>> -			AIROHA_FUNC_MUX,
>>>> -			REG_GPIO_SPI_CS1_MODE,
>>>> -			GPIO_PCM_INT_MODE_MASK,
>>>> -			GPIO_PCM_INT_MODE_MASK
>>>> -		},
>>>> -		.regmap_size = 1,
>>>> -	}, {
>>>> -		.name = "pcm_spi_rst",
>>>> -		.regmap[0] = {
>>>> -			AIROHA_FUNC_MUX,
>>>> -			REG_GPIO_SPI_CS1_MODE,
>>>> -			GPIO_PCM_RESET_MODE_MASK,
>>>> -			GPIO_PCM_RESET_MODE_MASK
>>>> -		},
>>>> -		.regmap_size = 1,
>>>> -	}, {
>>>> -		.name = "pcm_spi_cs1",
>>>> -		.regmap[0] = {
>>>> -			AIROHA_FUNC_MUX,
>>>> -			REG_GPIO_SPI_CS1_MODE,
>>>> -			GPIO_PCM_SPI_CS1_MODE_MASK,
>>>> -			GPIO_PCM_SPI_CS1_MODE_MASK
>>>> -		},
>>>> -		.regmap_size = 1,
>>>> -	}, {
>>>> -		.name = "pcm_spi_cs2_p128",
>>>> -		.regmap[0] = {
>>>> -			AIROHA_FUNC_MUX,
>>>> -			REG_GPIO_SPI_CS1_MODE,
>>>> -			GPIO_PCM_SPI_CS2_MODE_P128_MASK,
>>>> -			GPIO_PCM_SPI_CS2_MODE_P128_MASK
>>>> -		},
>>>> -		.regmap_size = 1,
>>>> -	}, {
>>>> -		.name = "pcm_spi_cs2_p156",
>>>> -		.regmap[0] = {
>>>> -			AIROHA_FUNC_MUX,
>>>> -			REG_GPIO_SPI_CS1_MODE,
>>>> -			GPIO_PCM_SPI_CS2_MODE_P156_MASK,
>>>> -			GPIO_PCM_SPI_CS2_MODE_P156_MASK
>>>> -		},
>>>> -		.regmap_size = 1,
>>>> -	}, {
>>>> -		.name = "pcm_spi_cs3",
>>>> -		.regmap[0] = {
>>>> -			AIROHA_FUNC_MUX,
>>>> -			REG_GPIO_SPI_CS1_MODE,
>>>> -			GPIO_PCM_SPI_CS3_MODE_MASK,
>>>> -			GPIO_PCM_SPI_CS3_MODE_MASK
>>>> -		},
>>>> -		.regmap_size = 1,
>>>> -	}, {
>>>> -		.name = "pcm_spi_cs4",
>>>> -		.regmap[0] = {
>>>> -			AIROHA_FUNC_MUX,
>>>> -			REG_GPIO_SPI_CS1_MODE,
>>>> -			GPIO_PCM_SPI_CS4_MODE_MASK,
>>>> -			GPIO_PCM_SPI_CS4_MODE_MASK
>>>> -		},
>>>> -		.regmap_size = 1,
>>>> -	},
>>>> -};
>>>> -
>>>> -static const struct airoha_pinctrl_func_group an7583_pcm_spi_func_group[] = {
>>>> -	{
>>>> -		.name = "pcm_spi",
>>>> -		.regmap[0] = {
>>>> -			AIROHA_FUNC_MUX,
>>>> -			REG_GPIO_SPI_CS1_MODE,
>>>> -			GPIO_PCM_SPI_MODE_MASK,
>>>> -			GPIO_PCM_SPI_MODE_MASK
>>>> -		},
>>>> -		.regmap_size = 1,
>>>> -	}, {
>>>> -		.name = "pcm_spi_int",
>>>> -		.regmap[0] = {
>>>> -			AIROHA_FUNC_MUX,
>>>> -			REG_GPIO_SPI_CS1_MODE,
>>>> -			GPIO_PCM_INT_MODE_MASK,
>>>> -			GPIO_PCM_INT_MODE_MASK
>>>> -		},
>>>> -		.regmap_size = 1,
>>>> -	}, {
>>>> -		.name = "pcm_spi_rst",
>>>> -		.regmap[0] = {
>>>> -			AIROHA_FUNC_MUX,
>>>> -			REG_GPIO_SPI_CS1_MODE,
>>>> -			GPIO_PCM_RESET_MODE_MASK,
>>>> -			GPIO_PCM_RESET_MODE_MASK
>>>> -		},
>>>> -		.regmap_size = 1,
>>>> -	}, {
>>>> -		.name = "pcm_spi_cs1",
>>>> -		.regmap[0] = {
>>>> -			AIROHA_FUNC_MUX,
>>>> -			REG_GPIO_SPI_CS1_MODE,
>>>> -			GPIO_PCM_SPI_CS1_MODE_MASK,
>>>> -			GPIO_PCM_SPI_CS1_MODE_MASK
>>>> -		},
>>>> -		.regmap_size = 1,
>>>> -	}, {
>>>> -		.name = "pcm_spi_cs2",
>>>> -		.regmap[0] = {
>>>> -			AIROHA_FUNC_MUX,
>>>> -			REG_GPIO_SPI_CS1_MODE,
>>>> -			AN7583_GPIO_PCM_SPI_CS2_MODE_MASK,
>>>> -			AN7583_GPIO_PCM_SPI_CS2_MODE_MASK
>>>> -		},
>>>> -		.regmap_size = 1,
>>>> -	}, {
>>>> -		.name = "pcm_spi_cs3",
>>>> -		.regmap[0] = {
>>>> -			AIROHA_FUNC_MUX,
>>>> -			REG_GPIO_SPI_CS1_MODE,
>>>> -			GPIO_PCM_SPI_CS3_MODE_MASK,
>>>> -			GPIO_PCM_SPI_CS3_MODE_MASK
>>>> -		},
>>>> -		.regmap_size = 1,
>>>> -	}, {
>>>> -		.name = "pcm_spi_cs4",
>>>> -		.regmap[0] = {
>>>> -			AIROHA_FUNC_MUX,
>>>> -			REG_GPIO_SPI_CS1_MODE,
>>>> -			GPIO_PCM_SPI_CS4_MODE_MASK,
>>>> -			GPIO_PCM_SPI_CS4_MODE_MASK
>>>> -		},
>>>> -		.regmap_size = 1,
>>>> -	},
>>>> -};
>>>> -
>>>> -static const struct airoha_pinctrl_func_group i2s_func_group[] = {
>>>> -	{
>>>> -		.name = "i2s",
>>>> -		.regmap[0] = {
>>>> -			AIROHA_FUNC_MUX,
>>>> -			REG_GPIO_2ND_I2C_MODE,
>>>> -			GPIO_I2S_MODE_MASK,
>>>> -			GPIO_I2S_MODE_MASK
>>>> -		},
>>>> -		.regmap_size = 1,
>>>> -	},
>>>> -};
>>>> -
>>>> -static const struct airoha_pinctrl_func_group emmc_func_group[] = {
>>>> -	{
>>>> -		.name = "emmc",
>>>> -		.regmap[0] = {
>>>> -			AIROHA_FUNC_MUX,
>>>> -			REG_GPIO_PON_MODE,
>>>> -			GPIO_EMMC_MODE_MASK,
>>>> -			GPIO_EMMC_MODE_MASK
>>>> -		},
>>>> -		.regmap_size = 1,
>>>> -	},
>>>> -};
>>>> -
>>>> -static const struct airoha_pinctrl_func_group pnand_func_group[] = {
>>>> -	{
>>>> -		.name = "pnand",
>>>> -		.regmap[0] = {
>>>> -			AIROHA_FUNC_MUX,
>>>> -			REG_GPIO_PON_MODE,
>>>> -			GPIO_PARALLEL_NAND_MODE_MASK,
>>>> -			GPIO_PARALLEL_NAND_MODE_MASK
>>>> -		},
>>>> -		.regmap_size = 1,
>>>> -	},
>>>> -};
>>>> -
>>>> -static const struct airoha_pinctrl_func_group gpio_func_group[] = {
>>>> -	AIROHA_PINCTRL_GPIO_EXT("gpio47", GPIO47_FLASH_MODE_CFG,
>>>> -				GPIO_PCIE_RESET0_MASK),
>>>> -	AIROHA_PINCTRL_GPIO_EXT("gpio48", GPIO48_FLASH_MODE_CFG,
>>>> -				GPIO_PCIE_RESET1_MASK),
>>>> -	AIROHA_PINCTRL_GPIO_EXT("gpio49", GPIO49_FLASH_MODE_CFG,
>>>> -				GPIO_PCIE_RESET2_MASK),
>>>> -};
>>>> -
>>>> -static const struct airoha_pinctrl_func_group pcie_reset_func_group[] = {
>>>> -	{
>>>> -		.name = "pcie_reset0",
>>>> -		.regmap[0] = {
>>>> -			AIROHA_FUNC_MUX,
>>>> -			REG_GPIO_PON_MODE,
>>>> -			GPIO_PCIE_RESET0_MASK,
>>>> -			0
>>>> -		},
>>>> -		.regmap_size = 1,
>>>> -	}, {
>>>> -		.name = "pcie_reset1",
>>>> -		.regmap[0] = {
>>>> -			AIROHA_FUNC_MUX,
>>>> -			REG_GPIO_PON_MODE,
>>>> -			GPIO_PCIE_RESET1_MASK,
>>>> -			0
>>>> -		},
>>>> -		.regmap_size = 1,
>>>> -	}, {
>>>> -		.name = "pcie_reset2",
>>>> -		.regmap[0] = {
>>>> -			AIROHA_FUNC_MUX,
>>>> -			REG_GPIO_PON_MODE,
>>>> -			GPIO_PCIE_RESET2_MASK,
>>>> -			0
>>>> -		},
>>>> -		.regmap_size = 1,
>>>> -	},
>>>> -};
>>>> -
>>>> -static const struct airoha_pinctrl_func_group an7583_gpio_func_group[] = {
>>>> -	AIROHA_PINCTRL_GPIO_EXT("gpio39", GPIO39_FLASH_MODE_CFG,
>>>> -				AN7583_I2C0_SCL_GPIO_MODE_MASK),
>>>> -	AIROHA_PINCTRL_GPIO_EXT("gpio40", GPIO40_FLASH_MODE_CFG,
>>>> -				AN7583_I2C0_SDA_GPIO_MODE_MASK),
>>>> -	AIROHA_PINCTRL_GPIO_EXT("gpio41", GPIO41_FLASH_MODE_CFG,
>>>> -				AN7583_I2C1_SCL_GPIO_MODE_MASK),
>>>> -	AIROHA_PINCTRL_GPIO_EXT("gpio42", GPIO42_FLASH_MODE_CFG,
>>>> -				AN7583_I2C1_SDA_GPIO_MODE_MASK),
>>>> -	AIROHA_PINCTRL_GPIO_EXT("gpio43", GPIO43_FLASH_MODE_CFG,
>>>> -				AN7583_SPI_CLK_GPIO_MODE_MASK),
>>>> -	AIROHA_PINCTRL_GPIO_EXT("gpio44", GPIO44_FLASH_MODE_CFG,
>>>> -				AN7583_SPI_CS_GPIO_MODE_MASK),
>>>> -	AIROHA_PINCTRL_GPIO_EXT("gpio45", GPIO45_FLASH_MODE_CFG,
>>>> -				AN7583_SPI_MOSI_GPIO_MODE_MASK),
>>>> -	AIROHA_PINCTRL_GPIO_EXT("gpio46", GPIO46_FLASH_MODE_CFG,
>>>> -				AN7583_SPI_MISO_GPIO_MODE_MASK),
>>>> -	AIROHA_PINCTRL_GPIO_EXT("gpio47", GPIO47_FLASH_MODE_CFG,
>>>> -				AN7583_UART_TXD_GPIO_MODE_MASK),
>>>> -	AIROHA_PINCTRL_GPIO_EXT("gpio48", GPIO48_FLASH_MODE_CFG,
>>>> -				AN7583_UART_RXD_GPIO_MODE_MASK),
>>>> -	AIROHA_PINCTRL_GPIO_EXT("gpio49", GPIO49_FLASH_MODE_CFG,
>>>> -				GPIO_PCIE_RESET0_MASK),
>>>> -	AIROHA_PINCTRL_GPIO_EXT("gpio50", GPIO50_FLASH_MODE_CFG,
>>>> -				GPIO_PCIE_RESET1_MASK),
>>>> -	AIROHA_PINCTRL_GPIO_EXT("gpio51", GPIO51_FLASH_MODE_CFG,
>>>> -				AN7583_MDC_0_GPIO_MODE_MASK),
>>>> -	AIROHA_PINCTRL_GPIO("gpio52", AN7583_MDIO_0_GPIO_MODE_MASK),
>>>> -};
>>>> -
>>>> -static const struct airoha_pinctrl_func_group an7583_pcie_reset_func_group[] = {
>>>> -	{
>>>> -		.name = "pcie_reset0",
>>>> -		.regmap[0] = {
>>>> -			AIROHA_FUNC_MUX,
>>>> -			REG_GPIO_PON_MODE,
>>>> -			GPIO_PCIE_RESET0_MASK,
>>>> -			0
>>>> -		},
>>>> -		.regmap_size = 1,
>>>> -	}, {
>>>> -		.name = "pcie_reset1",
>>>> -		.regmap[0] = {
>>>> -			AIROHA_FUNC_MUX,
>>>> -			REG_GPIO_PON_MODE,
>>>> -			GPIO_PCIE_RESET1_MASK,
>>>> -			0
>>>> -		},
>>>> -		.regmap_size = 1,
>>>> -	},
>>>> -};
>>>> -
>>>> -static const struct airoha_pinctrl_func_group pwm_func_group[] = {
>>>> -	AIROHA_PINCTRL_PWM("gpio0", GPIO0_FLASH_MODE_CFG),
>>>> -	AIROHA_PINCTRL_PWM("gpio1", GPIO1_FLASH_MODE_CFG),
>>>> -	AIROHA_PINCTRL_PWM("gpio2", GPIO2_FLASH_MODE_CFG),
>>>> -	AIROHA_PINCTRL_PWM("gpio3", GPIO3_FLASH_MODE_CFG),
>>>> -	AIROHA_PINCTRL_PWM("gpio4", GPIO4_FLASH_MODE_CFG),
>>>> -	AIROHA_PINCTRL_PWM("gpio5", GPIO5_FLASH_MODE_CFG),
>>>> -	AIROHA_PINCTRL_PWM("gpio6", GPIO6_FLASH_MODE_CFG),
>>>> -	AIROHA_PINCTRL_PWM("gpio7", GPIO7_FLASH_MODE_CFG),
>>>> -	AIROHA_PINCTRL_PWM("gpio8", GPIO8_FLASH_MODE_CFG),
>>>> -	AIROHA_PINCTRL_PWM("gpio9", GPIO9_FLASH_MODE_CFG),
>>>> -	AIROHA_PINCTRL_PWM("gpio10", GPIO10_FLASH_MODE_CFG),
>>>> -	AIROHA_PINCTRL_PWM("gpio11", GPIO11_FLASH_MODE_CFG),
>>>> -	AIROHA_PINCTRL_PWM("gpio12", GPIO12_FLASH_MODE_CFG),
>>>> -	AIROHA_PINCTRL_PWM("gpio13", GPIO13_FLASH_MODE_CFG),
>>>> -	AIROHA_PINCTRL_PWM("gpio14", GPIO14_FLASH_MODE_CFG),
>>>> -	AIROHA_PINCTRL_PWM("gpio15", GPIO15_FLASH_MODE_CFG),
>>>> -	AIROHA_PINCTRL_PWM_EXT("gpio16", GPIO16_FLASH_MODE_CFG),
>>>> -	AIROHA_PINCTRL_PWM_EXT("gpio17", GPIO17_FLASH_MODE_CFG),
>>>> -	AIROHA_PINCTRL_PWM_EXT("gpio18", GPIO18_FLASH_MODE_CFG),
>>>> -	AIROHA_PINCTRL_PWM_EXT("gpio19", GPIO19_FLASH_MODE_CFG),
>>>> -	AIROHA_PINCTRL_PWM_EXT("gpio20", GPIO20_FLASH_MODE_CFG),
>>>> -	AIROHA_PINCTRL_PWM_EXT("gpio21", GPIO21_FLASH_MODE_CFG),
>>>> -	AIROHA_PINCTRL_PWM_EXT("gpio22", GPIO22_FLASH_MODE_CFG),
>>>> -	AIROHA_PINCTRL_PWM_EXT("gpio23", GPIO23_FLASH_MODE_CFG),
>>>> -	AIROHA_PINCTRL_PWM_EXT("gpio24", GPIO24_FLASH_MODE_CFG),
>>>> -	AIROHA_PINCTRL_PWM_EXT("gpio25", GPIO25_FLASH_MODE_CFG),
>>>> -	AIROHA_PINCTRL_PWM_EXT("gpio26", GPIO26_FLASH_MODE_CFG),
>>>> -	AIROHA_PINCTRL_PWM_EXT("gpio27", GPIO27_FLASH_MODE_CFG),
>>>> -	AIROHA_PINCTRL_PWM_EXT("gpio28", GPIO28_FLASH_MODE_CFG),
>>>> -	AIROHA_PINCTRL_PWM_EXT("gpio29", GPIO29_FLASH_MODE_CFG),
>>>> -	AIROHA_PINCTRL_PWM_EXT("gpio30", GPIO30_FLASH_MODE_CFG),
>>>> -	AIROHA_PINCTRL_PWM_EXT("gpio31", GPIO31_FLASH_MODE_CFG),
>>>> -	AIROHA_PINCTRL_PWM_EXT("gpio36", GPIO36_FLASH_MODE_CFG),
>>>> -	AIROHA_PINCTRL_PWM_EXT("gpio37", GPIO37_FLASH_MODE_CFG),
>>>> -	AIROHA_PINCTRL_PWM_EXT("gpio38", GPIO38_FLASH_MODE_CFG),
>>>> -	AIROHA_PINCTRL_PWM_EXT("gpio39", GPIO39_FLASH_MODE_CFG),
>>>> -	AIROHA_PINCTRL_PWM_EXT("gpio40", GPIO40_FLASH_MODE_CFG),
>>>> -	AIROHA_PINCTRL_PWM_EXT("gpio41", GPIO41_FLASH_MODE_CFG),
>>>> -	AIROHA_PINCTRL_PWM_EXT("gpio42", GPIO42_FLASH_MODE_CFG),
>>>> -	AIROHA_PINCTRL_PWM_EXT("gpio43", GPIO43_FLASH_MODE_CFG),
>>>> -	AIROHA_PINCTRL_PWM_EXT("gpio44", GPIO44_FLASH_MODE_CFG),
>>>> -	AIROHA_PINCTRL_PWM_EXT("gpio45", GPIO45_FLASH_MODE_CFG),
>>>> -	AIROHA_PINCTRL_PWM_EXT("gpio46", GPIO46_FLASH_MODE_CFG),
>>>> -	AIROHA_PINCTRL_PWM_EXT_SEC("gpio47", GPIO47_FLASH_MODE_CFG,
>>>> -				   GPIO_PCIE_RESET0_MASK),
>>>> -	AIROHA_PINCTRL_PWM_EXT_SEC("gpio48", GPIO48_FLASH_MODE_CFG,
>>>> -				   GPIO_PCIE_RESET1_MASK),
>>>> -	AIROHA_PINCTRL_PWM_EXT_SEC("gpio49", GPIO49_FLASH_MODE_CFG,
>>>> -				   GPIO_PCIE_RESET2_MASK),
>>>> -};
>>>> -
>>>> -static const struct airoha_pinctrl_func_group an7583_pwm_func_group[] = {
>>>> -	AIROHA_PINCTRL_PWM("gpio0", GPIO0_FLASH_MODE_CFG),
>>>> -	AIROHA_PINCTRL_PWM("gpio1", GPIO1_FLASH_MODE_CFG),
>>>> -	AIROHA_PINCTRL_PWM("gpio2", GPIO2_FLASH_MODE_CFG),
>>>> -	AIROHA_PINCTRL_PWM("gpio3", GPIO3_FLASH_MODE_CFG),
>>>> -	AIROHA_PINCTRL_PWM("gpio4", GPIO4_FLASH_MODE_CFG),
>>>> -	AIROHA_PINCTRL_PWM("gpio5", GPIO5_FLASH_MODE_CFG),
>>>> -	AIROHA_PINCTRL_PWM("gpio6", GPIO6_FLASH_MODE_CFG),
>>>> -	AIROHA_PINCTRL_PWM("gpio7", GPIO7_FLASH_MODE_CFG),
>>>> -	AIROHA_PINCTRL_PWM("gpio8", GPIO8_FLASH_MODE_CFG),
>>>> -	AIROHA_PINCTRL_PWM("gpio9", GPIO9_FLASH_MODE_CFG),
>>>> -	AIROHA_PINCTRL_PWM("gpio10", GPIO10_FLASH_MODE_CFG),
>>>> -	AIROHA_PINCTRL_PWM("gpio11", GPIO11_FLASH_MODE_CFG),
>>>> -	AIROHA_PINCTRL_PWM("gpio12", GPIO12_FLASH_MODE_CFG),
>>>> -	AIROHA_PINCTRL_PWM("gpio13", GPIO13_FLASH_MODE_CFG),
>>>> -	AIROHA_PINCTRL_PWM("gpio14", GPIO14_FLASH_MODE_CFG),
>>>> -	AIROHA_PINCTRL_PWM("gpio15", GPIO15_FLASH_MODE_CFG),
>>>> -	AIROHA_PINCTRL_PWM_EXT("gpio16", GPIO16_FLASH_MODE_CFG),
>>>> -	AIROHA_PINCTRL_PWM_EXT("gpio17", GPIO17_FLASH_MODE_CFG),
>>>> -	AIROHA_PINCTRL_PWM_EXT("gpio18", GPIO18_FLASH_MODE_CFG),
>>>> -	AIROHA_PINCTRL_PWM_EXT("gpio19", GPIO19_FLASH_MODE_CFG),
>>>> -	AIROHA_PINCTRL_PWM_EXT("gpio20", GPIO20_FLASH_MODE_CFG),
>>>> -	AIROHA_PINCTRL_PWM_EXT("gpio21", GPIO21_FLASH_MODE_CFG),
>>>> -	AIROHA_PINCTRL_PWM_EXT("gpio22", GPIO22_FLASH_MODE_CFG),
>>>> -	AIROHA_PINCTRL_PWM_EXT("gpio23", GPIO23_FLASH_MODE_CFG),
>>>> -	AIROHA_PINCTRL_PWM_EXT("gpio24", GPIO24_FLASH_MODE_CFG),
>>>> -	AIROHA_PINCTRL_PWM_EXT("gpio25", GPIO25_FLASH_MODE_CFG),
>>>> -	AIROHA_PINCTRL_PWM_EXT("gpio26", GPIO26_FLASH_MODE_CFG),
>>>> -	AIROHA_PINCTRL_PWM_EXT("gpio27", GPIO27_FLASH_MODE_CFG),
>>>> -	AIROHA_PINCTRL_PWM_EXT("gpio28", GPIO28_FLASH_MODE_CFG),
>>>> -	AIROHA_PINCTRL_PWM_EXT("gpio29", GPIO29_FLASH_MODE_CFG),
>>>> -	AIROHA_PINCTRL_PWM_EXT("gpio30", GPIO30_FLASH_MODE_CFG),
>>>> -	AIROHA_PINCTRL_PWM_EXT("gpio31", GPIO31_FLASH_MODE_CFG),
>>>> -	AIROHA_PINCTRL_PWM_EXT("gpio36", GPIO36_FLASH_MODE_CFG),
>>>> -	AIROHA_PINCTRL_PWM_EXT("gpio37", GPIO37_FLASH_MODE_CFG),
>>>> -	AIROHA_PINCTRL_PWM_EXT("gpio38", GPIO38_FLASH_MODE_CFG),
>>>> -	AIROHA_PINCTRL_PWM_EXT_SEC("gpio39", GPIO39_FLASH_MODE_CFG,
>>>> -				   AN7583_I2C0_SCL_GPIO_MODE_MASK),
>>>> -	AIROHA_PINCTRL_PWM_EXT_SEC("gpio40", GPIO40_FLASH_MODE_CFG,
>>>> -				   AN7583_I2C0_SDA_GPIO_MODE_MASK),
>>>> -	AIROHA_PINCTRL_PWM_EXT_SEC("gpio41", GPIO41_FLASH_MODE_CFG,
>>>> -				   AN7583_I2C1_SCL_GPIO_MODE_MASK),
>>>> -	AIROHA_PINCTRL_PWM_EXT_SEC("gpio42", GPIO42_FLASH_MODE_CFG,
>>>> -				   AN7583_I2C1_SDA_GPIO_MODE_MASK),
>>>> -	AIROHA_PINCTRL_PWM_EXT_SEC("gpio43", GPIO43_FLASH_MODE_CFG,
>>>> -				   AN7583_SPI_CLK_GPIO_MODE_MASK),
>>>> -	AIROHA_PINCTRL_PWM_EXT_SEC("gpio44", GPIO44_FLASH_MODE_CFG,
>>>> -				   AN7583_SPI_CS_GPIO_MODE_MASK),
>>>> -	AIROHA_PINCTRL_PWM_EXT_SEC("gpio45", GPIO45_FLASH_MODE_CFG,
>>>> -				   AN7583_SPI_MOSI_GPIO_MODE_MASK),
>>>> -	AIROHA_PINCTRL_PWM_EXT_SEC("gpio46", GPIO46_FLASH_MODE_CFG,
>>>> -				   AN7583_SPI_MISO_GPIO_MODE_MASK),
>>>> -	AIROHA_PINCTRL_PWM_EXT_SEC("gpio47", GPIO47_FLASH_MODE_CFG,
>>>> -				   AN7583_UART_TXD_GPIO_MODE_MASK),
>>>> -	AIROHA_PINCTRL_PWM_EXT_SEC("gpio48", GPIO48_FLASH_MODE_CFG,
>>>> -				   AN7583_UART_RXD_GPIO_MODE_MASK),
>>>> -	AIROHA_PINCTRL_PWM_EXT_SEC("gpio49", GPIO49_FLASH_MODE_CFG,
>>>> -				   GPIO_PCIE_RESET0_MASK),
>>>> -	AIROHA_PINCTRL_PWM_EXT_SEC("gpio50", GPIO50_FLASH_MODE_CFG,
>>>> -				   GPIO_PCIE_RESET1_MASK),
>>>> -	AIROHA_PINCTRL_PWM_EXT_SEC("gpio51", GPIO51_FLASH_MODE_CFG,
>>>> -				   AN7583_MDC_0_GPIO_MODE_MASK),
>>>> -};
>>>> -
>>>> -static const struct airoha_pinctrl_func_group phy1_led0_func_group[] = {
>>>> -	AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK,
>>>> -				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),
>>>> -	AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK,
>>>> -				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)),
>>>> -	AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK,
>>>> -				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)),
>>>> -	AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK,
>>>> -				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),
>>>> -};
>>>> -
>>>> -static const struct airoha_pinctrl_func_group phy2_led0_func_group[] = {
>>>> -	AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK,
>>>> -				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),
>>>> -	AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK,
>>>> -				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)),
>>>> -	AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK,
>>>> -				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)),
>>>> -	AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK,
>>>> -				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),
>>>> -};
>>>> -
>>>> -static const struct airoha_pinctrl_func_group phy3_led0_func_group[] = {
>>>> -	AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK,
>>>> -				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
>>>> -	AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK,
>>>> -				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),
>>>> -	AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK,
>>>> -				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),
>>>> -	AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK,
>>>> -				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
>>>> -};
>>>> -
>>>> -static const struct airoha_pinctrl_func_group phy4_led0_func_group[] = {
>>>> -	AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK,
>>>> -				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)),
>>>> -	AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK,
>>>> -				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)),
>>>> -	AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK,
>>>> -				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)),
>>>> -	AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK,
>>>> -				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)),
>>>> -};
>>>> -
>>>> -static const struct airoha_pinctrl_func_group phy1_led1_func_group[] = {
>>>> -	AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK,
>>>> -				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),
>>>> -	AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK,
>>>> -				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)),
>>>> -	AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK,
>>>> -				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)),
>>>> -	AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK,
>>>> -				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),
>>>> -};
>>>> -
>>>> -static const struct airoha_pinctrl_func_group phy2_led1_func_group[] = {
>>>> -	AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK,
>>>> -				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),
>>>> -	AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK,
>>>> -				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)),
>>>> -	AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK,
>>>> -				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)),
>>>> -	AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK,
>>>> -				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),
>>>> -};
>>>> -
>>>> -static const struct airoha_pinctrl_func_group phy3_led1_func_group[] = {
>>>> -	AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK,
>>>> -				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
>>>> -	AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK,
>>>> -				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),
>>>> -	AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK,
>>>> -				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),
>>>> -	AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK,
>>>> -				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
>>>> -};
>>>> -
>>>> -static const struct airoha_pinctrl_func_group phy4_led1_func_group[] = {
>>>> -	AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK,
>>>> -				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)),
>>>> -	AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK,
>>>> -				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)),
>>>> -	AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK,
>>>> -				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)),
>>>> -	AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK,
>>>> -				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)),
>>>> -};
>>>> -
>>>> -static const struct airoha_pinctrl_func_group an7583_phy1_led0_func_group[] = {
>>>> -	AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK,
>>>> -				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),
>>>> -	AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK,
>>>> -				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)),
>>>> -	AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK,
>>>> -				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)),
>>>> -	AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK,
>>>> -				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),
>>>> -};
>>>> -
>>>> -static const struct airoha_pinctrl_func_group an7583_phy2_led0_func_group[] = {
>>>> -	AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK,
>>>> -				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),
>>>> -	AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK,
>>>> -				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)),
>>>> -	AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK,
>>>> -				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)),
>>>> -	AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK,
>>>> -				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),
>>>> -};
>>>> -
>>>> -static const struct airoha_pinctrl_func_group an7583_phy3_led0_func_group[] = {
>>>> -	AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK,
>>>> -				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
>>>> -	AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK,
>>>> -				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),
>>>> -	AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK,
>>>> -				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),
>>>> -	AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK,
>>>> -				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
>>>> -};
>>>> -
>>>> -static const struct airoha_pinctrl_func_group an7583_phy4_led0_func_group[] = {
>>>> -	AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK,
>>>> -				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)),
>>>> -	AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK,
>>>> -				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)),
>>>> -	AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK,
>>>> -				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)),
>>>> -	AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK,
>>>> -				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)),
>>>> -};
>>>> -
>>>> -static const struct airoha_pinctrl_func_group an7583_phy1_led1_func_group[] = {
>>>> -	AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK,
>>>> -				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),
>>>> -	AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK,
>>>> -				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)),
>>>> -	AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK,
>>>> -				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)),
>>>> -	AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK,
>>>> -				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),
>>>> -};
>>>> -
>>>> -static const struct airoha_pinctrl_func_group an7583_phy2_led1_func_group[] = {
>>>> -	AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK,
>>>> -				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),
>>>> -	AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK,
>>>> -				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)),
>>>> -	AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK,
>>>> -				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)),
>>>> -	AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK,
>>>> -				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),
>>>> -};
>>>> -
>>>> -static const struct airoha_pinctrl_func_group an7583_phy3_led1_func_group[] = {
>>>> -	AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK,
>>>> -				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
>>>> -	AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK,
>>>> -				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),
>>>> -	AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK,
>>>> -				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),
>>>> -	AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK,
>>>> -				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
>>>> -};
>>>> -
>>>> -static const struct airoha_pinctrl_func_group an7583_phy4_led1_func_group[] = {
>>>> -	AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK,
>>>> -				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)),
>>>> -	AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK,
>>>> -				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)),
>>>> -	AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK,
>>>> -				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)),
>>>> -	AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK,
>>>> -				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)),
>>>> -};
>>>> -
>>>> -static const struct airoha_pinctrl_func en7581_pinctrl_funcs[] = {
>>>> -	PINCTRL_FUNC_DESC("pon", pon),
>>>> -	PINCTRL_FUNC_DESC("tod_1pps", tod_1pps),
>>>> -	PINCTRL_FUNC_DESC("sipo", sipo),
>>>> -	PINCTRL_FUNC_DESC("mdio", mdio),
>>>> -	PINCTRL_FUNC_DESC("uart", uart),
>>>> -	PINCTRL_FUNC_DESC("i2c", i2c),
>>>> -	PINCTRL_FUNC_DESC("jtag", jtag),
>>>> -	PINCTRL_FUNC_DESC("pcm", pcm),
>>>> -	PINCTRL_FUNC_DESC("spi", spi),
>>>> -	PINCTRL_FUNC_DESC("pcm_spi", pcm_spi),
>>>> -	PINCTRL_FUNC_DESC("i2s", i2s),
>>>> -	PINCTRL_FUNC_DESC("emmc", emmc),
>>>> -	PINCTRL_FUNC_DESC("pnand", pnand),
>>>> -	PINCTRL_FUNC_DESC("gpio", gpio),
>>>> -	PINCTRL_FUNC_DESC("pcie_reset", pcie_reset),
>>>> -	PINCTRL_FUNC_DESC("pwm", pwm),
>>>> -	PINCTRL_FUNC_DESC("phy1_led0", phy1_led0),
>>>> -	PINCTRL_FUNC_DESC("phy2_led0", phy2_led0),
>>>> -	PINCTRL_FUNC_DESC("phy3_led0", phy3_led0),
>>>> -	PINCTRL_FUNC_DESC("phy4_led0", phy4_led0),
>>>> -	PINCTRL_FUNC_DESC("phy1_led1", phy1_led1),
>>>> -	PINCTRL_FUNC_DESC("phy2_led1", phy2_led1),
>>>> -	PINCTRL_FUNC_DESC("phy3_led1", phy3_led1),
>>>> -	PINCTRL_FUNC_DESC("phy4_led1", phy4_led1),
>>>> -};
>>>> -
>>>> -static const struct airoha_pinctrl_func an7583_pinctrl_funcs[] = {
>>>> -	PINCTRL_FUNC_DESC("pon", pon),
>>>> -	PINCTRL_FUNC_DESC("tod_1pps", tod_1pps),
>>>> -	PINCTRL_FUNC_DESC("sipo", sipo),
>>>> -	PINCTRL_FUNC_DESC("mdio", an7583_mdio),
>>>> -	PINCTRL_FUNC_DESC("uart", uart),
>>>> -	PINCTRL_FUNC_DESC("jtag", jtag),
>>>> -	PINCTRL_FUNC_DESC("pcm", pcm),
>>>> -	PINCTRL_FUNC_DESC("spi", spi),
>>>> -	PINCTRL_FUNC_DESC("pcm_spi", an7583_pcm_spi),
>>>> -	PINCTRL_FUNC_DESC("emmc", emmc),
>>>> -	PINCTRL_FUNC_DESC("pnand", pnand),
>>>> -	PINCTRL_FUNC_DESC("gpio", an7583_gpio),
>>>> -	PINCTRL_FUNC_DESC("pcie_reset", an7583_pcie_reset),
>>>> -	PINCTRL_FUNC_DESC("pwm", an7583_pwm),
>>>> -	PINCTRL_FUNC_DESC("phy1_led0", an7583_phy1_led0),
>>>> -	PINCTRL_FUNC_DESC("phy2_led0", an7583_phy2_led0),
>>>> -	PINCTRL_FUNC_DESC("phy3_led0", an7583_phy3_led0),
>>>> -	PINCTRL_FUNC_DESC("phy4_led0", an7583_phy4_led0),
>>>> -	PINCTRL_FUNC_DESC("phy1_led1", an7583_phy1_led1),
>>>> -	PINCTRL_FUNC_DESC("phy2_led1", an7583_phy2_led1),
>>>> -	PINCTRL_FUNC_DESC("phy3_led1", an7583_phy3_led1),
>>>> -	PINCTRL_FUNC_DESC("phy4_led1", an7583_phy4_led1),
>>>> -};
>>>> -
>>>> -static const struct airoha_pinctrl_conf en7581_pinctrl_pullup_conf[] = {
>>>> -	PINCTRL_CONF_DESC(0, REG_I2C_SDA_PU, UART1_TXD_PU_MASK),
>>>> -	PINCTRL_CONF_DESC(1, REG_I2C_SDA_PU, UART1_RXD_PU_MASK),
>>>> -	PINCTRL_CONF_DESC(2, REG_I2C_SDA_PU, I2C_SDA_PU_MASK),
>>>> -	PINCTRL_CONF_DESC(3, REG_I2C_SDA_PU, I2C_SCL_PU_MASK),
>>>> -	PINCTRL_CONF_DESC(4, REG_I2C_SDA_PU, SPI_CS0_PU_MASK),
>>>> -	PINCTRL_CONF_DESC(5, REG_I2C_SDA_PU, SPI_CLK_PU_MASK),
>>>> -	PINCTRL_CONF_DESC(6, REG_I2C_SDA_PU, SPI_MOSI_PU_MASK),
>>>> -	PINCTRL_CONF_DESC(7, REG_I2C_SDA_PU, SPI_MISO_PU_MASK),
>>>> -	PINCTRL_CONF_DESC(13, REG_GPIO_L_PU, BIT(0)),
>>>> -	PINCTRL_CONF_DESC(14, REG_GPIO_L_PU, BIT(1)),
>>>> -	PINCTRL_CONF_DESC(15, REG_GPIO_L_PU, BIT(2)),
>>>> -	PINCTRL_CONF_DESC(16, REG_GPIO_L_PU, BIT(3)),
>>>> -	PINCTRL_CONF_DESC(17, REG_GPIO_L_PU, BIT(4)),
>>>> -	PINCTRL_CONF_DESC(18, REG_GPIO_L_PU, BIT(5)),
>>>> -	PINCTRL_CONF_DESC(19, REG_GPIO_L_PU, BIT(6)),
>>>> -	PINCTRL_CONF_DESC(20, REG_GPIO_L_PU, BIT(7)),
>>>> -	PINCTRL_CONF_DESC(21, REG_GPIO_L_PU, BIT(8)),
>>>> -	PINCTRL_CONF_DESC(22, REG_GPIO_L_PU, BIT(9)),
>>>> -	PINCTRL_CONF_DESC(23, REG_GPIO_L_PU, BIT(10)),
>>>> -	PINCTRL_CONF_DESC(24, REG_GPIO_L_PU, BIT(11)),
>>>> -	PINCTRL_CONF_DESC(25, REG_GPIO_L_PU, BIT(12)),
>>>> -	PINCTRL_CONF_DESC(26, REG_GPIO_L_PU, BIT(13)),
>>>> -	PINCTRL_CONF_DESC(27, REG_GPIO_L_PU, BIT(14)),
>>>> -	PINCTRL_CONF_DESC(28, REG_GPIO_L_PU, BIT(15)),
>>>> -	PINCTRL_CONF_DESC(29, REG_GPIO_L_PU, BIT(16)),
>>>> -	PINCTRL_CONF_DESC(30, REG_GPIO_L_PU, BIT(17)),
>>>> -	PINCTRL_CONF_DESC(31, REG_GPIO_L_PU, BIT(18)),
>>>> -	PINCTRL_CONF_DESC(32, REG_GPIO_L_PU, BIT(19)),
>>>> -	PINCTRL_CONF_DESC(33, REG_GPIO_L_PU, BIT(20)),
>>>> -	PINCTRL_CONF_DESC(34, REG_GPIO_L_PU, BIT(21)),
>>>> -	PINCTRL_CONF_DESC(35, REG_GPIO_L_PU, BIT(22)),
>>>> -	PINCTRL_CONF_DESC(36, REG_GPIO_L_PU, BIT(23)),
>>>> -	PINCTRL_CONF_DESC(37, REG_GPIO_L_PU, BIT(24)),
>>>> -	PINCTRL_CONF_DESC(38, REG_GPIO_L_PU, BIT(25)),
>>>> -	PINCTRL_CONF_DESC(39, REG_GPIO_L_PU, BIT(26)),
>>>> -	PINCTRL_CONF_DESC(40, REG_GPIO_L_PU, BIT(27)),
>>>> -	PINCTRL_CONF_DESC(41, REG_GPIO_L_PU, BIT(28)),
>>>> -	PINCTRL_CONF_DESC(42, REG_GPIO_L_PU, BIT(29)),
>>>> -	PINCTRL_CONF_DESC(43, REG_GPIO_L_PU, BIT(30)),
>>>> -	PINCTRL_CONF_DESC(44, REG_GPIO_L_PU, BIT(31)),
>>>> -	PINCTRL_CONF_DESC(45, REG_GPIO_H_PU, BIT(0)),
>>>> -	PINCTRL_CONF_DESC(46, REG_GPIO_H_PU, BIT(1)),
>>>> -	PINCTRL_CONF_DESC(47, REG_GPIO_H_PU, BIT(2)),
>>>> -	PINCTRL_CONF_DESC(48, REG_GPIO_H_PU, BIT(3)),
>>>> -	PINCTRL_CONF_DESC(49, REG_GPIO_H_PU, BIT(4)),
>>>> -	PINCTRL_CONF_DESC(50, REG_GPIO_H_PU, BIT(5)),
>>>> -	PINCTRL_CONF_DESC(51, REG_GPIO_H_PU, BIT(6)),
>>>> -	PINCTRL_CONF_DESC(52, REG_GPIO_H_PU, BIT(7)),
>>>> -	PINCTRL_CONF_DESC(53, REG_GPIO_H_PU, BIT(8)),
>>>> -	PINCTRL_CONF_DESC(54, REG_GPIO_H_PU, BIT(9)),
>>>> -	PINCTRL_CONF_DESC(55, REG_GPIO_H_PU, BIT(10)),
>>>> -	PINCTRL_CONF_DESC(56, REG_GPIO_H_PU, BIT(11)),
>>>> -	PINCTRL_CONF_DESC(57, REG_GPIO_H_PU, BIT(12)),
>>>> -	PINCTRL_CONF_DESC(58, REG_GPIO_H_PU, BIT(13)),
>>>> -	PINCTRL_CONF_DESC(59, REG_GPIO_H_PU, BIT(14)),
>>>> -	PINCTRL_CONF_DESC(60, REG_I2C_SDA_PU, PCIE0_RESET_PU_MASK),
>>>> -	PINCTRL_CONF_DESC(61, REG_I2C_SDA_PU, PCIE1_RESET_PU_MASK),
>>>> -	PINCTRL_CONF_DESC(62, REG_I2C_SDA_PU, PCIE2_RESET_PU_MASK),
>>>> -};
>>>> -
>>>> -static const struct airoha_pinctrl_conf an7583_pinctrl_pullup_conf[] = {
>>>> -	PINCTRL_CONF_DESC(2, REG_GPIO_L_PU, BIT(0)),
>>>> -	PINCTRL_CONF_DESC(3, REG_GPIO_L_PU, BIT(1)),
>>>> -	PINCTRL_CONF_DESC(4, REG_GPIO_L_PU, BIT(2)),
>>>> -	PINCTRL_CONF_DESC(5, REG_GPIO_L_PU, BIT(3)),
>>>> -	PINCTRL_CONF_DESC(6, REG_GPIO_L_PU, BIT(4)),
>>>> -	PINCTRL_CONF_DESC(7, REG_GPIO_L_PU, BIT(5)),
>>>> -	PINCTRL_CONF_DESC(8, REG_GPIO_L_PU, BIT(6)),
>>>> -	PINCTRL_CONF_DESC(9, REG_GPIO_L_PU, BIT(7)),
>>>> -	PINCTRL_CONF_DESC(10, REG_GPIO_L_PU, BIT(8)),
>>>> -	PINCTRL_CONF_DESC(11, REG_GPIO_L_PU, BIT(9)),
>>>> -	PINCTRL_CONF_DESC(12, REG_GPIO_L_PU, BIT(10)),
>>>> -	PINCTRL_CONF_DESC(13, REG_GPIO_L_PU, BIT(11)),
>>>> -	PINCTRL_CONF_DESC(14, REG_GPIO_L_PU, BIT(12)),
>>>> -	PINCTRL_CONF_DESC(15, REG_GPIO_L_PU, BIT(13)),
>>>> -	PINCTRL_CONF_DESC(16, REG_GPIO_L_PU, BIT(14)),
>>>> -	PINCTRL_CONF_DESC(17, REG_GPIO_L_PU, BIT(15)),
>>>> -	PINCTRL_CONF_DESC(18, REG_GPIO_L_PU, BIT(16)),
>>>> -	PINCTRL_CONF_DESC(19, REG_GPIO_L_PU, BIT(17)),
>>>> -	PINCTRL_CONF_DESC(20, REG_GPIO_L_PU, BIT(18)),
>>>> -	PINCTRL_CONF_DESC(21, REG_GPIO_L_PU, BIT(19)),
>>>> -	PINCTRL_CONF_DESC(22, REG_GPIO_L_PU, BIT(20)),
>>>> -	PINCTRL_CONF_DESC(23, REG_GPIO_L_PU, BIT(21)),
>>>> -	PINCTRL_CONF_DESC(24, REG_GPIO_L_PU, BIT(22)),
>>>> -	PINCTRL_CONF_DESC(25, REG_GPIO_L_PU, BIT(23)),
>>>> -	PINCTRL_CONF_DESC(26, REG_GPIO_L_PU, BIT(24)),
>>>> -	PINCTRL_CONF_DESC(27, REG_GPIO_L_PU, BIT(25)),
>>>> -	PINCTRL_CONF_DESC(28, REG_GPIO_L_PU, BIT(26)),
>>>> -	PINCTRL_CONF_DESC(29, REG_GPIO_L_PU, BIT(27)),
>>>> -	PINCTRL_CONF_DESC(30, REG_GPIO_L_PU, BIT(28)),
>>>> -	PINCTRL_CONF_DESC(31, REG_GPIO_L_PU, BIT(29)),
>>>> -	PINCTRL_CONF_DESC(32, REG_GPIO_L_PU, BIT(30)),
>>>> -	PINCTRL_CONF_DESC(33, REG_GPIO_L_PU, BIT(31)),
>>>> -	PINCTRL_CONF_DESC(34, REG_GPIO_H_PU, BIT(0)),
>>>> -	PINCTRL_CONF_DESC(35, REG_GPIO_H_PU, BIT(1)),
>>>> -	PINCTRL_CONF_DESC(36, REG_GPIO_H_PU, BIT(2)),
>>>> -	PINCTRL_CONF_DESC(37, REG_GPIO_H_PU, BIT(3)),
>>>> -	PINCTRL_CONF_DESC(38, REG_GPIO_H_PU, BIT(4)),
>>>> -	PINCTRL_CONF_DESC(39, REG_GPIO_H_PU, BIT(5)),
>>>> -	PINCTRL_CONF_DESC(40, REG_GPIO_H_PU, BIT(6)),
>>>> -	PINCTRL_CONF_DESC(41, REG_I2C_SDA_PU, I2C_SCL_PU_MASK),
>>>> -	PINCTRL_CONF_DESC(42, REG_I2C_SDA_PU, I2C_SDA_PU_MASK),
>>>> -	PINCTRL_CONF_DESC(43, REG_I2C_SDA_PU, AN7583_I2C1_SCL_PU_MASK),
>>>> -	PINCTRL_CONF_DESC(44, REG_I2C_SDA_PU, AN7583_I2C1_SDA_PU_MASK),
>>>> -	PINCTRL_CONF_DESC(45, REG_I2C_SDA_PU, SPI_CLK_PU_MASK),
>>>> -	PINCTRL_CONF_DESC(46, REG_I2C_SDA_PU, SPI_CS0_PU_MASK),
>>>> -	PINCTRL_CONF_DESC(47, REG_I2C_SDA_PU, SPI_MOSI_PU_MASK),
>>>> -	PINCTRL_CONF_DESC(48, REG_I2C_SDA_PU, SPI_MISO_PU_MASK),
>>>> -	PINCTRL_CONF_DESC(49, REG_I2C_SDA_PU, UART1_TXD_PU_MASK),
>>>> -	PINCTRL_CONF_DESC(50, REG_I2C_SDA_PU, UART1_RXD_PU_MASK),
>>>> -	PINCTRL_CONF_DESC(51, REG_I2C_SDA_PU, PCIE0_RESET_PU_MASK),
>>>> -	PINCTRL_CONF_DESC(52, REG_I2C_SDA_PU, PCIE1_RESET_PU_MASK),
>>>> -	PINCTRL_CONF_DESC(53, REG_I2C_SDA_PU, AN7583_MDC_0_PU_MASK),
>>>> -	PINCTRL_CONF_DESC(54, REG_I2C_SDA_PU, AN7583_MDIO_0_PU_MASK),
>>>> -};
>>>> -
>>>> -static const struct airoha_pinctrl_conf en7581_pinctrl_pulldown_conf[] = {
>>>> -	PINCTRL_CONF_DESC(0, REG_I2C_SDA_PD, UART1_TXD_PD_MASK),
>>>> -	PINCTRL_CONF_DESC(1, REG_I2C_SDA_PD, UART1_RXD_PD_MASK),
>>>> -	PINCTRL_CONF_DESC(2, REG_I2C_SDA_PD, I2C_SDA_PD_MASK),
>>>> -	PINCTRL_CONF_DESC(3, REG_I2C_SDA_PD, I2C_SCL_PD_MASK),
>>>> -	PINCTRL_CONF_DESC(4, REG_I2C_SDA_PD, SPI_CS0_PD_MASK),
>>>> -	PINCTRL_CONF_DESC(5, REG_I2C_SDA_PD, SPI_CLK_PD_MASK),
>>>> -	PINCTRL_CONF_DESC(6, REG_I2C_SDA_PD, SPI_MOSI_PD_MASK),
>>>> -	PINCTRL_CONF_DESC(7, REG_I2C_SDA_PD, SPI_MISO_PD_MASK),
>>>> -	PINCTRL_CONF_DESC(13, REG_GPIO_L_PD, BIT(0)),
>>>> -	PINCTRL_CONF_DESC(14, REG_GPIO_L_PD, BIT(1)),
>>>> -	PINCTRL_CONF_DESC(15, REG_GPIO_L_PD, BIT(2)),
>>>> -	PINCTRL_CONF_DESC(16, REG_GPIO_L_PD, BIT(3)),
>>>> -	PINCTRL_CONF_DESC(17, REG_GPIO_L_PD, BIT(4)),
>>>> -	PINCTRL_CONF_DESC(18, REG_GPIO_L_PD, BIT(5)),
>>>> -	PINCTRL_CONF_DESC(19, REG_GPIO_L_PD, BIT(6)),
>>>> -	PINCTRL_CONF_DESC(20, REG_GPIO_L_PD, BIT(7)),
>>>> -	PINCTRL_CONF_DESC(21, REG_GPIO_L_PD, BIT(8)),
>>>> -	PINCTRL_CONF_DESC(22, REG_GPIO_L_PD, BIT(9)),
>>>> -	PINCTRL_CONF_DESC(23, REG_GPIO_L_PD, BIT(10)),
>>>> -	PINCTRL_CONF_DESC(24, REG_GPIO_L_PD, BIT(11)),
>>>> -	PINCTRL_CONF_DESC(25, REG_GPIO_L_PD, BIT(12)),
>>>> -	PINCTRL_CONF_DESC(26, REG_GPIO_L_PD, BIT(13)),
>>>> -	PINCTRL_CONF_DESC(27, REG_GPIO_L_PD, BIT(14)),
>>>> -	PINCTRL_CONF_DESC(28, REG_GPIO_L_PD, BIT(15)),
>>>> -	PINCTRL_CONF_DESC(29, REG_GPIO_L_PD, BIT(16)),
>>>> -	PINCTRL_CONF_DESC(30, REG_GPIO_L_PD, BIT(17)),
>>>> -	PINCTRL_CONF_DESC(31, REG_GPIO_L_PD, BIT(18)),
>>>> -	PINCTRL_CONF_DESC(32, REG_GPIO_L_PD, BIT(19)),
>>>> -	PINCTRL_CONF_DESC(33, REG_GPIO_L_PD, BIT(20)),
>>>> -	PINCTRL_CONF_DESC(34, REG_GPIO_L_PD, BIT(21)),
>>>> -	PINCTRL_CONF_DESC(35, REG_GPIO_L_PD, BIT(22)),
>>>> -	PINCTRL_CONF_DESC(36, REG_GPIO_L_PD, BIT(23)),
>>>> -	PINCTRL_CONF_DESC(37, REG_GPIO_L_PD, BIT(24)),
>>>> -	PINCTRL_CONF_DESC(38, REG_GPIO_L_PD, BIT(25)),
>>>> -	PINCTRL_CONF_DESC(39, REG_GPIO_L_PD, BIT(26)),
>>>> -	PINCTRL_CONF_DESC(40, REG_GPIO_L_PD, BIT(27)),
>>>> -	PINCTRL_CONF_DESC(41, REG_GPIO_L_PD, BIT(28)),
>>>> -	PINCTRL_CONF_DESC(42, REG_GPIO_L_PD, BIT(29)),
>>>> -	PINCTRL_CONF_DESC(43, REG_GPIO_L_PD, BIT(30)),
>>>> -	PINCTRL_CONF_DESC(44, REG_GPIO_L_PD, BIT(31)),
>>>> -	PINCTRL_CONF_DESC(45, REG_GPIO_H_PD, BIT(0)),
>>>> -	PINCTRL_CONF_DESC(46, REG_GPIO_H_PD, BIT(1)),
>>>> -	PINCTRL_CONF_DESC(47, REG_GPIO_H_PD, BIT(2)),
>>>> -	PINCTRL_CONF_DESC(48, REG_GPIO_H_PD, BIT(3)),
>>>> -	PINCTRL_CONF_DESC(49, REG_GPIO_H_PD, BIT(4)),
>>>> -	PINCTRL_CONF_DESC(50, REG_GPIO_H_PD, BIT(5)),
>>>> -	PINCTRL_CONF_DESC(51, REG_GPIO_H_PD, BIT(6)),
>>>> -	PINCTRL_CONF_DESC(52, REG_GPIO_H_PD, BIT(7)),
>>>> -	PINCTRL_CONF_DESC(53, REG_GPIO_H_PD, BIT(8)),
>>>> -	PINCTRL_CONF_DESC(54, REG_GPIO_H_PD, BIT(9)),
>>>> -	PINCTRL_CONF_DESC(55, REG_GPIO_H_PD, BIT(10)),
>>>> -	PINCTRL_CONF_DESC(56, REG_GPIO_H_PD, BIT(11)),
>>>> -	PINCTRL_CONF_DESC(57, REG_GPIO_H_PD, BIT(12)),
>>>> -	PINCTRL_CONF_DESC(58, REG_GPIO_H_PD, BIT(13)),
>>>> -	PINCTRL_CONF_DESC(59, REG_GPIO_H_PD, BIT(14)),
>>>> -	PINCTRL_CONF_DESC(60, REG_I2C_SDA_PD, PCIE0_RESET_PD_MASK),
>>>> -	PINCTRL_CONF_DESC(61, REG_I2C_SDA_PD, PCIE1_RESET_PD_MASK),
>>>> -	PINCTRL_CONF_DESC(62, REG_I2C_SDA_PD, PCIE2_RESET_PD_MASK),
>>>> -};
>>>> -
>>>> -static const struct airoha_pinctrl_conf an7583_pinctrl_pulldown_conf[] = {
>>>> -	PINCTRL_CONF_DESC(2, REG_GPIO_L_PD, BIT(0)),
>>>> -	PINCTRL_CONF_DESC(3, REG_GPIO_L_PD, BIT(1)),
>>>> -	PINCTRL_CONF_DESC(4, REG_GPIO_L_PD, BIT(2)),
>>>> -	PINCTRL_CONF_DESC(5, REG_GPIO_L_PD, BIT(3)),
>>>> -	PINCTRL_CONF_DESC(6, REG_GPIO_L_PD, BIT(4)),
>>>> -	PINCTRL_CONF_DESC(7, REG_GPIO_L_PD, BIT(5)),
>>>> -	PINCTRL_CONF_DESC(8, REG_GPIO_L_PD, BIT(6)),
>>>> -	PINCTRL_CONF_DESC(9, REG_GPIO_L_PD, BIT(7)),
>>>> -	PINCTRL_CONF_DESC(10, REG_GPIO_L_PD, BIT(8)),
>>>> -	PINCTRL_CONF_DESC(11, REG_GPIO_L_PD, BIT(9)),
>>>> -	PINCTRL_CONF_DESC(12, REG_GPIO_L_PD, BIT(10)),
>>>> -	PINCTRL_CONF_DESC(13, REG_GPIO_L_PD, BIT(11)),
>>>> -	PINCTRL_CONF_DESC(14, REG_GPIO_L_PD, BIT(12)),
>>>> -	PINCTRL_CONF_DESC(15, REG_GPIO_L_PD, BIT(13)),
>>>> -	PINCTRL_CONF_DESC(16, REG_GPIO_L_PD, BIT(14)),
>>>> -	PINCTRL_CONF_DESC(17, REG_GPIO_L_PD, BIT(15)),
>>>> -	PINCTRL_CONF_DESC(18, REG_GPIO_L_PD, BIT(16)),
>>>> -	PINCTRL_CONF_DESC(19, REG_GPIO_L_PD, BIT(17)),
>>>> -	PINCTRL_CONF_DESC(20, REG_GPIO_L_PD, BIT(18)),
>>>> -	PINCTRL_CONF_DESC(21, REG_GPIO_L_PD, BIT(19)),
>>>> -	PINCTRL_CONF_DESC(22, REG_GPIO_L_PD, BIT(20)),
>>>> -	PINCTRL_CONF_DESC(23, REG_GPIO_L_PD, BIT(21)),
>>>> -	PINCTRL_CONF_DESC(24, REG_GPIO_L_PD, BIT(22)),
>>>> -	PINCTRL_CONF_DESC(25, REG_GPIO_L_PD, BIT(23)),
>>>> -	PINCTRL_CONF_DESC(26, REG_GPIO_L_PD, BIT(24)),
>>>> -	PINCTRL_CONF_DESC(27, REG_GPIO_L_PD, BIT(25)),
>>>> -	PINCTRL_CONF_DESC(28, REG_GPIO_L_PD, BIT(26)),
>>>> -	PINCTRL_CONF_DESC(29, REG_GPIO_L_PD, BIT(27)),
>>>> -	PINCTRL_CONF_DESC(30, REG_GPIO_L_PD, BIT(28)),
>>>> -	PINCTRL_CONF_DESC(31, REG_GPIO_L_PD, BIT(29)),
>>>> -	PINCTRL_CONF_DESC(32, REG_GPIO_L_PD, BIT(30)),
>>>> -	PINCTRL_CONF_DESC(33, REG_GPIO_L_PD, BIT(31)),
>>>> -	PINCTRL_CONF_DESC(34, REG_GPIO_H_PD, BIT(0)),
>>>> -	PINCTRL_CONF_DESC(35, REG_GPIO_H_PD, BIT(1)),
>>>> -	PINCTRL_CONF_DESC(36, REG_GPIO_H_PD, BIT(2)),
>>>> -	PINCTRL_CONF_DESC(37, REG_GPIO_H_PD, BIT(3)),
>>>> -	PINCTRL_CONF_DESC(38, REG_GPIO_H_PD, BIT(4)),
>>>> -	PINCTRL_CONF_DESC(39, REG_GPIO_H_PD, BIT(5)),
>>>> -	PINCTRL_CONF_DESC(40, REG_GPIO_H_PD, BIT(6)),
>>>> -	PINCTRL_CONF_DESC(41, REG_I2C_SDA_PD, I2C_SCL_PD_MASK),
>>>> -	PINCTRL_CONF_DESC(42, REG_I2C_SDA_PD, I2C_SDA_PD_MASK),
>>>> -	PINCTRL_CONF_DESC(43, REG_I2C_SDA_PD, AN7583_I2C1_SCL_PD_MASK),
>>>> -	PINCTRL_CONF_DESC(44, REG_I2C_SDA_PD, AN7583_I2C1_SDA_PD_MASK),
>>>> -	PINCTRL_CONF_DESC(45, REG_I2C_SDA_PD, SPI_CLK_PD_MASK),
>>>> -	PINCTRL_CONF_DESC(46, REG_I2C_SDA_PD, SPI_CS0_PD_MASK),
>>>> -	PINCTRL_CONF_DESC(47, REG_I2C_SDA_PD, SPI_MOSI_PD_MASK),
>>>> -	PINCTRL_CONF_DESC(48, REG_I2C_SDA_PD, SPI_MISO_PD_MASK),
>>>> -	PINCTRL_CONF_DESC(49, REG_I2C_SDA_PD, UART1_TXD_PD_MASK),
>>>> -	PINCTRL_CONF_DESC(50, REG_I2C_SDA_PD, UART1_RXD_PD_MASK),
>>>> -	PINCTRL_CONF_DESC(51, REG_I2C_SDA_PD, PCIE0_RESET_PD_MASK),
>>>> -	PINCTRL_CONF_DESC(52, REG_I2C_SDA_PD, PCIE1_RESET_PD_MASK),
>>>> -	PINCTRL_CONF_DESC(53, REG_I2C_SDA_PD, AN7583_MDC_0_PD_MASK),
>>>> -	PINCTRL_CONF_DESC(54, REG_I2C_SDA_PD, AN7583_MDIO_0_PD_MASK),
>>>> -};
>>>> -
>>>> -static const struct airoha_pinctrl_conf en7581_pinctrl_drive_e2_conf[] = {
>>>> -	PINCTRL_CONF_DESC(0, REG_I2C_SDA_E2, UART1_TXD_E2_MASK),
>>>> -	PINCTRL_CONF_DESC(1, REG_I2C_SDA_E2, UART1_RXD_E2_MASK),
>>>> -	PINCTRL_CONF_DESC(2, REG_I2C_SDA_E2, I2C_SDA_E2_MASK),
>>>> -	PINCTRL_CONF_DESC(3, REG_I2C_SDA_E2, I2C_SCL_E2_MASK),
>>>> -	PINCTRL_CONF_DESC(4, REG_I2C_SDA_E2, SPI_CS0_E2_MASK),
>>>> -	PINCTRL_CONF_DESC(5, REG_I2C_SDA_E2, SPI_CLK_E2_MASK),
>>>> -	PINCTRL_CONF_DESC(6, REG_I2C_SDA_E2, SPI_MOSI_E2_MASK),
>>>> -	PINCTRL_CONF_DESC(7, REG_I2C_SDA_E2, SPI_MISO_E2_MASK),
>>>> -	PINCTRL_CONF_DESC(13, REG_GPIO_L_E2, BIT(0)),
>>>> -	PINCTRL_CONF_DESC(14, REG_GPIO_L_E2, BIT(1)),
>>>> -	PINCTRL_CONF_DESC(15, REG_GPIO_L_E2, BIT(2)),
>>>> -	PINCTRL_CONF_DESC(16, REG_GPIO_L_E2, BIT(3)),
>>>> -	PINCTRL_CONF_DESC(17, REG_GPIO_L_E2, BIT(4)),
>>>> -	PINCTRL_CONF_DESC(18, REG_GPIO_L_E2, BIT(5)),
>>>> -	PINCTRL_CONF_DESC(19, REG_GPIO_L_E2, BIT(6)),
>>>> -	PINCTRL_CONF_DESC(20, REG_GPIO_L_E2, BIT(7)),
>>>> -	PINCTRL_CONF_DESC(21, REG_GPIO_L_E2, BIT(8)),
>>>> -	PINCTRL_CONF_DESC(22, REG_GPIO_L_E2, BIT(9)),
>>>> -	PINCTRL_CONF_DESC(23, REG_GPIO_L_E2, BIT(10)),
>>>> -	PINCTRL_CONF_DESC(24, REG_GPIO_L_E2, BIT(11)),
>>>> -	PINCTRL_CONF_DESC(25, REG_GPIO_L_E2, BIT(12)),
>>>> -	PINCTRL_CONF_DESC(26, REG_GPIO_L_E2, BIT(13)),
>>>> -	PINCTRL_CONF_DESC(27, REG_GPIO_L_E2, BIT(14)),
>>>> -	PINCTRL_CONF_DESC(28, REG_GPIO_L_E2, BIT(15)),
>>>> -	PINCTRL_CONF_DESC(29, REG_GPIO_L_E2, BIT(16)),
>>>> -	PINCTRL_CONF_DESC(30, REG_GPIO_L_E2, BIT(17)),
>>>> -	PINCTRL_CONF_DESC(31, REG_GPIO_L_E2, BIT(18)),
>>>> -	PINCTRL_CONF_DESC(32, REG_GPIO_L_E2, BIT(19)),
>>>> -	PINCTRL_CONF_DESC(33, REG_GPIO_L_E2, BIT(20)),
>>>> -	PINCTRL_CONF_DESC(34, REG_GPIO_L_E2, BIT(21)),
>>>> -	PINCTRL_CONF_DESC(35, REG_GPIO_L_E2, BIT(22)),
>>>> -	PINCTRL_CONF_DESC(36, REG_GPIO_L_E2, BIT(23)),
>>>> -	PINCTRL_CONF_DESC(37, REG_GPIO_L_E2, BIT(24)),
>>>> -	PINCTRL_CONF_DESC(38, REG_GPIO_L_E2, BIT(25)),
>>>> -	PINCTRL_CONF_DESC(39, REG_GPIO_L_E2, BIT(26)),
>>>> -	PINCTRL_CONF_DESC(40, REG_GPIO_L_E2, BIT(27)),
>>>> -	PINCTRL_CONF_DESC(41, REG_GPIO_L_E2, BIT(28)),
>>>> -	PINCTRL_CONF_DESC(42, REG_GPIO_L_E2, BIT(29)),
>>>> -	PINCTRL_CONF_DESC(43, REG_GPIO_L_E2, BIT(30)),
>>>> -	PINCTRL_CONF_DESC(44, REG_GPIO_L_E2, BIT(31)),
>>>> -	PINCTRL_CONF_DESC(45, REG_GPIO_H_E2, BIT(0)),
>>>> -	PINCTRL_CONF_DESC(46, REG_GPIO_H_E2, BIT(1)),
>>>> -	PINCTRL_CONF_DESC(47, REG_GPIO_H_E2, BIT(2)),
>>>> -	PINCTRL_CONF_DESC(48, REG_GPIO_H_E2, BIT(3)),
>>>> -	PINCTRL_CONF_DESC(49, REG_GPIO_H_E2, BIT(4)),
>>>> -	PINCTRL_CONF_DESC(50, REG_GPIO_H_E2, BIT(5)),
>>>> -	PINCTRL_CONF_DESC(51, REG_GPIO_H_E2, BIT(6)),
>>>> -	PINCTRL_CONF_DESC(52, REG_GPIO_H_E2, BIT(7)),
>>>> -	PINCTRL_CONF_DESC(53, REG_GPIO_H_E2, BIT(8)),
>>>> -	PINCTRL_CONF_DESC(54, REG_GPIO_H_E2, BIT(9)),
>>>> -	PINCTRL_CONF_DESC(55, REG_GPIO_H_E2, BIT(10)),
>>>> -	PINCTRL_CONF_DESC(56, REG_GPIO_H_E2, BIT(11)),
>>>> -	PINCTRL_CONF_DESC(57, REG_GPIO_H_E2, BIT(12)),
>>>> -	PINCTRL_CONF_DESC(58, REG_GPIO_H_E2, BIT(13)),
>>>> -	PINCTRL_CONF_DESC(59, REG_GPIO_H_E2, BIT(14)),
>>>> -	PINCTRL_CONF_DESC(60, REG_I2C_SDA_E2, PCIE0_RESET_E2_MASK),
>>>> -	PINCTRL_CONF_DESC(61, REG_I2C_SDA_E2, PCIE1_RESET_E2_MASK),
>>>> -	PINCTRL_CONF_DESC(62, REG_I2C_SDA_E2, PCIE2_RESET_E2_MASK),
>>>> -};
>>>> -
>>>> -static const struct airoha_pinctrl_conf an7583_pinctrl_drive_e2_conf[] = {
>>>> -	PINCTRL_CONF_DESC(2, REG_GPIO_L_E2, BIT(0)),
>>>> -	PINCTRL_CONF_DESC(3, REG_GPIO_L_E2, BIT(1)),
>>>> -	PINCTRL_CONF_DESC(4, REG_GPIO_L_E2, BIT(2)),
>>>> -	PINCTRL_CONF_DESC(5, REG_GPIO_L_E2, BIT(3)),
>>>> -	PINCTRL_CONF_DESC(6, REG_GPIO_L_E2, BIT(4)),
>>>> -	PINCTRL_CONF_DESC(7, REG_GPIO_L_E2, BIT(5)),
>>>> -	PINCTRL_CONF_DESC(8, REG_GPIO_L_E2, BIT(6)),
>>>> -	PINCTRL_CONF_DESC(9, REG_GPIO_L_E2, BIT(7)),
>>>> -	PINCTRL_CONF_DESC(10, REG_GPIO_L_E2, BIT(8)),
>>>> -	PINCTRL_CONF_DESC(11, REG_GPIO_L_E2, BIT(9)),
>>>> -	PINCTRL_CONF_DESC(12, REG_GPIO_L_E2, BIT(10)),
>>>> -	PINCTRL_CONF_DESC(13, REG_GPIO_L_E2, BIT(11)),
>>>> -	PINCTRL_CONF_DESC(14, REG_GPIO_L_E2, BIT(12)),
>>>> -	PINCTRL_CONF_DESC(15, REG_GPIO_L_E2, BIT(13)),
>>>> -	PINCTRL_CONF_DESC(16, REG_GPIO_L_E2, BIT(14)),
>>>> -	PINCTRL_CONF_DESC(17, REG_GPIO_L_E2, BIT(15)),
>>>> -	PINCTRL_CONF_DESC(18, REG_GPIO_L_E2, BIT(16)),
>>>> -	PINCTRL_CONF_DESC(19, REG_GPIO_L_E2, BIT(17)),
>>>> -	PINCTRL_CONF_DESC(20, REG_GPIO_L_E2, BIT(18)),
>>>> -	PINCTRL_CONF_DESC(21, REG_GPIO_L_E2, BIT(19)),
>>>> -	PINCTRL_CONF_DESC(22, REG_GPIO_L_E2, BIT(20)),
>>>> -	PINCTRL_CONF_DESC(23, REG_GPIO_L_E2, BIT(21)),
>>>> -	PINCTRL_CONF_DESC(24, REG_GPIO_L_E2, BIT(22)),
>>>> -	PINCTRL_CONF_DESC(25, REG_GPIO_L_E2, BIT(23)),
>>>> -	PINCTRL_CONF_DESC(26, REG_GPIO_L_E2, BIT(24)),
>>>> -	PINCTRL_CONF_DESC(27, REG_GPIO_L_E2, BIT(25)),
>>>> -	PINCTRL_CONF_DESC(28, REG_GPIO_L_E2, BIT(26)),
>>>> -	PINCTRL_CONF_DESC(29, REG_GPIO_L_E2, BIT(27)),
>>>> -	PINCTRL_CONF_DESC(30, REG_GPIO_L_E2, BIT(28)),
>>>> -	PINCTRL_CONF_DESC(31, REG_GPIO_L_E2, BIT(29)),
>>>> -	PINCTRL_CONF_DESC(32, REG_GPIO_L_E2, BIT(30)),
>>>> -	PINCTRL_CONF_DESC(33, REG_GPIO_L_E2, BIT(31)),
>>>> -	PINCTRL_CONF_DESC(34, REG_GPIO_H_E2, BIT(0)),
>>>> -	PINCTRL_CONF_DESC(35, REG_GPIO_H_E2, BIT(1)),
>>>> -	PINCTRL_CONF_DESC(36, REG_GPIO_H_E2, BIT(2)),
>>>> -	PINCTRL_CONF_DESC(37, REG_GPIO_H_E2, BIT(3)),
>>>> -	PINCTRL_CONF_DESC(38, REG_GPIO_H_E2, BIT(4)),
>>>> -	PINCTRL_CONF_DESC(39, REG_GPIO_H_E2, BIT(5)),
>>>> -	PINCTRL_CONF_DESC(40, REG_GPIO_H_E2, BIT(6)),
>>>> -	PINCTRL_CONF_DESC(41, REG_I2C_SDA_E2, I2C_SCL_E2_MASK),
>>>> -	PINCTRL_CONF_DESC(42, REG_I2C_SDA_E2, I2C_SDA_E2_MASK),
>>>> -	PINCTRL_CONF_DESC(43, REG_I2C_SDA_E2, AN7583_I2C1_SCL_E2_MASK),
>>>> -	PINCTRL_CONF_DESC(44, REG_I2C_SDA_E2, AN7583_I2C1_SDA_E2_MASK),
>>>> -	PINCTRL_CONF_DESC(45, REG_I2C_SDA_E2, SPI_CLK_E2_MASK),
>>>> -	PINCTRL_CONF_DESC(46, REG_I2C_SDA_E2, SPI_CS0_E2_MASK),
>>>> -	PINCTRL_CONF_DESC(47, REG_I2C_SDA_E2, SPI_MOSI_E2_MASK),
>>>> -	PINCTRL_CONF_DESC(48, REG_I2C_SDA_E2, SPI_MISO_E2_MASK),
>>>> -	PINCTRL_CONF_DESC(49, REG_I2C_SDA_E2, UART1_TXD_E2_MASK),
>>>> -	PINCTRL_CONF_DESC(50, REG_I2C_SDA_E2, UART1_RXD_E2_MASK),
>>>> -	PINCTRL_CONF_DESC(51, REG_I2C_SDA_E2, PCIE0_RESET_E2_MASK),
>>>> -	PINCTRL_CONF_DESC(52, REG_I2C_SDA_E2, PCIE1_RESET_E2_MASK),
>>>> -	PINCTRL_CONF_DESC(53, REG_I2C_SDA_E2, AN7583_MDC_0_E2_MASK),
>>>> -	PINCTRL_CONF_DESC(54, REG_I2C_SDA_E2, AN7583_MDIO_0_E2_MASK),
>>>> -};
>>>> -
>>>> -static const struct airoha_pinctrl_conf en7581_pinctrl_drive_e4_conf[] = {
>>>> -	PINCTRL_CONF_DESC(0, REG_I2C_SDA_E4, UART1_TXD_E4_MASK),
>>>> -	PINCTRL_CONF_DESC(1, REG_I2C_SDA_E4, UART1_RXD_E4_MASK),
>>>> -	PINCTRL_CONF_DESC(2, REG_I2C_SDA_E4, I2C_SDA_E4_MASK),
>>>> -	PINCTRL_CONF_DESC(3, REG_I2C_SDA_E4, I2C_SCL_E4_MASK),
>>>> -	PINCTRL_CONF_DESC(4, REG_I2C_SDA_E4, SPI_CS0_E4_MASK),
>>>> -	PINCTRL_CONF_DESC(5, REG_I2C_SDA_E4, SPI_CLK_E4_MASK),
>>>> -	PINCTRL_CONF_DESC(6, REG_I2C_SDA_E4, SPI_MOSI_E4_MASK),
>>>> -	PINCTRL_CONF_DESC(7, REG_I2C_SDA_E4, SPI_MISO_E4_MASK),
>>>> -	PINCTRL_CONF_DESC(13, REG_GPIO_L_E4, BIT(0)),
>>>> -	PINCTRL_CONF_DESC(14, REG_GPIO_L_E4, BIT(1)),
>>>> -	PINCTRL_CONF_DESC(15, REG_GPIO_L_E4, BIT(2)),
>>>> -	PINCTRL_CONF_DESC(16, REG_GPIO_L_E4, BIT(3)),
>>>> -	PINCTRL_CONF_DESC(17, REG_GPIO_L_E4, BIT(4)),
>>>> -	PINCTRL_CONF_DESC(18, REG_GPIO_L_E4, BIT(5)),
>>>> -	PINCTRL_CONF_DESC(19, REG_GPIO_L_E4, BIT(6)),
>>>> -	PINCTRL_CONF_DESC(20, REG_GPIO_L_E4, BIT(7)),
>>>> -	PINCTRL_CONF_DESC(21, REG_GPIO_L_E4, BIT(8)),
>>>> -	PINCTRL_CONF_DESC(22, REG_GPIO_L_E4, BIT(9)),
>>>> -	PINCTRL_CONF_DESC(23, REG_GPIO_L_E4, BIT(10)),
>>>> -	PINCTRL_CONF_DESC(24, REG_GPIO_L_E4, BIT(11)),
>>>> -	PINCTRL_CONF_DESC(25, REG_GPIO_L_E4, BIT(12)),
>>>> -	PINCTRL_CONF_DESC(26, REG_GPIO_L_E4, BIT(13)),
>>>> -	PINCTRL_CONF_DESC(27, REG_GPIO_L_E4, BIT(14)),
>>>> -	PINCTRL_CONF_DESC(28, REG_GPIO_L_E4, BIT(15)),
>>>> -	PINCTRL_CONF_DESC(29, REG_GPIO_L_E4, BIT(16)),
>>>> -	PINCTRL_CONF_DESC(30, REG_GPIO_L_E4, BIT(17)),
>>>> -	PINCTRL_CONF_DESC(31, REG_GPIO_L_E4, BIT(18)),
>>>> -	PINCTRL_CONF_DESC(32, REG_GPIO_L_E4, BIT(19)),
>>>> -	PINCTRL_CONF_DESC(33, REG_GPIO_L_E4, BIT(20)),
>>>> -	PINCTRL_CONF_DESC(34, REG_GPIO_L_E4, BIT(21)),
>>>> -	PINCTRL_CONF_DESC(35, REG_GPIO_L_E4, BIT(22)),
>>>> -	PINCTRL_CONF_DESC(36, REG_GPIO_L_E4, BIT(23)),
>>>> -	PINCTRL_CONF_DESC(37, REG_GPIO_L_E4, BIT(24)),
>>>> -	PINCTRL_CONF_DESC(38, REG_GPIO_L_E4, BIT(25)),
>>>> -	PINCTRL_CONF_DESC(39, REG_GPIO_L_E4, BIT(26)),
>>>> -	PINCTRL_CONF_DESC(40, REG_GPIO_L_E4, BIT(27)),
>>>> -	PINCTRL_CONF_DESC(41, REG_GPIO_L_E4, BIT(28)),
>>>> -	PINCTRL_CONF_DESC(42, REG_GPIO_L_E4, BIT(29)),
>>>> -	PINCTRL_CONF_DESC(43, REG_GPIO_L_E4, BIT(30)),
>>>> -	PINCTRL_CONF_DESC(44, REG_GPIO_L_E4, BIT(31)),
>>>> -	PINCTRL_CONF_DESC(45, REG_GPIO_H_E4, BIT(0)),
>>>> -	PINCTRL_CONF_DESC(46, REG_GPIO_H_E4, BIT(1)),
>>>> -	PINCTRL_CONF_DESC(47, REG_GPIO_H_E4, BIT(2)),
>>>> -	PINCTRL_CONF_DESC(48, REG_GPIO_H_E4, BIT(3)),
>>>> -	PINCTRL_CONF_DESC(49, REG_GPIO_H_E4, BIT(4)),
>>>> -	PINCTRL_CONF_DESC(50, REG_GPIO_H_E4, BIT(5)),
>>>> -	PINCTRL_CONF_DESC(51, REG_GPIO_H_E4, BIT(6)),
>>>> -	PINCTRL_CONF_DESC(52, REG_GPIO_H_E4, BIT(7)),
>>>> -	PINCTRL_CONF_DESC(53, REG_GPIO_H_E4, BIT(8)),
>>>> -	PINCTRL_CONF_DESC(54, REG_GPIO_H_E4, BIT(9)),
>>>> -	PINCTRL_CONF_DESC(55, REG_GPIO_H_E4, BIT(10)),
>>>> -	PINCTRL_CONF_DESC(56, REG_GPIO_H_E4, BIT(11)),
>>>> -	PINCTRL_CONF_DESC(57, REG_GPIO_H_E4, BIT(12)),
>>>> -	PINCTRL_CONF_DESC(58, REG_GPIO_H_E4, BIT(13)),
>>>> -	PINCTRL_CONF_DESC(59, REG_GPIO_H_E4, BIT(14)),
>>>> -	PINCTRL_CONF_DESC(60, REG_I2C_SDA_E4, PCIE0_RESET_E4_MASK),
>>>> -	PINCTRL_CONF_DESC(61, REG_I2C_SDA_E4, PCIE1_RESET_E4_MASK),
>>>> -	PINCTRL_CONF_DESC(62, REG_I2C_SDA_E4, PCIE2_RESET_E4_MASK),
>>>> -};
>>>> -
>>>> -static const struct airoha_pinctrl_conf an7583_pinctrl_drive_e4_conf[] = {
>>>> -	PINCTRL_CONF_DESC(2, REG_GPIO_L_E4, BIT(0)),
>>>> -	PINCTRL_CONF_DESC(3, REG_GPIO_L_E4, BIT(1)),
>>>> -	PINCTRL_CONF_DESC(4, REG_GPIO_L_E4, BIT(2)),
>>>> -	PINCTRL_CONF_DESC(5, REG_GPIO_L_E4, BIT(3)),
>>>> -	PINCTRL_CONF_DESC(6, REG_GPIO_L_E4, BIT(4)),
>>>> -	PINCTRL_CONF_DESC(7, REG_GPIO_L_E4, BIT(5)),
>>>> -	PINCTRL_CONF_DESC(8, REG_GPIO_L_E4, BIT(6)),
>>>> -	PINCTRL_CONF_DESC(9, REG_GPIO_L_E4, BIT(7)),
>>>> -	PINCTRL_CONF_DESC(10, REG_GPIO_L_E4, BIT(8)),
>>>> -	PINCTRL_CONF_DESC(11, REG_GPIO_L_E4, BIT(9)),
>>>> -	PINCTRL_CONF_DESC(12, REG_GPIO_L_E4, BIT(10)),
>>>> -	PINCTRL_CONF_DESC(13, REG_GPIO_L_E4, BIT(11)),
>>>> -	PINCTRL_CONF_DESC(14, REG_GPIO_L_E4, BIT(12)),
>>>> -	PINCTRL_CONF_DESC(15, REG_GPIO_L_E4, BIT(13)),
>>>> -	PINCTRL_CONF_DESC(16, REG_GPIO_L_E4, BIT(14)),
>>>> -	PINCTRL_CONF_DESC(17, REG_GPIO_L_E4, BIT(15)),
>>>> -	PINCTRL_CONF_DESC(18, REG_GPIO_L_E4, BIT(16)),
>>>> -	PINCTRL_CONF_DESC(19, REG_GPIO_L_E4, BIT(17)),
>>>> -	PINCTRL_CONF_DESC(20, REG_GPIO_L_E4, BIT(18)),
>>>> -	PINCTRL_CONF_DESC(21, REG_GPIO_L_E4, BIT(19)),
>>>> -	PINCTRL_CONF_DESC(22, REG_GPIO_L_E4, BIT(20)),
>>>> -	PINCTRL_CONF_DESC(23, REG_GPIO_L_E4, BIT(21)),
>>>> -	PINCTRL_CONF_DESC(24, REG_GPIO_L_E4, BIT(22)),
>>>> -	PINCTRL_CONF_DESC(25, REG_GPIO_L_E4, BIT(23)),
>>>> -	PINCTRL_CONF_DESC(26, REG_GPIO_L_E4, BIT(24)),
>>>> -	PINCTRL_CONF_DESC(27, REG_GPIO_L_E4, BIT(25)),
>>>> -	PINCTRL_CONF_DESC(28, REG_GPIO_L_E4, BIT(26)),
>>>> -	PINCTRL_CONF_DESC(29, REG_GPIO_L_E4, BIT(27)),
>>>> -	PINCTRL_CONF_DESC(30, REG_GPIO_L_E4, BIT(28)),
>>>> -	PINCTRL_CONF_DESC(31, REG_GPIO_L_E4, BIT(29)),
>>>> -	PINCTRL_CONF_DESC(32, REG_GPIO_L_E4, BIT(30)),
>>>> -	PINCTRL_CONF_DESC(33, REG_GPIO_L_E4, BIT(31)),
>>>> -	PINCTRL_CONF_DESC(34, REG_GPIO_H_E4, BIT(0)),
>>>> -	PINCTRL_CONF_DESC(35, REG_GPIO_H_E4, BIT(1)),
>>>> -	PINCTRL_CONF_DESC(36, REG_GPIO_H_E4, BIT(2)),
>>>> -	PINCTRL_CONF_DESC(37, REG_GPIO_H_E4, BIT(3)),
>>>> -	PINCTRL_CONF_DESC(38, REG_GPIO_H_E4, BIT(4)),
>>>> -	PINCTRL_CONF_DESC(39, REG_GPIO_H_E4, BIT(5)),
>>>> -	PINCTRL_CONF_DESC(40, REG_GPIO_H_E4, BIT(6)),
>>>> -	PINCTRL_CONF_DESC(41, REG_I2C_SDA_E4, I2C_SCL_E4_MASK),
>>>> -	PINCTRL_CONF_DESC(42, REG_I2C_SDA_E4, I2C_SDA_E4_MASK),
>>>> -	PINCTRL_CONF_DESC(43, REG_I2C_SDA_E4, AN7583_I2C1_SCL_E4_MASK),
>>>> -	PINCTRL_CONF_DESC(44, REG_I2C_SDA_E4, AN7583_I2C1_SDA_E4_MASK),
>>>> -	PINCTRL_CONF_DESC(45, REG_I2C_SDA_E4, SPI_CLK_E4_MASK),
>>>> -	PINCTRL_CONF_DESC(46, REG_I2C_SDA_E4, SPI_CS0_E4_MASK),
>>>> -	PINCTRL_CONF_DESC(47, REG_I2C_SDA_E4, SPI_MOSI_E4_MASK),
>>>> -	PINCTRL_CONF_DESC(48, REG_I2C_SDA_E4, SPI_MISO_E4_MASK),
>>>> -	PINCTRL_CONF_DESC(49, REG_I2C_SDA_E4, UART1_TXD_E4_MASK),
>>>> -	PINCTRL_CONF_DESC(50, REG_I2C_SDA_E4, UART1_RXD_E4_MASK),
>>>> -	PINCTRL_CONF_DESC(51, REG_I2C_SDA_E4, PCIE0_RESET_E4_MASK),
>>>> -	PINCTRL_CONF_DESC(52, REG_I2C_SDA_E4, PCIE1_RESET_E4_MASK),
>>>> -	PINCTRL_CONF_DESC(53, REG_I2C_SDA_E4, AN7583_MDC_0_E4_MASK),
>>>> -	PINCTRL_CONF_DESC(54, REG_I2C_SDA_E4, AN7583_MDIO_0_E4_MASK),
>>>> -};
>>>> -
>>>> -static const struct airoha_pinctrl_conf en7581_pinctrl_pcie_rst_od_conf[] = {
>>>> -	PINCTRL_CONF_DESC(60, REG_PCIE_RESET_OD, PCIE0_RESET_OD_MASK),
>>>> -	PINCTRL_CONF_DESC(61, REG_PCIE_RESET_OD, PCIE1_RESET_OD_MASK),
>>>> -	PINCTRL_CONF_DESC(62, REG_PCIE_RESET_OD, PCIE2_RESET_OD_MASK),
>>>> -};
>>>> -
>>>> -static const struct airoha_pinctrl_conf an7583_pinctrl_pcie_rst_od_conf[] = {
>>>> -	PINCTRL_CONF_DESC(51, REG_PCIE_RESET_OD, PCIE0_RESET_OD_MASK),
>>>> -	PINCTRL_CONF_DESC(52, REG_PCIE_RESET_OD, PCIE1_RESET_OD_MASK),
>>>> -};
>>>> -
>>>>  static int airoha_convert_pin_to_reg_offset(struct pinctrl_dev *pctrl_dev,
>>>>  					    struct pinctrl_gpio_range *range,
>>>>  					    int pin)
>>>> @@ -2606,6 +318,7 @@ static int airoha_pinctrl_add_gpiochip(struct airoha_pinctrl *pinctrl,
>>>>  					struct platform_device *pdev)
>>>>  {
>>>>  	struct airoha_pinctrl_gpiochip *chip = &pinctrl->gpiochip;
>>>> +	struct irq_chip *irq_chip = &pinctrl->gpio_irq_chip;
>>>>  	struct gpio_chip *gc = &chip->chip;
>>>>  	struct gpio_irq_chip *girq = &gc->irq;
>>>>  	struct device *dev = &pdev->dev;
>>>> @@ -2630,9 +343,11 @@ static int airoha_pinctrl_add_gpiochip(struct airoha_pinctrl *pinctrl,
>>>>  	gc->base = -1;
>>>>  	gc->ngpio = AIROHA_NUM_PINS;
>>>>  
>>>> +	memcpy(irq_chip, &airoha_gpio_irq_chip, sizeof(struct irq_chip));
>>>> +
>>>>  	girq->default_type = IRQ_TYPE_NONE;
>>>>  	girq->handler = handle_bad_irq;
>>>> -	gpio_irq_chip_set_chip(girq, &airoha_gpio_irq_chip);
>>>> +	gpio_irq_chip_set_chip(girq, irq_chip);
>>>>  
>>>>  	irq = platform_get_irq(pdev, 0);
>>>>  	if (irq < 0)
>>>> @@ -3011,7 +726,7 @@ static const struct pinctrl_ops airoha_pctlops = {
>>>>  	.dt_free_map = pinconf_generic_dt_free_map,
>>>>  };
>>>>  
>>>> -static int airoha_pinctrl_probe(struct platform_device *pdev)
>>>> +int airoha_pinctrl_probe(struct platform_device *pdev)
>>>>  {
>>>>  	const struct airoha_pinctrl_match_data *data;
>>>>  	struct device *dev = &pdev->dev;
>>>> @@ -3020,6 +735,8 @@ static int airoha_pinctrl_probe(struct platform_device *pdev)
>>>>  	int err, i;
>>>>  
>>>>  	data = device_get_match_data(dev);
>>>> +	if (!data)
>>>> +		return -EINVAL;
>>>>  
>>>>  	pinctrl = devm_kzalloc(dev, sizeof(*pinctrl), GFP_KERNEL);
>>>>  	if (!pinctrl)
>>>> @@ -3036,8 +753,8 @@ static int airoha_pinctrl_probe(struct platform_device *pdev)
>>>>  	pinctrl->chip_scu = map;
>>>>  
>>>>  	/* Init pinctrl desc struct */
>>>> -	pinctrl->desc.name = KBUILD_MODNAME;
>>>> -	pinctrl->desc.owner = THIS_MODULE;
>>>> +	pinctrl->desc.name = data->pinctrl_name;
>>>> +	pinctrl->desc.owner = data->pinctrl_owner;
>>>>  	pinctrl->desc.pctlops = &airoha_pctlops;
>>>>  	pinctrl->desc.pmxops = &airoha_pmxops;
>>>>  	pinctrl->desc.confops = &airoha_confops;
>>>> @@ -3089,87 +806,10 @@ static int airoha_pinctrl_probe(struct platform_device *pdev)
>>>>  	/* build gpio-chip */
>>>>  	return airoha_pinctrl_add_gpiochip(pinctrl, pdev);
>>>>  }
>>>> -
>>>> -static const struct airoha_pinctrl_match_data en7581_pinctrl_match_data = {
>>>> -	.pins = en7581_pinctrl_pins,
>>>> -	.num_pins = ARRAY_SIZE(en7581_pinctrl_pins),
>>>> -	.grps = en7581_pinctrl_groups,
>>>> -	.num_grps = ARRAY_SIZE(en7581_pinctrl_groups),
>>>> -	.funcs = en7581_pinctrl_funcs,
>>>> -	.num_funcs = ARRAY_SIZE(en7581_pinctrl_funcs),
>>>> -	.confs_info = {
>>>> -		[AIROHA_PINCTRL_CONFS_PULLUP] = {
>>>> -			.confs = en7581_pinctrl_pullup_conf,
>>>> -			.num_confs = ARRAY_SIZE(en7581_pinctrl_pullup_conf),
>>>> -		},
>>>> -		[AIROHA_PINCTRL_CONFS_PULLDOWN] = {
>>>> -			.confs = en7581_pinctrl_pulldown_conf,
>>>> -			.num_confs = ARRAY_SIZE(en7581_pinctrl_pulldown_conf),
>>>> -		},
>>>> -		[AIROHA_PINCTRL_CONFS_DRIVE_E2] = {
>>>> -			.confs = en7581_pinctrl_drive_e2_conf,
>>>> -			.num_confs = ARRAY_SIZE(en7581_pinctrl_drive_e2_conf),
>>>> -		},
>>>> -		[AIROHA_PINCTRL_CONFS_DRIVE_E4] = {
>>>> -			.confs = en7581_pinctrl_drive_e4_conf,
>>>> -			.num_confs = ARRAY_SIZE(en7581_pinctrl_drive_e4_conf),
>>>> -		},
>>>> -		[AIROHA_PINCTRL_CONFS_PCIE_RST_OD] = {
>>>> -			.confs = en7581_pinctrl_pcie_rst_od_conf,
>>>> -			.num_confs = ARRAY_SIZE(en7581_pinctrl_pcie_rst_od_conf),
>>>> -		},
>>>> -	},
>>>> -};
>>>> -
>>>> -static const struct airoha_pinctrl_match_data an7583_pinctrl_match_data = {
>>>> -	.pins = an7583_pinctrl_pins,
>>>> -	.num_pins = ARRAY_SIZE(an7583_pinctrl_pins),
>>>> -	.grps = an7583_pinctrl_groups,
>>>> -	.num_grps = ARRAY_SIZE(an7583_pinctrl_groups),
>>>> -	.funcs = an7583_pinctrl_funcs,
>>>> -	.num_funcs = ARRAY_SIZE(an7583_pinctrl_funcs),
>>>> -	.confs_info = {
>>>> -		[AIROHA_PINCTRL_CONFS_PULLUP] = {
>>>> -			.confs = an7583_pinctrl_pullup_conf,
>>>> -			.num_confs = ARRAY_SIZE(an7583_pinctrl_pullup_conf),
>>>> -		},
>>>> -		[AIROHA_PINCTRL_CONFS_PULLDOWN] = {
>>>> -			.confs = an7583_pinctrl_pulldown_conf,
>>>> -			.num_confs = ARRAY_SIZE(an7583_pinctrl_pulldown_conf),
>>>> -		},
>>>> -		[AIROHA_PINCTRL_CONFS_DRIVE_E2] = {
>>>> -			.confs = an7583_pinctrl_drive_e2_conf,
>>>> -			.num_confs = ARRAY_SIZE(an7583_pinctrl_drive_e2_conf),
>>>> -		},
>>>> -		[AIROHA_PINCTRL_CONFS_DRIVE_E4] = {
>>>> -			.confs = an7583_pinctrl_drive_e4_conf,
>>>> -			.num_confs = ARRAY_SIZE(an7583_pinctrl_drive_e4_conf),
>>>> -		},
>>>> -		[AIROHA_PINCTRL_CONFS_PCIE_RST_OD] = {
>>>> -			.confs = an7583_pinctrl_pcie_rst_od_conf,
>>>> -			.num_confs = ARRAY_SIZE(an7583_pinctrl_pcie_rst_od_conf),
>>>> -		},
>>>> -	},
>>>> -};
>>>> -
>>>> -static const struct of_device_id airoha_pinctrl_of_match[] = {
>>>> -	{ .compatible = "airoha,en7581-pinctrl", .data = &en7581_pinctrl_match_data },
>>>> -	{ .compatible = "airoha,an7583-pinctrl", .data = &an7583_pinctrl_match_data },
>>>> -	{ /* sentinel */ }
>>>> -};
>>>> -MODULE_DEVICE_TABLE(of, airoha_pinctrl_of_match);
>>>> -
>>>> -static struct platform_driver airoha_pinctrl_driver = {
>>>> -	.probe = airoha_pinctrl_probe,
>>>> -	.driver = {
>>>> -		.name = "pinctrl-airoha",
>>>> -		.of_match_table = airoha_pinctrl_of_match,
>>>> -	},
>>>> -};
>>>> -module_platform_driver(airoha_pinctrl_driver);
>>>> +EXPORT_SYMBOL_GPL(airoha_pinctrl_probe);
>>>>  
>>>>  MODULE_LICENSE("GPL");
>>>>  MODULE_AUTHOR("Lorenzo Bianconi <lorenzo@kernel.org>");
>>>>  MODULE_AUTHOR("Benjamin Larsson <benjamin.larsson@genexis.eu>");
>>>>  MODULE_AUTHOR("Markus Gothe <markus.gothe@genexis.eu>");
>>>> -MODULE_DESCRIPTION("Pinctrl driver for Airoha SoC");
>>>> +MODULE_DESCRIPTION("Pinctrl common driver for Airoha SoC");
>>>> diff --git a/drivers/pinctrl/airoha/pinctrl-an7581.c b/drivers/pinctrl/airoha/pinctrl-an7581.c
>>>> new file mode 100644
>>>> index 0000000000000..522b35bbaa121
>>>> --- /dev/null
>>>> +++ b/drivers/pinctrl/airoha/pinctrl-an7581.c
>>>> @@ -0,0 +1,1486 @@
>>>> +// SPDX-License-Identifier: GPL-2.0-only
>>>> +/*
>>>> + * Author: Lorenzo Bianconi <lorenzo@kernel.org>
>>>> + * Author: Benjamin Larsson <benjamin.larsson@genexis.eu>
>>>> + * Author: Markus Gothe <markus.gothe@genexis.eu>
>>>> + */
>>>> +
>>>> +#include "airoha-common.h"
>>>> +
>>>> +/* MUX */
>>>> +#define REG_GPIO_2ND_I2C_MODE			0x0214
>>>> +#define GPIO_MDC_IO_MASTER_MODE_MASK		BIT(14)
>>>> +#define GPIO_I2C_MASTER_MODE_MODE		BIT(13)
>>>> +#define GPIO_I2S_MODE_MASK			BIT(12)
>>>> +#define GPIO_I2C_SLAVE_MODE_MODE		BIT(11)
>>>> +#define GPIO_LAN3_LED1_MODE_MASK		BIT(10)
>>>> +#define GPIO_LAN3_LED0_MODE_MASK		BIT(9)
>>>> +#define GPIO_LAN2_LED1_MODE_MASK		BIT(8)
>>>> +#define GPIO_LAN2_LED0_MODE_MASK		BIT(7)
>>>> +#define GPIO_LAN1_LED1_MODE_MASK		BIT(6)
>>>> +#define GPIO_LAN1_LED0_MODE_MASK		BIT(5)
>>>> +#define GPIO_LAN0_LED1_MODE_MASK		BIT(4)
>>>> +#define GPIO_LAN0_LED0_MODE_MASK		BIT(3)
>>>> +#define PON_TOD_1PPS_MODE_MASK			BIT(2)
>>>> +#define GSW_TOD_1PPS_MODE_MASK			BIT(1)
>>>> +#define GPIO_2ND_I2C_MODE_MASK			BIT(0)
>>>> +
>>>> +#define REG_GPIO_SPI_CS1_MODE			0x0218
>>>> +#define GPIO_PCM_SPI_CS4_MODE_MASK		BIT(21)
>>>> +#define GPIO_PCM_SPI_CS3_MODE_MASK		BIT(20)
>>>> +#define GPIO_PCM_SPI_CS2_MODE_P156_MASK		BIT(19)
>>>> +#define GPIO_PCM_SPI_CS2_MODE_P128_MASK		BIT(18)
>>>> +#define GPIO_PCM_SPI_CS1_MODE_MASK		BIT(17)
>>>> +#define GPIO_PCM_SPI_MODE_MASK			BIT(16)
>>>> +#define GPIO_PCM2_MODE_MASK			BIT(13)
>>>> +#define GPIO_PCM1_MODE_MASK			BIT(12)
>>>> +#define GPIO_PCM_INT_MODE_MASK			BIT(9)
>>>> +#define GPIO_PCM_RESET_MODE_MASK		BIT(8)
>>>> +#define GPIO_SPI_QUAD_MODE_MASK			BIT(4)
>>>> +#define GPIO_SPI_CS4_MODE_MASK			BIT(3)
>>>> +#define GPIO_SPI_CS3_MODE_MASK			BIT(2)
>>>> +#define GPIO_SPI_CS2_MODE_MASK			BIT(1)
>>>> +#define GPIO_SPI_CS1_MODE_MASK			BIT(0)
>>>> +
>>>> +#define REG_GPIO_PON_MODE			0x021c
>>>> +#define GPIO_PARALLEL_NAND_MODE_MASK		BIT(14)
>>>> +#define GPIO_SGMII_MDIO_MODE_MASK		BIT(13)
>>>> +#define GPIO_PCIE_RESET2_MASK			BIT(12)
>>>> +#define SIPO_RCLK_MODE_MASK			BIT(11)
>>>> +#define GPIO_PCIE_RESET1_MASK			BIT(10)
>>>> +#define GPIO_PCIE_RESET0_MASK			BIT(9)
>>>> +#define GPIO_UART5_MODE_MASK			BIT(8)
>>>> +#define GPIO_UART4_MODE_MASK			BIT(7)
>>>> +#define GPIO_HSUART_CTS_RTS_MODE_MASK		BIT(6)
>>>> +#define GPIO_HSUART_MODE_MASK			BIT(5)
>>>> +#define GPIO_UART2_CTS_RTS_MODE_MASK		BIT(4)
>>>> +#define GPIO_UART2_MODE_MASK			BIT(3)
>>>> +#define GPIO_SIPO_MODE_MASK			BIT(2)
>>>> +#define GPIO_EMMC_MODE_MASK			BIT(1)
>>>> +#define GPIO_PON_MODE_MASK			BIT(0)
>>>> +
>>>> +#define REG_NPU_UART_EN				0x0224
>>>> +#define JTAG_UDI_EN_MASK			BIT(4)
>>>> +#define JTAG_DFD_EN_MASK			BIT(3)
>>>> +
>>>> +#define REG_FORCE_GPIO_EN			0x0228
>>>> +#define FORCE_GPIO_EN(n)			BIT(n)
>>>> +
>>>> +/* LED MAP */
>>>> +#define REG_LAN_LED0_MAPPING			0x027c
>>>> +#define REG_LAN_LED1_MAPPING			0x0280
>>>> +
>>>> +#define LAN4_LED_MAPPING_MASK			GENMASK(18, 16)
>>>> +#define LAN4_PHY_LED_MAP(_n)			FIELD_PREP_CONST(LAN4_LED_MAPPING_MASK, (_n))
>>>> +
>>>> +#define LAN3_LED_MAPPING_MASK			GENMASK(14, 12)
>>>> +#define LAN3_PHY_LED_MAP(_n)			FIELD_PREP_CONST(LAN3_LED_MAPPING_MASK, (_n))
>>>> +
>>>> +#define LAN2_LED_MAPPING_MASK			GENMASK(10, 8)
>>>> +#define LAN2_PHY_LED_MAP(_n)			FIELD_PREP_CONST(LAN2_LED_MAPPING_MASK, (_n))
>>>> +
>>>> +#define LAN1_LED_MAPPING_MASK			GENMASK(6, 4)
>>>> +#define LAN1_PHY_LED_MAP(_n)			FIELD_PREP_CONST(LAN1_LED_MAPPING_MASK, (_n))
>>>> +
>>>> +#define LAN0_LED_MAPPING_MASK			GENMASK(2, 0)
>>>> +#define LAN0_PHY_LED_MAP(_n)			FIELD_PREP_CONST(LAN0_LED_MAPPING_MASK, (_n))
>>>> +
>>>> +/* CONF */
>>>> +#define REG_I2C_SDA_E2				0x001c
>>>> +#define SPI_MISO_E2_MASK			BIT(14)
>>>> +#define SPI_MOSI_E2_MASK			BIT(13)
>>>> +#define SPI_CLK_E2_MASK				BIT(12)
>>>> +#define SPI_CS0_E2_MASK				BIT(11)
>>>> +#define PCIE2_RESET_E2_MASK			BIT(10)
>>>> +#define PCIE1_RESET_E2_MASK			BIT(9)
>>>> +#define PCIE0_RESET_E2_MASK			BIT(8)
>>>> +#define UART1_RXD_E2_MASK			BIT(3)
>>>> +#define UART1_TXD_E2_MASK			BIT(2)
>>>> +#define I2C_SCL_E2_MASK				BIT(1)
>>>> +#define I2C_SDA_E2_MASK				BIT(0)
>>>> +
>>>> +#define REG_I2C_SDA_E4				0x0020
>>>> +#define SPI_MISO_E4_MASK			BIT(14)
>>>> +#define SPI_MOSI_E4_MASK			BIT(13)
>>>> +#define SPI_CLK_E4_MASK				BIT(12)
>>>> +#define SPI_CS0_E4_MASK				BIT(11)
>>>> +#define PCIE2_RESET_E4_MASK			BIT(10)
>>>> +#define PCIE1_RESET_E4_MASK			BIT(9)
>>>> +#define PCIE0_RESET_E4_MASK			BIT(8)
>>>> +#define UART1_RXD_E4_MASK			BIT(3)
>>>> +#define UART1_TXD_E4_MASK			BIT(2)
>>>> +#define I2C_SCL_E4_MASK				BIT(1)
>>>> +#define I2C_SDA_E4_MASK				BIT(0)
>>>> +
>>>> +#define REG_GPIO_L_E2				0x0024
>>>> +#define REG_GPIO_L_E4				0x0028
>>>> +#define REG_GPIO_H_E2				0x002c
>>>> +#define REG_GPIO_H_E4				0x0030
>>>> +
>>>> +#define REG_I2C_SDA_PU				0x0044
>>>> +#define SPI_MISO_PU_MASK			BIT(14)
>>>> +#define SPI_MOSI_PU_MASK			BIT(13)
>>>> +#define SPI_CLK_PU_MASK				BIT(12)
>>>> +#define SPI_CS0_PU_MASK				BIT(11)
>>>> +#define PCIE2_RESET_PU_MASK			BIT(10)
>>>> +#define PCIE1_RESET_PU_MASK			BIT(9)
>>>> +#define PCIE0_RESET_PU_MASK			BIT(8)
>>>> +#define UART1_RXD_PU_MASK			BIT(3)
>>>> +#define UART1_TXD_PU_MASK			BIT(2)
>>>> +#define I2C_SCL_PU_MASK				BIT(1)
>>>> +#define I2C_SDA_PU_MASK				BIT(0)
>>>> +
>>>> +#define REG_I2C_SDA_PD				0x0048
>>>> +#define SPI_MISO_PD_MASK			BIT(14)
>>>> +#define SPI_MOSI_PD_MASK			BIT(13)
>>>> +#define SPI_CLK_PD_MASK				BIT(12)
>>>> +#define SPI_CS0_PD_MASK				BIT(11)
>>>> +#define PCIE2_RESET_PD_MASK			BIT(10)
>>>> +#define PCIE1_RESET_PD_MASK			BIT(9)
>>>> +#define PCIE0_RESET_PD_MASK			BIT(8)
>>>> +#define UART1_RXD_PD_MASK			BIT(3)
>>>> +#define UART1_TXD_PD_MASK			BIT(2)
>>>> +#define I2C_SCL_PD_MASK				BIT(1)
>>>> +#define I2C_SDA_PD_MASK				BIT(0)
>>>> +
>>>> +#define REG_GPIO_L_PU				0x004c
>>>> +#define REG_GPIO_L_PD				0x0050
>>>> +#define REG_GPIO_H_PU				0x0054
>>>> +#define REG_GPIO_H_PD				0x0058
>>>> +
>>>> +#define REG_PCIE_RESET_OD			0x018c
>>>> +#define PCIE2_RESET_OD_MASK			BIT(2)
>>>> +#define PCIE1_RESET_OD_MASK			BIT(1)
>>>> +#define PCIE0_RESET_OD_MASK			BIT(0)
>>>> +
>>>> +/* PWM MODE CONF */
>>>> +#define REG_GPIO_FLASH_MODE_CFG			0x0034
>>>> +#define GPIO15_FLASH_MODE_CFG			BIT(15)
>>>> +#define GPIO14_FLASH_MODE_CFG			BIT(14)
>>>> +#define GPIO13_FLASH_MODE_CFG			BIT(13)
>>>> +#define GPIO12_FLASH_MODE_CFG			BIT(12)
>>>> +#define GPIO11_FLASH_MODE_CFG			BIT(11)
>>>> +#define GPIO10_FLASH_MODE_CFG			BIT(10)
>>>> +#define GPIO9_FLASH_MODE_CFG			BIT(9)
>>>> +#define GPIO8_FLASH_MODE_CFG			BIT(8)
>>>> +#define GPIO7_FLASH_MODE_CFG			BIT(7)
>>>> +#define GPIO6_FLASH_MODE_CFG			BIT(6)
>>>> +#define GPIO5_FLASH_MODE_CFG			BIT(5)
>>>> +#define GPIO4_FLASH_MODE_CFG			BIT(4)
>>>> +#define GPIO3_FLASH_MODE_CFG			BIT(3)
>>>> +#define GPIO2_FLASH_MODE_CFG			BIT(2)
>>>> +#define GPIO1_FLASH_MODE_CFG			BIT(1)
>>>> +#define GPIO0_FLASH_MODE_CFG			BIT(0)
>>>> +
>>>> +/* PWM MODE CONF EXT */
>>>> +#define REG_GPIO_FLASH_MODE_CFG_EXT		0x0068
>>>> +#define GPIO51_FLASH_MODE_CFG			BIT(31)
>>>> +#define GPIO50_FLASH_MODE_CFG			BIT(30)
>>>> +#define GPIO49_FLASH_MODE_CFG			BIT(29)
>>>> +#define GPIO48_FLASH_MODE_CFG			BIT(28)
>>>> +#define GPIO47_FLASH_MODE_CFG			BIT(27)
>>>> +#define GPIO46_FLASH_MODE_CFG			BIT(26)
>>>> +#define GPIO45_FLASH_MODE_CFG			BIT(25)
>>>> +#define GPIO44_FLASH_MODE_CFG			BIT(24)
>>>> +#define GPIO43_FLASH_MODE_CFG			BIT(23)
>>>> +#define GPIO42_FLASH_MODE_CFG			BIT(22)
>>>> +#define GPIO41_FLASH_MODE_CFG			BIT(21)
>>>> +#define GPIO40_FLASH_MODE_CFG			BIT(20)
>>>> +#define GPIO39_FLASH_MODE_CFG			BIT(19)
>>>> +#define GPIO38_FLASH_MODE_CFG			BIT(18)
>>>> +#define GPIO37_FLASH_MODE_CFG			BIT(17)
>>>> +#define GPIO36_FLASH_MODE_CFG			BIT(16)
>>>> +#define GPIO31_FLASH_MODE_CFG			BIT(15)
>>>> +#define GPIO30_FLASH_MODE_CFG			BIT(14)
>>>> +#define GPIO29_FLASH_MODE_CFG			BIT(13)
>>>> +#define GPIO28_FLASH_MODE_CFG			BIT(12)
>>>> +#define GPIO27_FLASH_MODE_CFG			BIT(11)
>>>> +#define GPIO26_FLASH_MODE_CFG			BIT(10)
>>>> +#define GPIO25_FLASH_MODE_CFG			BIT(9)
>>>> +#define GPIO24_FLASH_MODE_CFG			BIT(8)
>>>> +#define GPIO23_FLASH_MODE_CFG			BIT(7)
>>>> +#define GPIO22_FLASH_MODE_CFG			BIT(6)
>>>> +#define GPIO21_FLASH_MODE_CFG			BIT(5)
>>>> +#define GPIO20_FLASH_MODE_CFG			BIT(4)
>>>> +#define GPIO19_FLASH_MODE_CFG			BIT(3)
>>>> +#define GPIO18_FLASH_MODE_CFG			BIT(2)
>>>> +#define GPIO17_FLASH_MODE_CFG			BIT(1)
>>>> +#define GPIO16_FLASH_MODE_CFG			BIT(0)
>>>> +
>>>> +#define AIROHA_PINCTRL_GPIO(gpio, mux_val)			\
>>>> +	{							\
>>>> +		.name = (gpio),					\
>>>> +		.regmap[0] = {					\
>>>> +			AIROHA_FUNC_MUX,			\
>>>> +			REG_GPIO_PON_MODE,			\
>>>> +			(mux_val),				\
>>>> +			(mux_val)				\
>>>> +		},						\
>>>> +		.regmap_size = 1,				\
>>>> +	}
>>>> +
>>>> +#define AIROHA_PINCTRL_GPIO_EXT(gpio, mux_val, smux_val)	\
>>>> +	{							\
>>>> +		.name = (gpio),					\
>>>> +		.regmap[0] = {					\
>>>> +			AIROHA_FUNC_PWM_EXT_MUX,		\
>>>> +			REG_GPIO_FLASH_MODE_CFG_EXT,		\
>>>> +			(mux_val),				\
>>>> +			0					\
>>>> +		},						\
>>>> +		.regmap[1] = {					\
>>>> +			AIROHA_FUNC_MUX,			\
>>>> +			REG_GPIO_PON_MODE,			\
>>>> +			(smux_val),				\
>>>> +			(smux_val)				\
>>>> +		},						\
>>>> +		.regmap_size = 2,				\
>>>> +	}
>>>> +
>>>> +/* PWM */
>>>> +#define AIROHA_PINCTRL_PWM(gpio, mux_val)			\
>>>> +	{							\
>>>> +		.name = (gpio),					\
>>>> +		.regmap[0] = {					\
>>>> +			AIROHA_FUNC_PWM_MUX,			\
>>>> +			REG_GPIO_FLASH_MODE_CFG,		\
>>>> +			(mux_val),				\
>>>> +			(mux_val)				\
>>>> +		},						\
>>>> +		.regmap_size = 1,				\
>>>> +	}
>>>> +
>>>> +#define AIROHA_PINCTRL_PWM_EXT(gpio, mux_val)			\
>>>> +	{							\
>>>> +		.name = (gpio),					\
>>>> +		.regmap[0] = {					\
>>>> +			AIROHA_FUNC_PWM_EXT_MUX,		\
>>>> +			REG_GPIO_FLASH_MODE_CFG_EXT,		\
>>>> +			(mux_val),				\
>>>> +			(mux_val)				\
>>>> +		},						\
>>>> +		.regmap_size = 1,				\
>>>> +	}
>>>> +
>>>> +#define AIROHA_PINCTRL_PWM_EXT_SEC(gpio, mux_val, smux_val)	\
>>>> +	{							\
>>>> +		.name = (gpio),					\
>>>> +		.regmap[0] = {					\
>>>> +			AIROHA_FUNC_PWM_EXT_MUX,		\
>>>> +			REG_GPIO_FLASH_MODE_CFG_EXT,		\
>>>> +			(mux_val),				\
>>>> +			(mux_val)				\
>>>> +		},						\
>>>> +		.regmap[1] = {					\
>>>> +			AIROHA_FUNC_MUX,			\
>>>> +			REG_GPIO_PON_MODE,			\
>>>> +			(smux_val),				\
>>>> +			(smux_val)				\
>>>> +		},						\
>>>> +		.regmap_size = 2,				\
>>>> +	}
>>>> +
>>>> +#define AIROHA_PINCTRL_PHY_LED0(gpio, mux_val, map_mask, map_val)	\
>>>> +	{								\
>>>> +		.name = (gpio),						\
>>>> +		.regmap[0] = {						\
>>>> +			AIROHA_FUNC_MUX,				\
>>>> +			REG_GPIO_2ND_I2C_MODE,				\
>>>> +			(mux_val),					\
>>>> +			(mux_val),					\
>>>> +		},							\
>>>> +		.regmap[1] = {						\
>>>> +			AIROHA_FUNC_MUX,				\
>>>> +			REG_LAN_LED0_MAPPING,				\
>>>> +			(map_mask),					\
>>>> +			(map_val),					\
>>>> +		},							\
>>>> +		.regmap_size = 2,					\
>>>> +	}
>>>> +
>>>> +#define AIROHA_PINCTRL_PHY_LED1(gpio, mux_val, map_mask, map_val)	\
>>>> +	{								\
>>>> +		.name = (gpio),						\
>>>> +		.regmap[0] = {						\
>>>> +			AIROHA_FUNC_MUX,				\
>>>> +			REG_GPIO_2ND_I2C_MODE,				\
>>>> +			(mux_val),					\
>>>> +			(mux_val),					\
>>>> +		},							\
>>>> +		.regmap[1] = {						\
>>>> +			AIROHA_FUNC_MUX,				\
>>>> +			REG_LAN_LED1_MAPPING,				\
>>>> +			(map_mask),					\
>>>> +			(map_val),					\
>>>> +		},							\
>>>> +		.regmap_size = 2,					\
>>>> +	}
>>>> +
>>>> +static struct pinctrl_pin_desc en7581_pinctrl_pins[] = {
>>>> +	PINCTRL_PIN(0, "uart1_txd"),
>>>> +	PINCTRL_PIN(1, "uart1_rxd"),
>>>> +	PINCTRL_PIN(2, "i2c_scl"),
>>>> +	PINCTRL_PIN(3, "i2c_sda"),
>>>> +	PINCTRL_PIN(4, "spi_cs0"),
>>>> +	PINCTRL_PIN(5, "spi_clk"),
>>>> +	PINCTRL_PIN(6, "spi_mosi"),
>>>> +	PINCTRL_PIN(7, "spi_miso"),
>>>> +	PINCTRL_PIN(13, "gpio0"),
>>>> +	PINCTRL_PIN(14, "gpio1"),
>>>> +	PINCTRL_PIN(15, "gpio2"),
>>>> +	PINCTRL_PIN(16, "gpio3"),
>>>> +	PINCTRL_PIN(17, "gpio4"),
>>>> +	PINCTRL_PIN(18, "gpio5"),
>>>> +	PINCTRL_PIN(19, "gpio6"),
>>>> +	PINCTRL_PIN(20, "gpio7"),
>>>> +	PINCTRL_PIN(21, "gpio8"),
>>>> +	PINCTRL_PIN(22, "gpio9"),
>>>> +	PINCTRL_PIN(23, "gpio10"),
>>>> +	PINCTRL_PIN(24, "gpio11"),
>>>> +	PINCTRL_PIN(25, "gpio12"),
>>>> +	PINCTRL_PIN(26, "gpio13"),
>>>> +	PINCTRL_PIN(27, "gpio14"),
>>>> +	PINCTRL_PIN(28, "gpio15"),
>>>> +	PINCTRL_PIN(29, "gpio16"),
>>>> +	PINCTRL_PIN(30, "gpio17"),
>>>> +	PINCTRL_PIN(31, "gpio18"),
>>>> +	PINCTRL_PIN(32, "gpio19"),
>>>> +	PINCTRL_PIN(33, "gpio20"),
>>>> +	PINCTRL_PIN(34, "gpio21"),
>>>> +	PINCTRL_PIN(35, "gpio22"),
>>>> +	PINCTRL_PIN(36, "gpio23"),
>>>> +	PINCTRL_PIN(37, "gpio24"),
>>>> +	PINCTRL_PIN(38, "gpio25"),
>>>> +	PINCTRL_PIN(39, "gpio26"),
>>>> +	PINCTRL_PIN(40, "gpio27"),
>>>> +	PINCTRL_PIN(41, "gpio28"),
>>>> +	PINCTRL_PIN(42, "gpio29"),
>>>> +	PINCTRL_PIN(43, "gpio30"),
>>>> +	PINCTRL_PIN(44, "gpio31"),
>>>> +	PINCTRL_PIN(45, "gpio32"),
>>>> +	PINCTRL_PIN(46, "gpio33"),
>>>> +	PINCTRL_PIN(47, "gpio34"),
>>>> +	PINCTRL_PIN(48, "gpio35"),
>>>> +	PINCTRL_PIN(49, "gpio36"),
>>>> +	PINCTRL_PIN(50, "gpio37"),
>>>> +	PINCTRL_PIN(51, "gpio38"),
>>>> +	PINCTRL_PIN(52, "gpio39"),
>>>> +	PINCTRL_PIN(53, "gpio40"),
>>>> +	PINCTRL_PIN(54, "gpio41"),
>>>> +	PINCTRL_PIN(55, "gpio42"),
>>>> +	PINCTRL_PIN(56, "gpio43"),
>>>> +	PINCTRL_PIN(57, "gpio44"),
>>>> +	PINCTRL_PIN(58, "gpio45"),
>>>> +	PINCTRL_PIN(59, "gpio46"),
>>>> +	PINCTRL_PIN(60, "pcie_reset0"),
>>>> +	PINCTRL_PIN(61, "pcie_reset1"),
>>>> +	PINCTRL_PIN(62, "pcie_reset2"),
>>>> +};
>>>> +
>>>> +static const int en7581_pon_pins[] = { 49, 50, 51, 52, 53, 54 };
>>>> +static const int en7581_pon_tod_1pps_pins[] = { 46 };
>>>> +static const int en7581_gsw_tod_1pps_pins[] = { 46 };
>>>> +static const int en7581_sipo_pins[] = { 16, 17 };
>>>> +static const int en7581_sipo_rclk_pins[] = { 16, 17, 43 };
>>>> +static const int en7581_mdio_pins[] = { 14, 15 };
>>>> +static const int en7581_uart2_pins[] = { 48, 55 };
>>>> +static const int en7581_uart2_cts_rts_pins[] = { 46, 47 };
>>>> +static const int en7581_hsuart_pins[] = { 28, 29 };
>>>> +static const int en7581_hsuart_cts_rts_pins[] = { 26, 27 };
>>>> +static const int en7581_uart4_pins[] = { 38, 39 };
>>>> +static const int en7581_uart5_pins[] = { 18, 19 };
>>>> +static const int en7581_i2c0_pins[] = { 2, 3 };
>>>> +static const int en7581_i2c1_pins[] = { 14, 15 };
>>>> +static const int en7581_jtag_udi_pins[] = { 16, 17, 18, 19, 20 };
>>>> +static const int en7581_jtag_dfd_pins[] = { 16, 17, 18, 19, 20 };
>>>> +static const int en7581_i2s_pins[] = { 26, 27, 28, 29 };
>>>> +static const int en7581_pcm1_pins[] = { 22, 23, 24, 25 };
>>>> +static const int en7581_pcm2_pins[] = { 18, 19, 20, 21 };
>>>> +static const int en7581_spi_quad_pins[] = { 32, 33 };
>>>> +static const int en7581_spi_pins[] = { 4, 5, 6, 7 };
>>>> +static const int en7581_spi_cs1_pins[] = { 34 };
>>>> +static const int en7581_pcm_spi_pins[] = { 18, 19, 20, 21, 22, 23, 24, 25 };
>>>> +static const int en7581_pcm_spi_int_pins[] = { 14 };
>>>> +static const int en7581_pcm_spi_rst_pins[] = { 15 };
>>>> +static const int en7581_pcm_spi_cs1_pins[] = { 43 };
>>>> +static const int en7581_pcm_spi_cs2_pins[] = { 40 };
>>>> +static const int en7581_pcm_spi_cs2_p128_pins[] = { 40 };
>>>> +static const int en7581_pcm_spi_cs2_p156_pins[] = { 40 };
>>>> +static const int en7581_pcm_spi_cs3_pins[] = { 41 };
>>>> +static const int en7581_pcm_spi_cs4_pins[] = { 42 };
>>>> +static const int en7581_emmc_pins[] = {
>>>> +	4, 5, 6, 30, 31, 32, 33, 34, 35, 36, 37
>>>> +};
>>>> +static const int en7581_pnand_pins[] = {
>>>> +	4, 5, 6, 7, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42
>>>> +};
>>>> +static const int en7581_gpio0_pins[] = { 13 };
>>>> +static const int en7581_gpio1_pins[] = { 14 };
>>>> +static const int en7581_gpio2_pins[] = { 15 };
>>>> +static const int en7581_gpio3_pins[] = { 16 };
>>>> +static const int en7581_gpio4_pins[] = { 17 };
>>>> +static const int en7581_gpio5_pins[] = { 18 };
>>>> +static const int en7581_gpio6_pins[] = { 19 };
>>>> +static const int en7581_gpio7_pins[] = { 20 };
>>>> +static const int en7581_gpio8_pins[] = { 21 };
>>>> +static const int en7581_gpio9_pins[] = { 22 };
>>>> +static const int en7581_gpio10_pins[] = { 23 };
>>>> +static const int en7581_gpio11_pins[] = { 24 };
>>>> +static const int en7581_gpio12_pins[] = { 25 };
>>>> +static const int en7581_gpio13_pins[] = { 26 };
>>>> +static const int en7581_gpio14_pins[] = { 27 };
>>>> +static const int en7581_gpio15_pins[] = { 28 };
>>>> +static const int en7581_gpio16_pins[] = { 29 };
>>>> +static const int en7581_gpio17_pins[] = { 30 };
>>>> +static const int en7581_gpio18_pins[] = { 31 };
>>>> +static const int en7581_gpio19_pins[] = { 32 };
>>>> +static const int en7581_gpio20_pins[] = { 33 };
>>>> +static const int en7581_gpio21_pins[] = { 34 };
>>>> +static const int en7581_gpio22_pins[] = { 35 };
>>>> +static const int en7581_gpio23_pins[] = { 36 };
>>>> +static const int en7581_gpio24_pins[] = { 37 };
>>>> +static const int en7581_gpio25_pins[] = { 38 };
>>>> +static const int en7581_gpio26_pins[] = { 39 };
>>>> +static const int en7581_gpio27_pins[] = { 40 };
>>>> +static const int en7581_gpio28_pins[] = { 41 };
>>>> +static const int en7581_gpio29_pins[] = { 42 };
>>>> +static const int en7581_gpio30_pins[] = { 43 };
>>>> +static const int en7581_gpio31_pins[] = { 44 };
>>>> +static const int en7581_gpio32_pins[] = { 45 };
>>>> +static const int en7581_gpio33_pins[] = { 46 };
>>>> +static const int en7581_gpio34_pins[] = { 47 };
>>>> +static const int en7581_gpio35_pins[] = { 48 };
>>>> +static const int en7581_gpio36_pins[] = { 49 };
>>>> +static const int en7581_gpio37_pins[] = { 50 };
>>>> +static const int en7581_gpio38_pins[] = { 51 };
>>>> +static const int en7581_gpio39_pins[] = { 52 };
>>>> +static const int en7581_gpio40_pins[] = { 53 };
>>>> +static const int en7581_gpio41_pins[] = { 54 };
>>>> +static const int en7581_gpio42_pins[] = { 55 };
>>>> +static const int en7581_gpio43_pins[] = { 56 };
>>>> +static const int en7581_gpio44_pins[] = { 57 };
>>>> +static const int en7581_gpio45_pins[] = { 58 };
>>>> +static const int en7581_gpio46_pins[] = { 59 };
>>>> +static const int en7581_gpio47_pins[] = { 60 };
>>>> +static const int en7581_gpio48_pins[] = { 61 };
>>>> +static const int en7581_gpio49_pins[] = { 62 };
>>>> +static const int en7581_pcie_reset0_pins[] = { 60 };
>>>> +static const int en7581_pcie_reset1_pins[] = { 61 };
>>>> +static const int en7581_pcie_reset2_pins[] = { 62 };
>>>> +
>>>> +static const struct pingroup en7581_pinctrl_groups[] = {
>>>> +	PINCTRL_PIN_GROUP("pon", en7581_pon),
>>>> +	PINCTRL_PIN_GROUP("pon_tod_1pps", en7581_pon_tod_1pps),
>>>> +	PINCTRL_PIN_GROUP("gsw_tod_1pps", en7581_gsw_tod_1pps),
>>>> +	PINCTRL_PIN_GROUP("sipo", en7581_sipo),
>>>> +	PINCTRL_PIN_GROUP("sipo_rclk", en7581_sipo_rclk),
>>>> +	PINCTRL_PIN_GROUP("mdio", en7581_mdio),
>>>> +	PINCTRL_PIN_GROUP("uart2", en7581_uart2),
>>>> +	PINCTRL_PIN_GROUP("uart2_cts_rts", en7581_uart2_cts_rts),
>>>> +	PINCTRL_PIN_GROUP("hsuart", en7581_hsuart),
>>>> +	PINCTRL_PIN_GROUP("hsuart_cts_rts", en7581_hsuart_cts_rts),
>>>> +	PINCTRL_PIN_GROUP("uart4", en7581_uart4),
>>>> +	PINCTRL_PIN_GROUP("uart5", en7581_uart5),
>>>> +	PINCTRL_PIN_GROUP("i2c0", en7581_i2c0),
>>>> +	PINCTRL_PIN_GROUP("i2c1", en7581_i2c1),
>>>> +	PINCTRL_PIN_GROUP("jtag_udi", en7581_jtag_udi),
>>>> +	PINCTRL_PIN_GROUP("jtag_dfd", en7581_jtag_dfd),
>>>> +	PINCTRL_PIN_GROUP("i2s", en7581_i2s),
>>>> +	PINCTRL_PIN_GROUP("pcm1", en7581_pcm1),
>>>> +	PINCTRL_PIN_GROUP("pcm2", en7581_pcm2),
>>>> +	PINCTRL_PIN_GROUP("spi", en7581_spi),
>>>> +	PINCTRL_PIN_GROUP("spi_quad", en7581_spi_quad),
>>>> +	PINCTRL_PIN_GROUP("spi_cs1", en7581_spi_cs1),
>>>> +	PINCTRL_PIN_GROUP("pcm_spi", en7581_pcm_spi),
>>>> +	PINCTRL_PIN_GROUP("pcm_spi_int", en7581_pcm_spi_int),
>>>> +	PINCTRL_PIN_GROUP("pcm_spi_rst", en7581_pcm_spi_rst),
>>>> +	PINCTRL_PIN_GROUP("pcm_spi_cs1", en7581_pcm_spi_cs1),
>>>> +	PINCTRL_PIN_GROUP("pcm_spi_cs2_p128", en7581_pcm_spi_cs2_p128),
>>>> +	PINCTRL_PIN_GROUP("pcm_spi_cs2_p156", en7581_pcm_spi_cs2_p156),
>>>> +	PINCTRL_PIN_GROUP("pcm_spi_cs2", en7581_pcm_spi_cs2),
>>>> +	PINCTRL_PIN_GROUP("pcm_spi_cs3", en7581_pcm_spi_cs3),
>>>> +	PINCTRL_PIN_GROUP("pcm_spi_cs4", en7581_pcm_spi_cs4),
>>>> +	PINCTRL_PIN_GROUP("emmc", en7581_emmc),
>>>> +	PINCTRL_PIN_GROUP("pnand", en7581_pnand),
>>>> +	PINCTRL_PIN_GROUP("gpio0", en7581_gpio0),
>>>> +	PINCTRL_PIN_GROUP("gpio1", en7581_gpio1),
>>>> +	PINCTRL_PIN_GROUP("gpio2", en7581_gpio2),
>>>> +	PINCTRL_PIN_GROUP("gpio3", en7581_gpio3),
>>>> +	PINCTRL_PIN_GROUP("gpio4", en7581_gpio4),
>>>> +	PINCTRL_PIN_GROUP("gpio5", en7581_gpio5),
>>>> +	PINCTRL_PIN_GROUP("gpio6", en7581_gpio6),
>>>> +	PINCTRL_PIN_GROUP("gpio7", en7581_gpio7),
>>>> +	PINCTRL_PIN_GROUP("gpio8", en7581_gpio8),
>>>> +	PINCTRL_PIN_GROUP("gpio9", en7581_gpio9),
>>>> +	PINCTRL_PIN_GROUP("gpio10", en7581_gpio10),
>>>> +	PINCTRL_PIN_GROUP("gpio11", en7581_gpio11),
>>>> +	PINCTRL_PIN_GROUP("gpio12", en7581_gpio12),
>>>> +	PINCTRL_PIN_GROUP("gpio13", en7581_gpio13),
>>>> +	PINCTRL_PIN_GROUP("gpio14", en7581_gpio14),
>>>> +	PINCTRL_PIN_GROUP("gpio15", en7581_gpio15),
>>>> +	PINCTRL_PIN_GROUP("gpio16", en7581_gpio16),
>>>> +	PINCTRL_PIN_GROUP("gpio17", en7581_gpio17),
>>>> +	PINCTRL_PIN_GROUP("gpio18", en7581_gpio18),
>>>> +	PINCTRL_PIN_GROUP("gpio19", en7581_gpio19),
>>>> +	PINCTRL_PIN_GROUP("gpio20", en7581_gpio20),
>>>> +	PINCTRL_PIN_GROUP("gpio21", en7581_gpio21),
>>>> +	PINCTRL_PIN_GROUP("gpio22", en7581_gpio22),
>>>> +	PINCTRL_PIN_GROUP("gpio23", en7581_gpio23),
>>>> +	PINCTRL_PIN_GROUP("gpio24", en7581_gpio24),
>>>> +	PINCTRL_PIN_GROUP("gpio25", en7581_gpio25),
>>>> +	PINCTRL_PIN_GROUP("gpio26", en7581_gpio26),
>>>> +	PINCTRL_PIN_GROUP("gpio27", en7581_gpio27),
>>>> +	PINCTRL_PIN_GROUP("gpio28", en7581_gpio28),
>>>> +	PINCTRL_PIN_GROUP("gpio29", en7581_gpio29),
>>>> +	PINCTRL_PIN_GROUP("gpio30", en7581_gpio30),
>>>> +	PINCTRL_PIN_GROUP("gpio31", en7581_gpio31),
>>>> +	PINCTRL_PIN_GROUP("gpio32", en7581_gpio32),
>>>> +	PINCTRL_PIN_GROUP("gpio33", en7581_gpio33),
>>>> +	PINCTRL_PIN_GROUP("gpio34", en7581_gpio34),
>>>> +	PINCTRL_PIN_GROUP("gpio35", en7581_gpio35),
>>>> +	PINCTRL_PIN_GROUP("gpio36", en7581_gpio36),
>>>> +	PINCTRL_PIN_GROUP("gpio37", en7581_gpio37),
>>>> +	PINCTRL_PIN_GROUP("gpio38", en7581_gpio38),
>>>> +	PINCTRL_PIN_GROUP("gpio39", en7581_gpio39),
>>>> +	PINCTRL_PIN_GROUP("gpio40", en7581_gpio40),
>>>> +	PINCTRL_PIN_GROUP("gpio41", en7581_gpio41),
>>>> +	PINCTRL_PIN_GROUP("gpio42", en7581_gpio42),
>>>> +	PINCTRL_PIN_GROUP("gpio43", en7581_gpio43),
>>>> +	PINCTRL_PIN_GROUP("gpio44", en7581_gpio44),
>>>> +	PINCTRL_PIN_GROUP("gpio45", en7581_gpio45),
>>>> +	PINCTRL_PIN_GROUP("gpio46", en7581_gpio46),
>>>> +	PINCTRL_PIN_GROUP("gpio47", en7581_gpio47),
>>>> +	PINCTRL_PIN_GROUP("gpio48", en7581_gpio48),
>>>> +	PINCTRL_PIN_GROUP("gpio49", en7581_gpio49),
>>>> +	PINCTRL_PIN_GROUP("pcie_reset0", en7581_pcie_reset0),
>>>> +	PINCTRL_PIN_GROUP("pcie_reset1", en7581_pcie_reset1),
>>>> +	PINCTRL_PIN_GROUP("pcie_reset2", en7581_pcie_reset2),
>>>> +};
>>>> +
>>>> +static const char *const pon_groups[] = { "pon" };
>>>> +static const char *const tod_1pps_groups[] = {
>>>> +	"pon_tod_1pps", "gsw_tod_1pps"
>>>> +};
>>>> +static const char *const sipo_groups[] = { "sipo", "sipo_rclk" };
>>>> +static const char *const mdio_groups[] = { "mdio" };
>>>> +static const char *const uart_groups[] = {
>>>> +	"uart2", "uart2_cts_rts", "hsuart", "hsuart_cts_rts",
>>>> +	"uart4", "uart5"
>>>> +};
>>>> +static const char *const i2c_groups[] = { "i2c1" };
>>>> +static const char *const jtag_groups[] = { "jtag_udi", "jtag_dfd" };
>>>> +static const char *const pcm_groups[] = { "pcm1", "pcm2" };
>>>> +static const char *const spi_groups[] = { "spi_quad", "spi_cs1" };
>>>> +static const char *const pcm_spi_groups[] = {
>>>> +	"pcm_spi", "pcm_spi_int", "pcm_spi_rst", "pcm_spi_cs1",
>>>> +	"pcm_spi_cs2_p156", "pcm_spi_cs2_p128", "pcm_spi_cs3",
>>>> +	"pcm_spi_cs4"
>>>> +};
>>>> +static const char *const i2s_groups[] = { "i2s" };
>>>> +static const char *const emmc_groups[] = { "emmc" };
>>>> +static const char *const pnand_groups[] = { "pnand" };
>>>> +static const char *const gpio_groups[] = { "gpio47", "gpio48", "gpio49" };
>>>> +static const char *const pcie_reset_groups[] = {
>>>> +	"pcie_reset0", "pcie_reset1", "pcie_reset2"
>>>> +};
>>>> +static const char *const pwm_groups[] = {
>>>> +	"gpio0",  "gpio1",  "gpio2",  "gpio3",  "gpio4",  "gpio5",
>>>> +	"gpio6",  "gpio7",  "gpio8",  "gpio9",  "gpio10", "gpio11",
>>>> +	"gpio12", "gpio13", "gpio14", "gpio15", "gpio16", "gpio17",
>>>> +	"gpio18", "gpio19", "gpio20", "gpio21", "gpio22", "gpio23",
>>>> +	"gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29",
>>>> +	"gpio30", "gpio31", "gpio36", "gpio37", "gpio38", "gpio39",
>>>> +	"gpio40", "gpio41", "gpio42", "gpio43", "gpio44", "gpio45",
>>>> +	"gpio46", "gpio47", "gpio48", "gpio49"
>>>> +};
>>>> +static const char *const phy1_led0_groups[] = {
>>>> +	"gpio33", "gpio34", "gpio35", "gpio42"
>>>> +};
>>>> +static const char *const phy2_led0_groups[] = {
>>>> +	"gpio33", "gpio34", "gpio35", "gpio42"
>>>> +};
>>>> +static const char *const phy3_led0_groups[] = {
>>>> +	"gpio33", "gpio34", "gpio35", "gpio42"
>>>> +};
>>>> +static const char *const phy4_led0_groups[] = {
>>>> +	"gpio33", "gpio34", "gpio35", "gpio42"
>>>> +};
>>>> +static const char *const phy1_led1_groups[] = {
>>>> +	"gpio43", "gpio44", "gpio45", "gpio46"
>>>> +};
>>>> +static const char *const phy2_led1_groups[] = {
>>>> +	"gpio43", "gpio44", "gpio45", "gpio46"
>>>> +};
>>>> +static const char *const phy3_led1_groups[] = {
>>>> +	"gpio43", "gpio44", "gpio45", "gpio46"
>>>> +};
>>>> +static const char *const phy4_led1_groups[] = {
>>>> +	"gpio43", "gpio44", "gpio45", "gpio46"
>>>> +};
>>>> +
>>>> +static const struct airoha_pinctrl_func_group pon_func_group[] = {
>>>> +	{
>>>> +		.name = "pon",
>>>> +		.regmap[0] = {
>>>> +			AIROHA_FUNC_MUX,
>>>> +			REG_GPIO_PON_MODE,
>>>> +			GPIO_PON_MODE_MASK,
>>>> +			GPIO_PON_MODE_MASK
>>>> +		},
>>>> +		.regmap_size = 1,
>>>> +	},
>>>> +};
>>>> +
>>>> +static const struct airoha_pinctrl_func_group tod_1pps_func_group[] = {
>>>> +	{
>>>> +		.name = "pon_tod_1pps",
>>>> +		.regmap[0] = {
>>>> +			AIROHA_FUNC_MUX,
>>>> +			REG_GPIO_2ND_I2C_MODE,
>>>> +			PON_TOD_1PPS_MODE_MASK,
>>>> +			PON_TOD_1PPS_MODE_MASK
>>>> +		},
>>>> +		.regmap_size = 1,
>>>> +	}, {
>>>> +		.name = "gsw_tod_1pps",
>>>> +		.regmap[0] = {
>>>> +			AIROHA_FUNC_MUX,
>>>> +			REG_GPIO_2ND_I2C_MODE,
>>>> +			GSW_TOD_1PPS_MODE_MASK,
>>>> +			GSW_TOD_1PPS_MODE_MASK
>>>> +		},
>>>> +		.regmap_size = 1,
>>>> +	},
>>>> +};
>>>> +
>>>> +static const struct airoha_pinctrl_func_group sipo_func_group[] = {
>>>> +	{
>>>> +		.name = "sipo",
>>>> +		.regmap[0] = {
>>>> +			AIROHA_FUNC_MUX,
>>>> +			REG_GPIO_PON_MODE,
>>>> +			GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK,
>>>> +			GPIO_SIPO_MODE_MASK
>>>> +		},
>>>> +		.regmap_size = 1,
>>>> +	}, {
>>>> +		.name = "sipo_rclk",
>>>> +		.regmap[0] = {
>>>> +			AIROHA_FUNC_MUX,
>>>> +			REG_GPIO_PON_MODE,
>>>> +			GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK,
>>>> +			GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK
>>>> +		},
>>>> +		.regmap_size = 1,
>>>> +	},
>>>> +};
>>>> +
>>>> +static const struct airoha_pinctrl_func_group mdio_func_group[] = {
>>>> +	{
>>>> +		.name = "mdio",
>>>> +		.regmap[0] = {
>>>> +			AIROHA_FUNC_MUX,
>>>> +			REG_GPIO_2ND_I2C_MODE,
>>>> +			GPIO_MDC_IO_MASTER_MODE_MASK,
>>>> +			GPIO_MDC_IO_MASTER_MODE_MASK
>>>> +		},
>>>> +		.regmap[1] = {
>>>> +			AIROHA_FUNC_MUX,
>>>> +			REG_FORCE_GPIO_EN,
>>>> +			FORCE_GPIO_EN(1) | FORCE_GPIO_EN(2),
>>>> +			FORCE_GPIO_EN(1) | FORCE_GPIO_EN(2)
>>>> +		},
>>>> +		.regmap_size = 2,
>>>> +	},
>>>> +};
>>>> +
>>>> +static const struct airoha_pinctrl_func_group uart_func_group[] = {
>>>> +	{
>>>> +		.name = "uart2",
>>>> +		.regmap[0] = {
>>>> +			AIROHA_FUNC_MUX,
>>>> +			REG_GPIO_PON_MODE,
>>>> +			GPIO_UART2_MODE_MASK,
>>>> +			GPIO_UART2_MODE_MASK
>>>> +		},
>>>> +		.regmap_size = 1,
>>>> +	}, {
>>>> +		.name = "uart2_cts_rts",
>>>> +		.regmap[0] = {
>>>> +			AIROHA_FUNC_MUX,
>>>> +			REG_GPIO_PON_MODE,
>>>> +			GPIO_UART2_MODE_MASK | GPIO_UART2_CTS_RTS_MODE_MASK,
>>>> +			GPIO_UART2_MODE_MASK | GPIO_UART2_CTS_RTS_MODE_MASK
>>>> +		},
>>>> +		.regmap_size = 1,
>>>> +	}, {
>>>> +		.name = "hsuart",
>>>> +		.regmap[0] = {
>>>> +			AIROHA_FUNC_MUX,
>>>> +			REG_GPIO_PON_MODE,
>>>> +			GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK,
>>>> +			GPIO_HSUART_MODE_MASK
>>>> +		},
>>>> +		.regmap_size = 1,
>>>> +	},
>>>> +	{
>>>> +		.name = "hsuart_cts_rts",
>>>> +		.regmap[0] = {
>>>> +			AIROHA_FUNC_MUX,
>>>> +			REG_GPIO_PON_MODE,
>>>> +			GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK,
>>>> +			GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK
>>>> +		},
>>>> +		.regmap_size = 1,
>>>> +	}, {
>>>> +		.name = "uart4",
>>>> +		.regmap[0] = {
>>>> +			AIROHA_FUNC_MUX,
>>>> +			REG_GPIO_PON_MODE,
>>>> +			GPIO_UART4_MODE_MASK,
>>>> +			GPIO_UART4_MODE_MASK
>>>> +		},
>>>> +		.regmap_size = 1,
>>>> +	}, {
>>>> +		.name = "uart5",
>>>> +		.regmap[0] = {
>>>> +			AIROHA_FUNC_MUX,
>>>> +			REG_GPIO_PON_MODE,
>>>> +			GPIO_UART5_MODE_MASK,
>>>> +			GPIO_UART5_MODE_MASK
>>>> +		},
>>>> +		.regmap_size = 1,
>>>> +	},
>>>> +};
>>>> +
>>>> +static const struct airoha_pinctrl_func_group i2c_func_group[] = {
>>>> +	{
>>>> +		.name = "i2c1",
>>>> +		.regmap[0] = {
>>>> +			AIROHA_FUNC_MUX,
>>>> +			REG_GPIO_2ND_I2C_MODE,
>>>> +			GPIO_2ND_I2C_MODE_MASK,
>>>> +			GPIO_2ND_I2C_MODE_MASK
>>>> +		},
>>>> +		.regmap_size = 1,
>>>> +	},
>>>> +};
>>>> +
>>>> +static const struct airoha_pinctrl_func_group jtag_func_group[] = {
>>>> +	{
>>>> +		.name = "jtag_udi",
>>>> +		.regmap[0] = {
>>>> +			AIROHA_FUNC_MUX,
>>>> +			REG_NPU_UART_EN,
>>>> +			JTAG_UDI_EN_MASK,
>>>> +			JTAG_UDI_EN_MASK
>>>> +		},
>>>> +		.regmap_size = 1,
>>>> +	}, {
>>>> +		.name = "jtag_dfd",
>>>> +		.regmap[0] = {
>>>> +			AIROHA_FUNC_MUX,
>>>> +			REG_NPU_UART_EN,
>>>> +			JTAG_DFD_EN_MASK,
>>>> +			JTAG_DFD_EN_MASK
>>>> +		},
>>>> +		.regmap_size = 1,
>>>> +	},
>>>> +};
>>>> +
>>>> +static const struct airoha_pinctrl_func_group pcm_func_group[] = {
>>>> +	{
>>>> +		.name = "pcm1",
>>>> +		.regmap[0] = {
>>>> +			AIROHA_FUNC_MUX,
>>>> +			REG_GPIO_SPI_CS1_MODE,
>>>> +			GPIO_PCM1_MODE_MASK,
>>>> +			GPIO_PCM1_MODE_MASK
>>>> +		},
>>>> +		.regmap_size = 1,
>>>> +	}, {
>>>> +		.name = "pcm2",
>>>> +		.regmap[0] = {
>>>> +			AIROHA_FUNC_MUX,
>>>> +			REG_GPIO_SPI_CS1_MODE,
>>>> +			GPIO_PCM2_MODE_MASK,
>>>> +			GPIO_PCM2_MODE_MASK
>>>> +		},
>>>> +		.regmap_size = 1,
>>>> +	},
>>>> +};
>>>> +
>>>> +static const struct airoha_pinctrl_func_group spi_func_group[] = {
>>>> +	{
>>>> +		.name = "spi_quad",
>>>> +		.regmap[0] = {
>>>> +			AIROHA_FUNC_MUX,
>>>> +			REG_GPIO_SPI_CS1_MODE,
>>>> +			GPIO_SPI_QUAD_MODE_MASK,
>>>> +			GPIO_SPI_QUAD_MODE_MASK
>>>> +		},
>>>> +		.regmap_size = 1,
>>>> +	}, {
>>>> +		.name = "spi_cs1",
>>>> +		.regmap[0] = {
>>>> +			AIROHA_FUNC_MUX,
>>>> +			REG_GPIO_SPI_CS1_MODE,
>>>> +			GPIO_SPI_CS1_MODE_MASK,
>>>> +			GPIO_SPI_CS1_MODE_MASK
>>>> +		},
>>>> +		.regmap_size = 1,
>>>> +	}, {
>>>> +		.name = "spi_cs2",
>>>> +		.regmap[0] = {
>>>> +			AIROHA_FUNC_MUX,
>>>> +			REG_GPIO_SPI_CS1_MODE,
>>>> +			GPIO_SPI_CS2_MODE_MASK,
>>>> +			GPIO_SPI_CS2_MODE_MASK
>>>> +		},
>>>> +		.regmap_size = 1,
>>>> +	}, {
>>>> +		.name = "spi_cs3",
>>>> +		.regmap[0] = {
>>>> +			AIROHA_FUNC_MUX,
>>>> +			REG_GPIO_SPI_CS1_MODE,
>>>> +			GPIO_SPI_CS3_MODE_MASK,
>>>> +			GPIO_SPI_CS3_MODE_MASK
>>>> +		},
>>>> +		.regmap_size = 1,
>>>> +	}, {
>>>> +		.name = "spi_cs4",
>>>> +		.regmap[0] = {
>>>> +			AIROHA_FUNC_MUX,
>>>> +			REG_GPIO_SPI_CS1_MODE,
>>>> +			GPIO_SPI_CS4_MODE_MASK,
>>>> +			GPIO_SPI_CS4_MODE_MASK
>>>> +		},
>>>> +		.regmap_size = 1,
>>>> +	},
>>>> +};
>>>> +
>>>> +static const struct airoha_pinctrl_func_group pcm_spi_func_group[] = {
>>>> +	{
>>>> +		.name = "pcm_spi",
>>>> +		.regmap[0] = {
>>>> +			AIROHA_FUNC_MUX,
>>>> +			REG_GPIO_SPI_CS1_MODE,
>>>> +			GPIO_PCM_SPI_MODE_MASK,
>>>> +			GPIO_PCM_SPI_MODE_MASK
>>>> +		},
>>>> +		.regmap_size = 1,
>>>> +	}, {
>>>> +		.name = "pcm_spi_int",
>>>> +		.regmap[0] = {
>>>> +			AIROHA_FUNC_MUX,
>>>> +			REG_GPIO_SPI_CS1_MODE,
>>>> +			GPIO_PCM_INT_MODE_MASK,
>>>> +			GPIO_PCM_INT_MODE_MASK
>>>> +		},
>>>> +		.regmap_size = 1,
>>>> +	}, {
>>>> +		.name = "pcm_spi_rst",
>>>> +		.regmap[0] = {
>>>> +			AIROHA_FUNC_MUX,
>>>> +			REG_GPIO_SPI_CS1_MODE,
>>>> +			GPIO_PCM_RESET_MODE_MASK,
>>>> +			GPIO_PCM_RESET_MODE_MASK
>>>> +		},
>>>> +		.regmap_size = 1,
>>>> +	}, {
>>>> +		.name = "pcm_spi_cs1",
>>>> +		.regmap[0] = {
>>>> +			AIROHA_FUNC_MUX,
>>>> +			REG_GPIO_SPI_CS1_MODE,
>>>> +			GPIO_PCM_SPI_CS1_MODE_MASK,
>>>> +			GPIO_PCM_SPI_CS1_MODE_MASK
>>>> +		},
>>>> +		.regmap_size = 1,
>>>> +	}, {
>>>> +		.name = "pcm_spi_cs2_p128",
>>>> +		.regmap[0] = {
>>>> +			AIROHA_FUNC_MUX,
>>>> +			REG_GPIO_SPI_CS1_MODE,
>>>> +			GPIO_PCM_SPI_CS2_MODE_P128_MASK,
>>>> +			GPIO_PCM_SPI_CS2_MODE_P128_MASK
>>>> +		},
>>>> +		.regmap_size = 1,
>>>> +	}, {
>>>> +		.name = "pcm_spi_cs2_p156",
>>>> +		.regmap[0] = {
>>>> +			AIROHA_FUNC_MUX,
>>>> +			REG_GPIO_SPI_CS1_MODE,
>>>> +			GPIO_PCM_SPI_CS2_MODE_P156_MASK,
>>>> +			GPIO_PCM_SPI_CS2_MODE_P156_MASK
>>>> +		},
>>>> +		.regmap_size = 1,
>>>> +	}, {
>>>> +		.name = "pcm_spi_cs3",
>>>> +		.regmap[0] = {
>>>> +			AIROHA_FUNC_MUX,
>>>> +			REG_GPIO_SPI_CS1_MODE,
>>>> +			GPIO_PCM_SPI_CS3_MODE_MASK,
>>>> +			GPIO_PCM_SPI_CS3_MODE_MASK
>>>> +		},
>>>> +		.regmap_size = 1,
>>>> +	}, {
>>>> +		.name = "pcm_spi_cs4",
>>>> +		.regmap[0] = {
>>>> +			AIROHA_FUNC_MUX,
>>>> +			REG_GPIO_SPI_CS1_MODE,
>>>> +			GPIO_PCM_SPI_CS4_MODE_MASK,
>>>> +			GPIO_PCM_SPI_CS4_MODE_MASK
>>>> +		},
>>>> +		.regmap_size = 1,
>>>> +	},
>>>> +};
>>>> +
>>>> +static const struct airoha_pinctrl_func_group i2s_func_group[] = {
>>>> +	{
>>>> +		.name = "i2s",
>>>> +		.regmap[0] = {
>>>> +			AIROHA_FUNC_MUX,
>>>> +			REG_GPIO_2ND_I2C_MODE,
>>>> +			GPIO_I2S_MODE_MASK,
>>>> +			GPIO_I2S_MODE_MASK
>>>> +		},
>>>> +		.regmap_size = 1,
>>>> +	},
>>>> +};
>>>> +
>>>> +static const struct airoha_pinctrl_func_group emmc_func_group[] = {
>>>> +	{
>>>> +		.name = "emmc",
>>>> +		.regmap[0] = {
>>>> +			AIROHA_FUNC_MUX,
>>>> +			REG_GPIO_PON_MODE,
>>>> +			GPIO_EMMC_MODE_MASK,
>>>> +			GPIO_EMMC_MODE_MASK
>>>> +		},
>>>> +		.regmap_size = 1,
>>>> +	},
>>>> +};
>>>> +
>>>> +static const struct airoha_pinctrl_func_group pnand_func_group[] = {
>>>> +	{
>>>> +		.name = "pnand",
>>>> +		.regmap[0] = {
>>>> +			AIROHA_FUNC_MUX,
>>>> +			REG_GPIO_PON_MODE,
>>>> +			GPIO_PARALLEL_NAND_MODE_MASK,
>>>> +			GPIO_PARALLEL_NAND_MODE_MASK
>>>> +		},
>>>> +		.regmap_size = 1,
>>>> +	},
>>>> +};
>>>> +
>>>> +static const struct airoha_pinctrl_func_group gpio_func_group[] = {
>>>> +	AIROHA_PINCTRL_GPIO_EXT("gpio47", GPIO47_FLASH_MODE_CFG,
>>>> +				GPIO_PCIE_RESET0_MASK),
>>>> +	AIROHA_PINCTRL_GPIO_EXT("gpio48", GPIO48_FLASH_MODE_CFG,
>>>> +				GPIO_PCIE_RESET1_MASK),
>>>> +	AIROHA_PINCTRL_GPIO_EXT("gpio49", GPIO49_FLASH_MODE_CFG,
>>>> +				GPIO_PCIE_RESET2_MASK),
>>>> +};
>>>> +
>>>> +static const struct airoha_pinctrl_func_group pcie_reset_func_group[] = {
>>>> +	{
>>>> +		.name = "pcie_reset0",
>>>> +		.regmap[0] = {
>>>> +			AIROHA_FUNC_MUX,
>>>> +			REG_GPIO_PON_MODE,
>>>> +			GPIO_PCIE_RESET0_MASK,
>>>> +			0
>>>> +		},
>>>> +		.regmap_size = 1,
>>>> +	}, {
>>>> +		.name = "pcie_reset1",
>>>> +		.regmap[0] = {
>>>> +			AIROHA_FUNC_MUX,
>>>> +			REG_GPIO_PON_MODE,
>>>> +			GPIO_PCIE_RESET1_MASK,
>>>> +			0
>>>> +		},
>>>> +		.regmap_size = 1,
>>>> +	}, {
>>>> +		.name = "pcie_reset2",
>>>> +		.regmap[0] = {
>>>> +			AIROHA_FUNC_MUX,
>>>> +			REG_GPIO_PON_MODE,
>>>> +			GPIO_PCIE_RESET2_MASK,
>>>> +			0
>>>> +		},
>>>> +		.regmap_size = 1,
>>>> +	},
>>>> +};
>>>> +
>>>> +static const struct airoha_pinctrl_func_group pwm_func_group[] = {
>>>> +	AIROHA_PINCTRL_PWM("gpio0", GPIO0_FLASH_MODE_CFG),
>>>> +	AIROHA_PINCTRL_PWM("gpio1", GPIO1_FLASH_MODE_CFG),
>>>> +	AIROHA_PINCTRL_PWM("gpio2", GPIO2_FLASH_MODE_CFG),
>>>> +	AIROHA_PINCTRL_PWM("gpio3", GPIO3_FLASH_MODE_CFG),
>>>> +	AIROHA_PINCTRL_PWM("gpio4", GPIO4_FLASH_MODE_CFG),
>>>> +	AIROHA_PINCTRL_PWM("gpio5", GPIO5_FLASH_MODE_CFG),
>>>> +	AIROHA_PINCTRL_PWM("gpio6", GPIO6_FLASH_MODE_CFG),
>>>> +	AIROHA_PINCTRL_PWM("gpio7", GPIO7_FLASH_MODE_CFG),
>>>> +	AIROHA_PINCTRL_PWM("gpio8", GPIO8_FLASH_MODE_CFG),
>>>> +	AIROHA_PINCTRL_PWM("gpio9", GPIO9_FLASH_MODE_CFG),
>>>> +	AIROHA_PINCTRL_PWM("gpio10", GPIO10_FLASH_MODE_CFG),
>>>> +	AIROHA_PINCTRL_PWM("gpio11", GPIO11_FLASH_MODE_CFG),
>>>> +	AIROHA_PINCTRL_PWM("gpio12", GPIO12_FLASH_MODE_CFG),
>>>> +	AIROHA_PINCTRL_PWM("gpio13", GPIO13_FLASH_MODE_CFG),
>>>> +	AIROHA_PINCTRL_PWM("gpio14", GPIO14_FLASH_MODE_CFG),
>>>> +	AIROHA_PINCTRL_PWM("gpio15", GPIO15_FLASH_MODE_CFG),
>>>> +	AIROHA_PINCTRL_PWM_EXT("gpio16", GPIO16_FLASH_MODE_CFG),
>>>> +	AIROHA_PINCTRL_PWM_EXT("gpio17", GPIO17_FLASH_MODE_CFG),
>>>> +	AIROHA_PINCTRL_PWM_EXT("gpio18", GPIO18_FLASH_MODE_CFG),
>>>> +	AIROHA_PINCTRL_PWM_EXT("gpio19", GPIO19_FLASH_MODE_CFG),
>>>> +	AIROHA_PINCTRL_PWM_EXT("gpio20", GPIO20_FLASH_MODE_CFG),
>>>> +	AIROHA_PINCTRL_PWM_EXT("gpio21", GPIO21_FLASH_MODE_CFG),
>>>> +	AIROHA_PINCTRL_PWM_EXT("gpio22", GPIO22_FLASH_MODE_CFG),
>>>> +	AIROHA_PINCTRL_PWM_EXT("gpio23", GPIO23_FLASH_MODE_CFG),
>>>> +	AIROHA_PINCTRL_PWM_EXT("gpio24", GPIO24_FLASH_MODE_CFG),
>>>> +	AIROHA_PINCTRL_PWM_EXT("gpio25", GPIO25_FLASH_MODE_CFG),
>>>> +	AIROHA_PINCTRL_PWM_EXT("gpio26", GPIO26_FLASH_MODE_CFG),
>>>> +	AIROHA_PINCTRL_PWM_EXT("gpio27", GPIO27_FLASH_MODE_CFG),
>>>> +	AIROHA_PINCTRL_PWM_EXT("gpio28", GPIO28_FLASH_MODE_CFG),
>>>> +	AIROHA_PINCTRL_PWM_EXT("gpio29", GPIO29_FLASH_MODE_CFG),
>>>> +	AIROHA_PINCTRL_PWM_EXT("gpio30", GPIO30_FLASH_MODE_CFG),
>>>> +	AIROHA_PINCTRL_PWM_EXT("gpio31", GPIO31_FLASH_MODE_CFG),
>>>> +	AIROHA_PINCTRL_PWM_EXT("gpio36", GPIO36_FLASH_MODE_CFG),
>>>> +	AIROHA_PINCTRL_PWM_EXT("gpio37", GPIO37_FLASH_MODE_CFG),
>>>> +	AIROHA_PINCTRL_PWM_EXT("gpio38", GPIO38_FLASH_MODE_CFG),
>>>> +	AIROHA_PINCTRL_PWM_EXT("gpio39", GPIO39_FLASH_MODE_CFG),
>>>> +	AIROHA_PINCTRL_PWM_EXT("gpio40", GPIO40_FLASH_MODE_CFG),
>>>> +	AIROHA_PINCTRL_PWM_EXT("gpio41", GPIO41_FLASH_MODE_CFG),
>>>> +	AIROHA_PINCTRL_PWM_EXT("gpio42", GPIO42_FLASH_MODE_CFG),
>>>> +	AIROHA_PINCTRL_PWM_EXT("gpio43", GPIO43_FLASH_MODE_CFG),
>>>> +	AIROHA_PINCTRL_PWM_EXT("gpio44", GPIO44_FLASH_MODE_CFG),
>>>> +	AIROHA_PINCTRL_PWM_EXT("gpio45", GPIO45_FLASH_MODE_CFG),
>>>> +	AIROHA_PINCTRL_PWM_EXT("gpio46", GPIO46_FLASH_MODE_CFG),
>>>> +	AIROHA_PINCTRL_PWM_EXT_SEC("gpio47", GPIO47_FLASH_MODE_CFG,
>>>> +				   GPIO_PCIE_RESET0_MASK),
>>>> +	AIROHA_PINCTRL_PWM_EXT_SEC("gpio48", GPIO48_FLASH_MODE_CFG,
>>>> +				   GPIO_PCIE_RESET1_MASK),
>>>> +	AIROHA_PINCTRL_PWM_EXT_SEC("gpio49", GPIO49_FLASH_MODE_CFG,
>>>> +				   GPIO_PCIE_RESET2_MASK),
>>>> +};
>>>> +
>>>> +static const struct airoha_pinctrl_func_group phy1_led0_func_group[] = {
>>>> +	AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK,
>>>> +				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),
>>>> +	AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK,
>>>> +				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)),
>>>> +	AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK,
>>>> +				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)),
>>>> +	AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK,
>>>> +				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),
>>>> +};
>>>> +
>>>> +static const struct airoha_pinctrl_func_group phy2_led0_func_group[] = {
>>>> +	AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK,
>>>> +				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),
>>>> +	AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK,
>>>> +				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)),
>>>> +	AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK,
>>>> +				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)),
>>>> +	AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK,
>>>> +				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),
>>>> +};
>>>> +
>>>> +static const struct airoha_pinctrl_func_group phy3_led0_func_group[] = {
>>>> +	AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK,
>>>> +				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
>>>> +	AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK,
>>>> +				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),
>>>> +	AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK,
>>>> +				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),
>>>> +	AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK,
>>>> +				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
>>>> +};
>>>> +
>>>> +static const struct airoha_pinctrl_func_group phy4_led0_func_group[] = {
>>>> +	AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK,
>>>> +				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)),
>>>> +	AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK,
>>>> +				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)),
>>>> +	AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK,
>>>> +				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)),
>>>> +	AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK,
>>>> +				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)),
>>>> +};
>>>> +
>>>> +static const struct airoha_pinctrl_func_group phy1_led1_func_group[] = {
>>>> +	AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK,
>>>> +				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),
>>>> +	AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK,
>>>> +				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)),
>>>> +	AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK,
>>>> +				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)),
>>>> +	AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK,
>>>> +				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),
>>>> +};
>>>> +
>>>> +static const struct airoha_pinctrl_func_group phy2_led1_func_group[] = {
>>>> +	AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK,
>>>> +				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),
>>>> +	AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK,
>>>> +				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)),
>>>> +	AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK,
>>>> +				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)),
>>>> +	AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK,
>>>> +				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),
>>>> +};
>>>> +
>>>> +static const struct airoha_pinctrl_func_group phy3_led1_func_group[] = {
>>>> +	AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK,
>>>> +				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
>>>> +	AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK,
>>>> +				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),
>>>> +	AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK,
>>>> +				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),
>>>> +	AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK,
>>>> +				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
>>>> +};
>>>> +
>>>> +static const struct airoha_pinctrl_func_group phy4_led1_func_group[] = {
>>>> +	AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK,
>>>> +				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)),
>>>> +	AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK,
>>>> +				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)),
>>>> +	AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK,
>>>> +				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)),
>>>> +	AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK,
>>>> +				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)),
>>>> +};
>>>> +
>>>> +static const struct airoha_pinctrl_func en7581_pinctrl_funcs[] = {
>>>> +	PINCTRL_FUNC_DESC("pon", pon),
>>>> +	PINCTRL_FUNC_DESC("tod_1pps", tod_1pps),
>>>> +	PINCTRL_FUNC_DESC("sipo", sipo),
>>>> +	PINCTRL_FUNC_DESC("mdio", mdio),
>>>> +	PINCTRL_FUNC_DESC("uart", uart),
>>>> +	PINCTRL_FUNC_DESC("i2c", i2c),
>>>> +	PINCTRL_FUNC_DESC("jtag", jtag),
>>>> +	PINCTRL_FUNC_DESC("pcm", pcm),
>>>> +	PINCTRL_FUNC_DESC("spi", spi),
>>>> +	PINCTRL_FUNC_DESC("pcm_spi", pcm_spi),
>>>> +	PINCTRL_FUNC_DESC("i2s", i2s),
>>>> +	PINCTRL_FUNC_DESC("emmc", emmc),
>>>> +	PINCTRL_FUNC_DESC("pnand", pnand),
>>>> +	PINCTRL_FUNC_DESC("gpio", gpio),
>>>> +	PINCTRL_FUNC_DESC("pcie_reset", pcie_reset),
>>>> +	PINCTRL_FUNC_DESC("pwm", pwm),
>>>> +	PINCTRL_FUNC_DESC("phy1_led0", phy1_led0),
>>>> +	PINCTRL_FUNC_DESC("phy2_led0", phy2_led0),
>>>> +	PINCTRL_FUNC_DESC("phy3_led0", phy3_led0),
>>>> +	PINCTRL_FUNC_DESC("phy4_led0", phy4_led0),
>>>> +	PINCTRL_FUNC_DESC("phy1_led1", phy1_led1),
>>>> +	PINCTRL_FUNC_DESC("phy2_led1", phy2_led1),
>>>> +	PINCTRL_FUNC_DESC("phy3_led1", phy3_led1),
>>>> +	PINCTRL_FUNC_DESC("phy4_led1", phy4_led1),
>>>> +};
>>>> +
>>>> +static const struct airoha_pinctrl_conf en7581_pinctrl_pullup_conf[] = {
>>>> +	PINCTRL_CONF_DESC(0, REG_I2C_SDA_PU, UART1_TXD_PU_MASK),
>>>> +	PINCTRL_CONF_DESC(1, REG_I2C_SDA_PU, UART1_RXD_PU_MASK),
>>>> +	PINCTRL_CONF_DESC(2, REG_I2C_SDA_PU, I2C_SDA_PU_MASK),
>>>> +	PINCTRL_CONF_DESC(3, REG_I2C_SDA_PU, I2C_SCL_PU_MASK),
>>>> +	PINCTRL_CONF_DESC(4, REG_I2C_SDA_PU, SPI_CS0_PU_MASK),
>>>> +	PINCTRL_CONF_DESC(5, REG_I2C_SDA_PU, SPI_CLK_PU_MASK),
>>>> +	PINCTRL_CONF_DESC(6, REG_I2C_SDA_PU, SPI_MOSI_PU_MASK),
>>>> +	PINCTRL_CONF_DESC(7, REG_I2C_SDA_PU, SPI_MISO_PU_MASK),
>>>> +	PINCTRL_CONF_DESC(13, REG_GPIO_L_PU, BIT(0)),
>>>> +	PINCTRL_CONF_DESC(14, REG_GPIO_L_PU, BIT(1)),
>>>> +	PINCTRL_CONF_DESC(15, REG_GPIO_L_PU, BIT(2)),
>>>> +	PINCTRL_CONF_DESC(16, REG_GPIO_L_PU, BIT(3)),
>>>> +	PINCTRL_CONF_DESC(17, REG_GPIO_L_PU, BIT(4)),
>>>> +	PINCTRL_CONF_DESC(18, REG_GPIO_L_PU, BIT(5)),
>>>> +	PINCTRL_CONF_DESC(19, REG_GPIO_L_PU, BIT(6)),
>>>> +	PINCTRL_CONF_DESC(20, REG_GPIO_L_PU, BIT(7)),
>>>> +	PINCTRL_CONF_DESC(21, REG_GPIO_L_PU, BIT(8)),
>>>> +	PINCTRL_CONF_DESC(22, REG_GPIO_L_PU, BIT(9)),
>>>> +	PINCTRL_CONF_DESC(23, REG_GPIO_L_PU, BIT(10)),
>>>> +	PINCTRL_CONF_DESC(24, REG_GPIO_L_PU, BIT(11)),
>>>> +	PINCTRL_CONF_DESC(25, REG_GPIO_L_PU, BIT(12)),
>>>> +	PINCTRL_CONF_DESC(26, REG_GPIO_L_PU, BIT(13)),
>>>> +	PINCTRL_CONF_DESC(27, REG_GPIO_L_PU, BIT(14)),
>>>> +	PINCTRL_CONF_DESC(28, REG_GPIO_L_PU, BIT(15)),
>>>> +	PINCTRL_CONF_DESC(29, REG_GPIO_L_PU, BIT(16)),
>>>> +	PINCTRL_CONF_DESC(30, REG_GPIO_L_PU, BIT(17)),
>>>> +	PINCTRL_CONF_DESC(31, REG_GPIO_L_PU, BIT(18)),
>>>> +	PINCTRL_CONF_DESC(32, REG_GPIO_L_PU, BIT(19)),
>>>> +	PINCTRL_CONF_DESC(33, REG_GPIO_L_PU, BIT(20)),
>>>> +	PINCTRL_CONF_DESC(34, REG_GPIO_L_PU, BIT(21)),
>>>> +	PINCTRL_CONF_DESC(35, REG_GPIO_L_PU, BIT(22)),
>>>> +	PINCTRL_CONF_DESC(36, REG_GPIO_L_PU, BIT(23)),
>>>> +	PINCTRL_CONF_DESC(37, REG_GPIO_L_PU, BIT(24)),
>>>> +	PINCTRL_CONF_DESC(38, REG_GPIO_L_PU, BIT(25)),
>>>> +	PINCTRL_CONF_DESC(39, REG_GPIO_L_PU, BIT(26)),
>>>> +	PINCTRL_CONF_DESC(40, REG_GPIO_L_PU, BIT(27)),
>>>> +	PINCTRL_CONF_DESC(41, REG_GPIO_L_PU, BIT(28)),
>>>> +	PINCTRL_CONF_DESC(42, REG_GPIO_L_PU, BIT(29)),
>>>> +	PINCTRL_CONF_DESC(43, REG_GPIO_L_PU, BIT(30)),
>>>> +	PINCTRL_CONF_DESC(44, REG_GPIO_L_PU, BIT(31)),
>>>> +	PINCTRL_CONF_DESC(45, REG_GPIO_H_PU, BIT(0)),
>>>> +	PINCTRL_CONF_DESC(46, REG_GPIO_H_PU, BIT(1)),
>>>> +	PINCTRL_CONF_DESC(47, REG_GPIO_H_PU, BIT(2)),
>>>> +	PINCTRL_CONF_DESC(48, REG_GPIO_H_PU, BIT(3)),
>>>> +	PINCTRL_CONF_DESC(49, REG_GPIO_H_PU, BIT(4)),
>>>> +	PINCTRL_CONF_DESC(50, REG_GPIO_H_PU, BIT(5)),
>>>> +	PINCTRL_CONF_DESC(51, REG_GPIO_H_PU, BIT(6)),
>>>> +	PINCTRL_CONF_DESC(52, REG_GPIO_H_PU, BIT(7)),
>>>> +	PINCTRL_CONF_DESC(53, REG_GPIO_H_PU, BIT(8)),
>>>> +	PINCTRL_CONF_DESC(54, REG_GPIO_H_PU, BIT(9)),
>>>> +	PINCTRL_CONF_DESC(55, REG_GPIO_H_PU, BIT(10)),
>>>> +	PINCTRL_CONF_DESC(56, REG_GPIO_H_PU, BIT(11)),
>>>> +	PINCTRL_CONF_DESC(57, REG_GPIO_H_PU, BIT(12)),
>>>> +	PINCTRL_CONF_DESC(58, REG_GPIO_H_PU, BIT(13)),
>>>> +	PINCTRL_CONF_DESC(59, REG_GPIO_H_PU, BIT(14)),
>>>> +	PINCTRL_CONF_DESC(60, REG_I2C_SDA_PU, PCIE0_RESET_PU_MASK),
>>>> +	PINCTRL_CONF_DESC(61, REG_I2C_SDA_PU, PCIE1_RESET_PU_MASK),
>>>> +	PINCTRL_CONF_DESC(62, REG_I2C_SDA_PU, PCIE2_RESET_PU_MASK),
>>>> +};
>>>> +
>>>> +static const struct airoha_pinctrl_conf en7581_pinctrl_pulldown_conf[] = {
>>>> +	PINCTRL_CONF_DESC(0, REG_I2C_SDA_PD, UART1_TXD_PD_MASK),
>>>> +	PINCTRL_CONF_DESC(1, REG_I2C_SDA_PD, UART1_RXD_PD_MASK),
>>>> +	PINCTRL_CONF_DESC(2, REG_I2C_SDA_PD, I2C_SDA_PD_MASK),
>>>> +	PINCTRL_CONF_DESC(3, REG_I2C_SDA_PD, I2C_SCL_PD_MASK),
>>>> +	PINCTRL_CONF_DESC(4, REG_I2C_SDA_PD, SPI_CS0_PD_MASK),
>>>> +	PINCTRL_CONF_DESC(5, REG_I2C_SDA_PD, SPI_CLK_PD_MASK),
>>>> +	PINCTRL_CONF_DESC(6, REG_I2C_SDA_PD, SPI_MOSI_PD_MASK),
>>>> +	PINCTRL_CONF_DESC(7, REG_I2C_SDA_PD, SPI_MISO_PD_MASK),
>>>> +	PINCTRL_CONF_DESC(13, REG_GPIO_L_PD, BIT(0)),
>>>> +	PINCTRL_CONF_DESC(14, REG_GPIO_L_PD, BIT(1)),
>>>> +	PINCTRL_CONF_DESC(15, REG_GPIO_L_PD, BIT(2)),
>>>> +	PINCTRL_CONF_DESC(16, REG_GPIO_L_PD, BIT(3)),
>>>> +	PINCTRL_CONF_DESC(17, REG_GPIO_L_PD, BIT(4)),
>>>> +	PINCTRL_CONF_DESC(18, REG_GPIO_L_PD, BIT(5)),
>>>> +	PINCTRL_CONF_DESC(19, REG_GPIO_L_PD, BIT(6)),
>>>> +	PINCTRL_CONF_DESC(20, REG_GPIO_L_PD, BIT(7)),
>>>> +	PINCTRL_CONF_DESC(21, REG_GPIO_L_PD, BIT(8)),
>>>> +	PINCTRL_CONF_DESC(22, REG_GPIO_L_PD, BIT(9)),
>>>> +	PINCTRL_CONF_DESC(23, REG_GPIO_L_PD, BIT(10)),
>>>> +	PINCTRL_CONF_DESC(24, REG_GPIO_L_PD, BIT(11)),
>>>> +	PINCTRL_CONF_DESC(25, REG_GPIO_L_PD, BIT(12)),
>>>> +	PINCTRL_CONF_DESC(26, REG_GPIO_L_PD, BIT(13)),
>>>> +	PINCTRL_CONF_DESC(27, REG_GPIO_L_PD, BIT(14)),
>>>> +	PINCTRL_CONF_DESC(28, REG_GPIO_L_PD, BIT(15)),
>>>> +	PINCTRL_CONF_DESC(29, REG_GPIO_L_PD, BIT(16)),
>>>> +	PINCTRL_CONF_DESC(30, REG_GPIO_L_PD, BIT(17)),
>>>> +	PINCTRL_CONF_DESC(31, REG_GPIO_L_PD, BIT(18)),
>>>> +	PINCTRL_CONF_DESC(32, REG_GPIO_L_PD, BIT(19)),
>>>> +	PINCTRL_CONF_DESC(33, REG_GPIO_L_PD, BIT(20)),
>>>> +	PINCTRL_CONF_DESC(34, REG_GPIO_L_PD, BIT(21)),
>>>> +	PINCTRL_CONF_DESC(35, REG_GPIO_L_PD, BIT(22)),
>>>> +	PINCTRL_CONF_DESC(36, REG_GPIO_L_PD, BIT(23)),
>>>> +	PINCTRL_CONF_DESC(37, REG_GPIO_L_PD, BIT(24)),
>>>> +	PINCTRL_CONF_DESC(38, REG_GPIO_L_PD, BIT(25)),
>>>> +	PINCTRL_CONF_DESC(39, REG_GPIO_L_PD, BIT(26)),
>>>> +	PINCTRL_CONF_DESC(40, REG_GPIO_L_PD, BIT(27)),
>>>> +	PINCTRL_CONF_DESC(41, REG_GPIO_L_PD, BIT(28)),
>>>> +	PINCTRL_CONF_DESC(42, REG_GPIO_L_PD, BIT(29)),
>>>> +	PINCTRL_CONF_DESC(43, REG_GPIO_L_PD, BIT(30)),
>>>> +	PINCTRL_CONF_DESC(44, REG_GPIO_L_PD, BIT(31)),
>>>> +	PINCTRL_CONF_DESC(45, REG_GPIO_H_PD, BIT(0)),
>>>> +	PINCTRL_CONF_DESC(46, REG_GPIO_H_PD, BIT(1)),
>>>> +	PINCTRL_CONF_DESC(47, REG_GPIO_H_PD, BIT(2)),
>>>> +	PINCTRL_CONF_DESC(48, REG_GPIO_H_PD, BIT(3)),
>>>> +	PINCTRL_CONF_DESC(49, REG_GPIO_H_PD, BIT(4)),
>>>> +	PINCTRL_CONF_DESC(50, REG_GPIO_H_PD, BIT(5)),
>>>> +	PINCTRL_CONF_DESC(51, REG_GPIO_H_PD, BIT(6)),
>>>> +	PINCTRL_CONF_DESC(52, REG_GPIO_H_PD, BIT(7)),
>>>> +	PINCTRL_CONF_DESC(53, REG_GPIO_H_PD, BIT(8)),
>>>> +	PINCTRL_CONF_DESC(54, REG_GPIO_H_PD, BIT(9)),
>>>> +	PINCTRL_CONF_DESC(55, REG_GPIO_H_PD, BIT(10)),
>>>> +	PINCTRL_CONF_DESC(56, REG_GPIO_H_PD, BIT(11)),
>>>> +	PINCTRL_CONF_DESC(57, REG_GPIO_H_PD, BIT(12)),
>>>> +	PINCTRL_CONF_DESC(58, REG_GPIO_H_PD, BIT(13)),
>>>> +	PINCTRL_CONF_DESC(59, REG_GPIO_H_PD, BIT(14)),
>>>> +	PINCTRL_CONF_DESC(60, REG_I2C_SDA_PD, PCIE0_RESET_PD_MASK),
>>>> +	PINCTRL_CONF_DESC(61, REG_I2C_SDA_PD, PCIE1_RESET_PD_MASK),
>>>> +	PINCTRL_CONF_DESC(62, REG_I2C_SDA_PD, PCIE2_RESET_PD_MASK),
>>>> +};
>>>> +
>>>> +static const struct airoha_pinctrl_conf en7581_pinctrl_drive_e2_conf[] = {
>>>> +	PINCTRL_CONF_DESC(0, REG_I2C_SDA_E2, UART1_TXD_E2_MASK),
>>>> +	PINCTRL_CONF_DESC(1, REG_I2C_SDA_E2, UART1_RXD_E2_MASK),
>>>> +	PINCTRL_CONF_DESC(2, REG_I2C_SDA_E2, I2C_SDA_E2_MASK),
>>>> +	PINCTRL_CONF_DESC(3, REG_I2C_SDA_E2, I2C_SCL_E2_MASK),
>>>> +	PINCTRL_CONF_DESC(4, REG_I2C_SDA_E2, SPI_CS0_E2_MASK),
>>>> +	PINCTRL_CONF_DESC(5, REG_I2C_SDA_E2, SPI_CLK_E2_MASK),
>>>> +	PINCTRL_CONF_DESC(6, REG_I2C_SDA_E2, SPI_MOSI_E2_MASK),
>>>> +	PINCTRL_CONF_DESC(7, REG_I2C_SDA_E2, SPI_MISO_E2_MASK),
>>>> +	PINCTRL_CONF_DESC(13, REG_GPIO_L_E2, BIT(0)),
>>>> +	PINCTRL_CONF_DESC(14, REG_GPIO_L_E2, BIT(1)),
>>>> +	PINCTRL_CONF_DESC(15, REG_GPIO_L_E2, BIT(2)),
>>>> +	PINCTRL_CONF_DESC(16, REG_GPIO_L_E2, BIT(3)),
>>>> +	PINCTRL_CONF_DESC(17, REG_GPIO_L_E2, BIT(4)),
>>>> +	PINCTRL_CONF_DESC(18, REG_GPIO_L_E2, BIT(5)),
>>>> +	PINCTRL_CONF_DESC(19, REG_GPIO_L_E2, BIT(6)),
>>>> +	PINCTRL_CONF_DESC(20, REG_GPIO_L_E2, BIT(7)),
>>>> +	PINCTRL_CONF_DESC(21, REG_GPIO_L_E2, BIT(8)),
>>>> +	PINCTRL_CONF_DESC(22, REG_GPIO_L_E2, BIT(9)),
>>>> +	PINCTRL_CONF_DESC(23, REG_GPIO_L_E2, BIT(10)),
>>>> +	PINCTRL_CONF_DESC(24, REG_GPIO_L_E2, BIT(11)),
>>>> +	PINCTRL_CONF_DESC(25, REG_GPIO_L_E2, BIT(12)),
>>>> +	PINCTRL_CONF_DESC(26, REG_GPIO_L_E2, BIT(13)),
>>>> +	PINCTRL_CONF_DESC(27, REG_GPIO_L_E2, BIT(14)),
>>>> +	PINCTRL_CONF_DESC(28, REG_GPIO_L_E2, BIT(15)),
>>>> +	PINCTRL_CONF_DESC(29, REG_GPIO_L_E2, BIT(16)),
>>>> +	PINCTRL_CONF_DESC(30, REG_GPIO_L_E2, BIT(17)),
>>>> +	PINCTRL_CONF_DESC(31, REG_GPIO_L_E2, BIT(18)),
>>>> +	PINCTRL_CONF_DESC(32, REG_GPIO_L_E2, BIT(19)),
>>>> +	PINCTRL_CONF_DESC(33, REG_GPIO_L_E2, BIT(20)),
>>>> +	PINCTRL_CONF_DESC(34, REG_GPIO_L_E2, BIT(21)),
>>>> +	PINCTRL_CONF_DESC(35, REG_GPIO_L_E2, BIT(22)),
>>>> +	PINCTRL_CONF_DESC(36, REG_GPIO_L_E2, BIT(23)),
>>>> +	PINCTRL_CONF_DESC(37, REG_GPIO_L_E2, BIT(24)),
>>>> +	PINCTRL_CONF_DESC(38, REG_GPIO_L_E2, BIT(25)),
>>>> +	PINCTRL_CONF_DESC(39, REG_GPIO_L_E2, BIT(26)),
>>>> +	PINCTRL_CONF_DESC(40, REG_GPIO_L_E2, BIT(27)),
>>>> +	PINCTRL_CONF_DESC(41, REG_GPIO_L_E2, BIT(28)),
>>>> +	PINCTRL_CONF_DESC(42, REG_GPIO_L_E2, BIT(29)),
>>>> +	PINCTRL_CONF_DESC(43, REG_GPIO_L_E2, BIT(30)),
>>>> +	PINCTRL_CONF_DESC(44, REG_GPIO_L_E2, BIT(31)),
>>>> +	PINCTRL_CONF_DESC(45, REG_GPIO_H_E2, BIT(0)),
>>>> +	PINCTRL_CONF_DESC(46, REG_GPIO_H_E2, BIT(1)),
>>>> +	PINCTRL_CONF_DESC(47, REG_GPIO_H_E2, BIT(2)),
>>>> +	PINCTRL_CONF_DESC(48, REG_GPIO_H_E2, BIT(3)),
>>>> +	PINCTRL_CONF_DESC(49, REG_GPIO_H_E2, BIT(4)),
>>>> +	PINCTRL_CONF_DESC(50, REG_GPIO_H_E2, BIT(5)),
>>>> +	PINCTRL_CONF_DESC(51, REG_GPIO_H_E2, BIT(6)),
>>>> +	PINCTRL_CONF_DESC(52, REG_GPIO_H_E2, BIT(7)),
>>>> +	PINCTRL_CONF_DESC(53, REG_GPIO_H_E2, BIT(8)),
>>>> +	PINCTRL_CONF_DESC(54, REG_GPIO_H_E2, BIT(9)),
>>>> +	PINCTRL_CONF_DESC(55, REG_GPIO_H_E2, BIT(10)),
>>>> +	PINCTRL_CONF_DESC(56, REG_GPIO_H_E2, BIT(11)),
>>>> +	PINCTRL_CONF_DESC(57, REG_GPIO_H_E2, BIT(12)),
>>>> +	PINCTRL_CONF_DESC(58, REG_GPIO_H_E2, BIT(13)),
>>>> +	PINCTRL_CONF_DESC(59, REG_GPIO_H_E2, BIT(14)),
>>>> +	PINCTRL_CONF_DESC(60, REG_I2C_SDA_E2, PCIE0_RESET_E2_MASK),
>>>> +	PINCTRL_CONF_DESC(61, REG_I2C_SDA_E2, PCIE1_RESET_E2_MASK),
>>>> +	PINCTRL_CONF_DESC(62, REG_I2C_SDA_E2, PCIE2_RESET_E2_MASK),
>>>> +};
>>>> +
>>>> +static const struct airoha_pinctrl_conf en7581_pinctrl_drive_e4_conf[] = {
>>>> +	PINCTRL_CONF_DESC(0, REG_I2C_SDA_E4, UART1_TXD_E4_MASK),
>>>> +	PINCTRL_CONF_DESC(1, REG_I2C_SDA_E4, UART1_RXD_E4_MASK),
>>>> +	PINCTRL_CONF_DESC(2, REG_I2C_SDA_E4, I2C_SDA_E4_MASK),
>>>> +	PINCTRL_CONF_DESC(3, REG_I2C_SDA_E4, I2C_SCL_E4_MASK),
>>>> +	PINCTRL_CONF_DESC(4, REG_I2C_SDA_E4, SPI_CS0_E4_MASK),
>>>> +	PINCTRL_CONF_DESC(5, REG_I2C_SDA_E4, SPI_CLK_E4_MASK),
>>>> +	PINCTRL_CONF_DESC(6, REG_I2C_SDA_E4, SPI_MOSI_E4_MASK),
>>>> +	PINCTRL_CONF_DESC(7, REG_I2C_SDA_E4, SPI_MISO_E4_MASK),
>>>> +	PINCTRL_CONF_DESC(13, REG_GPIO_L_E4, BIT(0)),
>>>> +	PINCTRL_CONF_DESC(14, REG_GPIO_L_E4, BIT(1)),
>>>> +	PINCTRL_CONF_DESC(15, REG_GPIO_L_E4, BIT(2)),
>>>> +	PINCTRL_CONF_DESC(16, REG_GPIO_L_E4, BIT(3)),
>>>> +	PINCTRL_CONF_DESC(17, REG_GPIO_L_E4, BIT(4)),
>>>> +	PINCTRL_CONF_DESC(18, REG_GPIO_L_E4, BIT(5)),
>>>> +	PINCTRL_CONF_DESC(19, REG_GPIO_L_E4, BIT(6)),
>>>> +	PINCTRL_CONF_DESC(20, REG_GPIO_L_E4, BIT(7)),
>>>> +	PINCTRL_CONF_DESC(21, REG_GPIO_L_E4, BIT(8)),
>>>> +	PINCTRL_CONF_DESC(22, REG_GPIO_L_E4, BIT(9)),
>>>> +	PINCTRL_CONF_DESC(23, REG_GPIO_L_E4, BIT(10)),
>>>> +	PINCTRL_CONF_DESC(24, REG_GPIO_L_E4, BIT(11)),
>>>> +	PINCTRL_CONF_DESC(25, REG_GPIO_L_E4, BIT(12)),
>>>> +	PINCTRL_CONF_DESC(26, REG_GPIO_L_E4, BIT(13)),
>>>> +	PINCTRL_CONF_DESC(27, REG_GPIO_L_E4, BIT(14)),
>>>> +	PINCTRL_CONF_DESC(28, REG_GPIO_L_E4, BIT(15)),
>>>> +	PINCTRL_CONF_DESC(29, REG_GPIO_L_E4, BIT(16)),
>>>> +	PINCTRL_CONF_DESC(30, REG_GPIO_L_E4, BIT(17)),
>>>> +	PINCTRL_CONF_DESC(31, REG_GPIO_L_E4, BIT(18)),
>>>> +	PINCTRL_CONF_DESC(32, REG_GPIO_L_E4, BIT(19)),
>>>> +	PINCTRL_CONF_DESC(33, REG_GPIO_L_E4, BIT(20)),
>>>> +	PINCTRL_CONF_DESC(34, REG_GPIO_L_E4, BIT(21)),
>>>> +	PINCTRL_CONF_DESC(35, REG_GPIO_L_E4, BIT(22)),
>>>> +	PINCTRL_CONF_DESC(36, REG_GPIO_L_E4, BIT(23)),
>>>> +	PINCTRL_CONF_DESC(37, REG_GPIO_L_E4, BIT(24)),
>>>> +	PINCTRL_CONF_DESC(38, REG_GPIO_L_E4, BIT(25)),
>>>> +	PINCTRL_CONF_DESC(39, REG_GPIO_L_E4, BIT(26)),
>>>> +	PINCTRL_CONF_DESC(40, REG_GPIO_L_E4, BIT(27)),
>>>> +	PINCTRL_CONF_DESC(41, REG_GPIO_L_E4, BIT(28)),
>>>> +	PINCTRL_CONF_DESC(42, REG_GPIO_L_E4, BIT(29)),
>>>> +	PINCTRL_CONF_DESC(43, REG_GPIO_L_E4, BIT(30)),
>>>> +	PINCTRL_CONF_DESC(44, REG_GPIO_L_E4, BIT(31)),
>>>> +	PINCTRL_CONF_DESC(45, REG_GPIO_H_E4, BIT(0)),
>>>> +	PINCTRL_CONF_DESC(46, REG_GPIO_H_E4, BIT(1)),
>>>> +	PINCTRL_CONF_DESC(47, REG_GPIO_H_E4, BIT(2)),
>>>> +	PINCTRL_CONF_DESC(48, REG_GPIO_H_E4, BIT(3)),
>>>> +	PINCTRL_CONF_DESC(49, REG_GPIO_H_E4, BIT(4)),
>>>> +	PINCTRL_CONF_DESC(50, REG_GPIO_H_E4, BIT(5)),
>>>> +	PINCTRL_CONF_DESC(51, REG_GPIO_H_E4, BIT(6)),
>>>> +	PINCTRL_CONF_DESC(52, REG_GPIO_H_E4, BIT(7)),
>>>> +	PINCTRL_CONF_DESC(53, REG_GPIO_H_E4, BIT(8)),
>>>> +	PINCTRL_CONF_DESC(54, REG_GPIO_H_E4, BIT(9)),
>>>> +	PINCTRL_CONF_DESC(55, REG_GPIO_H_E4, BIT(10)),
>>>> +	PINCTRL_CONF_DESC(56, REG_GPIO_H_E4, BIT(11)),
>>>> +	PINCTRL_CONF_DESC(57, REG_GPIO_H_E4, BIT(12)),
>>>> +	PINCTRL_CONF_DESC(58, REG_GPIO_H_E4, BIT(13)),
>>>> +	PINCTRL_CONF_DESC(59, REG_GPIO_H_E4, BIT(14)),
>>>> +	PINCTRL_CONF_DESC(60, REG_I2C_SDA_E4, PCIE0_RESET_E4_MASK),
>>>> +	PINCTRL_CONF_DESC(61, REG_I2C_SDA_E4, PCIE1_RESET_E4_MASK),
>>>> +	PINCTRL_CONF_DESC(62, REG_I2C_SDA_E4, PCIE2_RESET_E4_MASK),
>>>> +};
>>>> +
>>>> +static const struct airoha_pinctrl_conf en7581_pinctrl_pcie_rst_od_conf[] = {
>>>> +	PINCTRL_CONF_DESC(60, REG_PCIE_RESET_OD, PCIE0_RESET_OD_MASK),
>>>> +	PINCTRL_CONF_DESC(61, REG_PCIE_RESET_OD, PCIE1_RESET_OD_MASK),
>>>> +	PINCTRL_CONF_DESC(62, REG_PCIE_RESET_OD, PCIE2_RESET_OD_MASK),
>>>> +};
>>>> +
>>>> +static const struct airoha_pinctrl_match_data en7581_pinctrl_match_data = {
>>>> +	.pinctrl_name = KBUILD_MODNAME,
>>>> +	.pinctrl_owner = THIS_MODULE,
>>>> +	.pins = en7581_pinctrl_pins,
>>>> +	.num_pins = ARRAY_SIZE(en7581_pinctrl_pins),
>>>> +	.grps = en7581_pinctrl_groups,
>>>> +	.num_grps = ARRAY_SIZE(en7581_pinctrl_groups),
>>>> +	.funcs = en7581_pinctrl_funcs,
>>>> +	.num_funcs = ARRAY_SIZE(en7581_pinctrl_funcs),
>>>> +	.confs_info = {
>>>> +		[AIROHA_PINCTRL_CONFS_PULLUP] = {
>>>> +			.confs = en7581_pinctrl_pullup_conf,
>>>> +			.num_confs = ARRAY_SIZE(en7581_pinctrl_pullup_conf),
>>>> +		},
>>>> +		[AIROHA_PINCTRL_CONFS_PULLDOWN] = {
>>>> +			.confs = en7581_pinctrl_pulldown_conf,
>>>> +			.num_confs = ARRAY_SIZE(en7581_pinctrl_pulldown_conf),
>>>> +		},
>>>> +		[AIROHA_PINCTRL_CONFS_DRIVE_E2] = {
>>>> +			.confs = en7581_pinctrl_drive_e2_conf,
>>>> +			.num_confs = ARRAY_SIZE(en7581_pinctrl_drive_e2_conf),
>>>> +		},
>>>> +		[AIROHA_PINCTRL_CONFS_DRIVE_E4] = {
>>>> +			.confs = en7581_pinctrl_drive_e4_conf,
>>>> +			.num_confs = ARRAY_SIZE(en7581_pinctrl_drive_e4_conf),
>>>> +		},
>>>> +		[AIROHA_PINCTRL_CONFS_PCIE_RST_OD] = {
>>>> +			.confs = en7581_pinctrl_pcie_rst_od_conf,
>>>> +			.num_confs = ARRAY_SIZE(en7581_pinctrl_pcie_rst_od_conf),
>>>> +		},
>>>> +	},
>>>> +};
>>>> +
>>>> +static const struct of_device_id airoha_pinctrl_of_match[] = {
>>>> +	{ .compatible = "airoha,en7581-pinctrl", .data = &en7581_pinctrl_match_data },
>>>> +	{ /* sentinel */ }
>>>> +};
>>>> +MODULE_DEVICE_TABLE(of, airoha_pinctrl_of_match);
>>>> +
>>>> +static struct platform_driver airoha_pinctrl_driver = {
>>>> +	.probe = airoha_pinctrl_probe,
>>>> +	.driver = {
>>>> +		.name = "pinctrl-airoha-an7581",
>>>> +		.of_match_table = airoha_pinctrl_of_match,
>>>> +	},
>>>> +};
>>>> +module_platform_driver(airoha_pinctrl_driver);
>>>> +
>>>> +MODULE_LICENSE("GPL");
>>>> +MODULE_AUTHOR("Lorenzo Bianconi <lorenzo@kernel.org>");
>>>> +MODULE_AUTHOR("Benjamin Larsson <benjamin.larsson@genexis.eu>");
>>>> +MODULE_AUTHOR("Markus Gothe <markus.gothe@genexis.eu>");
>>>> +MODULE_DESCRIPTION("Pinctrl driver for Airoha AN7581 SoC");
>>>> diff --git a/drivers/pinctrl/airoha/pinctrl-an7583.c b/drivers/pinctrl/airoha/pinctrl-an7583.c
>>>> new file mode 100644
>>>> index 0000000000000..b9d8dd94de5f0
>>>> --- /dev/null
>>>> +++ b/drivers/pinctrl/airoha/pinctrl-an7583.c
>>>> @@ -0,0 +1,1456 @@
>>>> +// SPDX-License-Identifier: GPL-2.0-only
>>>> +/*
>>>> + * Author: Lorenzo Bianconi <lorenzo@kernel.org>
>>>> + * Author: Benjamin Larsson <benjamin.larsson@genexis.eu>
>>>> + * Author: Markus Gothe <markus.gothe@genexis.eu>
>>>> + */
>>>> +
>>>> +#include "airoha-common.h"
>>>> +
>>>> +/* MUX */
>>>> +#define REG_GPIO_2ND_I2C_MODE			0x0214
>>>> +#define GPIO_LAN3_LED1_MODE_MASK		BIT(10)
>>>> +#define GPIO_LAN3_LED0_MODE_MASK		BIT(9)
>>>> +#define GPIO_LAN2_LED1_MODE_MASK		BIT(8)
>>>> +#define GPIO_LAN2_LED0_MODE_MASK		BIT(7)
>>>> +#define GPIO_LAN1_LED1_MODE_MASK		BIT(6)
>>>> +#define GPIO_LAN1_LED0_MODE_MASK		BIT(5)
>>>> +#define GPIO_LAN0_LED1_MODE_MASK		BIT(4)
>>>> +#define GPIO_LAN0_LED0_MODE_MASK		BIT(3)
>>>> +#define PON_TOD_1PPS_MODE_MASK			BIT(2)
>>>> +#define GSW_TOD_1PPS_MODE_MASK			BIT(1)
>>>> +
>>>> +#define REG_GPIO_SPI_CS1_MODE			0x0218
>>>> +#define GPIO_MDC_IO_MASTER_MODE_MASK		BIT(22)
>>>> +#define GPIO_PCM_SPI_CS4_MODE_MASK		BIT(21)
>>>> +#define GPIO_PCM_SPI_CS3_MODE_MASK		BIT(20)
>>>> +#define AN7583_GPIO_PCM_SPI_CS2_MODE_MASK	BIT(18)
>>>> +#define GPIO_PCM_SPI_CS1_MODE_MASK		BIT(17)
>>>> +#define GPIO_PCM_SPI_MODE_MASK			BIT(16)
>>>> +#define GPIO_PCM2_MODE_MASK			BIT(13)
>>>> +#define GPIO_PCM1_MODE_MASK			BIT(12)
>>>> +#define GPIO_PCM_INT_MODE_MASK			BIT(9)
>>>> +#define GPIO_PCM_RESET_MODE_MASK		BIT(8)
>>>> +#define GPIO_SPI_QUAD_MODE_MASK			BIT(4)
>>>> +#define GPIO_SPI_CS4_MODE_MASK			BIT(3)
>>>> +#define GPIO_SPI_CS3_MODE_MASK			BIT(2)
>>>> +#define GPIO_SPI_CS2_MODE_MASK			BIT(1)
>>>> +#define GPIO_SPI_CS1_MODE_MASK			BIT(0)
>>>> +
>>>> +#define REG_GPIO_PON_MODE			0x021c
>>>> +#define AN7583_MDIO_0_GPIO_MODE_MASK		BIT(26)
>>>> +#define AN7583_MDC_0_GPIO_MODE_MASK		BIT(25)
>>>> +#define AN7583_UART_RXD_GPIO_MODE_MASK		BIT(24)
>>>> +#define AN7583_UART_TXD_GPIO_MODE_MASK		BIT(23)
>>>> +#define AN7583_SPI_MISO_GPIO_MODE_MASK		BIT(22)
>>>> +#define AN7583_SPI_MOSI_GPIO_MODE_MASK		BIT(21)
>>>> +#define AN7583_SPI_CS_GPIO_MODE_MASK		BIT(20)
>>>> +#define AN7583_SPI_CLK_GPIO_MODE_MASK		BIT(19)
>>>> +#define AN7583_I2C1_SDA_GPIO_MODE_MASK		BIT(18)
>>>> +#define AN7583_I2C1_SCL_GPIO_MODE_MASK		BIT(17)
>>>> +#define AN7583_I2C0_SDA_GPIO_MODE_MASK		BIT(16)
>>>> +#define AN7583_I2C0_SCL_GPIO_MODE_MASK		BIT(15)
>>>> +#define GPIO_PARALLEL_NAND_MODE_MASK		BIT(14)
>>>> +#define GPIO_SGMII_MDIO_MODE_MASK		BIT(13)
>>>> +#define SIPO_RCLK_MODE_MASK			BIT(11)
>>>> +#define GPIO_PCIE_RESET1_MASK			BIT(10)
>>>> +#define GPIO_PCIE_RESET0_MASK			BIT(9)
>>>> +#define GPIO_UART5_MODE_MASK			BIT(8)
>>>> +#define GPIO_UART4_MODE_MASK			BIT(7)
>>>> +#define GPIO_HSUART_CTS_RTS_MODE_MASK		BIT(6)
>>>> +#define GPIO_HSUART_MODE_MASK			BIT(5)
>>>> +#define GPIO_UART2_CTS_RTS_MODE_MASK		BIT(4)
>>>> +#define GPIO_UART2_MODE_MASK			BIT(3)
>>>> +#define GPIO_SIPO_MODE_MASK			BIT(2)
>>>> +#define GPIO_EMMC_MODE_MASK			BIT(1)
>>>> +#define GPIO_PON_MODE_MASK			BIT(0)
>>>> +
>>>> +#define REG_NPU_UART_EN				0x0224
>>>> +#define JTAG_UDI_EN_MASK			BIT(4)
>>>> +#define JTAG_DFD_EN_MASK			BIT(3)
>>>> +
>>>> +#define REG_FORCE_GPIO_EN			0x0228
>>>> +#define FORCE_GPIO_EN(n)			BIT(n)
>>>> +
>>>> +/* LED MAP */
>>>> +#define REG_LAN_LED0_MAPPING			0x027c
>>>> +#define REG_LAN_LED1_MAPPING			0x0280
>>>> +
>>>> +#define LAN4_LED_MAPPING_MASK			GENMASK(18, 16)
>>>> +#define LAN4_PHY_LED_MAP(_n)			FIELD_PREP_CONST(LAN4_LED_MAPPING_MASK, (_n))
>>>> +
>>>> +#define LAN3_LED_MAPPING_MASK			GENMASK(14, 12)
>>>> +#define LAN3_PHY_LED_MAP(_n)			FIELD_PREP_CONST(LAN3_LED_MAPPING_MASK, (_n))
>>>> +
>>>> +#define LAN2_LED_MAPPING_MASK			GENMASK(10, 8)
>>>> +#define LAN2_PHY_LED_MAP(_n)			FIELD_PREP_CONST(LAN2_LED_MAPPING_MASK, (_n))
>>>> +
>>>> +#define LAN1_LED_MAPPING_MASK			GENMASK(6, 4)
>>>> +#define LAN1_PHY_LED_MAP(_n)			FIELD_PREP_CONST(LAN1_LED_MAPPING_MASK, (_n))
>>>> +
>>>> +#define LAN0_LED_MAPPING_MASK			GENMASK(2, 0)
>>>> +#define LAN0_PHY_LED_MAP(_n)			FIELD_PREP_CONST(LAN0_LED_MAPPING_MASK, (_n))
>>>> +
>>>> +/* CONF */
>>>> +#define REG_I2C_SDA_E2				0x001c
>>>> +#define AN7583_I2C1_SCL_E2_MASK			BIT(16)
>>>> +#define AN7583_I2C1_SDA_E2_MASK			BIT(15)
>>>> +#define SPI_MISO_E2_MASK			BIT(14)
>>>> +#define SPI_MOSI_E2_MASK			BIT(13)
>>>> +#define SPI_CLK_E2_MASK				BIT(12)
>>>> +#define SPI_CS0_E2_MASK				BIT(11)
>>>> +#define PCIE1_RESET_E2_MASK			BIT(9)
>>>> +#define PCIE0_RESET_E2_MASK			BIT(8)
>>>> +#define AN7583_MDIO_0_E2_MASK			BIT(5)
>>>> +#define AN7583_MDC_0_E2_MASK			BIT(4)
>>>> +#define UART1_RXD_E2_MASK			BIT(3)
>>>> +#define UART1_TXD_E2_MASK			BIT(2)
>>>> +#define I2C_SCL_E2_MASK				BIT(1)
>>>> +#define I2C_SDA_E2_MASK				BIT(0)
>>>> +
>>>> +#define REG_I2C_SDA_E4				0x0020
>>>> +#define AN7583_I2C1_SCL_E4_MASK			BIT(16)
>>>> +#define AN7583_I2C1_SDA_E4_MASK			BIT(15)
>>>> +#define SPI_MISO_E4_MASK			BIT(14)
>>>> +#define SPI_MOSI_E4_MASK			BIT(13)
>>>> +#define SPI_CLK_E4_MASK				BIT(12)
>>>> +#define SPI_CS0_E4_MASK				BIT(11)
>>>> +#define PCIE1_RESET_E4_MASK			BIT(9)
>>>> +#define PCIE0_RESET_E4_MASK			BIT(8)
>>>> +#define AN7583_MDIO_0_E4_MASK			BIT(5)
>>>> +#define AN7583_MDC_0_E4_MASK			BIT(4)
>>>> +#define UART1_RXD_E4_MASK			BIT(3)
>>>> +#define UART1_TXD_E4_MASK			BIT(2)
>>>> +#define I2C_SCL_E4_MASK				BIT(1)
>>>> +#define I2C_SDA_E4_MASK				BIT(0)
>>>> +
>>>> +#define REG_GPIO_L_E2				0x0024
>>>> +#define REG_GPIO_L_E4				0x0028
>>>> +#define REG_GPIO_H_E2				0x002c
>>>> +#define REG_GPIO_H_E4				0x0030
>>>> +
>>>> +#define REG_I2C_SDA_PU				0x0044
>>>> +#define AN7583_I2C1_SCL_PU_MASK			BIT(16)
>>>> +#define AN7583_I2C1_SDA_PU_MASK			BIT(15)
>>>> +#define SPI_MISO_PU_MASK			BIT(14)
>>>> +#define SPI_MOSI_PU_MASK			BIT(13)
>>>> +#define SPI_CLK_PU_MASK				BIT(12)
>>>> +#define SPI_CS0_PU_MASK				BIT(11)
>>>> +#define PCIE1_RESET_PU_MASK			BIT(9)
>>>> +#define PCIE0_RESET_PU_MASK			BIT(8)
>>>> +#define AN7583_MDIO_0_PU_MASK			BIT(5)
>>>> +#define AN7583_MDC_0_PU_MASK			BIT(4)
>>>> +#define UART1_RXD_PU_MASK			BIT(3)
>>>> +#define UART1_TXD_PU_MASK			BIT(2)
>>>> +#define I2C_SCL_PU_MASK				BIT(1)
>>>> +#define I2C_SDA_PU_MASK				BIT(0)
>>>> +
>>>> +#define REG_I2C_SDA_PD				0x0048
>>>> +#define AN7583_I2C1_SCL_PD_MASK			BIT(16)
>>>> +#define AN7583_I2C1_SDA_PD_MASK			BIT(15)
>>>> +#define SPI_MISO_PD_MASK			BIT(14)
>>>> +#define SPI_MOSI_PD_MASK			BIT(13)
>>>> +#define SPI_CLK_PD_MASK				BIT(12)
>>>> +#define SPI_CS0_PD_MASK				BIT(11)
>>>> +#define PCIE1_RESET_PD_MASK			BIT(9)
>>>> +#define PCIE0_RESET_PD_MASK			BIT(8)
>>>> +#define AN7583_MDIO_0_PD_MASK			BIT(5)
>>>> +#define AN7583_MDC_0_PD_MASK			BIT(4)
>>>> +#define UART1_RXD_PD_MASK			BIT(3)
>>>> +#define UART1_TXD_PD_MASK			BIT(2)
>>>> +#define I2C_SCL_PD_MASK				BIT(1)
>>>> +#define I2C_SDA_PD_MASK				BIT(0)
>>>> +
>>>> +#define REG_GPIO_L_PU				0x004c
>>>> +#define REG_GPIO_L_PD				0x0050
>>>> +#define REG_GPIO_H_PU				0x0054
>>>> +#define REG_GPIO_H_PD				0x0058
>>>> +
>>>> +#define REG_PCIE_RESET_OD			0x018c
>>>> +#define PCIE1_RESET_OD_MASK			BIT(1)
>>>> +#define PCIE0_RESET_OD_MASK			BIT(0)
>>>> +
>>>> +/* PWM MODE CONF */
>>>> +#define REG_GPIO_FLASH_MODE_CFG			0x0034
>>>> +#define GPIO15_FLASH_MODE_CFG			BIT(15)
>>>> +#define GPIO14_FLASH_MODE_CFG			BIT(14)
>>>> +#define GPIO13_FLASH_MODE_CFG			BIT(13)
>>>> +#define GPIO12_FLASH_MODE_CFG			BIT(12)
>>>> +#define GPIO11_FLASH_MODE_CFG			BIT(11)
>>>> +#define GPIO10_FLASH_MODE_CFG			BIT(10)
>>>> +#define GPIO9_FLASH_MODE_CFG			BIT(9)
>>>> +#define GPIO8_FLASH_MODE_CFG			BIT(8)
>>>> +#define GPIO7_FLASH_MODE_CFG			BIT(7)
>>>> +#define GPIO6_FLASH_MODE_CFG			BIT(6)
>>>> +#define GPIO5_FLASH_MODE_CFG			BIT(5)
>>>> +#define GPIO4_FLASH_MODE_CFG			BIT(4)
>>>> +#define GPIO3_FLASH_MODE_CFG			BIT(3)
>>>> +#define GPIO2_FLASH_MODE_CFG			BIT(2)
>>>> +#define GPIO1_FLASH_MODE_CFG			BIT(1)
>>>> +#define GPIO0_FLASH_MODE_CFG			BIT(0)
>>>> +
>>>> +/* PWM MODE CONF EXT */
>>>> +#define REG_GPIO_FLASH_MODE_CFG_EXT		0x0068
>>>> +#define GPIO51_FLASH_MODE_CFG			BIT(31)
>>>> +#define GPIO50_FLASH_MODE_CFG			BIT(30)
>>>> +#define GPIO49_FLASH_MODE_CFG			BIT(29)
>>>> +#define GPIO48_FLASH_MODE_CFG			BIT(28)
>>>> +#define GPIO47_FLASH_MODE_CFG			BIT(27)
>>>> +#define GPIO46_FLASH_MODE_CFG			BIT(26)
>>>> +#define GPIO45_FLASH_MODE_CFG			BIT(25)
>>>> +#define GPIO44_FLASH_MODE_CFG			BIT(24)
>>>> +#define GPIO43_FLASH_MODE_CFG			BIT(23)
>>>> +#define GPIO42_FLASH_MODE_CFG			BIT(22)
>>>> +#define GPIO41_FLASH_MODE_CFG			BIT(21)
>>>> +#define GPIO40_FLASH_MODE_CFG			BIT(20)
>>>> +#define GPIO39_FLASH_MODE_CFG			BIT(19)
>>>> +#define GPIO38_FLASH_MODE_CFG			BIT(18)
>>>> +#define GPIO37_FLASH_MODE_CFG			BIT(17)
>>>> +#define GPIO36_FLASH_MODE_CFG			BIT(16)
>>>> +#define GPIO31_FLASH_MODE_CFG			BIT(15)
>>>> +#define GPIO30_FLASH_MODE_CFG			BIT(14)
>>>> +#define GPIO29_FLASH_MODE_CFG			BIT(13)
>>>> +#define GPIO28_FLASH_MODE_CFG			BIT(12)
>>>> +#define GPIO27_FLASH_MODE_CFG			BIT(11)
>>>> +#define GPIO26_FLASH_MODE_CFG			BIT(10)
>>>> +#define GPIO25_FLASH_MODE_CFG			BIT(9)
>>>> +#define GPIO24_FLASH_MODE_CFG			BIT(8)
>>>> +#define GPIO23_FLASH_MODE_CFG			BIT(7)
>>>> +#define GPIO22_FLASH_MODE_CFG			BIT(6)
>>>> +#define GPIO21_FLASH_MODE_CFG			BIT(5)
>>>> +#define GPIO20_FLASH_MODE_CFG			BIT(4)
>>>> +#define GPIO19_FLASH_MODE_CFG			BIT(3)
>>>> +#define GPIO18_FLASH_MODE_CFG			BIT(2)
>>>> +#define GPIO17_FLASH_MODE_CFG			BIT(1)
>>>> +#define GPIO16_FLASH_MODE_CFG			BIT(0)
>>>> +
>>>> +#define AIROHA_PINCTRL_GPIO(gpio, mux_val)			\
>>>> +	{							\
>>>> +		.name = (gpio),					\
>>>> +		.regmap[0] = {					\
>>>> +			AIROHA_FUNC_MUX,			\
>>>> +			REG_GPIO_PON_MODE,			\
>>>> +			(mux_val),				\
>>>> +			(mux_val)				\
>>>> +		},						\
>>>> +		.regmap_size = 1,				\
>>>> +	}
>>>> +
>>>> +#define AIROHA_PINCTRL_GPIO_EXT(gpio, mux_val, smux_val)	\
>>>> +	{							\
>>>> +		.name = (gpio),					\
>>>> +		.regmap[0] = {					\
>>>> +			AIROHA_FUNC_PWM_EXT_MUX,		\
>>>> +			REG_GPIO_FLASH_MODE_CFG_EXT,		\
>>>> +			(mux_val),				\
>>>> +			0					\
>>>> +		},						\
>>>> +		.regmap[1] = {					\
>>>> +			AIROHA_FUNC_MUX,			\
>>>> +			REG_GPIO_PON_MODE,			\
>>>> +			(smux_val),				\
>>>> +			(smux_val)				\
>>>> +		},						\
>>>> +		.regmap_size = 2,				\
>>>> +	}
>>>> +
>>>> +/* PWM */
>>>> +#define AIROHA_PINCTRL_PWM(gpio, mux_val)			\
>>>> +	{							\
>>>> +		.name = (gpio),					\
>>>> +		.regmap[0] = {					\
>>>> +			AIROHA_FUNC_PWM_MUX,			\
>>>> +			REG_GPIO_FLASH_MODE_CFG,		\
>>>> +			(mux_val),				\
>>>> +			(mux_val)				\
>>>> +		},						\
>>>> +		.regmap_size = 1,				\
>>>> +	}
>>>> +
>>>> +#define AIROHA_PINCTRL_PWM_EXT(gpio, mux_val)			\
>>>> +	{							\
>>>> +		.name = (gpio),					\
>>>> +		.regmap[0] = {					\
>>>> +			AIROHA_FUNC_PWM_EXT_MUX,		\
>>>> +			REG_GPIO_FLASH_MODE_CFG_EXT,		\
>>>> +			(mux_val),				\
>>>> +			(mux_val)				\
>>>> +		},						\
>>>> +		.regmap_size = 1,				\
>>>> +	}
>>>> +
>>>> +#define AIROHA_PINCTRL_PWM_EXT_SEC(gpio, mux_val, smux_val)	\
>>>> +	{							\
>>>> +		.name = (gpio),					\
>>>> +		.regmap[0] = {					\
>>>> +			AIROHA_FUNC_PWM_EXT_MUX,		\
>>>> +			REG_GPIO_FLASH_MODE_CFG_EXT,		\
>>>> +			(mux_val),				\
>>>> +			(mux_val)				\
>>>> +		},						\
>>>> +		.regmap[1] = {					\
>>>> +			AIROHA_FUNC_MUX,			\
>>>> +			REG_GPIO_PON_MODE,			\
>>>> +			(smux_val),				\
>>>> +			(smux_val)				\
>>>> +		},						\
>>>> +		.regmap_size = 2,				\
>>>> +	}
>>>> +
>>>> +#define AIROHA_PINCTRL_PHY_LED0(gpio, mux_val, map_mask, map_val)	\
>>>> +	{								\
>>>> +		.name = (gpio),						\
>>>> +		.regmap[0] = {						\
>>>> +			AIROHA_FUNC_MUX,				\
>>>> +			REG_GPIO_2ND_I2C_MODE,				\
>>>> +			(mux_val),					\
>>>> +			(mux_val),					\
>>>> +		},							\
>>>> +		.regmap[1] = {						\
>>>> +			AIROHA_FUNC_MUX,				\
>>>> +			REG_LAN_LED0_MAPPING,				\
>>>> +			(map_mask),					\
>>>> +			(map_val),					\
>>>> +		},							\
>>>> +		.regmap_size = 2,					\
>>>> +	}
>>>> +
>>>> +#define AIROHA_PINCTRL_PHY_LED1(gpio, mux_val, map_mask, map_val)	\
>>>> +	{								\
>>>> +		.name = (gpio),						\
>>>> +		.regmap[0] = {						\
>>>> +			AIROHA_FUNC_MUX,				\
>>>> +			REG_GPIO_2ND_I2C_MODE,				\
>>>> +			(mux_val),					\
>>>> +			(mux_val),					\
>>>> +		},							\
>>>> +		.regmap[1] = {						\
>>>> +			AIROHA_FUNC_MUX,				\
>>>> +			REG_LAN_LED1_MAPPING,				\
>>>> +			(map_mask),					\
>>>> +			(map_val),					\
>>>> +		},							\
>>>> +		.regmap_size = 2,					\
>>>> +	}
>>>> +
>>>> +static struct pinctrl_pin_desc an7583_pinctrl_pins[] = {
>>>> +	PINCTRL_PIN(2, "gpio0"),
>>>> +	PINCTRL_PIN(3, "gpio1"),
>>>> +	PINCTRL_PIN(4, "gpio2"),
>>>> +	PINCTRL_PIN(5, "gpio3"),
>>>> +	PINCTRL_PIN(6, "gpio4"),
>>>> +	PINCTRL_PIN(7, "gpio5"),
>>>> +	PINCTRL_PIN(8, "gpio6"),
>>>> +	PINCTRL_PIN(9, "gpio7"),
>>>> +	PINCTRL_PIN(10, "gpio8"),
>>>> +	PINCTRL_PIN(11, "gpio9"),
>>>> +	PINCTRL_PIN(12, "gpio10"),
>>>> +	PINCTRL_PIN(13, "gpio11"),
>>>> +	PINCTRL_PIN(14, "gpio12"),
>>>> +	PINCTRL_PIN(15, "gpio13"),
>>>> +	PINCTRL_PIN(16, "gpio14"),
>>>> +	PINCTRL_PIN(17, "gpio15"),
>>>> +	PINCTRL_PIN(18, "gpio16"),
>>>> +	PINCTRL_PIN(19, "gpio17"),
>>>> +	PINCTRL_PIN(20, "gpio18"),
>>>> +	PINCTRL_PIN(21, "gpio19"),
>>>> +	PINCTRL_PIN(22, "gpio20"),
>>>> +	PINCTRL_PIN(23, "gpio21"),
>>>> +	PINCTRL_PIN(24, "gpio22"),
>>>> +	PINCTRL_PIN(25, "gpio23"),
>>>> +	PINCTRL_PIN(26, "gpio24"),
>>>> +	PINCTRL_PIN(27, "gpio25"),
>>>> +	PINCTRL_PIN(28, "gpio26"),
>>>> +	PINCTRL_PIN(29, "gpio27"),
>>>> +	PINCTRL_PIN(30, "gpio28"),
>>>> +	PINCTRL_PIN(31, "gpio29"),
>>>> +	PINCTRL_PIN(32, "gpio30"),
>>>> +	PINCTRL_PIN(33, "gpio31"),
>>>> +	PINCTRL_PIN(34, "gpio32"),
>>>> +	PINCTRL_PIN(35, "gpio33"),
>>>> +	PINCTRL_PIN(36, "gpio34"),
>>>> +	PINCTRL_PIN(37, "gpio35"),
>>>> +	PINCTRL_PIN(38, "gpio36"),
>>>> +	PINCTRL_PIN(39, "gpio37"),
>>>> +	PINCTRL_PIN(40, "gpio38"),
>>>> +	PINCTRL_PIN(41, "i2c0_scl"),
>>>> +	PINCTRL_PIN(42, "i2c0_sda"),
>>>> +	PINCTRL_PIN(43, "i2c1_scl"),
>>>> +	PINCTRL_PIN(44, "i2c1_sda"),
>>>> +	PINCTRL_PIN(45, "spi_clk"),
>>>> +	PINCTRL_PIN(46, "spi_cs"),
>>>> +	PINCTRL_PIN(47, "spi_mosi"),
>>>> +	PINCTRL_PIN(48, "spi_miso"),
>>>> +	PINCTRL_PIN(49, "uart_txd"),
>>>> +	PINCTRL_PIN(50, "uart_rxd"),
>>>> +	PINCTRL_PIN(51, "pcie_reset0"),
>>>> +	PINCTRL_PIN(52, "pcie_reset1"),
>>>> +	PINCTRL_PIN(53, "mdc_0"),
>>>> +	PINCTRL_PIN(54, "mdio_0"),
>>>> +};
>>>> +
>>>> +static const int an7583_pon_pins[] = { 15, 16, 17, 18, 19, 20 };
>>>> +static const int an7583_pon_tod_1pps_pins[] = { 32 };
>>>> +static const int an7583_gsw_tod_1pps_pins[] = { 32 };
>>>> +static const int an7583_sipo_pins[] = { 34, 35 };
>>>> +static const int an7583_sipo_rclk_pins[] = { 34, 35, 33 };
>>>> +static const int an7583_mdio_pins[] = { 43, 44 };
>>>> +static const int an7583_uart2_pins[] = { 34, 35 };
>>>> +static const int an7583_uart2_cts_rts_pins[] = { 32, 33 };
>>>> +static const int an7583_hsuart_pins[] = { 30, 31 };
>>>> +static const int an7583_hsuart_cts_rts_pins[] = { 28, 29 };
>>>> +static const int an7583_npu_uart_pins[] = { 7, 8 };
>>>> +static const int an7583_uart4_pins[] = { 7, 8 };
>>>> +static const int an7583_uart5_pins[] = { 23, 24 };
>>>> +static const int an7583_i2c0_pins[] = { 41, 42 };
>>>> +static const int an7583_i2c1_pins[] = { 43, 44 };
>>>> +static const int an7583_jtag_udi_pins[] = { 23, 24, 22, 25, 26 };
>>>> +static const int an7583_jtag_dfd_pins[] = { 23, 24, 22, 25, 26 };
>>>> +static const int an7583_pcm1_pins[] = { 10, 11, 12, 13, 14 };
>>>> +static const int an7583_pcm2_pins[] = { 28, 29, 30, 31, 24 };
>>>> +static const int an7583_spi_pins[] = { 28, 29, 30, 31 };
>>>> +static const int an7583_spi_quad_pins[] = { 25, 26 };
>>>> +static const int an7583_spi_cs1_pins[] = { 27 };
>>>> +static const int an7583_pcm_spi_pins[] = { 28, 29, 30, 31, 10, 11, 12, 13 };
>>>> +static const int an7583_pcm_spi_rst_pins[] = { 14 };
>>>> +static const int an7583_pcm_spi_cs1_pins[] = { 24 };
>>>> +static const int an7583_emmc_pins[] = {
>>>> +	7, 8, 9, 22, 23, 24, 25, 26, 45, 46, 47
>>>> +};
>>>> +static const int an7583_pnand_pins[] = {
>>>> +	7, 8, 9, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 45, 46, 47, 48
>>>> +};
>>>> +static const int an7583_gpio0_pins[] = { 2 };
>>>> +static const int an7583_gpio1_pins[] = { 3 };
>>>> +static const int an7583_gpio2_pins[] = { 4 };
>>>> +static const int an7583_gpio3_pins[] = { 5 };
>>>> +static const int an7583_gpio4_pins[] = { 6 };
>>>> +static const int an7583_gpio5_pins[] = { 7 };
>>>> +static const int an7583_gpio6_pins[] = { 8 };
>>>> +static const int an7583_gpio7_pins[] = { 9 };
>>>> +static const int an7583_gpio8_pins[] = { 10 };
>>>> +static const int an7583_gpio9_pins[] = { 11 };
>>>> +static const int an7583_gpio10_pins[] = { 12 };
>>>> +static const int an7583_gpio11_pins[] = { 13 };
>>>> +static const int an7583_gpio12_pins[] = { 14 };
>>>> +static const int an7583_gpio13_pins[] = { 15 };
>>>> +static const int an7583_gpio14_pins[] = { 16 };
>>>> +static const int an7583_gpio15_pins[] = { 17 };
>>>> +static const int an7583_gpio16_pins[] = { 18 };
>>>> +static const int an7583_gpio17_pins[] = { 19 };
>>>> +static const int an7583_gpio18_pins[] = { 20 };
>>>> +static const int an7583_gpio19_pins[] = { 21 };
>>>> +static const int an7583_gpio20_pins[] = { 22 };
>>>> +static const int an7583_gpio21_pins[] = { 23 };
>>>> +static const int an7583_gpio22_pins[] = { 24 };
>>>> +static const int an7583_gpio23_pins[] = { 25 };
>>>> +static const int an7583_gpio24_pins[] = { 26 };
>>>> +static const int an7583_gpio25_pins[] = { 27 };
>>>> +static const int an7583_gpio26_pins[] = { 28 };
>>>> +static const int an7583_gpio27_pins[] = { 29 };
>>>> +static const int an7583_gpio28_pins[] = { 30 };
>>>> +static const int an7583_gpio29_pins[] = { 31 };
>>>> +static const int an7583_gpio30_pins[] = { 32 };
>>>> +static const int an7583_gpio31_pins[] = { 33 };
>>>> +static const int an7583_gpio32_pins[] = { 34 };
>>>> +static const int an7583_gpio33_pins[] = { 35 };
>>>> +static const int an7583_gpio34_pins[] = { 36 };
>>>> +static const int an7583_gpio35_pins[] = { 37 };
>>>> +static const int an7583_gpio36_pins[] = { 38 };
>>>> +static const int an7583_gpio37_pins[] = { 39 };
>>>> +static const int an7583_gpio38_pins[] = { 40 };
>>>> +static const int an7583_gpio39_pins[] = { 41 };
>>>> +static const int an7583_gpio40_pins[] = { 42 };
>>>> +static const int an7583_gpio41_pins[] = { 43 };
>>>> +static const int an7583_gpio42_pins[] = { 44 };
>>>> +static const int an7583_gpio43_pins[] = { 45 };
>>>> +static const int an7583_gpio44_pins[] = { 46 };
>>>> +static const int an7583_gpio45_pins[] = { 47 };
>>>> +static const int an7583_gpio46_pins[] = { 48 };
>>>> +static const int an7583_gpio47_pins[] = { 49 };
>>>> +static const int an7583_gpio48_pins[] = { 50 };
>>>> +static const int an7583_gpio49_pins[] = { 51 };
>>>> +static const int an7583_gpio50_pins[] = { 52 };
>>>> +static const int an7583_gpio51_pins[] = { 53 };
>>>> +static const int an7583_gpio52_pins[] = { 54 };
>>>> +static const int an7583_pcie_reset0_pins[] = { 51 };
>>>> +static const int an7583_pcie_reset1_pins[] = { 52 };
>>>> +
>>>> +static const struct pingroup an7583_pinctrl_groups[] = {
>>>> +	PINCTRL_PIN_GROUP("pon", an7583_pon),
>>>> +	PINCTRL_PIN_GROUP("pon_tod_1pps", an7583_pon_tod_1pps),
>>>> +	PINCTRL_PIN_GROUP("gsw_tod_1pps", an7583_gsw_tod_1pps),
>>>> +	PINCTRL_PIN_GROUP("sipo", an7583_sipo),
>>>> +	PINCTRL_PIN_GROUP("sipo_rclk", an7583_sipo_rclk),
>>>> +	PINCTRL_PIN_GROUP("mdio", an7583_mdio),
>>>> +	PINCTRL_PIN_GROUP("uart2", an7583_uart2),
>>>> +	PINCTRL_PIN_GROUP("uart2_cts_rts", an7583_uart2_cts_rts),
>>>> +	PINCTRL_PIN_GROUP("hsuart", an7583_hsuart),
>>>> +	PINCTRL_PIN_GROUP("hsuart_cts_rts", an7583_hsuart_cts_rts),
>>>> +	PINCTRL_PIN_GROUP("npu_uart", an7583_npu_uart),
>>>> +	PINCTRL_PIN_GROUP("uart4", an7583_uart4),
>>>> +	PINCTRL_PIN_GROUP("uart5", an7583_uart5),
>>>> +	PINCTRL_PIN_GROUP("i2c0", an7583_i2c0),
>>>> +	PINCTRL_PIN_GROUP("i2c1", an7583_i2c1),
>>>> +	PINCTRL_PIN_GROUP("jtag_udi", an7583_jtag_udi),
>>>> +	PINCTRL_PIN_GROUP("jtag_dfd", an7583_jtag_dfd),
>>>> +	PINCTRL_PIN_GROUP("pcm1", an7583_pcm1),
>>>> +	PINCTRL_PIN_GROUP("pcm2", an7583_pcm2),
>>>> +	PINCTRL_PIN_GROUP("spi", an7583_spi),
>>>> +	PINCTRL_PIN_GROUP("spi_quad", an7583_spi_quad),
>>>> +	PINCTRL_PIN_GROUP("spi_cs1", an7583_spi_cs1),
>>>> +	PINCTRL_PIN_GROUP("pcm_spi", an7583_pcm_spi),
>>>> +	PINCTRL_PIN_GROUP("pcm_spi_rst", an7583_pcm_spi_rst),
>>>> +	PINCTRL_PIN_GROUP("pcm_spi_cs1", an7583_pcm_spi_cs1),
>>>> +	PINCTRL_PIN_GROUP("emmc", an7583_emmc),
>>>> +	PINCTRL_PIN_GROUP("pnand", an7583_pnand),
>>>> +	PINCTRL_PIN_GROUP("gpio0", an7583_gpio0),
>>>> +	PINCTRL_PIN_GROUP("gpio1", an7583_gpio1),
>>>> +	PINCTRL_PIN_GROUP("gpio2", an7583_gpio2),
>>>> +	PINCTRL_PIN_GROUP("gpio3", an7583_gpio3),
>>>> +	PINCTRL_PIN_GROUP("gpio4", an7583_gpio4),
>>>> +	PINCTRL_PIN_GROUP("gpio5", an7583_gpio5),
>>>> +	PINCTRL_PIN_GROUP("gpio6", an7583_gpio6),
>>>> +	PINCTRL_PIN_GROUP("gpio7", an7583_gpio7),
>>>> +	PINCTRL_PIN_GROUP("gpio8", an7583_gpio8),
>>>> +	PINCTRL_PIN_GROUP("gpio9", an7583_gpio9),
>>>> +	PINCTRL_PIN_GROUP("gpio10", an7583_gpio10),
>>>> +	PINCTRL_PIN_GROUP("gpio11", an7583_gpio11),
>>>> +	PINCTRL_PIN_GROUP("gpio12", an7583_gpio12),
>>>> +	PINCTRL_PIN_GROUP("gpio13", an7583_gpio13),
>>>> +	PINCTRL_PIN_GROUP("gpio14", an7583_gpio14),
>>>> +	PINCTRL_PIN_GROUP("gpio15", an7583_gpio15),
>>>> +	PINCTRL_PIN_GROUP("gpio16", an7583_gpio16),
>>>> +	PINCTRL_PIN_GROUP("gpio17", an7583_gpio17),
>>>> +	PINCTRL_PIN_GROUP("gpio18", an7583_gpio18),
>>>> +	PINCTRL_PIN_GROUP("gpio19", an7583_gpio19),
>>>> +	PINCTRL_PIN_GROUP("gpio20", an7583_gpio20),
>>>> +	PINCTRL_PIN_GROUP("gpio21", an7583_gpio21),
>>>> +	PINCTRL_PIN_GROUP("gpio22", an7583_gpio22),
>>>> +	PINCTRL_PIN_GROUP("gpio23", an7583_gpio23),
>>>> +	PINCTRL_PIN_GROUP("gpio24", an7583_gpio24),
>>>> +	PINCTRL_PIN_GROUP("gpio25", an7583_gpio25),
>>>> +	PINCTRL_PIN_GROUP("gpio26", an7583_gpio26),
>>>> +	PINCTRL_PIN_GROUP("gpio27", an7583_gpio27),
>>>> +	PINCTRL_PIN_GROUP("gpio28", an7583_gpio28),
>>>> +	PINCTRL_PIN_GROUP("gpio29", an7583_gpio29),
>>>> +	PINCTRL_PIN_GROUP("gpio30", an7583_gpio30),
>>>> +	PINCTRL_PIN_GROUP("gpio31", an7583_gpio31),
>>>> +	PINCTRL_PIN_GROUP("gpio32", an7583_gpio32),
>>>> +	PINCTRL_PIN_GROUP("gpio33", an7583_gpio33),
>>>> +	PINCTRL_PIN_GROUP("gpio34", an7583_gpio34),
>>>> +	PINCTRL_PIN_GROUP("gpio35", an7583_gpio35),
>>>> +	PINCTRL_PIN_GROUP("gpio36", an7583_gpio36),
>>>> +	PINCTRL_PIN_GROUP("gpio37", an7583_gpio37),
>>>> +	PINCTRL_PIN_GROUP("gpio38", an7583_gpio38),
>>>> +	PINCTRL_PIN_GROUP("gpio39", an7583_gpio39),
>>>> +	PINCTRL_PIN_GROUP("gpio40", an7583_gpio40),
>>>> +	PINCTRL_PIN_GROUP("gpio41", an7583_gpio41),
>>>> +	PINCTRL_PIN_GROUP("gpio42", an7583_gpio42),
>>>> +	PINCTRL_PIN_GROUP("gpio43", an7583_gpio43),
>>>> +	PINCTRL_PIN_GROUP("gpio44", an7583_gpio44),
>>>> +	PINCTRL_PIN_GROUP("gpio45", an7583_gpio45),
>>>> +	PINCTRL_PIN_GROUP("gpio46", an7583_gpio46),
>>>> +	PINCTRL_PIN_GROUP("gpio47", an7583_gpio47),
>>>> +	PINCTRL_PIN_GROUP("gpio48", an7583_gpio48),
>>>> +	PINCTRL_PIN_GROUP("gpio49", an7583_gpio49),
>>>> +	PINCTRL_PIN_GROUP("gpio50", an7583_gpio50),
>>>> +	PINCTRL_PIN_GROUP("gpio51", an7583_gpio51),
>>>> +	PINCTRL_PIN_GROUP("gpio52", an7583_gpio52),
>>>> +	PINCTRL_PIN_GROUP("pcie_reset0", an7583_pcie_reset0),
>>>> +	PINCTRL_PIN_GROUP("pcie_reset1", an7583_pcie_reset1),
>>>> +};
>>>> +
>>>> +static const char *const pon_groups[] = { "pon" };
>>>> +static const char *const tod_1pps_groups[] = {
>>>> +	"pon_tod_1pps", "gsw_tod_1pps"
>>>> +};
>>>> +static const char *const sipo_groups[] = { "sipo", "sipo_rclk" };
>>>> +static const char *const an7583_mdio_groups[] = { "mdio" };
>>>> +static const char *const uart_groups[] = {
>>>> +	"uart2", "uart2_cts_rts", "hsuart", "hsuart_cts_rts",
>>>> +	"uart4", "uart5"
>>>> +};
>>>> +static const char *const jtag_groups[] = { "jtag_udi", "jtag_dfd" };
>>>> +static const char *const pcm_groups[] = { "pcm1", "pcm2" };
>>>> +static const char *const spi_groups[] = { "spi_quad", "spi_cs1" };
>>>> +static const char *const an7583_pcm_spi_groups[] = {
>>>> +	"pcm_spi", "pcm_spi_rst", "pcm_spi_cs1"
>>>> +};
>>>> +static const char *const emmc_groups[] = { "emmc" };
>>>> +static const char *const pnand_groups[] = { "pnand" };
>>>> +static const char *const an7583_gpio_groups[] = {
>>>> +	"gpio39", "gpio40", "gpio41", "gpio42", "gpio43",
>>>> +	"gpio44", "gpio45", "gpio46", "gpio47", "gpio48",
>>>> +	"gpio49", "gpio50", "gpio51", "gpio52"
>>>> +};
>>>> +static const char *const an7583_pcie_reset_groups[] = {
>>>> +	"pcie_reset0", "pcie_reset1"
>>>> +};
>>>> +static const char *const an7583_pwm_groups[] = {
>>>> +	"gpio0",  "gpio1",  "gpio2",  "gpio3",  "gpio4",  "gpio5",
>>>> +	"gpio6",  "gpio7",  "gpio8",  "gpio9",  "gpio10", "gpio11",
>>>> +	"gpio12", "gpio13", "gpio14", "gpio15", "gpio16", "gpio17",
>>>> +	"gpio18", "gpio19", "gpio20", "gpio21", "gpio22", "gpio23",
>>>> +	"gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29",
>>>> +	"gpio30", "gpio31", "gpio36", "gpio37", "gpio38", "gpio39",
>>>> +	"gpio40", "gpio41", "gpio42", "gpio43", "gpio44", "gpio45",
>>>> +	"gpio46", "gpio47", "gpio48", "gpio49", "gpio50", "gpio51"
>>>> +};
>>>> +static const char *const an7583_phy1_led0_groups[] = {
>>>> +	"gpio1", "gpio2", "gpio3", "gpio4"
>>>> +};
>>>> +static const char *const an7583_phy2_led0_groups[] = {
>>>> +	"gpio1", "gpio2", "gpio3", "gpio4"
>>>> +};
>>>> +static const char *const an7583_phy3_led0_groups[] = {
>>>> +	"gpio1", "gpio2", "gpio3", "gpio4"
>>>> +};
>>>> +static const char *const an7583_phy4_led0_groups[] = {
>>>> +	"gpio1", "gpio2", "gpio3", "gpio4"
>>>> +};
>>>> +static const char *const an7583_phy1_led1_groups[] = {
>>>> +	"gpio8", "gpio9", "gpio10", "gpio11"
>>>> +};
>>>> +static const char *const an7583_phy2_led1_groups[] = {
>>>> +	"gpio8", "gpio9", "gpio10", "gpio11"
>>>> +};
>>>> +static const char *const an7583_phy3_led1_groups[] = {
>>>> +	"gpio8", "gpio9", "gpio10", "gpio11"
>>>> +};
>>>> +static const char *const an7583_phy4_led1_groups[] = {
>>>> +	"gpio8", "gpio9", "gpio10", "gpio11"
>>>> +};
>>>> +
>>>> +static const struct airoha_pinctrl_func_group pon_func_group[] = {
>>>> +	{
>>>> +		.name = "pon",
>>>> +		.regmap[0] = {
>>>> +			AIROHA_FUNC_MUX,
>>>> +			REG_GPIO_PON_MODE,
>>>> +			GPIO_PON_MODE_MASK,
>>>> +			GPIO_PON_MODE_MASK
>>>> +		},
>>>> +		.regmap_size = 1,
>>>> +	},
>>>> +};
>>>> +
>>>> +static const struct airoha_pinctrl_func_group tod_1pps_func_group[] = {
>>>> +	{
>>>> +		.name = "pon_tod_1pps",
>>>> +		.regmap[0] = {
>>>> +			AIROHA_FUNC_MUX,
>>>> +			REG_GPIO_2ND_I2C_MODE,
>>>> +			PON_TOD_1PPS_MODE_MASK,
>>>> +			PON_TOD_1PPS_MODE_MASK
>>>> +		},
>>>> +		.regmap_size = 1,
>>>> +	}, {
>>>> +		.name = "gsw_tod_1pps",
>>>> +		.regmap[0] = {
>>>> +			AIROHA_FUNC_MUX,
>>>> +			REG_GPIO_2ND_I2C_MODE,
>>>> +			GSW_TOD_1PPS_MODE_MASK,
>>>> +			GSW_TOD_1PPS_MODE_MASK
>>>> +		},
>>>> +		.regmap_size = 1,
>>>> +	},
>>>> +};
>>>> +
>>>> +static const struct airoha_pinctrl_func_group sipo_func_group[] = {
>>>> +	{
>>>> +		.name = "sipo",
>>>> +		.regmap[0] = {
>>>> +			AIROHA_FUNC_MUX,
>>>> +			REG_GPIO_PON_MODE,
>>>> +			GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK,
>>>> +			GPIO_SIPO_MODE_MASK
>>>> +		},
>>>> +		.regmap_size = 1,
>>>> +	}, {
>>>> +		.name = "sipo_rclk",
>>>> +		.regmap[0] = {
>>>> +			AIROHA_FUNC_MUX,
>>>> +			REG_GPIO_PON_MODE,
>>>> +			GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK,
>>>> +			GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK
>>>> +		},
>>>> +		.regmap_size = 1,
>>>> +	},
>>>> +};
>>>> +
>>>> +static const struct airoha_pinctrl_func_group an7583_mdio_func_group[] = {
>>>> +	{
>>>> +		.name = "mdio",
>>>> +		.regmap[0] = {
>>>> +			AIROHA_FUNC_MUX,
>>>> +			REG_GPIO_PON_MODE,
>>>> +			GPIO_SGMII_MDIO_MODE_MASK,
>>>> +			GPIO_SGMII_MDIO_MODE_MASK
>>>> +		},
>>>> +		.regmap[1] = {
>>>> +			AIROHA_FUNC_MUX,
>>>> +			REG_GPIO_SPI_CS1_MODE,
>>>> +			GPIO_MDC_IO_MASTER_MODE_MASK,
>>>> +			GPIO_MDC_IO_MASTER_MODE_MASK
>>>> +		},
>>>> +		.regmap_size = 2,
>>>> +	},
>>>> +};
>>>> +
>>>> +static const struct airoha_pinctrl_func_group uart_func_group[] = {
>>>> +	{
>>>> +		.name = "uart2",
>>>> +		.regmap[0] = {
>>>> +			AIROHA_FUNC_MUX,
>>>> +			REG_GPIO_PON_MODE,
>>>> +			GPIO_UART2_MODE_MASK,
>>>> +			GPIO_UART2_MODE_MASK
>>>> +		},
>>>> +		.regmap_size = 1,
>>>> +	}, {
>>>> +		.name = "uart2_cts_rts",
>>>> +		.regmap[0] = {
>>>> +			AIROHA_FUNC_MUX,
>>>> +			REG_GPIO_PON_MODE,
>>>> +			GPIO_UART2_MODE_MASK | GPIO_UART2_CTS_RTS_MODE_MASK,
>>>> +			GPIO_UART2_MODE_MASK | GPIO_UART2_CTS_RTS_MODE_MASK
>>>> +		},
>>>> +		.regmap_size = 1,
>>>> +	}, {
>>>> +		.name = "hsuart",
>>>> +		.regmap[0] = {
>>>> +			AIROHA_FUNC_MUX,
>>>> +			REG_GPIO_PON_MODE,
>>>> +			GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK,
>>>> +			GPIO_HSUART_MODE_MASK
>>>> +		},
>>>> +		.regmap_size = 1,
>>>> +	},
>>>> +	{
>>>> +		.name = "hsuart_cts_rts",
>>>> +		.regmap[0] = {
>>>> +			AIROHA_FUNC_MUX,
>>>> +			REG_GPIO_PON_MODE,
>>>> +			GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK,
>>>> +			GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK
>>>> +		},
>>>> +		.regmap_size = 1,
>>>> +	}, {
>>>> +		.name = "uart4",
>>>> +		.regmap[0] = {
>>>> +			AIROHA_FUNC_MUX,
>>>> +			REG_GPIO_PON_MODE,
>>>> +			GPIO_UART4_MODE_MASK,
>>>> +			GPIO_UART4_MODE_MASK
>>>> +		},
>>>> +		.regmap_size = 1,
>>>> +	}, {
>>>> +		.name = "uart5",
>>>> +		.regmap[0] = {
>>>> +			AIROHA_FUNC_MUX,
>>>> +			REG_GPIO_PON_MODE,
>>>> +			GPIO_UART5_MODE_MASK,
>>>> +			GPIO_UART5_MODE_MASK
>>>> +		},
>>>> +		.regmap_size = 1,
>>>> +	},
>>>> +};
>>>> +
>>>> +static const struct airoha_pinctrl_func_group jtag_func_group[] = {
>>>> +	{
>>>> +		.name = "jtag_udi",
>>>> +		.regmap[0] = {
>>>> +			AIROHA_FUNC_MUX,
>>>> +			REG_NPU_UART_EN,
>>>> +			JTAG_UDI_EN_MASK,
>>>> +			JTAG_UDI_EN_MASK
>>>> +		},
>>>> +		.regmap_size = 1,
>>>> +	}, {
>>>> +		.name = "jtag_dfd",
>>>> +		.regmap[0] = {
>>>> +			AIROHA_FUNC_MUX,
>>>> +			REG_NPU_UART_EN,
>>>> +			JTAG_DFD_EN_MASK,
>>>> +			JTAG_DFD_EN_MASK
>>>> +		},
>>>> +		.regmap_size = 1,
>>>> +	},
>>>> +};
>>>> +
>>>> +static const struct airoha_pinctrl_func_group pcm_func_group[] = {
>>>> +	{
>>>> +		.name = "pcm1",
>>>> +		.regmap[0] = {
>>>> +			AIROHA_FUNC_MUX,
>>>> +			REG_GPIO_SPI_CS1_MODE,
>>>> +			GPIO_PCM1_MODE_MASK,
>>>> +			GPIO_PCM1_MODE_MASK
>>>> +		},
>>>> +		.regmap_size = 1,
>>>> +	}, {
>>>> +		.name = "pcm2",
>>>> +		.regmap[0] = {
>>>> +			AIROHA_FUNC_MUX,
>>>> +			REG_GPIO_SPI_CS1_MODE,
>>>> +			GPIO_PCM2_MODE_MASK,
>>>> +			GPIO_PCM2_MODE_MASK
>>>> +		},
>>>> +		.regmap_size = 1,
>>>> +	},
>>>> +};
>>>> +
>>>> +static const struct airoha_pinctrl_func_group spi_func_group[] = {
>>>> +	{
>>>> +		.name = "spi_quad",
>>>> +		.regmap[0] = {
>>>> +			AIROHA_FUNC_MUX,
>>>> +			REG_GPIO_SPI_CS1_MODE,
>>>> +			GPIO_SPI_QUAD_MODE_MASK,
>>>> +			GPIO_SPI_QUAD_MODE_MASK
>>>> +		},
>>>> +		.regmap_size = 1,
>>>> +	}, {
>>>> +		.name = "spi_cs1",
>>>> +		.regmap[0] = {
>>>> +			AIROHA_FUNC_MUX,
>>>> +			REG_GPIO_SPI_CS1_MODE,
>>>> +			GPIO_SPI_CS1_MODE_MASK,
>>>> +			GPIO_SPI_CS1_MODE_MASK
>>>> +		},
>>>> +		.regmap_size = 1,
>>>> +	}, {
>>>> +		.name = "spi_cs2",
>>>> +		.regmap[0] = {
>>>> +			AIROHA_FUNC_MUX,
>>>> +			REG_GPIO_SPI_CS1_MODE,
>>>> +			GPIO_SPI_CS2_MODE_MASK,
>>>> +			GPIO_SPI_CS2_MODE_MASK
>>>> +		},
>>>> +		.regmap_size = 1,
>>>> +	}, {
>>>> +		.name = "spi_cs3",
>>>> +		.regmap[0] = {
>>>> +			AIROHA_FUNC_MUX,
>>>> +			REG_GPIO_SPI_CS1_MODE,
>>>> +			GPIO_SPI_CS3_MODE_MASK,
>>>> +			GPIO_SPI_CS3_MODE_MASK
>>>> +		},
>>>> +		.regmap_size = 1,
>>>> +	}, {
>>>> +		.name = "spi_cs4",
>>>> +		.regmap[0] = {
>>>> +			AIROHA_FUNC_MUX,
>>>> +			REG_GPIO_SPI_CS1_MODE,
>>>> +			GPIO_SPI_CS4_MODE_MASK,
>>>> +			GPIO_SPI_CS4_MODE_MASK
>>>> +		},
>>>> +		.regmap_size = 1,
>>>> +	},
>>>> +};
>>>> +
>>>> +static const struct airoha_pinctrl_func_group an7583_pcm_spi_func_group[] = {
>>>> +	{
>>>> +		.name = "pcm_spi",
>>>> +		.regmap[0] = {
>>>> +			AIROHA_FUNC_MUX,
>>>> +			REG_GPIO_SPI_CS1_MODE,
>>>> +			GPIO_PCM_SPI_MODE_MASK,
>>>> +			GPIO_PCM_SPI_MODE_MASK
>>>> +		},
>>>> +		.regmap_size = 1,
>>>> +	}, {
>>>> +		.name = "pcm_spi_int",
>>>> +		.regmap[0] = {
>>>> +			AIROHA_FUNC_MUX,
>>>> +			REG_GPIO_SPI_CS1_MODE,
>>>> +			GPIO_PCM_INT_MODE_MASK,
>>>> +			GPIO_PCM_INT_MODE_MASK
>>>> +		},
>>>> +		.regmap_size = 1,
>>>> +	}, {
>>>> +		.name = "pcm_spi_rst",
>>>> +		.regmap[0] = {
>>>> +			AIROHA_FUNC_MUX,
>>>> +			REG_GPIO_SPI_CS1_MODE,
>>>> +			GPIO_PCM_RESET_MODE_MASK,
>>>> +			GPIO_PCM_RESET_MODE_MASK
>>>> +		},
>>>> +		.regmap_size = 1,
>>>> +	}, {
>>>> +		.name = "pcm_spi_cs1",
>>>> +		.regmap[0] = {
>>>> +			AIROHA_FUNC_MUX,
>>>> +			REG_GPIO_SPI_CS1_MODE,
>>>> +			GPIO_PCM_SPI_CS1_MODE_MASK,
>>>> +			GPIO_PCM_SPI_CS1_MODE_MASK
>>>> +		},
>>>> +		.regmap_size = 1,
>>>> +	}, {
>>>> +		.name = "pcm_spi_cs2",
>>>> +		.regmap[0] = {
>>>> +			AIROHA_FUNC_MUX,
>>>> +			REG_GPIO_SPI_CS1_MODE,
>>>> +			AN7583_GPIO_PCM_SPI_CS2_MODE_MASK,
>>>> +			AN7583_GPIO_PCM_SPI_CS2_MODE_MASK
>>>> +		},
>>>> +		.regmap_size = 1,
>>>> +	}, {
>>>> +		.name = "pcm_spi_cs3",
>>>> +		.regmap[0] = {
>>>> +			AIROHA_FUNC_MUX,
>>>> +			REG_GPIO_SPI_CS1_MODE,
>>>> +			GPIO_PCM_SPI_CS3_MODE_MASK,
>>>> +			GPIO_PCM_SPI_CS3_MODE_MASK
>>>> +		},
>>>> +		.regmap_size = 1,
>>>> +	}, {
>>>> +		.name = "pcm_spi_cs4",
>>>> +		.regmap[0] = {
>>>> +			AIROHA_FUNC_MUX,
>>>> +			REG_GPIO_SPI_CS1_MODE,
>>>> +			GPIO_PCM_SPI_CS4_MODE_MASK,
>>>> +			GPIO_PCM_SPI_CS4_MODE_MASK
>>>> +		},
>>>> +		.regmap_size = 1,
>>>> +	},
>>>> +};
>>>> +
>>>> +static const struct airoha_pinctrl_func_group emmc_func_group[] = {
>>>> +	{
>>>> +		.name = "emmc",
>>>> +		.regmap[0] = {
>>>> +			AIROHA_FUNC_MUX,
>>>> +			REG_GPIO_PON_MODE,
>>>> +			GPIO_EMMC_MODE_MASK,
>>>> +			GPIO_EMMC_MODE_MASK
>>>> +		},
>>>> +		.regmap_size = 1,
>>>> +	},
>>>> +};
>>>> +
>>>> +static const struct airoha_pinctrl_func_group pnand_func_group[] = {
>>>> +	{
>>>> +		.name = "pnand",
>>>> +		.regmap[0] = {
>>>> +			AIROHA_FUNC_MUX,
>>>> +			REG_GPIO_PON_MODE,
>>>> +			GPIO_PARALLEL_NAND_MODE_MASK,
>>>> +			GPIO_PARALLEL_NAND_MODE_MASK
>>>> +		},
>>>> +		.regmap_size = 1,
>>>> +	},
>>>> +};
>>>> +
>>>> +static const struct airoha_pinctrl_func_group an7583_gpio_func_group[] = {
>>>> +	AIROHA_PINCTRL_GPIO_EXT("gpio39", GPIO39_FLASH_MODE_CFG,
>>>> +				AN7583_I2C0_SCL_GPIO_MODE_MASK),
>>>> +	AIROHA_PINCTRL_GPIO_EXT("gpio40", GPIO40_FLASH_MODE_CFG,
>>>> +				AN7583_I2C0_SDA_GPIO_MODE_MASK),
>>>> +	AIROHA_PINCTRL_GPIO_EXT("gpio41", GPIO41_FLASH_MODE_CFG,
>>>> +				AN7583_I2C1_SCL_GPIO_MODE_MASK),
>>>> +	AIROHA_PINCTRL_GPIO_EXT("gpio42", GPIO42_FLASH_MODE_CFG,
>>>> +				AN7583_I2C1_SDA_GPIO_MODE_MASK),
>>>> +	AIROHA_PINCTRL_GPIO_EXT("gpio43", GPIO43_FLASH_MODE_CFG,
>>>> +				AN7583_SPI_CLK_GPIO_MODE_MASK),
>>>> +	AIROHA_PINCTRL_GPIO_EXT("gpio44", GPIO44_FLASH_MODE_CFG,
>>>> +				AN7583_SPI_CS_GPIO_MODE_MASK),
>>>> +	AIROHA_PINCTRL_GPIO_EXT("gpio45", GPIO45_FLASH_MODE_CFG,
>>>> +				AN7583_SPI_MOSI_GPIO_MODE_MASK),
>>>> +	AIROHA_PINCTRL_GPIO_EXT("gpio46", GPIO46_FLASH_MODE_CFG,
>>>> +				AN7583_SPI_MISO_GPIO_MODE_MASK),
>>>> +	AIROHA_PINCTRL_GPIO_EXT("gpio47", GPIO47_FLASH_MODE_CFG,
>>>> +				AN7583_UART_TXD_GPIO_MODE_MASK),
>>>> +	AIROHA_PINCTRL_GPIO_EXT("gpio48", GPIO48_FLASH_MODE_CFG,
>>>> +				AN7583_UART_RXD_GPIO_MODE_MASK),
>>>> +	AIROHA_PINCTRL_GPIO_EXT("gpio49", GPIO49_FLASH_MODE_CFG,
>>>> +				GPIO_PCIE_RESET0_MASK),
>>>> +	AIROHA_PINCTRL_GPIO_EXT("gpio50", GPIO50_FLASH_MODE_CFG,
>>>> +				GPIO_PCIE_RESET1_MASK),
>>>> +	AIROHA_PINCTRL_GPIO_EXT("gpio51", GPIO51_FLASH_MODE_CFG,
>>>> +				AN7583_MDC_0_GPIO_MODE_MASK),
>>>> +	AIROHA_PINCTRL_GPIO("gpio52", AN7583_MDIO_0_GPIO_MODE_MASK),
>>>> +};
>>>> +
>>>> +static const struct airoha_pinctrl_func_group an7583_pcie_reset_func_group[] = {
>>>> +	{
>>>> +		.name = "pcie_reset0",
>>>> +		.regmap[0] = {
>>>> +			AIROHA_FUNC_MUX,
>>>> +			REG_GPIO_PON_MODE,
>>>> +			GPIO_PCIE_RESET0_MASK,
>>>> +			0
>>>> +		},
>>>> +		.regmap_size = 1,
>>>> +	}, {
>>>> +		.name = "pcie_reset1",
>>>> +		.regmap[0] = {
>>>> +			AIROHA_FUNC_MUX,
>>>> +			REG_GPIO_PON_MODE,
>>>> +			GPIO_PCIE_RESET1_MASK,
>>>> +			0
>>>> +		},
>>>> +		.regmap_size = 1,
>>>> +	},
>>>> +};
>>>> +
>>>> +static const struct airoha_pinctrl_func_group an7583_pwm_func_group[] = {
>>>> +	AIROHA_PINCTRL_PWM("gpio0", GPIO0_FLASH_MODE_CFG),
>>>> +	AIROHA_PINCTRL_PWM("gpio1", GPIO1_FLASH_MODE_CFG),
>>>> +	AIROHA_PINCTRL_PWM("gpio2", GPIO2_FLASH_MODE_CFG),
>>>> +	AIROHA_PINCTRL_PWM("gpio3", GPIO3_FLASH_MODE_CFG),
>>>> +	AIROHA_PINCTRL_PWM("gpio4", GPIO4_FLASH_MODE_CFG),
>>>> +	AIROHA_PINCTRL_PWM("gpio5", GPIO5_FLASH_MODE_CFG),
>>>> +	AIROHA_PINCTRL_PWM("gpio6", GPIO6_FLASH_MODE_CFG),
>>>> +	AIROHA_PINCTRL_PWM("gpio7", GPIO7_FLASH_MODE_CFG),
>>>> +	AIROHA_PINCTRL_PWM("gpio8", GPIO8_FLASH_MODE_CFG),
>>>> +	AIROHA_PINCTRL_PWM("gpio9", GPIO9_FLASH_MODE_CFG),
>>>> +	AIROHA_PINCTRL_PWM("gpio10", GPIO10_FLASH_MODE_CFG),
>>>> +	AIROHA_PINCTRL_PWM("gpio11", GPIO11_FLASH_MODE_CFG),
>>>> +	AIROHA_PINCTRL_PWM("gpio12", GPIO12_FLASH_MODE_CFG),
>>>> +	AIROHA_PINCTRL_PWM("gpio13", GPIO13_FLASH_MODE_CFG),
>>>> +	AIROHA_PINCTRL_PWM("gpio14", GPIO14_FLASH_MODE_CFG),
>>>> +	AIROHA_PINCTRL_PWM("gpio15", GPIO15_FLASH_MODE_CFG),
>>>> +	AIROHA_PINCTRL_PWM_EXT("gpio16", GPIO16_FLASH_MODE_CFG),
>>>> +	AIROHA_PINCTRL_PWM_EXT("gpio17", GPIO17_FLASH_MODE_CFG),
>>>> +	AIROHA_PINCTRL_PWM_EXT("gpio18", GPIO18_FLASH_MODE_CFG),
>>>> +	AIROHA_PINCTRL_PWM_EXT("gpio19", GPIO19_FLASH_MODE_CFG),
>>>> +	AIROHA_PINCTRL_PWM_EXT("gpio20", GPIO20_FLASH_MODE_CFG),
>>>> +	AIROHA_PINCTRL_PWM_EXT("gpio21", GPIO21_FLASH_MODE_CFG),
>>>> +	AIROHA_PINCTRL_PWM_EXT("gpio22", GPIO22_FLASH_MODE_CFG),
>>>> +	AIROHA_PINCTRL_PWM_EXT("gpio23", GPIO23_FLASH_MODE_CFG),
>>>> +	AIROHA_PINCTRL_PWM_EXT("gpio24", GPIO24_FLASH_MODE_CFG),
>>>> +	AIROHA_PINCTRL_PWM_EXT("gpio25", GPIO25_FLASH_MODE_CFG),
>>>> +	AIROHA_PINCTRL_PWM_EXT("gpio26", GPIO26_FLASH_MODE_CFG),
>>>> +	AIROHA_PINCTRL_PWM_EXT("gpio27", GPIO27_FLASH_MODE_CFG),
>>>> +	AIROHA_PINCTRL_PWM_EXT("gpio28", GPIO28_FLASH_MODE_CFG),
>>>> +	AIROHA_PINCTRL_PWM_EXT("gpio29", GPIO29_FLASH_MODE_CFG),
>>>> +	AIROHA_PINCTRL_PWM_EXT("gpio30", GPIO30_FLASH_MODE_CFG),
>>>> +	AIROHA_PINCTRL_PWM_EXT("gpio31", GPIO31_FLASH_MODE_CFG),
>>>> +	AIROHA_PINCTRL_PWM_EXT("gpio36", GPIO36_FLASH_MODE_CFG),
>>>> +	AIROHA_PINCTRL_PWM_EXT("gpio37", GPIO37_FLASH_MODE_CFG),
>>>> +	AIROHA_PINCTRL_PWM_EXT("gpio38", GPIO38_FLASH_MODE_CFG),
>>>> +	AIROHA_PINCTRL_PWM_EXT_SEC("gpio39", GPIO39_FLASH_MODE_CFG,
>>>> +				   AN7583_I2C0_SCL_GPIO_MODE_MASK),
>>>> +	AIROHA_PINCTRL_PWM_EXT_SEC("gpio40", GPIO40_FLASH_MODE_CFG,
>>>> +				   AN7583_I2C0_SDA_GPIO_MODE_MASK),
>>>> +	AIROHA_PINCTRL_PWM_EXT_SEC("gpio41", GPIO41_FLASH_MODE_CFG,
>>>> +				   AN7583_I2C1_SCL_GPIO_MODE_MASK),
>>>> +	AIROHA_PINCTRL_PWM_EXT_SEC("gpio42", GPIO42_FLASH_MODE_CFG,
>>>> +				   AN7583_I2C1_SDA_GPIO_MODE_MASK),
>>>> +	AIROHA_PINCTRL_PWM_EXT_SEC("gpio43", GPIO43_FLASH_MODE_CFG,
>>>> +				   AN7583_SPI_CLK_GPIO_MODE_MASK),
>>>> +	AIROHA_PINCTRL_PWM_EXT_SEC("gpio44", GPIO44_FLASH_MODE_CFG,
>>>> +				   AN7583_SPI_CS_GPIO_MODE_MASK),
>>>> +	AIROHA_PINCTRL_PWM_EXT_SEC("gpio45", GPIO45_FLASH_MODE_CFG,
>>>> +				   AN7583_SPI_MOSI_GPIO_MODE_MASK),
>>>> +	AIROHA_PINCTRL_PWM_EXT_SEC("gpio46", GPIO46_FLASH_MODE_CFG,
>>>> +				   AN7583_SPI_MISO_GPIO_MODE_MASK),
>>>> +	AIROHA_PINCTRL_PWM_EXT_SEC("gpio47", GPIO47_FLASH_MODE_CFG,
>>>> +				   AN7583_UART_TXD_GPIO_MODE_MASK),
>>>> +	AIROHA_PINCTRL_PWM_EXT_SEC("gpio48", GPIO48_FLASH_MODE_CFG,
>>>> +				   AN7583_UART_RXD_GPIO_MODE_MASK),
>>>> +	AIROHA_PINCTRL_PWM_EXT_SEC("gpio49", GPIO49_FLASH_MODE_CFG,
>>>> +				   GPIO_PCIE_RESET0_MASK),
>>>> +	AIROHA_PINCTRL_PWM_EXT_SEC("gpio50", GPIO50_FLASH_MODE_CFG,
>>>> +				   GPIO_PCIE_RESET1_MASK),
>>>> +	AIROHA_PINCTRL_PWM_EXT_SEC("gpio51", GPIO51_FLASH_MODE_CFG,
>>>> +				   AN7583_MDC_0_GPIO_MODE_MASK),
>>>> +};
>>>> +
>>>> +static const struct airoha_pinctrl_func_group an7583_phy1_led0_func_group[] = {
>>>> +	AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK,
>>>> +				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),
>>>> +	AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK,
>>>> +				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)),
>>>> +	AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK,
>>>> +				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)),
>>>> +	AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK,
>>>> +				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),
>>>> +};
>>>> +
>>>> +static const struct airoha_pinctrl_func_group an7583_phy2_led0_func_group[] = {
>>>> +	AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK,
>>>> +				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),
>>>> +	AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK,
>>>> +				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)),
>>>> +	AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK,
>>>> +				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)),
>>>> +	AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK,
>>>> +				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),
>>>> +};
>>>> +
>>>> +static const struct airoha_pinctrl_func_group an7583_phy3_led0_func_group[] = {
>>>> +	AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK,
>>>> +				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
>>>> +	AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK,
>>>> +				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),
>>>> +	AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK,
>>>> +				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),
>>>> +	AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK,
>>>> +				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
>>>> +};
>>>> +
>>>> +static const struct airoha_pinctrl_func_group an7583_phy4_led0_func_group[] = {
>>>> +	AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK,
>>>> +				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)),
>>>> +	AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK,
>>>> +				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)),
>>>> +	AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK,
>>>> +				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)),
>>>> +	AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK,
>>>> +				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)),
>>>> +};
>>>> +
>>>> +static const struct airoha_pinctrl_func_group an7583_phy1_led1_func_group[] = {
>>>> +	AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK,
>>>> +				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),
>>>> +	AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK,
>>>> +				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)),
>>>> +	AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK,
>>>> +				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)),
>>>> +	AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK,
>>>> +				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),
>>>> +};
>>>> +
>>>> +static const struct airoha_pinctrl_func_group an7583_phy2_led1_func_group[] = {
>>>> +	AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK,
>>>> +				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),
>>>> +	AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK,
>>>> +				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)),
>>>> +	AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK,
>>>> +				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)),
>>>> +	AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK,
>>>> +				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),
>>>> +};
>>>> +
>>>> +static const struct airoha_pinctrl_func_group an7583_phy3_led1_func_group[] = {
>>>> +	AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK,
>>>> +				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
>>>> +	AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK,
>>>> +				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),
>>>> +	AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK,
>>>> +				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),
>>>> +	AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK,
>>>> +				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
>>>> +};
>>>> +
>>>> +static const struct airoha_pinctrl_func_group an7583_phy4_led1_func_group[] = {
>>>> +	AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK,
>>>> +				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)),
>>>> +	AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK,
>>>> +				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)),
>>>> +	AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK,
>>>> +				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)),
>>>> +	AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK,
>>>> +				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)),
>>>> +};
>>>> +
>>>> +static const struct airoha_pinctrl_func an7583_pinctrl_funcs[] = {
>>>> +	PINCTRL_FUNC_DESC("pon", pon),
>>>> +	PINCTRL_FUNC_DESC("tod_1pps", tod_1pps),
>>>> +	PINCTRL_FUNC_DESC("sipo", sipo),
>>>> +	PINCTRL_FUNC_DESC("mdio", an7583_mdio),
>>>> +	PINCTRL_FUNC_DESC("uart", uart),
>>>> +	PINCTRL_FUNC_DESC("jtag", jtag),
>>>> +	PINCTRL_FUNC_DESC("pcm", pcm),
>>>> +	PINCTRL_FUNC_DESC("spi", spi),
>>>> +	PINCTRL_FUNC_DESC("pcm_spi", an7583_pcm_spi),
>>>> +	PINCTRL_FUNC_DESC("emmc", emmc),
>>>> +	PINCTRL_FUNC_DESC("pnand", pnand),
>>>> +	PINCTRL_FUNC_DESC("gpio", an7583_gpio),
>>>> +	PINCTRL_FUNC_DESC("pcie_reset", an7583_pcie_reset),
>>>> +	PINCTRL_FUNC_DESC("pwm", an7583_pwm),
>>>> +	PINCTRL_FUNC_DESC("phy1_led0", an7583_phy1_led0),
>>>> +	PINCTRL_FUNC_DESC("phy2_led0", an7583_phy2_led0),
>>>> +	PINCTRL_FUNC_DESC("phy3_led0", an7583_phy3_led0),
>>>> +	PINCTRL_FUNC_DESC("phy4_led0", an7583_phy4_led0),
>>>> +	PINCTRL_FUNC_DESC("phy1_led1", an7583_phy1_led1),
>>>> +	PINCTRL_FUNC_DESC("phy2_led1", an7583_phy2_led1),
>>>> +	PINCTRL_FUNC_DESC("phy3_led1", an7583_phy3_led1),
>>>> +	PINCTRL_FUNC_DESC("phy4_led1", an7583_phy4_led1),
>>>> +};
>>>> +
>>>> +static const struct airoha_pinctrl_conf an7583_pinctrl_pullup_conf[] = {
>>>> +	PINCTRL_CONF_DESC(2, REG_GPIO_L_PU, BIT(0)),
>>>> +	PINCTRL_CONF_DESC(3, REG_GPIO_L_PU, BIT(1)),
>>>> +	PINCTRL_CONF_DESC(4, REG_GPIO_L_PU, BIT(2)),
>>>> +	PINCTRL_CONF_DESC(5, REG_GPIO_L_PU, BIT(3)),
>>>> +	PINCTRL_CONF_DESC(6, REG_GPIO_L_PU, BIT(4)),
>>>> +	PINCTRL_CONF_DESC(7, REG_GPIO_L_PU, BIT(5)),
>>>> +	PINCTRL_CONF_DESC(8, REG_GPIO_L_PU, BIT(6)),
>>>> +	PINCTRL_CONF_DESC(9, REG_GPIO_L_PU, BIT(7)),
>>>> +	PINCTRL_CONF_DESC(10, REG_GPIO_L_PU, BIT(8)),
>>>> +	PINCTRL_CONF_DESC(11, REG_GPIO_L_PU, BIT(9)),
>>>> +	PINCTRL_CONF_DESC(12, REG_GPIO_L_PU, BIT(10)),
>>>> +	PINCTRL_CONF_DESC(13, REG_GPIO_L_PU, BIT(11)),
>>>> +	PINCTRL_CONF_DESC(14, REG_GPIO_L_PU, BIT(12)),
>>>> +	PINCTRL_CONF_DESC(15, REG_GPIO_L_PU, BIT(13)),
>>>> +	PINCTRL_CONF_DESC(16, REG_GPIO_L_PU, BIT(14)),
>>>> +	PINCTRL_CONF_DESC(17, REG_GPIO_L_PU, BIT(15)),
>>>> +	PINCTRL_CONF_DESC(18, REG_GPIO_L_PU, BIT(16)),
>>>> +	PINCTRL_CONF_DESC(19, REG_GPIO_L_PU, BIT(17)),
>>>> +	PINCTRL_CONF_DESC(20, REG_GPIO_L_PU, BIT(18)),
>>>> +	PINCTRL_CONF_DESC(21, REG_GPIO_L_PU, BIT(19)),
>>>> +	PINCTRL_CONF_DESC(22, REG_GPIO_L_PU, BIT(20)),
>>>> +	PINCTRL_CONF_DESC(23, REG_GPIO_L_PU, BIT(21)),
>>>> +	PINCTRL_CONF_DESC(24, REG_GPIO_L_PU, BIT(22)),
>>>> +	PINCTRL_CONF_DESC(25, REG_GPIO_L_PU, BIT(23)),
>>>> +	PINCTRL_CONF_DESC(26, REG_GPIO_L_PU, BIT(24)),
>>>> +	PINCTRL_CONF_DESC(27, REG_GPIO_L_PU, BIT(25)),
>>>> +	PINCTRL_CONF_DESC(28, REG_GPIO_L_PU, BIT(26)),
>>>> +	PINCTRL_CONF_DESC(29, REG_GPIO_L_PU, BIT(27)),
>>>> +	PINCTRL_CONF_DESC(30, REG_GPIO_L_PU, BIT(28)),
>>>> +	PINCTRL_CONF_DESC(31, REG_GPIO_L_PU, BIT(29)),
>>>> +	PINCTRL_CONF_DESC(32, REG_GPIO_L_PU, BIT(30)),
>>>> +	PINCTRL_CONF_DESC(33, REG_GPIO_L_PU, BIT(31)),
>>>> +	PINCTRL_CONF_DESC(34, REG_GPIO_H_PU, BIT(0)),
>>>> +	PINCTRL_CONF_DESC(35, REG_GPIO_H_PU, BIT(1)),
>>>> +	PINCTRL_CONF_DESC(36, REG_GPIO_H_PU, BIT(2)),
>>>> +	PINCTRL_CONF_DESC(37, REG_GPIO_H_PU, BIT(3)),
>>>> +	PINCTRL_CONF_DESC(38, REG_GPIO_H_PU, BIT(4)),
>>>> +	PINCTRL_CONF_DESC(39, REG_GPIO_H_PU, BIT(5)),
>>>> +	PINCTRL_CONF_DESC(40, REG_GPIO_H_PU, BIT(6)),
>>>> +	PINCTRL_CONF_DESC(41, REG_I2C_SDA_PU, I2C_SCL_PU_MASK),
>>>> +	PINCTRL_CONF_DESC(42, REG_I2C_SDA_PU, I2C_SDA_PU_MASK),
>>>> +	PINCTRL_CONF_DESC(43, REG_I2C_SDA_PU, AN7583_I2C1_SCL_PU_MASK),
>>>> +	PINCTRL_CONF_DESC(44, REG_I2C_SDA_PU, AN7583_I2C1_SDA_PU_MASK),
>>>> +	PINCTRL_CONF_DESC(45, REG_I2C_SDA_PU, SPI_CLK_PU_MASK),
>>>> +	PINCTRL_CONF_DESC(46, REG_I2C_SDA_PU, SPI_CS0_PU_MASK),
>>>> +	PINCTRL_CONF_DESC(47, REG_I2C_SDA_PU, SPI_MOSI_PU_MASK),
>>>> +	PINCTRL_CONF_DESC(48, REG_I2C_SDA_PU, SPI_MISO_PU_MASK),
>>>> +	PINCTRL_CONF_DESC(49, REG_I2C_SDA_PU, UART1_TXD_PU_MASK),
>>>> +	PINCTRL_CONF_DESC(50, REG_I2C_SDA_PU, UART1_RXD_PU_MASK),
>>>> +	PINCTRL_CONF_DESC(51, REG_I2C_SDA_PU, PCIE0_RESET_PU_MASK),
>>>> +	PINCTRL_CONF_DESC(52, REG_I2C_SDA_PU, PCIE1_RESET_PU_MASK),
>>>> +	PINCTRL_CONF_DESC(53, REG_I2C_SDA_PU, AN7583_MDC_0_PU_MASK),
>>>> +	PINCTRL_CONF_DESC(54, REG_I2C_SDA_PU, AN7583_MDIO_0_PU_MASK),
>>>> +};
>>>> +
>>>> +static const struct airoha_pinctrl_conf an7583_pinctrl_pulldown_conf[] = {
>>>> +	PINCTRL_CONF_DESC(2, REG_GPIO_L_PD, BIT(0)),
>>>> +	PINCTRL_CONF_DESC(3, REG_GPIO_L_PD, BIT(1)),
>>>> +	PINCTRL_CONF_DESC(4, REG_GPIO_L_PD, BIT(2)),
>>>> +	PINCTRL_CONF_DESC(5, REG_GPIO_L_PD, BIT(3)),
>>>> +	PINCTRL_CONF_DESC(6, REG_GPIO_L_PD, BIT(4)),
>>>> +	PINCTRL_CONF_DESC(7, REG_GPIO_L_PD, BIT(5)),
>>>> +	PINCTRL_CONF_DESC(8, REG_GPIO_L_PD, BIT(6)),
>>>> +	PINCTRL_CONF_DESC(9, REG_GPIO_L_PD, BIT(7)),
>>>> +	PINCTRL_CONF_DESC(10, REG_GPIO_L_PD, BIT(8)),
>>>> +	PINCTRL_CONF_DESC(11, REG_GPIO_L_PD, BIT(9)),
>>>> +	PINCTRL_CONF_DESC(12, REG_GPIO_L_PD, BIT(10)),
>>>> +	PINCTRL_CONF_DESC(13, REG_GPIO_L_PD, BIT(11)),
>>>> +	PINCTRL_CONF_DESC(14, REG_GPIO_L_PD, BIT(12)),
>>>> +	PINCTRL_CONF_DESC(15, REG_GPIO_L_PD, BIT(13)),
>>>> +	PINCTRL_CONF_DESC(16, REG_GPIO_L_PD, BIT(14)),
>>>> +	PINCTRL_CONF_DESC(17, REG_GPIO_L_PD, BIT(15)),
>>>> +	PINCTRL_CONF_DESC(18, REG_GPIO_L_PD, BIT(16)),
>>>> +	PINCTRL_CONF_DESC(19, REG_GPIO_L_PD, BIT(17)),
>>>> +	PINCTRL_CONF_DESC(20, REG_GPIO_L_PD, BIT(18)),
>>>> +	PINCTRL_CONF_DESC(21, REG_GPIO_L_PD, BIT(19)),
>>>> +	PINCTRL_CONF_DESC(22, REG_GPIO_L_PD, BIT(20)),
>>>> +	PINCTRL_CONF_DESC(23, REG_GPIO_L_PD, BIT(21)),
>>>> +	PINCTRL_CONF_DESC(24, REG_GPIO_L_PD, BIT(22)),
>>>> +	PINCTRL_CONF_DESC(25, REG_GPIO_L_PD, BIT(23)),
>>>> +	PINCTRL_CONF_DESC(26, REG_GPIO_L_PD, BIT(24)),
>>>> +	PINCTRL_CONF_DESC(27, REG_GPIO_L_PD, BIT(25)),
>>>> +	PINCTRL_CONF_DESC(28, REG_GPIO_L_PD, BIT(26)),
>>>> +	PINCTRL_CONF_DESC(29, REG_GPIO_L_PD, BIT(27)),
>>>> +	PINCTRL_CONF_DESC(30, REG_GPIO_L_PD, BIT(28)),
>>>> +	PINCTRL_CONF_DESC(31, REG_GPIO_L_PD, BIT(29)),
>>>> +	PINCTRL_CONF_DESC(32, REG_GPIO_L_PD, BIT(30)),
>>>> +	PINCTRL_CONF_DESC(33, REG_GPIO_L_PD, BIT(31)),
>>>> +	PINCTRL_CONF_DESC(34, REG_GPIO_H_PD, BIT(0)),
>>>> +	PINCTRL_CONF_DESC(35, REG_GPIO_H_PD, BIT(1)),
>>>> +	PINCTRL_CONF_DESC(36, REG_GPIO_H_PD, BIT(2)),
>>>> +	PINCTRL_CONF_DESC(37, REG_GPIO_H_PD, BIT(3)),
>>>> +	PINCTRL_CONF_DESC(38, REG_GPIO_H_PD, BIT(4)),
>>>> +	PINCTRL_CONF_DESC(39, REG_GPIO_H_PD, BIT(5)),
>>>> +	PINCTRL_CONF_DESC(40, REG_GPIO_H_PD, BIT(6)),
>>>> +	PINCTRL_CONF_DESC(41, REG_I2C_SDA_PD, I2C_SCL_PD_MASK),
>>>> +	PINCTRL_CONF_DESC(42, REG_I2C_SDA_PD, I2C_SDA_PD_MASK),
>>>> +	PINCTRL_CONF_DESC(43, REG_I2C_SDA_PD, AN7583_I2C1_SCL_PD_MASK),
>>>> +	PINCTRL_CONF_DESC(44, REG_I2C_SDA_PD, AN7583_I2C1_SDA_PD_MASK),
>>>> +	PINCTRL_CONF_DESC(45, REG_I2C_SDA_PD, SPI_CLK_PD_MASK),
>>>> +	PINCTRL_CONF_DESC(46, REG_I2C_SDA_PD, SPI_CS0_PD_MASK),
>>>> +	PINCTRL_CONF_DESC(47, REG_I2C_SDA_PD, SPI_MOSI_PD_MASK),
>>>> +	PINCTRL_CONF_DESC(48, REG_I2C_SDA_PD, SPI_MISO_PD_MASK),
>>>> +	PINCTRL_CONF_DESC(49, REG_I2C_SDA_PD, UART1_TXD_PD_MASK),
>>>> +	PINCTRL_CONF_DESC(50, REG_I2C_SDA_PD, UART1_RXD_PD_MASK),
>>>> +	PINCTRL_CONF_DESC(51, REG_I2C_SDA_PD, PCIE0_RESET_PD_MASK),
>>>> +	PINCTRL_CONF_DESC(52, REG_I2C_SDA_PD, PCIE1_RESET_PD_MASK),
>>>> +	PINCTRL_CONF_DESC(53, REG_I2C_SDA_PD, AN7583_MDC_0_PD_MASK),
>>>> +	PINCTRL_CONF_DESC(54, REG_I2C_SDA_PD, AN7583_MDIO_0_PD_MASK),
>>>> +};
>>>> +
>>>> +static const struct airoha_pinctrl_conf an7583_pinctrl_drive_e2_conf[] = {
>>>> +	PINCTRL_CONF_DESC(2, REG_GPIO_L_E2, BIT(0)),
>>>> +	PINCTRL_CONF_DESC(3, REG_GPIO_L_E2, BIT(1)),
>>>> +	PINCTRL_CONF_DESC(4, REG_GPIO_L_E2, BIT(2)),
>>>> +	PINCTRL_CONF_DESC(5, REG_GPIO_L_E2, BIT(3)),
>>>> +	PINCTRL_CONF_DESC(6, REG_GPIO_L_E2, BIT(4)),
>>>> +	PINCTRL_CONF_DESC(7, REG_GPIO_L_E2, BIT(5)),
>>>> +	PINCTRL_CONF_DESC(8, REG_GPIO_L_E2, BIT(6)),
>>>> +	PINCTRL_CONF_DESC(9, REG_GPIO_L_E2, BIT(7)),
>>>> +	PINCTRL_CONF_DESC(10, REG_GPIO_L_E2, BIT(8)),
>>>> +	PINCTRL_CONF_DESC(11, REG_GPIO_L_E2, BIT(9)),
>>>> +	PINCTRL_CONF_DESC(12, REG_GPIO_L_E2, BIT(10)),
>>>> +	PINCTRL_CONF_DESC(13, REG_GPIO_L_E2, BIT(11)),
>>>> +	PINCTRL_CONF_DESC(14, REG_GPIO_L_E2, BIT(12)),
>>>> +	PINCTRL_CONF_DESC(15, REG_GPIO_L_E2, BIT(13)),
>>>> +	PINCTRL_CONF_DESC(16, REG_GPIO_L_E2, BIT(14)),
>>>> +	PINCTRL_CONF_DESC(17, REG_GPIO_L_E2, BIT(15)),
>>>> +	PINCTRL_CONF_DESC(18, REG_GPIO_L_E2, BIT(16)),
>>>> +	PINCTRL_CONF_DESC(19, REG_GPIO_L_E2, BIT(17)),
>>>> +	PINCTRL_CONF_DESC(20, REG_GPIO_L_E2, BIT(18)),
>>>> +	PINCTRL_CONF_DESC(21, REG_GPIO_L_E2, BIT(19)),
>>>> +	PINCTRL_CONF_DESC(22, REG_GPIO_L_E2, BIT(20)),
>>>> +	PINCTRL_CONF_DESC(23, REG_GPIO_L_E2, BIT(21)),
>>>> +	PINCTRL_CONF_DESC(24, REG_GPIO_L_E2, BIT(22)),
>>>> +	PINCTRL_CONF_DESC(25, REG_GPIO_L_E2, BIT(23)),
>>>> +	PINCTRL_CONF_DESC(26, REG_GPIO_L_E2, BIT(24)),
>>>> +	PINCTRL_CONF_DESC(27, REG_GPIO_L_E2, BIT(25)),
>>>> +	PINCTRL_CONF_DESC(28, REG_GPIO_L_E2, BIT(26)),
>>>> +	PINCTRL_CONF_DESC(29, REG_GPIO_L_E2, BIT(27)),
>>>> +	PINCTRL_CONF_DESC(30, REG_GPIO_L_E2, BIT(28)),
>>>> +	PINCTRL_CONF_DESC(31, REG_GPIO_L_E2, BIT(29)),
>>>> +	PINCTRL_CONF_DESC(32, REG_GPIO_L_E2, BIT(30)),
>>>> +	PINCTRL_CONF_DESC(33, REG_GPIO_L_E2, BIT(31)),
>>>> +	PINCTRL_CONF_DESC(34, REG_GPIO_H_E2, BIT(0)),
>>>> +	PINCTRL_CONF_DESC(35, REG_GPIO_H_E2, BIT(1)),
>>>> +	PINCTRL_CONF_DESC(36, REG_GPIO_H_E2, BIT(2)),
>>>> +	PINCTRL_CONF_DESC(37, REG_GPIO_H_E2, BIT(3)),
>>>> +	PINCTRL_CONF_DESC(38, REG_GPIO_H_E2, BIT(4)),
>>>> +	PINCTRL_CONF_DESC(39, REG_GPIO_H_E2, BIT(5)),
>>>> +	PINCTRL_CONF_DESC(40, REG_GPIO_H_E2, BIT(6)),
>>>> +	PINCTRL_CONF_DESC(41, REG_I2C_SDA_E2, I2C_SCL_E2_MASK),
>>>> +	PINCTRL_CONF_DESC(42, REG_I2C_SDA_E2, I2C_SDA_E2_MASK),
>>>> +	PINCTRL_CONF_DESC(43, REG_I2C_SDA_E2, AN7583_I2C1_SCL_E2_MASK),
>>>> +	PINCTRL_CONF_DESC(44, REG_I2C_SDA_E2, AN7583_I2C1_SDA_E2_MASK),
>>>> +	PINCTRL_CONF_DESC(45, REG_I2C_SDA_E2, SPI_CLK_E2_MASK),
>>>> +	PINCTRL_CONF_DESC(46, REG_I2C_SDA_E2, SPI_CS0_E2_MASK),
>>>> +	PINCTRL_CONF_DESC(47, REG_I2C_SDA_E2, SPI_MOSI_E2_MASK),
>>>> +	PINCTRL_CONF_DESC(48, REG_I2C_SDA_E2, SPI_MISO_E2_MASK),
>>>> +	PINCTRL_CONF_DESC(49, REG_I2C_SDA_E2, UART1_TXD_E2_MASK),
>>>> +	PINCTRL_CONF_DESC(50, REG_I2C_SDA_E2, UART1_RXD_E2_MASK),
>>>> +	PINCTRL_CONF_DESC(51, REG_I2C_SDA_E2, PCIE0_RESET_E2_MASK),
>>>> +	PINCTRL_CONF_DESC(52, REG_I2C_SDA_E2, PCIE1_RESET_E2_MASK),
>>>> +	PINCTRL_CONF_DESC(53, REG_I2C_SDA_E2, AN7583_MDC_0_E2_MASK),
>>>> +	PINCTRL_CONF_DESC(54, REG_I2C_SDA_E2, AN7583_MDIO_0_E2_MASK),
>>>> +};
>>>> +
>>>> +static const struct airoha_pinctrl_conf an7583_pinctrl_drive_e4_conf[] = {
>>>> +	PINCTRL_CONF_DESC(2, REG_GPIO_L_E4, BIT(0)),
>>>> +	PINCTRL_CONF_DESC(3, REG_GPIO_L_E4, BIT(1)),
>>>> +	PINCTRL_CONF_DESC(4, REG_GPIO_L_E4, BIT(2)),
>>>> +	PINCTRL_CONF_DESC(5, REG_GPIO_L_E4, BIT(3)),
>>>> +	PINCTRL_CONF_DESC(6, REG_GPIO_L_E4, BIT(4)),
>>>> +	PINCTRL_CONF_DESC(7, REG_GPIO_L_E4, BIT(5)),
>>>> +	PINCTRL_CONF_DESC(8, REG_GPIO_L_E4, BIT(6)),
>>>> +	PINCTRL_CONF_DESC(9, REG_GPIO_L_E4, BIT(7)),
>>>> +	PINCTRL_CONF_DESC(10, REG_GPIO_L_E4, BIT(8)),
>>>> +	PINCTRL_CONF_DESC(11, REG_GPIO_L_E4, BIT(9)),
>>>> +	PINCTRL_CONF_DESC(12, REG_GPIO_L_E4, BIT(10)),
>>>> +	PINCTRL_CONF_DESC(13, REG_GPIO_L_E4, BIT(11)),
>>>> +	PINCTRL_CONF_DESC(14, REG_GPIO_L_E4, BIT(12)),
>>>> +	PINCTRL_CONF_DESC(15, REG_GPIO_L_E4, BIT(13)),
>>>> +	PINCTRL_CONF_DESC(16, REG_GPIO_L_E4, BIT(14)),
>>>> +	PINCTRL_CONF_DESC(17, REG_GPIO_L_E4, BIT(15)),
>>>> +	PINCTRL_CONF_DESC(18, REG_GPIO_L_E4, BIT(16)),
>>>> +	PINCTRL_CONF_DESC(19, REG_GPIO_L_E4, BIT(17)),
>>>> +	PINCTRL_CONF_DESC(20, REG_GPIO_L_E4, BIT(18)),
>>>> +	PINCTRL_CONF_DESC(21, REG_GPIO_L_E4, BIT(19)),
>>>> +	PINCTRL_CONF_DESC(22, REG_GPIO_L_E4, BIT(20)),
>>>> +	PINCTRL_CONF_DESC(23, REG_GPIO_L_E4, BIT(21)),
>>>> +	PINCTRL_CONF_DESC(24, REG_GPIO_L_E4, BIT(22)),
>>>> +	PINCTRL_CONF_DESC(25, REG_GPIO_L_E4, BIT(23)),
>>>> +	PINCTRL_CONF_DESC(26, REG_GPIO_L_E4, BIT(24)),
>>>> +	PINCTRL_CONF_DESC(27, REG_GPIO_L_E4, BIT(25)),
>>>> +	PINCTRL_CONF_DESC(28, REG_GPIO_L_E4, BIT(26)),
>>>> +	PINCTRL_CONF_DESC(29, REG_GPIO_L_E4, BIT(27)),
>>>> +	PINCTRL_CONF_DESC(30, REG_GPIO_L_E4, BIT(28)),
>>>> +	PINCTRL_CONF_DESC(31, REG_GPIO_L_E4, BIT(29)),
>>>> +	PINCTRL_CONF_DESC(32, REG_GPIO_L_E4, BIT(30)),
>>>> +	PINCTRL_CONF_DESC(33, REG_GPIO_L_E4, BIT(31)),
>>>> +	PINCTRL_CONF_DESC(34, REG_GPIO_H_E4, BIT(0)),
>>>> +	PINCTRL_CONF_DESC(35, REG_GPIO_H_E4, BIT(1)),
>>>> +	PINCTRL_CONF_DESC(36, REG_GPIO_H_E4, BIT(2)),
>>>> +	PINCTRL_CONF_DESC(37, REG_GPIO_H_E4, BIT(3)),
>>>> +	PINCTRL_CONF_DESC(38, REG_GPIO_H_E4, BIT(4)),
>>>> +	PINCTRL_CONF_DESC(39, REG_GPIO_H_E4, BIT(5)),
>>>> +	PINCTRL_CONF_DESC(40, REG_GPIO_H_E4, BIT(6)),
>>>> +	PINCTRL_CONF_DESC(41, REG_I2C_SDA_E4, I2C_SCL_E4_MASK),
>>>> +	PINCTRL_CONF_DESC(42, REG_I2C_SDA_E4, I2C_SDA_E4_MASK),
>>>> +	PINCTRL_CONF_DESC(43, REG_I2C_SDA_E4, AN7583_I2C1_SCL_E4_MASK),
>>>> +	PINCTRL_CONF_DESC(44, REG_I2C_SDA_E4, AN7583_I2C1_SDA_E4_MASK),
>>>> +	PINCTRL_CONF_DESC(45, REG_I2C_SDA_E4, SPI_CLK_E4_MASK),
>>>> +	PINCTRL_CONF_DESC(46, REG_I2C_SDA_E4, SPI_CS0_E4_MASK),
>>>> +	PINCTRL_CONF_DESC(47, REG_I2C_SDA_E4, SPI_MOSI_E4_MASK),
>>>> +	PINCTRL_CONF_DESC(48, REG_I2C_SDA_E4, SPI_MISO_E4_MASK),
>>>> +	PINCTRL_CONF_DESC(49, REG_I2C_SDA_E4, UART1_TXD_E4_MASK),
>>>> +	PINCTRL_CONF_DESC(50, REG_I2C_SDA_E4, UART1_RXD_E4_MASK),
>>>> +	PINCTRL_CONF_DESC(51, REG_I2C_SDA_E4, PCIE0_RESET_E4_MASK),
>>>> +	PINCTRL_CONF_DESC(52, REG_I2C_SDA_E4, PCIE1_RESET_E4_MASK),
>>>> +	PINCTRL_CONF_DESC(53, REG_I2C_SDA_E4, AN7583_MDC_0_E4_MASK),
>>>> +	PINCTRL_CONF_DESC(54, REG_I2C_SDA_E4, AN7583_MDIO_0_E4_MASK),
>>>> +};
>>>> +
>>>> +static const struct airoha_pinctrl_conf an7583_pinctrl_pcie_rst_od_conf[] = {
>>>> +	PINCTRL_CONF_DESC(51, REG_PCIE_RESET_OD, PCIE0_RESET_OD_MASK),
>>>> +	PINCTRL_CONF_DESC(52, REG_PCIE_RESET_OD, PCIE1_RESET_OD_MASK),
>>>> +};
>>>> +
>>>> +static const struct airoha_pinctrl_match_data an7583_pinctrl_match_data = {
>>>> +	.pinctrl_name = KBUILD_MODNAME,
>>>> +	.pinctrl_owner = THIS_MODULE,
>>>> +	.pins = an7583_pinctrl_pins,
>>>> +	.num_pins = ARRAY_SIZE(an7583_pinctrl_pins),
>>>> +	.grps = an7583_pinctrl_groups,
>>>> +	.num_grps = ARRAY_SIZE(an7583_pinctrl_groups),
>>>> +	.funcs = an7583_pinctrl_funcs,
>>>> +	.num_funcs = ARRAY_SIZE(an7583_pinctrl_funcs),
>>>> +	.confs_info = {
>>>> +		[AIROHA_PINCTRL_CONFS_PULLUP] = {
>>>> +			.confs = an7583_pinctrl_pullup_conf,
>>>> +			.num_confs = ARRAY_SIZE(an7583_pinctrl_pullup_conf),
>>>> +		},
>>>> +		[AIROHA_PINCTRL_CONFS_PULLDOWN] = {
>>>> +			.confs = an7583_pinctrl_pulldown_conf,
>>>> +			.num_confs = ARRAY_SIZE(an7583_pinctrl_pulldown_conf),
>>>> +		},
>>>> +		[AIROHA_PINCTRL_CONFS_DRIVE_E2] = {
>>>> +			.confs = an7583_pinctrl_drive_e2_conf,
>>>> +			.num_confs = ARRAY_SIZE(an7583_pinctrl_drive_e2_conf),
>>>> +		},
>>>> +		[AIROHA_PINCTRL_CONFS_DRIVE_E4] = {
>>>> +			.confs = an7583_pinctrl_drive_e4_conf,
>>>> +			.num_confs = ARRAY_SIZE(an7583_pinctrl_drive_e4_conf),
>>>> +		},
>>>> +		[AIROHA_PINCTRL_CONFS_PCIE_RST_OD] = {
>>>> +			.confs = an7583_pinctrl_pcie_rst_od_conf,
>>>> +			.num_confs = ARRAY_SIZE(an7583_pinctrl_pcie_rst_od_conf),
>>>> +		},
>>>> +	},
>>>> +};
>>>> +
>>>> +static const struct of_device_id airoha_pinctrl_of_match[] = {
>>>> +	{ .compatible = "airoha,an7583-pinctrl", .data = &an7583_pinctrl_match_data },
>>>> +	{ /* sentinel */ }
>>>> +};
>>>> +MODULE_DEVICE_TABLE(of, airoha_pinctrl_of_match);
>>>> +
>>>> +static struct platform_driver airoha_pinctrl_driver = {
>>>> +	.probe = airoha_pinctrl_probe,
>>>> +	.driver = {
>>>> +		.name = "pinctrl-airoha-an7583",
>>>> +		.of_match_table = airoha_pinctrl_of_match,
>>>> +	},
>>>> +};
>>>> +module_platform_driver(airoha_pinctrl_driver);
>>>> +
>>>> +MODULE_LICENSE("GPL");
>>>> +MODULE_AUTHOR("Lorenzo Bianconi <lorenzo@kernel.org>");
>>>> +MODULE_AUTHOR("Benjamin Larsson <benjamin.larsson@genexis.eu>");
>>>> +MODULE_AUTHOR("Markus Gothe <markus.gothe@genexis.eu>");
>>>> +MODULE_DESCRIPTION("Pinctrl driver for Airoha AN7583 SoC");
>>>> -- 
>>>> 2.53.0
>>>>

Re: [PATCH v7 20/34] pinctrl: airoha: split driver on shared code and SoC specific drivers

[Lorenzo Bianconi]

[-- Attachment #1: Type: text/plain, Size: 249661 bytes --]

> 
> On 7/27/26 12:27, Lorenzo Bianconi wrote:
> >> On 7/27/26 12:14, Lorenzo Bianconi wrote:
> >>>> Split combined an7581/an7583 source file on a
> >>>>  * shared pinctrl code (pinctrl-airoha.c)
> >>>>  * an7581 specific pinctrl driver (pinctrl-an7581.c)
> >>>>  * an7583 specific pinctrl driver (pinctrl-an7583.c)
> >>> I do not think we can have 7581 and 7583 chips at the same time on a given
> >>> board so I guess we can avoid creating a dedicated module for the common code.
> >>> I guess we can just create a library we can compile in. What do yout think?
> >>>
> >>> Regards,
> >>> Lorenzo
> >> Hm, how do you suggest to implement it? In the generic kernel case  we
> >> should not
> >> load airoha pinctrl library if we are booting from non airoha board. 
> > I mean just compile the code in en7581 or an7583 modules without a dedicated
> > module.
> 
> so in the generic kernel case we will have 4 copies of shared code?

I mean to compile in the soc object, something like:

obj-$(CONFIG_PINCTRL_AIROHA_AN7581) = an7581-pinctrl
an7581-pinctrl-y := pinctrl-airoha.o pinctrl-an7581.o

but I do not have a strong opinion about it.
@Mikhail, @Linus: what do you think?

Regards,
Lorenzo

> 
> 
> >
> > Regards,
> > Lorenzo
> >
> >>>> Ininialization code was adapted a bit to work properly for shared
> >>>> and SoC specific cases.
> >>>>
> >>>> Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
> >>>> ---
> >>>>  drivers/pinctrl/airoha/Kconfig          |   24 +-
> >>>>  drivers/pinctrl/airoha/Makefile         |    5 +
> >>>>  drivers/pinctrl/airoha/airoha-common.h  |    5 +
> >>>>  drivers/pinctrl/airoha/pinctrl-airoha.c | 2382 +----------------------
> >>>>  drivers/pinctrl/airoha/pinctrl-an7581.c | 1486 ++++++++++++++
> >>>>  drivers/pinctrl/airoha/pinctrl-an7583.c | 1456 ++++++++++++++
> >>>>  6 files changed, 2984 insertions(+), 2374 deletions(-)
> >>>>  create mode 100644 drivers/pinctrl/airoha/pinctrl-an7581.c
> >>>>  create mode 100644 drivers/pinctrl/airoha/pinctrl-an7583.c
> >>>>
> >>>> diff --git a/drivers/pinctrl/airoha/Kconfig b/drivers/pinctrl/airoha/Kconfig
> >>>> index 03adaeae8fc3a..dae6608bc72dd 100644
> >>>> --- a/drivers/pinctrl/airoha/Kconfig
> >>>> +++ b/drivers/pinctrl/airoha/Kconfig
> >>>> @@ -3,9 +3,9 @@ menu "Airoha pinctrl drivers"
> >>>>  	depends on ARCH_AIROHA || COMPILE_TEST
> >>>>  
> >>>>  config PINCTRL_AIROHA
> >>>> -	tristate "Airoha EN7581 pin control"
> >>>> +	tristate "Airoha pin control"
> >>>>  	depends on OF
> >>>> -	depends on ARM64 || COMPILE_TEST
> >>>> +	depends on ARCH_AIROHA || COMPILE_TEST
> >>>>  	select PINMUX
> >>>>  	select GENERIC_PINCONF
> >>>>  	select GENERIC_PINCTRL_GROUPS
> >>>> @@ -13,8 +13,26 @@ config PINCTRL_AIROHA
> >>>>  	select GPIOLIB
> >>>>  	select GPIOLIB_IRQCHIP
> >>>>  	select REGMAP_MMIO
> >>>> +	imply PINCTRL_AIROHA_AN7581
> >>>> +	imply PINCTRL_AIROHA_AN7583
> >>>> +	help
> >>>> +	  Shared pin controller and gpio driver code for different
> >>>> +	  Airoha SoCs.
> >>>> +
> >>>> +config PINCTRL_AIROHA_AN7581
> >>>> +	tristate "AN7581 pinctrl"
> >>>> +	depends on ARM64 || COMPILE_TEST
> >>>> +	depends on PINCTRL_AIROHA
> >>>> +	help
> >>>> +	  Say yes here to support pin controller and gpio driver
> >>>> +	  on Airoha AN7581, AN7566, AN7551 and other compatible SoCs.
> >>>> +
> >>>> +config PINCTRL_AIROHA_AN7583
> >>>> +	tristate "AN7583 pinctrl"
> >>>> +	depends on ARM64 || COMPILE_TEST
> >>>> +	depends on PINCTRL_AIROHA
> >>>>  	help
> >>>>  	  Say yes here to support pin controller and gpio driver
> >>>> -	  on Airoha EN7581 SoC.
> >>>> +	  on Airoha AN7583, AN7553, AN7567 and other compatible SoCs.
> >>>>  
> >>>>  endmenu
> >>>> diff --git a/drivers/pinctrl/airoha/Makefile b/drivers/pinctrl/airoha/Makefile
> >>>> index a25b744dd7a8a..cfd68c45ae0f0 100644
> >>>> --- a/drivers/pinctrl/airoha/Makefile
> >>>> +++ b/drivers/pinctrl/airoha/Makefile
> >>>> @@ -1,3 +1,8 @@
> >>>>  # SPDX-License-Identifier: GPL-2.0
> >>>>  
> >>>> +# shared code
> >>>>  obj-$(CONFIG_PINCTRL_AIROHA)		+= pinctrl-airoha.o
> >>>> +
> >>>> +# SoC drivers
> >>>> +obj-$(CONFIG_PINCTRL_AIROHA_AN7581)	+= pinctrl-an7581.o
> >>>> +obj-$(CONFIG_PINCTRL_AIROHA_AN7583)	+= pinctrl-an7583.o
> >>>> diff --git a/drivers/pinctrl/airoha/airoha-common.h b/drivers/pinctrl/airoha/airoha-common.h
> >>>> index 40d7e515c09eb..f73e90ca860f4 100644
> >>>> --- a/drivers/pinctrl/airoha/airoha-common.h
> >>>> +++ b/drivers/pinctrl/airoha/airoha-common.h
> >>>> @@ -148,9 +148,12 @@ struct airoha_pinctrl {
> >>>>  	struct regmap *regmap;
> >>>>  
> >>>>  	struct airoha_pinctrl_gpiochip gpiochip;
> >>>> +	struct irq_chip gpio_irq_chip;
> >>>>  };
> >>>>  
> >>>>  struct airoha_pinctrl_match_data {
> >>>> +	const char *pinctrl_name;
> >>>> +	struct module *pinctrl_owner;
> >>>>  	const struct pinctrl_pin_desc *pins;
> >>>>  	const unsigned int num_pins;
> >>>>  	const struct pingroup *grps;
> >>>> @@ -160,4 +163,6 @@ struct airoha_pinctrl_match_data {
> >>>>  	const struct airoha_pinctrl_confs_info confs_info[AIROHA_PINCTRL_CONFS_MAX];
> >>>>  };
> >>>>  
> >>>> +int airoha_pinctrl_probe(struct platform_device *pdev);
> >>>> +
> >>>>  #endif
> >>>> diff --git a/drivers/pinctrl/airoha/pinctrl-airoha.c b/drivers/pinctrl/airoha/pinctrl-airoha.c
> >>>> index f42631afc05d3..a46596eb1493b 100644
> >>>> --- a/drivers/pinctrl/airoha/pinctrl-airoha.c
> >>>> +++ b/drivers/pinctrl/airoha/pinctrl-airoha.c
> >>>> @@ -7,365 +7,6 @@
> >>>>  
> >>>>  #include "airoha-common.h"
> >>>>  
> >>>> -/* MUX */
> >>>> -#define REG_GPIO_2ND_I2C_MODE			0x0214
> >>>> -#define GPIO_MDC_IO_MASTER_MODE_MASK		BIT(14)
> >>>> -#define GPIO_I2C_MASTER_MODE_MODE		BIT(13)
> >>>> -#define GPIO_I2S_MODE_MASK			BIT(12)
> >>>> -#define GPIO_I2C_SLAVE_MODE_MODE		BIT(11)
> >>>> -#define GPIO_LAN3_LED1_MODE_MASK		BIT(10)
> >>>> -#define GPIO_LAN3_LED0_MODE_MASK		BIT(9)
> >>>> -#define GPIO_LAN2_LED1_MODE_MASK		BIT(8)
> >>>> -#define GPIO_LAN2_LED0_MODE_MASK		BIT(7)
> >>>> -#define GPIO_LAN1_LED1_MODE_MASK		BIT(6)
> >>>> -#define GPIO_LAN1_LED0_MODE_MASK		BIT(5)
> >>>> -#define GPIO_LAN0_LED1_MODE_MASK		BIT(4)
> >>>> -#define GPIO_LAN0_LED0_MODE_MASK		BIT(3)
> >>>> -#define PON_TOD_1PPS_MODE_MASK			BIT(2)
> >>>> -#define GSW_TOD_1PPS_MODE_MASK			BIT(1)
> >>>> -#define GPIO_2ND_I2C_MODE_MASK			BIT(0)
> >>>> -
> >>>> -#define REG_GPIO_SPI_CS1_MODE			0x0218
> >>>> -#define GPIO_PCM_SPI_CS4_MODE_MASK		BIT(21)
> >>>> -#define GPIO_PCM_SPI_CS3_MODE_MASK		BIT(20)
> >>>> -#define GPIO_PCM_SPI_CS2_MODE_P156_MASK		BIT(19)
> >>>> -#define GPIO_PCM_SPI_CS2_MODE_P128_MASK		BIT(18)
> >>>> -#define AN7583_GPIO_PCM_SPI_CS2_MODE_MASK	BIT(18)
> >>>> -#define GPIO_PCM_SPI_CS1_MODE_MASK		BIT(17)
> >>>> -#define GPIO_PCM_SPI_MODE_MASK			BIT(16)
> >>>> -#define GPIO_PCM2_MODE_MASK			BIT(13)
> >>>> -#define GPIO_PCM1_MODE_MASK			BIT(12)
> >>>> -#define GPIO_PCM_INT_MODE_MASK			BIT(9)
> >>>> -#define GPIO_PCM_RESET_MODE_MASK		BIT(8)
> >>>> -#define GPIO_SPI_QUAD_MODE_MASK			BIT(4)
> >>>> -#define GPIO_SPI_CS4_MODE_MASK			BIT(3)
> >>>> -#define GPIO_SPI_CS3_MODE_MASK			BIT(2)
> >>>> -#define GPIO_SPI_CS2_MODE_MASK			BIT(1)
> >>>> -#define GPIO_SPI_CS1_MODE_MASK			BIT(0)
> >>>> -
> >>>> -#define REG_GPIO_PON_MODE			0x021c
> >>>> -#define AN7583_MDIO_0_GPIO_MODE_MASK		BIT(26)
> >>>> -#define AN7583_MDC_0_GPIO_MODE_MASK		BIT(25)
> >>>> -#define AN7583_UART_RXD_GPIO_MODE_MASK		BIT(24)
> >>>> -#define AN7583_UART_TXD_GPIO_MODE_MASK		BIT(23)
> >>>> -#define AN7583_SPI_MISO_GPIO_MODE_MASK		BIT(22)
> >>>> -#define AN7583_SPI_MOSI_GPIO_MODE_MASK		BIT(21)
> >>>> -#define AN7583_SPI_CS_GPIO_MODE_MASK		BIT(20)
> >>>> -#define AN7583_SPI_CLK_GPIO_MODE_MASK		BIT(19)
> >>>> -#define AN7583_I2C1_SDA_GPIO_MODE_MASK		BIT(18)
> >>>> -#define AN7583_I2C1_SCL_GPIO_MODE_MASK		BIT(17)
> >>>> -#define AN7583_I2C0_SDA_GPIO_MODE_MASK		BIT(16)
> >>>> -#define AN7583_I2C0_SCL_GPIO_MODE_MASK		BIT(15)
> >>>> -#define GPIO_PARALLEL_NAND_MODE_MASK		BIT(14)
> >>>> -#define GPIO_SGMII_MDIO_MODE_MASK		BIT(13)
> >>>> -#define GPIO_PCIE_RESET2_MASK			BIT(12)
> >>>> -#define SIPO_RCLK_MODE_MASK			BIT(11)
> >>>> -#define GPIO_PCIE_RESET1_MASK			BIT(10)
> >>>> -#define GPIO_PCIE_RESET0_MASK			BIT(9)
> >>>> -#define GPIO_UART5_MODE_MASK			BIT(8)
> >>>> -#define GPIO_UART4_MODE_MASK			BIT(7)
> >>>> -#define GPIO_HSUART_CTS_RTS_MODE_MASK		BIT(6)
> >>>> -#define GPIO_HSUART_MODE_MASK			BIT(5)
> >>>> -#define GPIO_UART2_CTS_RTS_MODE_MASK		BIT(4)
> >>>> -#define GPIO_UART2_MODE_MASK			BIT(3)
> >>>> -#define GPIO_SIPO_MODE_MASK			BIT(2)
> >>>> -#define GPIO_EMMC_MODE_MASK			BIT(1)
> >>>> -#define GPIO_PON_MODE_MASK			BIT(0)
> >>>> -
> >>>> -#define REG_NPU_UART_EN				0x0224
> >>>> -#define JTAG_UDI_EN_MASK			BIT(4)
> >>>> -#define JTAG_DFD_EN_MASK			BIT(3)
> >>>> -
> >>>> -#define REG_FORCE_GPIO_EN			0x0228
> >>>> -#define FORCE_GPIO_EN(n)			BIT(n)
> >>>> -
> >>>> -/* LED MAP */
> >>>> -#define REG_LAN_LED0_MAPPING			0x027c
> >>>> -#define REG_LAN_LED1_MAPPING			0x0280
> >>>> -
> >>>> -#define LAN4_LED_MAPPING_MASK			GENMASK(18, 16)
> >>>> -#define LAN4_PHY_LED_MAP(_n)			FIELD_PREP_CONST(LAN4_LED_MAPPING_MASK, (_n))
> >>>> -
> >>>> -#define LAN3_LED_MAPPING_MASK			GENMASK(14, 12)
> >>>> -#define LAN3_PHY_LED_MAP(_n)			FIELD_PREP_CONST(LAN3_LED_MAPPING_MASK, (_n))
> >>>> -
> >>>> -#define LAN2_LED_MAPPING_MASK			GENMASK(10, 8)
> >>>> -#define LAN2_PHY_LED_MAP(_n)			FIELD_PREP_CONST(LAN2_LED_MAPPING_MASK, (_n))
> >>>> -
> >>>> -#define LAN1_LED_MAPPING_MASK			GENMASK(6, 4)
> >>>> -#define LAN1_PHY_LED_MAP(_n)			FIELD_PREP_CONST(LAN1_LED_MAPPING_MASK, (_n))
> >>>> -
> >>>> -#define LAN0_LED_MAPPING_MASK			GENMASK(2, 0)
> >>>> -#define LAN0_PHY_LED_MAP(_n)			FIELD_PREP_CONST(LAN0_LED_MAPPING_MASK, (_n))
> >>>> -
> >>>> -/* CONF */
> >>>> -#define REG_I2C_SDA_E2				0x001c
> >>>> -#define AN7583_I2C1_SCL_E2_MASK			BIT(16)
> >>>> -#define AN7583_I2C1_SDA_E2_MASK			BIT(15)
> >>>> -#define SPI_MISO_E2_MASK			BIT(14)
> >>>> -#define SPI_MOSI_E2_MASK			BIT(13)
> >>>> -#define SPI_CLK_E2_MASK				BIT(12)
> >>>> -#define SPI_CS0_E2_MASK				BIT(11)
> >>>> -#define PCIE2_RESET_E2_MASK			BIT(10)
> >>>> -#define PCIE1_RESET_E2_MASK			BIT(9)
> >>>> -#define PCIE0_RESET_E2_MASK			BIT(8)
> >>>> -#define AN7583_MDIO_0_E2_MASK			BIT(5)
> >>>> -#define AN7583_MDC_0_E2_MASK			BIT(4)
> >>>> -#define UART1_RXD_E2_MASK			BIT(3)
> >>>> -#define UART1_TXD_E2_MASK			BIT(2)
> >>>> -#define I2C_SCL_E2_MASK				BIT(1)
> >>>> -#define I2C_SDA_E2_MASK				BIT(0)
> >>>> -
> >>>> -#define REG_I2C_SDA_E4				0x0020
> >>>> -#define AN7583_I2C1_SCL_E4_MASK			BIT(16)
> >>>> -#define AN7583_I2C1_SDA_E4_MASK			BIT(15)
> >>>> -#define SPI_MISO_E4_MASK			BIT(14)
> >>>> -#define SPI_MOSI_E4_MASK			BIT(13)
> >>>> -#define SPI_CLK_E4_MASK				BIT(12)
> >>>> -#define SPI_CS0_E4_MASK				BIT(11)
> >>>> -#define PCIE2_RESET_E4_MASK			BIT(10)
> >>>> -#define PCIE1_RESET_E4_MASK			BIT(9)
> >>>> -#define PCIE0_RESET_E4_MASK			BIT(8)
> >>>> -#define AN7583_MDIO_0_E4_MASK			BIT(5)
> >>>> -#define AN7583_MDC_0_E4_MASK			BIT(4)
> >>>> -#define UART1_RXD_E4_MASK			BIT(3)
> >>>> -#define UART1_TXD_E4_MASK			BIT(2)
> >>>> -#define I2C_SCL_E4_MASK				BIT(1)
> >>>> -#define I2C_SDA_E4_MASK				BIT(0)
> >>>> -
> >>>> -#define REG_GPIO_L_E2				0x0024
> >>>> -#define REG_GPIO_L_E4				0x0028
> >>>> -#define REG_GPIO_H_E2				0x002c
> >>>> -#define REG_GPIO_H_E4				0x0030
> >>>> -
> >>>> -#define REG_I2C_SDA_PU				0x0044
> >>>> -#define AN7583_I2C1_SCL_PU_MASK			BIT(16)
> >>>> -#define AN7583_I2C1_SDA_PU_MASK			BIT(15)
> >>>> -#define SPI_MISO_PU_MASK			BIT(14)
> >>>> -#define SPI_MOSI_PU_MASK			BIT(13)
> >>>> -#define SPI_CLK_PU_MASK				BIT(12)
> >>>> -#define SPI_CS0_PU_MASK				BIT(11)
> >>>> -#define PCIE2_RESET_PU_MASK			BIT(10)
> >>>> -#define PCIE1_RESET_PU_MASK			BIT(9)
> >>>> -#define PCIE0_RESET_PU_MASK			BIT(8)
> >>>> -#define AN7583_MDIO_0_PU_MASK			BIT(5)
> >>>> -#define AN7583_MDC_0_PU_MASK			BIT(4)
> >>>> -#define UART1_RXD_PU_MASK			BIT(3)
> >>>> -#define UART1_TXD_PU_MASK			BIT(2)
> >>>> -#define I2C_SCL_PU_MASK				BIT(1)
> >>>> -#define I2C_SDA_PU_MASK				BIT(0)
> >>>> -
> >>>> -#define REG_I2C_SDA_PD				0x0048
> >>>> -#define AN7583_I2C1_SCL_PD_MASK			BIT(16)
> >>>> -#define AN7583_I2C1_SDA_PD_MASK			BIT(15)
> >>>> -#define SPI_MISO_PD_MASK			BIT(14)
> >>>> -#define SPI_MOSI_PD_MASK			BIT(13)
> >>>> -#define SPI_CLK_PD_MASK				BIT(12)
> >>>> -#define SPI_CS0_PD_MASK				BIT(11)
> >>>> -#define PCIE2_RESET_PD_MASK			BIT(10)
> >>>> -#define PCIE1_RESET_PD_MASK			BIT(9)
> >>>> -#define PCIE0_RESET_PD_MASK			BIT(8)
> >>>> -#define AN7583_MDIO_0_PD_MASK			BIT(5)
> >>>> -#define AN7583_MDC_0_PD_MASK			BIT(4)
> >>>> -#define UART1_RXD_PD_MASK			BIT(3)
> >>>> -#define UART1_TXD_PD_MASK			BIT(2)
> >>>> -#define I2C_SCL_PD_MASK				BIT(1)
> >>>> -#define I2C_SDA_PD_MASK				BIT(0)
> >>>> -
> >>>> -#define REG_GPIO_L_PU				0x004c
> >>>> -#define REG_GPIO_L_PD				0x0050
> >>>> -#define REG_GPIO_H_PU				0x0054
> >>>> -#define REG_GPIO_H_PD				0x0058
> >>>> -
> >>>> -#define REG_PCIE_RESET_OD			0x018c
> >>>> -#define PCIE2_RESET_OD_MASK			BIT(2)
> >>>> -#define PCIE1_RESET_OD_MASK			BIT(1)
> >>>> -#define PCIE0_RESET_OD_MASK			BIT(0)
> >>>> -
> >>>> -/* GPIOs */
> >>>> -#define REG_GPIO_CTRL				0x0000
> >>>> -#define REG_GPIO_DATA				0x0004
> >>>> -#define REG_GPIO_INT				0x0008
> >>>> -#define REG_GPIO_INT_EDGE			0x000c
> >>>> -#define REG_GPIO_INT_LEVEL			0x0010
> >>>> -#define REG_GPIO_OE				0x0014
> >>>> -#define REG_GPIO_CTRL1				0x0020
> >>>> -#define REG_GPIO_CTRL2				0x0060
> >>>> -#define REG_GPIO_CTRL3				0x0064
> >>>> -
> >>>> -/* PWM MODE CONF */
> >>>> -#define REG_GPIO_FLASH_MODE_CFG			0x0034
> >>>> -#define GPIO15_FLASH_MODE_CFG			BIT(15)
> >>>> -#define GPIO14_FLASH_MODE_CFG			BIT(14)
> >>>> -#define GPIO13_FLASH_MODE_CFG			BIT(13)
> >>>> -#define GPIO12_FLASH_MODE_CFG			BIT(12)
> >>>> -#define GPIO11_FLASH_MODE_CFG			BIT(11)
> >>>> -#define GPIO10_FLASH_MODE_CFG			BIT(10)
> >>>> -#define GPIO9_FLASH_MODE_CFG			BIT(9)
> >>>> -#define GPIO8_FLASH_MODE_CFG			BIT(8)
> >>>> -#define GPIO7_FLASH_MODE_CFG			BIT(7)
> >>>> -#define GPIO6_FLASH_MODE_CFG			BIT(6)
> >>>> -#define GPIO5_FLASH_MODE_CFG			BIT(5)
> >>>> -#define GPIO4_FLASH_MODE_CFG			BIT(4)
> >>>> -#define GPIO3_FLASH_MODE_CFG			BIT(3)
> >>>> -#define GPIO2_FLASH_MODE_CFG			BIT(2)
> >>>> -#define GPIO1_FLASH_MODE_CFG			BIT(1)
> >>>> -#define GPIO0_FLASH_MODE_CFG			BIT(0)
> >>>> -
> >>>> -/* PWM MODE CONF EXT */
> >>>> -#define REG_GPIO_FLASH_MODE_CFG_EXT		0x0068
> >>>> -#define GPIO51_FLASH_MODE_CFG			BIT(31)
> >>>> -#define GPIO50_FLASH_MODE_CFG			BIT(30)
> >>>> -#define GPIO49_FLASH_MODE_CFG			BIT(29)
> >>>> -#define GPIO48_FLASH_MODE_CFG			BIT(28)
> >>>> -#define GPIO47_FLASH_MODE_CFG			BIT(27)
> >>>> -#define GPIO46_FLASH_MODE_CFG			BIT(26)
> >>>> -#define GPIO45_FLASH_MODE_CFG			BIT(25)
> >>>> -#define GPIO44_FLASH_MODE_CFG			BIT(24)
> >>>> -#define GPIO43_FLASH_MODE_CFG			BIT(23)
> >>>> -#define GPIO42_FLASH_MODE_CFG			BIT(22)
> >>>> -#define GPIO41_FLASH_MODE_CFG			BIT(21)
> >>>> -#define GPIO40_FLASH_MODE_CFG			BIT(20)
> >>>> -#define GPIO39_FLASH_MODE_CFG			BIT(19)
> >>>> -#define GPIO38_FLASH_MODE_CFG			BIT(18)
> >>>> -#define GPIO37_FLASH_MODE_CFG			BIT(17)
> >>>> -#define GPIO36_FLASH_MODE_CFG			BIT(16)
> >>>> -#define GPIO31_FLASH_MODE_CFG			BIT(15)
> >>>> -#define GPIO30_FLASH_MODE_CFG			BIT(14)
> >>>> -#define GPIO29_FLASH_MODE_CFG			BIT(13)
> >>>> -#define GPIO28_FLASH_MODE_CFG			BIT(12)
> >>>> -#define GPIO27_FLASH_MODE_CFG			BIT(11)
> >>>> -#define GPIO26_FLASH_MODE_CFG			BIT(10)
> >>>> -#define GPIO25_FLASH_MODE_CFG			BIT(9)
> >>>> -#define GPIO24_FLASH_MODE_CFG			BIT(8)
> >>>> -#define GPIO23_FLASH_MODE_CFG			BIT(7)
> >>>> -#define GPIO22_FLASH_MODE_CFG			BIT(6)
> >>>> -#define GPIO21_FLASH_MODE_CFG			BIT(5)
> >>>> -#define GPIO20_FLASH_MODE_CFG			BIT(4)
> >>>> -#define GPIO19_FLASH_MODE_CFG			BIT(3)
> >>>> -#define GPIO18_FLASH_MODE_CFG			BIT(2)
> >>>> -#define GPIO17_FLASH_MODE_CFG			BIT(1)
> >>>> -#define GPIO16_FLASH_MODE_CFG			BIT(0)
> >>>> -
> >>>> -#define REG_GPIO_DATA1				0x0070
> >>>> -#define REG_GPIO_OE1				0x0078
> >>>> -#define REG_GPIO_INT1				0x007c
> >>>> -#define REG_GPIO_INT_EDGE1			0x0080
> >>>> -#define REG_GPIO_INT_EDGE2			0x0084
> >>>> -#define REG_GPIO_INT_EDGE3			0x0088
> >>>> -#define REG_GPIO_INT_LEVEL1			0x008c
> >>>> -#define REG_GPIO_INT_LEVEL2			0x0090
> >>>> -#define REG_GPIO_INT_LEVEL3			0x0094
> >>>> -
> >>>> -#define AIROHA_PINCTRL_GPIO(gpio, mux_val)			\
> >>>> -	{							\
> >>>> -		.name = (gpio),					\
> >>>> -		.regmap[0] = {					\
> >>>> -			AIROHA_FUNC_MUX,			\
> >>>> -			REG_GPIO_PON_MODE,			\
> >>>> -			(mux_val),				\
> >>>> -			(mux_val)				\
> >>>> -		},						\
> >>>> -		.regmap_size = 1,				\
> >>>> -	}
> >>>> -
> >>>> -#define AIROHA_PINCTRL_GPIO_EXT(gpio, mux_val, smux_val)	\
> >>>> -	{							\
> >>>> -		.name = (gpio),					\
> >>>> -		.regmap[0] = {					\
> >>>> -			AIROHA_FUNC_PWM_EXT_MUX,		\
> >>>> -			REG_GPIO_FLASH_MODE_CFG_EXT,		\
> >>>> -			(mux_val),				\
> >>>> -			0					\
> >>>> -		},						\
> >>>> -		.regmap[1] = {					\
> >>>> -			AIROHA_FUNC_MUX,			\
> >>>> -			REG_GPIO_PON_MODE,			\
> >>>> -			(smux_val),				\
> >>>> -			(smux_val)				\
> >>>> -		},						\
> >>>> -		.regmap_size = 2,				\
> >>>> -	}
> >>>> -
> >>>> -/* PWM */
> >>>> -#define AIROHA_PINCTRL_PWM(gpio, mux_val)		\
> >>>> -	{						\
> >>>> -		.name = (gpio),				\
> >>>> -		.regmap[0] = {				\
> >>>> -			AIROHA_FUNC_PWM_MUX,		\
> >>>> -			REG_GPIO_FLASH_MODE_CFG,	\
> >>>> -			(mux_val),			\
> >>>> -			(mux_val)			\
> >>>> -		},					\
> >>>> -		.regmap_size = 1,			\
> >>>> -	}
> >>>> -
> >>>> -#define AIROHA_PINCTRL_PWM_EXT(gpio, mux_val)		\
> >>>> -	{						\
> >>>> -		.name = (gpio),				\
> >>>> -		.regmap[0] = {				\
> >>>> -			AIROHA_FUNC_PWM_EXT_MUX,	\
> >>>> -			REG_GPIO_FLASH_MODE_CFG_EXT,	\
> >>>> -			(mux_val),			\
> >>>> -			(mux_val)			\
> >>>> -		},					\
> >>>> -		.regmap_size = 1,			\
> >>>> -	}
> >>>> -
> >>>> -#define AIROHA_PINCTRL_PWM_EXT_SEC(gpio, mux_val, smux_val)	\
> >>>> -	{							\
> >>>> -		.name = (gpio),					\
> >>>> -		.regmap[0] = {					\
> >>>> -			AIROHA_FUNC_PWM_EXT_MUX,		\
> >>>> -			REG_GPIO_FLASH_MODE_CFG_EXT,		\
> >>>> -			(mux_val),				\
> >>>> -			(mux_val)				\
> >>>> -		},						\
> >>>> -		.regmap[1] = {					\
> >>>> -			AIROHA_FUNC_MUX,			\
> >>>> -			REG_GPIO_PON_MODE,			\
> >>>> -			(smux_val),				\
> >>>> -			(smux_val)				\
> >>>> -		},						\
> >>>> -		.regmap_size = 2,				\
> >>>> -	}
> >>>> -
> >>>> -#define AIROHA_PINCTRL_PHY_LED0(gpio, mux_val, map_mask, map_val)	\
> >>>> -	{								\
> >>>> -		.name = (gpio),						\
> >>>> -		.regmap[0] = {						\
> >>>> -			AIROHA_FUNC_MUX,				\
> >>>> -			REG_GPIO_2ND_I2C_MODE,				\
> >>>> -			(mux_val),					\
> >>>> -			(mux_val),					\
> >>>> -		},							\
> >>>> -		.regmap[1] = {						\
> >>>> -			AIROHA_FUNC_MUX,				\
> >>>> -			REG_LAN_LED0_MAPPING,				\
> >>>> -			(map_mask),					\
> >>>> -			(map_val),					\
> >>>> -		},							\
> >>>> -		.regmap_size = 2,					\
> >>>> -	}
> >>>> -
> >>>> -#define AIROHA_PINCTRL_PHY_LED1(gpio, mux_val, map_mask, map_val)	\
> >>>> -	{								\
> >>>> -		.name = (gpio),						\
> >>>> -		.regmap[0] = {						\
> >>>> -			AIROHA_FUNC_MUX,				\
> >>>> -			REG_GPIO_2ND_I2C_MODE,				\
> >>>> -			(mux_val),					\
> >>>> -			(mux_val),					\
> >>>> -		},							\
> >>>> -		.regmap[1] = {						\
> >>>> -			AIROHA_FUNC_MUX,				\
> >>>> -			REG_LAN_LED1_MAPPING,				\
> >>>> -			(map_mask),					\
> >>>> -			(map_val),					\
> >>>> -		},							\
> >>>> -		.regmap_size = 2,					\
> >>>> -	}
> >>>> -
> >>>>  #define airoha_pinctrl_get_pullup_conf(pinctrl, pin, val)			\
> >>>>  	airoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_PULLUP,		\
> >>>>  				(pin), (val))
> >>>> @@ -433,1935 +74,6 @@ static const u32 irq_edge_regs[] = {
> >>>>  	REG_GPIO_INT_EDGE3
> >>>>  };
> >>>>  
> >>>> -static struct pinctrl_pin_desc en7581_pinctrl_pins[] = {
> >>>> -	PINCTRL_PIN(0, "uart1_txd"),
> >>>> -	PINCTRL_PIN(1, "uart1_rxd"),
> >>>> -	PINCTRL_PIN(2, "i2c_scl"),
> >>>> -	PINCTRL_PIN(3, "i2c_sda"),
> >>>> -	PINCTRL_PIN(4, "spi_cs0"),
> >>>> -	PINCTRL_PIN(5, "spi_clk"),
> >>>> -	PINCTRL_PIN(6, "spi_mosi"),
> >>>> -	PINCTRL_PIN(7, "spi_miso"),
> >>>> -	PINCTRL_PIN(13, "gpio0"),
> >>>> -	PINCTRL_PIN(14, "gpio1"),
> >>>> -	PINCTRL_PIN(15, "gpio2"),
> >>>> -	PINCTRL_PIN(16, "gpio3"),
> >>>> -	PINCTRL_PIN(17, "gpio4"),
> >>>> -	PINCTRL_PIN(18, "gpio5"),
> >>>> -	PINCTRL_PIN(19, "gpio6"),
> >>>> -	PINCTRL_PIN(20, "gpio7"),
> >>>> -	PINCTRL_PIN(21, "gpio8"),
> >>>> -	PINCTRL_PIN(22, "gpio9"),
> >>>> -	PINCTRL_PIN(23, "gpio10"),
> >>>> -	PINCTRL_PIN(24, "gpio11"),
> >>>> -	PINCTRL_PIN(25, "gpio12"),
> >>>> -	PINCTRL_PIN(26, "gpio13"),
> >>>> -	PINCTRL_PIN(27, "gpio14"),
> >>>> -	PINCTRL_PIN(28, "gpio15"),
> >>>> -	PINCTRL_PIN(29, "gpio16"),
> >>>> -	PINCTRL_PIN(30, "gpio17"),
> >>>> -	PINCTRL_PIN(31, "gpio18"),
> >>>> -	PINCTRL_PIN(32, "gpio19"),
> >>>> -	PINCTRL_PIN(33, "gpio20"),
> >>>> -	PINCTRL_PIN(34, "gpio21"),
> >>>> -	PINCTRL_PIN(35, "gpio22"),
> >>>> -	PINCTRL_PIN(36, "gpio23"),
> >>>> -	PINCTRL_PIN(37, "gpio24"),
> >>>> -	PINCTRL_PIN(38, "gpio25"),
> >>>> -	PINCTRL_PIN(39, "gpio26"),
> >>>> -	PINCTRL_PIN(40, "gpio27"),
> >>>> -	PINCTRL_PIN(41, "gpio28"),
> >>>> -	PINCTRL_PIN(42, "gpio29"),
> >>>> -	PINCTRL_PIN(43, "gpio30"),
> >>>> -	PINCTRL_PIN(44, "gpio31"),
> >>>> -	PINCTRL_PIN(45, "gpio32"),
> >>>> -	PINCTRL_PIN(46, "gpio33"),
> >>>> -	PINCTRL_PIN(47, "gpio34"),
> >>>> -	PINCTRL_PIN(48, "gpio35"),
> >>>> -	PINCTRL_PIN(49, "gpio36"),
> >>>> -	PINCTRL_PIN(50, "gpio37"),
> >>>> -	PINCTRL_PIN(51, "gpio38"),
> >>>> -	PINCTRL_PIN(52, "gpio39"),
> >>>> -	PINCTRL_PIN(53, "gpio40"),
> >>>> -	PINCTRL_PIN(54, "gpio41"),
> >>>> -	PINCTRL_PIN(55, "gpio42"),
> >>>> -	PINCTRL_PIN(56, "gpio43"),
> >>>> -	PINCTRL_PIN(57, "gpio44"),
> >>>> -	PINCTRL_PIN(58, "gpio45"),
> >>>> -	PINCTRL_PIN(59, "gpio46"),
> >>>> -	PINCTRL_PIN(60, "pcie_reset0"),
> >>>> -	PINCTRL_PIN(61, "pcie_reset1"),
> >>>> -	PINCTRL_PIN(62, "pcie_reset2"),
> >>>> -};
> >>>> -
> >>>> -static const int en7581_pon_pins[] = { 49, 50, 51, 52, 53, 54 };
> >>>> -static const int en7581_pon_tod_1pps_pins[] = { 46 };
> >>>> -static const int en7581_gsw_tod_1pps_pins[] = { 46 };
> >>>> -static const int en7581_sipo_pins[] = { 16, 17 };
> >>>> -static const int en7581_sipo_rclk_pins[] = { 16, 17, 43 };
> >>>> -static const int en7581_mdio_pins[] = { 14, 15 };
> >>>> -static const int en7581_uart2_pins[] = { 48, 55 };
> >>>> -static const int en7581_uart2_cts_rts_pins[] = { 46, 47 };
> >>>> -static const int en7581_hsuart_pins[] = { 28, 29 };
> >>>> -static const int en7581_hsuart_cts_rts_pins[] = { 26, 27 };
> >>>> -static const int en7581_uart4_pins[] = { 38, 39 };
> >>>> -static const int en7581_uart5_pins[] = { 18, 19 };
> >>>> -static const int en7581_i2c0_pins[] = { 2, 3 };
> >>>> -static const int en7581_i2c1_pins[] = { 14, 15 };
> >>>> -static const int en7581_jtag_udi_pins[] = { 16, 17, 18, 19, 20 };
> >>>> -static const int en7581_jtag_dfd_pins[] = { 16, 17, 18, 19, 20 };
> >>>> -static const int en7581_i2s_pins[] = { 26, 27, 28, 29 };
> >>>> -static const int en7581_pcm1_pins[] = { 22, 23, 24, 25 };
> >>>> -static const int en7581_pcm2_pins[] = { 18, 19, 20, 21 };
> >>>> -static const int en7581_spi_quad_pins[] = { 32, 33 };
> >>>> -static const int en7581_spi_pins[] = { 4, 5, 6, 7 };
> >>>> -static const int en7581_spi_cs1_pins[] = { 34 };
> >>>> -static const int en7581_pcm_spi_pins[] = { 18, 19, 20, 21, 22, 23, 24, 25 };
> >>>> -static const int en7581_pcm_spi_int_pins[] = { 14 };
> >>>> -static const int en7581_pcm_spi_rst_pins[] = { 15 };
> >>>> -static const int en7581_pcm_spi_cs1_pins[] = { 43 };
> >>>> -static const int en7581_pcm_spi_cs2_pins[] = { 40 };
> >>>> -static const int en7581_pcm_spi_cs2_p128_pins[] = { 40 };
> >>>> -static const int en7581_pcm_spi_cs2_p156_pins[] = { 40 };
> >>>> -static const int en7581_pcm_spi_cs3_pins[] = { 41 };
> >>>> -static const int en7581_pcm_spi_cs4_pins[] = { 42 };
> >>>> -static const int en7581_emmc_pins[] = { 4, 5, 6, 30, 31, 32, 33, 34, 35, 36, 37 };
> >>>> -static const int en7581_pnand_pins[] = { 4, 5, 6, 7, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42 };
> >>>> -static const int en7581_gpio0_pins[] = { 13 };
> >>>> -static const int en7581_gpio1_pins[] = { 14 };
> >>>> -static const int en7581_gpio2_pins[] = { 15 };
> >>>> -static const int en7581_gpio3_pins[] = { 16 };
> >>>> -static const int en7581_gpio4_pins[] = { 17 };
> >>>> -static const int en7581_gpio5_pins[] = { 18 };
> >>>> -static const int en7581_gpio6_pins[] = { 19 };
> >>>> -static const int en7581_gpio7_pins[] = { 20 };
> >>>> -static const int en7581_gpio8_pins[] = { 21 };
> >>>> -static const int en7581_gpio9_pins[] = { 22 };
> >>>> -static const int en7581_gpio10_pins[] = { 23 };
> >>>> -static const int en7581_gpio11_pins[] = { 24 };
> >>>> -static const int en7581_gpio12_pins[] = { 25 };
> >>>> -static const int en7581_gpio13_pins[] = { 26 };
> >>>> -static const int en7581_gpio14_pins[] = { 27 };
> >>>> -static const int en7581_gpio15_pins[] = { 28 };
> >>>> -static const int en7581_gpio16_pins[] = { 29 };
> >>>> -static const int en7581_gpio17_pins[] = { 30 };
> >>>> -static const int en7581_gpio18_pins[] = { 31 };
> >>>> -static const int en7581_gpio19_pins[] = { 32 };
> >>>> -static const int en7581_gpio20_pins[] = { 33 };
> >>>> -static const int en7581_gpio21_pins[] = { 34 };
> >>>> -static const int en7581_gpio22_pins[] = { 35 };
> >>>> -static const int en7581_gpio23_pins[] = { 36 };
> >>>> -static const int en7581_gpio24_pins[] = { 37 };
> >>>> -static const int en7581_gpio25_pins[] = { 38 };
> >>>> -static const int en7581_gpio26_pins[] = { 39 };
> >>>> -static const int en7581_gpio27_pins[] = { 40 };
> >>>> -static const int en7581_gpio28_pins[] = { 41 };
> >>>> -static const int en7581_gpio29_pins[] = { 42 };
> >>>> -static const int en7581_gpio30_pins[] = { 43 };
> >>>> -static const int en7581_gpio31_pins[] = { 44 };
> >>>> -static const int en7581_gpio32_pins[] = { 45 };
> >>>> -static const int en7581_gpio33_pins[] = { 46 };
> >>>> -static const int en7581_gpio34_pins[] = { 47 };
> >>>> -static const int en7581_gpio35_pins[] = { 48 };
> >>>> -static const int en7581_gpio36_pins[] = { 49 };
> >>>> -static const int en7581_gpio37_pins[] = { 50 };
> >>>> -static const int en7581_gpio38_pins[] = { 51 };
> >>>> -static const int en7581_gpio39_pins[] = { 52 };
> >>>> -static const int en7581_gpio40_pins[] = { 53 };
> >>>> -static const int en7581_gpio41_pins[] = { 54 };
> >>>> -static const int en7581_gpio42_pins[] = { 55 };
> >>>> -static const int en7581_gpio43_pins[] = { 56 };
> >>>> -static const int en7581_gpio44_pins[] = { 57 };
> >>>> -static const int en7581_gpio45_pins[] = { 58 };
> >>>> -static const int en7581_gpio46_pins[] = { 59 };
> >>>> -static const int en7581_gpio47_pins[] = { 60 };
> >>>> -static const int en7581_gpio48_pins[] = { 61 };
> >>>> -static const int en7581_gpio49_pins[] = { 62 };
> >>>> -static const int en7581_pcie_reset0_pins[] = { 60 };
> >>>> -static const int en7581_pcie_reset1_pins[] = { 61 };
> >>>> -static const int en7581_pcie_reset2_pins[] = { 62 };
> >>>> -
> >>>> -static const struct pingroup en7581_pinctrl_groups[] = {
> >>>> -	PINCTRL_PIN_GROUP("pon", en7581_pon),
> >>>> -	PINCTRL_PIN_GROUP("pon_tod_1pps", en7581_pon_tod_1pps),
> >>>> -	PINCTRL_PIN_GROUP("gsw_tod_1pps", en7581_gsw_tod_1pps),
> >>>> -	PINCTRL_PIN_GROUP("sipo", en7581_sipo),
> >>>> -	PINCTRL_PIN_GROUP("sipo_rclk", en7581_sipo_rclk),
> >>>> -	PINCTRL_PIN_GROUP("mdio", en7581_mdio),
> >>>> -	PINCTRL_PIN_GROUP("uart2", en7581_uart2),
> >>>> -	PINCTRL_PIN_GROUP("uart2_cts_rts", en7581_uart2_cts_rts),
> >>>> -	PINCTRL_PIN_GROUP("hsuart", en7581_hsuart),
> >>>> -	PINCTRL_PIN_GROUP("hsuart_cts_rts", en7581_hsuart_cts_rts),
> >>>> -	PINCTRL_PIN_GROUP("uart4", en7581_uart4),
> >>>> -	PINCTRL_PIN_GROUP("uart5", en7581_uart5),
> >>>> -	PINCTRL_PIN_GROUP("i2c0", en7581_i2c0),
> >>>> -	PINCTRL_PIN_GROUP("i2c1", en7581_i2c1),
> >>>> -	PINCTRL_PIN_GROUP("jtag_udi", en7581_jtag_udi),
> >>>> -	PINCTRL_PIN_GROUP("jtag_dfd", en7581_jtag_dfd),
> >>>> -	PINCTRL_PIN_GROUP("i2s", en7581_i2s),
> >>>> -	PINCTRL_PIN_GROUP("pcm1", en7581_pcm1),
> >>>> -	PINCTRL_PIN_GROUP("pcm2", en7581_pcm2),
> >>>> -	PINCTRL_PIN_GROUP("spi", en7581_spi),
> >>>> -	PINCTRL_PIN_GROUP("spi_quad", en7581_spi_quad),
> >>>> -	PINCTRL_PIN_GROUP("spi_cs1", en7581_spi_cs1),
> >>>> -	PINCTRL_PIN_GROUP("pcm_spi", en7581_pcm_spi),
> >>>> -	PINCTRL_PIN_GROUP("pcm_spi_int", en7581_pcm_spi_int),
> >>>> -	PINCTRL_PIN_GROUP("pcm_spi_rst", en7581_pcm_spi_rst),
> >>>> -	PINCTRL_PIN_GROUP("pcm_spi_cs1", en7581_pcm_spi_cs1),
> >>>> -	PINCTRL_PIN_GROUP("pcm_spi_cs2_p128", en7581_pcm_spi_cs2_p128),
> >>>> -	PINCTRL_PIN_GROUP("pcm_spi_cs2_p156", en7581_pcm_spi_cs2_p156),
> >>>> -	PINCTRL_PIN_GROUP("pcm_spi_cs2", en7581_pcm_spi_cs2),
> >>>> -	PINCTRL_PIN_GROUP("pcm_spi_cs3", en7581_pcm_spi_cs3),
> >>>> -	PINCTRL_PIN_GROUP("pcm_spi_cs4", en7581_pcm_spi_cs4),
> >>>> -	PINCTRL_PIN_GROUP("emmc", en7581_emmc),
> >>>> -	PINCTRL_PIN_GROUP("pnand", en7581_pnand),
> >>>> -	PINCTRL_PIN_GROUP("gpio0", en7581_gpio0),
> >>>> -	PINCTRL_PIN_GROUP("gpio1", en7581_gpio1),
> >>>> -	PINCTRL_PIN_GROUP("gpio2", en7581_gpio2),
> >>>> -	PINCTRL_PIN_GROUP("gpio3", en7581_gpio3),
> >>>> -	PINCTRL_PIN_GROUP("gpio4", en7581_gpio4),
> >>>> -	PINCTRL_PIN_GROUP("gpio5", en7581_gpio5),
> >>>> -	PINCTRL_PIN_GROUP("gpio6", en7581_gpio6),
> >>>> -	PINCTRL_PIN_GROUP("gpio7", en7581_gpio7),
> >>>> -	PINCTRL_PIN_GROUP("gpio8", en7581_gpio8),
> >>>> -	PINCTRL_PIN_GROUP("gpio9", en7581_gpio9),
> >>>> -	PINCTRL_PIN_GROUP("gpio10", en7581_gpio10),
> >>>> -	PINCTRL_PIN_GROUP("gpio11", en7581_gpio11),
> >>>> -	PINCTRL_PIN_GROUP("gpio12", en7581_gpio12),
> >>>> -	PINCTRL_PIN_GROUP("gpio13", en7581_gpio13),
> >>>> -	PINCTRL_PIN_GROUP("gpio14", en7581_gpio14),
> >>>> -	PINCTRL_PIN_GROUP("gpio15", en7581_gpio15),
> >>>> -	PINCTRL_PIN_GROUP("gpio16", en7581_gpio16),
> >>>> -	PINCTRL_PIN_GROUP("gpio17", en7581_gpio17),
> >>>> -	PINCTRL_PIN_GROUP("gpio18", en7581_gpio18),
> >>>> -	PINCTRL_PIN_GROUP("gpio19", en7581_gpio19),
> >>>> -	PINCTRL_PIN_GROUP("gpio20", en7581_gpio20),
> >>>> -	PINCTRL_PIN_GROUP("gpio21", en7581_gpio21),
> >>>> -	PINCTRL_PIN_GROUP("gpio22", en7581_gpio22),
> >>>> -	PINCTRL_PIN_GROUP("gpio23", en7581_gpio23),
> >>>> -	PINCTRL_PIN_GROUP("gpio24", en7581_gpio24),
> >>>> -	PINCTRL_PIN_GROUP("gpio25", en7581_gpio25),
> >>>> -	PINCTRL_PIN_GROUP("gpio26", en7581_gpio26),
> >>>> -	PINCTRL_PIN_GROUP("gpio27", en7581_gpio27),
> >>>> -	PINCTRL_PIN_GROUP("gpio28", en7581_gpio28),
> >>>> -	PINCTRL_PIN_GROUP("gpio29", en7581_gpio29),
> >>>> -	PINCTRL_PIN_GROUP("gpio30", en7581_gpio30),
> >>>> -	PINCTRL_PIN_GROUP("gpio31", en7581_gpio31),
> >>>> -	PINCTRL_PIN_GROUP("gpio32", en7581_gpio32),
> >>>> -	PINCTRL_PIN_GROUP("gpio33", en7581_gpio33),
> >>>> -	PINCTRL_PIN_GROUP("gpio34", en7581_gpio34),
> >>>> -	PINCTRL_PIN_GROUP("gpio35", en7581_gpio35),
> >>>> -	PINCTRL_PIN_GROUP("gpio36", en7581_gpio36),
> >>>> -	PINCTRL_PIN_GROUP("gpio37", en7581_gpio37),
> >>>> -	PINCTRL_PIN_GROUP("gpio38", en7581_gpio38),
> >>>> -	PINCTRL_PIN_GROUP("gpio39", en7581_gpio39),
> >>>> -	PINCTRL_PIN_GROUP("gpio40", en7581_gpio40),
> >>>> -	PINCTRL_PIN_GROUP("gpio41", en7581_gpio41),
> >>>> -	PINCTRL_PIN_GROUP("gpio42", en7581_gpio42),
> >>>> -	PINCTRL_PIN_GROUP("gpio43", en7581_gpio43),
> >>>> -	PINCTRL_PIN_GROUP("gpio44", en7581_gpio44),
> >>>> -	PINCTRL_PIN_GROUP("gpio45", en7581_gpio45),
> >>>> -	PINCTRL_PIN_GROUP("gpio46", en7581_gpio46),
> >>>> -	PINCTRL_PIN_GROUP("gpio47", en7581_gpio47),
> >>>> -	PINCTRL_PIN_GROUP("gpio48", en7581_gpio48),
> >>>> -	PINCTRL_PIN_GROUP("gpio49", en7581_gpio49),
> >>>> -	PINCTRL_PIN_GROUP("pcie_reset0", en7581_pcie_reset0),
> >>>> -	PINCTRL_PIN_GROUP("pcie_reset1", en7581_pcie_reset1),
> >>>> -	PINCTRL_PIN_GROUP("pcie_reset2", en7581_pcie_reset2),
> >>>> -};
> >>>> -
> >>>> -static struct pinctrl_pin_desc an7583_pinctrl_pins[] = {
> >>>> -	PINCTRL_PIN(2, "gpio0"),
> >>>> -	PINCTRL_PIN(3, "gpio1"),
> >>>> -	PINCTRL_PIN(4, "gpio2"),
> >>>> -	PINCTRL_PIN(5, "gpio3"),
> >>>> -	PINCTRL_PIN(6, "gpio4"),
> >>>> -	PINCTRL_PIN(7, "gpio5"),
> >>>> -	PINCTRL_PIN(8, "gpio6"),
> >>>> -	PINCTRL_PIN(9, "gpio7"),
> >>>> -	PINCTRL_PIN(10, "gpio8"),
> >>>> -	PINCTRL_PIN(11, "gpio9"),
> >>>> -	PINCTRL_PIN(12, "gpio10"),
> >>>> -	PINCTRL_PIN(13, "gpio11"),
> >>>> -	PINCTRL_PIN(14, "gpio12"),
> >>>> -	PINCTRL_PIN(15, "gpio13"),
> >>>> -	PINCTRL_PIN(16, "gpio14"),
> >>>> -	PINCTRL_PIN(17, "gpio15"),
> >>>> -	PINCTRL_PIN(18, "gpio16"),
> >>>> -	PINCTRL_PIN(19, "gpio17"),
> >>>> -	PINCTRL_PIN(20, "gpio18"),
> >>>> -	PINCTRL_PIN(21, "gpio19"),
> >>>> -	PINCTRL_PIN(22, "gpio20"),
> >>>> -	PINCTRL_PIN(23, "gpio21"),
> >>>> -	PINCTRL_PIN(24, "gpio22"),
> >>>> -	PINCTRL_PIN(25, "gpio23"),
> >>>> -	PINCTRL_PIN(26, "gpio24"),
> >>>> -	PINCTRL_PIN(27, "gpio25"),
> >>>> -	PINCTRL_PIN(28, "gpio26"),
> >>>> -	PINCTRL_PIN(29, "gpio27"),
> >>>> -	PINCTRL_PIN(30, "gpio28"),
> >>>> -	PINCTRL_PIN(31, "gpio29"),
> >>>> -	PINCTRL_PIN(32, "gpio30"),
> >>>> -	PINCTRL_PIN(33, "gpio31"),
> >>>> -	PINCTRL_PIN(34, "gpio32"),
> >>>> -	PINCTRL_PIN(35, "gpio33"),
> >>>> -	PINCTRL_PIN(36, "gpio34"),
> >>>> -	PINCTRL_PIN(37, "gpio35"),
> >>>> -	PINCTRL_PIN(38, "gpio36"),
> >>>> -	PINCTRL_PIN(39, "gpio37"),
> >>>> -	PINCTRL_PIN(40, "gpio38"),
> >>>> -	PINCTRL_PIN(41, "i2c0_scl"),
> >>>> -	PINCTRL_PIN(42, "i2c0_sda"),
> >>>> -	PINCTRL_PIN(43, "i2c1_scl"),
> >>>> -	PINCTRL_PIN(44, "i2c1_sda"),
> >>>> -	PINCTRL_PIN(45, "spi_clk"),
> >>>> -	PINCTRL_PIN(46, "spi_cs"),
> >>>> -	PINCTRL_PIN(47, "spi_mosi"),
> >>>> -	PINCTRL_PIN(48, "spi_miso"),
> >>>> -	PINCTRL_PIN(49, "uart_txd"),
> >>>> -	PINCTRL_PIN(50, "uart_rxd"),
> >>>> -	PINCTRL_PIN(51, "pcie_reset0"),
> >>>> -	PINCTRL_PIN(52, "pcie_reset1"),
> >>>> -	PINCTRL_PIN(53, "mdc_0"),
> >>>> -	PINCTRL_PIN(54, "mdio_0"),
> >>>> -};
> >>>> -
> >>>> -static const int an7583_pon_pins[] = { 15, 16, 17, 18, 19, 20 };
> >>>> -static const int an7583_pon_tod_1pps_pins[] = { 32 };
> >>>> -static const int an7583_gsw_tod_1pps_pins[] = { 32 };
> >>>> -static const int an7583_sipo_pins[] = { 34, 35 };
> >>>> -static const int an7583_sipo_rclk_pins[] = { 34, 35, 33 };
> >>>> -static const int an7583_mdio_pins[] = { 43, 44 };
> >>>> -static const int an7583_uart2_pins[] = { 34, 35 };
> >>>> -static const int an7583_uart2_cts_rts_pins[] = { 32, 33 };
> >>>> -static const int an7583_hsuart_pins[] = { 30, 31 };
> >>>> -static const int an7583_hsuart_cts_rts_pins[] = { 28, 29 };
> >>>> -static const int an7583_npu_uart_pins[] = { 7, 8 };
> >>>> -static const int an7583_uart4_pins[] = { 7, 8 };
> >>>> -static const int an7583_uart5_pins[] = { 23, 24 };
> >>>> -static const int an7583_i2c0_pins[] = { 41, 42 };
> >>>> -static const int an7583_i2c1_pins[] = { 43, 44 };
> >>>> -static const int an7583_jtag_udi_pins[] = { 23, 24, 22, 25, 26 };
> >>>> -static const int an7583_jtag_dfd_pins[] = { 23, 24, 22, 25, 26 };
> >>>> -static const int an7583_pcm1_pins[] = { 10, 11, 12, 13, 14 };
> >>>> -static const int an7583_pcm2_pins[] = { 28, 29, 30, 31, 24 };
> >>>> -static const int an7583_spi_pins[] = { 28, 29, 30, 31 };
> >>>> -static const int an7583_spi_quad_pins[] = { 25, 26 };
> >>>> -static const int an7583_spi_cs1_pins[] = { 27 };
> >>>> -static const int an7583_pcm_spi_pins[] = { 28, 29, 30, 31, 10, 11, 12, 13 };
> >>>> -static const int an7583_pcm_spi_rst_pins[] = { 14 };
> >>>> -static const int an7583_pcm_spi_cs1_pins[] = { 24 };
> >>>> -static const int an7583_emmc_pins[] = { 7, 8, 9, 22, 23, 24, 25, 26, 45, 46, 47 };
> >>>> -static const int an7583_pnand_pins[] = { 7, 8, 9, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 45, 46, 47, 48 };
> >>>> -static const int an7583_gpio0_pins[] = { 2 };
> >>>> -static const int an7583_gpio1_pins[] = { 3 };
> >>>> -static const int an7583_gpio2_pins[] = { 4 };
> >>>> -static const int an7583_gpio3_pins[] = { 5 };
> >>>> -static const int an7583_gpio4_pins[] = { 6 };
> >>>> -static const int an7583_gpio5_pins[] = { 7 };
> >>>> -static const int an7583_gpio6_pins[] = { 8 };
> >>>> -static const int an7583_gpio7_pins[] = { 9 };
> >>>> -static const int an7583_gpio8_pins[] = { 10 };
> >>>> -static const int an7583_gpio9_pins[] = { 11 };
> >>>> -static const int an7583_gpio10_pins[] = { 12 };
> >>>> -static const int an7583_gpio11_pins[] = { 13 };
> >>>> -static const int an7583_gpio12_pins[] = { 14 };
> >>>> -static const int an7583_gpio13_pins[] = { 15 };
> >>>> -static const int an7583_gpio14_pins[] = { 16 };
> >>>> -static const int an7583_gpio15_pins[] = { 17 };
> >>>> -static const int an7583_gpio16_pins[] = { 18 };
> >>>> -static const int an7583_gpio17_pins[] = { 19 };
> >>>> -static const int an7583_gpio18_pins[] = { 20 };
> >>>> -static const int an7583_gpio19_pins[] = { 21 };
> >>>> -static const int an7583_gpio20_pins[] = { 22 };
> >>>> -static const int an7583_gpio21_pins[] = { 23 };
> >>>> -static const int an7583_gpio22_pins[] = { 24 };
> >>>> -static const int an7583_gpio23_pins[] = { 25 };
> >>>> -static const int an7583_gpio24_pins[] = { 26 };
> >>>> -static const int an7583_gpio25_pins[] = { 27 };
> >>>> -static const int an7583_gpio26_pins[] = { 28 };
> >>>> -static const int an7583_gpio27_pins[] = { 29 };
> >>>> -static const int an7583_gpio28_pins[] = { 30 };
> >>>> -static const int an7583_gpio29_pins[] = { 31 };
> >>>> -static const int an7583_gpio30_pins[] = { 32 };
> >>>> -static const int an7583_gpio31_pins[] = { 33 };
> >>>> -static const int an7583_gpio32_pins[] = { 34 };
> >>>> -static const int an7583_gpio33_pins[] = { 35 };
> >>>> -static const int an7583_gpio34_pins[] = { 36 };
> >>>> -static const int an7583_gpio35_pins[] = { 37 };
> >>>> -static const int an7583_gpio36_pins[] = { 38 };
> >>>> -static const int an7583_gpio37_pins[] = { 39 };
> >>>> -static const int an7583_gpio38_pins[] = { 40 };
> >>>> -static const int an7583_gpio39_pins[] = { 41 };
> >>>> -static const int an7583_gpio40_pins[] = { 42 };
> >>>> -static const int an7583_gpio41_pins[] = { 43 };
> >>>> -static const int an7583_gpio42_pins[] = { 44 };
> >>>> -static const int an7583_gpio43_pins[] = { 45 };
> >>>> -static const int an7583_gpio44_pins[] = { 46 };
> >>>> -static const int an7583_gpio45_pins[] = { 47 };
> >>>> -static const int an7583_gpio46_pins[] = { 48 };
> >>>> -static const int an7583_gpio47_pins[] = { 49 };
> >>>> -static const int an7583_gpio48_pins[] = { 50 };
> >>>> -static const int an7583_gpio49_pins[] = { 51 };
> >>>> -static const int an7583_gpio50_pins[] = { 52 };
> >>>> -static const int an7583_gpio51_pins[] = { 53 };
> >>>> -static const int an7583_gpio52_pins[] = { 54 };
> >>>> -static const int an7583_pcie_reset0_pins[] = { 51 };
> >>>> -static const int an7583_pcie_reset1_pins[] = { 52 };
> >>>> -
> >>>> -static const struct pingroup an7583_pinctrl_groups[] = {
> >>>> -	PINCTRL_PIN_GROUP("pon", an7583_pon),
> >>>> -	PINCTRL_PIN_GROUP("pon_tod_1pps", an7583_pon_tod_1pps),
> >>>> -	PINCTRL_PIN_GROUP("gsw_tod_1pps", an7583_gsw_tod_1pps),
> >>>> -	PINCTRL_PIN_GROUP("sipo", an7583_sipo),
> >>>> -	PINCTRL_PIN_GROUP("sipo_rclk", an7583_sipo_rclk),
> >>>> -	PINCTRL_PIN_GROUP("mdio", an7583_mdio),
> >>>> -	PINCTRL_PIN_GROUP("uart2", an7583_uart2),
> >>>> -	PINCTRL_PIN_GROUP("uart2_cts_rts", an7583_uart2_cts_rts),
> >>>> -	PINCTRL_PIN_GROUP("hsuart", an7583_hsuart),
> >>>> -	PINCTRL_PIN_GROUP("hsuart_cts_rts", an7583_hsuart_cts_rts),
> >>>> -	PINCTRL_PIN_GROUP("npu_uart", an7583_npu_uart),
> >>>> -	PINCTRL_PIN_GROUP("uart4", an7583_uart4),
> >>>> -	PINCTRL_PIN_GROUP("uart5", an7583_uart5),
> >>>> -	PINCTRL_PIN_GROUP("i2c0", an7583_i2c0),
> >>>> -	PINCTRL_PIN_GROUP("i2c1", an7583_i2c1),
> >>>> -	PINCTRL_PIN_GROUP("jtag_udi", an7583_jtag_udi),
> >>>> -	PINCTRL_PIN_GROUP("jtag_dfd", an7583_jtag_dfd),
> >>>> -	PINCTRL_PIN_GROUP("pcm1", an7583_pcm1),
> >>>> -	PINCTRL_PIN_GROUP("pcm2", an7583_pcm2),
> >>>> -	PINCTRL_PIN_GROUP("spi", an7583_spi),
> >>>> -	PINCTRL_PIN_GROUP("spi_quad", an7583_spi_quad),
> >>>> -	PINCTRL_PIN_GROUP("spi_cs1", an7583_spi_cs1),
> >>>> -	PINCTRL_PIN_GROUP("pcm_spi", an7583_pcm_spi),
> >>>> -	PINCTRL_PIN_GROUP("pcm_spi_rst", an7583_pcm_spi_rst),
> >>>> -	PINCTRL_PIN_GROUP("pcm_spi_cs1", an7583_pcm_spi_cs1),
> >>>> -	PINCTRL_PIN_GROUP("emmc", an7583_emmc),
> >>>> -	PINCTRL_PIN_GROUP("pnand", an7583_pnand),
> >>>> -	PINCTRL_PIN_GROUP("gpio0", an7583_gpio0),
> >>>> -	PINCTRL_PIN_GROUP("gpio1", an7583_gpio1),
> >>>> -	PINCTRL_PIN_GROUP("gpio2", an7583_gpio2),
> >>>> -	PINCTRL_PIN_GROUP("gpio3", an7583_gpio3),
> >>>> -	PINCTRL_PIN_GROUP("gpio4", an7583_gpio4),
> >>>> -	PINCTRL_PIN_GROUP("gpio5", an7583_gpio5),
> >>>> -	PINCTRL_PIN_GROUP("gpio6", an7583_gpio6),
> >>>> -	PINCTRL_PIN_GROUP("gpio7", an7583_gpio7),
> >>>> -	PINCTRL_PIN_GROUP("gpio8", an7583_gpio8),
> >>>> -	PINCTRL_PIN_GROUP("gpio9", an7583_gpio9),
> >>>> -	PINCTRL_PIN_GROUP("gpio10", an7583_gpio10),
> >>>> -	PINCTRL_PIN_GROUP("gpio11", an7583_gpio11),
> >>>> -	PINCTRL_PIN_GROUP("gpio12", an7583_gpio12),
> >>>> -	PINCTRL_PIN_GROUP("gpio13", an7583_gpio13),
> >>>> -	PINCTRL_PIN_GROUP("gpio14", an7583_gpio14),
> >>>> -	PINCTRL_PIN_GROUP("gpio15", an7583_gpio15),
> >>>> -	PINCTRL_PIN_GROUP("gpio16", an7583_gpio16),
> >>>> -	PINCTRL_PIN_GROUP("gpio17", an7583_gpio17),
> >>>> -	PINCTRL_PIN_GROUP("gpio18", an7583_gpio18),
> >>>> -	PINCTRL_PIN_GROUP("gpio19", an7583_gpio19),
> >>>> -	PINCTRL_PIN_GROUP("gpio20", an7583_gpio20),
> >>>> -	PINCTRL_PIN_GROUP("gpio21", an7583_gpio21),
> >>>> -	PINCTRL_PIN_GROUP("gpio22", an7583_gpio22),
> >>>> -	PINCTRL_PIN_GROUP("gpio23", an7583_gpio23),
> >>>> -	PINCTRL_PIN_GROUP("gpio24", an7583_gpio24),
> >>>> -	PINCTRL_PIN_GROUP("gpio25", an7583_gpio25),
> >>>> -	PINCTRL_PIN_GROUP("gpio26", an7583_gpio26),
> >>>> -	PINCTRL_PIN_GROUP("gpio27", an7583_gpio27),
> >>>> -	PINCTRL_PIN_GROUP("gpio28", an7583_gpio28),
> >>>> -	PINCTRL_PIN_GROUP("gpio29", an7583_gpio29),
> >>>> -	PINCTRL_PIN_GROUP("gpio30", an7583_gpio30),
> >>>> -	PINCTRL_PIN_GROUP("gpio31", an7583_gpio31),
> >>>> -	PINCTRL_PIN_GROUP("gpio32", an7583_gpio32),
> >>>> -	PINCTRL_PIN_GROUP("gpio33", an7583_gpio33),
> >>>> -	PINCTRL_PIN_GROUP("gpio34", an7583_gpio34),
> >>>> -	PINCTRL_PIN_GROUP("gpio35", an7583_gpio35),
> >>>> -	PINCTRL_PIN_GROUP("gpio36", an7583_gpio36),
> >>>> -	PINCTRL_PIN_GROUP("gpio37", an7583_gpio37),
> >>>> -	PINCTRL_PIN_GROUP("gpio38", an7583_gpio38),
> >>>> -	PINCTRL_PIN_GROUP("gpio39", an7583_gpio39),
> >>>> -	PINCTRL_PIN_GROUP("gpio40", an7583_gpio40),
> >>>> -	PINCTRL_PIN_GROUP("gpio41", an7583_gpio41),
> >>>> -	PINCTRL_PIN_GROUP("gpio42", an7583_gpio42),
> >>>> -	PINCTRL_PIN_GROUP("gpio43", an7583_gpio43),
> >>>> -	PINCTRL_PIN_GROUP("gpio44", an7583_gpio44),
> >>>> -	PINCTRL_PIN_GROUP("gpio45", an7583_gpio45),
> >>>> -	PINCTRL_PIN_GROUP("gpio46", an7583_gpio46),
> >>>> -	PINCTRL_PIN_GROUP("gpio47", an7583_gpio47),
> >>>> -	PINCTRL_PIN_GROUP("gpio48", an7583_gpio48),
> >>>> -	PINCTRL_PIN_GROUP("gpio49", an7583_gpio49),
> >>>> -	PINCTRL_PIN_GROUP("gpio50", an7583_gpio50),
> >>>> -	PINCTRL_PIN_GROUP("gpio51", an7583_gpio51),
> >>>> -	PINCTRL_PIN_GROUP("gpio52", an7583_gpio52),
> >>>> -	PINCTRL_PIN_GROUP("pcie_reset0", an7583_pcie_reset0),
> >>>> -	PINCTRL_PIN_GROUP("pcie_reset1", an7583_pcie_reset1),
> >>>> -};
> >>>> -
> >>>> -static const char *const pon_groups[] = { "pon" };
> >>>> -static const char *const tod_1pps_groups[] = { "pon_tod_1pps", "gsw_tod_1pps" };
> >>>> -static const char *const sipo_groups[] = { "sipo", "sipo_rclk" };
> >>>> -static const char *const mdio_groups[] = { "mdio" };
> >>>> -static const char *const an7583_mdio_groups[] = { "mdio" };
> >>>> -static const char *const uart_groups[] = { "uart2", "uart2_cts_rts", "hsuart",
> >>>> -					   "hsuart_cts_rts", "uart4",
> >>>> -					   "uart5" };
> >>>> -static const char *const i2c_groups[] = { "i2c1" };
> >>>> -static const char *const jtag_groups[] = { "jtag_udi", "jtag_dfd" };
> >>>> -static const char *const pcm_groups[] = { "pcm1", "pcm2" };
> >>>> -static const char *const spi_groups[] = { "spi_quad", "spi_cs1" };
> >>>> -static const char *const pcm_spi_groups[] = { "pcm_spi", "pcm_spi_int",
> >>>> -					      "pcm_spi_rst", "pcm_spi_cs1",
> >>>> -					      "pcm_spi_cs2_p156",
> >>>> -					      "pcm_spi_cs2_p128",
> >>>> -					      "pcm_spi_cs3", "pcm_spi_cs4" };
> >>>> -static const char *const an7583_pcm_spi_groups[] = { "pcm_spi",
> >>>> -						     "pcm_spi_rst", "pcm_spi_cs1" };
> >>>> -static const char *const i2s_groups[] = { "i2s" };
> >>>> -static const char *const emmc_groups[] = { "emmc" };
> >>>> -static const char *const pnand_groups[] = { "pnand" };
> >>>> -static const char *const gpio_groups[] = { "gpio47", "gpio48", "gpio49" };
> >>>> -static const char *const pcie_reset_groups[] = { "pcie_reset0", "pcie_reset1",
> >>>> -						 "pcie_reset2" };
> >>>> -static const char *const an7583_gpio_groups[] = { "gpio39", "gpio40", "gpio41",
> >>>> -						  "gpio42", "gpio43", "gpio44",
> >>>> -						  "gpio45", "gpio46", "gpio47",
> >>>> -						  "gpio48", "gpio49", "gpio50",
> >>>> -						  "gpio51", "gpio52" };
> >>>> -static const char *const an7583_pcie_reset_groups[] = { "pcie_reset0", "pcie_reset1" };
> >>>> -static const char *const pwm_groups[] = { "gpio0", "gpio1",
> >>>> -					  "gpio2", "gpio3",
> >>>> -					  "gpio4", "gpio5",
> >>>> -					  "gpio6", "gpio7",
> >>>> -					  "gpio8", "gpio9",
> >>>> -					  "gpio10", "gpio11",
> >>>> -					  "gpio12", "gpio13",
> >>>> -					  "gpio14", "gpio15",
> >>>> -					  "gpio16", "gpio17",
> >>>> -					  "gpio18", "gpio19",
> >>>> -					  "gpio20", "gpio21",
> >>>> -					  "gpio22", "gpio23",
> >>>> -					  "gpio24", "gpio25",
> >>>> -					  "gpio26", "gpio27",
> >>>> -					  "gpio28", "gpio29",
> >>>> -					  "gpio30", "gpio31",
> >>>> -					  "gpio36", "gpio37",
> >>>> -					  "gpio38", "gpio39",
> >>>> -					  "gpio40", "gpio41",
> >>>> -					  "gpio42", "gpio43",
> >>>> -					  "gpio44", "gpio45",
> >>>> -					  "gpio46", "gpio47",
> >>>> -					  "gpio48", "gpio49" };
> >>>> -static const char *const an7583_pwm_groups[] = { "gpio0", "gpio1",
> >>>> -						 "gpio2", "gpio3",
> >>>> -						 "gpio4", "gpio5",
> >>>> -						 "gpio6", "gpio7",
> >>>> -						 "gpio8", "gpio9",
> >>>> -						 "gpio10", "gpio11",
> >>>> -						 "gpio12", "gpio13",
> >>>> -						 "gpio14", "gpio15",
> >>>> -						 "gpio16", "gpio17",
> >>>> -						 "gpio18", "gpio19",
> >>>> -						 "gpio20", "gpio21",
> >>>> -						 "gpio22", "gpio23",
> >>>> -						 "gpio24", "gpio25",
> >>>> -						 "gpio26", "gpio27",
> >>>> -						 "gpio28", "gpio29",
> >>>> -						 "gpio30", "gpio31",
> >>>> -						 "gpio36", "gpio37",
> >>>> -						 "gpio38", "gpio39",
> >>>> -						 "gpio40", "gpio41",
> >>>> -						 "gpio42", "gpio43",
> >>>> -						 "gpio44", "gpio45",
> >>>> -						 "gpio46", "gpio47",
> >>>> -						 "gpio48", "gpio49",
> >>>> -						 "gpio50", "gpio51" };
> >>>> -static const char *const phy1_led0_groups[] = { "gpio33", "gpio34",
> >>>> -						"gpio35", "gpio42" };
> >>>> -static const char *const phy2_led0_groups[] = { "gpio33", "gpio34",
> >>>> -						"gpio35", "gpio42" };
> >>>> -static const char *const phy3_led0_groups[] = { "gpio33", "gpio34",
> >>>> -						"gpio35", "gpio42" };
> >>>> -static const char *const phy4_led0_groups[] = { "gpio33", "gpio34",
> >>>> -						"gpio35", "gpio42" };
> >>>> -static const char *const phy1_led1_groups[] = { "gpio43", "gpio44",
> >>>> -						"gpio45", "gpio46" };
> >>>> -static const char *const phy2_led1_groups[] = { "gpio43", "gpio44",
> >>>> -						"gpio45", "gpio46" };
> >>>> -static const char *const phy3_led1_groups[] = { "gpio43", "gpio44",
> >>>> -						"gpio45", "gpio46" };
> >>>> -static const char *const phy4_led1_groups[] = { "gpio43", "gpio44",
> >>>> -						"gpio45", "gpio46" };
> >>>> -static const char *const an7583_phy1_led0_groups[] = { "gpio1", "gpio2",
> >>>> -							"gpio3", "gpio4" };
> >>>> -static const char *const an7583_phy2_led0_groups[] = { "gpio1", "gpio2",
> >>>> -							"gpio3", "gpio4" };
> >>>> -static const char *const an7583_phy3_led0_groups[] = { "gpio1", "gpio2",
> >>>> -							"gpio3", "gpio4" };
> >>>> -static const char *const an7583_phy4_led0_groups[] = { "gpio1", "gpio2",
> >>>> -							"gpio3", "gpio4" };
> >>>> -static const char *const an7583_phy1_led1_groups[] = { "gpio8", "gpio9",
> >>>> -							"gpio10", "gpio11" };
> >>>> -static const char *const an7583_phy2_led1_groups[] = { "gpio8", "gpio9",
> >>>> -							"gpio10", "gpio11" };
> >>>> -static const char *const an7583_phy3_led1_groups[] = { "gpio8", "gpio9",
> >>>> -							"gpio10", "gpio11" };
> >>>> -static const char *const an7583_phy4_led1_groups[] = { "gpio8", "gpio9",
> >>>> -							"gpio10", "gpio11" };
> >>>> -
> >>>> -static const struct airoha_pinctrl_func_group pon_func_group[] = {
> >>>> -	{
> >>>> -		.name = "pon",
> >>>> -		.regmap[0] = {
> >>>> -			AIROHA_FUNC_MUX,
> >>>> -			REG_GPIO_PON_MODE,
> >>>> -			GPIO_PON_MODE_MASK,
> >>>> -			GPIO_PON_MODE_MASK
> >>>> -		},
> >>>> -		.regmap_size = 1,
> >>>> -	},
> >>>> -};
> >>>> -
> >>>> -static const struct airoha_pinctrl_func_group tod_1pps_func_group[] = {
> >>>> -	{
> >>>> -		.name = "pon_tod_1pps",
> >>>> -		.regmap[0] = {
> >>>> -			AIROHA_FUNC_MUX,
> >>>> -			REG_GPIO_2ND_I2C_MODE,
> >>>> -			PON_TOD_1PPS_MODE_MASK,
> >>>> -			PON_TOD_1PPS_MODE_MASK
> >>>> -		},
> >>>> -		.regmap_size = 1,
> >>>> -	}, {
> >>>> -		.name = "gsw_tod_1pps",
> >>>> -		.regmap[0] = {
> >>>> -			AIROHA_FUNC_MUX,
> >>>> -			REG_GPIO_2ND_I2C_MODE,
> >>>> -			GSW_TOD_1PPS_MODE_MASK,
> >>>> -			GSW_TOD_1PPS_MODE_MASK
> >>>> -		},
> >>>> -		.regmap_size = 1,
> >>>> -	},
> >>>> -};
> >>>> -
> >>>> -static const struct airoha_pinctrl_func_group sipo_func_group[] = {
> >>>> -	{
> >>>> -		.name = "sipo",
> >>>> -		.regmap[0] = {
> >>>> -			AIROHA_FUNC_MUX,
> >>>> -			REG_GPIO_PON_MODE,
> >>>> -			GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK,
> >>>> -			GPIO_SIPO_MODE_MASK
> >>>> -		},
> >>>> -		.regmap_size = 1,
> >>>> -	}, {
> >>>> -		.name = "sipo_rclk",
> >>>> -		.regmap[0] = {
> >>>> -			AIROHA_FUNC_MUX,
> >>>> -			REG_GPIO_PON_MODE,
> >>>> -			GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK,
> >>>> -			GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK
> >>>> -		},
> >>>> -		.regmap_size = 1,
> >>>> -	},
> >>>> -};
> >>>> -
> >>>> -static const struct airoha_pinctrl_func_group mdio_func_group[] = {
> >>>> -	{
> >>>> -		.name = "mdio",
> >>>> -		.regmap[0] = {
> >>>> -			AIROHA_FUNC_MUX,
> >>>> -			REG_GPIO_2ND_I2C_MODE,
> >>>> -			GPIO_MDC_IO_MASTER_MODE_MASK,
> >>>> -			GPIO_MDC_IO_MASTER_MODE_MASK
> >>>> -		},
> >>>> -		.regmap[1] = {
> >>>> -			AIROHA_FUNC_MUX,
> >>>> -			REG_FORCE_GPIO_EN,
> >>>> -			FORCE_GPIO_EN(1) | FORCE_GPIO_EN(2),
> >>>> -			FORCE_GPIO_EN(1) | FORCE_GPIO_EN(2)
> >>>> -		},
> >>>> -		.regmap_size = 2,
> >>>> -	},
> >>>> -};
> >>>> -
> >>>> -static const struct airoha_pinctrl_func_group an7583_mdio_func_group[] = {
> >>>> -	{
> >>>> -		.name = "mdio",
> >>>> -		.regmap[0] = {
> >>>> -			AIROHA_FUNC_MUX,
> >>>> -			REG_GPIO_PON_MODE,
> >>>> -			GPIO_SGMII_MDIO_MODE_MASK,
> >>>> -			GPIO_SGMII_MDIO_MODE_MASK
> >>>> -		},
> >>>> -		.regmap[1] = {
> >>>> -			AIROHA_FUNC_MUX,
> >>>> -			REG_GPIO_SPI_CS1_MODE,
> >>>> -			GPIO_MDC_IO_MASTER_MODE_MASK,
> >>>> -			GPIO_MDC_IO_MASTER_MODE_MASK
> >>>> -		},
> >>>> -		.regmap_size = 2,
> >>>> -	},
> >>>> -};
> >>>> -
> >>>> -static const struct airoha_pinctrl_func_group uart_func_group[] = {
> >>>> -	{
> >>>> -		.name = "uart2",
> >>>> -		.regmap[0] = {
> >>>> -			AIROHA_FUNC_MUX,
> >>>> -			REG_GPIO_PON_MODE,
> >>>> -			GPIO_UART2_MODE_MASK,
> >>>> -			GPIO_UART2_MODE_MASK
> >>>> -		},
> >>>> -		.regmap_size = 1,
> >>>> -	}, {
> >>>> -		.name = "uart2_cts_rts",
> >>>> -		.regmap[0] = {
> >>>> -			AIROHA_FUNC_MUX,
> >>>> -			REG_GPIO_PON_MODE,
> >>>> -			GPIO_UART2_MODE_MASK | GPIO_UART2_CTS_RTS_MODE_MASK,
> >>>> -			GPIO_UART2_MODE_MASK | GPIO_UART2_CTS_RTS_MODE_MASK
> >>>> -		},
> >>>> -		.regmap_size = 1,
> >>>> -	}, {
> >>>> -		.name = "hsuart",
> >>>> -		.regmap[0] = {
> >>>> -			AIROHA_FUNC_MUX,
> >>>> -			REG_GPIO_PON_MODE,
> >>>> -			GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK,
> >>>> -			GPIO_HSUART_MODE_MASK
> >>>> -		},
> >>>> -		.regmap_size = 1,
> >>>> -	},
> >>>> -	{
> >>>> -		.name = "hsuart_cts_rts",
> >>>> -		.regmap[0] = {
> >>>> -			AIROHA_FUNC_MUX,
> >>>> -			REG_GPIO_PON_MODE,
> >>>> -			GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK,
> >>>> -			GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK
> >>>> -		},
> >>>> -		.regmap_size = 1,
> >>>> -	}, {
> >>>> -		.name = "uart4",
> >>>> -		.regmap[0] = {
> >>>> -			AIROHA_FUNC_MUX,
> >>>> -			REG_GPIO_PON_MODE,
> >>>> -			GPIO_UART4_MODE_MASK,
> >>>> -			GPIO_UART4_MODE_MASK
> >>>> -		},
> >>>> -		.regmap_size = 1,
> >>>> -	}, {
> >>>> -		.name = "uart5",
> >>>> -		.regmap[0] = {
> >>>> -			AIROHA_FUNC_MUX,
> >>>> -			REG_GPIO_PON_MODE,
> >>>> -			GPIO_UART5_MODE_MASK,
> >>>> -			GPIO_UART5_MODE_MASK
> >>>> -		},
> >>>> -		.regmap_size = 1,
> >>>> -	},
> >>>> -};
> >>>> -
> >>>> -static const struct airoha_pinctrl_func_group i2c_func_group[] = {
> >>>> -	{
> >>>> -		.name = "i2c1",
> >>>> -		.regmap[0] = {
> >>>> -			AIROHA_FUNC_MUX,
> >>>> -			REG_GPIO_2ND_I2C_MODE,
> >>>> -			GPIO_2ND_I2C_MODE_MASK,
> >>>> -			GPIO_2ND_I2C_MODE_MASK
> >>>> -		},
> >>>> -		.regmap_size = 1,
> >>>> -	},
> >>>> -};
> >>>> -
> >>>> -static const struct airoha_pinctrl_func_group jtag_func_group[] = {
> >>>> -	{
> >>>> -		.name = "jtag_udi",
> >>>> -		.regmap[0] = {
> >>>> -			AIROHA_FUNC_MUX,
> >>>> -			REG_NPU_UART_EN,
> >>>> -			JTAG_UDI_EN_MASK,
> >>>> -			JTAG_UDI_EN_MASK
> >>>> -		},
> >>>> -		.regmap_size = 1,
> >>>> -	}, {
> >>>> -		.name = "jtag_dfd",
> >>>> -		.regmap[0] = {
> >>>> -			AIROHA_FUNC_MUX,
> >>>> -			REG_NPU_UART_EN,
> >>>> -			JTAG_DFD_EN_MASK,
> >>>> -			JTAG_DFD_EN_MASK
> >>>> -		},
> >>>> -		.regmap_size = 1,
> >>>> -	},
> >>>> -};
> >>>> -
> >>>> -static const struct airoha_pinctrl_func_group pcm_func_group[] = {
> >>>> -	{
> >>>> -		.name = "pcm1",
> >>>> -		.regmap[0] = {
> >>>> -			AIROHA_FUNC_MUX,
> >>>> -			REG_GPIO_SPI_CS1_MODE,
> >>>> -			GPIO_PCM1_MODE_MASK,
> >>>> -			GPIO_PCM1_MODE_MASK
> >>>> -		},
> >>>> -		.regmap_size = 1,
> >>>> -	}, {
> >>>> -		.name = "pcm2",
> >>>> -		.regmap[0] = {
> >>>> -			AIROHA_FUNC_MUX,
> >>>> -			REG_GPIO_SPI_CS1_MODE,
> >>>> -			GPIO_PCM2_MODE_MASK,
> >>>> -			GPIO_PCM2_MODE_MASK
> >>>> -		},
> >>>> -		.regmap_size = 1,
> >>>> -	},
> >>>> -};
> >>>> -
> >>>> -static const struct airoha_pinctrl_func_group spi_func_group[] = {
> >>>> -	{
> >>>> -		.name = "spi_quad",
> >>>> -		.regmap[0] = {
> >>>> -			AIROHA_FUNC_MUX,
> >>>> -			REG_GPIO_SPI_CS1_MODE,
> >>>> -			GPIO_SPI_QUAD_MODE_MASK,
> >>>> -			GPIO_SPI_QUAD_MODE_MASK
> >>>> -		},
> >>>> -		.regmap_size = 1,
> >>>> -	}, {
> >>>> -		.name = "spi_cs1",
> >>>> -		.regmap[0] = {
> >>>> -			AIROHA_FUNC_MUX,
> >>>> -			REG_GPIO_SPI_CS1_MODE,
> >>>> -			GPIO_SPI_CS1_MODE_MASK,
> >>>> -			GPIO_SPI_CS1_MODE_MASK
> >>>> -		},
> >>>> -		.regmap_size = 1,
> >>>> -	}, {
> >>>> -		.name = "spi_cs2",
> >>>> -		.regmap[0] = {
> >>>> -			AIROHA_FUNC_MUX,
> >>>> -			REG_GPIO_SPI_CS1_MODE,
> >>>> -			GPIO_SPI_CS2_MODE_MASK,
> >>>> -			GPIO_SPI_CS2_MODE_MASK
> >>>> -		},
> >>>> -		.regmap_size = 1,
> >>>> -	}, {
> >>>> -		.name = "spi_cs3",
> >>>> -		.regmap[0] = {
> >>>> -			AIROHA_FUNC_MUX,
> >>>> -			REG_GPIO_SPI_CS1_MODE,
> >>>> -			GPIO_SPI_CS3_MODE_MASK,
> >>>> -			GPIO_SPI_CS3_MODE_MASK
> >>>> -		},
> >>>> -		.regmap_size = 1,
> >>>> -	}, {
> >>>> -		.name = "spi_cs4",
> >>>> -		.regmap[0] = {
> >>>> -			AIROHA_FUNC_MUX,
> >>>> -			REG_GPIO_SPI_CS1_MODE,
> >>>> -			GPIO_SPI_CS4_MODE_MASK,
> >>>> -			GPIO_SPI_CS4_MODE_MASK
> >>>> -		},
> >>>> -		.regmap_size = 1,
> >>>> -	},
> >>>> -};
> >>>> -
> >>>> -static const struct airoha_pinctrl_func_group pcm_spi_func_group[] = {
> >>>> -	{
> >>>> -		.name = "pcm_spi",
> >>>> -		.regmap[0] = {
> >>>> -			AIROHA_FUNC_MUX,
> >>>> -			REG_GPIO_SPI_CS1_MODE,
> >>>> -			GPIO_PCM_SPI_MODE_MASK,
> >>>> -			GPIO_PCM_SPI_MODE_MASK
> >>>> -		},
> >>>> -		.regmap_size = 1,
> >>>> -	}, {
> >>>> -		.name = "pcm_spi_int",
> >>>> -		.regmap[0] = {
> >>>> -			AIROHA_FUNC_MUX,
> >>>> -			REG_GPIO_SPI_CS1_MODE,
> >>>> -			GPIO_PCM_INT_MODE_MASK,
> >>>> -			GPIO_PCM_INT_MODE_MASK
> >>>> -		},
> >>>> -		.regmap_size = 1,
> >>>> -	}, {
> >>>> -		.name = "pcm_spi_rst",
> >>>> -		.regmap[0] = {
> >>>> -			AIROHA_FUNC_MUX,
> >>>> -			REG_GPIO_SPI_CS1_MODE,
> >>>> -			GPIO_PCM_RESET_MODE_MASK,
> >>>> -			GPIO_PCM_RESET_MODE_MASK
> >>>> -		},
> >>>> -		.regmap_size = 1,
> >>>> -	}, {
> >>>> -		.name = "pcm_spi_cs1",
> >>>> -		.regmap[0] = {
> >>>> -			AIROHA_FUNC_MUX,
> >>>> -			REG_GPIO_SPI_CS1_MODE,
> >>>> -			GPIO_PCM_SPI_CS1_MODE_MASK,
> >>>> -			GPIO_PCM_SPI_CS1_MODE_MASK
> >>>> -		},
> >>>> -		.regmap_size = 1,
> >>>> -	}, {
> >>>> -		.name = "pcm_spi_cs2_p128",
> >>>> -		.regmap[0] = {
> >>>> -			AIROHA_FUNC_MUX,
> >>>> -			REG_GPIO_SPI_CS1_MODE,
> >>>> -			GPIO_PCM_SPI_CS2_MODE_P128_MASK,
> >>>> -			GPIO_PCM_SPI_CS2_MODE_P128_MASK
> >>>> -		},
> >>>> -		.regmap_size = 1,
> >>>> -	}, {
> >>>> -		.name = "pcm_spi_cs2_p156",
> >>>> -		.regmap[0] = {
> >>>> -			AIROHA_FUNC_MUX,
> >>>> -			REG_GPIO_SPI_CS1_MODE,
> >>>> -			GPIO_PCM_SPI_CS2_MODE_P156_MASK,
> >>>> -			GPIO_PCM_SPI_CS2_MODE_P156_MASK
> >>>> -		},
> >>>> -		.regmap_size = 1,
> >>>> -	}, {
> >>>> -		.name = "pcm_spi_cs3",
> >>>> -		.regmap[0] = {
> >>>> -			AIROHA_FUNC_MUX,
> >>>> -			REG_GPIO_SPI_CS1_MODE,
> >>>> -			GPIO_PCM_SPI_CS3_MODE_MASK,
> >>>> -			GPIO_PCM_SPI_CS3_MODE_MASK
> >>>> -		},
> >>>> -		.regmap_size = 1,
> >>>> -	}, {
> >>>> -		.name = "pcm_spi_cs4",
> >>>> -		.regmap[0] = {
> >>>> -			AIROHA_FUNC_MUX,
> >>>> -			REG_GPIO_SPI_CS1_MODE,
> >>>> -			GPIO_PCM_SPI_CS4_MODE_MASK,
> >>>> -			GPIO_PCM_SPI_CS4_MODE_MASK
> >>>> -		},
> >>>> -		.regmap_size = 1,
> >>>> -	},
> >>>> -};
> >>>> -
> >>>> -static const struct airoha_pinctrl_func_group an7583_pcm_spi_func_group[] = {
> >>>> -	{
> >>>> -		.name = "pcm_spi",
> >>>> -		.regmap[0] = {
> >>>> -			AIROHA_FUNC_MUX,
> >>>> -			REG_GPIO_SPI_CS1_MODE,
> >>>> -			GPIO_PCM_SPI_MODE_MASK,
> >>>> -			GPIO_PCM_SPI_MODE_MASK
> >>>> -		},
> >>>> -		.regmap_size = 1,
> >>>> -	}, {
> >>>> -		.name = "pcm_spi_int",
> >>>> -		.regmap[0] = {
> >>>> -			AIROHA_FUNC_MUX,
> >>>> -			REG_GPIO_SPI_CS1_MODE,
> >>>> -			GPIO_PCM_INT_MODE_MASK,
> >>>> -			GPIO_PCM_INT_MODE_MASK
> >>>> -		},
> >>>> -		.regmap_size = 1,
> >>>> -	}, {
> >>>> -		.name = "pcm_spi_rst",
> >>>> -		.regmap[0] = {
> >>>> -			AIROHA_FUNC_MUX,
> >>>> -			REG_GPIO_SPI_CS1_MODE,
> >>>> -			GPIO_PCM_RESET_MODE_MASK,
> >>>> -			GPIO_PCM_RESET_MODE_MASK
> >>>> -		},
> >>>> -		.regmap_size = 1,
> >>>> -	}, {
> >>>> -		.name = "pcm_spi_cs1",
> >>>> -		.regmap[0] = {
> >>>> -			AIROHA_FUNC_MUX,
> >>>> -			REG_GPIO_SPI_CS1_MODE,
> >>>> -			GPIO_PCM_SPI_CS1_MODE_MASK,
> >>>> -			GPIO_PCM_SPI_CS1_MODE_MASK
> >>>> -		},
> >>>> -		.regmap_size = 1,
> >>>> -	}, {
> >>>> -		.name = "pcm_spi_cs2",
> >>>> -		.regmap[0] = {
> >>>> -			AIROHA_FUNC_MUX,
> >>>> -			REG_GPIO_SPI_CS1_MODE,
> >>>> -			AN7583_GPIO_PCM_SPI_CS2_MODE_MASK,
> >>>> -			AN7583_GPIO_PCM_SPI_CS2_MODE_MASK
> >>>> -		},
> >>>> -		.regmap_size = 1,
> >>>> -	}, {
> >>>> -		.name = "pcm_spi_cs3",
> >>>> -		.regmap[0] = {
> >>>> -			AIROHA_FUNC_MUX,
> >>>> -			REG_GPIO_SPI_CS1_MODE,
> >>>> -			GPIO_PCM_SPI_CS3_MODE_MASK,
> >>>> -			GPIO_PCM_SPI_CS3_MODE_MASK
> >>>> -		},
> >>>> -		.regmap_size = 1,
> >>>> -	}, {
> >>>> -		.name = "pcm_spi_cs4",
> >>>> -		.regmap[0] = {
> >>>> -			AIROHA_FUNC_MUX,
> >>>> -			REG_GPIO_SPI_CS1_MODE,
> >>>> -			GPIO_PCM_SPI_CS4_MODE_MASK,
> >>>> -			GPIO_PCM_SPI_CS4_MODE_MASK
> >>>> -		},
> >>>> -		.regmap_size = 1,
> >>>> -	},
> >>>> -};
> >>>> -
> >>>> -static const struct airoha_pinctrl_func_group i2s_func_group[] = {
> >>>> -	{
> >>>> -		.name = "i2s",
> >>>> -		.regmap[0] = {
> >>>> -			AIROHA_FUNC_MUX,
> >>>> -			REG_GPIO_2ND_I2C_MODE,
> >>>> -			GPIO_I2S_MODE_MASK,
> >>>> -			GPIO_I2S_MODE_MASK
> >>>> -		},
> >>>> -		.regmap_size = 1,
> >>>> -	},
> >>>> -};
> >>>> -
> >>>> -static const struct airoha_pinctrl_func_group emmc_func_group[] = {
> >>>> -	{
> >>>> -		.name = "emmc",
> >>>> -		.regmap[0] = {
> >>>> -			AIROHA_FUNC_MUX,
> >>>> -			REG_GPIO_PON_MODE,
> >>>> -			GPIO_EMMC_MODE_MASK,
> >>>> -			GPIO_EMMC_MODE_MASK
> >>>> -		},
> >>>> -		.regmap_size = 1,
> >>>> -	},
> >>>> -};
> >>>> -
> >>>> -static const struct airoha_pinctrl_func_group pnand_func_group[] = {
> >>>> -	{
> >>>> -		.name = "pnand",
> >>>> -		.regmap[0] = {
> >>>> -			AIROHA_FUNC_MUX,
> >>>> -			REG_GPIO_PON_MODE,
> >>>> -			GPIO_PARALLEL_NAND_MODE_MASK,
> >>>> -			GPIO_PARALLEL_NAND_MODE_MASK
> >>>> -		},
> >>>> -		.regmap_size = 1,
> >>>> -	},
> >>>> -};
> >>>> -
> >>>> -static const struct airoha_pinctrl_func_group gpio_func_group[] = {
> >>>> -	AIROHA_PINCTRL_GPIO_EXT("gpio47", GPIO47_FLASH_MODE_CFG,
> >>>> -				GPIO_PCIE_RESET0_MASK),
> >>>> -	AIROHA_PINCTRL_GPIO_EXT("gpio48", GPIO48_FLASH_MODE_CFG,
> >>>> -				GPIO_PCIE_RESET1_MASK),
> >>>> -	AIROHA_PINCTRL_GPIO_EXT("gpio49", GPIO49_FLASH_MODE_CFG,
> >>>> -				GPIO_PCIE_RESET2_MASK),
> >>>> -};
> >>>> -
> >>>> -static const struct airoha_pinctrl_func_group pcie_reset_func_group[] = {
> >>>> -	{
> >>>> -		.name = "pcie_reset0",
> >>>> -		.regmap[0] = {
> >>>> -			AIROHA_FUNC_MUX,
> >>>> -			REG_GPIO_PON_MODE,
> >>>> -			GPIO_PCIE_RESET0_MASK,
> >>>> -			0
> >>>> -		},
> >>>> -		.regmap_size = 1,
> >>>> -	}, {
> >>>> -		.name = "pcie_reset1",
> >>>> -		.regmap[0] = {
> >>>> -			AIROHA_FUNC_MUX,
> >>>> -			REG_GPIO_PON_MODE,
> >>>> -			GPIO_PCIE_RESET1_MASK,
> >>>> -			0
> >>>> -		},
> >>>> -		.regmap_size = 1,
> >>>> -	}, {
> >>>> -		.name = "pcie_reset2",
> >>>> -		.regmap[0] = {
> >>>> -			AIROHA_FUNC_MUX,
> >>>> -			REG_GPIO_PON_MODE,
> >>>> -			GPIO_PCIE_RESET2_MASK,
> >>>> -			0
> >>>> -		},
> >>>> -		.regmap_size = 1,
> >>>> -	},
> >>>> -};
> >>>> -
> >>>> -static const struct airoha_pinctrl_func_group an7583_gpio_func_group[] = {
> >>>> -	AIROHA_PINCTRL_GPIO_EXT("gpio39", GPIO39_FLASH_MODE_CFG,
> >>>> -				AN7583_I2C0_SCL_GPIO_MODE_MASK),
> >>>> -	AIROHA_PINCTRL_GPIO_EXT("gpio40", GPIO40_FLASH_MODE_CFG,
> >>>> -				AN7583_I2C0_SDA_GPIO_MODE_MASK),
> >>>> -	AIROHA_PINCTRL_GPIO_EXT("gpio41", GPIO41_FLASH_MODE_CFG,
> >>>> -				AN7583_I2C1_SCL_GPIO_MODE_MASK),
> >>>> -	AIROHA_PINCTRL_GPIO_EXT("gpio42", GPIO42_FLASH_MODE_CFG,
> >>>> -				AN7583_I2C1_SDA_GPIO_MODE_MASK),
> >>>> -	AIROHA_PINCTRL_GPIO_EXT("gpio43", GPIO43_FLASH_MODE_CFG,
> >>>> -				AN7583_SPI_CLK_GPIO_MODE_MASK),
> >>>> -	AIROHA_PINCTRL_GPIO_EXT("gpio44", GPIO44_FLASH_MODE_CFG,
> >>>> -				AN7583_SPI_CS_GPIO_MODE_MASK),
> >>>> -	AIROHA_PINCTRL_GPIO_EXT("gpio45", GPIO45_FLASH_MODE_CFG,
> >>>> -				AN7583_SPI_MOSI_GPIO_MODE_MASK),
> >>>> -	AIROHA_PINCTRL_GPIO_EXT("gpio46", GPIO46_FLASH_MODE_CFG,
> >>>> -				AN7583_SPI_MISO_GPIO_MODE_MASK),
> >>>> -	AIROHA_PINCTRL_GPIO_EXT("gpio47", GPIO47_FLASH_MODE_CFG,
> >>>> -				AN7583_UART_TXD_GPIO_MODE_MASK),
> >>>> -	AIROHA_PINCTRL_GPIO_EXT("gpio48", GPIO48_FLASH_MODE_CFG,
> >>>> -				AN7583_UART_RXD_GPIO_MODE_MASK),
> >>>> -	AIROHA_PINCTRL_GPIO_EXT("gpio49", GPIO49_FLASH_MODE_CFG,
> >>>> -				GPIO_PCIE_RESET0_MASK),
> >>>> -	AIROHA_PINCTRL_GPIO_EXT("gpio50", GPIO50_FLASH_MODE_CFG,
> >>>> -				GPIO_PCIE_RESET1_MASK),
> >>>> -	AIROHA_PINCTRL_GPIO_EXT("gpio51", GPIO51_FLASH_MODE_CFG,
> >>>> -				AN7583_MDC_0_GPIO_MODE_MASK),
> >>>> -	AIROHA_PINCTRL_GPIO("gpio52", AN7583_MDIO_0_GPIO_MODE_MASK),
> >>>> -};
> >>>> -
> >>>> -static const struct airoha_pinctrl_func_group an7583_pcie_reset_func_group[] = {
> >>>> -	{
> >>>> -		.name = "pcie_reset0",
> >>>> -		.regmap[0] = {
> >>>> -			AIROHA_FUNC_MUX,
> >>>> -			REG_GPIO_PON_MODE,
> >>>> -			GPIO_PCIE_RESET0_MASK,
> >>>> -			0
> >>>> -		},
> >>>> -		.regmap_size = 1,
> >>>> -	}, {
> >>>> -		.name = "pcie_reset1",
> >>>> -		.regmap[0] = {
> >>>> -			AIROHA_FUNC_MUX,
> >>>> -			REG_GPIO_PON_MODE,
> >>>> -			GPIO_PCIE_RESET1_MASK,
> >>>> -			0
> >>>> -		},
> >>>> -		.regmap_size = 1,
> >>>> -	},
> >>>> -};
> >>>> -
> >>>> -static const struct airoha_pinctrl_func_group pwm_func_group[] = {
> >>>> -	AIROHA_PINCTRL_PWM("gpio0", GPIO0_FLASH_MODE_CFG),
> >>>> -	AIROHA_PINCTRL_PWM("gpio1", GPIO1_FLASH_MODE_CFG),
> >>>> -	AIROHA_PINCTRL_PWM("gpio2", GPIO2_FLASH_MODE_CFG),
> >>>> -	AIROHA_PINCTRL_PWM("gpio3", GPIO3_FLASH_MODE_CFG),
> >>>> -	AIROHA_PINCTRL_PWM("gpio4", GPIO4_FLASH_MODE_CFG),
> >>>> -	AIROHA_PINCTRL_PWM("gpio5", GPIO5_FLASH_MODE_CFG),
> >>>> -	AIROHA_PINCTRL_PWM("gpio6", GPIO6_FLASH_MODE_CFG),
> >>>> -	AIROHA_PINCTRL_PWM("gpio7", GPIO7_FLASH_MODE_CFG),
> >>>> -	AIROHA_PINCTRL_PWM("gpio8", GPIO8_FLASH_MODE_CFG),
> >>>> -	AIROHA_PINCTRL_PWM("gpio9", GPIO9_FLASH_MODE_CFG),
> >>>> -	AIROHA_PINCTRL_PWM("gpio10", GPIO10_FLASH_MODE_CFG),
> >>>> -	AIROHA_PINCTRL_PWM("gpio11", GPIO11_FLASH_MODE_CFG),
> >>>> -	AIROHA_PINCTRL_PWM("gpio12", GPIO12_FLASH_MODE_CFG),
> >>>> -	AIROHA_PINCTRL_PWM("gpio13", GPIO13_FLASH_MODE_CFG),
> >>>> -	AIROHA_PINCTRL_PWM("gpio14", GPIO14_FLASH_MODE_CFG),
> >>>> -	AIROHA_PINCTRL_PWM("gpio15", GPIO15_FLASH_MODE_CFG),
> >>>> -	AIROHA_PINCTRL_PWM_EXT("gpio16", GPIO16_FLASH_MODE_CFG),
> >>>> -	AIROHA_PINCTRL_PWM_EXT("gpio17", GPIO17_FLASH_MODE_CFG),
> >>>> -	AIROHA_PINCTRL_PWM_EXT("gpio18", GPIO18_FLASH_MODE_CFG),
> >>>> -	AIROHA_PINCTRL_PWM_EXT("gpio19", GPIO19_FLASH_MODE_CFG),
> >>>> -	AIROHA_PINCTRL_PWM_EXT("gpio20", GPIO20_FLASH_MODE_CFG),
> >>>> -	AIROHA_PINCTRL_PWM_EXT("gpio21", GPIO21_FLASH_MODE_CFG),
> >>>> -	AIROHA_PINCTRL_PWM_EXT("gpio22", GPIO22_FLASH_MODE_CFG),
> >>>> -	AIROHA_PINCTRL_PWM_EXT("gpio23", GPIO23_FLASH_MODE_CFG),
> >>>> -	AIROHA_PINCTRL_PWM_EXT("gpio24", GPIO24_FLASH_MODE_CFG),
> >>>> -	AIROHA_PINCTRL_PWM_EXT("gpio25", GPIO25_FLASH_MODE_CFG),
> >>>> -	AIROHA_PINCTRL_PWM_EXT("gpio26", GPIO26_FLASH_MODE_CFG),
> >>>> -	AIROHA_PINCTRL_PWM_EXT("gpio27", GPIO27_FLASH_MODE_CFG),
> >>>> -	AIROHA_PINCTRL_PWM_EXT("gpio28", GPIO28_FLASH_MODE_CFG),
> >>>> -	AIROHA_PINCTRL_PWM_EXT("gpio29", GPIO29_FLASH_MODE_CFG),
> >>>> -	AIROHA_PINCTRL_PWM_EXT("gpio30", GPIO30_FLASH_MODE_CFG),
> >>>> -	AIROHA_PINCTRL_PWM_EXT("gpio31", GPIO31_FLASH_MODE_CFG),
> >>>> -	AIROHA_PINCTRL_PWM_EXT("gpio36", GPIO36_FLASH_MODE_CFG),
> >>>> -	AIROHA_PINCTRL_PWM_EXT("gpio37", GPIO37_FLASH_MODE_CFG),
> >>>> -	AIROHA_PINCTRL_PWM_EXT("gpio38", GPIO38_FLASH_MODE_CFG),
> >>>> -	AIROHA_PINCTRL_PWM_EXT("gpio39", GPIO39_FLASH_MODE_CFG),
> >>>> -	AIROHA_PINCTRL_PWM_EXT("gpio40", GPIO40_FLASH_MODE_CFG),
> >>>> -	AIROHA_PINCTRL_PWM_EXT("gpio41", GPIO41_FLASH_MODE_CFG),
> >>>> -	AIROHA_PINCTRL_PWM_EXT("gpio42", GPIO42_FLASH_MODE_CFG),
> >>>> -	AIROHA_PINCTRL_PWM_EXT("gpio43", GPIO43_FLASH_MODE_CFG),
> >>>> -	AIROHA_PINCTRL_PWM_EXT("gpio44", GPIO44_FLASH_MODE_CFG),
> >>>> -	AIROHA_PINCTRL_PWM_EXT("gpio45", GPIO45_FLASH_MODE_CFG),
> >>>> -	AIROHA_PINCTRL_PWM_EXT("gpio46", GPIO46_FLASH_MODE_CFG),
> >>>> -	AIROHA_PINCTRL_PWM_EXT_SEC("gpio47", GPIO47_FLASH_MODE_CFG,
> >>>> -				   GPIO_PCIE_RESET0_MASK),
> >>>> -	AIROHA_PINCTRL_PWM_EXT_SEC("gpio48", GPIO48_FLASH_MODE_CFG,
> >>>> -				   GPIO_PCIE_RESET1_MASK),
> >>>> -	AIROHA_PINCTRL_PWM_EXT_SEC("gpio49", GPIO49_FLASH_MODE_CFG,
> >>>> -				   GPIO_PCIE_RESET2_MASK),
> >>>> -};
> >>>> -
> >>>> -static const struct airoha_pinctrl_func_group an7583_pwm_func_group[] = {
> >>>> -	AIROHA_PINCTRL_PWM("gpio0", GPIO0_FLASH_MODE_CFG),
> >>>> -	AIROHA_PINCTRL_PWM("gpio1", GPIO1_FLASH_MODE_CFG),
> >>>> -	AIROHA_PINCTRL_PWM("gpio2", GPIO2_FLASH_MODE_CFG),
> >>>> -	AIROHA_PINCTRL_PWM("gpio3", GPIO3_FLASH_MODE_CFG),
> >>>> -	AIROHA_PINCTRL_PWM("gpio4", GPIO4_FLASH_MODE_CFG),
> >>>> -	AIROHA_PINCTRL_PWM("gpio5", GPIO5_FLASH_MODE_CFG),
> >>>> -	AIROHA_PINCTRL_PWM("gpio6", GPIO6_FLASH_MODE_CFG),
> >>>> -	AIROHA_PINCTRL_PWM("gpio7", GPIO7_FLASH_MODE_CFG),
> >>>> -	AIROHA_PINCTRL_PWM("gpio8", GPIO8_FLASH_MODE_CFG),
> >>>> -	AIROHA_PINCTRL_PWM("gpio9", GPIO9_FLASH_MODE_CFG),
> >>>> -	AIROHA_PINCTRL_PWM("gpio10", GPIO10_FLASH_MODE_CFG),
> >>>> -	AIROHA_PINCTRL_PWM("gpio11", GPIO11_FLASH_MODE_CFG),
> >>>> -	AIROHA_PINCTRL_PWM("gpio12", GPIO12_FLASH_MODE_CFG),
> >>>> -	AIROHA_PINCTRL_PWM("gpio13", GPIO13_FLASH_MODE_CFG),
> >>>> -	AIROHA_PINCTRL_PWM("gpio14", GPIO14_FLASH_MODE_CFG),
> >>>> -	AIROHA_PINCTRL_PWM("gpio15", GPIO15_FLASH_MODE_CFG),
> >>>> -	AIROHA_PINCTRL_PWM_EXT("gpio16", GPIO16_FLASH_MODE_CFG),
> >>>> -	AIROHA_PINCTRL_PWM_EXT("gpio17", GPIO17_FLASH_MODE_CFG),
> >>>> -	AIROHA_PINCTRL_PWM_EXT("gpio18", GPIO18_FLASH_MODE_CFG),
> >>>> -	AIROHA_PINCTRL_PWM_EXT("gpio19", GPIO19_FLASH_MODE_CFG),
> >>>> -	AIROHA_PINCTRL_PWM_EXT("gpio20", GPIO20_FLASH_MODE_CFG),
> >>>> -	AIROHA_PINCTRL_PWM_EXT("gpio21", GPIO21_FLASH_MODE_CFG),
> >>>> -	AIROHA_PINCTRL_PWM_EXT("gpio22", GPIO22_FLASH_MODE_CFG),
> >>>> -	AIROHA_PINCTRL_PWM_EXT("gpio23", GPIO23_FLASH_MODE_CFG),
> >>>> -	AIROHA_PINCTRL_PWM_EXT("gpio24", GPIO24_FLASH_MODE_CFG),
> >>>> -	AIROHA_PINCTRL_PWM_EXT("gpio25", GPIO25_FLASH_MODE_CFG),
> >>>> -	AIROHA_PINCTRL_PWM_EXT("gpio26", GPIO26_FLASH_MODE_CFG),
> >>>> -	AIROHA_PINCTRL_PWM_EXT("gpio27", GPIO27_FLASH_MODE_CFG),
> >>>> -	AIROHA_PINCTRL_PWM_EXT("gpio28", GPIO28_FLASH_MODE_CFG),
> >>>> -	AIROHA_PINCTRL_PWM_EXT("gpio29", GPIO29_FLASH_MODE_CFG),
> >>>> -	AIROHA_PINCTRL_PWM_EXT("gpio30", GPIO30_FLASH_MODE_CFG),
> >>>> -	AIROHA_PINCTRL_PWM_EXT("gpio31", GPIO31_FLASH_MODE_CFG),
> >>>> -	AIROHA_PINCTRL_PWM_EXT("gpio36", GPIO36_FLASH_MODE_CFG),
> >>>> -	AIROHA_PINCTRL_PWM_EXT("gpio37", GPIO37_FLASH_MODE_CFG),
> >>>> -	AIROHA_PINCTRL_PWM_EXT("gpio38", GPIO38_FLASH_MODE_CFG),
> >>>> -	AIROHA_PINCTRL_PWM_EXT_SEC("gpio39", GPIO39_FLASH_MODE_CFG,
> >>>> -				   AN7583_I2C0_SCL_GPIO_MODE_MASK),
> >>>> -	AIROHA_PINCTRL_PWM_EXT_SEC("gpio40", GPIO40_FLASH_MODE_CFG,
> >>>> -				   AN7583_I2C0_SDA_GPIO_MODE_MASK),
> >>>> -	AIROHA_PINCTRL_PWM_EXT_SEC("gpio41", GPIO41_FLASH_MODE_CFG,
> >>>> -				   AN7583_I2C1_SCL_GPIO_MODE_MASK),
> >>>> -	AIROHA_PINCTRL_PWM_EXT_SEC("gpio42", GPIO42_FLASH_MODE_CFG,
> >>>> -				   AN7583_I2C1_SDA_GPIO_MODE_MASK),
> >>>> -	AIROHA_PINCTRL_PWM_EXT_SEC("gpio43", GPIO43_FLASH_MODE_CFG,
> >>>> -				   AN7583_SPI_CLK_GPIO_MODE_MASK),
> >>>> -	AIROHA_PINCTRL_PWM_EXT_SEC("gpio44", GPIO44_FLASH_MODE_CFG,
> >>>> -				   AN7583_SPI_CS_GPIO_MODE_MASK),
> >>>> -	AIROHA_PINCTRL_PWM_EXT_SEC("gpio45", GPIO45_FLASH_MODE_CFG,
> >>>> -				   AN7583_SPI_MOSI_GPIO_MODE_MASK),
> >>>> -	AIROHA_PINCTRL_PWM_EXT_SEC("gpio46", GPIO46_FLASH_MODE_CFG,
> >>>> -				   AN7583_SPI_MISO_GPIO_MODE_MASK),
> >>>> -	AIROHA_PINCTRL_PWM_EXT_SEC("gpio47", GPIO47_FLASH_MODE_CFG,
> >>>> -				   AN7583_UART_TXD_GPIO_MODE_MASK),
> >>>> -	AIROHA_PINCTRL_PWM_EXT_SEC("gpio48", GPIO48_FLASH_MODE_CFG,
> >>>> -				   AN7583_UART_RXD_GPIO_MODE_MASK),
> >>>> -	AIROHA_PINCTRL_PWM_EXT_SEC("gpio49", GPIO49_FLASH_MODE_CFG,
> >>>> -				   GPIO_PCIE_RESET0_MASK),
> >>>> -	AIROHA_PINCTRL_PWM_EXT_SEC("gpio50", GPIO50_FLASH_MODE_CFG,
> >>>> -				   GPIO_PCIE_RESET1_MASK),
> >>>> -	AIROHA_PINCTRL_PWM_EXT_SEC("gpio51", GPIO51_FLASH_MODE_CFG,
> >>>> -				   AN7583_MDC_0_GPIO_MODE_MASK),
> >>>> -};
> >>>> -
> >>>> -static const struct airoha_pinctrl_func_group phy1_led0_func_group[] = {
> >>>> -	AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK,
> >>>> -				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),
> >>>> -	AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK,
> >>>> -				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)),
> >>>> -	AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK,
> >>>> -				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)),
> >>>> -	AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK,
> >>>> -				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),
> >>>> -};
> >>>> -
> >>>> -static const struct airoha_pinctrl_func_group phy2_led0_func_group[] = {
> >>>> -	AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK,
> >>>> -				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),
> >>>> -	AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK,
> >>>> -				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)),
> >>>> -	AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK,
> >>>> -				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)),
> >>>> -	AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK,
> >>>> -				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),
> >>>> -};
> >>>> -
> >>>> -static const struct airoha_pinctrl_func_group phy3_led0_func_group[] = {
> >>>> -	AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK,
> >>>> -				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
> >>>> -	AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK,
> >>>> -				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),
> >>>> -	AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK,
> >>>> -				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),
> >>>> -	AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK,
> >>>> -				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
> >>>> -};
> >>>> -
> >>>> -static const struct airoha_pinctrl_func_group phy4_led0_func_group[] = {
> >>>> -	AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK,
> >>>> -				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)),
> >>>> -	AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK,
> >>>> -				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)),
> >>>> -	AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK,
> >>>> -				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)),
> >>>> -	AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK,
> >>>> -				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)),
> >>>> -};
> >>>> -
> >>>> -static const struct airoha_pinctrl_func_group phy1_led1_func_group[] = {
> >>>> -	AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK,
> >>>> -				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),
> >>>> -	AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK,
> >>>> -				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)),
> >>>> -	AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK,
> >>>> -				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)),
> >>>> -	AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK,
> >>>> -				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),
> >>>> -};
> >>>> -
> >>>> -static const struct airoha_pinctrl_func_group phy2_led1_func_group[] = {
> >>>> -	AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK,
> >>>> -				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),
> >>>> -	AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK,
> >>>> -				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)),
> >>>> -	AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK,
> >>>> -				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)),
> >>>> -	AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK,
> >>>> -				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),
> >>>> -};
> >>>> -
> >>>> -static const struct airoha_pinctrl_func_group phy3_led1_func_group[] = {
> >>>> -	AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK,
> >>>> -				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
> >>>> -	AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK,
> >>>> -				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),
> >>>> -	AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK,
> >>>> -				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),
> >>>> -	AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK,
> >>>> -				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
> >>>> -};
> >>>> -
> >>>> -static const struct airoha_pinctrl_func_group phy4_led1_func_group[] = {
> >>>> -	AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK,
> >>>> -				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)),
> >>>> -	AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK,
> >>>> -				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)),
> >>>> -	AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK,
> >>>> -				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)),
> >>>> -	AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK,
> >>>> -				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)),
> >>>> -};
> >>>> -
> >>>> -static const struct airoha_pinctrl_func_group an7583_phy1_led0_func_group[] = {
> >>>> -	AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK,
> >>>> -				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),
> >>>> -	AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK,
> >>>> -				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)),
> >>>> -	AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK,
> >>>> -				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)),
> >>>> -	AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK,
> >>>> -				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),
> >>>> -};
> >>>> -
> >>>> -static const struct airoha_pinctrl_func_group an7583_phy2_led0_func_group[] = {
> >>>> -	AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK,
> >>>> -				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),
> >>>> -	AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK,
> >>>> -				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)),
> >>>> -	AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK,
> >>>> -				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)),
> >>>> -	AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK,
> >>>> -				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),
> >>>> -};
> >>>> -
> >>>> -static const struct airoha_pinctrl_func_group an7583_phy3_led0_func_group[] = {
> >>>> -	AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK,
> >>>> -				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
> >>>> -	AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK,
> >>>> -				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),
> >>>> -	AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK,
> >>>> -				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),
> >>>> -	AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK,
> >>>> -				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
> >>>> -};
> >>>> -
> >>>> -static const struct airoha_pinctrl_func_group an7583_phy4_led0_func_group[] = {
> >>>> -	AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK,
> >>>> -				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)),
> >>>> -	AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK,
> >>>> -				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)),
> >>>> -	AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK,
> >>>> -				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)),
> >>>> -	AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK,
> >>>> -				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)),
> >>>> -};
> >>>> -
> >>>> -static const struct airoha_pinctrl_func_group an7583_phy1_led1_func_group[] = {
> >>>> -	AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK,
> >>>> -				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),
> >>>> -	AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK,
> >>>> -				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)),
> >>>> -	AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK,
> >>>> -				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)),
> >>>> -	AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK,
> >>>> -				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),
> >>>> -};
> >>>> -
> >>>> -static const struct airoha_pinctrl_func_group an7583_phy2_led1_func_group[] = {
> >>>> -	AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK,
> >>>> -				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),
> >>>> -	AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK,
> >>>> -				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)),
> >>>> -	AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK,
> >>>> -				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)),
> >>>> -	AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK,
> >>>> -				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),
> >>>> -};
> >>>> -
> >>>> -static const struct airoha_pinctrl_func_group an7583_phy3_led1_func_group[] = {
> >>>> -	AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK,
> >>>> -				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
> >>>> -	AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK,
> >>>> -				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),
> >>>> -	AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK,
> >>>> -				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),
> >>>> -	AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK,
> >>>> -				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
> >>>> -};
> >>>> -
> >>>> -static const struct airoha_pinctrl_func_group an7583_phy4_led1_func_group[] = {
> >>>> -	AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK,
> >>>> -				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)),
> >>>> -	AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK,
> >>>> -				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)),
> >>>> -	AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK,
> >>>> -				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)),
> >>>> -	AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK,
> >>>> -				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)),
> >>>> -};
> >>>> -
> >>>> -static const struct airoha_pinctrl_func en7581_pinctrl_funcs[] = {
> >>>> -	PINCTRL_FUNC_DESC("pon", pon),
> >>>> -	PINCTRL_FUNC_DESC("tod_1pps", tod_1pps),
> >>>> -	PINCTRL_FUNC_DESC("sipo", sipo),
> >>>> -	PINCTRL_FUNC_DESC("mdio", mdio),
> >>>> -	PINCTRL_FUNC_DESC("uart", uart),
> >>>> -	PINCTRL_FUNC_DESC("i2c", i2c),
> >>>> -	PINCTRL_FUNC_DESC("jtag", jtag),
> >>>> -	PINCTRL_FUNC_DESC("pcm", pcm),
> >>>> -	PINCTRL_FUNC_DESC("spi", spi),
> >>>> -	PINCTRL_FUNC_DESC("pcm_spi", pcm_spi),
> >>>> -	PINCTRL_FUNC_DESC("i2s", i2s),
> >>>> -	PINCTRL_FUNC_DESC("emmc", emmc),
> >>>> -	PINCTRL_FUNC_DESC("pnand", pnand),
> >>>> -	PINCTRL_FUNC_DESC("gpio", gpio),
> >>>> -	PINCTRL_FUNC_DESC("pcie_reset", pcie_reset),
> >>>> -	PINCTRL_FUNC_DESC("pwm", pwm),
> >>>> -	PINCTRL_FUNC_DESC("phy1_led0", phy1_led0),
> >>>> -	PINCTRL_FUNC_DESC("phy2_led0", phy2_led0),
> >>>> -	PINCTRL_FUNC_DESC("phy3_led0", phy3_led0),
> >>>> -	PINCTRL_FUNC_DESC("phy4_led0", phy4_led0),
> >>>> -	PINCTRL_FUNC_DESC("phy1_led1", phy1_led1),
> >>>> -	PINCTRL_FUNC_DESC("phy2_led1", phy2_led1),
> >>>> -	PINCTRL_FUNC_DESC("phy3_led1", phy3_led1),
> >>>> -	PINCTRL_FUNC_DESC("phy4_led1", phy4_led1),
> >>>> -};
> >>>> -
> >>>> -static const struct airoha_pinctrl_func an7583_pinctrl_funcs[] = {
> >>>> -	PINCTRL_FUNC_DESC("pon", pon),
> >>>> -	PINCTRL_FUNC_DESC("tod_1pps", tod_1pps),
> >>>> -	PINCTRL_FUNC_DESC("sipo", sipo),
> >>>> -	PINCTRL_FUNC_DESC("mdio", an7583_mdio),
> >>>> -	PINCTRL_FUNC_DESC("uart", uart),
> >>>> -	PINCTRL_FUNC_DESC("jtag", jtag),
> >>>> -	PINCTRL_FUNC_DESC("pcm", pcm),
> >>>> -	PINCTRL_FUNC_DESC("spi", spi),
> >>>> -	PINCTRL_FUNC_DESC("pcm_spi", an7583_pcm_spi),
> >>>> -	PINCTRL_FUNC_DESC("emmc", emmc),
> >>>> -	PINCTRL_FUNC_DESC("pnand", pnand),
> >>>> -	PINCTRL_FUNC_DESC("gpio", an7583_gpio),
> >>>> -	PINCTRL_FUNC_DESC("pcie_reset", an7583_pcie_reset),
> >>>> -	PINCTRL_FUNC_DESC("pwm", an7583_pwm),
> >>>> -	PINCTRL_FUNC_DESC("phy1_led0", an7583_phy1_led0),
> >>>> -	PINCTRL_FUNC_DESC("phy2_led0", an7583_phy2_led0),
> >>>> -	PINCTRL_FUNC_DESC("phy3_led0", an7583_phy3_led0),
> >>>> -	PINCTRL_FUNC_DESC("phy4_led0", an7583_phy4_led0),
> >>>> -	PINCTRL_FUNC_DESC("phy1_led1", an7583_phy1_led1),
> >>>> -	PINCTRL_FUNC_DESC("phy2_led1", an7583_phy2_led1),
> >>>> -	PINCTRL_FUNC_DESC("phy3_led1", an7583_phy3_led1),
> >>>> -	PINCTRL_FUNC_DESC("phy4_led1", an7583_phy4_led1),
> >>>> -};
> >>>> -
> >>>> -static const struct airoha_pinctrl_conf en7581_pinctrl_pullup_conf[] = {
> >>>> -	PINCTRL_CONF_DESC(0, REG_I2C_SDA_PU, UART1_TXD_PU_MASK),
> >>>> -	PINCTRL_CONF_DESC(1, REG_I2C_SDA_PU, UART1_RXD_PU_MASK),
> >>>> -	PINCTRL_CONF_DESC(2, REG_I2C_SDA_PU, I2C_SDA_PU_MASK),
> >>>> -	PINCTRL_CONF_DESC(3, REG_I2C_SDA_PU, I2C_SCL_PU_MASK),
> >>>> -	PINCTRL_CONF_DESC(4, REG_I2C_SDA_PU, SPI_CS0_PU_MASK),
> >>>> -	PINCTRL_CONF_DESC(5, REG_I2C_SDA_PU, SPI_CLK_PU_MASK),
> >>>> -	PINCTRL_CONF_DESC(6, REG_I2C_SDA_PU, SPI_MOSI_PU_MASK),
> >>>> -	PINCTRL_CONF_DESC(7, REG_I2C_SDA_PU, SPI_MISO_PU_MASK),
> >>>> -	PINCTRL_CONF_DESC(13, REG_GPIO_L_PU, BIT(0)),
> >>>> -	PINCTRL_CONF_DESC(14, REG_GPIO_L_PU, BIT(1)),
> >>>> -	PINCTRL_CONF_DESC(15, REG_GPIO_L_PU, BIT(2)),
> >>>> -	PINCTRL_CONF_DESC(16, REG_GPIO_L_PU, BIT(3)),
> >>>> -	PINCTRL_CONF_DESC(17, REG_GPIO_L_PU, BIT(4)),
> >>>> -	PINCTRL_CONF_DESC(18, REG_GPIO_L_PU, BIT(5)),
> >>>> -	PINCTRL_CONF_DESC(19, REG_GPIO_L_PU, BIT(6)),
> >>>> -	PINCTRL_CONF_DESC(20, REG_GPIO_L_PU, BIT(7)),
> >>>> -	PINCTRL_CONF_DESC(21, REG_GPIO_L_PU, BIT(8)),
> >>>> -	PINCTRL_CONF_DESC(22, REG_GPIO_L_PU, BIT(9)),
> >>>> -	PINCTRL_CONF_DESC(23, REG_GPIO_L_PU, BIT(10)),
> >>>> -	PINCTRL_CONF_DESC(24, REG_GPIO_L_PU, BIT(11)),
> >>>> -	PINCTRL_CONF_DESC(25, REG_GPIO_L_PU, BIT(12)),
> >>>> -	PINCTRL_CONF_DESC(26, REG_GPIO_L_PU, BIT(13)),
> >>>> -	PINCTRL_CONF_DESC(27, REG_GPIO_L_PU, BIT(14)),
> >>>> -	PINCTRL_CONF_DESC(28, REG_GPIO_L_PU, BIT(15)),
> >>>> -	PINCTRL_CONF_DESC(29, REG_GPIO_L_PU, BIT(16)),
> >>>> -	PINCTRL_CONF_DESC(30, REG_GPIO_L_PU, BIT(17)),
> >>>> -	PINCTRL_CONF_DESC(31, REG_GPIO_L_PU, BIT(18)),
> >>>> -	PINCTRL_CONF_DESC(32, REG_GPIO_L_PU, BIT(19)),
> >>>> -	PINCTRL_CONF_DESC(33, REG_GPIO_L_PU, BIT(20)),
> >>>> -	PINCTRL_CONF_DESC(34, REG_GPIO_L_PU, BIT(21)),
> >>>> -	PINCTRL_CONF_DESC(35, REG_GPIO_L_PU, BIT(22)),
> >>>> -	PINCTRL_CONF_DESC(36, REG_GPIO_L_PU, BIT(23)),
> >>>> -	PINCTRL_CONF_DESC(37, REG_GPIO_L_PU, BIT(24)),
> >>>> -	PINCTRL_CONF_DESC(38, REG_GPIO_L_PU, BIT(25)),
> >>>> -	PINCTRL_CONF_DESC(39, REG_GPIO_L_PU, BIT(26)),
> >>>> -	PINCTRL_CONF_DESC(40, REG_GPIO_L_PU, BIT(27)),
> >>>> -	PINCTRL_CONF_DESC(41, REG_GPIO_L_PU, BIT(28)),
> >>>> -	PINCTRL_CONF_DESC(42, REG_GPIO_L_PU, BIT(29)),
> >>>> -	PINCTRL_CONF_DESC(43, REG_GPIO_L_PU, BIT(30)),
> >>>> -	PINCTRL_CONF_DESC(44, REG_GPIO_L_PU, BIT(31)),
> >>>> -	PINCTRL_CONF_DESC(45, REG_GPIO_H_PU, BIT(0)),
> >>>> -	PINCTRL_CONF_DESC(46, REG_GPIO_H_PU, BIT(1)),
> >>>> -	PINCTRL_CONF_DESC(47, REG_GPIO_H_PU, BIT(2)),
> >>>> -	PINCTRL_CONF_DESC(48, REG_GPIO_H_PU, BIT(3)),
> >>>> -	PINCTRL_CONF_DESC(49, REG_GPIO_H_PU, BIT(4)),
> >>>> -	PINCTRL_CONF_DESC(50, REG_GPIO_H_PU, BIT(5)),
> >>>> -	PINCTRL_CONF_DESC(51, REG_GPIO_H_PU, BIT(6)),
> >>>> -	PINCTRL_CONF_DESC(52, REG_GPIO_H_PU, BIT(7)),
> >>>> -	PINCTRL_CONF_DESC(53, REG_GPIO_H_PU, BIT(8)),
> >>>> -	PINCTRL_CONF_DESC(54, REG_GPIO_H_PU, BIT(9)),
> >>>> -	PINCTRL_CONF_DESC(55, REG_GPIO_H_PU, BIT(10)),
> >>>> -	PINCTRL_CONF_DESC(56, REG_GPIO_H_PU, BIT(11)),
> >>>> -	PINCTRL_CONF_DESC(57, REG_GPIO_H_PU, BIT(12)),
> >>>> -	PINCTRL_CONF_DESC(58, REG_GPIO_H_PU, BIT(13)),
> >>>> -	PINCTRL_CONF_DESC(59, REG_GPIO_H_PU, BIT(14)),
> >>>> -	PINCTRL_CONF_DESC(60, REG_I2C_SDA_PU, PCIE0_RESET_PU_MASK),
> >>>> -	PINCTRL_CONF_DESC(61, REG_I2C_SDA_PU, PCIE1_RESET_PU_MASK),
> >>>> -	PINCTRL_CONF_DESC(62, REG_I2C_SDA_PU, PCIE2_RESET_PU_MASK),
> >>>> -};
> >>>> -
> >>>> -static const struct airoha_pinctrl_conf an7583_pinctrl_pullup_conf[] = {
> >>>> -	PINCTRL_CONF_DESC(2, REG_GPIO_L_PU, BIT(0)),
> >>>> -	PINCTRL_CONF_DESC(3, REG_GPIO_L_PU, BIT(1)),
> >>>> -	PINCTRL_CONF_DESC(4, REG_GPIO_L_PU, BIT(2)),
> >>>> -	PINCTRL_CONF_DESC(5, REG_GPIO_L_PU, BIT(3)),
> >>>> -	PINCTRL_CONF_DESC(6, REG_GPIO_L_PU, BIT(4)),
> >>>> -	PINCTRL_CONF_DESC(7, REG_GPIO_L_PU, BIT(5)),
> >>>> -	PINCTRL_CONF_DESC(8, REG_GPIO_L_PU, BIT(6)),
> >>>> -	PINCTRL_CONF_DESC(9, REG_GPIO_L_PU, BIT(7)),
> >>>> -	PINCTRL_CONF_DESC(10, REG_GPIO_L_PU, BIT(8)),
> >>>> -	PINCTRL_CONF_DESC(11, REG_GPIO_L_PU, BIT(9)),
> >>>> -	PINCTRL_CONF_DESC(12, REG_GPIO_L_PU, BIT(10)),
> >>>> -	PINCTRL_CONF_DESC(13, REG_GPIO_L_PU, BIT(11)),
> >>>> -	PINCTRL_CONF_DESC(14, REG_GPIO_L_PU, BIT(12)),
> >>>> -	PINCTRL_CONF_DESC(15, REG_GPIO_L_PU, BIT(13)),
> >>>> -	PINCTRL_CONF_DESC(16, REG_GPIO_L_PU, BIT(14)),
> >>>> -	PINCTRL_CONF_DESC(17, REG_GPIO_L_PU, BIT(15)),
> >>>> -	PINCTRL_CONF_DESC(18, REG_GPIO_L_PU, BIT(16)),
> >>>> -	PINCTRL_CONF_DESC(19, REG_GPIO_L_PU, BIT(17)),
> >>>> -	PINCTRL_CONF_DESC(20, REG_GPIO_L_PU, BIT(18)),
> >>>> -	PINCTRL_CONF_DESC(21, REG_GPIO_L_PU, BIT(19)),
> >>>> -	PINCTRL_CONF_DESC(22, REG_GPIO_L_PU, BIT(20)),
> >>>> -	PINCTRL_CONF_DESC(23, REG_GPIO_L_PU, BIT(21)),
> >>>> -	PINCTRL_CONF_DESC(24, REG_GPIO_L_PU, BIT(22)),
> >>>> -	PINCTRL_CONF_DESC(25, REG_GPIO_L_PU, BIT(23)),
> >>>> -	PINCTRL_CONF_DESC(26, REG_GPIO_L_PU, BIT(24)),
> >>>> -	PINCTRL_CONF_DESC(27, REG_GPIO_L_PU, BIT(25)),
> >>>> -	PINCTRL_CONF_DESC(28, REG_GPIO_L_PU, BIT(26)),
> >>>> -	PINCTRL_CONF_DESC(29, REG_GPIO_L_PU, BIT(27)),
> >>>> -	PINCTRL_CONF_DESC(30, REG_GPIO_L_PU, BIT(28)),
> >>>> -	PINCTRL_CONF_DESC(31, REG_GPIO_L_PU, BIT(29)),
> >>>> -	PINCTRL_CONF_DESC(32, REG_GPIO_L_PU, BIT(30)),
> >>>> -	PINCTRL_CONF_DESC(33, REG_GPIO_L_PU, BIT(31)),
> >>>> -	PINCTRL_CONF_DESC(34, REG_GPIO_H_PU, BIT(0)),
> >>>> -	PINCTRL_CONF_DESC(35, REG_GPIO_H_PU, BIT(1)),
> >>>> -	PINCTRL_CONF_DESC(36, REG_GPIO_H_PU, BIT(2)),
> >>>> -	PINCTRL_CONF_DESC(37, REG_GPIO_H_PU, BIT(3)),
> >>>> -	PINCTRL_CONF_DESC(38, REG_GPIO_H_PU, BIT(4)),
> >>>> -	PINCTRL_CONF_DESC(39, REG_GPIO_H_PU, BIT(5)),
> >>>> -	PINCTRL_CONF_DESC(40, REG_GPIO_H_PU, BIT(6)),
> >>>> -	PINCTRL_CONF_DESC(41, REG_I2C_SDA_PU, I2C_SCL_PU_MASK),
> >>>> -	PINCTRL_CONF_DESC(42, REG_I2C_SDA_PU, I2C_SDA_PU_MASK),
> >>>> -	PINCTRL_CONF_DESC(43, REG_I2C_SDA_PU, AN7583_I2C1_SCL_PU_MASK),
> >>>> -	PINCTRL_CONF_DESC(44, REG_I2C_SDA_PU, AN7583_I2C1_SDA_PU_MASK),
> >>>> -	PINCTRL_CONF_DESC(45, REG_I2C_SDA_PU, SPI_CLK_PU_MASK),
> >>>> -	PINCTRL_CONF_DESC(46, REG_I2C_SDA_PU, SPI_CS0_PU_MASK),
> >>>> -	PINCTRL_CONF_DESC(47, REG_I2C_SDA_PU, SPI_MOSI_PU_MASK),
> >>>> -	PINCTRL_CONF_DESC(48, REG_I2C_SDA_PU, SPI_MISO_PU_MASK),
> >>>> -	PINCTRL_CONF_DESC(49, REG_I2C_SDA_PU, UART1_TXD_PU_MASK),
> >>>> -	PINCTRL_CONF_DESC(50, REG_I2C_SDA_PU, UART1_RXD_PU_MASK),
> >>>> -	PINCTRL_CONF_DESC(51, REG_I2C_SDA_PU, PCIE0_RESET_PU_MASK),
> >>>> -	PINCTRL_CONF_DESC(52, REG_I2C_SDA_PU, PCIE1_RESET_PU_MASK),
> >>>> -	PINCTRL_CONF_DESC(53, REG_I2C_SDA_PU, AN7583_MDC_0_PU_MASK),
> >>>> -	PINCTRL_CONF_DESC(54, REG_I2C_SDA_PU, AN7583_MDIO_0_PU_MASK),
> >>>> -};
> >>>> -
> >>>> -static const struct airoha_pinctrl_conf en7581_pinctrl_pulldown_conf[] = {
> >>>> -	PINCTRL_CONF_DESC(0, REG_I2C_SDA_PD, UART1_TXD_PD_MASK),
> >>>> -	PINCTRL_CONF_DESC(1, REG_I2C_SDA_PD, UART1_RXD_PD_MASK),
> >>>> -	PINCTRL_CONF_DESC(2, REG_I2C_SDA_PD, I2C_SDA_PD_MASK),
> >>>> -	PINCTRL_CONF_DESC(3, REG_I2C_SDA_PD, I2C_SCL_PD_MASK),
> >>>> -	PINCTRL_CONF_DESC(4, REG_I2C_SDA_PD, SPI_CS0_PD_MASK),
> >>>> -	PINCTRL_CONF_DESC(5, REG_I2C_SDA_PD, SPI_CLK_PD_MASK),
> >>>> -	PINCTRL_CONF_DESC(6, REG_I2C_SDA_PD, SPI_MOSI_PD_MASK),
> >>>> -	PINCTRL_CONF_DESC(7, REG_I2C_SDA_PD, SPI_MISO_PD_MASK),
> >>>> -	PINCTRL_CONF_DESC(13, REG_GPIO_L_PD, BIT(0)),
> >>>> -	PINCTRL_CONF_DESC(14, REG_GPIO_L_PD, BIT(1)),
> >>>> -	PINCTRL_CONF_DESC(15, REG_GPIO_L_PD, BIT(2)),
> >>>> -	PINCTRL_CONF_DESC(16, REG_GPIO_L_PD, BIT(3)),
> >>>> -	PINCTRL_CONF_DESC(17, REG_GPIO_L_PD, BIT(4)),
> >>>> -	PINCTRL_CONF_DESC(18, REG_GPIO_L_PD, BIT(5)),
> >>>> -	PINCTRL_CONF_DESC(19, REG_GPIO_L_PD, BIT(6)),
> >>>> -	PINCTRL_CONF_DESC(20, REG_GPIO_L_PD, BIT(7)),
> >>>> -	PINCTRL_CONF_DESC(21, REG_GPIO_L_PD, BIT(8)),
> >>>> -	PINCTRL_CONF_DESC(22, REG_GPIO_L_PD, BIT(9)),
> >>>> -	PINCTRL_CONF_DESC(23, REG_GPIO_L_PD, BIT(10)),
> >>>> -	PINCTRL_CONF_DESC(24, REG_GPIO_L_PD, BIT(11)),
> >>>> -	PINCTRL_CONF_DESC(25, REG_GPIO_L_PD, BIT(12)),
> >>>> -	PINCTRL_CONF_DESC(26, REG_GPIO_L_PD, BIT(13)),
> >>>> -	PINCTRL_CONF_DESC(27, REG_GPIO_L_PD, BIT(14)),
> >>>> -	PINCTRL_CONF_DESC(28, REG_GPIO_L_PD, BIT(15)),
> >>>> -	PINCTRL_CONF_DESC(29, REG_GPIO_L_PD, BIT(16)),
> >>>> -	PINCTRL_CONF_DESC(30, REG_GPIO_L_PD, BIT(17)),
> >>>> -	PINCTRL_CONF_DESC(31, REG_GPIO_L_PD, BIT(18)),
> >>>> -	PINCTRL_CONF_DESC(32, REG_GPIO_L_PD, BIT(19)),
> >>>> -	PINCTRL_CONF_DESC(33, REG_GPIO_L_PD, BIT(20)),
> >>>> -	PINCTRL_CONF_DESC(34, REG_GPIO_L_PD, BIT(21)),
> >>>> -	PINCTRL_CONF_DESC(35, REG_GPIO_L_PD, BIT(22)),
> >>>> -	PINCTRL_CONF_DESC(36, REG_GPIO_L_PD, BIT(23)),
> >>>> -	PINCTRL_CONF_DESC(37, REG_GPIO_L_PD, BIT(24)),
> >>>> -	PINCTRL_CONF_DESC(38, REG_GPIO_L_PD, BIT(25)),
> >>>> -	PINCTRL_CONF_DESC(39, REG_GPIO_L_PD, BIT(26)),
> >>>> -	PINCTRL_CONF_DESC(40, REG_GPIO_L_PD, BIT(27)),
> >>>> -	PINCTRL_CONF_DESC(41, REG_GPIO_L_PD, BIT(28)),
> >>>> -	PINCTRL_CONF_DESC(42, REG_GPIO_L_PD, BIT(29)),
> >>>> -	PINCTRL_CONF_DESC(43, REG_GPIO_L_PD, BIT(30)),
> >>>> -	PINCTRL_CONF_DESC(44, REG_GPIO_L_PD, BIT(31)),
> >>>> -	PINCTRL_CONF_DESC(45, REG_GPIO_H_PD, BIT(0)),
> >>>> -	PINCTRL_CONF_DESC(46, REG_GPIO_H_PD, BIT(1)),
> >>>> -	PINCTRL_CONF_DESC(47, REG_GPIO_H_PD, BIT(2)),
> >>>> -	PINCTRL_CONF_DESC(48, REG_GPIO_H_PD, BIT(3)),
> >>>> -	PINCTRL_CONF_DESC(49, REG_GPIO_H_PD, BIT(4)),
> >>>> -	PINCTRL_CONF_DESC(50, REG_GPIO_H_PD, BIT(5)),
> >>>> -	PINCTRL_CONF_DESC(51, REG_GPIO_H_PD, BIT(6)),
> >>>> -	PINCTRL_CONF_DESC(52, REG_GPIO_H_PD, BIT(7)),
> >>>> -	PINCTRL_CONF_DESC(53, REG_GPIO_H_PD, BIT(8)),
> >>>> -	PINCTRL_CONF_DESC(54, REG_GPIO_H_PD, BIT(9)),
> >>>> -	PINCTRL_CONF_DESC(55, REG_GPIO_H_PD, BIT(10)),
> >>>> -	PINCTRL_CONF_DESC(56, REG_GPIO_H_PD, BIT(11)),
> >>>> -	PINCTRL_CONF_DESC(57, REG_GPIO_H_PD, BIT(12)),
> >>>> -	PINCTRL_CONF_DESC(58, REG_GPIO_H_PD, BIT(13)),
> >>>> -	PINCTRL_CONF_DESC(59, REG_GPIO_H_PD, BIT(14)),
> >>>> -	PINCTRL_CONF_DESC(60, REG_I2C_SDA_PD, PCIE0_RESET_PD_MASK),
> >>>> -	PINCTRL_CONF_DESC(61, REG_I2C_SDA_PD, PCIE1_RESET_PD_MASK),
> >>>> -	PINCTRL_CONF_DESC(62, REG_I2C_SDA_PD, PCIE2_RESET_PD_MASK),
> >>>> -};
> >>>> -
> >>>> -static const struct airoha_pinctrl_conf an7583_pinctrl_pulldown_conf[] = {
> >>>> -	PINCTRL_CONF_DESC(2, REG_GPIO_L_PD, BIT(0)),
> >>>> -	PINCTRL_CONF_DESC(3, REG_GPIO_L_PD, BIT(1)),
> >>>> -	PINCTRL_CONF_DESC(4, REG_GPIO_L_PD, BIT(2)),
> >>>> -	PINCTRL_CONF_DESC(5, REG_GPIO_L_PD, BIT(3)),
> >>>> -	PINCTRL_CONF_DESC(6, REG_GPIO_L_PD, BIT(4)),
> >>>> -	PINCTRL_CONF_DESC(7, REG_GPIO_L_PD, BIT(5)),
> >>>> -	PINCTRL_CONF_DESC(8, REG_GPIO_L_PD, BIT(6)),
> >>>> -	PINCTRL_CONF_DESC(9, REG_GPIO_L_PD, BIT(7)),
> >>>> -	PINCTRL_CONF_DESC(10, REG_GPIO_L_PD, BIT(8)),
> >>>> -	PINCTRL_CONF_DESC(11, REG_GPIO_L_PD, BIT(9)),
> >>>> -	PINCTRL_CONF_DESC(12, REG_GPIO_L_PD, BIT(10)),
> >>>> -	PINCTRL_CONF_DESC(13, REG_GPIO_L_PD, BIT(11)),
> >>>> -	PINCTRL_CONF_DESC(14, REG_GPIO_L_PD, BIT(12)),
> >>>> -	PINCTRL_CONF_DESC(15, REG_GPIO_L_PD, BIT(13)),
> >>>> -	PINCTRL_CONF_DESC(16, REG_GPIO_L_PD, BIT(14)),
> >>>> -	PINCTRL_CONF_DESC(17, REG_GPIO_L_PD, BIT(15)),
> >>>> -	PINCTRL_CONF_DESC(18, REG_GPIO_L_PD, BIT(16)),
> >>>> -	PINCTRL_CONF_DESC(19, REG_GPIO_L_PD, BIT(17)),
> >>>> -	PINCTRL_CONF_DESC(20, REG_GPIO_L_PD, BIT(18)),
> >>>> -	PINCTRL_CONF_DESC(21, REG_GPIO_L_PD, BIT(19)),
> >>>> -	PINCTRL_CONF_DESC(22, REG_GPIO_L_PD, BIT(20)),
> >>>> -	PINCTRL_CONF_DESC(23, REG_GPIO_L_PD, BIT(21)),
> >>>> -	PINCTRL_CONF_DESC(24, REG_GPIO_L_PD, BIT(22)),
> >>>> -	PINCTRL_CONF_DESC(25, REG_GPIO_L_PD, BIT(23)),
> >>>> -	PINCTRL_CONF_DESC(26, REG_GPIO_L_PD, BIT(24)),
> >>>> -	PINCTRL_CONF_DESC(27, REG_GPIO_L_PD, BIT(25)),
> >>>> -	PINCTRL_CONF_DESC(28, REG_GPIO_L_PD, BIT(26)),
> >>>> -	PINCTRL_CONF_DESC(29, REG_GPIO_L_PD, BIT(27)),
> >>>> -	PINCTRL_CONF_DESC(30, REG_GPIO_L_PD, BIT(28)),
> >>>> -	PINCTRL_CONF_DESC(31, REG_GPIO_L_PD, BIT(29)),
> >>>> -	PINCTRL_CONF_DESC(32, REG_GPIO_L_PD, BIT(30)),
> >>>> -	PINCTRL_CONF_DESC(33, REG_GPIO_L_PD, BIT(31)),
> >>>> -	PINCTRL_CONF_DESC(34, REG_GPIO_H_PD, BIT(0)),
> >>>> -	PINCTRL_CONF_DESC(35, REG_GPIO_H_PD, BIT(1)),
> >>>> -	PINCTRL_CONF_DESC(36, REG_GPIO_H_PD, BIT(2)),
> >>>> -	PINCTRL_CONF_DESC(37, REG_GPIO_H_PD, BIT(3)),
> >>>> -	PINCTRL_CONF_DESC(38, REG_GPIO_H_PD, BIT(4)),
> >>>> -	PINCTRL_CONF_DESC(39, REG_GPIO_H_PD, BIT(5)),
> >>>> -	PINCTRL_CONF_DESC(40, REG_GPIO_H_PD, BIT(6)),
> >>>> -	PINCTRL_CONF_DESC(41, REG_I2C_SDA_PD, I2C_SCL_PD_MASK),
> >>>> -	PINCTRL_CONF_DESC(42, REG_I2C_SDA_PD, I2C_SDA_PD_MASK),
> >>>> -	PINCTRL_CONF_DESC(43, REG_I2C_SDA_PD, AN7583_I2C1_SCL_PD_MASK),
> >>>> -	PINCTRL_CONF_DESC(44, REG_I2C_SDA_PD, AN7583_I2C1_SDA_PD_MASK),
> >>>> -	PINCTRL_CONF_DESC(45, REG_I2C_SDA_PD, SPI_CLK_PD_MASK),
> >>>> -	PINCTRL_CONF_DESC(46, REG_I2C_SDA_PD, SPI_CS0_PD_MASK),
> >>>> -	PINCTRL_CONF_DESC(47, REG_I2C_SDA_PD, SPI_MOSI_PD_MASK),
> >>>> -	PINCTRL_CONF_DESC(48, REG_I2C_SDA_PD, SPI_MISO_PD_MASK),
> >>>> -	PINCTRL_CONF_DESC(49, REG_I2C_SDA_PD, UART1_TXD_PD_MASK),
> >>>> -	PINCTRL_CONF_DESC(50, REG_I2C_SDA_PD, UART1_RXD_PD_MASK),
> >>>> -	PINCTRL_CONF_DESC(51, REG_I2C_SDA_PD, PCIE0_RESET_PD_MASK),
> >>>> -	PINCTRL_CONF_DESC(52, REG_I2C_SDA_PD, PCIE1_RESET_PD_MASK),
> >>>> -	PINCTRL_CONF_DESC(53, REG_I2C_SDA_PD, AN7583_MDC_0_PD_MASK),
> >>>> -	PINCTRL_CONF_DESC(54, REG_I2C_SDA_PD, AN7583_MDIO_0_PD_MASK),
> >>>> -};
> >>>> -
> >>>> -static const struct airoha_pinctrl_conf en7581_pinctrl_drive_e2_conf[] = {
> >>>> -	PINCTRL_CONF_DESC(0, REG_I2C_SDA_E2, UART1_TXD_E2_MASK),
> >>>> -	PINCTRL_CONF_DESC(1, REG_I2C_SDA_E2, UART1_RXD_E2_MASK),
> >>>> -	PINCTRL_CONF_DESC(2, REG_I2C_SDA_E2, I2C_SDA_E2_MASK),
> >>>> -	PINCTRL_CONF_DESC(3, REG_I2C_SDA_E2, I2C_SCL_E2_MASK),
> >>>> -	PINCTRL_CONF_DESC(4, REG_I2C_SDA_E2, SPI_CS0_E2_MASK),
> >>>> -	PINCTRL_CONF_DESC(5, REG_I2C_SDA_E2, SPI_CLK_E2_MASK),
> >>>> -	PINCTRL_CONF_DESC(6, REG_I2C_SDA_E2, SPI_MOSI_E2_MASK),
> >>>> -	PINCTRL_CONF_DESC(7, REG_I2C_SDA_E2, SPI_MISO_E2_MASK),
> >>>> -	PINCTRL_CONF_DESC(13, REG_GPIO_L_E2, BIT(0)),
> >>>> -	PINCTRL_CONF_DESC(14, REG_GPIO_L_E2, BIT(1)),
> >>>> -	PINCTRL_CONF_DESC(15, REG_GPIO_L_E2, BIT(2)),
> >>>> -	PINCTRL_CONF_DESC(16, REG_GPIO_L_E2, BIT(3)),
> >>>> -	PINCTRL_CONF_DESC(17, REG_GPIO_L_E2, BIT(4)),
> >>>> -	PINCTRL_CONF_DESC(18, REG_GPIO_L_E2, BIT(5)),
> >>>> -	PINCTRL_CONF_DESC(19, REG_GPIO_L_E2, BIT(6)),
> >>>> -	PINCTRL_CONF_DESC(20, REG_GPIO_L_E2, BIT(7)),
> >>>> -	PINCTRL_CONF_DESC(21, REG_GPIO_L_E2, BIT(8)),
> >>>> -	PINCTRL_CONF_DESC(22, REG_GPIO_L_E2, BIT(9)),
> >>>> -	PINCTRL_CONF_DESC(23, REG_GPIO_L_E2, BIT(10)),
> >>>> -	PINCTRL_CONF_DESC(24, REG_GPIO_L_E2, BIT(11)),
> >>>> -	PINCTRL_CONF_DESC(25, REG_GPIO_L_E2, BIT(12)),
> >>>> -	PINCTRL_CONF_DESC(26, REG_GPIO_L_E2, BIT(13)),
> >>>> -	PINCTRL_CONF_DESC(27, REG_GPIO_L_E2, BIT(14)),
> >>>> -	PINCTRL_CONF_DESC(28, REG_GPIO_L_E2, BIT(15)),
> >>>> -	PINCTRL_CONF_DESC(29, REG_GPIO_L_E2, BIT(16)),
> >>>> -	PINCTRL_CONF_DESC(30, REG_GPIO_L_E2, BIT(17)),
> >>>> -	PINCTRL_CONF_DESC(31, REG_GPIO_L_E2, BIT(18)),
> >>>> -	PINCTRL_CONF_DESC(32, REG_GPIO_L_E2, BIT(19)),
> >>>> -	PINCTRL_CONF_DESC(33, REG_GPIO_L_E2, BIT(20)),
> >>>> -	PINCTRL_CONF_DESC(34, REG_GPIO_L_E2, BIT(21)),
> >>>> -	PINCTRL_CONF_DESC(35, REG_GPIO_L_E2, BIT(22)),
> >>>> -	PINCTRL_CONF_DESC(36, REG_GPIO_L_E2, BIT(23)),
> >>>> -	PINCTRL_CONF_DESC(37, REG_GPIO_L_E2, BIT(24)),
> >>>> -	PINCTRL_CONF_DESC(38, REG_GPIO_L_E2, BIT(25)),
> >>>> -	PINCTRL_CONF_DESC(39, REG_GPIO_L_E2, BIT(26)),
> >>>> -	PINCTRL_CONF_DESC(40, REG_GPIO_L_E2, BIT(27)),
> >>>> -	PINCTRL_CONF_DESC(41, REG_GPIO_L_E2, BIT(28)),
> >>>> -	PINCTRL_CONF_DESC(42, REG_GPIO_L_E2, BIT(29)),
> >>>> -	PINCTRL_CONF_DESC(43, REG_GPIO_L_E2, BIT(30)),
> >>>> -	PINCTRL_CONF_DESC(44, REG_GPIO_L_E2, BIT(31)),
> >>>> -	PINCTRL_CONF_DESC(45, REG_GPIO_H_E2, BIT(0)),
> >>>> -	PINCTRL_CONF_DESC(46, REG_GPIO_H_E2, BIT(1)),
> >>>> -	PINCTRL_CONF_DESC(47, REG_GPIO_H_E2, BIT(2)),
> >>>> -	PINCTRL_CONF_DESC(48, REG_GPIO_H_E2, BIT(3)),
> >>>> -	PINCTRL_CONF_DESC(49, REG_GPIO_H_E2, BIT(4)),
> >>>> -	PINCTRL_CONF_DESC(50, REG_GPIO_H_E2, BIT(5)),
> >>>> -	PINCTRL_CONF_DESC(51, REG_GPIO_H_E2, BIT(6)),
> >>>> -	PINCTRL_CONF_DESC(52, REG_GPIO_H_E2, BIT(7)),
> >>>> -	PINCTRL_CONF_DESC(53, REG_GPIO_H_E2, BIT(8)),
> >>>> -	PINCTRL_CONF_DESC(54, REG_GPIO_H_E2, BIT(9)),
> >>>> -	PINCTRL_CONF_DESC(55, REG_GPIO_H_E2, BIT(10)),
> >>>> -	PINCTRL_CONF_DESC(56, REG_GPIO_H_E2, BIT(11)),
> >>>> -	PINCTRL_CONF_DESC(57, REG_GPIO_H_E2, BIT(12)),
> >>>> -	PINCTRL_CONF_DESC(58, REG_GPIO_H_E2, BIT(13)),
> >>>> -	PINCTRL_CONF_DESC(59, REG_GPIO_H_E2, BIT(14)),
> >>>> -	PINCTRL_CONF_DESC(60, REG_I2C_SDA_E2, PCIE0_RESET_E2_MASK),
> >>>> -	PINCTRL_CONF_DESC(61, REG_I2C_SDA_E2, PCIE1_RESET_E2_MASK),
> >>>> -	PINCTRL_CONF_DESC(62, REG_I2C_SDA_E2, PCIE2_RESET_E2_MASK),
> >>>> -};
> >>>> -
> >>>> -static const struct airoha_pinctrl_conf an7583_pinctrl_drive_e2_conf[] = {
> >>>> -	PINCTRL_CONF_DESC(2, REG_GPIO_L_E2, BIT(0)),
> >>>> -	PINCTRL_CONF_DESC(3, REG_GPIO_L_E2, BIT(1)),
> >>>> -	PINCTRL_CONF_DESC(4, REG_GPIO_L_E2, BIT(2)),
> >>>> -	PINCTRL_CONF_DESC(5, REG_GPIO_L_E2, BIT(3)),
> >>>> -	PINCTRL_CONF_DESC(6, REG_GPIO_L_E2, BIT(4)),
> >>>> -	PINCTRL_CONF_DESC(7, REG_GPIO_L_E2, BIT(5)),
> >>>> -	PINCTRL_CONF_DESC(8, REG_GPIO_L_E2, BIT(6)),
> >>>> -	PINCTRL_CONF_DESC(9, REG_GPIO_L_E2, BIT(7)),
> >>>> -	PINCTRL_CONF_DESC(10, REG_GPIO_L_E2, BIT(8)),
> >>>> -	PINCTRL_CONF_DESC(11, REG_GPIO_L_E2, BIT(9)),
> >>>> -	PINCTRL_CONF_DESC(12, REG_GPIO_L_E2, BIT(10)),
> >>>> -	PINCTRL_CONF_DESC(13, REG_GPIO_L_E2, BIT(11)),
> >>>> -	PINCTRL_CONF_DESC(14, REG_GPIO_L_E2, BIT(12)),
> >>>> -	PINCTRL_CONF_DESC(15, REG_GPIO_L_E2, BIT(13)),
> >>>> -	PINCTRL_CONF_DESC(16, REG_GPIO_L_E2, BIT(14)),
> >>>> -	PINCTRL_CONF_DESC(17, REG_GPIO_L_E2, BIT(15)),
> >>>> -	PINCTRL_CONF_DESC(18, REG_GPIO_L_E2, BIT(16)),
> >>>> -	PINCTRL_CONF_DESC(19, REG_GPIO_L_E2, BIT(17)),
> >>>> -	PINCTRL_CONF_DESC(20, REG_GPIO_L_E2, BIT(18)),
> >>>> -	PINCTRL_CONF_DESC(21, REG_GPIO_L_E2, BIT(19)),
> >>>> -	PINCTRL_CONF_DESC(22, REG_GPIO_L_E2, BIT(20)),
> >>>> -	PINCTRL_CONF_DESC(23, REG_GPIO_L_E2, BIT(21)),
> >>>> -	PINCTRL_CONF_DESC(24, REG_GPIO_L_E2, BIT(22)),
> >>>> -	PINCTRL_CONF_DESC(25, REG_GPIO_L_E2, BIT(23)),
> >>>> -	PINCTRL_CONF_DESC(26, REG_GPIO_L_E2, BIT(24)),
> >>>> -	PINCTRL_CONF_DESC(27, REG_GPIO_L_E2, BIT(25)),
> >>>> -	PINCTRL_CONF_DESC(28, REG_GPIO_L_E2, BIT(26)),
> >>>> -	PINCTRL_CONF_DESC(29, REG_GPIO_L_E2, BIT(27)),
> >>>> -	PINCTRL_CONF_DESC(30, REG_GPIO_L_E2, BIT(28)),
> >>>> -	PINCTRL_CONF_DESC(31, REG_GPIO_L_E2, BIT(29)),
> >>>> -	PINCTRL_CONF_DESC(32, REG_GPIO_L_E2, BIT(30)),
> >>>> -	PINCTRL_CONF_DESC(33, REG_GPIO_L_E2, BIT(31)),
> >>>> -	PINCTRL_CONF_DESC(34, REG_GPIO_H_E2, BIT(0)),
> >>>> -	PINCTRL_CONF_DESC(35, REG_GPIO_H_E2, BIT(1)),
> >>>> -	PINCTRL_CONF_DESC(36, REG_GPIO_H_E2, BIT(2)),
> >>>> -	PINCTRL_CONF_DESC(37, REG_GPIO_H_E2, BIT(3)),
> >>>> -	PINCTRL_CONF_DESC(38, REG_GPIO_H_E2, BIT(4)),
> >>>> -	PINCTRL_CONF_DESC(39, REG_GPIO_H_E2, BIT(5)),
> >>>> -	PINCTRL_CONF_DESC(40, REG_GPIO_H_E2, BIT(6)),
> >>>> -	PINCTRL_CONF_DESC(41, REG_I2C_SDA_E2, I2C_SCL_E2_MASK),
> >>>> -	PINCTRL_CONF_DESC(42, REG_I2C_SDA_E2, I2C_SDA_E2_MASK),
> >>>> -	PINCTRL_CONF_DESC(43, REG_I2C_SDA_E2, AN7583_I2C1_SCL_E2_MASK),
> >>>> -	PINCTRL_CONF_DESC(44, REG_I2C_SDA_E2, AN7583_I2C1_SDA_E2_MASK),
> >>>> -	PINCTRL_CONF_DESC(45, REG_I2C_SDA_E2, SPI_CLK_E2_MASK),
> >>>> -	PINCTRL_CONF_DESC(46, REG_I2C_SDA_E2, SPI_CS0_E2_MASK),
> >>>> -	PINCTRL_CONF_DESC(47, REG_I2C_SDA_E2, SPI_MOSI_E2_MASK),
> >>>> -	PINCTRL_CONF_DESC(48, REG_I2C_SDA_E2, SPI_MISO_E2_MASK),
> >>>> -	PINCTRL_CONF_DESC(49, REG_I2C_SDA_E2, UART1_TXD_E2_MASK),
> >>>> -	PINCTRL_CONF_DESC(50, REG_I2C_SDA_E2, UART1_RXD_E2_MASK),
> >>>> -	PINCTRL_CONF_DESC(51, REG_I2C_SDA_E2, PCIE0_RESET_E2_MASK),
> >>>> -	PINCTRL_CONF_DESC(52, REG_I2C_SDA_E2, PCIE1_RESET_E2_MASK),
> >>>> -	PINCTRL_CONF_DESC(53, REG_I2C_SDA_E2, AN7583_MDC_0_E2_MASK),
> >>>> -	PINCTRL_CONF_DESC(54, REG_I2C_SDA_E2, AN7583_MDIO_0_E2_MASK),
> >>>> -};
> >>>> -
> >>>> -static const struct airoha_pinctrl_conf en7581_pinctrl_drive_e4_conf[] = {
> >>>> -	PINCTRL_CONF_DESC(0, REG_I2C_SDA_E4, UART1_TXD_E4_MASK),
> >>>> -	PINCTRL_CONF_DESC(1, REG_I2C_SDA_E4, UART1_RXD_E4_MASK),
> >>>> -	PINCTRL_CONF_DESC(2, REG_I2C_SDA_E4, I2C_SDA_E4_MASK),
> >>>> -	PINCTRL_CONF_DESC(3, REG_I2C_SDA_E4, I2C_SCL_E4_MASK),
> >>>> -	PINCTRL_CONF_DESC(4, REG_I2C_SDA_E4, SPI_CS0_E4_MASK),
> >>>> -	PINCTRL_CONF_DESC(5, REG_I2C_SDA_E4, SPI_CLK_E4_MASK),
> >>>> -	PINCTRL_CONF_DESC(6, REG_I2C_SDA_E4, SPI_MOSI_E4_MASK),
> >>>> -	PINCTRL_CONF_DESC(7, REG_I2C_SDA_E4, SPI_MISO_E4_MASK),
> >>>> -	PINCTRL_CONF_DESC(13, REG_GPIO_L_E4, BIT(0)),
> >>>> -	PINCTRL_CONF_DESC(14, REG_GPIO_L_E4, BIT(1)),
> >>>> -	PINCTRL_CONF_DESC(15, REG_GPIO_L_E4, BIT(2)),
> >>>> -	PINCTRL_CONF_DESC(16, REG_GPIO_L_E4, BIT(3)),
> >>>> -	PINCTRL_CONF_DESC(17, REG_GPIO_L_E4, BIT(4)),
> >>>> -	PINCTRL_CONF_DESC(18, REG_GPIO_L_E4, BIT(5)),
> >>>> -	PINCTRL_CONF_DESC(19, REG_GPIO_L_E4, BIT(6)),
> >>>> -	PINCTRL_CONF_DESC(20, REG_GPIO_L_E4, BIT(7)),
> >>>> -	PINCTRL_CONF_DESC(21, REG_GPIO_L_E4, BIT(8)),
> >>>> -	PINCTRL_CONF_DESC(22, REG_GPIO_L_E4, BIT(9)),
> >>>> -	PINCTRL_CONF_DESC(23, REG_GPIO_L_E4, BIT(10)),
> >>>> -	PINCTRL_CONF_DESC(24, REG_GPIO_L_E4, BIT(11)),
> >>>> -	PINCTRL_CONF_DESC(25, REG_GPIO_L_E4, BIT(12)),
> >>>> -	PINCTRL_CONF_DESC(26, REG_GPIO_L_E4, BIT(13)),
> >>>> -	PINCTRL_CONF_DESC(27, REG_GPIO_L_E4, BIT(14)),
> >>>> -	PINCTRL_CONF_DESC(28, REG_GPIO_L_E4, BIT(15)),
> >>>> -	PINCTRL_CONF_DESC(29, REG_GPIO_L_E4, BIT(16)),
> >>>> -	PINCTRL_CONF_DESC(30, REG_GPIO_L_E4, BIT(17)),
> >>>> -	PINCTRL_CONF_DESC(31, REG_GPIO_L_E4, BIT(18)),
> >>>> -	PINCTRL_CONF_DESC(32, REG_GPIO_L_E4, BIT(19)),
> >>>> -	PINCTRL_CONF_DESC(33, REG_GPIO_L_E4, BIT(20)),
> >>>> -	PINCTRL_CONF_DESC(34, REG_GPIO_L_E4, BIT(21)),
> >>>> -	PINCTRL_CONF_DESC(35, REG_GPIO_L_E4, BIT(22)),
> >>>> -	PINCTRL_CONF_DESC(36, REG_GPIO_L_E4, BIT(23)),
> >>>> -	PINCTRL_CONF_DESC(37, REG_GPIO_L_E4, BIT(24)),
> >>>> -	PINCTRL_CONF_DESC(38, REG_GPIO_L_E4, BIT(25)),
> >>>> -	PINCTRL_CONF_DESC(39, REG_GPIO_L_E4, BIT(26)),
> >>>> -	PINCTRL_CONF_DESC(40, REG_GPIO_L_E4, BIT(27)),
> >>>> -	PINCTRL_CONF_DESC(41, REG_GPIO_L_E4, BIT(28)),
> >>>> -	PINCTRL_CONF_DESC(42, REG_GPIO_L_E4, BIT(29)),
> >>>> -	PINCTRL_CONF_DESC(43, REG_GPIO_L_E4, BIT(30)),
> >>>> -	PINCTRL_CONF_DESC(44, REG_GPIO_L_E4, BIT(31)),
> >>>> -	PINCTRL_CONF_DESC(45, REG_GPIO_H_E4, BIT(0)),
> >>>> -	PINCTRL_CONF_DESC(46, REG_GPIO_H_E4, BIT(1)),
> >>>> -	PINCTRL_CONF_DESC(47, REG_GPIO_H_E4, BIT(2)),
> >>>> -	PINCTRL_CONF_DESC(48, REG_GPIO_H_E4, BIT(3)),
> >>>> -	PINCTRL_CONF_DESC(49, REG_GPIO_H_E4, BIT(4)),
> >>>> -	PINCTRL_CONF_DESC(50, REG_GPIO_H_E4, BIT(5)),
> >>>> -	PINCTRL_CONF_DESC(51, REG_GPIO_H_E4, BIT(6)),
> >>>> -	PINCTRL_CONF_DESC(52, REG_GPIO_H_E4, BIT(7)),
> >>>> -	PINCTRL_CONF_DESC(53, REG_GPIO_H_E4, BIT(8)),
> >>>> -	PINCTRL_CONF_DESC(54, REG_GPIO_H_E4, BIT(9)),
> >>>> -	PINCTRL_CONF_DESC(55, REG_GPIO_H_E4, BIT(10)),
> >>>> -	PINCTRL_CONF_DESC(56, REG_GPIO_H_E4, BIT(11)),
> >>>> -	PINCTRL_CONF_DESC(57, REG_GPIO_H_E4, BIT(12)),
> >>>> -	PINCTRL_CONF_DESC(58, REG_GPIO_H_E4, BIT(13)),
> >>>> -	PINCTRL_CONF_DESC(59, REG_GPIO_H_E4, BIT(14)),
> >>>> -	PINCTRL_CONF_DESC(60, REG_I2C_SDA_E4, PCIE0_RESET_E4_MASK),
> >>>> -	PINCTRL_CONF_DESC(61, REG_I2C_SDA_E4, PCIE1_RESET_E4_MASK),
> >>>> -	PINCTRL_CONF_DESC(62, REG_I2C_SDA_E4, PCIE2_RESET_E4_MASK),
> >>>> -};
> >>>> -
> >>>> -static const struct airoha_pinctrl_conf an7583_pinctrl_drive_e4_conf[] = {
> >>>> -	PINCTRL_CONF_DESC(2, REG_GPIO_L_E4, BIT(0)),
> >>>> -	PINCTRL_CONF_DESC(3, REG_GPIO_L_E4, BIT(1)),
> >>>> -	PINCTRL_CONF_DESC(4, REG_GPIO_L_E4, BIT(2)),
> >>>> -	PINCTRL_CONF_DESC(5, REG_GPIO_L_E4, BIT(3)),
> >>>> -	PINCTRL_CONF_DESC(6, REG_GPIO_L_E4, BIT(4)),
> >>>> -	PINCTRL_CONF_DESC(7, REG_GPIO_L_E4, BIT(5)),
> >>>> -	PINCTRL_CONF_DESC(8, REG_GPIO_L_E4, BIT(6)),
> >>>> -	PINCTRL_CONF_DESC(9, REG_GPIO_L_E4, BIT(7)),
> >>>> -	PINCTRL_CONF_DESC(10, REG_GPIO_L_E4, BIT(8)),
> >>>> -	PINCTRL_CONF_DESC(11, REG_GPIO_L_E4, BIT(9)),
> >>>> -	PINCTRL_CONF_DESC(12, REG_GPIO_L_E4, BIT(10)),
> >>>> -	PINCTRL_CONF_DESC(13, REG_GPIO_L_E4, BIT(11)),
> >>>> -	PINCTRL_CONF_DESC(14, REG_GPIO_L_E4, BIT(12)),
> >>>> -	PINCTRL_CONF_DESC(15, REG_GPIO_L_E4, BIT(13)),
> >>>> -	PINCTRL_CONF_DESC(16, REG_GPIO_L_E4, BIT(14)),
> >>>> -	PINCTRL_CONF_DESC(17, REG_GPIO_L_E4, BIT(15)),
> >>>> -	PINCTRL_CONF_DESC(18, REG_GPIO_L_E4, BIT(16)),
> >>>> -	PINCTRL_CONF_DESC(19, REG_GPIO_L_E4, BIT(17)),
> >>>> -	PINCTRL_CONF_DESC(20, REG_GPIO_L_E4, BIT(18)),
> >>>> -	PINCTRL_CONF_DESC(21, REG_GPIO_L_E4, BIT(19)),
> >>>> -	PINCTRL_CONF_DESC(22, REG_GPIO_L_E4, BIT(20)),
> >>>> -	PINCTRL_CONF_DESC(23, REG_GPIO_L_E4, BIT(21)),
> >>>> -	PINCTRL_CONF_DESC(24, REG_GPIO_L_E4, BIT(22)),
> >>>> -	PINCTRL_CONF_DESC(25, REG_GPIO_L_E4, BIT(23)),
> >>>> -	PINCTRL_CONF_DESC(26, REG_GPIO_L_E4, BIT(24)),
> >>>> -	PINCTRL_CONF_DESC(27, REG_GPIO_L_E4, BIT(25)),
> >>>> -	PINCTRL_CONF_DESC(28, REG_GPIO_L_E4, BIT(26)),
> >>>> -	PINCTRL_CONF_DESC(29, REG_GPIO_L_E4, BIT(27)),
> >>>> -	PINCTRL_CONF_DESC(30, REG_GPIO_L_E4, BIT(28)),
> >>>> -	PINCTRL_CONF_DESC(31, REG_GPIO_L_E4, BIT(29)),
> >>>> -	PINCTRL_CONF_DESC(32, REG_GPIO_L_E4, BIT(30)),
> >>>> -	PINCTRL_CONF_DESC(33, REG_GPIO_L_E4, BIT(31)),
> >>>> -	PINCTRL_CONF_DESC(34, REG_GPIO_H_E4, BIT(0)),
> >>>> -	PINCTRL_CONF_DESC(35, REG_GPIO_H_E4, BIT(1)),
> >>>> -	PINCTRL_CONF_DESC(36, REG_GPIO_H_E4, BIT(2)),
> >>>> -	PINCTRL_CONF_DESC(37, REG_GPIO_H_E4, BIT(3)),
> >>>> -	PINCTRL_CONF_DESC(38, REG_GPIO_H_E4, BIT(4)),
> >>>> -	PINCTRL_CONF_DESC(39, REG_GPIO_H_E4, BIT(5)),
> >>>> -	PINCTRL_CONF_DESC(40, REG_GPIO_H_E4, BIT(6)),
> >>>> -	PINCTRL_CONF_DESC(41, REG_I2C_SDA_E4, I2C_SCL_E4_MASK),
> >>>> -	PINCTRL_CONF_DESC(42, REG_I2C_SDA_E4, I2C_SDA_E4_MASK),
> >>>> -	PINCTRL_CONF_DESC(43, REG_I2C_SDA_E4, AN7583_I2C1_SCL_E4_MASK),
> >>>> -	PINCTRL_CONF_DESC(44, REG_I2C_SDA_E4, AN7583_I2C1_SDA_E4_MASK),
> >>>> -	PINCTRL_CONF_DESC(45, REG_I2C_SDA_E4, SPI_CLK_E4_MASK),
> >>>> -	PINCTRL_CONF_DESC(46, REG_I2C_SDA_E4, SPI_CS0_E4_MASK),
> >>>> -	PINCTRL_CONF_DESC(47, REG_I2C_SDA_E4, SPI_MOSI_E4_MASK),
> >>>> -	PINCTRL_CONF_DESC(48, REG_I2C_SDA_E4, SPI_MISO_E4_MASK),
> >>>> -	PINCTRL_CONF_DESC(49, REG_I2C_SDA_E4, UART1_TXD_E4_MASK),
> >>>> -	PINCTRL_CONF_DESC(50, REG_I2C_SDA_E4, UART1_RXD_E4_MASK),
> >>>> -	PINCTRL_CONF_DESC(51, REG_I2C_SDA_E4, PCIE0_RESET_E4_MASK),
> >>>> -	PINCTRL_CONF_DESC(52, REG_I2C_SDA_E4, PCIE1_RESET_E4_MASK),
> >>>> -	PINCTRL_CONF_DESC(53, REG_I2C_SDA_E4, AN7583_MDC_0_E4_MASK),
> >>>> -	PINCTRL_CONF_DESC(54, REG_I2C_SDA_E4, AN7583_MDIO_0_E4_MASK),
> >>>> -};
> >>>> -
> >>>> -static const struct airoha_pinctrl_conf en7581_pinctrl_pcie_rst_od_conf[] = {
> >>>> -	PINCTRL_CONF_DESC(60, REG_PCIE_RESET_OD, PCIE0_RESET_OD_MASK),
> >>>> -	PINCTRL_CONF_DESC(61, REG_PCIE_RESET_OD, PCIE1_RESET_OD_MASK),
> >>>> -	PINCTRL_CONF_DESC(62, REG_PCIE_RESET_OD, PCIE2_RESET_OD_MASK),
> >>>> -};
> >>>> -
> >>>> -static const struct airoha_pinctrl_conf an7583_pinctrl_pcie_rst_od_conf[] = {
> >>>> -	PINCTRL_CONF_DESC(51, REG_PCIE_RESET_OD, PCIE0_RESET_OD_MASK),
> >>>> -	PINCTRL_CONF_DESC(52, REG_PCIE_RESET_OD, PCIE1_RESET_OD_MASK),
> >>>> -};
> >>>> -
> >>>>  static int airoha_convert_pin_to_reg_offset(struct pinctrl_dev *pctrl_dev,
> >>>>  					    struct pinctrl_gpio_range *range,
> >>>>  					    int pin)
> >>>> @@ -2606,6 +318,7 @@ static int airoha_pinctrl_add_gpiochip(struct airoha_pinctrl *pinctrl,
> >>>>  					struct platform_device *pdev)
> >>>>  {
> >>>>  	struct airoha_pinctrl_gpiochip *chip = &pinctrl->gpiochip;
> >>>> +	struct irq_chip *irq_chip = &pinctrl->gpio_irq_chip;
> >>>>  	struct gpio_chip *gc = &chip->chip;
> >>>>  	struct gpio_irq_chip *girq = &gc->irq;
> >>>>  	struct device *dev = &pdev->dev;
> >>>> @@ -2630,9 +343,11 @@ static int airoha_pinctrl_add_gpiochip(struct airoha_pinctrl *pinctrl,
> >>>>  	gc->base = -1;
> >>>>  	gc->ngpio = AIROHA_NUM_PINS;
> >>>>  
> >>>> +	memcpy(irq_chip, &airoha_gpio_irq_chip, sizeof(struct irq_chip));
> >>>> +
> >>>>  	girq->default_type = IRQ_TYPE_NONE;
> >>>>  	girq->handler = handle_bad_irq;
> >>>> -	gpio_irq_chip_set_chip(girq, &airoha_gpio_irq_chip);
> >>>> +	gpio_irq_chip_set_chip(girq, irq_chip);
> >>>>  
> >>>>  	irq = platform_get_irq(pdev, 0);
> >>>>  	if (irq < 0)
> >>>> @@ -3011,7 +726,7 @@ static const struct pinctrl_ops airoha_pctlops = {
> >>>>  	.dt_free_map = pinconf_generic_dt_free_map,
> >>>>  };
> >>>>  
> >>>> -static int airoha_pinctrl_probe(struct platform_device *pdev)
> >>>> +int airoha_pinctrl_probe(struct platform_device *pdev)
> >>>>  {
> >>>>  	const struct airoha_pinctrl_match_data *data;
> >>>>  	struct device *dev = &pdev->dev;
> >>>> @@ -3020,6 +735,8 @@ static int airoha_pinctrl_probe(struct platform_device *pdev)
> >>>>  	int err, i;
> >>>>  
> >>>>  	data = device_get_match_data(dev);
> >>>> +	if (!data)
> >>>> +		return -EINVAL;
> >>>>  
> >>>>  	pinctrl = devm_kzalloc(dev, sizeof(*pinctrl), GFP_KERNEL);
> >>>>  	if (!pinctrl)
> >>>> @@ -3036,8 +753,8 @@ static int airoha_pinctrl_probe(struct platform_device *pdev)
> >>>>  	pinctrl->chip_scu = map;
> >>>>  
> >>>>  	/* Init pinctrl desc struct */
> >>>> -	pinctrl->desc.name = KBUILD_MODNAME;
> >>>> -	pinctrl->desc.owner = THIS_MODULE;
> >>>> +	pinctrl->desc.name = data->pinctrl_name;
> >>>> +	pinctrl->desc.owner = data->pinctrl_owner;
> >>>>  	pinctrl->desc.pctlops = &airoha_pctlops;
> >>>>  	pinctrl->desc.pmxops = &airoha_pmxops;
> >>>>  	pinctrl->desc.confops = &airoha_confops;
> >>>> @@ -3089,87 +806,10 @@ static int airoha_pinctrl_probe(struct platform_device *pdev)
> >>>>  	/* build gpio-chip */
> >>>>  	return airoha_pinctrl_add_gpiochip(pinctrl, pdev);
> >>>>  }
> >>>> -
> >>>> -static const struct airoha_pinctrl_match_data en7581_pinctrl_match_data = {
> >>>> -	.pins = en7581_pinctrl_pins,
> >>>> -	.num_pins = ARRAY_SIZE(en7581_pinctrl_pins),
> >>>> -	.grps = en7581_pinctrl_groups,
> >>>> -	.num_grps = ARRAY_SIZE(en7581_pinctrl_groups),
> >>>> -	.funcs = en7581_pinctrl_funcs,
> >>>> -	.num_funcs = ARRAY_SIZE(en7581_pinctrl_funcs),
> >>>> -	.confs_info = {
> >>>> -		[AIROHA_PINCTRL_CONFS_PULLUP] = {
> >>>> -			.confs = en7581_pinctrl_pullup_conf,
> >>>> -			.num_confs = ARRAY_SIZE(en7581_pinctrl_pullup_conf),
> >>>> -		},
> >>>> -		[AIROHA_PINCTRL_CONFS_PULLDOWN] = {
> >>>> -			.confs = en7581_pinctrl_pulldown_conf,
> >>>> -			.num_confs = ARRAY_SIZE(en7581_pinctrl_pulldown_conf),
> >>>> -		},
> >>>> -		[AIROHA_PINCTRL_CONFS_DRIVE_E2] = {
> >>>> -			.confs = en7581_pinctrl_drive_e2_conf,
> >>>> -			.num_confs = ARRAY_SIZE(en7581_pinctrl_drive_e2_conf),
> >>>> -		},
> >>>> -		[AIROHA_PINCTRL_CONFS_DRIVE_E4] = {
> >>>> -			.confs = en7581_pinctrl_drive_e4_conf,
> >>>> -			.num_confs = ARRAY_SIZE(en7581_pinctrl_drive_e4_conf),
> >>>> -		},
> >>>> -		[AIROHA_PINCTRL_CONFS_PCIE_RST_OD] = {
> >>>> -			.confs = en7581_pinctrl_pcie_rst_od_conf,
> >>>> -			.num_confs = ARRAY_SIZE(en7581_pinctrl_pcie_rst_od_conf),
> >>>> -		},
> >>>> -	},
> >>>> -};
> >>>> -
> >>>> -static const struct airoha_pinctrl_match_data an7583_pinctrl_match_data = {
> >>>> -	.pins = an7583_pinctrl_pins,
> >>>> -	.num_pins = ARRAY_SIZE(an7583_pinctrl_pins),
> >>>> -	.grps = an7583_pinctrl_groups,
> >>>> -	.num_grps = ARRAY_SIZE(an7583_pinctrl_groups),
> >>>> -	.funcs = an7583_pinctrl_funcs,
> >>>> -	.num_funcs = ARRAY_SIZE(an7583_pinctrl_funcs),
> >>>> -	.confs_info = {
> >>>> -		[AIROHA_PINCTRL_CONFS_PULLUP] = {
> >>>> -			.confs = an7583_pinctrl_pullup_conf,
> >>>> -			.num_confs = ARRAY_SIZE(an7583_pinctrl_pullup_conf),
> >>>> -		},
> >>>> -		[AIROHA_PINCTRL_CONFS_PULLDOWN] = {
> >>>> -			.confs = an7583_pinctrl_pulldown_conf,
> >>>> -			.num_confs = ARRAY_SIZE(an7583_pinctrl_pulldown_conf),
> >>>> -		},
> >>>> -		[AIROHA_PINCTRL_CONFS_DRIVE_E2] = {
> >>>> -			.confs = an7583_pinctrl_drive_e2_conf,
> >>>> -			.num_confs = ARRAY_SIZE(an7583_pinctrl_drive_e2_conf),
> >>>> -		},
> >>>> -		[AIROHA_PINCTRL_CONFS_DRIVE_E4] = {
> >>>> -			.confs = an7583_pinctrl_drive_e4_conf,
> >>>> -			.num_confs = ARRAY_SIZE(an7583_pinctrl_drive_e4_conf),
> >>>> -		},
> >>>> -		[AIROHA_PINCTRL_CONFS_PCIE_RST_OD] = {
> >>>> -			.confs = an7583_pinctrl_pcie_rst_od_conf,
> >>>> -			.num_confs = ARRAY_SIZE(an7583_pinctrl_pcie_rst_od_conf),
> >>>> -		},
> >>>> -	},
> >>>> -};
> >>>> -
> >>>> -static const struct of_device_id airoha_pinctrl_of_match[] = {
> >>>> -	{ .compatible = "airoha,en7581-pinctrl", .data = &en7581_pinctrl_match_data },
> >>>> -	{ .compatible = "airoha,an7583-pinctrl", .data = &an7583_pinctrl_match_data },
> >>>> -	{ /* sentinel */ }
> >>>> -};
> >>>> -MODULE_DEVICE_TABLE(of, airoha_pinctrl_of_match);
> >>>> -
> >>>> -static struct platform_driver airoha_pinctrl_driver = {
> >>>> -	.probe = airoha_pinctrl_probe,
> >>>> -	.driver = {
> >>>> -		.name = "pinctrl-airoha",
> >>>> -		.of_match_table = airoha_pinctrl_of_match,
> >>>> -	},
> >>>> -};
> >>>> -module_platform_driver(airoha_pinctrl_driver);
> >>>> +EXPORT_SYMBOL_GPL(airoha_pinctrl_probe);
> >>>>  
> >>>>  MODULE_LICENSE("GPL");
> >>>>  MODULE_AUTHOR("Lorenzo Bianconi <lorenzo@kernel.org>");
> >>>>  MODULE_AUTHOR("Benjamin Larsson <benjamin.larsson@genexis.eu>");
> >>>>  MODULE_AUTHOR("Markus Gothe <markus.gothe@genexis.eu>");
> >>>> -MODULE_DESCRIPTION("Pinctrl driver for Airoha SoC");
> >>>> +MODULE_DESCRIPTION("Pinctrl common driver for Airoha SoC");
> >>>> diff --git a/drivers/pinctrl/airoha/pinctrl-an7581.c b/drivers/pinctrl/airoha/pinctrl-an7581.c
> >>>> new file mode 100644
> >>>> index 0000000000000..522b35bbaa121
> >>>> --- /dev/null
> >>>> +++ b/drivers/pinctrl/airoha/pinctrl-an7581.c
> >>>> @@ -0,0 +1,1486 @@
> >>>> +// SPDX-License-Identifier: GPL-2.0-only
> >>>> +/*
> >>>> + * Author: Lorenzo Bianconi <lorenzo@kernel.org>
> >>>> + * Author: Benjamin Larsson <benjamin.larsson@genexis.eu>
> >>>> + * Author: Markus Gothe <markus.gothe@genexis.eu>
> >>>> + */
> >>>> +
> >>>> +#include "airoha-common.h"
> >>>> +
> >>>> +/* MUX */
> >>>> +#define REG_GPIO_2ND_I2C_MODE			0x0214
> >>>> +#define GPIO_MDC_IO_MASTER_MODE_MASK		BIT(14)
> >>>> +#define GPIO_I2C_MASTER_MODE_MODE		BIT(13)
> >>>> +#define GPIO_I2S_MODE_MASK			BIT(12)
> >>>> +#define GPIO_I2C_SLAVE_MODE_MODE		BIT(11)
> >>>> +#define GPIO_LAN3_LED1_MODE_MASK		BIT(10)
> >>>> +#define GPIO_LAN3_LED0_MODE_MASK		BIT(9)
> >>>> +#define GPIO_LAN2_LED1_MODE_MASK		BIT(8)
> >>>> +#define GPIO_LAN2_LED0_MODE_MASK		BIT(7)
> >>>> +#define GPIO_LAN1_LED1_MODE_MASK		BIT(6)
> >>>> +#define GPIO_LAN1_LED0_MODE_MASK		BIT(5)
> >>>> +#define GPIO_LAN0_LED1_MODE_MASK		BIT(4)
> >>>> +#define GPIO_LAN0_LED0_MODE_MASK		BIT(3)
> >>>> +#define PON_TOD_1PPS_MODE_MASK			BIT(2)
> >>>> +#define GSW_TOD_1PPS_MODE_MASK			BIT(1)
> >>>> +#define GPIO_2ND_I2C_MODE_MASK			BIT(0)
> >>>> +
> >>>> +#define REG_GPIO_SPI_CS1_MODE			0x0218
> >>>> +#define GPIO_PCM_SPI_CS4_MODE_MASK		BIT(21)
> >>>> +#define GPIO_PCM_SPI_CS3_MODE_MASK		BIT(20)
> >>>> +#define GPIO_PCM_SPI_CS2_MODE_P156_MASK		BIT(19)
> >>>> +#define GPIO_PCM_SPI_CS2_MODE_P128_MASK		BIT(18)
> >>>> +#define GPIO_PCM_SPI_CS1_MODE_MASK		BIT(17)
> >>>> +#define GPIO_PCM_SPI_MODE_MASK			BIT(16)
> >>>> +#define GPIO_PCM2_MODE_MASK			BIT(13)
> >>>> +#define GPIO_PCM1_MODE_MASK			BIT(12)
> >>>> +#define GPIO_PCM_INT_MODE_MASK			BIT(9)
> >>>> +#define GPIO_PCM_RESET_MODE_MASK		BIT(8)
> >>>> +#define GPIO_SPI_QUAD_MODE_MASK			BIT(4)
> >>>> +#define GPIO_SPI_CS4_MODE_MASK			BIT(3)
> >>>> +#define GPIO_SPI_CS3_MODE_MASK			BIT(2)
> >>>> +#define GPIO_SPI_CS2_MODE_MASK			BIT(1)
> >>>> +#define GPIO_SPI_CS1_MODE_MASK			BIT(0)
> >>>> +
> >>>> +#define REG_GPIO_PON_MODE			0x021c
> >>>> +#define GPIO_PARALLEL_NAND_MODE_MASK		BIT(14)
> >>>> +#define GPIO_SGMII_MDIO_MODE_MASK		BIT(13)
> >>>> +#define GPIO_PCIE_RESET2_MASK			BIT(12)
> >>>> +#define SIPO_RCLK_MODE_MASK			BIT(11)
> >>>> +#define GPIO_PCIE_RESET1_MASK			BIT(10)
> >>>> +#define GPIO_PCIE_RESET0_MASK			BIT(9)
> >>>> +#define GPIO_UART5_MODE_MASK			BIT(8)
> >>>> +#define GPIO_UART4_MODE_MASK			BIT(7)
> >>>> +#define GPIO_HSUART_CTS_RTS_MODE_MASK		BIT(6)
> >>>> +#define GPIO_HSUART_MODE_MASK			BIT(5)
> >>>> +#define GPIO_UART2_CTS_RTS_MODE_MASK		BIT(4)
> >>>> +#define GPIO_UART2_MODE_MASK			BIT(3)
> >>>> +#define GPIO_SIPO_MODE_MASK			BIT(2)
> >>>> +#define GPIO_EMMC_MODE_MASK			BIT(1)
> >>>> +#define GPIO_PON_MODE_MASK			BIT(0)
> >>>> +
> >>>> +#define REG_NPU_UART_EN				0x0224
> >>>> +#define JTAG_UDI_EN_MASK			BIT(4)
> >>>> +#define JTAG_DFD_EN_MASK			BIT(3)
> >>>> +
> >>>> +#define REG_FORCE_GPIO_EN			0x0228
> >>>> +#define FORCE_GPIO_EN(n)			BIT(n)
> >>>> +
> >>>> +/* LED MAP */
> >>>> +#define REG_LAN_LED0_MAPPING			0x027c
> >>>> +#define REG_LAN_LED1_MAPPING			0x0280
> >>>> +
> >>>> +#define LAN4_LED_MAPPING_MASK			GENMASK(18, 16)
> >>>> +#define LAN4_PHY_LED_MAP(_n)			FIELD_PREP_CONST(LAN4_LED_MAPPING_MASK, (_n))
> >>>> +
> >>>> +#define LAN3_LED_MAPPING_MASK			GENMASK(14, 12)
> >>>> +#define LAN3_PHY_LED_MAP(_n)			FIELD_PREP_CONST(LAN3_LED_MAPPING_MASK, (_n))
> >>>> +
> >>>> +#define LAN2_LED_MAPPING_MASK			GENMASK(10, 8)
> >>>> +#define LAN2_PHY_LED_MAP(_n)			FIELD_PREP_CONST(LAN2_LED_MAPPING_MASK, (_n))
> >>>> +
> >>>> +#define LAN1_LED_MAPPING_MASK			GENMASK(6, 4)
> >>>> +#define LAN1_PHY_LED_MAP(_n)			FIELD_PREP_CONST(LAN1_LED_MAPPING_MASK, (_n))
> >>>> +
> >>>> +#define LAN0_LED_MAPPING_MASK			GENMASK(2, 0)
> >>>> +#define LAN0_PHY_LED_MAP(_n)			FIELD_PREP_CONST(LAN0_LED_MAPPING_MASK, (_n))
> >>>> +
> >>>> +/* CONF */
> >>>> +#define REG_I2C_SDA_E2				0x001c
> >>>> +#define SPI_MISO_E2_MASK			BIT(14)
> >>>> +#define SPI_MOSI_E2_MASK			BIT(13)
> >>>> +#define SPI_CLK_E2_MASK				BIT(12)
> >>>> +#define SPI_CS0_E2_MASK				BIT(11)
> >>>> +#define PCIE2_RESET_E2_MASK			BIT(10)
> >>>> +#define PCIE1_RESET_E2_MASK			BIT(9)
> >>>> +#define PCIE0_RESET_E2_MASK			BIT(8)
> >>>> +#define UART1_RXD_E2_MASK			BIT(3)
> >>>> +#define UART1_TXD_E2_MASK			BIT(2)
> >>>> +#define I2C_SCL_E2_MASK				BIT(1)
> >>>> +#define I2C_SDA_E2_MASK				BIT(0)
> >>>> +
> >>>> +#define REG_I2C_SDA_E4				0x0020
> >>>> +#define SPI_MISO_E4_MASK			BIT(14)
> >>>> +#define SPI_MOSI_E4_MASK			BIT(13)
> >>>> +#define SPI_CLK_E4_MASK				BIT(12)
> >>>> +#define SPI_CS0_E4_MASK				BIT(11)
> >>>> +#define PCIE2_RESET_E4_MASK			BIT(10)
> >>>> +#define PCIE1_RESET_E4_MASK			BIT(9)
> >>>> +#define PCIE0_RESET_E4_MASK			BIT(8)
> >>>> +#define UART1_RXD_E4_MASK			BIT(3)
> >>>> +#define UART1_TXD_E4_MASK			BIT(2)
> >>>> +#define I2C_SCL_E4_MASK				BIT(1)
> >>>> +#define I2C_SDA_E4_MASK				BIT(0)
> >>>> +
> >>>> +#define REG_GPIO_L_E2				0x0024
> >>>> +#define REG_GPIO_L_E4				0x0028
> >>>> +#define REG_GPIO_H_E2				0x002c
> >>>> +#define REG_GPIO_H_E4				0x0030
> >>>> +
> >>>> +#define REG_I2C_SDA_PU				0x0044
> >>>> +#define SPI_MISO_PU_MASK			BIT(14)
> >>>> +#define SPI_MOSI_PU_MASK			BIT(13)
> >>>> +#define SPI_CLK_PU_MASK				BIT(12)
> >>>> +#define SPI_CS0_PU_MASK				BIT(11)
> >>>> +#define PCIE2_RESET_PU_MASK			BIT(10)
> >>>> +#define PCIE1_RESET_PU_MASK			BIT(9)
> >>>> +#define PCIE0_RESET_PU_MASK			BIT(8)
> >>>> +#define UART1_RXD_PU_MASK			BIT(3)
> >>>> +#define UART1_TXD_PU_MASK			BIT(2)
> >>>> +#define I2C_SCL_PU_MASK				BIT(1)
> >>>> +#define I2C_SDA_PU_MASK				BIT(0)
> >>>> +
> >>>> +#define REG_I2C_SDA_PD				0x0048
> >>>> +#define SPI_MISO_PD_MASK			BIT(14)
> >>>> +#define SPI_MOSI_PD_MASK			BIT(13)
> >>>> +#define SPI_CLK_PD_MASK				BIT(12)
> >>>> +#define SPI_CS0_PD_MASK				BIT(11)
> >>>> +#define PCIE2_RESET_PD_MASK			BIT(10)
> >>>> +#define PCIE1_RESET_PD_MASK			BIT(9)
> >>>> +#define PCIE0_RESET_PD_MASK			BIT(8)
> >>>> +#define UART1_RXD_PD_MASK			BIT(3)
> >>>> +#define UART1_TXD_PD_MASK			BIT(2)
> >>>> +#define I2C_SCL_PD_MASK				BIT(1)
> >>>> +#define I2C_SDA_PD_MASK				BIT(0)
> >>>> +
> >>>> +#define REG_GPIO_L_PU				0x004c
> >>>> +#define REG_GPIO_L_PD				0x0050
> >>>> +#define REG_GPIO_H_PU				0x0054
> >>>> +#define REG_GPIO_H_PD				0x0058
> >>>> +
> >>>> +#define REG_PCIE_RESET_OD			0x018c
> >>>> +#define PCIE2_RESET_OD_MASK			BIT(2)
> >>>> +#define PCIE1_RESET_OD_MASK			BIT(1)
> >>>> +#define PCIE0_RESET_OD_MASK			BIT(0)
> >>>> +
> >>>> +/* PWM MODE CONF */
> >>>> +#define REG_GPIO_FLASH_MODE_CFG			0x0034
> >>>> +#define GPIO15_FLASH_MODE_CFG			BIT(15)
> >>>> +#define GPIO14_FLASH_MODE_CFG			BIT(14)
> >>>> +#define GPIO13_FLASH_MODE_CFG			BIT(13)
> >>>> +#define GPIO12_FLASH_MODE_CFG			BIT(12)
> >>>> +#define GPIO11_FLASH_MODE_CFG			BIT(11)
> >>>> +#define GPIO10_FLASH_MODE_CFG			BIT(10)
> >>>> +#define GPIO9_FLASH_MODE_CFG			BIT(9)
> >>>> +#define GPIO8_FLASH_MODE_CFG			BIT(8)
> >>>> +#define GPIO7_FLASH_MODE_CFG			BIT(7)
> >>>> +#define GPIO6_FLASH_MODE_CFG			BIT(6)
> >>>> +#define GPIO5_FLASH_MODE_CFG			BIT(5)
> >>>> +#define GPIO4_FLASH_MODE_CFG			BIT(4)
> >>>> +#define GPIO3_FLASH_MODE_CFG			BIT(3)
> >>>> +#define GPIO2_FLASH_MODE_CFG			BIT(2)
> >>>> +#define GPIO1_FLASH_MODE_CFG			BIT(1)
> >>>> +#define GPIO0_FLASH_MODE_CFG			BIT(0)
> >>>> +
> >>>> +/* PWM MODE CONF EXT */
> >>>> +#define REG_GPIO_FLASH_MODE_CFG_EXT		0x0068
> >>>> +#define GPIO51_FLASH_MODE_CFG			BIT(31)
> >>>> +#define GPIO50_FLASH_MODE_CFG			BIT(30)
> >>>> +#define GPIO49_FLASH_MODE_CFG			BIT(29)
> >>>> +#define GPIO48_FLASH_MODE_CFG			BIT(28)
> >>>> +#define GPIO47_FLASH_MODE_CFG			BIT(27)
> >>>> +#define GPIO46_FLASH_MODE_CFG			BIT(26)
> >>>> +#define GPIO45_FLASH_MODE_CFG			BIT(25)
> >>>> +#define GPIO44_FLASH_MODE_CFG			BIT(24)
> >>>> +#define GPIO43_FLASH_MODE_CFG			BIT(23)
> >>>> +#define GPIO42_FLASH_MODE_CFG			BIT(22)
> >>>> +#define GPIO41_FLASH_MODE_CFG			BIT(21)
> >>>> +#define GPIO40_FLASH_MODE_CFG			BIT(20)
> >>>> +#define GPIO39_FLASH_MODE_CFG			BIT(19)
> >>>> +#define GPIO38_FLASH_MODE_CFG			BIT(18)
> >>>> +#define GPIO37_FLASH_MODE_CFG			BIT(17)
> >>>> +#define GPIO36_FLASH_MODE_CFG			BIT(16)
> >>>> +#define GPIO31_FLASH_MODE_CFG			BIT(15)
> >>>> +#define GPIO30_FLASH_MODE_CFG			BIT(14)
> >>>> +#define GPIO29_FLASH_MODE_CFG			BIT(13)
> >>>> +#define GPIO28_FLASH_MODE_CFG			BIT(12)
> >>>> +#define GPIO27_FLASH_MODE_CFG			BIT(11)
> >>>> +#define GPIO26_FLASH_MODE_CFG			BIT(10)
> >>>> +#define GPIO25_FLASH_MODE_CFG			BIT(9)
> >>>> +#define GPIO24_FLASH_MODE_CFG			BIT(8)
> >>>> +#define GPIO23_FLASH_MODE_CFG			BIT(7)
> >>>> +#define GPIO22_FLASH_MODE_CFG			BIT(6)
> >>>> +#define GPIO21_FLASH_MODE_CFG			BIT(5)
> >>>> +#define GPIO20_FLASH_MODE_CFG			BIT(4)
> >>>> +#define GPIO19_FLASH_MODE_CFG			BIT(3)
> >>>> +#define GPIO18_FLASH_MODE_CFG			BIT(2)
> >>>> +#define GPIO17_FLASH_MODE_CFG			BIT(1)
> >>>> +#define GPIO16_FLASH_MODE_CFG			BIT(0)
> >>>> +
> >>>> +#define AIROHA_PINCTRL_GPIO(gpio, mux_val)			\
> >>>> +	{							\
> >>>> +		.name = (gpio),					\
> >>>> +		.regmap[0] = {					\
> >>>> +			AIROHA_FUNC_MUX,			\
> >>>> +			REG_GPIO_PON_MODE,			\
> >>>> +			(mux_val),				\
> >>>> +			(mux_val)				\
> >>>> +		},						\
> >>>> +		.regmap_size = 1,				\
> >>>> +	}
> >>>> +
> >>>> +#define AIROHA_PINCTRL_GPIO_EXT(gpio, mux_val, smux_val)	\
> >>>> +	{							\
> >>>> +		.name = (gpio),					\
> >>>> +		.regmap[0] = {					\
> >>>> +			AIROHA_FUNC_PWM_EXT_MUX,		\
> >>>> +			REG_GPIO_FLASH_MODE_CFG_EXT,		\
> >>>> +			(mux_val),				\
> >>>> +			0					\
> >>>> +		},						\
> >>>> +		.regmap[1] = {					\
> >>>> +			AIROHA_FUNC_MUX,			\
> >>>> +			REG_GPIO_PON_MODE,			\
> >>>> +			(smux_val),				\
> >>>> +			(smux_val)				\
> >>>> +		},						\
> >>>> +		.regmap_size = 2,				\
> >>>> +	}
> >>>> +
> >>>> +/* PWM */
> >>>> +#define AIROHA_PINCTRL_PWM(gpio, mux_val)			\
> >>>> +	{							\
> >>>> +		.name = (gpio),					\
> >>>> +		.regmap[0] = {					\
> >>>> +			AIROHA_FUNC_PWM_MUX,			\
> >>>> +			REG_GPIO_FLASH_MODE_CFG,		\
> >>>> +			(mux_val),				\
> >>>> +			(mux_val)				\
> >>>> +		},						\
> >>>> +		.regmap_size = 1,				\
> >>>> +	}
> >>>> +
> >>>> +#define AIROHA_PINCTRL_PWM_EXT(gpio, mux_val)			\
> >>>> +	{							\
> >>>> +		.name = (gpio),					\
> >>>> +		.regmap[0] = {					\
> >>>> +			AIROHA_FUNC_PWM_EXT_MUX,		\
> >>>> +			REG_GPIO_FLASH_MODE_CFG_EXT,		\
> >>>> +			(mux_val),				\
> >>>> +			(mux_val)				\
> >>>> +		},						\
> >>>> +		.regmap_size = 1,				\
> >>>> +	}
> >>>> +
> >>>> +#define AIROHA_PINCTRL_PWM_EXT_SEC(gpio, mux_val, smux_val)	\
> >>>> +	{							\
> >>>> +		.name = (gpio),					\
> >>>> +		.regmap[0] = {					\
> >>>> +			AIROHA_FUNC_PWM_EXT_MUX,		\
> >>>> +			REG_GPIO_FLASH_MODE_CFG_EXT,		\
> >>>> +			(mux_val),				\
> >>>> +			(mux_val)				\
> >>>> +		},						\
> >>>> +		.regmap[1] = {					\
> >>>> +			AIROHA_FUNC_MUX,			\
> >>>> +			REG_GPIO_PON_MODE,			\
> >>>> +			(smux_val),				\
> >>>> +			(smux_val)				\
> >>>> +		},						\
> >>>> +		.regmap_size = 2,				\
> >>>> +	}
> >>>> +
> >>>> +#define AIROHA_PINCTRL_PHY_LED0(gpio, mux_val, map_mask, map_val)	\
> >>>> +	{								\
> >>>> +		.name = (gpio),						\
> >>>> +		.regmap[0] = {						\
> >>>> +			AIROHA_FUNC_MUX,				\
> >>>> +			REG_GPIO_2ND_I2C_MODE,				\
> >>>> +			(mux_val),					\
> >>>> +			(mux_val),					\
> >>>> +		},							\
> >>>> +		.regmap[1] = {						\
> >>>> +			AIROHA_FUNC_MUX,				\
> >>>> +			REG_LAN_LED0_MAPPING,				\
> >>>> +			(map_mask),					\
> >>>> +			(map_val),					\
> >>>> +		},							\
> >>>> +		.regmap_size = 2,					\
> >>>> +	}
> >>>> +
> >>>> +#define AIROHA_PINCTRL_PHY_LED1(gpio, mux_val, map_mask, map_val)	\
> >>>> +	{								\
> >>>> +		.name = (gpio),						\
> >>>> +		.regmap[0] = {						\
> >>>> +			AIROHA_FUNC_MUX,				\
> >>>> +			REG_GPIO_2ND_I2C_MODE,				\
> >>>> +			(mux_val),					\
> >>>> +			(mux_val),					\
> >>>> +		},							\
> >>>> +		.regmap[1] = {						\
> >>>> +			AIROHA_FUNC_MUX,				\
> >>>> +			REG_LAN_LED1_MAPPING,				\
> >>>> +			(map_mask),					\
> >>>> +			(map_val),					\
> >>>> +		},							\
> >>>> +		.regmap_size = 2,					\
> >>>> +	}
> >>>> +
> >>>> +static struct pinctrl_pin_desc en7581_pinctrl_pins[] = {
> >>>> +	PINCTRL_PIN(0, "uart1_txd"),
> >>>> +	PINCTRL_PIN(1, "uart1_rxd"),
> >>>> +	PINCTRL_PIN(2, "i2c_scl"),
> >>>> +	PINCTRL_PIN(3, "i2c_sda"),
> >>>> +	PINCTRL_PIN(4, "spi_cs0"),
> >>>> +	PINCTRL_PIN(5, "spi_clk"),
> >>>> +	PINCTRL_PIN(6, "spi_mosi"),
> >>>> +	PINCTRL_PIN(7, "spi_miso"),
> >>>> +	PINCTRL_PIN(13, "gpio0"),
> >>>> +	PINCTRL_PIN(14, "gpio1"),
> >>>> +	PINCTRL_PIN(15, "gpio2"),
> >>>> +	PINCTRL_PIN(16, "gpio3"),
> >>>> +	PINCTRL_PIN(17, "gpio4"),
> >>>> +	PINCTRL_PIN(18, "gpio5"),
> >>>> +	PINCTRL_PIN(19, "gpio6"),
> >>>> +	PINCTRL_PIN(20, "gpio7"),
> >>>> +	PINCTRL_PIN(21, "gpio8"),
> >>>> +	PINCTRL_PIN(22, "gpio9"),
> >>>> +	PINCTRL_PIN(23, "gpio10"),
> >>>> +	PINCTRL_PIN(24, "gpio11"),
> >>>> +	PINCTRL_PIN(25, "gpio12"),
> >>>> +	PINCTRL_PIN(26, "gpio13"),
> >>>> +	PINCTRL_PIN(27, "gpio14"),
> >>>> +	PINCTRL_PIN(28, "gpio15"),
> >>>> +	PINCTRL_PIN(29, "gpio16"),
> >>>> +	PINCTRL_PIN(30, "gpio17"),
> >>>> +	PINCTRL_PIN(31, "gpio18"),
> >>>> +	PINCTRL_PIN(32, "gpio19"),
> >>>> +	PINCTRL_PIN(33, "gpio20"),
> >>>> +	PINCTRL_PIN(34, "gpio21"),
> >>>> +	PINCTRL_PIN(35, "gpio22"),
> >>>> +	PINCTRL_PIN(36, "gpio23"),
> >>>> +	PINCTRL_PIN(37, "gpio24"),
> >>>> +	PINCTRL_PIN(38, "gpio25"),
> >>>> +	PINCTRL_PIN(39, "gpio26"),
> >>>> +	PINCTRL_PIN(40, "gpio27"),
> >>>> +	PINCTRL_PIN(41, "gpio28"),
> >>>> +	PINCTRL_PIN(42, "gpio29"),
> >>>> +	PINCTRL_PIN(43, "gpio30"),
> >>>> +	PINCTRL_PIN(44, "gpio31"),
> >>>> +	PINCTRL_PIN(45, "gpio32"),
> >>>> +	PINCTRL_PIN(46, "gpio33"),
> >>>> +	PINCTRL_PIN(47, "gpio34"),
> >>>> +	PINCTRL_PIN(48, "gpio35"),
> >>>> +	PINCTRL_PIN(49, "gpio36"),
> >>>> +	PINCTRL_PIN(50, "gpio37"),
> >>>> +	PINCTRL_PIN(51, "gpio38"),
> >>>> +	PINCTRL_PIN(52, "gpio39"),
> >>>> +	PINCTRL_PIN(53, "gpio40"),
> >>>> +	PINCTRL_PIN(54, "gpio41"),
> >>>> +	PINCTRL_PIN(55, "gpio42"),
> >>>> +	PINCTRL_PIN(56, "gpio43"),
> >>>> +	PINCTRL_PIN(57, "gpio44"),
> >>>> +	PINCTRL_PIN(58, "gpio45"),
> >>>> +	PINCTRL_PIN(59, "gpio46"),
> >>>> +	PINCTRL_PIN(60, "pcie_reset0"),
> >>>> +	PINCTRL_PIN(61, "pcie_reset1"),
> >>>> +	PINCTRL_PIN(62, "pcie_reset2"),
> >>>> +};
> >>>> +
> >>>> +static const int en7581_pon_pins[] = { 49, 50, 51, 52, 53, 54 };
> >>>> +static const int en7581_pon_tod_1pps_pins[] = { 46 };
> >>>> +static const int en7581_gsw_tod_1pps_pins[] = { 46 };
> >>>> +static const int en7581_sipo_pins[] = { 16, 17 };
> >>>> +static const int en7581_sipo_rclk_pins[] = { 16, 17, 43 };
> >>>> +static const int en7581_mdio_pins[] = { 14, 15 };
> >>>> +static const int en7581_uart2_pins[] = { 48, 55 };
> >>>> +static const int en7581_uart2_cts_rts_pins[] = { 46, 47 };
> >>>> +static const int en7581_hsuart_pins[] = { 28, 29 };
> >>>> +static const int en7581_hsuart_cts_rts_pins[] = { 26, 27 };
> >>>> +static const int en7581_uart4_pins[] = { 38, 39 };
> >>>> +static const int en7581_uart5_pins[] = { 18, 19 };
> >>>> +static const int en7581_i2c0_pins[] = { 2, 3 };
> >>>> +static const int en7581_i2c1_pins[] = { 14, 15 };
> >>>> +static const int en7581_jtag_udi_pins[] = { 16, 17, 18, 19, 20 };
> >>>> +static const int en7581_jtag_dfd_pins[] = { 16, 17, 18, 19, 20 };
> >>>> +static const int en7581_i2s_pins[] = { 26, 27, 28, 29 };
> >>>> +static const int en7581_pcm1_pins[] = { 22, 23, 24, 25 };
> >>>> +static const int en7581_pcm2_pins[] = { 18, 19, 20, 21 };
> >>>> +static const int en7581_spi_quad_pins[] = { 32, 33 };
> >>>> +static const int en7581_spi_pins[] = { 4, 5, 6, 7 };
> >>>> +static const int en7581_spi_cs1_pins[] = { 34 };
> >>>> +static const int en7581_pcm_spi_pins[] = { 18, 19, 20, 21, 22, 23, 24, 25 };
> >>>> +static const int en7581_pcm_spi_int_pins[] = { 14 };
> >>>> +static const int en7581_pcm_spi_rst_pins[] = { 15 };
> >>>> +static const int en7581_pcm_spi_cs1_pins[] = { 43 };
> >>>> +static const int en7581_pcm_spi_cs2_pins[] = { 40 };
> >>>> +static const int en7581_pcm_spi_cs2_p128_pins[] = { 40 };
> >>>> +static const int en7581_pcm_spi_cs2_p156_pins[] = { 40 };
> >>>> +static const int en7581_pcm_spi_cs3_pins[] = { 41 };
> >>>> +static const int en7581_pcm_spi_cs4_pins[] = { 42 };
> >>>> +static const int en7581_emmc_pins[] = {
> >>>> +	4, 5, 6, 30, 31, 32, 33, 34, 35, 36, 37
> >>>> +};
> >>>> +static const int en7581_pnand_pins[] = {
> >>>> +	4, 5, 6, 7, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42
> >>>> +};
> >>>> +static const int en7581_gpio0_pins[] = { 13 };
> >>>> +static const int en7581_gpio1_pins[] = { 14 };
> >>>> +static const int en7581_gpio2_pins[] = { 15 };
> >>>> +static const int en7581_gpio3_pins[] = { 16 };
> >>>> +static const int en7581_gpio4_pins[] = { 17 };
> >>>> +static const int en7581_gpio5_pins[] = { 18 };
> >>>> +static const int en7581_gpio6_pins[] = { 19 };
> >>>> +static const int en7581_gpio7_pins[] = { 20 };
> >>>> +static const int en7581_gpio8_pins[] = { 21 };
> >>>> +static const int en7581_gpio9_pins[] = { 22 };
> >>>> +static const int en7581_gpio10_pins[] = { 23 };
> >>>> +static const int en7581_gpio11_pins[] = { 24 };
> >>>> +static const int en7581_gpio12_pins[] = { 25 };
> >>>> +static const int en7581_gpio13_pins[] = { 26 };
> >>>> +static const int en7581_gpio14_pins[] = { 27 };
> >>>> +static const int en7581_gpio15_pins[] = { 28 };
> >>>> +static const int en7581_gpio16_pins[] = { 29 };
> >>>> +static const int en7581_gpio17_pins[] = { 30 };
> >>>> +static const int en7581_gpio18_pins[] = { 31 };
> >>>> +static const int en7581_gpio19_pins[] = { 32 };
> >>>> +static const int en7581_gpio20_pins[] = { 33 };
> >>>> +static const int en7581_gpio21_pins[] = { 34 };
> >>>> +static const int en7581_gpio22_pins[] = { 35 };
> >>>> +static const int en7581_gpio23_pins[] = { 36 };
> >>>> +static const int en7581_gpio24_pins[] = { 37 };
> >>>> +static const int en7581_gpio25_pins[] = { 38 };
> >>>> +static const int en7581_gpio26_pins[] = { 39 };
> >>>> +static const int en7581_gpio27_pins[] = { 40 };
> >>>> +static const int en7581_gpio28_pins[] = { 41 };
> >>>> +static const int en7581_gpio29_pins[] = { 42 };
> >>>> +static const int en7581_gpio30_pins[] = { 43 };
> >>>> +static const int en7581_gpio31_pins[] = { 44 };
> >>>> +static const int en7581_gpio32_pins[] = { 45 };
> >>>> +static const int en7581_gpio33_pins[] = { 46 };
> >>>> +static const int en7581_gpio34_pins[] = { 47 };
> >>>> +static const int en7581_gpio35_pins[] = { 48 };
> >>>> +static const int en7581_gpio36_pins[] = { 49 };
> >>>> +static const int en7581_gpio37_pins[] = { 50 };
> >>>> +static const int en7581_gpio38_pins[] = { 51 };
> >>>> +static const int en7581_gpio39_pins[] = { 52 };
> >>>> +static const int en7581_gpio40_pins[] = { 53 };
> >>>> +static const int en7581_gpio41_pins[] = { 54 };
> >>>> +static const int en7581_gpio42_pins[] = { 55 };
> >>>> +static const int en7581_gpio43_pins[] = { 56 };
> >>>> +static const int en7581_gpio44_pins[] = { 57 };
> >>>> +static const int en7581_gpio45_pins[] = { 58 };
> >>>> +static const int en7581_gpio46_pins[] = { 59 };
> >>>> +static const int en7581_gpio47_pins[] = { 60 };
> >>>> +static const int en7581_gpio48_pins[] = { 61 };
> >>>> +static const int en7581_gpio49_pins[] = { 62 };
> >>>> +static const int en7581_pcie_reset0_pins[] = { 60 };
> >>>> +static const int en7581_pcie_reset1_pins[] = { 61 };
> >>>> +static const int en7581_pcie_reset2_pins[] = { 62 };
> >>>> +
> >>>> +static const struct pingroup en7581_pinctrl_groups[] = {
> >>>> +	PINCTRL_PIN_GROUP("pon", en7581_pon),
> >>>> +	PINCTRL_PIN_GROUP("pon_tod_1pps", en7581_pon_tod_1pps),
> >>>> +	PINCTRL_PIN_GROUP("gsw_tod_1pps", en7581_gsw_tod_1pps),
> >>>> +	PINCTRL_PIN_GROUP("sipo", en7581_sipo),
> >>>> +	PINCTRL_PIN_GROUP("sipo_rclk", en7581_sipo_rclk),
> >>>> +	PINCTRL_PIN_GROUP("mdio", en7581_mdio),
> >>>> +	PINCTRL_PIN_GROUP("uart2", en7581_uart2),
> >>>> +	PINCTRL_PIN_GROUP("uart2_cts_rts", en7581_uart2_cts_rts),
> >>>> +	PINCTRL_PIN_GROUP("hsuart", en7581_hsuart),
> >>>> +	PINCTRL_PIN_GROUP("hsuart_cts_rts", en7581_hsuart_cts_rts),
> >>>> +	PINCTRL_PIN_GROUP("uart4", en7581_uart4),
> >>>> +	PINCTRL_PIN_GROUP("uart5", en7581_uart5),
> >>>> +	PINCTRL_PIN_GROUP("i2c0", en7581_i2c0),
> >>>> +	PINCTRL_PIN_GROUP("i2c1", en7581_i2c1),
> >>>> +	PINCTRL_PIN_GROUP("jtag_udi", en7581_jtag_udi),
> >>>> +	PINCTRL_PIN_GROUP("jtag_dfd", en7581_jtag_dfd),
> >>>> +	PINCTRL_PIN_GROUP("i2s", en7581_i2s),
> >>>> +	PINCTRL_PIN_GROUP("pcm1", en7581_pcm1),
> >>>> +	PINCTRL_PIN_GROUP("pcm2", en7581_pcm2),
> >>>> +	PINCTRL_PIN_GROUP("spi", en7581_spi),
> >>>> +	PINCTRL_PIN_GROUP("spi_quad", en7581_spi_quad),
> >>>> +	PINCTRL_PIN_GROUP("spi_cs1", en7581_spi_cs1),
> >>>> +	PINCTRL_PIN_GROUP("pcm_spi", en7581_pcm_spi),
> >>>> +	PINCTRL_PIN_GROUP("pcm_spi_int", en7581_pcm_spi_int),
> >>>> +	PINCTRL_PIN_GROUP("pcm_spi_rst", en7581_pcm_spi_rst),
> >>>> +	PINCTRL_PIN_GROUP("pcm_spi_cs1", en7581_pcm_spi_cs1),
> >>>> +	PINCTRL_PIN_GROUP("pcm_spi_cs2_p128", en7581_pcm_spi_cs2_p128),
> >>>> +	PINCTRL_PIN_GROUP("pcm_spi_cs2_p156", en7581_pcm_spi_cs2_p156),
> >>>> +	PINCTRL_PIN_GROUP("pcm_spi_cs2", en7581_pcm_spi_cs2),
> >>>> +	PINCTRL_PIN_GROUP("pcm_spi_cs3", en7581_pcm_spi_cs3),
> >>>> +	PINCTRL_PIN_GROUP("pcm_spi_cs4", en7581_pcm_spi_cs4),
> >>>> +	PINCTRL_PIN_GROUP("emmc", en7581_emmc),
> >>>> +	PINCTRL_PIN_GROUP("pnand", en7581_pnand),
> >>>> +	PINCTRL_PIN_GROUP("gpio0", en7581_gpio0),
> >>>> +	PINCTRL_PIN_GROUP("gpio1", en7581_gpio1),
> >>>> +	PINCTRL_PIN_GROUP("gpio2", en7581_gpio2),
> >>>> +	PINCTRL_PIN_GROUP("gpio3", en7581_gpio3),
> >>>> +	PINCTRL_PIN_GROUP("gpio4", en7581_gpio4),
> >>>> +	PINCTRL_PIN_GROUP("gpio5", en7581_gpio5),
> >>>> +	PINCTRL_PIN_GROUP("gpio6", en7581_gpio6),
> >>>> +	PINCTRL_PIN_GROUP("gpio7", en7581_gpio7),
> >>>> +	PINCTRL_PIN_GROUP("gpio8", en7581_gpio8),
> >>>> +	PINCTRL_PIN_GROUP("gpio9", en7581_gpio9),
> >>>> +	PINCTRL_PIN_GROUP("gpio10", en7581_gpio10),
> >>>> +	PINCTRL_PIN_GROUP("gpio11", en7581_gpio11),
> >>>> +	PINCTRL_PIN_GROUP("gpio12", en7581_gpio12),
> >>>> +	PINCTRL_PIN_GROUP("gpio13", en7581_gpio13),
> >>>> +	PINCTRL_PIN_GROUP("gpio14", en7581_gpio14),
> >>>> +	PINCTRL_PIN_GROUP("gpio15", en7581_gpio15),
> >>>> +	PINCTRL_PIN_GROUP("gpio16", en7581_gpio16),
> >>>> +	PINCTRL_PIN_GROUP("gpio17", en7581_gpio17),
> >>>> +	PINCTRL_PIN_GROUP("gpio18", en7581_gpio18),
> >>>> +	PINCTRL_PIN_GROUP("gpio19", en7581_gpio19),
> >>>> +	PINCTRL_PIN_GROUP("gpio20", en7581_gpio20),
> >>>> +	PINCTRL_PIN_GROUP("gpio21", en7581_gpio21),
> >>>> +	PINCTRL_PIN_GROUP("gpio22", en7581_gpio22),
> >>>> +	PINCTRL_PIN_GROUP("gpio23", en7581_gpio23),
> >>>> +	PINCTRL_PIN_GROUP("gpio24", en7581_gpio24),
> >>>> +	PINCTRL_PIN_GROUP("gpio25", en7581_gpio25),
> >>>> +	PINCTRL_PIN_GROUP("gpio26", en7581_gpio26),
> >>>> +	PINCTRL_PIN_GROUP("gpio27", en7581_gpio27),
> >>>> +	PINCTRL_PIN_GROUP("gpio28", en7581_gpio28),
> >>>> +	PINCTRL_PIN_GROUP("gpio29", en7581_gpio29),
> >>>> +	PINCTRL_PIN_GROUP("gpio30", en7581_gpio30),
> >>>> +	PINCTRL_PIN_GROUP("gpio31", en7581_gpio31),
> >>>> +	PINCTRL_PIN_GROUP("gpio32", en7581_gpio32),
> >>>> +	PINCTRL_PIN_GROUP("gpio33", en7581_gpio33),
> >>>> +	PINCTRL_PIN_GROUP("gpio34", en7581_gpio34),
> >>>> +	PINCTRL_PIN_GROUP("gpio35", en7581_gpio35),
> >>>> +	PINCTRL_PIN_GROUP("gpio36", en7581_gpio36),
> >>>> +	PINCTRL_PIN_GROUP("gpio37", en7581_gpio37),
> >>>> +	PINCTRL_PIN_GROUP("gpio38", en7581_gpio38),
> >>>> +	PINCTRL_PIN_GROUP("gpio39", en7581_gpio39),
> >>>> +	PINCTRL_PIN_GROUP("gpio40", en7581_gpio40),
> >>>> +	PINCTRL_PIN_GROUP("gpio41", en7581_gpio41),
> >>>> +	PINCTRL_PIN_GROUP("gpio42", en7581_gpio42),
> >>>> +	PINCTRL_PIN_GROUP("gpio43", en7581_gpio43),
> >>>> +	PINCTRL_PIN_GROUP("gpio44", en7581_gpio44),
> >>>> +	PINCTRL_PIN_GROUP("gpio45", en7581_gpio45),
> >>>> +	PINCTRL_PIN_GROUP("gpio46", en7581_gpio46),
> >>>> +	PINCTRL_PIN_GROUP("gpio47", en7581_gpio47),
> >>>> +	PINCTRL_PIN_GROUP("gpio48", en7581_gpio48),
> >>>> +	PINCTRL_PIN_GROUP("gpio49", en7581_gpio49),
> >>>> +	PINCTRL_PIN_GROUP("pcie_reset0", en7581_pcie_reset0),
> >>>> +	PINCTRL_PIN_GROUP("pcie_reset1", en7581_pcie_reset1),
> >>>> +	PINCTRL_PIN_GROUP("pcie_reset2", en7581_pcie_reset2),
> >>>> +};
> >>>> +
> >>>> +static const char *const pon_groups[] = { "pon" };
> >>>> +static const char *const tod_1pps_groups[] = {
> >>>> +	"pon_tod_1pps", "gsw_tod_1pps"
> >>>> +};
> >>>> +static const char *const sipo_groups[] = { "sipo", "sipo_rclk" };
> >>>> +static const char *const mdio_groups[] = { "mdio" };
> >>>> +static const char *const uart_groups[] = {
> >>>> +	"uart2", "uart2_cts_rts", "hsuart", "hsuart_cts_rts",
> >>>> +	"uart4", "uart5"
> >>>> +};
> >>>> +static const char *const i2c_groups[] = { "i2c1" };
> >>>> +static const char *const jtag_groups[] = { "jtag_udi", "jtag_dfd" };
> >>>> +static const char *const pcm_groups[] = { "pcm1", "pcm2" };
> >>>> +static const char *const spi_groups[] = { "spi_quad", "spi_cs1" };
> >>>> +static const char *const pcm_spi_groups[] = {
> >>>> +	"pcm_spi", "pcm_spi_int", "pcm_spi_rst", "pcm_spi_cs1",
> >>>> +	"pcm_spi_cs2_p156", "pcm_spi_cs2_p128", "pcm_spi_cs3",
> >>>> +	"pcm_spi_cs4"
> >>>> +};
> >>>> +static const char *const i2s_groups[] = { "i2s" };
> >>>> +static const char *const emmc_groups[] = { "emmc" };
> >>>> +static const char *const pnand_groups[] = { "pnand" };
> >>>> +static const char *const gpio_groups[] = { "gpio47", "gpio48", "gpio49" };
> >>>> +static const char *const pcie_reset_groups[] = {
> >>>> +	"pcie_reset0", "pcie_reset1", "pcie_reset2"
> >>>> +};
> >>>> +static const char *const pwm_groups[] = {
> >>>> +	"gpio0",  "gpio1",  "gpio2",  "gpio3",  "gpio4",  "gpio5",
> >>>> +	"gpio6",  "gpio7",  "gpio8",  "gpio9",  "gpio10", "gpio11",
> >>>> +	"gpio12", "gpio13", "gpio14", "gpio15", "gpio16", "gpio17",
> >>>> +	"gpio18", "gpio19", "gpio20", "gpio21", "gpio22", "gpio23",
> >>>> +	"gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29",
> >>>> +	"gpio30", "gpio31", "gpio36", "gpio37", "gpio38", "gpio39",
> >>>> +	"gpio40", "gpio41", "gpio42", "gpio43", "gpio44", "gpio45",
> >>>> +	"gpio46", "gpio47", "gpio48", "gpio49"
> >>>> +};
> >>>> +static const char *const phy1_led0_groups[] = {
> >>>> +	"gpio33", "gpio34", "gpio35", "gpio42"
> >>>> +};
> >>>> +static const char *const phy2_led0_groups[] = {
> >>>> +	"gpio33", "gpio34", "gpio35", "gpio42"
> >>>> +};
> >>>> +static const char *const phy3_led0_groups[] = {
> >>>> +	"gpio33", "gpio34", "gpio35", "gpio42"
> >>>> +};
> >>>> +static const char *const phy4_led0_groups[] = {
> >>>> +	"gpio33", "gpio34", "gpio35", "gpio42"
> >>>> +};
> >>>> +static const char *const phy1_led1_groups[] = {
> >>>> +	"gpio43", "gpio44", "gpio45", "gpio46"
> >>>> +};
> >>>> +static const char *const phy2_led1_groups[] = {
> >>>> +	"gpio43", "gpio44", "gpio45", "gpio46"
> >>>> +};
> >>>> +static const char *const phy3_led1_groups[] = {
> >>>> +	"gpio43", "gpio44", "gpio45", "gpio46"
> >>>> +};
> >>>> +static const char *const phy4_led1_groups[] = {
> >>>> +	"gpio43", "gpio44", "gpio45", "gpio46"
> >>>> +};
> >>>> +
> >>>> +static const struct airoha_pinctrl_func_group pon_func_group[] = {
> >>>> +	{
> >>>> +		.name = "pon",
> >>>> +		.regmap[0] = {
> >>>> +			AIROHA_FUNC_MUX,
> >>>> +			REG_GPIO_PON_MODE,
> >>>> +			GPIO_PON_MODE_MASK,
> >>>> +			GPIO_PON_MODE_MASK
> >>>> +		},
> >>>> +		.regmap_size = 1,
> >>>> +	},
> >>>> +};
> >>>> +
> >>>> +static const struct airoha_pinctrl_func_group tod_1pps_func_group[] = {
> >>>> +	{
> >>>> +		.name = "pon_tod_1pps",
> >>>> +		.regmap[0] = {
> >>>> +			AIROHA_FUNC_MUX,
> >>>> +			REG_GPIO_2ND_I2C_MODE,
> >>>> +			PON_TOD_1PPS_MODE_MASK,
> >>>> +			PON_TOD_1PPS_MODE_MASK
> >>>> +		},
> >>>> +		.regmap_size = 1,
> >>>> +	}, {
> >>>> +		.name = "gsw_tod_1pps",
> >>>> +		.regmap[0] = {
> >>>> +			AIROHA_FUNC_MUX,
> >>>> +			REG_GPIO_2ND_I2C_MODE,
> >>>> +			GSW_TOD_1PPS_MODE_MASK,
> >>>> +			GSW_TOD_1PPS_MODE_MASK
> >>>> +		},
> >>>> +		.regmap_size = 1,
> >>>> +	},
> >>>> +};
> >>>> +
> >>>> +static const struct airoha_pinctrl_func_group sipo_func_group[] = {
> >>>> +	{
> >>>> +		.name = "sipo",
> >>>> +		.regmap[0] = {
> >>>> +			AIROHA_FUNC_MUX,
> >>>> +			REG_GPIO_PON_MODE,
> >>>> +			GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK,
> >>>> +			GPIO_SIPO_MODE_MASK
> >>>> +		},
> >>>> +		.regmap_size = 1,
> >>>> +	}, {
> >>>> +		.name = "sipo_rclk",
> >>>> +		.regmap[0] = {
> >>>> +			AIROHA_FUNC_MUX,
> >>>> +			REG_GPIO_PON_MODE,
> >>>> +			GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK,
> >>>> +			GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK
> >>>> +		},
> >>>> +		.regmap_size = 1,
> >>>> +	},
> >>>> +};
> >>>> +
> >>>> +static const struct airoha_pinctrl_func_group mdio_func_group[] = {
> >>>> +	{
> >>>> +		.name = "mdio",
> >>>> +		.regmap[0] = {
> >>>> +			AIROHA_FUNC_MUX,
> >>>> +			REG_GPIO_2ND_I2C_MODE,
> >>>> +			GPIO_MDC_IO_MASTER_MODE_MASK,
> >>>> +			GPIO_MDC_IO_MASTER_MODE_MASK
> >>>> +		},
> >>>> +		.regmap[1] = {
> >>>> +			AIROHA_FUNC_MUX,
> >>>> +			REG_FORCE_GPIO_EN,
> >>>> +			FORCE_GPIO_EN(1) | FORCE_GPIO_EN(2),
> >>>> +			FORCE_GPIO_EN(1) | FORCE_GPIO_EN(2)
> >>>> +		},
> >>>> +		.regmap_size = 2,
> >>>> +	},
> >>>> +};
> >>>> +
> >>>> +static const struct airoha_pinctrl_func_group uart_func_group[] = {
> >>>> +	{
> >>>> +		.name = "uart2",
> >>>> +		.regmap[0] = {
> >>>> +			AIROHA_FUNC_MUX,
> >>>> +			REG_GPIO_PON_MODE,
> >>>> +			GPIO_UART2_MODE_MASK,
> >>>> +			GPIO_UART2_MODE_MASK
> >>>> +		},
> >>>> +		.regmap_size = 1,
> >>>> +	}, {
> >>>> +		.name = "uart2_cts_rts",
> >>>> +		.regmap[0] = {
> >>>> +			AIROHA_FUNC_MUX,
> >>>> +			REG_GPIO_PON_MODE,
> >>>> +			GPIO_UART2_MODE_MASK | GPIO_UART2_CTS_RTS_MODE_MASK,
> >>>> +			GPIO_UART2_MODE_MASK | GPIO_UART2_CTS_RTS_MODE_MASK
> >>>> +		},
> >>>> +		.regmap_size = 1,
> >>>> +	}, {
> >>>> +		.name = "hsuart",
> >>>> +		.regmap[0] = {
> >>>> +			AIROHA_FUNC_MUX,
> >>>> +			REG_GPIO_PON_MODE,
> >>>> +			GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK,
> >>>> +			GPIO_HSUART_MODE_MASK
> >>>> +		},
> >>>> +		.regmap_size = 1,
> >>>> +	},
> >>>> +	{
> >>>> +		.name = "hsuart_cts_rts",
> >>>> +		.regmap[0] = {
> >>>> +			AIROHA_FUNC_MUX,
> >>>> +			REG_GPIO_PON_MODE,
> >>>> +			GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK,
> >>>> +			GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK
> >>>> +		},
> >>>> +		.regmap_size = 1,
> >>>> +	}, {
> >>>> +		.name = "uart4",
> >>>> +		.regmap[0] = {
> >>>> +			AIROHA_FUNC_MUX,
> >>>> +			REG_GPIO_PON_MODE,
> >>>> +			GPIO_UART4_MODE_MASK,
> >>>> +			GPIO_UART4_MODE_MASK
> >>>> +		},
> >>>> +		.regmap_size = 1,
> >>>> +	}, {
> >>>> +		.name = "uart5",
> >>>> +		.regmap[0] = {
> >>>> +			AIROHA_FUNC_MUX,
> >>>> +			REG_GPIO_PON_MODE,
> >>>> +			GPIO_UART5_MODE_MASK,
> >>>> +			GPIO_UART5_MODE_MASK
> >>>> +		},
> >>>> +		.regmap_size = 1,
> >>>> +	},
> >>>> +};
> >>>> +
> >>>> +static const struct airoha_pinctrl_func_group i2c_func_group[] = {
> >>>> +	{
> >>>> +		.name = "i2c1",
> >>>> +		.regmap[0] = {
> >>>> +			AIROHA_FUNC_MUX,
> >>>> +			REG_GPIO_2ND_I2C_MODE,
> >>>> +			GPIO_2ND_I2C_MODE_MASK,
> >>>> +			GPIO_2ND_I2C_MODE_MASK
> >>>> +		},
> >>>> +		.regmap_size = 1,
> >>>> +	},
> >>>> +};
> >>>> +
> >>>> +static const struct airoha_pinctrl_func_group jtag_func_group[] = {
> >>>> +	{
> >>>> +		.name = "jtag_udi",
> >>>> +		.regmap[0] = {
> >>>> +			AIROHA_FUNC_MUX,
> >>>> +			REG_NPU_UART_EN,
> >>>> +			JTAG_UDI_EN_MASK,
> >>>> +			JTAG_UDI_EN_MASK
> >>>> +		},
> >>>> +		.regmap_size = 1,
> >>>> +	}, {
> >>>> +		.name = "jtag_dfd",
> >>>> +		.regmap[0] = {
> >>>> +			AIROHA_FUNC_MUX,
> >>>> +			REG_NPU_UART_EN,
> >>>> +			JTAG_DFD_EN_MASK,
> >>>> +			JTAG_DFD_EN_MASK
> >>>> +		},
> >>>> +		.regmap_size = 1,
> >>>> +	},
> >>>> +};
> >>>> +
> >>>> +static const struct airoha_pinctrl_func_group pcm_func_group[] = {
> >>>> +	{
> >>>> +		.name = "pcm1",
> >>>> +		.regmap[0] = {
> >>>> +			AIROHA_FUNC_MUX,
> >>>> +			REG_GPIO_SPI_CS1_MODE,
> >>>> +			GPIO_PCM1_MODE_MASK,
> >>>> +			GPIO_PCM1_MODE_MASK
> >>>> +		},
> >>>> +		.regmap_size = 1,
> >>>> +	}, {
> >>>> +		.name = "pcm2",
> >>>> +		.regmap[0] = {
> >>>> +			AIROHA_FUNC_MUX,
> >>>> +			REG_GPIO_SPI_CS1_MODE,
> >>>> +			GPIO_PCM2_MODE_MASK,
> >>>> +			GPIO_PCM2_MODE_MASK
> >>>> +		},
> >>>> +		.regmap_size = 1,
> >>>> +	},
> >>>> +};
> >>>> +
> >>>> +static const struct airoha_pinctrl_func_group spi_func_group[] = {
> >>>> +	{
> >>>> +		.name = "spi_quad",
> >>>> +		.regmap[0] = {
> >>>> +			AIROHA_FUNC_MUX,
> >>>> +			REG_GPIO_SPI_CS1_MODE,
> >>>> +			GPIO_SPI_QUAD_MODE_MASK,
> >>>> +			GPIO_SPI_QUAD_MODE_MASK
> >>>> +		},
> >>>> +		.regmap_size = 1,
> >>>> +	}, {
> >>>> +		.name = "spi_cs1",
> >>>> +		.regmap[0] = {
> >>>> +			AIROHA_FUNC_MUX,
> >>>> +			REG_GPIO_SPI_CS1_MODE,
> >>>> +			GPIO_SPI_CS1_MODE_MASK,
> >>>> +			GPIO_SPI_CS1_MODE_MASK
> >>>> +		},
> >>>> +		.regmap_size = 1,
> >>>> +	}, {
> >>>> +		.name = "spi_cs2",
> >>>> +		.regmap[0] = {
> >>>> +			AIROHA_FUNC_MUX,
> >>>> +			REG_GPIO_SPI_CS1_MODE,
> >>>> +			GPIO_SPI_CS2_MODE_MASK,
> >>>> +			GPIO_SPI_CS2_MODE_MASK
> >>>> +		},
> >>>> +		.regmap_size = 1,
> >>>> +	}, {
> >>>> +		.name = "spi_cs3",
> >>>> +		.regmap[0] = {
> >>>> +			AIROHA_FUNC_MUX,
> >>>> +			REG_GPIO_SPI_CS1_MODE,
> >>>> +			GPIO_SPI_CS3_MODE_MASK,
> >>>> +			GPIO_SPI_CS3_MODE_MASK
> >>>> +		},
> >>>> +		.regmap_size = 1,
> >>>> +	}, {
> >>>> +		.name = "spi_cs4",
> >>>> +		.regmap[0] = {
> >>>> +			AIROHA_FUNC_MUX,
> >>>> +			REG_GPIO_SPI_CS1_MODE,
> >>>> +			GPIO_SPI_CS4_MODE_MASK,
> >>>> +			GPIO_SPI_CS4_MODE_MASK
> >>>> +		},
> >>>> +		.regmap_size = 1,
> >>>> +	},
> >>>> +};
> >>>> +
> >>>> +static const struct airoha_pinctrl_func_group pcm_spi_func_group[] = {
> >>>> +	{
> >>>> +		.name = "pcm_spi",
> >>>> +		.regmap[0] = {
> >>>> +			AIROHA_FUNC_MUX,
> >>>> +			REG_GPIO_SPI_CS1_MODE,
> >>>> +			GPIO_PCM_SPI_MODE_MASK,
> >>>> +			GPIO_PCM_SPI_MODE_MASK
> >>>> +		},
> >>>> +		.regmap_size = 1,
> >>>> +	}, {
> >>>> +		.name = "pcm_spi_int",
> >>>> +		.regmap[0] = {
> >>>> +			AIROHA_FUNC_MUX,
> >>>> +			REG_GPIO_SPI_CS1_MODE,
> >>>> +			GPIO_PCM_INT_MODE_MASK,
> >>>> +			GPIO_PCM_INT_MODE_MASK
> >>>> +		},
> >>>> +		.regmap_size = 1,
> >>>> +	}, {
> >>>> +		.name = "pcm_spi_rst",
> >>>> +		.regmap[0] = {
> >>>> +			AIROHA_FUNC_MUX,
> >>>> +			REG_GPIO_SPI_CS1_MODE,
> >>>> +			GPIO_PCM_RESET_MODE_MASK,
> >>>> +			GPIO_PCM_RESET_MODE_MASK
> >>>> +		},
> >>>> +		.regmap_size = 1,
> >>>> +	}, {
> >>>> +		.name = "pcm_spi_cs1",
> >>>> +		.regmap[0] = {
> >>>> +			AIROHA_FUNC_MUX,
> >>>> +			REG_GPIO_SPI_CS1_MODE,
> >>>> +			GPIO_PCM_SPI_CS1_MODE_MASK,
> >>>> +			GPIO_PCM_SPI_CS1_MODE_MASK
> >>>> +		},
> >>>> +		.regmap_size = 1,
> >>>> +	}, {
> >>>> +		.name = "pcm_spi_cs2_p128",
> >>>> +		.regmap[0] = {
> >>>> +			AIROHA_FUNC_MUX,
> >>>> +			REG_GPIO_SPI_CS1_MODE,
> >>>> +			GPIO_PCM_SPI_CS2_MODE_P128_MASK,
> >>>> +			GPIO_PCM_SPI_CS2_MODE_P128_MASK
> >>>> +		},
> >>>> +		.regmap_size = 1,
> >>>> +	}, {
> >>>> +		.name = "pcm_spi_cs2_p156",
> >>>> +		.regmap[0] = {
> >>>> +			AIROHA_FUNC_MUX,
> >>>> +			REG_GPIO_SPI_CS1_MODE,
> >>>> +			GPIO_PCM_SPI_CS2_MODE_P156_MASK,
> >>>> +			GPIO_PCM_SPI_CS2_MODE_P156_MASK
> >>>> +		},
> >>>> +		.regmap_size = 1,
> >>>> +	}, {
> >>>> +		.name = "pcm_spi_cs3",
> >>>> +		.regmap[0] = {
> >>>> +			AIROHA_FUNC_MUX,
> >>>> +			REG_GPIO_SPI_CS1_MODE,
> >>>> +			GPIO_PCM_SPI_CS3_MODE_MASK,
> >>>> +			GPIO_PCM_SPI_CS3_MODE_MASK
> >>>> +		},
> >>>> +		.regmap_size = 1,
> >>>> +	}, {
> >>>> +		.name = "pcm_spi_cs4",
> >>>> +		.regmap[0] = {
> >>>> +			AIROHA_FUNC_MUX,
> >>>> +			REG_GPIO_SPI_CS1_MODE,
> >>>> +			GPIO_PCM_SPI_CS4_MODE_MASK,
> >>>> +			GPIO_PCM_SPI_CS4_MODE_MASK
> >>>> +		},
> >>>> +		.regmap_size = 1,
> >>>> +	},
> >>>> +};
> >>>> +
> >>>> +static const struct airoha_pinctrl_func_group i2s_func_group[] = {
> >>>> +	{
> >>>> +		.name = "i2s",
> >>>> +		.regmap[0] = {
> >>>> +			AIROHA_FUNC_MUX,
> >>>> +			REG_GPIO_2ND_I2C_MODE,
> >>>> +			GPIO_I2S_MODE_MASK,
> >>>> +			GPIO_I2S_MODE_MASK
> >>>> +		},
> >>>> +		.regmap_size = 1,
> >>>> +	},
> >>>> +};
> >>>> +
> >>>> +static const struct airoha_pinctrl_func_group emmc_func_group[] = {
> >>>> +	{
> >>>> +		.name = "emmc",
> >>>> +		.regmap[0] = {
> >>>> +			AIROHA_FUNC_MUX,
> >>>> +			REG_GPIO_PON_MODE,
> >>>> +			GPIO_EMMC_MODE_MASK,
> >>>> +			GPIO_EMMC_MODE_MASK
> >>>> +		},
> >>>> +		.regmap_size = 1,
> >>>> +	},
> >>>> +};
> >>>> +
> >>>> +static const struct airoha_pinctrl_func_group pnand_func_group[] = {
> >>>> +	{
> >>>> +		.name = "pnand",
> >>>> +		.regmap[0] = {
> >>>> +			AIROHA_FUNC_MUX,
> >>>> +			REG_GPIO_PON_MODE,
> >>>> +			GPIO_PARALLEL_NAND_MODE_MASK,
> >>>> +			GPIO_PARALLEL_NAND_MODE_MASK
> >>>> +		},
> >>>> +		.regmap_size = 1,
> >>>> +	},
> >>>> +};
> >>>> +
> >>>> +static const struct airoha_pinctrl_func_group gpio_func_group[] = {
> >>>> +	AIROHA_PINCTRL_GPIO_EXT("gpio47", GPIO47_FLASH_MODE_CFG,
> >>>> +				GPIO_PCIE_RESET0_MASK),
> >>>> +	AIROHA_PINCTRL_GPIO_EXT("gpio48", GPIO48_FLASH_MODE_CFG,
> >>>> +				GPIO_PCIE_RESET1_MASK),
> >>>> +	AIROHA_PINCTRL_GPIO_EXT("gpio49", GPIO49_FLASH_MODE_CFG,
> >>>> +				GPIO_PCIE_RESET2_MASK),
> >>>> +};
> >>>> +
> >>>> +static const struct airoha_pinctrl_func_group pcie_reset_func_group[] = {
> >>>> +	{
> >>>> +		.name = "pcie_reset0",
> >>>> +		.regmap[0] = {
> >>>> +			AIROHA_FUNC_MUX,
> >>>> +			REG_GPIO_PON_MODE,
> >>>> +			GPIO_PCIE_RESET0_MASK,
> >>>> +			0
> >>>> +		},
> >>>> +		.regmap_size = 1,
> >>>> +	}, {
> >>>> +		.name = "pcie_reset1",
> >>>> +		.regmap[0] = {
> >>>> +			AIROHA_FUNC_MUX,
> >>>> +			REG_GPIO_PON_MODE,
> >>>> +			GPIO_PCIE_RESET1_MASK,
> >>>> +			0
> >>>> +		},
> >>>> +		.regmap_size = 1,
> >>>> +	}, {
> >>>> +		.name = "pcie_reset2",
> >>>> +		.regmap[0] = {
> >>>> +			AIROHA_FUNC_MUX,
> >>>> +			REG_GPIO_PON_MODE,
> >>>> +			GPIO_PCIE_RESET2_MASK,
> >>>> +			0
> >>>> +		},
> >>>> +		.regmap_size = 1,
> >>>> +	},
> >>>> +};
> >>>> +
> >>>> +static const struct airoha_pinctrl_func_group pwm_func_group[] = {
> >>>> +	AIROHA_PINCTRL_PWM("gpio0", GPIO0_FLASH_MODE_CFG),
> >>>> +	AIROHA_PINCTRL_PWM("gpio1", GPIO1_FLASH_MODE_CFG),
> >>>> +	AIROHA_PINCTRL_PWM("gpio2", GPIO2_FLASH_MODE_CFG),
> >>>> +	AIROHA_PINCTRL_PWM("gpio3", GPIO3_FLASH_MODE_CFG),
> >>>> +	AIROHA_PINCTRL_PWM("gpio4", GPIO4_FLASH_MODE_CFG),
> >>>> +	AIROHA_PINCTRL_PWM("gpio5", GPIO5_FLASH_MODE_CFG),
> >>>> +	AIROHA_PINCTRL_PWM("gpio6", GPIO6_FLASH_MODE_CFG),
> >>>> +	AIROHA_PINCTRL_PWM("gpio7", GPIO7_FLASH_MODE_CFG),
> >>>> +	AIROHA_PINCTRL_PWM("gpio8", GPIO8_FLASH_MODE_CFG),
> >>>> +	AIROHA_PINCTRL_PWM("gpio9", GPIO9_FLASH_MODE_CFG),
> >>>> +	AIROHA_PINCTRL_PWM("gpio10", GPIO10_FLASH_MODE_CFG),
> >>>> +	AIROHA_PINCTRL_PWM("gpio11", GPIO11_FLASH_MODE_CFG),
> >>>> +	AIROHA_PINCTRL_PWM("gpio12", GPIO12_FLASH_MODE_CFG),
> >>>> +	AIROHA_PINCTRL_PWM("gpio13", GPIO13_FLASH_MODE_CFG),
> >>>> +	AIROHA_PINCTRL_PWM("gpio14", GPIO14_FLASH_MODE_CFG),
> >>>> +	AIROHA_PINCTRL_PWM("gpio15", GPIO15_FLASH_MODE_CFG),
> >>>> +	AIROHA_PINCTRL_PWM_EXT("gpio16", GPIO16_FLASH_MODE_CFG),
> >>>> +	AIROHA_PINCTRL_PWM_EXT("gpio17", GPIO17_FLASH_MODE_CFG),
> >>>> +	AIROHA_PINCTRL_PWM_EXT("gpio18", GPIO18_FLASH_MODE_CFG),
> >>>> +	AIROHA_PINCTRL_PWM_EXT("gpio19", GPIO19_FLASH_MODE_CFG),
> >>>> +	AIROHA_PINCTRL_PWM_EXT("gpio20", GPIO20_FLASH_MODE_CFG),
> >>>> +	AIROHA_PINCTRL_PWM_EXT("gpio21", GPIO21_FLASH_MODE_CFG),
> >>>> +	AIROHA_PINCTRL_PWM_EXT("gpio22", GPIO22_FLASH_MODE_CFG),
> >>>> +	AIROHA_PINCTRL_PWM_EXT("gpio23", GPIO23_FLASH_MODE_CFG),
> >>>> +	AIROHA_PINCTRL_PWM_EXT("gpio24", GPIO24_FLASH_MODE_CFG),
> >>>> +	AIROHA_PINCTRL_PWM_EXT("gpio25", GPIO25_FLASH_MODE_CFG),
> >>>> +	AIROHA_PINCTRL_PWM_EXT("gpio26", GPIO26_FLASH_MODE_CFG),
> >>>> +	AIROHA_PINCTRL_PWM_EXT("gpio27", GPIO27_FLASH_MODE_CFG),
> >>>> +	AIROHA_PINCTRL_PWM_EXT("gpio28", GPIO28_FLASH_MODE_CFG),
> >>>> +	AIROHA_PINCTRL_PWM_EXT("gpio29", GPIO29_FLASH_MODE_CFG),
> >>>> +	AIROHA_PINCTRL_PWM_EXT("gpio30", GPIO30_FLASH_MODE_CFG),
> >>>> +	AIROHA_PINCTRL_PWM_EXT("gpio31", GPIO31_FLASH_MODE_CFG),
> >>>> +	AIROHA_PINCTRL_PWM_EXT("gpio36", GPIO36_FLASH_MODE_CFG),
> >>>> +	AIROHA_PINCTRL_PWM_EXT("gpio37", GPIO37_FLASH_MODE_CFG),
> >>>> +	AIROHA_PINCTRL_PWM_EXT("gpio38", GPIO38_FLASH_MODE_CFG),
> >>>> +	AIROHA_PINCTRL_PWM_EXT("gpio39", GPIO39_FLASH_MODE_CFG),
> >>>> +	AIROHA_PINCTRL_PWM_EXT("gpio40", GPIO40_FLASH_MODE_CFG),
> >>>> +	AIROHA_PINCTRL_PWM_EXT("gpio41", GPIO41_FLASH_MODE_CFG),
> >>>> +	AIROHA_PINCTRL_PWM_EXT("gpio42", GPIO42_FLASH_MODE_CFG),
> >>>> +	AIROHA_PINCTRL_PWM_EXT("gpio43", GPIO43_FLASH_MODE_CFG),
> >>>> +	AIROHA_PINCTRL_PWM_EXT("gpio44", GPIO44_FLASH_MODE_CFG),
> >>>> +	AIROHA_PINCTRL_PWM_EXT("gpio45", GPIO45_FLASH_MODE_CFG),
> >>>> +	AIROHA_PINCTRL_PWM_EXT("gpio46", GPIO46_FLASH_MODE_CFG),
> >>>> +	AIROHA_PINCTRL_PWM_EXT_SEC("gpio47", GPIO47_FLASH_MODE_CFG,
> >>>> +				   GPIO_PCIE_RESET0_MASK),
> >>>> +	AIROHA_PINCTRL_PWM_EXT_SEC("gpio48", GPIO48_FLASH_MODE_CFG,
> >>>> +				   GPIO_PCIE_RESET1_MASK),
> >>>> +	AIROHA_PINCTRL_PWM_EXT_SEC("gpio49", GPIO49_FLASH_MODE_CFG,
> >>>> +				   GPIO_PCIE_RESET2_MASK),
> >>>> +};
> >>>> +
> >>>> +static const struct airoha_pinctrl_func_group phy1_led0_func_group[] = {
> >>>> +	AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK,
> >>>> +				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),
> >>>> +	AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK,
> >>>> +				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)),
> >>>> +	AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK,
> >>>> +				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)),
> >>>> +	AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK,
> >>>> +				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),
> >>>> +};
> >>>> +
> >>>> +static const struct airoha_pinctrl_func_group phy2_led0_func_group[] = {
> >>>> +	AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK,
> >>>> +				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),
> >>>> +	AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK,
> >>>> +				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)),
> >>>> +	AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK,
> >>>> +				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)),
> >>>> +	AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK,
> >>>> +				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),
> >>>> +};
> >>>> +
> >>>> +static const struct airoha_pinctrl_func_group phy3_led0_func_group[] = {
> >>>> +	AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK,
> >>>> +				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
> >>>> +	AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK,
> >>>> +				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),
> >>>> +	AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK,
> >>>> +				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),
> >>>> +	AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK,
> >>>> +				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
> >>>> +};
> >>>> +
> >>>> +static const struct airoha_pinctrl_func_group phy4_led0_func_group[] = {
> >>>> +	AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK,
> >>>> +				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)),
> >>>> +	AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK,
> >>>> +				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)),
> >>>> +	AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK,
> >>>> +				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)),
> >>>> +	AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK,
> >>>> +				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)),
> >>>> +};
> >>>> +
> >>>> +static const struct airoha_pinctrl_func_group phy1_led1_func_group[] = {
> >>>> +	AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK,
> >>>> +				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),
> >>>> +	AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK,
> >>>> +				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)),
> >>>> +	AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK,
> >>>> +				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)),
> >>>> +	AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK,
> >>>> +				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),
> >>>> +};
> >>>> +
> >>>> +static const struct airoha_pinctrl_func_group phy2_led1_func_group[] = {
> >>>> +	AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK,
> >>>> +				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),
> >>>> +	AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK,
> >>>> +				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)),
> >>>> +	AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK,
> >>>> +				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)),
> >>>> +	AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK,
> >>>> +				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),
> >>>> +};
> >>>> +
> >>>> +static const struct airoha_pinctrl_func_group phy3_led1_func_group[] = {
> >>>> +	AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK,
> >>>> +				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
> >>>> +	AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK,
> >>>> +				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),
> >>>> +	AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK,
> >>>> +				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),
> >>>> +	AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK,
> >>>> +				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
> >>>> +};
> >>>> +
> >>>> +static const struct airoha_pinctrl_func_group phy4_led1_func_group[] = {
> >>>> +	AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK,
> >>>> +				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)),
> >>>> +	AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK,
> >>>> +				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)),
> >>>> +	AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK,
> >>>> +				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)),
> >>>> +	AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK,
> >>>> +				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)),
> >>>> +};
> >>>> +
> >>>> +static const struct airoha_pinctrl_func en7581_pinctrl_funcs[] = {
> >>>> +	PINCTRL_FUNC_DESC("pon", pon),
> >>>> +	PINCTRL_FUNC_DESC("tod_1pps", tod_1pps),
> >>>> +	PINCTRL_FUNC_DESC("sipo", sipo),
> >>>> +	PINCTRL_FUNC_DESC("mdio", mdio),
> >>>> +	PINCTRL_FUNC_DESC("uart", uart),
> >>>> +	PINCTRL_FUNC_DESC("i2c", i2c),
> >>>> +	PINCTRL_FUNC_DESC("jtag", jtag),
> >>>> +	PINCTRL_FUNC_DESC("pcm", pcm),
> >>>> +	PINCTRL_FUNC_DESC("spi", spi),
> >>>> +	PINCTRL_FUNC_DESC("pcm_spi", pcm_spi),
> >>>> +	PINCTRL_FUNC_DESC("i2s", i2s),
> >>>> +	PINCTRL_FUNC_DESC("emmc", emmc),
> >>>> +	PINCTRL_FUNC_DESC("pnand", pnand),
> >>>> +	PINCTRL_FUNC_DESC("gpio", gpio),
> >>>> +	PINCTRL_FUNC_DESC("pcie_reset", pcie_reset),
> >>>> +	PINCTRL_FUNC_DESC("pwm", pwm),
> >>>> +	PINCTRL_FUNC_DESC("phy1_led0", phy1_led0),
> >>>> +	PINCTRL_FUNC_DESC("phy2_led0", phy2_led0),
> >>>> +	PINCTRL_FUNC_DESC("phy3_led0", phy3_led0),
> >>>> +	PINCTRL_FUNC_DESC("phy4_led0", phy4_led0),
> >>>> +	PINCTRL_FUNC_DESC("phy1_led1", phy1_led1),
> >>>> +	PINCTRL_FUNC_DESC("phy2_led1", phy2_led1),
> >>>> +	PINCTRL_FUNC_DESC("phy3_led1", phy3_led1),
> >>>> +	PINCTRL_FUNC_DESC("phy4_led1", phy4_led1),
> >>>> +};
> >>>> +
> >>>> +static const struct airoha_pinctrl_conf en7581_pinctrl_pullup_conf[] = {
> >>>> +	PINCTRL_CONF_DESC(0, REG_I2C_SDA_PU, UART1_TXD_PU_MASK),
> >>>> +	PINCTRL_CONF_DESC(1, REG_I2C_SDA_PU, UART1_RXD_PU_MASK),
> >>>> +	PINCTRL_CONF_DESC(2, REG_I2C_SDA_PU, I2C_SDA_PU_MASK),
> >>>> +	PINCTRL_CONF_DESC(3, REG_I2C_SDA_PU, I2C_SCL_PU_MASK),
> >>>> +	PINCTRL_CONF_DESC(4, REG_I2C_SDA_PU, SPI_CS0_PU_MASK),
> >>>> +	PINCTRL_CONF_DESC(5, REG_I2C_SDA_PU, SPI_CLK_PU_MASK),
> >>>> +	PINCTRL_CONF_DESC(6, REG_I2C_SDA_PU, SPI_MOSI_PU_MASK),
> >>>> +	PINCTRL_CONF_DESC(7, REG_I2C_SDA_PU, SPI_MISO_PU_MASK),
> >>>> +	PINCTRL_CONF_DESC(13, REG_GPIO_L_PU, BIT(0)),
> >>>> +	PINCTRL_CONF_DESC(14, REG_GPIO_L_PU, BIT(1)),
> >>>> +	PINCTRL_CONF_DESC(15, REG_GPIO_L_PU, BIT(2)),
> >>>> +	PINCTRL_CONF_DESC(16, REG_GPIO_L_PU, BIT(3)),
> >>>> +	PINCTRL_CONF_DESC(17, REG_GPIO_L_PU, BIT(4)),
> >>>> +	PINCTRL_CONF_DESC(18, REG_GPIO_L_PU, BIT(5)),
> >>>> +	PINCTRL_CONF_DESC(19, REG_GPIO_L_PU, BIT(6)),
> >>>> +	PINCTRL_CONF_DESC(20, REG_GPIO_L_PU, BIT(7)),
> >>>> +	PINCTRL_CONF_DESC(21, REG_GPIO_L_PU, BIT(8)),
> >>>> +	PINCTRL_CONF_DESC(22, REG_GPIO_L_PU, BIT(9)),
> >>>> +	PINCTRL_CONF_DESC(23, REG_GPIO_L_PU, BIT(10)),
> >>>> +	PINCTRL_CONF_DESC(24, REG_GPIO_L_PU, BIT(11)),
> >>>> +	PINCTRL_CONF_DESC(25, REG_GPIO_L_PU, BIT(12)),
> >>>> +	PINCTRL_CONF_DESC(26, REG_GPIO_L_PU, BIT(13)),
> >>>> +	PINCTRL_CONF_DESC(27, REG_GPIO_L_PU, BIT(14)),
> >>>> +	PINCTRL_CONF_DESC(28, REG_GPIO_L_PU, BIT(15)),
> >>>> +	PINCTRL_CONF_DESC(29, REG_GPIO_L_PU, BIT(16)),
> >>>> +	PINCTRL_CONF_DESC(30, REG_GPIO_L_PU, BIT(17)),
> >>>> +	PINCTRL_CONF_DESC(31, REG_GPIO_L_PU, BIT(18)),
> >>>> +	PINCTRL_CONF_DESC(32, REG_GPIO_L_PU, BIT(19)),
> >>>> +	PINCTRL_CONF_DESC(33, REG_GPIO_L_PU, BIT(20)),
> >>>> +	PINCTRL_CONF_DESC(34, REG_GPIO_L_PU, BIT(21)),
> >>>> +	PINCTRL_CONF_DESC(35, REG_GPIO_L_PU, BIT(22)),
> >>>> +	PINCTRL_CONF_DESC(36, REG_GPIO_L_PU, BIT(23)),
> >>>> +	PINCTRL_CONF_DESC(37, REG_GPIO_L_PU, BIT(24)),
> >>>> +	PINCTRL_CONF_DESC(38, REG_GPIO_L_PU, BIT(25)),
> >>>> +	PINCTRL_CONF_DESC(39, REG_GPIO_L_PU, BIT(26)),
> >>>> +	PINCTRL_CONF_DESC(40, REG_GPIO_L_PU, BIT(27)),
> >>>> +	PINCTRL_CONF_DESC(41, REG_GPIO_L_PU, BIT(28)),
> >>>> +	PINCTRL_CONF_DESC(42, REG_GPIO_L_PU, BIT(29)),
> >>>> +	PINCTRL_CONF_DESC(43, REG_GPIO_L_PU, BIT(30)),
> >>>> +	PINCTRL_CONF_DESC(44, REG_GPIO_L_PU, BIT(31)),
> >>>> +	PINCTRL_CONF_DESC(45, REG_GPIO_H_PU, BIT(0)),
> >>>> +	PINCTRL_CONF_DESC(46, REG_GPIO_H_PU, BIT(1)),
> >>>> +	PINCTRL_CONF_DESC(47, REG_GPIO_H_PU, BIT(2)),
> >>>> +	PINCTRL_CONF_DESC(48, REG_GPIO_H_PU, BIT(3)),
> >>>> +	PINCTRL_CONF_DESC(49, REG_GPIO_H_PU, BIT(4)),
> >>>> +	PINCTRL_CONF_DESC(50, REG_GPIO_H_PU, BIT(5)),
> >>>> +	PINCTRL_CONF_DESC(51, REG_GPIO_H_PU, BIT(6)),
> >>>> +	PINCTRL_CONF_DESC(52, REG_GPIO_H_PU, BIT(7)),
> >>>> +	PINCTRL_CONF_DESC(53, REG_GPIO_H_PU, BIT(8)),
> >>>> +	PINCTRL_CONF_DESC(54, REG_GPIO_H_PU, BIT(9)),
> >>>> +	PINCTRL_CONF_DESC(55, REG_GPIO_H_PU, BIT(10)),
> >>>> +	PINCTRL_CONF_DESC(56, REG_GPIO_H_PU, BIT(11)),
> >>>> +	PINCTRL_CONF_DESC(57, REG_GPIO_H_PU, BIT(12)),
> >>>> +	PINCTRL_CONF_DESC(58, REG_GPIO_H_PU, BIT(13)),
> >>>> +	PINCTRL_CONF_DESC(59, REG_GPIO_H_PU, BIT(14)),
> >>>> +	PINCTRL_CONF_DESC(60, REG_I2C_SDA_PU, PCIE0_RESET_PU_MASK),
> >>>> +	PINCTRL_CONF_DESC(61, REG_I2C_SDA_PU, PCIE1_RESET_PU_MASK),
> >>>> +	PINCTRL_CONF_DESC(62, REG_I2C_SDA_PU, PCIE2_RESET_PU_MASK),
> >>>> +};
> >>>> +
> >>>> +static const struct airoha_pinctrl_conf en7581_pinctrl_pulldown_conf[] = {
> >>>> +	PINCTRL_CONF_DESC(0, REG_I2C_SDA_PD, UART1_TXD_PD_MASK),
> >>>> +	PINCTRL_CONF_DESC(1, REG_I2C_SDA_PD, UART1_RXD_PD_MASK),
> >>>> +	PINCTRL_CONF_DESC(2, REG_I2C_SDA_PD, I2C_SDA_PD_MASK),
> >>>> +	PINCTRL_CONF_DESC(3, REG_I2C_SDA_PD, I2C_SCL_PD_MASK),
> >>>> +	PINCTRL_CONF_DESC(4, REG_I2C_SDA_PD, SPI_CS0_PD_MASK),
> >>>> +	PINCTRL_CONF_DESC(5, REG_I2C_SDA_PD, SPI_CLK_PD_MASK),
> >>>> +	PINCTRL_CONF_DESC(6, REG_I2C_SDA_PD, SPI_MOSI_PD_MASK),
> >>>> +	PINCTRL_CONF_DESC(7, REG_I2C_SDA_PD, SPI_MISO_PD_MASK),
> >>>> +	PINCTRL_CONF_DESC(13, REG_GPIO_L_PD, BIT(0)),
> >>>> +	PINCTRL_CONF_DESC(14, REG_GPIO_L_PD, BIT(1)),
> >>>> +	PINCTRL_CONF_DESC(15, REG_GPIO_L_PD, BIT(2)),
> >>>> +	PINCTRL_CONF_DESC(16, REG_GPIO_L_PD, BIT(3)),
> >>>> +	PINCTRL_CONF_DESC(17, REG_GPIO_L_PD, BIT(4)),
> >>>> +	PINCTRL_CONF_DESC(18, REG_GPIO_L_PD, BIT(5)),
> >>>> +	PINCTRL_CONF_DESC(19, REG_GPIO_L_PD, BIT(6)),
> >>>> +	PINCTRL_CONF_DESC(20, REG_GPIO_L_PD, BIT(7)),
> >>>> +	PINCTRL_CONF_DESC(21, REG_GPIO_L_PD, BIT(8)),
> >>>> +	PINCTRL_CONF_DESC(22, REG_GPIO_L_PD, BIT(9)),
> >>>> +	PINCTRL_CONF_DESC(23, REG_GPIO_L_PD, BIT(10)),
> >>>> +	PINCTRL_CONF_DESC(24, REG_GPIO_L_PD, BIT(11)),
> >>>> +	PINCTRL_CONF_DESC(25, REG_GPIO_L_PD, BIT(12)),
> >>>> +	PINCTRL_CONF_DESC(26, REG_GPIO_L_PD, BIT(13)),
> >>>> +	PINCTRL_CONF_DESC(27, REG_GPIO_L_PD, BIT(14)),
> >>>> +	PINCTRL_CONF_DESC(28, REG_GPIO_L_PD, BIT(15)),
> >>>> +	PINCTRL_CONF_DESC(29, REG_GPIO_L_PD, BIT(16)),
> >>>> +	PINCTRL_CONF_DESC(30, REG_GPIO_L_PD, BIT(17)),
> >>>> +	PINCTRL_CONF_DESC(31, REG_GPIO_L_PD, BIT(18)),
> >>>> +	PINCTRL_CONF_DESC(32, REG_GPIO_L_PD, BIT(19)),
> >>>> +	PINCTRL_CONF_DESC(33, REG_GPIO_L_PD, BIT(20)),
> >>>> +	PINCTRL_CONF_DESC(34, REG_GPIO_L_PD, BIT(21)),
> >>>> +	PINCTRL_CONF_DESC(35, REG_GPIO_L_PD, BIT(22)),
> >>>> +	PINCTRL_CONF_DESC(36, REG_GPIO_L_PD, BIT(23)),
> >>>> +	PINCTRL_CONF_DESC(37, REG_GPIO_L_PD, BIT(24)),
> >>>> +	PINCTRL_CONF_DESC(38, REG_GPIO_L_PD, BIT(25)),
> >>>> +	PINCTRL_CONF_DESC(39, REG_GPIO_L_PD, BIT(26)),
> >>>> +	PINCTRL_CONF_DESC(40, REG_GPIO_L_PD, BIT(27)),
> >>>> +	PINCTRL_CONF_DESC(41, REG_GPIO_L_PD, BIT(28)),
> >>>> +	PINCTRL_CONF_DESC(42, REG_GPIO_L_PD, BIT(29)),
> >>>> +	PINCTRL_CONF_DESC(43, REG_GPIO_L_PD, BIT(30)),
> >>>> +	PINCTRL_CONF_DESC(44, REG_GPIO_L_PD, BIT(31)),
> >>>> +	PINCTRL_CONF_DESC(45, REG_GPIO_H_PD, BIT(0)),
> >>>> +	PINCTRL_CONF_DESC(46, REG_GPIO_H_PD, BIT(1)),
> >>>> +	PINCTRL_CONF_DESC(47, REG_GPIO_H_PD, BIT(2)),
> >>>> +	PINCTRL_CONF_DESC(48, REG_GPIO_H_PD, BIT(3)),
> >>>> +	PINCTRL_CONF_DESC(49, REG_GPIO_H_PD, BIT(4)),
> >>>> +	PINCTRL_CONF_DESC(50, REG_GPIO_H_PD, BIT(5)),
> >>>> +	PINCTRL_CONF_DESC(51, REG_GPIO_H_PD, BIT(6)),
> >>>> +	PINCTRL_CONF_DESC(52, REG_GPIO_H_PD, BIT(7)),
> >>>> +	PINCTRL_CONF_DESC(53, REG_GPIO_H_PD, BIT(8)),
> >>>> +	PINCTRL_CONF_DESC(54, REG_GPIO_H_PD, BIT(9)),
> >>>> +	PINCTRL_CONF_DESC(55, REG_GPIO_H_PD, BIT(10)),
> >>>> +	PINCTRL_CONF_DESC(56, REG_GPIO_H_PD, BIT(11)),
> >>>> +	PINCTRL_CONF_DESC(57, REG_GPIO_H_PD, BIT(12)),
> >>>> +	PINCTRL_CONF_DESC(58, REG_GPIO_H_PD, BIT(13)),
> >>>> +	PINCTRL_CONF_DESC(59, REG_GPIO_H_PD, BIT(14)),
> >>>> +	PINCTRL_CONF_DESC(60, REG_I2C_SDA_PD, PCIE0_RESET_PD_MASK),
> >>>> +	PINCTRL_CONF_DESC(61, REG_I2C_SDA_PD, PCIE1_RESET_PD_MASK),
> >>>> +	PINCTRL_CONF_DESC(62, REG_I2C_SDA_PD, PCIE2_RESET_PD_MASK),
> >>>> +};
> >>>> +
> >>>> +static const struct airoha_pinctrl_conf en7581_pinctrl_drive_e2_conf[] = {
> >>>> +	PINCTRL_CONF_DESC(0, REG_I2C_SDA_E2, UART1_TXD_E2_MASK),
> >>>> +	PINCTRL_CONF_DESC(1, REG_I2C_SDA_E2, UART1_RXD_E2_MASK),
> >>>> +	PINCTRL_CONF_DESC(2, REG_I2C_SDA_E2, I2C_SDA_E2_MASK),
> >>>> +	PINCTRL_CONF_DESC(3, REG_I2C_SDA_E2, I2C_SCL_E2_MASK),
> >>>> +	PINCTRL_CONF_DESC(4, REG_I2C_SDA_E2, SPI_CS0_E2_MASK),
> >>>> +	PINCTRL_CONF_DESC(5, REG_I2C_SDA_E2, SPI_CLK_E2_MASK),
> >>>> +	PINCTRL_CONF_DESC(6, REG_I2C_SDA_E2, SPI_MOSI_E2_MASK),
> >>>> +	PINCTRL_CONF_DESC(7, REG_I2C_SDA_E2, SPI_MISO_E2_MASK),
> >>>> +	PINCTRL_CONF_DESC(13, REG_GPIO_L_E2, BIT(0)),
> >>>> +	PINCTRL_CONF_DESC(14, REG_GPIO_L_E2, BIT(1)),
> >>>> +	PINCTRL_CONF_DESC(15, REG_GPIO_L_E2, BIT(2)),
> >>>> +	PINCTRL_CONF_DESC(16, REG_GPIO_L_E2, BIT(3)),
> >>>> +	PINCTRL_CONF_DESC(17, REG_GPIO_L_E2, BIT(4)),
> >>>> +	PINCTRL_CONF_DESC(18, REG_GPIO_L_E2, BIT(5)),
> >>>> +	PINCTRL_CONF_DESC(19, REG_GPIO_L_E2, BIT(6)),
> >>>> +	PINCTRL_CONF_DESC(20, REG_GPIO_L_E2, BIT(7)),
> >>>> +	PINCTRL_CONF_DESC(21, REG_GPIO_L_E2, BIT(8)),
> >>>> +	PINCTRL_CONF_DESC(22, REG_GPIO_L_E2, BIT(9)),
> >>>> +	PINCTRL_CONF_DESC(23, REG_GPIO_L_E2, BIT(10)),
> >>>> +	PINCTRL_CONF_DESC(24, REG_GPIO_L_E2, BIT(11)),
> >>>> +	PINCTRL_CONF_DESC(25, REG_GPIO_L_E2, BIT(12)),
> >>>> +	PINCTRL_CONF_DESC(26, REG_GPIO_L_E2, BIT(13)),
> >>>> +	PINCTRL_CONF_DESC(27, REG_GPIO_L_E2, BIT(14)),
> >>>> +	PINCTRL_CONF_DESC(28, REG_GPIO_L_E2, BIT(15)),
> >>>> +	PINCTRL_CONF_DESC(29, REG_GPIO_L_E2, BIT(16)),
> >>>> +	PINCTRL_CONF_DESC(30, REG_GPIO_L_E2, BIT(17)),
> >>>> +	PINCTRL_CONF_DESC(31, REG_GPIO_L_E2, BIT(18)),
> >>>> +	PINCTRL_CONF_DESC(32, REG_GPIO_L_E2, BIT(19)),
> >>>> +	PINCTRL_CONF_DESC(33, REG_GPIO_L_E2, BIT(20)),
> >>>> +	PINCTRL_CONF_DESC(34, REG_GPIO_L_E2, BIT(21)),
> >>>> +	PINCTRL_CONF_DESC(35, REG_GPIO_L_E2, BIT(22)),
> >>>> +	PINCTRL_CONF_DESC(36, REG_GPIO_L_E2, BIT(23)),
> >>>> +	PINCTRL_CONF_DESC(37, REG_GPIO_L_E2, BIT(24)),
> >>>> +	PINCTRL_CONF_DESC(38, REG_GPIO_L_E2, BIT(25)),
> >>>> +	PINCTRL_CONF_DESC(39, REG_GPIO_L_E2, BIT(26)),
> >>>> +	PINCTRL_CONF_DESC(40, REG_GPIO_L_E2, BIT(27)),
> >>>> +	PINCTRL_CONF_DESC(41, REG_GPIO_L_E2, BIT(28)),
> >>>> +	PINCTRL_CONF_DESC(42, REG_GPIO_L_E2, BIT(29)),
> >>>> +	PINCTRL_CONF_DESC(43, REG_GPIO_L_E2, BIT(30)),
> >>>> +	PINCTRL_CONF_DESC(44, REG_GPIO_L_E2, BIT(31)),
> >>>> +	PINCTRL_CONF_DESC(45, REG_GPIO_H_E2, BIT(0)),
> >>>> +	PINCTRL_CONF_DESC(46, REG_GPIO_H_E2, BIT(1)),
> >>>> +	PINCTRL_CONF_DESC(47, REG_GPIO_H_E2, BIT(2)),
> >>>> +	PINCTRL_CONF_DESC(48, REG_GPIO_H_E2, BIT(3)),
> >>>> +	PINCTRL_CONF_DESC(49, REG_GPIO_H_E2, BIT(4)),
> >>>> +	PINCTRL_CONF_DESC(50, REG_GPIO_H_E2, BIT(5)),
> >>>> +	PINCTRL_CONF_DESC(51, REG_GPIO_H_E2, BIT(6)),
> >>>> +	PINCTRL_CONF_DESC(52, REG_GPIO_H_E2, BIT(7)),
> >>>> +	PINCTRL_CONF_DESC(53, REG_GPIO_H_E2, BIT(8)),
> >>>> +	PINCTRL_CONF_DESC(54, REG_GPIO_H_E2, BIT(9)),
> >>>> +	PINCTRL_CONF_DESC(55, REG_GPIO_H_E2, BIT(10)),
> >>>> +	PINCTRL_CONF_DESC(56, REG_GPIO_H_E2, BIT(11)),
> >>>> +	PINCTRL_CONF_DESC(57, REG_GPIO_H_E2, BIT(12)),
> >>>> +	PINCTRL_CONF_DESC(58, REG_GPIO_H_E2, BIT(13)),
> >>>> +	PINCTRL_CONF_DESC(59, REG_GPIO_H_E2, BIT(14)),
> >>>> +	PINCTRL_CONF_DESC(60, REG_I2C_SDA_E2, PCIE0_RESET_E2_MASK),
> >>>> +	PINCTRL_CONF_DESC(61, REG_I2C_SDA_E2, PCIE1_RESET_E2_MASK),
> >>>> +	PINCTRL_CONF_DESC(62, REG_I2C_SDA_E2, PCIE2_RESET_E2_MASK),
> >>>> +};
> >>>> +
> >>>> +static const struct airoha_pinctrl_conf en7581_pinctrl_drive_e4_conf[] = {
> >>>> +	PINCTRL_CONF_DESC(0, REG_I2C_SDA_E4, UART1_TXD_E4_MASK),
> >>>> +	PINCTRL_CONF_DESC(1, REG_I2C_SDA_E4, UART1_RXD_E4_MASK),
> >>>> +	PINCTRL_CONF_DESC(2, REG_I2C_SDA_E4, I2C_SDA_E4_MASK),
> >>>> +	PINCTRL_CONF_DESC(3, REG_I2C_SDA_E4, I2C_SCL_E4_MASK),
> >>>> +	PINCTRL_CONF_DESC(4, REG_I2C_SDA_E4, SPI_CS0_E4_MASK),
> >>>> +	PINCTRL_CONF_DESC(5, REG_I2C_SDA_E4, SPI_CLK_E4_MASK),
> >>>> +	PINCTRL_CONF_DESC(6, REG_I2C_SDA_E4, SPI_MOSI_E4_MASK),
> >>>> +	PINCTRL_CONF_DESC(7, REG_I2C_SDA_E4, SPI_MISO_E4_MASK),
> >>>> +	PINCTRL_CONF_DESC(13, REG_GPIO_L_E4, BIT(0)),
> >>>> +	PINCTRL_CONF_DESC(14, REG_GPIO_L_E4, BIT(1)),
> >>>> +	PINCTRL_CONF_DESC(15, REG_GPIO_L_E4, BIT(2)),
> >>>> +	PINCTRL_CONF_DESC(16, REG_GPIO_L_E4, BIT(3)),
> >>>> +	PINCTRL_CONF_DESC(17, REG_GPIO_L_E4, BIT(4)),
> >>>> +	PINCTRL_CONF_DESC(18, REG_GPIO_L_E4, BIT(5)),
> >>>> +	PINCTRL_CONF_DESC(19, REG_GPIO_L_E4, BIT(6)),
> >>>> +	PINCTRL_CONF_DESC(20, REG_GPIO_L_E4, BIT(7)),
> >>>> +	PINCTRL_CONF_DESC(21, REG_GPIO_L_E4, BIT(8)),
> >>>> +	PINCTRL_CONF_DESC(22, REG_GPIO_L_E4, BIT(9)),
> >>>> +	PINCTRL_CONF_DESC(23, REG_GPIO_L_E4, BIT(10)),
> >>>> +	PINCTRL_CONF_DESC(24, REG_GPIO_L_E4, BIT(11)),
> >>>> +	PINCTRL_CONF_DESC(25, REG_GPIO_L_E4, BIT(12)),
> >>>> +	PINCTRL_CONF_DESC(26, REG_GPIO_L_E4, BIT(13)),
> >>>> +	PINCTRL_CONF_DESC(27, REG_GPIO_L_E4, BIT(14)),
> >>>> +	PINCTRL_CONF_DESC(28, REG_GPIO_L_E4, BIT(15)),
> >>>> +	PINCTRL_CONF_DESC(29, REG_GPIO_L_E4, BIT(16)),
> >>>> +	PINCTRL_CONF_DESC(30, REG_GPIO_L_E4, BIT(17)),
> >>>> +	PINCTRL_CONF_DESC(31, REG_GPIO_L_E4, BIT(18)),
> >>>> +	PINCTRL_CONF_DESC(32, REG_GPIO_L_E4, BIT(19)),
> >>>> +	PINCTRL_CONF_DESC(33, REG_GPIO_L_E4, BIT(20)),
> >>>> +	PINCTRL_CONF_DESC(34, REG_GPIO_L_E4, BIT(21)),
> >>>> +	PINCTRL_CONF_DESC(35, REG_GPIO_L_E4, BIT(22)),
> >>>> +	PINCTRL_CONF_DESC(36, REG_GPIO_L_E4, BIT(23)),
> >>>> +	PINCTRL_CONF_DESC(37, REG_GPIO_L_E4, BIT(24)),
> >>>> +	PINCTRL_CONF_DESC(38, REG_GPIO_L_E4, BIT(25)),
> >>>> +	PINCTRL_CONF_DESC(39, REG_GPIO_L_E4, BIT(26)),
> >>>> +	PINCTRL_CONF_DESC(40, REG_GPIO_L_E4, BIT(27)),
> >>>> +	PINCTRL_CONF_DESC(41, REG_GPIO_L_E4, BIT(28)),
> >>>> +	PINCTRL_CONF_DESC(42, REG_GPIO_L_E4, BIT(29)),
> >>>> +	PINCTRL_CONF_DESC(43, REG_GPIO_L_E4, BIT(30)),
> >>>> +	PINCTRL_CONF_DESC(44, REG_GPIO_L_E4, BIT(31)),
> >>>> +	PINCTRL_CONF_DESC(45, REG_GPIO_H_E4, BIT(0)),
> >>>> +	PINCTRL_CONF_DESC(46, REG_GPIO_H_E4, BIT(1)),
> >>>> +	PINCTRL_CONF_DESC(47, REG_GPIO_H_E4, BIT(2)),
> >>>> +	PINCTRL_CONF_DESC(48, REG_GPIO_H_E4, BIT(3)),
> >>>> +	PINCTRL_CONF_DESC(49, REG_GPIO_H_E4, BIT(4)),
> >>>> +	PINCTRL_CONF_DESC(50, REG_GPIO_H_E4, BIT(5)),
> >>>> +	PINCTRL_CONF_DESC(51, REG_GPIO_H_E4, BIT(6)),
> >>>> +	PINCTRL_CONF_DESC(52, REG_GPIO_H_E4, BIT(7)),
> >>>> +	PINCTRL_CONF_DESC(53, REG_GPIO_H_E4, BIT(8)),
> >>>> +	PINCTRL_CONF_DESC(54, REG_GPIO_H_E4, BIT(9)),
> >>>> +	PINCTRL_CONF_DESC(55, REG_GPIO_H_E4, BIT(10)),
> >>>> +	PINCTRL_CONF_DESC(56, REG_GPIO_H_E4, BIT(11)),
> >>>> +	PINCTRL_CONF_DESC(57, REG_GPIO_H_E4, BIT(12)),
> >>>> +	PINCTRL_CONF_DESC(58, REG_GPIO_H_E4, BIT(13)),
> >>>> +	PINCTRL_CONF_DESC(59, REG_GPIO_H_E4, BIT(14)),
> >>>> +	PINCTRL_CONF_DESC(60, REG_I2C_SDA_E4, PCIE0_RESET_E4_MASK),
> >>>> +	PINCTRL_CONF_DESC(61, REG_I2C_SDA_E4, PCIE1_RESET_E4_MASK),
> >>>> +	PINCTRL_CONF_DESC(62, REG_I2C_SDA_E4, PCIE2_RESET_E4_MASK),
> >>>> +};
> >>>> +
> >>>> +static const struct airoha_pinctrl_conf en7581_pinctrl_pcie_rst_od_conf[] = {
> >>>> +	PINCTRL_CONF_DESC(60, REG_PCIE_RESET_OD, PCIE0_RESET_OD_MASK),
> >>>> +	PINCTRL_CONF_DESC(61, REG_PCIE_RESET_OD, PCIE1_RESET_OD_MASK),
> >>>> +	PINCTRL_CONF_DESC(62, REG_PCIE_RESET_OD, PCIE2_RESET_OD_MASK),
> >>>> +};
> >>>> +
> >>>> +static const struct airoha_pinctrl_match_data en7581_pinctrl_match_data = {
> >>>> +	.pinctrl_name = KBUILD_MODNAME,
> >>>> +	.pinctrl_owner = THIS_MODULE,
> >>>> +	.pins = en7581_pinctrl_pins,
> >>>> +	.num_pins = ARRAY_SIZE(en7581_pinctrl_pins),
> >>>> +	.grps = en7581_pinctrl_groups,
> >>>> +	.num_grps = ARRAY_SIZE(en7581_pinctrl_groups),
> >>>> +	.funcs = en7581_pinctrl_funcs,
> >>>> +	.num_funcs = ARRAY_SIZE(en7581_pinctrl_funcs),
> >>>> +	.confs_info = {
> >>>> +		[AIROHA_PINCTRL_CONFS_PULLUP] = {
> >>>> +			.confs = en7581_pinctrl_pullup_conf,
> >>>> +			.num_confs = ARRAY_SIZE(en7581_pinctrl_pullup_conf),
> >>>> +		},
> >>>> +		[AIROHA_PINCTRL_CONFS_PULLDOWN] = {
> >>>> +			.confs = en7581_pinctrl_pulldown_conf,
> >>>> +			.num_confs = ARRAY_SIZE(en7581_pinctrl_pulldown_conf),
> >>>> +		},
> >>>> +		[AIROHA_PINCTRL_CONFS_DRIVE_E2] = {
> >>>> +			.confs = en7581_pinctrl_drive_e2_conf,
> >>>> +			.num_confs = ARRAY_SIZE(en7581_pinctrl_drive_e2_conf),
> >>>> +		},
> >>>> +		[AIROHA_PINCTRL_CONFS_DRIVE_E4] = {
> >>>> +			.confs = en7581_pinctrl_drive_e4_conf,
> >>>> +			.num_confs = ARRAY_SIZE(en7581_pinctrl_drive_e4_conf),
> >>>> +		},
> >>>> +		[AIROHA_PINCTRL_CONFS_PCIE_RST_OD] = {
> >>>> +			.confs = en7581_pinctrl_pcie_rst_od_conf,
> >>>> +			.num_confs = ARRAY_SIZE(en7581_pinctrl_pcie_rst_od_conf),
> >>>> +		},
> >>>> +	},
> >>>> +};
> >>>> +
> >>>> +static const struct of_device_id airoha_pinctrl_of_match[] = {
> >>>> +	{ .compatible = "airoha,en7581-pinctrl", .data = &en7581_pinctrl_match_data },
> >>>> +	{ /* sentinel */ }
> >>>> +};
> >>>> +MODULE_DEVICE_TABLE(of, airoha_pinctrl_of_match);
> >>>> +
> >>>> +static struct platform_driver airoha_pinctrl_driver = {
> >>>> +	.probe = airoha_pinctrl_probe,
> >>>> +	.driver = {
> >>>> +		.name = "pinctrl-airoha-an7581",
> >>>> +		.of_match_table = airoha_pinctrl_of_match,
> >>>> +	},
> >>>> +};
> >>>> +module_platform_driver(airoha_pinctrl_driver);
> >>>> +
> >>>> +MODULE_LICENSE("GPL");
> >>>> +MODULE_AUTHOR("Lorenzo Bianconi <lorenzo@kernel.org>");
> >>>> +MODULE_AUTHOR("Benjamin Larsson <benjamin.larsson@genexis.eu>");
> >>>> +MODULE_AUTHOR("Markus Gothe <markus.gothe@genexis.eu>");
> >>>> +MODULE_DESCRIPTION("Pinctrl driver for Airoha AN7581 SoC");
> >>>> diff --git a/drivers/pinctrl/airoha/pinctrl-an7583.c b/drivers/pinctrl/airoha/pinctrl-an7583.c
> >>>> new file mode 100644
> >>>> index 0000000000000..b9d8dd94de5f0
> >>>> --- /dev/null
> >>>> +++ b/drivers/pinctrl/airoha/pinctrl-an7583.c
> >>>> @@ -0,0 +1,1456 @@
> >>>> +// SPDX-License-Identifier: GPL-2.0-only
> >>>> +/*
> >>>> + * Author: Lorenzo Bianconi <lorenzo@kernel.org>
> >>>> + * Author: Benjamin Larsson <benjamin.larsson@genexis.eu>
> >>>> + * Author: Markus Gothe <markus.gothe@genexis.eu>
> >>>> + */
> >>>> +
> >>>> +#include "airoha-common.h"
> >>>> +
> >>>> +/* MUX */
> >>>> +#define REG_GPIO_2ND_I2C_MODE			0x0214
> >>>> +#define GPIO_LAN3_LED1_MODE_MASK		BIT(10)
> >>>> +#define GPIO_LAN3_LED0_MODE_MASK		BIT(9)
> >>>> +#define GPIO_LAN2_LED1_MODE_MASK		BIT(8)
> >>>> +#define GPIO_LAN2_LED0_MODE_MASK		BIT(7)
> >>>> +#define GPIO_LAN1_LED1_MODE_MASK		BIT(6)
> >>>> +#define GPIO_LAN1_LED0_MODE_MASK		BIT(5)
> >>>> +#define GPIO_LAN0_LED1_MODE_MASK		BIT(4)
> >>>> +#define GPIO_LAN0_LED0_MODE_MASK		BIT(3)
> >>>> +#define PON_TOD_1PPS_MODE_MASK			BIT(2)
> >>>> +#define GSW_TOD_1PPS_MODE_MASK			BIT(1)
> >>>> +
> >>>> +#define REG_GPIO_SPI_CS1_MODE			0x0218
> >>>> +#define GPIO_MDC_IO_MASTER_MODE_MASK		BIT(22)
> >>>> +#define GPIO_PCM_SPI_CS4_MODE_MASK		BIT(21)
> >>>> +#define GPIO_PCM_SPI_CS3_MODE_MASK		BIT(20)
> >>>> +#define AN7583_GPIO_PCM_SPI_CS2_MODE_MASK	BIT(18)
> >>>> +#define GPIO_PCM_SPI_CS1_MODE_MASK		BIT(17)
> >>>> +#define GPIO_PCM_SPI_MODE_MASK			BIT(16)
> >>>> +#define GPIO_PCM2_MODE_MASK			BIT(13)
> >>>> +#define GPIO_PCM1_MODE_MASK			BIT(12)
> >>>> +#define GPIO_PCM_INT_MODE_MASK			BIT(9)
> >>>> +#define GPIO_PCM_RESET_MODE_MASK		BIT(8)
> >>>> +#define GPIO_SPI_QUAD_MODE_MASK			BIT(4)
> >>>> +#define GPIO_SPI_CS4_MODE_MASK			BIT(3)
> >>>> +#define GPIO_SPI_CS3_MODE_MASK			BIT(2)
> >>>> +#define GPIO_SPI_CS2_MODE_MASK			BIT(1)
> >>>> +#define GPIO_SPI_CS1_MODE_MASK			BIT(0)
> >>>> +
> >>>> +#define REG_GPIO_PON_MODE			0x021c
> >>>> +#define AN7583_MDIO_0_GPIO_MODE_MASK		BIT(26)
> >>>> +#define AN7583_MDC_0_GPIO_MODE_MASK		BIT(25)
> >>>> +#define AN7583_UART_RXD_GPIO_MODE_MASK		BIT(24)
> >>>> +#define AN7583_UART_TXD_GPIO_MODE_MASK		BIT(23)
> >>>> +#define AN7583_SPI_MISO_GPIO_MODE_MASK		BIT(22)
> >>>> +#define AN7583_SPI_MOSI_GPIO_MODE_MASK		BIT(21)
> >>>> +#define AN7583_SPI_CS_GPIO_MODE_MASK		BIT(20)
> >>>> +#define AN7583_SPI_CLK_GPIO_MODE_MASK		BIT(19)
> >>>> +#define AN7583_I2C1_SDA_GPIO_MODE_MASK		BIT(18)
> >>>> +#define AN7583_I2C1_SCL_GPIO_MODE_MASK		BIT(17)
> >>>> +#define AN7583_I2C0_SDA_GPIO_MODE_MASK		BIT(16)
> >>>> +#define AN7583_I2C0_SCL_GPIO_MODE_MASK		BIT(15)
> >>>> +#define GPIO_PARALLEL_NAND_MODE_MASK		BIT(14)
> >>>> +#define GPIO_SGMII_MDIO_MODE_MASK		BIT(13)
> >>>> +#define SIPO_RCLK_MODE_MASK			BIT(11)
> >>>> +#define GPIO_PCIE_RESET1_MASK			BIT(10)
> >>>> +#define GPIO_PCIE_RESET0_MASK			BIT(9)
> >>>> +#define GPIO_UART5_MODE_MASK			BIT(8)
> >>>> +#define GPIO_UART4_MODE_MASK			BIT(7)
> >>>> +#define GPIO_HSUART_CTS_RTS_MODE_MASK		BIT(6)
> >>>> +#define GPIO_HSUART_MODE_MASK			BIT(5)
> >>>> +#define GPIO_UART2_CTS_RTS_MODE_MASK		BIT(4)
> >>>> +#define GPIO_UART2_MODE_MASK			BIT(3)
> >>>> +#define GPIO_SIPO_MODE_MASK			BIT(2)
> >>>> +#define GPIO_EMMC_MODE_MASK			BIT(1)
> >>>> +#define GPIO_PON_MODE_MASK			BIT(0)
> >>>> +
> >>>> +#define REG_NPU_UART_EN				0x0224
> >>>> +#define JTAG_UDI_EN_MASK			BIT(4)
> >>>> +#define JTAG_DFD_EN_MASK			BIT(3)
> >>>> +
> >>>> +#define REG_FORCE_GPIO_EN			0x0228
> >>>> +#define FORCE_GPIO_EN(n)			BIT(n)
> >>>> +
> >>>> +/* LED MAP */
> >>>> +#define REG_LAN_LED0_MAPPING			0x027c
> >>>> +#define REG_LAN_LED1_MAPPING			0x0280
> >>>> +
> >>>> +#define LAN4_LED_MAPPING_MASK			GENMASK(18, 16)
> >>>> +#define LAN4_PHY_LED_MAP(_n)			FIELD_PREP_CONST(LAN4_LED_MAPPING_MASK, (_n))
> >>>> +
> >>>> +#define LAN3_LED_MAPPING_MASK			GENMASK(14, 12)
> >>>> +#define LAN3_PHY_LED_MAP(_n)			FIELD_PREP_CONST(LAN3_LED_MAPPING_MASK, (_n))
> >>>> +
> >>>> +#define LAN2_LED_MAPPING_MASK			GENMASK(10, 8)
> >>>> +#define LAN2_PHY_LED_MAP(_n)			FIELD_PREP_CONST(LAN2_LED_MAPPING_MASK, (_n))
> >>>> +
> >>>> +#define LAN1_LED_MAPPING_MASK			GENMASK(6, 4)
> >>>> +#define LAN1_PHY_LED_MAP(_n)			FIELD_PREP_CONST(LAN1_LED_MAPPING_MASK, (_n))
> >>>> +
> >>>> +#define LAN0_LED_MAPPING_MASK			GENMASK(2, 0)
> >>>> +#define LAN0_PHY_LED_MAP(_n)			FIELD_PREP_CONST(LAN0_LED_MAPPING_MASK, (_n))
> >>>> +
> >>>> +/* CONF */
> >>>> +#define REG_I2C_SDA_E2				0x001c
> >>>> +#define AN7583_I2C1_SCL_E2_MASK			BIT(16)
> >>>> +#define AN7583_I2C1_SDA_E2_MASK			BIT(15)
> >>>> +#define SPI_MISO_E2_MASK			BIT(14)
> >>>> +#define SPI_MOSI_E2_MASK			BIT(13)
> >>>> +#define SPI_CLK_E2_MASK				BIT(12)
> >>>> +#define SPI_CS0_E2_MASK				BIT(11)
> >>>> +#define PCIE1_RESET_E2_MASK			BIT(9)
> >>>> +#define PCIE0_RESET_E2_MASK			BIT(8)
> >>>> +#define AN7583_MDIO_0_E2_MASK			BIT(5)
> >>>> +#define AN7583_MDC_0_E2_MASK			BIT(4)
> >>>> +#define UART1_RXD_E2_MASK			BIT(3)
> >>>> +#define UART1_TXD_E2_MASK			BIT(2)
> >>>> +#define I2C_SCL_E2_MASK				BIT(1)
> >>>> +#define I2C_SDA_E2_MASK				BIT(0)
> >>>> +
> >>>> +#define REG_I2C_SDA_E4				0x0020
> >>>> +#define AN7583_I2C1_SCL_E4_MASK			BIT(16)
> >>>> +#define AN7583_I2C1_SDA_E4_MASK			BIT(15)
> >>>> +#define SPI_MISO_E4_MASK			BIT(14)
> >>>> +#define SPI_MOSI_E4_MASK			BIT(13)
> >>>> +#define SPI_CLK_E4_MASK				BIT(12)
> >>>> +#define SPI_CS0_E4_MASK				BIT(11)
> >>>> +#define PCIE1_RESET_E4_MASK			BIT(9)
> >>>> +#define PCIE0_RESET_E4_MASK			BIT(8)
> >>>> +#define AN7583_MDIO_0_E4_MASK			BIT(5)
> >>>> +#define AN7583_MDC_0_E4_MASK			BIT(4)
> >>>> +#define UART1_RXD_E4_MASK			BIT(3)
> >>>> +#define UART1_TXD_E4_MASK			BIT(2)
> >>>> +#define I2C_SCL_E4_MASK				BIT(1)
> >>>> +#define I2C_SDA_E4_MASK				BIT(0)
> >>>> +
> >>>> +#define REG_GPIO_L_E2				0x0024
> >>>> +#define REG_GPIO_L_E4				0x0028
> >>>> +#define REG_GPIO_H_E2				0x002c
> >>>> +#define REG_GPIO_H_E4				0x0030
> >>>> +
> >>>> +#define REG_I2C_SDA_PU				0x0044
> >>>> +#define AN7583_I2C1_SCL_PU_MASK			BIT(16)
> >>>> +#define AN7583_I2C1_SDA_PU_MASK			BIT(15)
> >>>> +#define SPI_MISO_PU_MASK			BIT(14)
> >>>> +#define SPI_MOSI_PU_MASK			BIT(13)
> >>>> +#define SPI_CLK_PU_MASK				BIT(12)
> >>>> +#define SPI_CS0_PU_MASK				BIT(11)
> >>>> +#define PCIE1_RESET_PU_MASK			BIT(9)
> >>>> +#define PCIE0_RESET_PU_MASK			BIT(8)
> >>>> +#define AN7583_MDIO_0_PU_MASK			BIT(5)
> >>>> +#define AN7583_MDC_0_PU_MASK			BIT(4)
> >>>> +#define UART1_RXD_PU_MASK			BIT(3)
> >>>> +#define UART1_TXD_PU_MASK			BIT(2)
> >>>> +#define I2C_SCL_PU_MASK				BIT(1)
> >>>> +#define I2C_SDA_PU_MASK				BIT(0)
> >>>> +
> >>>> +#define REG_I2C_SDA_PD				0x0048
> >>>> +#define AN7583_I2C1_SCL_PD_MASK			BIT(16)
> >>>> +#define AN7583_I2C1_SDA_PD_MASK			BIT(15)
> >>>> +#define SPI_MISO_PD_MASK			BIT(14)
> >>>> +#define SPI_MOSI_PD_MASK			BIT(13)
> >>>> +#define SPI_CLK_PD_MASK				BIT(12)
> >>>> +#define SPI_CS0_PD_MASK				BIT(11)
> >>>> +#define PCIE1_RESET_PD_MASK			BIT(9)
> >>>> +#define PCIE0_RESET_PD_MASK			BIT(8)
> >>>> +#define AN7583_MDIO_0_PD_MASK			BIT(5)
> >>>> +#define AN7583_MDC_0_PD_MASK			BIT(4)
> >>>> +#define UART1_RXD_PD_MASK			BIT(3)
> >>>> +#define UART1_TXD_PD_MASK			BIT(2)
> >>>> +#define I2C_SCL_PD_MASK				BIT(1)
> >>>> +#define I2C_SDA_PD_MASK				BIT(0)
> >>>> +
> >>>> +#define REG_GPIO_L_PU				0x004c
> >>>> +#define REG_GPIO_L_PD				0x0050
> >>>> +#define REG_GPIO_H_PU				0x0054
> >>>> +#define REG_GPIO_H_PD				0x0058
> >>>> +
> >>>> +#define REG_PCIE_RESET_OD			0x018c
> >>>> +#define PCIE1_RESET_OD_MASK			BIT(1)
> >>>> +#define PCIE0_RESET_OD_MASK			BIT(0)
> >>>> +
> >>>> +/* PWM MODE CONF */
> >>>> +#define REG_GPIO_FLASH_MODE_CFG			0x0034
> >>>> +#define GPIO15_FLASH_MODE_CFG			BIT(15)
> >>>> +#define GPIO14_FLASH_MODE_CFG			BIT(14)
> >>>> +#define GPIO13_FLASH_MODE_CFG			BIT(13)
> >>>> +#define GPIO12_FLASH_MODE_CFG			BIT(12)
> >>>> +#define GPIO11_FLASH_MODE_CFG			BIT(11)
> >>>> +#define GPIO10_FLASH_MODE_CFG			BIT(10)
> >>>> +#define GPIO9_FLASH_MODE_CFG			BIT(9)
> >>>> +#define GPIO8_FLASH_MODE_CFG			BIT(8)
> >>>> +#define GPIO7_FLASH_MODE_CFG			BIT(7)
> >>>> +#define GPIO6_FLASH_MODE_CFG			BIT(6)
> >>>> +#define GPIO5_FLASH_MODE_CFG			BIT(5)
> >>>> +#define GPIO4_FLASH_MODE_CFG			BIT(4)
> >>>> +#define GPIO3_FLASH_MODE_CFG			BIT(3)
> >>>> +#define GPIO2_FLASH_MODE_CFG			BIT(2)
> >>>> +#define GPIO1_FLASH_MODE_CFG			BIT(1)
> >>>> +#define GPIO0_FLASH_MODE_CFG			BIT(0)
> >>>> +
> >>>> +/* PWM MODE CONF EXT */
> >>>> +#define REG_GPIO_FLASH_MODE_CFG_EXT		0x0068
> >>>> +#define GPIO51_FLASH_MODE_CFG			BIT(31)
> >>>> +#define GPIO50_FLASH_MODE_CFG			BIT(30)
> >>>> +#define GPIO49_FLASH_MODE_CFG			BIT(29)
> >>>> +#define GPIO48_FLASH_MODE_CFG			BIT(28)
> >>>> +#define GPIO47_FLASH_MODE_CFG			BIT(27)
> >>>> +#define GPIO46_FLASH_MODE_CFG			BIT(26)
> >>>> +#define GPIO45_FLASH_MODE_CFG			BIT(25)
> >>>> +#define GPIO44_FLASH_MODE_CFG			BIT(24)
> >>>> +#define GPIO43_FLASH_MODE_CFG			BIT(23)
> >>>> +#define GPIO42_FLASH_MODE_CFG			BIT(22)
> >>>> +#define GPIO41_FLASH_MODE_CFG			BIT(21)
> >>>> +#define GPIO40_FLASH_MODE_CFG			BIT(20)
> >>>> +#define GPIO39_FLASH_MODE_CFG			BIT(19)
> >>>> +#define GPIO38_FLASH_MODE_CFG			BIT(18)
> >>>> +#define GPIO37_FLASH_MODE_CFG			BIT(17)
> >>>> +#define GPIO36_FLASH_MODE_CFG			BIT(16)
> >>>> +#define GPIO31_FLASH_MODE_CFG			BIT(15)
> >>>> +#define GPIO30_FLASH_MODE_CFG			BIT(14)
> >>>> +#define GPIO29_FLASH_MODE_CFG			BIT(13)
> >>>> +#define GPIO28_FLASH_MODE_CFG			BIT(12)
> >>>> +#define GPIO27_FLASH_MODE_CFG			BIT(11)
> >>>> +#define GPIO26_FLASH_MODE_CFG			BIT(10)
> >>>> +#define GPIO25_FLASH_MODE_CFG			BIT(9)
> >>>> +#define GPIO24_FLASH_MODE_CFG			BIT(8)
> >>>> +#define GPIO23_FLASH_MODE_CFG			BIT(7)
> >>>> +#define GPIO22_FLASH_MODE_CFG			BIT(6)
> >>>> +#define GPIO21_FLASH_MODE_CFG			BIT(5)
> >>>> +#define GPIO20_FLASH_MODE_CFG			BIT(4)
> >>>> +#define GPIO19_FLASH_MODE_CFG			BIT(3)
> >>>> +#define GPIO18_FLASH_MODE_CFG			BIT(2)
> >>>> +#define GPIO17_FLASH_MODE_CFG			BIT(1)
> >>>> +#define GPIO16_FLASH_MODE_CFG			BIT(0)
> >>>> +
> >>>> +#define AIROHA_PINCTRL_GPIO(gpio, mux_val)			\
> >>>> +	{							\
> >>>> +		.name = (gpio),					\
> >>>> +		.regmap[0] = {					\
> >>>> +			AIROHA_FUNC_MUX,			\
> >>>> +			REG_GPIO_PON_MODE,			\
> >>>> +			(mux_val),				\
> >>>> +			(mux_val)				\
> >>>> +		},						\
> >>>> +		.regmap_size = 1,				\
> >>>> +	}
> >>>> +
> >>>> +#define AIROHA_PINCTRL_GPIO_EXT(gpio, mux_val, smux_val)	\
> >>>> +	{							\
> >>>> +		.name = (gpio),					\
> >>>> +		.regmap[0] = {					\
> >>>> +			AIROHA_FUNC_PWM_EXT_MUX,		\
> >>>> +			REG_GPIO_FLASH_MODE_CFG_EXT,		\
> >>>> +			(mux_val),				\
> >>>> +			0					\
> >>>> +		},						\
> >>>> +		.regmap[1] = {					\
> >>>> +			AIROHA_FUNC_MUX,			\
> >>>> +			REG_GPIO_PON_MODE,			\
> >>>> +			(smux_val),				\
> >>>> +			(smux_val)				\
> >>>> +		},						\
> >>>> +		.regmap_size = 2,				\
> >>>> +	}
> >>>> +
> >>>> +/* PWM */
> >>>> +#define AIROHA_PINCTRL_PWM(gpio, mux_val)			\
> >>>> +	{							\
> >>>> +		.name = (gpio),					\
> >>>> +		.regmap[0] = {					\
> >>>> +			AIROHA_FUNC_PWM_MUX,			\
> >>>> +			REG_GPIO_FLASH_MODE_CFG,		\
> >>>> +			(mux_val),				\
> >>>> +			(mux_val)				\
> >>>> +		},						\
> >>>> +		.regmap_size = 1,				\
> >>>> +	}
> >>>> +
> >>>> +#define AIROHA_PINCTRL_PWM_EXT(gpio, mux_val)			\
> >>>> +	{							\
> >>>> +		.name = (gpio),					\
> >>>> +		.regmap[0] = {					\
> >>>> +			AIROHA_FUNC_PWM_EXT_MUX,		\
> >>>> +			REG_GPIO_FLASH_MODE_CFG_EXT,		\
> >>>> +			(mux_val),				\
> >>>> +			(mux_val)				\
> >>>> +		},						\
> >>>> +		.regmap_size = 1,				\
> >>>> +	}
> >>>> +
> >>>> +#define AIROHA_PINCTRL_PWM_EXT_SEC(gpio, mux_val, smux_val)	\
> >>>> +	{							\
> >>>> +		.name = (gpio),					\
> >>>> +		.regmap[0] = {					\
> >>>> +			AIROHA_FUNC_PWM_EXT_MUX,		\
> >>>> +			REG_GPIO_FLASH_MODE_CFG_EXT,		\
> >>>> +			(mux_val),				\
> >>>> +			(mux_val)				\
> >>>> +		},						\
> >>>> +		.regmap[1] = {					\
> >>>> +			AIROHA_FUNC_MUX,			\
> >>>> +			REG_GPIO_PON_MODE,			\
> >>>> +			(smux_val),				\
> >>>> +			(smux_val)				\
> >>>> +		},						\
> >>>> +		.regmap_size = 2,				\
> >>>> +	}
> >>>> +
> >>>> +#define AIROHA_PINCTRL_PHY_LED0(gpio, mux_val, map_mask, map_val)	\
> >>>> +	{								\
> >>>> +		.name = (gpio),						\
> >>>> +		.regmap[0] = {						\
> >>>> +			AIROHA_FUNC_MUX,				\
> >>>> +			REG_GPIO_2ND_I2C_MODE,				\
> >>>> +			(mux_val),					\
> >>>> +			(mux_val),					\
> >>>> +		},							\
> >>>> +		.regmap[1] = {						\
> >>>> +			AIROHA_FUNC_MUX,				\
> >>>> +			REG_LAN_LED0_MAPPING,				\
> >>>> +			(map_mask),					\
> >>>> +			(map_val),					\
> >>>> +		},							\
> >>>> +		.regmap_size = 2,					\
> >>>> +	}
> >>>> +
> >>>> +#define AIROHA_PINCTRL_PHY_LED1(gpio, mux_val, map_mask, map_val)	\
> >>>> +	{								\
> >>>> +		.name = (gpio),						\
> >>>> +		.regmap[0] = {						\
> >>>> +			AIROHA_FUNC_MUX,				\
> >>>> +			REG_GPIO_2ND_I2C_MODE,				\
> >>>> +			(mux_val),					\
> >>>> +			(mux_val),					\
> >>>> +		},							\
> >>>> +		.regmap[1] = {						\
> >>>> +			AIROHA_FUNC_MUX,				\
> >>>> +			REG_LAN_LED1_MAPPING,				\
> >>>> +			(map_mask),					\
> >>>> +			(map_val),					\
> >>>> +		},							\
> >>>> +		.regmap_size = 2,					\
> >>>> +	}
> >>>> +
> >>>> +static struct pinctrl_pin_desc an7583_pinctrl_pins[] = {
> >>>> +	PINCTRL_PIN(2, "gpio0"),
> >>>> +	PINCTRL_PIN(3, "gpio1"),
> >>>> +	PINCTRL_PIN(4, "gpio2"),
> >>>> +	PINCTRL_PIN(5, "gpio3"),
> >>>> +	PINCTRL_PIN(6, "gpio4"),
> >>>> +	PINCTRL_PIN(7, "gpio5"),
> >>>> +	PINCTRL_PIN(8, "gpio6"),
> >>>> +	PINCTRL_PIN(9, "gpio7"),
> >>>> +	PINCTRL_PIN(10, "gpio8"),
> >>>> +	PINCTRL_PIN(11, "gpio9"),
> >>>> +	PINCTRL_PIN(12, "gpio10"),
> >>>> +	PINCTRL_PIN(13, "gpio11"),
> >>>> +	PINCTRL_PIN(14, "gpio12"),
> >>>> +	PINCTRL_PIN(15, "gpio13"),
> >>>> +	PINCTRL_PIN(16, "gpio14"),
> >>>> +	PINCTRL_PIN(17, "gpio15"),
> >>>> +	PINCTRL_PIN(18, "gpio16"),
> >>>> +	PINCTRL_PIN(19, "gpio17"),
> >>>> +	PINCTRL_PIN(20, "gpio18"),
> >>>> +	PINCTRL_PIN(21, "gpio19"),
> >>>> +	PINCTRL_PIN(22, "gpio20"),
> >>>> +	PINCTRL_PIN(23, "gpio21"),
> >>>> +	PINCTRL_PIN(24, "gpio22"),
> >>>> +	PINCTRL_PIN(25, "gpio23"),
> >>>> +	PINCTRL_PIN(26, "gpio24"),
> >>>> +	PINCTRL_PIN(27, "gpio25"),
> >>>> +	PINCTRL_PIN(28, "gpio26"),
> >>>> +	PINCTRL_PIN(29, "gpio27"),
> >>>> +	PINCTRL_PIN(30, "gpio28"),
> >>>> +	PINCTRL_PIN(31, "gpio29"),
> >>>> +	PINCTRL_PIN(32, "gpio30"),
> >>>> +	PINCTRL_PIN(33, "gpio31"),
> >>>> +	PINCTRL_PIN(34, "gpio32"),
> >>>> +	PINCTRL_PIN(35, "gpio33"),
> >>>> +	PINCTRL_PIN(36, "gpio34"),
> >>>> +	PINCTRL_PIN(37, "gpio35"),
> >>>> +	PINCTRL_PIN(38, "gpio36"),
> >>>> +	PINCTRL_PIN(39, "gpio37"),
> >>>> +	PINCTRL_PIN(40, "gpio38"),
> >>>> +	PINCTRL_PIN(41, "i2c0_scl"),
> >>>> +	PINCTRL_PIN(42, "i2c0_sda"),
> >>>> +	PINCTRL_PIN(43, "i2c1_scl"),
> >>>> +	PINCTRL_PIN(44, "i2c1_sda"),
> >>>> +	PINCTRL_PIN(45, "spi_clk"),
> >>>> +	PINCTRL_PIN(46, "spi_cs"),
> >>>> +	PINCTRL_PIN(47, "spi_mosi"),
> >>>> +	PINCTRL_PIN(48, "spi_miso"),
> >>>> +	PINCTRL_PIN(49, "uart_txd"),
> >>>> +	PINCTRL_PIN(50, "uart_rxd"),
> >>>> +	PINCTRL_PIN(51, "pcie_reset0"),
> >>>> +	PINCTRL_PIN(52, "pcie_reset1"),
> >>>> +	PINCTRL_PIN(53, "mdc_0"),
> >>>> +	PINCTRL_PIN(54, "mdio_0"),
> >>>> +};
> >>>> +
> >>>> +static const int an7583_pon_pins[] = { 15, 16, 17, 18, 19, 20 };
> >>>> +static const int an7583_pon_tod_1pps_pins[] = { 32 };
> >>>> +static const int an7583_gsw_tod_1pps_pins[] = { 32 };
> >>>> +static const int an7583_sipo_pins[] = { 34, 35 };
> >>>> +static const int an7583_sipo_rclk_pins[] = { 34, 35, 33 };
> >>>> +static const int an7583_mdio_pins[] = { 43, 44 };
> >>>> +static const int an7583_uart2_pins[] = { 34, 35 };
> >>>> +static const int an7583_uart2_cts_rts_pins[] = { 32, 33 };
> >>>> +static const int an7583_hsuart_pins[] = { 30, 31 };
> >>>> +static const int an7583_hsuart_cts_rts_pins[] = { 28, 29 };
> >>>> +static const int an7583_npu_uart_pins[] = { 7, 8 };
> >>>> +static const int an7583_uart4_pins[] = { 7, 8 };
> >>>> +static const int an7583_uart5_pins[] = { 23, 24 };
> >>>> +static const int an7583_i2c0_pins[] = { 41, 42 };
> >>>> +static const int an7583_i2c1_pins[] = { 43, 44 };
> >>>> +static const int an7583_jtag_udi_pins[] = { 23, 24, 22, 25, 26 };
> >>>> +static const int an7583_jtag_dfd_pins[] = { 23, 24, 22, 25, 26 };
> >>>> +static const int an7583_pcm1_pins[] = { 10, 11, 12, 13, 14 };
> >>>> +static const int an7583_pcm2_pins[] = { 28, 29, 30, 31, 24 };
> >>>> +static const int an7583_spi_pins[] = { 28, 29, 30, 31 };
> >>>> +static const int an7583_spi_quad_pins[] = { 25, 26 };
> >>>> +static const int an7583_spi_cs1_pins[] = { 27 };
> >>>> +static const int an7583_pcm_spi_pins[] = { 28, 29, 30, 31, 10, 11, 12, 13 };
> >>>> +static const int an7583_pcm_spi_rst_pins[] = { 14 };
> >>>> +static const int an7583_pcm_spi_cs1_pins[] = { 24 };
> >>>> +static const int an7583_emmc_pins[] = {
> >>>> +	7, 8, 9, 22, 23, 24, 25, 26, 45, 46, 47
> >>>> +};
> >>>> +static const int an7583_pnand_pins[] = {
> >>>> +	7, 8, 9, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 45, 46, 47, 48
> >>>> +};
> >>>> +static const int an7583_gpio0_pins[] = { 2 };
> >>>> +static const int an7583_gpio1_pins[] = { 3 };
> >>>> +static const int an7583_gpio2_pins[] = { 4 };
> >>>> +static const int an7583_gpio3_pins[] = { 5 };
> >>>> +static const int an7583_gpio4_pins[] = { 6 };
> >>>> +static const int an7583_gpio5_pins[] = { 7 };
> >>>> +static const int an7583_gpio6_pins[] = { 8 };
> >>>> +static const int an7583_gpio7_pins[] = { 9 };
> >>>> +static const int an7583_gpio8_pins[] = { 10 };
> >>>> +static const int an7583_gpio9_pins[] = { 11 };
> >>>> +static const int an7583_gpio10_pins[] = { 12 };
> >>>> +static const int an7583_gpio11_pins[] = { 13 };
> >>>> +static const int an7583_gpio12_pins[] = { 14 };
> >>>> +static const int an7583_gpio13_pins[] = { 15 };
> >>>> +static const int an7583_gpio14_pins[] = { 16 };
> >>>> +static const int an7583_gpio15_pins[] = { 17 };
> >>>> +static const int an7583_gpio16_pins[] = { 18 };
> >>>> +static const int an7583_gpio17_pins[] = { 19 };
> >>>> +static const int an7583_gpio18_pins[] = { 20 };
> >>>> +static const int an7583_gpio19_pins[] = { 21 };
> >>>> +static const int an7583_gpio20_pins[] = { 22 };
> >>>> +static const int an7583_gpio21_pins[] = { 23 };
> >>>> +static const int an7583_gpio22_pins[] = { 24 };
> >>>> +static const int an7583_gpio23_pins[] = { 25 };
> >>>> +static const int an7583_gpio24_pins[] = { 26 };
> >>>> +static const int an7583_gpio25_pins[] = { 27 };
> >>>> +static const int an7583_gpio26_pins[] = { 28 };
> >>>> +static const int an7583_gpio27_pins[] = { 29 };
> >>>> +static const int an7583_gpio28_pins[] = { 30 };
> >>>> +static const int an7583_gpio29_pins[] = { 31 };
> >>>> +static const int an7583_gpio30_pins[] = { 32 };
> >>>> +static const int an7583_gpio31_pins[] = { 33 };
> >>>> +static const int an7583_gpio32_pins[] = { 34 };
> >>>> +static const int an7583_gpio33_pins[] = { 35 };
> >>>> +static const int an7583_gpio34_pins[] = { 36 };
> >>>> +static const int an7583_gpio35_pins[] = { 37 };
> >>>> +static const int an7583_gpio36_pins[] = { 38 };
> >>>> +static const int an7583_gpio37_pins[] = { 39 };
> >>>> +static const int an7583_gpio38_pins[] = { 40 };
> >>>> +static const int an7583_gpio39_pins[] = { 41 };
> >>>> +static const int an7583_gpio40_pins[] = { 42 };
> >>>> +static const int an7583_gpio41_pins[] = { 43 };
> >>>> +static const int an7583_gpio42_pins[] = { 44 };
> >>>> +static const int an7583_gpio43_pins[] = { 45 };
> >>>> +static const int an7583_gpio44_pins[] = { 46 };
> >>>> +static const int an7583_gpio45_pins[] = { 47 };
> >>>> +static const int an7583_gpio46_pins[] = { 48 };
> >>>> +static const int an7583_gpio47_pins[] = { 49 };
> >>>> +static const int an7583_gpio48_pins[] = { 50 };
> >>>> +static const int an7583_gpio49_pins[] = { 51 };
> >>>> +static const int an7583_gpio50_pins[] = { 52 };
> >>>> +static const int an7583_gpio51_pins[] = { 53 };
> >>>> +static const int an7583_gpio52_pins[] = { 54 };
> >>>> +static const int an7583_pcie_reset0_pins[] = { 51 };
> >>>> +static const int an7583_pcie_reset1_pins[] = { 52 };
> >>>> +
> >>>> +static const struct pingroup an7583_pinctrl_groups[] = {
> >>>> +	PINCTRL_PIN_GROUP("pon", an7583_pon),
> >>>> +	PINCTRL_PIN_GROUP("pon_tod_1pps", an7583_pon_tod_1pps),
> >>>> +	PINCTRL_PIN_GROUP("gsw_tod_1pps", an7583_gsw_tod_1pps),
> >>>> +	PINCTRL_PIN_GROUP("sipo", an7583_sipo),
> >>>> +	PINCTRL_PIN_GROUP("sipo_rclk", an7583_sipo_rclk),
> >>>> +	PINCTRL_PIN_GROUP("mdio", an7583_mdio),
> >>>> +	PINCTRL_PIN_GROUP("uart2", an7583_uart2),
> >>>> +	PINCTRL_PIN_GROUP("uart2_cts_rts", an7583_uart2_cts_rts),
> >>>> +	PINCTRL_PIN_GROUP("hsuart", an7583_hsuart),
> >>>> +	PINCTRL_PIN_GROUP("hsuart_cts_rts", an7583_hsuart_cts_rts),
> >>>> +	PINCTRL_PIN_GROUP("npu_uart", an7583_npu_uart),
> >>>> +	PINCTRL_PIN_GROUP("uart4", an7583_uart4),
> >>>> +	PINCTRL_PIN_GROUP("uart5", an7583_uart5),
> >>>> +	PINCTRL_PIN_GROUP("i2c0", an7583_i2c0),
> >>>> +	PINCTRL_PIN_GROUP("i2c1", an7583_i2c1),
> >>>> +	PINCTRL_PIN_GROUP("jtag_udi", an7583_jtag_udi),
> >>>> +	PINCTRL_PIN_GROUP("jtag_dfd", an7583_jtag_dfd),
> >>>> +	PINCTRL_PIN_GROUP("pcm1", an7583_pcm1),
> >>>> +	PINCTRL_PIN_GROUP("pcm2", an7583_pcm2),
> >>>> +	PINCTRL_PIN_GROUP("spi", an7583_spi),
> >>>> +	PINCTRL_PIN_GROUP("spi_quad", an7583_spi_quad),
> >>>> +	PINCTRL_PIN_GROUP("spi_cs1", an7583_spi_cs1),
> >>>> +	PINCTRL_PIN_GROUP("pcm_spi", an7583_pcm_spi),
> >>>> +	PINCTRL_PIN_GROUP("pcm_spi_rst", an7583_pcm_spi_rst),
> >>>> +	PINCTRL_PIN_GROUP("pcm_spi_cs1", an7583_pcm_spi_cs1),
> >>>> +	PINCTRL_PIN_GROUP("emmc", an7583_emmc),
> >>>> +	PINCTRL_PIN_GROUP("pnand", an7583_pnand),
> >>>> +	PINCTRL_PIN_GROUP("gpio0", an7583_gpio0),
> >>>> +	PINCTRL_PIN_GROUP("gpio1", an7583_gpio1),
> >>>> +	PINCTRL_PIN_GROUP("gpio2", an7583_gpio2),
> >>>> +	PINCTRL_PIN_GROUP("gpio3", an7583_gpio3),
> >>>> +	PINCTRL_PIN_GROUP("gpio4", an7583_gpio4),
> >>>> +	PINCTRL_PIN_GROUP("gpio5", an7583_gpio5),
> >>>> +	PINCTRL_PIN_GROUP("gpio6", an7583_gpio6),
> >>>> +	PINCTRL_PIN_GROUP("gpio7", an7583_gpio7),
> >>>> +	PINCTRL_PIN_GROUP("gpio8", an7583_gpio8),
> >>>> +	PINCTRL_PIN_GROUP("gpio9", an7583_gpio9),
> >>>> +	PINCTRL_PIN_GROUP("gpio10", an7583_gpio10),
> >>>> +	PINCTRL_PIN_GROUP("gpio11", an7583_gpio11),
> >>>> +	PINCTRL_PIN_GROUP("gpio12", an7583_gpio12),
> >>>> +	PINCTRL_PIN_GROUP("gpio13", an7583_gpio13),
> >>>> +	PINCTRL_PIN_GROUP("gpio14", an7583_gpio14),
> >>>> +	PINCTRL_PIN_GROUP("gpio15", an7583_gpio15),
> >>>> +	PINCTRL_PIN_GROUP("gpio16", an7583_gpio16),
> >>>> +	PINCTRL_PIN_GROUP("gpio17", an7583_gpio17),
> >>>> +	PINCTRL_PIN_GROUP("gpio18", an7583_gpio18),
> >>>> +	PINCTRL_PIN_GROUP("gpio19", an7583_gpio19),
> >>>> +	PINCTRL_PIN_GROUP("gpio20", an7583_gpio20),
> >>>> +	PINCTRL_PIN_GROUP("gpio21", an7583_gpio21),
> >>>> +	PINCTRL_PIN_GROUP("gpio22", an7583_gpio22),
> >>>> +	PINCTRL_PIN_GROUP("gpio23", an7583_gpio23),
> >>>> +	PINCTRL_PIN_GROUP("gpio24", an7583_gpio24),
> >>>> +	PINCTRL_PIN_GROUP("gpio25", an7583_gpio25),
> >>>> +	PINCTRL_PIN_GROUP("gpio26", an7583_gpio26),
> >>>> +	PINCTRL_PIN_GROUP("gpio27", an7583_gpio27),
> >>>> +	PINCTRL_PIN_GROUP("gpio28", an7583_gpio28),
> >>>> +	PINCTRL_PIN_GROUP("gpio29", an7583_gpio29),
> >>>> +	PINCTRL_PIN_GROUP("gpio30", an7583_gpio30),
> >>>> +	PINCTRL_PIN_GROUP("gpio31", an7583_gpio31),
> >>>> +	PINCTRL_PIN_GROUP("gpio32", an7583_gpio32),
> >>>> +	PINCTRL_PIN_GROUP("gpio33", an7583_gpio33),
> >>>> +	PINCTRL_PIN_GROUP("gpio34", an7583_gpio34),
> >>>> +	PINCTRL_PIN_GROUP("gpio35", an7583_gpio35),
> >>>> +	PINCTRL_PIN_GROUP("gpio36", an7583_gpio36),
> >>>> +	PINCTRL_PIN_GROUP("gpio37", an7583_gpio37),
> >>>> +	PINCTRL_PIN_GROUP("gpio38", an7583_gpio38),
> >>>> +	PINCTRL_PIN_GROUP("gpio39", an7583_gpio39),
> >>>> +	PINCTRL_PIN_GROUP("gpio40", an7583_gpio40),
> >>>> +	PINCTRL_PIN_GROUP("gpio41", an7583_gpio41),
> >>>> +	PINCTRL_PIN_GROUP("gpio42", an7583_gpio42),
> >>>> +	PINCTRL_PIN_GROUP("gpio43", an7583_gpio43),
> >>>> +	PINCTRL_PIN_GROUP("gpio44", an7583_gpio44),
> >>>> +	PINCTRL_PIN_GROUP("gpio45", an7583_gpio45),
> >>>> +	PINCTRL_PIN_GROUP("gpio46", an7583_gpio46),
> >>>> +	PINCTRL_PIN_GROUP("gpio47", an7583_gpio47),
> >>>> +	PINCTRL_PIN_GROUP("gpio48", an7583_gpio48),
> >>>> +	PINCTRL_PIN_GROUP("gpio49", an7583_gpio49),
> >>>> +	PINCTRL_PIN_GROUP("gpio50", an7583_gpio50),
> >>>> +	PINCTRL_PIN_GROUP("gpio51", an7583_gpio51),
> >>>> +	PINCTRL_PIN_GROUP("gpio52", an7583_gpio52),
> >>>> +	PINCTRL_PIN_GROUP("pcie_reset0", an7583_pcie_reset0),
> >>>> +	PINCTRL_PIN_GROUP("pcie_reset1", an7583_pcie_reset1),
> >>>> +};
> >>>> +
> >>>> +static const char *const pon_groups[] = { "pon" };
> >>>> +static const char *const tod_1pps_groups[] = {
> >>>> +	"pon_tod_1pps", "gsw_tod_1pps"
> >>>> +};
> >>>> +static const char *const sipo_groups[] = { "sipo", "sipo_rclk" };
> >>>> +static const char *const an7583_mdio_groups[] = { "mdio" };
> >>>> +static const char *const uart_groups[] = {
> >>>> +	"uart2", "uart2_cts_rts", "hsuart", "hsuart_cts_rts",
> >>>> +	"uart4", "uart5"
> >>>> +};
> >>>> +static const char *const jtag_groups[] = { "jtag_udi", "jtag_dfd" };
> >>>> +static const char *const pcm_groups[] = { "pcm1", "pcm2" };
> >>>> +static const char *const spi_groups[] = { "spi_quad", "spi_cs1" };
> >>>> +static const char *const an7583_pcm_spi_groups[] = {
> >>>> +	"pcm_spi", "pcm_spi_rst", "pcm_spi_cs1"
> >>>> +};
> >>>> +static const char *const emmc_groups[] = { "emmc" };
> >>>> +static const char *const pnand_groups[] = { "pnand" };
> >>>> +static const char *const an7583_gpio_groups[] = {
> >>>> +	"gpio39", "gpio40", "gpio41", "gpio42", "gpio43",
> >>>> +	"gpio44", "gpio45", "gpio46", "gpio47", "gpio48",
> >>>> +	"gpio49", "gpio50", "gpio51", "gpio52"
> >>>> +};
> >>>> +static const char *const an7583_pcie_reset_groups[] = {
> >>>> +	"pcie_reset0", "pcie_reset1"
> >>>> +};
> >>>> +static const char *const an7583_pwm_groups[] = {
> >>>> +	"gpio0",  "gpio1",  "gpio2",  "gpio3",  "gpio4",  "gpio5",
> >>>> +	"gpio6",  "gpio7",  "gpio8",  "gpio9",  "gpio10", "gpio11",
> >>>> +	"gpio12", "gpio13", "gpio14", "gpio15", "gpio16", "gpio17",
> >>>> +	"gpio18", "gpio19", "gpio20", "gpio21", "gpio22", "gpio23",
> >>>> +	"gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29",
> >>>> +	"gpio30", "gpio31", "gpio36", "gpio37", "gpio38", "gpio39",
> >>>> +	"gpio40", "gpio41", "gpio42", "gpio43", "gpio44", "gpio45",
> >>>> +	"gpio46", "gpio47", "gpio48", "gpio49", "gpio50", "gpio51"
> >>>> +};
> >>>> +static const char *const an7583_phy1_led0_groups[] = {
> >>>> +	"gpio1", "gpio2", "gpio3", "gpio4"
> >>>> +};
> >>>> +static const char *const an7583_phy2_led0_groups[] = {
> >>>> +	"gpio1", "gpio2", "gpio3", "gpio4"
> >>>> +};
> >>>> +static const char *const an7583_phy3_led0_groups[] = {
> >>>> +	"gpio1", "gpio2", "gpio3", "gpio4"
> >>>> +};
> >>>> +static const char *const an7583_phy4_led0_groups[] = {
> >>>> +	"gpio1", "gpio2", "gpio3", "gpio4"
> >>>> +};
> >>>> +static const char *const an7583_phy1_led1_groups[] = {
> >>>> +	"gpio8", "gpio9", "gpio10", "gpio11"
> >>>> +};
> >>>> +static const char *const an7583_phy2_led1_groups[] = {
> >>>> +	"gpio8", "gpio9", "gpio10", "gpio11"
> >>>> +};
> >>>> +static const char *const an7583_phy3_led1_groups[] = {
> >>>> +	"gpio8", "gpio9", "gpio10", "gpio11"
> >>>> +};
> >>>> +static const char *const an7583_phy4_led1_groups[] = {
> >>>> +	"gpio8", "gpio9", "gpio10", "gpio11"
> >>>> +};
> >>>> +
> >>>> +static const struct airoha_pinctrl_func_group pon_func_group[] = {
> >>>> +	{
> >>>> +		.name = "pon",
> >>>> +		.regmap[0] = {
> >>>> +			AIROHA_FUNC_MUX,
> >>>> +			REG_GPIO_PON_MODE,
> >>>> +			GPIO_PON_MODE_MASK,
> >>>> +			GPIO_PON_MODE_MASK
> >>>> +		},
> >>>> +		.regmap_size = 1,
> >>>> +	},
> >>>> +};
> >>>> +
> >>>> +static const struct airoha_pinctrl_func_group tod_1pps_func_group[] = {
> >>>> +	{
> >>>> +		.name = "pon_tod_1pps",
> >>>> +		.regmap[0] = {
> >>>> +			AIROHA_FUNC_MUX,
> >>>> +			REG_GPIO_2ND_I2C_MODE,
> >>>> +			PON_TOD_1PPS_MODE_MASK,
> >>>> +			PON_TOD_1PPS_MODE_MASK
> >>>> +		},
> >>>> +		.regmap_size = 1,
> >>>> +	}, {
> >>>> +		.name = "gsw_tod_1pps",
> >>>> +		.regmap[0] = {
> >>>> +			AIROHA_FUNC_MUX,
> >>>> +			REG_GPIO_2ND_I2C_MODE,
> >>>> +			GSW_TOD_1PPS_MODE_MASK,
> >>>> +			GSW_TOD_1PPS_MODE_MASK
> >>>> +		},
> >>>> +		.regmap_size = 1,
> >>>> +	},
> >>>> +};
> >>>> +
> >>>> +static const struct airoha_pinctrl_func_group sipo_func_group[] = {
> >>>> +	{
> >>>> +		.name = "sipo",
> >>>> +		.regmap[0] = {
> >>>> +			AIROHA_FUNC_MUX,
> >>>> +			REG_GPIO_PON_MODE,
> >>>> +			GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK,
> >>>> +			GPIO_SIPO_MODE_MASK
> >>>> +		},
> >>>> +		.regmap_size = 1,
> >>>> +	}, {
> >>>> +		.name = "sipo_rclk",
> >>>> +		.regmap[0] = {
> >>>> +			AIROHA_FUNC_MUX,
> >>>> +			REG_GPIO_PON_MODE,
> >>>> +			GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK,
> >>>> +			GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK
> >>>> +		},
> >>>> +		.regmap_size = 1,
> >>>> +	},
> >>>> +};
> >>>> +
> >>>> +static const struct airoha_pinctrl_func_group an7583_mdio_func_group[] = {
> >>>> +	{
> >>>> +		.name = "mdio",
> >>>> +		.regmap[0] = {
> >>>> +			AIROHA_FUNC_MUX,
> >>>> +			REG_GPIO_PON_MODE,
> >>>> +			GPIO_SGMII_MDIO_MODE_MASK,
> >>>> +			GPIO_SGMII_MDIO_MODE_MASK
> >>>> +		},
> >>>> +		.regmap[1] = {
> >>>> +			AIROHA_FUNC_MUX,
> >>>> +			REG_GPIO_SPI_CS1_MODE,
> >>>> +			GPIO_MDC_IO_MASTER_MODE_MASK,
> >>>> +			GPIO_MDC_IO_MASTER_MODE_MASK
> >>>> +		},
> >>>> +		.regmap_size = 2,
> >>>> +	},
> >>>> +};
> >>>> +
> >>>> +static const struct airoha_pinctrl_func_group uart_func_group[] = {
> >>>> +	{
> >>>> +		.name = "uart2",
> >>>> +		.regmap[0] = {
> >>>> +			AIROHA_FUNC_MUX,
> >>>> +			REG_GPIO_PON_MODE,
> >>>> +			GPIO_UART2_MODE_MASK,
> >>>> +			GPIO_UART2_MODE_MASK
> >>>> +		},
> >>>> +		.regmap_size = 1,
> >>>> +	}, {
> >>>> +		.name = "uart2_cts_rts",
> >>>> +		.regmap[0] = {
> >>>> +			AIROHA_FUNC_MUX,
> >>>> +			REG_GPIO_PON_MODE,
> >>>> +			GPIO_UART2_MODE_MASK | GPIO_UART2_CTS_RTS_MODE_MASK,
> >>>> +			GPIO_UART2_MODE_MASK | GPIO_UART2_CTS_RTS_MODE_MASK
> >>>> +		},
> >>>> +		.regmap_size = 1,
> >>>> +	}, {
> >>>> +		.name = "hsuart",
> >>>> +		.regmap[0] = {
> >>>> +			AIROHA_FUNC_MUX,
> >>>> +			REG_GPIO_PON_MODE,
> >>>> +			GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK,
> >>>> +			GPIO_HSUART_MODE_MASK
> >>>> +		},
> >>>> +		.regmap_size = 1,
> >>>> +	},
> >>>> +	{
> >>>> +		.name = "hsuart_cts_rts",
> >>>> +		.regmap[0] = {
> >>>> +			AIROHA_FUNC_MUX,
> >>>> +			REG_GPIO_PON_MODE,
> >>>> +			GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK,
> >>>> +			GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK
> >>>> +		},
> >>>> +		.regmap_size = 1,
> >>>> +	}, {
> >>>> +		.name = "uart4",
> >>>> +		.regmap[0] = {
> >>>> +			AIROHA_FUNC_MUX,
> >>>> +			REG_GPIO_PON_MODE,
> >>>> +			GPIO_UART4_MODE_MASK,
> >>>> +			GPIO_UART4_MODE_MASK
> >>>> +		},
> >>>> +		.regmap_size = 1,
> >>>> +	}, {
> >>>> +		.name = "uart5",
> >>>> +		.regmap[0] = {
> >>>> +			AIROHA_FUNC_MUX,
> >>>> +			REG_GPIO_PON_MODE,
> >>>> +			GPIO_UART5_MODE_MASK,
> >>>> +			GPIO_UART5_MODE_MASK
> >>>> +		},
> >>>> +		.regmap_size = 1,
> >>>> +	},
> >>>> +};
> >>>> +
> >>>> +static const struct airoha_pinctrl_func_group jtag_func_group[] = {
> >>>> +	{
> >>>> +		.name = "jtag_udi",
> >>>> +		.regmap[0] = {
> >>>> +			AIROHA_FUNC_MUX,
> >>>> +			REG_NPU_UART_EN,
> >>>> +			JTAG_UDI_EN_MASK,
> >>>> +			JTAG_UDI_EN_MASK
> >>>> +		},
> >>>> +		.regmap_size = 1,
> >>>> +	}, {
> >>>> +		.name = "jtag_dfd",
> >>>> +		.regmap[0] = {
> >>>> +			AIROHA_FUNC_MUX,
> >>>> +			REG_NPU_UART_EN,
> >>>> +			JTAG_DFD_EN_MASK,
> >>>> +			JTAG_DFD_EN_MASK
> >>>> +		},
> >>>> +		.regmap_size = 1,
> >>>> +	},
> >>>> +};
> >>>> +
> >>>> +static const struct airoha_pinctrl_func_group pcm_func_group[] = {
> >>>> +	{
> >>>> +		.name = "pcm1",
> >>>> +		.regmap[0] = {
> >>>> +			AIROHA_FUNC_MUX,
> >>>> +			REG_GPIO_SPI_CS1_MODE,
> >>>> +			GPIO_PCM1_MODE_MASK,
> >>>> +			GPIO_PCM1_MODE_MASK
> >>>> +		},
> >>>> +		.regmap_size = 1,
> >>>> +	}, {
> >>>> +		.name = "pcm2",
> >>>> +		.regmap[0] = {
> >>>> +			AIROHA_FUNC_MUX,
> >>>> +			REG_GPIO_SPI_CS1_MODE,
> >>>> +			GPIO_PCM2_MODE_MASK,
> >>>> +			GPIO_PCM2_MODE_MASK
> >>>> +		},
> >>>> +		.regmap_size = 1,
> >>>> +	},
> >>>> +};
> >>>> +
> >>>> +static const struct airoha_pinctrl_func_group spi_func_group[] = {
> >>>> +	{
> >>>> +		.name = "spi_quad",
> >>>> +		.regmap[0] = {
> >>>> +			AIROHA_FUNC_MUX,
> >>>> +			REG_GPIO_SPI_CS1_MODE,
> >>>> +			GPIO_SPI_QUAD_MODE_MASK,
> >>>> +			GPIO_SPI_QUAD_MODE_MASK
> >>>> +		},
> >>>> +		.regmap_size = 1,
> >>>> +	}, {
> >>>> +		.name = "spi_cs1",
> >>>> +		.regmap[0] = {
> >>>> +			AIROHA_FUNC_MUX,
> >>>> +			REG_GPIO_SPI_CS1_MODE,
> >>>> +			GPIO_SPI_CS1_MODE_MASK,
> >>>> +			GPIO_SPI_CS1_MODE_MASK
> >>>> +		},
> >>>> +		.regmap_size = 1,
> >>>> +	}, {
> >>>> +		.name = "spi_cs2",
> >>>> +		.regmap[0] = {
> >>>> +			AIROHA_FUNC_MUX,
> >>>> +			REG_GPIO_SPI_CS1_MODE,
> >>>> +			GPIO_SPI_CS2_MODE_MASK,
> >>>> +			GPIO_SPI_CS2_MODE_MASK
> >>>> +		},
> >>>> +		.regmap_size = 1,
> >>>> +	}, {
> >>>> +		.name = "spi_cs3",
> >>>> +		.regmap[0] = {
> >>>> +			AIROHA_FUNC_MUX,
> >>>> +			REG_GPIO_SPI_CS1_MODE,
> >>>> +			GPIO_SPI_CS3_MODE_MASK,
> >>>> +			GPIO_SPI_CS3_MODE_MASK
> >>>> +		},
> >>>> +		.regmap_size = 1,
> >>>> +	}, {
> >>>> +		.name = "spi_cs4",
> >>>> +		.regmap[0] = {
> >>>> +			AIROHA_FUNC_MUX,
> >>>> +			REG_GPIO_SPI_CS1_MODE,
> >>>> +			GPIO_SPI_CS4_MODE_MASK,
> >>>> +			GPIO_SPI_CS4_MODE_MASK
> >>>> +		},
> >>>> +		.regmap_size = 1,
> >>>> +	},
> >>>> +};
> >>>> +
> >>>> +static const struct airoha_pinctrl_func_group an7583_pcm_spi_func_group[] = {
> >>>> +	{
> >>>> +		.name = "pcm_spi",
> >>>> +		.regmap[0] = {
> >>>> +			AIROHA_FUNC_MUX,
> >>>> +			REG_GPIO_SPI_CS1_MODE,
> >>>> +			GPIO_PCM_SPI_MODE_MASK,
> >>>> +			GPIO_PCM_SPI_MODE_MASK
> >>>> +		},
> >>>> +		.regmap_size = 1,
> >>>> +	}, {
> >>>> +		.name = "pcm_spi_int",
> >>>> +		.regmap[0] = {
> >>>> +			AIROHA_FUNC_MUX,
> >>>> +			REG_GPIO_SPI_CS1_MODE,
> >>>> +			GPIO_PCM_INT_MODE_MASK,
> >>>> +			GPIO_PCM_INT_MODE_MASK
> >>>> +		},
> >>>> +		.regmap_size = 1,
> >>>> +	}, {
> >>>> +		.name = "pcm_spi_rst",
> >>>> +		.regmap[0] = {
> >>>> +			AIROHA_FUNC_MUX,
> >>>> +			REG_GPIO_SPI_CS1_MODE,
> >>>> +			GPIO_PCM_RESET_MODE_MASK,
> >>>> +			GPIO_PCM_RESET_MODE_MASK
> >>>> +		},
> >>>> +		.regmap_size = 1,
> >>>> +	}, {
> >>>> +		.name = "pcm_spi_cs1",
> >>>> +		.regmap[0] = {
> >>>> +			AIROHA_FUNC_MUX,
> >>>> +			REG_GPIO_SPI_CS1_MODE,
> >>>> +			GPIO_PCM_SPI_CS1_MODE_MASK,
> >>>> +			GPIO_PCM_SPI_CS1_MODE_MASK
> >>>> +		},
> >>>> +		.regmap_size = 1,
> >>>> +	}, {
> >>>> +		.name = "pcm_spi_cs2",
> >>>> +		.regmap[0] = {
> >>>> +			AIROHA_FUNC_MUX,
> >>>> +			REG_GPIO_SPI_CS1_MODE,
> >>>> +			AN7583_GPIO_PCM_SPI_CS2_MODE_MASK,
> >>>> +			AN7583_GPIO_PCM_SPI_CS2_MODE_MASK
> >>>> +		},
> >>>> +		.regmap_size = 1,
> >>>> +	}, {
> >>>> +		.name = "pcm_spi_cs3",
> >>>> +		.regmap[0] = {
> >>>> +			AIROHA_FUNC_MUX,
> >>>> +			REG_GPIO_SPI_CS1_MODE,
> >>>> +			GPIO_PCM_SPI_CS3_MODE_MASK,
> >>>> +			GPIO_PCM_SPI_CS3_MODE_MASK
> >>>> +		},
> >>>> +		.regmap_size = 1,
> >>>> +	}, {
> >>>> +		.name = "pcm_spi_cs4",
> >>>> +		.regmap[0] = {
> >>>> +			AIROHA_FUNC_MUX,
> >>>> +			REG_GPIO_SPI_CS1_MODE,
> >>>> +			GPIO_PCM_SPI_CS4_MODE_MASK,
> >>>> +			GPIO_PCM_SPI_CS4_MODE_MASK
> >>>> +		},
> >>>> +		.regmap_size = 1,
> >>>> +	},
> >>>> +};
> >>>> +
> >>>> +static const struct airoha_pinctrl_func_group emmc_func_group[] = {
> >>>> +	{
> >>>> +		.name = "emmc",
> >>>> +		.regmap[0] = {
> >>>> +			AIROHA_FUNC_MUX,
> >>>> +			REG_GPIO_PON_MODE,
> >>>> +			GPIO_EMMC_MODE_MASK,
> >>>> +			GPIO_EMMC_MODE_MASK
> >>>> +		},
> >>>> +		.regmap_size = 1,
> >>>> +	},
> >>>> +};
> >>>> +
> >>>> +static const struct airoha_pinctrl_func_group pnand_func_group[] = {
> >>>> +	{
> >>>> +		.name = "pnand",
> >>>> +		.regmap[0] = {
> >>>> +			AIROHA_FUNC_MUX,
> >>>> +			REG_GPIO_PON_MODE,
> >>>> +			GPIO_PARALLEL_NAND_MODE_MASK,
> >>>> +			GPIO_PARALLEL_NAND_MODE_MASK
> >>>> +		},
> >>>> +		.regmap_size = 1,
> >>>> +	},
> >>>> +};
> >>>> +
> >>>> +static const struct airoha_pinctrl_func_group an7583_gpio_func_group[] = {
> >>>> +	AIROHA_PINCTRL_GPIO_EXT("gpio39", GPIO39_FLASH_MODE_CFG,
> >>>> +				AN7583_I2C0_SCL_GPIO_MODE_MASK),
> >>>> +	AIROHA_PINCTRL_GPIO_EXT("gpio40", GPIO40_FLASH_MODE_CFG,
> >>>> +				AN7583_I2C0_SDA_GPIO_MODE_MASK),
> >>>> +	AIROHA_PINCTRL_GPIO_EXT("gpio41", GPIO41_FLASH_MODE_CFG,
> >>>> +				AN7583_I2C1_SCL_GPIO_MODE_MASK),
> >>>> +	AIROHA_PINCTRL_GPIO_EXT("gpio42", GPIO42_FLASH_MODE_CFG,
> >>>> +				AN7583_I2C1_SDA_GPIO_MODE_MASK),
> >>>> +	AIROHA_PINCTRL_GPIO_EXT("gpio43", GPIO43_FLASH_MODE_CFG,
> >>>> +				AN7583_SPI_CLK_GPIO_MODE_MASK),
> >>>> +	AIROHA_PINCTRL_GPIO_EXT("gpio44", GPIO44_FLASH_MODE_CFG,
> >>>> +				AN7583_SPI_CS_GPIO_MODE_MASK),
> >>>> +	AIROHA_PINCTRL_GPIO_EXT("gpio45", GPIO45_FLASH_MODE_CFG,
> >>>> +				AN7583_SPI_MOSI_GPIO_MODE_MASK),
> >>>> +	AIROHA_PINCTRL_GPIO_EXT("gpio46", GPIO46_FLASH_MODE_CFG,
> >>>> +				AN7583_SPI_MISO_GPIO_MODE_MASK),
> >>>> +	AIROHA_PINCTRL_GPIO_EXT("gpio47", GPIO47_FLASH_MODE_CFG,
> >>>> +				AN7583_UART_TXD_GPIO_MODE_MASK),
> >>>> +	AIROHA_PINCTRL_GPIO_EXT("gpio48", GPIO48_FLASH_MODE_CFG,
> >>>> +				AN7583_UART_RXD_GPIO_MODE_MASK),
> >>>> +	AIROHA_PINCTRL_GPIO_EXT("gpio49", GPIO49_FLASH_MODE_CFG,
> >>>> +				GPIO_PCIE_RESET0_MASK),
> >>>> +	AIROHA_PINCTRL_GPIO_EXT("gpio50", GPIO50_FLASH_MODE_CFG,
> >>>> +				GPIO_PCIE_RESET1_MASK),
> >>>> +	AIROHA_PINCTRL_GPIO_EXT("gpio51", GPIO51_FLASH_MODE_CFG,
> >>>> +				AN7583_MDC_0_GPIO_MODE_MASK),
> >>>> +	AIROHA_PINCTRL_GPIO("gpio52", AN7583_MDIO_0_GPIO_MODE_MASK),
> >>>> +};
> >>>> +
> >>>> +static const struct airoha_pinctrl_func_group an7583_pcie_reset_func_group[] = {
> >>>> +	{
> >>>> +		.name = "pcie_reset0",
> >>>> +		.regmap[0] = {
> >>>> +			AIROHA_FUNC_MUX,
> >>>> +			REG_GPIO_PON_MODE,
> >>>> +			GPIO_PCIE_RESET0_MASK,
> >>>> +			0
> >>>> +		},
> >>>> +		.regmap_size = 1,
> >>>> +	}, {
> >>>> +		.name = "pcie_reset1",
> >>>> +		.regmap[0] = {
> >>>> +			AIROHA_FUNC_MUX,
> >>>> +			REG_GPIO_PON_MODE,
> >>>> +			GPIO_PCIE_RESET1_MASK,
> >>>> +			0
> >>>> +		},
> >>>> +		.regmap_size = 1,
> >>>> +	},
> >>>> +};
> >>>> +
> >>>> +static const struct airoha_pinctrl_func_group an7583_pwm_func_group[] = {
> >>>> +	AIROHA_PINCTRL_PWM("gpio0", GPIO0_FLASH_MODE_CFG),
> >>>> +	AIROHA_PINCTRL_PWM("gpio1", GPIO1_FLASH_MODE_CFG),
> >>>> +	AIROHA_PINCTRL_PWM("gpio2", GPIO2_FLASH_MODE_CFG),
> >>>> +	AIROHA_PINCTRL_PWM("gpio3", GPIO3_FLASH_MODE_CFG),
> >>>> +	AIROHA_PINCTRL_PWM("gpio4", GPIO4_FLASH_MODE_CFG),
> >>>> +	AIROHA_PINCTRL_PWM("gpio5", GPIO5_FLASH_MODE_CFG),
> >>>> +	AIROHA_PINCTRL_PWM("gpio6", GPIO6_FLASH_MODE_CFG),
> >>>> +	AIROHA_PINCTRL_PWM("gpio7", GPIO7_FLASH_MODE_CFG),
> >>>> +	AIROHA_PINCTRL_PWM("gpio8", GPIO8_FLASH_MODE_CFG),
> >>>> +	AIROHA_PINCTRL_PWM("gpio9", GPIO9_FLASH_MODE_CFG),
> >>>> +	AIROHA_PINCTRL_PWM("gpio10", GPIO10_FLASH_MODE_CFG),
> >>>> +	AIROHA_PINCTRL_PWM("gpio11", GPIO11_FLASH_MODE_CFG),
> >>>> +	AIROHA_PINCTRL_PWM("gpio12", GPIO12_FLASH_MODE_CFG),
> >>>> +	AIROHA_PINCTRL_PWM("gpio13", GPIO13_FLASH_MODE_CFG),
> >>>> +	AIROHA_PINCTRL_PWM("gpio14", GPIO14_FLASH_MODE_CFG),
> >>>> +	AIROHA_PINCTRL_PWM("gpio15", GPIO15_FLASH_MODE_CFG),
> >>>> +	AIROHA_PINCTRL_PWM_EXT("gpio16", GPIO16_FLASH_MODE_CFG),
> >>>> +	AIROHA_PINCTRL_PWM_EXT("gpio17", GPIO17_FLASH_MODE_CFG),
> >>>> +	AIROHA_PINCTRL_PWM_EXT("gpio18", GPIO18_FLASH_MODE_CFG),
> >>>> +	AIROHA_PINCTRL_PWM_EXT("gpio19", GPIO19_FLASH_MODE_CFG),
> >>>> +	AIROHA_PINCTRL_PWM_EXT("gpio20", GPIO20_FLASH_MODE_CFG),
> >>>> +	AIROHA_PINCTRL_PWM_EXT("gpio21", GPIO21_FLASH_MODE_CFG),
> >>>> +	AIROHA_PINCTRL_PWM_EXT("gpio22", GPIO22_FLASH_MODE_CFG),
> >>>> +	AIROHA_PINCTRL_PWM_EXT("gpio23", GPIO23_FLASH_MODE_CFG),
> >>>> +	AIROHA_PINCTRL_PWM_EXT("gpio24", GPIO24_FLASH_MODE_CFG),
> >>>> +	AIROHA_PINCTRL_PWM_EXT("gpio25", GPIO25_FLASH_MODE_CFG),
> >>>> +	AIROHA_PINCTRL_PWM_EXT("gpio26", GPIO26_FLASH_MODE_CFG),
> >>>> +	AIROHA_PINCTRL_PWM_EXT("gpio27", GPIO27_FLASH_MODE_CFG),
> >>>> +	AIROHA_PINCTRL_PWM_EXT("gpio28", GPIO28_FLASH_MODE_CFG),
> >>>> +	AIROHA_PINCTRL_PWM_EXT("gpio29", GPIO29_FLASH_MODE_CFG),
> >>>> +	AIROHA_PINCTRL_PWM_EXT("gpio30", GPIO30_FLASH_MODE_CFG),
> >>>> +	AIROHA_PINCTRL_PWM_EXT("gpio31", GPIO31_FLASH_MODE_CFG),
> >>>> +	AIROHA_PINCTRL_PWM_EXT("gpio36", GPIO36_FLASH_MODE_CFG),
> >>>> +	AIROHA_PINCTRL_PWM_EXT("gpio37", GPIO37_FLASH_MODE_CFG),
> >>>> +	AIROHA_PINCTRL_PWM_EXT("gpio38", GPIO38_FLASH_MODE_CFG),
> >>>> +	AIROHA_PINCTRL_PWM_EXT_SEC("gpio39", GPIO39_FLASH_MODE_CFG,
> >>>> +				   AN7583_I2C0_SCL_GPIO_MODE_MASK),
> >>>> +	AIROHA_PINCTRL_PWM_EXT_SEC("gpio40", GPIO40_FLASH_MODE_CFG,
> >>>> +				   AN7583_I2C0_SDA_GPIO_MODE_MASK),
> >>>> +	AIROHA_PINCTRL_PWM_EXT_SEC("gpio41", GPIO41_FLASH_MODE_CFG,
> >>>> +				   AN7583_I2C1_SCL_GPIO_MODE_MASK),
> >>>> +	AIROHA_PINCTRL_PWM_EXT_SEC("gpio42", GPIO42_FLASH_MODE_CFG,
> >>>> +				   AN7583_I2C1_SDA_GPIO_MODE_MASK),
> >>>> +	AIROHA_PINCTRL_PWM_EXT_SEC("gpio43", GPIO43_FLASH_MODE_CFG,
> >>>> +				   AN7583_SPI_CLK_GPIO_MODE_MASK),
> >>>> +	AIROHA_PINCTRL_PWM_EXT_SEC("gpio44", GPIO44_FLASH_MODE_CFG,
> >>>> +				   AN7583_SPI_CS_GPIO_MODE_MASK),
> >>>> +	AIROHA_PINCTRL_PWM_EXT_SEC("gpio45", GPIO45_FLASH_MODE_CFG,
> >>>> +				   AN7583_SPI_MOSI_GPIO_MODE_MASK),
> >>>> +	AIROHA_PINCTRL_PWM_EXT_SEC("gpio46", GPIO46_FLASH_MODE_CFG,
> >>>> +				   AN7583_SPI_MISO_GPIO_MODE_MASK),
> >>>> +	AIROHA_PINCTRL_PWM_EXT_SEC("gpio47", GPIO47_FLASH_MODE_CFG,
> >>>> +				   AN7583_UART_TXD_GPIO_MODE_MASK),
> >>>> +	AIROHA_PINCTRL_PWM_EXT_SEC("gpio48", GPIO48_FLASH_MODE_CFG,
> >>>> +				   AN7583_UART_RXD_GPIO_MODE_MASK),
> >>>> +	AIROHA_PINCTRL_PWM_EXT_SEC("gpio49", GPIO49_FLASH_MODE_CFG,
> >>>> +				   GPIO_PCIE_RESET0_MASK),
> >>>> +	AIROHA_PINCTRL_PWM_EXT_SEC("gpio50", GPIO50_FLASH_MODE_CFG,
> >>>> +				   GPIO_PCIE_RESET1_MASK),
> >>>> +	AIROHA_PINCTRL_PWM_EXT_SEC("gpio51", GPIO51_FLASH_MODE_CFG,
> >>>> +				   AN7583_MDC_0_GPIO_MODE_MASK),
> >>>> +};
> >>>> +
> >>>> +static const struct airoha_pinctrl_func_group an7583_phy1_led0_func_group[] = {
> >>>> +	AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK,
> >>>> +				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),
> >>>> +	AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK,
> >>>> +				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)),
> >>>> +	AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK,
> >>>> +				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)),
> >>>> +	AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK,
> >>>> +				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),
> >>>> +};
> >>>> +
> >>>> +static const struct airoha_pinctrl_func_group an7583_phy2_led0_func_group[] = {
> >>>> +	AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK,
> >>>> +				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),
> >>>> +	AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK,
> >>>> +				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)),
> >>>> +	AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK,
> >>>> +				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)),
> >>>> +	AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK,
> >>>> +				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),
> >>>> +};
> >>>> +
> >>>> +static const struct airoha_pinctrl_func_group an7583_phy3_led0_func_group[] = {
> >>>> +	AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK,
> >>>> +				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
> >>>> +	AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK,
> >>>> +				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),
> >>>> +	AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK,
> >>>> +				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),
> >>>> +	AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK,
> >>>> +				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
> >>>> +};
> >>>> +
> >>>> +static const struct airoha_pinctrl_func_group an7583_phy4_led0_func_group[] = {
> >>>> +	AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK,
> >>>> +				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)),
> >>>> +	AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK,
> >>>> +				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)),
> >>>> +	AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK,
> >>>> +				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)),
> >>>> +	AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK,
> >>>> +				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)),
> >>>> +};
> >>>> +
> >>>> +static const struct airoha_pinctrl_func_group an7583_phy1_led1_func_group[] = {
> >>>> +	AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK,
> >>>> +				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),
> >>>> +	AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK,
> >>>> +				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)),
> >>>> +	AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK,
> >>>> +				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)),
> >>>> +	AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK,
> >>>> +				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),
> >>>> +};
> >>>> +
> >>>> +static const struct airoha_pinctrl_func_group an7583_phy2_led1_func_group[] = {
> >>>> +	AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK,
> >>>> +				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),
> >>>> +	AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK,
> >>>> +				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)),
> >>>> +	AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK,
> >>>> +				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)),
> >>>> +	AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK,
> >>>> +				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),
> >>>> +};
> >>>> +
> >>>> +static const struct airoha_pinctrl_func_group an7583_phy3_led1_func_group[] = {
> >>>> +	AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK,
> >>>> +				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
> >>>> +	AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK,
> >>>> +				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),
> >>>> +	AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK,
> >>>> +				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),
> >>>> +	AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK,
> >>>> +				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
> >>>> +};
> >>>> +
> >>>> +static const struct airoha_pinctrl_func_group an7583_phy4_led1_func_group[] = {
> >>>> +	AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK,
> >>>> +				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)),
> >>>> +	AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK,
> >>>> +				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)),
> >>>> +	AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK,
> >>>> +				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)),
> >>>> +	AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK,
> >>>> +				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)),
> >>>> +};
> >>>> +
> >>>> +static const struct airoha_pinctrl_func an7583_pinctrl_funcs[] = {
> >>>> +	PINCTRL_FUNC_DESC("pon", pon),
> >>>> +	PINCTRL_FUNC_DESC("tod_1pps", tod_1pps),
> >>>> +	PINCTRL_FUNC_DESC("sipo", sipo),
> >>>> +	PINCTRL_FUNC_DESC("mdio", an7583_mdio),
> >>>> +	PINCTRL_FUNC_DESC("uart", uart),
> >>>> +	PINCTRL_FUNC_DESC("jtag", jtag),
> >>>> +	PINCTRL_FUNC_DESC("pcm", pcm),
> >>>> +	PINCTRL_FUNC_DESC("spi", spi),
> >>>> +	PINCTRL_FUNC_DESC("pcm_spi", an7583_pcm_spi),
> >>>> +	PINCTRL_FUNC_DESC("emmc", emmc),
> >>>> +	PINCTRL_FUNC_DESC("pnand", pnand),
> >>>> +	PINCTRL_FUNC_DESC("gpio", an7583_gpio),
> >>>> +	PINCTRL_FUNC_DESC("pcie_reset", an7583_pcie_reset),
> >>>> +	PINCTRL_FUNC_DESC("pwm", an7583_pwm),
> >>>> +	PINCTRL_FUNC_DESC("phy1_led0", an7583_phy1_led0),
> >>>> +	PINCTRL_FUNC_DESC("phy2_led0", an7583_phy2_led0),
> >>>> +	PINCTRL_FUNC_DESC("phy3_led0", an7583_phy3_led0),
> >>>> +	PINCTRL_FUNC_DESC("phy4_led0", an7583_phy4_led0),
> >>>> +	PINCTRL_FUNC_DESC("phy1_led1", an7583_phy1_led1),
> >>>> +	PINCTRL_FUNC_DESC("phy2_led1", an7583_phy2_led1),
> >>>> +	PINCTRL_FUNC_DESC("phy3_led1", an7583_phy3_led1),
> >>>> +	PINCTRL_FUNC_DESC("phy4_led1", an7583_phy4_led1),
> >>>> +};
> >>>> +
> >>>> +static const struct airoha_pinctrl_conf an7583_pinctrl_pullup_conf[] = {
> >>>> +	PINCTRL_CONF_DESC(2, REG_GPIO_L_PU, BIT(0)),
> >>>> +	PINCTRL_CONF_DESC(3, REG_GPIO_L_PU, BIT(1)),
> >>>> +	PINCTRL_CONF_DESC(4, REG_GPIO_L_PU, BIT(2)),
> >>>> +	PINCTRL_CONF_DESC(5, REG_GPIO_L_PU, BIT(3)),
> >>>> +	PINCTRL_CONF_DESC(6, REG_GPIO_L_PU, BIT(4)),
> >>>> +	PINCTRL_CONF_DESC(7, REG_GPIO_L_PU, BIT(5)),
> >>>> +	PINCTRL_CONF_DESC(8, REG_GPIO_L_PU, BIT(6)),
> >>>> +	PINCTRL_CONF_DESC(9, REG_GPIO_L_PU, BIT(7)),
> >>>> +	PINCTRL_CONF_DESC(10, REG_GPIO_L_PU, BIT(8)),
> >>>> +	PINCTRL_CONF_DESC(11, REG_GPIO_L_PU, BIT(9)),
> >>>> +	PINCTRL_CONF_DESC(12, REG_GPIO_L_PU, BIT(10)),
> >>>> +	PINCTRL_CONF_DESC(13, REG_GPIO_L_PU, BIT(11)),
> >>>> +	PINCTRL_CONF_DESC(14, REG_GPIO_L_PU, BIT(12)),
> >>>> +	PINCTRL_CONF_DESC(15, REG_GPIO_L_PU, BIT(13)),
> >>>> +	PINCTRL_CONF_DESC(16, REG_GPIO_L_PU, BIT(14)),
> >>>> +	PINCTRL_CONF_DESC(17, REG_GPIO_L_PU, BIT(15)),
> >>>> +	PINCTRL_CONF_DESC(18, REG_GPIO_L_PU, BIT(16)),
> >>>> +	PINCTRL_CONF_DESC(19, REG_GPIO_L_PU, BIT(17)),
> >>>> +	PINCTRL_CONF_DESC(20, REG_GPIO_L_PU, BIT(18)),
> >>>> +	PINCTRL_CONF_DESC(21, REG_GPIO_L_PU, BIT(19)),
> >>>> +	PINCTRL_CONF_DESC(22, REG_GPIO_L_PU, BIT(20)),
> >>>> +	PINCTRL_CONF_DESC(23, REG_GPIO_L_PU, BIT(21)),
> >>>> +	PINCTRL_CONF_DESC(24, REG_GPIO_L_PU, BIT(22)),
> >>>> +	PINCTRL_CONF_DESC(25, REG_GPIO_L_PU, BIT(23)),
> >>>> +	PINCTRL_CONF_DESC(26, REG_GPIO_L_PU, BIT(24)),
> >>>> +	PINCTRL_CONF_DESC(27, REG_GPIO_L_PU, BIT(25)),
> >>>> +	PINCTRL_CONF_DESC(28, REG_GPIO_L_PU, BIT(26)),
> >>>> +	PINCTRL_CONF_DESC(29, REG_GPIO_L_PU, BIT(27)),
> >>>> +	PINCTRL_CONF_DESC(30, REG_GPIO_L_PU, BIT(28)),
> >>>> +	PINCTRL_CONF_DESC(31, REG_GPIO_L_PU, BIT(29)),
> >>>> +	PINCTRL_CONF_DESC(32, REG_GPIO_L_PU, BIT(30)),
> >>>> +	PINCTRL_CONF_DESC(33, REG_GPIO_L_PU, BIT(31)),
> >>>> +	PINCTRL_CONF_DESC(34, REG_GPIO_H_PU, BIT(0)),
> >>>> +	PINCTRL_CONF_DESC(35, REG_GPIO_H_PU, BIT(1)),
> >>>> +	PINCTRL_CONF_DESC(36, REG_GPIO_H_PU, BIT(2)),
> >>>> +	PINCTRL_CONF_DESC(37, REG_GPIO_H_PU, BIT(3)),
> >>>> +	PINCTRL_CONF_DESC(38, REG_GPIO_H_PU, BIT(4)),
> >>>> +	PINCTRL_CONF_DESC(39, REG_GPIO_H_PU, BIT(5)),
> >>>> +	PINCTRL_CONF_DESC(40, REG_GPIO_H_PU, BIT(6)),
> >>>> +	PINCTRL_CONF_DESC(41, REG_I2C_SDA_PU, I2C_SCL_PU_MASK),
> >>>> +	PINCTRL_CONF_DESC(42, REG_I2C_SDA_PU, I2C_SDA_PU_MASK),
> >>>> +	PINCTRL_CONF_DESC(43, REG_I2C_SDA_PU, AN7583_I2C1_SCL_PU_MASK),
> >>>> +	PINCTRL_CONF_DESC(44, REG_I2C_SDA_PU, AN7583_I2C1_SDA_PU_MASK),
> >>>> +	PINCTRL_CONF_DESC(45, REG_I2C_SDA_PU, SPI_CLK_PU_MASK),
> >>>> +	PINCTRL_CONF_DESC(46, REG_I2C_SDA_PU, SPI_CS0_PU_MASK),
> >>>> +	PINCTRL_CONF_DESC(47, REG_I2C_SDA_PU, SPI_MOSI_PU_MASK),
> >>>> +	PINCTRL_CONF_DESC(48, REG_I2C_SDA_PU, SPI_MISO_PU_MASK),
> >>>> +	PINCTRL_CONF_DESC(49, REG_I2C_SDA_PU, UART1_TXD_PU_MASK),
> >>>> +	PINCTRL_CONF_DESC(50, REG_I2C_SDA_PU, UART1_RXD_PU_MASK),
> >>>> +	PINCTRL_CONF_DESC(51, REG_I2C_SDA_PU, PCIE0_RESET_PU_MASK),
> >>>> +	PINCTRL_CONF_DESC(52, REG_I2C_SDA_PU, PCIE1_RESET_PU_MASK),
> >>>> +	PINCTRL_CONF_DESC(53, REG_I2C_SDA_PU, AN7583_MDC_0_PU_MASK),
> >>>> +	PINCTRL_CONF_DESC(54, REG_I2C_SDA_PU, AN7583_MDIO_0_PU_MASK),
> >>>> +};
> >>>> +
> >>>> +static const struct airoha_pinctrl_conf an7583_pinctrl_pulldown_conf[] = {
> >>>> +	PINCTRL_CONF_DESC(2, REG_GPIO_L_PD, BIT(0)),
> >>>> +	PINCTRL_CONF_DESC(3, REG_GPIO_L_PD, BIT(1)),
> >>>> +	PINCTRL_CONF_DESC(4, REG_GPIO_L_PD, BIT(2)),
> >>>> +	PINCTRL_CONF_DESC(5, REG_GPIO_L_PD, BIT(3)),
> >>>> +	PINCTRL_CONF_DESC(6, REG_GPIO_L_PD, BIT(4)),
> >>>> +	PINCTRL_CONF_DESC(7, REG_GPIO_L_PD, BIT(5)),
> >>>> +	PINCTRL_CONF_DESC(8, REG_GPIO_L_PD, BIT(6)),
> >>>> +	PINCTRL_CONF_DESC(9, REG_GPIO_L_PD, BIT(7)),
> >>>> +	PINCTRL_CONF_DESC(10, REG_GPIO_L_PD, BIT(8)),
> >>>> +	PINCTRL_CONF_DESC(11, REG_GPIO_L_PD, BIT(9)),
> >>>> +	PINCTRL_CONF_DESC(12, REG_GPIO_L_PD, BIT(10)),
> >>>> +	PINCTRL_CONF_DESC(13, REG_GPIO_L_PD, BIT(11)),
> >>>> +	PINCTRL_CONF_DESC(14, REG_GPIO_L_PD, BIT(12)),
> >>>> +	PINCTRL_CONF_DESC(15, REG_GPIO_L_PD, BIT(13)),
> >>>> +	PINCTRL_CONF_DESC(16, REG_GPIO_L_PD, BIT(14)),
> >>>> +	PINCTRL_CONF_DESC(17, REG_GPIO_L_PD, BIT(15)),
> >>>> +	PINCTRL_CONF_DESC(18, REG_GPIO_L_PD, BIT(16)),
> >>>> +	PINCTRL_CONF_DESC(19, REG_GPIO_L_PD, BIT(17)),
> >>>> +	PINCTRL_CONF_DESC(20, REG_GPIO_L_PD, BIT(18)),
> >>>> +	PINCTRL_CONF_DESC(21, REG_GPIO_L_PD, BIT(19)),
> >>>> +	PINCTRL_CONF_DESC(22, REG_GPIO_L_PD, BIT(20)),
> >>>> +	PINCTRL_CONF_DESC(23, REG_GPIO_L_PD, BIT(21)),
> >>>> +	PINCTRL_CONF_DESC(24, REG_GPIO_L_PD, BIT(22)),
> >>>> +	PINCTRL_CONF_DESC(25, REG_GPIO_L_PD, BIT(23)),
> >>>> +	PINCTRL_CONF_DESC(26, REG_GPIO_L_PD, BIT(24)),
> >>>> +	PINCTRL_CONF_DESC(27, REG_GPIO_L_PD, BIT(25)),
> >>>> +	PINCTRL_CONF_DESC(28, REG_GPIO_L_PD, BIT(26)),
> >>>> +	PINCTRL_CONF_DESC(29, REG_GPIO_L_PD, BIT(27)),
> >>>> +	PINCTRL_CONF_DESC(30, REG_GPIO_L_PD, BIT(28)),
> >>>> +	PINCTRL_CONF_DESC(31, REG_GPIO_L_PD, BIT(29)),
> >>>> +	PINCTRL_CONF_DESC(32, REG_GPIO_L_PD, BIT(30)),
> >>>> +	PINCTRL_CONF_DESC(33, REG_GPIO_L_PD, BIT(31)),
> >>>> +	PINCTRL_CONF_DESC(34, REG_GPIO_H_PD, BIT(0)),
> >>>> +	PINCTRL_CONF_DESC(35, REG_GPIO_H_PD, BIT(1)),
> >>>> +	PINCTRL_CONF_DESC(36, REG_GPIO_H_PD, BIT(2)),
> >>>> +	PINCTRL_CONF_DESC(37, REG_GPIO_H_PD, BIT(3)),
> >>>> +	PINCTRL_CONF_DESC(38, REG_GPIO_H_PD, BIT(4)),
> >>>> +	PINCTRL_CONF_DESC(39, REG_GPIO_H_PD, BIT(5)),
> >>>> +	PINCTRL_CONF_DESC(40, REG_GPIO_H_PD, BIT(6)),
> >>>> +	PINCTRL_CONF_DESC(41, REG_I2C_SDA_PD, I2C_SCL_PD_MASK),
> >>>> +	PINCTRL_CONF_DESC(42, REG_I2C_SDA_PD, I2C_SDA_PD_MASK),
> >>>> +	PINCTRL_CONF_DESC(43, REG_I2C_SDA_PD, AN7583_I2C1_SCL_PD_MASK),
> >>>> +	PINCTRL_CONF_DESC(44, REG_I2C_SDA_PD, AN7583_I2C1_SDA_PD_MASK),
> >>>> +	PINCTRL_CONF_DESC(45, REG_I2C_SDA_PD, SPI_CLK_PD_MASK),
> >>>> +	PINCTRL_CONF_DESC(46, REG_I2C_SDA_PD, SPI_CS0_PD_MASK),
> >>>> +	PINCTRL_CONF_DESC(47, REG_I2C_SDA_PD, SPI_MOSI_PD_MASK),
> >>>> +	PINCTRL_CONF_DESC(48, REG_I2C_SDA_PD, SPI_MISO_PD_MASK),
> >>>> +	PINCTRL_CONF_DESC(49, REG_I2C_SDA_PD, UART1_TXD_PD_MASK),
> >>>> +	PINCTRL_CONF_DESC(50, REG_I2C_SDA_PD, UART1_RXD_PD_MASK),
> >>>> +	PINCTRL_CONF_DESC(51, REG_I2C_SDA_PD, PCIE0_RESET_PD_MASK),
> >>>> +	PINCTRL_CONF_DESC(52, REG_I2C_SDA_PD, PCIE1_RESET_PD_MASK),
> >>>> +	PINCTRL_CONF_DESC(53, REG_I2C_SDA_PD, AN7583_MDC_0_PD_MASK),
> >>>> +	PINCTRL_CONF_DESC(54, REG_I2C_SDA_PD, AN7583_MDIO_0_PD_MASK),
> >>>> +};
> >>>> +
> >>>> +static const struct airoha_pinctrl_conf an7583_pinctrl_drive_e2_conf[] = {
> >>>> +	PINCTRL_CONF_DESC(2, REG_GPIO_L_E2, BIT(0)),
> >>>> +	PINCTRL_CONF_DESC(3, REG_GPIO_L_E2, BIT(1)),
> >>>> +	PINCTRL_CONF_DESC(4, REG_GPIO_L_E2, BIT(2)),
> >>>> +	PINCTRL_CONF_DESC(5, REG_GPIO_L_E2, BIT(3)),
> >>>> +	PINCTRL_CONF_DESC(6, REG_GPIO_L_E2, BIT(4)),
> >>>> +	PINCTRL_CONF_DESC(7, REG_GPIO_L_E2, BIT(5)),
> >>>> +	PINCTRL_CONF_DESC(8, REG_GPIO_L_E2, BIT(6)),
> >>>> +	PINCTRL_CONF_DESC(9, REG_GPIO_L_E2, BIT(7)),
> >>>> +	PINCTRL_CONF_DESC(10, REG_GPIO_L_E2, BIT(8)),
> >>>> +	PINCTRL_CONF_DESC(11, REG_GPIO_L_E2, BIT(9)),
> >>>> +	PINCTRL_CONF_DESC(12, REG_GPIO_L_E2, BIT(10)),
> >>>> +	PINCTRL_CONF_DESC(13, REG_GPIO_L_E2, BIT(11)),
> >>>> +	PINCTRL_CONF_DESC(14, REG_GPIO_L_E2, BIT(12)),
> >>>> +	PINCTRL_CONF_DESC(15, REG_GPIO_L_E2, BIT(13)),
> >>>> +	PINCTRL_CONF_DESC(16, REG_GPIO_L_E2, BIT(14)),
> >>>> +	PINCTRL_CONF_DESC(17, REG_GPIO_L_E2, BIT(15)),
> >>>> +	PINCTRL_CONF_DESC(18, REG_GPIO_L_E2, BIT(16)),
> >>>> +	PINCTRL_CONF_DESC(19, REG_GPIO_L_E2, BIT(17)),
> >>>> +	PINCTRL_CONF_DESC(20, REG_GPIO_L_E2, BIT(18)),
> >>>> +	PINCTRL_CONF_DESC(21, REG_GPIO_L_E2, BIT(19)),
> >>>> +	PINCTRL_CONF_DESC(22, REG_GPIO_L_E2, BIT(20)),
> >>>> +	PINCTRL_CONF_DESC(23, REG_GPIO_L_E2, BIT(21)),
> >>>> +	PINCTRL_CONF_DESC(24, REG_GPIO_L_E2, BIT(22)),
> >>>> +	PINCTRL_CONF_DESC(25, REG_GPIO_L_E2, BIT(23)),
> >>>> +	PINCTRL_CONF_DESC(26, REG_GPIO_L_E2, BIT(24)),
> >>>> +	PINCTRL_CONF_DESC(27, REG_GPIO_L_E2, BIT(25)),
> >>>> +	PINCTRL_CONF_DESC(28, REG_GPIO_L_E2, BIT(26)),
> >>>> +	PINCTRL_CONF_DESC(29, REG_GPIO_L_E2, BIT(27)),
> >>>> +	PINCTRL_CONF_DESC(30, REG_GPIO_L_E2, BIT(28)),
> >>>> +	PINCTRL_CONF_DESC(31, REG_GPIO_L_E2, BIT(29)),
> >>>> +	PINCTRL_CONF_DESC(32, REG_GPIO_L_E2, BIT(30)),
> >>>> +	PINCTRL_CONF_DESC(33, REG_GPIO_L_E2, BIT(31)),
> >>>> +	PINCTRL_CONF_DESC(34, REG_GPIO_H_E2, BIT(0)),
> >>>> +	PINCTRL_CONF_DESC(35, REG_GPIO_H_E2, BIT(1)),
> >>>> +	PINCTRL_CONF_DESC(36, REG_GPIO_H_E2, BIT(2)),
> >>>> +	PINCTRL_CONF_DESC(37, REG_GPIO_H_E2, BIT(3)),
> >>>> +	PINCTRL_CONF_DESC(38, REG_GPIO_H_E2, BIT(4)),
> >>>> +	PINCTRL_CONF_DESC(39, REG_GPIO_H_E2, BIT(5)),
> >>>> +	PINCTRL_CONF_DESC(40, REG_GPIO_H_E2, BIT(6)),
> >>>> +	PINCTRL_CONF_DESC(41, REG_I2C_SDA_E2, I2C_SCL_E2_MASK),
> >>>> +	PINCTRL_CONF_DESC(42, REG_I2C_SDA_E2, I2C_SDA_E2_MASK),
> >>>> +	PINCTRL_CONF_DESC(43, REG_I2C_SDA_E2, AN7583_I2C1_SCL_E2_MASK),
> >>>> +	PINCTRL_CONF_DESC(44, REG_I2C_SDA_E2, AN7583_I2C1_SDA_E2_MASK),
> >>>> +	PINCTRL_CONF_DESC(45, REG_I2C_SDA_E2, SPI_CLK_E2_MASK),
> >>>> +	PINCTRL_CONF_DESC(46, REG_I2C_SDA_E2, SPI_CS0_E2_MASK),
> >>>> +	PINCTRL_CONF_DESC(47, REG_I2C_SDA_E2, SPI_MOSI_E2_MASK),
> >>>> +	PINCTRL_CONF_DESC(48, REG_I2C_SDA_E2, SPI_MISO_E2_MASK),
> >>>> +	PINCTRL_CONF_DESC(49, REG_I2C_SDA_E2, UART1_TXD_E2_MASK),
> >>>> +	PINCTRL_CONF_DESC(50, REG_I2C_SDA_E2, UART1_RXD_E2_MASK),
> >>>> +	PINCTRL_CONF_DESC(51, REG_I2C_SDA_E2, PCIE0_RESET_E2_MASK),
> >>>> +	PINCTRL_CONF_DESC(52, REG_I2C_SDA_E2, PCIE1_RESET_E2_MASK),
> >>>> +	PINCTRL_CONF_DESC(53, REG_I2C_SDA_E2, AN7583_MDC_0_E2_MASK),
> >>>> +	PINCTRL_CONF_DESC(54, REG_I2C_SDA_E2, AN7583_MDIO_0_E2_MASK),
> >>>> +};
> >>>> +
> >>>> +static const struct airoha_pinctrl_conf an7583_pinctrl_drive_e4_conf[] = {
> >>>> +	PINCTRL_CONF_DESC(2, REG_GPIO_L_E4, BIT(0)),
> >>>> +	PINCTRL_CONF_DESC(3, REG_GPIO_L_E4, BIT(1)),
> >>>> +	PINCTRL_CONF_DESC(4, REG_GPIO_L_E4, BIT(2)),
> >>>> +	PINCTRL_CONF_DESC(5, REG_GPIO_L_E4, BIT(3)),
> >>>> +	PINCTRL_CONF_DESC(6, REG_GPIO_L_E4, BIT(4)),
> >>>> +	PINCTRL_CONF_DESC(7, REG_GPIO_L_E4, BIT(5)),
> >>>> +	PINCTRL_CONF_DESC(8, REG_GPIO_L_E4, BIT(6)),
> >>>> +	PINCTRL_CONF_DESC(9, REG_GPIO_L_E4, BIT(7)),
> >>>> +	PINCTRL_CONF_DESC(10, REG_GPIO_L_E4, BIT(8)),
> >>>> +	PINCTRL_CONF_DESC(11, REG_GPIO_L_E4, BIT(9)),
> >>>> +	PINCTRL_CONF_DESC(12, REG_GPIO_L_E4, BIT(10)),
> >>>> +	PINCTRL_CONF_DESC(13, REG_GPIO_L_E4, BIT(11)),
> >>>> +	PINCTRL_CONF_DESC(14, REG_GPIO_L_E4, BIT(12)),
> >>>> +	PINCTRL_CONF_DESC(15, REG_GPIO_L_E4, BIT(13)),
> >>>> +	PINCTRL_CONF_DESC(16, REG_GPIO_L_E4, BIT(14)),
> >>>> +	PINCTRL_CONF_DESC(17, REG_GPIO_L_E4, BIT(15)),
> >>>> +	PINCTRL_CONF_DESC(18, REG_GPIO_L_E4, BIT(16)),
> >>>> +	PINCTRL_CONF_DESC(19, REG_GPIO_L_E4, BIT(17)),
> >>>> +	PINCTRL_CONF_DESC(20, REG_GPIO_L_E4, BIT(18)),
> >>>> +	PINCTRL_CONF_DESC(21, REG_GPIO_L_E4, BIT(19)),
> >>>> +	PINCTRL_CONF_DESC(22, REG_GPIO_L_E4, BIT(20)),
> >>>> +	PINCTRL_CONF_DESC(23, REG_GPIO_L_E4, BIT(21)),
> >>>> +	PINCTRL_CONF_DESC(24, REG_GPIO_L_E4, BIT(22)),
> >>>> +	PINCTRL_CONF_DESC(25, REG_GPIO_L_E4, BIT(23)),
> >>>> +	PINCTRL_CONF_DESC(26, REG_GPIO_L_E4, BIT(24)),
> >>>> +	PINCTRL_CONF_DESC(27, REG_GPIO_L_E4, BIT(25)),
> >>>> +	PINCTRL_CONF_DESC(28, REG_GPIO_L_E4, BIT(26)),
> >>>> +	PINCTRL_CONF_DESC(29, REG_GPIO_L_E4, BIT(27)),
> >>>> +	PINCTRL_CONF_DESC(30, REG_GPIO_L_E4, BIT(28)),
> >>>> +	PINCTRL_CONF_DESC(31, REG_GPIO_L_E4, BIT(29)),
> >>>> +	PINCTRL_CONF_DESC(32, REG_GPIO_L_E4, BIT(30)),
> >>>> +	PINCTRL_CONF_DESC(33, REG_GPIO_L_E4, BIT(31)),
> >>>> +	PINCTRL_CONF_DESC(34, REG_GPIO_H_E4, BIT(0)),
> >>>> +	PINCTRL_CONF_DESC(35, REG_GPIO_H_E4, BIT(1)),
> >>>> +	PINCTRL_CONF_DESC(36, REG_GPIO_H_E4, BIT(2)),
> >>>> +	PINCTRL_CONF_DESC(37, REG_GPIO_H_E4, BIT(3)),
> >>>> +	PINCTRL_CONF_DESC(38, REG_GPIO_H_E4, BIT(4)),
> >>>> +	PINCTRL_CONF_DESC(39, REG_GPIO_H_E4, BIT(5)),
> >>>> +	PINCTRL_CONF_DESC(40, REG_GPIO_H_E4, BIT(6)),
> >>>> +	PINCTRL_CONF_DESC(41, REG_I2C_SDA_E4, I2C_SCL_E4_MASK),
> >>>> +	PINCTRL_CONF_DESC(42, REG_I2C_SDA_E4, I2C_SDA_E4_MASK),
> >>>> +	PINCTRL_CONF_DESC(43, REG_I2C_SDA_E4, AN7583_I2C1_SCL_E4_MASK),
> >>>> +	PINCTRL_CONF_DESC(44, REG_I2C_SDA_E4, AN7583_I2C1_SDA_E4_MASK),
> >>>> +	PINCTRL_CONF_DESC(45, REG_I2C_SDA_E4, SPI_CLK_E4_MASK),
> >>>> +	PINCTRL_CONF_DESC(46, REG_I2C_SDA_E4, SPI_CS0_E4_MASK),
> >>>> +	PINCTRL_CONF_DESC(47, REG_I2C_SDA_E4, SPI_MOSI_E4_MASK),
> >>>> +	PINCTRL_CONF_DESC(48, REG_I2C_SDA_E4, SPI_MISO_E4_MASK),
> >>>> +	PINCTRL_CONF_DESC(49, REG_I2C_SDA_E4, UART1_TXD_E4_MASK),
> >>>> +	PINCTRL_CONF_DESC(50, REG_I2C_SDA_E4, UART1_RXD_E4_MASK),
> >>>> +	PINCTRL_CONF_DESC(51, REG_I2C_SDA_E4, PCIE0_RESET_E4_MASK),
> >>>> +	PINCTRL_CONF_DESC(52, REG_I2C_SDA_E4, PCIE1_RESET_E4_MASK),
> >>>> +	PINCTRL_CONF_DESC(53, REG_I2C_SDA_E4, AN7583_MDC_0_E4_MASK),
> >>>> +	PINCTRL_CONF_DESC(54, REG_I2C_SDA_E4, AN7583_MDIO_0_E4_MASK),
> >>>> +};
> >>>> +
> >>>> +static const struct airoha_pinctrl_conf an7583_pinctrl_pcie_rst_od_conf[] = {
> >>>> +	PINCTRL_CONF_DESC(51, REG_PCIE_RESET_OD, PCIE0_RESET_OD_MASK),
> >>>> +	PINCTRL_CONF_DESC(52, REG_PCIE_RESET_OD, PCIE1_RESET_OD_MASK),
> >>>> +};
> >>>> +
> >>>> +static const struct airoha_pinctrl_match_data an7583_pinctrl_match_data = {
> >>>> +	.pinctrl_name = KBUILD_MODNAME,
> >>>> +	.pinctrl_owner = THIS_MODULE,
> >>>> +	.pins = an7583_pinctrl_pins,
> >>>> +	.num_pins = ARRAY_SIZE(an7583_pinctrl_pins),
> >>>> +	.grps = an7583_pinctrl_groups,
> >>>> +	.num_grps = ARRAY_SIZE(an7583_pinctrl_groups),
> >>>> +	.funcs = an7583_pinctrl_funcs,
> >>>> +	.num_funcs = ARRAY_SIZE(an7583_pinctrl_funcs),
> >>>> +	.confs_info = {
> >>>> +		[AIROHA_PINCTRL_CONFS_PULLUP] = {
> >>>> +			.confs = an7583_pinctrl_pullup_conf,
> >>>> +			.num_confs = ARRAY_SIZE(an7583_pinctrl_pullup_conf),
> >>>> +		},
> >>>> +		[AIROHA_PINCTRL_CONFS_PULLDOWN] = {
> >>>> +			.confs = an7583_pinctrl_pulldown_conf,
> >>>> +			.num_confs = ARRAY_SIZE(an7583_pinctrl_pulldown_conf),
> >>>> +		},
> >>>> +		[AIROHA_PINCTRL_CONFS_DRIVE_E2] = {
> >>>> +			.confs = an7583_pinctrl_drive_e2_conf,
> >>>> +			.num_confs = ARRAY_SIZE(an7583_pinctrl_drive_e2_conf),
> >>>> +		},
> >>>> +		[AIROHA_PINCTRL_CONFS_DRIVE_E4] = {
> >>>> +			.confs = an7583_pinctrl_drive_e4_conf,
> >>>> +			.num_confs = ARRAY_SIZE(an7583_pinctrl_drive_e4_conf),
> >>>> +		},
> >>>> +		[AIROHA_PINCTRL_CONFS_PCIE_RST_OD] = {
> >>>> +			.confs = an7583_pinctrl_pcie_rst_od_conf,
> >>>> +			.num_confs = ARRAY_SIZE(an7583_pinctrl_pcie_rst_od_conf),
> >>>> +		},
> >>>> +	},
> >>>> +};
> >>>> +
> >>>> +static const struct of_device_id airoha_pinctrl_of_match[] = {
> >>>> +	{ .compatible = "airoha,an7583-pinctrl", .data = &an7583_pinctrl_match_data },
> >>>> +	{ /* sentinel */ }
> >>>> +};
> >>>> +MODULE_DEVICE_TABLE(of, airoha_pinctrl_of_match);
> >>>> +
> >>>> +static struct platform_driver airoha_pinctrl_driver = {
> >>>> +	.probe = airoha_pinctrl_probe,
> >>>> +	.driver = {
> >>>> +		.name = "pinctrl-airoha-an7583",
> >>>> +		.of_match_table = airoha_pinctrl_of_match,
> >>>> +	},
> >>>> +};
> >>>> +module_platform_driver(airoha_pinctrl_driver);
> >>>> +
> >>>> +MODULE_LICENSE("GPL");
> >>>> +MODULE_AUTHOR("Lorenzo Bianconi <lorenzo@kernel.org>");
> >>>> +MODULE_AUTHOR("Benjamin Larsson <benjamin.larsson@genexis.eu>");
> >>>> +MODULE_AUTHOR("Markus Gothe <markus.gothe@genexis.eu>");
> >>>> +MODULE_DESCRIPTION("Pinctrl driver for Airoha AN7583 SoC");
> >>>> -- 
> >>>> 2.53.0
> >>>>

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]

[PATCH v7 21/34] pinctrl: airoha: an7581: remove en7581 prefix from variable names

[Mikhail Kshevetskiy]

We have only an7581 specific code in the pinctrl-an7581 kernel module,
so 'en7581_' prefix is not necessary anymore. Remove it.

Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
---
 drivers/pinctrl/airoha/pinctrl-an7581.c | 398 ++++++++++++------------
 1 file changed, 199 insertions(+), 199 deletions(-)

diff --git a/drivers/pinctrl/airoha/pinctrl-an7581.c b/drivers/pinctrl/airoha/pinctrl-an7581.c
index 522b35bbaa121..6e53143e91d70 100644
--- a/drivers/pinctrl/airoha/pinctrl-an7581.c
+++ b/drivers/pinctrl/airoha/pinctrl-an7581.c
@@ -316,7 +316,7 @@
 		.regmap_size = 2,					\
 	}
 
-static struct pinctrl_pin_desc en7581_pinctrl_pins[] = {
+static struct pinctrl_pin_desc pinctrl_pins[] = {
 	PINCTRL_PIN(0, "uart1_txd"),
 	PINCTRL_PIN(1, "uart1_rxd"),
 	PINCTRL_PIN(2, "i2c_scl"),
@@ -377,184 +377,184 @@ static struct pinctrl_pin_desc en7581_pinctrl_pins[] = {
 	PINCTRL_PIN(62, "pcie_reset2"),
 };
 
-static const int en7581_pon_pins[] = { 49, 50, 51, 52, 53, 54 };
-static const int en7581_pon_tod_1pps_pins[] = { 46 };
-static const int en7581_gsw_tod_1pps_pins[] = { 46 };
-static const int en7581_sipo_pins[] = { 16, 17 };
-static const int en7581_sipo_rclk_pins[] = { 16, 17, 43 };
-static const int en7581_mdio_pins[] = { 14, 15 };
-static const int en7581_uart2_pins[] = { 48, 55 };
-static const int en7581_uart2_cts_rts_pins[] = { 46, 47 };
-static const int en7581_hsuart_pins[] = { 28, 29 };
-static const int en7581_hsuart_cts_rts_pins[] = { 26, 27 };
-static const int en7581_uart4_pins[] = { 38, 39 };
-static const int en7581_uart5_pins[] = { 18, 19 };
-static const int en7581_i2c0_pins[] = { 2, 3 };
-static const int en7581_i2c1_pins[] = { 14, 15 };
-static const int en7581_jtag_udi_pins[] = { 16, 17, 18, 19, 20 };
-static const int en7581_jtag_dfd_pins[] = { 16, 17, 18, 19, 20 };
-static const int en7581_i2s_pins[] = { 26, 27, 28, 29 };
-static const int en7581_pcm1_pins[] = { 22, 23, 24, 25 };
-static const int en7581_pcm2_pins[] = { 18, 19, 20, 21 };
-static const int en7581_spi_quad_pins[] = { 32, 33 };
-static const int en7581_spi_pins[] = { 4, 5, 6, 7 };
-static const int en7581_spi_cs1_pins[] = { 34 };
-static const int en7581_pcm_spi_pins[] = { 18, 19, 20, 21, 22, 23, 24, 25 };
-static const int en7581_pcm_spi_int_pins[] = { 14 };
-static const int en7581_pcm_spi_rst_pins[] = { 15 };
-static const int en7581_pcm_spi_cs1_pins[] = { 43 };
-static const int en7581_pcm_spi_cs2_pins[] = { 40 };
-static const int en7581_pcm_spi_cs2_p128_pins[] = { 40 };
-static const int en7581_pcm_spi_cs2_p156_pins[] = { 40 };
-static const int en7581_pcm_spi_cs3_pins[] = { 41 };
-static const int en7581_pcm_spi_cs4_pins[] = { 42 };
-static const int en7581_emmc_pins[] = {
+static const int pon_pins[] = { 49, 50, 51, 52, 53, 54 };
+static const int pon_tod_1pps_pins[] = { 46 };
+static const int gsw_tod_1pps_pins[] = { 46 };
+static const int sipo_pins[] = { 16, 17 };
+static const int sipo_rclk_pins[] = { 16, 17, 43 };
+static const int mdio_pins[] = { 14, 15 };
+static const int uart2_pins[] = { 48, 55 };
+static const int uart2_cts_rts_pins[] = { 46, 47 };
+static const int hsuart_pins[] = { 28, 29 };
+static const int hsuart_cts_rts_pins[] = { 26, 27 };
+static const int uart4_pins[] = { 38, 39 };
+static const int uart5_pins[] = { 18, 19 };
+static const int i2c0_pins[] = { 2, 3 };
+static const int i2c1_pins[] = { 14, 15 };
+static const int jtag_udi_pins[] = { 16, 17, 18, 19, 20 };
+static const int jtag_dfd_pins[] = { 16, 17, 18, 19, 20 };
+static const int i2s_pins[] = { 26, 27, 28, 29 };
+static const int pcm1_pins[] = { 22, 23, 24, 25 };
+static const int pcm2_pins[] = { 18, 19, 20, 21 };
+static const int spi_quad_pins[] = { 32, 33 };
+static const int spi_pins[] = { 4, 5, 6, 7 };
+static const int spi_cs1_pins[] = { 34 };
+static const int pcm_spi_pins[] = { 18, 19, 20, 21, 22, 23, 24, 25 };
+static const int pcm_spi_int_pins[] = { 14 };
+static const int pcm_spi_rst_pins[] = { 15 };
+static const int pcm_spi_cs1_pins[] = { 43 };
+static const int pcm_spi_cs2_pins[] = { 40 };
+static const int pcm_spi_cs2_p128_pins[] = { 40 };
+static const int pcm_spi_cs2_p156_pins[] = { 40 };
+static const int pcm_spi_cs3_pins[] = { 41 };
+static const int pcm_spi_cs4_pins[] = { 42 };
+static const int emmc_pins[] = {
 	4, 5, 6, 30, 31, 32, 33, 34, 35, 36, 37
 };
-static const int en7581_pnand_pins[] = {
+static const int pnand_pins[] = {
 	4, 5, 6, 7, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42
 };
-static const int en7581_gpio0_pins[] = { 13 };
-static const int en7581_gpio1_pins[] = { 14 };
-static const int en7581_gpio2_pins[] = { 15 };
-static const int en7581_gpio3_pins[] = { 16 };
-static const int en7581_gpio4_pins[] = { 17 };
-static const int en7581_gpio5_pins[] = { 18 };
-static const int en7581_gpio6_pins[] = { 19 };
-static const int en7581_gpio7_pins[] = { 20 };
-static const int en7581_gpio8_pins[] = { 21 };
-static const int en7581_gpio9_pins[] = { 22 };
-static const int en7581_gpio10_pins[] = { 23 };
-static const int en7581_gpio11_pins[] = { 24 };
-static const int en7581_gpio12_pins[] = { 25 };
-static const int en7581_gpio13_pins[] = { 26 };
-static const int en7581_gpio14_pins[] = { 27 };
-static const int en7581_gpio15_pins[] = { 28 };
-static const int en7581_gpio16_pins[] = { 29 };
-static const int en7581_gpio17_pins[] = { 30 };
-static const int en7581_gpio18_pins[] = { 31 };
-static const int en7581_gpio19_pins[] = { 32 };
-static const int en7581_gpio20_pins[] = { 33 };
-static const int en7581_gpio21_pins[] = { 34 };
-static const int en7581_gpio22_pins[] = { 35 };
-static const int en7581_gpio23_pins[] = { 36 };
-static const int en7581_gpio24_pins[] = { 37 };
-static const int en7581_gpio25_pins[] = { 38 };
-static const int en7581_gpio26_pins[] = { 39 };
-static const int en7581_gpio27_pins[] = { 40 };
-static const int en7581_gpio28_pins[] = { 41 };
-static const int en7581_gpio29_pins[] = { 42 };
-static const int en7581_gpio30_pins[] = { 43 };
-static const int en7581_gpio31_pins[] = { 44 };
-static const int en7581_gpio32_pins[] = { 45 };
-static const int en7581_gpio33_pins[] = { 46 };
-static const int en7581_gpio34_pins[] = { 47 };
-static const int en7581_gpio35_pins[] = { 48 };
-static const int en7581_gpio36_pins[] = { 49 };
-static const int en7581_gpio37_pins[] = { 50 };
-static const int en7581_gpio38_pins[] = { 51 };
-static const int en7581_gpio39_pins[] = { 52 };
-static const int en7581_gpio40_pins[] = { 53 };
-static const int en7581_gpio41_pins[] = { 54 };
-static const int en7581_gpio42_pins[] = { 55 };
-static const int en7581_gpio43_pins[] = { 56 };
-static const int en7581_gpio44_pins[] = { 57 };
-static const int en7581_gpio45_pins[] = { 58 };
-static const int en7581_gpio46_pins[] = { 59 };
-static const int en7581_gpio47_pins[] = { 60 };
-static const int en7581_gpio48_pins[] = { 61 };
-static const int en7581_gpio49_pins[] = { 62 };
-static const int en7581_pcie_reset0_pins[] = { 60 };
-static const int en7581_pcie_reset1_pins[] = { 61 };
-static const int en7581_pcie_reset2_pins[] = { 62 };
-
-static const struct pingroup en7581_pinctrl_groups[] = {
-	PINCTRL_PIN_GROUP("pon", en7581_pon),
-	PINCTRL_PIN_GROUP("pon_tod_1pps", en7581_pon_tod_1pps),
-	PINCTRL_PIN_GROUP("gsw_tod_1pps", en7581_gsw_tod_1pps),
-	PINCTRL_PIN_GROUP("sipo", en7581_sipo),
-	PINCTRL_PIN_GROUP("sipo_rclk", en7581_sipo_rclk),
-	PINCTRL_PIN_GROUP("mdio", en7581_mdio),
-	PINCTRL_PIN_GROUP("uart2", en7581_uart2),
-	PINCTRL_PIN_GROUP("uart2_cts_rts", en7581_uart2_cts_rts),
-	PINCTRL_PIN_GROUP("hsuart", en7581_hsuart),
-	PINCTRL_PIN_GROUP("hsuart_cts_rts", en7581_hsuart_cts_rts),
-	PINCTRL_PIN_GROUP("uart4", en7581_uart4),
-	PINCTRL_PIN_GROUP("uart5", en7581_uart5),
-	PINCTRL_PIN_GROUP("i2c0", en7581_i2c0),
-	PINCTRL_PIN_GROUP("i2c1", en7581_i2c1),
-	PINCTRL_PIN_GROUP("jtag_udi", en7581_jtag_udi),
-	PINCTRL_PIN_GROUP("jtag_dfd", en7581_jtag_dfd),
-	PINCTRL_PIN_GROUP("i2s", en7581_i2s),
-	PINCTRL_PIN_GROUP("pcm1", en7581_pcm1),
-	PINCTRL_PIN_GROUP("pcm2", en7581_pcm2),
-	PINCTRL_PIN_GROUP("spi", en7581_spi),
-	PINCTRL_PIN_GROUP("spi_quad", en7581_spi_quad),
-	PINCTRL_PIN_GROUP("spi_cs1", en7581_spi_cs1),
-	PINCTRL_PIN_GROUP("pcm_spi", en7581_pcm_spi),
-	PINCTRL_PIN_GROUP("pcm_spi_int", en7581_pcm_spi_int),
-	PINCTRL_PIN_GROUP("pcm_spi_rst", en7581_pcm_spi_rst),
-	PINCTRL_PIN_GROUP("pcm_spi_cs1", en7581_pcm_spi_cs1),
-	PINCTRL_PIN_GROUP("pcm_spi_cs2_p128", en7581_pcm_spi_cs2_p128),
-	PINCTRL_PIN_GROUP("pcm_spi_cs2_p156", en7581_pcm_spi_cs2_p156),
-	PINCTRL_PIN_GROUP("pcm_spi_cs2", en7581_pcm_spi_cs2),
-	PINCTRL_PIN_GROUP("pcm_spi_cs3", en7581_pcm_spi_cs3),
-	PINCTRL_PIN_GROUP("pcm_spi_cs4", en7581_pcm_spi_cs4),
-	PINCTRL_PIN_GROUP("emmc", en7581_emmc),
-	PINCTRL_PIN_GROUP("pnand", en7581_pnand),
-	PINCTRL_PIN_GROUP("gpio0", en7581_gpio0),
-	PINCTRL_PIN_GROUP("gpio1", en7581_gpio1),
-	PINCTRL_PIN_GROUP("gpio2", en7581_gpio2),
-	PINCTRL_PIN_GROUP("gpio3", en7581_gpio3),
-	PINCTRL_PIN_GROUP("gpio4", en7581_gpio4),
-	PINCTRL_PIN_GROUP("gpio5", en7581_gpio5),
-	PINCTRL_PIN_GROUP("gpio6", en7581_gpio6),
-	PINCTRL_PIN_GROUP("gpio7", en7581_gpio7),
-	PINCTRL_PIN_GROUP("gpio8", en7581_gpio8),
-	PINCTRL_PIN_GROUP("gpio9", en7581_gpio9),
-	PINCTRL_PIN_GROUP("gpio10", en7581_gpio10),
-	PINCTRL_PIN_GROUP("gpio11", en7581_gpio11),
-	PINCTRL_PIN_GROUP("gpio12", en7581_gpio12),
-	PINCTRL_PIN_GROUP("gpio13", en7581_gpio13),
-	PINCTRL_PIN_GROUP("gpio14", en7581_gpio14),
-	PINCTRL_PIN_GROUP("gpio15", en7581_gpio15),
-	PINCTRL_PIN_GROUP("gpio16", en7581_gpio16),
-	PINCTRL_PIN_GROUP("gpio17", en7581_gpio17),
-	PINCTRL_PIN_GROUP("gpio18", en7581_gpio18),
-	PINCTRL_PIN_GROUP("gpio19", en7581_gpio19),
-	PINCTRL_PIN_GROUP("gpio20", en7581_gpio20),
-	PINCTRL_PIN_GROUP("gpio21", en7581_gpio21),
-	PINCTRL_PIN_GROUP("gpio22", en7581_gpio22),
-	PINCTRL_PIN_GROUP("gpio23", en7581_gpio23),
-	PINCTRL_PIN_GROUP("gpio24", en7581_gpio24),
-	PINCTRL_PIN_GROUP("gpio25", en7581_gpio25),
-	PINCTRL_PIN_GROUP("gpio26", en7581_gpio26),
-	PINCTRL_PIN_GROUP("gpio27", en7581_gpio27),
-	PINCTRL_PIN_GROUP("gpio28", en7581_gpio28),
-	PINCTRL_PIN_GROUP("gpio29", en7581_gpio29),
-	PINCTRL_PIN_GROUP("gpio30", en7581_gpio30),
-	PINCTRL_PIN_GROUP("gpio31", en7581_gpio31),
-	PINCTRL_PIN_GROUP("gpio32", en7581_gpio32),
-	PINCTRL_PIN_GROUP("gpio33", en7581_gpio33),
-	PINCTRL_PIN_GROUP("gpio34", en7581_gpio34),
-	PINCTRL_PIN_GROUP("gpio35", en7581_gpio35),
-	PINCTRL_PIN_GROUP("gpio36", en7581_gpio36),
-	PINCTRL_PIN_GROUP("gpio37", en7581_gpio37),
-	PINCTRL_PIN_GROUP("gpio38", en7581_gpio38),
-	PINCTRL_PIN_GROUP("gpio39", en7581_gpio39),
-	PINCTRL_PIN_GROUP("gpio40", en7581_gpio40),
-	PINCTRL_PIN_GROUP("gpio41", en7581_gpio41),
-	PINCTRL_PIN_GROUP("gpio42", en7581_gpio42),
-	PINCTRL_PIN_GROUP("gpio43", en7581_gpio43),
-	PINCTRL_PIN_GROUP("gpio44", en7581_gpio44),
-	PINCTRL_PIN_GROUP("gpio45", en7581_gpio45),
-	PINCTRL_PIN_GROUP("gpio46", en7581_gpio46),
-	PINCTRL_PIN_GROUP("gpio47", en7581_gpio47),
-	PINCTRL_PIN_GROUP("gpio48", en7581_gpio48),
-	PINCTRL_PIN_GROUP("gpio49", en7581_gpio49),
-	PINCTRL_PIN_GROUP("pcie_reset0", en7581_pcie_reset0),
-	PINCTRL_PIN_GROUP("pcie_reset1", en7581_pcie_reset1),
-	PINCTRL_PIN_GROUP("pcie_reset2", en7581_pcie_reset2),
+static const int gpio0_pins[] = { 13 };
+static const int gpio1_pins[] = { 14 };
+static const int gpio2_pins[] = { 15 };
+static const int gpio3_pins[] = { 16 };
+static const int gpio4_pins[] = { 17 };
+static const int gpio5_pins[] = { 18 };
+static const int gpio6_pins[] = { 19 };
+static const int gpio7_pins[] = { 20 };
+static const int gpio8_pins[] = { 21 };
+static const int gpio9_pins[] = { 22 };
+static const int gpio10_pins[] = { 23 };
+static const int gpio11_pins[] = { 24 };
+static const int gpio12_pins[] = { 25 };
+static const int gpio13_pins[] = { 26 };
+static const int gpio14_pins[] = { 27 };
+static const int gpio15_pins[] = { 28 };
+static const int gpio16_pins[] = { 29 };
+static const int gpio17_pins[] = { 30 };
+static const int gpio18_pins[] = { 31 };
+static const int gpio19_pins[] = { 32 };
+static const int gpio20_pins[] = { 33 };
+static const int gpio21_pins[] = { 34 };
+static const int gpio22_pins[] = { 35 };
+static const int gpio23_pins[] = { 36 };
+static const int gpio24_pins[] = { 37 };
+static const int gpio25_pins[] = { 38 };
+static const int gpio26_pins[] = { 39 };
+static const int gpio27_pins[] = { 40 };
+static const int gpio28_pins[] = { 41 };
+static const int gpio29_pins[] = { 42 };
+static const int gpio30_pins[] = { 43 };
+static const int gpio31_pins[] = { 44 };
+static const int gpio32_pins[] = { 45 };
+static const int gpio33_pins[] = { 46 };
+static const int gpio34_pins[] = { 47 };
+static const int gpio35_pins[] = { 48 };
+static const int gpio36_pins[] = { 49 };
+static const int gpio37_pins[] = { 50 };
+static const int gpio38_pins[] = { 51 };
+static const int gpio39_pins[] = { 52 };
+static const int gpio40_pins[] = { 53 };
+static const int gpio41_pins[] = { 54 };
+static const int gpio42_pins[] = { 55 };
+static const int gpio43_pins[] = { 56 };
+static const int gpio44_pins[] = { 57 };
+static const int gpio45_pins[] = { 58 };
+static const int gpio46_pins[] = { 59 };
+static const int gpio47_pins[] = { 60 };
+static const int gpio48_pins[] = { 61 };
+static const int gpio49_pins[] = { 62 };
+static const int pcie_reset0_pins[] = { 60 };
+static const int pcie_reset1_pins[] = { 61 };
+static const int pcie_reset2_pins[] = { 62 };
+
+static const struct pingroup pinctrl_groups[] = {
+	PINCTRL_PIN_GROUP("pon", pon),
+	PINCTRL_PIN_GROUP("pon_tod_1pps", pon_tod_1pps),
+	PINCTRL_PIN_GROUP("gsw_tod_1pps", gsw_tod_1pps),
+	PINCTRL_PIN_GROUP("sipo", sipo),
+	PINCTRL_PIN_GROUP("sipo_rclk", sipo_rclk),
+	PINCTRL_PIN_GROUP("mdio", mdio),
+	PINCTRL_PIN_GROUP("uart2", uart2),
+	PINCTRL_PIN_GROUP("uart2_cts_rts", uart2_cts_rts),
+	PINCTRL_PIN_GROUP("hsuart", hsuart),
+	PINCTRL_PIN_GROUP("hsuart_cts_rts", hsuart_cts_rts),
+	PINCTRL_PIN_GROUP("uart4", uart4),
+	PINCTRL_PIN_GROUP("uart5", uart5),
+	PINCTRL_PIN_GROUP("i2c0", i2c0),
+	PINCTRL_PIN_GROUP("i2c1", i2c1),
+	PINCTRL_PIN_GROUP("jtag_udi", jtag_udi),
+	PINCTRL_PIN_GROUP("jtag_dfd", jtag_dfd),
+	PINCTRL_PIN_GROUP("i2s", i2s),
+	PINCTRL_PIN_GROUP("pcm1", pcm1),
+	PINCTRL_PIN_GROUP("pcm2", pcm2),
+	PINCTRL_PIN_GROUP("spi", spi),
+	PINCTRL_PIN_GROUP("spi_quad", spi_quad),
+	PINCTRL_PIN_GROUP("spi_cs1", spi_cs1),
+	PINCTRL_PIN_GROUP("pcm_spi", pcm_spi),
+	PINCTRL_PIN_GROUP("pcm_spi_int", pcm_spi_int),
+	PINCTRL_PIN_GROUP("pcm_spi_rst", pcm_spi_rst),
+	PINCTRL_PIN_GROUP("pcm_spi_cs1", pcm_spi_cs1),
+	PINCTRL_PIN_GROUP("pcm_spi_cs2_p128", pcm_spi_cs2_p128),
+	PINCTRL_PIN_GROUP("pcm_spi_cs2_p156", pcm_spi_cs2_p156),
+	PINCTRL_PIN_GROUP("pcm_spi_cs2", pcm_spi_cs2),
+	PINCTRL_PIN_GROUP("pcm_spi_cs3", pcm_spi_cs3),
+	PINCTRL_PIN_GROUP("pcm_spi_cs4", pcm_spi_cs4),
+	PINCTRL_PIN_GROUP("emmc", emmc),
+	PINCTRL_PIN_GROUP("pnand", pnand),
+	PINCTRL_PIN_GROUP("gpio0", gpio0),
+	PINCTRL_PIN_GROUP("gpio1", gpio1),
+	PINCTRL_PIN_GROUP("gpio2", gpio2),
+	PINCTRL_PIN_GROUP("gpio3", gpio3),
+	PINCTRL_PIN_GROUP("gpio4", gpio4),
+	PINCTRL_PIN_GROUP("gpio5", gpio5),
+	PINCTRL_PIN_GROUP("gpio6", gpio6),
+	PINCTRL_PIN_GROUP("gpio7", gpio7),
+	PINCTRL_PIN_GROUP("gpio8", gpio8),
+	PINCTRL_PIN_GROUP("gpio9", gpio9),
+	PINCTRL_PIN_GROUP("gpio10", gpio10),
+	PINCTRL_PIN_GROUP("gpio11", gpio11),
+	PINCTRL_PIN_GROUP("gpio12", gpio12),
+	PINCTRL_PIN_GROUP("gpio13", gpio13),
+	PINCTRL_PIN_GROUP("gpio14", gpio14),
+	PINCTRL_PIN_GROUP("gpio15", gpio15),
+	PINCTRL_PIN_GROUP("gpio16", gpio16),
+	PINCTRL_PIN_GROUP("gpio17", gpio17),
+	PINCTRL_PIN_GROUP("gpio18", gpio18),
+	PINCTRL_PIN_GROUP("gpio19", gpio19),
+	PINCTRL_PIN_GROUP("gpio20", gpio20),
+	PINCTRL_PIN_GROUP("gpio21", gpio21),
+	PINCTRL_PIN_GROUP("gpio22", gpio22),
+	PINCTRL_PIN_GROUP("gpio23", gpio23),
+	PINCTRL_PIN_GROUP("gpio24", gpio24),
+	PINCTRL_PIN_GROUP("gpio25", gpio25),
+	PINCTRL_PIN_GROUP("gpio26", gpio26),
+	PINCTRL_PIN_GROUP("gpio27", gpio27),
+	PINCTRL_PIN_GROUP("gpio28", gpio28),
+	PINCTRL_PIN_GROUP("gpio29", gpio29),
+	PINCTRL_PIN_GROUP("gpio30", gpio30),
+	PINCTRL_PIN_GROUP("gpio31", gpio31),
+	PINCTRL_PIN_GROUP("gpio32", gpio32),
+	PINCTRL_PIN_GROUP("gpio33", gpio33),
+	PINCTRL_PIN_GROUP("gpio34", gpio34),
+	PINCTRL_PIN_GROUP("gpio35", gpio35),
+	PINCTRL_PIN_GROUP("gpio36", gpio36),
+	PINCTRL_PIN_GROUP("gpio37", gpio37),
+	PINCTRL_PIN_GROUP("gpio38", gpio38),
+	PINCTRL_PIN_GROUP("gpio39", gpio39),
+	PINCTRL_PIN_GROUP("gpio40", gpio40),
+	PINCTRL_PIN_GROUP("gpio41", gpio41),
+	PINCTRL_PIN_GROUP("gpio42", gpio42),
+	PINCTRL_PIN_GROUP("gpio43", gpio43),
+	PINCTRL_PIN_GROUP("gpio44", gpio44),
+	PINCTRL_PIN_GROUP("gpio45", gpio45),
+	PINCTRL_PIN_GROUP("gpio46", gpio46),
+	PINCTRL_PIN_GROUP("gpio47", gpio47),
+	PINCTRL_PIN_GROUP("gpio48", gpio48),
+	PINCTRL_PIN_GROUP("gpio49", gpio49),
+	PINCTRL_PIN_GROUP("pcie_reset0", pcie_reset0),
+	PINCTRL_PIN_GROUP("pcie_reset1", pcie_reset1),
+	PINCTRL_PIN_GROUP("pcie_reset2", pcie_reset2),
 };
 
 static const char *const pon_groups[] = { "pon" };
@@ -1154,7 +1154,7 @@ static const struct airoha_pinctrl_func_group phy4_led1_func_group[] = {
 				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)),
 };
 
-static const struct airoha_pinctrl_func en7581_pinctrl_funcs[] = {
+static const struct airoha_pinctrl_func pinctrl_funcs[] = {
 	PINCTRL_FUNC_DESC("pon", pon),
 	PINCTRL_FUNC_DESC("tod_1pps", tod_1pps),
 	PINCTRL_FUNC_DESC("sipo", sipo),
@@ -1181,7 +1181,7 @@ static const struct airoha_pinctrl_func en7581_pinctrl_funcs[] = {
 	PINCTRL_FUNC_DESC("phy4_led1", phy4_led1),
 };
 
-static const struct airoha_pinctrl_conf en7581_pinctrl_pullup_conf[] = {
+static const struct airoha_pinctrl_conf pinctrl_pullup_conf[] = {
 	PINCTRL_CONF_DESC(0, REG_I2C_SDA_PU, UART1_TXD_PU_MASK),
 	PINCTRL_CONF_DESC(1, REG_I2C_SDA_PU, UART1_RXD_PU_MASK),
 	PINCTRL_CONF_DESC(2, REG_I2C_SDA_PU, I2C_SDA_PU_MASK),
@@ -1242,7 +1242,7 @@ static const struct airoha_pinctrl_conf en7581_pinctrl_pullup_conf[] = {
 	PINCTRL_CONF_DESC(62, REG_I2C_SDA_PU, PCIE2_RESET_PU_MASK),
 };
 
-static const struct airoha_pinctrl_conf en7581_pinctrl_pulldown_conf[] = {
+static const struct airoha_pinctrl_conf pinctrl_pulldown_conf[] = {
 	PINCTRL_CONF_DESC(0, REG_I2C_SDA_PD, UART1_TXD_PD_MASK),
 	PINCTRL_CONF_DESC(1, REG_I2C_SDA_PD, UART1_RXD_PD_MASK),
 	PINCTRL_CONF_DESC(2, REG_I2C_SDA_PD, I2C_SDA_PD_MASK),
@@ -1303,7 +1303,7 @@ static const struct airoha_pinctrl_conf en7581_pinctrl_pulldown_conf[] = {
 	PINCTRL_CONF_DESC(62, REG_I2C_SDA_PD, PCIE2_RESET_PD_MASK),
 };
 
-static const struct airoha_pinctrl_conf en7581_pinctrl_drive_e2_conf[] = {
+static const struct airoha_pinctrl_conf pinctrl_drive_e2_conf[] = {
 	PINCTRL_CONF_DESC(0, REG_I2C_SDA_E2, UART1_TXD_E2_MASK),
 	PINCTRL_CONF_DESC(1, REG_I2C_SDA_E2, UART1_RXD_E2_MASK),
 	PINCTRL_CONF_DESC(2, REG_I2C_SDA_E2, I2C_SDA_E2_MASK),
@@ -1364,7 +1364,7 @@ static const struct airoha_pinctrl_conf en7581_pinctrl_drive_e2_conf[] = {
 	PINCTRL_CONF_DESC(62, REG_I2C_SDA_E2, PCIE2_RESET_E2_MASK),
 };
 
-static const struct airoha_pinctrl_conf en7581_pinctrl_drive_e4_conf[] = {
+static const struct airoha_pinctrl_conf pinctrl_drive_e4_conf[] = {
 	PINCTRL_CONF_DESC(0, REG_I2C_SDA_E4, UART1_TXD_E4_MASK),
 	PINCTRL_CONF_DESC(1, REG_I2C_SDA_E4, UART1_RXD_E4_MASK),
 	PINCTRL_CONF_DESC(2, REG_I2C_SDA_E4, I2C_SDA_E4_MASK),
@@ -1425,47 +1425,47 @@ static const struct airoha_pinctrl_conf en7581_pinctrl_drive_e4_conf[] = {
 	PINCTRL_CONF_DESC(62, REG_I2C_SDA_E4, PCIE2_RESET_E4_MASK),
 };
 
-static const struct airoha_pinctrl_conf en7581_pinctrl_pcie_rst_od_conf[] = {
+static const struct airoha_pinctrl_conf pinctrl_pcie_rst_od_conf[] = {
 	PINCTRL_CONF_DESC(60, REG_PCIE_RESET_OD, PCIE0_RESET_OD_MASK),
 	PINCTRL_CONF_DESC(61, REG_PCIE_RESET_OD, PCIE1_RESET_OD_MASK),
 	PINCTRL_CONF_DESC(62, REG_PCIE_RESET_OD, PCIE2_RESET_OD_MASK),
 };
 
-static const struct airoha_pinctrl_match_data en7581_pinctrl_match_data = {
+static const struct airoha_pinctrl_match_data pinctrl_match_data = {
 	.pinctrl_name = KBUILD_MODNAME,
 	.pinctrl_owner = THIS_MODULE,
-	.pins = en7581_pinctrl_pins,
-	.num_pins = ARRAY_SIZE(en7581_pinctrl_pins),
-	.grps = en7581_pinctrl_groups,
-	.num_grps = ARRAY_SIZE(en7581_pinctrl_groups),
-	.funcs = en7581_pinctrl_funcs,
-	.num_funcs = ARRAY_SIZE(en7581_pinctrl_funcs),
+	.pins = pinctrl_pins,
+	.num_pins = ARRAY_SIZE(pinctrl_pins),
+	.grps = pinctrl_groups,
+	.num_grps = ARRAY_SIZE(pinctrl_groups),
+	.funcs = pinctrl_funcs,
+	.num_funcs = ARRAY_SIZE(pinctrl_funcs),
 	.confs_info = {
 		[AIROHA_PINCTRL_CONFS_PULLUP] = {
-			.confs = en7581_pinctrl_pullup_conf,
-			.num_confs = ARRAY_SIZE(en7581_pinctrl_pullup_conf),
+			.confs = pinctrl_pullup_conf,
+			.num_confs = ARRAY_SIZE(pinctrl_pullup_conf),
 		},
 		[AIROHA_PINCTRL_CONFS_PULLDOWN] = {
-			.confs = en7581_pinctrl_pulldown_conf,
-			.num_confs = ARRAY_SIZE(en7581_pinctrl_pulldown_conf),
+			.confs = pinctrl_pulldown_conf,
+			.num_confs = ARRAY_SIZE(pinctrl_pulldown_conf),
 		},
 		[AIROHA_PINCTRL_CONFS_DRIVE_E2] = {
-			.confs = en7581_pinctrl_drive_e2_conf,
-			.num_confs = ARRAY_SIZE(en7581_pinctrl_drive_e2_conf),
+			.confs = pinctrl_drive_e2_conf,
+			.num_confs = ARRAY_SIZE(pinctrl_drive_e2_conf),
 		},
 		[AIROHA_PINCTRL_CONFS_DRIVE_E4] = {
-			.confs = en7581_pinctrl_drive_e4_conf,
-			.num_confs = ARRAY_SIZE(en7581_pinctrl_drive_e4_conf),
+			.confs = pinctrl_drive_e4_conf,
+			.num_confs = ARRAY_SIZE(pinctrl_drive_e4_conf),
 		},
 		[AIROHA_PINCTRL_CONFS_PCIE_RST_OD] = {
-			.confs = en7581_pinctrl_pcie_rst_od_conf,
-			.num_confs = ARRAY_SIZE(en7581_pinctrl_pcie_rst_od_conf),
+			.confs = pinctrl_pcie_rst_od_conf,
+			.num_confs = ARRAY_SIZE(pinctrl_pcie_rst_od_conf),
 		},
 	},
 };
 
 static const struct of_device_id airoha_pinctrl_of_match[] = {
-	{ .compatible = "airoha,en7581-pinctrl", .data = &en7581_pinctrl_match_data },
+	{ .compatible = "airoha,en7581-pinctrl", .data = &pinctrl_match_data },
 	{ /* sentinel */ }
 };
 MODULE_DEVICE_TABLE(of, airoha_pinctrl_of_match);
-- 
2.53.0

[PATCH v7 22/34] pinctrl: airoha: an7583: remove an7583 prefix from variable names and definitions

[Mikhail Kshevetskiy]

We have only an7583 specific code in the pinctrl-an7583 kernel module,
so an7583 prefix is not necessary anymore. Remove it.

Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
---
 drivers/pinctrl/airoha/pinctrl-an7583.c | 600 ++++++++++++------------
 1 file changed, 300 insertions(+), 300 deletions(-)

diff --git a/drivers/pinctrl/airoha/pinctrl-an7583.c b/drivers/pinctrl/airoha/pinctrl-an7583.c
index b9d8dd94de5f0..637b9377ff8fc 100644
--- a/drivers/pinctrl/airoha/pinctrl-an7583.c
+++ b/drivers/pinctrl/airoha/pinctrl-an7583.c
@@ -24,7 +24,7 @@
 #define GPIO_MDC_IO_MASTER_MODE_MASK		BIT(22)
 #define GPIO_PCM_SPI_CS4_MODE_MASK		BIT(21)
 #define GPIO_PCM_SPI_CS3_MODE_MASK		BIT(20)
-#define AN7583_GPIO_PCM_SPI_CS2_MODE_MASK	BIT(18)
+#define GPIO_PCM_SPI_CS2_MODE_MASK		BIT(18)
 #define GPIO_PCM_SPI_CS1_MODE_MASK		BIT(17)
 #define GPIO_PCM_SPI_MODE_MASK			BIT(16)
 #define GPIO_PCM2_MODE_MASK			BIT(13)
@@ -38,18 +38,18 @@
 #define GPIO_SPI_CS1_MODE_MASK			BIT(0)
 
 #define REG_GPIO_PON_MODE			0x021c
-#define AN7583_MDIO_0_GPIO_MODE_MASK		BIT(26)
-#define AN7583_MDC_0_GPIO_MODE_MASK		BIT(25)
-#define AN7583_UART_RXD_GPIO_MODE_MASK		BIT(24)
-#define AN7583_UART_TXD_GPIO_MODE_MASK		BIT(23)
-#define AN7583_SPI_MISO_GPIO_MODE_MASK		BIT(22)
-#define AN7583_SPI_MOSI_GPIO_MODE_MASK		BIT(21)
-#define AN7583_SPI_CS_GPIO_MODE_MASK		BIT(20)
-#define AN7583_SPI_CLK_GPIO_MODE_MASK		BIT(19)
-#define AN7583_I2C1_SDA_GPIO_MODE_MASK		BIT(18)
-#define AN7583_I2C1_SCL_GPIO_MODE_MASK		BIT(17)
-#define AN7583_I2C0_SDA_GPIO_MODE_MASK		BIT(16)
-#define AN7583_I2C0_SCL_GPIO_MODE_MASK		BIT(15)
+#define MDIO_0_GPIO_MODE_MASK			BIT(26)
+#define MDC_0_GPIO_MODE_MASK			BIT(25)
+#define UART_RXD_GPIO_MODE_MASK			BIT(24)
+#define UART_TXD_GPIO_MODE_MASK			BIT(23)
+#define SPI_MISO_GPIO_MODE_MASK			BIT(22)
+#define SPI_MOSI_GPIO_MODE_MASK			BIT(21)
+#define SPI_CS_GPIO_MODE_MASK			BIT(20)
+#define SPI_CLK_GPIO_MODE_MASK			BIT(19)
+#define I2C1_SDA_GPIO_MODE_MASK			BIT(18)
+#define I2C1_SCL_GPIO_MODE_MASK			BIT(17)
+#define I2C0_SDA_GPIO_MODE_MASK			BIT(16)
+#define I2C0_SCL_GPIO_MODE_MASK			BIT(15)
 #define GPIO_PARALLEL_NAND_MODE_MASK		BIT(14)
 #define GPIO_SGMII_MDIO_MODE_MASK		BIT(13)
 #define SIPO_RCLK_MODE_MASK			BIT(11)
@@ -93,32 +93,32 @@
 
 /* CONF */
 #define REG_I2C_SDA_E2				0x001c
-#define AN7583_I2C1_SCL_E2_MASK			BIT(16)
-#define AN7583_I2C1_SDA_E2_MASK			BIT(15)
+#define I2C1_SCL_E2_MASK			BIT(16)
+#define I2C1_SDA_E2_MASK			BIT(15)
 #define SPI_MISO_E2_MASK			BIT(14)
 #define SPI_MOSI_E2_MASK			BIT(13)
 #define SPI_CLK_E2_MASK				BIT(12)
 #define SPI_CS0_E2_MASK				BIT(11)
 #define PCIE1_RESET_E2_MASK			BIT(9)
 #define PCIE0_RESET_E2_MASK			BIT(8)
-#define AN7583_MDIO_0_E2_MASK			BIT(5)
-#define AN7583_MDC_0_E2_MASK			BIT(4)
+#define MDIO_0_E2_MASK				BIT(5)
+#define MDC_0_E2_MASK				BIT(4)
 #define UART1_RXD_E2_MASK			BIT(3)
 #define UART1_TXD_E2_MASK			BIT(2)
 #define I2C_SCL_E2_MASK				BIT(1)
 #define I2C_SDA_E2_MASK				BIT(0)
 
 #define REG_I2C_SDA_E4				0x0020
-#define AN7583_I2C1_SCL_E4_MASK			BIT(16)
-#define AN7583_I2C1_SDA_E4_MASK			BIT(15)
+#define I2C1_SCL_E4_MASK			BIT(16)
+#define I2C1_SDA_E4_MASK			BIT(15)
 #define SPI_MISO_E4_MASK			BIT(14)
 #define SPI_MOSI_E4_MASK			BIT(13)
 #define SPI_CLK_E4_MASK				BIT(12)
 #define SPI_CS0_E4_MASK				BIT(11)
 #define PCIE1_RESET_E4_MASK			BIT(9)
 #define PCIE0_RESET_E4_MASK			BIT(8)
-#define AN7583_MDIO_0_E4_MASK			BIT(5)
-#define AN7583_MDC_0_E4_MASK			BIT(4)
+#define MDIO_0_E4_MASK				BIT(5)
+#define MDC_0_E4_MASK				BIT(4)
 #define UART1_RXD_E4_MASK			BIT(3)
 #define UART1_TXD_E4_MASK			BIT(2)
 #define I2C_SCL_E4_MASK				BIT(1)
@@ -130,32 +130,32 @@
 #define REG_GPIO_H_E4				0x0030
 
 #define REG_I2C_SDA_PU				0x0044
-#define AN7583_I2C1_SCL_PU_MASK			BIT(16)
-#define AN7583_I2C1_SDA_PU_MASK			BIT(15)
+#define I2C1_SCL_PU_MASK			BIT(16)
+#define I2C1_SDA_PU_MASK			BIT(15)
 #define SPI_MISO_PU_MASK			BIT(14)
 #define SPI_MOSI_PU_MASK			BIT(13)
 #define SPI_CLK_PU_MASK				BIT(12)
 #define SPI_CS0_PU_MASK				BIT(11)
 #define PCIE1_RESET_PU_MASK			BIT(9)
 #define PCIE0_RESET_PU_MASK			BIT(8)
-#define AN7583_MDIO_0_PU_MASK			BIT(5)
-#define AN7583_MDC_0_PU_MASK			BIT(4)
+#define MDIO_0_PU_MASK				BIT(5)
+#define MDC_0_PU_MASK				BIT(4)
 #define UART1_RXD_PU_MASK			BIT(3)
 #define UART1_TXD_PU_MASK			BIT(2)
 #define I2C_SCL_PU_MASK				BIT(1)
 #define I2C_SDA_PU_MASK				BIT(0)
 
 #define REG_I2C_SDA_PD				0x0048
-#define AN7583_I2C1_SCL_PD_MASK			BIT(16)
-#define AN7583_I2C1_SDA_PD_MASK			BIT(15)
+#define I2C1_SCL_PD_MASK			BIT(16)
+#define I2C1_SDA_PD_MASK			BIT(15)
 #define SPI_MISO_PD_MASK			BIT(14)
 #define SPI_MOSI_PD_MASK			BIT(13)
 #define SPI_CLK_PD_MASK				BIT(12)
 #define SPI_CS0_PD_MASK				BIT(11)
 #define PCIE1_RESET_PD_MASK			BIT(9)
 #define PCIE0_RESET_PD_MASK			BIT(8)
-#define AN7583_MDIO_0_PD_MASK			BIT(5)
-#define AN7583_MDC_0_PD_MASK			BIT(4)
+#define MDIO_0_PD_MASK				BIT(5)
+#define MDC_0_PD_MASK				BIT(4)
 #define UART1_RXD_PD_MASK			BIT(3)
 #define UART1_TXD_PD_MASK			BIT(2)
 #define I2C_SCL_PD_MASK				BIT(1)
@@ -333,7 +333,7 @@
 		.regmap_size = 2,					\
 	}
 
-static struct pinctrl_pin_desc an7583_pinctrl_pins[] = {
+static struct pinctrl_pin_desc pinctrl_pins[] = {
 	PINCTRL_PIN(2, "gpio0"),
 	PINCTRL_PIN(3, "gpio1"),
 	PINCTRL_PIN(4, "gpio2"),
@@ -389,176 +389,176 @@ static struct pinctrl_pin_desc an7583_pinctrl_pins[] = {
 	PINCTRL_PIN(54, "mdio_0"),
 };
 
-static const int an7583_pon_pins[] = { 15, 16, 17, 18, 19, 20 };
-static const int an7583_pon_tod_1pps_pins[] = { 32 };
-static const int an7583_gsw_tod_1pps_pins[] = { 32 };
-static const int an7583_sipo_pins[] = { 34, 35 };
-static const int an7583_sipo_rclk_pins[] = { 34, 35, 33 };
-static const int an7583_mdio_pins[] = { 43, 44 };
-static const int an7583_uart2_pins[] = { 34, 35 };
-static const int an7583_uart2_cts_rts_pins[] = { 32, 33 };
-static const int an7583_hsuart_pins[] = { 30, 31 };
-static const int an7583_hsuart_cts_rts_pins[] = { 28, 29 };
-static const int an7583_npu_uart_pins[] = { 7, 8 };
-static const int an7583_uart4_pins[] = { 7, 8 };
-static const int an7583_uart5_pins[] = { 23, 24 };
-static const int an7583_i2c0_pins[] = { 41, 42 };
-static const int an7583_i2c1_pins[] = { 43, 44 };
-static const int an7583_jtag_udi_pins[] = { 23, 24, 22, 25, 26 };
-static const int an7583_jtag_dfd_pins[] = { 23, 24, 22, 25, 26 };
-static const int an7583_pcm1_pins[] = { 10, 11, 12, 13, 14 };
-static const int an7583_pcm2_pins[] = { 28, 29, 30, 31, 24 };
-static const int an7583_spi_pins[] = { 28, 29, 30, 31 };
-static const int an7583_spi_quad_pins[] = { 25, 26 };
-static const int an7583_spi_cs1_pins[] = { 27 };
-static const int an7583_pcm_spi_pins[] = { 28, 29, 30, 31, 10, 11, 12, 13 };
-static const int an7583_pcm_spi_rst_pins[] = { 14 };
-static const int an7583_pcm_spi_cs1_pins[] = { 24 };
-static const int an7583_emmc_pins[] = {
+static const int pon_pins[] = { 15, 16, 17, 18, 19, 20 };
+static const int pon_tod_1pps_pins[] = { 32 };
+static const int gsw_tod_1pps_pins[] = { 32 };
+static const int sipo_pins[] = { 34, 35 };
+static const int sipo_rclk_pins[] = { 34, 35, 33 };
+static const int mdio_pins[] = { 43, 44 };
+static const int uart2_pins[] = { 34, 35 };
+static const int uart2_cts_rts_pins[] = { 32, 33 };
+static const int hsuart_pins[] = { 30, 31 };
+static const int hsuart_cts_rts_pins[] = { 28, 29 };
+static const int npu_uart_pins[] = { 7, 8 };
+static const int uart4_pins[] = { 7, 8 };
+static const int uart5_pins[] = { 23, 24 };
+static const int i2c0_pins[] = { 41, 42 };
+static const int i2c1_pins[] = { 43, 44 };
+static const int jtag_udi_pins[] = { 23, 24, 22, 25, 26 };
+static const int jtag_dfd_pins[] = { 23, 24, 22, 25, 26 };
+static const int pcm1_pins[] = { 10, 11, 12, 13, 14 };
+static const int pcm2_pins[] = { 28, 29, 30, 31, 24 };
+static const int spi_pins[] = { 28, 29, 30, 31 };
+static const int spi_quad_pins[] = { 25, 26 };
+static const int spi_cs1_pins[] = { 27 };
+static const int pcm_spi_pins[] = { 28, 29, 30, 31, 10, 11, 12, 13 };
+static const int pcm_spi_rst_pins[] = { 14 };
+static const int pcm_spi_cs1_pins[] = { 24 };
+static const int emmc_pins[] = {
 	7, 8, 9, 22, 23, 24, 25, 26, 45, 46, 47
 };
-static const int an7583_pnand_pins[] = {
+static const int pnand_pins[] = {
 	7, 8, 9, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 45, 46, 47, 48
 };
-static const int an7583_gpio0_pins[] = { 2 };
-static const int an7583_gpio1_pins[] = { 3 };
-static const int an7583_gpio2_pins[] = { 4 };
-static const int an7583_gpio3_pins[] = { 5 };
-static const int an7583_gpio4_pins[] = { 6 };
-static const int an7583_gpio5_pins[] = { 7 };
-static const int an7583_gpio6_pins[] = { 8 };
-static const int an7583_gpio7_pins[] = { 9 };
-static const int an7583_gpio8_pins[] = { 10 };
-static const int an7583_gpio9_pins[] = { 11 };
-static const int an7583_gpio10_pins[] = { 12 };
-static const int an7583_gpio11_pins[] = { 13 };
-static const int an7583_gpio12_pins[] = { 14 };
-static const int an7583_gpio13_pins[] = { 15 };
-static const int an7583_gpio14_pins[] = { 16 };
-static const int an7583_gpio15_pins[] = { 17 };
-static const int an7583_gpio16_pins[] = { 18 };
-static const int an7583_gpio17_pins[] = { 19 };
-static const int an7583_gpio18_pins[] = { 20 };
-static const int an7583_gpio19_pins[] = { 21 };
-static const int an7583_gpio20_pins[] = { 22 };
-static const int an7583_gpio21_pins[] = { 23 };
-static const int an7583_gpio22_pins[] = { 24 };
-static const int an7583_gpio23_pins[] = { 25 };
-static const int an7583_gpio24_pins[] = { 26 };
-static const int an7583_gpio25_pins[] = { 27 };
-static const int an7583_gpio26_pins[] = { 28 };
-static const int an7583_gpio27_pins[] = { 29 };
-static const int an7583_gpio28_pins[] = { 30 };
-static const int an7583_gpio29_pins[] = { 31 };
-static const int an7583_gpio30_pins[] = { 32 };
-static const int an7583_gpio31_pins[] = { 33 };
-static const int an7583_gpio32_pins[] = { 34 };
-static const int an7583_gpio33_pins[] = { 35 };
-static const int an7583_gpio34_pins[] = { 36 };
-static const int an7583_gpio35_pins[] = { 37 };
-static const int an7583_gpio36_pins[] = { 38 };
-static const int an7583_gpio37_pins[] = { 39 };
-static const int an7583_gpio38_pins[] = { 40 };
-static const int an7583_gpio39_pins[] = { 41 };
-static const int an7583_gpio40_pins[] = { 42 };
-static const int an7583_gpio41_pins[] = { 43 };
-static const int an7583_gpio42_pins[] = { 44 };
-static const int an7583_gpio43_pins[] = { 45 };
-static const int an7583_gpio44_pins[] = { 46 };
-static const int an7583_gpio45_pins[] = { 47 };
-static const int an7583_gpio46_pins[] = { 48 };
-static const int an7583_gpio47_pins[] = { 49 };
-static const int an7583_gpio48_pins[] = { 50 };
-static const int an7583_gpio49_pins[] = { 51 };
-static const int an7583_gpio50_pins[] = { 52 };
-static const int an7583_gpio51_pins[] = { 53 };
-static const int an7583_gpio52_pins[] = { 54 };
-static const int an7583_pcie_reset0_pins[] = { 51 };
-static const int an7583_pcie_reset1_pins[] = { 52 };
-
-static const struct pingroup an7583_pinctrl_groups[] = {
-	PINCTRL_PIN_GROUP("pon", an7583_pon),
-	PINCTRL_PIN_GROUP("pon_tod_1pps", an7583_pon_tod_1pps),
-	PINCTRL_PIN_GROUP("gsw_tod_1pps", an7583_gsw_tod_1pps),
-	PINCTRL_PIN_GROUP("sipo", an7583_sipo),
-	PINCTRL_PIN_GROUP("sipo_rclk", an7583_sipo_rclk),
-	PINCTRL_PIN_GROUP("mdio", an7583_mdio),
-	PINCTRL_PIN_GROUP("uart2", an7583_uart2),
-	PINCTRL_PIN_GROUP("uart2_cts_rts", an7583_uart2_cts_rts),
-	PINCTRL_PIN_GROUP("hsuart", an7583_hsuart),
-	PINCTRL_PIN_GROUP("hsuart_cts_rts", an7583_hsuart_cts_rts),
-	PINCTRL_PIN_GROUP("npu_uart", an7583_npu_uart),
-	PINCTRL_PIN_GROUP("uart4", an7583_uart4),
-	PINCTRL_PIN_GROUP("uart5", an7583_uart5),
-	PINCTRL_PIN_GROUP("i2c0", an7583_i2c0),
-	PINCTRL_PIN_GROUP("i2c1", an7583_i2c1),
-	PINCTRL_PIN_GROUP("jtag_udi", an7583_jtag_udi),
-	PINCTRL_PIN_GROUP("jtag_dfd", an7583_jtag_dfd),
-	PINCTRL_PIN_GROUP("pcm1", an7583_pcm1),
-	PINCTRL_PIN_GROUP("pcm2", an7583_pcm2),
-	PINCTRL_PIN_GROUP("spi", an7583_spi),
-	PINCTRL_PIN_GROUP("spi_quad", an7583_spi_quad),
-	PINCTRL_PIN_GROUP("spi_cs1", an7583_spi_cs1),
-	PINCTRL_PIN_GROUP("pcm_spi", an7583_pcm_spi),
-	PINCTRL_PIN_GROUP("pcm_spi_rst", an7583_pcm_spi_rst),
-	PINCTRL_PIN_GROUP("pcm_spi_cs1", an7583_pcm_spi_cs1),
-	PINCTRL_PIN_GROUP("emmc", an7583_emmc),
-	PINCTRL_PIN_GROUP("pnand", an7583_pnand),
-	PINCTRL_PIN_GROUP("gpio0", an7583_gpio0),
-	PINCTRL_PIN_GROUP("gpio1", an7583_gpio1),
-	PINCTRL_PIN_GROUP("gpio2", an7583_gpio2),
-	PINCTRL_PIN_GROUP("gpio3", an7583_gpio3),
-	PINCTRL_PIN_GROUP("gpio4", an7583_gpio4),
-	PINCTRL_PIN_GROUP("gpio5", an7583_gpio5),
-	PINCTRL_PIN_GROUP("gpio6", an7583_gpio6),
-	PINCTRL_PIN_GROUP("gpio7", an7583_gpio7),
-	PINCTRL_PIN_GROUP("gpio8", an7583_gpio8),
-	PINCTRL_PIN_GROUP("gpio9", an7583_gpio9),
-	PINCTRL_PIN_GROUP("gpio10", an7583_gpio10),
-	PINCTRL_PIN_GROUP("gpio11", an7583_gpio11),
-	PINCTRL_PIN_GROUP("gpio12", an7583_gpio12),
-	PINCTRL_PIN_GROUP("gpio13", an7583_gpio13),
-	PINCTRL_PIN_GROUP("gpio14", an7583_gpio14),
-	PINCTRL_PIN_GROUP("gpio15", an7583_gpio15),
-	PINCTRL_PIN_GROUP("gpio16", an7583_gpio16),
-	PINCTRL_PIN_GROUP("gpio17", an7583_gpio17),
-	PINCTRL_PIN_GROUP("gpio18", an7583_gpio18),
-	PINCTRL_PIN_GROUP("gpio19", an7583_gpio19),
-	PINCTRL_PIN_GROUP("gpio20", an7583_gpio20),
-	PINCTRL_PIN_GROUP("gpio21", an7583_gpio21),
-	PINCTRL_PIN_GROUP("gpio22", an7583_gpio22),
-	PINCTRL_PIN_GROUP("gpio23", an7583_gpio23),
-	PINCTRL_PIN_GROUP("gpio24", an7583_gpio24),
-	PINCTRL_PIN_GROUP("gpio25", an7583_gpio25),
-	PINCTRL_PIN_GROUP("gpio26", an7583_gpio26),
-	PINCTRL_PIN_GROUP("gpio27", an7583_gpio27),
-	PINCTRL_PIN_GROUP("gpio28", an7583_gpio28),
-	PINCTRL_PIN_GROUP("gpio29", an7583_gpio29),
-	PINCTRL_PIN_GROUP("gpio30", an7583_gpio30),
-	PINCTRL_PIN_GROUP("gpio31", an7583_gpio31),
-	PINCTRL_PIN_GROUP("gpio32", an7583_gpio32),
-	PINCTRL_PIN_GROUP("gpio33", an7583_gpio33),
-	PINCTRL_PIN_GROUP("gpio34", an7583_gpio34),
-	PINCTRL_PIN_GROUP("gpio35", an7583_gpio35),
-	PINCTRL_PIN_GROUP("gpio36", an7583_gpio36),
-	PINCTRL_PIN_GROUP("gpio37", an7583_gpio37),
-	PINCTRL_PIN_GROUP("gpio38", an7583_gpio38),
-	PINCTRL_PIN_GROUP("gpio39", an7583_gpio39),
-	PINCTRL_PIN_GROUP("gpio40", an7583_gpio40),
-	PINCTRL_PIN_GROUP("gpio41", an7583_gpio41),
-	PINCTRL_PIN_GROUP("gpio42", an7583_gpio42),
-	PINCTRL_PIN_GROUP("gpio43", an7583_gpio43),
-	PINCTRL_PIN_GROUP("gpio44", an7583_gpio44),
-	PINCTRL_PIN_GROUP("gpio45", an7583_gpio45),
-	PINCTRL_PIN_GROUP("gpio46", an7583_gpio46),
-	PINCTRL_PIN_GROUP("gpio47", an7583_gpio47),
-	PINCTRL_PIN_GROUP("gpio48", an7583_gpio48),
-	PINCTRL_PIN_GROUP("gpio49", an7583_gpio49),
-	PINCTRL_PIN_GROUP("gpio50", an7583_gpio50),
-	PINCTRL_PIN_GROUP("gpio51", an7583_gpio51),
-	PINCTRL_PIN_GROUP("gpio52", an7583_gpio52),
-	PINCTRL_PIN_GROUP("pcie_reset0", an7583_pcie_reset0),
-	PINCTRL_PIN_GROUP("pcie_reset1", an7583_pcie_reset1),
+static const int gpio0_pins[] = { 2 };
+static const int gpio1_pins[] = { 3 };
+static const int gpio2_pins[] = { 4 };
+static const int gpio3_pins[] = { 5 };
+static const int gpio4_pins[] = { 6 };
+static const int gpio5_pins[] = { 7 };
+static const int gpio6_pins[] = { 8 };
+static const int gpio7_pins[] = { 9 };
+static const int gpio8_pins[] = { 10 };
+static const int gpio9_pins[] = { 11 };
+static const int gpio10_pins[] = { 12 };
+static const int gpio11_pins[] = { 13 };
+static const int gpio12_pins[] = { 14 };
+static const int gpio13_pins[] = { 15 };
+static const int gpio14_pins[] = { 16 };
+static const int gpio15_pins[] = { 17 };
+static const int gpio16_pins[] = { 18 };
+static const int gpio17_pins[] = { 19 };
+static const int gpio18_pins[] = { 20 };
+static const int gpio19_pins[] = { 21 };
+static const int gpio20_pins[] = { 22 };
+static const int gpio21_pins[] = { 23 };
+static const int gpio22_pins[] = { 24 };
+static const int gpio23_pins[] = { 25 };
+static const int gpio24_pins[] = { 26 };
+static const int gpio25_pins[] = { 27 };
+static const int gpio26_pins[] = { 28 };
+static const int gpio27_pins[] = { 29 };
+static const int gpio28_pins[] = { 30 };
+static const int gpio29_pins[] = { 31 };
+static const int gpio30_pins[] = { 32 };
+static const int gpio31_pins[] = { 33 };
+static const int gpio32_pins[] = { 34 };
+static const int gpio33_pins[] = { 35 };
+static const int gpio34_pins[] = { 36 };
+static const int gpio35_pins[] = { 37 };
+static const int gpio36_pins[] = { 38 };
+static const int gpio37_pins[] = { 39 };
+static const int gpio38_pins[] = { 40 };
+static const int gpio39_pins[] = { 41 };
+static const int gpio40_pins[] = { 42 };
+static const int gpio41_pins[] = { 43 };
+static const int gpio42_pins[] = { 44 };
+static const int gpio43_pins[] = { 45 };
+static const int gpio44_pins[] = { 46 };
+static const int gpio45_pins[] = { 47 };
+static const int gpio46_pins[] = { 48 };
+static const int gpio47_pins[] = { 49 };
+static const int gpio48_pins[] = { 50 };
+static const int gpio49_pins[] = { 51 };
+static const int gpio50_pins[] = { 52 };
+static const int gpio51_pins[] = { 53 };
+static const int gpio52_pins[] = { 54 };
+static const int pcie_reset0_pins[] = { 51 };
+static const int pcie_reset1_pins[] = { 52 };
+
+static const struct pingroup pinctrl_groups[] = {
+	PINCTRL_PIN_GROUP("pon", pon),
+	PINCTRL_PIN_GROUP("pon_tod_1pps", pon_tod_1pps),
+	PINCTRL_PIN_GROUP("gsw_tod_1pps", gsw_tod_1pps),
+	PINCTRL_PIN_GROUP("sipo", sipo),
+	PINCTRL_PIN_GROUP("sipo_rclk", sipo_rclk),
+	PINCTRL_PIN_GROUP("mdio", mdio),
+	PINCTRL_PIN_GROUP("uart2", uart2),
+	PINCTRL_PIN_GROUP("uart2_cts_rts", uart2_cts_rts),
+	PINCTRL_PIN_GROUP("hsuart", hsuart),
+	PINCTRL_PIN_GROUP("hsuart_cts_rts", hsuart_cts_rts),
+	PINCTRL_PIN_GROUP("npu_uart", npu_uart),
+	PINCTRL_PIN_GROUP("uart4", uart4),
+	PINCTRL_PIN_GROUP("uart5", uart5),
+	PINCTRL_PIN_GROUP("i2c0", i2c0),
+	PINCTRL_PIN_GROUP("i2c1", i2c1),
+	PINCTRL_PIN_GROUP("jtag_udi", jtag_udi),
+	PINCTRL_PIN_GROUP("jtag_dfd", jtag_dfd),
+	PINCTRL_PIN_GROUP("pcm1", pcm1),
+	PINCTRL_PIN_GROUP("pcm2", pcm2),
+	PINCTRL_PIN_GROUP("spi", spi),
+	PINCTRL_PIN_GROUP("spi_quad", spi_quad),
+	PINCTRL_PIN_GROUP("spi_cs1", spi_cs1),
+	PINCTRL_PIN_GROUP("pcm_spi", pcm_spi),
+	PINCTRL_PIN_GROUP("pcm_spi_rst", pcm_spi_rst),
+	PINCTRL_PIN_GROUP("pcm_spi_cs1", pcm_spi_cs1),
+	PINCTRL_PIN_GROUP("emmc", emmc),
+	PINCTRL_PIN_GROUP("pnand", pnand),
+	PINCTRL_PIN_GROUP("gpio0", gpio0),
+	PINCTRL_PIN_GROUP("gpio1", gpio1),
+	PINCTRL_PIN_GROUP("gpio2", gpio2),
+	PINCTRL_PIN_GROUP("gpio3", gpio3),
+	PINCTRL_PIN_GROUP("gpio4", gpio4),
+	PINCTRL_PIN_GROUP("gpio5", gpio5),
+	PINCTRL_PIN_GROUP("gpio6", gpio6),
+	PINCTRL_PIN_GROUP("gpio7", gpio7),
+	PINCTRL_PIN_GROUP("gpio8", gpio8),
+	PINCTRL_PIN_GROUP("gpio9", gpio9),
+	PINCTRL_PIN_GROUP("gpio10", gpio10),
+	PINCTRL_PIN_GROUP("gpio11", gpio11),
+	PINCTRL_PIN_GROUP("gpio12", gpio12),
+	PINCTRL_PIN_GROUP("gpio13", gpio13),
+	PINCTRL_PIN_GROUP("gpio14", gpio14),
+	PINCTRL_PIN_GROUP("gpio15", gpio15),
+	PINCTRL_PIN_GROUP("gpio16", gpio16),
+	PINCTRL_PIN_GROUP("gpio17", gpio17),
+	PINCTRL_PIN_GROUP("gpio18", gpio18),
+	PINCTRL_PIN_GROUP("gpio19", gpio19),
+	PINCTRL_PIN_GROUP("gpio20", gpio20),
+	PINCTRL_PIN_GROUP("gpio21", gpio21),
+	PINCTRL_PIN_GROUP("gpio22", gpio22),
+	PINCTRL_PIN_GROUP("gpio23", gpio23),
+	PINCTRL_PIN_GROUP("gpio24", gpio24),
+	PINCTRL_PIN_GROUP("gpio25", gpio25),
+	PINCTRL_PIN_GROUP("gpio26", gpio26),
+	PINCTRL_PIN_GROUP("gpio27", gpio27),
+	PINCTRL_PIN_GROUP("gpio28", gpio28),
+	PINCTRL_PIN_GROUP("gpio29", gpio29),
+	PINCTRL_PIN_GROUP("gpio30", gpio30),
+	PINCTRL_PIN_GROUP("gpio31", gpio31),
+	PINCTRL_PIN_GROUP("gpio32", gpio32),
+	PINCTRL_PIN_GROUP("gpio33", gpio33),
+	PINCTRL_PIN_GROUP("gpio34", gpio34),
+	PINCTRL_PIN_GROUP("gpio35", gpio35),
+	PINCTRL_PIN_GROUP("gpio36", gpio36),
+	PINCTRL_PIN_GROUP("gpio37", gpio37),
+	PINCTRL_PIN_GROUP("gpio38", gpio38),
+	PINCTRL_PIN_GROUP("gpio39", gpio39),
+	PINCTRL_PIN_GROUP("gpio40", gpio40),
+	PINCTRL_PIN_GROUP("gpio41", gpio41),
+	PINCTRL_PIN_GROUP("gpio42", gpio42),
+	PINCTRL_PIN_GROUP("gpio43", gpio43),
+	PINCTRL_PIN_GROUP("gpio44", gpio44),
+	PINCTRL_PIN_GROUP("gpio45", gpio45),
+	PINCTRL_PIN_GROUP("gpio46", gpio46),
+	PINCTRL_PIN_GROUP("gpio47", gpio47),
+	PINCTRL_PIN_GROUP("gpio48", gpio48),
+	PINCTRL_PIN_GROUP("gpio49", gpio49),
+	PINCTRL_PIN_GROUP("gpio50", gpio50),
+	PINCTRL_PIN_GROUP("gpio51", gpio51),
+	PINCTRL_PIN_GROUP("gpio52", gpio52),
+	PINCTRL_PIN_GROUP("pcie_reset0", pcie_reset0),
+	PINCTRL_PIN_GROUP("pcie_reset1", pcie_reset1),
 };
 
 static const char *const pon_groups[] = { "pon" };
@@ -566,7 +566,7 @@ static const char *const tod_1pps_groups[] = {
 	"pon_tod_1pps", "gsw_tod_1pps"
 };
 static const char *const sipo_groups[] = { "sipo", "sipo_rclk" };
-static const char *const an7583_mdio_groups[] = { "mdio" };
+static const char *const mdio_groups[] = { "mdio" };
 static const char *const uart_groups[] = {
 	"uart2", "uart2_cts_rts", "hsuart", "hsuart_cts_rts",
 	"uart4", "uart5"
@@ -574,20 +574,20 @@ static const char *const uart_groups[] = {
 static const char *const jtag_groups[] = { "jtag_udi", "jtag_dfd" };
 static const char *const pcm_groups[] = { "pcm1", "pcm2" };
 static const char *const spi_groups[] = { "spi_quad", "spi_cs1" };
-static const char *const an7583_pcm_spi_groups[] = {
+static const char *const pcm_spi_groups[] = {
 	"pcm_spi", "pcm_spi_rst", "pcm_spi_cs1"
 };
 static const char *const emmc_groups[] = { "emmc" };
 static const char *const pnand_groups[] = { "pnand" };
-static const char *const an7583_gpio_groups[] = {
+static const char *const gpio_groups[] = {
 	"gpio39", "gpio40", "gpio41", "gpio42", "gpio43",
 	"gpio44", "gpio45", "gpio46", "gpio47", "gpio48",
 	"gpio49", "gpio50", "gpio51", "gpio52"
 };
-static const char *const an7583_pcie_reset_groups[] = {
+static const char *const pcie_reset_groups[] = {
 	"pcie_reset0", "pcie_reset1"
 };
-static const char *const an7583_pwm_groups[] = {
+static const char *const pwm_groups[] = {
 	"gpio0",  "gpio1",  "gpio2",  "gpio3",  "gpio4",  "gpio5",
 	"gpio6",  "gpio7",  "gpio8",  "gpio9",  "gpio10", "gpio11",
 	"gpio12", "gpio13", "gpio14", "gpio15", "gpio16", "gpio17",
@@ -597,28 +597,28 @@ static const char *const an7583_pwm_groups[] = {
 	"gpio40", "gpio41", "gpio42", "gpio43", "gpio44", "gpio45",
 	"gpio46", "gpio47", "gpio48", "gpio49", "gpio50", "gpio51"
 };
-static const char *const an7583_phy1_led0_groups[] = {
+static const char *const phy1_led0_groups[] = {
 	"gpio1", "gpio2", "gpio3", "gpio4"
 };
-static const char *const an7583_phy2_led0_groups[] = {
+static const char *const phy2_led0_groups[] = {
 	"gpio1", "gpio2", "gpio3", "gpio4"
 };
-static const char *const an7583_phy3_led0_groups[] = {
+static const char *const phy3_led0_groups[] = {
 	"gpio1", "gpio2", "gpio3", "gpio4"
 };
-static const char *const an7583_phy4_led0_groups[] = {
+static const char *const phy4_led0_groups[] = {
 	"gpio1", "gpio2", "gpio3", "gpio4"
 };
-static const char *const an7583_phy1_led1_groups[] = {
+static const char *const phy1_led1_groups[] = {
 	"gpio8", "gpio9", "gpio10", "gpio11"
 };
-static const char *const an7583_phy2_led1_groups[] = {
+static const char *const phy2_led1_groups[] = {
 	"gpio8", "gpio9", "gpio10", "gpio11"
 };
-static const char *const an7583_phy3_led1_groups[] = {
+static const char *const phy3_led1_groups[] = {
 	"gpio8", "gpio9", "gpio10", "gpio11"
 };
-static const char *const an7583_phy4_led1_groups[] = {
+static const char *const phy4_led1_groups[] = {
 	"gpio8", "gpio9", "gpio10", "gpio11"
 };
 
@@ -679,7 +679,7 @@ static const struct airoha_pinctrl_func_group sipo_func_group[] = {
 	},
 };
 
-static const struct airoha_pinctrl_func_group an7583_mdio_func_group[] = {
+static const struct airoha_pinctrl_func_group mdio_func_group[] = {
 	{
 		.name = "mdio",
 		.regmap[0] = {
@@ -850,7 +850,7 @@ static const struct airoha_pinctrl_func_group spi_func_group[] = {
 	},
 };
 
-static const struct airoha_pinctrl_func_group an7583_pcm_spi_func_group[] = {
+static const struct airoha_pinctrl_func_group pcm_spi_func_group[] = {
 	{
 		.name = "pcm_spi",
 		.regmap[0] = {
@@ -892,8 +892,8 @@ static const struct airoha_pinctrl_func_group an7583_pcm_spi_func_group[] = {
 		.regmap[0] = {
 			AIROHA_FUNC_MUX,
 			REG_GPIO_SPI_CS1_MODE,
-			AN7583_GPIO_PCM_SPI_CS2_MODE_MASK,
-			AN7583_GPIO_PCM_SPI_CS2_MODE_MASK
+			GPIO_PCM_SPI_CS2_MODE_MASK,
+			GPIO_PCM_SPI_CS2_MODE_MASK
 		},
 		.regmap_size = 1,
 	}, {
@@ -943,37 +943,37 @@ static const struct airoha_pinctrl_func_group pnand_func_group[] = {
 	},
 };
 
-static const struct airoha_pinctrl_func_group an7583_gpio_func_group[] = {
+static const struct airoha_pinctrl_func_group gpio_func_group[] = {
 	AIROHA_PINCTRL_GPIO_EXT("gpio39", GPIO39_FLASH_MODE_CFG,
-				AN7583_I2C0_SCL_GPIO_MODE_MASK),
+				I2C0_SCL_GPIO_MODE_MASK),
 	AIROHA_PINCTRL_GPIO_EXT("gpio40", GPIO40_FLASH_MODE_CFG,
-				AN7583_I2C0_SDA_GPIO_MODE_MASK),
+				I2C0_SDA_GPIO_MODE_MASK),
 	AIROHA_PINCTRL_GPIO_EXT("gpio41", GPIO41_FLASH_MODE_CFG,
-				AN7583_I2C1_SCL_GPIO_MODE_MASK),
+				I2C1_SCL_GPIO_MODE_MASK),
 	AIROHA_PINCTRL_GPIO_EXT("gpio42", GPIO42_FLASH_MODE_CFG,
-				AN7583_I2C1_SDA_GPIO_MODE_MASK),
+				I2C1_SDA_GPIO_MODE_MASK),
 	AIROHA_PINCTRL_GPIO_EXT("gpio43", GPIO43_FLASH_MODE_CFG,
-				AN7583_SPI_CLK_GPIO_MODE_MASK),
+				SPI_CLK_GPIO_MODE_MASK),
 	AIROHA_PINCTRL_GPIO_EXT("gpio44", GPIO44_FLASH_MODE_CFG,
-				AN7583_SPI_CS_GPIO_MODE_MASK),
+				SPI_CS_GPIO_MODE_MASK),
 	AIROHA_PINCTRL_GPIO_EXT("gpio45", GPIO45_FLASH_MODE_CFG,
-				AN7583_SPI_MOSI_GPIO_MODE_MASK),
+				SPI_MOSI_GPIO_MODE_MASK),
 	AIROHA_PINCTRL_GPIO_EXT("gpio46", GPIO46_FLASH_MODE_CFG,
-				AN7583_SPI_MISO_GPIO_MODE_MASK),
+				SPI_MISO_GPIO_MODE_MASK),
 	AIROHA_PINCTRL_GPIO_EXT("gpio47", GPIO47_FLASH_MODE_CFG,
-				AN7583_UART_TXD_GPIO_MODE_MASK),
+				UART_TXD_GPIO_MODE_MASK),
 	AIROHA_PINCTRL_GPIO_EXT("gpio48", GPIO48_FLASH_MODE_CFG,
-				AN7583_UART_RXD_GPIO_MODE_MASK),
+				UART_RXD_GPIO_MODE_MASK),
 	AIROHA_PINCTRL_GPIO_EXT("gpio49", GPIO49_FLASH_MODE_CFG,
 				GPIO_PCIE_RESET0_MASK),
 	AIROHA_PINCTRL_GPIO_EXT("gpio50", GPIO50_FLASH_MODE_CFG,
 				GPIO_PCIE_RESET1_MASK),
 	AIROHA_PINCTRL_GPIO_EXT("gpio51", GPIO51_FLASH_MODE_CFG,
-				AN7583_MDC_0_GPIO_MODE_MASK),
-	AIROHA_PINCTRL_GPIO("gpio52", AN7583_MDIO_0_GPIO_MODE_MASK),
+				MDC_0_GPIO_MODE_MASK),
+	AIROHA_PINCTRL_GPIO("gpio52", MDIO_0_GPIO_MODE_MASK),
 };
 
-static const struct airoha_pinctrl_func_group an7583_pcie_reset_func_group[] = {
+static const struct airoha_pinctrl_func_group pcie_reset_func_group[] = {
 	{
 		.name = "pcie_reset0",
 		.regmap[0] = {
@@ -995,7 +995,7 @@ static const struct airoha_pinctrl_func_group an7583_pcie_reset_func_group[] = {
 	},
 };
 
-static const struct airoha_pinctrl_func_group an7583_pwm_func_group[] = {
+static const struct airoha_pinctrl_func_group pwm_func_group[] = {
 	AIROHA_PINCTRL_PWM("gpio0", GPIO0_FLASH_MODE_CFG),
 	AIROHA_PINCTRL_PWM("gpio1", GPIO1_FLASH_MODE_CFG),
 	AIROHA_PINCTRL_PWM("gpio2", GPIO2_FLASH_MODE_CFG),
@@ -1032,34 +1032,34 @@ static const struct airoha_pinctrl_func_group an7583_pwm_func_group[] = {
 	AIROHA_PINCTRL_PWM_EXT("gpio37", GPIO37_FLASH_MODE_CFG),
 	AIROHA_PINCTRL_PWM_EXT("gpio38", GPIO38_FLASH_MODE_CFG),
 	AIROHA_PINCTRL_PWM_EXT_SEC("gpio39", GPIO39_FLASH_MODE_CFG,
-				   AN7583_I2C0_SCL_GPIO_MODE_MASK),
+				   I2C0_SCL_GPIO_MODE_MASK),
 	AIROHA_PINCTRL_PWM_EXT_SEC("gpio40", GPIO40_FLASH_MODE_CFG,
-				   AN7583_I2C0_SDA_GPIO_MODE_MASK),
+				   I2C0_SDA_GPIO_MODE_MASK),
 	AIROHA_PINCTRL_PWM_EXT_SEC("gpio41", GPIO41_FLASH_MODE_CFG,
-				   AN7583_I2C1_SCL_GPIO_MODE_MASK),
+				   I2C1_SCL_GPIO_MODE_MASK),
 	AIROHA_PINCTRL_PWM_EXT_SEC("gpio42", GPIO42_FLASH_MODE_CFG,
-				   AN7583_I2C1_SDA_GPIO_MODE_MASK),
+				   I2C1_SDA_GPIO_MODE_MASK),
 	AIROHA_PINCTRL_PWM_EXT_SEC("gpio43", GPIO43_FLASH_MODE_CFG,
-				   AN7583_SPI_CLK_GPIO_MODE_MASK),
+				   SPI_CLK_GPIO_MODE_MASK),
 	AIROHA_PINCTRL_PWM_EXT_SEC("gpio44", GPIO44_FLASH_MODE_CFG,
-				   AN7583_SPI_CS_GPIO_MODE_MASK),
+				   SPI_CS_GPIO_MODE_MASK),
 	AIROHA_PINCTRL_PWM_EXT_SEC("gpio45", GPIO45_FLASH_MODE_CFG,
-				   AN7583_SPI_MOSI_GPIO_MODE_MASK),
+				   SPI_MOSI_GPIO_MODE_MASK),
 	AIROHA_PINCTRL_PWM_EXT_SEC("gpio46", GPIO46_FLASH_MODE_CFG,
-				   AN7583_SPI_MISO_GPIO_MODE_MASK),
+				   SPI_MISO_GPIO_MODE_MASK),
 	AIROHA_PINCTRL_PWM_EXT_SEC("gpio47", GPIO47_FLASH_MODE_CFG,
-				   AN7583_UART_TXD_GPIO_MODE_MASK),
+				   UART_TXD_GPIO_MODE_MASK),
 	AIROHA_PINCTRL_PWM_EXT_SEC("gpio48", GPIO48_FLASH_MODE_CFG,
-				   AN7583_UART_RXD_GPIO_MODE_MASK),
+				   UART_RXD_GPIO_MODE_MASK),
 	AIROHA_PINCTRL_PWM_EXT_SEC("gpio49", GPIO49_FLASH_MODE_CFG,
 				   GPIO_PCIE_RESET0_MASK),
 	AIROHA_PINCTRL_PWM_EXT_SEC("gpio50", GPIO50_FLASH_MODE_CFG,
 				   GPIO_PCIE_RESET1_MASK),
 	AIROHA_PINCTRL_PWM_EXT_SEC("gpio51", GPIO51_FLASH_MODE_CFG,
-				   AN7583_MDC_0_GPIO_MODE_MASK),
+				   MDC_0_GPIO_MODE_MASK),
 };
 
-static const struct airoha_pinctrl_func_group an7583_phy1_led0_func_group[] = {
+static const struct airoha_pinctrl_func_group phy1_led0_func_group[] = {
 	AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK,
 				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),
 	AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK,
@@ -1070,7 +1070,7 @@ static const struct airoha_pinctrl_func_group an7583_phy1_led0_func_group[] = {
 				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),
 };
 
-static const struct airoha_pinctrl_func_group an7583_phy2_led0_func_group[] = {
+static const struct airoha_pinctrl_func_group phy2_led0_func_group[] = {
 	AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK,
 				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),
 	AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK,
@@ -1081,7 +1081,7 @@ static const struct airoha_pinctrl_func_group an7583_phy2_led0_func_group[] = {
 				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),
 };
 
-static const struct airoha_pinctrl_func_group an7583_phy3_led0_func_group[] = {
+static const struct airoha_pinctrl_func_group phy3_led0_func_group[] = {
 	AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK,
 				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
 	AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK,
@@ -1092,7 +1092,7 @@ static const struct airoha_pinctrl_func_group an7583_phy3_led0_func_group[] = {
 				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
 };
 
-static const struct airoha_pinctrl_func_group an7583_phy4_led0_func_group[] = {
+static const struct airoha_pinctrl_func_group phy4_led0_func_group[] = {
 	AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK,
 				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)),
 	AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK,
@@ -1103,7 +1103,7 @@ static const struct airoha_pinctrl_func_group an7583_phy4_led0_func_group[] = {
 				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)),
 };
 
-static const struct airoha_pinctrl_func_group an7583_phy1_led1_func_group[] = {
+static const struct airoha_pinctrl_func_group phy1_led1_func_group[] = {
 	AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK,
 				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),
 	AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK,
@@ -1114,7 +1114,7 @@ static const struct airoha_pinctrl_func_group an7583_phy1_led1_func_group[] = {
 				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),
 };
 
-static const struct airoha_pinctrl_func_group an7583_phy2_led1_func_group[] = {
+static const struct airoha_pinctrl_func_group phy2_led1_func_group[] = {
 	AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK,
 				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),
 	AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK,
@@ -1125,7 +1125,7 @@ static const struct airoha_pinctrl_func_group an7583_phy2_led1_func_group[] = {
 				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),
 };
 
-static const struct airoha_pinctrl_func_group an7583_phy3_led1_func_group[] = {
+static const struct airoha_pinctrl_func_group phy3_led1_func_group[] = {
 	AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK,
 				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
 	AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK,
@@ -1136,7 +1136,7 @@ static const struct airoha_pinctrl_func_group an7583_phy3_led1_func_group[] = {
 				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
 };
 
-static const struct airoha_pinctrl_func_group an7583_phy4_led1_func_group[] = {
+static const struct airoha_pinctrl_func_group phy4_led1_func_group[] = {
 	AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK,
 				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)),
 	AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK,
@@ -1147,32 +1147,32 @@ static const struct airoha_pinctrl_func_group an7583_phy4_led1_func_group[] = {
 				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)),
 };
 
-static const struct airoha_pinctrl_func an7583_pinctrl_funcs[] = {
+static const struct airoha_pinctrl_func pinctrl_funcs[] = {
 	PINCTRL_FUNC_DESC("pon", pon),
 	PINCTRL_FUNC_DESC("tod_1pps", tod_1pps),
 	PINCTRL_FUNC_DESC("sipo", sipo),
-	PINCTRL_FUNC_DESC("mdio", an7583_mdio),
+	PINCTRL_FUNC_DESC("mdio", mdio),
 	PINCTRL_FUNC_DESC("uart", uart),
 	PINCTRL_FUNC_DESC("jtag", jtag),
 	PINCTRL_FUNC_DESC("pcm", pcm),
 	PINCTRL_FUNC_DESC("spi", spi),
-	PINCTRL_FUNC_DESC("pcm_spi", an7583_pcm_spi),
+	PINCTRL_FUNC_DESC("pcm_spi", pcm_spi),
 	PINCTRL_FUNC_DESC("emmc", emmc),
 	PINCTRL_FUNC_DESC("pnand", pnand),
-	PINCTRL_FUNC_DESC("gpio", an7583_gpio),
-	PINCTRL_FUNC_DESC("pcie_reset", an7583_pcie_reset),
-	PINCTRL_FUNC_DESC("pwm", an7583_pwm),
-	PINCTRL_FUNC_DESC("phy1_led0", an7583_phy1_led0),
-	PINCTRL_FUNC_DESC("phy2_led0", an7583_phy2_led0),
-	PINCTRL_FUNC_DESC("phy3_led0", an7583_phy3_led0),
-	PINCTRL_FUNC_DESC("phy4_led0", an7583_phy4_led0),
-	PINCTRL_FUNC_DESC("phy1_led1", an7583_phy1_led1),
-	PINCTRL_FUNC_DESC("phy2_led1", an7583_phy2_led1),
-	PINCTRL_FUNC_DESC("phy3_led1", an7583_phy3_led1),
-	PINCTRL_FUNC_DESC("phy4_led1", an7583_phy4_led1),
+	PINCTRL_FUNC_DESC("gpio", gpio),
+	PINCTRL_FUNC_DESC("pcie_reset", pcie_reset),
+	PINCTRL_FUNC_DESC("pwm", pwm),
+	PINCTRL_FUNC_DESC("phy1_led0", phy1_led0),
+	PINCTRL_FUNC_DESC("phy2_led0", phy2_led0),
+	PINCTRL_FUNC_DESC("phy3_led0", phy3_led0),
+	PINCTRL_FUNC_DESC("phy4_led0", phy4_led0),
+	PINCTRL_FUNC_DESC("phy1_led1", phy1_led1),
+	PINCTRL_FUNC_DESC("phy2_led1", phy2_led1),
+	PINCTRL_FUNC_DESC("phy3_led1", phy3_led1),
+	PINCTRL_FUNC_DESC("phy4_led1", phy4_led1),
 };
 
-static const struct airoha_pinctrl_conf an7583_pinctrl_pullup_conf[] = {
+static const struct airoha_pinctrl_conf pinctrl_pullup_conf[] = {
 	PINCTRL_CONF_DESC(2, REG_GPIO_L_PU, BIT(0)),
 	PINCTRL_CONF_DESC(3, REG_GPIO_L_PU, BIT(1)),
 	PINCTRL_CONF_DESC(4, REG_GPIO_L_PU, BIT(2)),
@@ -1214,8 +1214,8 @@ static const struct airoha_pinctrl_conf an7583_pinctrl_pullup_conf[] = {
 	PINCTRL_CONF_DESC(40, REG_GPIO_H_PU, BIT(6)),
 	PINCTRL_CONF_DESC(41, REG_I2C_SDA_PU, I2C_SCL_PU_MASK),
 	PINCTRL_CONF_DESC(42, REG_I2C_SDA_PU, I2C_SDA_PU_MASK),
-	PINCTRL_CONF_DESC(43, REG_I2C_SDA_PU, AN7583_I2C1_SCL_PU_MASK),
-	PINCTRL_CONF_DESC(44, REG_I2C_SDA_PU, AN7583_I2C1_SDA_PU_MASK),
+	PINCTRL_CONF_DESC(43, REG_I2C_SDA_PU, I2C1_SCL_PU_MASK),
+	PINCTRL_CONF_DESC(44, REG_I2C_SDA_PU, I2C1_SDA_PU_MASK),
 	PINCTRL_CONF_DESC(45, REG_I2C_SDA_PU, SPI_CLK_PU_MASK),
 	PINCTRL_CONF_DESC(46, REG_I2C_SDA_PU, SPI_CS0_PU_MASK),
 	PINCTRL_CONF_DESC(47, REG_I2C_SDA_PU, SPI_MOSI_PU_MASK),
@@ -1224,11 +1224,11 @@ static const struct airoha_pinctrl_conf an7583_pinctrl_pullup_conf[] = {
 	PINCTRL_CONF_DESC(50, REG_I2C_SDA_PU, UART1_RXD_PU_MASK),
 	PINCTRL_CONF_DESC(51, REG_I2C_SDA_PU, PCIE0_RESET_PU_MASK),
 	PINCTRL_CONF_DESC(52, REG_I2C_SDA_PU, PCIE1_RESET_PU_MASK),
-	PINCTRL_CONF_DESC(53, REG_I2C_SDA_PU, AN7583_MDC_0_PU_MASK),
-	PINCTRL_CONF_DESC(54, REG_I2C_SDA_PU, AN7583_MDIO_0_PU_MASK),
+	PINCTRL_CONF_DESC(53, REG_I2C_SDA_PU, MDC_0_PU_MASK),
+	PINCTRL_CONF_DESC(54, REG_I2C_SDA_PU, MDIO_0_PU_MASK),
 };
 
-static const struct airoha_pinctrl_conf an7583_pinctrl_pulldown_conf[] = {
+static const struct airoha_pinctrl_conf pinctrl_pulldown_conf[] = {
 	PINCTRL_CONF_DESC(2, REG_GPIO_L_PD, BIT(0)),
 	PINCTRL_CONF_DESC(3, REG_GPIO_L_PD, BIT(1)),
 	PINCTRL_CONF_DESC(4, REG_GPIO_L_PD, BIT(2)),
@@ -1270,8 +1270,8 @@ static const struct airoha_pinctrl_conf an7583_pinctrl_pulldown_conf[] = {
 	PINCTRL_CONF_DESC(40, REG_GPIO_H_PD, BIT(6)),
 	PINCTRL_CONF_DESC(41, REG_I2C_SDA_PD, I2C_SCL_PD_MASK),
 	PINCTRL_CONF_DESC(42, REG_I2C_SDA_PD, I2C_SDA_PD_MASK),
-	PINCTRL_CONF_DESC(43, REG_I2C_SDA_PD, AN7583_I2C1_SCL_PD_MASK),
-	PINCTRL_CONF_DESC(44, REG_I2C_SDA_PD, AN7583_I2C1_SDA_PD_MASK),
+	PINCTRL_CONF_DESC(43, REG_I2C_SDA_PD, I2C1_SCL_PD_MASK),
+	PINCTRL_CONF_DESC(44, REG_I2C_SDA_PD, I2C1_SDA_PD_MASK),
 	PINCTRL_CONF_DESC(45, REG_I2C_SDA_PD, SPI_CLK_PD_MASK),
 	PINCTRL_CONF_DESC(46, REG_I2C_SDA_PD, SPI_CS0_PD_MASK),
 	PINCTRL_CONF_DESC(47, REG_I2C_SDA_PD, SPI_MOSI_PD_MASK),
@@ -1280,11 +1280,11 @@ static const struct airoha_pinctrl_conf an7583_pinctrl_pulldown_conf[] = {
 	PINCTRL_CONF_DESC(50, REG_I2C_SDA_PD, UART1_RXD_PD_MASK),
 	PINCTRL_CONF_DESC(51, REG_I2C_SDA_PD, PCIE0_RESET_PD_MASK),
 	PINCTRL_CONF_DESC(52, REG_I2C_SDA_PD, PCIE1_RESET_PD_MASK),
-	PINCTRL_CONF_DESC(53, REG_I2C_SDA_PD, AN7583_MDC_0_PD_MASK),
-	PINCTRL_CONF_DESC(54, REG_I2C_SDA_PD, AN7583_MDIO_0_PD_MASK),
+	PINCTRL_CONF_DESC(53, REG_I2C_SDA_PD, MDC_0_PD_MASK),
+	PINCTRL_CONF_DESC(54, REG_I2C_SDA_PD, MDIO_0_PD_MASK),
 };
 
-static const struct airoha_pinctrl_conf an7583_pinctrl_drive_e2_conf[] = {
+static const struct airoha_pinctrl_conf pinctrl_drive_e2_conf[] = {
 	PINCTRL_CONF_DESC(2, REG_GPIO_L_E2, BIT(0)),
 	PINCTRL_CONF_DESC(3, REG_GPIO_L_E2, BIT(1)),
 	PINCTRL_CONF_DESC(4, REG_GPIO_L_E2, BIT(2)),
@@ -1326,8 +1326,8 @@ static const struct airoha_pinctrl_conf an7583_pinctrl_drive_e2_conf[] = {
 	PINCTRL_CONF_DESC(40, REG_GPIO_H_E2, BIT(6)),
 	PINCTRL_CONF_DESC(41, REG_I2C_SDA_E2, I2C_SCL_E2_MASK),
 	PINCTRL_CONF_DESC(42, REG_I2C_SDA_E2, I2C_SDA_E2_MASK),
-	PINCTRL_CONF_DESC(43, REG_I2C_SDA_E2, AN7583_I2C1_SCL_E2_MASK),
-	PINCTRL_CONF_DESC(44, REG_I2C_SDA_E2, AN7583_I2C1_SDA_E2_MASK),
+	PINCTRL_CONF_DESC(43, REG_I2C_SDA_E2, I2C1_SCL_E2_MASK),
+	PINCTRL_CONF_DESC(44, REG_I2C_SDA_E2, I2C1_SDA_E2_MASK),
 	PINCTRL_CONF_DESC(45, REG_I2C_SDA_E2, SPI_CLK_E2_MASK),
 	PINCTRL_CONF_DESC(46, REG_I2C_SDA_E2, SPI_CS0_E2_MASK),
 	PINCTRL_CONF_DESC(47, REG_I2C_SDA_E2, SPI_MOSI_E2_MASK),
@@ -1336,11 +1336,11 @@ static const struct airoha_pinctrl_conf an7583_pinctrl_drive_e2_conf[] = {
 	PINCTRL_CONF_DESC(50, REG_I2C_SDA_E2, UART1_RXD_E2_MASK),
 	PINCTRL_CONF_DESC(51, REG_I2C_SDA_E2, PCIE0_RESET_E2_MASK),
 	PINCTRL_CONF_DESC(52, REG_I2C_SDA_E2, PCIE1_RESET_E2_MASK),
-	PINCTRL_CONF_DESC(53, REG_I2C_SDA_E2, AN7583_MDC_0_E2_MASK),
-	PINCTRL_CONF_DESC(54, REG_I2C_SDA_E2, AN7583_MDIO_0_E2_MASK),
+	PINCTRL_CONF_DESC(53, REG_I2C_SDA_E2, MDC_0_E2_MASK),
+	PINCTRL_CONF_DESC(54, REG_I2C_SDA_E2, MDIO_0_E2_MASK),
 };
 
-static const struct airoha_pinctrl_conf an7583_pinctrl_drive_e4_conf[] = {
+static const struct airoha_pinctrl_conf pinctrl_drive_e4_conf[] = {
 	PINCTRL_CONF_DESC(2, REG_GPIO_L_E4, BIT(0)),
 	PINCTRL_CONF_DESC(3, REG_GPIO_L_E4, BIT(1)),
 	PINCTRL_CONF_DESC(4, REG_GPIO_L_E4, BIT(2)),
@@ -1382,8 +1382,8 @@ static const struct airoha_pinctrl_conf an7583_pinctrl_drive_e4_conf[] = {
 	PINCTRL_CONF_DESC(40, REG_GPIO_H_E4, BIT(6)),
 	PINCTRL_CONF_DESC(41, REG_I2C_SDA_E4, I2C_SCL_E4_MASK),
 	PINCTRL_CONF_DESC(42, REG_I2C_SDA_E4, I2C_SDA_E4_MASK),
-	PINCTRL_CONF_DESC(43, REG_I2C_SDA_E4, AN7583_I2C1_SCL_E4_MASK),
-	PINCTRL_CONF_DESC(44, REG_I2C_SDA_E4, AN7583_I2C1_SDA_E4_MASK),
+	PINCTRL_CONF_DESC(43, REG_I2C_SDA_E4, I2C1_SCL_E4_MASK),
+	PINCTRL_CONF_DESC(44, REG_I2C_SDA_E4, I2C1_SDA_E4_MASK),
 	PINCTRL_CONF_DESC(45, REG_I2C_SDA_E4, SPI_CLK_E4_MASK),
 	PINCTRL_CONF_DESC(46, REG_I2C_SDA_E4, SPI_CS0_E4_MASK),
 	PINCTRL_CONF_DESC(47, REG_I2C_SDA_E4, SPI_MOSI_E4_MASK),
@@ -1392,50 +1392,50 @@ static const struct airoha_pinctrl_conf an7583_pinctrl_drive_e4_conf[] = {
 	PINCTRL_CONF_DESC(50, REG_I2C_SDA_E4, UART1_RXD_E4_MASK),
 	PINCTRL_CONF_DESC(51, REG_I2C_SDA_E4, PCIE0_RESET_E4_MASK),
 	PINCTRL_CONF_DESC(52, REG_I2C_SDA_E4, PCIE1_RESET_E4_MASK),
-	PINCTRL_CONF_DESC(53, REG_I2C_SDA_E4, AN7583_MDC_0_E4_MASK),
-	PINCTRL_CONF_DESC(54, REG_I2C_SDA_E4, AN7583_MDIO_0_E4_MASK),
+	PINCTRL_CONF_DESC(53, REG_I2C_SDA_E4, MDC_0_E4_MASK),
+	PINCTRL_CONF_DESC(54, REG_I2C_SDA_E4, MDIO_0_E4_MASK),
 };
 
-static const struct airoha_pinctrl_conf an7583_pinctrl_pcie_rst_od_conf[] = {
+static const struct airoha_pinctrl_conf pinctrl_pcie_rst_od_conf[] = {
 	PINCTRL_CONF_DESC(51, REG_PCIE_RESET_OD, PCIE0_RESET_OD_MASK),
 	PINCTRL_CONF_DESC(52, REG_PCIE_RESET_OD, PCIE1_RESET_OD_MASK),
 };
 
-static const struct airoha_pinctrl_match_data an7583_pinctrl_match_data = {
+static const struct airoha_pinctrl_match_data pinctrl_match_data = {
 	.pinctrl_name = KBUILD_MODNAME,
 	.pinctrl_owner = THIS_MODULE,
-	.pins = an7583_pinctrl_pins,
-	.num_pins = ARRAY_SIZE(an7583_pinctrl_pins),
-	.grps = an7583_pinctrl_groups,
-	.num_grps = ARRAY_SIZE(an7583_pinctrl_groups),
-	.funcs = an7583_pinctrl_funcs,
-	.num_funcs = ARRAY_SIZE(an7583_pinctrl_funcs),
+	.pins = pinctrl_pins,
+	.num_pins = ARRAY_SIZE(pinctrl_pins),
+	.grps = pinctrl_groups,
+	.num_grps = ARRAY_SIZE(pinctrl_groups),
+	.funcs = pinctrl_funcs,
+	.num_funcs = ARRAY_SIZE(pinctrl_funcs),
 	.confs_info = {
 		[AIROHA_PINCTRL_CONFS_PULLUP] = {
-			.confs = an7583_pinctrl_pullup_conf,
-			.num_confs = ARRAY_SIZE(an7583_pinctrl_pullup_conf),
+			.confs = pinctrl_pullup_conf,
+			.num_confs = ARRAY_SIZE(pinctrl_pullup_conf),
 		},
 		[AIROHA_PINCTRL_CONFS_PULLDOWN] = {
-			.confs = an7583_pinctrl_pulldown_conf,
-			.num_confs = ARRAY_SIZE(an7583_pinctrl_pulldown_conf),
+			.confs = pinctrl_pulldown_conf,
+			.num_confs = ARRAY_SIZE(pinctrl_pulldown_conf),
 		},
 		[AIROHA_PINCTRL_CONFS_DRIVE_E2] = {
-			.confs = an7583_pinctrl_drive_e2_conf,
-			.num_confs = ARRAY_SIZE(an7583_pinctrl_drive_e2_conf),
+			.confs = pinctrl_drive_e2_conf,
+			.num_confs = ARRAY_SIZE(pinctrl_drive_e2_conf),
 		},
 		[AIROHA_PINCTRL_CONFS_DRIVE_E4] = {
-			.confs = an7583_pinctrl_drive_e4_conf,
-			.num_confs = ARRAY_SIZE(an7583_pinctrl_drive_e4_conf),
+			.confs = pinctrl_drive_e4_conf,
+			.num_confs = ARRAY_SIZE(pinctrl_drive_e4_conf),
 		},
 		[AIROHA_PINCTRL_CONFS_PCIE_RST_OD] = {
-			.confs = an7583_pinctrl_pcie_rst_od_conf,
-			.num_confs = ARRAY_SIZE(an7583_pinctrl_pcie_rst_od_conf),
+			.confs = pinctrl_pcie_rst_od_conf,
+			.num_confs = ARRAY_SIZE(pinctrl_pcie_rst_od_conf),
 		},
 	},
 };
 
 static const struct of_device_id airoha_pinctrl_of_match[] = {
-	{ .compatible = "airoha,an7583-pinctrl", .data = &an7583_pinctrl_match_data },
+	{ .compatible = "airoha,an7583-pinctrl", .data = &pinctrl_match_data },
 	{ /* sentinel */ }
 };
 MODULE_DEVICE_TABLE(of, airoha_pinctrl_of_match);
-- 
2.53.0

[PATCH v7 23/34] pinctrl: airoha: an7583: rename registers to match its an7583 names

[Mikhail Kshevetskiy]

In the an7581 case the register at 0x1FA20214 is called
RG_GPIO_2ND_I2C_MODE. The same register in the an7583 case is called
RG_SW_TOD_1PPS_MODE.

Let's rename this register to avoid potential confuse.

Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
---
 drivers/pinctrl/airoha/pinctrl-an7583.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/pinctrl/airoha/pinctrl-an7583.c b/drivers/pinctrl/airoha/pinctrl-an7583.c
index 637b9377ff8fc..b0b1dbbb4d768 100644
--- a/drivers/pinctrl/airoha/pinctrl-an7583.c
+++ b/drivers/pinctrl/airoha/pinctrl-an7583.c
@@ -8,7 +8,7 @@
 #include "airoha-common.h"
 
 /* MUX */
-#define REG_GPIO_2ND_I2C_MODE			0x0214
+#define REG_SW_TOD_1PPS_MODE			0x0214
 #define GPIO_LAN3_LED1_MODE_MASK		BIT(10)
 #define GPIO_LAN3_LED0_MODE_MASK		BIT(9)
 #define GPIO_LAN2_LED1_MODE_MASK		BIT(8)
@@ -302,7 +302,7 @@
 		.name = (gpio),						\
 		.regmap[0] = {						\
 			AIROHA_FUNC_MUX,				\
-			REG_GPIO_2ND_I2C_MODE,				\
+			REG_SW_TOD_1PPS_MODE,				\
 			(mux_val),					\
 			(mux_val),					\
 		},							\
@@ -320,7 +320,7 @@
 		.name = (gpio),						\
 		.regmap[0] = {						\
 			AIROHA_FUNC_MUX,				\
-			REG_GPIO_2ND_I2C_MODE,				\
+			REG_SW_TOD_1PPS_MODE,				\
 			(mux_val),					\
 			(mux_val),					\
 		},							\
@@ -640,7 +640,7 @@ static const struct airoha_pinctrl_func_group tod_1pps_func_group[] = {
 		.name = "pon_tod_1pps",
 		.regmap[0] = {
 			AIROHA_FUNC_MUX,
-			REG_GPIO_2ND_I2C_MODE,
+			REG_SW_TOD_1PPS_MODE,
 			PON_TOD_1PPS_MODE_MASK,
 			PON_TOD_1PPS_MODE_MASK
 		},
@@ -649,7 +649,7 @@ static const struct airoha_pinctrl_func_group tod_1pps_func_group[] = {
 		.name = "gsw_tod_1pps",
 		.regmap[0] = {
 			AIROHA_FUNC_MUX,
-			REG_GPIO_2ND_I2C_MODE,
+			REG_SW_TOD_1PPS_MODE,
 			GSW_TOD_1PPS_MODE_MASK,
 			GSW_TOD_1PPS_MODE_MASK
 		},
-- 
2.53.0

[PATCH v7 24/34] pinctrl: airoha: an7583: add support for npu_uart pinmux

[Mikhail Kshevetskiy]

Add support for uart pin function for npu_uart pin group.

Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
---
 drivers/pinctrl/airoha/pinctrl-an7583.c | 12 +++++++++++-
 1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/drivers/pinctrl/airoha/pinctrl-an7583.c b/drivers/pinctrl/airoha/pinctrl-an7583.c
index b0b1dbbb4d768..9b5c7ea5e5472 100644
--- a/drivers/pinctrl/airoha/pinctrl-an7583.c
+++ b/drivers/pinctrl/airoha/pinctrl-an7583.c
@@ -68,6 +68,7 @@
 #define REG_NPU_UART_EN				0x0224
 #define JTAG_UDI_EN_MASK			BIT(4)
 #define JTAG_DFD_EN_MASK			BIT(3)
+#define NPU_UART_EN_MASK			BIT(2)
 
 #define REG_FORCE_GPIO_EN			0x0228
 #define FORCE_GPIO_EN(n)			BIT(n)
@@ -569,7 +570,7 @@ static const char *const sipo_groups[] = { "sipo", "sipo_rclk" };
 static const char *const mdio_groups[] = { "mdio" };
 static const char *const uart_groups[] = {
 	"uart2", "uart2_cts_rts", "hsuart", "hsuart_cts_rts",
-	"uart4", "uart5"
+	"uart4", "uart5", "npu_uart"
 };
 static const char *const jtag_groups[] = { "jtag_udi", "jtag_dfd" };
 static const char *const pcm_groups[] = { "pcm1", "pcm2" };
@@ -754,6 +755,15 @@ static const struct airoha_pinctrl_func_group uart_func_group[] = {
 			GPIO_UART5_MODE_MASK
 		},
 		.regmap_size = 1,
+	}, {
+		.name = "npu_uart",
+		.regmap[0] = {
+			AIROHA_FUNC_MUX,
+			REG_NPU_UART_EN,
+			NPU_UART_EN_MASK,
+			NPU_UART_EN_MASK
+		},
+		.regmap_size = 1,
 	},
 };
 
-- 
2.53.0

Re: [PATCH v7 24/34] pinctrl: airoha: an7583: add support for npu_uart pinmux

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] The commit adds support for the 'npu_uart' pin group in the pinctrl driver for the 'uart' function but fails to update the corresponding device tree bindings.
--

--- Patch [24]: [PATCH v7 24/34] pinctrl: airoha: an7583: add support for npu_uart pinmux ---
commit e389a2bc465838a0c68580627d10aa31667842fb
Author: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>

pinctrl: airoha: an7583: add support for npu_uart pinmux

This commit adds support for the npu_uart pin function and group to the 
AN7583 pinctrl driver.

> diff --git a/drivers/pinctrl/airoha/pinctrl-an7583.c b/drivers/pinctrl/airoha/pinctrl-an7583.c
> index b0b1dbbb4d768..9b5c7ea5e5472 100644
> --- a/drivers/pinctrl/airoha/pinctrl-an7583.c
> +++ b/drivers/pinctrl/airoha/pinctrl-an7583.c
[ ... ]
> @@ -569,7 +570,7 @@ static const char *const sipo_groups[] = { "sipo", "sipo_rclk" };
>  static const char *const mdio_groups[] = { "mdio" };
>  static const char *const uart_groups[] = {
>  	"uart2", "uart2_cts_rts", "hsuart", "hsuart_cts_rts",
> -	"uart4", "uart5"
> +	"uart4", "uart5", "npu_uart"

[Severity: Low]
Should npu_uart also be added to the device tree bindings in
Documentation/devicetree/bindings/pinctrl/airoha,an7583-pinctrl.yaml?

If a device tree uses this new group, it appears it will fail make dtbs_check
validation because npu_uart is not listed in the allowed groups for the uart
function:

Documentation/devicetree/bindings/pinctrl/airoha,an7583-pinctrl.yaml:
          - if:
              properties:
                function:
                  const: uart
            then:
              properties:
                groups:
                  items:
                    enum: [uart2, uart2_cts_rts, hsuart, hsuart_cts_rts,
                           uart4, uart5]

>  };
>  static const char *const jtag_groups[] = { "jtag_udi", "jtag_dfd" };
>  static const char *const pcm_groups[] = { "pcm1", "pcm2" };

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260727074234.3761170-1-mikhail.kshevetskiy@iopsys.eu?part=24

[PATCH v7 25/34] dt-bindings: pinctrl: airoha: an7583: add npu_uart pin group

[Mikhail Kshevetskiy]

Add npu_uart pin-group support for an7583 pin controller.

Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
---
 .../devicetree/bindings/pinctrl/airoha,an7583-pinctrl.yaml      | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/pinctrl/airoha,an7583-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/airoha,an7583-pinctrl.yaml
index bedcb6374f1a0..0a217429b2cb7 100644
--- a/Documentation/devicetree/bindings/pinctrl/airoha,an7583-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/airoha,an7583-pinctrl.yaml
@@ -115,7 +115,7 @@ patternProperties:
                 groups:
                   items:
                     enum: [uart2, uart2_cts_rts, hsuart, hsuart_cts_rts,
-                           uart4, uart5]
+                           uart4, uart5, npu_uart]
                   maxItems: 2
           - if:
               properties:
-- 
2.53.0

[PATCH v7 26/34] pinctrl: airoha: an7583: add support for pon_alt pinmux

[Mikhail Kshevetskiy]

Add support for pon pin function for pon_alt pin group.

Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
---
 drivers/pinctrl/airoha/pinctrl-an7583.c | 16 ++++++++++++++--
 1 file changed, 14 insertions(+), 2 deletions(-)

diff --git a/drivers/pinctrl/airoha/pinctrl-an7583.c b/drivers/pinctrl/airoha/pinctrl-an7583.c
index 9b5c7ea5e5472..7e94dcb3b61a5 100644
--- a/drivers/pinctrl/airoha/pinctrl-an7583.c
+++ b/drivers/pinctrl/airoha/pinctrl-an7583.c
@@ -38,6 +38,7 @@
 #define GPIO_SPI_CS1_MODE_MASK			BIT(0)
 
 #define REG_GPIO_PON_MODE			0x021c
+#define GPIO_PON_ALT_MODE_MASK			BIT(27)
 #define MDIO_0_GPIO_MODE_MASK			BIT(26)
 #define MDC_0_GPIO_MODE_MASK			BIT(25)
 #define UART_RXD_GPIO_MODE_MASK			BIT(24)
@@ -391,6 +392,7 @@ static struct pinctrl_pin_desc pinctrl_pins[] = {
 };
 
 static const int pon_pins[] = { 15, 16, 17, 18, 19, 20 };
+static const int pon_alt_pins[] = { 36, 37, 38, 39, 40 };
 static const int pon_tod_1pps_pins[] = { 32 };
 static const int gsw_tod_1pps_pins[] = { 32 };
 static const int sipo_pins[] = { 34, 35 };
@@ -479,6 +481,7 @@ static const int pcie_reset1_pins[] = { 52 };
 
 static const struct pingroup pinctrl_groups[] = {
 	PINCTRL_PIN_GROUP("pon", pon),
+	PINCTRL_PIN_GROUP("pon_alt", pon_alt),
 	PINCTRL_PIN_GROUP("pon_tod_1pps", pon_tod_1pps),
 	PINCTRL_PIN_GROUP("gsw_tod_1pps", gsw_tod_1pps),
 	PINCTRL_PIN_GROUP("sipo", sipo),
@@ -562,7 +565,7 @@ static const struct pingroup pinctrl_groups[] = {
 	PINCTRL_PIN_GROUP("pcie_reset1", pcie_reset1),
 };
 
-static const char *const pon_groups[] = { "pon" };
+static const char *const pon_groups[] = { "pon", "pon_alt" };
 static const char *const tod_1pps_groups[] = {
 	"pon_tod_1pps", "gsw_tod_1pps"
 };
@@ -629,10 +632,19 @@ static const struct airoha_pinctrl_func_group pon_func_group[] = {
 		.regmap[0] = {
 			AIROHA_FUNC_MUX,
 			REG_GPIO_PON_MODE,
-			GPIO_PON_MODE_MASK,
+			GPIO_PON_MODE_MASK | GPIO_PON_ALT_MODE_MASK,
 			GPIO_PON_MODE_MASK
 		},
 		.regmap_size = 1,
+	}, {
+		.name = "pon_alt",
+		.regmap[0] = {
+			AIROHA_FUNC_MUX,
+			REG_GPIO_PON_MODE,
+			GPIO_PON_MODE_MASK | GPIO_PON_ALT_MODE_MASK,
+			GPIO_PON_ALT_MODE_MASK
+		},
+		.regmap_size = 1,
 	},
 };
 
-- 
2.53.0

Re: [PATCH v7 26/34] pinctrl: airoha: an7583: add support for pon_alt pinmux

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] The introduction of the `pon_alt` pinmux introduces a new mux bit for pins 36-40 (gpio34-gpio38) but fails to update the GPIO and PWM functions to clear this bit, rendering these pins permanently stuck in `pon_alt` mode if left enabled by a bootloader or dynamically switched by Linux.
--

--- Patch [26]: [PATCH v7 26/34] pinctrl: airoha: an7583: add support for pon_alt pinmux ---
commit b1dabfb03ae8c035084ec1f24b413e2c3334d17a
Author: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
Subject: pinctrl: airoha: an7583: add support for pon_alt pinmux

This commit adds support for the pon pin function using the pon_alt pin group.

> diff --git a/drivers/pinctrl/airoha/pinctrl-an7583.c b/drivers/pinctrl/airoha/pinctrl-an7583.c
> index 9b5c7ea5e5472..7e94dcb3b61a5 100644
> --- a/drivers/pinctrl/airoha/pinctrl-an7583.c
> +++ b/drivers/pinctrl/airoha/pinctrl-an7583.c

[ ... ]

> @@ -629,10 +632,19 @@ static const struct airoha_pinctrl_func_group pon_func_group[] = {
>  		.regmap[0] = {
>  			AIROHA_FUNC_MUX,
>  			REG_GPIO_PON_MODE,
> -			GPIO_PON_MODE_MASK,
> +			GPIO_PON_MODE_MASK | GPIO_PON_ALT_MODE_MASK,
>  			GPIO_PON_MODE_MASK
>  		},
>  		.regmap_size = 1,
> +	}, {
> +		.name = "pon_alt",
> +		.regmap[0] = {
> +			AIROHA_FUNC_MUX,
> +			REG_GPIO_PON_MODE,
> +			GPIO_PON_MODE_MASK | GPIO_PON_ALT_MODE_MASK,
> +			GPIO_PON_ALT_MODE_MASK
> +		},
> +		.regmap_size = 1,
>  	},
>  };

[Severity: High]
Since pon_alt uses pins 36-40 (gpio34-gpio38) and sets GPIO_PON_ALT_MODE_MASK
in REG_GPIO_PON_MODE, do we also need to add these pins to gpio_groups[]?

Currently, gpio34 through gpio38 appear to be missing from gpio_groups[]:

drivers/pinctrl/airoha/pinctrl-an7583.c:gpio_groups[] {
    ...
    static const char *const gpio_groups[] = {
    	"gpio39", "gpio40", "gpio41", "gpio42", "gpio43",
    ...
}

Without being in gpio_groups[], it seems impossible to select the "gpio" 
function in the device tree to clear the pon_alt mux bit.

Additionally, will these pins get stuck in pon_alt mode if requested as PWM?

The PWM mapping for pins 36-38 uses AIROHA_PINCTRL_PWM_EXT:

drivers/pinctrl/airoha/pinctrl-an7583.c:pwm_func_group[] {
    ...
	AIROHA_PINCTRL_PWM_EXT("gpio36", GPIO36_FLASH_MODE_CFG),
	AIROHA_PINCTRL_PWM_EXT("gpio37", GPIO37_FLASH_MODE_CFG),
	AIROHA_PINCTRL_PWM_EXT("gpio38", GPIO38_FLASH_MODE_CFG),
    ...
}

This macro only seems to modify REG_GPIO_FLASH_MODE_CFG_EXT and does not clear
the GPIO_PON_ALT_MODE_MASK bit in REG_GPIO_PON_MODE. If a bootloader leaves
these pins in pon_alt mode, or if they are dynamically switched, won't the PWM
output fail silently because the pins remain multiplexed to pon_alt?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260727074234.3761170-1-mikhail.kshevetskiy@iopsys.eu?part=26

[PATCH v7 27/34] dt-bindings: pinctrl: airoha: an7583: add pon_alt pin group

[Mikhail Kshevetskiy]

Add pon_alt pin-group support for an7583 pin controller.

Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
---
 .../devicetree/bindings/pinctrl/airoha,an7583-pinctrl.yaml      | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/pinctrl/airoha,an7583-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/airoha,an7583-pinctrl.yaml
index 0a217429b2cb7..7deb48db52c3a 100644
--- a/Documentation/devicetree/bindings/pinctrl/airoha,an7583-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/airoha,an7583-pinctrl.yaml
@@ -81,7 +81,7 @@ patternProperties:
             then:
               properties:
                 groups:
-                  enum: [pon]
+                  enum: [pon, pon_alt]
           - if:
               properties:
                 function:
-- 
2.53.0

[PATCH v7 28/34] pinctrl: airoha: an7583: add support for olt pinmux

[Mikhail Kshevetskiy]

Add support for olt pin function for olt pin group.

Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
---
 drivers/pinctrl/airoha/pinctrl-an7583.c | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/drivers/pinctrl/airoha/pinctrl-an7583.c b/drivers/pinctrl/airoha/pinctrl-an7583.c
index 7e94dcb3b61a5..74f93327d41a1 100644
--- a/drivers/pinctrl/airoha/pinctrl-an7583.c
+++ b/drivers/pinctrl/airoha/pinctrl-an7583.c
@@ -53,6 +53,7 @@
 #define I2C0_SCL_GPIO_MODE_MASK			BIT(15)
 #define GPIO_PARALLEL_NAND_MODE_MASK		BIT(14)
 #define GPIO_SGMII_MDIO_MODE_MASK		BIT(13)
+#define GPIO_OLT_MODE_MASK			BIT(12)
 #define SIPO_RCLK_MODE_MASK			BIT(11)
 #define GPIO_PCIE_RESET1_MASK			BIT(10)
 #define GPIO_PCIE_RESET0_MASK			BIT(9)
@@ -393,6 +394,7 @@ static struct pinctrl_pin_desc pinctrl_pins[] = {
 
 static const int pon_pins[] = { 15, 16, 17, 18, 19, 20 };
 static const int pon_alt_pins[] = { 36, 37, 38, 39, 40 };
+static const int olt_pins[] = { 36, 37, 38, 39, 40 };
 static const int pon_tod_1pps_pins[] = { 32 };
 static const int gsw_tod_1pps_pins[] = { 32 };
 static const int sipo_pins[] = { 34, 35 };
@@ -482,6 +484,7 @@ static const int pcie_reset1_pins[] = { 52 };
 static const struct pingroup pinctrl_groups[] = {
 	PINCTRL_PIN_GROUP("pon", pon),
 	PINCTRL_PIN_GROUP("pon_alt", pon_alt),
+	PINCTRL_PIN_GROUP("olt", olt),
 	PINCTRL_PIN_GROUP("pon_tod_1pps", pon_tod_1pps),
 	PINCTRL_PIN_GROUP("gsw_tod_1pps", gsw_tod_1pps),
 	PINCTRL_PIN_GROUP("sipo", sipo),
@@ -566,6 +569,7 @@ static const struct pingroup pinctrl_groups[] = {
 };
 
 static const char *const pon_groups[] = { "pon", "pon_alt" };
+static const char *const olt_groups[] = { "olt" };
 static const char *const tod_1pps_groups[] = {
 	"pon_tod_1pps", "gsw_tod_1pps"
 };
@@ -648,6 +652,19 @@ static const struct airoha_pinctrl_func_group pon_func_group[] = {
 	},
 };
 
+static const struct airoha_pinctrl_func_group olt_func_group[] = {
+	{
+		.name = "olt",
+		.regmap[0] = {
+			AIROHA_FUNC_MUX,
+			REG_GPIO_PON_MODE,
+			GPIO_OLT_MODE_MASK,
+			GPIO_OLT_MODE_MASK
+		},
+		.regmap_size = 1,
+	},
+};
+
 static const struct airoha_pinctrl_func_group tod_1pps_func_group[] = {
 	{
 		.name = "pon_tod_1pps",
@@ -1171,6 +1188,7 @@ static const struct airoha_pinctrl_func_group phy4_led1_func_group[] = {
 
 static const struct airoha_pinctrl_func pinctrl_funcs[] = {
 	PINCTRL_FUNC_DESC("pon", pon),
+	PINCTRL_FUNC_DESC("olt", olt),
 	PINCTRL_FUNC_DESC("tod_1pps", tod_1pps),
 	PINCTRL_FUNC_DESC("sipo", sipo),
 	PINCTRL_FUNC_DESC("mdio", mdio),
-- 
2.53.0

[PATCH v7 29/34] dt-bindings: pinctrl: airoha: an7583: add olt function/group

[Mikhail Kshevetskiy]

Add support for olt pin function for olt pin group.

Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
---
 .../bindings/pinctrl/airoha,an7583-pinctrl.yaml        | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/pinctrl/airoha,an7583-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/airoha,an7583-pinctrl.yaml
index 7deb48db52c3a..f016e0da65a57 100644
--- a/Documentation/devicetree/bindings/pinctrl/airoha,an7583-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/airoha,an7583-pinctrl.yaml
@@ -60,7 +60,7 @@ patternProperties:
           function:
             description:
               A string containing the name of the function to mux to the group.
-            enum: [pon, tod_1pps, sipo, mdio, uart, jtag, pcm, spi,
+            enum: [pon, olt, tod_1pps, sipo, mdio, uart, jtag, pcm, spi,
                    pcm_spi, emmc, pnand, gpio, pcie_reset, pwm, phy1_led0,
                    phy2_led0, phy3_led0, phy4_led0, phy1_led1, phy2_led1,
                    phy3_led1, phy4_led1]
@@ -82,6 +82,14 @@ patternProperties:
               properties:
                 groups:
                   enum: [pon, pon_alt]
+          - if:
+              properties:
+                function:
+                  const: olt
+            then:
+              properties:
+                groups:
+                  enum: [olt]
           - if:
               properties:
                 function:
-- 
2.53.0

[PATCH v7 30/34] pinctrl: airoha: add support of en7523 SoC

[Mikhail Kshevetskiy]

This patch adds support of Airoha en7523 SoC pin controller.

Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
---
 drivers/pinctrl/airoha/Kconfig          |    9 +
 drivers/pinctrl/airoha/Makefile         |    1 +
 drivers/pinctrl/airoha/pinctrl-en7523.c | 1124 +++++++++++++++++++++++
 3 files changed, 1134 insertions(+)
 create mode 100644 drivers/pinctrl/airoha/pinctrl-en7523.c

diff --git a/drivers/pinctrl/airoha/Kconfig b/drivers/pinctrl/airoha/Kconfig
index dae6608bc72dd..363d6b7ff906f 100644
--- a/drivers/pinctrl/airoha/Kconfig
+++ b/drivers/pinctrl/airoha/Kconfig
@@ -15,6 +15,7 @@ config PINCTRL_AIROHA
 	select REGMAP_MMIO
 	imply PINCTRL_AIROHA_AN7581
 	imply PINCTRL_AIROHA_AN7583
+	imply PINCTRL_AIROHA_EN7523
 	help
 	  Shared pin controller and gpio driver code for different
 	  Airoha SoCs.
@@ -35,4 +36,12 @@ config PINCTRL_AIROHA_AN7583
 	  Say yes here to support pin controller and gpio driver
 	  on Airoha AN7583, AN7553, AN7567 and other compatible SoCs.
 
+config PINCTRL_AIROHA_EN7523
+	tristate "EN7523 pinctrl"
+	depends on ARM || COMPILE_TEST
+	depends on PINCTRL_AIROHA
+	help
+	  Say yes here to support pin controller and gpio driver
+	  on Airoha EN7523, EN7529, EN7562 and other compatible SoCs.
+
 endmenu
diff --git a/drivers/pinctrl/airoha/Makefile b/drivers/pinctrl/airoha/Makefile
index cfd68c45ae0f0..8b9202321ba86 100644
--- a/drivers/pinctrl/airoha/Makefile
+++ b/drivers/pinctrl/airoha/Makefile
@@ -6,3 +6,4 @@ obj-$(CONFIG_PINCTRL_AIROHA)		+= pinctrl-airoha.o
 # SoC drivers
 obj-$(CONFIG_PINCTRL_AIROHA_AN7581)	+= pinctrl-an7581.o
 obj-$(CONFIG_PINCTRL_AIROHA_AN7583)	+= pinctrl-an7583.o
+obj-$(CONFIG_PINCTRL_AIROHA_EN7523)	+= pinctrl-en7523.o
diff --git a/drivers/pinctrl/airoha/pinctrl-en7523.c b/drivers/pinctrl/airoha/pinctrl-en7523.c
new file mode 100644
index 0000000000000..7f434c9bce923
--- /dev/null
+++ b/drivers/pinctrl/airoha/pinctrl-en7523.c
@@ -0,0 +1,1124 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Author: Lorenzo Bianconi <lorenzo@kernel.org>
+ * Author: Benjamin Larsson <benjamin.larsson@genexis.eu>
+ * Author: Markus Gothe <markus.gothe@genexis.eu>
+ * Author: Matheus Sampaio Queiroga <srherobrine20@gmail.com>
+ * Author: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
+ */
+#include "airoha-common.h"
+
+/* MUX */
+#define REG_GPIO_2ND_I2C_MODE			0x0210
+#define GPIO_I2S_MODE_MASK			BIT(12)
+#define GPIO_I2C_SLAVE_MODE_MODE		BIT(11)
+#define GPIO_LAN3_LED1_MODE_MASK		BIT(10)
+#define GPIO_LAN3_LED0_MODE_MASK		BIT(9)
+#define GPIO_LAN2_LED1_MODE_MASK		BIT(8)
+#define GPIO_LAN2_LED0_MODE_MASK		BIT(7)
+#define GPIO_LAN1_LED1_MODE_MASK		BIT(6)
+#define GPIO_LAN1_LED0_MODE_MASK		BIT(5)
+#define GPIO_LAN0_LED1_MODE_MASK		BIT(4)
+#define GPIO_LAN0_LED0_MODE_MASK		BIT(3)
+#define PON_TOD_1PPS_MODE_MASK			BIT(2)
+#define GSW_TOD_1PPS_MODE_MASK			BIT(1)
+#define GPIO_2ND_I2C_MODE_MASK			BIT(0)
+
+#define REG_GPIO_SPI_CS1_MODE			0x0214
+#define GPIO_PCM_SPI_CS4_MODE_MASK		BIT(21)
+#define GPIO_PCM_SPI_CS3_MODE_MASK		BIT(20)
+#define GPIO_PCM_SPI_CS2_MODE_P156_MASK		BIT(19)
+#define GPIO_PCM_SPI_CS2_MODE_P128_MASK		BIT(18)
+#define GPIO_PCM_SPI_CS1_MODE_MASK		BIT(17)
+#define GPIO_PCM_SPI_MODE_MASK			BIT(16)
+#define GPIO_PCM2_MODE_MASK			BIT(13)
+#define GPIO_PCM1_MODE_MASK			BIT(12)
+#define GPIO_PCM_INT_MODE_MASK			BIT(9)
+#define GPIO_PCM_RESET_MODE_MASK		BIT(8)
+#define GPIO_SPI_QUAD_MODE_MASK			BIT(4)
+#define GPIO_SPI_CS1_MODE_MASK			BIT(0)
+
+#define REG_GPIO_PON_MODE			0x0218
+#define GPIO_SGMII_MDIO_MODE_MASK		BIT(13)
+#define SIPO_RCLK_MODE_MASK			BIT(11)
+#define GPIO_PCIE_RESET1_MASK			BIT(10)
+#define GPIO_PCIE_RESET0_MASK			BIT(9)
+#define GPIO_UART2_MODE_MASK			BIT(3)
+#define GPIO_SIPO_MODE_MASK			BIT(2)
+#define GPIO_PON_MODE_MASK			BIT(0)
+
+#define REG_NPU_UART_EN				0x0220
+#define JTAG_UDI_EN_MASK			BIT(4)
+#define JTAG_DFD_EN_MASK			BIT(3)
+#define NPU_UART_EN_MASK			BIT(2)
+
+#define REG_FORCE_GPIO_EN			0x0224
+#define FORCE_GPIO_EN(n)			BIT(n)
+
+/* LED MAP */
+#define REG_LAN_LED0_MAPPING			0x0278
+#define REG_LAN_LED1_MAPPING			0x027c
+
+#define LAN3_LED_MAPPING_MASK			GENMASK(14, 12)
+#define LAN3_PHY_LED_MAP(_n)			FIELD_PREP_CONST(LAN3_LED_MAPPING_MASK, (_n))
+
+#define LAN2_LED_MAPPING_MASK			GENMASK(10, 8)
+#define LAN2_PHY_LED_MAP(_n)			FIELD_PREP_CONST(LAN2_LED_MAPPING_MASK, (_n))
+
+#define LAN1_LED_MAPPING_MASK			GENMASK(6, 4)
+#define LAN1_PHY_LED_MAP(_n)			FIELD_PREP_CONST(LAN1_LED_MAPPING_MASK, (_n))
+
+#define LAN0_LED_MAPPING_MASK			GENMASK(2, 0)
+#define LAN0_PHY_LED_MAP(_n)			FIELD_PREP_CONST(LAN0_LED_MAPPING_MASK, (_n))
+
+/* CONF */
+#define REG_I2C_SDA_E2				0x001c
+#define SPI_MISO_E2_MASK			BIT(13)
+#define SPI_MOSI_E2_MASK			BIT(12)
+#define SPI_CLK_E2_MASK				BIT(11)
+#define SPI_CS0_E2_MASK				BIT(10)
+#define PCIE1_RESET_E2_MASK			BIT(9)
+#define PCIE0_RESET_E2_MASK			BIT(8)
+#define UART1_RXD_E2_MASK			BIT(3)
+#define UART1_TXD_E2_MASK			BIT(2)
+#define I2C_SCL_E2_MASK				BIT(1)
+#define I2C_SDA_E2_MASK				BIT(0)
+
+#define REG_I2C_SDA_E4				0x0020
+#define SPI_MISO_E4_MASK			BIT(13)
+#define SPI_MOSI_E4_MASK			BIT(12)
+#define SPI_CLK_E4_MASK				BIT(11)
+#define SPI_CS0_E4_MASK				BIT(10)
+#define PCIE1_RESET_E4_MASK			BIT(9)
+#define PCIE0_RESET_E4_MASK			BIT(8)
+#define UART1_RXD_E4_MASK			BIT(3)
+#define UART1_TXD_E4_MASK			BIT(2)
+#define I2C_SCL_E4_MASK				BIT(1)
+#define I2C_SDA_E4_MASK				BIT(0)
+
+#define REG_GPIO_L_E2				0x0024
+#define REG_GPIO_L_E4				0x0028
+
+#define REG_I2C_SDA_PU				0x0044
+#define SPI_MISO_PU_MASK			BIT(13)
+#define SPI_MOSI_PU_MASK			BIT(12)
+#define SPI_CLK_PU_MASK				BIT(11)
+#define SPI_CS0_PU_MASK				BIT(10)
+#define PCIE1_RESET_PU_MASK			BIT(9)
+#define PCIE0_RESET_PU_MASK			BIT(8)
+#define UART1_RXD_PU_MASK			BIT(3)
+#define UART1_TXD_PU_MASK			BIT(2)
+#define I2C_SCL_PU_MASK				BIT(1)
+#define I2C_SDA_PU_MASK				BIT(0)
+
+#define REG_I2C_SDA_PD				0x0048
+#define SPI_MISO_PD_MASK			BIT(13)
+#define SPI_MOSI_PD_MASK			BIT(12)
+#define SPI_CLK_PD_MASK				BIT(11)
+#define SPI_CS0_PD_MASK				BIT(10)
+#define PCIE1_RESET_PD_MASK			BIT(9)
+#define PCIE0_RESET_PD_MASK			BIT(8)
+#define UART1_RXD_PD_MASK			BIT(3)
+#define UART1_TXD_PD_MASK			BIT(2)
+#define I2C_SCL_PD_MASK				BIT(1)
+#define I2C_SDA_PD_MASK				BIT(0)
+
+#define REG_GPIO_L_PU				0x004c
+#define REG_GPIO_L_PD				0x0050
+
+/* PWM MODE CONF */
+#define REG_GPIO_FLASH_MODE_CFG			0x0034
+#define GPIO15_FLASH_MODE_CFG			BIT(15)
+#define GPIO14_FLASH_MODE_CFG			BIT(14)
+#define GPIO13_FLASH_MODE_CFG			BIT(13)
+#define GPIO12_FLASH_MODE_CFG			BIT(12)
+#define GPIO11_FLASH_MODE_CFG			BIT(11)
+#define GPIO10_FLASH_MODE_CFG			BIT(10)
+#define GPIO9_FLASH_MODE_CFG			BIT(9)
+#define GPIO8_FLASH_MODE_CFG			BIT(8)
+#define GPIO7_FLASH_MODE_CFG			BIT(7)
+#define GPIO6_FLASH_MODE_CFG			BIT(6)
+#define GPIO5_FLASH_MODE_CFG			BIT(5)
+#define GPIO4_FLASH_MODE_CFG			BIT(4)
+#define GPIO3_FLASH_MODE_CFG			BIT(3)
+#define GPIO2_FLASH_MODE_CFG			BIT(2)
+#define GPIO1_FLASH_MODE_CFG			BIT(1)
+#define GPIO0_FLASH_MODE_CFG			BIT(0)
+
+/* PWM MODE CONF EXT */
+#define REG_GPIO_FLASH_MODE_CFG_EXT		0x0068
+#define GPIO51_FLASH_MODE_CFG			BIT(31)
+#define GPIO50_FLASH_MODE_CFG			BIT(30)
+#define GPIO49_FLASH_MODE_CFG			BIT(29)
+#define GPIO48_FLASH_MODE_CFG			BIT(28)
+#define GPIO47_FLASH_MODE_CFG			BIT(27)
+#define GPIO46_FLASH_MODE_CFG			BIT(26)
+#define GPIO45_FLASH_MODE_CFG			BIT(25)
+#define GPIO44_FLASH_MODE_CFG			BIT(24)
+#define GPIO43_FLASH_MODE_CFG			BIT(23)
+#define GPIO42_FLASH_MODE_CFG			BIT(22)
+#define GPIO41_FLASH_MODE_CFG			BIT(21)
+#define GPIO40_FLASH_MODE_CFG			BIT(20)
+#define GPIO39_FLASH_MODE_CFG			BIT(19)
+#define GPIO38_FLASH_MODE_CFG			BIT(18)
+#define GPIO37_FLASH_MODE_CFG			BIT(17)
+#define GPIO36_FLASH_MODE_CFG			BIT(16)
+#define GPIO31_FLASH_MODE_CFG			BIT(15)
+#define GPIO30_FLASH_MODE_CFG			BIT(14)
+#define GPIO29_FLASH_MODE_CFG			BIT(13)
+#define GPIO28_FLASH_MODE_CFG			BIT(12)
+#define GPIO27_FLASH_MODE_CFG			BIT(11)
+#define GPIO26_FLASH_MODE_CFG			BIT(10)
+#define GPIO25_FLASH_MODE_CFG			BIT(9)
+#define GPIO24_FLASH_MODE_CFG			BIT(8)
+#define GPIO23_FLASH_MODE_CFG			BIT(7)
+#define GPIO22_FLASH_MODE_CFG			BIT(6)
+#define GPIO21_FLASH_MODE_CFG			BIT(5)
+#define GPIO20_FLASH_MODE_CFG			BIT(4)
+#define GPIO19_FLASH_MODE_CFG			BIT(3)
+#define GPIO18_FLASH_MODE_CFG			BIT(2)
+#define GPIO17_FLASH_MODE_CFG			BIT(1)
+#define GPIO16_FLASH_MODE_CFG			BIT(0)
+
+#define AIROHA_PINCTRL_GPIO(gpio, mux_val)			\
+	{							\
+		.name = (gpio),					\
+		.regmap[0] = {					\
+			AIROHA_FUNC_MUX,			\
+			REG_GPIO_PON_MODE,			\
+			(mux_val),				\
+			(mux_val)				\
+		},						\
+		.regmap_size = 1,				\
+	}
+
+#define AIROHA_PINCTRL_GPIO_EXT(gpio, mux_val, smux_val)	\
+	{							\
+		.name = (gpio),					\
+		.regmap[0] = {					\
+			AIROHA_FUNC_PWM_EXT_MUX,		\
+			REG_GPIO_FLASH_MODE_CFG_EXT,		\
+			(mux_val),				\
+			0					\
+		},						\
+		.regmap[1] = {					\
+			AIROHA_FUNC_MUX,			\
+			REG_GPIO_PON_MODE,			\
+			(smux_val),				\
+			(smux_val)				\
+		},						\
+		.regmap_size = 2,				\
+	}
+
+/* PWM */
+#define AIROHA_PINCTRL_PWM(gpio, mux_val)			\
+	{							\
+		.name = (gpio),					\
+		.regmap[0] = {					\
+			AIROHA_FUNC_PWM_MUX,			\
+			REG_GPIO_FLASH_MODE_CFG,		\
+			(mux_val),				\
+			(mux_val)				\
+		},						\
+		.regmap_size = 1,				\
+	}
+
+#define AIROHA_PINCTRL_PWM_EXT(gpio, mux_val)			\
+	{							\
+		.name = (gpio),					\
+		.regmap[0] = {					\
+			AIROHA_FUNC_PWM_EXT_MUX,		\
+			REG_GPIO_FLASH_MODE_CFG_EXT,		\
+			(mux_val),				\
+			(mux_val)				\
+		},						\
+		.regmap_size = 1,				\
+	}
+
+#define AIROHA_PINCTRL_PWM_EXT_SEC(gpio, mux_val, smux_val)	\
+	{							\
+		.name = (gpio),					\
+		.regmap[0] = {					\
+			AIROHA_FUNC_PWM_EXT_MUX,		\
+			REG_GPIO_FLASH_MODE_CFG_EXT,		\
+			(mux_val),				\
+			(mux_val)				\
+		},						\
+		.regmap[1] = {					\
+			AIROHA_FUNC_MUX,			\
+			REG_GPIO_PON_MODE,			\
+			(smux_val),				\
+			(smux_val)				\
+		},						\
+		.regmap_size = 2,				\
+	}
+
+#define AIROHA_PINCTRL_PHY_LED0(gpio, mux_val, map_mask, map_val)	\
+	{								\
+		.name = (gpio),						\
+		.regmap[0] = {						\
+			AIROHA_FUNC_MUX,				\
+			REG_GPIO_2ND_I2C_MODE,				\
+			(mux_val),					\
+			(mux_val),					\
+		},							\
+		.regmap[1] = {						\
+			AIROHA_FUNC_MUX,				\
+			REG_LAN_LED0_MAPPING,				\
+			(map_mask),					\
+			(map_val),					\
+		},							\
+		.regmap_size = 2,					\
+	}
+
+#define AIROHA_PINCTRL_PHY_LED1(gpio, mux_val, map_mask, map_val)	\
+	{								\
+		.name = (gpio),						\
+		.regmap[0] = {						\
+			AIROHA_FUNC_MUX,				\
+			REG_GPIO_2ND_I2C_MODE,				\
+			(mux_val),					\
+			(mux_val),					\
+		},							\
+		.regmap[1] = {						\
+			AIROHA_FUNC_MUX,				\
+			REG_LAN_LED1_MAPPING,				\
+			(map_mask),					\
+			(map_val),					\
+		},							\
+		.regmap_size = 2,					\
+	}
+
+static struct pinctrl_pin_desc pinctrl_pins[] = {
+	PINCTRL_PIN(2, "i2c_sda"),
+	PINCTRL_PIN(3, "i2c_scl"),
+	PINCTRL_PIN(4, "spi_cs0"),
+	PINCTRL_PIN(5, "spi_clk"),
+	PINCTRL_PIN(6, "spi_mosi"),
+	PINCTRL_PIN(7, "spi_miso"),
+	PINCTRL_PIN(8, "uart1_txd"),
+	PINCTRL_PIN(9, "uart1_rxd"),
+	PINCTRL_PIN(12, "gpio0"),
+	PINCTRL_PIN(13, "gpio1"),
+	PINCTRL_PIN(14, "gpio2"),
+	PINCTRL_PIN(15, "gpio3"),
+	PINCTRL_PIN(16, "gpio4"),
+	PINCTRL_PIN(17, "gpio5"),
+	PINCTRL_PIN(18, "gpio6"),
+	PINCTRL_PIN(19, "gpio7"),
+	PINCTRL_PIN(20, "gpio8"),
+	PINCTRL_PIN(21, "gpio9"),
+	PINCTRL_PIN(22, "gpio10"),
+	PINCTRL_PIN(23, "gpio11"),
+	PINCTRL_PIN(24, "gpio12"),
+	PINCTRL_PIN(25, "gpio13"),
+	PINCTRL_PIN(26, "gpio14"),
+	PINCTRL_PIN(27, "gpio15"),
+	PINCTRL_PIN(28, "gpio16"),
+	PINCTRL_PIN(29, "gpio17"),
+	PINCTRL_PIN(30, "gpio18"),
+	PINCTRL_PIN(31, "gpio19"),
+	PINCTRL_PIN(32, "gpio20"),
+	PINCTRL_PIN(33, "gpio21"),
+	PINCTRL_PIN(34, "gpio22"),
+	PINCTRL_PIN(35, "gpio23"),
+	PINCTRL_PIN(36, "gpio24"),
+	PINCTRL_PIN(37, "gpio25"),
+	PINCTRL_PIN(38, "gpio26"),
+	PINCTRL_PIN(39, "gpio27"),
+	PINCTRL_PIN(40, "pcie_reset0"),
+	PINCTRL_PIN(41, "pcie_reset1"),
+};
+
+static const int pon_pins[] = { 28, 29, 30, 31, 32, 33 };
+static const int pon_tod_1pps_pins[] = { 21 };
+static const int gsw_tod_1pps_pins[] = { 21 };
+static const int sipo_pins[] = { 13, 38 };
+static const int sipo_rclk_pins[] = { 13, 30, 38 };
+static const int mdio_pins[] = { 20, 21 };
+static const int uart2_pins[] = { 20, 21 };
+static const int npu_uart_pins[] = { 13, 38 };
+static const int i2c0_pins[] = { 2, 3 };
+static const int i2c1_pins[] = { 14, 15 };
+static const int jtag_udi_pins[] = { 34, 35, 36, 37, 38 };
+static const int jtag_dfd_pins[] = { 34, 35, 36, 37, 38 };
+static const int i2s_pins[] = { 16, 17, 18, 19 };
+static const int pcm1_pins[] = { 24, 25, 26, 27 };
+static const int pcm2_pins[] = { 16, 17, 18, 19 };
+static const int spi_pins[] = { 4, 5, 6, 7 };
+static const int spi_quad_pins[] = { 14, 15 };
+static const int spi_cs1_pins[] = { 21 };
+static const int pcm_spi_pins[] = { 16, 17, 18, 19, 24, 25, 26, 27 };
+static const int pcm_spi_int_pins[] = { 15 };
+static const int pcm_spi_rst_pins[] = { 14 };
+static const int pcm_spi_cs1_pins[] = { 22 };
+static const int pcm_spi_cs2_p128_pins[] = { 39 };
+static const int pcm_spi_cs2_p156_pins[] = { 39 };
+static const int pcm_spi_cs3_pins[] = { 20 };
+static const int pcm_spi_cs4_pins[] = { 23 };
+static const int gpio0_pins[] = { 12 };
+static const int gpio1_pins[] = { 13 };
+static const int gpio2_pins[] = { 14 };
+static const int gpio3_pins[] = { 15 };
+static const int gpio4_pins[] = { 16 };
+static const int gpio5_pins[] = { 17 };
+static const int gpio6_pins[] = { 18 };
+static const int gpio7_pins[] = { 19 };
+static const int gpio8_pins[] = { 20 };
+static const int gpio9_pins[] = { 21 };
+static const int gpio10_pins[] = { 22 };
+static const int gpio11_pins[] = { 23 };
+static const int gpio12_pins[] = { 24 };
+static const int gpio13_pins[] = { 25 };
+static const int gpio14_pins[] = { 26 };
+static const int gpio15_pins[] = { 27 };
+static const int gpio16_pins[] = { 28 };
+static const int gpio17_pins[] = { 29 };
+static const int gpio18_pins[] = { 30 };
+static const int gpio19_pins[] = { 31 };
+static const int gpio20_pins[] = { 32 };
+static const int gpio21_pins[] = { 33 };
+static const int gpio22_pins[] = { 34 };
+static const int gpio23_pins[] = { 35 };
+static const int gpio24_pins[] = { 36 };
+static const int gpio25_pins[] = { 37 };
+static const int gpio26_pins[] = { 38 };
+static const int gpio27_pins[] = { 39 };
+static const int gpio28_pins[] = { 40 };
+static const int gpio29_pins[] = { 41 };
+static const int pcie_reset0_pins[] = { 40 };
+static const int pcie_reset1_pins[] = { 41 };
+
+static const struct pingroup pinctrl_groups[] = {
+	PINCTRL_PIN_GROUP("pon", pon),
+	PINCTRL_PIN_GROUP("pon_tod_1pps", pon_tod_1pps),
+	PINCTRL_PIN_GROUP("gsw_tod_1pps", gsw_tod_1pps),
+	PINCTRL_PIN_GROUP("sipo", sipo),
+	PINCTRL_PIN_GROUP("sipo_rclk", sipo_rclk),
+	PINCTRL_PIN_GROUP("mdio", mdio),
+	PINCTRL_PIN_GROUP("uart2", uart2),
+	PINCTRL_PIN_GROUP("npu_uart", npu_uart),
+	PINCTRL_PIN_GROUP("i2c0", i2c0),
+	PINCTRL_PIN_GROUP("i2c1", i2c1),
+	PINCTRL_PIN_GROUP("jtag_udi", jtag_udi),
+	PINCTRL_PIN_GROUP("jtag_dfd", jtag_dfd),
+	PINCTRL_PIN_GROUP("i2s", i2s),
+	PINCTRL_PIN_GROUP("pcm1", pcm1),
+	PINCTRL_PIN_GROUP("pcm2", pcm2),
+	PINCTRL_PIN_GROUP("spi", spi),
+	PINCTRL_PIN_GROUP("spi_quad", spi_quad),
+	PINCTRL_PIN_GROUP("spi_cs1", spi_cs1),
+	PINCTRL_PIN_GROUP("pcm_spi", pcm_spi),
+	PINCTRL_PIN_GROUP("pcm_spi_int", pcm_spi_int),
+	PINCTRL_PIN_GROUP("pcm_spi_rst", pcm_spi_rst),
+	PINCTRL_PIN_GROUP("pcm_spi_cs1", pcm_spi_cs1),
+	PINCTRL_PIN_GROUP("pcm_spi_cs2_p128", pcm_spi_cs2_p128),
+	PINCTRL_PIN_GROUP("pcm_spi_cs2_p156", pcm_spi_cs2_p156),
+	PINCTRL_PIN_GROUP("pcm_spi_cs3", pcm_spi_cs3),
+	PINCTRL_PIN_GROUP("pcm_spi_cs4", pcm_spi_cs4),
+	PINCTRL_PIN_GROUP("gpio0", gpio0),
+	PINCTRL_PIN_GROUP("gpio1", gpio1),
+	PINCTRL_PIN_GROUP("gpio2", gpio2),
+	PINCTRL_PIN_GROUP("gpio3", gpio3),
+	PINCTRL_PIN_GROUP("gpio4", gpio4),
+	PINCTRL_PIN_GROUP("gpio5", gpio5),
+	PINCTRL_PIN_GROUP("gpio6", gpio6),
+	PINCTRL_PIN_GROUP("gpio7", gpio7),
+	PINCTRL_PIN_GROUP("gpio8", gpio8),
+	PINCTRL_PIN_GROUP("gpio9", gpio9),
+	PINCTRL_PIN_GROUP("gpio10", gpio10),
+	PINCTRL_PIN_GROUP("gpio11", gpio11),
+	PINCTRL_PIN_GROUP("gpio12", gpio12),
+	PINCTRL_PIN_GROUP("gpio13", gpio13),
+	PINCTRL_PIN_GROUP("gpio14", gpio14),
+	PINCTRL_PIN_GROUP("gpio15", gpio15),
+	PINCTRL_PIN_GROUP("gpio16", gpio16),
+	PINCTRL_PIN_GROUP("gpio17", gpio17),
+	PINCTRL_PIN_GROUP("gpio18", gpio18),
+	PINCTRL_PIN_GROUP("gpio19", gpio19),
+	PINCTRL_PIN_GROUP("gpio20", gpio20),
+	PINCTRL_PIN_GROUP("gpio21", gpio21),
+	PINCTRL_PIN_GROUP("gpio22", gpio22),
+	PINCTRL_PIN_GROUP("gpio23", gpio23),
+	PINCTRL_PIN_GROUP("gpio24", gpio24),
+	PINCTRL_PIN_GROUP("gpio25", gpio25),
+	PINCTRL_PIN_GROUP("gpio26", gpio26),
+	PINCTRL_PIN_GROUP("gpio27", gpio27),
+	PINCTRL_PIN_GROUP("gpio28", gpio28),
+	PINCTRL_PIN_GROUP("gpio29", gpio29),
+	PINCTRL_PIN_GROUP("pcie_reset0", pcie_reset0),
+	PINCTRL_PIN_GROUP("pcie_reset1", pcie_reset1),
+};
+
+static const char *const pon_groups[] = { "pon" };
+static const char *const tod_1pps_groups[] = {
+	"pon_tod_1pps", "gsw_tod_1pps"
+};
+static const char *const sipo_groups[] = { "sipo", "sipo_rclk" };
+static const char *const mdio_groups[] = { "mdio" };
+static const char *const uart_groups[] = { "uart2", "npu_uart" };
+static const char *const i2c_groups[] = { "i2c1" };
+static const char *const jtag_groups[] = { "jtag_udi", "jtag_dfd" };
+static const char *const pcm_groups[] = { "pcm1", "pcm2" };
+static const char *const spi_groups[] = { "spi_quad", "spi_cs1" };
+static const char *const pcm_spi_groups[] = {
+	"pcm_spi", "pcm_spi_int", "pcm_spi_rst", "pcm_spi_cs1",
+	"pcm_spi_cs2_p156", "pcm_spi_cs2_p128", "pcm_spi_cs3", "pcm_spi_cs4"
+};
+static const char *const i2s_groups[] = { "i2s" };
+static const char *const gpio_groups[] = { "gpio28", "gpio29" };
+static const char *const pcie_reset_groups[] = {
+	"pcie_reset0", "pcie_reset1"
+};
+static const char *const pwm_groups[] = {
+	"gpio0",  "gpio1",  "gpio2",  "gpio3",  "gpio4",  "gpio5",
+	"gpio6",  "gpio7",  "gpio8",  "gpio9",  "gpio10", "gpio11",
+	"gpio12", "gpio13", "gpio14", "gpio15", "gpio16", "gpio17",
+	"gpio18", "gpio19", "gpio20", "gpio21", "gpio22", "gpio23",
+	"gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29"
+};
+static const char *const phy1_led0_groups[] = {
+	"gpio22", "gpio23", "gpio24", "gpio25"
+};
+static const char *const phy2_led0_groups[] = {
+	"gpio22", "gpio23", "gpio24", "gpio25"
+};
+static const char *const phy3_led0_groups[] = {
+	"gpio22", "gpio23", "gpio24", "gpio25"
+};
+static const char *const phy4_led0_groups[] = {
+	"gpio22", "gpio23", "gpio24", "gpio25"
+};
+static const char *const phy1_led1_groups[] = {
+	"gpio7", "gpio6", "gpio5", "gpio4"
+};
+static const char *const phy2_led1_groups[] = {
+	"gpio7", "gpio6", "gpio5", "gpio4"
+};
+static const char *const phy3_led1_groups[] = {
+	"gpio7", "gpio6", "gpio5", "gpio4"
+};
+static const char *const phy4_led1_groups[] = {
+	"gpio7", "gpio6", "gpio5", "gpio4"
+};
+
+static const struct airoha_pinctrl_func_group pon_func_group[] = {
+	{
+		.name = "pon",
+		.regmap[0] = {
+			AIROHA_FUNC_MUX,
+			REG_GPIO_PON_MODE,
+			GPIO_PON_MODE_MASK,
+			GPIO_PON_MODE_MASK
+		},
+		.regmap_size = 1,
+	},
+};
+
+static const struct airoha_pinctrl_func_group tod_1pps_func_group[] = {
+	{
+		.name = "pon_tod_1pps",
+		.regmap[0] = {
+			AIROHA_FUNC_MUX,
+			REG_GPIO_2ND_I2C_MODE,
+			PON_TOD_1PPS_MODE_MASK,
+			PON_TOD_1PPS_MODE_MASK
+		},
+		.regmap_size = 1,
+	}, {
+		.name = "gsw_tod_1pps",
+		.regmap[0] = {
+			AIROHA_FUNC_MUX,
+			REG_GPIO_2ND_I2C_MODE,
+			GSW_TOD_1PPS_MODE_MASK,
+			GSW_TOD_1PPS_MODE_MASK
+		},
+		.regmap_size = 1,
+	},
+};
+
+static const struct airoha_pinctrl_func_group sipo_func_group[] = {
+	{
+		.name = "sipo",
+		.regmap[0] = {
+			AIROHA_FUNC_MUX,
+			REG_GPIO_PON_MODE,
+			GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK,
+			GPIO_SIPO_MODE_MASK
+		},
+		.regmap_size = 1,
+	}, {
+		.name = "sipo_rclk",
+		.regmap[0] = {
+			AIROHA_FUNC_MUX,
+			REG_GPIO_PON_MODE,
+			GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK,
+			GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK
+		},
+		.regmap_size = 1,
+	},
+};
+
+static const struct airoha_pinctrl_func_group mdio_func_group[] = {
+	{
+		.name = "mdio",
+		.regmap[0] = {
+			AIROHA_FUNC_MUX,
+			REG_GPIO_PON_MODE,
+			GPIO_SGMII_MDIO_MODE_MASK,
+			GPIO_SGMII_MDIO_MODE_MASK
+		},
+		.regmap_size = 1,
+	},
+};
+
+static const struct airoha_pinctrl_func_group uart_func_group[] = {
+	{
+		.name = "uart2",
+		.regmap[0] = {
+			AIROHA_FUNC_MUX,
+			REG_GPIO_PON_MODE,
+			GPIO_UART2_MODE_MASK,
+			GPIO_UART2_MODE_MASK
+		},
+		.regmap_size = 1,
+	}, {
+		.name = "npu_uart",
+		.regmap[0] = {
+			AIROHA_FUNC_MUX,
+			REG_NPU_UART_EN,
+			NPU_UART_EN_MASK,
+			NPU_UART_EN_MASK
+		},
+		.regmap_size = 1,
+	}
+};
+
+static const struct airoha_pinctrl_func_group i2c_func_group[] = {
+	{
+		.name = "i2c1",
+		.regmap[0] = {
+			AIROHA_FUNC_MUX,
+			REG_GPIO_2ND_I2C_MODE,
+			GPIO_2ND_I2C_MODE_MASK,
+			GPIO_2ND_I2C_MODE_MASK
+		},
+		.regmap_size = 1,
+	},
+};
+
+static const struct airoha_pinctrl_func_group jtag_func_group[] = {
+	{
+		.name = "jtag_udi",
+		.regmap[0] = {
+			AIROHA_FUNC_MUX,
+			REG_NPU_UART_EN,
+			JTAG_UDI_EN_MASK,
+			JTAG_UDI_EN_MASK
+		},
+		.regmap_size = 1,
+	}, {
+		.name = "jtag_dfd",
+		.regmap[0] = {
+			AIROHA_FUNC_MUX,
+			REG_NPU_UART_EN,
+			JTAG_DFD_EN_MASK,
+			JTAG_DFD_EN_MASK
+		},
+		.regmap_size = 1,
+	},
+};
+
+static const struct airoha_pinctrl_func_group pcm_func_group[] = {
+	{
+		.name = "pcm1",
+		.regmap[0] = {
+			AIROHA_FUNC_MUX,
+			REG_GPIO_SPI_CS1_MODE,
+			GPIO_PCM1_MODE_MASK,
+			GPIO_PCM1_MODE_MASK
+		},
+		.regmap_size = 1,
+	}, {
+		.name = "pcm2",
+		.regmap[0] = {
+			AIROHA_FUNC_MUX,
+			REG_GPIO_SPI_CS1_MODE,
+			GPIO_PCM2_MODE_MASK,
+			GPIO_PCM2_MODE_MASK
+		},
+		.regmap_size = 1,
+	},
+};
+
+static const struct airoha_pinctrl_func_group spi_func_group[] = {
+	{
+		.name = "spi_quad",
+		.regmap[0] = {
+			AIROHA_FUNC_MUX,
+			REG_GPIO_SPI_CS1_MODE,
+			GPIO_SPI_QUAD_MODE_MASK,
+			GPIO_SPI_QUAD_MODE_MASK
+		},
+		.regmap_size = 1,
+	}, {
+		.name = "spi_cs1",
+		.regmap[0] = {
+			AIROHA_FUNC_MUX,
+			REG_GPIO_SPI_CS1_MODE,
+			GPIO_SPI_CS1_MODE_MASK,
+			GPIO_SPI_CS1_MODE_MASK
+		},
+		.regmap_size = 1,
+	},
+};
+
+static const struct airoha_pinctrl_func_group pcm_spi_func_group[] = {
+	{
+		.name = "pcm_spi",
+		.regmap[0] = {
+			AIROHA_FUNC_MUX,
+			REG_GPIO_SPI_CS1_MODE,
+			GPIO_PCM_SPI_MODE_MASK,
+			GPIO_PCM_SPI_MODE_MASK
+		},
+		.regmap_size = 1,
+	}, {
+		.name = "pcm_spi_int",
+		.regmap[0] = {
+			AIROHA_FUNC_MUX,
+			REG_GPIO_SPI_CS1_MODE,
+			GPIO_PCM_INT_MODE_MASK,
+			GPIO_PCM_INT_MODE_MASK
+		},
+		.regmap_size = 1,
+	}, {
+		.name = "pcm_spi_rst",
+		.regmap[0] = {
+			AIROHA_FUNC_MUX,
+			REG_GPIO_SPI_CS1_MODE,
+			GPIO_PCM_RESET_MODE_MASK,
+			GPIO_PCM_RESET_MODE_MASK
+		},
+		.regmap_size = 1,
+	}, {
+		.name = "pcm_spi_cs1",
+		.regmap[0] = {
+			AIROHA_FUNC_MUX,
+			REG_GPIO_SPI_CS1_MODE,
+			GPIO_PCM_SPI_CS1_MODE_MASK,
+			GPIO_PCM_SPI_CS1_MODE_MASK
+		},
+		.regmap_size = 1,
+	}, {
+		.name = "pcm_spi_cs2_p128",
+		.regmap[0] = {
+			AIROHA_FUNC_MUX,
+			REG_GPIO_SPI_CS1_MODE,
+			GPIO_PCM_SPI_CS2_MODE_P128_MASK,
+			GPIO_PCM_SPI_CS2_MODE_P128_MASK
+		},
+		.regmap_size = 1,
+	}, {
+		.name = "pcm_spi_cs2_p156",
+		.regmap[0] = {
+			AIROHA_FUNC_MUX,
+			REG_GPIO_SPI_CS1_MODE,
+			GPIO_PCM_SPI_CS2_MODE_P156_MASK,
+			GPIO_PCM_SPI_CS2_MODE_P156_MASK
+		},
+		.regmap_size = 1,
+	}, {
+		.name = "pcm_spi_cs3",
+		.regmap[0] = {
+			AIROHA_FUNC_MUX,
+			REG_GPIO_SPI_CS1_MODE,
+			GPIO_PCM_SPI_CS3_MODE_MASK,
+			GPIO_PCM_SPI_CS3_MODE_MASK
+		},
+		.regmap_size = 1,
+	}, {
+		.name = "pcm_spi_cs4",
+		.regmap[0] = {
+			AIROHA_FUNC_MUX,
+			REG_GPIO_SPI_CS1_MODE,
+			GPIO_PCM_SPI_CS4_MODE_MASK,
+			GPIO_PCM_SPI_CS4_MODE_MASK
+		},
+		.regmap_size = 1,
+	},
+};
+
+static const struct airoha_pinctrl_func_group i2s_func_group[] = {
+	{
+		.name = "i2s",
+		.regmap[0] = {
+			AIROHA_FUNC_MUX,
+			REG_GPIO_2ND_I2C_MODE,
+			GPIO_I2S_MODE_MASK,
+			GPIO_I2S_MODE_MASK
+		},
+		.regmap_size = 1,
+	},
+};
+
+static const struct airoha_pinctrl_func_group gpio_func_group[] = {
+	AIROHA_PINCTRL_GPIO_EXT("gpio28", GPIO28_FLASH_MODE_CFG,
+				GPIO_PCIE_RESET0_MASK),
+	AIROHA_PINCTRL_GPIO_EXT("gpio29", GPIO29_FLASH_MODE_CFG,
+				GPIO_PCIE_RESET1_MASK),
+};
+
+static const struct airoha_pinctrl_func_group pcie_reset_func_group[] = {
+	{
+		.name = "pcie_reset0",
+		.regmap[0] = {
+			AIROHA_FUNC_MUX,
+			REG_GPIO_PON_MODE,
+			GPIO_PCIE_RESET0_MASK,
+			0
+		},
+		.regmap_size = 1,
+	}, {
+		.name = "pcie_reset1",
+		.regmap[0] = {
+			AIROHA_FUNC_MUX,
+			REG_GPIO_PON_MODE,
+			GPIO_PCIE_RESET1_MASK,
+			0
+		},
+		.regmap_size = 1,
+	},
+};
+
+static const struct airoha_pinctrl_func_group pwm_func_group[] = {
+	AIROHA_PINCTRL_PWM("gpio0", GPIO0_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM("gpio1", GPIO1_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM("gpio2", GPIO2_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM("gpio3", GPIO3_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM("gpio4", GPIO4_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM("gpio5", GPIO5_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM("gpio6", GPIO6_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM("gpio7", GPIO7_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM("gpio8", GPIO8_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM("gpio9", GPIO9_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM("gpio10", GPIO10_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM("gpio11", GPIO11_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM("gpio12", GPIO12_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM("gpio13", GPIO13_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM("gpio14", GPIO14_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM("gpio15", GPIO15_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM_EXT("gpio16", GPIO16_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM_EXT("gpio17", GPIO17_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM_EXT("gpio18", GPIO18_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM_EXT("gpio19", GPIO19_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM_EXT("gpio20", GPIO20_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM_EXT("gpio21", GPIO21_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM_EXT("gpio22", GPIO22_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM_EXT("gpio23", GPIO23_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM_EXT("gpio24", GPIO24_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM_EXT("gpio25", GPIO25_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM_EXT("gpio26", GPIO26_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM_EXT("gpio27", GPIO27_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM_EXT_SEC("gpio28", GPIO28_FLASH_MODE_CFG,
+				   GPIO_PCIE_RESET0_MASK),
+	AIROHA_PINCTRL_PWM_EXT_SEC("gpio29", GPIO29_FLASH_MODE_CFG,
+				   GPIO_PCIE_RESET1_MASK),
+};
+
+static const struct airoha_pinctrl_func_group phy1_led0_func_group[] = {
+	AIROHA_PINCTRL_PHY_LED0("gpio22", GPIO_LAN0_LED0_MODE_MASK,
+				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),
+	AIROHA_PINCTRL_PHY_LED0("gpio23", GPIO_LAN1_LED0_MODE_MASK,
+				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)),
+	AIROHA_PINCTRL_PHY_LED0("gpio24", GPIO_LAN2_LED0_MODE_MASK,
+				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)),
+	AIROHA_PINCTRL_PHY_LED0("gpio25", GPIO_LAN3_LED0_MODE_MASK,
+				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),
+};
+
+static const struct airoha_pinctrl_func_group phy2_led0_func_group[] = {
+	AIROHA_PINCTRL_PHY_LED0("gpio22", GPIO_LAN0_LED0_MODE_MASK,
+				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),
+	AIROHA_PINCTRL_PHY_LED0("gpio23", GPIO_LAN1_LED0_MODE_MASK,
+				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)),
+	AIROHA_PINCTRL_PHY_LED0("gpio24", GPIO_LAN2_LED0_MODE_MASK,
+				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)),
+	AIROHA_PINCTRL_PHY_LED0("gpio25", GPIO_LAN3_LED0_MODE_MASK,
+				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),
+};
+
+static const struct airoha_pinctrl_func_group phy3_led0_func_group[] = {
+	AIROHA_PINCTRL_PHY_LED0("gpio22", GPIO_LAN0_LED0_MODE_MASK,
+				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
+	AIROHA_PINCTRL_PHY_LED0("gpio23", GPIO_LAN1_LED0_MODE_MASK,
+				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),
+	AIROHA_PINCTRL_PHY_LED0("gpio24", GPIO_LAN2_LED0_MODE_MASK,
+				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),
+	AIROHA_PINCTRL_PHY_LED0("gpio25", GPIO_LAN3_LED0_MODE_MASK,
+				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
+};
+
+static const struct airoha_pinctrl_func_group phy4_led0_func_group[] = {
+	AIROHA_PINCTRL_PHY_LED0("gpio22", GPIO_LAN0_LED0_MODE_MASK,
+				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)),
+	AIROHA_PINCTRL_PHY_LED0("gpio23", GPIO_LAN1_LED0_MODE_MASK,
+				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)),
+	AIROHA_PINCTRL_PHY_LED0("gpio24", GPIO_LAN2_LED0_MODE_MASK,
+				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)),
+	AIROHA_PINCTRL_PHY_LED0("gpio25", GPIO_LAN3_LED0_MODE_MASK,
+				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)),
+};
+
+static const struct airoha_pinctrl_func_group phy1_led1_func_group[] = {
+	AIROHA_PINCTRL_PHY_LED1("gpio7", GPIO_LAN0_LED1_MODE_MASK,
+				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),
+	AIROHA_PINCTRL_PHY_LED1("gpio6", GPIO_LAN1_LED1_MODE_MASK,
+				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)),
+	AIROHA_PINCTRL_PHY_LED1("gpio5", GPIO_LAN2_LED1_MODE_MASK,
+				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)),
+	AIROHA_PINCTRL_PHY_LED1("gpio4", GPIO_LAN3_LED1_MODE_MASK,
+				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),
+};
+
+static const struct airoha_pinctrl_func_group phy2_led1_func_group[] = {
+	AIROHA_PINCTRL_PHY_LED1("gpio7", GPIO_LAN0_LED1_MODE_MASK,
+				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),
+	AIROHA_PINCTRL_PHY_LED1("gpio6", GPIO_LAN1_LED1_MODE_MASK,
+				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)),
+	AIROHA_PINCTRL_PHY_LED1("gpio5", GPIO_LAN2_LED1_MODE_MASK,
+				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)),
+	AIROHA_PINCTRL_PHY_LED1("gpio4", GPIO_LAN3_LED1_MODE_MASK,
+				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),
+};
+
+static const struct airoha_pinctrl_func_group phy3_led1_func_group[] = {
+	AIROHA_PINCTRL_PHY_LED1("gpio7", GPIO_LAN0_LED1_MODE_MASK,
+				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
+	AIROHA_PINCTRL_PHY_LED1("gpio6", GPIO_LAN1_LED1_MODE_MASK,
+				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),
+	AIROHA_PINCTRL_PHY_LED1("gpio5", GPIO_LAN2_LED1_MODE_MASK,
+				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),
+	AIROHA_PINCTRL_PHY_LED1("gpio4", GPIO_LAN3_LED1_MODE_MASK,
+				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
+};
+
+static const struct airoha_pinctrl_func_group phy4_led1_func_group[] = {
+	AIROHA_PINCTRL_PHY_LED1("gpio7", GPIO_LAN0_LED1_MODE_MASK,
+				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)),
+	AIROHA_PINCTRL_PHY_LED1("gpio6", GPIO_LAN1_LED1_MODE_MASK,
+				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)),
+	AIROHA_PINCTRL_PHY_LED1("gpio5", GPIO_LAN2_LED1_MODE_MASK,
+				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)),
+	AIROHA_PINCTRL_PHY_LED1("gpio4", GPIO_LAN3_LED1_MODE_MASK,
+				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)),
+};
+
+static const struct airoha_pinctrl_func pinctrl_funcs[] = {
+	PINCTRL_FUNC_DESC("pon", pon),
+	PINCTRL_FUNC_DESC("tod_1pps", tod_1pps),
+	PINCTRL_FUNC_DESC("sipo", sipo),
+	PINCTRL_FUNC_DESC("mdio", mdio),
+	PINCTRL_FUNC_DESC("uart", uart),
+	PINCTRL_FUNC_DESC("i2c", i2c),
+	PINCTRL_FUNC_DESC("jtag", jtag),
+	PINCTRL_FUNC_DESC("pcm", pcm),
+	PINCTRL_FUNC_DESC("spi", spi),
+	PINCTRL_FUNC_DESC("pcm_spi", pcm_spi),
+	PINCTRL_FUNC_DESC("i2s", i2s),
+	PINCTRL_FUNC_DESC("gpio", gpio),
+	PINCTRL_FUNC_DESC("pcie_reset", pcie_reset),
+	PINCTRL_FUNC_DESC("pwm", pwm),
+	PINCTRL_FUNC_DESC("phy1_led0", phy1_led0),
+	PINCTRL_FUNC_DESC("phy2_led0", phy2_led0),
+	PINCTRL_FUNC_DESC("phy3_led0", phy3_led0),
+	PINCTRL_FUNC_DESC("phy4_led0", phy4_led0),
+	PINCTRL_FUNC_DESC("phy1_led1", phy1_led1),
+	PINCTRL_FUNC_DESC("phy2_led1", phy2_led1),
+	PINCTRL_FUNC_DESC("phy3_led1", phy3_led1),
+	PINCTRL_FUNC_DESC("phy4_led1", phy4_led1),
+};
+
+static const struct airoha_pinctrl_conf pinctrl_pullup_conf[] = {
+	PINCTRL_CONF_DESC(12, REG_GPIO_L_PU, BIT(0)),
+	PINCTRL_CONF_DESC(13, REG_GPIO_L_PU, BIT(1)),
+	PINCTRL_CONF_DESC(14, REG_GPIO_L_PU, BIT(2)),
+	PINCTRL_CONF_DESC(15, REG_GPIO_L_PU, BIT(3)),
+	PINCTRL_CONF_DESC(16, REG_GPIO_L_PU, BIT(4)),
+	PINCTRL_CONF_DESC(17, REG_GPIO_L_PU, BIT(5)),
+	PINCTRL_CONF_DESC(18, REG_GPIO_L_PU, BIT(6)),
+	PINCTRL_CONF_DESC(19, REG_GPIO_L_PU, BIT(7)),
+	PINCTRL_CONF_DESC(20, REG_GPIO_L_PU, BIT(8)),
+	PINCTRL_CONF_DESC(21, REG_GPIO_L_PU, BIT(9)),
+	PINCTRL_CONF_DESC(22, REG_GPIO_L_PU, BIT(10)),
+	PINCTRL_CONF_DESC(23, REG_GPIO_L_PU, BIT(11)),
+	PINCTRL_CONF_DESC(24, REG_GPIO_L_PU, BIT(12)),
+	PINCTRL_CONF_DESC(25, REG_GPIO_L_PU, BIT(13)),
+	PINCTRL_CONF_DESC(26, REG_GPIO_L_PU, BIT(14)),
+	PINCTRL_CONF_DESC(27, REG_GPIO_L_PU, BIT(15)),
+	PINCTRL_CONF_DESC(28, REG_GPIO_L_PU, BIT(16)),
+	PINCTRL_CONF_DESC(29, REG_GPIO_L_PU, BIT(17)),
+	PINCTRL_CONF_DESC(30, REG_GPIO_L_PU, BIT(18)),
+	PINCTRL_CONF_DESC(31, REG_GPIO_L_PU, BIT(19)),
+	PINCTRL_CONF_DESC(32, REG_GPIO_L_PU, BIT(20)),
+	PINCTRL_CONF_DESC(33, REG_GPIO_L_PU, BIT(21)),
+	PINCTRL_CONF_DESC(34, REG_GPIO_L_PU, BIT(22)),
+	PINCTRL_CONF_DESC(35, REG_GPIO_L_PU, BIT(23)),
+	PINCTRL_CONF_DESC(36, REG_GPIO_L_PU, BIT(24)),
+	PINCTRL_CONF_DESC(37, REG_GPIO_L_PU, BIT(25)),
+	PINCTRL_CONF_DESC(38, REG_GPIO_L_PU, BIT(26)),
+	PINCTRL_CONF_DESC(39, REG_GPIO_L_PU, BIT(27)),
+	PINCTRL_CONF_DESC(40, REG_GPIO_L_PU, BIT(28)),
+	PINCTRL_CONF_DESC(41, REG_GPIO_L_PU, BIT(29)),
+};
+
+static const struct airoha_pinctrl_conf pinctrl_pulldown_conf[] = {
+	PINCTRL_CONF_DESC(12, REG_GPIO_L_PD, BIT(0)),
+	PINCTRL_CONF_DESC(13, REG_GPIO_L_PD, BIT(1)),
+	PINCTRL_CONF_DESC(14, REG_GPIO_L_PD, BIT(2)),
+	PINCTRL_CONF_DESC(15, REG_GPIO_L_PD, BIT(3)),
+	PINCTRL_CONF_DESC(16, REG_GPIO_L_PD, BIT(4)),
+	PINCTRL_CONF_DESC(17, REG_GPIO_L_PD, BIT(5)),
+	PINCTRL_CONF_DESC(18, REG_GPIO_L_PD, BIT(6)),
+	PINCTRL_CONF_DESC(19, REG_GPIO_L_PD, BIT(7)),
+	PINCTRL_CONF_DESC(20, REG_GPIO_L_PD, BIT(8)),
+	PINCTRL_CONF_DESC(21, REG_GPIO_L_PD, BIT(9)),
+	PINCTRL_CONF_DESC(22, REG_GPIO_L_PD, BIT(10)),
+	PINCTRL_CONF_DESC(23, REG_GPIO_L_PD, BIT(11)),
+	PINCTRL_CONF_DESC(24, REG_GPIO_L_PD, BIT(12)),
+	PINCTRL_CONF_DESC(25, REG_GPIO_L_PD, BIT(13)),
+	PINCTRL_CONF_DESC(26, REG_GPIO_L_PD, BIT(14)),
+	PINCTRL_CONF_DESC(27, REG_GPIO_L_PD, BIT(15)),
+	PINCTRL_CONF_DESC(28, REG_GPIO_L_PD, BIT(16)),
+	PINCTRL_CONF_DESC(29, REG_GPIO_L_PD, BIT(17)),
+	PINCTRL_CONF_DESC(30, REG_GPIO_L_PD, BIT(18)),
+	PINCTRL_CONF_DESC(31, REG_GPIO_L_PD, BIT(19)),
+	PINCTRL_CONF_DESC(32, REG_GPIO_L_PD, BIT(20)),
+	PINCTRL_CONF_DESC(33, REG_GPIO_L_PD, BIT(21)),
+	PINCTRL_CONF_DESC(34, REG_GPIO_L_PD, BIT(22)),
+	PINCTRL_CONF_DESC(35, REG_GPIO_L_PD, BIT(23)),
+	PINCTRL_CONF_DESC(36, REG_GPIO_L_PD, BIT(24)),
+	PINCTRL_CONF_DESC(37, REG_GPIO_L_PD, BIT(25)),
+	PINCTRL_CONF_DESC(38, REG_GPIO_L_PD, BIT(26)),
+	PINCTRL_CONF_DESC(39, REG_GPIO_L_PD, BIT(27)),
+	PINCTRL_CONF_DESC(40, REG_GPIO_L_PD, BIT(28)),
+	PINCTRL_CONF_DESC(41, REG_GPIO_L_PD, BIT(29)),
+};
+
+static const struct airoha_pinctrl_conf pinctrl_drive_e2_conf[] = {
+	PINCTRL_CONF_DESC(12, REG_GPIO_L_E2, BIT(0)),
+	PINCTRL_CONF_DESC(13, REG_GPIO_L_E2, BIT(1)),
+	PINCTRL_CONF_DESC(14, REG_GPIO_L_E2, BIT(2)),
+	PINCTRL_CONF_DESC(15, REG_GPIO_L_E2, BIT(3)),
+	PINCTRL_CONF_DESC(16, REG_GPIO_L_E2, BIT(4)),
+	PINCTRL_CONF_DESC(17, REG_GPIO_L_E2, BIT(5)),
+	PINCTRL_CONF_DESC(18, REG_GPIO_L_E2, BIT(6)),
+	PINCTRL_CONF_DESC(19, REG_GPIO_L_E2, BIT(7)),
+	PINCTRL_CONF_DESC(20, REG_GPIO_L_E2, BIT(8)),
+	PINCTRL_CONF_DESC(21, REG_GPIO_L_E2, BIT(9)),
+	PINCTRL_CONF_DESC(22, REG_GPIO_L_E2, BIT(10)),
+	PINCTRL_CONF_DESC(23, REG_GPIO_L_E2, BIT(11)),
+	PINCTRL_CONF_DESC(24, REG_GPIO_L_E2, BIT(12)),
+	PINCTRL_CONF_DESC(25, REG_GPIO_L_E2, BIT(13)),
+	PINCTRL_CONF_DESC(26, REG_GPIO_L_E2, BIT(14)),
+	PINCTRL_CONF_DESC(27, REG_GPIO_L_E2, BIT(15)),
+	PINCTRL_CONF_DESC(28, REG_GPIO_L_E2, BIT(16)),
+	PINCTRL_CONF_DESC(29, REG_GPIO_L_E2, BIT(17)),
+	PINCTRL_CONF_DESC(30, REG_GPIO_L_E2, BIT(18)),
+	PINCTRL_CONF_DESC(31, REG_GPIO_L_E2, BIT(19)),
+	PINCTRL_CONF_DESC(32, REG_GPIO_L_E2, BIT(20)),
+	PINCTRL_CONF_DESC(33, REG_GPIO_L_E2, BIT(21)),
+	PINCTRL_CONF_DESC(34, REG_GPIO_L_E2, BIT(22)),
+	PINCTRL_CONF_DESC(35, REG_GPIO_L_E2, BIT(23)),
+	PINCTRL_CONF_DESC(36, REG_GPIO_L_E2, BIT(24)),
+	PINCTRL_CONF_DESC(37, REG_GPIO_L_E2, BIT(25)),
+	PINCTRL_CONF_DESC(38, REG_GPIO_L_E2, BIT(26)),
+	PINCTRL_CONF_DESC(39, REG_GPIO_L_E2, BIT(27)),
+	PINCTRL_CONF_DESC(40, REG_GPIO_L_E2, BIT(28)),
+	PINCTRL_CONF_DESC(41, REG_GPIO_L_E2, BIT(29)),
+};
+
+static const struct airoha_pinctrl_conf pinctrl_drive_e4_conf[] = {
+	PINCTRL_CONF_DESC(12, REG_GPIO_L_E4, BIT(0)),
+	PINCTRL_CONF_DESC(13, REG_GPIO_L_E4, BIT(1)),
+	PINCTRL_CONF_DESC(14, REG_GPIO_L_E4, BIT(2)),
+	PINCTRL_CONF_DESC(15, REG_GPIO_L_E4, BIT(3)),
+	PINCTRL_CONF_DESC(16, REG_GPIO_L_E4, BIT(4)),
+	PINCTRL_CONF_DESC(17, REG_GPIO_L_E4, BIT(5)),
+	PINCTRL_CONF_DESC(18, REG_GPIO_L_E4, BIT(6)),
+	PINCTRL_CONF_DESC(19, REG_GPIO_L_E4, BIT(7)),
+	PINCTRL_CONF_DESC(20, REG_GPIO_L_E4, BIT(8)),
+	PINCTRL_CONF_DESC(21, REG_GPIO_L_E4, BIT(9)),
+	PINCTRL_CONF_DESC(22, REG_GPIO_L_E4, BIT(10)),
+	PINCTRL_CONF_DESC(23, REG_GPIO_L_E4, BIT(11)),
+	PINCTRL_CONF_DESC(24, REG_GPIO_L_E4, BIT(12)),
+	PINCTRL_CONF_DESC(25, REG_GPIO_L_E4, BIT(13)),
+	PINCTRL_CONF_DESC(26, REG_GPIO_L_E4, BIT(14)),
+	PINCTRL_CONF_DESC(27, REG_GPIO_L_E4, BIT(15)),
+	PINCTRL_CONF_DESC(28, REG_GPIO_L_E4, BIT(16)),
+	PINCTRL_CONF_DESC(29, REG_GPIO_L_E4, BIT(17)),
+	PINCTRL_CONF_DESC(30, REG_GPIO_L_E4, BIT(18)),
+	PINCTRL_CONF_DESC(31, REG_GPIO_L_E4, BIT(19)),
+	PINCTRL_CONF_DESC(32, REG_GPIO_L_E4, BIT(20)),
+	PINCTRL_CONF_DESC(33, REG_GPIO_L_E4, BIT(21)),
+	PINCTRL_CONF_DESC(34, REG_GPIO_L_E4, BIT(22)),
+	PINCTRL_CONF_DESC(35, REG_GPIO_L_E4, BIT(23)),
+	PINCTRL_CONF_DESC(36, REG_GPIO_L_E4, BIT(24)),
+	PINCTRL_CONF_DESC(37, REG_GPIO_L_E4, BIT(25)),
+	PINCTRL_CONF_DESC(38, REG_GPIO_L_E4, BIT(26)),
+	PINCTRL_CONF_DESC(39, REG_GPIO_L_E4, BIT(27)),
+	PINCTRL_CONF_DESC(40, REG_GPIO_L_E4, BIT(28)),
+	PINCTRL_CONF_DESC(41, REG_GPIO_L_E4, BIT(29)),
+};
+
+static const struct airoha_pinctrl_match_data pinctrl_match_data = {
+	.pinctrl_name = KBUILD_MODNAME,
+	.pinctrl_owner = THIS_MODULE,
+	.pins = pinctrl_pins,
+	.num_pins = ARRAY_SIZE(pinctrl_pins),
+	.grps = pinctrl_groups,
+	.num_grps = ARRAY_SIZE(pinctrl_groups),
+	.funcs = pinctrl_funcs,
+	.num_funcs = ARRAY_SIZE(pinctrl_funcs),
+	.confs_info = {
+		[AIROHA_PINCTRL_CONFS_PULLUP] = {
+			.confs = pinctrl_pullup_conf,
+			.num_confs = ARRAY_SIZE(pinctrl_pullup_conf),
+		},
+		[AIROHA_PINCTRL_CONFS_PULLDOWN] = {
+			.confs = pinctrl_pulldown_conf,
+			.num_confs = ARRAY_SIZE(pinctrl_pulldown_conf),
+		},
+		[AIROHA_PINCTRL_CONFS_DRIVE_E2] = {
+			.confs = pinctrl_drive_e2_conf,
+			.num_confs = ARRAY_SIZE(pinctrl_drive_e2_conf),
+		},
+		[AIROHA_PINCTRL_CONFS_DRIVE_E4] = {
+			.confs = pinctrl_drive_e4_conf,
+			.num_confs = ARRAY_SIZE(pinctrl_drive_e4_conf),
+		},
+	},
+};
+
+static const struct of_device_id airoha_pinctrl_of_match[] = {
+	{ .compatible = "airoha,en7523-pinctrl", .data = &pinctrl_match_data },
+	{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, airoha_pinctrl_of_match);
+
+static struct platform_driver airoha_pinctrl_driver = {
+	.probe = airoha_pinctrl_probe,
+	.driver = {
+		.name = "pinctrl-airoha-en7523",
+		.of_match_table = airoha_pinctrl_of_match,
+	},
+};
+module_platform_driver(airoha_pinctrl_driver);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Lorenzo Bianconi <lorenzo@kernel.org>");
+MODULE_AUTHOR("Benjamin Larsson <benjamin.larsson@genexis.eu>");
+MODULE_AUTHOR("Markus Gothe <markus.gothe@genexis.eu>");
+MODULE_AUTHOR("Matheus Sampaio Queiroga <srherobrine20@gmail.com>");
+MODULE_AUTHOR("Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>");
+MODULE_DESCRIPTION("Pinctrl driver for Airoha EN7523 SoC");
-- 
2.53.0

Re: [PATCH v7 30/34] pinctrl: airoha: add support of en7523 SoC

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider:

New issues:
- [Medium] Missing hardware configuration for dedicated non-GPIO and PCIe reset pins
- [Low] Dead code: Unused macro definitions

Pre-existing issues:
- [High] Driver probe failure due to hardcoded EN7581 syscon dependency
--

--- Patch [30]: [PATCH v7 30/34] pinctrl: airoha: add support of en7523 SoC ---
commit cb202b59244d84caae5e01de5b50036f419bfc6e
Author: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
Subject: pinctrl: airoha: add support of en7523 SoC

This patch adds support of Airoha en7523 SoC pin controller.

> diff --git a/drivers/pinctrl/airoha/pinctrl-en7523.c b/drivers/pinctrl/airoha/pinctrl-en7523.c
> new file mode 100644
> --- /dev/null
> +++ b/drivers/pinctrl/airoha/pinctrl-en7523.c
> @@ -0,0 +1,1124 @@

[ ... ]

> +#define REG_NPU_UART_EN				0x0220
> +#define JTAG_UDI_EN_MASK			BIT(4)
> +#define JTAG_DFD_EN_MASK			BIT(3)
> +#define NPU_UART_EN_MASK			BIT(2)
> +
> +#define REG_FORCE_GPIO_EN			0x0224
> +#define FORCE_GPIO_EN(n)			BIT(n)
> +
> +/* LED MAP */

[Severity: Low]
Are these register definitions for REG_FORCE_GPIO_EN and FORCE_GPIO_EN
utilized anywhere in this file? They seem to be defined here but never
mapped or used. Is this leftover code from another SoC driver?

[ ... ]

> +#define AIROHA_PINCTRL_GPIO(gpio, mux_val)			\
> +	{							\
> +		.name = (gpio),					\
> +		.regmap[0] = {					\
> +			AIROHA_FUNC_MUX,			\
> +			REG_GPIO_PON_MODE,			\
> +			(mux_val),				\
> +			(mux_val)				\
> +		},						\
> +		.regmap_size = 1,				\
> +	}
> +
> +#define AIROHA_PINCTRL_GPIO_EXT(gpio, mux_val, smux_val)	\

[Severity: Low]
Is the AIROHA_PINCTRL_GPIO macro needed? It appears only
AIROHA_PINCTRL_GPIO_EXT is used below in gpio_func_group.

[ ... ]

> +static const struct airoha_pinctrl_conf pinctrl_pullup_conf[] = {
> +	PINCTRL_CONF_DESC(12, REG_GPIO_L_PU, BIT(0)),
> +	PINCTRL_CONF_DESC(13, REG_GPIO_L_PU, BIT(1)),

[Severity: Medium]
Should pins 2 through 9 be included in this configuration array?

The driver defines registers and bitmasks for configuring pull-up, pull-down,
and drive strength for these dedicated I2C, SPI, and UART pins (like
REG_I2C_SDA_PU), but they appear to be entirely missing from the
pinctrl_pullup_conf, pinctrl_pulldown_conf, pinctrl_drive_e2_conf, and
pinctrl_drive_e4_conf arrays.

Will device tree properties attempting to configure these electrical
characteristics fail?

[ ... ]

> +	PINCTRL_CONF_DESC(38, REG_GPIO_L_PU, BIT(26)),
> +	PINCTRL_CONF_DESC(39, REG_GPIO_L_PU, BIT(27)),
> +	PINCTRL_CONF_DESC(40, REG_GPIO_L_PU, BIT(28)),
> +	PINCTRL_CONF_DESC(41, REG_GPIO_L_PU, BIT(29)),
> +};

[Severity: Medium]
Are pins 40 and 41 correctly mapped here?

They are mapped to REG_GPIO_L_PU bits 28 and 29, but earlier in the file
PCIE0_RESET_PU_MASK and PCIE1_RESET_PU_MASK are defined as bits 8 and 9 of
REG_I2C_SDA_PU.

Will configuring the PCIe resets write to the wrong register?

[ ... ]

> +static struct platform_driver airoha_pinctrl_driver = {
> +	.probe = airoha_pinctrl_probe,
> +	.driver = {
> +		.name = "pinctrl-airoha-en7523",
> +		.of_match_table = airoha_pinctrl_of_match,
> +	},
> +};
> +module_platform_driver(airoha_pinctrl_driver);

[Severity: High]
This is a pre-existing issue, but will this driver successfully probe on
EN7523 hardware?

The core function airoha_pinctrl_probe() appears to unconditionally look up
the system controller using syscon_regmap_lookup_by_compatible() with the
hardcoded string "airoha,en7581-chip-scu". Since the EN7523 device tree
likely uses its own compatible string, won't this lookup fail and cause the
probe function to return -ENODEV?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260727074234.3761170-1-mikhail.kshevetskiy@iopsys.eu?part=30

[PATCH v7 31/34] pinctrl: airoha: try to find chip scu node by phandle first

[Mikhail Kshevetskiy]

The "airoha,en7581-chip-scu" is not a good compatible string in the en7523
case. Let's search chip scu regmap with "airoha,chip-scu" phangle first
and fallback to SoC specific chip scu compatible string on failure.

Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
---
 drivers/pinctrl/airoha/airoha-common.h  | 1 +
 drivers/pinctrl/airoha/pinctrl-airoha.c | 9 ++++++---
 drivers/pinctrl/airoha/pinctrl-an7581.c | 1 +
 drivers/pinctrl/airoha/pinctrl-an7583.c | 1 +
 drivers/pinctrl/airoha/pinctrl-en7523.c | 1 +
 5 files changed, 10 insertions(+), 3 deletions(-)

diff --git a/drivers/pinctrl/airoha/airoha-common.h b/drivers/pinctrl/airoha/airoha-common.h
index f73e90ca860f4..d8555cf32786b 100644
--- a/drivers/pinctrl/airoha/airoha-common.h
+++ b/drivers/pinctrl/airoha/airoha-common.h
@@ -152,6 +152,7 @@ struct airoha_pinctrl {
 };
 
 struct airoha_pinctrl_match_data {
+	const char *chip_scu_compatible;
 	const char *pinctrl_name;
 	struct module *pinctrl_owner;
 	const struct pinctrl_pin_desc *pins;
diff --git a/drivers/pinctrl/airoha/pinctrl-airoha.c b/drivers/pinctrl/airoha/pinctrl-airoha.c
index a46596eb1493b..0fd9457afc501 100644
--- a/drivers/pinctrl/airoha/pinctrl-airoha.c
+++ b/drivers/pinctrl/airoha/pinctrl-airoha.c
@@ -746,9 +746,12 @@ int airoha_pinctrl_probe(struct platform_device *pdev)
 	if (IS_ERR(pinctrl->regmap))
 		return PTR_ERR(pinctrl->regmap);
 
-	map = syscon_regmap_lookup_by_compatible("airoha,en7581-chip-scu");
-	if (IS_ERR(map))
-		return PTR_ERR(map);
+	map = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, "airoha,chip-scu");
+	if (IS_ERR_OR_NULL(map)) {
+		map = syscon_regmap_lookup_by_compatible(data->chip_scu_compatible);
+		if (IS_ERR(map))
+			return PTR_ERR(map);
+	}
 
 	pinctrl->chip_scu = map;
 
diff --git a/drivers/pinctrl/airoha/pinctrl-an7581.c b/drivers/pinctrl/airoha/pinctrl-an7581.c
index 6e53143e91d70..6d6c5f1ee5d23 100644
--- a/drivers/pinctrl/airoha/pinctrl-an7581.c
+++ b/drivers/pinctrl/airoha/pinctrl-an7581.c
@@ -1432,6 +1432,7 @@ static const struct airoha_pinctrl_conf pinctrl_pcie_rst_od_conf[] = {
 };
 
 static const struct airoha_pinctrl_match_data pinctrl_match_data = {
+	.chip_scu_compatible = "airoha,en7581-chip-scu",
 	.pinctrl_name = KBUILD_MODNAME,
 	.pinctrl_owner = THIS_MODULE,
 	.pins = pinctrl_pins,
diff --git a/drivers/pinctrl/airoha/pinctrl-an7583.c b/drivers/pinctrl/airoha/pinctrl-an7583.c
index 74f93327d41a1..6d3ef32acf627 100644
--- a/drivers/pinctrl/airoha/pinctrl-an7583.c
+++ b/drivers/pinctrl/airoha/pinctrl-an7583.c
@@ -1442,6 +1442,7 @@ static const struct airoha_pinctrl_conf pinctrl_pcie_rst_od_conf[] = {
 };
 
 static const struct airoha_pinctrl_match_data pinctrl_match_data = {
+	.chip_scu_compatible = "airoha,en7581-chip-scu",
 	.pinctrl_name = KBUILD_MODNAME,
 	.pinctrl_owner = THIS_MODULE,
 	.pins = pinctrl_pins,
diff --git a/drivers/pinctrl/airoha/pinctrl-en7523.c b/drivers/pinctrl/airoha/pinctrl-en7523.c
index 7f434c9bce923..a6202f6313d5b 100644
--- a/drivers/pinctrl/airoha/pinctrl-en7523.c
+++ b/drivers/pinctrl/airoha/pinctrl-en7523.c
@@ -1072,6 +1072,7 @@ static const struct airoha_pinctrl_conf pinctrl_drive_e4_conf[] = {
 };
 
 static const struct airoha_pinctrl_match_data pinctrl_match_data = {
+	.chip_scu_compatible = "airoha,en7523-chip-scu",
 	.pinctrl_name = KBUILD_MODNAME,
 	.pinctrl_owner = THIS_MODULE,
 	.pins = pinctrl_pins,
-- 
2.53.0

Re: [PATCH v7 31/34] pinctrl: airoha: try to find chip scu node by phandle first

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] The fallback logic unconditionally catches all errors from `syscon_regmap_lookup_by_phandle()` (including `-EPROBE_DEFER` and `-ENOMEM`), which can mask critical errors by overwriting them with permanent `-ENODEV` failures.
--

--- Patch [31]: [PATCH v7 31/34] pinctrl: airoha: try to find chip scu node by phandle first ---
commit bdb88d3420346c0c992b6bccf51e7ae7eb4e0a9a
Author: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>

pinctrl: airoha: try to find chip scu node by phandle first

This patch updates the probe function to first search for the chip SCU regmap
using the airoha,chip-scu phandle. If that fails, it falls back to searching
by a SoC-specific compatible string to maintain compatibility across different
chip variants.

> diff --git a/drivers/pinctrl/airoha/pinctrl-airoha.c b/drivers/pinctrl/airoha/pinctrl-airoha.c
> index a671d34b334eb..460010c001eb2 100644
> --- a/drivers/pinctrl/airoha/pinctrl-airoha.c
> +++ b/drivers/pinctrl/airoha/pinctrl-airoha.c
> @@ -748,9 +748,12 @@ int airoha_pinctrl_probe(struct platform_device *pdev)
>  	if (IS_ERR(pinctrl->regmap))
>  		return PTR_ERR(pinctrl->regmap);
>  
> -	map = syscon_regmap_lookup_by_compatible("airoha,en7581-chip-scu");
> -	if (IS_ERR(map))
> -		return PTR_ERR(map);
> +	map = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, "airoha,chip-scu");
> +	if (IS_ERR_OR_NULL(map)) {

[Severity: High]
Does this error check unintentionally mask -EPROBE_DEFER?

If the device tree uses the modern phandle binding but the SCU syscon is not
ready, syscon_regmap_lookup_by_phandle() returns -EPROBE_DEFER.

Because this check unconditionally catches all errors, it will fall back to
syscon_regmap_lookup_by_compatible(). If the legacy compatible string isn't
present in the device tree, that fallback returns -ENODEV, which overwrites
the original -EPROBE_DEFER and causes a permanent probe failure instead of
deferring.

Should the fallback only be executed if the initial lookup returns -ENODEV?

> +		map = syscon_regmap_lookup_by_compatible(data->chip_scu_compatible);
> +		if (IS_ERR(map))
> +			return PTR_ERR(map);
> +	}
>  
>  	pinctrl->chip_scu = map;
>

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260727074234.3761170-1-mikhail.kshevetskiy@iopsys.eu?part=31

[PATCH v7 32/34] dt-bindings: pinctrl: airoha: add support of en7523 pin controller

[Mikhail Kshevetskiy]

This patch adds device tree binding schema for Airoha EN7523 SoC pin
controller.

Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
---
 .../pinctrl/airoha,en7523-pinctrl.yaml        | 375 ++++++++++++++++++
 1 file changed, 375 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/airoha,en7523-pinctrl.yaml

diff --git a/Documentation/devicetree/bindings/pinctrl/airoha,en7523-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/airoha,en7523-pinctrl.yaml
new file mode 100644
index 0000000000000..db8e39af1a152
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/airoha,en7523-pinctrl.yaml
@@ -0,0 +1,375 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/airoha,en7523-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Airoha EN7523 Pin Controller
+
+maintainers:
+  - Lorenzo Bianconi <lorenzo@kernel.org>
+
+description:
+  The Airoha's EN7523 Pin controller is used to control SoC pins.
+
+properties:
+  compatible:
+    const: airoha,en7523-pinctrl
+
+  interrupts:
+    maxItems: 1
+
+  gpio-controller: true
+
+  '#gpio-cells':
+    const: 2
+
+  gpio-ranges:
+    maxItems: 1
+
+  interrupt-controller: true
+
+  '#interrupt-cells':
+    const: 2
+
+allOf:
+  - $ref: pinctrl.yaml#
+
+required:
+  - compatible
+  - interrupts
+  - gpio-controller
+  - "#gpio-cells"
+  - interrupt-controller
+  - "#interrupt-cells"
+
+patternProperties:
+  '-pins$':
+    type: object
+
+    patternProperties:
+      '^mux(-|$)':
+        type: object
+
+        description:
+          pinmux configuration nodes.
+
+        $ref: /schemas/pinctrl/pinmux-node.yaml
+
+        properties:
+          function:
+            description:
+              A string containing the name of the function to mux to the group.
+            enum: [pon, tod_1pps, sipo, mdio, uart, i2c, jtag, pcm, spi,
+                   pcm_spi, i2s, gpio, pcie_reset, pwm, phy1_led0,
+                   phy2_led0, phy3_led0, phy4_led0, phy1_led1, phy2_led1,
+                   phy3_led1, phy4_led1]
+
+          groups:
+            description:
+              An array of strings. Each string contains the name of a group.
+
+        required:
+          - function
+          - groups
+
+        allOf:
+          - if:
+              properties:
+                function:
+                  const: pon
+            then:
+              properties:
+                groups:
+                  enum: [pon]
+          - if:
+              properties:
+                function:
+                  const: tod_1pps
+            then:
+              properties:
+                groups:
+                  enum: [pon_tod_1pps, gsw_tod_1pps]
+          - if:
+              properties:
+                function:
+                  const: sipo
+            then:
+              properties:
+                groups:
+                  enum: [sipo, sipo_rclk]
+          - if:
+              properties:
+                function:
+                  const: mdio
+            then:
+              properties:
+                groups:
+                  enum: [mdio]
+          - if:
+              properties:
+                function:
+                  const: uart
+            then:
+              properties:
+                groups:
+                  items:
+                    enum: [uart2, npu_uart]
+                  maxItems: 2
+          - if:
+              properties:
+                function:
+                  const: i2c
+            then:
+              properties:
+                groups:
+                  enum: [i2c1]
+          - if:
+              properties:
+                function:
+                  const: jtag
+            then:
+              properties:
+                groups:
+                  enum: [jtag_udi, jtag_dfd]
+          - if:
+              properties:
+                function:
+                  const: pcm
+            then:
+              properties:
+                groups:
+                  enum: [pcm1, pcm2]
+          - if:
+              properties:
+                function:
+                  const: spi
+            then:
+              properties:
+                groups:
+                  items:
+                    enum: [spi_quad, spi_cs1]
+                  maxItems: 2
+          - if:
+              properties:
+                function:
+                  const: pcm_spi
+            then:
+              properties:
+                groups:
+                  items:
+                    enum: [pcm_spi, pcm_spi_int, pcm_spi_rst, pcm_spi_cs1,
+                           pcm_spi_cs2_p156, pcm_spi_cs2_p128, pcm_spi_cs3,
+                           pcm_spi_cs4]
+                  maxItems: 7
+          - if:
+              properties:
+                function:
+                  const: i2s
+            then:
+              properties:
+                groups:
+                  enum: [i2s]
+          - if:
+              properties:
+                function:
+                  const: gpio
+            then:
+              properties:
+                groups:
+                  enum: [gpio28, gpio29]
+          - if:
+              properties:
+                function:
+                  const: pcie_reset
+            then:
+              properties:
+                groups:
+                  enum: [pcie_reset0, pcie_reset1]
+          - if:
+              properties:
+                function:
+                  const: pwm
+            then:
+              properties:
+                groups:
+                  enum: [gpio0, gpio1, gpio2, gpio3, gpio4, gpio5, gpio6,
+                         gpio7, gpio8, gpio9, gpio10, gpio11, gpio12, gpio13,
+                         gpio14, gpio15, gpio16, gpio17, gpio18, gpio19,
+                         gpio20, gpio21, gpio22, gpio23, gpio24, gpio25,
+                         gpio26, gpio27, gpio28, gpio29]
+          - if:
+              properties:
+                function:
+                  const: phy1_led0
+            then:
+              properties:
+                groups:
+                  enum: [gpio22, gpio23, gpio24, gpio25]
+          - if:
+              properties:
+                function:
+                  const: phy2_led0
+            then:
+              properties:
+                groups:
+                  enum: [gpio22, gpio23, gpio24, gpio25]
+          - if:
+              properties:
+                function:
+                  const: phy3_led0
+            then:
+              properties:
+                groups:
+                  enum: [gpio22, gpio23, gpio24, gpio25]
+          - if:
+              properties:
+                function:
+                  const: phy4_led0
+            then:
+              properties:
+                groups:
+                  enum: [gpio22, gpio23, gpio24, gpio25]
+          - if:
+              properties:
+                function:
+                  const: phy1_led1
+            then:
+              properties:
+                groups:
+                  enum: [gpio7, gpio6, gpio5, gpio4]
+          - if:
+              properties:
+                function:
+                  const: phy2_led1
+            then:
+              properties:
+                groups:
+                  enum: [gpio7, gpio6, gpio5, gpio4]
+          - if:
+              properties:
+                function:
+                  const: phy3_led1
+            then:
+              properties:
+                groups:
+                  enum: [gpio7, gpio6, gpio5, gpio4]
+          - if:
+              properties:
+                function:
+                  const: phy4_led1
+            then:
+              properties:
+                groups:
+                  enum: [gpio7, gpio6, gpio5, gpio4]
+
+        additionalProperties: false
+
+      '^conf(-|$)':
+        type: object
+
+        description:
+          pinconf configuration nodes.
+
+        $ref: /schemas/pinctrl/pincfg-node.yaml
+
+        properties:
+          pins:
+            description:
+              An array of strings. Each string contains the name of a pin.
+            items:
+              enum: [i2c_sda, i2c_scl, spi_cs0, spi_clk, spi_mosi, spi_miso,
+                     uart1_txd, uart1_rxd, gpio0, gpio1, gpio2, gpio3, gpio4,
+                     gpio5, gpio6, gpio7, gpio8, gpio9, gpio10, gpio11, gpio12,
+                     gpio13, gpio14, gpio15, gpio16, gpio17, gpio18, gpio19,
+                     gpio20, gpio21, gpio22, gpio23, gpio24, gpio25, gpio26,
+                     gpio27, pcie_reset0, pcie_reset1]
+            minItems: 1
+            maxItems: 38
+
+          bias-disable: true
+
+          bias-pull-up: true
+
+          bias-pull-down: true
+
+          input-enable: true
+
+          output-enable: true
+
+          output-low: true
+
+          output-high: true
+
+          drive-open-drain: true
+
+          drive-strength:
+            description:
+              Selects the drive strength for MIO pins, in mA.
+            enum: [2, 4, 6, 8]
+
+        required:
+          - pins
+
+        additionalProperties: false
+
+    additionalProperties: false
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+    pinctrl {
+      compatible = "airoha,en7523-pinctrl";
+
+      interrupt-parent = <&gic>;
+      interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+
+      gpio-controller;
+      #gpio-cells = <2>;
+
+      interrupt-controller;
+      #interrupt-cells = <2>;
+
+      pcie1-rst-pins {
+        conf {
+          pins = "pcie_reset1";
+          drive-open-drain = <1>;
+        };
+      };
+
+      pwm-pins {
+        mux {
+          function = "pwm";
+          groups = "gpio18";
+        };
+      };
+
+      spi-pins {
+        mux {
+          function = "spi";
+          groups = "spi_quad", "spi_cs1";
+        };
+      };
+
+      uart2-pins {
+        mux {
+          function = "uart";
+          groups = "uart2";
+        };
+      };
+
+      mdio-pins {
+        mux {
+          function = "mdio";
+          groups = "mdio";
+        };
+
+        conf {
+          pins = "gpio2";
+          output-enable;
+        };
+      };
+    };
-- 
2.53.0

Re: [PATCH v7 32/34] dt-bindings: pinctrl: airoha: add support of en7523 pin controller

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 5 potential issue(s) to consider:
- [Medium] The binding schema is missing the 'airoha,chip-scu' phandle property, which is explicitly parsed by the pinctrl driver.
- [Medium] The dt-binding example misleadingly presents the pinctrl node as a standalone top-level device, which will cause probe failure due to a missing parent regmap.
- [Medium] The 'groups' property constraints in the 'allOf' conditionals incorrectly use 'enum' instead of 'items: enum' for single-item arrays, which will cause valid device trees to fail dt-schema validation.
- [Medium] The top-level schema incorrectly uses 'additionalProperties: false' instead of 'unevaluatedProperties: false' when including a reference to 'pinctrl.yaml#'.
- [Low] The example node incorrectly assigns an integer value to the boolean property 'drive-open-drain'.
--

--- Patch [32]: [PATCH v7 32/34] dt-bindings: pinctrl: airoha: add support of en7523 pin controller ---
commit 995063565828879967b4a8fd673a347a158aa81e
Author: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>

dt-bindings: pinctrl: airoha: add support of en7523 pin controller

This patch adds device tree binding schema for Airoha EN7523 SoC pin
controller.

> diff --git a/Documentation/devicetree/bindings/pinctrl/airoha,en7523-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/airoha,en7523-pinctrl.yaml
> new file mode 100644
> index 0000000000000..db8e39af1a152
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pinctrl/airoha,en7523-pinctrl.yaml
> @@ -0,0 +1,375 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pinctrl/airoha,en7523-pinctrl.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Airoha EN7523 Pin Controller
> +
> +maintainers:
> +  - Lorenzo Bianconi <lorenzo@kernel.org>
> +
> +description:
> +  The Airoha's EN7523 Pin controller is used to control SoC pins.
> +
> +properties:
> +  compatible:
> +    const: airoha,en7523-pinctrl

[Severity: Medium]
Should the airoha,chip-scu property be documented here as well?

If a device tree includes the airoha,chip-scu phandle, which the driver
specifically looks for via syscon_regmap_lookup_by_phandle(), it will fail
validation because the property is completely undocumented in this schema.

[ ... ]

> +          - if:
> +              properties:
> +                function:
> +                  const: pwm
> +            then:
> +              properties:
> +                groups:
> +                  enum: [gpio0, gpio1, gpio2, gpio3, gpio4, gpio5, gpio6,
> +                         gpio7, gpio8, gpio9, gpio10, gpio11, gpio12, gpio13,

[Severity: Medium]
Could this cause validation failures for valid device trees?

It looks like groups is constrained using enum instead of items: enum for
single-item arrays. Because device tree string-arrays are evaluated as arrays,
using enum for a scalar string expectation might cause dt_binding_check to
reject legitimate configurations like pwm or pon functions. Is this same
pattern present in the other conditionals?

[ ... ]

> +    additionalProperties: false
> +
> +additionalProperties: false

[Severity: Medium]
Will this top-level directive reject standard pinctrl properties?

Since the schema includes a reference to pinctrl.yaml# in its allOf block,
using additionalProperties: false instead of unevaluatedProperties: false
might cause the schema to reject standard properties like pinctrl-0 or
pinctrl-names on the provider node.

> +
> +examples:
> +  - |
> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +    pinctrl {
> +      compatible = "airoha,en7523-pinctrl";

[Severity: Medium]
Would placing the pinctrl node at the top level without a parent syscon cause
probe failures?

The driver relies on device_node_to_regmap(dev->parent->of_node) during probe.
If users copy this example and place the pinctrl node directly under the root
bus, it appears the driver will fail to find the parent regmap.

[ ... ]

> +      pcie1-rst-pins {
> +        conf {
> +          pins = "pcie_reset1";
> +          drive-open-drain = <1>;

[Severity: Low]
Does assigning an integer value to drive-open-drain violate the core schema?

The core pincfg-node.yaml schema expects boolean properties to be present
without an assigned value, but the <1> assignment creates an integer array.

> +        };
> +      };

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260727074234.3761170-1-mikhail.kshevetskiy@iopsys.eu?part=32

[PATCH v7 33/34] pinctrl: airoha: add support of an7563 SoC

[Mikhail Kshevetskiy]

This patch adds support of Airoha an7563 SoC pin controller.

Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
---
 drivers/pinctrl/airoha/Kconfig          |    9 +
 drivers/pinctrl/airoha/Makefile         |    1 +
 drivers/pinctrl/airoha/pinctrl-an7563.c | 1115 +++++++++++++++++++++++
 3 files changed, 1125 insertions(+)
 create mode 100644 drivers/pinctrl/airoha/pinctrl-an7563.c

diff --git a/drivers/pinctrl/airoha/Kconfig b/drivers/pinctrl/airoha/Kconfig
index 363d6b7ff906f..22b8f850cee1c 100644
--- a/drivers/pinctrl/airoha/Kconfig
+++ b/drivers/pinctrl/airoha/Kconfig
@@ -13,6 +13,7 @@ config PINCTRL_AIROHA
 	select GPIOLIB
 	select GPIOLIB_IRQCHIP
 	select REGMAP_MMIO
+	imply PINCTRL_AIROHA_AN7563
 	imply PINCTRL_AIROHA_AN7581
 	imply PINCTRL_AIROHA_AN7583
 	imply PINCTRL_AIROHA_EN7523
@@ -20,6 +21,14 @@ config PINCTRL_AIROHA
 	  Shared pin controller and gpio driver code for different
 	  Airoha SoCs.
 
+config PINCTRL_AIROHA_AN7563
+	tristate "AN7563 pinctrl"
+	depends on ARM64 || COMPILE_TEST
+	depends on PINCTRL_AIROHA
+	help
+	  Say yes here to support pin controller and gpio driver
+	  on Airoha AN7563 and other compatible SoCs.
+
 config PINCTRL_AIROHA_AN7581
 	tristate "AN7581 pinctrl"
 	depends on ARM64 || COMPILE_TEST
diff --git a/drivers/pinctrl/airoha/Makefile b/drivers/pinctrl/airoha/Makefile
index 8b9202321ba86..30e4bee57a4a1 100644
--- a/drivers/pinctrl/airoha/Makefile
+++ b/drivers/pinctrl/airoha/Makefile
@@ -4,6 +4,7 @@
 obj-$(CONFIG_PINCTRL_AIROHA)		+= pinctrl-airoha.o
 
 # SoC drivers
+obj-$(CONFIG_PINCTRL_AIROHA_AN7563)	+= pinctrl-an7563.o
 obj-$(CONFIG_PINCTRL_AIROHA_AN7581)	+= pinctrl-an7581.o
 obj-$(CONFIG_PINCTRL_AIROHA_AN7583)	+= pinctrl-an7583.o
 obj-$(CONFIG_PINCTRL_AIROHA_EN7523)	+= pinctrl-en7523.o
diff --git a/drivers/pinctrl/airoha/pinctrl-an7563.c b/drivers/pinctrl/airoha/pinctrl-an7563.c
new file mode 100644
index 0000000000000..40cbbe90cc464
--- /dev/null
+++ b/drivers/pinctrl/airoha/pinctrl-an7563.c
@@ -0,0 +1,1115 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * AN7563 SoC pinctrl data for the Airoha pinctrl driver (pinctrl-airoha.c).
+ *
+ * Sources: AN7563 Programming Guide chapter 2 (CHIP SCU, base 0x1fa20000),
+ * chapter 17 (GPIO controller, base 0x1fbf0200) and AN7563PT datasheet
+ * chapter 4.3 (pin sharing scheme).
+ *
+ * Pin numbering follows the GPIO line numbering of the SoC:
+ *   pins  0-27 -> GPIO0-GPIO27 (dedicated GPIO pads)
+ *   pins 28/29 -> PCIE_RESET0/PCIE_RESET1 pads (GPIO28/GPIO29)
+ *   pins 30/31 -> I2C_SCL/I2C_SDA pads (GPIO30/GPIO31)
+ *   pins 32-35 -> SPI_CLK/SPI_CS/SPI_MOSI/SPI_MISO pads (GPIO32-GPIO35)
+ *   pins 36/37 -> UART_TXD/UART_RXD pads (GPIO36/GPIO37)
+ *
+ * Definitions marked "shared" are identical to the ones already present in
+ * pinctrl-airoha.c (EN7581/AN7583) and must be dropped when this data is
+ * merged there.
+ */
+
+#include "airoha-common.h"
+
+/*
+ * shared - named RG_SW_TOD_1PPS_MODE on AN7563. Only the LAN LED mode
+ * bits and GSW_TOD_1PPS exist on AN7563 (no 2nd I2C, I2S or PON 1PPS).
+ */
+#define REG_GPIO_2ND_I2C_MODE			0x0214
+#define GPIO_LAN3_LED1_MODE_MASK		BIT(10)
+#define GPIO_LAN3_LED0_MODE_MASK		BIT(9)
+#define GPIO_LAN2_LED1_MODE_MASK		BIT(8)
+#define GPIO_LAN2_LED0_MODE_MASK		BIT(7)
+#define GPIO_LAN1_LED1_MODE_MASK		BIT(6)
+#define GPIO_LAN1_LED0_MODE_MASK		BIT(5)
+#define GPIO_LAN0_LED1_MODE_MASK		BIT(4)
+#define GPIO_LAN0_LED0_MODE_MASK		BIT(3)
+#define GSW_TOD_1PPS_MODE_MASK			BIT(1)
+
+/* shared */
+#define REG_GPIO_SPI_CS1_MODE			0x0218
+#define GPIO_PCM_SPI_CS4_MODE_MASK		BIT(21)
+#define GPIO_PCM_SPI_CS3_MODE_MASK		BIT(20)
+#define GPIO_PCM_SPI_CS2_MODE_MASK		BIT(18)
+#define GPIO_PCM_SPI_CS1_MODE_MASK		BIT(17)
+#define GPIO_PCM_SPI_MODE_MASK			BIT(16)
+#define GPIO_PCM2_MODE_MASK			BIT(13)
+#define GPIO_PCM1_MODE_MASK			BIT(12)
+#define GPIO_PCM_INT_MODE_MASK			BIT(9)
+#define GPIO_PCM_RESET_MODE_MASK		BIT(8)
+#define GPIO_SPI_QUAD_MODE_MASK			BIT(4)
+#define GPIO_SPI_CS4_MODE_MASK			BIT(3)
+#define GPIO_SPI_CS3_MODE_MASK			BIT(2)
+#define GPIO_SPI_CS2_MODE_MASK			BIT(1)
+#define GPIO_SPI_CS1_MODE_MASK			BIT(0)
+
+#define REG_GPIO_PON_MODE			0x021c
+/*
+ * AN7563 specific: route the standalone pads to their GPIO function.
+ * 0: pad keeps its base function, 1: pad is GPIO<n>.
+ */
+#define UART_RXD_GPIO_MODE_MASK			BIT(22)	/* GPIO37 */
+#define UART_TXD_GPIO_MODE_MASK			BIT(21)	/* GPIO36 */
+#define SPI_MISO_GPIO_MODE_MASK			BIT(20)	/* GPIO35 */
+#define SPI_MOSI_GPIO_MODE_MASK			BIT(19)	/* GPIO34 */
+#define SPI_CS_GPIO_MODE_MASK			BIT(18)	/* GPIO33 */
+#define SPI_CLK_GPIO_MODE_MASK			BIT(17)	/* GPIO32 */
+#define I2C_SDA_GPIO_MODE_MASK			BIT(16)	/* GPIO31 */
+#define I2C_SCL_GPIO_MODE_MASK			BIT(15)	/* GPIO30 */
+/* shared */
+#define GPIO_PARALLEL_NAND_MODE_MASK		BIT(14)
+#define GPIO_SGMII_MDIO_MODE_MASK		BIT(13)
+#define SIPO_RCLK_MODE_MASK			BIT(11)
+/*
+ * Note: on AN7563 GPIO_PCIE_RESET{0,1} select the GPIO function of the
+ * PCIE_RESET pads (0: PCIe reset, 1: GPIO28/GPIO29).
+ */
+#define GPIO_PCIE_RESET1_MASK			BIT(10)	/* GPIO29 */
+#define GPIO_PCIE_RESET0_MASK			BIT(9)	/* GPIO28 */
+#define GPIO_HSUART_CTS_RTS_MODE_MASK		BIT(6)
+#define GPIO_HSUART_MODE_MASK			BIT(5)
+#define GPIO_SIPO_MODE_MASK			BIT(2)
+#define GPIO_PON_MODE_MASK			BIT(0)
+
+/* shared */
+#define REG_NPU_UART_EN				0x0224
+#define JTAG_UDI_EN_MASK			BIT(4)
+#define JTAG_DFD_EN_MASK			BIT(3)
+
+/* LED MAP - shared */
+#define REG_LAN_LED0_MAPPING			0x027c
+#define REG_LAN_LED1_MAPPING			0x0280
+
+#define LAN3_LED_MAPPING_MASK			GENMASK(14, 12)
+#define LAN3_PHY_LED_MAP(_n)			FIELD_PREP_CONST(LAN3_LED_MAPPING_MASK, (_n))
+
+#define LAN2_LED_MAPPING_MASK			GENMASK(10, 8)
+#define LAN2_PHY_LED_MAP(_n)			FIELD_PREP_CONST(LAN2_LED_MAPPING_MASK, (_n))
+
+#define LAN1_LED_MAPPING_MASK			GENMASK(6, 4)
+#define LAN1_PHY_LED_MAP(_n)			FIELD_PREP_CONST(LAN1_LED_MAPPING_MASK, (_n))
+
+#define LAN0_LED_MAPPING_MASK			GENMASK(2, 0)
+#define LAN0_PHY_LED_MAP(_n)			FIELD_PREP_CONST(LAN0_LED_MAPPING_MASK, (_n))
+
+/*
+ * CONF - shared.
+ * The AN7563 standalone IO conf registers use the same bit layout as
+ * EN7581 (UART1_TXD/RXD are named UART_TXD/RXD on AN7563).
+ */
+#define REG_I2C_SDA_E2				0x001c
+#define SPI_MISO_E2_MASK			BIT(14)
+#define SPI_MOSI_E2_MASK			BIT(13)
+#define SPI_CLK_E2_MASK				BIT(12)
+#define SPI_CS0_E2_MASK				BIT(11)
+#define PCIE1_RESET_E2_MASK			BIT(9)
+#define PCIE0_RESET_E2_MASK			BIT(8)
+#define UART1_RXD_E2_MASK			BIT(3)
+#define UART1_TXD_E2_MASK			BIT(2)
+#define I2C_SCL_E2_MASK				BIT(1)
+#define I2C_SDA_E2_MASK				BIT(0)
+
+#define REG_I2C_SDA_E4				0x0020
+#define SPI_MISO_E4_MASK			BIT(14)
+#define SPI_MOSI_E4_MASK			BIT(13)
+#define SPI_CLK_E4_MASK				BIT(12)
+#define SPI_CS0_E4_MASK				BIT(11)
+#define PCIE1_RESET_E4_MASK			BIT(9)
+#define PCIE0_RESET_E4_MASK			BIT(8)
+#define UART1_RXD_E4_MASK			BIT(3)
+#define UART1_TXD_E4_MASK			BIT(2)
+#define I2C_SCL_E4_MASK				BIT(1)
+#define I2C_SDA_E4_MASK				BIT(0)
+
+#define REG_GPIO_L_E2				0x0024
+#define REG_GPIO_L_E4				0x0028
+
+#define REG_I2C_SDA_PU				0x0044
+#define SPI_MISO_PU_MASK			BIT(14)
+#define SPI_MOSI_PU_MASK			BIT(13)
+#define SPI_CLK_PU_MASK				BIT(12)
+#define SPI_CS0_PU_MASK				BIT(11)
+#define PCIE1_RESET_PU_MASK			BIT(9)
+#define PCIE0_RESET_PU_MASK			BIT(8)
+#define UART1_RXD_PU_MASK			BIT(3)
+#define UART1_TXD_PU_MASK			BIT(2)
+#define I2C_SCL_PU_MASK				BIT(1)
+#define I2C_SDA_PU_MASK				BIT(0)
+
+#define REG_I2C_SDA_PD				0x0048
+#define SPI_MISO_PD_MASK			BIT(14)
+#define SPI_MOSI_PD_MASK			BIT(13)
+#define SPI_CLK_PD_MASK				BIT(12)
+#define SPI_CS0_PD_MASK				BIT(11)
+#define PCIE1_RESET_PD_MASK			BIT(9)
+#define PCIE0_RESET_PD_MASK			BIT(8)
+#define UART1_RXD_PD_MASK			BIT(3)
+#define UART1_TXD_PD_MASK			BIT(2)
+#define I2C_SCL_PD_MASK				BIT(1)
+#define I2C_SDA_PD_MASK				BIT(0)
+
+#define REG_GPIO_L_PU				0x004c
+#define REG_GPIO_L_PD				0x0050
+
+#define REG_PCIE_RESET_OD			0x018c
+#define PCIE1_RESET_OD_MASK			BIT(1)
+#define PCIE0_RESET_OD_MASK			BIT(0)
+
+/*
+ * PWM MODE CONF - shared.
+ * The AN7563 GPIO flash mode registers use the same layout as EN7581:
+ * REG_GPIO_FLASH_MODE_CFG covers GPIO0-15, REG_GPIO_FLASH_MODE_CFG_EXT
+ * covers GPIO16-31 (bits 0-15) and GPIO36+ (bits 16+). The SPI pads
+ * (GPIO32-35) have no flash mode configuration bit.
+ */
+#define REG_GPIO_FLASH_MODE_CFG			0x0034
+#define GPIO15_FLASH_MODE_CFG			BIT(15)
+#define GPIO14_FLASH_MODE_CFG			BIT(14)
+#define GPIO13_FLASH_MODE_CFG			BIT(13)
+#define GPIO12_FLASH_MODE_CFG			BIT(12)
+#define GPIO11_FLASH_MODE_CFG			BIT(11)
+#define GPIO10_FLASH_MODE_CFG			BIT(10)
+#define GPIO9_FLASH_MODE_CFG			BIT(9)
+#define GPIO8_FLASH_MODE_CFG			BIT(8)
+#define GPIO7_FLASH_MODE_CFG			BIT(7)
+#define GPIO6_FLASH_MODE_CFG			BIT(6)
+#define GPIO5_FLASH_MODE_CFG			BIT(5)
+#define GPIO4_FLASH_MODE_CFG			BIT(4)
+#define GPIO3_FLASH_MODE_CFG			BIT(3)
+#define GPIO2_FLASH_MODE_CFG			BIT(2)
+#define GPIO1_FLASH_MODE_CFG			BIT(1)
+#define GPIO0_FLASH_MODE_CFG			BIT(0)
+
+#define REG_GPIO_FLASH_MODE_CFG_EXT		0x0068
+#define GPIO37_FLASH_MODE_CFG			BIT(17)
+#define GPIO36_FLASH_MODE_CFG			BIT(16)
+#define GPIO31_FLASH_MODE_CFG			BIT(15)
+#define GPIO30_FLASH_MODE_CFG			BIT(14)
+#define GPIO29_FLASH_MODE_CFG			BIT(13)
+#define GPIO28_FLASH_MODE_CFG			BIT(12)
+#define GPIO27_FLASH_MODE_CFG			BIT(11)
+#define GPIO26_FLASH_MODE_CFG			BIT(10)
+#define GPIO25_FLASH_MODE_CFG			BIT(9)
+#define GPIO24_FLASH_MODE_CFG			BIT(8)
+#define GPIO23_FLASH_MODE_CFG			BIT(7)
+#define GPIO22_FLASH_MODE_CFG			BIT(6)
+#define GPIO21_FLASH_MODE_CFG			BIT(5)
+#define GPIO20_FLASH_MODE_CFG			BIT(4)
+#define GPIO19_FLASH_MODE_CFG			BIT(3)
+#define GPIO18_FLASH_MODE_CFG			BIT(2)
+#define GPIO17_FLASH_MODE_CFG			BIT(1)
+#define GPIO16_FLASH_MODE_CFG			BIT(0)
+
+#define AIROHA_PINCTRL_GPIO(gpio, mux_val)			\
+	{							\
+		.name = (gpio),					\
+		.regmap[0] = {					\
+			AIROHA_FUNC_MUX,			\
+			REG_GPIO_PON_MODE,			\
+			(mux_val),				\
+			(mux_val)				\
+		},						\
+		.regmap_size = 1,				\
+	}
+
+#define AIROHA_PINCTRL_GPIO_EXT(gpio, mux_val, smux_val)	\
+	{							\
+		.name = (gpio),					\
+		.regmap[0] = {					\
+			AIROHA_FUNC_PWM_EXT_MUX,		\
+			REG_GPIO_FLASH_MODE_CFG_EXT,		\
+			(mux_val),				\
+			0					\
+		},						\
+		.regmap[1] = {					\
+			AIROHA_FUNC_MUX,			\
+			REG_GPIO_PON_MODE,			\
+			(smux_val),				\
+			(smux_val)				\
+		},						\
+		.regmap_size = 2,				\
+	}
+
+/* PWM */
+#define AIROHA_PINCTRL_PWM(gpio, mux_val)			\
+	{							\
+		.name = (gpio),					\
+		.regmap[0] = {					\
+			AIROHA_FUNC_PWM_MUX,			\
+			REG_GPIO_FLASH_MODE_CFG,		\
+			(mux_val),				\
+			(mux_val)				\
+		},						\
+		.regmap_size = 1,				\
+	}
+
+#define AIROHA_PINCTRL_PWM_EXT(gpio, mux_val)			\
+	{							\
+		.name = (gpio),					\
+		.regmap[0] = {					\
+			AIROHA_FUNC_PWM_EXT_MUX,		\
+			REG_GPIO_FLASH_MODE_CFG_EXT,		\
+			(mux_val),				\
+			(mux_val)				\
+		},						\
+		.regmap_size = 1,				\
+	}
+
+#define AIROHA_PINCTRL_PWM_EXT_SEC(gpio, mux_val, smux_val)	\
+	{							\
+		.name = (gpio),					\
+		.regmap[0] = {					\
+			AIROHA_FUNC_PWM_EXT_MUX,		\
+			REG_GPIO_FLASH_MODE_CFG_EXT,		\
+			(mux_val),				\
+			(mux_val)				\
+		},						\
+		.regmap[1] = {					\
+			AIROHA_FUNC_MUX,			\
+			REG_GPIO_PON_MODE,			\
+			(smux_val),				\
+			(smux_val)				\
+		},						\
+		.regmap_size = 2,				\
+	}
+
+#define AIROHA_PINCTRL_PHY_LED0(gpio, mux_val, map_mask, map_val)	\
+	{								\
+		.name = (gpio),						\
+		.regmap[0] = {						\
+			AIROHA_FUNC_MUX,				\
+			REG_GPIO_2ND_I2C_MODE,				\
+			(mux_val),					\
+			(mux_val),					\
+		},							\
+		.regmap[1] = {						\
+			AIROHA_FUNC_MUX,				\
+			REG_LAN_LED0_MAPPING,				\
+			(map_mask),					\
+			(map_val),					\
+		},							\
+		.regmap_size = 2,					\
+	}
+
+#define AIROHA_PINCTRL_PHY_LED1(gpio, mux_val, map_mask, map_val)	\
+	{								\
+		.name = (gpio),						\
+		.regmap[0] = {						\
+			AIROHA_FUNC_MUX,				\
+			REG_GPIO_2ND_I2C_MODE,				\
+			(mux_val),					\
+			(mux_val),					\
+		},							\
+		.regmap[1] = {						\
+			AIROHA_FUNC_MUX,				\
+			REG_LAN_LED1_MAPPING,				\
+			(map_mask),					\
+			(map_val),					\
+		},							\
+		.regmap_size = 2,					\
+	}
+
+static const struct pinctrl_pin_desc pinctrl_pins[] = {
+	PINCTRL_PIN(0, "gpio0"),
+	PINCTRL_PIN(1, "gpio1"),
+	PINCTRL_PIN(2, "gpio2"),
+	PINCTRL_PIN(3, "gpio3"),
+	PINCTRL_PIN(4, "gpio4"),
+	PINCTRL_PIN(5, "gpio5"),
+	PINCTRL_PIN(6, "gpio6"),
+	PINCTRL_PIN(7, "gpio7"),
+	PINCTRL_PIN(8, "gpio8"),
+	PINCTRL_PIN(9, "gpio9"),
+	PINCTRL_PIN(10, "gpio10"),
+	PINCTRL_PIN(11, "gpio11"),
+	PINCTRL_PIN(12, "gpio12"),
+	PINCTRL_PIN(13, "gpio13"),
+	PINCTRL_PIN(14, "gpio14"),
+	PINCTRL_PIN(15, "gpio15"),
+	PINCTRL_PIN(16, "gpio16"),
+	PINCTRL_PIN(17, "gpio17"),
+	PINCTRL_PIN(18, "gpio18"),
+	PINCTRL_PIN(19, "gpio19"),
+	PINCTRL_PIN(20, "gpio20"),
+	PINCTRL_PIN(21, "gpio21"),
+	PINCTRL_PIN(22, "gpio22"),
+	PINCTRL_PIN(23, "gpio23"),
+	PINCTRL_PIN(24, "gpio24"),
+	PINCTRL_PIN(25, "gpio25"),
+	PINCTRL_PIN(26, "gpio26"),
+	PINCTRL_PIN(27, "gpio27"),
+	PINCTRL_PIN(28, "pcie_reset0"),	/* GPIO28 */
+	PINCTRL_PIN(29, "pcie_reset1"),	/* GPIO29 */
+	PINCTRL_PIN(30, "i2c_scl"),	/* GPIO30 */
+	PINCTRL_PIN(31, "i2c_sda"),	/* GPIO31 */
+	PINCTRL_PIN(32, "spi_clk"),	/* GPIO32 */
+	PINCTRL_PIN(33, "spi_cs"),	/* GPIO33 */
+	PINCTRL_PIN(34, "spi_mosi"),	/* GPIO34 */
+	PINCTRL_PIN(35, "spi_miso"),	/* GPIO35 */
+	PINCTRL_PIN(36, "uart_txd"),	/* GPIO36 */
+	PINCTRL_PIN(37, "uart_rxd"),	/* GPIO37 */
+};
+
+static const int pon_pins[] = { 14, 15, 16, 17, 18, 19 };
+static const int sipo_pins[] = { 20, 21 };
+static const int sipo_rclk_pins[] = { 20, 21, 26 };
+static const int mdio_pins[] = { 30, 31 };
+static const int hsuart_pins[] = { 16, 17 };
+static const int hsuart_cts_rts_pins[] = { 14, 15 };
+static const int i2c_pins[] = { 30, 31 };
+static const int jtag_udi_pins[] = { 7, 8, 9, 10, 11 };
+static const int jtag_dfd_pins[] = { 7, 8, 9, 10, 11 };
+static const int pcm1_pins[] = { 22, 23, 24, 25 };
+static const int pcm2_pins[] = { 1, 2, 3, 4 };
+static const int spi_pins[] = { 32, 33, 34, 35 };
+static const int spi_quad_pins[] = { 2, 3 };
+static const int spi_cs1_pins[] = { 4 };
+static const int pnand_pins[] = {
+	1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 27, 32, 33, 34, 35
+};
+static const int gpio0_pins[] = { 0 };
+static const int gpio1_pins[] = { 1 };
+static const int gpio2_pins[] = { 2 };
+static const int gpio3_pins[] = { 3 };
+static const int gpio4_pins[] = { 4 };
+static const int gpio5_pins[] = { 5 };
+static const int gpio6_pins[] = { 6 };
+static const int gpio7_pins[] = { 7 };
+static const int gpio8_pins[] = { 8 };
+static const int gpio9_pins[] = { 9 };
+static const int gpio10_pins[] = { 10 };
+static const int gpio11_pins[] = { 11 };
+static const int gpio12_pins[] = { 12 };
+static const int gpio13_pins[] = { 13 };
+static const int gpio14_pins[] = { 14 };
+static const int gpio15_pins[] = { 15 };
+static const int gpio16_pins[] = { 16 };
+static const int gpio17_pins[] = { 17 };
+static const int gpio18_pins[] = { 18 };
+static const int gpio19_pins[] = { 19 };
+static const int gpio20_pins[] = { 20 };
+static const int gpio21_pins[] = { 21 };
+static const int gpio22_pins[] = { 22 };
+static const int gpio23_pins[] = { 23 };
+static const int gpio24_pins[] = { 24 };
+static const int gpio25_pins[] = { 25 };
+static const int gpio26_pins[] = { 26 };
+static const int gpio27_pins[] = { 27 };
+static const int gpio28_pins[] = { 28 };
+static const int gpio29_pins[] = { 29 };
+static const int gpio30_pins[] = { 30 };
+static const int gpio31_pins[] = { 31 };
+static const int gpio32_pins[] = { 32 };
+static const int gpio33_pins[] = { 33 };
+static const int gpio34_pins[] = { 34 };
+static const int gpio35_pins[] = { 35 };
+static const int gpio36_pins[] = { 36 };
+static const int gpio37_pins[] = { 37 };
+static const int pcie_reset0_pins[] = { 28 };
+static const int pcie_reset1_pins[] = { 29 };
+
+static const struct pingroup pinctrl_groups[] = {
+	PINCTRL_PIN_GROUP("pon", pon),
+	PINCTRL_PIN_GROUP("sipo", sipo),
+	PINCTRL_PIN_GROUP("sipo_rclk", sipo_rclk),
+	PINCTRL_PIN_GROUP("mdio", mdio),
+	PINCTRL_PIN_GROUP("hsuart", hsuart),
+	PINCTRL_PIN_GROUP("hsuart_cts_rts", hsuart_cts_rts),
+	PINCTRL_PIN_GROUP("i2c", i2c),
+	PINCTRL_PIN_GROUP("jtag_udi", jtag_udi),
+	PINCTRL_PIN_GROUP("jtag_dfd", jtag_dfd),
+	PINCTRL_PIN_GROUP("pcm1", pcm1),
+	PINCTRL_PIN_GROUP("pcm2", pcm2),
+	PINCTRL_PIN_GROUP("spi", spi),
+	PINCTRL_PIN_GROUP("spi_quad", spi_quad),
+	PINCTRL_PIN_GROUP("spi_cs1", spi_cs1),
+	PINCTRL_PIN_GROUP("pnand", pnand),
+	PINCTRL_PIN_GROUP("gpio0", gpio0),
+	PINCTRL_PIN_GROUP("gpio1", gpio1),
+	PINCTRL_PIN_GROUP("gpio2", gpio2),
+	PINCTRL_PIN_GROUP("gpio3", gpio3),
+	PINCTRL_PIN_GROUP("gpio4", gpio4),
+	PINCTRL_PIN_GROUP("gpio5", gpio5),
+	PINCTRL_PIN_GROUP("gpio6", gpio6),
+	PINCTRL_PIN_GROUP("gpio7", gpio7),
+	PINCTRL_PIN_GROUP("gpio8", gpio8),
+	PINCTRL_PIN_GROUP("gpio9", gpio9),
+	PINCTRL_PIN_GROUP("gpio10", gpio10),
+	PINCTRL_PIN_GROUP("gpio11", gpio11),
+	PINCTRL_PIN_GROUP("gpio12", gpio12),
+	PINCTRL_PIN_GROUP("gpio13", gpio13),
+	PINCTRL_PIN_GROUP("gpio14", gpio14),
+	PINCTRL_PIN_GROUP("gpio15", gpio15),
+	PINCTRL_PIN_GROUP("gpio16", gpio16),
+	PINCTRL_PIN_GROUP("gpio17", gpio17),
+	PINCTRL_PIN_GROUP("gpio18", gpio18),
+	PINCTRL_PIN_GROUP("gpio19", gpio19),
+	PINCTRL_PIN_GROUP("gpio20", gpio20),
+	PINCTRL_PIN_GROUP("gpio21", gpio21),
+	PINCTRL_PIN_GROUP("gpio22", gpio22),
+	PINCTRL_PIN_GROUP("gpio23", gpio23),
+	PINCTRL_PIN_GROUP("gpio24", gpio24),
+	PINCTRL_PIN_GROUP("gpio25", gpio25),
+	PINCTRL_PIN_GROUP("gpio26", gpio26),
+	PINCTRL_PIN_GROUP("gpio27", gpio27),
+	PINCTRL_PIN_GROUP("gpio28", gpio28),
+	PINCTRL_PIN_GROUP("gpio29", gpio29),
+	PINCTRL_PIN_GROUP("gpio30", gpio30),
+	PINCTRL_PIN_GROUP("gpio31", gpio31),
+	PINCTRL_PIN_GROUP("gpio32", gpio32),
+	PINCTRL_PIN_GROUP("gpio33", gpio33),
+	PINCTRL_PIN_GROUP("gpio34", gpio34),
+	PINCTRL_PIN_GROUP("gpio35", gpio35),
+	PINCTRL_PIN_GROUP("gpio36", gpio36),
+	PINCTRL_PIN_GROUP("gpio37", gpio37),
+	PINCTRL_PIN_GROUP("pcie_reset0", pcie_reset0),
+	PINCTRL_PIN_GROUP("pcie_reset1", pcie_reset1),
+};
+
+/* shared */
+static const char *const pon_groups[] = { "pon" };
+static const char *const sipo_groups[] = { "sipo", "sipo_rclk" };
+static const char *const mdio_groups[] = { "mdio" };
+static const char *const uart_groups[] = {
+	"hsuart", "hsuart_cts_rts"
+};
+static const char *const jtag_groups[] = { "jtag_udi", "jtag_dfd" };
+static const char *const pcm_groups[] = { "pcm1", "pcm2" };
+static const char *const spi_groups[] = { "spi_quad", "spi_cs1" };
+static const char *const pnand_groups[] = { "pnand" };
+static const char *const gpio_groups[] = {
+	"gpio28", "gpio29", "gpio30", "gpio31", "gpio32",
+	"gpio33", "gpio34", "gpio35", "gpio36", "gpio37"
+};
+static const char *const pcie_reset_groups[] = {
+	"pcie_reset0", "pcie_reset1"
+};
+static const char *const pwm_groups[] = {
+	"gpio0",  "gpio1",  "gpio2",  "gpio3",  "gpio4",  "gpio5",
+	"gpio6",  "gpio7",  "gpio8",  "gpio9",  "gpio10", "gpio11",
+	"gpio12", "gpio13", "gpio14", "gpio15", "gpio16", "gpio17",
+	"gpio18", "gpio19", "gpio20", "gpio21", "gpio22", "gpio23",
+	"gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29",
+	"gpio30", "gpio31", "gpio36", "gpio37"
+};
+static const char *const phy1_led0_groups[] = {
+	"gpio8", "gpio9", "gpio10", "gpio11"
+};
+static const char *const phy2_led0_groups[] = {
+	"gpio8", "gpio9", "gpio10", "gpio11"
+};
+static const char *const phy3_led0_groups[] = {
+	"gpio8", "gpio9", "gpio10", "gpio11"
+};
+static const char *const phy4_led0_groups[] = {
+	"gpio8", "gpio9", "gpio10", "gpio11"
+};
+static const char *const phy1_led1_groups[] = {
+	"gpio4", "gpio5", "gpio6", "gpio7"
+};
+static const char *const phy2_led1_groups[] = {
+	"gpio4", "gpio5", "gpio6", "gpio7"
+};
+static const char *const phy3_led1_groups[] = {
+	"gpio4", "gpio5", "gpio6", "gpio7"
+};
+static const char *const phy4_led1_groups[] = {
+	"gpio4", "gpio5", "gpio6", "gpio7"
+};
+
+/* shared */
+static const struct airoha_pinctrl_func_group pon_func_group[] = {
+	{
+		.name = "pon",
+		.regmap[0] = {
+			AIROHA_FUNC_MUX,
+			REG_GPIO_PON_MODE,
+			GPIO_PON_MODE_MASK,
+			GPIO_PON_MODE_MASK
+		},
+		.regmap_size = 1,
+	},
+};
+
+/* shared */
+static const struct airoha_pinctrl_func_group sipo_func_group[] = {
+	{
+		.name = "sipo",
+		.regmap[0] = {
+			AIROHA_FUNC_MUX,
+			REG_GPIO_PON_MODE,
+			GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK,
+			GPIO_SIPO_MODE_MASK
+		},
+		.regmap_size = 1,
+	}, {
+		.name = "sipo_rclk",
+		.regmap[0] = {
+			AIROHA_FUNC_MUX,
+			REG_GPIO_PON_MODE,
+			GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK,
+			GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK
+		},
+		.regmap_size = 1,
+	},
+};
+
+/*
+ * On AN7563 the SMI master (MDC/MDIO) is shared with the I2C_SCL/I2C_SDA
+ * pads and selected via the SGMII MDIO mode bit. I2C is the default pad
+ * function (no mux bit).
+ */
+static const struct airoha_pinctrl_func_group mdio_func_group[] = {
+	{
+		.name = "mdio",
+		.regmap[0] = {
+			AIROHA_FUNC_MUX,
+			REG_GPIO_PON_MODE,
+			GPIO_SGMII_MDIO_MODE_MASK,
+			GPIO_SGMII_MDIO_MODE_MASK
+		},
+		.regmap_size = 1,
+	},
+};
+
+static const struct airoha_pinctrl_func_group uart_func_group[] = {
+	{
+		.name = "hsuart",
+		.regmap[0] = {
+			AIROHA_FUNC_MUX,
+			REG_GPIO_PON_MODE,
+			GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK,
+			GPIO_HSUART_MODE_MASK
+		},
+		.regmap_size = 1,
+	},
+	{
+		.name = "hsuart_cts_rts",
+		.regmap[0] = {
+			AIROHA_FUNC_MUX,
+			REG_GPIO_PON_MODE,
+			GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK,
+			GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK
+		},
+		.regmap_size = 1,
+	},
+};
+
+/* shared */
+static const struct airoha_pinctrl_func_group jtag_func_group[] = {
+	{
+		.name = "jtag_udi",
+		.regmap[0] = {
+			AIROHA_FUNC_MUX,
+			REG_NPU_UART_EN,
+			JTAG_UDI_EN_MASK,
+			JTAG_UDI_EN_MASK
+		},
+		.regmap_size = 1,
+	}, {
+		.name = "jtag_dfd",
+		.regmap[0] = {
+			AIROHA_FUNC_MUX,
+			REG_NPU_UART_EN,
+			JTAG_DFD_EN_MASK,
+			JTAG_DFD_EN_MASK
+		},
+		.regmap_size = 1,
+	},
+};
+
+/* shared */
+static const struct airoha_pinctrl_func_group pcm_func_group[] = {
+	{
+		.name = "pcm1",
+		.regmap[0] = {
+			AIROHA_FUNC_MUX,
+			REG_GPIO_SPI_CS1_MODE,
+			GPIO_PCM1_MODE_MASK,
+			GPIO_PCM1_MODE_MASK
+		},
+		.regmap_size = 1,
+	}, {
+		.name = "pcm2",
+		.regmap[0] = {
+			AIROHA_FUNC_MUX,
+			REG_GPIO_SPI_CS1_MODE,
+			GPIO_PCM2_MODE_MASK,
+			GPIO_PCM2_MODE_MASK
+		},
+		.regmap_size = 1,
+	},
+};
+
+/* shared */
+static const struct airoha_pinctrl_func_group spi_func_group[] = {
+	{
+		.name = "spi_quad",
+		.regmap[0] = {
+			AIROHA_FUNC_MUX,
+			REG_GPIO_SPI_CS1_MODE,
+			GPIO_SPI_QUAD_MODE_MASK,
+			GPIO_SPI_QUAD_MODE_MASK
+		},
+		.regmap_size = 1,
+	}, {
+		.name = "spi_cs1",
+		.regmap[0] = {
+			AIROHA_FUNC_MUX,
+			REG_GPIO_SPI_CS1_MODE,
+			GPIO_SPI_CS1_MODE_MASK,
+			GPIO_SPI_CS1_MODE_MASK
+		},
+		.regmap_size = 1,
+	},
+};
+
+/* shared */
+static const struct airoha_pinctrl_func_group pnand_func_group[] = {
+	{
+		.name = "pnand",
+		.regmap[0] = {
+			AIROHA_FUNC_MUX,
+			REG_GPIO_PON_MODE,
+			GPIO_PARALLEL_NAND_MODE_MASK,
+			GPIO_PARALLEL_NAND_MODE_MASK
+		},
+		.regmap_size = 1,
+	},
+};
+
+static const struct airoha_pinctrl_func_group gpio_func_group[] = {
+	AIROHA_PINCTRL_GPIO_EXT("gpio28", GPIO28_FLASH_MODE_CFG,
+				GPIO_PCIE_RESET0_MASK),
+	AIROHA_PINCTRL_GPIO_EXT("gpio29", GPIO29_FLASH_MODE_CFG,
+				GPIO_PCIE_RESET1_MASK),
+	AIROHA_PINCTRL_GPIO_EXT("gpio30", GPIO30_FLASH_MODE_CFG,
+				I2C_SCL_GPIO_MODE_MASK),
+	AIROHA_PINCTRL_GPIO_EXT("gpio31", GPIO31_FLASH_MODE_CFG,
+				I2C_SDA_GPIO_MODE_MASK),
+	AIROHA_PINCTRL_GPIO("gpio32", SPI_CLK_GPIO_MODE_MASK),
+	AIROHA_PINCTRL_GPIO("gpio33", SPI_CS_GPIO_MODE_MASK),
+	AIROHA_PINCTRL_GPIO("gpio34", SPI_MOSI_GPIO_MODE_MASK),
+	AIROHA_PINCTRL_GPIO("gpio35", SPI_MISO_GPIO_MODE_MASK),
+	AIROHA_PINCTRL_GPIO_EXT("gpio36", GPIO36_FLASH_MODE_CFG,
+				UART_TXD_GPIO_MODE_MASK),
+	AIROHA_PINCTRL_GPIO_EXT("gpio37", GPIO37_FLASH_MODE_CFG,
+				UART_RXD_GPIO_MODE_MASK),
+};
+
+/*
+ * On AN7563 a set GPIO_PCIE_RESET{0,1} bit routes the pad to its GPIO
+ * function, so the PCIe reset function must clear it.
+ */
+static const struct airoha_pinctrl_func_group pcie_reset_func_group[] = {
+	{
+		.name = "pcie_reset0",
+		.regmap[0] = {
+			AIROHA_FUNC_MUX,
+			REG_GPIO_PON_MODE,
+			GPIO_PCIE_RESET0_MASK,
+			0
+		},
+		.regmap_size = 1,
+	}, {
+		.name = "pcie_reset1",
+		.regmap[0] = {
+			AIROHA_FUNC_MUX,
+			REG_GPIO_PON_MODE,
+			GPIO_PCIE_RESET1_MASK,
+			0
+		},
+		.regmap_size = 1,
+	},
+};
+
+static const struct airoha_pinctrl_func_group pwm_func_group[] = {
+	AIROHA_PINCTRL_PWM("gpio0", GPIO0_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM("gpio1", GPIO1_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM("gpio2", GPIO2_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM("gpio3", GPIO3_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM("gpio4", GPIO4_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM("gpio5", GPIO5_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM("gpio6", GPIO6_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM("gpio7", GPIO7_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM("gpio8", GPIO8_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM("gpio9", GPIO9_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM("gpio10", GPIO10_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM("gpio11", GPIO11_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM("gpio12", GPIO12_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM("gpio13", GPIO13_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM("gpio14", GPIO14_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM("gpio15", GPIO15_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM_EXT("gpio16", GPIO16_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM_EXT("gpio17", GPIO17_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM_EXT("gpio18", GPIO18_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM_EXT("gpio19", GPIO19_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM_EXT("gpio20", GPIO20_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM_EXT("gpio21", GPIO21_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM_EXT("gpio22", GPIO22_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM_EXT("gpio23", GPIO23_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM_EXT("gpio24", GPIO24_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM_EXT("gpio25", GPIO25_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM_EXT("gpio26", GPIO26_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM_EXT("gpio27", GPIO27_FLASH_MODE_CFG),
+	AIROHA_PINCTRL_PWM_EXT_SEC("gpio28", GPIO28_FLASH_MODE_CFG,
+				   GPIO_PCIE_RESET0_MASK),
+	AIROHA_PINCTRL_PWM_EXT_SEC("gpio29", GPIO29_FLASH_MODE_CFG,
+				   GPIO_PCIE_RESET1_MASK),
+	AIROHA_PINCTRL_PWM_EXT_SEC("gpio30", GPIO30_FLASH_MODE_CFG,
+				   I2C_SCL_GPIO_MODE_MASK),
+	AIROHA_PINCTRL_PWM_EXT_SEC("gpio31", GPIO31_FLASH_MODE_CFG,
+				   I2C_SDA_GPIO_MODE_MASK),
+	AIROHA_PINCTRL_PWM_EXT_SEC("gpio36", GPIO36_FLASH_MODE_CFG,
+				   UART_TXD_GPIO_MODE_MASK),
+	AIROHA_PINCTRL_PWM_EXT_SEC("gpio37", GPIO37_FLASH_MODE_CFG,
+				   UART_RXD_GPIO_MODE_MASK),
+};
+
+/*
+ * LED pad mapping (datasheet table 4-9):
+ * GPIO8: LAN0_LED0, GPIO9: LAN1_LED0, GPIO10: LAN2_LED0, GPIO11: LAN3_LED0
+ * GPIO7: LAN0_LED1, GPIO6: LAN1_LED1, GPIO5: LAN2_LED1, GPIO4: LAN3_LED1
+ */
+static const struct airoha_pinctrl_func_group phy1_led0_func_group[] = {
+	AIROHA_PINCTRL_PHY_LED0("gpio8", GPIO_LAN0_LED0_MODE_MASK,
+				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),
+	AIROHA_PINCTRL_PHY_LED0("gpio9", GPIO_LAN1_LED0_MODE_MASK,
+				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)),
+	AIROHA_PINCTRL_PHY_LED0("gpio10", GPIO_LAN2_LED0_MODE_MASK,
+				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)),
+	AIROHA_PINCTRL_PHY_LED0("gpio11", GPIO_LAN3_LED0_MODE_MASK,
+				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),
+};
+
+static const struct airoha_pinctrl_func_group phy2_led0_func_group[] = {
+	AIROHA_PINCTRL_PHY_LED0("gpio8", GPIO_LAN0_LED0_MODE_MASK,
+				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),
+	AIROHA_PINCTRL_PHY_LED0("gpio9", GPIO_LAN1_LED0_MODE_MASK,
+				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)),
+	AIROHA_PINCTRL_PHY_LED0("gpio10", GPIO_LAN2_LED0_MODE_MASK,
+				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)),
+	AIROHA_PINCTRL_PHY_LED0("gpio11", GPIO_LAN3_LED0_MODE_MASK,
+				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),
+};
+
+static const struct airoha_pinctrl_func_group phy3_led0_func_group[] = {
+	AIROHA_PINCTRL_PHY_LED0("gpio8", GPIO_LAN0_LED0_MODE_MASK,
+				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
+	AIROHA_PINCTRL_PHY_LED0("gpio9", GPIO_LAN1_LED0_MODE_MASK,
+				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),
+	AIROHA_PINCTRL_PHY_LED0("gpio10", GPIO_LAN2_LED0_MODE_MASK,
+				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),
+	AIROHA_PINCTRL_PHY_LED0("gpio11", GPIO_LAN3_LED0_MODE_MASK,
+				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
+};
+
+static const struct airoha_pinctrl_func_group phy4_led0_func_group[] = {
+	AIROHA_PINCTRL_PHY_LED0("gpio8", GPIO_LAN0_LED0_MODE_MASK,
+				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)),
+	AIROHA_PINCTRL_PHY_LED0("gpio9", GPIO_LAN1_LED0_MODE_MASK,
+				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)),
+	AIROHA_PINCTRL_PHY_LED0("gpio10", GPIO_LAN2_LED0_MODE_MASK,
+				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)),
+	AIROHA_PINCTRL_PHY_LED0("gpio11", GPIO_LAN3_LED0_MODE_MASK,
+				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)),
+};
+
+static const struct airoha_pinctrl_func_group phy1_led1_func_group[] = {
+	AIROHA_PINCTRL_PHY_LED1("gpio4", GPIO_LAN3_LED1_MODE_MASK,
+				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),
+	AIROHA_PINCTRL_PHY_LED1("gpio5", GPIO_LAN2_LED1_MODE_MASK,
+				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)),
+	AIROHA_PINCTRL_PHY_LED1("gpio6", GPIO_LAN1_LED1_MODE_MASK,
+				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)),
+	AIROHA_PINCTRL_PHY_LED1("gpio7", GPIO_LAN0_LED1_MODE_MASK,
+				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),
+};
+
+static const struct airoha_pinctrl_func_group phy2_led1_func_group[] = {
+	AIROHA_PINCTRL_PHY_LED1("gpio4", GPIO_LAN3_LED1_MODE_MASK,
+				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),
+	AIROHA_PINCTRL_PHY_LED1("gpio5", GPIO_LAN2_LED1_MODE_MASK,
+				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)),
+	AIROHA_PINCTRL_PHY_LED1("gpio6", GPIO_LAN1_LED1_MODE_MASK,
+				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)),
+	AIROHA_PINCTRL_PHY_LED1("gpio7", GPIO_LAN0_LED1_MODE_MASK,
+				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),
+};
+
+static const struct airoha_pinctrl_func_group phy3_led1_func_group[] = {
+	AIROHA_PINCTRL_PHY_LED1("gpio4", GPIO_LAN3_LED1_MODE_MASK,
+				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
+	AIROHA_PINCTRL_PHY_LED1("gpio5", GPIO_LAN2_LED1_MODE_MASK,
+				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),
+	AIROHA_PINCTRL_PHY_LED1("gpio6", GPIO_LAN1_LED1_MODE_MASK,
+				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),
+	AIROHA_PINCTRL_PHY_LED1("gpio7", GPIO_LAN0_LED1_MODE_MASK,
+				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
+};
+
+static const struct airoha_pinctrl_func_group phy4_led1_func_group[] = {
+	AIROHA_PINCTRL_PHY_LED1("gpio4", GPIO_LAN3_LED1_MODE_MASK,
+				LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)),
+	AIROHA_PINCTRL_PHY_LED1("gpio5", GPIO_LAN2_LED1_MODE_MASK,
+				LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)),
+	AIROHA_PINCTRL_PHY_LED1("gpio6", GPIO_LAN1_LED1_MODE_MASK,
+				LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)),
+	AIROHA_PINCTRL_PHY_LED1("gpio7", GPIO_LAN0_LED1_MODE_MASK,
+				LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)),
+};
+
+static const struct airoha_pinctrl_func pinctrl_funcs[] = {
+	PINCTRL_FUNC_DESC("pon", pon),
+	PINCTRL_FUNC_DESC("sipo", sipo),
+	PINCTRL_FUNC_DESC("mdio", mdio),
+	PINCTRL_FUNC_DESC("uart", uart),
+	PINCTRL_FUNC_DESC("jtag", jtag),
+	PINCTRL_FUNC_DESC("pcm", pcm),
+	PINCTRL_FUNC_DESC("spi", spi),
+	PINCTRL_FUNC_DESC("pnand", pnand),
+	PINCTRL_FUNC_DESC("gpio", gpio),
+	PINCTRL_FUNC_DESC("pcie_reset", pcie_reset),
+	PINCTRL_FUNC_DESC("pwm", pwm),
+	PINCTRL_FUNC_DESC("phy1_led0", phy1_led0),
+	PINCTRL_FUNC_DESC("phy2_led0", phy2_led0),
+	PINCTRL_FUNC_DESC("phy3_led0", phy3_led0),
+	PINCTRL_FUNC_DESC("phy4_led0", phy4_led0),
+	PINCTRL_FUNC_DESC("phy1_led1", phy1_led1),
+	PINCTRL_FUNC_DESC("phy2_led1", phy2_led1),
+	PINCTRL_FUNC_DESC("phy3_led1", phy3_led1),
+	PINCTRL_FUNC_DESC("phy4_led1", phy4_led1),
+};
+
+static const struct airoha_pinctrl_conf pinctrl_pullup_conf[] = {
+	PINCTRL_CONF_DESC(0, REG_GPIO_L_PU, BIT(0)),
+	PINCTRL_CONF_DESC(1, REG_GPIO_L_PU, BIT(1)),
+	PINCTRL_CONF_DESC(2, REG_GPIO_L_PU, BIT(2)),
+	PINCTRL_CONF_DESC(3, REG_GPIO_L_PU, BIT(3)),
+	PINCTRL_CONF_DESC(4, REG_GPIO_L_PU, BIT(4)),
+	PINCTRL_CONF_DESC(5, REG_GPIO_L_PU, BIT(5)),
+	PINCTRL_CONF_DESC(6, REG_GPIO_L_PU, BIT(6)),
+	PINCTRL_CONF_DESC(7, REG_GPIO_L_PU, BIT(7)),
+	PINCTRL_CONF_DESC(8, REG_GPIO_L_PU, BIT(8)),
+	PINCTRL_CONF_DESC(9, REG_GPIO_L_PU, BIT(9)),
+	PINCTRL_CONF_DESC(10, REG_GPIO_L_PU, BIT(10)),
+	PINCTRL_CONF_DESC(11, REG_GPIO_L_PU, BIT(11)),
+	PINCTRL_CONF_DESC(12, REG_GPIO_L_PU, BIT(12)),
+	PINCTRL_CONF_DESC(13, REG_GPIO_L_PU, BIT(13)),
+	PINCTRL_CONF_DESC(14, REG_GPIO_L_PU, BIT(14)),
+	PINCTRL_CONF_DESC(15, REG_GPIO_L_PU, BIT(15)),
+	PINCTRL_CONF_DESC(16, REG_GPIO_L_PU, BIT(16)),
+	PINCTRL_CONF_DESC(17, REG_GPIO_L_PU, BIT(17)),
+	PINCTRL_CONF_DESC(18, REG_GPIO_L_PU, BIT(18)),
+	PINCTRL_CONF_DESC(19, REG_GPIO_L_PU, BIT(19)),
+	PINCTRL_CONF_DESC(20, REG_GPIO_L_PU, BIT(20)),
+	PINCTRL_CONF_DESC(21, REG_GPIO_L_PU, BIT(21)),
+	PINCTRL_CONF_DESC(22, REG_GPIO_L_PU, BIT(22)),
+	PINCTRL_CONF_DESC(23, REG_GPIO_L_PU, BIT(23)),
+	PINCTRL_CONF_DESC(24, REG_GPIO_L_PU, BIT(24)),
+	PINCTRL_CONF_DESC(25, REG_GPIO_L_PU, BIT(25)),
+	PINCTRL_CONF_DESC(26, REG_GPIO_L_PU, BIT(26)),
+	PINCTRL_CONF_DESC(27, REG_GPIO_L_PU, BIT(27)),
+	PINCTRL_CONF_DESC(28, REG_I2C_SDA_PU, PCIE0_RESET_PU_MASK),
+	PINCTRL_CONF_DESC(29, REG_I2C_SDA_PU, PCIE1_RESET_PU_MASK),
+	PINCTRL_CONF_DESC(30, REG_I2C_SDA_PU, I2C_SCL_PU_MASK),
+	PINCTRL_CONF_DESC(31, REG_I2C_SDA_PU, I2C_SDA_PU_MASK),
+	PINCTRL_CONF_DESC(32, REG_I2C_SDA_PU, SPI_CLK_PU_MASK),
+	PINCTRL_CONF_DESC(33, REG_I2C_SDA_PU, SPI_CS0_PU_MASK),
+	PINCTRL_CONF_DESC(34, REG_I2C_SDA_PU, SPI_MOSI_PU_MASK),
+	PINCTRL_CONF_DESC(35, REG_I2C_SDA_PU, SPI_MISO_PU_MASK),
+	PINCTRL_CONF_DESC(36, REG_I2C_SDA_PU, UART1_TXD_PU_MASK),
+	PINCTRL_CONF_DESC(37, REG_I2C_SDA_PU, UART1_RXD_PU_MASK),
+};
+
+static const struct airoha_pinctrl_conf pinctrl_pulldown_conf[] = {
+	PINCTRL_CONF_DESC(0, REG_GPIO_L_PD, BIT(0)),
+	PINCTRL_CONF_DESC(1, REG_GPIO_L_PD, BIT(1)),
+	PINCTRL_CONF_DESC(2, REG_GPIO_L_PD, BIT(2)),
+	PINCTRL_CONF_DESC(3, REG_GPIO_L_PD, BIT(3)),
+	PINCTRL_CONF_DESC(4, REG_GPIO_L_PD, BIT(4)),
+	PINCTRL_CONF_DESC(5, REG_GPIO_L_PD, BIT(5)),
+	PINCTRL_CONF_DESC(6, REG_GPIO_L_PD, BIT(6)),
+	PINCTRL_CONF_DESC(7, REG_GPIO_L_PD, BIT(7)),
+	PINCTRL_CONF_DESC(8, REG_GPIO_L_PD, BIT(8)),
+	PINCTRL_CONF_DESC(9, REG_GPIO_L_PD, BIT(9)),
+	PINCTRL_CONF_DESC(10, REG_GPIO_L_PD, BIT(10)),
+	PINCTRL_CONF_DESC(11, REG_GPIO_L_PD, BIT(11)),
+	PINCTRL_CONF_DESC(12, REG_GPIO_L_PD, BIT(12)),
+	PINCTRL_CONF_DESC(13, REG_GPIO_L_PD, BIT(13)),
+	PINCTRL_CONF_DESC(14, REG_GPIO_L_PD, BIT(14)),
+	PINCTRL_CONF_DESC(15, REG_GPIO_L_PD, BIT(15)),
+	PINCTRL_CONF_DESC(16, REG_GPIO_L_PD, BIT(16)),
+	PINCTRL_CONF_DESC(17, REG_GPIO_L_PD, BIT(17)),
+	PINCTRL_CONF_DESC(18, REG_GPIO_L_PD, BIT(18)),
+	PINCTRL_CONF_DESC(19, REG_GPIO_L_PD, BIT(19)),
+	PINCTRL_CONF_DESC(20, REG_GPIO_L_PD, BIT(20)),
+	PINCTRL_CONF_DESC(21, REG_GPIO_L_PD, BIT(21)),
+	PINCTRL_CONF_DESC(22, REG_GPIO_L_PD, BIT(22)),
+	PINCTRL_CONF_DESC(23, REG_GPIO_L_PD, BIT(23)),
+	PINCTRL_CONF_DESC(24, REG_GPIO_L_PD, BIT(24)),
+	PINCTRL_CONF_DESC(25, REG_GPIO_L_PD, BIT(25)),
+	PINCTRL_CONF_DESC(26, REG_GPIO_L_PD, BIT(26)),
+	PINCTRL_CONF_DESC(27, REG_GPIO_L_PD, BIT(27)),
+	PINCTRL_CONF_DESC(28, REG_I2C_SDA_PD, PCIE0_RESET_PD_MASK),
+	PINCTRL_CONF_DESC(29, REG_I2C_SDA_PD, PCIE1_RESET_PD_MASK),
+	PINCTRL_CONF_DESC(30, REG_I2C_SDA_PD, I2C_SCL_PD_MASK),
+	PINCTRL_CONF_DESC(31, REG_I2C_SDA_PD, I2C_SDA_PD_MASK),
+	PINCTRL_CONF_DESC(32, REG_I2C_SDA_PD, SPI_CLK_PD_MASK),
+	PINCTRL_CONF_DESC(33, REG_I2C_SDA_PD, SPI_CS0_PD_MASK),
+	PINCTRL_CONF_DESC(34, REG_I2C_SDA_PD, SPI_MOSI_PD_MASK),
+	PINCTRL_CONF_DESC(35, REG_I2C_SDA_PD, SPI_MISO_PD_MASK),
+	PINCTRL_CONF_DESC(36, REG_I2C_SDA_PD, UART1_TXD_PD_MASK),
+	PINCTRL_CONF_DESC(37, REG_I2C_SDA_PD, UART1_RXD_PD_MASK),
+};
+
+static const struct airoha_pinctrl_conf pinctrl_drive_e2_conf[] = {
+	PINCTRL_CONF_DESC(0, REG_GPIO_L_E2, BIT(0)),
+	PINCTRL_CONF_DESC(1, REG_GPIO_L_E2, BIT(1)),
+	PINCTRL_CONF_DESC(2, REG_GPIO_L_E2, BIT(2)),
+	PINCTRL_CONF_DESC(3, REG_GPIO_L_E2, BIT(3)),
+	PINCTRL_CONF_DESC(4, REG_GPIO_L_E2, BIT(4)),
+	PINCTRL_CONF_DESC(5, REG_GPIO_L_E2, BIT(5)),
+	PINCTRL_CONF_DESC(6, REG_GPIO_L_E2, BIT(6)),
+	PINCTRL_CONF_DESC(7, REG_GPIO_L_E2, BIT(7)),
+	PINCTRL_CONF_DESC(8, REG_GPIO_L_E2, BIT(8)),
+	PINCTRL_CONF_DESC(9, REG_GPIO_L_E2, BIT(9)),
+	PINCTRL_CONF_DESC(10, REG_GPIO_L_E2, BIT(10)),
+	PINCTRL_CONF_DESC(11, REG_GPIO_L_E2, BIT(11)),
+	PINCTRL_CONF_DESC(12, REG_GPIO_L_E2, BIT(12)),
+	PINCTRL_CONF_DESC(13, REG_GPIO_L_E2, BIT(13)),
+	PINCTRL_CONF_DESC(14, REG_GPIO_L_E2, BIT(14)),
+	PINCTRL_CONF_DESC(15, REG_GPIO_L_E2, BIT(15)),
+	PINCTRL_CONF_DESC(16, REG_GPIO_L_E2, BIT(16)),
+	PINCTRL_CONF_DESC(17, REG_GPIO_L_E2, BIT(17)),
+	PINCTRL_CONF_DESC(18, REG_GPIO_L_E2, BIT(18)),
+	PINCTRL_CONF_DESC(19, REG_GPIO_L_E2, BIT(19)),
+	PINCTRL_CONF_DESC(20, REG_GPIO_L_E2, BIT(20)),
+	PINCTRL_CONF_DESC(21, REG_GPIO_L_E2, BIT(21)),
+	PINCTRL_CONF_DESC(22, REG_GPIO_L_E2, BIT(22)),
+	PINCTRL_CONF_DESC(23, REG_GPIO_L_E2, BIT(23)),
+	PINCTRL_CONF_DESC(24, REG_GPIO_L_E2, BIT(24)),
+	PINCTRL_CONF_DESC(25, REG_GPIO_L_E2, BIT(25)),
+	PINCTRL_CONF_DESC(26, REG_GPIO_L_E2, BIT(26)),
+	PINCTRL_CONF_DESC(27, REG_GPIO_L_E2, BIT(27)),
+	PINCTRL_CONF_DESC(28, REG_I2C_SDA_E2, PCIE0_RESET_E2_MASK),
+	PINCTRL_CONF_DESC(29, REG_I2C_SDA_E2, PCIE1_RESET_E2_MASK),
+	PINCTRL_CONF_DESC(30, REG_I2C_SDA_E2, I2C_SCL_E2_MASK),
+	PINCTRL_CONF_DESC(31, REG_I2C_SDA_E2, I2C_SDA_E2_MASK),
+	PINCTRL_CONF_DESC(32, REG_I2C_SDA_E2, SPI_CLK_E2_MASK),
+	PINCTRL_CONF_DESC(33, REG_I2C_SDA_E2, SPI_CS0_E2_MASK),
+	PINCTRL_CONF_DESC(34, REG_I2C_SDA_E2, SPI_MOSI_E2_MASK),
+	PINCTRL_CONF_DESC(35, REG_I2C_SDA_E2, SPI_MISO_E2_MASK),
+	PINCTRL_CONF_DESC(36, REG_I2C_SDA_E2, UART1_TXD_E2_MASK),
+	PINCTRL_CONF_DESC(37, REG_I2C_SDA_E2, UART1_RXD_E2_MASK),
+};
+
+static const struct airoha_pinctrl_conf pinctrl_drive_e4_conf[] = {
+	PINCTRL_CONF_DESC(0, REG_GPIO_L_E4, BIT(0)),
+	PINCTRL_CONF_DESC(1, REG_GPIO_L_E4, BIT(1)),
+	PINCTRL_CONF_DESC(2, REG_GPIO_L_E4, BIT(2)),
+	PINCTRL_CONF_DESC(3, REG_GPIO_L_E4, BIT(3)),
+	PINCTRL_CONF_DESC(4, REG_GPIO_L_E4, BIT(4)),
+	PINCTRL_CONF_DESC(5, REG_GPIO_L_E4, BIT(5)),
+	PINCTRL_CONF_DESC(6, REG_GPIO_L_E4, BIT(6)),
+	PINCTRL_CONF_DESC(7, REG_GPIO_L_E4, BIT(7)),
+	PINCTRL_CONF_DESC(8, REG_GPIO_L_E4, BIT(8)),
+	PINCTRL_CONF_DESC(9, REG_GPIO_L_E4, BIT(9)),
+	PINCTRL_CONF_DESC(10, REG_GPIO_L_E4, BIT(10)),
+	PINCTRL_CONF_DESC(11, REG_GPIO_L_E4, BIT(11)),
+	PINCTRL_CONF_DESC(12, REG_GPIO_L_E4, BIT(12)),
+	PINCTRL_CONF_DESC(13, REG_GPIO_L_E4, BIT(13)),
+	PINCTRL_CONF_DESC(14, REG_GPIO_L_E4, BIT(14)),
+	PINCTRL_CONF_DESC(15, REG_GPIO_L_E4, BIT(15)),
+	PINCTRL_CONF_DESC(16, REG_GPIO_L_E4, BIT(16)),
+	PINCTRL_CONF_DESC(17, REG_GPIO_L_E4, BIT(17)),
+	PINCTRL_CONF_DESC(18, REG_GPIO_L_E4, BIT(18)),
+	PINCTRL_CONF_DESC(19, REG_GPIO_L_E4, BIT(19)),
+	PINCTRL_CONF_DESC(20, REG_GPIO_L_E4, BIT(20)),
+	PINCTRL_CONF_DESC(21, REG_GPIO_L_E4, BIT(21)),
+	PINCTRL_CONF_DESC(22, REG_GPIO_L_E4, BIT(22)),
+	PINCTRL_CONF_DESC(23, REG_GPIO_L_E4, BIT(23)),
+	PINCTRL_CONF_DESC(24, REG_GPIO_L_E4, BIT(24)),
+	PINCTRL_CONF_DESC(25, REG_GPIO_L_E4, BIT(25)),
+	PINCTRL_CONF_DESC(26, REG_GPIO_L_E4, BIT(26)),
+	PINCTRL_CONF_DESC(27, REG_GPIO_L_E4, BIT(27)),
+	PINCTRL_CONF_DESC(28, REG_I2C_SDA_E4, PCIE0_RESET_E4_MASK),
+	PINCTRL_CONF_DESC(29, REG_I2C_SDA_E4, PCIE1_RESET_E4_MASK),
+	PINCTRL_CONF_DESC(30, REG_I2C_SDA_E4, I2C_SCL_E4_MASK),
+	PINCTRL_CONF_DESC(31, REG_I2C_SDA_E4, I2C_SDA_E4_MASK),
+	PINCTRL_CONF_DESC(32, REG_I2C_SDA_E4, SPI_CLK_E4_MASK),
+	PINCTRL_CONF_DESC(33, REG_I2C_SDA_E4, SPI_CS0_E4_MASK),
+	PINCTRL_CONF_DESC(34, REG_I2C_SDA_E4, SPI_MOSI_E4_MASK),
+	PINCTRL_CONF_DESC(35, REG_I2C_SDA_E4, SPI_MISO_E4_MASK),
+	PINCTRL_CONF_DESC(36, REG_I2C_SDA_E4, UART1_TXD_E4_MASK),
+	PINCTRL_CONF_DESC(37, REG_I2C_SDA_E4, UART1_RXD_E4_MASK),
+};
+
+static const struct airoha_pinctrl_conf pinctrl_pcie_rst_od_conf[] = {
+	PINCTRL_CONF_DESC(28, REG_PCIE_RESET_OD, PCIE0_RESET_OD_MASK),
+	PINCTRL_CONF_DESC(29, REG_PCIE_RESET_OD, PCIE1_RESET_OD_MASK),
+};
+
+static const struct airoha_pinctrl_match_data pinctrl_match_data = {
+	.chip_scu_compatible = "airoha,en7581-chip-scu",
+	.pinctrl_name = KBUILD_MODNAME,
+	.pinctrl_owner = THIS_MODULE,
+	.pins = pinctrl_pins,
+	.num_pins = ARRAY_SIZE(pinctrl_pins),
+	.grps = pinctrl_groups,
+	.num_grps = ARRAY_SIZE(pinctrl_groups),
+	.funcs = pinctrl_funcs,
+	.num_funcs = ARRAY_SIZE(pinctrl_funcs),
+	.confs_info = {
+		[AIROHA_PINCTRL_CONFS_PULLUP] = {
+			.confs = pinctrl_pullup_conf,
+			.num_confs = ARRAY_SIZE(pinctrl_pullup_conf),
+		},
+		[AIROHA_PINCTRL_CONFS_PULLDOWN] = {
+			.confs = pinctrl_pulldown_conf,
+			.num_confs = ARRAY_SIZE(pinctrl_pulldown_conf),
+		},
+		[AIROHA_PINCTRL_CONFS_DRIVE_E2] = {
+			.confs = pinctrl_drive_e2_conf,
+			.num_confs = ARRAY_SIZE(pinctrl_drive_e2_conf),
+		},
+		[AIROHA_PINCTRL_CONFS_DRIVE_E4] = {
+			.confs = pinctrl_drive_e4_conf,
+			.num_confs = ARRAY_SIZE(pinctrl_drive_e4_conf),
+		},
+		[AIROHA_PINCTRL_CONFS_PCIE_RST_OD] = {
+			.confs = pinctrl_pcie_rst_od_conf,
+			.num_confs = ARRAY_SIZE(pinctrl_pcie_rst_od_conf),
+		},
+	},
+};
+
+static const struct of_device_id airoha_pinctrl_of_match[] = {
+	{ .compatible = "airoha,an7563-pinctrl", .data = &pinctrl_match_data },
+	{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, airoha_pinctrl_of_match);
+
+static struct platform_driver airoha_pinctrl_driver = {
+	.probe = airoha_pinctrl_probe,
+	.driver = {
+		.name = "pinctrl-airoha-an7563",
+		.of_match_table = airoha_pinctrl_of_match,
+	},
+};
+module_platform_driver(airoha_pinctrl_driver);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Lorenzo Bianconi <lorenzo@kernel.org>");
+MODULE_AUTHOR("Benjamin Larsson <benjamin.larsson@genexis.eu>");
+MODULE_AUTHOR("Markus Gothe <markus.gothe@genexis.eu>");
+MODULE_DESCRIPTION("Pinctrl driver for Airoha AN7563 SoC");
-- 
2.53.0

Re: [PATCH v7 33/34] pinctrl: airoha: add support of an7563 SoC

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [Medium] Missing pinmux functions to restore default pad behaviors (I2C, SPI, UART) and failure to clear GPIO mode override bits when selecting alternate functions (MDIO, PNAND).
- [Medium] The `hsuart_cts_rts` pin group alters the mux state of the base HSUART pins without claiming them, causing potential pin conflicts and DT application order races.
--

--- Patch [33]: [PATCH v7 33/34] pinctrl: airoha: add support of an7563 SoC ---
commit fc95ee9a88a14501536fae31cd14f1346c7074c0
Author: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>

pinctrl: airoha: add support of an7563 SoC

This patch adds support of Airoha an7563 SoC pin controller.

> diff --git a/drivers/pinctrl/airoha/pinctrl-an7563.c b/drivers/pinctrl/airoha/pinctrl-an7563.c
> new file mode 100644
> --- /dev/null
> +++ b/drivers/pinctrl/airoha/pinctrl-an7563.c

[ ... ]

> +static const struct airoha_pinctrl_func_group mdio_func_group[] = {
> +	{
> +		.name = "mdio",
> +		.regmap[0] = {
> +			AIROHA_FUNC_MUX,
> +			REG_GPIO_PON_MODE,
> +			GPIO_SGMII_MDIO_MODE_MASK,
> +			GPIO_SGMII_MDIO_MODE_MASK
> +		},
> +		.regmap_size = 1,
> +	},
> +};

[Severity: Medium]
Does this configuration properly clear the GPIO mode override bits if the
bootloader left these pads in GPIO mode?

Looking at mdio_func_group, it only sets GPIO_SGMII_MDIO_MODE_MASK.
However, MDIO shares the I2C_SCL and I2C_SDA pads. If the bootloader
previously set I2C_SCL_GPIO_MODE_MASK and I2C_SDA_GPIO_MODE_MASK, they
would not be cleared here, potentially leaving the pads in GPIO mode
instead of routing them to MDIO.

> +static const struct airoha_pinctrl_func_group uart_func_group[] = {
> +	{
> +		.name = "hsuart",
> +		.regmap[0] = {
> +			AIROHA_FUNC_MUX,
> +			REG_GPIO_PON_MODE,
> +			GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK,
> +			GPIO_HSUART_MODE_MASK
> +		},
> +		.regmap_size = 1,
> +	},
> +	{
> +		.name = "hsuart_cts_rts",
> +		.regmap[0] = {
> +			AIROHA_FUNC_MUX,
> +			REG_GPIO_PON_MODE,
> +			GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK,
> +			GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK
> +		},
> +		.regmap_size = 1,
> +	},
> +};

[Severity: Medium]
Will applying the hsuart group silently disable CTS/RTS if it happens to be
evaluated after hsuart_cts_rts? The hsuart function clears the
GPIO_HSUART_CTS_RTS_MODE_MASK bit.

Additionally, hsuart_cts_rts modifies GPIO_HSUART_MODE_MASK (which routes
pins 16 and 17) despite those pins not being claimed by the group in
hsuart_cts_rts_pins. Could this allow the pinctrl core to mistakenly grant
pins 16 and 17 to another driver as GPIOs, creating a silent hardware
conflict?

[ ... ]

> +static const struct airoha_pinctrl_func_group pnand_func_group[] = {
> +	{
> +		.name = "pnand",
> +		.regmap[0] = {
> +			AIROHA_FUNC_MUX,
> +			REG_GPIO_PON_MODE,
> +			GPIO_PARALLEL_NAND_MODE_MASK,
> +			GPIO_PARALLEL_NAND_MODE_MASK
> +		},
> +		.regmap_size = 1,
> +	},
> +};

[Severity: Medium]
Is this missing the clearing of SPI GPIO mode override bits? Similar to the
MDIO function above, if the bootloader leaves the shared SPI pads in GPIO
mode, setting only GPIO_PARALLEL_NAND_MODE_MASK might not be enough to route
them to the PNAND controller.

[ ... ]

> +static const struct airoha_pinctrl_func pinctrl_funcs[] = {
> +	PINCTRL_FUNC_DESC("pon", pon),
> +	PINCTRL_FUNC_DESC("sipo", sipo),
> +	PINCTRL_FUNC_DESC("mdio", mdio),
> +	PINCTRL_FUNC_DESC("uart", uart),
> +	PINCTRL_FUNC_DESC("jtag", jtag),
> +	PINCTRL_FUNC_DESC("pcm", pcm),
> +	PINCTRL_FUNC_DESC("spi", spi),
> +	PINCTRL_FUNC_DESC("pnand", pnand),
> +	PINCTRL_FUNC_DESC("gpio", gpio),

[Severity: Medium]
Are we missing function descriptors to restore the default I2C and base
SPI/UART pad functions? Since there are no i2c, spi (base), or uart
functions registered here, it appears there is no way for Linux to clear the
GPIO override bits if the bootloader initialized them as GPIOs, which could
leave those hardware blocks unusable.

[ ... ]

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260727074234.3761170-1-mikhail.kshevetskiy@iopsys.eu?part=33

[PATCH v7 34/34] dt-bindings: pinctrl: airoha: add support of an7563 pin controller

[Mikhail Kshevetskiy]

This patch adds device tree binding schema for Airoha AN7563 SoC pin
controller.

Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
---
 .../pinctrl/airoha,an7563-pinctrl.yaml        | 348 ++++++++++++++++++
 1 file changed, 348 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/airoha,an7563-pinctrl.yaml

diff --git a/Documentation/devicetree/bindings/pinctrl/airoha,an7563-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/airoha,an7563-pinctrl.yaml
new file mode 100644
index 0000000000000..e626d34661285
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/airoha,an7563-pinctrl.yaml
@@ -0,0 +1,348 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/airoha,an7563-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Airoha AN7563 Pin Controller
+
+maintainers:
+  - Lorenzo Bianconi <lorenzo@kernel.org>
+
+description:
+  The Airoha's AN7563 Pin controller is used to control SoC pins.
+
+properties:
+  compatible:
+    const: airoha,an7563-pinctrl
+
+  interrupts:
+    maxItems: 1
+
+  gpio-controller: true
+
+  '#gpio-cells':
+    const: 2
+
+  gpio-ranges:
+    maxItems: 1
+
+  interrupt-controller: true
+
+  '#interrupt-cells':
+    const: 2
+
+allOf:
+  - $ref: pinctrl.yaml#
+
+required:
+  - compatible
+  - interrupts
+  - gpio-controller
+  - "#gpio-cells"
+  - interrupt-controller
+  - "#interrupt-cells"
+
+patternProperties:
+  '-pins$':
+    type: object
+
+    patternProperties:
+      '^mux(-|$)':
+        type: object
+
+        description:
+          pinmux configuration nodes.
+
+        $ref: /schemas/pinctrl/pinmux-node.yaml
+
+        properties:
+          function:
+            description:
+              A string containing the name of the function to mux to the group.
+            enum: [pon, sipo, mdio, uart, jtag, pcm, spi, pnand, gpio,
+                   pcie_reset, pwm, phy1_led0, phy2_led0, phy3_led0,
+                   phy4_led0, phy1_led1, phy2_led1, phy3_led1, phy4_led1]
+
+          groups:
+            description:
+              An array of strings. Each string contains the name of a group.
+
+        required:
+          - function
+          - groups
+
+        allOf:
+          - if:
+              properties:
+                function:
+                  const: pon
+            then:
+              properties:
+                groups:
+                  enum: [pon]
+          - if:
+              properties:
+                function:
+                  const: sipo
+            then:
+              properties:
+                groups:
+                  enum: [sipo, sipo_rclk]
+          - if:
+              properties:
+                function:
+                  const: mdio
+            then:
+              properties:
+                groups:
+                  enum: [mdio]
+          - if:
+              properties:
+                function:
+                  const: uart
+            then:
+              properties:
+                groups:
+                  items:
+                    enum: [hsuart, hsuart_cts_rts]
+                  maxItems: 2
+          - if:
+              properties:
+                function:
+                  const: jtag
+            then:
+              properties:
+                groups:
+                  enum: [jtag_udi, jtag_dfd]
+          - if:
+              properties:
+                function:
+                  const: pcm
+            then:
+              properties:
+                groups:
+                  enum: [pcm1, pcm2]
+          - if:
+              properties:
+                function:
+                  const: spi
+            then:
+              properties:
+                groups:
+                  items:
+                    enum: [spi_quad, spi_cs1]
+                  maxItems: 2
+          - if:
+              properties:
+                function:
+                  const: pnand
+            then:
+              properties:
+                groups:
+                  enum: [pnand]
+          - if:
+              properties:
+                function:
+                  const: gpio
+            then:
+              properties:
+                groups:
+                  enum: [gpio28, gpio29, gpio30, gpio31, gpio32,
+                         gpio33, gpio34, gpio35, gpio36, gpio37]
+          - if:
+              properties:
+                function:
+                  const: pcie_reset
+            then:
+              properties:
+                groups:
+                  enum: [pcie_reset0, pcie_reset1]
+          - if:
+              properties:
+                function:
+                  const: pwm
+            then:
+              properties:
+                groups:
+                  enum: [gpio0, gpio1, gpio2, gpio3, gpio4, gpio5, gpio6,
+                         gpio7, gpio8, gpio9, gpio10, gpio11, gpio12, gpio13,
+                         gpio14, gpio15, gpio16, gpio17, gpio18, gpio19,
+                         gpio20, gpio21, gpio22, gpio23, gpio24, gpio25,
+                         gpio26, gpio27, gpio28, gpio29, gpio30, gpio31,
+                         gpio36, gpio37]
+          - if:
+              properties:
+                function:
+                  const: phy1_led0
+            then:
+              properties:
+                groups:
+                  enum: [gpio8, gpio9, gpio10, gpio11]
+          - if:
+              properties:
+                function:
+                  const: phy2_led0
+            then:
+              properties:
+                groups:
+                  enum: [gpio8, gpio9, gpio10, gpio11]
+          - if:
+              properties:
+                function:
+                  const: phy3_led0
+            then:
+              properties:
+                groups:
+                  enum: [gpio8, gpio9, gpio10, gpio11]
+          - if:
+              properties:
+                function:
+                  const: phy4_led0
+            then:
+              properties:
+                groups:
+                  enum: [gpio8, gpio9, gpio10, gpio11]
+          - if:
+              properties:
+                function:
+                  const: phy1_led1
+            then:
+              properties:
+                groups:
+                  enum: [gpio4, gpio5, gpio6, gpio7]
+          - if:
+              properties:
+                function:
+                  const: phy2_led1
+            then:
+              properties:
+                groups:
+                  enum: [gpio4, gpio5, gpio6, gpio7]
+          - if:
+              properties:
+                function:
+                  const: phy3_led1
+            then:
+              properties:
+                groups:
+                  enum: [gpio4, gpio5, gpio6, gpio7]
+          - if:
+              properties:
+                function:
+                  const: phy4_led1
+            then:
+              properties:
+                groups:
+                  enum: [gpio4, gpio5, gpio6, gpio7]
+
+        additionalProperties: false
+
+      '^conf(-|$)':
+        type: object
+
+        description:
+          pinconf configuration nodes.
+
+        $ref: /schemas/pinctrl/pincfg-node.yaml
+
+        properties:
+          pins:
+            description:
+              An array of strings. Each string contains the name of a pin.
+            items:
+              enum: [gpio0, gpio1, gpio2, gpio3, gpio4, gpio5, gpio6, gpio7,
+                     gpio8, gpio9, gpio10, gpio11, gpio12, gpio13, gpio14,
+                     gpio15, gpio16, gpio17, gpio18, gpio19, gpio20, gpio21,
+                     gpio22, gpio23, gpio24, gpio25, gpio26, gpio27,
+                     pcie_reset0, pcie_reset1, i2c_scl, i2c_sda, spi_clk,
+                     spi_cs, spi_mosi, spi_miso, uart_txd, uart_rxd]
+            minItems: 1
+            maxItems: 38
+
+          bias-disable: true
+
+          bias-pull-up: true
+
+          bias-pull-down: true
+
+          input-enable: true
+
+          output-enable: true
+
+          output-low: true
+
+          output-high: true
+
+          drive-open-drain: true
+
+          drive-strength:
+            description:
+              Selects the drive strength for MIO pins, in mA.
+            enum: [2, 4, 6, 8]
+
+        required:
+          - pins
+
+        additionalProperties: false
+
+    additionalProperties: false
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+    pinctrl {
+      compatible = "airoha,an7563-pinctrl";
+
+      interrupt-parent = <&gic>;
+      interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+
+      gpio-controller;
+      #gpio-cells = <2>;
+
+      interrupt-controller;
+      #interrupt-cells = <2>;
+
+      pcie1-rst-pins {
+        conf {
+          pins = "pcie_reset1";
+          drive-open-drain = <1>;
+        };
+      };
+
+      pwm-pins {
+        mux {
+          function = "pwm";
+          groups = "gpio18";
+        };
+      };
+
+      spi-pins {
+        mux {
+          function = "spi";
+          groups = "spi_quad", "spi_cs1";
+        };
+      };
+
+      hsuart-pins {
+        mux {
+          function = "uart";
+          groups = "hsuart", "hsuart_cts_rts";
+        };
+      };
+
+      mdio-pins {
+        mux {
+          function = "mdio";
+          groups = "mdio";
+        };
+
+        conf {
+          pins = "gpio2";
+          output-enable;
+        };
+      };
+    };
-- 
2.53.0

Re: [PATCH v7 34/34] dt-bindings: pinctrl: airoha: add support of an7563 pin controller

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider:
- [Medium] The binding lacks a parent syscon relationship or `reg` property, and omits the required `airoha,chip-scu` phandle property.
- [Low] Invalid and deprecated integer value assignment to the boolean property `drive-open-drain` in the device tree example.
- [Low] Incorrect JSON Schema array constraints for the `groups` property in most multiplexing conditional blocks.
--

--- Patch [34]: [PATCH v7 34/34] dt-bindings: pinctrl: airoha: add support of an7563 pin controller ---
commit fedf510207cace3632698b52e7e3162470e8e08a
Author: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>

dt-bindings: pinctrl: airoha: add support of an7563 pin controller

This patch adds device tree binding schema for Airoha AN7563 SoC pin
controller.

> diff --git a/Documentation/devicetree/bindings/pinctrl/airoha,an7563-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/airoha,an7563-pinctrl.yaml
> new file mode 100644
> index 0000000000000..e626d34661285
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pinctrl/airoha,an7563-pinctrl.yaml
> @@ -0,0 +1,348 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pinctrl/airoha,an7563-pinctrl.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Airoha AN7563 Pin Controller
> +
> +maintainers:
> +  - Lorenzo Bianconi <lorenzo@kernel.org>
> +
> +description:
> +  The Airoha's AN7563 Pin controller is used to control SoC pins.
> +
> +properties:
> +  compatible:
> +    const: airoha,an7563-pinctrl

[Severity: Medium]
Does the schema need to document the parent-child syscon requirement and the
airoha,chip-scu property?

The driver relies on device_node_to_regmap(dev->parent->of_node), meaning
the pin controller node needs to be instantiated as a child of a syscon
node.

It also expects an airoha,chip-scu phandle property in the pin
controller node. Both the schema definition and the example omit these
requirements.

> [ ... ]
> +        allOf:
> +          - if:
> +              properties:
> +                function:
> +                  const: pon
> +            then:
> +              properties:
> +                groups:
> +                  enum: [pon]
> +          - if:
> +              properties:
> +                function:
> +                  const: sipo
> +            then:
> +              properties:
> +                groups:
> +                  enum: [sipo, sipo_rclk]

[Severity: Low]
Is this enum constraint structurally correct for the array?

Since groups is defined as a string-array via
/schemas/pinctrl/pinmux-node.yaml, applying the enum constraint directly to
the array instance means the entire array object must equal one of those
scalar strings, which will fail schema validation.

Should this use the items keyword to restrict the array elements, similar to
how it was done for the uart and spi functions? For example:
  items:
    enum: [sipo, sipo_rclk]

> [ ... ]
> +examples:
> +  - |
> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +    pinctrl {
> +      compatible = "airoha,an7563-pinctrl";

[Severity: Medium]
Will this example node fail to probe if developers use it as a template?

As mentioned above, the driver expects this node to be a child of a syscon
node, but the example shows it as a standalone top-level node.

If developers use this as a top-level node, device_node_to_regmap() will fail
and the driver will abort probing.

> +
> +      interrupt-parent = <&gic>;
> +      interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
> +
> +      gpio-controller;
> +      #gpio-cells = <2>;
> +
> +      interrupt-controller;
> +      #interrupt-cells = <2>;
> +
> +      pcie1-rst-pins {
> +        conf {
> +          pins = "pcie_reset1";
> +          drive-open-drain = <1>;

[Severity: Low]
Is it intentional to assign an integer value to drive-open-drain?

The core pincfg-node.yaml schema defines drive-open-drain as a boolean
property, which should be declared merely by its presence (i.e.,
drive-open-drain;).

Assigning it a value of <1> violates the schema and causes dt_binding_check
to throw a type error.

> +        };
> +      };

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260727074234.3761170-1-mikhail.kshevetskiy@iopsys.eu?part=34