Re: [PATCH v2 01/14] dt-bindings: phy: Document the Qualcomm IPQ5332 UNIPHY USB Super-speed PHY

[Krzysztof Kozlowski <krzk@kernel.org>]

On Wed, Aug 12, 2026 at 01:34:36PM +0400, George Moussalem wrote:
> From: Praveenkumar I <quic_ipkumar@quicinc.com>
> 
> Document the Qualcomm USB3 22ull UNIPHY present in the IPQ5018 and
> IPQ5332 SoCs.
> 
> Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com>
> Signed-off-by: George Moussalem <george.moussalem@outlook.com>
> ---
>  .../phy/qcom,ipq5332-uniphy-usb-ss-phy.yaml        | 111 +++++++++++++++++++++
>  1 file changed, 111 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/phy/qcom,ipq5332-uniphy-usb-ss-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,ipq5332-uniphy-usb-ss-phy.yaml
> new file mode 100644
> index 000000000000..cc9eccac51dd
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/qcom,ipq5332-uniphy-usb-ss-phy.yaml
> @@ -0,0 +1,111 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/phy/qcom,ipq5332-uniphy-usb-ss-phy.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm UNIPHY USB Super-Speed 22ull PHY
> +
> +maintainers:
> +  - Praveenkumar I <quic_ipkumar@quicinc.com>
> +  - Varadarajan Narayanan <quic_varada@quicinc.com>
> +
> +description:
> +  USB Super-Speed UNIPHY found in Qualcomm IPQ5018 & IPQ5332 SoCs.
> +
> +properties:
> +  compatible:
> +    enum:
> +      - qcom,ipq5018-uniphy-usb-ss-phy
> +      - qcom,ipq5332-uniphy-usb-ss-phy
> +
> +  reg:
> +    maxItems: 1
> +
> +  clocks:
> +    minItems: 2
> +    maxItems: 3
> +
> +  resets:
> +    maxItems: 1
> +
> +  vdd-supply:
> +    description:
> +      Phandle to 5V regulator supply to PHY digital circuit.
> +
> +  qcom,phy-usb-mux-sel:
> +    description: |

Do not need '|' unless you need to preserve formatting.

> +      Mux selection for USB PHY. The USB3 and PCIe PHY pads are muxed and the
> +      mux selection is done via a register in TCSR syscon.

git grep qcom,phy-usb-mux-sel gave me zero, so I wonder how is it done
from the PCI side.

> +    $ref: /schemas/types.yaml#/definitions/phandle-array
> +    items:
> +      - items:
> +          - description: phandle of TCSR syscon
> +          - description: offset of PHY mux selection register
> +
> +  "#clock-cells":
> +    const: 0
> +
> +  "#phy-cells":
> +    const: 0
> +
> +required:
> +  - compatible
> +  - reg
> +  - clocks
> +  - resets
> +  - vdd-supply
> +  - qcom,phy-usb-mux-sel
> +  - "#clock-cells"
> +  - "#phy-cells"
> +


> +additionalProperties: false

This goes after "allOf:" block.

> +
> +allOf:
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            enum:
> +              - qcom,ipq5018-uniphy-usb-ss-phy
> +    then:
> +      properties:
> +        clocks:
> +          items:
> +            - description: USB3 PHY CFG AHB clock
> +            - description: USB3 pipe clock
> +
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            enum:
> +              - qcom,ipq5332-uniphy-usb-ss-phy
> +    then:
> +      properties:
> +        clocks:
> +          items:
> +            - description: Shared PCIe/USB3 PHY AHB clock
> +            - description: USB3 PHY CFG AHB clock
> +            - description: USB3 pipe clock
> +
> +examples:
> +  - |
> +    #include <dt-bindings/clock/qcom,ipq5332-gcc.h>
> +
> +    phy@4b0000 {
> +        compatible = "qcom,ipq5332-uniphy-usb-ss-phy";
> +        reg = <0x4b0000 0x800>;

That is the same address as PCI PHY, so you have one device, not two.

Best regards,
Krzysztof