[PATCH 01/15] cxl/core: Add CXL.cache device struct

[Ben Cheatham <Benjamin.Cheatham@amd.com>]

Add a new CXL.cache device (struct cxl_cachedev) that is the cache
analogue to struct cxl_memdev. This device will be created by CXL type
1 & 2 endpoint drivers to enable and manage the cache capabilities of
the underlying PCIe device via the CXL core.

Signed-off-by: Ben Cheatham <Benjamin.Cheatham@amd.com>
---
 drivers/cxl/core/Makefile   |   1 +
 drivers/cxl/core/cachedev.c | 119 ++++++++++++++++++++++++++++++++++++
 drivers/cxl/core/port.c     |   3 +
 drivers/cxl/cxl.h           |   1 +
 drivers/cxl/cxlcache.h      |  37 +++++++++++
 include/cxl/cxl.h           |   2 +
 6 files changed, 163 insertions(+)
 create mode 100644 drivers/cxl/core/cachedev.c
 create mode 100644 drivers/cxl/cxlcache.h

diff --git a/drivers/cxl/core/Makefile b/drivers/cxl/core/Makefile
index ce7213818d3c..f51575abe5af 100644
--- a/drivers/cxl/core/Makefile
+++ b/drivers/cxl/core/Makefile
@@ -9,6 +9,7 @@ cxl_core-y := port.o
 cxl_core-y += pmem.o
 cxl_core-y += regs.o
 cxl_core-y += memdev.o
+cxl_core-y += cachedev.o
 cxl_core-y += mbox.o
 cxl_core-y += pci.o
 cxl_core-y += hdm.o
diff --git a/drivers/cxl/core/cachedev.c b/drivers/cxl/core/cachedev.c
new file mode 100644
index 000000000000..3a7a60165f62
--- /dev/null
+++ b/drivers/cxl/core/cachedev.c
@@ -0,0 +1,119 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/* Copyright (C) 2026 Advanced Micro Devices, Inc. */
+#include <linux/device.h>
+#include <linux/pci.h>
+#include <cxlcache.h>
+
+static DEFINE_IDA(cxl_cachedev_ida);
+
+static void cxl_cachedev_release(struct device *dev)
+{
+	struct cxl_cachedev *cxlcd = to_cxl_cachedev(dev);
+
+	ida_free(&cxl_cachedev_ida, cxlcd->id);
+	kfree(cxlcd);
+}
+
+static void cxl_cachedev_unregister(void *dev)
+{
+	struct cxl_cachedev *cxlcd = dev;
+	struct cxl_dev_state *cxlds = cxlcd->cxlds;
+
+	cxlcd->cxlds = NULL;
+	cxlds->cxlcd = NULL;
+	device_del(&cxlcd->dev);
+	put_device(&cxlcd->dev);
+}
+
+static char *cxl_cachedev_devnode(const struct device *dev, umode_t *mode,
+				  kuid_t *uid, kgid_t *gid)
+{
+	return kasprintf(GFP_KERNEL, "cxl/%s", dev_name(dev));
+}
+
+static const struct device_type cxl_cachedev_type = {
+	.name = "cxl_cachedev",
+	.release = cxl_cachedev_release,
+	.devnode = cxl_cachedev_devnode,
+};
+
+bool is_cxl_cachedev(const struct device *dev)
+{
+	return dev->type == &cxl_cachedev_type;
+}
+EXPORT_SYMBOL_NS_GPL(is_cxl_cachedev, "CXL");
+
+static struct lock_class_key cxl_cachedev_key;
+
+static struct cxl_cachedev *cxl_cachedev_alloc(struct cxl_dev_state *cxlds)
+{
+	struct device *dev;
+	int rc;
+
+	struct cxl_cachedev *cxlcd __free(kfree) =
+		kzalloc(sizeof(*cxlcd), GFP_KERNEL);
+	if (!cxlcd)
+		return ERR_PTR(-ENOMEM);
+
+	rc = ida_alloc(&cxl_cachedev_ida, GFP_KERNEL);
+	if (rc < 0)
+		return ERR_PTR(rc);
+
+	cxlcd->id = rc;
+	cxlcd->depth = -1;
+	cxlcd->endpoint = ERR_PTR(-ENODEV);
+
+	dev = &cxlcd->dev;
+	device_initialize(dev);
+	lockdep_set_class(&dev->mutex, &cxl_cachedev_key);
+	dev->parent = cxlds->dev;
+	dev->bus = &cxl_bus_type;
+	dev->type = &cxl_cachedev_type;
+	device_set_pm_not_required(dev);
+
+	return_ptr(cxlcd);
+}
+
+DEFINE_FREE(put_cxlcd, struct cxl_cachedev *,
+	    if (!IS_ERR_OR_NULL(_T)) put_device(&_T->dev));
+
+static struct cxl_cachedev *cxl_cachedev_autoremove(struct cxl_cachedev *cxlcd)
+{
+	int rc;
+
+	rc = devm_add_action_or_reset(cxlcd->cxlds->dev,
+				      cxl_cachedev_unregister, cxlcd);
+	if (rc)
+		return ERR_PTR(rc);
+
+	return cxlcd;
+}
+
+struct cxl_cachedev *__devm_cxl_add_cachedev(struct cxl_dev_state *cxlds,
+					     void *attach)
+{
+	struct device *dev;
+	int rc;
+
+	struct cxl_cachedev *cxlcd __free(put_cxlcd) =
+		cxl_cachedev_alloc(cxlds);
+	if (IS_ERR(cxlcd))
+		return cxlcd;
+
+	dev = &cxlcd->dev;
+	rc = dev_set_name(dev, "cache%d", cxlcd->id);
+	if (rc)
+		return ERR_PTR(rc);
+
+	cxlcd->cxlds = cxlds;
+	cxlds->cxlcd = cxlcd;
+
+	rc = device_add(dev);
+	if (rc) {
+		cxlds->cxlcd = NULL;
+		return ERR_PTR(rc);
+	}
+
+	return cxl_cachedev_autoremove(no_free_ptr(cxlcd));
+}
+EXPORT_SYMBOL_NS_GPL(__devm_cxl_add_cachedev, "CXL");
diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
index 625e4aa427db..c0f066c0d3d1 100644
--- a/drivers/cxl/core/port.c
+++ b/drivers/cxl/core/port.c
@@ -12,6 +12,7 @@
 #include <linux/node.h>
 #include <cxl/einj.h>
 #include <cxl/pci.h>
+#include <cxlcache.h>
 #include <cxlmem.h>
 #include <cxlpci.h>
 #include <cxl.h>
@@ -78,6 +79,8 @@ static int cxl_device_id(const struct device *dev)
 		return CXL_DEVICE_REGION;
 	if (dev->type == &cxl_pmu_type)
 		return CXL_DEVICE_PMU;
+	if (is_cxl_cachedev(dev))
+		return CXL_DEVICE_ACCELERATOR;
 	return 0;
 }
 
diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
index cab8ce39f465..72d2686a408b 100644
--- a/drivers/cxl/cxl.h
+++ b/drivers/cxl/cxl.h
@@ -853,6 +853,7 @@ void cxl_driver_unregister(struct cxl_driver *cxl_drv);
 #define CXL_DEVICE_PMEM_REGION		7
 #define CXL_DEVICE_DAX_REGION		8
 #define CXL_DEVICE_PMU			9
+#define CXL_DEVICE_ACCELERATOR		10
 
 #define MODULE_ALIAS_CXL(type) MODULE_ALIAS("cxl:t" __stringify(type) "*")
 #define CXL_MODALIAS_FMT "cxl:t%d"
diff --git a/drivers/cxl/cxlcache.h b/drivers/cxl/cxlcache.h
new file mode 100644
index 000000000000..6ca887e078a1
--- /dev/null
+++ b/drivers/cxl/cxlcache.h
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+#ifndef __CXL_CACHE_H__
+#define __CXL_CACHE_H__
+
+#include "cxl.h"
+
+/**
+ * struct cxl_cachedev - CXL bus object representing the cache capabilities of
+ * a CXL device
+ * @dev: driver core device object
+ * @cxlds: device state backing this device
+ * @endpoint: connection to the CXL port topology for this device
+ * @id: id number of this cachedev instance
+ * @depth: endpoint port depth in hierarchy
+ */
+struct cxl_cachedev {
+	struct device dev;
+	struct cxl_dev_state *cxlds;
+	struct cxl_port *endpoint;
+	int id;
+	int depth;
+};
+
+bool is_cxl_cachedev(const struct device *dev);
+
+static inline struct cxl_cachedev *to_cxl_cachedev(struct device *dev)
+{
+	if (dev_WARN_ONCE(dev, !is_cxl_cachedev(dev),
+			  "to_cxl_cachedev() called on non cxl_cachedev device"))
+		return NULL;
+
+	return container_of(dev, struct cxl_cachedev, dev);
+}
+
+struct cxl_cachedev *__devm_cxl_add_cachedev(struct cxl_dev_state *cxlds,
+					     void *attach);
+#endif
diff --git a/include/cxl/cxl.h b/include/cxl/cxl.h
index 802b143de83d..f0077ffa0d91 100644
--- a/include/cxl/cxl.h
+++ b/include/cxl/cxl.h
@@ -158,6 +158,7 @@ struct cxl_dpa_partition {
  *
  * @dev: The device associated with this CXL state
  * @cxlmd: The device representing the CXL.mem capabilities of @dev
+ * @cxlcd: The device representing the CXL.cache capabilities of @dev
  * @reg_map: component and ras register mapping parameters
  * @regs: Parsed register blocks
  * @cxl_dvsec: Offset to the PCIe device DVSEC
@@ -175,6 +176,7 @@ struct cxl_dev_state {
 	/* public for Type2 drivers */
 	struct device *dev;
 	struct cxl_memdev *cxlmd;
+	struct cxl_cachedev *cxlcd;
 
 	/* private for Type2 drivers */
 	struct cxl_register_map reg_map;
-- 
2.53.0