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From: sashiko-bot@kernel.org
To: "Ben Cheatham" <Benjamin.Cheatham@amd.com>
Cc: linux-cxl@vger.kernel.org
Subject: Re: [PATCH 05/15] cxl/port: Split endpoint port probe on device type
Date: Wed, 23 Sep 2026 17:46:11 +0000	[thread overview]
Message-ID: <20260923174611.9D9401F000FF@smtp.kernel.org> (raw)
In-Reply-To: <20260923173342.5584-6-Benjamin.Cheatham@amd.com>

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] cxl/port: type mismatch due to implicit pointer cast in schedule_detach()
--

commit 4ffbc8dadee1abe8b3c2deec219a795c0d6ff353
Author: Ben Cheatham <Benjamin.Cheatham@amd.com>

cxl/port: Split endpoint port probe on device type

This commit splits endpoint port probe on device type and refactors
dport RAS set up into a common routine. CXL.cache devices do not support
or need all of the set up done by endpoint port probe for CXL.mem devices.

> diff --git a/drivers/cxl/port.c b/drivers/cxl/port.c
> index edf0ff759fbf6..7c93fabfb0956 100644
> --- a/drivers/cxl/port.c
> +++ b/drivers/cxl/port.c
[ ... ]
> @@ -26,9 +27,13 @@
>   * PCIe topology.
>   */
>  
> -static void schedule_detach(void *cxlmd)
> +static void schedule_detach(void *ep_dev)
>  {
> -	schedule_cxl_memdev_detach(cxlmd);
> +	if (is_cxl_memdev(ep_dev))
> +		schedule_cxl_memdev_detach(ep_dev);
> +
> +	if (is_cxl_cachedev(ep_dev))
> +		schedule_cxl_cachedev_detach(ep_dev);
>  }

[Severity: Low]
Does this code inadvertently bypass type safety by passing ep_dev (which holds
a struct device *) directly to schedule_cxl_memdev_detach() and
schedule_cxl_cachedev_detach()?

These functions expect struct cxl_memdev * and struct cxl_cachedev *
respectively. While this avoids memory corruption right now because the dev
member is located at offset 0 in both container structures, it relies on an
implicit pointer cast.

Would it be better to use to_cxl_memdev() and to_cxl_cachedev() to explicitly
resolve the container structs before passing them?

[ ... ]
> @@ -151,6 +141,27 @@ static int cxl_endpoint_port_probe(struct cxl_port *port)
[ ... ]
> +static int cxl_mem_endpoint_port_probe(struct cxl_port *port)
> +{
> +	struct cxl_memdev *cxlmd = to_cxl_memdev(port->uport_dev);
> +	int rc;
> +
> +	/* Cache the data early to ensure is_visible() works */
> +	read_cdat_data(port);
> +	cxl_endpoint_parse_cdat(port);
> +
> +	get_device(&cxlmd->dev);
> +	rc = devm_add_action_or_reset(&port->dev, schedule_detach, &cxlmd->dev);

[Severity: Low]
Is this where the mismatch originates? The devres data queued for
schedule_detach is explicitly set to a struct device * here, confirming
what is passed when the callback executes.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260923173342.5584-1-Benjamin.Cheatham@amd.com?part=5

  reply	other threads:[~2026-09-23 17:46 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-09-23 17:33 [PATCH 00/15] Add initial CXL.cache support Ben Cheatham
2026-09-23 17:33 ` [PATCH 01/15] cxl/core: Add CXL.cache device struct Ben Cheatham
2026-09-23 17:41   ` sashiko-bot
2026-09-23 17:33 ` [PATCH 02/15] cxl/cache: Add cxl_cache driver Ben Cheatham
2026-09-23 17:49   ` sashiko-bot
2026-09-23 17:33 ` [PATCH 03/15] cxl/core: Change cxl_ep_load() to use device pointer parameter Ben Cheatham
2026-09-23 17:33 ` [PATCH 04/15] cxl/core: Update devm_cxl_enumerate_ports() for cxl_cachedevs Ben Cheatham
2026-09-23 17:33 ` [PATCH 05/15] cxl/port: Split endpoint port probe on device type Ben Cheatham
2026-09-23 17:46   ` sashiko-bot [this message]
2026-09-23 17:33 ` [PATCH 06/15] cxl/core: Update devm_cxl_add_endpoint() for cxl_cachedevs Ben Cheatham
2026-09-23 17:51   ` sashiko-bot
2026-09-23 17:33 ` [PATCH 07/15] cxl/cache: Verify port hierarchy has CXL.cache enabled Ben Cheatham
2026-09-23 17:33 ` [PATCH 08/15] cxl/core, cache: Add Cache ID register probing and init Ben Cheatham
2026-09-23 17:46   ` sashiko-bot
2026-09-23 17:33 ` [PATCH 09/15] cxl/core: Add Cache ID verification Ben Cheatham
2026-09-23 17:49   ` sashiko-bot
2026-09-23 17:33 ` [PATCH 10/15] cxl/core: Add Cache ID allocation Ben Cheatham
2026-09-23 17:49   ` sashiko-bot
2026-09-23 17:33 ` [PATCH 11/15] cxl/core: Add support for HDM-D cache id programming Ben Cheatham
2026-09-23 17:51   ` sashiko-bot
2026-09-23 17:33 ` [PATCH 12/15] cxl/cache: Add snoop filter creation and set up Ben Cheatham
2026-09-23 17:50   ` sashiko-bot
2026-09-23 17:33 ` [PATCH 13/15] cxl/cache: Add snoop filter allocation Ben Cheatham
2026-09-23 17:58   ` sashiko-bot
2026-09-23 17:33 ` [PATCH 14/15] iommu, cxl: Configure IOMMU for CXL.cache Ben Cheatham
2026-09-23 17:57   ` sashiko-bot
2026-09-23 17:33 ` [PATCH 15/15] cxl/cache: Enable CXL.cache on successful probe Ben Cheatham
2026-09-23 17:35 ` [PATCH 00/15] Add initial CXL.cache support Cheatham, Benjamin

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