From: sashiko-bot@kernel.org
To: "Ben Cheatham" <Benjamin.Cheatham@amd.com>
Cc: linux-cxl@vger.kernel.org
Subject: Re: [PATCH 06/15] cxl/core: Update devm_cxl_add_endpoint() for cxl_cachedevs
Date: Wed, 23 Sep 2026 17:51:50 +0000 [thread overview]
Message-ID: <20260923175151.4E3091F000FF@smtp.kernel.org> (raw)
In-Reply-To: <20260923173342.5584-7-Benjamin.Cheatham@amd.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] cxl: implicit cast from void* to struct bypassing container_of in schedule_detach
--
commit e4fe9279629e13947567c92e9190b5eeaa65a71a
Author: Ben Cheatham <Benjamin.Cheatham@amd.com>
cxl/core: Update devm_cxl_add_endpoint() for cxl_cachedevs
Update devm_cxl_add_endpoint() to allow for cxl_cachedevs as well as
cxl_memdevs. Add cxl_cachedevs to the port heirarchy.
> diff --git a/drivers/cxl/port.c b/drivers/cxl/port.c
> index 99cf77b6b6990..44d978d4205a2 100644
> --- a/drivers/cxl/port.c
> +++ b/drivers/cxl/port.c
> @@ -26,9 +27,13 @@
> * PCIe topology.
> */
>
> -static void schedule_detach(void *cxlmd)
> +static void schedule_detach(void *ep_dev)
> {
> - schedule_cxl_memdev_detach(cxlmd);
> + if (is_cxl_memdev(ep_dev))
> + schedule_cxl_memdev_detach(ep_dev);
> +
> + if (is_cxl_cachedev(ep_dev))
> + schedule_cxl_cachedev_detach(ep_dev);
[Severity: Low]
In schedule_detach(), does this code implicitly cast the void pointer
representing a struct device directly to incompatible struct types?
Because ep_dev is a void pointer, passing it to schedule_cxl_memdev_detach()
and schedule_cxl_cachedev_detach() casts it to struct cxl_memdev * and
struct cxl_cachedev * without using the proper container_of() wrappers
like to_cxl_memdev() and to_cxl_cachedev().
While this works currently because struct device is the first member of these
structures, could this regression cause memory corruption if the struct
layouts ever change?
> }
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260923173342.5584-1-Benjamin.Cheatham@amd.com?part=6
next prev parent reply other threads:[~2026-09-23 17:51 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-23 17:33 [PATCH 00/15] Add initial CXL.cache support Ben Cheatham
2026-09-23 17:33 ` [PATCH 01/15] cxl/core: Add CXL.cache device struct Ben Cheatham
2026-09-23 17:41 ` sashiko-bot
2026-09-23 17:33 ` [PATCH 02/15] cxl/cache: Add cxl_cache driver Ben Cheatham
2026-09-23 17:49 ` sashiko-bot
2026-09-23 17:33 ` [PATCH 03/15] cxl/core: Change cxl_ep_load() to use device pointer parameter Ben Cheatham
2026-09-23 17:33 ` [PATCH 04/15] cxl/core: Update devm_cxl_enumerate_ports() for cxl_cachedevs Ben Cheatham
2026-09-23 17:33 ` [PATCH 05/15] cxl/port: Split endpoint port probe on device type Ben Cheatham
2026-09-23 17:46 ` sashiko-bot
2026-09-23 17:33 ` [PATCH 06/15] cxl/core: Update devm_cxl_add_endpoint() for cxl_cachedevs Ben Cheatham
2026-09-23 17:51 ` sashiko-bot [this message]
2026-09-23 17:33 ` [PATCH 07/15] cxl/cache: Verify port hierarchy has CXL.cache enabled Ben Cheatham
2026-09-23 17:33 ` [PATCH 08/15] cxl/core, cache: Add Cache ID register probing and init Ben Cheatham
2026-09-23 17:46 ` sashiko-bot
2026-09-23 17:33 ` [PATCH 09/15] cxl/core: Add Cache ID verification Ben Cheatham
2026-09-23 17:49 ` sashiko-bot
2026-09-23 17:33 ` [PATCH 10/15] cxl/core: Add Cache ID allocation Ben Cheatham
2026-09-23 17:49 ` sashiko-bot
2026-09-23 17:33 ` [PATCH 11/15] cxl/core: Add support for HDM-D cache id programming Ben Cheatham
2026-09-23 17:51 ` sashiko-bot
2026-09-23 17:33 ` [PATCH 12/15] cxl/cache: Add snoop filter creation and set up Ben Cheatham
2026-09-23 17:50 ` sashiko-bot
2026-09-23 17:33 ` [PATCH 13/15] cxl/cache: Add snoop filter allocation Ben Cheatham
2026-09-23 17:58 ` sashiko-bot
2026-09-23 17:33 ` [PATCH 14/15] iommu, cxl: Configure IOMMU for CXL.cache Ben Cheatham
2026-09-23 17:57 ` sashiko-bot
2026-09-23 17:33 ` [PATCH 15/15] cxl/cache: Enable CXL.cache on successful probe Ben Cheatham
2026-09-23 17:35 ` [PATCH 00/15] Add initial CXL.cache support Cheatham, Benjamin
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