From: Ben Cheatham <Benjamin.Cheatham@amd.com>
To: <linux-cxl@vger.kernel.org>, <dave@stgolabs.net>,
<jic23@kernel.org>, <dave.jiang@intel.com>,
<alison.schofield@intel.com>
Cc: <linux-iommu@vger.kernel.org>, <benjamin.cheatham@amd.com>,
<terry.bowman@amd.com>, <robert.richter@amd.com>
Subject: [PATCH 03/15] cxl/core: Change cxl_ep_load() to use device pointer parameter
Date: Wed, 23 Sep 2026 12:33:30 -0500 [thread overview]
Message-ID: <20260923173342.5584-4-Benjamin.Cheatham@amd.com> (raw)
In-Reply-To: <20260923173342.5584-1-Benjamin.Cheatham@amd.com>
cxl_ep_load() currently takes a struct cxl_memdev pointer parameter to
find endpoint devices under a port. Change this paramater to use a
device pointer in preparation for adding cxl_cachedev devices to the
CXL port hierarchy.
No functional change intended.
Signed-off-by: Ben Cheatham <Benjamin.Cheatham@amd.com>
---
drivers/cxl/core/port.c | 4 ++--
drivers/cxl/core/region.c | 24 ++++++++++++------------
drivers/cxl/cxlmem.h | 4 ++--
drivers/cxl/port.c | 2 +-
4 files changed, 17 insertions(+), 17 deletions(-)
diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
index c0f066c0d3d1..6181ec730ec2 100644
--- a/drivers/cxl/core/port.c
+++ b/drivers/cxl/core/port.c
@@ -1504,7 +1504,7 @@ static int port_has_memdev(struct device *dev, const void *data)
if (port->depth != ctx->depth)
return 0;
- return !!cxl_ep_load(port, ctx->cxlmd);
+ return !!cxl_ep_load(port, &ctx->cxlmd->dev);
}
static void cxl_detach_ep(void *data)
@@ -1529,7 +1529,7 @@ static void cxl_detach_ep(void *data)
parent_port = to_cxl_port(port->dev.parent);
device_lock(&parent_port->dev);
device_lock(&port->dev);
- ep = cxl_ep_load(port, cxlmd);
+ ep = cxl_ep_load(port, &cxlmd->dev);
dev_dbg(&cxlmd->dev, "disconnect %s from %s\n",
ep ? dev_name(ep->ep) : "", dev_name(&port->dev));
cxl_ep_remove(port, ep);
diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c
index 27e63e6dab7c..a8ed7161296c 100644
--- a/drivers/cxl/core/region.c
+++ b/drivers/cxl/core/region.c
@@ -272,8 +272,8 @@ static void cxl_region_decode_reset(struct cxl_region *cxlr, int count)
while (!is_cxl_root(to_cxl_port(iter->dev.parent)))
iter = to_cxl_port(iter->dev.parent);
- for (ep = cxl_ep_load(iter, cxlmd); iter;
- iter = ep->next, ep = cxl_ep_load(iter, cxlmd)) {
+ for (ep = cxl_ep_load(iter, &cxlmd->dev); iter;
+ iter = ep->next, ep = cxl_ep_load(iter, &cxlmd->dev)) {
struct cxl_region_ref *cxl_rr;
struct cxl_decoder *cxld;
@@ -334,8 +334,8 @@ static int cxl_region_decode_commit(struct cxl_region *cxlr)
if (rc) {
/* programming @iter failed, teardown */
- for (ep = cxl_ep_load(iter, cxlmd); ep && iter;
- iter = ep->next, ep = cxl_ep_load(iter, cxlmd)) {
+ for (ep = cxl_ep_load(iter, &cxlmd->dev); ep && iter;
+ iter = ep->next, ep = cxl_ep_load(iter, &cxlmd->dev)) {
cxl_rr = cxl_rr_load(iter, cxlr);
cxld = cxl_rr->decoder;
if (cxld->reset)
@@ -1092,7 +1092,7 @@ static int cxl_rr_ep_add(struct cxl_region_ref *cxl_rr,
struct cxl_port *port = cxl_rr->port;
struct cxl_region *cxlr = cxl_rr->region;
struct cxl_decoder *cxld = cxl_rr->decoder;
- struct cxl_ep *ep = cxl_ep_load(port, cxled_to_memdev(cxled));
+ struct cxl_ep *ep = cxl_ep_load(port, &cxled_to_memdev(cxled)->dev);
if (ep) {
rc = xa_insert(&cxl_rr->endpoints, (unsigned long)cxled, ep,
@@ -1200,7 +1200,7 @@ static int cxl_port_attach_region(struct cxl_port *port,
struct cxl_endpoint_decoder *cxled, int pos)
{
struct cxl_memdev *cxlmd = cxled_to_memdev(cxled);
- struct cxl_ep *ep = cxl_ep_load(port, cxlmd);
+ struct cxl_ep *ep = cxl_ep_load(port, &cxlmd->dev);
struct cxl_region_ref *cxl_rr;
bool nr_targets_inc = false;
struct cxl_decoder *cxld;
@@ -1377,7 +1377,7 @@ static int check_last_peer(struct cxl_endpoint_decoder *cxled,
}
cxled_peer = p->targets[pos - distance];
cxlmd_peer = cxled_to_memdev(cxled_peer);
- ep_peer = cxl_ep_load(port, cxlmd_peer);
+ ep_peer = cxl_ep_load(port, &cxlmd_peer->dev);
if (ep->dport != ep_peer->dport) {
dev_dbg(&cxlr->dev,
"%s:%s: %s:%s pos %d mismatched peer %s:%s\n",
@@ -1444,7 +1444,7 @@ static int cxl_port_setup_targets(struct cxl_port *port,
struct cxl_port *parent_port = to_cxl_port(port->dev.parent);
struct cxl_region_ref *cxl_rr = cxl_rr_load(port, cxlr);
struct cxl_memdev *cxlmd = cxled_to_memdev(cxled);
- struct cxl_ep *ep = cxl_ep_load(port, cxlmd);
+ struct cxl_ep *ep = cxl_ep_load(port, &cxlmd->dev);
struct cxl_region_params *p = &cxlr->params;
struct cxl_decoder *cxld = cxl_rr->decoder;
struct cxl_switch_decoder *cxlsd;
@@ -1692,8 +1692,8 @@ static void cxl_region_teardown_targets(struct cxl_region *cxlr)
while (!is_cxl_root(to_cxl_port(iter->dev.parent)))
iter = to_cxl_port(iter->dev.parent);
- for (ep = cxl_ep_load(iter, cxlmd); iter;
- iter = ep->next, ep = cxl_ep_load(iter, cxlmd))
+ for (ep = cxl_ep_load(iter, &cxlmd->dev); iter;
+ iter = ep->next, ep = cxl_ep_load(iter, &cxlmd->dev))
cxl_port_reset_targets(iter, cxlr);
}
}
@@ -1729,8 +1729,8 @@ static int cxl_region_setup_targets(struct cxl_region *cxlr)
* Descend the topology tree programming / validating
* targets while looking for conflicts.
*/
- for (ep = cxl_ep_load(iter, cxlmd); iter;
- iter = ep->next, ep = cxl_ep_load(iter, cxlmd)) {
+ for (ep = cxl_ep_load(iter, &cxlmd->dev); iter;
+ iter = ep->next, ep = cxl_ep_load(iter, &cxlmd->dev)) {
rc = cxl_port_setup_targets(iter, cxlr, cxled);
if (rc) {
cxl_region_teardown_targets(cxlr);
diff --git a/drivers/cxl/cxlmem.h b/drivers/cxl/cxlmem.h
index c401e3a1af06..a102b8eba5cd 100644
--- a/drivers/cxl/cxlmem.h
+++ b/drivers/cxl/cxlmem.h
@@ -147,12 +147,12 @@ struct cxl_dpa_info {
int cxl_dpa_setup(struct cxl_dev_state *cxlds, const struct cxl_dpa_info *info);
static inline struct cxl_ep *cxl_ep_load(struct cxl_port *port,
- struct cxl_memdev *cxlmd)
+ struct device *ep_dev)
{
if (!port)
return NULL;
- return xa_load(&port->endpoints, (unsigned long)&cxlmd->dev);
+ return xa_load(&port->endpoints, (unsigned long)ep_dev);
}
/*
diff --git a/drivers/cxl/port.c b/drivers/cxl/port.c
index 99cf77b6b699..edf0ff759fbf 100644
--- a/drivers/cxl/port.c
+++ b/drivers/cxl/port.c
@@ -298,7 +298,7 @@ int devm_cxl_add_endpoint(struct device *host, struct cxl_memdev *cxlmd,
down = iter, iter = to_cxl_port(iter->dev.parent)) {
struct cxl_ep *ep;
- ep = cxl_ep_load(iter, cxlmd);
+ ep = cxl_ep_load(iter, &cxlmd->dev);
ep->next = down;
}
--
2.53.0
next prev parent reply other threads:[~2026-09-23 17:33 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-23 17:33 [PATCH 00/15] Add initial CXL.cache support Ben Cheatham
2026-09-23 17:33 ` [PATCH 01/15] cxl/core: Add CXL.cache device struct Ben Cheatham
2026-09-23 17:41 ` sashiko-bot
2026-09-23 17:33 ` [PATCH 02/15] cxl/cache: Add cxl_cache driver Ben Cheatham
2026-09-23 17:49 ` sashiko-bot
2026-09-23 17:33 ` Ben Cheatham [this message]
2026-09-23 17:33 ` [PATCH 04/15] cxl/core: Update devm_cxl_enumerate_ports() for cxl_cachedevs Ben Cheatham
2026-09-23 17:33 ` [PATCH 05/15] cxl/port: Split endpoint port probe on device type Ben Cheatham
2026-09-23 17:46 ` sashiko-bot
2026-09-23 17:33 ` [PATCH 06/15] cxl/core: Update devm_cxl_add_endpoint() for cxl_cachedevs Ben Cheatham
2026-09-23 17:51 ` sashiko-bot
2026-09-23 17:33 ` [PATCH 07/15] cxl/cache: Verify port hierarchy has CXL.cache enabled Ben Cheatham
2026-09-23 17:33 ` [PATCH 08/15] cxl/core, cache: Add Cache ID register probing and init Ben Cheatham
2026-09-23 17:46 ` sashiko-bot
2026-09-23 17:33 ` [PATCH 09/15] cxl/core: Add Cache ID verification Ben Cheatham
2026-09-23 17:49 ` sashiko-bot
2026-09-23 17:33 ` [PATCH 10/15] cxl/core: Add Cache ID allocation Ben Cheatham
2026-09-23 17:49 ` sashiko-bot
2026-09-23 17:33 ` [PATCH 11/15] cxl/core: Add support for HDM-D cache id programming Ben Cheatham
2026-09-23 17:51 ` sashiko-bot
2026-09-23 17:33 ` [PATCH 12/15] cxl/cache: Add snoop filter creation and set up Ben Cheatham
2026-09-23 17:50 ` sashiko-bot
2026-09-23 17:33 ` [PATCH 13/15] cxl/cache: Add snoop filter allocation Ben Cheatham
2026-09-23 17:58 ` sashiko-bot
2026-09-23 17:33 ` [PATCH 14/15] iommu, cxl: Configure IOMMU for CXL.cache Ben Cheatham
2026-09-23 17:57 ` sashiko-bot
2026-09-23 17:33 ` [PATCH 15/15] cxl/cache: Enable CXL.cache on successful probe Ben Cheatham
2026-09-23 17:35 ` [PATCH 00/15] Add initial CXL.cache support Cheatham, Benjamin
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