[PATCH 07/15] cxl/cache: Verify port hierarchy has CXL.cache enabled

[Ben Cheatham <Benjamin.Cheatham@amd.com>]

Check that the ports above a CXL.cache device support CXL.cache and have
the protocol enabled. The device's CXL.cache enable bit will be set in a
later commit.

CXL.cache should be enabled as part of link negotiation by firmware
during boot. Upstream ports can't be programmed after boot, but
downstream ports can. Reprogramming downstream ports requires a link
reset and is may have implications for the underlying PCI device, so
fail probe instead of reprogramming the downstream port.

Signed-off-by: Ben Cheatham <Benjamin.Cheatham@amd.com>
---
 drivers/cxl/cache.c           | 76 ++++++++++++++++++++++++++++++++++-
 include/uapi/linux/pci_regs.h |  4 ++
 2 files changed, 79 insertions(+), 1 deletion(-)

diff --git a/drivers/cxl/cache.c b/drivers/cxl/cache.c
index dea5af7b2d3f..dfefd301696a 100644
--- a/drivers/cxl/cache.c
+++ b/drivers/cxl/cache.c
@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /* Copyright (C) 2026 Advanced Micro Devices, Inc. */
 
+#include <linux/pci.h>
 #include <cxl/cxl.h>
 
 #include "cxlcache.h"
@@ -14,6 +15,75 @@
  * device-specific driver is required for discovery and portions of set up.
  */
 
+static bool cxl_flexbus_cache_enabled(struct device *host)
+{
+
+	u16 dvsec, cap, status;
+	struct pci_dev *pdev;
+	int rc;
+
+	if (!dev_is_pci(host))
+		return false;
+	pdev = to_pci_dev(host);
+
+	dvsec = pci_find_dvsec_capability(pdev, PCI_VENDOR_ID_CXL,
+					  PCI_DVSEC_CXL_FLEXBUS_PORT);
+	if (!dvsec)
+		return false;
+
+	rc = pci_read_config_word(pdev,
+				  dvsec + PCI_DVSEC_CXL_FLEXBUS_PORT_CAPABILITY,
+				  &cap);
+	if (rc)
+		return false;
+
+	if (!FIELD_GET(PCI_DVSEC_CXL_FLEXBUS_PORT_CAP_CACHE, cap))
+		return false;
+
+	rc = pci_read_config_word(pdev,
+				  dvsec + PCI_DVSEC_CXL_FLEXBUS_PORT_STATUS,
+				  &status);
+	if (rc)
+		return false;
+
+	return FIELD_GET(PCI_DVSEC_CXL_FLEXBUS_PORT_STATUS_CACHE, status);
+}
+
+static int cxl_endpoint_cache_enabled(struct cxl_port *endpoint)
+{
+	struct cxl_dport *dport_iter = endpoint->parent_dport;
+	struct cxl_port *port_iter = dport_iter->port;
+
+	while (!is_cxl_root(port_iter)) {
+		/* 
+		 * CXL host bridge isn't a PCI device, but we still need to
+		 * check the PCIe root port
+		 */
+		if (dev_is_pci(port_iter->uport_dev) &&
+		    !cxl_flexbus_cache_enabled(port_iter->uport_dev)) {
+			dev_dbg(port_iter->uport_dev,
+				"CXL.cache not supported or enabled\n");
+			return -ENXIO;
+		}
+
+		/*
+		 * Cache can be enabled for dports, but it requires a link
+		 * reset. Could be done here, but should probably be done
+		 * by the endpoint's driver.
+		 */
+		if (!cxl_flexbus_cache_enabled(dport_iter->dport_dev)) {
+			dev_dbg(dport_iter->dport_dev,
+				"CXL.cache not supported or enabled\n");
+			return -ENXIO;
+		}
+
+		dport_iter = port_iter->parent_dport;
+		port_iter = dport_iter->port;
+	}
+
+	return 0;
+}
+
 /**
  * devm_cxl_add_cachedev - Add a CXL cache device
  * @cxlds: CXL device state to associate with the cachedev
@@ -71,7 +141,11 @@ static int cxl_cache_probe(struct device *dev)
 			return rc;
 	}
 
-	return 0;
+	rc = cxl_endpoint_cache_enabled(cxlcd->endpoint);
+	if (rc)
+		dev_err(dev, "CXL.cache not enabled on parent port(s)");
+
+	return rc;
 }
 
 static struct cxl_driver cxl_cache_driver = {
diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
index 5383b54ede96..9146ee574de8 100644
--- a/include/uapi/linux/pci_regs.h
+++ b/include/uapi/linux/pci_regs.h
@@ -1392,6 +1392,10 @@
 
 /* CXL r4.0, 8.1.8: Flex Bus DVSEC */
 #define PCI_DVSEC_CXL_FLEXBUS_PORT			7
+#define  PCI_DVSEC_CXL_FLEXBUS_PORT_CAPABILITY		0xA
+#define   PCI_DVSEC_CXL_FLEXBUS_PORT_CAP_CACHE		_BITUL(0)
+#define  PCI_DVSEC_CXL_FLEXBUS_PORT_CONTROL		0xC
+#define   PCI_DVSEC_CXL_FLEXBUS_PORT_CTRL_CACHE_EN	_BITUL(0)
 #define  PCI_DVSEC_CXL_FLEXBUS_PORT_STATUS		0xE
 #define   PCI_DVSEC_CXL_FLEXBUS_PORT_STATUS_CACHE	_BITUL(0)
 #define   PCI_DVSEC_CXL_FLEXBUS_PORT_STATUS_MEM		_BITUL(2)
-- 
2.53.0