* [PATCH 00/26] powerpc: drop EOL boards and SoCs, take over maintenance
@ 2026-10-09 19:36 Bradley Morgan
2026-10-09 19:36 ` [PATCH 01/26] board: powerpc: Remove MPC8548CDS support Bradley Morgan
` (25 more replies)
0 siblings, 26 replies; 31+ messages in thread
From: Bradley Morgan @ 2026-10-09 19:36 UTC (permalink / raw)
To: Tom Rini, u-boot
Cc: Bradley Morgan, Marek Behún, Marek Mojík,
NXP i . MX U-Boot Team, Alexey Charkov, Anshul Dalal,
Daniel Golle, Fabio Estevam, Gaurav Jain, Ilias Apalodimas,
Jaehoon Chung, James Hilliard, Jerome Forissier, Johan Jonker,
Lukasz Majewski, Marek Vasut, Mario Six, Michael Walle,
Michal Simek, Neil Armstrong, Peng Fan, Pengpeng Hou,
Priyanka Jain, Quentin Schulz, Simon Glass, Stefano Babic,
Tanmay Kathpalia, Torsten Rupp, Vincent Jardin, Weijie Gao
PowerPC in U-Boot has been orphaned since October 2022, and a huge chunk
of what sits in arch/powerpc is ancient NXP hardware that has been out
of production for years. Nobody is running or testing these boards, NXP
marked them obsolete or archived, and having dead silicon files hang around
just gets in the way of treewide cleanups.
So heres a sweep to get rid of them. The first seven patches drop the
obsolete boards (MPC8548CDS, MPC837XERDB, P2020RDB-PC, P3041DS, P4080DS,
P5040DS, T1042D4RDB). Once the boards are gone, patches 8 through 24
peel off the dead SoCs and all the orphaned serdes tables and errata glue
that lost their last callers. Then MPC86xx goes away completely, and
the last patch adds me to MAINTAINERS so arch/powerpc actually has an
active maintainer instead of sitting orphaned.
Net diff drops about 12.8k lines of dead code.
Bradley Morgan (26):
board: powerpc: Remove MPC8548CDS support
board: powerpc: Remove MPC837XERDB support
board: powerpc: Remove P2020RDB-PC support
board: powerpc: Remove P3041DS support
board: powerpc: Remove P4080DS support
board: powerpc: Remove P5040DS support
board: powerpc: Remove T1042D4RDB support
powerpc: mpc85xx: Remove P3041 support
powerpc: mpc85xx: Remove P4080 support
powerpc: mpc85xx: Remove P5040 support
powerpc: mpc83xx: Remove MPC837x support
powerpc: mpc85xx: Remove C29x support
powerpc: mpc85xx: Remove P1011 support
powerpc: mpc85xx: Remove P1023 support
powerpc: mpc85xx: Remove P1025 support
powerpc: mpc85xx: Remove MPC8536 support
powerpc: mpc85xx: Remove MPC8540 support
powerpc: mpc85xx: Remove MPC8560 support
powerpc: mpc85xx: Remove BSC9132 support
powerpc: mpc83xx: Remove MPC831x support
powerpc: mpc83xx: Remove MPC834x support
powerpc: mpc85xx: Remove P1024 support
powerpc: mpc85xx: Remove BSC9131 support
powerpc: mpc83xx: Remove MPC8309 support
powerpc: Remove MPC86xx support
MAINTAINERS: powerpc: Add me as PowerPC maintainer
MAINTAINERS | 3 +-
README | 2 +-
api/api_platform-powerpc.c | 2 +-
arch/Kconfig | 7 +-
arch/Kconfig.nxp | 9 +-
arch/powerpc/cpu/Makefile | 1 -
arch/powerpc/cpu/mpc83xx/Kconfig | 44 --
arch/powerpc/cpu/mpc83xx/cpu.c | 17 +-
arch/powerpc/cpu/mpc83xx/cpu_init.c | 24 -
arch/powerpc/cpu/mpc83xx/fdt.c | 47 +-
arch/powerpc/cpu/mpc83xx/hid/Kconfig | 4 +-
arch/powerpc/cpu/mpc83xx/hid/hid.h | 5 -
arch/powerpc/cpu/mpc83xx/hrcw/Kconfig | 82 +--
arch/powerpc/cpu/mpc83xx/initreg/Kconfig.lcrr | 6 +-
arch/powerpc/cpu/mpc83xx/initreg/Kconfig.spcr | 2 +-
arch/powerpc/cpu/mpc83xx/pci.c | 2 -
arch/powerpc/cpu/mpc83xx/spd_sdram.c | 4 +-
arch/powerpc/cpu/mpc83xx/speed.c | 112 +--
arch/powerpc/cpu/mpc83xx/traps.c | 1 -
arch/powerpc/cpu/mpc85xx/Kconfig | 443 +-----------
arch/powerpc/cpu/mpc85xx/Makefile | 14 -
arch/powerpc/cpu/mpc85xx/bsc9132_serdes.c | 101 ---
arch/powerpc/cpu/mpc85xx/c29x_serdes.c | 70 --
arch/powerpc/cpu/mpc85xx/cmd_errata.c | 43 +-
arch/powerpc/cpu/mpc85xx/cpu.c | 17 -
arch/powerpc/cpu/mpc85xx/cpu_init.c | 49 +-
arch/powerpc/cpu/mpc85xx/fdt.c | 28 +-
arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c | 665 ------------------
arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.h | 4 -
arch/powerpc/cpu/mpc85xx/mpc8536_serdes.c | 250 -------
arch/powerpc/cpu/mpc85xx/mpc8548_serdes.c | 57 --
arch/powerpc/cpu/mpc85xx/p1023_serdes.c | 59 --
arch/powerpc/cpu/mpc85xx/p3041_ids.c | 112 ---
arch/powerpc/cpu/mpc85xx/p3041_serdes.c | 133 ----
arch/powerpc/cpu/mpc85xx/p4080_ids.c | 112 ---
arch/powerpc/cpu/mpc85xx/p4080_serdes.c | 80 ---
arch/powerpc/cpu/mpc85xx/p5040_ids.c | 111 ---
arch/powerpc/cpu/mpc85xx/p5040_serdes.c | 99 ---
arch/powerpc/cpu/mpc85xx/release.S | 23 +-
arch/powerpc/cpu/mpc85xx/speed.c | 6 +-
arch/powerpc/cpu/mpc8xxx/Makefile | 1 -
arch/powerpc/cpu/mpc8xxx/cpu.c | 20 +-
arch/powerpc/cpu/mpc8xxx/fdt.c | 8 +-
arch/powerpc/cpu/mpc8xxx/srio.c | 6 -
arch/powerpc/dts/Makefile | 7 -
arch/powerpc/dts/mpc8379erdb.dts | 153 ----
arch/powerpc/dts/mpc8548-post.dtsi | 36 -
arch/powerpc/dts/mpc8548.dtsi | 27 -
arch/powerpc/dts/mpc8548cds.dts | 29 -
arch/powerpc/dts/mpc8548cds_36b.dts | 29 -
arch/powerpc/dts/p2020rdb-pc.dts | 59 --
arch/powerpc/dts/p2020rdb-pc.dtsi | 50 --
arch/powerpc/dts/p2020rdb-pc_36b.dts | 59 --
arch/powerpc/dts/p3041.dtsi | 149 ----
arch/powerpc/dts/p3041ds.dts | 158 -----
arch/powerpc/dts/p3041si-post.dtsi | 43 --
arch/powerpc/dts/p4080.dtsi | 148 ----
arch/powerpc/dts/p4080ds.dts | 220 ------
arch/powerpc/dts/p4080si-post.dtsi | 62 --
arch/powerpc/dts/p5040.dtsi | 137 ----
arch/powerpc/dts/p5040ds.dts | 281 --------
arch/powerpc/dts/p5040si-post.dtsi | 70 --
arch/powerpc/dts/t1042d4rdb-u-boot.dtsi | 12 -
arch/powerpc/dts/t1042d4rdb.dts | 89 ---
arch/powerpc/dts/t104x.dtsi | 148 ----
arch/powerpc/include/asm/arch-mpc83xx/gpio.h | 4 +-
arch/powerpc/include/asm/arch-mpc83xx/soc.h | 37 +-
arch/powerpc/include/asm/config.h | 1 -
arch/powerpc/include/asm/config_mpc85xx.h | 56 +-
arch/powerpc/include/asm/fsl_law.h | 8 -
arch/powerpc/include/asm/fsl_lbc.h | 15 +-
arch/powerpc/include/asm/fsl_pci.h | 7 -
arch/powerpc/include/asm/fsl_secure_boot.h | 1 -
arch/powerpc/include/asm/fsl_serdes.h | 3 -
arch/powerpc/include/asm/global_data.h | 19 +-
arch/powerpc/include/asm/immap_83xx.h | 123 +---
arch/powerpc/include/asm/immap_85xx.h | 253 +------
arch/powerpc/include/asm/mpc8349_pci.h | 165 -----
arch/powerpc/include/asm/mpc8xxx_spi.h | 5 +-
arch/powerpc/include/asm/ppc.h | 14 +-
arch/powerpc/include/asm/processor.h | 36 +-
arch/powerpc/lib/bdinfo.c | 2 +-
arch/powerpc/lib/bootm.c | 7 -
arch/powerpc/lib/ppccache.S | 4 +-
arch/powerpc/lib/stack.c | 2 +-
board/nxp/common/Makefile | 11 -
board/nxp/common/cds_pci_ft.c | 17 -
board/nxp/common/cds_via.c | 95 ---
board/nxp/common/ics307_clk.c | 149 ----
board/nxp/common/ics307_clk.h | 14 -
board/nxp/common/ngpixis.c | 247 -------
board/nxp/common/ngpixis.h | 60 --
board/nxp/common/sdhc_boot.c | 2 +-
board/nxp/mpc837xerdb/Kconfig | 15 -
board/nxp/mpc837xerdb/MAINTAINERS | 6 -
board/nxp/mpc837xerdb/Makefile | 6 -
board/nxp/mpc837xerdb/README | 97 ---
board/nxp/mpc837xerdb/mpc837xerdb.c | 242 -------
board/nxp/mpc8548cds/Kconfig | 24 -
board/nxp/mpc8548cds/MAINTAINERS | 8 -
board/nxp/mpc8548cds/Makefile | 10 -
board/nxp/mpc8548cds/ddr.c | 51 --
board/nxp/mpc8548cds/law.c | 18 -
board/nxp/mpc8548cds/mpc8548cds.c | 170 -----
board/nxp/mpc8548cds/tlb.c | 87 ---
board/nxp/p1_p2_rdb_pc/Kconfig | 3 +-
board/nxp/p1_p2_rdb_pc/MAINTAINERS | 8 -
board/nxp/p1_p2_rdb_pc/README | 7 +-
board/nxp/p1_p2_rdb_pc/ddr.c | 68 --
board/nxp/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 2 -
board/nxp/t104xrdb/Kconfig | 12 -
board/nxp/t104xrdb/MAINTAINERS | 13 -
board/nxp/t104xrdb/Makefile | 13 -
board/nxp/t104xrdb/README | 386 ----------
board/nxp/t104xrdb/cpld.c | 116 ---
board/nxp/t104xrdb/cpld.h | 45 --
board/nxp/t104xrdb/ddr.c | 148 ----
board/nxp/t104xrdb/ddr.h | 56 --
board/nxp/t104xrdb/law.c | 31 -
board/nxp/t104xrdb/spl.c | 131 ----
board/nxp/t104xrdb/t1040_nand_rcw.cfg | 7 -
board/nxp/t104xrdb/t1040_sd_rcw.cfg | 7 -
board/nxp/t104xrdb/t1040_spi_rcw.cfg | 7 -
board/nxp/t104xrdb/t1040d4_nand_rcw.cfg | 7 -
board/nxp/t104xrdb/t1040d4_sd_rcw.cfg | 7 -
board/nxp/t104xrdb/t1040d4_spi_rcw.cfg | 7 -
board/nxp/t104xrdb/t1042_nand_rcw.cfg | 7 -
board/nxp/t104xrdb/t1042_pi_nand_rcw.cfg | 7 -
board/nxp/t104xrdb/t1042_pi_sd_rcw.cfg | 7 -
board/nxp/t104xrdb/t1042_pi_spi_rcw.cfg | 7 -
board/nxp/t104xrdb/t1042_sd_rcw.cfg | 7 -
board/nxp/t104xrdb/t1042_spi_rcw.cfg | 7 -
board/nxp/t104xrdb/t1042d4_nand_rcw.cfg | 7 -
board/nxp/t104xrdb/t1042d4_sd_rcw.cfg | 7 -
board/nxp/t104xrdb/t1042d4_spi_rcw.cfg | 7 -
board/nxp/t104xrdb/t104x_pbi.cfg | 36 -
board/nxp/t104xrdb/t104x_pbi_sb.cfg | 38 -
board/nxp/t104xrdb/t104xrdb.c | 159 -----
board/nxp/t104xrdb/t104xrdb.h | 11 -
board/nxp/t104xrdb/tlb.c | 132 ----
boot/Kconfig | 4 +-
common/board_r.c | 2 +-
configs/MPC837XERDB_defconfig | 193 -----
configs/MPC8548CDS_36BIT_defconfig | 108 ---
configs/MPC8548CDS_defconfig | 106 ---
configs/MPC8548CDS_legacy_defconfig | 106 ---
configs/P2020RDB-PC_36BIT_NAND_defconfig | 164 -----
configs/P2020RDB-PC_36BIT_SDCARD_defconfig | 145 ----
configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig | 147 ----
configs/P2020RDB-PC_36BIT_defconfig | 125 ----
configs/P2020RDB-PC_NAND_defconfig | 162 -----
configs/P2020RDB-PC_SDCARD_defconfig | 142 ----
configs/P2020RDB-PC_SPIFLASH_defconfig | 145 ----
configs/P2020RDB-PC_defconfig | 123 ----
configs/T1042D4RDB_NAND_defconfig | 144 ----
configs/T1042D4RDB_SDCARD_defconfig | 138 ----
configs/T1042D4RDB_SPIFLASH_defconfig | 141 ----
configs/T1042D4RDB_defconfig | 114 ---
doc/README.mpc83xxads | 97 ---
doc/README.mpc85xx-sd-spi-boot | 8 -
doc/README.mpc85xxcds | 225 ------
doc/README.pblimage | 6 +-
doc/README.sata | 68 --
doc/README.srio-pcie-boot-corenet | 118 ----
.../clock/fsl,mpc83xx-clk.txt | 7 +-
doc/device-tree-bindings/cpu/fsl,mpc83xx.txt | 13 +-
.../gpio/fsl,mpc83xx-spisel-boot.txt | 4 +-
drivers/clk/mpc83xx_clk.c | 19 +-
drivers/clk/mpc83xx_clk.h | 30 +-
drivers/cpu/mpc83xx_cpu.c | 62 +-
drivers/cpu/mpc83xx_cpu.h | 44 --
drivers/crypto/fsl/jr.c | 14 +-
drivers/ddr/fsl/Kconfig | 8 +-
drivers/ddr/fsl/ctrl_regs.c | 1 -
drivers/dma/fsl_dma.c | 4 -
drivers/gpio/mpc83xx_spisel_boot.c | 1 -
drivers/gpio/mpc8xxx_gpio.c | 1 -
drivers/mmc/Kconfig | 3 +-
drivers/net/Kconfig | 4 -
drivers/net/fm/Makefile | 6 +-
drivers/net/fm/fm.h | 4 -
drivers/net/fm/p1023.c | 72 --
drivers/net/fm/p4080.c | 98 ---
drivers/net/fm/p5040.c | 106 ---
drivers/pci/Kconfig | 2 +-
drivers/pci/pci_auto.c | 14 -
drivers/pci/pcie_fsl.c | 23 -
drivers/qe/Kconfig | 3 +-
drivers/qe/qe.c | 1 -
drivers/ram/mpc83xx_sdram.c | 14 +-
drivers/usb/common/fsl-errata.c | 15 -
drivers/usb/host/Kconfig | 2 +-
env/Kconfig | 3 +-
include/asm-generic/u-boot.h | 2 +-
include/configs/MPC837XERDB.h | 218 ------
include/configs/MPC8548CDS.h | 312 --------
include/configs/T104xRDB.h | 397 -----------
include/configs/p1_p2_rdb_pc.h | 21 -
include/dt-bindings/clk/mpc83xx-clk.h | 1 -
include/fsl_immap.h | 2 +-
include/fsl_sec.h | 3 -
include/mpc83xx.h | 319 +--------
include/pci_ids.h | 4 -
include/serial.h | 1 -
204 files changed, 178 insertions(+), 12873 deletions(-)
delete mode 100644 arch/powerpc/cpu/mpc85xx/bsc9132_serdes.c
delete mode 100644 arch/powerpc/cpu/mpc85xx/c29x_serdes.c
delete mode 100644 arch/powerpc/cpu/mpc85xx/mpc8536_serdes.c
delete mode 100644 arch/powerpc/cpu/mpc85xx/mpc8548_serdes.c
delete mode 100644 arch/powerpc/cpu/mpc85xx/p1023_serdes.c
delete mode 100644 arch/powerpc/cpu/mpc85xx/p3041_ids.c
delete mode 100644 arch/powerpc/cpu/mpc85xx/p3041_serdes.c
delete mode 100644 arch/powerpc/cpu/mpc85xx/p4080_ids.c
delete mode 100644 arch/powerpc/cpu/mpc85xx/p4080_serdes.c
delete mode 100644 arch/powerpc/cpu/mpc85xx/p5040_ids.c
delete mode 100644 arch/powerpc/cpu/mpc85xx/p5040_serdes.c
delete mode 100644 arch/powerpc/dts/mpc8379erdb.dts
delete mode 100644 arch/powerpc/dts/mpc8548-post.dtsi
delete mode 100644 arch/powerpc/dts/mpc8548.dtsi
delete mode 100644 arch/powerpc/dts/mpc8548cds.dts
delete mode 100644 arch/powerpc/dts/mpc8548cds_36b.dts
delete mode 100644 arch/powerpc/dts/p2020rdb-pc.dts
delete mode 100644 arch/powerpc/dts/p2020rdb-pc.dtsi
delete mode 100644 arch/powerpc/dts/p2020rdb-pc_36b.dts
delete mode 100644 arch/powerpc/dts/p3041.dtsi
delete mode 100644 arch/powerpc/dts/p3041ds.dts
delete mode 100644 arch/powerpc/dts/p3041si-post.dtsi
delete mode 100644 arch/powerpc/dts/p4080.dtsi
delete mode 100644 arch/powerpc/dts/p4080ds.dts
delete mode 100644 arch/powerpc/dts/p4080si-post.dtsi
delete mode 100644 arch/powerpc/dts/p5040.dtsi
delete mode 100644 arch/powerpc/dts/p5040ds.dts
delete mode 100644 arch/powerpc/dts/p5040si-post.dtsi
delete mode 100644 arch/powerpc/dts/t1042d4rdb-u-boot.dtsi
delete mode 100644 arch/powerpc/dts/t1042d4rdb.dts
delete mode 100644 arch/powerpc/dts/t104x.dtsi
delete mode 100644 arch/powerpc/include/asm/mpc8349_pci.h
delete mode 100644 board/nxp/common/cds_pci_ft.c
delete mode 100644 board/nxp/common/cds_via.c
delete mode 100644 board/nxp/common/ics307_clk.c
delete mode 100644 board/nxp/common/ics307_clk.h
delete mode 100644 board/nxp/common/ngpixis.c
delete mode 100644 board/nxp/common/ngpixis.h
delete mode 100644 board/nxp/mpc837xerdb/Kconfig
delete mode 100644 board/nxp/mpc837xerdb/MAINTAINERS
delete mode 100644 board/nxp/mpc837xerdb/Makefile
delete mode 100644 board/nxp/mpc837xerdb/README
delete mode 100644 board/nxp/mpc837xerdb/mpc837xerdb.c
delete mode 100644 board/nxp/mpc8548cds/Kconfig
delete mode 100644 board/nxp/mpc8548cds/MAINTAINERS
delete mode 100644 board/nxp/mpc8548cds/Makefile
delete mode 100644 board/nxp/mpc8548cds/ddr.c
delete mode 100644 board/nxp/mpc8548cds/law.c
delete mode 100644 board/nxp/mpc8548cds/mpc8548cds.c
delete mode 100644 board/nxp/mpc8548cds/tlb.c
delete mode 100644 board/nxp/t104xrdb/Kconfig
delete mode 100644 board/nxp/t104xrdb/MAINTAINERS
delete mode 100644 board/nxp/t104xrdb/Makefile
delete mode 100644 board/nxp/t104xrdb/README
delete mode 100644 board/nxp/t104xrdb/cpld.c
delete mode 100644 board/nxp/t104xrdb/cpld.h
delete mode 100644 board/nxp/t104xrdb/ddr.c
delete mode 100644 board/nxp/t104xrdb/ddr.h
delete mode 100644 board/nxp/t104xrdb/law.c
delete mode 100644 board/nxp/t104xrdb/spl.c
delete mode 100644 board/nxp/t104xrdb/t1040_nand_rcw.cfg
delete mode 100644 board/nxp/t104xrdb/t1040_sd_rcw.cfg
delete mode 100644 board/nxp/t104xrdb/t1040_spi_rcw.cfg
delete mode 100644 board/nxp/t104xrdb/t1040d4_nand_rcw.cfg
delete mode 100644 board/nxp/t104xrdb/t1040d4_sd_rcw.cfg
delete mode 100644 board/nxp/t104xrdb/t1040d4_spi_rcw.cfg
delete mode 100644 board/nxp/t104xrdb/t1042_nand_rcw.cfg
delete mode 100644 board/nxp/t104xrdb/t1042_pi_nand_rcw.cfg
delete mode 100644 board/nxp/t104xrdb/t1042_pi_sd_rcw.cfg
delete mode 100644 board/nxp/t104xrdb/t1042_pi_spi_rcw.cfg
delete mode 100644 board/nxp/t104xrdb/t1042_sd_rcw.cfg
delete mode 100644 board/nxp/t104xrdb/t1042_spi_rcw.cfg
delete mode 100644 board/nxp/t104xrdb/t1042d4_nand_rcw.cfg
delete mode 100644 board/nxp/t104xrdb/t1042d4_sd_rcw.cfg
delete mode 100644 board/nxp/t104xrdb/t1042d4_spi_rcw.cfg
delete mode 100644 board/nxp/t104xrdb/t104x_pbi.cfg
delete mode 100644 board/nxp/t104xrdb/t104x_pbi_sb.cfg
delete mode 100644 board/nxp/t104xrdb/t104xrdb.c
delete mode 100644 board/nxp/t104xrdb/t104xrdb.h
delete mode 100644 board/nxp/t104xrdb/tlb.c
delete mode 100644 configs/MPC837XERDB_defconfig
delete mode 100644 configs/MPC8548CDS_36BIT_defconfig
delete mode 100644 configs/MPC8548CDS_defconfig
delete mode 100644 configs/MPC8548CDS_legacy_defconfig
delete mode 100644 configs/P2020RDB-PC_36BIT_NAND_defconfig
delete mode 100644 configs/P2020RDB-PC_36BIT_SDCARD_defconfig
delete mode 100644 configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig
delete mode 100644 configs/P2020RDB-PC_36BIT_defconfig
delete mode 100644 configs/P2020RDB-PC_NAND_defconfig
delete mode 100644 configs/P2020RDB-PC_SDCARD_defconfig
delete mode 100644 configs/P2020RDB-PC_SPIFLASH_defconfig
delete mode 100644 configs/P2020RDB-PC_defconfig
delete mode 100644 configs/T1042D4RDB_NAND_defconfig
delete mode 100644 configs/T1042D4RDB_SDCARD_defconfig
delete mode 100644 configs/T1042D4RDB_SPIFLASH_defconfig
delete mode 100644 configs/T1042D4RDB_defconfig
delete mode 100644 doc/README.mpc83xxads
delete mode 100644 doc/README.mpc85xxcds
delete mode 100644 doc/README.sata
delete mode 100644 doc/README.srio-pcie-boot-corenet
delete mode 100644 drivers/net/fm/p1023.c
delete mode 100644 drivers/net/fm/p4080.c
delete mode 100644 drivers/net/fm/p5040.c
delete mode 100644 include/configs/MPC837XERDB.h
delete mode 100644 include/configs/MPC8548CDS.h
delete mode 100644 include/configs/T104xRDB.h
--
2.47.3
^ permalink raw reply [flat|nested] 31+ messages in thread
* [PATCH 01/26] board: powerpc: Remove MPC8548CDS support
2026-10-09 19:36 [PATCH 00/26] powerpc: drop EOL boards and SoCs, take over maintenance Bradley Morgan
@ 2026-10-09 19:36 ` Bradley Morgan
2026-10-09 21:55 ` Tom Rini
2026-10-09 19:36 ` [PATCH 02/26] board: powerpc: Remove MPC837XERDB support Bradley Morgan
` (24 subsequent siblings)
25 siblings, 1 reply; 31+ messages in thread
From: Bradley Morgan @ 2026-10-09 19:36 UTC (permalink / raw)
To: Tom Rini, u-boot
Cc: Bradley Morgan, Marek Behún, Marek Mojík,
NXP i . MX U-Boot Team, Alexey Charkov, Anshul Dalal,
Daniel Golle, Fabio Estevam, Gaurav Jain, Ilias Apalodimas,
Jaehoon Chung, James Hilliard, Jerome Forissier, Johan Jonker,
Lukasz Majewski, Marek Vasut, Mario Six, Michael Walle,
Michal Simek, Neil Armstrong, Peng Fan, Pengpeng Hou,
Priyanka Jain, Quentin Schulz, Simon Glass, Stefano Babic,
Tanmay Kathpalia, Torsten Rupp, Vincent Jardin, Weijie Gao
MPC8548 silicon is no longer manufactured, and the MPC8548CDS board is
obsolete. Remove the board and its SoC support.
Signed-off-by: Bradley Morgan <brads@mainlining.org>
---
arch/powerpc/cpu/mpc85xx/Kconfig | 37 +--
arch/powerpc/cpu/mpc85xx/Makefile | 1 -
arch/powerpc/cpu/mpc85xx/cpu_init.c | 13 -
arch/powerpc/cpu/mpc85xx/mpc8548_serdes.c | 57 ----
arch/powerpc/dts/Makefile | 1 -
arch/powerpc/dts/mpc8548-post.dtsi | 36 ---
arch/powerpc/dts/mpc8548.dtsi | 27 --
arch/powerpc/dts/mpc8548cds.dts | 29 --
arch/powerpc/dts/mpc8548cds_36b.dts | 29 --
arch/powerpc/include/asm/config_mpc85xx.h | 8 +-
arch/powerpc/include/asm/immap_85xx.h | 3 +-
board/nxp/common/Makefile | 2 -
board/nxp/common/cds_pci_ft.c | 17 --
board/nxp/common/cds_via.c | 95 -------
board/nxp/mpc8548cds/Kconfig | 24 --
board/nxp/mpc8548cds/MAINTAINERS | 8 -
board/nxp/mpc8548cds/Makefile | 10 -
board/nxp/mpc8548cds/ddr.c | 51 ----
board/nxp/mpc8548cds/law.c | 18 --
board/nxp/mpc8548cds/mpc8548cds.c | 170 ------------
board/nxp/mpc8548cds/tlb.c | 87 ------
configs/MPC8548CDS_36BIT_defconfig | 108 --------
configs/MPC8548CDS_defconfig | 106 --------
configs/MPC8548CDS_legacy_defconfig | 106 --------
doc/README.mpc85xxcds | 225 ----------------
env/Kconfig | 1 -
include/configs/MPC8548CDS.h | 312 ----------------------
27 files changed, 4 insertions(+), 1577 deletions(-)
delete mode 100644 arch/powerpc/cpu/mpc85xx/mpc8548_serdes.c
delete mode 100644 arch/powerpc/dts/mpc8548-post.dtsi
delete mode 100644 arch/powerpc/dts/mpc8548.dtsi
delete mode 100644 arch/powerpc/dts/mpc8548cds.dts
delete mode 100644 arch/powerpc/dts/mpc8548cds_36b.dts
delete mode 100644 board/nxp/common/cds_pci_ft.c
delete mode 100644 board/nxp/common/cds_via.c
delete mode 100644 board/nxp/mpc8548cds/Kconfig
delete mode 100644 board/nxp/mpc8548cds/MAINTAINERS
delete mode 100644 board/nxp/mpc8548cds/Makefile
delete mode 100644 board/nxp/mpc8548cds/ddr.c
delete mode 100644 board/nxp/mpc8548cds/law.c
delete mode 100644 board/nxp/mpc8548cds/mpc8548cds.c
delete mode 100644 board/nxp/mpc8548cds/tlb.c
delete mode 100644 configs/MPC8548CDS_36BIT_defconfig
delete mode 100644 configs/MPC8548CDS_defconfig
delete mode 100644 configs/MPC8548CDS_legacy_defconfig
delete mode 100644 doc/README.mpc85xxcds
delete mode 100644 include/configs/MPC8548CDS.h
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index 32a140b0913..309becda5ac 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -115,12 +115,6 @@ config TARGET_P5040DS
imply SATA
imply PANIC_HANG
-config TARGET_MPC8548CDS
- bool "Support MPC8548CDS"
- select ARCH_MPC8548
- select FSL_VIA
- select SYS_CACHE_SHIFT_5
-
config TARGET_P1010RDB_PA
bool "Support P1010RDB_PA"
select ARCH_P1010
@@ -427,25 +421,6 @@ config ARCH_MPC8544
select SYS_PPC_E500_USE_DEBUG_TLB
select FSL_ELBC
-config ARCH_MPC8548
- bool
- select BTB
- select FSL_LAW
- select SYS_FSL_ERRATUM_A005125
- select SYS_FSL_ERRATUM_NMG_DDR120
- select SYS_FSL_ERRATUM_NMG_LBC103
- select SYS_FSL_ERRATUM_NMG_ETSEC129
- select SYS_FSL_ERRATUM_I2C_A004447
- select FSL_PCIE_RESET
- select SYS_FSL_HAS_DDR2
- select SYS_FSL_HAS_DDR1
- select SYS_FSL_HAS_SEC
- select SYS_FSL_RMU
- select SYS_FSL_SEC_BE
- select SYS_FSL_SEC_COMPAT_2
- select SYS_PPC_E500_USE_DEBUG_TLB
- imply CMD_REGINFO
-
config ARCH_MPC8560
bool
select FSL_LAW
@@ -1031,7 +1006,6 @@ config SYS_CCSRBAR_DEFAULT
ARCH_MPC8536 || \
ARCH_MPC8540 || \
ARCH_MPC8544 || \
- ARCH_MPC8548 || \
ARCH_MPC8560 || \
ARCH_P1010 || \
ARCH_P1011 || \
@@ -1182,7 +1156,6 @@ config SYS_FSL_ERRATUM_I2C_A004447
config SYS_FSL_A004447_SVR_REV
hex
depends on SYS_FSL_ERRATUM_I2C_A004447
- default 0x00 if ARCH_MPC8548
default 0x10 if ARCH_P1010
default 0x11 if ARCH_P1023 || ARCH_P2041 || ARCH_BSC9132
default 0x20 if ARCH_P3041 || ARCH_P4080
@@ -1282,8 +1255,7 @@ config SYS_FSL_NUM_LAWS
ARCH_P1024 || \
ARCH_P1025 || \
ARCH_P2020
- default 10 if ARCH_MPC8544 || \
- ARCH_MPC8548
+ default 10 if ARCH_MPC8544
default 8 if ARCH_MPC8540 || \
ARCH_MPC8560
help
@@ -1389,7 +1361,7 @@ config FSL_ELBC
config SYS_PPC_E500_DEBUG_TLB
int "Temporary TLB entry for external debugger"
depends on SYS_PPC_E500_USE_DEBUG_TLB
- default 0 if ARCH_MPC8544 || ARCH_MPC8548
+ default 0 if ARCH_MPC8544
default 1 if ARCH_MPC8536
default 2 if ARCH_P1011 || \
ARCH_P1020 || \
@@ -1425,7 +1397,6 @@ config SYS_FSL_IFC_CLK_DIV
config SYS_FSL_LBC_CLK_DIV
int "Divider of platform clock"
depends on FSL_ELBC || ARCH_MPC8540 || \
- ARCH_MPC8548 || \
ARCH_MPC8560
default 2 if ARCH_P2041 || \
@@ -1537,12 +1508,8 @@ config TPL_SYS_MPC85XX_NO_RESETVEC
the section .bootpg is placed in the previous 4k of the .text section,
of the SPL portion of the binary.
-config FSL_VIA
- bool
-
source "board/CZ.NIC/turris_1x/Kconfig"
source "board/emulation/qemu-ppce500/Kconfig"
-source "board/nxp/mpc8548cds/Kconfig"
source "board/nxp/p1010rdb/Kconfig"
source "board/nxp/p1_p2_rdb_pc/Kconfig"
source "board/nxp/p2041rdb/Kconfig"
diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile
index bf74228efde..6717e2c4578 100644
--- a/arch/powerpc/cpu/mpc85xx/Makefile
+++ b/arch/powerpc/cpu/mpc85xx/Makefile
@@ -57,7 +57,6 @@ obj-$(CONFIG_SYS_FSL_QORIQ_CHASSIS2) += fsl_corenet2_serdes.o
obj-$(CONFIG_ARCH_C29X) += c29x_serdes.o
obj-$(CONFIG_ARCH_MPC8536) += mpc8536_serdes.o
obj-$(CONFIG_ARCH_MPC8544) += mpc8544_serdes.o
-obj-$(CONFIG_ARCH_MPC8548) += mpc8548_serdes.o
obj-$(CONFIG_ARCH_P1010) += p1010_serdes.o
obj-$(CONFIG_ARCH_P1011) += p1021_serdes.o
obj-$(CONFIG_ARCH_P1020) += p1021_serdes.o
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 414782c835f..4390f754809 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -384,19 +384,6 @@ ulong cpu_init_f(void)
#if defined(CONFIG_NXP_ESBC) && !defined(CONFIG_SYS_RAMBOOT)
struct law_entry law;
#endif
-#ifdef CONFIG_ARCH_MPC8548
- ccsr_local_ecm_t *ecm = (void *)(CFG_SYS_MPC85xx_ECM_ADDR);
- uint svr = get_svr();
-
- /*
- * CPU2 errata workaround: A core hang possible while executing
- * a msync instruction and a snoopable transaction from an I/O
- * master tagged to make quick forward progress is present.
- * Fixed in silicon rev 2.1.
- */
- if ((SVR_MAJ(svr) == 1) || ((SVR_MAJ(svr) == 2 && SVR_MIN(svr) == 0x0)))
- out_be32(&ecm->eebpcr, in_be32(&ecm->eebpcr) | (1 << 16));
-#endif
disable_tlb(14);
disable_tlb(15);
diff --git a/arch/powerpc/cpu/mpc85xx/mpc8548_serdes.c b/arch/powerpc/cpu/mpc85xx/mpc8548_serdes.c
deleted file mode 100644
index 924afa096d1..00000000000
--- a/arch/powerpc/cpu/mpc85xx/mpc8548_serdes.c
+++ /dev/null
@@ -1,57 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2010 Freescale Semiconductor, Inc.
- */
-
-#include <config.h>
-#include <log.h>
-#include <asm/io.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_serdes.h>
-
-#define SRDS1_MAX_LANES 8
-
-static u32 serdes1_prtcl_map;
-
-static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = {
- [0x3] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1},
- [0x4] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1},
- [0x5] = {NONE, NONE, NONE, NONE, SRIO1, SRIO1, SRIO1, SRIO1},
- [0x6] = {NONE, NONE, NONE, NONE, SRIO1, SRIO1, SRIO1, SRIO1},
- [0x7] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1},
-};
-
-int is_serdes_configured(enum srds_prtcl prtcl)
-{
- if (!(serdes1_prtcl_map & (1 << NONE)))
- fsl_serdes_init();
-
- return (1 << prtcl) & serdes1_prtcl_map;
-}
-
-void fsl_serdes_init(void)
-{
- ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
- u32 pordevsr = in_be32(&gur->pordevsr);
- u32 srds1_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
- MPC85xx_PORDEVSR_IO_SEL_SHIFT;
- int lane;
-
- if (serdes1_prtcl_map & (1 << NONE))
- return;
-
- debug("PORDEVSR[IO_SEL] = %x\n", srds1_cfg);
-
- if (srds1_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) {
- printf("Invalid PORDEVSR[IO_SEL] = %d\n", srds1_cfg);
- return;
- }
-
- for (lane = 0; lane < SRDS1_MAX_LANES; lane++) {
- enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds1_cfg][lane];
- serdes1_prtcl_map |= (1 << lane_prtcl);
- }
-
- /* Set the first bit to indicate serdes has been initialized */
- serdes1_prtcl_map |= (1 << NONE);
-}
diff --git a/arch/powerpc/dts/Makefile b/arch/powerpc/dts/Makefile
index a9075c16fef..2540684307e 100644
--- a/arch/powerpc/dts/Makefile
+++ b/arch/powerpc/dts/Makefile
@@ -8,7 +8,6 @@ dtb-$(CONFIG_TARGET_KMSUPX5) += kmsupc5.dtb kmsupm5.dtb
dtb-$(CONFIG_TARGET_KMTEGR1) += kmtegr1.dtb
dtb-$(CONFIG_TARGET_KMTEPR2) += kmtepr2.dtb
dtb-$(CONFIG_TARGET_MPC837XERDB) += mpc8379erdb.dtb
-dtb-$(CONFIG_TARGET_MPC8548CDS) += mpc8548cds.dtb mpc8548cds_36b.dtb
dtb-$(CONFIG_TARGET_P1010RDB_PA) += p1010rdb-pa.dtb p1010rdb-pa_36b.dtb
dtb-$(CONFIG_TARGET_P1010RDB_PB) += p1010rdb-pb.dtb p1010rdb-pb_36b.dtb
dtb-$(CONFIG_TARGET_P1020RDB_PC) += p1020rdb-pc.dtb p1020rdb-pc_36b.dtb
diff --git a/arch/powerpc/dts/mpc8548-post.dtsi b/arch/powerpc/dts/mpc8548-post.dtsi
deleted file mode 100644
index 97c3ce6e74d..00000000000
--- a/arch/powerpc/dts/mpc8548-post.dtsi
+++ /dev/null
@@ -1,36 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+ OR X11
-/*
- * MPC8548 Silicon/SoC Device Tree Source (post include)
- *
- * Copyright 2012 Freescale Semiconductor Inc.
- * Copyright 2019 NXP
- */
-
-&soc {
- #address-cells = <1>;
- #size-cells = <1>;
- device_type = "soc";
- compatible = "fsl,mpc8548-immr", "simple-bus";
- bus-frequency = <0x0>;
-
- mpic: pic@40000 {
- interrupt-controller;
- #address-cells = <0>;
- #interrupt-cells = <4>;
- reg = <0x40000 0x40000>;
- compatible = "fsl,mpic";
- device_type = "open-pic";
- big-endian;
- single-cpu-affinity;
- last-interrupt-source = <255>;
- };
-};
-
-&pcie {
- compatible = "fsl,mpc8548-pcie", "fsl,pcie-fsl-qoriq";
- law_trgt_if = <2>;
- #address-cells = <3>;
- #size-cells = <2>;
- device_type = "pci";
- bus-range = <0x0 0xff>;
-};
diff --git a/arch/powerpc/dts/mpc8548.dtsi b/arch/powerpc/dts/mpc8548.dtsi
deleted file mode 100644
index b24567dc653..00000000000
--- a/arch/powerpc/dts/mpc8548.dtsi
+++ /dev/null
@@ -1,27 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+ OR X11
-/*
- * MPC8548CDS Silicon/SoC Device Tree Source (pre include)
- *
- * Copyright 2011 Freescale Semiconductor Inc.
- * Copyright 2019 NXP
- */
-
-/dts-v1/;
-
-/include/ "e500v2_power_isa.dtsi"
-
-/ {
- #address-cells = <2>;
- #size-cells = <2>;
- interrupt-parent = <&mpic>;
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- PowerPC,8548@0 {
- device_type = "cpu";
- reg = <0>;
- };
- };
-};
diff --git a/arch/powerpc/dts/mpc8548cds.dts b/arch/powerpc/dts/mpc8548cds.dts
deleted file mode 100644
index 3b927bd2657..00000000000
--- a/arch/powerpc/dts/mpc8548cds.dts
+++ /dev/null
@@ -1,29 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+ OR X11
-/*
- * MPC8548CDS Device Tree Source
- *
- * Copyright 2006 - 2012 Freescale Semiconductor Inc.
- * Copyright 2019 NXP
- */
-
-/include/ "mpc8548.dtsi"
-
-/ {
- model = "fsl,MPC8548CDS";
- compatible = "fsl,MPC8548CDS";
- #address-cells = <2>;
- #size-cells = <2>;
- interrupt-parent = <&mpic>;
-
- soc: soc8548@e0000000 {
- ranges = <0x0 0x0 0xe0000000 0x100000>;
- };
-
- pcie: pcie@e000a000 {
- reg = <0x0 0xe000a000 0x0 0x1000>; /* registers */
- ranges = <0x01000000 0x0 0x00000000 0x0 0xe3000000 0x0 0x00100000 /* downstream I/O */
- 0x02000000 0x0 0xa0000000 0x0 0xa0000000 0x0 0x20000000>; /* non-prefetchable memory */
- };
-};
-
-/include/ "mpc8548-post.dtsi"
diff --git a/arch/powerpc/dts/mpc8548cds_36b.dts b/arch/powerpc/dts/mpc8548cds_36b.dts
deleted file mode 100644
index 98d7c2410bc..00000000000
--- a/arch/powerpc/dts/mpc8548cds_36b.dts
+++ /dev/null
@@ -1,29 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+ OR X11
-/*
- * MPC8548CDS (36-bit address map) Device Tree Source
- *
- * Copyright 2012 - 2015 Freescale Semiconductor Inc.
- * Copyright 2019 NXP
- */
-
-/include/ "mpc8548.dtsi"
-
-/ {
- model = "fsl,MPC8548CDS";
- compatible = "fsl,MPC8548CDS";
- #address-cells = <2>;
- #size-cells = <2>;
- interrupt-parent = <&mpic>;
-
- soc: soc8548@fe0000000 {
- ranges = <0x0 0xf 0xe0000000 0x100000>;
- };
-
- pcie: pcie@fe000a000 {
- reg = <0xf 0xe000a000 0x0 0x1000>; /* registers */
- ranges = <0x01000000 0x0 0x00000000 0xf 0xe3000000 0x0 0x00100000 /* downstream I/O */
- 0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000>; /* non-prefetchable memory */
- };
-};
-
-/include/ "mpc8548-post.dtsi"
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index abdaffbe00b..d7d18c3eeca 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -10,13 +10,7 @@
#include <fsl_ddrc_version.h>
-#if defined(CONFIG_ARCH_MPC8548)
-#define CFG_SYS_FSL_SRIO_MAX_PORTS 1
-#define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9
-#define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5
-#define CFG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
-
-#elif defined(CONFIG_ARCH_P1021)
+#if defined(CONFIG_ARCH_P1021)
#define QE_MURAM_SIZE 0x6000UL
#define MAX_QE_RISC 1
#define QE_NUM_OF_SNUM 28
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index 3565a287154..9e082a87a3b 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -123,8 +123,7 @@ typedef struct ccsr_i2c {
u8 res[4096 - 1 * sizeof(struct fsl_i2c_base)];
} ccsr_i2c_t;
-#if defined(CONFIG_ARCH_MPC8540) || \
- defined(CONFIG_ARCH_MPC8548)
+#if defined(CONFIG_ARCH_MPC8540)
/* DUART Registers */
typedef struct ccsr_duart {
u8 res1[1280];
diff --git a/board/nxp/common/Makefile b/board/nxp/common/Makefile
index dafd3717948..46e43a4e45a 100644
--- a/board/nxp/common/Makefile
+++ b/board/nxp/common/Makefile
@@ -27,7 +27,6 @@ I2C_COMMON=y
endif
obj-$(CONFIG_FSL_CADMUS) += cadmus.o
-obj-$(CONFIG_FSL_VIA) += cds_via.o
obj-$(CONFIG_FMAN_ENET) += fman.o
ifndef CONFIG_XPL_BUILD
obj-$(CONFIG_FSL_NGPIXIS) += ngpixis.o
@@ -49,7 +48,6 @@ else
obj-$(CONFIG_DEEP_SLEEP) += mpc85xx_sleep.o
endif
-obj-$(CONFIG_TARGET_MPC8548CDS) += cds_pci_ft.o
obj-$(CONFIG_TARGET_P3041DS) += ics307_clk.o
obj-$(CONFIG_TARGET_P4080DS) += ics307_clk.o
diff --git a/board/nxp/common/cds_pci_ft.c b/board/nxp/common/cds_pci_ft.c
deleted file mode 100644
index 56b01e3f51f..00000000000
--- a/board/nxp/common/cds_pci_ft.c
+++ /dev/null
@@ -1,17 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2004 Freescale Semiconductor.
- */
-
-#include <linux/libfdt.h>
-#include <fdt_support.h>
-#include "cadmus.h"
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-int ft_board_setup(void *blob, struct bd_info *bd)
-{
- ft_cpu_setup(blob, bd);
-
- return 0;
-}
-#endif
diff --git a/board/nxp/common/cds_via.c b/board/nxp/common/cds_via.c
deleted file mode 100644
index 6fc3a21780f..00000000000
--- a/board/nxp/common/cds_via.c
+++ /dev/null
@@ -1,95 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2006 Freescale Semiconductor.
- */
-
-#include <pci.h>
-
-/* Config the VIA chip */
-void mpc85xx_config_via(struct pci_controller *hose,
- pci_dev_t dev, struct pci_config_table *tab)
-{
- pci_dev_t bridge;
- unsigned int cmdstat;
-
- /* Enable USB and IDE functions */
- pci_hose_write_config_byte(hose, dev, 0x48, 0x08);
-
- pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat);
- cmdstat |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY| PCI_COMMAND_MASTER;
- pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat);
- pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
- pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
-
- /*
- * Force the backplane P2P bridge to have a window
- * open from 0x00000000-0x00001fff in PCI I/O space.
- * This allows legacy I/O (i8259, etc) on the VIA
- * southbridge to be accessed.
- */
-#ifdef CONFIG_TARGET_MPC8548CDS_LEGACY
- bridge = PCI_BDF(0, 17, 0);
-#else
- bridge = PCI_BDF(0, 28, 0);
-#endif
- pci_hose_write_config_byte(hose, bridge, PCI_IO_BASE, 0);
- pci_hose_write_config_word(hose, bridge, PCI_IO_BASE_UPPER16, 0);
- pci_hose_write_config_byte(hose, bridge, PCI_IO_LIMIT, 0x10);
- pci_hose_write_config_word(hose, bridge, PCI_IO_LIMIT_UPPER16, 0);
-}
-
-/* Function 1, IDE */
-void mpc85xx_config_via_usbide(struct pci_controller *hose,
- pci_dev_t dev, struct pci_config_table *tab)
-{
- pciauto_config_device(hose, dev);
- /*
- * Since the P2P window was forced to cover the fixed
- * legacy I/O addresses, it is necessary to manually
- * place the base addresses for the IDE and USB functions
- * within this window.
- */
- pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0x1ff8);
- pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_1, 0x1ff4);
- pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_2, 0x1fe8);
- pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_3, 0x1fe4);
- pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_4, 0x1fd0);
-}
-
-/* Function 2, USB ports 0-1 */
-void mpc85xx_config_via_usb(struct pci_controller *hose,
- pci_dev_t dev, struct pci_config_table *tab)
-{
- pciauto_config_device(hose, dev);
-
- pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_4, 0x1fa0);
-}
-
-/* Function 3, USB ports 2-3 */
-void mpc85xx_config_via_usb2(struct pci_controller *hose,
- pci_dev_t dev, struct pci_config_table *tab)
-{
- pciauto_config_device(hose, dev);
-
- pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_4, 0x1f80);
-}
-
-/* Function 5, Power Management */
-void mpc85xx_config_via_power(struct pci_controller *hose,
- pci_dev_t dev, struct pci_config_table *tab)
-{
- pciauto_config_device(hose, dev);
-
- pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0x1e00);
- pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_1, 0x1dfc);
- pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_2, 0x1df8);
-}
-
-/* Function 6, AC97 Interface */
-void mpc85xx_config_via_ac97(struct pci_controller *hose,
- pci_dev_t dev, struct pci_config_table *tab)
-{
- pciauto_config_device(hose, dev);
-
- pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0x1c00);
-}
diff --git a/board/nxp/mpc8548cds/Kconfig b/board/nxp/mpc8548cds/Kconfig
deleted file mode 100644
index e43c2030e00..00000000000
--- a/board/nxp/mpc8548cds/Kconfig
+++ /dev/null
@@ -1,24 +0,0 @@
-if TARGET_MPC8548CDS
-
-config PCI1
- def_bool y
-
-config FSL_CADMUS
- def_bool y
-
-config INTERRUPTS
- def_bool y
-
-config SYS_BOARD
- default "mpc8548cds"
-
-config SYS_VENDOR
- default "nxp"
-
-config SYS_CONFIG_NAME
- default "MPC8548CDS"
-
-config TARGET_MPC8548CDS_LEGACY
- bool "Legacy platform support"
-
-endif
diff --git a/board/nxp/mpc8548cds/MAINTAINERS b/board/nxp/mpc8548cds/MAINTAINERS
deleted file mode 100644
index 51e62a34365..00000000000
--- a/board/nxp/mpc8548cds/MAINTAINERS
+++ /dev/null
@@ -1,8 +0,0 @@
-MPC8548CDS BOARD
-M: Priyanka Jain <priyanka.jain@nxp.com>
-S: Maintained
-F: board/nxp/mpc8548cds/
-F: include/configs/MPC8548CDS.h
-F: configs/MPC8548CDS_defconfig
-F: configs/MPC8548CDS_36BIT_defconfig
-F: configs/MPC8548CDS_legacy_defconfig
diff --git a/board/nxp/mpc8548cds/Makefile b/board/nxp/mpc8548cds/Makefile
deleted file mode 100644
index 5ed40e92eb9..00000000000
--- a/board/nxp/mpc8548cds/Makefile
+++ /dev/null
@@ -1,10 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright 2004 Freescale Semiconductor.
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-
-obj-y += mpc8548cds.o
-obj-y += ddr.o
-obj-y += law.o
-obj-y += tlb.o
diff --git a/board/nxp/mpc8548cds/ddr.c b/board/nxp/mpc8548cds/ddr.c
deleted file mode 100644
index 4b8ddcc3ae4..00000000000
--- a/board/nxp/mpc8548cds/ddr.c
+++ /dev/null
@@ -1,51 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright 2008 Freescale Semiconductor, Inc.
- */
-
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-
-void fsl_ddr_board_options(memctl_options_t *popts,
- dimm_params_t *pdimm,
- unsigned int ctrl_num)
-{
- /*
- * Factors to consider for clock adjust:
- * - number of chips on bus
- * - position of slot
- * - DDR1 vs. DDR2?
- * - ???
- *
- * This needs to be determined on a board-by-board basis.
- * 0110 3/4 cycle late
- * 0111 7/8 cycle late
- */
- popts->clk_adjust = 7;
-
- /*
- * Factors to consider for CPO:
- * - frequency
- * - ddr1 vs. ddr2
- */
- popts->cpo_override = 10;
-
- /*
- * Factors to consider for write data delay:
- * - number of DIMMs
- *
- * 1 = 1/4 clock delay
- * 2 = 1/2 clock delay
- * 3 = 3/4 clock delay
- * 4 = 1 clock delay
- * 5 = 5/4 clock delay
- * 6 = 3/2 clock delay
- */
- popts->write_data_delay = 3;
-
- /*
- * Factors to consider for half-strength driver enable:
- * - number of DIMMs installed
- */
- popts->half_strength_driver_enable = 0;
-}
diff --git a/board/nxp/mpc8548cds/law.c b/board/nxp/mpc8548cds/law.c
deleted file mode 100644
index 2334870fda0..00000000000
--- a/board/nxp/mpc8548cds/law.c
+++ /dev/null
@@ -1,18 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2008,2010-2011 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- */
-
-#include <config.h>
-#include <asm/fsl_law.h>
-#include <asm/mmu.h>
-
-struct law_entry law_table[] = {
- /* LBC window - maps 256M */
- SET_LAW(CFG_SYS_LBC_SDRAM_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
-};
-
-int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/nxp/mpc8548cds/mpc8548cds.c b/board/nxp/mpc8548cds/mpc8548cds.c
deleted file mode 100644
index 7810010fd04..00000000000
--- a/board/nxp/mpc8548cds/mpc8548cds.c
+++ /dev/null
@@ -1,170 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2004, 2007, 2009-2011 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
- */
-
-#include <config.h>
-#include <display_options.h>
-#include <init.h>
-#include <net.h>
-#include <pci.h>
-#include <vsprintf.h>
-#include <asm/processor.h>
-#include <asm/mmu.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_pci.h>
-#include <fsl_ddr_sdram.h>
-#include <asm/fsl_serdes.h>
-#include <miiphy.h>
-#include <linux/delay.h>
-#include <linux/libfdt.h>
-#include <fdt_support.h>
-#include <tsec.h>
-#include <fsl_mdio.h>
-#include <netdev.h>
-
-#include "../common/cadmus.h"
-#include "../common/eeprom.h"
-#include "../common/via.h"
-
-void local_bus_init(void);
-
-int checkboard (void)
-{
- volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
- volatile ccsr_local_ecm_t *ecm = (void *)(CFG_SYS_MPC85xx_ECM_ADDR);
-
- /* PCI slot in USER bits CSR[6:7] by convention. */
- uint pci_slot = get_pci_slot ();
-
- uint cpu_board_rev = get_cpu_board_revision ();
-
- puts("Board: MPC8548CDS");
- printf(" Carrier Rev: 0x%02x, PCI Slot %d\n",
- get_board_version(), pci_slot);
- printf(" Daughtercard Rev: %d.%d (0x%04x)\n",
- MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev),
- MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev);
- /*
- * Initialize local bus.
- */
- local_bus_init ();
-
- /*
- * Hack TSEC 3 and 4 IO voltages.
- */
- gur->tsec34ioovcr = 0xe7e0; /* 1110 0111 1110 0xxx */
-
- ecm->eedr = 0xffffffff; /* clear ecm errors */
- ecm->eeer = 0xffffffff; /* enable ecm errors */
- return 0;
-}
-
-/*
- * Initialize Local Bus
- */
-void
-local_bus_init(void)
-{
- volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
- volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
-
- uint clkdiv;
- sys_info_t sysinfo;
-
- get_sys_info(&sysinfo);
- clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2;
-
- gur->lbiuiplldcr1 = 0x00078080;
- if (clkdiv == 16) {
- gur->lbiuiplldcr0 = 0x7c0f1bf0;
- } else if (clkdiv == 8) {
- gur->lbiuiplldcr0 = 0x6c0f1bf0;
- } else if (clkdiv == 4) {
- gur->lbiuiplldcr0 = 0x5c0f1bf0;
- }
-
- lbc->lcrr |= 0x00030000;
-
- asm("sync;isync;msync");
-
- lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */
- lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */
-}
-
-/*
- * Initialize SDRAM memory on the Local Bus.
- */
-void lbc_sdram_init(void)
-{
-#if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
-
- uint idx;
- volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
- uint *sdram_addr = (uint *)CFG_SYS_LBC_SDRAM_BASE;
- uint lsdmr_common;
-
- puts("LBC SDRAM: ");
- print_size(CFG_SYS_LBC_SDRAM_SIZE * 1024 * 1024,
- "\n");
-
- /*
- * Setup SDRAM Base and Option Registers
- */
- set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
- set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
- lbc->lbcr = CFG_SYS_LBC_LBCR;
- asm("msync");
-
- lbc->lsrt = CFG_SYS_LBC_LSRT;
- lbc->mrtpr = CFG_SYS_LBC_MRTPR;
- asm("msync");
-
- /*
- * MPC8548 uses "new" 15-16 style addressing.
- */
- lsdmr_common = CFG_SYS_LBC_LSDMR_COMMON;
- lsdmr_common |= LSDMR_BSMA1516;
-
- /*
- * Issue PRECHARGE ALL command.
- */
- lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL;
- asm("sync;msync");
- *sdram_addr = 0xff;
- ppcDcbf((unsigned long) sdram_addr);
- udelay(100);
-
- /*
- * Issue 8 AUTO REFRESH commands.
- */
- for (idx = 0; idx < 8; idx++) {
- lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH;
- asm("sync;msync");
- *sdram_addr = 0xff;
- ppcDcbf((unsigned long) sdram_addr);
- udelay(100);
- }
-
- /*
- * Issue 8 MODE-set command.
- */
- lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW;
- asm("sync;msync");
- *sdram_addr = 0xff;
- ppcDcbf((unsigned long) sdram_addr);
- udelay(100);
-
- /*
- * Issue NORMAL OP command.
- */
- lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
- asm("sync;msync");
- *sdram_addr = 0xff;
- ppcDcbf((unsigned long) sdram_addr);
- udelay(200); /* Overkill. Must wait > 200 bus cycles */
-
-#endif /* enable SDRAM init */
-}
diff --git a/board/nxp/mpc8548cds/tlb.c b/board/nxp/mpc8548cds/tlb.c
deleted file mode 100644
index 0b2afa8054d..00000000000
--- a/board/nxp/mpc8548cds/tlb.c
+++ /dev/null
@@ -1,87 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2008, 2011 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- */
-
-#include <config.h>
-#include <asm/mmu.h>
-#include <asm/ppc.h>
-
-struct fsl_e_tlb_entry tlb_table[] = {
- /* TLB 0 - for temp stack in cache */
- SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR, CFG_SYS_INIT_RAM_ADDR,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 4 * 1024 , CFG_SYS_INIT_RAM_ADDR + 4 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 8 * 1024 , CFG_SYS_INIT_RAM_ADDR + 8 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 12 * 1024 , CFG_SYS_INIT_RAM_ADDR + 12 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
-
- /* TLB 1 */
- /*
- * Entry 0:
- * FLASH(cover boot page) 16M Non-cacheable, guarded
- */
- SET_TLB_ENTRY(1, CFG_SYS_FLASH_BASE, CFG_SYS_FLASH_BASE_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 0, BOOKE_PAGESZ_16M, 1),
-
- /*
- * Entry 1:
- * CCSRBAR 1M Non-cacheable, guarded
- */
- SET_TLB_ENTRY(1, CFG_SYS_CCSRBAR, CFG_SYS_CCSRBAR_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 1, BOOKE_PAGESZ_1M, 1),
-
- /*
- * Entry 2:
- * LBC SDRAM 64M Cacheable, non-guarded
- */
- SET_TLB_ENTRY(1, CFG_SYS_LBC_SDRAM_BASE,
- CFG_SYS_LBC_SDRAM_BASE_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
- 0, 2, BOOKE_PAGESZ_64M, 1),
-
- /*
- * Entry 3:
- * CADMUS registers 1M Non-cacheable, guarded
- */
- SET_TLB_ENTRY(1, CADMUS_BASE_ADDR, CADMUS_BASE_ADDR_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 3, BOOKE_PAGESZ_1M, 1),
-
- /*
- * Entry 4:
- * PCI and PCIe MEM 1G Non-cacheable, guarded
- */
- SET_TLB_ENTRY(1, CFG_SYS_PCI1_MEM_VIRT, CFG_SYS_PCI1_MEM_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 4, BOOKE_PAGESZ_1G, 1),
-
- /*
- * Entry 5:
- * PCI1 IO 1M Non-cacheable, guarded
- */
- SET_TLB_ENTRY(1, CFG_SYS_PCI1_IO_VIRT, CFG_SYS_PCI1_IO_PHYS,
- MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 5, BOOKE_PAGESZ_1M, 1),
-
- /*
- * Entry 6:
- * PCIe IO 1M Non-cacheable, guarded
- */
- SET_TLB_ENTRY(1, CFG_SYS_PCIE1_IO_VIRT, CFG_SYS_PCIE1_IO_PHYS,
- MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 6, BOOKE_PAGESZ_1M, 1),
-};
-
-int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/configs/MPC8548CDS_36BIT_defconfig b/configs/MPC8548CDS_36BIT_defconfig
deleted file mode 100644
index 45dfb9237cf..00000000000
--- a/configs/MPC8548CDS_36BIT_defconfig
+++ /dev/null
@@ -1,108 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_IMMR=0xE0000000
-CONFIG_TEXT_BASE=0xFFF80000
-CONFIG_SYS_MALLOC_LEN=0x100000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_DEFAULT_DEVICE_TREE="mpc8548cds_36b"
-CONFIG_SYS_MONITOR_LEN=524288
-CONFIG_ENV_ADDR=0xFFF60000
-CONFIG_MPC85xx=y
-CONFIG_SYS_INIT_RAM_LOCK=y
-CONFIG_SYS_SRIO=y
-CONFIG_SRIO1=y
-# CONFIG_CMD_ERRATA is not set
-CONFIG_TARGET_MPC8548CDS=y
-CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
-CONFIG_L2_CACHE=y
-CONFIG_ENABLE_36BIT_PHYS=y
-CONFIG_USE_UBOOTPATH=y
-CONFIG_UBOOTPATH="8548cds/u-boot.bin"
-CONFIG_PCIE1=y
-CONFIG_PHYS_64BIT=y
-CONFIG_DYNAMIC_SYS_CLK_FREQ=y
-CONFIG_BOOTDELAY=10
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_USE_BOOTCOMMAND=y
-CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr - $fdtaddr"
-CONFIG_SYS_PBSIZE=276
-# CONFIG_MISC_INIT_R is not set
-CONFIG_ID_EEPROM=y
-CONFIG_SYS_I2C_EEPROM_CCID=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
-CONFIG_CMD_I2C=y
-CONFIG_LOADS_ECHO=y
-CONFIG_SYS_LOADS_BAUD_CHANGE=y
-CONFIG_CMD_PCI=y
-CONFIG_BOOTP_BOOTFILESIZE=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-# CONFIG_CMD_HASH is not set
-CONFIG_OF_CONTROL=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_USE_BOOTFILE=y
-CONFIG_BOOTFILE="8548cds/uImage.uboot"
-CONFIG_USE_ETHPRIME=y
-CONFIG_ETHPRIME="eTSEC0"
-CONFIG_USE_HOSTNAME=y
-CONFIG_USE_GATEWAYIP=y
-CONFIG_GATEWAYIP="192.168.1.1"
-CONFIG_USE_IPADDR=y
-CONFIG_IPADDR="192.168.1.253"
-CONFIG_USE_NETMASK=y
-CONFIG_NETMASK="255.255.255.0"
-CONFIG_USE_ROOTPATH=y
-CONFIG_ROOTPATH="/nfsroot"
-CONFIG_USE_SERVERIP=y
-CONFIG_SERVERIP="192.168.1.1"
-CONFIG_SPD_EEPROM=y
-CONFIG_CHIP_SELECTS_PER_CTRL=2
-CONFIG_DDR_ECC=y
-CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
-CONFIG_SYS_BR0_PRELIM_BOOL=y
-CONFIG_SYS_BR0_PRELIM=0xFF807001
-CONFIG_SYS_OR0_PRELIM=0xFF806E65
-CONFIG_SYS_BR1_PRELIM_BOOL=y
-CONFIG_SYS_BR1_PRELIM=0xFF007001
-CONFIG_SYS_OR1_PRELIM=0xFF806E65
-CONFIG_SYS_BR2_PRELIM_BOOL=y
-CONFIG_SYS_BR2_PRELIM=0xF0007861
-CONFIG_SYS_OR2_PRELIM=0xFC006901
-CONFIG_SYS_BR3_PRELIM_BOOL=y
-CONFIG_SYS_BR3_PRELIM=0xF8006801
-CONFIG_SYS_OR3_PRELIM=0xFFF00FF7
-CONFIG_DM_I2C=y
-CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
-CONFIG_SYS_I2C_FSL=y
-CONFIG_SYS_I2C_EEPROM_ADDR=0x57
-# CONFIG_MMC is not set
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_FLASH_SHOW_PROGRESS=0
-CONFIG_SYS_FLASH_EMPTY_INFO=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SYS_MAX_FLASH_SECT=128
-CONFIG_SYS_MAX_FLASH_BANKS=2
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_FSL=y
-CONFIG_DM_SERIAL=y
-CONFIG_SYS_NS16550=y
-CONFIG_ADDR_MAP=y
diff --git a/configs/MPC8548CDS_defconfig b/configs/MPC8548CDS_defconfig
deleted file mode 100644
index 13e352b5d1c..00000000000
--- a/configs/MPC8548CDS_defconfig
+++ /dev/null
@@ -1,106 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_IMMR=0xE0000000
-CONFIG_TEXT_BASE=0xFFF80000
-CONFIG_SYS_MALLOC_LEN=0x100000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_DEFAULT_DEVICE_TREE="mpc8548cds"
-CONFIG_SYS_MONITOR_LEN=524288
-CONFIG_ENV_ADDR=0xFFF60000
-CONFIG_MPC85xx=y
-CONFIG_SYS_INIT_RAM_LOCK=y
-CONFIG_SYS_SRIO=y
-CONFIG_SRIO1=y
-# CONFIG_CMD_ERRATA is not set
-CONFIG_TARGET_MPC8548CDS=y
-CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
-CONFIG_L2_CACHE=y
-CONFIG_ENABLE_36BIT_PHYS=y
-CONFIG_USE_UBOOTPATH=y
-CONFIG_UBOOTPATH="8548cds/u-boot.bin"
-CONFIG_PCIE1=y
-CONFIG_DYNAMIC_SYS_CLK_FREQ=y
-CONFIG_BOOTDELAY=10
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_USE_BOOTCOMMAND=y
-CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr - $fdtaddr"
-CONFIG_SYS_PBSIZE=276
-# CONFIG_MISC_INIT_R is not set
-CONFIG_ID_EEPROM=y
-CONFIG_SYS_I2C_EEPROM_CCID=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
-CONFIG_CMD_I2C=y
-CONFIG_LOADS_ECHO=y
-CONFIG_SYS_LOADS_BAUD_CHANGE=y
-CONFIG_CMD_PCI=y
-CONFIG_BOOTP_BOOTFILESIZE=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-# CONFIG_CMD_HASH is not set
-CONFIG_OF_CONTROL=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_USE_BOOTFILE=y
-CONFIG_BOOTFILE="8548cds/uImage.uboot"
-CONFIG_USE_ETHPRIME=y
-CONFIG_ETHPRIME="eTSEC0"
-CONFIG_USE_HOSTNAME=y
-CONFIG_USE_GATEWAYIP=y
-CONFIG_GATEWAYIP="192.168.1.1"
-CONFIG_USE_IPADDR=y
-CONFIG_IPADDR="192.168.1.253"
-CONFIG_USE_NETMASK=y
-CONFIG_NETMASK="255.255.255.0"
-CONFIG_USE_ROOTPATH=y
-CONFIG_ROOTPATH="/nfsroot"
-CONFIG_USE_SERVERIP=y
-CONFIG_SERVERIP="192.168.1.1"
-CONFIG_SPD_EEPROM=y
-CONFIG_CHIP_SELECTS_PER_CTRL=2
-CONFIG_DDR_ECC=y
-CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
-CONFIG_SYS_BR0_PRELIM_BOOL=y
-CONFIG_SYS_BR0_PRELIM=0xFF801001
-CONFIG_SYS_OR0_PRELIM=0xFF806E65
-CONFIG_SYS_BR1_PRELIM_BOOL=y
-CONFIG_SYS_BR1_PRELIM=0xFF001001
-CONFIG_SYS_OR1_PRELIM=0xFF806E65
-CONFIG_SYS_BR2_PRELIM_BOOL=y
-CONFIG_SYS_BR2_PRELIM=0xF0001861
-CONFIG_SYS_OR2_PRELIM=0xFC006901
-CONFIG_SYS_BR3_PRELIM_BOOL=y
-CONFIG_SYS_BR3_PRELIM=0xF8000801
-CONFIG_SYS_OR3_PRELIM=0xFFF00FF7
-CONFIG_DM_I2C=y
-CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
-CONFIG_SYS_I2C_FSL=y
-CONFIG_SYS_I2C_EEPROM_ADDR=0x57
-# CONFIG_MMC is not set
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_FLASH_SHOW_PROGRESS=0
-CONFIG_SYS_FLASH_EMPTY_INFO=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SYS_MAX_FLASH_SECT=128
-CONFIG_SYS_MAX_FLASH_BANKS=2
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_FSL=y
-CONFIG_DM_SERIAL=y
-CONFIG_SYS_NS16550=y
diff --git a/configs/MPC8548CDS_legacy_defconfig b/configs/MPC8548CDS_legacy_defconfig
deleted file mode 100644
index 1a5c1becbb6..00000000000
--- a/configs/MPC8548CDS_legacy_defconfig
+++ /dev/null
@@ -1,106 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_IMMR=0xE0000000
-CONFIG_TEXT_BASE=0xFFF80000
-CONFIG_SYS_MALLOC_LEN=0x100000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_DEFAULT_DEVICE_TREE="mpc8548cds"
-CONFIG_SYS_MONITOR_LEN=524288
-CONFIG_ENV_ADDR=0xFFF60000
-CONFIG_MPC85xx=y
-CONFIG_SYS_INIT_RAM_LOCK=y
-CONFIG_SYS_SRIO=y
-CONFIG_SRIO1=y
-# CONFIG_CMD_ERRATA is not set
-CONFIG_TARGET_MPC8548CDS=y
-CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
-CONFIG_L2_CACHE=y
-CONFIG_ENABLE_36BIT_PHYS=y
-CONFIG_TARGET_MPC8548CDS_LEGACY=y
-CONFIG_USE_UBOOTPATH=y
-CONFIG_UBOOTPATH="8548cds/u-boot.bin"
-CONFIG_PCIE1=y
-CONFIG_DYNAMIC_SYS_CLK_FREQ=y
-CONFIG_BOOTDELAY=10
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_USE_BOOTCOMMAND=y
-CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr - $fdtaddr"
-CONFIG_SYS_PBSIZE=276
-# CONFIG_MISC_INIT_R is not set
-CONFIG_ID_EEPROM=y
-CONFIG_SYS_I2C_EEPROM_CCID=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
-CONFIG_CMD_I2C=y
-CONFIG_LOADS_ECHO=y
-CONFIG_SYS_LOADS_BAUD_CHANGE=y
-CONFIG_CMD_PCI=y
-CONFIG_BOOTP_BOOTFILESIZE=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-# CONFIG_CMD_HASH is not set
-CONFIG_OF_CONTROL=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_USE_BOOTFILE=y
-CONFIG_BOOTFILE="8548cds/uImage.uboot"
-CONFIG_USE_ETHPRIME=y
-CONFIG_ETHPRIME="eTSEC0"
-CONFIG_USE_HOSTNAME=y
-CONFIG_USE_GATEWAYIP=y
-CONFIG_GATEWAYIP="192.168.1.1"
-CONFIG_USE_IPADDR=y
-CONFIG_IPADDR="192.168.1.253"
-CONFIG_USE_NETMASK=y
-CONFIG_NETMASK="255.255.255.0"
-CONFIG_USE_ROOTPATH=y
-CONFIG_ROOTPATH="/nfsroot"
-CONFIG_USE_SERVERIP=y
-CONFIG_SERVERIP="192.168.1.1"
-CONFIG_SPD_EEPROM=y
-CONFIG_CHIP_SELECTS_PER_CTRL=2
-CONFIG_DDR_ECC=y
-CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
-CONFIG_SYS_BR0_PRELIM_BOOL=y
-CONFIG_SYS_BR0_PRELIM=0xFF801001
-CONFIG_SYS_OR0_PRELIM=0xFF806E65
-CONFIG_SYS_BR1_PRELIM_BOOL=y
-CONFIG_SYS_BR1_PRELIM=0xFF001001
-CONFIG_SYS_OR1_PRELIM=0xFF806E65
-CONFIG_SYS_BR2_PRELIM_BOOL=y
-CONFIG_SYS_BR2_PRELIM=0xF0001861
-CONFIG_SYS_OR2_PRELIM=0xFC006901
-CONFIG_SYS_BR3_PRELIM_BOOL=y
-CONFIG_SYS_BR3_PRELIM=0xF8000801
-CONFIG_SYS_OR3_PRELIM=0xFFF00FF7
-CONFIG_DM_I2C=y
-CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
-CONFIG_SYS_I2C_FSL=y
-CONFIG_SYS_I2C_EEPROM_ADDR=0x57
-# CONFIG_MMC is not set
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_FLASH_SHOW_PROGRESS=0
-CONFIG_SYS_FLASH_EMPTY_INFO=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SYS_MAX_FLASH_SECT=128
-CONFIG_SYS_MAX_FLASH_BANKS=2
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_FSL=y
-CONFIG_DM_SERIAL=y
-CONFIG_SYS_NS16550=y
diff --git a/doc/README.mpc85xxcds b/doc/README.mpc85xxcds
deleted file mode 100644
index 79d71cb37f6..00000000000
--- a/doc/README.mpc85xxcds
+++ /dev/null
@@ -1,225 +0,0 @@
-Motorola MPC85xxCDS boards
---------------------------
-
-The CDS family of boards consists of a PCI backplane called the
-"Arcadia", a PCI-form-factor carrier card that plugs into a PCI slot,
-and a CPU daughter card that bolts onto the daughter card.
-
-Much of the content of the README.mpc85xxads for the 85xx ADS boards
-applies to the 85xx CDS boards as well. In particular the toolchain,
-the switch nomenclature, and the basis for the memory map. There are
-some differences, though.
-
-
-Building U-Boot
----------------
-
-The Binutils in current ELDK toolchain will not support MPC85xx
-chip. You need to use binutils-2.14.tar.bz2 (or newer) from
- http://ftp.gnu.org/gnu/binutils.
-
-The 85xx CDS code base is known to compile using:
- gcc (GCC) 3.2.2 20030217 (Yellow Dog Linux 3.0 3.2.2-2a)
-
-
-Memory Map
-----------
-
-The memory map for U-Boot and linux has been extended w.r.t. the ADS
-platform to allow for utilization of all 85xx CDS devices. The memory
-map is setup for linux to operate properly. The linux source when
-configured for MPC85xx CDS has been updated to reflect the new memory
-map.
-
-The mapping is:
-
- 0x0000_0000 0x7fff_ffff DDR 2G
- 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
- 0xa000_0000 0xbfff_ffff PCI2 MEM 512M
- 0xe000_0000 0xe00f_ffff CCSR 1M
- 0xe200_0000 0xe2ff_ffff PCI1 IO 16M
- 0xe300_0000 0xe3ff_ffff PCI2 IO 16M
- 0xf000_0000 0xf7ff_ffff SDRAM 128M
- 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M
- 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M
- 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M
-
- (*) The system control registers (CADMUS) start at offset 0xfdb0_4000
- within the NVRAM/CADMUS region of memory.
-
-
-Using Flash
------------
-
-The CDS board has two flash banks, each 8MB in size (2^23 = 0x00800000).
-There is a switch which allows the boot-bank to be selected. The switch
-settings for updating flash are given below.
-
-The U-Boot commands for copying the boot-bank into the secondary bank are
-as follows:
-
- erase ff780000 ff7fffff
- cp.b fff80000 ff780000 80000
-
-
-U-Boot/kermit commands for downloading an image, then copying
-it into the secondary bank:
-
- loadb
- [Drop to kermit:
- ^\c
- send <u-boot-bin-image>
- c
- ]
-
- erase ff780000 ff7fffff
- cp.b $loadaddr ff780000 80000
-
-
-U-Boot commands for downloading an image via tftp and flashing
-it into the second bank:
-
- tftp 10000 <u-boot.bin.image>
- erase ff780000 ff7fffff
- cp.b 10000 ff780000 80000
-
-
-After copying the image into the second bank of flash, be sure to toggle
-SW2[2] on the carrier card before resetting the board in order to set the
-secondary bank as the boot-bank.
-
-
-Carrier Board Switches
-----------------------
-
-As a reminder, you should read the README.mpc85xxads too.
-
-Most switches on the carrier board should not be changed. The only
-user-settable switches on the carrier board are used to configure
-the flash banks and determining the PCI slot.
-
-The first two bits of SW2 control how flash is used on the board:
-
- 12345678
- --------
- SW2=00XXXXXX FLASH: Boot bank 1, bank 2 available.
- 01XXXXXX FLASH: Boot bank 2, bank 1 available (swapped).
- 10XXXXXX FLASH: Boot promjet, bank 1 available
- 11XXXXXX FLASH: Boot promjet, bank 2 available
-
-The boot bank is always mapped to FF80_0000 and listed first by
-the "flinfo" command. The secondary bank is always FF00_0000.
-
-When using PCI, linux needs to know to which slot the CDS carrier is
-connected.. By convention, the user-specific bits of SW2 are used to
-convey this information:
-
- 12345678
- --------
- SW2=xxxxxx00 PCI SLOT INFORM: The CDS carrier is in slot0 of the Arcadia
- xxxxxx01 PCI SLOT INFORM: The CDS carrier is in slot1 of the Arcadia
- xxxxxx10 PCI SLOT INFORM: The CDS carrier is in slot2 of the Arcadia
- xxxxxx11 PCI SLOT INFORM: The CDS carrier is in slot3 of the Arcadia
-
-These are cleverly, er, clearly silkscreened as Slot 1 through 4,
-respectively, on the Arcadia near the support posts.
-
-
-The default setting of all switches on the carrier board is:
-
- 12345678
- --------
- SW1=01101100
- SW2=0x1111yy x=Flash bank, yy=PCI slot
- SW3=11101111
- SW4=10001000
-
-
-8555/41 CPU Card Switches
--------------------------
-
-Most switches on the CPU Card should not be changed. However, the
-frequency can be changed by setting SW3:
-
- 12345678
- --------
- SW3=XX00XXXX == CORE:CCB 2:1
- XX01XXXX == CORE:CCB 5:2
- XX10XXXX == CORE:CCB 3:1
- XX11XXXX == CORE:CCB 7:2
- XXXX1000 == CCB:SYSCLK 8:1
- XXXX1010 == CCB:SYSCLK 10:1
-
-A safe default setting for all switches on the CPU board is:
-
- 12345678
- --------
- SW1=10001111
- SW2=01000111
- SW3=00001000
- SW4=11111110
-
-
-8548 CPU Card Switches
-----------------------
-And, just to be confusing, in this set of switches:
-
- ON = 1
- OFF = 0
-
-Default
- SW1=11111101
- SW2=10011111
- SW3=11001000 (8X) (2:1)
- SW4=11110011
-
- SW3=X000XXXX == CORE:CCB 4:1
- X001XXXX == CORE:CCB 9:2
- X010XXXX == CORE:CCB 1:1
- X011XXXX == CORE:CCB 3:2
- X100XXXX == CORE:CCB 2:1
- X101XXXX == CORE:CCB 5:2
- X110XXXX == CORE:CCB 3:1
- X111XXXX == CORE:CCB 7:2
- XXXX0000 == CCB:SYSCLK 16:1
- XXXX0001 == RESERVED
- XXXX0010 == CCB:SYSCLK 2:1
- XXXX0011 == CCB:SYSCLK 3:1
- XXXX0100 == CCB:SYSCLK 4:1
- XXXX0101 == CCB:SYSCLK 5:1
- XXXX0110 == CCB:SYSCLK 6:1
- XXXX0111 == RESERVED
- XXXX1000 == CCB:SYSCLK 8:1
- XXXX1001 == CCB:SYSCLK 9:1
- XXXX1010 == CCB:SYSCLK 10:1
- XXXX1011 == RESERVED
- XXXX1100 == CCB:SYSCLK 12:1
- XXXX1101 == CCB:SYSCLK 20:1
- XXXX1110 == RESERVED
- XXXX1111 == RESERVED
-
-
-eDINK Info
-----------
-
-One bank of flash may contain an eDINK image.
-
-Memory Map:
-
- CCSRBAR @ 0xe0000000
- Flash Bank 1 @ 0xfe000000
- Flash Bank 2 @ 0xff000000
- Ram @ 0
-
-Commands for downloading a U-Boot image to memory from edink:
-
- env -c
- time -s 4/8/2004 4:30p
- dl -k -b -o 100000
- [Drop to kermit:
- ^\c
- transmit /binary <u-boot-bin-image>
- c
- ]
-
- fu -l 100000 fe780000 80000
diff --git a/env/Kconfig b/env/Kconfig
index c6df09a3349..fa4cf30af39 100644
--- a/env/Kconfig
+++ b/env/Kconfig
@@ -156,7 +156,6 @@ config ENV_IS_IN_FLASH
default y if M548x || M547x || M5282
default y if MCF532x || MCF52x2
default y if MPC86xx || MPC83xx
- default y if ARCH_MPC8548
default y if SH && !CPU_SH4
help
Define this if you have a flash device which you want to use for the
diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h
deleted file mode 100644
index 71e81e09ddb..00000000000
--- a/include/configs/MPC8548CDS.h
+++ /dev/null
@@ -1,312 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2004, 2007, 2010-2011 Freescale Semiconductor.
- * Copyright 2020 NXP
- */
-
-/*
- * mpc8548cds board configuration file
- *
- * Please refer to doc/README.mpc85xxcds for more info.
- *
- */
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#ifndef __ASSEMBLY__
-#include <linux/stringify.h>
-#endif
-
-/*
- * Only possible on E500 Version 2 or newer cores.
- */
-
-#define CFG_SYS_CCSRBAR 0xe0000000
-#define CFG_SYS_CCSRBAR_PHYS_LOW CFG_SYS_CCSRBAR
-
-/* DDR Setup */
-
-#define CFG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
-#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
-
-/* I2C addresses of SPD EEPROMs */
-#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
-
-/* Make sure required options are set */
-#ifndef CONFIG_SPD_EEPROM
-#error ("CONFIG_SPD_EEPROM is required")
-#endif
-
-/*
- * Physical Address Map
- *
- * 32bit:
- * 0x0000_0000 0x7fff_ffff DDR 2G cacheable
- * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M cacheable
- * 0xa000_0000 0xbfff_ffff PCIe MEM 512M cacheable
- * 0xc000_0000 0xdfff_ffff RapidIO 512M cacheable
- * 0xe000_0000 0xe00f_ffff CCSR 1M non-cacheable
- * 0xe200_0000 0xe20f_ffff PCI1 IO 1M non-cacheable
- * 0xe300_0000 0xe30f_ffff PCIe IO 1M non-cacheable
- * 0xf000_0000 0xf3ff_ffff SDRAM 64M cacheable
- * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS 1M non-cacheable
- * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M non-cacheable
- * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M non-cacheable
- *
- * 36bit:
- * 0x00000_0000 0x07fff_ffff DDR 2G cacheable
- * 0xc0000_0000 0xc1fff_ffff PCI1 MEM 512M cacheable
- * 0xc2000_0000 0xc3fff_ffff PCIe MEM 512M cacheable
- * 0xc4000_0000 0xc5fff_ffff RapidIO 512M cacheable
- * 0xfe000_0000 0xfe00f_ffff CCSR 1M non-cacheable
- * 0xfe200_0000 0xfe20f_ffff PCI1 IO 1M non-cacheable
- * 0xfe300_0000 0xfe30f_ffff PCIe IO 1M non-cacheable
- * 0xff000_0000 0xff3ff_ffff SDRAM 64M cacheable
- * 0xff800_0000 0xff80f_ffff NVRAM/CADMUS 1M non-cacheable
- * 0xfff00_0000 0xfff7f_ffff FLASH (2nd bank) 8M non-cacheable
- * 0xfff80_0000 0xfffff_ffff FLASH (boot bank) 8M non-cacheable
- *
- */
-
-/*
- * Local Bus Definitions
- */
-
-/*
- * FLASH on the Local Bus
- * Two banks, 8M each, using the CFI driver.
- * Boot from BR0/OR0 bank at 0xff00_0000
- * Alternate BR1/OR1 bank at 0xff80_0000
- *
- * BR0, BR1:
- * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
- * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0
- * Port Size = 16 bits = BRx[19:20] = 10
- * Use GPCM = BRx[24:26] = 000
- * Valid = BRx[31] = 1
- *
- * 0 4 8 12 16 20 24 28
- * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0
- * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1
- *
- * OR0, OR1:
- * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0
- * Reserved ORx[17:18] = 11, confusion here?
- * CSNT = ORx[20] = 1
- * ACS = half cycle delay = ORx[21:22] = 11
- * SCY = 6 = ORx[24:27] = 0110
- * TRLX = use relaxed timing = ORx[29] = 1
- * EAD = use external address latch delay = OR[31] = 1
- *
- * 0 4 8 12 16 20 24 28
- * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx
- */
-
-#define CFG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */
-#ifdef CONFIG_PHYS_64BIT
-#define CFG_SYS_FLASH_BASE_PHYS 0xfff000000ull
-#else
-#define CFG_SYS_FLASH_BASE_PHYS CFG_SYS_FLASH_BASE
-#endif
-
-#define CFG_SYS_FLASH_BANKS_LIST \
- {CFG_SYS_FLASH_BASE_PHYS + 0x800000, CFG_SYS_FLASH_BASE_PHYS}
-
-/*
- * SDRAM on the Local Bus
- */
-#define CFG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
-#ifdef CONFIG_PHYS_64BIT
-#define CFG_SYS_LBC_SDRAM_BASE_PHYS 0xff0000000ull
-#else
-#define CFG_SYS_LBC_SDRAM_BASE_PHYS CFG_SYS_LBC_SDRAM_BASE
-#endif
-#define CFG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
-
-/*
- * Base Register 2 and Option Register 2 configure SDRAM.
- * The SDRAM base address, CFG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
- *
- * For BR2, need:
- * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
- * port-size = 32-bits = BR2[19:20] = 11
- * no parity checking = BR2[21:22] = 00
- * SDRAM for MSEL = BR2[24:26] = 011
- * Valid = BR[31] = 1
- *
- * 0 4 8 12 16 20 24 28
- * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
- *
- * FIXME: CFG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
- * FIXME: the top 17 bits of BR2.
- */
-
-/*
- * The SDRAM size in MB, CFG_SYS_LBC_SDRAM_SIZE, is 64.
- *
- * For OR2, need:
- * 64MB mask for AM, OR2[0:7] = 1111 1100
- * XAM, OR2[17:18] = 11
- * 9 columns OR2[19-21] = 010
- * 13 rows OR2[23-25] = 100
- * EAD set for extra time OR[31] = 1
- *
- * 0 4 8 12 16 20 24 28
- * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
- */
-
-#define CFG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
-#define CFG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
-#define CFG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
-#define CFG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/
-
-/*
- * Common settings for all Local Bus SDRAM commands.
- * At run time, either BSMA1516 (for CPU 1.1)
- * or BSMA1617 (for CPU 1.0) (old)
- * is OR'ed in too.
- */
-#define CFG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \
- | LSDMR_PRETOACT7 \
- | LSDMR_ACTTORW7 \
- | LSDMR_BL8 \
- | LSDMR_WRC4 \
- | LSDMR_CL3 \
- | LSDMR_RFEN \
- )
-
-/*
- * The CADMUS registers are connected to CS3 on CDS.
- * The new memory map places CADMUS at 0xf8000000.
- *
- * For BR3, need:
- * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0
- * port-size = 8-bits = BR[19:20] = 01
- * no parity checking = BR[21:22] = 00
- * GPMC for MSEL = BR[24:26] = 000
- * Valid = BR[31] = 1
- *
- * 0 4 8 12 16 20 24 28
- * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801
- *
- * For OR3, need:
- * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0
- * disable buffer ctrl OR[19] = 0
- * CSNT OR[20] = 1
- * ACS OR[21:22] = 11
- * XACS OR[23] = 1
- * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe
- * SETA OR[28] = 0
- * TRLX OR[29] = 1
- * EHTR OR[30] = 1
- * EAD extra time OR[31] = 1
- *
- * 0 4 8 12 16 20 24 28
- * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
- */
-
-#define CADMUS_BASE_ADDR 0xf8000000
-#ifdef CONFIG_PHYS_64BIT
-#define CADMUS_BASE_ADDR_PHYS 0xff8000000ull
-#else
-#define CADMUS_BASE_ADDR_PHYS CADMUS_BASE_ADDR
-#endif
-
-#define CFG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
-#define CFG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
-
-#define CFG_SYS_INIT_SP_OFFSET (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-
-#define CFG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
-
-#define CFG_SYS_NS16550_COM1 (CFG_SYS_CCSRBAR+0x4500)
-#define CFG_SYS_NS16550_COM2 (CFG_SYS_CCSRBAR+0x4600)
-
-/*
- * I2C
- */
-#if !CONFIG_IS_ENABLED(DM_I2C)
-#define CFG_SYS_I2C_NOPROBES { {0, 0x69} }
-#endif
-
-/*
- * General PCI
- * Memory space is mapped 1-1, but I/O space must start from 0.
- */
-#define CFG_SYS_PCI1_MEM_VIRT 0x80000000
-#ifdef CONFIG_PHYS_64BIT
-#define CFG_SYS_PCI1_MEM_PHYS 0xc00000000ull
-#else
-#define CFG_SYS_PCI1_MEM_PHYS 0x80000000
-#endif
-#define CFG_SYS_PCI1_IO_VIRT 0xe2000000
-#ifdef CONFIG_PHYS_64BIT
-#define CFG_SYS_PCI1_IO_PHYS 0xfe2000000ull
-#else
-#define CFG_SYS_PCI1_IO_PHYS 0xe2000000
-#endif
-
-#ifdef CONFIG_PCIE1
-#define CFG_SYS_PCIE1_MEM_VIRT 0xa0000000
-#ifdef CONFIG_PHYS_64BIT
-#define CFG_SYS_PCIE1_MEM_PHYS 0xc20000000ull
-#else
-#define CFG_SYS_PCIE1_MEM_PHYS 0xa0000000
-#endif
-#define CFG_SYS_PCIE1_IO_VIRT 0xe3000000
-#ifdef CONFIG_PHYS_64BIT
-#define CFG_SYS_PCIE1_IO_PHYS 0xfe3000000ull
-#else
-#define CFG_SYS_PCIE1_IO_PHYS 0xe3000000
-#endif
-#endif
-
-/*
- * RapidIO MMU
- */
-#define CFG_SYS_SRIO1_MEM_VIRT 0xc0000000
-#ifdef CONFIG_PHYS_64BIT
-#define CFG_SYS_SRIO1_MEM_PHYS 0xc40000000ull
-#else
-#define CFG_SYS_SRIO1_MEM_PHYS 0xc0000000
-#endif
-#define CFG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */
-
-/*
- * Miscellaneous configurable options
- */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 64 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CFG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
-
-/*
- * Environment Configuration
- */
-
-#define CFG_EXTRA_ENV_SETTINGS \
- "hwconfig=fsl_ddr:ecc=off\0" \
- "netdev=eth0\0" \
- "uboot=" CONFIG_UBOOTPATH "\0" \
- "tftpflash=tftpboot $loadaddr $uboot; " \
- "protect off " __stringify(CONFIG_TEXT_BASE) \
- " +$filesize; " \
- "erase " __stringify(CONFIG_TEXT_BASE) \
- " +$filesize; " \
- "cp.b $loadaddr " __stringify(CONFIG_TEXT_BASE) \
- " $filesize; " \
- "protect on " __stringify(CONFIG_TEXT_BASE) \
- " +$filesize; " \
- "cmp.b $loadaddr " __stringify(CONFIG_TEXT_BASE) \
- " $filesize\0" \
- "consoledev=ttyS1\0" \
- "ramdiskaddr=2000000\0" \
- "ramdiskfile=ramdisk.uboot\0" \
- "fdtaddr=1e00000\0" \
- "fdtfile=mpc8548cds.dtb\0"
-
-#endif /* __CONFIG_H */
--
2.47.3
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH 02/26] board: powerpc: Remove MPC837XERDB support
2026-10-09 19:36 [PATCH 00/26] powerpc: drop EOL boards and SoCs, take over maintenance Bradley Morgan
2026-10-09 19:36 ` [PATCH 01/26] board: powerpc: Remove MPC8548CDS support Bradley Morgan
@ 2026-10-09 19:36 ` Bradley Morgan
2026-10-09 20:18 ` Bradley Morgan
2026-10-09 19:36 ` [PATCH 03/26] board: powerpc: Remove P2020RDB-PC support Bradley Morgan
` (23 subsequent siblings)
25 siblings, 1 reply; 31+ messages in thread
From: Bradley Morgan @ 2026-10-09 19:36 UTC (permalink / raw)
To: Tom Rini, u-boot
Cc: Bradley Morgan, Marek Behún, Marek Mojík,
NXP i . MX U-Boot Team, Alexey Charkov, Anshul Dalal,
Daniel Golle, Fabio Estevam, Gaurav Jain, Ilias Apalodimas,
Jaehoon Chung, James Hilliard, Jerome Forissier, Johan Jonker,
Lukasz Majewski, Marek Vasut, Mario Six, Michael Walle,
Michal Simek, Neil Armstrong, Peng Fan, Pengpeng Hou,
Priyanka Jain, Quentin Schulz, Simon Glass, Stefano Babic,
Tanmay Kathpalia, Torsten Rupp, Vincent Jardin, Weijie Gao
NXP marks the MPC8377ERDB as archived and no longer manufactured. Drop this target and its board files.
Signed-off-by: Bradley Morgan <brads@mainlining.org>
---
arch/powerpc/cpu/mpc83xx/Kconfig | 7 -
arch/powerpc/dts/Makefile | 1 -
arch/powerpc/dts/mpc8379erdb.dts | 153 ------------------
board/nxp/mpc837xerdb/Kconfig | 15 --
board/nxp/mpc837xerdb/MAINTAINERS | 6 -
board/nxp/mpc837xerdb/Makefile | 6 -
board/nxp/mpc837xerdb/README | 97 -----------
board/nxp/mpc837xerdb/mpc837xerdb.c | 242 ----------------------------
configs/MPC837XERDB_defconfig | 193 ----------------------
include/configs/MPC837XERDB.h | 218 -------------------------
10 files changed, 938 deletions(-)
delete mode 100644 arch/powerpc/dts/mpc8379erdb.dts
delete mode 100644 board/nxp/mpc837xerdb/Kconfig
delete mode 100644 board/nxp/mpc837xerdb/MAINTAINERS
delete mode 100644 board/nxp/mpc837xerdb/Makefile
delete mode 100644 board/nxp/mpc837xerdb/README
delete mode 100644 board/nxp/mpc837xerdb/mpc837xerdb.c
delete mode 100644 configs/MPC837XERDB_defconfig
delete mode 100644 include/configs/MPC837XERDB.h
diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig
index 0dc72c87423..088283d646c 100644
--- a/arch/powerpc/cpu/mpc83xx/Kconfig
+++ b/arch/powerpc/cpu/mpc83xx/Kconfig
@@ -24,12 +24,6 @@ config TARGET_CMPCPRO
bool "Support CMPCPRO board from CSSI"
select ARCH_MPC832X
-config TARGET_MPC837XERDB
- bool "Support MPC837XERDB"
- select ARCH_MPC837X
- select BOARD_EARLY_INIT_F
- select SYS_83XX_DDR_USES_CS0
-
config TARGET_KMETER1
bool "Support kmeter1"
select VENDOR_KM
@@ -208,7 +202,6 @@ config FSL_SERDES
config NEVER_ASSERT_ODT_TO_CPU
bool "Never assert ODT to internal IOs"
-source "board/nxp/mpc837xerdb/Kconfig"
source "board/gdsys/mpc8308/Kconfig"
source "board/cssi/cmpcpro/Kconfig"
diff --git a/arch/powerpc/dts/Makefile b/arch/powerpc/dts/Makefile
index 2540684307e..01191273269 100644
--- a/arch/powerpc/dts/Makefile
+++ b/arch/powerpc/dts/Makefile
@@ -7,7 +7,6 @@ dtb-$(CONFIG_TARGET_KMOPTI2) += kmopti2.dtb
dtb-$(CONFIG_TARGET_KMSUPX5) += kmsupc5.dtb kmsupm5.dtb
dtb-$(CONFIG_TARGET_KMTEGR1) += kmtegr1.dtb
dtb-$(CONFIG_TARGET_KMTEPR2) += kmtepr2.dtb
-dtb-$(CONFIG_TARGET_MPC837XERDB) += mpc8379erdb.dtb
dtb-$(CONFIG_TARGET_P1010RDB_PA) += p1010rdb-pa.dtb p1010rdb-pa_36b.dtb
dtb-$(CONFIG_TARGET_P1010RDB_PB) += p1010rdb-pb.dtb p1010rdb-pb_36b.dtb
dtb-$(CONFIG_TARGET_P1020RDB_PC) += p1020rdb-pc.dtb p1020rdb-pc_36b.dtb
diff --git a/arch/powerpc/dts/mpc8379erdb.dts b/arch/powerpc/dts/mpc8379erdb.dts
deleted file mode 100644
index 3db5ececaec..00000000000
--- a/arch/powerpc/dts/mpc8379erdb.dts
+++ /dev/null
@@ -1,153 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+ OR X11
-/*
- * MPC8379E RDB Device Tree Source
- *
- * Copyright 2020 NXP
- */
-
-/dts-v1/;
-
-/ {
- compatible = "fsl,mpc8379erdb";
-
- #address-cells = <1>;
- #size-cells = <1>;
-
- aliases {
- serial0 = &serial0;
- serial1 = &serial1;
- };
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- PowerPC,8379@0 {
- device_type = "cpu";
- reg = <0x0>;
- d-cache-line-size = <32>;
- i-cache-line-size = <32>;
- d-cache-size = <32768>;
- i-cache-size = <32768>;
- timebase-frequency = <0>;
- bus-frequency = <0>;
- clock-frequency = <0>;
- };
- };
-
- memory {
- device_type = "memory";
- reg = <0x00000000 0x10000000>; // 256MB at 0
- };
-
- localbus@e0005000 {
- #address-cells = <2>;
- #size-cells = <1>;
- compatible = "fsl,elbc", "simple-bus";
- reg = <0xe0005000 0x1000>;
- interrupts = <77 0x8>;
- interrupt-parent = <&ipic>;
- };
-
- immr@e0000000 {
- #address-cells = <1>;
- #size-cells = <1>;
- device_type = "soc";
- compatible = "simple-bus";
- ranges = <0 0xe0000000 0x00100000>;
- reg = <0xe0000000 0x00000200>;
- bus-frequency = <0>;
-
- sdhc@2e000 {
- compatible = "fsl,esdhc";
- reg = <0x2e000 0x1000>;
- bus-width = <0x4>;
- clock-frequency = <0>;
- };
-
- serial0: serial@4500 {
- cell-index = <0>;
- device_type = "serial";
- compatible = "fsl,ns16550", "ns16550";
- reg = <0x4500 0x100>;
- clock-frequency = <333333000>;
- interrupts = <9 0x8>;
- interrupt-parent = <&ipic>;
- bootph-all;
- };
-
- serial1: serial@4600 {
- cell-index = <1>;
- device_type = "serial";
- compatible = "fsl,ns16550", "ns16550";
- reg = <0x4600 0x100>;
- clock-frequency = <333333000>;
- interrupts = <10 0x8>;
- interrupt-parent = <&ipic>;
- bootph-all;
- };
-
- ipic: interrupt-controller@700 {
- compatible = "fsl,ipic";
- interrupt-controller;
- #address-cells = <0>;
- #interrupt-cells = <2>;
- reg = <0x700 0x100>;
- device_type = "ipic";
- };
-
- usb@23000 {
- compatible = "fsl-usb2-dr";
- reg = <0x23000 0x1000>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupt-parent = <&ipic>;
- interrupts = <38 0x8>;
- phy_type = "ulpi";
- };
-
- enet0: ethernet@24000 {
- #address-cells = <1>;
- #size-cells = <1>;
- cell-index = <0>;
- device_type = "network";
- model = "eTSEC";
- compatible = "fsl,etsec2";
- reg = <0x24000 0x1000>;
- ranges = <0x0 0x24000 0x1000>;
- local-mac-address = [ 00 00 00 00 00 00 ];
- interrupts = <32 0x8 33 0x8 34 0x8>;
- phy-connection-type = "mii";
- interrupt-parent = <&ipic>;
- fixed-link = <1 0 1000 0 0>;
- phy-handle = <&phy>;
- fsl,magic-packet;
-
- mdio@520 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "fsl,etsec2-mdio";
- reg = <0x520 0x20>;
-
- phy: ethernet-phy@2 {
- interrupt-parent = <&ipic>;
- interrupts = <17 0x8>;
- reg = <0x2>;
- device_type = "ethernet-phy";
- };
- };
- };
-
- pci0: pci@e0008300 {
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
- device_type = "pci";
- reg = <0x0 0xe0008300 0x0 0x00000fff>;
- compatible = "fsl,mpc837x-pci";
- clock-frequency = <0>;
- };
-
- };
-
-};
diff --git a/board/nxp/mpc837xerdb/Kconfig b/board/nxp/mpc837xerdb/Kconfig
deleted file mode 100644
index f11f6f5bfea..00000000000
--- a/board/nxp/mpc837xerdb/Kconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-if TARGET_MPC837XERDB
-
-config PCIE
- def_bool y
-
-config SYS_BOARD
- default "mpc837xerdb"
-
-config SYS_VENDOR
- default "nxp"
-
-config SYS_CONFIG_NAME
- default "MPC837XERDB"
-
-endif
diff --git a/board/nxp/mpc837xerdb/MAINTAINERS b/board/nxp/mpc837xerdb/MAINTAINERS
deleted file mode 100644
index cc0a6acd8c3..00000000000
--- a/board/nxp/mpc837xerdb/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-MPC837XERDB BOARD
-M: Sinan Akman <sinan@writeme.com>
-S: Maintained
-F: board/nxp/mpc837xerdb/
-F: include/configs/MPC837XERDB.h
-F: configs/MPC837XERDB_defconfig
diff --git a/board/nxp/mpc837xerdb/Makefile b/board/nxp/mpc837xerdb/Makefile
deleted file mode 100644
index 4661e4cf232..00000000000
--- a/board/nxp/mpc837xerdb/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-
-obj-y += mpc837xerdb.o
diff --git a/board/nxp/mpc837xerdb/README b/board/nxp/mpc837xerdb/README
deleted file mode 100644
index 12df2f2e756..00000000000
--- a/board/nxp/mpc837xerdb/README
+++ /dev/null
@@ -1,97 +0,0 @@
-Freescale MPC837xE-RDB Board
------------------------------------------
-
-1. Board Description
-
- The MPC837xE-RDB are reference boards featuring the Freescale MPC8377E,
- MPC8378E, and the MPC8379E processors in a Mini-ITX form factor.
-
- The MPC837xE-RDB's have the following common features:
-
- A) 256-MBytes on-board DDR2 unbuffered SDRAM
- B) 8-Mbytes NOR Flash
- C) 32-MBytes NAND Flash
- D) 1 Secure Digital High Speed Card (SDHC) Interface
- E) 1 Gigabit Ethernet
- F) 5-port Ethernet switch (Vitesse 7385)
- G) 1 32-bit, 3.3 V, PCI slot
- H) 1 32-bit, 3.3 V, Mini-PCI slot
- I) 4-port USB 2.0 Hub
- J) 1-port OTG USB
- K) 2 serial ports (top main console)
- L) on board Oscillator: 66M
-
- The MPC837xE-RDB's have the following differences:
-
- MPC8377E-RDB MPC8378E-RDB MPC8379E-RDB
- SATA controllers 2 0 4
- PCI-Express (mini) 2 2 0
- SGMII Ports 0 2 0
-
-
-2. Memory Map
-
-2.1. The memory map should look pretty much like this:
-
- Address Range Device Size Port Size
- (Bytes) (Bits)
- =========================== ================= ======= =========
- 0x0000_0000 0x0fff_ffff DDR 256M 64
- 0x1000_0000 0x7fff_ffff Empty 1.75G -
- 0x8000_0000 0x8fff_ffff PCI MEM prefetch 256M 32
- 0x9000_0000 0x9fff_ffff PCI MEM non-prefetch 256M 32
- 0xe030_0000 0xe03f_ffff PCI I/O space 1M 32
- 0xe000_0000 0xe00f_ffff Int Mem Reg Space 1M -
- 0xe060_0000 0xe060_7fff NAND Flash 32K 8
- 0xfe00_0000 0xfe7f_ffff NOR Flash on CS0 8M 16
-
-
-3. Definitions
-
-3.1 Explanation of NEW definitions in:
-
- include/configs/MPC837XERDB.h
-
- CONFIG_MPC83xx MPC83xx family for both MPC8349 and MPC8360
- CONFIG_MPC837x MPC837x specific
- CONFIG_MPC837XERDB MPC837xE-RDB board specific
-
-
-4. Compilation
-
- Assuming you're using BASH shell:
-
- export CROSS_COMPILE=your-cross-compile-prefix
- cd u-boot
- make distclean
- make MPC837XERDB_config
- make
-
-
-5. Downloading and Flashing Images
-
-5.0 Download over serial line using Kermit:
-
- loadb $loadaddr
- [Drop to kermit:
- ^\c
- send <u-boot-bin-image>
- c
- ]
-
-
- Or via tftp:
-
- tftp $loadaddr u-boot.bin
-
-5.1 Reflash U-Boot Image using U-Boot
-
- tftp $loadaddr u-boot.bin
- protect off fe000000 fe0fffff
- erase fe000000 fe0fffff
- cp.b $loadaddr fe000000 $filesize
-
-
-6. Additional Notes:
- 1) The console is connected to the top RS-232 connector and the
- baudrate for MPC837XE-RDB is 115200bps.
diff --git a/board/nxp/mpc837xerdb/mpc837xerdb.c b/board/nxp/mpc837xerdb/mpc837xerdb.c
deleted file mode 100644
index 55299745a3c..00000000000
--- a/board/nxp/mpc837xerdb/mpc837xerdb.c
+++ /dev/null
@@ -1,242 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2007 Freescale Semiconductor, Inc.
- * Kevin Lam <kevin.lam@freescale.com>
- * Joe D'Abbraccio <joe.d'abbraccio@freescale.com>
- */
-
-#include <config.h>
-#include <env.h>
-#include <hwconfig.h>
-#include <i2c.h>
-#include <init.h>
-#include <asm/bitops.h>
-#include <asm/global_data.h>
-#include <asm/io.h>
-#include <asm/fsl_mpc83xx_serdes.h>
-#include <fdt_support.h>
-#include <spd_sdram.h>
-#include <vsc7385.h>
-#include <fsl_esdhc.h>
-#include <linux/delay.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#if defined(CFG_SYS_DRAM_TEST)
-int
-testdram(void)
-{
- uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
- uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
- uint *p;
-
- printf("Testing DRAM from 0x%08x to 0x%08x\n",
- CONFIG_SYS_MEMTEST_START,
- CONFIG_SYS_MEMTEST_END);
-
- printf("DRAM test phase 1:\n");
- for (p = pstart; p < pend; p++)
- *p = 0xaaaaaaaa;
-
- for (p = pstart; p < pend; p++) {
- if (*p != 0xaaaaaaaa) {
- printf("DRAM test fails at: %08x\n", (uint) p);
- return 1;
- }
- }
-
- printf("DRAM test phase 2:\n");
- for (p = pstart; p < pend; p++)
- *p = 0x55555555;
-
- for (p = pstart; p < pend; p++) {
- if (*p != 0x55555555) {
- printf("DRAM test fails at: %08x\n", (uint) p);
- return 1;
- }
- }
-
- printf("DRAM test passed.\n");
- return 0;
-}
-#endif
-
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
-void ddr_enable_ecc(unsigned int dram_size);
-#endif
-int fixed_sdram(void);
-
-int dram_init(void)
-{
- immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
- u32 msize = 0;
-
- if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
- return -ENXIO;
-
-#if defined(CONFIG_SPD_EEPROM)
- msize = spd_sdram();
-#else
- msize = fixed_sdram();
-#endif
-
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
- /* Initialize DDR ECC byte */
- ddr_enable_ecc(msize * 1024 * 1024);
-#endif
- /* return total bus DDR size(bytes) */
- gd->ram_size = msize * 1024 * 1024;
-
- return 0;
-}
-
-#if !defined(CONFIG_SPD_EEPROM)
-/*************************************************************************
- * fixed sdram init -- doesn't use serial presence detect.
- ************************************************************************/
-int fixed_sdram(void)
-{
- immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
- u32 msize = CFG_SYS_SDRAM_SIZE;
- u32 msize_log2 = __ilog2(msize);
-
- im->sysconf.ddrlaw[0].bar = CFG_SYS_SDRAM_BASE & 0xfffff000;
- im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
-
- im->sysconf.ddrcdr = CFG_SYS_DDRCDR_VALUE;
- udelay(50000);
-
- im->ddr.sdram_clk_cntl = CFG_SYS_DDR_SDRAM_CLK_CNTL;
- udelay(1000);
-
- im->ddr.csbnds[0].csbnds = CFG_SYS_DDR_CS0_BNDS;
- im->ddr.cs_config[0] = CFG_SYS_DDR_CS0_CONFIG;
- udelay(1000);
-
- im->ddr.timing_cfg_0 = CFG_SYS_DDR_TIMING_0;
- im->ddr.timing_cfg_1 = CFG_SYS_DDR_TIMING_1;
- im->ddr.timing_cfg_2 = CFG_SYS_DDR_TIMING_2;
- im->ddr.timing_cfg_3 = CFG_SYS_DDR_TIMING_3;
- im->ddr.sdram_cfg = CFG_SYS_DDR_SDRAM_CFG;
- im->ddr.sdram_cfg2 = CFG_SYS_DDR_SDRAM_CFG2;
- im->ddr.sdram_mode = CFG_SYS_DDR_MODE;
- im->ddr.sdram_mode2 = CFG_SYS_DDR_MODE2;
- im->ddr.sdram_interval = CFG_SYS_DDR_INTERVAL;
- sync();
- udelay(1000);
-
- im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
- udelay(2000);
- return CFG_SYS_SDRAM_SIZE >> 20;
-}
-#endif /*!CONFIG_SYS_SPD_EEPROM */
-
-int checkboard(void)
-{
- puts("Board: Freescale MPC837xERDB\n");
- return 0;
-}
-
-int board_early_init_f(void)
-{
- immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
-#ifdef CONFIG_FSL_SERDES
- u32 spridr = in_be32(&immr->sysconf.spridr);
-
- /* we check only part num, and don't look for CPU revisions */
- switch (PARTID_NO_E(spridr)) {
- case SPR_8377:
- fsl_setup_serdes(CFG_FSL_SERDES1, FSL_SERDES_PROTO_SATA,
- FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
- fsl_setup_serdes(CFG_FSL_SERDES2, FSL_SERDES_PROTO_PEX,
- FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
- break;
- case SPR_8378:
- fsl_setup_serdes(CFG_FSL_SERDES2, FSL_SERDES_PROTO_PEX,
- FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
- break;
- case SPR_8379:
- fsl_setup_serdes(CFG_FSL_SERDES1, FSL_SERDES_PROTO_SATA,
- FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
- fsl_setup_serdes(CFG_FSL_SERDES2, FSL_SERDES_PROTO_SATA,
- FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
- break;
- default:
- printf("serdes not configured: unknown CPU part number: "
- "%04x\n", spridr >> 16);
- break;
- }
-#endif /* CONFIG_FSL_SERDES */
-
-#ifdef CONFIG_FSL_ESDHC
- clrsetbits_be32(&immr->sysconf.sicrl, SICRL_USB_B, SICRL_USB_B_SD);
- clrsetbits_be32(&immr->sysconf.sicrh, SICRH_SPI, SICRH_SPI_SD);
-#endif
- return 0;
-}
-
-#ifdef CONFIG_FSL_ESDHC
-#if !(CONFIG_IS_ENABLED(DM_MMC) || CONFIG_IS_ENABLED(DM_USB))
-int board_mmc_init(struct bd_info *bd)
-{
- struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR;
- char buffer[HWCONFIG_BUFFER_SIZE] = {0};
- int esdhc_hwconfig_enabled = 0;
-
- if (env_get_f("hwconfig", buffer, sizeof(buffer)) > 0)
- esdhc_hwconfig_enabled = hwconfig_f("esdhc", buffer);
-
- if (esdhc_hwconfig_enabled == 0)
- return 0;
-
- clrsetbits_be32(&im->sysconf.sicrl, SICRL_USB_B, SICRL_USB_B_SD);
- clrsetbits_be32(&im->sysconf.sicrh, SICRH_SPI, SICRH_SPI_SD);
-
- return fsl_esdhc_mmc_init(bd);
-}
-#endif
-#endif
-
-/*
- * Miscellaneous late-boot configurations
- *
- * If a VSC7385 microcode image is present, then upload it.
-*/
-int misc_init_r(void)
-{
- int rc = 0;
-
-#ifdef CFG_VSC7385_IMAGE
- if (vsc7385_upload_firmware((void *) CFG_VSC7385_IMAGE,
- CFG_VSC7385_IMAGE_SIZE)) {
- puts("Failure uploading VSC7385 microcode.\n");
- rc = 1;
- }
-#endif
-
- return rc;
-}
-
-int board_late_init(void)
-{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-#ifdef CONFIG_USB_HOST
- clrsetbits_be32(&immap->sysconf.sicrl, SICRL_USB_A, 0x40000000);
-#endif
- return 0;
-}
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-
-int ft_board_setup(void *blob, struct bd_info *bd)
-{
-#ifdef CONFIG_PCI
- ft_pci_setup(blob, bd);
-#endif
- ft_cpu_setup(blob, bd);
- fsl_fdt_fixup_dr_usb(blob, bd);
- fdt_fixup_esdhc(blob, bd);
-
- return 0;
-}
-#endif /* CONFIG_OF_BOARD_SETUP */
diff --git a/configs/MPC837XERDB_defconfig b/configs/MPC837XERDB_defconfig
deleted file mode 100644
index a9d06785186..00000000000
--- a/configs/MPC837XERDB_defconfig
+++ /dev/null
@@ -1,193 +0,0 @@
-CONFIG_PPC=y
-CONFIG_TEXT_BASE=0xFE000000
-CONFIG_SYS_MALLOC_LEN=0x80000
-CONFIG_ENV_SIZE=0x4000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_DEFAULT_DEVICE_TREE="mpc8379erdb"
-CONFIG_SYS_MONITOR_LEN=524288
-CONFIG_DEBUG_UART_BASE=0xe0004500
-CONFIG_DEBUG_UART_CLOCK=333333000
-CONFIG_SYS_CLK_FREQ=66666667
-CONFIG_ENV_ADDR=0xFE080000
-# CONFIG_SYS_PCI_64BIT is not set
-CONFIG_MPC83xx=y
-CONFIG_HIGH_BATS=y
-CONFIG_SYS_INIT_RAM_LOCK=y
-CONFIG_TARGET_MPC837XERDB=y
-CONFIG_DDR_MC_CLOCK_MODE_1_1=y
-CONFIG_SYSTEM_PLL_FACTOR_5_1=y
-CONFIG_CORE_PLL_RATIO_2_1=y
-CONFIG_PCI_HOST_MODE_ENABLE=y
-CONFIG_PCI_INT_ARBITER1_ENABLE=y
-CONFIG_BOOT_MEMORY_SPACE_LOW=y
-CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
-CONFIG_TSEC1_MODE_RGMII=y
-CONFIG_TSEC2_MODE_RGMII=y
-CONFIG_LDP_PIN_MUX_STATE_0=y
-CONFIG_BAT0=y
-CONFIG_BAT0_NAME="SDRAM_LOWER"
-CONFIG_BAT0_BASE=0x00000000
-CONFIG_BAT0_LENGTH_256_MBYTES=y
-CONFIG_BAT0_ACCESS_RW=y
-CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
-CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
-CONFIG_BAT0_USER_MODE_VALID=y
-CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT1=y
-CONFIG_BAT1_NAME="SDRAM_UPPER"
-CONFIG_BAT1_BASE=0x10000000
-CONFIG_BAT1_LENGTH_256_MBYTES=y
-CONFIG_BAT1_ACCESS_RW=y
-CONFIG_BAT1_ICACHE_MEMORYCOHERENCE=y
-CONFIG_BAT1_DCACHE_MEMORYCOHERENCE=y
-CONFIG_BAT1_USER_MODE_VALID=y
-CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT2=y
-CONFIG_BAT2_NAME="IMMR"
-CONFIG_BAT2_BASE=0xE0000000
-CONFIG_BAT2_LENGTH_8_MBYTES=y
-CONFIG_BAT2_ACCESS_RW=y
-CONFIG_BAT2_ICACHE_INHIBITED=y
-CONFIG_BAT2_DCACHE_INHIBITED=y
-CONFIG_BAT2_DCACHE_GUARDED=y
-CONFIG_BAT2_USER_MODE_VALID=y
-CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT3=y
-CONFIG_BAT3_NAME="L2_SWITCH"
-CONFIG_BAT3_BASE=0xF0000000
-CONFIG_BAT3_ACCESS_RW=y
-CONFIG_BAT3_ICACHE_INHIBITED=y
-CONFIG_BAT3_DCACHE_INHIBITED=y
-CONFIG_BAT3_DCACHE_GUARDED=y
-CONFIG_BAT3_USER_MODE_VALID=y
-CONFIG_BAT3_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT4=y
-CONFIG_BAT4_NAME="FLASH"
-CONFIG_BAT4_BASE=0xFE000000
-CONFIG_BAT4_LENGTH_32_MBYTES=y
-CONFIG_BAT4_ACCESS_RW=y
-CONFIG_BAT4_ICACHE_MEMORYCOHERENCE=y
-CONFIG_BAT4_DCACHE_INHIBITED=y
-CONFIG_BAT4_DCACHE_GUARDED=y
-CONFIG_BAT4_USER_MODE_VALID=y
-CONFIG_BAT4_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT5=y
-CONFIG_BAT5_NAME="STACH_IN_DCACHE"
-CONFIG_BAT5_BASE=0xE6000000
-CONFIG_BAT5_ACCESS_RW=y
-CONFIG_BAT5_USER_MODE_VALID=y
-CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT6=y
-CONFIG_BAT6_NAME="PCI_MEM"
-CONFIG_BAT6_BASE=0x80000000
-CONFIG_BAT6_LENGTH_256_MBYTES=y
-CONFIG_BAT6_ACCESS_RW=y
-CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y
-CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y
-CONFIG_BAT6_USER_MODE_VALID=y
-CONFIG_BAT6_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT7=y
-CONFIG_BAT7_NAME="PCI_MMIO"
-CONFIG_BAT7_BASE=0x90000000
-CONFIG_BAT7_LENGTH_256_MBYTES=y
-CONFIG_BAT7_ACCESS_RW=y
-CONFIG_BAT7_ICACHE_INHIBITED=y
-CONFIG_BAT7_DCACHE_INHIBITED=y
-CONFIG_BAT7_DCACHE_GUARDED=y
-CONFIG_BAT7_USER_MODE_VALID=y
-CONFIG_BAT7_SUPERVISOR_MODE_VALID=y
-CONFIG_LBLAW0=y
-CONFIG_LBLAW0_BASE=0xFE000000
-CONFIG_LBLAW0_NAME="FLASH"
-CONFIG_LBLAW0_LENGTH_8_MBYTES=y
-CONFIG_LBLAW1=y
-CONFIG_LBLAW1_BASE=0xE0600000
-CONFIG_LBLAW1_NAME="NAND"
-CONFIG_LBLAW1_LENGTH_32_KBYTES=y
-CONFIG_LBLAW2=y
-CONFIG_LBLAW2_BASE=0xF0000000
-CONFIG_LBLAW2_NAME="VSC7385"
-CONFIG_LBLAW2_LENGTH_128_KBYTES=y
-CONFIG_HID0_FINAL_EMCP=y
-CONFIG_HID0_FINAL_ICE=y
-CONFIG_HID2_HBE=y
-CONFIG_ACR_PIPE_DEP_4=y
-CONFIG_ACR_RPTCNT_4=y
-CONFIG_SPCR_TSECEP_3=y
-CONFIG_LCRR_DBYP_PLL_BYPASSED=y
-CONFIG_LCRR_CLKDIV_8=y
-CONFIG_FSL_SERDES=y
-CONFIG_USE_UBOOTPATH=y
-CONFIG_DEBUG_UART=y
-CONFIG_BOOTDELAY=6
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_PBSIZE=276
-CONFIG_BOARD_LATE_INIT=y
-CONFIG_MISC_INIT_R=y
-CONFIG_PCI_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_LOADS_ECHO=y
-CONFIG_SYS_LOADS_BAUD_CHANGE=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_BOOTP_BOOTFILESIZE=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_OF_CONTROL=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_USE_BOOTFILE=y
-CONFIG_BOOTFILE="uImage"
-CONFIG_USE_ETHPRIME=y
-CONFIG_ETHPRIME="TSEC0"
-CONFIG_USE_HOSTNAME=y
-CONFIG_HOSTNAME="mpc837x_rdb"
-CONFIG_USE_ROOTPATH=y
-CONFIG_ROOTPATH="/nfsroot"
-CONFIG_SATA=y
-CONFIG_FSL_SATA=y
-CONFIG_SYS_SATA_MAX_DEVICE=2
-CONFIG_SYS_BR0_PRELIM_BOOL=y
-CONFIG_SYS_BR0_PRELIM=0xFE001001
-CONFIG_SYS_OR0_PRELIM=0xFF800193
-CONFIG_SYS_BR1_PRELIM_BOOL=y
-CONFIG_SYS_BR1_PRELIM=0xE0600C21
-CONFIG_SYS_OR1_PRELIM=0xFFFF8396
-CONFIG_SYS_BR2_PRELIM_BOOL=y
-CONFIG_SYS_BR2_PRELIM=0xF0000801
-CONFIG_SYS_OR2_PRELIM=0xFFFE09FF
-CONFIG_SYS_I2C_LEGACY=y
-CONFIG_SYS_I2C_FSL=y
-CONFIG_SYS_FSL_I2C_OFFSET=0x3000
-CONFIG_SYS_I2C_SLAVE=0x7F
-CONFIG_SYS_I2C_SPEED=400000
-CONFIG_FSL_ESDHC=y
-CONFIG_FSL_ESDHC_PIN_MUX=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_FLASH_SHOW_PROGRESS=0
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_EMPTY_INFO=y
-CONFIG_SYS_FLASH_PROTECTION=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SYS_MAX_FLASH_SECT=256
-CONFIG_DM_MDIO=y
-CONFIG_DM_ETH_PHY=y
-CONFIG_RGMII=y
-CONFIG_MII=y
-CONFIG_VSC7385_ENET=y
-CONFIG_TSEC_ENET=y
-CONFIG_RTC_DS1374=y
-CONFIG_SPECIFY_CONSOLE_INDEX=y
-CONFIG_DM_SERIAL=y
-CONFIG_SYS_NS16550=y
-CONFIG_USB=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_EHCI_FSL=y
diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h
deleted file mode 100644
index b22c720d07f..00000000000
--- a/include/configs/MPC837XERDB.h
+++ /dev/null
@@ -1,218 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2007 Freescale Semiconductor, Inc.
- * Kevin Lam <kevin.lam@freescale.com>
- * Joe D'Abbraccio <joe.d'abbraccio@freescale.com>
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <linux/stringify.h>
-
-/*
- * High Level Configuration Options
- */
-
-/* System performance - define the value i.e. CONFIG_SYS_XXX
-*/
-
-/* System Clock Configuration Register */
-#define CFG_SYS_SCCR_TSEC1CM 1 /* eTSEC1 clock mode (0-3) */
-#define CFG_SYS_SCCR_TSEC2CM 1 /* eTSEC2 clock mode (0-3) */
-#define CFG_SYS_SCCR_SATACM SCCR_SATACM_2 /* SATA1-4 clock mode (0-3) */
-
-/*
- * System IO Config
- */
-#define CFG_SYS_SICRH 0x08200000
-#define CFG_SYS_SICRL 0x00000000
-
-/*
- * Output Buffer Impedance
- */
-#define CFG_SYS_OBIR 0x30100000
-
-/*
- * Device configurations
- */
-
-/* Vitesse 7385 */
-
-#ifdef CONFIG_VSC7385_ENET
-
-/* The flash address and size of the VSC7385 firmware image */
-#define CFG_VSC7385_IMAGE 0xFE7FE000
-#define CFG_VSC7385_IMAGE_SIZE 8192
-
-#endif
-
-/*
- * DDR Setup
- */
-#define CFG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */
-#define CFG_SYS_DDR_SDRAM_CLK_CNTL 0x03000000
-
-#define CFG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN | DDRCDR_ODT | DDRCDR_Q_DRN)
-
-/*
- * Manually set up DDR parameters
- */
-#define CFG_SYS_SDRAM_SIZE 0x10000000 /* 256 MiB */
-#define CFG_SYS_DDR_CS0_BNDS 0x0000000f
-#define CFG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
- | CSCONFIG_ODT_WR_ONLY_CURRENT \
- | CSCONFIG_ROW_BIT_13 \
- | CSCONFIG_COL_BIT_10)
-
-#define CFG_SYS_DDR_TIMING_3 0x00000000
-#define CFG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
- | (0 << TIMING_CFG0_WRT_SHIFT) \
- | (0 << TIMING_CFG0_RRT_SHIFT) \
- | (0 << TIMING_CFG0_WWT_SHIFT) \
- | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
- | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
- | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
- | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
- /* 0x00260802 */ /* DDR400 */
-#define CFG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
- | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
- | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
- | (7 << TIMING_CFG1_CASLAT_SHIFT) \
- | (13 << TIMING_CFG1_REFREC_SHIFT) \
- | (3 << TIMING_CFG1_WRREC_SHIFT) \
- | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
- | (2 << TIMING_CFG1_WRTORD_SHIFT))
- /* 0x3937d322 */
-#define CFG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
- | (5 << TIMING_CFG2_CPO_SHIFT) \
- | (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
- | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
- | (3 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
- | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
- | (8 << TIMING_CFG2_FOUR_ACT_SHIFT))
- /* 0x02984cc8 */
-
-#define CFG_SYS_DDR_INTERVAL ((1024 << SDRAM_INTERVAL_REFINT_SHIFT) \
- | (0 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
- /* 0x06090100 */
-
-#define CFG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
- | SDRAM_CFG_SDRAM_TYPE_DDR2)
- /* 0x43000000 */
-#define CFG_SYS_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */
-#define CFG_SYS_DDR_MODE ((0x0406 << SDRAM_MODE_ESD_SHIFT) \
- | (0x0442 << SDRAM_MODE_SD_SHIFT))
- /* 0x04400442 */ /* DDR400 */
-#define CFG_SYS_DDR_MODE2 0x00000000
-
-/*
- * Memory test
- */
-#undef CFG_SYS_DRAM_TEST /* memory test, takes time */
-
-/*
- * The reserved memory
- */
-
-/*
- * Initial RAM Base Address Setup
- */
-#define CFG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
-#define CFG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
-
-/*
- * FLASH on the Local Bus
- */
-#define CFG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
-#define CFG_SYS_FLASH_SIZE 8 /* max FLASH size is 32M */
-
-/*
- * NAND Flash on the Local Bus
- */
-#define CFG_SYS_NAND_BASE 0xE0600000
-
-/* Vitesse 7385 */
-
-#define CFG_SYS_VSC7385_BASE 0xF0000000
-
-#define CFG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
-
-#define CFG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
-#define CFG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
-
-/* SERDES */
-#define CFG_FSL_SERDES1 0xe3000
-#define CFG_FSL_SERDES2 0xe3100
-
-/* I2C */
-#define CFG_SYS_I2C_NOPROBES { {0, 0x51} }
-
-/*
- * Config on-board RTC
- */
-#define CFG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
-
-/*
- * General PCI
- * Addresses are mapped 1-1.
- */
-#define CFG_SYS_PCIE1_CFG_BASE 0xA0000000
-#define CFG_SYS_PCIE1_CFG_SIZE 0x08000000
-#define CFG_SYS_PCIE1_MEM_PHYS 0xA8000000
-#define CFG_SYS_PCIE1_IO_PHYS 0xB8000000
-
-#define CFG_SYS_PCIE2_CFG_BASE 0xC0000000
-#define CFG_SYS_PCIE2_CFG_SIZE 0x08000000
-#define CFG_SYS_PCIE2_MEM_PHYS 0xC8000000
-#define CFG_SYS_PCIE2_IO_PHYS 0xD8000000
-
-#ifdef CONFIG_MMC
-#define CFG_SYS_FSL_ESDHC_ADDR CFG_SYS_MPC83xx_ESDHC_ADDR
-#endif
-
-/*
- * Miscellaneous configurable options
- */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 256 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CFG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
-
-/*
- * Environment Configuration
- */
-
-#define FDTFILE "mpc8379_rdb.dtb"
-
-#define CFG_EXTRA_ENV_SETTINGS \
- "netdev=eth1\0" \
- "uboot=" CONFIG_UBOOTPATH "\0" \
- "tftpflash=tftp $loadaddr $uboot;" \
- "protect off " __stringify(CONFIG_TEXT_BASE) \
- " +$filesize; " \
- "erase " __stringify(CONFIG_TEXT_BASE) \
- " +$filesize; " \
- "cp.b $loadaddr " __stringify(CONFIG_TEXT_BASE) \
- " $filesize; " \
- "protect on " __stringify(CONFIG_TEXT_BASE) \
- " +$filesize; " \
- "cmp.b $loadaddr " __stringify(CONFIG_TEXT_BASE) \
- " $filesize\0" \
- "fdtaddr=780000\0" \
- "fdtfile=" FDTFILE "\0" \
- "ramdiskaddr=1000000\0" \
- "ramdiskfile=rootfs.ext2.gz.uboot\0" \
- "console=ttyS0\0" \
- "setbootargs=setenv bootargs " \
- "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
- "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
- "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
- "$netdev:off " \
- "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
-
-#endif /* __CONFIG_H */
--
2.47.3
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH 03/26] board: powerpc: Remove P2020RDB-PC support
2026-10-09 19:36 [PATCH 00/26] powerpc: drop EOL boards and SoCs, take over maintenance Bradley Morgan
2026-10-09 19:36 ` [PATCH 01/26] board: powerpc: Remove MPC8548CDS support Bradley Morgan
2026-10-09 19:36 ` [PATCH 02/26] board: powerpc: Remove MPC837XERDB support Bradley Morgan
@ 2026-10-09 19:36 ` Bradley Morgan
2026-10-09 19:36 ` [PATCH 04/26] board: powerpc: Remove P3041DS support Bradley Morgan
` (22 subsequent siblings)
25 siblings, 0 replies; 31+ messages in thread
From: Bradley Morgan @ 2026-10-09 19:36 UTC (permalink / raw)
To: Tom Rini, u-boot
Cc: Bradley Morgan, Marek Behún, Marek Mojík,
NXP i . MX U-Boot Team, Alexey Charkov, Anshul Dalal,
Daniel Golle, Fabio Estevam, Gaurav Jain, Ilias Apalodimas,
Jaehoon Chung, James Hilliard, Jerome Forissier, Johan Jonker,
Lukasz Majewski, Marek Vasut, Mario Six, Michael Walle,
Michal Simek, Neil Armstrong, Peng Fan, Pengpeng Hou,
Priyanka Jain, Quentin Schulz, Simon Glass, Stefano Babic,
Tanmay Kathpalia, Torsten Rupp, Vincent Jardin, Weijie Gao
NXP marks the P2020 reference design board no longer manufactured. Remove its target, configurations, and board specific code.
Signed-off-by: Bradley Morgan <brads@mainlining.org>
---
arch/powerpc/cpu/mpc85xx/Kconfig | 10 --
arch/powerpc/dts/Makefile | 1 -
arch/powerpc/dts/p2020rdb-pc.dts | 59 -------
arch/powerpc/dts/p2020rdb-pc.dtsi | 50 ------
arch/powerpc/dts/p2020rdb-pc_36b.dts | 59 -------
board/nxp/p1_p2_rdb_pc/Kconfig | 3 +-
board/nxp/p1_p2_rdb_pc/MAINTAINERS | 8 -
board/nxp/p1_p2_rdb_pc/README | 6 +-
board/nxp/p1_p2_rdb_pc/ddr.c | 31 ----
board/nxp/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 2 -
boot/Kconfig | 2 +-
configs/P2020RDB-PC_36BIT_NAND_defconfig | 164 -------------------
configs/P2020RDB-PC_36BIT_SDCARD_defconfig | 145 ----------------
configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig | 147 -----------------
configs/P2020RDB-PC_36BIT_defconfig | 125 --------------
configs/P2020RDB-PC_NAND_defconfig | 162 ------------------
configs/P2020RDB-PC_SDCARD_defconfig | 142 ----------------
configs/P2020RDB-PC_SPIFLASH_defconfig | 145 ----------------
configs/P2020RDB-PC_defconfig | 123 --------------
doc/README.mpc85xx-sd-spi-boot | 3 -
drivers/ddr/fsl/Kconfig | 2 +-
include/configs/p1_p2_rdb_pc.h | 21 ---
22 files changed, 5 insertions(+), 1405 deletions(-)
delete mode 100644 arch/powerpc/dts/p2020rdb-pc.dts
delete mode 100644 arch/powerpc/dts/p2020rdb-pc.dtsi
delete mode 100644 arch/powerpc/dts/p2020rdb-pc_36b.dts
delete mode 100644 configs/P2020RDB-PC_36BIT_NAND_defconfig
delete mode 100644 configs/P2020RDB-PC_36BIT_SDCARD_defconfig
delete mode 100644 configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig
delete mode 100644 configs/P2020RDB-PC_36BIT_defconfig
delete mode 100644 configs/P2020RDB-PC_NAND_defconfig
delete mode 100644 configs/P2020RDB-PC_SDCARD_defconfig
delete mode 100644 configs/P2020RDB-PC_SPIFLASH_defconfig
delete mode 100644 configs/P2020RDB-PC_defconfig
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index 309becda5ac..7e885014ebe 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -157,16 +157,6 @@ config TARGET_P1020RDB_PD
imply SATA
imply PANIC_HANG
-config TARGET_P2020RDB
- bool "Support P2020RDB-PC"
- select SUPPORT_SPL
- select SUPPORT_TPL
- select ARCH_P2020
- select SYS_L2_SIZE_512KB
- imply CMD_EEPROM
- imply SATA
- imply SATA_SIL
-
config TARGET_TURRIS_1X
bool "Support Turris 1.x"
select SUPPORT_SPL
diff --git a/arch/powerpc/dts/Makefile b/arch/powerpc/dts/Makefile
index 01191273269..e44d49cabdf 100644
--- a/arch/powerpc/dts/Makefile
+++ b/arch/powerpc/dts/Makefile
@@ -11,7 +11,6 @@ dtb-$(CONFIG_TARGET_P1010RDB_PA) += p1010rdb-pa.dtb p1010rdb-pa_36b.dtb
dtb-$(CONFIG_TARGET_P1010RDB_PB) += p1010rdb-pb.dtb p1010rdb-pb_36b.dtb
dtb-$(CONFIG_TARGET_P1020RDB_PC) += p1020rdb-pc.dtb p1020rdb-pc_36b.dtb
dtb-$(CONFIG_TARGET_P1020RDB_PD) += p1020rdb-pd.dtb
-dtb-$(CONFIG_TARGET_P2020RDB) += p2020rdb-pc.dtb p2020rdb-pc_36b.dtb
dtb-$(CONFIG_TARGET_P3041DS) += p3041ds.dtb
dtb-$(CONFIG_TARGET_P4080DS) += p4080ds.dtb
dtb-$(CONFIG_TARGET_P5040DS) += p5040ds.dtb
diff --git a/arch/powerpc/dts/p2020rdb-pc.dts b/arch/powerpc/dts/p2020rdb-pc.dts
deleted file mode 100644
index 84d32360baa..00000000000
--- a/arch/powerpc/dts/p2020rdb-pc.dts
+++ /dev/null
@@ -1,59 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+ OR X11
-/*
- * P2020RDB-PC Device Tree Source
- *
- * Copyright 2013 - 2015 Freescale Semiconductor Inc.
- * Copyright 2019 NXP
- */
-
-/include/ "p2020.dtsi"
-
-/ {
- model = "fsl,P2020RDB-PC";
- compatible = "fsl,P2020RDB-PC";
- #address-cells = <2>;
- #size-cells = <2>;
- interrupt-parent = <&mpic>;
-
- lbc: localbus@ffe05000 {
- reg = <0 0xffe05000 0 0x1000>;
- };
-
- soc: soc@ffe00000 {
- ranges = <0x0 0x0 0xffe00000 0x100000>;
- };
-
- pci2: pcie@ffe08000 {
- reg = <0x0 0xffe08000 0x0 0x1000>; /* registers */
- status = "disabled";
- };
-
- pci1: pcie@ffe09000 {
- reg = <0x0 0xffe09000 0x0 0x1000>; /* registers */
- ranges = <0x01000000 0x0 0x00000000 0x0 0xffc10000 0x0 0x00010000 /* downstream I/O */
- 0x02000000 0x0 0xa0000000 0x0 0xa0000000 0x0 0x20000000>; /* non-prefetchable memory */
- };
-
- pci0: pcie@ffe0a000 {
- reg = <0x0 0xffe0a000 0x0 0x1000>; /* registers */
- ranges = <0x01000000 0x0 0x00000000 0x0 0xffc00000 0x0 0x00010000 /* downstream I/O */
- 0x02000000 0x0 0x80000000 0x0 0x80000000 0x0 0x20000000>; /* non-prefetchable memory */
- };
-
- aliases {
- spi0 = &espi0;
- };
-};
-
-/include/ "p2020rdb-pc.dtsi"
-/include/ "p2020-post.dtsi"
-
-&espi0 {
- flash@0 {
- compatible = "jedec,spi-nor";
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0>;
- spi-max-frequency = <10000000>; /* input clock */
- };
-};
diff --git a/arch/powerpc/dts/p2020rdb-pc.dtsi b/arch/powerpc/dts/p2020rdb-pc.dtsi
deleted file mode 100644
index 0d2acc746e4..00000000000
--- a/arch/powerpc/dts/p2020rdb-pc.dtsi
+++ /dev/null
@@ -1,50 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+ OR X11
-/*
- * P2020 RDB-PC Device Tree Source stub (no addresses or top-level ranges)
- *
- * Copyright 2011 Freescale Semiconductor Inc.
- * Copyright 2020 NXP
- */
-
-&soc {
- mdio@24520 {
- phy0: ethernet-phy@0 {
- interrupts = <3 1 0 0>;
- reg = <0x0>;
- };
- phy1: ethernet-phy@1 {
- interrupts = <2 1 0 0>;
- reg = <0x1>;
- };
- };
-
- mdio@25520 {
- tbi0: tbi-phy@11 {
- reg = <0x11>;
- device_type = "tbi-phy";
- };
- };
-
- mdio@26520 {
- status = "disabled";
- };
-
- enet0: ethernet@24000 {
- phy-connection-type = "rgmii-id";
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
-
- enet1: ethernet@25000 {
- tbi-handle = <&tbi0>;
- phy-handle = <&phy0>;
- phy-connection-type = "sgmii";
- };
-
- enet2: ethernet@26000 {
- phy-handle = <&phy1>;
- phy-connection-type = "rgmii-id";
- };
-};
diff --git a/arch/powerpc/dts/p2020rdb-pc_36b.dts b/arch/powerpc/dts/p2020rdb-pc_36b.dts
deleted file mode 100644
index c847417df99..00000000000
--- a/arch/powerpc/dts/p2020rdb-pc_36b.dts
+++ /dev/null
@@ -1,59 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+ OR X11
-/*
- * P2020RDB-PC (36-bit address map) Device Tree Source
- *
- * Copyright 2013 - 2015 Freescale Semiconductor Inc.
- * Copyright 2019 NXP
- */
-
-/include/ "p2020.dtsi"
-
-/ {
- model = "fsl,P2020RDB-PC";
- compatible = "fsl,P2020RDB-PC";
- #address-cells = <2>;
- #size-cells = <2>;
- interrupt-parent = <&mpic>;
-
- lbc: localbus@fffe05000 {
- reg = <0xf 0xffe05000 0 0x1000>;
- };
-
- soc: soc@fffe00000 {
- ranges = <0x0 0xf 0xffe00000 0x100000>;
- };
-
- pci2: pcie@fffe08000 {
- reg = <0xf 0xffe08000 0x0 0x1000>; /* registers */
- status = "disabled";
- };
-
- pci1: pcie@fffe09000 {
- reg = <0xf 0xffe09000 0x0 0x1000>; /* registers */
- ranges = <0x01000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x00010000 /* downstream I/O */
- 0x02000000 0x0 0xc0000000 0xc 0x20000000 0x0 0x20000000>; /* non-prefetchable memory */
- };
-
- pci0: pcie@fffe0a000 {
- reg = <0xf 0xffe0a000 0x0 0x1000>; /* registers */
- ranges = <0x01000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x00010000 /* downstream I/O */
- 0x02000000 0x0 0x80000000 0xc 0x00000000 0x0 0x20000000>; /* non-prefetchable memory */
- };
-
- aliases {
- spi0 = &espi0;
- };
-};
-
-/include/ "p2020rdb-pc.dtsi"
-/include/ "p2020-post.dtsi"
-
-&espi0 {
- flash@0 {
- compatible = "jedec,spi-nor";
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0>;
- spi-max-frequency = <10000000>; /* input clock */
- };
-};
diff --git a/board/nxp/p1_p2_rdb_pc/Kconfig b/board/nxp/p1_p2_rdb_pc/Kconfig
index 2ab46d99434..2c82048564d 100644
--- a/board/nxp/p1_p2_rdb_pc/Kconfig
+++ b/board/nxp/p1_p2_rdb_pc/Kconfig
@@ -1,6 +1,5 @@
if TARGET_P1020RDB_PC || \
- TARGET_P1020RDB_PD || \
- TARGET_P2020RDB
+ TARGET_P1020RDB_PD
config SYS_BOARD
default "p1_p2_rdb_pc"
diff --git a/board/nxp/p1_p2_rdb_pc/MAINTAINERS b/board/nxp/p1_p2_rdb_pc/MAINTAINERS
index 1ce3501f379..d9a5cdf3f42 100644
--- a/board/nxp/p1_p2_rdb_pc/MAINTAINERS
+++ b/board/nxp/p1_p2_rdb_pc/MAINTAINERS
@@ -15,11 +15,3 @@ F: configs/P1020RDB-PD_defconfig
F: configs/P1020RDB-PD_NAND_defconfig
F: configs/P1020RDB-PD_SDCARD_defconfig
F: configs/P1020RDB-PD_SPIFLASH_defconfig
-F: configs/P2020RDB-PC_defconfig
-F: configs/P2020RDB-PC_36BIT_defconfig
-F: configs/P2020RDB-PC_36BIT_NAND_defconfig
-F: configs/P2020RDB-PC_36BIT_SDCARD_defconfig
-F: configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig
-F: configs/P2020RDB-PC_NAND_defconfig
-F: configs/P2020RDB-PC_SDCARD_defconfig
-F: configs/P2020RDB-PC_SPIFLASH_defconfig
diff --git a/board/nxp/p1_p2_rdb_pc/README b/board/nxp/p1_p2_rdb_pc/README
index fd849bfc29a..5bf27816ab2 100644
--- a/board/nxp/p1_p2_rdb_pc/README
+++ b/board/nxp/p1_p2_rdb_pc/README
@@ -6,10 +6,8 @@ P1_P2_RDB_PC represents a set of boards including
P1020RDB-PD
P1021RDB-PC
P1024RDB
- P2020RDB-PC
-They have similar design of P1020RDB but have DDR3 instead of DDR2. P2020RDB-PC
-has 64-bit DDR. All others have 32-bit DDR.
+They have similar design of P1020RDB but have DDR3 instead of DDR2.
Key features on these boards include:
* DDR3
@@ -46,7 +44,7 @@ enable QE-TDM for linux kernel, set "qe;tdm" in hwconfig. Syntax is as below
Device tree support and how to enable it for different configs
--------------------------------------------------------------
-Device tree support is available for p1020rdb and p2020rdb for below mentioned boot,
+Device tree support is available for p1020rdb for below mentioned boot,
1. NOR Boot
2. NAND Boot
3. SD Boot
diff --git a/board/nxp/p1_p2_rdb_pc/ddr.c b/board/nxp/p1_p2_rdb_pc/ddr.c
index 8622a5a610a..74c9c78c4e1 100644
--- a/board/nxp/p1_p2_rdb_pc/ddr.c
+++ b/board/nxp/p1_p2_rdb_pc/ddr.c
@@ -46,37 +46,6 @@ dimm_params_t ddr_raw_timing = {
.refresh_rate_ps = 7800000,
.tfaw_ps = 37500,
};
-#elif defined(CONFIG_TARGET_P2020RDB)
-/* Micron MT41J128M16_15E */
-dimm_params_t ddr_raw_timing = {
- .n_ranks = 1,
- .rank_density = 1073741824u,
- .capacity = 1073741824u,
- .primary_sdram_width = 64,
- .ec_sdram_width = 0,
- .registered_dimm = 0,
- .mirrored_dimm = 0,
- .n_row_addr = 14,
- .n_col_addr = 10,
- .n_banks_per_sdram_device = 8,
- .edc_config = 0,
- .burst_lengths_bitmask = 0x0c,
-
- .tckmin_x_ps = 1500,
- .caslat_x = 0x7e << 4, /* 5,6,7,8,9,10 */
- .taa_ps = 13500,
- .twr_ps = 15000,
- .trcd_ps = 13500,
- .trrd_ps = 6000,
- .trp_ps = 13500,
- .tras_ps = 36000,
- .trc_ps = 49500,
- .trfc_ps = 160000,
- .twtr_ps = 7500,
- .trtp_ps = 7500,
- .refresh_rate_ps = 7800000,
- .tfaw_ps = 30000,
-};
#elif (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD))
/* Micron MT41J512M8_187E */
dimm_params_t ddr_raw_timing = {
diff --git a/board/nxp/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/nxp/p1_p2_rdb_pc/p1_p2_rdb_pc.c
index a19a98dd0d1..57c355068db 100644
--- a/board/nxp/p1_p2_rdb_pc/p1_p2_rdb_pc.c
+++ b/board/nxp/p1_p2_rdb_pc/p1_p2_rdb_pc.c
@@ -220,8 +220,6 @@ int board_early_init_f(void)
#define BOARD_NAME "P1020RDB-PC"
#elif defined(CONFIG_TARGET_P1020RDB_PD)
#define BOARD_NAME "P1020RDB-PD"
-#elif defined(CONFIG_TARGET_P2020RDB)
-#define BOARD_NAME "P2020RDB-PC"
#endif
int checkboard_p1_p2(void)
diff --git a/boot/Kconfig b/boot/Kconfig
index 8fcdc36c931..11b5036caad 100644
--- a/boot/Kconfig
+++ b/boot/Kconfig
@@ -1179,7 +1179,7 @@ config RAMBOOT_PBL
choice
prompt "Freescale PBL (or predecessor) load location"
depends on RAMBOOT_PBL || ((TARGET_P1010RDB_PA || TARGET_P1010RDB_PB \
- || TARGET_P1020RDB_PC || TARGET_P1020RDB_PD || TARGET_P2020RDB) \
+ || TARGET_P1020RDB_PC || TARGET_P1020RDB_PD) \
&& !CMD_NAND) || (TARGET_TURRIS_1X && SYS_MPC85XX_NO_RESETVEC)
config SDCARD
diff --git a/configs/P2020RDB-PC_36BIT_NAND_defconfig b/configs/P2020RDB-PC_36BIT_NAND_defconfig
deleted file mode 100644
index 6a8b750555b..00000000000
--- a/configs/P2020RDB-PC_36BIT_NAND_defconfig
+++ /dev/null
@@ -1,164 +0,0 @@
-CONFIG_PPC=y
-CONFIG_TEXT_BASE=0x11000000
-CONFIG_SYS_MALLOC_LEN=0x100000
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_ENV_SIZE=0x4000
-CONFIG_ENV_OFFSET=0x100000
-CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc_36b"
-CONFIG_SYS_MONITOR_LEN=786432
-CONFIG_SPL_SERIAL=y
-CONFIG_TPL_TEXT_BASE=0xF8F80000
-CONFIG_TPL_LIBCOMMON_SUPPORT=y
-CONFIG_TPL_LIBGENERIC_SUPPORT=y
-CONFIG_TPL_SERIAL=y
-CONFIG_SPL_TEXT_BASE=0xFF800000
-CONFIG_SPL=y
-CONFIG_TPL_MAX_SIZE=0x20000
-CONFIG_MPC85xx=y
-CONFIG_SYS_INIT_RAM_LOCK=y
-# CONFIG_CMD_ERRATA is not set
-CONFIG_TARGET_P2020RDB=y
-CONFIG_L2_CACHE=y
-CONFIG_ENABLE_36BIT_PHYS=y
-CONFIG_SYS_MPC85XX_NO_RESETVEC=y
-CONFIG_TPL_SYS_MPC85XX_NO_RESETVEC=y
-CONFIG_USE_UBOOTPATH=y
-CONFIG_PCIE1=y
-CONFIG_PCIE2=y
-CONFIG_PHYS_64BIT=y
-CONFIG_MP=y
-CONFIG_TPL_SYS_MONITOR_BASE=0xF8F80000
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_BOOTDELAY=10
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_USE_BOOTCOMMAND=y
-CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw rootdelay=30 console=$consoledev,$baudrate $othbootargs;usb start;ext2load usb 0:1 $loadaddr /boot/$bootfile;ext2load usb 0:1 $fdtaddr /boot/$fdtfile;bootm $loadaddr - $fdtaddr"
-CONFIG_SYS_PBSIZE=276
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_MISC_INIT_R is not set
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_MAX_SIZE=0x1000
-CONFIG_SPL_NAND_BOOT=y
-CONFIG_SPL_SYS_CCSR_DO_NOT_RELOCATE=y
-CONFIG_SPL_INIT_MINIMAL=y
-CONFIG_SPL_FLUSH_IMAGE=y
-CONFIG_SPL_RELOC_TEXT_BASE=0xf8ffe000
-CONFIG_SPL_RELOC_STACK=0xf8fffff0
-CONFIG_TPL_GD_ADDR=0xf8fac000
-CONFIG_TPL_RELOC_TEXT_BASE=0xf8f80000
-CONFIG_TPL_RELOC_STACK=0xf8fb0000
-CONFIG_TPL_RELOC_MALLOC=y
-CONFIG_TPL_RELOC_MALLOC_ADDR=0xf8fb4000
-CONFIG_TPL_RELOC_MALLOC_SIZE=0xc000
-CONFIG_SPL_NAND_SUPPORT=y
-CONFIG_TPL=y
-CONFIG_TPL_ENV_SUPPORT=y
-CONFIG_TPL_I2C=y
-CONFIG_TPL_MPC8XXX_INIT_DDR=y
-CONFIG_TPL_NAND_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_CMD_IMLS=y
-CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
-CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
-CONFIG_CMD_I2C=y
-CONFIG_LOADS_ECHO=y
-CONFIG_SYS_LOADS_BAUD_CHANGE=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nor0=fef000000.nor"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=fef000000.nor:256k(vsc7385-firmware),256k(dtb),4608k(kernel),9984k(fs),1280k(u-boot)"
-CONFIG_OF_CONTROL=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_NAND=y
-CONFIG_ENV_RANGE=0xc000
-CONFIG_ENV_RELOC_GD_ENV_ADDR=y
-CONFIG_USE_BOOTFILE=y
-CONFIG_BOOTFILE="uImage"
-CONFIG_USE_ETHPRIME=y
-CONFIG_ETHPRIME="eTSEC1"
-CONFIG_USE_HOSTNAME=y
-CONFIG_USE_ROOTPATH=y
-CONFIG_LBA48=y
-CONFIG_DDR_CLK_FREQ=66666666
-CONFIG_SYS_SPD_BUS_NUM=1
-CONFIG_CHIP_SELECTS_PER_CTRL=1
-CONFIG_SYS_DDR_RAW_TIMING=y
-CONFIG_SYS_BR0_PRELIM_BOOL=y
-CONFIG_SYS_BR0_PRELIM=0xFF800C21
-CONFIG_SYS_OR0_PRELIM=0xFFFF8396
-CONFIG_SYS_BR1_PRELIM_BOOL=y
-CONFIG_SYS_BR1_PRELIM=0xEF001001
-CONFIG_SYS_OR1_PRELIM=0xFC000FF7
-CONFIG_SYS_BR2_PRELIM_BOOL=y
-CONFIG_SYS_BR2_PRELIM=0xFFB00801
-CONFIG_SYS_OR2_PRELIM=0xFFFE09FF
-CONFIG_SYS_BR3_PRELIM_BOOL=y
-CONFIG_SYS_BR3_PRELIM=0xFFA00801
-CONFIG_SYS_OR3_PRELIM=0xFFF009F7
-CONFIG_TPL_COMMON_INIT_DDR=y
-CONFIG_DM_I2C=y
-CONFIG_SPL_SYS_I2C_LEGACY=y
-CONFIG_TPL_SYS_I2C_LEGACY=y
-CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
-CONFIG_SYS_I2C_FSL=y
-CONFIG_SYS_FSL_I2C_OFFSET=0x3000
-CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y
-CONFIG_SYS_FSL_I2C2_OFFSET=0x3100
-CONFIG_SYS_I2C_EEPROM_ADDR=0x52
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_EMPTY_INFO=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SYS_FLASH_QUIET_TEST=y
-CONFIG_SYS_MAX_FLASH_SECT=128
-CONFIG_MTD_RAW_NAND=y
-CONFIG_NAND_FSL_ELBC=y
-CONFIG_SYS_NAND_BLOCK_SIZE=0x4000
-CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
-CONFIG_SYS_NAND_U_BOOT_OFFS=0x20000
-CONFIG_DM_SPI_FLASH=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_DM_MDIO=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_VSC7385_ENET=y
-CONFIG_TSEC_ENET=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_FIXED=y
-CONFIG_PCIE_FSL=y
-CONFIG_DM_RTC=y
-CONFIG_RTC_PT7C4338=y
-CONFIG_DM_SERIAL=y
-CONFIG_SPL_SYS_NS16550_SERIAL=y
-CONFIG_SPL_NS16550_MIN_FUNCTIONS=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_EHCI_FSL=y
-CONFIG_USB_STORAGE=y
-CONFIG_ADDR_MAP=y
diff --git a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig
deleted file mode 100644
index e516e8c0d6e..00000000000
--- a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig
+++ /dev/null
@@ -1,145 +0,0 @@
-CONFIG_PPC=y
-CONFIG_TEXT_BASE=0x11000000
-CONFIG_SYS_MALLOC_LEN=0x100000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x0
-CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc_36b"
-CONFIG_SYS_MONITOR_LEN=786432
-CONFIG_SPL_MMC=y
-CONFIG_SPL_SERIAL=y
-CONFIG_SPL_TEXT_BASE=0xf8f80000
-CONFIG_SPL=y
-CONFIG_MPC85xx=y
-CONFIG_SYS_INIT_RAM_LOCK=y
-# CONFIG_CMD_ERRATA is not set
-CONFIG_TARGET_P2020RDB=y
-CONFIG_L2_CACHE=y
-CONFIG_ENABLE_36BIT_PHYS=y
-CONFIG_SYS_MPC85XX_NO_RESETVEC=y
-CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
-CONFIG_USE_UBOOTPATH=y
-CONFIG_PCIE1=y
-CONFIG_PCIE2=y
-CONFIG_PHYS_64BIT=y
-CONFIG_MP=y
-CONFIG_SPL_SYS_MONITOR_BASE=0xF8F80000
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_FSL_FIXED_MMC_LOCATION=y
-CONFIG_BOOTDELAY=10
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_USE_BOOTCOMMAND=y
-CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw rootdelay=30 console=$consoledev,$baudrate $othbootargs;usb start;ext2load usb 0:1 $loadaddr /boot/$bootfile;ext2load usb 0:1 $fdtaddr /boot/$fdtfile;bootm $loadaddr - $fdtaddr"
-CONFIG_SYS_PBSIZE=276
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_MISC_INIT_R is not set
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_MAX_SIZE=0x20000
-CONFIG_SPL_MMC_BOOT=y
-CONFIG_SPL_SYS_CCSR_DO_NOT_RELOCATE=y
-CONFIG_SPL_FLUSH_IMAGE=y
-CONFIG_SPL_GD_ADDR=0xf8f9c000
-CONFIG_SPL_RELOC_STACK=0xf8f9d000
-CONFIG_SPL_RELOC_MALLOC=y
-CONFIG_SPL_RELOC_MALLOC_ADDR=0xf8fa5000
-CONFIG_SPL_RELOC_MALLOC_SIZE=0x5b000
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C=y
-CONFIG_SPL_MPC8XXX_INIT_DDR=y
-CONFIG_HUSH_PARSER=y
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_CMD_IMLS=y
-CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
-CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
-CONFIG_CMD_I2C=y
-CONFIG_LOADS_ECHO=y
-CONFIG_SYS_LOADS_BAUD_CHANGE=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nor0=fef000000.nor"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=fef000000.nor:256k(vsc7385-firmware),256k(dtb),4608k(kernel),9984k(fs),1280k(u-boot)"
-CONFIG_OF_CONTROL=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_ENV_RELOC_GD_ENV_ADDR=y
-CONFIG_USE_BOOTFILE=y
-CONFIG_BOOTFILE="uImage"
-CONFIG_USE_ETHPRIME=y
-CONFIG_ETHPRIME="eTSEC1"
-CONFIG_USE_HOSTNAME=y
-CONFIG_USE_ROOTPATH=y
-CONFIG_LBA48=y
-CONFIG_DDR_CLK_FREQ=66666666
-CONFIG_SYS_SPD_BUS_NUM=1
-CONFIG_CHIP_SELECTS_PER_CTRL=1
-CONFIG_SYS_DDR_RAW_TIMING=y
-CONFIG_SYS_BR0_PRELIM_BOOL=y
-CONFIG_SYS_BR0_PRELIM=0xEF001001
-CONFIG_SYS_OR0_PRELIM=0xFC000FF7
-CONFIG_SYS_BR2_PRELIM_BOOL=y
-CONFIG_SYS_BR2_PRELIM=0xFFB00801
-CONFIG_SYS_OR2_PRELIM=0xFFFE09FF
-CONFIG_SYS_BR3_PRELIM_BOOL=y
-CONFIG_SYS_BR3_PRELIM=0xFFA00801
-CONFIG_SYS_OR3_PRELIM=0xFFF009F7
-CONFIG_SPL_COMMON_INIT_DDR=y
-CONFIG_DM_I2C=y
-CONFIG_SPL_SYS_I2C_LEGACY=y
-CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
-CONFIG_SYS_I2C_FSL=y
-CONFIG_SYS_FSL_I2C_OFFSET=0x3000
-CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y
-CONFIG_SYS_FSL_I2C2_OFFSET=0x3100
-CONFIG_SYS_I2C_EEPROM_ADDR=0x52
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_EMPTY_INFO=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SYS_FLASH_QUIET_TEST=y
-CONFIG_SYS_MAX_FLASH_SECT=128
-CONFIG_DM_SPI_FLASH=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_DM_MDIO=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_VSC7385_ENET=y
-CONFIG_TSEC_ENET=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_FIXED=y
-CONFIG_PCIE_FSL=y
-CONFIG_DM_RTC=y
-CONFIG_RTC_PT7C4338=y
-CONFIG_DM_SERIAL=y
-CONFIG_SPL_SYS_NS16550_SERIAL=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_EHCI_FSL=y
-CONFIG_USB_STORAGE=y
-CONFIG_ADDR_MAP=y
diff --git a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig
deleted file mode 100644
index bc25dbe17df..00000000000
--- a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig
+++ /dev/null
@@ -1,147 +0,0 @@
-CONFIG_PPC=y
-CONFIG_TEXT_BASE=0x11000000
-CONFIG_SYS_MALLOC_LEN=0x100000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x100000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc_36b"
-CONFIG_SYS_MONITOR_LEN=786432
-CONFIG_SPL_SERIAL=y
-CONFIG_SPL_TEXT_BASE=0xf8f80000
-CONFIG_SPL=y
-CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI=y
-CONFIG_MPC85xx=y
-CONFIG_SYS_INIT_RAM_LOCK=y
-# CONFIG_CMD_ERRATA is not set
-CONFIG_TARGET_P2020RDB=y
-CONFIG_L2_CACHE=y
-CONFIG_ENABLE_36BIT_PHYS=y
-CONFIG_SYS_MPC85XX_NO_RESETVEC=y
-CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
-CONFIG_USE_UBOOTPATH=y
-CONFIG_PCIE1=y
-CONFIG_PCIE2=y
-CONFIG_PHYS_64BIT=y
-CONFIG_MP=y
-CONFIG_SPL_SYS_MONITOR_BASE=0xF8F80000
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_SPIFLASH=y
-CONFIG_BOOTDELAY=10
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_USE_BOOTCOMMAND=y
-CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw rootdelay=30 console=$consoledev,$baudrate $othbootargs;usb start;ext2load usb 0:1 $loadaddr /boot/$bootfile;ext2load usb 0:1 $fdtaddr /boot/$fdtfile;bootm $loadaddr - $fdtaddr"
-CONFIG_SYS_PBSIZE=276
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_MISC_INIT_R is not set
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_MAX_SIZE=0x20000
-CONFIG_SPL_SPI_BOOT=y
-CONFIG_SPL_SYS_CCSR_DO_NOT_RELOCATE=y
-CONFIG_SPL_FLUSH_IMAGE=y
-CONFIG_SPL_GD_ADDR=0xf8f9c000
-CONFIG_SPL_RELOC_STACK=0xf8f9d000
-CONFIG_SPL_RELOC_MALLOC=y
-CONFIG_SPL_RELOC_MALLOC_ADDR=0xf8fa5000
-CONFIG_SPL_RELOC_MALLOC_SIZE=0x5b000
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C=y
-CONFIG_SPL_MPC8XXX_INIT_DDR=y
-CONFIG_HUSH_PARSER=y
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_CMD_IMLS=y
-CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
-CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
-CONFIG_CMD_I2C=y
-CONFIG_LOADS_ECHO=y
-CONFIG_SYS_LOADS_BAUD_CHANGE=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nor0=fef000000.nor"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=fef000000.nor:256k(vsc7385-firmware),256k(dtb),4608k(kernel),9984k(fs),1280k(u-boot)"
-CONFIG_OF_CONTROL=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_ENV_RELOC_GD_ENV_ADDR=y
-CONFIG_USE_BOOTFILE=y
-CONFIG_BOOTFILE="uImage"
-CONFIG_USE_ETHPRIME=y
-CONFIG_ETHPRIME="eTSEC1"
-CONFIG_USE_HOSTNAME=y
-CONFIG_USE_ROOTPATH=y
-CONFIG_LBA48=y
-CONFIG_DDR_CLK_FREQ=66666666
-CONFIG_SYS_SPD_BUS_NUM=1
-CONFIG_CHIP_SELECTS_PER_CTRL=1
-CONFIG_SYS_DDR_RAW_TIMING=y
-CONFIG_SYS_BR0_PRELIM_BOOL=y
-CONFIG_SYS_BR0_PRELIM=0xEF001001
-CONFIG_SYS_OR0_PRELIM=0xFC000FF7
-CONFIG_SYS_BR2_PRELIM_BOOL=y
-CONFIG_SYS_BR2_PRELIM=0xFFB00801
-CONFIG_SYS_OR2_PRELIM=0xFFFE09FF
-CONFIG_SYS_BR3_PRELIM_BOOL=y
-CONFIG_SYS_BR3_PRELIM=0xFFA00801
-CONFIG_SYS_OR3_PRELIM=0xFFF009F7
-CONFIG_SPL_COMMON_INIT_DDR=y
-CONFIG_DM_I2C=y
-CONFIG_SPL_SYS_I2C_LEGACY=y
-CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
-CONFIG_SYS_I2C_FSL=y
-CONFIG_SYS_FSL_I2C_OFFSET=0x3000
-CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y
-CONFIG_SYS_FSL_I2C2_OFFSET=0x3100
-CONFIG_SYS_I2C_EEPROM_ADDR=0x52
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_EMPTY_INFO=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SYS_FLASH_QUIET_TEST=y
-CONFIG_SYS_MAX_FLASH_SECT=128
-CONFIG_DM_SPI_FLASH=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_DM_MDIO=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_VSC7385_ENET=y
-CONFIG_TSEC_ENET=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_FIXED=y
-CONFIG_PCIE_FSL=y
-CONFIG_DM_RTC=y
-CONFIG_RTC_PT7C4338=y
-CONFIG_DM_SERIAL=y
-CONFIG_SPL_SYS_NS16550_SERIAL=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_EHCI_FSL=y
-CONFIG_USB_STORAGE=y
-CONFIG_ADDR_MAP=y
diff --git a/configs/P2020RDB-PC_36BIT_defconfig b/configs/P2020RDB-PC_36BIT_defconfig
deleted file mode 100644
index 429b83465ad..00000000000
--- a/configs/P2020RDB-PC_36BIT_defconfig
+++ /dev/null
@@ -1,125 +0,0 @@
-CONFIG_PPC=y
-CONFIG_TEXT_BASE=0xEFF40000
-CONFIG_SYS_MALLOC_LEN=0x100000
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc_36b"
-CONFIG_SYS_MONITOR_LEN=786432
-CONFIG_ENV_ADDR=0xEFF20000
-CONFIG_MPC85xx=y
-CONFIG_SYS_INIT_RAM_LOCK=y
-# CONFIG_CMD_ERRATA is not set
-CONFIG_TARGET_P2020RDB=y
-CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
-CONFIG_L2_CACHE=y
-CONFIG_ENABLE_36BIT_PHYS=y
-CONFIG_USE_UBOOTPATH=y
-CONFIG_PCIE1=y
-CONFIG_PCIE2=y
-CONFIG_PHYS_64BIT=y
-CONFIG_MP=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_NO_PBL=y
-CONFIG_BOOTDELAY=10
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_USE_BOOTCOMMAND=y
-CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw rootdelay=30 console=$consoledev,$baudrate $othbootargs;usb start;ext2load usb 0:1 $loadaddr /boot/$bootfile;ext2load usb 0:1 $fdtaddr /boot/$fdtfile;bootm $loadaddr - $fdtaddr"
-CONFIG_SYS_PBSIZE=276
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_MISC_INIT_R is not set
-CONFIG_HUSH_PARSER=y
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_CMD_IMLS=y
-CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
-CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
-CONFIG_CMD_I2C=y
-CONFIG_LOADS_ECHO=y
-CONFIG_SYS_LOADS_BAUD_CHANGE=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nor0=fef000000.nor"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=fef000000.nor:256k(vsc7385-firmware),256k(dtb),4608k(kernel),9984k(fs),1280k(u-boot)"
-CONFIG_OF_CONTROL=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_USE_BOOTFILE=y
-CONFIG_BOOTFILE="uImage"
-CONFIG_USE_ETHPRIME=y
-CONFIG_ETHPRIME="eTSEC1"
-CONFIG_USE_HOSTNAME=y
-CONFIG_USE_ROOTPATH=y
-CONFIG_LBA48=y
-CONFIG_DDR_CLK_FREQ=66666666
-CONFIG_SYS_SPD_BUS_NUM=1
-CONFIG_CHIP_SELECTS_PER_CTRL=1
-CONFIG_SYS_DDR_RAW_TIMING=y
-CONFIG_SYS_BR0_PRELIM_BOOL=y
-CONFIG_SYS_BR0_PRELIM=0xEF001001
-CONFIG_SYS_OR0_PRELIM=0xFC000FF7
-CONFIG_SYS_BR2_PRELIM_BOOL=y
-CONFIG_SYS_BR2_PRELIM=0xFFB00801
-CONFIG_SYS_OR2_PRELIM=0xFFFE09FF
-CONFIG_SYS_BR3_PRELIM_BOOL=y
-CONFIG_SYS_BR3_PRELIM=0xFFA00801
-CONFIG_SYS_OR3_PRELIM=0xFFF009F7
-CONFIG_COMMON_INIT_DDR=y
-CONFIG_SPL_COMMON_INIT_DDR=y
-CONFIG_DM_I2C=y
-CONFIG_SPL_SYS_I2C_LEGACY=y
-CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
-CONFIG_SYS_I2C_FSL=y
-CONFIG_SYS_FSL_I2C_OFFSET=0x3000
-CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y
-CONFIG_SYS_FSL_I2C2_OFFSET=0x3100
-CONFIG_SYS_I2C_EEPROM_ADDR=0x52
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_EMPTY_INFO=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SYS_FLASH_QUIET_TEST=y
-CONFIG_SYS_MAX_FLASH_SECT=128
-CONFIG_DM_SPI_FLASH=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_DM_MDIO=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_VSC7385_ENET=y
-CONFIG_TSEC_ENET=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_FIXED=y
-CONFIG_PCIE_FSL=y
-CONFIG_DM_RTC=y
-CONFIG_RTC_PT7C4338=y
-CONFIG_DM_SERIAL=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_EHCI_FSL=y
-CONFIG_USB_STORAGE=y
-CONFIG_ADDR_MAP=y
diff --git a/configs/P2020RDB-PC_NAND_defconfig b/configs/P2020RDB-PC_NAND_defconfig
deleted file mode 100644
index e60677d55dc..00000000000
--- a/configs/P2020RDB-PC_NAND_defconfig
+++ /dev/null
@@ -1,162 +0,0 @@
-CONFIG_PPC=y
-CONFIG_TEXT_BASE=0x11000000
-CONFIG_SYS_MALLOC_LEN=0x100000
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_ENV_SIZE=0x4000
-CONFIG_ENV_OFFSET=0x100000
-CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc"
-CONFIG_SYS_MONITOR_LEN=786432
-CONFIG_SPL_SERIAL=y
-CONFIG_TPL_TEXT_BASE=0xF8F80000
-CONFIG_TPL_LIBCOMMON_SUPPORT=y
-CONFIG_TPL_LIBGENERIC_SUPPORT=y
-CONFIG_TPL_SERIAL=y
-CONFIG_SPL_TEXT_BASE=0xFF800000
-CONFIG_SPL=y
-CONFIG_TPL_MAX_SIZE=0x20000
-CONFIG_MPC85xx=y
-CONFIG_SYS_INIT_RAM_LOCK=y
-# CONFIG_CMD_ERRATA is not set
-CONFIG_TARGET_P2020RDB=y
-CONFIG_L2_CACHE=y
-CONFIG_ENABLE_36BIT_PHYS=y
-CONFIG_SYS_MPC85XX_NO_RESETVEC=y
-CONFIG_TPL_SYS_MPC85XX_NO_RESETVEC=y
-CONFIG_USE_UBOOTPATH=y
-CONFIG_PCIE1=y
-CONFIG_PCIE2=y
-CONFIG_MP=y
-CONFIG_TPL_SYS_MONITOR_BASE=0xF8F80000
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_BOOTDELAY=10
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_USE_BOOTCOMMAND=y
-CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw rootdelay=30 console=$consoledev,$baudrate $othbootargs;usb start;ext2load usb 0:1 $loadaddr /boot/$bootfile;ext2load usb 0:1 $fdtaddr /boot/$fdtfile;bootm $loadaddr - $fdtaddr"
-CONFIG_SYS_PBSIZE=276
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_MISC_INIT_R is not set
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_MAX_SIZE=0x1000
-CONFIG_SPL_NAND_BOOT=y
-CONFIG_SPL_SYS_CCSR_DO_NOT_RELOCATE=y
-CONFIG_SPL_INIT_MINIMAL=y
-CONFIG_SPL_FLUSH_IMAGE=y
-CONFIG_SPL_RELOC_TEXT_BASE=0xf8ffe000
-CONFIG_SPL_RELOC_STACK=0xf8fffff0
-CONFIG_TPL_GD_ADDR=0xf8fac000
-CONFIG_TPL_RELOC_TEXT_BASE=0xf8f80000
-CONFIG_TPL_RELOC_STACK=0xf8fb0000
-CONFIG_TPL_RELOC_MALLOC=y
-CONFIG_TPL_RELOC_MALLOC_ADDR=0xf8fb4000
-CONFIG_TPL_RELOC_MALLOC_SIZE=0xc000
-CONFIG_SPL_NAND_SUPPORT=y
-CONFIG_TPL=y
-CONFIG_TPL_ENV_SUPPORT=y
-CONFIG_TPL_I2C=y
-CONFIG_TPL_MPC8XXX_INIT_DDR=y
-CONFIG_TPL_NAND_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_CMD_IMLS=y
-CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
-CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
-CONFIG_CMD_I2C=y
-CONFIG_LOADS_ECHO=y
-CONFIG_SYS_LOADS_BAUD_CHANGE=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nor0=ef000000.nor"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=ef000000.nor:256k(vsc7385-firmware),256k(dtb),4608k(kernel),9984k(fs),1280k(u-boot)"
-CONFIG_OF_CONTROL=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_NAND=y
-CONFIG_ENV_RANGE=0xc000
-CONFIG_ENV_RELOC_GD_ENV_ADDR=y
-CONFIG_USE_BOOTFILE=y
-CONFIG_BOOTFILE="uImage"
-CONFIG_USE_ETHPRIME=y
-CONFIG_ETHPRIME="eTSEC1"
-CONFIG_USE_HOSTNAME=y
-CONFIG_USE_ROOTPATH=y
-CONFIG_LBA48=y
-CONFIG_DDR_CLK_FREQ=66666666
-CONFIG_SYS_SPD_BUS_NUM=1
-CONFIG_CHIP_SELECTS_PER_CTRL=1
-CONFIG_SYS_DDR_RAW_TIMING=y
-CONFIG_SYS_BR0_PRELIM_BOOL=y
-CONFIG_SYS_BR0_PRELIM=0xFF800C21
-CONFIG_SYS_OR0_PRELIM=0xFFFF8396
-CONFIG_SYS_BR1_PRELIM_BOOL=y
-CONFIG_SYS_BR1_PRELIM=0xEF001001
-CONFIG_SYS_OR1_PRELIM=0xFC000FF7
-CONFIG_SYS_BR2_PRELIM_BOOL=y
-CONFIG_SYS_BR2_PRELIM=0xFFB00801
-CONFIG_SYS_OR2_PRELIM=0xFFFE09FF
-CONFIG_SYS_BR3_PRELIM_BOOL=y
-CONFIG_SYS_BR3_PRELIM=0xFFA00801
-CONFIG_SYS_OR3_PRELIM=0xFFF009F7
-CONFIG_TPL_COMMON_INIT_DDR=y
-CONFIG_DM_I2C=y
-CONFIG_SPL_SYS_I2C_LEGACY=y
-CONFIG_TPL_SYS_I2C_LEGACY=y
-CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
-CONFIG_SYS_I2C_FSL=y
-CONFIG_SYS_FSL_I2C_OFFSET=0x3000
-CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y
-CONFIG_SYS_FSL_I2C2_OFFSET=0x3100
-CONFIG_SYS_I2C_EEPROM_ADDR=0x52
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_EMPTY_INFO=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SYS_FLASH_QUIET_TEST=y
-CONFIG_SYS_MAX_FLASH_SECT=128
-CONFIG_MTD_RAW_NAND=y
-CONFIG_NAND_FSL_ELBC=y
-CONFIG_SYS_NAND_BLOCK_SIZE=0x4000
-CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
-CONFIG_SYS_NAND_U_BOOT_OFFS=0x20000
-CONFIG_DM_SPI_FLASH=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_DM_MDIO=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_VSC7385_ENET=y
-CONFIG_TSEC_ENET=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_FIXED=y
-CONFIG_PCIE_FSL=y
-CONFIG_DM_RTC=y
-CONFIG_RTC_PT7C4338=y
-CONFIG_DM_SERIAL=y
-CONFIG_SPL_SYS_NS16550_SERIAL=y
-CONFIG_SPL_NS16550_MIN_FUNCTIONS=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_EHCI_FSL=y
-CONFIG_USB_STORAGE=y
diff --git a/configs/P2020RDB-PC_SDCARD_defconfig b/configs/P2020RDB-PC_SDCARD_defconfig
deleted file mode 100644
index fe433c5e358..00000000000
--- a/configs/P2020RDB-PC_SDCARD_defconfig
+++ /dev/null
@@ -1,142 +0,0 @@
-CONFIG_PPC=y
-CONFIG_TEXT_BASE=0x11000000
-CONFIG_SYS_MALLOC_LEN=0x100000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x0
-CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc"
-CONFIG_SYS_MONITOR_LEN=786432
-CONFIG_SPL_MMC=y
-CONFIG_SPL_SERIAL=y
-CONFIG_SPL_TEXT_BASE=0xf8f80000
-CONFIG_SPL=y
-CONFIG_MPC85xx=y
-CONFIG_SYS_INIT_RAM_LOCK=y
-# CONFIG_CMD_ERRATA is not set
-CONFIG_TARGET_P2020RDB=y
-CONFIG_L2_CACHE=y
-CONFIG_ENABLE_36BIT_PHYS=y
-CONFIG_SYS_MPC85XX_NO_RESETVEC=y
-CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
-CONFIG_USE_UBOOTPATH=y
-CONFIG_PCIE1=y
-CONFIG_PCIE2=y
-CONFIG_MP=y
-CONFIG_SPL_SYS_MONITOR_BASE=0xF8F80000
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_FSL_FIXED_MMC_LOCATION=y
-CONFIG_BOOTDELAY=10
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_USE_BOOTCOMMAND=y
-CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw rootdelay=30 console=$consoledev,$baudrate $othbootargs;usb start;ext2load usb 0:1 $loadaddr /boot/$bootfile;ext2load usb 0:1 $fdtaddr /boot/$fdtfile;bootm $loadaddr - $fdtaddr"
-CONFIG_SYS_PBSIZE=276
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_MISC_INIT_R is not set
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_MAX_SIZE=0x20000
-CONFIG_SPL_MMC_BOOT=y
-CONFIG_SPL_SYS_CCSR_DO_NOT_RELOCATE=y
-CONFIG_SPL_FLUSH_IMAGE=y
-CONFIG_SPL_GD_ADDR=0xf8f9c000
-CONFIG_SPL_RELOC_STACK=0xf8f9d000
-CONFIG_SPL_RELOC_MALLOC=y
-CONFIG_SPL_RELOC_MALLOC_ADDR=0xf8fa5000
-CONFIG_SPL_RELOC_MALLOC_SIZE=0x5b000
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C=y
-CONFIG_SPL_MPC8XXX_INIT_DDR=y
-CONFIG_HUSH_PARSER=y
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_CMD_IMLS=y
-CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
-CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
-CONFIG_CMD_I2C=y
-CONFIG_LOADS_ECHO=y
-CONFIG_SYS_LOADS_BAUD_CHANGE=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nor0=ef000000.nor"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=ef000000.nor:256k(vsc7385-firmware),256k(dtb),4608k(kernel),9984k(fs),1280k(u-boot)"
-CONFIG_OF_CONTROL=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_ENV_RELOC_GD_ENV_ADDR=y
-CONFIG_USE_BOOTFILE=y
-CONFIG_BOOTFILE="uImage"
-CONFIG_USE_ETHPRIME=y
-CONFIG_ETHPRIME="eTSEC1"
-CONFIG_USE_HOSTNAME=y
-CONFIG_USE_ROOTPATH=y
-CONFIG_LBA48=y
-CONFIG_DDR_CLK_FREQ=66666666
-CONFIG_SYS_SPD_BUS_NUM=1
-CONFIG_CHIP_SELECTS_PER_CTRL=1
-CONFIG_SYS_DDR_RAW_TIMING=y
-CONFIG_SYS_BR0_PRELIM_BOOL=y
-CONFIG_SYS_BR0_PRELIM=0xEF001001
-CONFIG_SYS_OR0_PRELIM=0xFC000FF7
-CONFIG_SYS_BR2_PRELIM_BOOL=y
-CONFIG_SYS_BR2_PRELIM=0xFFB00801
-CONFIG_SYS_OR2_PRELIM=0xFFFE09FF
-CONFIG_SYS_BR3_PRELIM_BOOL=y
-CONFIG_SYS_BR3_PRELIM=0xFFA00801
-CONFIG_SYS_OR3_PRELIM=0xFFF009F7
-CONFIG_SPL_COMMON_INIT_DDR=y
-CONFIG_DM_I2C=y
-CONFIG_SPL_SYS_I2C_LEGACY=y
-CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
-CONFIG_SYS_I2C_FSL=y
-CONFIG_SYS_FSL_I2C_OFFSET=0x3000
-CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y
-CONFIG_SYS_FSL_I2C2_OFFSET=0x3100
-CONFIG_SYS_I2C_EEPROM_ADDR=0x52
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_EMPTY_INFO=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SYS_FLASH_QUIET_TEST=y
-CONFIG_SYS_MAX_FLASH_SECT=128
-CONFIG_DM_SPI_FLASH=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_DM_MDIO=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_VSC7385_ENET=y
-CONFIG_TSEC_ENET=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_FIXED=y
-CONFIG_PCIE_FSL=y
-CONFIG_DM_RTC=y
-CONFIG_RTC_PT7C4338=y
-CONFIG_DM_SERIAL=y
-CONFIG_SPL_SYS_NS16550_SERIAL=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_EHCI_FSL=y
diff --git a/configs/P2020RDB-PC_SPIFLASH_defconfig b/configs/P2020RDB-PC_SPIFLASH_defconfig
deleted file mode 100644
index 0184dcb4e8b..00000000000
--- a/configs/P2020RDB-PC_SPIFLASH_defconfig
+++ /dev/null
@@ -1,145 +0,0 @@
-CONFIG_PPC=y
-CONFIG_TEXT_BASE=0x11000000
-CONFIG_SYS_MALLOC_LEN=0x100000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x100000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc"
-CONFIG_SYS_MONITOR_LEN=786432
-CONFIG_SPL_SERIAL=y
-CONFIG_SPL_TEXT_BASE=0xf8f80000
-CONFIG_SPL=y
-CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI=y
-CONFIG_MPC85xx=y
-CONFIG_SYS_INIT_RAM_LOCK=y
-# CONFIG_CMD_ERRATA is not set
-CONFIG_TARGET_P2020RDB=y
-CONFIG_L2_CACHE=y
-CONFIG_ENABLE_36BIT_PHYS=y
-CONFIG_SYS_MPC85XX_NO_RESETVEC=y
-CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
-CONFIG_USE_UBOOTPATH=y
-CONFIG_PCIE1=y
-CONFIG_PCIE2=y
-CONFIG_MP=y
-CONFIG_SPL_SYS_MONITOR_BASE=0xF8F80000
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_SPIFLASH=y
-CONFIG_BOOTDELAY=10
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_USE_BOOTCOMMAND=y
-CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw rootdelay=30 console=$consoledev,$baudrate $othbootargs;usb start;ext2load usb 0:1 $loadaddr /boot/$bootfile;ext2load usb 0:1 $fdtaddr /boot/$fdtfile;bootm $loadaddr - $fdtaddr"
-CONFIG_SYS_PBSIZE=276
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_MISC_INIT_R is not set
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_MAX_SIZE=0x20000
-CONFIG_SPL_SPI_BOOT=y
-CONFIG_SPL_SYS_CCSR_DO_NOT_RELOCATE=y
-CONFIG_SPL_FLUSH_IMAGE=y
-CONFIG_SPL_GD_ADDR=0xf8f9c000
-CONFIG_SPL_RELOC_STACK=0xf8f9d000
-CONFIG_SPL_RELOC_MALLOC=y
-CONFIG_SPL_RELOC_MALLOC_ADDR=0xf8fa5000
-CONFIG_SPL_RELOC_MALLOC_SIZE=0x5b000
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C=y
-CONFIG_SPL_MPC8XXX_INIT_DDR=y
-CONFIG_HUSH_PARSER=y
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_CMD_IMLS=y
-CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
-CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
-CONFIG_CMD_I2C=y
-CONFIG_LOADS_ECHO=y
-CONFIG_SYS_LOADS_BAUD_CHANGE=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nor0=ef000000.nor"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=ef000000.nor:256k(vsc7385-firmware),256k(dtb),4608k(kernel),9984k(fs),1280k(u-boot)"
-CONFIG_OF_CONTROL=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_ENV_RELOC_GD_ENV_ADDR=y
-CONFIG_USE_BOOTFILE=y
-CONFIG_BOOTFILE="uImage"
-CONFIG_USE_ETHPRIME=y
-CONFIG_ETHPRIME="eTSEC1"
-CONFIG_USE_HOSTNAME=y
-CONFIG_USE_ROOTPATH=y
-CONFIG_LBA48=y
-CONFIG_DDR_CLK_FREQ=66666666
-CONFIG_SYS_SPD_BUS_NUM=1
-CONFIG_CHIP_SELECTS_PER_CTRL=1
-CONFIG_SYS_DDR_RAW_TIMING=y
-CONFIG_SYS_BR0_PRELIM_BOOL=y
-CONFIG_SYS_BR0_PRELIM=0xEF001001
-CONFIG_SYS_OR0_PRELIM=0xFC000FF7
-CONFIG_SYS_BR2_PRELIM_BOOL=y
-CONFIG_SYS_BR2_PRELIM=0xFFB00801
-CONFIG_SYS_OR2_PRELIM=0xFFFE09FF
-CONFIG_SYS_BR3_PRELIM_BOOL=y
-CONFIG_SYS_BR3_PRELIM=0xFFA00801
-CONFIG_SYS_OR3_PRELIM=0xFFF009F7
-CONFIG_SPL_COMMON_INIT_DDR=y
-CONFIG_DM_I2C=y
-CONFIG_SPL_SYS_I2C_LEGACY=y
-CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
-CONFIG_SYS_I2C_FSL=y
-CONFIG_SYS_FSL_I2C_OFFSET=0x3000
-CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y
-CONFIG_SYS_FSL_I2C2_OFFSET=0x3100
-CONFIG_SYS_I2C_EEPROM_ADDR=0x52
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_EMPTY_INFO=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SYS_FLASH_QUIET_TEST=y
-CONFIG_SYS_MAX_FLASH_SECT=128
-CONFIG_DM_SPI_FLASH=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_DM_MDIO=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_VSC7385_ENET=y
-CONFIG_TSEC_ENET=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_FIXED=y
-CONFIG_PCIE_FSL=y
-CONFIG_DM_RTC=y
-CONFIG_RTC_PT7C4338=y
-CONFIG_DM_SERIAL=y
-CONFIG_SPL_SYS_NS16550_SERIAL=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_EHCI_FSL=y
-CONFIG_USB_STORAGE=y
diff --git a/configs/P2020RDB-PC_defconfig b/configs/P2020RDB-PC_defconfig
deleted file mode 100644
index a3efd89e218..00000000000
--- a/configs/P2020RDB-PC_defconfig
+++ /dev/null
@@ -1,123 +0,0 @@
-CONFIG_PPC=y
-CONFIG_TEXT_BASE=0xEFF40000
-CONFIG_SYS_MALLOC_LEN=0x100000
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc"
-CONFIG_SYS_MONITOR_LEN=786432
-CONFIG_ENV_ADDR=0xEFF20000
-CONFIG_MPC85xx=y
-CONFIG_SYS_INIT_RAM_LOCK=y
-# CONFIG_CMD_ERRATA is not set
-CONFIG_TARGET_P2020RDB=y
-CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
-CONFIG_L2_CACHE=y
-CONFIG_ENABLE_36BIT_PHYS=y
-CONFIG_USE_UBOOTPATH=y
-CONFIG_PCIE1=y
-CONFIG_PCIE2=y
-CONFIG_MP=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_NO_PBL=y
-CONFIG_BOOTDELAY=10
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_USE_BOOTCOMMAND=y
-CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw rootdelay=30 console=$consoledev,$baudrate $othbootargs;usb start;ext2load usb 0:1 $loadaddr /boot/$bootfile;ext2load usb 0:1 $fdtaddr /boot/$fdtfile;bootm $loadaddr - $fdtaddr"
-CONFIG_SYS_PBSIZE=276
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_MISC_INIT_R is not set
-CONFIG_HUSH_PARSER=y
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_CMD_IMLS=y
-CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
-CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
-CONFIG_CMD_I2C=y
-CONFIG_LOADS_ECHO=y
-CONFIG_SYS_LOADS_BAUD_CHANGE=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nor0=ef000000.nor"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=ef000000.nor:256k(vsc7385-firmware),256k(dtb),4608k(kernel),9984k(fs),1280k(u-boot)"
-CONFIG_OF_CONTROL=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_USE_BOOTFILE=y
-CONFIG_BOOTFILE="uImage"
-CONFIG_USE_ETHPRIME=y
-CONFIG_ETHPRIME="eTSEC1"
-CONFIG_USE_HOSTNAME=y
-CONFIG_USE_ROOTPATH=y
-CONFIG_LBA48=y
-CONFIG_DDR_CLK_FREQ=66666666
-CONFIG_SYS_SPD_BUS_NUM=1
-CONFIG_CHIP_SELECTS_PER_CTRL=1
-CONFIG_SYS_DDR_RAW_TIMING=y
-CONFIG_SYS_BR0_PRELIM_BOOL=y
-CONFIG_SYS_BR0_PRELIM=0xEF001001
-CONFIG_SYS_OR0_PRELIM=0xFC000FF7
-CONFIG_SYS_BR2_PRELIM_BOOL=y
-CONFIG_SYS_BR2_PRELIM=0xFFB00801
-CONFIG_SYS_OR2_PRELIM=0xFFFE09FF
-CONFIG_SYS_BR3_PRELIM_BOOL=y
-CONFIG_SYS_BR3_PRELIM=0xFFA00801
-CONFIG_SYS_OR3_PRELIM=0xFFF009F7
-CONFIG_COMMON_INIT_DDR=y
-CONFIG_SPL_COMMON_INIT_DDR=y
-CONFIG_DM_I2C=y
-CONFIG_SPL_SYS_I2C_LEGACY=y
-CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
-CONFIG_SYS_I2C_FSL=y
-CONFIG_SYS_FSL_I2C_OFFSET=0x3000
-CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y
-CONFIG_SYS_FSL_I2C2_OFFSET=0x3100
-CONFIG_SYS_I2C_EEPROM_ADDR=0x52
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_EMPTY_INFO=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SYS_FLASH_QUIET_TEST=y
-CONFIG_SYS_MAX_FLASH_SECT=128
-CONFIG_DM_SPI_FLASH=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_DM_MDIO=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_VSC7385_ENET=y
-CONFIG_TSEC_ENET=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_FIXED=y
-CONFIG_PCIE_FSL=y
-CONFIG_DM_RTC=y
-CONFIG_RTC_PT7C4338=y
-CONFIG_DM_SERIAL=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_EHCI_FSL=y
-CONFIG_USB_STORAGE=y
diff --git a/doc/README.mpc85xx-sd-spi-boot b/doc/README.mpc85xx-sd-spi-boot
index 7608fc3aacb..8e98fc9f659 100644
--- a/doc/README.mpc85xx-sd-spi-boot
+++ b/doc/README.mpc85xx-sd-spi-boot
@@ -59,9 +59,6 @@ P1022DS config_sram_p1022ds.dat
P2020DS config_sram_p2020ds.dat
P1020RDB config_ddr2_1g_p1020rdb_533M.dat
P1020RDB config_ddr2_1g_p1020rdb_667M.dat
-P2020RDB config_ddr2_1g_p2020rdb_800M.dat
-P2020RDB config_ddr2_1g_p2020rdb_667M.dat
-P2020RDB config_ddr3_1gb_64bit_p2020rdb_pc.dat
P1020RDB config_ddr3_1gb_p1_p2_rdb_pc_800M.dat
P1011RDB config_ddr3_1gb_p1_p2_rdb_pc_800M.dat
P1010RDB config_ddr3_1gb_p1010rdb_800M.dat
diff --git a/drivers/ddr/fsl/Kconfig b/drivers/ddr/fsl/Kconfig
index b11fa79ca59..d5c0af7d3b1 100644
--- a/drivers/ddr/fsl/Kconfig
+++ b/drivers/ddr/fsl/Kconfig
@@ -291,7 +291,7 @@ config SYS_OR7_PRELIM
endmenu
if TARGET_P1010RDB_PA || TARGET_P1010RDB_PB || TARGET_P1020RDB_PC || \
- TARGET_P1020RDB_PD || TARGET_P2020RDB
+ TARGET_P1020RDB_PD
config COMMON_INIT_DDR
bool "Do not have a TLB entry to cover common DDR init with serial presence detect (SPD)"
diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
index 2d9d5b27511..2ef8fa02188 100644
--- a/include/configs/p1_p2_rdb_pc.h
+++ b/include/configs/p1_p2_rdb_pc.h
@@ -60,25 +60,6 @@
*/
#endif
-#if defined(CONFIG_TARGET_P2020RDB)
-#define __SW_BOOT_MASK 0x03
-#define __SW_BOOT_NOR 0xc8
-#define __SW_BOOT_SPI 0x28
-#define __SW_BOOT_SD 0x68
-#define __SW_BOOT_SD2 0x18
-#define __SW_BOOT_NAND 0xe8
-#define __SW_BOOT_PCIE 0xa8
-#define __SW_NOR_BANK_MASK 0xfd
-#define __SW_NOR_BANK_UP 0x00
-#define __SW_NOR_BANK_LO 0x02
-#define __SW_BOOT_NOR_BANK_UP 0xc8 /* (__SW_BOOT_NOR | __SW_NOR_BANK_UP) */
-#define __SW_BOOT_NOR_BANK_LO 0xca /* (__SW_BOOT_NOR | __SW_NOR_BANK_LO) */
-#define __SW_BOOT_NOR_BANK_MASK 0x01 /* (__SW_BOOT_MASK & __SW_NOR_BANK_MASK) */
-/*
- * Dynamic MTD Partition support with mtdparts
- */
-#endif
-
#ifdef CONFIG_SDCARD
#define CFG_SYS_MMC_U_BOOT_SIZE (768 << 10)
#define CFG_SYS_MMC_U_BOOT_DST CONFIG_TEXT_BASE
@@ -125,7 +106,6 @@
#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
/* Default settings for DDR3 */
-#ifndef CONFIG_TARGET_P2020RDB
#define CFG_SYS_DDR_CS0_BNDS 0x0000003f
#define CFG_SYS_DDR_CS0_CONFIG 0x80014302
#define CFG_SYS_DDR_CS0_CONFIG_2 0x00000000
@@ -155,7 +135,6 @@
#define CFG_SYS_DDR_MODE_1 0x40461520
#define CFG_SYS_DDR_MODE_2 0x8000c000
#define CFG_SYS_DDR_INTERVAL 0x0C300000
-#endif
/*
* Memory map
--
2.47.3
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH 04/26] board: powerpc: Remove P3041DS support
2026-10-09 19:36 [PATCH 00/26] powerpc: drop EOL boards and SoCs, take over maintenance Bradley Morgan
` (2 preceding siblings ...)
2026-10-09 19:36 ` [PATCH 03/26] board: powerpc: Remove P2020RDB-PC support Bradley Morgan
@ 2026-10-09 19:36 ` Bradley Morgan
2026-10-09 19:36 ` [PATCH 05/26] board: powerpc: Remove P4080DS support Bradley Morgan
` (21 subsequent siblings)
25 siblings, 0 replies; 31+ messages in thread
From: Bradley Morgan @ 2026-10-09 19:36 UTC (permalink / raw)
To: Tom Rini, u-boot
Cc: Bradley Morgan, Marek Behún, Marek Mojík,
NXP i . MX U-Boot Team, Alexey Charkov, Anshul Dalal,
Daniel Golle, Fabio Estevam, Gaurav Jain, Ilias Apalodimas,
Jaehoon Chung, James Hilliard, Jerome Forissier, Johan Jonker,
Lukasz Majewski, Marek Vasut, Mario Six, Michael Walle,
Michal Simek, Neil Armstrong, Peng Fan, Pengpeng Hou,
Priyanka Jain, Quentin Schulz, Simon Glass, Stefano Babic,
Tanmay Kathpalia, Torsten Rupp, Vincent Jardin, Weijie Gao
NXP marks the P3041 development system no longer manufactured. Drop its target and device tree.
Signed-off-by: Bradley Morgan <brads@mainlining.org>
---
arch/powerpc/cpu/mpc85xx/Kconfig | 9 --
arch/powerpc/dts/Makefile | 1 -
arch/powerpc/dts/p3041.dtsi | 149 ---------------------------
arch/powerpc/dts/p3041ds.dts | 158 -----------------------------
arch/powerpc/dts/p3041si-post.dtsi | 43 --------
board/nxp/common/Makefile | 2 -
6 files changed, 362 deletions(-)
delete mode 100644 arch/powerpc/dts/p3041.dtsi
delete mode 100644 arch/powerpc/dts/p3041ds.dts
delete mode 100644 arch/powerpc/dts/p3041si-post.dtsi
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index 7e885014ebe..65081b5bd63 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -87,15 +87,6 @@ config TARGET_SOCRATES
select ARCH_MPC8544
select BINMAN
-config TARGET_P3041DS
- bool "Support P3041DS"
- select PHYS_64BIT
- select ARCH_P3041
- select BOARD_LATE_INIT if CHAIN_OF_TRUST
- select FSL_NGPIXIS
- imply SATA
- imply PANIC_HANG
-
config TARGET_P4080DS
bool "Support P4080DS"
select PHYS_64BIT
diff --git a/arch/powerpc/dts/Makefile b/arch/powerpc/dts/Makefile
index e44d49cabdf..c603369e7cc 100644
--- a/arch/powerpc/dts/Makefile
+++ b/arch/powerpc/dts/Makefile
@@ -11,7 +11,6 @@ dtb-$(CONFIG_TARGET_P1010RDB_PA) += p1010rdb-pa.dtb p1010rdb-pa_36b.dtb
dtb-$(CONFIG_TARGET_P1010RDB_PB) += p1010rdb-pb.dtb p1010rdb-pb_36b.dtb
dtb-$(CONFIG_TARGET_P1020RDB_PC) += p1020rdb-pc.dtb p1020rdb-pc_36b.dtb
dtb-$(CONFIG_TARGET_P1020RDB_PD) += p1020rdb-pd.dtb
-dtb-$(CONFIG_TARGET_P3041DS) += p3041ds.dtb
dtb-$(CONFIG_TARGET_P4080DS) += p4080ds.dtb
dtb-$(CONFIG_TARGET_P5040DS) += p5040ds.dtb
dtb-$(CONFIG_TARGET_SOCRATES) += socrates.dtb
diff --git a/arch/powerpc/dts/p3041.dtsi b/arch/powerpc/dts/p3041.dtsi
deleted file mode 100644
index e34117b65a0..00000000000
--- a/arch/powerpc/dts/p3041.dtsi
+++ /dev/null
@@ -1,149 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+ OR X11
-/*
- * P3041 Silicon/SoC Device Tree Source (pre include)
- *
- * Copyright 2010 - 2015 Freescale Semiconductor Inc.
- * Copyright 2019-2020 NXP
- */
-
-/dts-v1/;
-
-/include/ "e500mc_power_isa.dtsi"
-
-/ {
- compatible = "fsl,P3041";
- #address-cells = <2>;
- #size-cells = <2>;
- interrupt-parent = <&mpic>;
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu0: PowerPC,e500mc@0 {
- device_type = "cpu";
- reg = <0>;
- fsl,portid-mapping = <0x80000000>;
- };
- cpu1: PowerPC,e500mc@1 {
- device_type = "cpu";
- reg = <1>;
- fsl,portid-mapping = <0x40000000>;
- };
- cpu2: PowerPC,e500mc@2 {
- device_type = "cpu";
- reg = <2>;
- fsl,portid-mapping = <0x20000000>;
- };
- cpu3: PowerPC,e500mc@3 {
- device_type = "cpu";
- reg = <3>;
- fsl,portid-mapping = <0x10000000>;
- };
- };
-
- soc: soc@ffe000000 {
- ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
- reg = <0xf 0xfe000000 0 0x00001000>;
- #address-cells = <1>;
- #size-cells = <1>;
- device_type = "soc";
- compatible = "simple-bus";
-
- mpic: pic@40000 {
- interrupt-controller;
- #address-cells = <0>;
- #interrupt-cells = <4>;
- reg = <0x40000 0x40000>;
- compatible = "fsl,mpic", "chrp,open-pic";
- device_type = "open-pic";
- clock-frequency = <0x0>;
- };
-
- espi0: spi@110000 {
- compatible = "fsl,mpc8536-espi";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x110000 0x1000>;
- fsl,espi-num-chipselects = <4>;
- status = "disabled";
- };
-
- usb0: usb@fe210000 {
- compatible = "fsl-usb2-mph";
- reg = <0x210000 0x1000>;
- phy_type = "utmi";
- };
-
- usb1: usb@fe211000 {
- compatible = "fsl-usb2-dr";
- reg = <0x211000 0x1000>;
- phy_type = "utmi";
- };
-
- sata: sata@220000 {
- compatible = "fsl,pq-sata-v2";
- reg = <0x220000 0x1000>;
- interrupts = <68 0x2 0 0>;
- sata-offset = <0x1000>;
- sata-number = <2>;
- sata-fpdma = <0>;
- };
-
- esdhc: esdhc@114000 {
- compatible = "fsl,esdhc";
- reg = <0x114000 0x1000>;
- clock-frequency = <0>;
- };
- /include/ "qoriq-i2c-0.dtsi"
- /include/ "qoriq-i2c-1.dtsi"
- };
-
- pcie@ffe200000 {
- compatible = "fsl,pcie-p3041", "fsl,pcie-fsl-qoriq";
- reg = <0xf 0xfe200000 0x0 0x1000>; /* registers */
- law_trgt_if = <0>;
- #address-cells = <3>;
- #size-cells = <2>;
- device_type = "pci";
- bus-range = <0x0 0xff>;
- ranges = <0x01000000 0x0 0x00000000 0xf 0xf8000000 0x0 0x00010000 /* downstream I/O */
- 0x02000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000>; /* non-prefetchable memory */
- };
-
- pcie@ffe201000 {
- compatible = "fsl,pcie-p3041", "fsl,pcie-fsl-qoriq";
- reg = <0xf 0xfe201000 0x0 0x1000>; /* registers */
- law_trgt_if = <1>;
- #address-cells = <3>;
- #size-cells = <2>;
- device_type = "pci";
- bus-range = <0x0 0xff>;
- ranges = <0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000 /* downstream I/O */
- 0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000>; /* non-prefetchable memory */
- };
-
- pcie@ffe202000 {
- compatible = "fsl,pcie-p3041", "fsl,pcie-fsl-qoriq";
- reg = <0xf 0xfe202000 0x0 0x1000>; /* registers */
- law_trgt_if = <2>;
- #address-cells = <3>;
- #size-cells = <2>;
- device_type = "pci";
- bus-range = <0x0 0xff>;
- ranges = <0x01000000 0x0 0x00000000 0xf 0xf8020000 0x0 0x00010000 /* downstream I/O */
- 0x02000000 0x0 0xe0000000 0xc 0x40000000 0x0 0x20000000>; /* non-prefetchable memory */
- };
-
- pcie@ffe203000 {
- compatible = "fsl,pcie-p3041", "fsl,pcie-fsl-qoriq";
- reg = <0xf 0xfe203000 0x0 0x1000>; /* registers */
- law_trgt_if = <3>;
- #address-cells = <3>;
- #size-cells = <2>;
- device_type = "pci";
- bus-range = <0x0 0xff>;
- ranges = <0x01000000 0x0 0x00000000 0xf 0xf8030000 0x0 0x00010000 /* downstream I/O */
- 0x02000000 0x0 0xe0000000 0xc 0x60000000 0x0 0x20000000>; /* non-prefetchable memory */
- };
-};
diff --git a/arch/powerpc/dts/p3041ds.dts b/arch/powerpc/dts/p3041ds.dts
deleted file mode 100644
index 069dae3b85b..00000000000
--- a/arch/powerpc/dts/p3041ds.dts
+++ /dev/null
@@ -1,158 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+ OR X11
-/*
- * P3041DS Device Tree Source
- *
- * Copyright 2010 - 2015 Freescale Semiconductor Inc.
- * Copyright 2019-2020 NXP
- */
-
-/include/ "p3041.dtsi"
-
-/ {
- model = "fsl,P3041DS";
- compatible = "fsl,P3041DS";
- #address-cells = <2>;
- #size-cells = <2>;
- interrupt-parent = <&mpic>;
-
- aliases{
- phy_rgmii_0 = &phy_rgmii_0;
- phy_rgmii_1 = &phy_rgmii_1;
- phy_sgmii_1c = &phy_sgmii_1c;
- phy_sgmii_1d = &phy_sgmii_1d;
- phy_sgmii_1e = &phy_sgmii_1e;
- phy_sgmii_1f = &phy_sgmii_1f;
- phy_xgmii_1 = &phy_xgmii_1;
- phy_xgmii_2 = &phy_xgmii_2;
- emi1_rgmii = &hydra_mdio_rgmii;
- emi1_sgmii = &hydra_mdio_sgmii;
- emi2_xgmii = &hydra_mdio_xgmii;
- spi0 = &espi0;
- };
-
- soc: soc@ffe000000 {
- ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
- reg = <0xf 0xfe000000 0 0x00001000>;
- fman@400000{
- ethernet@e0000 {
- phy-handle = <&phy_sgmii_1c>;
- phy-connection-type = "sgmii";
- };
-
- ethernet@e2000 {
- phy-handle = <&phy_sgmii_1d>;
- phy-connection-type = "sgmii";
- };
-
- ethernet@e4000 {
- phy-handle = <&phy_sgmii_1e>;
- phy-connection-type = "sgmii";
- };
-
- ethernet@e6000 {
- phy-handle = <&phy_sgmii_1f>;
- phy-connection-type = "sgmii";
- };
-
- ethernet@e8000 {
- phy-handle = <&phy_rgmii_1>;
- phy-connection-type = "rgmii";
- };
-
- ethernet@f0000 {
- phy-handle = <&phy_xgmii_1>;
- phy-connection-type = "xgmii";
- };
-
- hydra_mdio_xgmii: mdio@f1000 {
- status = "disabled";
-
- phy_xgmii_1: ethernet-phy@4 {
- compatible = "ethernet-phy-ieee802.3-c45";
- reg = <0x4>;
- };
-
- phy_xgmii_2: ethernet-phy@0 {
- compatible = "ethernet-phy-ieee802.3-c45";
- reg = <0x0>;
- };
- };
- };
- };
-
- lbc: localbus@ffe124000 {
- reg = <0xf 0xfe124000 0 0x1000>;
- ranges = <0 0 0xf 0xe8000000 0x08000000
- 2 0 0xf 0xffa00000 0x00040000
- 3 0 0xf 0xffdf0000 0x00008000>;
-
- board-control@3,0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "fsl,p3041ds-fpga", "fsl,fpga-ngpixis";
- reg = <3 0 0x30>;
- ranges = <0 3 0 0x30>;
-
- mdio-mux-emi1 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "mdio-mux-mmioreg", "mdio-mux";
- mdio-parent-bus = <&mdio0>;
- reg = <9 1>;
- mux-mask = <0x78>;
-
- hydra_mdio_rgmii: rgmii-mdio@8 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <8>;
- status = "disabled";
-
- phy_rgmii_0: ethernet-phy@0 {
- reg = <0x0>;
- };
-
- phy_rgmii_1: ethernet-phy@1 {
- reg = <0x1>;
- };
- };
-
- hydra_mdio_sgmii: sgmii-mdio@28 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x28>;
- status = "disabled";
-
- phy_sgmii_1c: ethernet-phy@1c {
- reg = <0x1c>;
- };
-
- phy_sgmii_1d: ethernet-phy@1d {
- reg = <0x1d>;
- };
-
- phy_sgmii_1e: ethernet-phy@1e {
- reg = <0x1e>;
- };
-
- phy_sgmii_1f: ethernet-phy@1f {
- reg = <0x1f>;
- };
- };
- };
- };
- };
-};
-
-&espi0 {
- status = "okay";
- flash@0 {
- compatible = "jedec,spi-nor";
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0>;
- /* input clock */
- spi-max-frequency = <10000000>;
- };
-};
-
-/include/ "p3041si-post.dtsi"
diff --git a/arch/powerpc/dts/p3041si-post.dtsi b/arch/powerpc/dts/p3041si-post.dtsi
deleted file mode 100644
index a3e8088d25b..00000000000
--- a/arch/powerpc/dts/p3041si-post.dtsi
+++ /dev/null
@@ -1,43 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-/*
- * P3041 Silicon/SoC Device Tree Source (post include)
- *
- * Copyright 2011 - 2015 Freescale Semiconductor Inc.
- * Copyright 2020 NXP
- *
- */
-
-&soc {
-
-/include/ "qoriq-clockgen1.dtsi"
-/include/ "qoriq-gpio-0.dtsi"
-/include/ "qoriq-sec4.2-0.dtsi"
-
-/* include used FMan blocks */
-/include/ "qoriq-fman-0.dtsi"
-/include/ "qoriq-fman-0-1g-0.dtsi"
-/include/ "qoriq-fman-0-1g-1.dtsi"
-/include/ "qoriq-fman-0-1g-2.dtsi"
-/include/ "qoriq-fman-0-1g-3.dtsi"
-/include/ "qoriq-fman-0-1g-4.dtsi"
-/include/ "qoriq-fman-0-10g-0.dtsi"
- fman@400000 {
- enet0: ethernet@e0000 {
- };
-
- enet1: ethernet@e2000 {
- };
-
- enet2: ethernet@e4000 {
- };
-
- enet3: ethernet@e6000 {
- };
-
- enet4: ethernet@e8000 {
- };
-
- enet5: ethernet@f0000 {
- };
- };
-};
diff --git a/board/nxp/common/Makefile b/board/nxp/common/Makefile
index 46e43a4e45a..ba1aa084aa4 100644
--- a/board/nxp/common/Makefile
+++ b/board/nxp/common/Makefile
@@ -49,7 +49,6 @@ obj-$(CONFIG_DEEP_SLEEP) += mpc85xx_sleep.o
endif
-obj-$(CONFIG_TARGET_P3041DS) += ics307_clk.o
obj-$(CONFIG_TARGET_P4080DS) += ics307_clk.o
obj-$(CONFIG_TARGET_P5040DS) += ics307_clk.o
ifeq ($(CONFIG_$(PHASE_)POWER_LEGACY),y)
@@ -67,7 +66,6 @@ obj-$(CONFIG_EMC2305) += emc2305.o
# deal with common files for P-series corenet based devices
obj-$(CONFIG_TARGET_P2041RDB) += p_corenet/
-obj-$(CONFIG_TARGET_P3041DS) += p_corenet/
obj-$(CONFIG_TARGET_P4080DS) += p_corenet/
obj-$(CONFIG_TARGET_P5040DS) += p_corenet/
--
2.47.3
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH 05/26] board: powerpc: Remove P4080DS support
2026-10-09 19:36 [PATCH 00/26] powerpc: drop EOL boards and SoCs, take over maintenance Bradley Morgan
` (3 preceding siblings ...)
2026-10-09 19:36 ` [PATCH 04/26] board: powerpc: Remove P3041DS support Bradley Morgan
@ 2026-10-09 19:36 ` Bradley Morgan
2026-10-09 19:36 ` [PATCH 06/26] board: powerpc: Remove P5040DS support Bradley Morgan
` (20 subsequent siblings)
25 siblings, 0 replies; 31+ messages in thread
From: Bradley Morgan @ 2026-10-09 19:36 UTC (permalink / raw)
To: Tom Rini, u-boot
Cc: Bradley Morgan, Marek Behún, Marek Mojík,
NXP i . MX U-Boot Team, Alexey Charkov, Anshul Dalal,
Daniel Golle, Fabio Estevam, Gaurav Jain, Ilias Apalodimas,
Jaehoon Chung, James Hilliard, Jerome Forissier, Johan Jonker,
Lukasz Majewski, Marek Vasut, Mario Six, Michael Walle,
Michal Simek, Neil Armstrong, Peng Fan, Pengpeng Hou,
Priyanka Jain, Quentin Schulz, Simon Glass, Stefano Babic,
Tanmay Kathpalia, Torsten Rupp, Vincent Jardin, Weijie Gao
NXP marks the P4080 Development System no longer manufactured. Drop its target, device trees, and board guide.
Signed-off-by: Bradley Morgan <brads@mainlining.org>
---
arch/powerpc/cpu/mpc85xx/Kconfig | 9 --
arch/powerpc/dts/Makefile | 1 -
arch/powerpc/dts/p4080.dtsi | 148 -------------------
arch/powerpc/dts/p4080ds.dts | 220 -----------------------------
arch/powerpc/dts/p4080si-post.dtsi | 62 --------
board/nxp/common/Makefile | 2 -
doc/README.srio-pcie-boot-corenet | 118 ----------------
7 files changed, 560 deletions(-)
delete mode 100644 arch/powerpc/dts/p4080.dtsi
delete mode 100644 arch/powerpc/dts/p4080ds.dts
delete mode 100644 arch/powerpc/dts/p4080si-post.dtsi
delete mode 100644 doc/README.srio-pcie-boot-corenet
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index 65081b5bd63..5e480325062 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -87,15 +87,6 @@ config TARGET_SOCRATES
select ARCH_MPC8544
select BINMAN
-config TARGET_P4080DS
- bool "Support P4080DS"
- select PHYS_64BIT
- select ARCH_P4080
- select BOARD_LATE_INIT if CHAIN_OF_TRUST
- select FSL_NGPIXIS
- imply SATA
- imply PANIC_HANG
-
config TARGET_P5040DS
bool "Support P5040DS"
select PHYS_64BIT
diff --git a/arch/powerpc/dts/Makefile b/arch/powerpc/dts/Makefile
index c603369e7cc..09b79faf165 100644
--- a/arch/powerpc/dts/Makefile
+++ b/arch/powerpc/dts/Makefile
@@ -11,7 +11,6 @@ dtb-$(CONFIG_TARGET_P1010RDB_PA) += p1010rdb-pa.dtb p1010rdb-pa_36b.dtb
dtb-$(CONFIG_TARGET_P1010RDB_PB) += p1010rdb-pb.dtb p1010rdb-pb_36b.dtb
dtb-$(CONFIG_TARGET_P1020RDB_PC) += p1020rdb-pc.dtb p1020rdb-pc_36b.dtb
dtb-$(CONFIG_TARGET_P1020RDB_PD) += p1020rdb-pd.dtb
-dtb-$(CONFIG_TARGET_P4080DS) += p4080ds.dtb
dtb-$(CONFIG_TARGET_P5040DS) += p5040ds.dtb
dtb-$(CONFIG_TARGET_SOCRATES) += socrates.dtb
dtb-$(CONFIG_TARGET_T1024RDB) += t1024rdb.dtb
diff --git a/arch/powerpc/dts/p4080.dtsi b/arch/powerpc/dts/p4080.dtsi
deleted file mode 100644
index 8ab5cf541a0..00000000000
--- a/arch/powerpc/dts/p4080.dtsi
+++ /dev/null
@@ -1,148 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+ OR X11
-/*
- * P4080/P4040 Silicon/SoC Device Tree Source (pre include)
- *
- * Copyright 2011 - 2015 Freescale Semiconductor Inc.
- * Copyright 2019-2020 NXP
- */
-
-/dts-v1/;
-
-/include/ "e500mc_power_isa.dtsi"
-
-/ {
- compatible = "fsl,P4080";
- #address-cells = <2>;
- #size-cells = <2>;
- interrupt-parent = <&mpic>;
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu0: PowerPC,e500mc@0 {
- device_type = "cpu";
- reg = <0>;
- fsl,portid-mapping = <0x80000000>;
- };
- cpu1: PowerPC,e500mc@1 {
- device_type = "cpu";
- reg = <1>;
- fsl,portid-mapping = <0x40000000>;
- };
- cpu2: PowerPC,e500mc@2 {
- device_type = "cpu";
- reg = <2>;
- fsl,portid-mapping = <0x20000000>;
- };
- cpu3: PowerPC,e500mc@3 {
- device_type = "cpu";
- reg = <3>;
- fsl,portid-mapping = <0x10000000>;
- };
- cpu4: PowerPC,e500mc@4 {
- device_type = "cpu";
- reg = <4>;
- fsl,portid-mapping = <0x08000000>;
- };
- cpu5: PowerPC,e500mc@5 {
- device_type = "cpu";
- reg = <5>;
- fsl,portid-mapping = <0x04000000>;
- };
- cpu6: PowerPC,e500mc@6 {
- device_type = "cpu";
- reg = <6>;
- fsl,portid-mapping = <0x02000000>;
- };
- cpu7: PowerPC,e500mc@7 {
- device_type = "cpu";
- reg = <7>;
- fsl,portid-mapping = <0x01000000>;
- };
- };
-
- soc: soc@ffe000000 {
- ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
- reg = <0xf 0xfe000000 0 0x00001000>;
- #address-cells = <1>;
- #size-cells = <1>;
- device_type = "soc";
- compatible = "simple-bus";
-
- mpic: pic@40000 {
- interrupt-controller;
- #address-cells = <0>;
- #interrupt-cells = <4>;
- reg = <0x40000 0x40000>;
- compatible = "fsl,mpic", "chrp,open-pic";
- device_type = "open-pic";
- clock-frequency = <0x0>;
- };
-
- espi0: spi@110000 {
- compatible = "fsl,mpc8536-espi";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x110000 0x1000>;
- fsl,espi-num-chipselects = <4>;
- status = "disabled";
- };
-
- esdhc: esdhc@114000 {
- compatible = "fsl,esdhc";
- reg = <0x114000 0x1000>;
- clock-frequency = <0>;
- };
-
- usb0@210000 {
- compatible = "fsl-usb2-mph";
- reg = <0x210000 0x1000>;
- phy_type = "ulpi";
- };
-
- usb1@211000 {
- compatible = "fsl-usb2-dr";
- reg = <0x211000 0x1000>;
- phy_type = "ulpi";
- };
- /include/ "qoriq-i2c-0.dtsi"
- /include/ "qoriq-i2c-1.dtsi"
- };
-
- pcie@ffe200000 {
- compatible = "fsl,pcie-p4080", "fsl,pcie-fsl-qoriq";
- reg = <0xf 0xfe200000 0x0 0x1000>; /* registers */
- law_trgt_if = <0>;
- #address-cells = <3>;
- #size-cells = <2>;
- device_type = "pci";
- bus-range = <0x0 0xff>;
- ranges = <0x01000000 0x0 0x00000000 0xf 0xf8000000 0x0 0x00010000 /* downstream I/O */
- 0x02000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000>; /* non-prefetchable memory */
- };
-
- pcie@ffe201000 {
- compatible = "fsl,pcie-p4080", "fsl,pcie-fsl-qoriq";
- reg = <0xf 0xfe201000 0x0 0x1000>; /* registers */
- law_trgt_if = <1>;
- #address-cells = <3>;
- #size-cells = <2>;
- device_type = "pci";
- bus-range = <0x0 0xff>;
- ranges = <0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000 /* downstream I/O */
- 0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000>; /* non-prefetchable memory */
- };
-
- pcie@ffe202000 {
- compatible = "fsl,pcie-p4080", "fsl,pcie-fsl-qoriq";
- reg = <0xf 0xfe202000 0x0 0x1000>; /* registers */
- law_trgt_if = <2>;
- #address-cells = <3>;
- #size-cells = <2>;
- device_type = "pci";
- bus-range = <0x0 0xff>;
- ranges = <0x01000000 0x0 0x00000000 0xf 0xf8020000 0x0 0x00010000 /* downstream I/O */
- 0x02000000 0x0 0xe0000000 0xc 0x40000000 0x0 0x20000000>; /* non-prefetchable memory */
- };
-};
diff --git a/arch/powerpc/dts/p4080ds.dts b/arch/powerpc/dts/p4080ds.dts
deleted file mode 100644
index d5618f1e49a..00000000000
--- a/arch/powerpc/dts/p4080ds.dts
+++ /dev/null
@@ -1,220 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+ OR X11
-/*
- * P4080DS Device Tree Source
- *
- * Copyright 2011 - 2015 Freescale Semiconductor Inc.
- * Copyright 2019-2020 NXP
- */
-
-/include/ "p4080.dtsi"
-
-/ {
- model = "fsl,P4080DS";
- compatible = "fsl,P4080DS";
- #address-cells = <2>;
- #size-cells = <2>;
- interrupt-parent = <&mpic>;
-
- aliases {
- phy_rgmii = &phyrgmii;
- phy5_slot3 = &phy5slot3;
- phy6_slot3 = &phy6slot3;
- phy7_slot3 = &phy7slot3;
- phy8_slot3 = &phy8slot3;
- emi1_slot3 = &p4080mdio2;
- emi1_slot4 = &p4080mdio1;
- emi1_slot5 = &p4080mdio3;
- emi1_rgmii = &p4080mdio0;
- emi2_slot4 = &p4080xmdio1;
- emi2_slot5 = &p4080xmdio3;
- spi0 = &espi0;
- };
-
- soc: soc@ffe000000 {
- ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
- reg = <0xf 0xfe000000 0 0x00001000>;
-
- fman@400000 {
- ethernet@e0000 {
- phy-handle = <&phy0>;
- phy-connection-type = "sgmii";
- };
-
- ethernet@e2000 {
- phy-handle = <&phy1>;
- phy-connection-type = "sgmii";
- };
-
- ethernet@e4000 {
- phy-handle = <&phy2>;
- phy-connection-type = "sgmii";
- };
-
- ethernet@e6000 {
- phy-handle = <&phy3>;
- phy-connection-type = "sgmii";
- };
-
- ethernet@f0000 {
- phy-handle = <&phy10>;
- phy-connection-type = "xgmii";
- };
- };
-
- fman@500000 {
- ethernet@e0000 {
- phy-handle = <&phy5>;
- phy-connection-type = "sgmii";
- };
-
- ethernet@e2000 {
- phy-handle = <&phy6>;
- phy-connection-type = "sgmii";
- };
-
- ethernet@e4000 {
- phy-handle = <&phy7>;
- phy-connection-type = "sgmii";
- };
-
- ethernet@e6000 {
- phy-handle = <&phy8>;
- phy-connection-type = "sgmii";
- };
-
- ethernet@f0000 {
- phy-handle = <&phy11>;
- phy-connection-type = "xgmii";
- };
- };
- };
-
- mdio-mux-emi1 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "mdio-mux-gpio", "mdio-mux";
- mdio-parent-bus = <&mdio0>;
- gpios = <&gpio0 1 0>, <&gpio0 0 0>;
-
- p4080mdio0: mdio@0 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0>;
-
- phyrgmii: ethernet-phy@0 {
- reg = <0x0>;
- };
- };
-
- p4080mdio1: mdio@1 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <1>;
-
- phy5: ethernet-phy@1c {
- reg = <0x1c>;
- };
-
- phy6: ethernet-phy@1d {
- reg = <0x1d>;
- };
-
- phy7: ethernet-phy@1e {
- reg = <0x1e>;
- };
-
- phy8: ethernet-phy@1f {
- reg = <0x1f>;
- };
- };
-
- p4080mdio2: mdio@2 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <2>;
- status = "disabled";
-
- phy5slot3: ethernet-phy@1c {
- reg = <0x1c>;
- };
-
- phy6slot3: ethernet-phy@1d {
- reg = <0x1d>;
- };
-
- phy7slot3: ethernet-phy@1e {
- reg = <0x1e>;
- };
-
- phy8slot3: ethernet-phy@1f {
- reg = <0x1f>;
- };
- };
-
- p4080mdio3: mdio@3 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <3>;
-
- phy0: ethernet-phy@1c {
- reg = <0x1c>;
- };
-
- phy1: ethernet-phy@1d {
- reg = <0x1d>;
- };
-
- phy2: ethernet-phy@1e {
- reg = <0x1e>;
- };
-
- phy3: ethernet-phy@1f {
- reg = <0x1f>;
- };
- };
- };
-
- mdio-mux-emi2 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "mdio-mux-gpio", "mdio-mux";
- mdio-parent-bus = <&xmdio0>;
- gpios = <&gpio0 3 0>, <&gpio0 2 0>;
-
- p4080xmdio1: mdio@1 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <1>;
-
- phy11: ethernet-phy@0 {
- compatible = "ethernet-phy-ieee802.3-c45";
- reg = <0x0>;
- };
- };
-
- p4080xmdio3: mdio@3 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <3>;
-
- phy10: ethernet-phy@4 {
- compatible = "ethernet-phy-ieee802.3-c45";
- reg = <0x4>;
- };
- };
- };
-};
-
-&espi0 {
- status = "okay";
- flash@0 {
- compatible = "jedec,spi-nor";
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0>;
- /* input clock */
- spi-max-frequency = <10000000>;
- };
-};
-
-/include/ "p4080si-post.dtsi"
diff --git a/arch/powerpc/dts/p4080si-post.dtsi b/arch/powerpc/dts/p4080si-post.dtsi
deleted file mode 100644
index 56b79b14f4a..00000000000
--- a/arch/powerpc/dts/p4080si-post.dtsi
+++ /dev/null
@@ -1,62 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-/*
- * P4080/P4040 Silicon/SoC Device Tree Source (post include)
- *
- * Copyright 2011 - 2015 Freescale Semiconductor Inc.
- * Copyright 2020 NXP
- *
- */
-
-&soc {
-
-/include/ "qoriq-clockgen1.dtsi"
-/include/ "qoriq-gpio-0.dtsi"
-/include/ "qoriq-sec4.0-0.dtsi"
-
-/* include used FMan blocks */
-/include/ "qoriq-fman-0.dtsi"
-/include/ "qoriq-fman-0-1g-0.dtsi"
-/include/ "qoriq-fman-0-1g-1.dtsi"
-/include/ "qoriq-fman-0-1g-2.dtsi"
-/include/ "qoriq-fman-0-1g-3.dtsi"
-/include/ "qoriq-fman-0-10g-0.dtsi"
- fman@400000 {
- enet0: ethernet@e0000 {
- };
-
- enet1: ethernet@e2000 {
- };
-
- enet2: ethernet@e4000 {
- };
-
- enet3: ethernet@e6000 {
- };
-
- enet4: ethernet@f0000 {
- };
- };
-
-/include/ "qoriq-fman-1.dtsi"
-/include/ "qoriq-fman-1-1g-0.dtsi"
-/include/ "qoriq-fman-1-1g-1.dtsi"
-/include/ "qoriq-fman-1-1g-2.dtsi"
-/include/ "qoriq-fman-1-1g-3.dtsi"
-/include/ "qoriq-fman-1-10g-0.dtsi"
- fman@500000 {
- enet5: ethernet@e0000 {
- };
-
- enet6: ethernet@e2000 {
- };
-
- enet7: ethernet@e4000 {
- };
-
- enet8: ethernet@e6000 {
- };
-
- enet9: ethernet@f0000 {
- };
- };
-};
diff --git a/board/nxp/common/Makefile b/board/nxp/common/Makefile
index ba1aa084aa4..8fd6d6ce8c2 100644
--- a/board/nxp/common/Makefile
+++ b/board/nxp/common/Makefile
@@ -49,7 +49,6 @@ obj-$(CONFIG_DEEP_SLEEP) += mpc85xx_sleep.o
endif
-obj-$(CONFIG_TARGET_P4080DS) += ics307_clk.o
obj-$(CONFIG_TARGET_P5040DS) += ics307_clk.o
ifeq ($(CONFIG_$(PHASE_)POWER_LEGACY),y)
obj-$(CONFIG_POWER_PFUZE100) += pfuze.o
@@ -66,7 +65,6 @@ obj-$(CONFIG_EMC2305) += emc2305.o
# deal with common files for P-series corenet based devices
obj-$(CONFIG_TARGET_P2041RDB) += p_corenet/
-obj-$(CONFIG_TARGET_P4080DS) += p_corenet/
obj-$(CONFIG_TARGET_P5040DS) += p_corenet/
obj-$(CONFIG_LAYERSCAPE_NS_ACCESS) += ns_access.o
diff --git a/doc/README.srio-pcie-boot-corenet b/doc/README.srio-pcie-boot-corenet
deleted file mode 100644
index 5625ad1a2bb..00000000000
--- a/doc/README.srio-pcie-boot-corenet
+++ /dev/null
@@ -1,118 +0,0 @@
----------------------------------------
-SRIO and PCIE Boot on Corenet Platforms
----------------------------------------
-
-For some PowerPC processors with SRIO or PCIE interface, boot location can be
-configured to SRIO or PCIE by RCW. The processor booting from SRIO or PCIE can
-do without flash for u-boot image, ucode and ENV. All the images can be fetched
-from another processor's memory space by SRIO or PCIE link connected between
-them.
-
-This document describes the processes based on an example implemented on P4080DS
-platforms and a RCW example with boot from SRIO or PCIE configuration.
-
-Environment of the SRIO or PCIE boot:
- a) Master and slave can be SOCs in one board or SOCs in separate boards.
- b) They are connected with SRIO or PCIE links, whether 1x, 2x or 4x, and
- directly or through switch system.
- c) Only Master has NorFlash for booting, and all the Master's and Slave's
- U-Boot images, UCodes will be stored in this flash.
- d) Slave has its own EEPROM for RCW and PBI.
- e) Slave's RCW should configure the SerDes for SRIO or PCIE boot port, set
- the boot location to SRIO or PCIE, and holdoff all the cores.
-
- ----------- ----------- -----------
- | | | | | |
- | | | | | |
- | NorFlash|<----->| Master |SRIO or PCIE | Slave |<---->[EEPROM]
- | | | |<===========>| |
- | | | | | |
- ----------- ----------- -----------
-
-The example based on P4080DS platform:
- Two P4080DS platforms can be used to implement the boot from SRIO or PCIE.
- Their SRIO or PCIE ports 1 will be connected directly and will be used for
- the boot from SRIO or PCIE.
-
- 1. Slave's RCW example for boot from SRIO port 1 and all cores in holdoff.
- 00000000: aa55 aa55 010e 0100 0c58 0000 0000 0000
- 00000010: 1818 1818 0000 8888 7440 4000 0000 2000
- 00000020: f440 0000 0100 0000 0000 0000 0000 0000
- 00000030: 0000 0000 0083 0000 0000 0000 0000 0000
- 00000040: 0000 0000 0000 0000 0813 8040 063c 778f
-
- 2. Slave's RCW example for boot from PCIE port 1 and all cores in holdoff.
- 00000000: aa55 aa55 010e 0100 0c58 0000 0000 0000
- 00000010: 1818 1818 0000 8888 1440 4000 0000 2000
- 00000020: f040 0000 0100 0000 0020 0000 0000 0000
- 00000030: 0000 0000 0083 0000 0000 0000 0000 0000
- 00000040: 0000 0000 0000 0000 0813 8040 547e ffc9
-
- 3. Sequence in Step by Step.
- a) Update RCW for slave with boot from SRIO or PCIE port 1 configuration.
- b) Program slave's U-Boot image, UCode, and ENV parameters into master's
- NorFlash.
- c) Set environment variable "bootmaster" to "SRIO1" or "PCIE1" and save
- environment for master.
- env set bootmaster SRIO1
- or
- env set bootmaster PCIE1
- saveenv
- d) Restart up master and it will boot up normally from its NorFlash.
- Then, it will finish necessary configurations for slave's boot from
- SRIO or PCIE port 1.
- e) Master will set inbound SRIO or PCIE windows covered slave's U-Boot
- image stored in master's NorFlash.
- f) Master will set an inbound SRIO or PCIE window covered slave's UCode
- and ENV stored in master's NorFlash.
- g) Master will set outbound SRIO or PCIE windows in order to configure
- slave's registers for the core's releasing.
- h) Since all cores of slave in holdoff, slave should be powered on before
- all the above master's steps, and wait to be released by master. In the
- startup phase of the slave from SRIO or PCIE, it will finish some
- necessary configurations.
- i) Slave will set a specific TLB entry for the boot process.
- j) Slave will set a LAW entry with the TargetID SRIO or PCIE port 1 for
- the boot.
- k) Slave will set a specific TLB entry in order to fetch UCode and ENV
- from master.
- l) Slave will set a LAW entry with the TargetID SRIO or PCIE port 1 for
- UCode and ENV.
-
-How to use this feature:
- To use this feature, you need to focus those points.
-
- 1. Slave's RCW with SRIO or PCIE boot configurations, and all cores in holdoff
- configurations.
- Please refer to the examples given above.
-
- 2. U-Boot image's compilation.
- For master, U-Boot image should be generated normally.
-
- For example, master U-Boot image used on P4080DS should be compiled with
-
- make P4080DS_config.
-
- For slave, U-Boot image should be generated specifically by
-
- make xxxx_SRIO_PCIE_BOOT_config.
-
- For example, slave U-Boot image used on P4080DS should be compiled with
-
- make P4080DS_SRIO_PCIE_BOOT_config.
-
- 3. Necessary modifications based on a specific environment.
- For a specific environment, the addresses of the slave's U-Boot image,
- UCode, ENV stored in master's NorFlash, and any other configurations
- can be modified in the file:
- include/configs/corenet_ds.h.
-
- 4. Set and save the environment variable "bootmaster" with "SRIO1", "SRIO2"
- or "PCIE1", "PCIE2", "PCIE3" for master, and then restart it in order to
- perform the role as a master for boot from SRIO or PCIE.
-
-NOTE: When the Slave's ENV parameters are stored in Master's NorFlash,
- it can fetch them through PCIE or SRIO interface. But the ENV
- parameters can not be modified by "saveenv" or other commands under
- the Slave's u-boot environment, because the Slave can not erase,
- write Master's NorFlash by PCIE or SRIO link.
--
2.47.3
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH 06/26] board: powerpc: Remove P5040DS support
2026-10-09 19:36 [PATCH 00/26] powerpc: drop EOL boards and SoCs, take over maintenance Bradley Morgan
` (4 preceding siblings ...)
2026-10-09 19:36 ` [PATCH 05/26] board: powerpc: Remove P4080DS support Bradley Morgan
@ 2026-10-09 19:36 ` Bradley Morgan
2026-10-09 19:36 ` [PATCH 07/26] board: powerpc: Remove T1042D4RDB support Bradley Morgan
` (19 subsequent siblings)
25 siblings, 0 replies; 31+ messages in thread
From: Bradley Morgan @ 2026-10-09 19:36 UTC (permalink / raw)
To: Tom Rini, u-boot
Cc: Bradley Morgan, Marek Behún, Marek Mojík,
NXP i . MX U-Boot Team, Alexey Charkov, Anshul Dalal,
Daniel Golle, Fabio Estevam, Gaurav Jain, Ilias Apalodimas,
Jaehoon Chung, James Hilliard, Jerome Forissier, Johan Jonker,
Lukasz Majewski, Marek Vasut, Mario Six, Michael Walle,
Michal Simek, Neil Armstrong, Peng Fan, Pengpeng Hou,
Priyanka Jain, Quentin Schulz, Simon Glass, Stefano Babic,
Tanmay Kathpalia, Torsten Rupp, Vincent Jardin, Weijie Gao
The P5040DS-PB board and its P5040 processor are no longer manufactured. Drop the target, device trees, and its PIXIS support.
Signed-off-by: Bradley Morgan <brads@mainlining.org>
---
arch/powerpc/cpu/mpc85xx/Kconfig | 13 --
arch/powerpc/dts/Makefile | 1 -
arch/powerpc/dts/p5040.dtsi | 137 --------------
arch/powerpc/dts/p5040ds.dts | 281 -----------------------------
arch/powerpc/dts/p5040si-post.dtsi | 70 -------
board/nxp/common/Makefile | 5 -
board/nxp/common/ics307_clk.c | 149 ---------------
board/nxp/common/ics307_clk.h | 14 --
board/nxp/common/ngpixis.c | 247 -------------------------
board/nxp/common/ngpixis.h | 60 ------
10 files changed, 977 deletions(-)
delete mode 100644 arch/powerpc/dts/p5040.dtsi
delete mode 100644 arch/powerpc/dts/p5040ds.dts
delete mode 100644 arch/powerpc/dts/p5040si-post.dtsi
delete mode 100644 board/nxp/common/ics307_clk.c
delete mode 100644 board/nxp/common/ics307_clk.h
delete mode 100644 board/nxp/common/ngpixis.c
delete mode 100644 board/nxp/common/ngpixis.h
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index 5e480325062..8a37191bea0 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -87,16 +87,6 @@ config TARGET_SOCRATES
select ARCH_MPC8544
select BINMAN
-config TARGET_P5040DS
- bool "Support P5040DS"
- select PHYS_64BIT
- select ARCH_P5040
- select BOARD_LATE_INIT if CHAIN_OF_TRUST
- select FSL_NGPIXIS
- select SYS_FSL_RAID_ENGINE
- imply SATA
- imply PANIC_HANG
-
config TARGET_P1010RDB_PA
bool "Support P1010RDB_PA"
select ARCH_P1010
@@ -1392,9 +1382,6 @@ config FSL_CORENET
bool
select SYS_FSL_CPC
-config FSL_NGPIXIS
- bool
-
config SYS_CPC_REINIT_F
bool
help
diff --git a/arch/powerpc/dts/Makefile b/arch/powerpc/dts/Makefile
index 09b79faf165..3f5473b80af 100644
--- a/arch/powerpc/dts/Makefile
+++ b/arch/powerpc/dts/Makefile
@@ -11,7 +11,6 @@ dtb-$(CONFIG_TARGET_P1010RDB_PA) += p1010rdb-pa.dtb p1010rdb-pa_36b.dtb
dtb-$(CONFIG_TARGET_P1010RDB_PB) += p1010rdb-pb.dtb p1010rdb-pb_36b.dtb
dtb-$(CONFIG_TARGET_P1020RDB_PC) += p1020rdb-pc.dtb p1020rdb-pc_36b.dtb
dtb-$(CONFIG_TARGET_P1020RDB_PD) += p1020rdb-pd.dtb
-dtb-$(CONFIG_TARGET_P5040DS) += p5040ds.dtb
dtb-$(CONFIG_TARGET_SOCRATES) += socrates.dtb
dtb-$(CONFIG_TARGET_T1024RDB) += t1024rdb.dtb
dtb-$(CONFIG_TARGET_T1042D4RDB) += t1042d4rdb.dtb
diff --git a/arch/powerpc/dts/p5040.dtsi b/arch/powerpc/dts/p5040.dtsi
deleted file mode 100644
index 10402cf2224..00000000000
--- a/arch/powerpc/dts/p5040.dtsi
+++ /dev/null
@@ -1,137 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+ OR X11
-/*
- * P5040 Silicon/SoC Device Tree Source (pre include)
- *
- * Copyright 2012 - 2015 Freescale Semiconductor Inc.
- * Copyright 2019-2020 NXP
- */
-
-/dts-v1/;
-
-/include/ "e5500_power_isa.dtsi"
-
-/ {
- #address-cells = <2>;
- #size-cells = <2>;
- interrupt-parent = <&mpic>;
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu0: PowerPC,e5500@0 {
- device_type = "cpu";
- reg = <0>;
- fsl,portid-mapping = <0x80000000>;
- };
- cpu1: PowerPC,e5500@1 {
- device_type = "cpu";
- reg = <1>;
- fsl,portid-mapping = <0x40000000>;
- };
- cpu2: PowerPC,e5500@2 {
- device_type = "cpu";
- reg = <2>;
- fsl,portid-mapping = <0x20000000>;
- };
- cpu3: PowerPC,e5500@3 {
- device_type = "cpu";
- reg = <3>;
- fsl,portid-mapping = <0x10000000>;
- };
- };
-
- soc: soc@ffe000000 {
- ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
- reg = <0xf 0xfe000000 0 0x00001000>;
- #address-cells = <1>;
- #size-cells = <1>;
- device_type = "soc";
- compatible = "simple-bus";
-
- mpic: pic@40000 {
- interrupt-controller;
- #address-cells = <0>;
- #interrupt-cells = <4>;
- reg = <0x40000 0x40000>;
- compatible = "fsl,mpic", "chrp,open-pic";
- device_type = "open-pic";
- clock-frequency = <0x0>;
- };
-
- espi0: spi@110000 {
- compatible = "fsl,mpc8536-espi";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x110000 0x1000>;
- fsl,espi-num-chipselects = <4>;
- status = "disabled";
- };
-
- usb@210000 {
- compatible = "fsl-usb2-mph";
- reg = <0x210000 0x1000>;
- phy_type = "utmi";
- };
-
- usb@211000 {
- compatible = "fsl-usb2-dr";
- reg = <0x211000 0x1000>;
- phy_type = "utmi";
- };
-
- sata: sata@220000 {
- compatible = "fsl,pq-sata-v2";
- reg = <0x220000 0x1000>;
- interrupts = <68 0x2 0 0>;
- sata-offset = <0x1000>;
- sata-number = <2>;
- sata-fpdma = <0>;
- };
-
- esdhc: esdhc@114000 {
- compatible = "fsl,esdhc";
- reg = <0x114000 0x1000>;
- clock-frequency = <0>;
- };
-
- /include/ "qoriq-i2c-0.dtsi"
- /include/ "qoriq-i2c-1.dtsi"
- };
-
- pcie@ffe200000 {
- compatible = "fsl,pcie-p5040", "fsl,pcie-fsl-qoriq";
- reg = <0xf 0xfe200000 0x0 0x1000>; /* registers */
- law_trgt_if = <0>;
- #address-cells = <3>;
- #size-cells = <2>;
- device_type = "pci";
- bus-range = <0x0 0xff>;
- ranges = <0x01000000 0x0 0x00000000 0xf 0xf8000000 0x0 0x00010000 /* downstream I/O */
- 0x02000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000>; /* non-prefetchable memory */
- };
-
- pcie@ffe201000 {
- compatible = "fsl,pcie-p5040", "fsl,pcie-fsl-qoriq";
- reg = <0xf 0xfe201000 0x0 0x1000>; /* registers */
- law_trgt_if = <1>;
- #address-cells = <3>;
- #size-cells = <2>;
- device_type = "pci";
- bus-range = <0x0 0xff>;
- ranges = <0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000 /* downstream I/O */
- 0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000>; /* non-prefetchable memory */
- };
-
- pcie@ffe202000 {
- compatible = "fsl,pcie-p5040", "fsl,pcie-fsl-qoriq";
- reg = <0xf 0xfe202000 0x0 0x1000>; /* registers */
- law_trgt_if = <2>;
- #address-cells = <3>;
- #size-cells = <2>;
- device_type = "pci";
- bus-range = <0x0 0xff>;
- ranges = <0x01000000 0x0 0x00000000 0xf 0xf8020000 0x0 0x00010000 /* downstream I/O */
- 0x02000000 0x0 0xe0000000 0xc 0x40000000 0x0 0x20000000>; /* non-prefetchable memory */
- };
-};
diff --git a/arch/powerpc/dts/p5040ds.dts b/arch/powerpc/dts/p5040ds.dts
deleted file mode 100644
index c2ec765d3e4..00000000000
--- a/arch/powerpc/dts/p5040ds.dts
+++ /dev/null
@@ -1,281 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+ OR X11
-/*
- * P5040DS Device Tree Source
- *
- * Copyright 2012 - 2015 Freescale Semiconductor Inc.
- * Copyright 2019-2020 NXP
- */
-
-/include/ "p5040.dtsi"
-
-/ {
- model = "fsl,P5040DS";
- compatible = "fsl,P5040DS";
- #address-cells = <2>;
- #size-cells = <2>;
- interrupt-parent = <&mpic>;
-
- aliases{
- phy_sgmii_slot2_1c = &phy_sgmii_slot2_1c;
- phy_sgmii_slot2_1d = &phy_sgmii_slot2_1d;
- phy_sgmii_slot2_1e = &phy_sgmii_slot2_1e;
- phy_sgmii_slot2_1f = &phy_sgmii_slot2_1f;
- phy_sgmii_slot3_1c = &phy_sgmii_slot3_1c;
- phy_sgmii_slot3_1d = &phy_sgmii_slot3_1d;
- phy_sgmii_slot3_1e = &phy_sgmii_slot3_1e;
- phy_sgmii_slot3_1f = &phy_sgmii_slot3_1f;
- phy_sgmii_slot5_1c = &phy_sgmii_slot5_1c;
- phy_sgmii_slot5_1d = &phy_sgmii_slot5_1d;
- phy_sgmii_slot5_1e = &phy_sgmii_slot5_1e;
- phy_sgmii_slot5_1f = &phy_sgmii_slot5_1f;
- phy_sgmii_slot6_1c = &phy_sgmii_slot6_1c;
- phy_sgmii_slot6_1d = &phy_sgmii_slot6_1d;
- phy_sgmii_slot6_1e = &phy_sgmii_slot6_1e;
- phy_sgmii_slot6_1f = &phy_sgmii_slot6_1f;
- hydra_rg = &hydra_rg;
- hydra_sg_slot2 = &hydra_sg_slot2;
- hydra_sg_slot3 = &hydra_sg_slot3;
- hydra_sg_slot5 = &hydra_sg_slot5;
- hydra_sg_slot6 = &hydra_sg_slot6;
- hydra_xg_slot1 = &hydra_xg_slot1;
- hydra_xg_slot2 = &hydra_xg_slot2;
- spi0 = &espi0;
- };
-
- soc: soc@ffe000000 {
- ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
- reg = <0xf 0xfe000000 0 0x00001000>;
-
- fman@400000 {
- ethernet@e0000 {
- phy-connection-type = "sgmii";
- };
-
- ethernet@e2000 {
- phy-connection-type = "sgmii";
- };
-
- ethernet@e4000 {
- phy-connection-type = "sgmii";
- };
-
- ethernet@e6000 {
- phy-connection-type = "sgmii";
- };
-
- ethernet@e8000 {
- phy-handle = <&phy_rgmii_0>;
- phy-connection-type = "rgmii";
- };
-
- ethernet@f0000 {
- phy-handle = <&phy_xgmii_slot_2>;
- phy-connection-type = "xgmii";
- };
- };
-
- fman@500000 {
- ethernet@e0000 {
- phy-connection-type = "sgmii";
- };
-
- ethernet@e2000 {
- phy-connection-type = "sgmii";
- };
-
- ethernet@e4000 {
- phy-connection-type = "sgmii";
- };
-
- ethernet@e6000 {
- phy-connection-type = "sgmii";
- };
-
- ethernet@e8000 {
- phy-handle = <&phy_rgmii_1>;
- phy-connection-type = "rgmii";
- };
-
- ethernet@f0000 {
- phy-handle = <&phy_xgmii_slot_1>;
- phy-connection-type = "xgmii";
- };
- };
- };
-
- lbc: localbus@ffe124000 {
- reg = <0xf 0xfe124000 0 0x1000>;
- ranges = <0 0 0xf 0xe8000000 0x08000000
- 2 0 0xf 0xffa00000 0x00040000
- 3 0 0xf 0xffdf0000 0x00008000>;
-
- board-control@3,0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "fsl,p5040ds-fpga", "fsl,fpga-ngpixis";
- reg = <3 0 0x40>;
- ranges = <0 3 0 0x40>;
-
- mdio-mux-emi1 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "mdio-mux-mmioreg", "mdio-mux";
- mdio-parent-bus = <&mdio0>;
- reg = <9 1>;
- mux-mask = <0x78>;
-
- hydra_rg:rgmii-mdio@8 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <8>;
- status = "disabled";
-
- phy_rgmii_0: ethernet-phy@0 {
- reg = <0x0>;
- };
-
- phy_rgmii_1: ethernet-phy@1 {
- reg = <0x1>;
- };
- };
-
- hydra_sg_slot2: sgmii-mdio@28 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x28>;
- status = "disabled";
-
- phy_sgmii_slot2_1c: ethernet-phy@1c {
- reg = <0x1c>;
- };
-
- phy_sgmii_slot2_1d: ethernet-phy@1d {
- reg = <0x1d>;
- };
-
- phy_sgmii_slot2_1e: ethernet-phy@1e {
- reg = <0x1e>;
- };
-
- phy_sgmii_slot2_1f: ethernet-phy@1f {
- reg = <0x1f>;
- };
- };
-
- hydra_sg_slot3: sgmii-mdio@68 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x68>;
- status = "disabled";
-
- phy_sgmii_slot3_1c: ethernet-phy@1c {
- reg = <0x1c>;
- };
-
- phy_sgmii_slot3_1d: ethernet-phy@1d {
- reg = <0x1d>;
- };
-
- phy_sgmii_slot3_1e: ethernet-phy@1e {
- reg = <0x1e>;
- };
-
- phy_sgmii_slot3_1f: ethernet-phy@1f {
- reg = <0x1f>;
- };
- };
-
- hydra_sg_slot5: sgmii-mdio@38 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x38>;
- status = "disabled";
-
- phy_sgmii_slot5_1c: ethernet-phy@1c {
- reg = <0x1c>;
- };
-
- phy_sgmii_slot5_1d: ethernet-phy@1d {
- reg = <0x1d>;
- };
-
- phy_sgmii_slot5_1e: ethernet-phy@1e {
- reg = <0x1e>;
- };
-
- phy_sgmii_slot5_1f: ethernet-phy@1f {
- reg = <0x1f>;
- };
- };
- hydra_sg_slot6: sgmii-mdio@48 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x48>;
- status = "disabled";
-
- phy_sgmii_slot6_1c: ethernet-phy@1c {
- reg = <0x1c>;
- };
-
- phy_sgmii_slot6_1d: ethernet-phy@1d {
- reg = <0x1d>;
- };
-
- phy_sgmii_slot6_1e: ethernet-phy@1e {
- reg = <0x1e>;
- };
-
- phy_sgmii_slot6_1f: ethernet-phy@1f {
- reg = <0x1f>;
- };
- };
- };
-
- mdio-mux-emi2 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "mdio-mux-mmioreg", "mdio-mux";
- mdio-parent-bus = <&xmdio0>;
- reg = <9 1>;
- mux-mask = <0x06>;
-
- hydra_xg_slot1: hydra-xg-slot1@0 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0>;
- status = "disabled";
-
- phy_xgmii_slot_1: ethernet-phy@0 {
- compatible = "ethernet-phy-ieee802.3-c45";
- reg = <4>;
- };
- };
-
- hydra_xg_slot2: hydra-xg-slot2@2 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <2>;
-
- phy_xgmii_slot_2: ethernet-phy@4 {
- compatible = "ethernet-phy-ieee802.3-c45";
- reg = <0>;
- };
- };
- };
- };
- };
-};
-
-&espi0 {
- status = "okay";
- flash@0 {
- compatible = "jedec,spi-nor";
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0>;
- /* input clock */
- spi-max-frequency = <10000000>;
- };
-};
-
-/include/ "p5040si-post.dtsi"
diff --git a/arch/powerpc/dts/p5040si-post.dtsi b/arch/powerpc/dts/p5040si-post.dtsi
deleted file mode 100644
index fae3ed31a5d..00000000000
--- a/arch/powerpc/dts/p5040si-post.dtsi
+++ /dev/null
@@ -1,70 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-/*
- * P5040 Silicon/SoC Device Tree Source (post include)
- *
- * Copyright 2012 - 2015 Freescale Semiconductor Inc.
- * Copyright 2020 NXP
- *
- */
-
-&soc {
-
-/include/ "qoriq-clockgen1.dtsi"
-/include/ "qoriq-gpio-0.dtsi"
-/include/ "qoriq-sec5.2-0.dtsi"
-
-/* include used FMan blocks */
-/include/ "qoriq-fman-0.dtsi"
-/include/ "qoriq-fman-0-1g-0.dtsi"
-/include/ "qoriq-fman-0-1g-1.dtsi"
-/include/ "qoriq-fman-0-1g-2.dtsi"
-/include/ "qoriq-fman-0-1g-3.dtsi"
-/include/ "qoriq-fman-0-1g-4.dtsi"
-/include/ "qoriq-fman-0-10g-0.dtsi"
- fman@400000 {
- enet0: ethernet@e0000 {
- };
-
- enet1: ethernet@e2000 {
- };
-
- enet2: ethernet@e4000 {
- };
-
- enet3: ethernet@e6000 {
- };
-
- enet4: ethernet@e8000 {
- };
-
- enet5: ethernet@f0000 {
- };
- };
-
-/include/ "qoriq-fman-1.dtsi"
-/include/ "qoriq-fman-1-1g-0.dtsi"
-/include/ "qoriq-fman-1-1g-1.dtsi"
-/include/ "qoriq-fman-1-1g-2.dtsi"
-/include/ "qoriq-fman-1-1g-3.dtsi"
-/include/ "qoriq-fman-1-1g-4.dtsi"
-/include/ "qoriq-fman-1-10g-0.dtsi"
- fman@500000 {
- enet6: ethernet@e0000 {
- };
-
- enet7: ethernet@e2000 {
- };
-
- enet8: ethernet@e4000 {
- };
-
- enet9: ethernet@e6000 {
- };
-
- enet10: ethernet@e8000 {
- };
-
- enet11: ethernet@f0000 {
- };
- };
-};
diff --git a/board/nxp/common/Makefile b/board/nxp/common/Makefile
index 8fd6d6ce8c2..8817fcf027d 100644
--- a/board/nxp/common/Makefile
+++ b/board/nxp/common/Makefile
@@ -28,9 +28,6 @@ endif
obj-$(CONFIG_FSL_CADMUS) += cadmus.o
obj-$(CONFIG_FMAN_ENET) += fman.o
-ifndef CONFIG_XPL_BUILD
-obj-$(CONFIG_FSL_NGPIXIS) += ngpixis.o
-endif
obj-$(I2C_COMMON) += i2c_common.o
obj-$(CONFIG_FSL_USE_PCA9547_MUX) += i2c_mux.o
obj-$(CONFIG_$(PHASE_)VID) += vid.o
@@ -49,7 +46,6 @@ obj-$(CONFIG_DEEP_SLEEP) += mpc85xx_sleep.o
endif
-obj-$(CONFIG_TARGET_P5040DS) += ics307_clk.o
ifeq ($(CONFIG_$(PHASE_)POWER_LEGACY),y)
obj-$(CONFIG_POWER_PFUZE100) += pfuze.o
endif
@@ -65,7 +61,6 @@ obj-$(CONFIG_EMC2305) += emc2305.o
# deal with common files for P-series corenet based devices
obj-$(CONFIG_TARGET_P2041RDB) += p_corenet/
-obj-$(CONFIG_TARGET_P5040DS) += p_corenet/
obj-$(CONFIG_LAYERSCAPE_NS_ACCESS) += ns_access.o
diff --git a/board/nxp/common/ics307_clk.c b/board/nxp/common/ics307_clk.c
deleted file mode 100644
index af30faa0c5f..00000000000
--- a/board/nxp/common/ics307_clk.c
+++ /dev/null
@@ -1,149 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2010-2011 Freescale Semiconductor, Inc.
- */
-
-#include <config.h>
-#include <clock_legacy.h>
-#include <log.h>
-#include <asm/io.h>
-
-#include "ics307_clk.h"
-
-#if defined(CONFIG_FSL_NGPIXIS)
-#include "ngpixis.h"
-#define fpga_reg pixis
-#elif defined(CONFIG_FSL_QIXIS)
-#include "qixis.h"
-#define fpga_reg ((struct qixis *)QIXIS_BASE)
-#else
-#include "pixis.h"
-#define fpga_reg pixis
-#endif
-
-/* define for SYS CLK or CLK1Frequency */
-#define TTL 1
-#define CLK2 0
-#define CRYSTAL 0
-#define MAX_VDW (511 + 8)
-#define MAX_RDW (127 + 2)
-#define MIN_VDW (4 + 8)
-#define MIN_RDW (1 + 2)
-#define NUM_OD_SETTING 8
-/*
- * These defines cover the industrial temperature range part,
- * for commercial, change below to 400000 and 55000, respectively
- */
-#define MAX_VCO 360000
-#define MIN_VCO 60000
-
-/* decode S[0-2] to Output Divider (OD) */
-static u8 ics307_s_to_od[] = {
- 10, 2, 8, 4, 5, 7, 3, 6
-};
-
-/*
- * Find one solution to generate required frequency for SYSCLK
- * out_freq: KHz, required frequency to the SYSCLK
- * the result will be retuned with component RDW, VDW, OD, TTL,
- * CLK2 and crystal
- */
-unsigned long ics307_sysclk_calculator(unsigned long out_freq)
-{
- const unsigned long input_freq = CFG_ICS307_REFCLK_HZ;
- unsigned long vdw, rdw, odp, s_vdw = 0, s_rdw = 0, s_odp = 0, od;
- unsigned long tmp_out, diff, result = 0;
- int found = 0;
-
- for (odp = 0; odp < NUM_OD_SETTING; odp++) {
- od = ics307_s_to_od[odp];
- if (od * out_freq < MIN_VCO || od * out_freq > MAX_VCO)
- continue;
- for (rdw = MIN_RDW; rdw <= MAX_RDW; rdw++) {
- /* Calculate the VDW */
- vdw = out_freq * 1000 * od * rdw / (input_freq * 2);
- if (vdw > MAX_VDW)
- vdw = MAX_VDW;
- if (vdw < MIN_VDW)
- continue;
- /* Calculate the temp out frequency */
- tmp_out = input_freq * 2 * vdw / (rdw * od * 1000);
- diff = max(out_freq, tmp_out) - min(out_freq, tmp_out);
- /*
- * calculate the percent, the precision is 1/1000
- * If greater than 1/1000, continue
- * otherwise, we think the solution is we required
- */
- if (diff * 1000 / out_freq > 1)
- continue;
- else {
- s_vdw = vdw;
- s_rdw = rdw;
- s_odp = odp;
- found = 1;
- break;
- }
- }
- }
-
- if (found)
- result = (s_rdw - 2) | (s_vdw - 8) << 7 | s_odp << 16 |
- CLK2 << 19 | TTL << 21 | CRYSTAL << 22;
-
- debug("ICS307-02: RDW: %ld, VDW: %ld, OD: %d\n", s_rdw - 2, s_vdw - 8,
- ics307_s_to_od[s_odp]);
- return result;
-}
-
-/*
- * Calculate frequency being generated by ICS307-02 clock chip based upon
- * the control bytes being programmed into it.
- */
-static unsigned long ics307_clk_freq(u8 cw0, u8 cw1, u8 cw2)
-{
- const unsigned long input_freq = CFG_ICS307_REFCLK_HZ;
- unsigned long vdw = ((cw1 << 1) & 0x1FE) + ((cw2 >> 7) & 1);
- unsigned long rdw = cw2 & 0x7F;
- unsigned long od = ics307_s_to_od[cw0 & 0x7];
- unsigned long freq;
-
- /*
- * CLK1 Freq = Input Frequency * 2 * (VDW + 8) / ((RDW + 2) * OD)
- *
- * cw0: C1 C0 TTL F1 F0 S2 S1 S0
- * cw1: V8 V7 V6 V5 V4 V3 V2 V1
- * cw2: V0 R6 R5 R4 R3 R2 R1 R0
- *
- * R6:R0 = Reference Divider Word (RDW)
- * V8:V0 = VCO Divider Word (VDW)
- * S2:S0 = Output Divider Select (OD)
- * F1:F0 = Function of CLK2 Output
- * TTL = duty cycle
- * C1:C0 = internal load capacitance for cyrstal
- *
- */
-
- freq = input_freq * 2 * (vdw + 8) / ((rdw + 2) * od);
-
- debug("ICS307: CW[0-2]: %02X %02X %02X => %lu Hz\n", cw0, cw1, cw2,
- freq);
- return freq;
-}
-
-unsigned long get_board_sys_clk(void)
-{
- return ics307_clk_freq(
- in_8(&fpga_reg->sclk[0]),
- in_8(&fpga_reg->sclk[1]),
- in_8(&fpga_reg->sclk[2]));
-}
-
-#ifdef CONFIG_DYNAMIC_DDR_CLK_FREQ
-unsigned long get_board_ddr_clk(void)
-{
- return ics307_clk_freq(
- in_8(&fpga_reg->dclk[0]),
- in_8(&fpga_reg->dclk[1]),
- in_8(&fpga_reg->dclk[2]));
-}
-#endif
diff --git a/board/nxp/common/ics307_clk.h b/board/nxp/common/ics307_clk.h
deleted file mode 100644
index 163496930c8..00000000000
--- a/board/nxp/common/ics307_clk.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2010-2011 Freescale Semiconductor, Inc.
- */
-#ifndef __ICS_CLK_H_
-#define __ICS_CLK_H_ 1
-
-#ifndef __ASSEMBLY__
-
-extern unsigned long get_board_sys_clk(void);
-extern unsigned long ics307_sysclk_calculator(unsigned long out_freq);
-#endif
-
-#endif /* __ICS_CLK_H_ */
diff --git a/board/nxp/common/ngpixis.c b/board/nxp/common/ngpixis.c
deleted file mode 100644
index 74c345807e6..00000000000
--- a/board/nxp/common/ngpixis.c
+++ /dev/null
@@ -1,247 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/**
- * Copyright 2010-2011 Freescale Semiconductor
- * Author: Timur Tabi <timur@freescale.com>
- *
- * This file provides support for the ngPIXIS, a board-specific FPGA used on
- * some Freescale reference boards.
- *
- * A "switch" is black rectangular block on the motherboard. It contains
- * eight "bits". The ngPIXIS has a set of memory-mapped registers (SWx) that
- * shadow the actual physical switches. There is also another set of
- * registers (ENx) that tell the ngPIXIS which bits of SWx should actually be
- * used to override the values of the bits in the physical switches.
- *
- * The following macros need to be defined:
- *
- * PIXIS_BASE - The virtual address of the base of the PIXIS register map
- *
- * PIXIS_LBMAP_SWITCH - The switch number (i.e. the "x" in "SWx"). This value
- * is used in the PIXIS_SW() macro to determine which offset in
- * the PIXIS register map corresponds to the physical switch that controls
- * the boot bank.
- *
- * PIXIS_LBMAP_MASK - A bit mask the defines which bits in SWx to use.
- *
- * PIXIS_LBMAP_SHIFT - The shift value that corresponds to PIXIS_LBMAP_MASK.
- *
- * PIXIS_LBMAP_ALTBANK - The value to program into SWx to tell the ngPIXIS to
- * boot from the alternate bank.
- */
-
-#include <command.h>
-#include <asm/io.h>
-
-#include "ngpixis.h"
-
-static u8 __pixis_read(unsigned int reg)
-{
- void *p = (void *)PIXIS_BASE;
-
- return in_8(p + reg);
-}
-u8 pixis_read(unsigned int reg) __attribute__((weak, alias("__pixis_read")));
-
-static void __pixis_write(unsigned int reg, u8 value)
-{
- void *p = (void *)PIXIS_BASE;
-
- out_8(p + reg, value);
-}
-void pixis_write(unsigned int reg, u8 value)
- __attribute__((weak, alias("__pixis_write")));
-
-/*
- * Reset the board. This ignores the ENx registers.
- */
-void __pixis_reset(void)
-{
- PIXIS_WRITE(rst, 0);
-
- while (1);
-}
-void pixis_reset(void) __attribute__((weak, alias("__pixis_reset")));
-
-/*
- * Reset the board. Like pixis_reset(), but it honors the ENx registers.
- */
-void __pixis_bank_reset(void)
-{
- PIXIS_WRITE(vctl, 0);
- PIXIS_WRITE(vctl, 1);
-
- while (1);
-}
-void pixis_bank_reset(void) __attribute__((weak, alias("__pixis_bank_reset")));
-
-/**
- * Set the boot bank to the power-on default bank
- */
-void __clear_altbank(void)
-{
- u8 reg;
-
- /* Tell the ngPIXIS to use this the bits in the physical switch for the
- * boot bank value, instead of the SWx register. We need to be careful
- * only to set the bits in SWx that correspond to the boot bank.
- */
- reg = PIXIS_READ(s[PIXIS_LBMAP_SWITCH - 1].en);
- reg &= ~PIXIS_LBMAP_MASK;
- PIXIS_WRITE(s[PIXIS_LBMAP_SWITCH - 1].en, reg);
-}
-void clear_altbank(void) __attribute__((weak, alias("__clear_altbank")));
-
-/**
- * Set the boot bank to the alternate bank
- */
-void __set_altbank(void)
-{
- u8 reg;
-
- /* Program the alternate bank number into the SWx register.
- */
- reg = PIXIS_READ(s[PIXIS_LBMAP_SWITCH - 1].sw);
- reg = (reg & ~PIXIS_LBMAP_MASK) | PIXIS_LBMAP_ALTBANK;
- PIXIS_WRITE(s[PIXIS_LBMAP_SWITCH - 1].sw, reg);
-
- /* Tell the ngPIXIS to use this the bits in the SWx register for the
- * boot bank value, instead of the physical switch. We need to be
- * careful only to set the bits in SWx that correspond to the boot bank.
- */
- reg = PIXIS_READ(s[PIXIS_LBMAP_SWITCH - 1].en);
- reg |= PIXIS_LBMAP_MASK;
- PIXIS_WRITE(s[PIXIS_LBMAP_SWITCH - 1].en, reg);
-}
-void set_altbank(void) __attribute__((weak, alias("__set_altbank")));
-
-#ifdef DEBUG
-static void pixis_dump_regs(void)
-{
- unsigned int i;
-
- printf("id=%02x\n", PIXIS_READ(id));
- printf("arch=%02x\n", PIXIS_READ(arch));
- printf("scver=%02x\n", PIXIS_READ(scver));
- printf("csr=%02x\n", PIXIS_READ(csr));
- printf("rst=%02x\n", PIXIS_READ(rst));
- printf("aux=%02x\n", PIXIS_READ(aux));
- printf("spd=%02x\n", PIXIS_READ(spd));
- printf("brdcfg0=%02x\n", PIXIS_READ(brdcfg0));
- printf("brdcfg1=%02x\n", PIXIS_READ(brdcfg1));
- printf("addr=%02x\n", PIXIS_READ(addr));
- printf("data=%02x\n", PIXIS_READ(data));
- printf("led=%02x\n", PIXIS_READ(led));
- printf("vctl=%02x\n", PIXIS_READ(vctl));
- printf("vstat=%02x\n", PIXIS_READ(vstat));
- printf("vcfgen0=%02x\n", PIXIS_READ(vcfgen0));
- printf("ocmcsr=%02x\n", PIXIS_READ(ocmcsr));
- printf("ocmmsg=%02x\n", PIXIS_READ(ocmmsg));
- printf("gmdbg=%02x\n", PIXIS_READ(gmdbg));
- printf("sclk=%02x%02x%02x\n",
- PIXIS_READ(sclk[0]), PIXIS_READ(sclk[1]), PIXIS_READ(sclk[2]));
- printf("dclk=%02x%02x%02x\n",
- PIXIS_READ(dclk[0]), PIXIS_READ(dclk[1]), PIXIS_READ(dclk[2]));
- printf("watch=%02x\n", PIXIS_READ(watch));
-
- for (i = 0; i < 8; i++) {
- printf("SW%u=%02x/%02x ", i + 1,
- PIXIS_READ(s[i].sw), PIXIS_READ(s[i].en));
- }
- putc('\n');
-}
-#endif
-
-void pixis_sysclk_set(unsigned long sysclk)
-{
- unsigned long freq_word;
- u8 sclk0, sclk1, sclk2;
-
- freq_word = ics307_sysclk_calculator(sysclk);
- sclk2 = freq_word & 0xff;
- sclk1 = (freq_word >> 8) & 0xff;
- sclk0 = (freq_word >> 16) & 0xff;
-
- /* set SYSCLK enable bit */
- PIXIS_WRITE(vcfgen0, 0x01);
-
- /* SYSCLK to required frequency */
- PIXIS_WRITE(sclk[0], sclk0);
- PIXIS_WRITE(sclk[1], sclk1);
- PIXIS_WRITE(sclk[2], sclk2);
-}
-
-int pixis_reset_cmd(struct cmd_tbl *cmdtp, int flag, int argc,
- char *const argv[])
-{
- unsigned int i;
- unsigned long sysclk;
- char *p_altbank = NULL;
-#ifdef DEBUG
- char *p_dump = NULL;
-#endif
- char *unknown_param = NULL;
-
- /* No args is a simple reset request.
- */
- if (argc <= 1)
- pixis_reset();
-
- for (i = 1; i < argc; i++) {
- if (strcmp(argv[i], "altbank") == 0) {
- p_altbank = argv[i];
- continue;
- }
-
-#ifdef DEBUG
- if (strcmp(argv[i], "dump") == 0) {
- p_dump = argv[i];
- continue;
- }
-#endif
- if (strcmp(argv[i], "sysclk") == 0) {
- sysclk = simple_strtoul(argv[i + 1], NULL, 0);
- i += 1;
- pixis_sysclk_set(sysclk);
- continue;
- }
-
- unknown_param = argv[i];
- }
-
- if (unknown_param) {
- printf("Invalid option: %s\n", unknown_param);
- return 1;
- }
-
-#ifdef DEBUG
- if (p_dump) {
- pixis_dump_regs();
-
- /* 'dump' ignores other commands */
- return 0;
- }
-#endif
-
- if (p_altbank)
- set_altbank();
- else
- clear_altbank();
-
- pixis_bank_reset();
-
- /* Shouldn't be reached. */
- return 0;
-}
-
-U_BOOT_LONGHELP(pixis,
- "- hard reset to default bank\n"
- "pixis_reset altbank - reset to alternate bank\n"
-#ifdef DEBUG
- "pixis_reset dump - display the PIXIS registers\n"
-#endif
- "pixis_reset sysclk <SYSCLK_freq> - reset with SYSCLK frequency(KHz)\n");
-
-U_BOOT_CMD(
- pixis_reset, CONFIG_SYS_MAXARGS, 1, pixis_reset_cmd,
- "Reset the board using the FPGA sequencer", pixis_help_text
- );
diff --git a/board/nxp/common/ngpixis.h b/board/nxp/common/ngpixis.h
deleted file mode 100644
index 7a20ee015fa..00000000000
--- a/board/nxp/common/ngpixis.h
+++ /dev/null
@@ -1,60 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/**
- * Copyright 2010-2011 Freescale Semiconductor
- * Author: Timur Tabi <timur@freescale.com>
- *
- * This file provides support for the ngPIXIS, a board-specific FPGA used on
- * some Freescale reference boards.
- */
-
-/* ngPIXIS register set. Hopefully, this won't change too much over time.
- * Feel free to add board-specific #ifdefs where necessary.
- */
-typedef struct ngpixis {
- u8 id;
- u8 arch;
- u8 scver;
- u8 csr;
- u8 rst;
- u8 serclk;
- u8 aux;
- u8 spd;
- u8 brdcfg0;
- u8 brdcfg1; /* On some boards, this register is called 'dma' */
- u8 addr;
- u8 brdcfg2;
- u8 gpiodir;
- u8 data;
- u8 led;
- u8 tag;
- u8 vctl;
- u8 vstat;
- u8 vcfgen0;
- u8 res4;
- u8 ocmcsr;
- u8 ocmmsg;
- u8 gmdbg;
- u8 res5[2];
- u8 sclk[3];
- u8 dclk[3];
- u8 watch;
- struct {
- u8 sw;
- u8 en;
- } s[9]; /* s[0]..s[7] is SW1..SW8, and s[8] is SW11 */
-} __attribute__ ((packed)) ngpixis_t;
-
-/* Pointer to the PIXIS register set */
-#define pixis ((ngpixis_t *)PIXIS_BASE)
-
-/* The PIXIS SW register that corresponds to board switch X, where x >= 1 */
-#define PIXIS_SW(x) (pixis->s[(x) - 1].sw)
-
-/* The PIXIS EN register that corresponds to board switch X, where x >= 1 */
-#define PIXIS_EN(x) (pixis->s[(x) - 1].en)
-
-u8 pixis_read(unsigned int reg);
-void pixis_write(unsigned int reg, u8 value);
-
-#define PIXIS_READ(reg) pixis_read(offsetof(ngpixis_t, reg))
-#define PIXIS_WRITE(reg, value) pixis_write(offsetof(ngpixis_t, reg), value)
--
2.47.3
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH 07/26] board: powerpc: Remove T1042D4RDB support
2026-10-09 19:36 [PATCH 00/26] powerpc: drop EOL boards and SoCs, take over maintenance Bradley Morgan
` (5 preceding siblings ...)
2026-10-09 19:36 ` [PATCH 06/26] board: powerpc: Remove P5040DS support Bradley Morgan
@ 2026-10-09 19:36 ` Bradley Morgan
2026-10-09 19:36 ` [PATCH 08/26] powerpc: mpc85xx: Remove P3041 support Bradley Morgan
` (18 subsequent siblings)
25 siblings, 0 replies; 31+ messages in thread
From: Bradley Morgan @ 2026-10-09 19:36 UTC (permalink / raw)
To: Tom Rini, u-boot
Cc: Bradley Morgan, Marek Behún, Marek Mojík,
NXP i . MX U-Boot Team, Alexey Charkov, Anshul Dalal,
Daniel Golle, Fabio Estevam, Gaurav Jain, Ilias Apalodimas,
Jaehoon Chung, James Hilliard, Jerome Forissier, Johan Jonker,
Lukasz Majewski, Marek Vasut, Mario Six, Michael Walle,
Michal Simek, Neil Armstrong, Peng Fan, Pengpeng Hou,
Priyanka Jain, Quentin Schulz, Simon Glass, Stefano Babic,
Tanmay Kathpalia, Torsten Rupp, Vincent Jardin, Weijie Gao
The T1042D4RDB-PA is obsolete and no longer manufactured. Remove the target and its board support.
Signed-off-by: Bradley Morgan <brads@mainlining.org>
---
arch/powerpc/cpu/mpc85xx/Kconfig | 10 -
arch/powerpc/dts/Makefile | 1 -
arch/powerpc/dts/t1042d4rdb-u-boot.dtsi | 12 -
arch/powerpc/dts/t1042d4rdb.dts | 89 -----
arch/powerpc/dts/t104x.dtsi | 148 --------
arch/powerpc/include/asm/fsl_secure_boot.h | 1 -
board/nxp/t104xrdb/Kconfig | 12 -
board/nxp/t104xrdb/MAINTAINERS | 13 -
board/nxp/t104xrdb/Makefile | 13 -
board/nxp/t104xrdb/README | 386 --------------------
board/nxp/t104xrdb/cpld.c | 116 ------
board/nxp/t104xrdb/cpld.h | 45 ---
board/nxp/t104xrdb/ddr.c | 148 --------
board/nxp/t104xrdb/ddr.h | 56 ---
board/nxp/t104xrdb/law.c | 31 --
board/nxp/t104xrdb/spl.c | 131 -------
board/nxp/t104xrdb/t1040_nand_rcw.cfg | 7 -
board/nxp/t104xrdb/t1040_sd_rcw.cfg | 7 -
board/nxp/t104xrdb/t1040_spi_rcw.cfg | 7 -
board/nxp/t104xrdb/t1040d4_nand_rcw.cfg | 7 -
board/nxp/t104xrdb/t1040d4_sd_rcw.cfg | 7 -
board/nxp/t104xrdb/t1040d4_spi_rcw.cfg | 7 -
board/nxp/t104xrdb/t1042_nand_rcw.cfg | 7 -
board/nxp/t104xrdb/t1042_pi_nand_rcw.cfg | 7 -
board/nxp/t104xrdb/t1042_pi_sd_rcw.cfg | 7 -
board/nxp/t104xrdb/t1042_pi_spi_rcw.cfg | 7 -
board/nxp/t104xrdb/t1042_sd_rcw.cfg | 7 -
board/nxp/t104xrdb/t1042_spi_rcw.cfg | 7 -
board/nxp/t104xrdb/t1042d4_nand_rcw.cfg | 7 -
board/nxp/t104xrdb/t1042d4_sd_rcw.cfg | 7 -
board/nxp/t104xrdb/t1042d4_spi_rcw.cfg | 7 -
board/nxp/t104xrdb/t104x_pbi.cfg | 36 --
board/nxp/t104xrdb/t104x_pbi_sb.cfg | 38 --
board/nxp/t104xrdb/t104xrdb.c | 159 ---------
board/nxp/t104xrdb/t104xrdb.h | 11 -
board/nxp/t104xrdb/tlb.c | 132 -------
configs/T1042D4RDB_NAND_defconfig | 144 --------
configs/T1042D4RDB_SDCARD_defconfig | 138 -------
configs/T1042D4RDB_SPIFLASH_defconfig | 141 --------
configs/T1042D4RDB_defconfig | 114 ------
include/configs/T104xRDB.h | 397 ---------------------
41 files changed, 2627 deletions(-)
delete mode 100644 arch/powerpc/dts/t1042d4rdb-u-boot.dtsi
delete mode 100644 arch/powerpc/dts/t1042d4rdb.dts
delete mode 100644 arch/powerpc/dts/t104x.dtsi
delete mode 100644 board/nxp/t104xrdb/Kconfig
delete mode 100644 board/nxp/t104xrdb/MAINTAINERS
delete mode 100644 board/nxp/t104xrdb/Makefile
delete mode 100644 board/nxp/t104xrdb/README
delete mode 100644 board/nxp/t104xrdb/cpld.c
delete mode 100644 board/nxp/t104xrdb/cpld.h
delete mode 100644 board/nxp/t104xrdb/ddr.c
delete mode 100644 board/nxp/t104xrdb/ddr.h
delete mode 100644 board/nxp/t104xrdb/law.c
delete mode 100644 board/nxp/t104xrdb/spl.c
delete mode 100644 board/nxp/t104xrdb/t1040_nand_rcw.cfg
delete mode 100644 board/nxp/t104xrdb/t1040_sd_rcw.cfg
delete mode 100644 board/nxp/t104xrdb/t1040_spi_rcw.cfg
delete mode 100644 board/nxp/t104xrdb/t1040d4_nand_rcw.cfg
delete mode 100644 board/nxp/t104xrdb/t1040d4_sd_rcw.cfg
delete mode 100644 board/nxp/t104xrdb/t1040d4_spi_rcw.cfg
delete mode 100644 board/nxp/t104xrdb/t1042_nand_rcw.cfg
delete mode 100644 board/nxp/t104xrdb/t1042_pi_nand_rcw.cfg
delete mode 100644 board/nxp/t104xrdb/t1042_pi_sd_rcw.cfg
delete mode 100644 board/nxp/t104xrdb/t1042_pi_spi_rcw.cfg
delete mode 100644 board/nxp/t104xrdb/t1042_sd_rcw.cfg
delete mode 100644 board/nxp/t104xrdb/t1042_spi_rcw.cfg
delete mode 100644 board/nxp/t104xrdb/t1042d4_nand_rcw.cfg
delete mode 100644 board/nxp/t104xrdb/t1042d4_sd_rcw.cfg
delete mode 100644 board/nxp/t104xrdb/t1042d4_spi_rcw.cfg
delete mode 100644 board/nxp/t104xrdb/t104x_pbi.cfg
delete mode 100644 board/nxp/t104xrdb/t104x_pbi_sb.cfg
delete mode 100644 board/nxp/t104xrdb/t104xrdb.c
delete mode 100644 board/nxp/t104xrdb/t104xrdb.h
delete mode 100644 board/nxp/t104xrdb/tlb.c
delete mode 100644 configs/T1042D4RDB_NAND_defconfig
delete mode 100644 configs/T1042D4RDB_SDCARD_defconfig
delete mode 100644 configs/T1042D4RDB_SPIFLASH_defconfig
delete mode 100644 configs/T1042D4RDB_defconfig
delete mode 100644 include/configs/T104xRDB.h
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index 8a37191bea0..7fee93862c7 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -167,15 +167,6 @@ config TARGET_T1024RDB
imply CMD_EEPROM
imply PANIC_HANG
-config TARGET_T1042D4RDB
- bool "Support T1042D4RDB"
- select ARCH_T1042
- select BOARD_LATE_INIT if CHAIN_OF_TRUST
- select SUPPORT_SPL
- select PHYS_64BIT
- select SYS_L3_SIZE_256KB
- imply PANIC_HANG
-
config TARGET_T2080QDS
bool "Support T2080QDS"
select ARCH_T2080
@@ -1473,7 +1464,6 @@ source "board/nxp/p1010rdb/Kconfig"
source "board/nxp/p1_p2_rdb_pc/Kconfig"
source "board/nxp/p2041rdb/Kconfig"
source "board/nxp/t102xrdb/Kconfig"
-source "board/nxp/t104xrdb/Kconfig"
source "board/nxp/t208xqds/Kconfig"
source "board/nxp/t208xrdb/Kconfig"
source "board/nxp/t4rdb/Kconfig"
diff --git a/arch/powerpc/dts/Makefile b/arch/powerpc/dts/Makefile
index 3f5473b80af..4bc6e9085f4 100644
--- a/arch/powerpc/dts/Makefile
+++ b/arch/powerpc/dts/Makefile
@@ -13,7 +13,6 @@ dtb-$(CONFIG_TARGET_P1020RDB_PC) += p1020rdb-pc.dtb p1020rdb-pc_36b.dtb
dtb-$(CONFIG_TARGET_P1020RDB_PD) += p1020rdb-pd.dtb
dtb-$(CONFIG_TARGET_SOCRATES) += socrates.dtb
dtb-$(CONFIG_TARGET_T1024RDB) += t1024rdb.dtb
-dtb-$(CONFIG_TARGET_T1042D4RDB) += t1042d4rdb.dtb
dtb-$(CONFIG_TARGET_T2080QDS) += t2080qds.dtb
dtb-$(CONFIG_TARGET_T2080RDB) += t2080rdb.dtb
dtb-$(CONFIG_TARGET_T4240RDB) += t4240rdb.dtb
diff --git a/arch/powerpc/dts/t1042d4rdb-u-boot.dtsi b/arch/powerpc/dts/t1042d4rdb-u-boot.dtsi
deleted file mode 100644
index b50b922aeb2..00000000000
--- a/arch/powerpc/dts/t1042d4rdb-u-boot.dtsi
+++ /dev/null
@@ -1,12 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/* Copyright 2023 NXP */
-
-&serial0 {
- bootph-all;
-};
-
-&serial1 {
- bootph-all;
-};
-
-#include "u-boot.dtsi"
diff --git a/arch/powerpc/dts/t1042d4rdb.dts b/arch/powerpc/dts/t1042d4rdb.dts
deleted file mode 100644
index 0230d3ba675..00000000000
--- a/arch/powerpc/dts/t1042d4rdb.dts
+++ /dev/null
@@ -1,89 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+ OR X11
-/*
- * T1042D4RDB Device Tree Source
- *
- * Copyright 2013 - 2015 Freescale Semiconductor Inc.
- * Copyright 2019-2023 NXP
- */
-
-/include/ "t104x.dtsi"
-
-/ {
- model = "fsl,T1042D4RDB";
- compatible = "fsl,T1042D4RDB";
- #address-cells = <2>;
- #size-cells = <2>;
- interrupt-parent = <&mpic>;
-
- aliases {
- spi0 = &espi0;
- serial0 = &serial0;
- serial1 = &serial1;
- serial2 = &serial2;
- serial3 = &serial3;
- };
-};
-
-&soc {
- fman0: fman@400000 {
- ethernet@e0000 {
- phy-handle = <&phy_sgmii_0>;
- phy-connection-type = "sgmii";
- };
-
- ethernet@e2000 {
- phy-handle = <&phy_sgmii_1>;
- phy-connection-type = "sgmii";
- };
-
- ethernet@e4000 {
- phy-handle = <&phy_sgmii_2>;
- phy-connection-type = "sgmii";
- };
-
- ethernet@e6000 {
- phy-handle = <&phy_rgmii_0>;
- phy-connection-type = "rgmii";
- };
-
- ethernet@e8000 {
- phy-handle = <&phy_rgmii_1>;
- phy-connection-type = "rgmii";
- };
-
- mdio0: mdio@fc000 {
- phy_sgmii_0: ethernet-phy@2 {
- reg = <0x02>;
- };
-
- phy_sgmii_1: ethernet-phy@3 {
- reg = <0x03>;
- };
-
- phy_sgmii_2: ethernet-phy@1 {
- reg = <0x01>;
- };
-
- phy_rgmii_0: ethernet-phy@4 {
- reg = <0x04>;
- };
-
- phy_rgmii_1: ethernet-phy@5 {
- reg = <0x05>;
- };
- };
- };
-};
-
-&espi0 {
- status = "okay";
- flash@0 {
- compatible = "jedec,spi-nor";
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0>;
- spi-max-frequency = <10000000>; /* input clock */
- };
-};
-
-/include/ "t1042si-post.dtsi"
diff --git a/arch/powerpc/dts/t104x.dtsi b/arch/powerpc/dts/t104x.dtsi
deleted file mode 100644
index 2c7e5b47185..00000000000
--- a/arch/powerpc/dts/t104x.dtsi
+++ /dev/null
@@ -1,148 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+ OR X11
-/*
- * T104X Silicon/SoC Device Tree Source (pre include)
- *
- * Copyright 2013 Freescale Semiconductor Inc.
- * Copyright 2019-2020 NXP
- */
-
-/dts-v1/;
-
-/include/ "e5500_power_isa.dtsi"
-
-/ {
- #address-cells = <2>;
- #size-cells = <2>;
- interrupt-parent = <&mpic>;
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu0: PowerPC,e5500@0 {
- device_type = "cpu";
- reg = <0>;
- #cooling-cells = <2>;
- };
- cpu1: PowerPC,e5500@1 {
- device_type = "cpu";
- reg = <1>;
- #cooling-cells = <2>;
- };
- cpu2: PowerPC,e5500@2 {
- device_type = "cpu";
- reg = <2>;
- #cooling-cells = <2>;
- };
- cpu3: PowerPC,e5500@3 {
- device_type = "cpu";
- reg = <3>;
- #cooling-cells = <2>;
- };
- };
-
- soc: soc@ffe000000 {
- ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
- reg = <0xf 0xfe000000 0 0x00001000>;
- #address-cells = <1>;
- #size-cells = <1>;
- device_type = "soc";
- compatible = "simple-bus";
-
- mpic: pic@40000 {
- interrupt-controller;
- #address-cells = <0>;
- #interrupt-cells = <4>;
- reg = <0x40000 0x40000>;
- compatible = "fsl,mpic", "chrp,open-pic";
- device_type = "open-pic";
- clock-frequency = <0x0>;
- };
-
- espi0: spi@110000 {
- compatible = "fsl,mpc8536-espi";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x110000 0x1000>;
- fsl,espi-num-chipselects = <4>;
- status = "disabled";
- };
-
- usb0@210000 {
- compatible = "fsl-usb2-mph";
- reg = <0x210000 0x1000>;
- phy_type = "utmi";
- };
-
- usb1@211000 {
- compatible = "fsl-usb2-dr";
- reg = <0x211000 0x1000>;
- phy_type = "utmi";
- };
-
- sata: sata@220000 {
- compatible = "fsl,pq-sata-v2";
- reg = <0x220000 0x1000>;
- interrupts = <68 0x2 0 0>;
- sata-offset = <0x1000>;
- sata-number = <2>;
- sata-fpdma = <0>;
- };
-
- esdhc: esdhc@114000 {
- compatible = "fsl,esdhc";
- reg = <0x114000 0x1000>;
- clock-frequency = <0>;
- };
- /include/ "qoriq-i2c-0.dtsi"
- /include/ "qoriq-i2c-1.dtsi"
- };
-
- pcie@ffe240000 {
- compatible = "fsl,pcie-t104x", "fsl,pcie-fsl-qoriq";
- reg = <0xf 0xfe240000 0x0 0x1000>; /* registers */
- law_trgt_if = <0>;
- #address-cells = <3>;
- #size-cells = <2>;
- device_type = "pci";
- bus-range = <0x0 0xff>;
- ranges = <0x01000000 0x0 0x00000000 0xf 0xf8000000 0x0 0x00010000 /* downstream I/O */
- 0x02000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x10000000>; /* non-prefetchable memory */
- };
-
- pcie@ffe250000 {
- compatible = "fsl,pcie-t104x", "fsl,pcie-fsl-qoriq";
- reg = <0xf 0xfe250000 0x0 0x1000>; /* registers */
- law_trgt_if = <1>;
- #address-cells = <3>;
- #size-cells = <2>;
- device_type = "pci";
- bus-range = <0x0 0xff>;
- ranges = <0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000 /* downstream I/O */
- 0x02000000 0x0 0xe0000000 0xc 0x10000000 0x0 0x10000000>; /* non-prefetchable memory */
- };
-
- pcie@ffe260000 {
- compatible = "fsl,pcie-t104x", "fsl,pcie-fsl-qoriq";
- reg = <0xf 0xfe260000 0x0 0x1000>; /* registers */
- law_trgt_if = <2>;
- #address-cells = <3>;
- #size-cells = <2>;
- device_type = "pci";
- bus-range = <0x0 0xff>;
- ranges = <0x01000000 0x0 0x00000000 0xf 0xf8020000 0x0 0x00010000 /* downstream I/O */
- 0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x10000000>; /* non-prefetchable memory */
- };
-
- pcie@ffe270000 {
- compatible = "fsl,pcie-t104x", "fsl,pcie-fsl-qoriq";
- reg = <0xf 0xfe270000 0x0 0x1000>; /* registers */
- law_trgt_if = <3>;
- #address-cells = <3>;
- #size-cells = <2>;
- device_type = "pci";
- bus-range = <0x0 0xff>;
- ranges = <0x01000000 0x0 0x00000000 0xf 0xf8030000 0x0 0x00010000 /* downstream I/O */
- 0x02000000 0x0 0xe0000000 0xc 0x30000000 0x0 0x10000000>; /* non-prefetchable memory */
- };
-};
diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h b/arch/powerpc/include/asm/fsl_secure_boot.h
index f12830984c6..10f8b0fcd09 100644
--- a/arch/powerpc/include/asm/fsl_secure_boot.h
+++ b/arch/powerpc/include/asm/fsl_secure_boot.h
@@ -17,7 +17,6 @@
#if defined(CONFIG_TARGET_T2080QDS) || \
defined(CONFIG_TARGET_T2080RDB) || \
- defined(CONFIG_TARGET_T1042D4RDB) || \
defined(CONFIG_ARCH_T1024)
#undef CFG_SYS_INIT_L3_ADDR
#define CFG_SYS_INIT_L3_ADDR 0xbff00000
diff --git a/board/nxp/t104xrdb/Kconfig b/board/nxp/t104xrdb/Kconfig
deleted file mode 100644
index fb26b7c9256..00000000000
--- a/board/nxp/t104xrdb/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_T1042D4RDB
-
-config SYS_BOARD
- default "t104xrdb"
-
-config SYS_VENDOR
- default "nxp"
-
-config SYS_CONFIG_NAME
- default "T104xRDB"
-
-endif
diff --git a/board/nxp/t104xrdb/MAINTAINERS b/board/nxp/t104xrdb/MAINTAINERS
deleted file mode 100644
index d0b5709df81..00000000000
--- a/board/nxp/t104xrdb/MAINTAINERS
+++ /dev/null
@@ -1,13 +0,0 @@
-T104XRDB BOARD
-M: Priyanka Jain <priyanka.jain@nxp.com>
-S: Maintained
-F: board/nxp/t104xrdb/
-F: include/configs/T104xRDB.h
-F: configs/T1042D4RDB_defconfig
-F: configs/T1042D4RDB_NAND_defconfig
-F: configs/T1042D4RDB_SPIFLASH_defconfig
-
-T1040RDB_SDCARD BOARD
-M: Priyanka Jain <priyanka.jain@nxp.com>
-S: Maintained
-F: configs/T1042D4RDB_SDCARD_defconfig
diff --git a/board/nxp/t104xrdb/Makefile b/board/nxp/t104xrdb/Makefile
deleted file mode 100644
index cee574aabb9..00000000000
--- a/board/nxp/t104xrdb/Makefile
+++ /dev/null
@@ -1,13 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright 2013 Freescale Semiconductor, Inc.
-
-ifdef CONFIG_XPL_BUILD
-obj-y += spl.o
-else
-obj-y += t104xrdb.o
-obj-y += cpld.o
-endif
-obj-y += ddr.o
-obj-y += law.o
-obj-y += tlb.o
diff --git a/board/nxp/t104xrdb/README b/board/nxp/t104xrdb/README
deleted file mode 100644
index b852f72998d..00000000000
--- a/board/nxp/t104xrdb/README
+++ /dev/null
@@ -1,386 +0,0 @@
-Overview
---------
-The T1040RDB is a Freescale reference board that hosts the T1040 SoC
-(and variants). Variants inclued T1042 presonality of T1040, in which
-case T1040RDB can also be called T1042RDB.
-
-The T1042RDB is a Freescale reference board that hosts the T1042 SoC
-(and variants). The board is similar to T1040RDB, T1040 is a reduced
-personality of T1040 SoC without Integrated 8-port Gigabit(L2 Switch).
-
-The T1042RDB_PI is a Freescale reference board that hosts the T1042 SoC.
-(a personality of T1040 SoC). The board is similar to T1040RDB but is
-designed specially with low power features targeted for Printing Image Market.
-
-The T1040D4RDB is a Freescale reference board that hosts the T1040 SoC.
-The board is re-designed T1040RDB board with following changes :
- - Support of DDR4 memory and some enhancements
-
-The T1042D4RDB is a Freescale reference board that hosts the T1042 SoC.
-The board is re-designed T1040RDB board with following changes :
- - Support of DDR4 memory
- - Support for 0x86 serdes protocol which can support following interfaces
- - 2 RGMII's on DTSEC4, DTSEC5
- - 3 SGMII on DTSEC1, DTSEC2 & DTSEC3
-
-Basic difference's among T1040RDB, T1042RDB_PI, T1042RDB
--------------------------------------------------------------------------
-Board Si Protocol Targeted Market
--------------------------------------------------------------------------
-T1040RDB T1040 0x66 Networking
-T1040RDB T1042 0x86 Networking
-T1042RDB_PI T1042 0x06 Printing & Imaging
-T1040D4RDB T1040 0x66 Networking
-T1042D4RDB T1042 0x86 Networking
-
-
-T1040 SoC Overview
-------------------
-The QorIQ T1040/T1042 processor support four integrated 64-bit e5500 PA
-processor cores with high-performance data path acceleration architecture
-and network peripheral interfaces required for networking & telecommunications.
-
-The T1040/T1042 SoC includes the following function and features:
-
- - Four e5500 cores, each with a private 256 KB L2 cache
- - 256 KB shared L3 CoreNet platform cache (CPC)
- - Interconnect CoreNet platform
- - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving
- support
- - Data Path Acceleration Architecture (DPAA) incorporating acceleration
- for the following functions:
- - Packet parsing, classification, and distribution
- - Queue management for scheduling, packet sequencing, and congestion
- management
- - Cryptography Acceleration (SEC 5.0)
- - RegEx Pattern Matching Acceleration (PME 2.2)
- - IEEE Std 1588 support
- - Hardware buffer management for buffer allocation and deallocation
- - Ethernet interfaces
- - Integrated 8-port Gigabit Ethernet switch (T1040 only)
- - Four 1 Gbps Ethernet controllers
- - Two RGMII interfaces or one RGMII and one MII interfaces
- - High speed peripheral interfaces
- - Four PCI Express 2.0 controllers running at up to 5 GHz
- - Two SATA controllers supporting 1.5 and 3.0 Gb/s operation
- - Upto two QSGMII interface
- - Upto six SGMII interface supporting 1000 Mbps
- - One SGMII interface supporting upto 2500 Mbps
- - Additional peripheral interfaces
- - Two USB 2.0 controllers with integrated PHY
- - SD/eSDHC/eMMC
- - eSPI controller
- - Four I2C controllers
- - Four UARTs
- - Four GPIO controllers
- - Integrated flash controller (IFC)
- - LCD and HDMI interface (DIU) with 12 bit dual data rate
- - TDM interface
- - Multicore programmable interrupt controller (PIC)
- - Two 8-channel DMA engines
- - Single source clocking implementation
- - Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB)
-
-T1040 SoC Personalities
--------------------------
-T1022 Personality:
-T1022 is a reduced personality of T1040 with less core/clusters.
-
-T1042 Personality:
-T1042 is a reduced personality of T1040 without Integrated 8-port Gigabit
-Ethernet switch. Rest of the blocks are same as T1040
-
-
-T1040RDB board Overview
--------------------------
- - SERDES Connections, 8 lanes information:
- 1: None
- 2: SGMII
- 3: QSGMII
- 4: QSGMII
- 5: PCIe1 x1 slot
- 6: mini PCIe connector
- 7: mini PCIe connector
- 8: SATA connector
- - DDR Controller
- - Supports rates of up to 1600 MHz data-rate
- - Supports one DDR3LP UDIMM/RDIMMs, of single-, dual- or quad-rank types.
- - IFC/Local Bus
- - NAND flash: 1GB 8-bit NAND flash
- - NOR: 128MB 16-bit NOR Flash
- - Ethernet
- - Two on-board RGMII 10/100/1G ethernet ports.
- - CPLD
- - Clocks
- - System and DDR clock (SYSCLK, “DDRCLK”)
- - SERDES clocks
- - Power Supplies
- - USB
- - Supports two USB 2.0 ports with integrated PHYs
- - Two type A ports with 5V@1.5A per port.
- - SDHC
- - SDHC/SDXC connector
- - SPI
- - On-board 64MB SPI flash
- - Other IO
- - Two Serial ports
- - Four I2C ports
-
-T1042RDB_PI board Overview
--------------------------
- - SERDES Connections, 8 lanes information:
- 1, 2, 3, 4 : PCIe x4 slot
- 5: mini PCIe connector
- 6: mini PCIe connector
- 7: NA
- 8: SATA connector
- - DDR Controller
- - Supports rates of up to 1600 MHz data-rate
- - Supports one DDR3LP UDIMM/RDIMMs, of single-, dual- or quad-rank types.
- - IFC/Local Bus
- - NAND flash: 1GB 8-bit NAND flash
- - NOR: 128MB 16-bit NOR Flash
- - Ethernet
- - Two on-board RGMII 10/100/1G ethernet ports.
- - CPLD
- - Clocks
- - System and DDR clock (SYSCLK, “DDRCLK”)
- - SERDES clocks
- - Video
- - DIU supports video at up to 1280x1024x32bpp
- - Power Supplies
- - USB
- - Supports two USB 2.0 ports with integrated PHYs
- - Two type A ports with 5V@1.5A per port.
- - SDHC
- - SDHC/SDXC connector
- - SPI
- - On-board 64MB SPI flash
- - Other IO
- - Two Serial ports
- - Four I2C ports
-
-Memory map
------------
-The addresses in brackets are physical addresses.
-
-Start Address End Address Description Size
-0xF_FFDF_0000 0xF_FFDF_0FFF IFC - CPLD 4KB
-0xF_FF80_0000 0xF_FF80_FFFF IFC - NAND Flash 64KB
-0xF_FE00_0000 0xF_FEFF_FFFF CCSRBAR 16MB
-0xF_F803_0000 0xF_F803_FFFF PCI Express 4 I/O Space 64KB
-0xF_F802_0000 0xF_F802_FFFF PCI Express 3 I/O Space 64KB
-0xF_F801_0000 0xF_F801_FFFF PCI Express 2 I/O Space 64KB
-0xF_F800_0000 0xF_F800_FFFF PCI Express 1 I/O Space 64KB
-0xF_F600_0000 0xF_F7FF_FFFF Queue manager software portal 32MB
-0xF_F400_0000 0xF_F5FF_FFFF Buffer manager software portal 32MB
-0xF_E800_0000 0xF_EFFF_FFFF IFC - NOR Flash 128MB
-0xF_0000_0000 0xF_003F_FFFF DCSR 4MB
-0xC_3000_0000 0xC_3FFF_FFFF PCI Express 4 Mem Space 256MB
-0xC_2000_0000 0xC_2FFF_FFFF PCI Express 3 Mem Space 256MB
-0xC_1000_0000 0xC_1FFF_FFFF PCI Express 2 Mem Space 256MB
-0xC_0000_0000 0xC_0FFF_FFFF PCI Express 1 Mem Space 256MB
-0x0_0000_0000 0x0_ffff_ffff DDR 2GB
-
-
-NOR Flash memory Map
----------------------
- Start End Definition Size
-0xEFF40000 0xEFFFFFFF U-Boot (current bank) 768KB
-0xEFF20000 0xEFF3FFFF U-Boot env (current bank) 128KB
-0xEFF00000 0xEFF1FFFF FMAN Ucode (current bank) 128KB
-0xED300000 0xEFEFFFFF rootfs (alt bank) 44MB
-0xEC800000 0xEC8FFFFF Hardware device tree (alt bank) 1MB
-0xEC020000 0xEC7FFFFF Linux.uImage (alt bank) 7MB + 875KB
-0xEC000000 0xEC01FFFF RCW (alt bank) 128KB
-0xEBF40000 0xEBFFFFFF U-Boot (alt bank) 768KB
-0xEBF20000 0xEBF3FFFF U-Boot env (alt bank) 128KB
-0xEBF00000 0xEBF1FFFF FMAN ucode (alt bank) 128KB
-0xE9300000 0xEBEFFFFF rootfs (current bank) 44MB
-0xE8800000 0xE88FFFFF Hardware device tree (cur bank) 11MB + 512KB
-0xE8020000 0xE86FFFFF Linux.uImage (current bank) 7MB + 875KB
-0xE8000000 0xE801FFFF RCW (current bank) 128KB
-
-
-Various Software configurations/environment variables/commands
---------------------------------------------------------------
-The below commands apply to the board
-
-1. U-Boot environment variable hwconfig
- The default hwconfig is:
- hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=cs0_cs1;usb1:
- dr_mode=host,phy_type=utmi
- Note: For USB gadget set "dr_mode=peripheral"
-
-2. FMAN Ucode versions
- fsl_fman_ucode_t1040.bin
-
-3. Switching to alternate bank
- Commands for switching to alternate bank.
-
- 1. To change from vbank0 to vbank4
- => cpld reset altbank (it will boot using vbank4)
-
- 2.To change from vbank4 to vbank0
- => cpld reset (it will boot using vbank0)
-
-NAND boot with 2 Stage boot loader
-----------------------------------
-PBL initialise the internal SRAM and copy SPL(160KB) in SRAM.
-SPL further initialise DDR using SPD and environment variables and copy
-U-Boot(768 KB) from flash to DDR.
-Finally SPL transer control to U-Boot for futher booting.
-
-SPL has following features:
- - Executes within 256K
- - No relocation required
-
- Run time view of SPL framework during boot :-
- -----------------------------------------------
- Area | Address |
------------------------------------------------
- Secure boot | 0xFFFC0000 (32KB) |
- headers | |
- -----------------------------------------------
- GD, BD | 0xFFFC8000 (4KB) |
- -----------------------------------------------
- ENV | 0xFFFC9000 (8KB) |
- -----------------------------------------------
- HEAP | 0xFFFCB000 (30KB) |
- -----------------------------------------------
- STACK | 0xFFFD8000 (22KB) |
- -----------------------------------------------
- U-Boot SPL | 0xFFFD8000 (160KB) |
- -----------------------------------------------
-
-NAND Flash memory Map on T104xRDB
-------------------------------------------
- Start End Definition Size
-0x000000 0x0FFFFF U-Boot 1MB
-0x180000 0x19FFFF U-Boot env 128KB
-0x280000 0x29FFFF FMAN Ucode 128KB
-0x380000 0x39FFFF QE Firmware 128KB
-
-SD Card memory Map on T104xRDB
-------------------------------------------
- Block #blocks Definition Size
-0x008 2048 U-Boot 1MB
-0x800 0024 U-Boot env 8KB
-0x820 0256 FMAN Ucode 128KB
-0x920 0256 QE Firmware 128KB
-
-SPI Flash memory Map on T104xRDB
-------------------------------------------
- Start End Definition Size
-0x000000 0x0FFFFF U-Boot 1MB
-0x100000 0x101FFF U-Boot env 8KB
-0x110000 0x12FFFF FMAN Ucode 128KB
-0x130000 0x14FFFF QE Firmware 128KB
-
-Please note QE Firmware is only valid for T1040RDB
-
-
-Switch Settings for T104xRDB boards: (ON is 0, OFF is 1)
-==========================================================
-NOR boot SW setting:
-SW1: 00010011
-SW2: 10111011
-SW3: 11100001
-
-NAND boot SW setting:
-SW1: 10001000
-SW2: 00111011
-SW3: 11110001
-
-SPI boot SW setting:
-SW1: 00100010
-SW2: 10111011
-SW3: 11100001
-
-SD boot SW setting:
-SW1: 00100000
-SW2: 00111011
-SW3: 11100001
-
-Switch Settings for T104xD4RDB boards: (ON is 0, OFF is 1)
-=============================================================
-NOR boot SW setting:
-SW1: 00010011
-SW2: 10111001
-SW3: 11100001
-
-NAND boot SW setting:
-SW1: 10001000
-SW2: 00111001
-SW3: 11110001
-
-SPI boot SW setting:
-SW1: 00100010
-SW2: 10111001
-SW3: 11100001
-
-SD boot SW setting:
-SW1: 00100000
-SW2: 00111001
-SW3: 11100001
-
-PBL-based image generation
-==========================
-Changes only the required register bit in in PBI commands.
-
-Provides reference code which might needs some
-modification as per requirement.
-example:
-By default PBI_SRC=14 (which is for IFC-NAND/NOR) in rcw.cfg file
-which needs to be changed for SPI and SD.
-
-For SD-boot
-==============
-1. Set RCW[192:195], PBI_SRC bits as 6 in RCW file (t1040d4_rcw.cfg type files)
-
-example:
- RCW file: board/nxp/t104xrdb/t1040d4_rcw.cfg
-
-Change
-66000002 40000002 ec027000 01000000
-to
-66000002 40000002 6c027000 01000000
-
-2. SD does not support flush so remove flush from pbl, make changes in
- tools/pblimage.c file, Update value of pbl_end_cmd[0] = 0x09138000
- with 0x091380c0
-
-For SPI-boot
-==============
-1. Set RCW[192:195], PBI_SRC bits as 5 in RCW file (t1040d4_rcw.cfg type files)
-
-example:
- RCW file: board/nxp/t104xrdb/t1040d4_rcw.cfg
-
-Change
-66000002 40000002 ec027000 01000000
-to
-66000002 40000002 5c027000 01000000
-
-2. SPI does not support flush so remove flush from pbl, make changes in
- tools/pblimage.c file, Update value of pbl_end_cmd[0] = 0x09138000
- with 0x091380c0
-
-Device tree support and how to enable it for different configs
---------------------------------------------------------------
-Device tree support is available for t1042d4rdb for below mentioned boot,
-1. NOR Boot
-2. NAND Boot
-3. SD Boot
-4. SPIFLASH Boot
-
-To enable device tree support for other boot, below configs need to be
-enabled in relative defconfig file,
-1. CONFIG_DEFAULT_DEVICE_TREE="t1042d4rdb" (Change default device tree name if required)
-2. CONFIG_OF_CONTROL
-3. CONFIG_MPC85XX_HAVE_RESET_VECTOR if reset vector is located at
- CFG_RESET_VECTOR_ADDRESS - 0xffc
-
-If device tree support is enabled in defconfig,
-1. use 'u-boot.bin' for NOR boot.
-2. use 'u-boot-with-spl-pbl.bin' for other boot.
diff --git a/board/nxp/t104xrdb/cpld.c b/board/nxp/t104xrdb/cpld.c
deleted file mode 100644
index 038e40e2fae..00000000000
--- a/board/nxp/t104xrdb/cpld.c
+++ /dev/null
@@ -1,116 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/**
- * Copyright 2014 Freescale Semiconductor
- *
- * This file provides support for the board-specific CPLD used on some Freescale
- * reference boards.
- *
- * The following macros need to be defined:
- *
- * CFG_SYS_CPLD_BASE-The virtual address of the base of the CPLD register map
- */
-
-#include <config.h>
-#include <command.h>
-#include <linux/string.h>
-#include <asm/io.h>
-
-#include "cpld.h"
-
-u8 cpld_read(unsigned int reg)
-{
- void *p = (void *)CFG_SYS_CPLD_BASE;
-
- return in_8(p + reg);
-}
-
-void cpld_write(unsigned int reg, u8 value)
-{
- void *p = (void *)CFG_SYS_CPLD_BASE;
-
- out_8(p + reg, value);
-}
-
-/**
- * Set the boot bank to the alternate bank
- */
-void cpld_set_altbank(void)
-{
- u8 reg = CPLD_READ(flash_ctl_status);
-
- reg = (reg & ~CPLD_BANK_SEL_MASK) | CPLD_LBMAP_ALTBANK;
-
- CPLD_WRITE(flash_ctl_status, reg);
- CPLD_WRITE(reset_ctl1, CPLD_LBMAP_RESET);
-}
-
-/**
- * Set the boot bank to the default bank
- */
-void cpld_set_defbank(void)
-{
- u8 reg = CPLD_READ(flash_ctl_status);
-
- reg = (reg & ~CPLD_BANK_SEL_MASK) | CPLD_LBMAP_DFLTBANK;
-
- CPLD_WRITE(flash_ctl_status, reg);
- CPLD_WRITE(reset_ctl1, CPLD_LBMAP_RESET);
-}
-
-#ifdef DEBUG
-static void cpld_dump_regs(void)
-{
- printf("cpld_ver = 0x%02x\n", CPLD_READ(cpld_ver));
- printf("cpld_ver_sub = 0x%02x\n", CPLD_READ(cpld_ver_sub));
- printf("hw_ver = 0x%02x\n", CPLD_READ(hw_ver));
- printf("sw_ver = 0x%02x\n", CPLD_READ(sw_ver));
- printf("reset_ctl1 = 0x%02x\n", CPLD_READ(reset_ctl1));
- printf("reset_ctl2 = 0x%02x\n", CPLD_READ(reset_ctl2));
- printf("int_status = 0x%02x\n", CPLD_READ(int_status));
- printf("flash_ctl_status = 0x%02x\n", CPLD_READ(flash_ctl_status));
- printf("fan_ctl_status = 0x%02x\n", CPLD_READ(fan_ctl_status));
-#if defined(CONFIG_TARGET_T1040D4D4RDB) || defined(CONFIG_TARGET_T1042D4RDB)
- printf("int_mask = 0x%02x\n", CPLD_READ(int_mask));
-#else
- printf("led_ctl_status = 0x%02x\n", CPLD_READ(led_ctl_status));
-#endif
- printf("sfp_ctl_status = 0x%02x\n", CPLD_READ(sfp_ctl_status));
- printf("misc_ctl_status = 0x%02x\n", CPLD_READ(misc_ctl_status));
- printf("boot_override = 0x%02x\n", CPLD_READ(boot_override));
- printf("boot_config1 = 0x%02x\n", CPLD_READ(boot_config1));
- printf("boot_config2 = 0x%02x\n", CPLD_READ(boot_config2));
- putc('\n');
-}
-#endif
-
-int do_cpld(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
-{
- int rc = 0;
-
- if (argc <= 1)
- return cmd_usage(cmdtp);
-
- if (strcmp(argv[1], "reset") == 0) {
- if (strcmp(argv[2], "altbank") == 0)
- cpld_set_altbank();
- else
- cpld_set_defbank();
-#ifdef DEBUG
- } else if (strcmp(argv[1], "dump") == 0) {
- cpld_dump_regs();
-#endif
- } else
- rc = cmd_usage(cmdtp);
-
- return rc;
-}
-
-U_BOOT_CMD(
- cpld, CONFIG_SYS_MAXARGS, 1, do_cpld,
- "Reset the board or alternate bank",
- "reset - hard reset to default bank\n"
- "cpld reset altbank - reset to alternate bank\n"
-#ifdef DEBUG
- "cpld dump - display the CPLD registers\n"
-#endif
- );
diff --git a/board/nxp/t104xrdb/cpld.h b/board/nxp/t104xrdb/cpld.h
deleted file mode 100644
index 0384202fbcb..00000000000
--- a/board/nxp/t104xrdb/cpld.h
+++ /dev/null
@@ -1,45 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/**
- * Copyright 2013 Freescale Semiconductor
- *
- * This file provides support for the ngPIXIS, a board-specific FPGA used on
- * some Freescale reference boards.
- */
-
-/*
- * CPLD register set. Feel free to add board-specific #ifdefs where necessary.
- */
-struct cpld_data {
- u8 cpld_ver; /* 0x00 - CPLD Major Revision Register */
- u8 cpld_ver_sub; /* 0x01 - CPLD Minor Revision Register */
- u8 hw_ver; /* 0x02 - Hardware Revision Register */
- u8 sw_ver; /* 0x03 - Software Revision register */
- u8 res0[12]; /* 0x04 - 0x0F - not used */
- u8 reset_ctl1; /* 0x10 - Reset control Register1 */
- u8 reset_ctl2; /* 0x11 - Reset control Register2 */
- u8 int_status; /* 0x12 - Interrupt status Register */
- u8 flash_ctl_status; /* 0x13 - Flash control and status register */
- u8 fan_ctl_status; /* 0x14 - Fan control and status register */
-#if defined(CONFIG_TARGET_T1042D4RDB)
- u8 int_mask; /* 0x15 - Interrupt mask Register */
-#else
- u8 led_ctl_status; /* 0x15 - LED control and status register */
-#endif
- u8 sfp_ctl_status; /* 0x16 - SFP control and status register */
- u8 misc_ctl_status; /* 0x17 - Miscellanies ctrl & status register*/
- u8 boot_override; /* 0x18 - Boot override register */
- u8 boot_config1; /* 0x19 - Boot config override register*/
- u8 boot_config2; /* 0x1A - Boot config override register*/
-};
-
-/* Pointer to the CPLD register set */
-
-u8 cpld_read(unsigned int reg);
-void cpld_write(unsigned int reg, u8 value);
-
-#define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg))
-#define CPLD_WRITE(reg, value)\
- cpld_write(offsetof(struct cpld_data, reg), value)
-#define MISC_CTL_SG_SEL 0x80
-#define MISC_CTL_AURORA_SEL 0x02
-#define MISC_MUX_QE_TDM 0xc0
diff --git a/board/nxp/t104xrdb/ddr.c b/board/nxp/t104xrdb/ddr.c
deleted file mode 100644
index 6c066480b46..00000000000
--- a/board/nxp/t104xrdb/ddr.c
+++ /dev/null
@@ -1,148 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- * Copyright 2021 NXP
- */
-
-#include <config.h>
-#include <i2c.h>
-#include <hwconfig.h>
-#include <init.h>
-#include <log.h>
-#include <asm/global_data.h>
-#include <asm/mmu.h>
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-#include <asm/fsl_law.h>
-#include <asm/mpc85xx_gpio.h>
-#include <linux/delay.h>
-#include "ddr.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void fsl_ddr_board_options(memctl_options_t *popts,
- dimm_params_t *pdimm,
- unsigned int ctrl_num)
-{
- const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
- ulong ddr_freq;
-
- if (ctrl_num > 1) {
- printf("Not supported controller number %d\n", ctrl_num);
- return;
- }
- if (!pdimm->n_ranks)
- return;
-
- pbsp = udimms[0];
-
- /* Get clk_adjust according to the board ddr
- * freqency and n_banks specified in board_specific_parameters table.
- */
- ddr_freq = get_ddr_freq(0) / 1000000;
- while (pbsp->datarate_mhz_high) {
- if (pbsp->n_ranks == pdimm->n_ranks &&
- (pdimm->rank_density >> 30) >= pbsp->rank_gb) {
- if (ddr_freq <= pbsp->datarate_mhz_high) {
- popts->clk_adjust = pbsp->clk_adjust;
- popts->wrlvl_start = pbsp->wrlvl_start;
- popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
- popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
- goto found;
- }
- pbsp_highest = pbsp;
- }
- pbsp++;
- }
-
- if (pbsp_highest) {
- printf("Error: board specific timing not found\n");
- printf("for data rate %lu MT/s\n", ddr_freq);
- printf("Trying to use the highest speed (%u) parameters\n",
- pbsp_highest->datarate_mhz_high);
- popts->clk_adjust = pbsp_highest->clk_adjust;
- popts->wrlvl_start = pbsp_highest->wrlvl_start;
- popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
- popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
- } else {
- panic("DIMM is not supported by this board");
- }
-found:
- debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
- "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, "
- "wrlvl_ctrl_3 0x%x\n",
- pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
- pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
- pbsp->wrlvl_ctl_3);
-
- /*
- * Factors to consider for half-strength driver enable:
- * - number of DIMMs installed
- */
-#ifdef CONFIG_SYS_FSL_DDR4
- popts->half_strength_driver_enable = 1;
- /* optimize cpo for erratum A-009942 */
- popts->cpo_sample = 0x59;
-#else
- popts->cpo_sample = 0x54;
- popts->half_strength_driver_enable = 0;
-#endif
- /*
- * Write leveling override
- */
- popts->wrlvl_override = 1;
- popts->wrlvl_sample = 0xf;
-
- /*
- * rtt and rtt_wr override
- */
- popts->rtt_override = 0;
-
- /* Enable ZQ calibration */
- popts->zq_en = 1;
-
- /* DHC_EN =1, ODT = 75 Ohm */
-#ifdef CONFIG_SYS_FSL_DDR4
- popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_120OHM);
- popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_120OHM) |
- DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */
-#else
- popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
- popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
-#endif
-}
-
-#if defined(CONFIG_DEEP_SLEEP)
-void board_mem_sleep_setup(void)
-{
- void __iomem *cpld_base = (void *)CFG_SYS_CPLD_BASE;
-
- /* does not provide HW signals for power management */
- clrbits_8(cpld_base + 0x17, 0x40);
- /* Disable MCKE isolation */
- gpio_set_value(2, 0);
- udelay(1);
-}
-#endif
-
-int dram_init(void)
-{
- phys_size_t dram_size;
-
-#if defined(CONFIG_XPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
- puts("Initializing....using SPD\n");
- dram_size = fsl_ddr_sdram();
-#else
- dram_size = fsl_ddr_sdram_size();
-#endif
- dram_size = setup_ddr_tlbs(dram_size / 0x100000);
- dram_size *= 0x100000;
-
-#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_XPL_BUILD)
- fsl_dp_resume();
-#endif
-
- gd->ram_size = dram_size;
-
- return 0;
-}
diff --git a/board/nxp/t104xrdb/ddr.h b/board/nxp/t104xrdb/ddr.h
deleted file mode 100644
index f9d667f6174..00000000000
--- a/board/nxp/t104xrdb/ddr.h
+++ /dev/null
@@ -1,56 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-#ifndef __DDR_H__
-#define __DDR_H__
-struct board_specific_parameters {
- u32 n_ranks;
- u32 datarate_mhz_high;
- u32 rank_gb;
- u32 clk_adjust;
- u32 wrlvl_start;
- u32 wrlvl_ctl_2;
- u32 wrlvl_ctl_3;
-};
-
-/*
- * These tables contain all valid speeds we want to override with board
- * specific parameters. datarate_mhz_high values need to be in ascending order
- * for each n_ranks group.
- */
-
-static const struct board_specific_parameters udimm0[] = {
- /*
- * memory controller 0
- * num| hi| rank| clk| wrlvl | wrlvl
- * ranks| mhz| GB |adjst| start | ctl2
- */
-#ifdef CONFIG_SYS_FSL_DDR4
- {2, 1600, 4, 8, 6, 0x07090A0c, 0x0e0f100a},
- {1, 1600, 4, 8, 5, 0x0607080B, 0x0C0C0D09},
-#elif defined(CONFIG_SYS_FSL_DDR3)
- {2, 833, 4, 8, 6, 0x06060607, 0x08080807},
- {2, 833, 0, 8, 6, 0x06060607, 0x08080807},
- {2, 1350, 4, 8, 7, 0x0708080A, 0x0A0B0C09},
- {2, 1350, 0, 8, 7, 0x0708080A, 0x0A0B0C09},
- {2, 1666, 4, 8, 7, 0x0808090B, 0x0C0D0E0A},
- {2, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A},
- {1, 833, 4, 8, 6, 0x06060607, 0x08080807},
- {1, 833, 0, 8, 6, 0x06060607, 0x08080807},
- {1, 1350, 4, 8, 7, 0x0708080A, 0x0A0B0C09},
- {1, 1350, 0, 8, 7, 0x0708080A, 0x0A0B0C09},
- {1, 1666, 4, 8, 7, 0x0808090B, 0x0C0D0E0A},
- {1, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A},
-#else
-#error DDR type not defined
-#endif
- {}
-};
-
-#endif
-
-static const struct board_specific_parameters *udimms[] = {
- udimm0,
-};
diff --git a/board/nxp/t104xrdb/law.c b/board/nxp/t104xrdb/law.c
deleted file mode 100644
index d34641c2397..00000000000
--- a/board/nxp/t104xrdb/law.c
+++ /dev/null
@@ -1,31 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-#include <config.h>
-#include <asm/fsl_law.h>
-#include <asm/mmu.h>
-
-struct law_entry law_table[] = {
-#ifdef CONFIG_MTD_NOR_FLASH
- SET_LAW(CFG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC),
-#endif
-#ifdef CFG_SYS_BMAN_MEM_PHYS
- SET_LAW(CFG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN),
-#endif
-#ifdef CFG_SYS_QMAN_MEM_PHYS
- SET_LAW(CFG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
-#endif
-#ifdef CFG_SYS_CPLD_BASE_PHYS
- SET_LAW(CFG_SYS_CPLD_BASE_PHYS, LAW_SIZE_128K, LAW_TRGT_IF_IFC),
-#endif
-#ifdef CFG_SYS_DCSRBAR_PHYS
- SET_LAW(CFG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR),
-#endif
-#ifdef CFG_SYS_NAND_BASE_PHYS
- SET_LAW(CFG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
-#endif
-};
-
-int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/nxp/t104xrdb/spl.c b/board/nxp/t104xrdb/spl.c
deleted file mode 100644
index e02a1f95d4c..00000000000
--- a/board/nxp/t104xrdb/spl.c
+++ /dev/null
@@ -1,131 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/* Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-#include <config.h>
-#include <clock_legacy.h>
-#include <console.h>
-#include <env_internal.h>
-#include <init.h>
-#include <malloc.h>
-#include <ns16550.h>
-#include <nand.h>
-#include <i2c.h>
-#include <mmc.h>
-#include <fsl_esdhc.h>
-#include <spi_flash.h>
-#include <asm/global_data.h>
-#include "../common/sleep.h"
-#include "../common/spl.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-phys_size_t get_effective_memsize(void)
-{
- return CONFIG_SYS_L3_SIZE;
-}
-
-#define FSL_CORENET_CCSR_PORSR1_RCW_MASK 0xFF800000
-void board_init_f(ulong bootflag)
-{
- u32 plat_ratio, sys_clk, uart_clk;
-#if defined(CONFIG_SPL_NAND_BOOT) && defined(CONFIG_A008044_WORKAROUND)
- u32 porsr1, pinctl;
- u32 svr = get_svr();
-#endif
- ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR;
-
-#if defined(CONFIG_SPL_NAND_BOOT) && defined(CONFIG_A008044_WORKAROUND)
- if (IS_SVR_REV(svr, 1, 0)) {
- /*
- * There is T1040 SoC issue where NOR, FPGA are inaccessible
- * during NAND boot because IFC signals > IFC_AD7 are not
- * enabled. This workaround changes RCW source to make all
- * signals enabled.
- */
- porsr1 = in_be32(&gur->porsr1);
- pinctl = ((porsr1 & ~(FSL_CORENET_CCSR_PORSR1_RCW_MASK))
- | 0x24800000);
- out_be32((unsigned int *)(CFG_SYS_DCSRBAR + 0x20000),
- pinctl);
- }
-#endif
-
- /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
- memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));
-
- /* Update GD pointer */
- gd = (gd_t *)(CONFIG_SPL_GD_ADDR);
-
-#ifdef CONFIG_DEEP_SLEEP
- /* disable the console if boot from deep sleep */
- if (is_warm_boot())
- fsl_dp_disable_console();
-#endif
- /* compiler optimization barrier needed for GCC >= 3.4 */
- __asm__ __volatile__("" : : : "memory");
-
- console_init_f();
-
- /* initialize selected port with appropriate baud rate */
- sys_clk = get_board_sys_clk();
- plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
- uart_clk = sys_clk * plat_ratio / 2;
-
- ns16550_init((struct ns16550 *)CFG_SYS_NS16550_COM1,
- uart_clk / 16 / CONFIG_BAUDRATE);
-
- relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0);
-}
-
-void board_init_r(gd_t *gd, ulong dest_addr)
-{
- struct bd_info *bd;
-
- bd = (struct bd_info *)(gd + sizeof(gd_t));
- memset(bd, 0, sizeof(struct bd_info));
- gd->bd = bd;
-
- arch_cpu_init();
- get_clocks();
- mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
- CONFIG_SPL_RELOC_MALLOC_SIZE);
- gd->flags |= GD_FLG_FULL_MALLOC_INIT;
-
-#ifdef CONFIG_SPL_MMC_BOOT
- mmc_initialize(bd);
-#endif
-
- /* relocate environment function pointers etc. */
-#if defined(CONFIG_ENV_IS_IN_NAND) || defined(CONFIG_ENV_IS_IN_MMC) || \
- defined(CONFIG_ENV_IS_IN_SPI_FLASH)
-#ifdef CONFIG_SPL_NAND_BOOT
- nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
- (uchar *)SPL_ENV_ADDR);
-#endif
-#ifdef CONFIG_SPL_MMC_BOOT
- mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
- (uchar *)SPL_ENV_ADDR);
-#endif
-#ifdef CONFIG_SPL_SPI_BOOT
- fsl_spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
- (uchar *)SPL_ENV_ADDR);
-#endif
- gd->env_addr = (ulong)(SPL_ENV_ADDR);
- gd->env_valid = ENV_VALID;
-#endif
-
- i2c_init_all();
-
- puts("\n\n");
-
- dram_init();
-
-#ifdef CONFIG_SPL_MMC_BOOT
- mmc_boot();
-#elif defined(CONFIG_SPL_SPI_BOOT)
- fsl_spi_boot();
-#elif defined(CONFIG_SPL_NAND_BOOT)
- nand_boot();
-#endif
-}
diff --git a/board/nxp/t104xrdb/t1040_nand_rcw.cfg b/board/nxp/t104xrdb/t1040_nand_rcw.cfg
deleted file mode 100644
index 3300c184a1a..00000000000
--- a/board/nxp/t104xrdb/t1040_nand_rcw.cfg
+++ /dev/null
@@ -1,7 +0,0 @@
-#PBL preamble and RCW header
-aa55aa55 010e0100
-# serdes protocol 0x66
-0c18000e 0e000000 00000000 00000000
-66000002 80000002 e8106000 01000000
-00000000 00000000 00000000 00032810
-00000000 0342500f 00000000 00000000
diff --git a/board/nxp/t104xrdb/t1040_sd_rcw.cfg b/board/nxp/t104xrdb/t1040_sd_rcw.cfg
deleted file mode 100644
index fd3e8c5bbf5..00000000000
--- a/board/nxp/t104xrdb/t1040_sd_rcw.cfg
+++ /dev/null
@@ -1,7 +0,0 @@
-#PBL preamble and RCW header
-aa55aa55 010e0100
-# serdes protocol 0x66
-0c18000e 0e000000 00000000 00000000
-66000002 80000002 68106000 01000000
-00000000 00000000 00000000 00032810
-00000000 0342500f 00000000 00000000
diff --git a/board/nxp/t104xrdb/t1040_spi_rcw.cfg b/board/nxp/t104xrdb/t1040_spi_rcw.cfg
deleted file mode 100644
index fccde5e01fe..00000000000
--- a/board/nxp/t104xrdb/t1040_spi_rcw.cfg
+++ /dev/null
@@ -1,7 +0,0 @@
-#PBL preamble and RCW header
-aa55aa55 010e0100
-# serdes protocol 0x66
-0c18000e 0e000000 00000000 00000000
-66000002 80000002 58106000 01000000
-00000000 00000000 00000000 00032810
-00000000 0342500f 00000000 00000000
diff --git a/board/nxp/t104xrdb/t1040d4_nand_rcw.cfg b/board/nxp/t104xrdb/t1040d4_nand_rcw.cfg
deleted file mode 100644
index c1034b3dfa3..00000000000
--- a/board/nxp/t104xrdb/t1040d4_nand_rcw.cfg
+++ /dev/null
@@ -1,7 +0,0 @@
-#PBL preamble and RCW header
-aa55aa55 010e0100
-# serdes protocol 0x66
-0c18000e 0e000000 00000000 00000000
-66000002 40000002 ec027000 01000000
-00000000 00000000 00000000 00030810
-00000000 0342580f 00000000 00000000
diff --git a/board/nxp/t104xrdb/t1040d4_sd_rcw.cfg b/board/nxp/t104xrdb/t1040d4_sd_rcw.cfg
deleted file mode 100644
index e6f7585bb02..00000000000
--- a/board/nxp/t104xrdb/t1040d4_sd_rcw.cfg
+++ /dev/null
@@ -1,7 +0,0 @@
-#PBL preamble and RCW header
-aa55aa55 010e0100
-# serdes protocol 0x66
-0c18000e 0e000000 00000000 00000000
-66000002 40000002 6c027000 01000000
-00000000 00000000 00000000 00030810
-00000000 0342580f 00000000 00000000
diff --git a/board/nxp/t104xrdb/t1040d4_spi_rcw.cfg b/board/nxp/t104xrdb/t1040d4_spi_rcw.cfg
deleted file mode 100644
index cde862dff5c..00000000000
--- a/board/nxp/t104xrdb/t1040d4_spi_rcw.cfg
+++ /dev/null
@@ -1,7 +0,0 @@
-#PBL preamble and RCW header
-aa55aa55 010e0100
-# serdes protocol 0x66
-0c18000e 0e000000 00000000 00000000
-66000002 40000002 5c027000 01000000
-00000000 00000000 00000000 00030810
-00000000 0342580f 00000000 00000000
diff --git a/board/nxp/t104xrdb/t1042_nand_rcw.cfg b/board/nxp/t104xrdb/t1042_nand_rcw.cfg
deleted file mode 100644
index db4d52f397d..00000000000
--- a/board/nxp/t104xrdb/t1042_nand_rcw.cfg
+++ /dev/null
@@ -1,7 +0,0 @@
-#PBL preamble and RCW header
-aa55aa55 010e0100
-# serdes protocol 0x86
-0c18000e 0e000000 00000000 00000000
-86000002 80000002 ec027000 01000000
-00000000 00000000 00000000 00032810
-00000000 0342500f 00000000 00000000
diff --git a/board/nxp/t104xrdb/t1042_pi_nand_rcw.cfg b/board/nxp/t104xrdb/t1042_pi_nand_rcw.cfg
deleted file mode 100644
index 57de89ad0e7..00000000000
--- a/board/nxp/t104xrdb/t1042_pi_nand_rcw.cfg
+++ /dev/null
@@ -1,7 +0,0 @@
-#PBL preamble and RCW header
-aa55aa55 010e0100
-# serdes protocol 0x06
-0c18000e 0e000000 00000000 00000000
-06000002 00400002 e8106000 01000000
-00000000 00000000 00000000 00030810
-00000000 01fe0a06 00000000 00000000
diff --git a/board/nxp/t104xrdb/t1042_pi_sd_rcw.cfg b/board/nxp/t104xrdb/t1042_pi_sd_rcw.cfg
deleted file mode 100644
index bbce9a36930..00000000000
--- a/board/nxp/t104xrdb/t1042_pi_sd_rcw.cfg
+++ /dev/null
@@ -1,7 +0,0 @@
-#PBL preamble and RCW header
-aa55aa55 010e0100
-# serdes protocol 0x06
-0c18000e 0e000000 00000000 00000000
-06000002 00400002 68106000 01000000
-00000000 00000000 00000000 00030810
-00000000 01fe0a06 00000000 00000000
diff --git a/board/nxp/t104xrdb/t1042_pi_spi_rcw.cfg b/board/nxp/t104xrdb/t1042_pi_spi_rcw.cfg
deleted file mode 100644
index b1d8b4c65af..00000000000
--- a/board/nxp/t104xrdb/t1042_pi_spi_rcw.cfg
+++ /dev/null
@@ -1,7 +0,0 @@
-#PBL preamble and RCW header
-aa55aa55 010e0100
-# serdes protocol 0x06
-0c18000e 0e000000 00000000 00000000
-06000002 00400002 58106000 01000000
-00000000 00000000 00000000 00030810
-00000000 01fe0a06 00000000 00000000
diff --git a/board/nxp/t104xrdb/t1042_sd_rcw.cfg b/board/nxp/t104xrdb/t1042_sd_rcw.cfg
deleted file mode 100644
index d77bf189b22..00000000000
--- a/board/nxp/t104xrdb/t1042_sd_rcw.cfg
+++ /dev/null
@@ -1,7 +0,0 @@
-#PBL preamble and RCW header
-aa55aa55 010e0100
-# serdes protocol 0x86
-0c18000e 0e000000 00000000 00000000
-86000002 80000002 6c027000 01000000
-00000000 00000000 00000000 00032810
-00000000 0342500f 00000000 00000000
diff --git a/board/nxp/t104xrdb/t1042_spi_rcw.cfg b/board/nxp/t104xrdb/t1042_spi_rcw.cfg
deleted file mode 100644
index e8a3ad12804..00000000000
--- a/board/nxp/t104xrdb/t1042_spi_rcw.cfg
+++ /dev/null
@@ -1,7 +0,0 @@
-#PBL preamble and RCW header
-aa55aa55 010e0100
-# serdes protocol 0x86
-0c18000e 0e000000 00000000 00000000
-86000002 80000002 5c027000 01000000
-00000000 00000000 00000000 00032810
-00000000 0342500f 00000000 00000000
diff --git a/board/nxp/t104xrdb/t1042d4_nand_rcw.cfg b/board/nxp/t104xrdb/t1042d4_nand_rcw.cfg
deleted file mode 100644
index 9e0ee2795f8..00000000000
--- a/board/nxp/t104xrdb/t1042d4_nand_rcw.cfg
+++ /dev/null
@@ -1,7 +0,0 @@
-#PBL preamble and RCW header
-aa55aa55 010e0100
-# serdes protocol 0x86
-0c18000e 0e000000 00000000 00000000
-86000002 40000002 ec027000 01000000
-00000000 00000000 00000000 00030810
-00000000 0342500f 00000000 00000000
diff --git a/board/nxp/t104xrdb/t1042d4_sd_rcw.cfg b/board/nxp/t104xrdb/t1042d4_sd_rcw.cfg
deleted file mode 100644
index 9d9046d6549..00000000000
--- a/board/nxp/t104xrdb/t1042d4_sd_rcw.cfg
+++ /dev/null
@@ -1,7 +0,0 @@
-#PBL preamble and RCW header
-aa55aa55 010e0100
-# serdes protocol 0x86
-0c18000e 0e000000 00000000 00000000
-86000002 40000002 6c027000 01000000
-00000000 00000000 00000000 00030810
-00000000 0342500f 00000000 00000000
diff --git a/board/nxp/t104xrdb/t1042d4_spi_rcw.cfg b/board/nxp/t104xrdb/t1042d4_spi_rcw.cfg
deleted file mode 100644
index f1ec98932f8..00000000000
--- a/board/nxp/t104xrdb/t1042d4_spi_rcw.cfg
+++ /dev/null
@@ -1,7 +0,0 @@
-#PBL preamble and RCW header
-aa55aa55 010e0100
-# serdes protocol 0x86
-0c18000e 0e000000 00000000 00000000
-86000002 40000002 5c027000 01000000
-00000000 00000000 00000000 00030810
-00000000 0342500f 00000000 00000000
diff --git a/board/nxp/t104xrdb/t104x_pbi.cfg b/board/nxp/t104xrdb/t104x_pbi.cfg
deleted file mode 100644
index 51945b47489..00000000000
--- a/board/nxp/t104xrdb/t104x_pbi.cfg
+++ /dev/null
@@ -1,36 +0,0 @@
-#PBI commands
-#Software Workaround for errata A-007662 to train PCIe2 controller in Gen2 speed
-09250100 00000400
-09250108 00002000
-#Software Workaround for errata A-008007 to reset PVR register
-09000010 0000000b
-09000014 c0000000
-09000018 81d00017
-89020400 a1000000
-091380c0 000f0000
-89020400 00000000
-#Initialize CPC1
-09010000 00200400
-09138000 00000000
-091380c0 00000100
-#Configure CPC1 as 256KB SRAM
-09010100 00000000
-09010104 fffc0007
-09010f00 081e000d
-09010000 80000000
-#Configure LAW for CPC1
-09000cd0 00000000
-09000cd4 fffc0000
-09000cd8 81000011
-#Configure alternate space
-09000010 00000000
-09000014 ff000000
-09000018 81000000
-#Configure SPI controller
-09110000 80000403
-09110020 2d170008
-09110024 00100008
-09110028 00100008
-0911002c 00100008
-#Flush PBL data
-091380c0 000FFFFF
diff --git a/board/nxp/t104xrdb/t104x_pbi_sb.cfg b/board/nxp/t104xrdb/t104x_pbi_sb.cfg
deleted file mode 100644
index 98dc8e4c240..00000000000
--- a/board/nxp/t104xrdb/t104x_pbi_sb.cfg
+++ /dev/null
@@ -1,38 +0,0 @@
-#PBI commands
-#Software Workaround for errata A-007662 to train PCIe2 controller in Gen2 speed
-09250100 00000400
-09250108 00002000
-#Software Workaround for errata A-008007 to reset PVR register
-09000010 0000000b
-09000014 c0000000
-09000018 81d00017
-89020400 a1000000
-091380c0 000f0000
-89020400 00000000
-#Initialize CPC1
-09010000 00200400
-09138000 00000000
-091380c0 00000100
-#Configure CPC1 as 256KB SRAM
-09010100 00000000
-09010104 bffc0007
-09010f00 081e000d
-09010000 80000000
-#Configure LAW for CPC1
-09000cd0 00000000
-09000cd4 bffc0000
-09000cd8 81000011
-#Configure alternate space
-09000010 00000000
-09000014 bf000000
-09000018 81000000
-#Configure SPI controller
-09110000 80000403
-09110020 2d170008
-09110024 00100008
-09110028 00100008
-0911002c 00100008
-#Flush PBL data
-091380c0 000FFFFF
-090e0200 bffd0000
-091380c0 000FFFFF
diff --git a/board/nxp/t104xrdb/t104xrdb.c b/board/nxp/t104xrdb/t104xrdb.c
deleted file mode 100644
index ef4dfef4965..00000000000
--- a/board/nxp/t104xrdb/t104xrdb.c
+++ /dev/null
@@ -1,159 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- * Copyright 2023 NXP
- */
-
-#include <config.h>
-#include <command.h>
-#include <env.h>
-#include <fdt_support.h>
-#include <hwconfig.h>
-#include <image.h>
-#include <init.h>
-#include <log.h>
-#include <netdev.h>
-#include <asm/global_data.h>
-#include <linux/compiler.h>
-#include <asm/mmu.h>
-#include <asm/processor.h>
-#include <asm/cache.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_fdt.h>
-#include <asm/fsl_law.h>
-#include <asm/fsl_serdes.h>
-#include <asm/fsl_liodn.h>
-#include <clock_legacy.h>
-#include <fm_eth.h>
-#include "../common/sleep.h"
-#include "t104xrdb.h"
-#include "cpld.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#if CONFIG_IS_ENABLED(DM_SERIAL)
-int get_serial_clock(void)
-{
- return get_bus_freq(0) / 2;
-}
-#endif
-
-int checkboard(void)
-{
- struct cpu_type *cpu = gd->arch.cpu;
- u8 sw;
-
-#if defined(CONFIG_TARGET_T1042D4RDB)
- printf("Board: %sD4RDB\n", cpu->name);
-#else
- printf("Board: %sRDB\n", cpu->name);
-#endif
- printf("Board rev: 0x%02x CPLD ver: 0x%02x, ",
- CPLD_READ(hw_ver), CPLD_READ(sw_ver));
-
- sw = CPLD_READ(flash_ctl_status);
- sw = ((sw & CPLD_LBMAP_MASK) >> CPLD_LBMAP_SHIFT);
-
- printf("vBank: %d\n", sw);
-
- return 0;
-}
-
-int board_early_init_f(void)
-{
-#if defined(CONFIG_DEEP_SLEEP)
- if (is_warm_boot())
- fsl_dp_disable_console();
-#endif
-
- return 0;
-}
-
-int board_early_init_r(void)
-{
-#ifdef CFG_SYS_FLASH_BASE
- const unsigned int flashbase = CFG_SYS_FLASH_BASE;
- int flash_esel = find_tlb_idx((void *)flashbase, 1);
-
- /*
- * Remap Boot flash region to caching-inhibited
- * so that flash can be erased properly.
- */
-
- /* Flush d-cache and invalidate i-cache of any FLASH data */
- flush_dcache();
- invalidate_icache();
-
- if (flash_esel == -1) {
- /* very unlikely unless something is messed up */
- puts("Error: Could not find TLB for FLASH BASE\n");
- flash_esel = 2; /* give our best effort to continue */
- } else {
- /* invalidate existing TLB entry for flash */
- disable_tlb(flash_esel);
- }
-
- set_tlb(1, flashbase, CFG_SYS_FLASH_BASE_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, flash_esel, BOOKE_PAGESZ_256M, 1);
-#endif
-
- pci_init();
-
- return 0;
-}
-
-int misc_init_r(void)
-{
- ccsr_gur_t __iomem *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
- u32 srds_s1;
-
- srds_s1 = in_be32(&gur->rcwsr[4]) >> 24;
-
- printf("SERDES Reference : 0x%X\n", srds_s1);
-
- /* select SGMII*/
- if (srds_s1 == 0x86)
- CPLD_WRITE(misc_ctl_status, CPLD_READ(misc_ctl_status) |
- MISC_CTL_SG_SEL);
-
- /* select SGMII and Aurora*/
- if (srds_s1 == 0x8E)
- CPLD_WRITE(misc_ctl_status, CPLD_READ(misc_ctl_status) |
- MISC_CTL_SG_SEL | MISC_CTL_AURORA_SEL);
-
- return 0;
-}
-
-int ft_board_setup(void *blob, struct bd_info *bd)
-{
- phys_addr_t base;
- phys_size_t size;
-
- ft_cpu_setup(blob, bd);
-
- base = env_get_bootm_low();
- size = env_get_bootm_size();
-
- fdt_fixup_memory(blob, (u64)base, (u64)size);
-
-#ifdef CONFIG_PCI
- pci_of_setup(blob, bd);
-#endif
-
- fdt_fixup_liodn(blob);
-
-#ifdef CONFIG_HAS_FSL_DR_USB
- fsl_fdt_fixup_dr_usb(blob, bd);
-#endif
-
-#ifdef CONFIG_SYS_DPAA_FMAN
-#ifndef CONFIG_DM_ETH
- fdt_fixup_fman_ethernet(blob);
-#endif
-#endif
-
- if (hwconfig("qe-tdm"))
- fdt_del_diu(blob);
- return 0;
-}
diff --git a/board/nxp/t104xrdb/t104xrdb.h b/board/nxp/t104xrdb/t104xrdb.h
deleted file mode 100644
index 5825e69cdb4..00000000000
--- a/board/nxp/t104xrdb/t104xrdb.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-#ifndef __T104x_RDB_H__
-#define __T104x_RDB_H__
-
-void pci_of_setup(void *blob, struct bd_info *bd);
-
-#endif
diff --git a/board/nxp/t104xrdb/tlb.c b/board/nxp/t104xrdb/tlb.c
deleted file mode 100644
index 7b2183da8b0..00000000000
--- a/board/nxp/t104xrdb/tlb.c
+++ /dev/null
@@ -1,132 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-#include <config.h>
-#include <asm/mmu.h>
-#include <asm/ppc.h>
-
-struct fsl_e_tlb_entry tlb_table[] = {
- /* TLB 0 - for temp stack in cache */
- SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR,
- CFG_SYS_INIT_RAM_ADDR_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 4 * 1024,
- CFG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 8 * 1024,
- CFG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 12 * 1024,
- CFG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
-
- /* TLB 1 */
- /* *I*** - Covers boot page */
-#if defined(CONFIG_SYS_RAMBOOT) && defined(CFG_SYS_INIT_L3_ADDR) && \
- !defined(CONFIG_NXP_ESBC)
- /*
- * *I*G - L3SRAM. When L3 is used as 256K SRAM, the address of the
- * SRAM is at 0xfffc0000, it covered the 0xfffff000.
- */
- SET_TLB_ENTRY(1, CFG_SYS_INIT_L3_ADDR, CFG_SYS_INIT_L3_ADDR,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 0, BOOKE_PAGESZ_256K, 1),
-
-#elif defined(CONFIG_NXP_ESBC) && defined(CONFIG_XPL_BUILD)
- /*
- * *I*G - L3SRAM. When L3 is used as 256K SRAM, in case of Secure Boot
- * the physical address of the SRAM is at 0xbffc0000,
- * and virtual address is 0xfffc0000
- */
-
- SET_TLB_ENTRY(1, CFG_SYS_INIT_L3_VADDR,
- CFG_SYS_INIT_L3_ADDR,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 0, BOOKE_PAGESZ_256K, 1),
-#else
- SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 0, BOOKE_PAGESZ_4K, 1),
-#endif
-
- /* *I*G* - CCSRBAR */
- SET_TLB_ENTRY(1, CFG_SYS_CCSRBAR, CFG_SYS_CCSRBAR_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 1, BOOKE_PAGESZ_16M, 1),
-
- /* *I*G* - Flash, localbus */
- /* This will be changed to *I*G* after relocation to RAM. */
- SET_TLB_ENTRY(1, CFG_SYS_FLASH_BASE, CFG_SYS_FLASH_BASE_PHYS,
- MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
- 0, 2, BOOKE_PAGESZ_256M, 1),
-
-#ifndef CONFIG_XPL_BUILD
- /* *I*G* - PCI */
- SET_TLB_ENTRY(1, CFG_SYS_PCIE1_MEM_VIRT, CFG_SYS_PCIE1_MEM_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 3, BOOKE_PAGESZ_1G, 1),
-
- /* *I*G* - PCI I/O */
- SET_TLB_ENTRY(1, CFG_SYS_PCIE1_IO_VIRT, CFG_SYS_PCIE1_IO_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 4, BOOKE_PAGESZ_256K, 1),
-
- /* Bman/Qman */
-#ifdef CFG_SYS_BMAN_MEM_PHYS
- SET_TLB_ENTRY(1, CFG_SYS_BMAN_MEM_BASE, CFG_SYS_BMAN_MEM_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 5, BOOKE_PAGESZ_16M, 1),
- SET_TLB_ENTRY(1, CFG_SYS_BMAN_MEM_BASE + 0x01000000,
- CFG_SYS_BMAN_MEM_PHYS + 0x01000000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 6, BOOKE_PAGESZ_16M, 1),
-#endif
-#ifdef CFG_SYS_QMAN_MEM_PHYS
- SET_TLB_ENTRY(1, CFG_SYS_QMAN_MEM_BASE, CFG_SYS_QMAN_MEM_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 7, BOOKE_PAGESZ_16M, 1),
- SET_TLB_ENTRY(1, CFG_SYS_QMAN_MEM_BASE + 0x01000000,
- CFG_SYS_QMAN_MEM_PHYS + 0x01000000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 8, BOOKE_PAGESZ_16M, 1),
-#endif
-#endif
-#ifdef CFG_SYS_DCSRBAR_PHYS
- SET_TLB_ENTRY(1, CFG_SYS_DCSRBAR, CFG_SYS_DCSRBAR_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 9, BOOKE_PAGESZ_4M, 1),
-#endif
-#ifdef CFG_SYS_NAND_BASE
- /*
- * *I*G - NAND
- * entry 14 and 15 has been used hard coded, they will be disabled
- * in cpu_init_f, so we use entry 16 for nand.
- */
- SET_TLB_ENTRY(1, CFG_SYS_NAND_BASE, CFG_SYS_NAND_BASE_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 10, BOOKE_PAGESZ_64K, 1),
-#endif
-#ifdef CFG_SYS_CPLD_BASE
- SET_TLB_ENTRY(1, CFG_SYS_CPLD_BASE, CFG_SYS_CPLD_BASE_PHYS,
- MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 11, BOOKE_PAGESZ_256K, 1),
-#endif
-
-#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_XPL_BUILD)
- SET_TLB_ENTRY(1, CFG_SYS_DDR_SDRAM_BASE, CFG_SYS_DDR_SDRAM_BASE,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
- 0, 12, BOOKE_PAGESZ_1G, 1),
- SET_TLB_ENTRY(1, CFG_SYS_DDR_SDRAM_BASE + 0x40000000,
- CFG_SYS_DDR_SDRAM_BASE + 0x40000000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
- 0, 13, BOOKE_PAGESZ_1G, 1)
-#endif
-};
-
-int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/configs/T1042D4RDB_NAND_defconfig b/configs/T1042D4RDB_NAND_defconfig
deleted file mode 100644
index 7ec5bfd2ad0..00000000000
--- a/configs/T1042D4RDB_NAND_defconfig
+++ /dev/null
@@ -1,144 +0,0 @@
-CONFIG_PPC=y
-CONFIG_TEXT_BASE=0x30000000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x180000
-CONFIG_DEFAULT_DEVICE_TREE="t1042d4rdb"
-CONFIG_SYS_MONITOR_LEN=786432
-CONFIG_SPL_SERIAL=y
-CONFIG_SPL_DRIVERS_MISC=y
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
-CONFIG_SPL=y
-CONFIG_MPC85xx=y
-CONFIG_SYS_INIT_RAM_LOCK=y
-CONFIG_TARGET_T1042D4RDB=y
-CONFIG_ENABLE_36BIT_PHYS=y
-CONFIG_SYS_BOOK3E_HV=y
-CONFIG_SYS_CACHE_STASHING=y
-CONFIG_SYS_MPC85XX_NO_RESETVEC=y
-CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
-CONFIG_USE_UBOOTPATH=y
-CONFIG_PCIE1=y
-CONFIG_PCIE2=y
-CONFIG_PCIE3=y
-CONFIG_PCIE4=y
-CONFIG_SYS_FSL_NUM_CC_PLLS=2
-CONFIG_MP=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_RAMBOOT_PBL=y
-CONFIG_SYS_FSL_PBL_PBI="$(SRCTREE)/board/nxp/t104xrdb/t104x_pbi.cfg"
-CONFIG_SYS_FSL_PBL_RCW="$(SRCTREE)/board/nxp/t104xrdb/t1042d4_nand_rcw.cfg"
-CONFIG_BOOTDELAY=10
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_USE_BOOTCOMMAND=y
-CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs;setenv ramdiskaddr 0x02000000;setenv fdtaddr 0x00c00000;setenv loadaddr 0x1000000;bootm $loadaddr $ramdiskaddr $fdtaddr"
-CONFIG_SYS_PBSIZE=276
-CONFIG_SILENT_CONSOLE=y
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_MAX_SIZE=0x28000
-CONFIG_SPL_PAD_TO=0x40000
-CONFIG_SPL_NAND_BOOT=y
-CONFIG_SPL_FSL_PBL=y
-CONFIG_SPL_SYS_CCSR_DO_NOT_RELOCATE=y
-CONFIG_SPL_FLUSH_IMAGE=y
-CONFIG_SPL_SKIP_RELOCATE=y
-CONFIG_SPL_GD_ADDR=0xfffc8000
-CONFIG_SPL_RELOC_STACK=0xfffd8000
-CONFIG_SPL_RELOC_MALLOC=y
-CONFIG_SPL_RELOC_MALLOC_ADDR=0xfffcb000
-CONFIG_SPL_RELOC_MALLOC_SIZE=0x7800
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C=y
-CONFIG_SPL_MPC8XXX_INIT_DDR=y
-CONFIG_SPL_NAND_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_DM=y
-CONFIG_CMD_I2C=y
-CONFIG_LOADS_ECHO=y
-CONFIG_SYS_LOADS_BAUD_CHANGE=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:2m(uboot),9m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:2m(uboot),9m(kernel),128k(dtb),-(user)"
-CONFIG_OF_CONTROL=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_NAND=y
-CONFIG_USE_BOOTFILE=y
-CONFIG_BOOTFILE="uImage"
-CONFIG_USE_ETHPRIME=y
-CONFIG_ETHPRIME="FM1@DTSEC4"
-CONFIG_USE_ROOTPATH=y
-CONFIG_FSL_CAAM=y
-CONFIG_DDR_CLK_FREQ=66666666
-CONFIG_CHIP_SELECTS_PER_CTRL=2
-CONFIG_DDR_ECC=y
-CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
-CONFIG_DM_I2C=y
-CONFIG_SPL_SYS_I2C_LEGACY=y
-CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
-CONFIG_SYS_I2C_FSL=y
-CONFIG_SYS_FSL_I2C_OFFSET=0x118000
-CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y
-CONFIG_SYS_FSL_I2C2_OFFSET=0x118100
-CONFIG_SYS_FSL_HAS_I2C3_OFFSET=y
-CONFIG_SYS_FSL_I2C3_OFFSET=0x119000
-CONFIG_SYS_FSL_HAS_I2C4_OFFSET=y
-CONFIG_SYS_FSL_I2C4_OFFSET=0x119100
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_EMPTY_INFO=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SYS_FLASH_QUIET_TEST=y
-CONFIG_SYS_MAX_FLASH_SECT=1024
-CONFIG_SYS_MAX_FLASH_BANKS=2
-CONFIG_MTD_RAW_NAND=y
-CONFIG_NAND_FSL_IFC=y
-CONFIG_SYS_NAND_ONFI_DETECTION=y
-CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
-CONFIG_SYS_NAND_U_BOOT_OFFS=0x40000
-CONFIG_DM_SPI_FLASH=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_DM_MDIO=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_SYS_FMAN_FW_ADDR=0x280000
-CONFIG_MII=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PCIE_FSL=y
-CONFIG_U_QE=y
-CONFIG_SYS_QE_FW_ADDR=0x380000
-CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
-CONFIG_DM_RTC=y
-CONFIG_RTC_DS1337=y
-CONFIG_DM_SERIAL=y
-CONFIG_SPL_SYS_NS16550_SERIAL=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_EHCI_FSL=y
-CONFIG_USB_MAX_CONTROLLER_COUNT=2
-CONFIG_USB_STORAGE=y
-CONFIG_ADDR_MAP=y
-CONFIG_SYS_NUM_ADDR_MAP=64
diff --git a/configs/T1042D4RDB_SDCARD_defconfig b/configs/T1042D4RDB_SDCARD_defconfig
deleted file mode 100644
index c418c3064d4..00000000000
--- a/configs/T1042D4RDB_SDCARD_defconfig
+++ /dev/null
@@ -1,138 +0,0 @@
-CONFIG_PPC=y
-CONFIG_TEXT_BASE=0x30000000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x100000
-CONFIG_DEFAULT_DEVICE_TREE="t1042d4rdb"
-CONFIG_SYS_MONITOR_LEN=786432
-CONFIG_SPL_MMC=y
-CONFIG_SPL_SERIAL=y
-CONFIG_SPL_DRIVERS_MISC=y
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
-CONFIG_SPL=y
-CONFIG_MPC85xx=y
-CONFIG_SYS_INIT_RAM_LOCK=y
-CONFIG_TARGET_T1042D4RDB=y
-CONFIG_ENABLE_36BIT_PHYS=y
-CONFIG_SYS_BOOK3E_HV=y
-CONFIG_SYS_CACHE_STASHING=y
-CONFIG_SYS_MPC85XX_NO_RESETVEC=y
-CONFIG_USE_UBOOTPATH=y
-CONFIG_PCIE1=y
-CONFIG_PCIE2=y
-CONFIG_PCIE3=y
-CONFIG_PCIE4=y
-CONFIG_SYS_FSL_NUM_CC_PLLS=2
-CONFIG_MP=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_RAMBOOT_PBL=y
-CONFIG_SYS_FSL_PBL_PBI="$(SRCTREE)/board/nxp/t104xrdb/t104x_pbi.cfg"
-CONFIG_SYS_FSL_PBL_RCW="$(SRCTREE)/board/nxp/t104xrdb/t1042d4_sd_rcw.cfg"
-CONFIG_BOOTDELAY=10
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_USE_BOOTCOMMAND=y
-CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs;setenv ramdiskaddr 0x02000000;setenv fdtaddr 0x00c00000;setenv loadaddr 0x1000000;bootm $loadaddr $ramdiskaddr $fdtaddr"
-CONFIG_SYS_PBSIZE=276
-CONFIG_SILENT_CONSOLE=y
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_MAX_SIZE=0x28000
-CONFIG_SPL_PAD_TO=0x40000
-CONFIG_SPL_MMC_BOOT=y
-CONFIG_SPL_FSL_PBL=y
-CONFIG_SPL_SYS_CCSR_DO_NOT_RELOCATE=y
-CONFIG_SPL_FLUSH_IMAGE=y
-CONFIG_SPL_SKIP_RELOCATE=y
-CONFIG_SPL_GD_ADDR=0xfffc8000
-CONFIG_SPL_RELOC_STACK=0xfffd8000
-CONFIG_SPL_RELOC_MALLOC=y
-CONFIG_SPL_RELOC_MALLOC_ADDR=0xfffcb000
-CONFIG_SPL_RELOC_MALLOC_SIZE=0x7800
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C=y
-CONFIG_SPL_MPC8XXX_INIT_DDR=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_DM=y
-CONFIG_CMD_I2C=y
-CONFIG_LOADS_ECHO=y
-CONFIG_SYS_LOADS_BAUD_CHANGE=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:2m(uboot),9m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:2m(uboot),9m(kernel),128k(dtb),-(user)"
-CONFIG_OF_CONTROL=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_USE_BOOTFILE=y
-CONFIG_BOOTFILE="uImage"
-CONFIG_USE_ETHPRIME=y
-CONFIG_ETHPRIME="FM1@DTSEC4"
-CONFIG_USE_ROOTPATH=y
-CONFIG_FSL_CAAM=y
-CONFIG_DDR_CLK_FREQ=66666666
-CONFIG_CHIP_SELECTS_PER_CTRL=2
-CONFIG_DDR_ECC=y
-CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
-CONFIG_DM_I2C=y
-CONFIG_SPL_SYS_I2C_LEGACY=y
-CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
-CONFIG_SYS_I2C_FSL=y
-CONFIG_SYS_FSL_I2C_OFFSET=0x118000
-CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y
-CONFIG_SYS_FSL_I2C2_OFFSET=0x118100
-CONFIG_SYS_FSL_HAS_I2C3_OFFSET=y
-CONFIG_SYS_FSL_I2C3_OFFSET=0x119000
-CONFIG_SYS_FSL_HAS_I2C4_OFFSET=y
-CONFIG_SYS_FSL_I2C4_OFFSET=0x119100
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_EMPTY_INFO=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SYS_FLASH_QUIET_TEST=y
-CONFIG_SYS_MAX_FLASH_SECT=1024
-CONFIG_SYS_MAX_FLASH_BANKS=2
-CONFIG_DM_SPI_FLASH=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_DM_MDIO=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_SYS_FMAN_FW_ADDR=0x10400
-CONFIG_MII=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PCIE_FSL=y
-CONFIG_U_QE=y
-CONFIG_SYS_QE_FW_ADDR=0x124000
-CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
-CONFIG_DM_RTC=y
-CONFIG_RTC_DS1337=y
-CONFIG_DM_SERIAL=y
-CONFIG_SPL_SYS_NS16550_SERIAL=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_EHCI_FSL=y
-CONFIG_USB_MAX_CONTROLLER_COUNT=2
-CONFIG_USB_STORAGE=y
-CONFIG_ADDR_MAP=y
-CONFIG_SYS_NUM_ADDR_MAP=64
diff --git a/configs/T1042D4RDB_SPIFLASH_defconfig b/configs/T1042D4RDB_SPIFLASH_defconfig
deleted file mode 100644
index f758cd9aaa5..00000000000
--- a/configs/T1042D4RDB_SPIFLASH_defconfig
+++ /dev/null
@@ -1,141 +0,0 @@
-CONFIG_PPC=y
-CONFIG_TEXT_BASE=0x30000000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x100000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_DEFAULT_DEVICE_TREE="t1042d4rdb"
-CONFIG_SYS_MONITOR_LEN=786432
-CONFIG_SPL_SERIAL=y
-CONFIG_SPL_DRIVERS_MISC=y
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
-CONFIG_SPL=y
-CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI=y
-CONFIG_MPC85xx=y
-CONFIG_SYS_INIT_RAM_LOCK=y
-CONFIG_TARGET_T1042D4RDB=y
-CONFIG_ENABLE_36BIT_PHYS=y
-CONFIG_SYS_BOOK3E_HV=y
-CONFIG_SYS_CACHE_STASHING=y
-CONFIG_SYS_MPC85XX_NO_RESETVEC=y
-CONFIG_USE_UBOOTPATH=y
-CONFIG_PCIE1=y
-CONFIG_PCIE2=y
-CONFIG_PCIE3=y
-CONFIG_PCIE4=y
-CONFIG_SYS_FSL_NUM_CC_PLLS=2
-CONFIG_MP=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_RAMBOOT_PBL=y
-CONFIG_SPIFLASH=y
-CONFIG_SYS_FSL_PBL_PBI="$(SRCTREE)/board/nxp/t104xrdb/t104x_pbi.cfg"
-CONFIG_SYS_FSL_PBL_RCW="$(SRCTREE)/board/nxp/t104xrdb/t1042d4_spi_rcw.cfg"
-CONFIG_BOOTDELAY=10
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_USE_BOOTCOMMAND=y
-CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs;setenv ramdiskaddr 0x02000000;setenv fdtaddr 0x00c00000;setenv loadaddr 0x1000000;bootm $loadaddr $ramdiskaddr $fdtaddr"
-CONFIG_SYS_PBSIZE=276
-CONFIG_SILENT_CONSOLE=y
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_MAX_SIZE=0x28000
-CONFIG_SPL_PAD_TO=0x40000
-CONFIG_SPL_SPI_BOOT=y
-CONFIG_SPL_FSL_PBL=y
-CONFIG_SPL_SYS_CCSR_DO_NOT_RELOCATE=y
-CONFIG_SPL_FLUSH_IMAGE=y
-CONFIG_SPL_SKIP_RELOCATE=y
-CONFIG_SPL_GD_ADDR=0xfffc8000
-CONFIG_SPL_RELOC_STACK=0xfffd8000
-CONFIG_SPL_RELOC_MALLOC=y
-CONFIG_SPL_RELOC_MALLOC_ADDR=0xfffcb000
-CONFIG_SPL_RELOC_MALLOC_SIZE=0x7800
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C=y
-CONFIG_SPL_MPC8XXX_INIT_DDR=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_DM=y
-CONFIG_CMD_I2C=y
-CONFIG_LOADS_ECHO=y
-CONFIG_SYS_LOADS_BAUD_CHANGE=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:2m(uboot),9m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:2m(uboot),9m(kernel),128k(dtb),-(user)"
-CONFIG_OF_CONTROL=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_USE_BOOTFILE=y
-CONFIG_BOOTFILE="uImage"
-CONFIG_USE_ETHPRIME=y
-CONFIG_ETHPRIME="FM1@DTSEC4"
-CONFIG_USE_ROOTPATH=y
-CONFIG_FSL_CAAM=y
-CONFIG_DDR_CLK_FREQ=66666666
-CONFIG_CHIP_SELECTS_PER_CTRL=2
-CONFIG_DDR_ECC=y
-CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
-CONFIG_DM_I2C=y
-CONFIG_SPL_SYS_I2C_LEGACY=y
-CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
-CONFIG_SYS_I2C_FSL=y
-CONFIG_SYS_FSL_I2C_OFFSET=0x118000
-CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y
-CONFIG_SYS_FSL_I2C2_OFFSET=0x118100
-CONFIG_SYS_FSL_HAS_I2C3_OFFSET=y
-CONFIG_SYS_FSL_I2C3_OFFSET=0x119000
-CONFIG_SYS_FSL_HAS_I2C4_OFFSET=y
-CONFIG_SYS_FSL_I2C4_OFFSET=0x119100
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_EMPTY_INFO=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SYS_FLASH_QUIET_TEST=y
-CONFIG_SYS_MAX_FLASH_SECT=1024
-CONFIG_SYS_MAX_FLASH_BANKS=2
-CONFIG_DM_SPI_FLASH=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_DM_MDIO=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_SYS_FMAN_FW_ADDR=0x110000
-CONFIG_MII=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PCIE_FSL=y
-CONFIG_U_QE=y
-CONFIG_SYS_QE_FW_ADDR=0x130000
-CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
-CONFIG_DM_RTC=y
-CONFIG_RTC_DS1337=y
-CONFIG_DM_SERIAL=y
-CONFIG_SPL_SYS_NS16550_SERIAL=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_EHCI_FSL=y
-CONFIG_USB_MAX_CONTROLLER_COUNT=2
-CONFIG_USB_STORAGE=y
-CONFIG_ADDR_MAP=y
-CONFIG_SYS_NUM_ADDR_MAP=64
diff --git a/configs/T1042D4RDB_defconfig b/configs/T1042D4RDB_defconfig
deleted file mode 100644
index 6e53e581c81..00000000000
--- a/configs/T1042D4RDB_defconfig
+++ /dev/null
@@ -1,114 +0,0 @@
-CONFIG_PPC=y
-CONFIG_TEXT_BASE=0xEFF40000
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_DEFAULT_DEVICE_TREE="t1042d4rdb"
-CONFIG_SYS_MONITOR_LEN=786432
-CONFIG_ENV_ADDR=0xEFF20000
-CONFIG_MPC85xx=y
-CONFIG_SYS_INIT_RAM_LOCK=y
-CONFIG_TARGET_T1042D4RDB=y
-CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
-CONFIG_ENABLE_36BIT_PHYS=y
-CONFIG_SYS_BOOK3E_HV=y
-CONFIG_SYS_CACHE_STASHING=y
-CONFIG_USE_UBOOTPATH=y
-CONFIG_PCIE1=y
-CONFIG_PCIE2=y
-CONFIG_PCIE3=y
-CONFIG_PCIE4=y
-CONFIG_SYS_FSL_NUM_CC_PLLS=2
-CONFIG_MP=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_BOOTDELAY=10
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_USE_BOOTCOMMAND=y
-CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs;setenv ramdiskaddr 0x02000000;setenv fdtaddr 0x00c00000;setenv loadaddr 0x1000000;bootm $loadaddr $ramdiskaddr $fdtaddr"
-CONFIG_SYS_PBSIZE=276
-CONFIG_SILENT_CONSOLE=y
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_DM=y
-CONFIG_CMD_I2C=y
-CONFIG_LOADS_ECHO=y
-CONFIG_SYS_LOADS_BAUD_CHANGE=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:2m(uboot),9m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:2m(uboot),9m(kernel),128k(dtb),-(user)"
-CONFIG_OF_CONTROL=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_USE_BOOTFILE=y
-CONFIG_BOOTFILE="uImage"
-CONFIG_USE_ETHPRIME=y
-CONFIG_ETHPRIME="FM1@DTSEC4"
-CONFIG_USE_ROOTPATH=y
-CONFIG_FSL_CAAM=y
-CONFIG_DDR_CLK_FREQ=66666666
-CONFIG_CHIP_SELECTS_PER_CTRL=2
-CONFIG_DDR_ECC=y
-CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
-CONFIG_DM_I2C=y
-CONFIG_SPL_SYS_I2C_LEGACY=y
-CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
-CONFIG_SYS_I2C_FSL=y
-CONFIG_SYS_FSL_I2C_OFFSET=0x118000
-CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y
-CONFIG_SYS_FSL_I2C2_OFFSET=0x118100
-CONFIG_SYS_FSL_HAS_I2C3_OFFSET=y
-CONFIG_SYS_FSL_I2C3_OFFSET=0x119000
-CONFIG_SYS_FSL_HAS_I2C4_OFFSET=y
-CONFIG_SYS_FSL_I2C4_OFFSET=0x119100
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_EMPTY_INFO=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SYS_FLASH_QUIET_TEST=y
-CONFIG_SYS_MAX_FLASH_SECT=1024
-CONFIG_SYS_MAX_FLASH_BANKS=2
-CONFIG_DM_SPI_FLASH=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_DM_MDIO=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_SYS_FMAN_FW_ADDR=0xEFF00000
-CONFIG_MII=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PCIE_FSL=y
-CONFIG_U_QE=y
-CONFIG_SYS_QE_FW_ADDR=0xEFF10000
-CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_DM_RTC=y
-CONFIG_RTC_DS1337=y
-CONFIG_SPECIFY_CONSOLE_INDEX=y
-CONFIG_DM_SERIAL=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_EHCI_FSL=y
-CONFIG_USB_MAX_CONTROLLER_COUNT=2
-CONFIG_USB_STORAGE=y
-CONFIG_ADDR_MAP=y
-CONFIG_SYS_NUM_ADDR_MAP=64
diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h
deleted file mode 100644
index 01db298f38e..00000000000
--- a/include/configs/T104xRDB.h
+++ /dev/null
@@ -1,397 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2014 Freescale Semiconductor, Inc.
- * Copyright 2020-2023 NXP
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <linux/stringify.h>
-
-/*
- * T104x RDB board configuration file
- */
-#include <asm/config_mpc85xx.h>
-
-#ifdef CONFIG_RAMBOOT_PBL
-#define RESET_VECTOR_OFFSET 0x27FFC
-#define BOOT_PAGE_OFFSET 0x27000
-
-#ifdef CONFIG_MTD_RAW_NAND
-#ifdef CONFIG_NXP_ESBC
-#define CFG_SYS_NAND_U_BOOT_SIZE ((768 << 10) + (16 << 10))
-#else
-#define CFG_SYS_NAND_U_BOOT_SIZE (768 << 10)
-#endif
-#define CFG_SYS_NAND_U_BOOT_DST 0x30000000
-#define CFG_SYS_NAND_U_BOOT_START 0x30000000
-#endif
-
-#ifdef CONFIG_SPIFLASH
-#define CFG_RESET_VECTOR_ADDRESS 0x30000FFC
-#define CFG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
-#define CFG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000)
-#define CFG_SYS_SPI_FLASH_U_BOOT_START (0x30000000)
-#define CFG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
-#endif
-
-#ifdef CONFIG_SDCARD
-#define CFG_RESET_VECTOR_ADDRESS 0x30000FFC
-#define CFG_SYS_MMC_U_BOOT_SIZE (768 << 10)
-#define CFG_SYS_MMC_U_BOOT_DST (0x30000000)
-#define CFG_SYS_MMC_U_BOOT_START (0x30000000)
-#define CFG_SYS_MMC_U_BOOT_OFFS (260 << 10)
-#endif
-
-#endif
-
-/* High Level Configuration Options */
-
-#ifndef CFG_RESET_VECTOR_ADDRESS
-#define CFG_RESET_VECTOR_ADDRESS 0xeffffffc
-#endif
-
-#define CFG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
-
-/*
- * These can be toggled for performance analysis, otherwise use default.
- */
-#define CFG_SYS_INIT_L2CSR0 L2CSR0_L2E
-
-/*
- * Config the L3 Cache as L3 SRAM
- */
-#define CFG_SYS_INIT_L3_ADDR 0xFFFC0000
-/*
- * For Secure Boot CFG_SYS_INIT_L3_ADDR will be redefined and hence
- * Physical address (CFG_SYS_INIT_L3_ADDR) and virtual address
- * (CFG_SYS_INIT_L3_VADDR) will be different.
- */
-#define CFG_SYS_INIT_L3_VADDR 0xFFFC0000
-#define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
-
-#define CFG_SYS_DCSRBAR 0xf0000000
-#define CFG_SYS_DCSRBAR_PHYS 0xf00000000ull
-
-/*
- * DDR Setup
- */
-#define CFG_SYS_DDR_SDRAM_BASE 0x00000000
-#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
-
-#define SPD_EEPROM_ADDRESS 0x51
-
-#define CFG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
-
-/*
- * IFC Definitions
- */
-#define CFG_SYS_FLASH_BASE 0xe8000000
-#define CFG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CFG_SYS_FLASH_BASE)
-
-#define CFG_SYS_NOR_CSPR_EXT (0xf)
-#define CFG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE) | \
- CSPR_PORT_SIZE_16 | \
- CSPR_MSEL_NOR | \
- CSPR_V)
-#define CFG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
-
-/*
- * TDM Definition
- */
-#define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000
-
-/* NOR Flash Timing Params */
-#define CFG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
-#define CFG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
- FTIM0_NOR_TEADC(0x5) | \
- FTIM0_NOR_TEAHC(0x5))
-#define CFG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
- FTIM1_NOR_TRAD_NOR(0x1A) |\
- FTIM1_NOR_TSEQRAD_NOR(0x13))
-#define CFG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
- FTIM2_NOR_TCH(0x4) | \
- FTIM2_NOR_TWPH(0x0E) | \
- FTIM2_NOR_TWP(0x1c))
-#define CFG_SYS_NOR_FTIM3 0x0
-
-#define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS}
-
-/* CPLD on IFC */
-#define CPLD_LBMAP_MASK 0x3F
-#define CPLD_BANK_SEL_MASK 0x07
-#define CPLD_BANK_OVERRIDE 0x40
-#define CPLD_LBMAP_ALTBANK 0x44 /* BANK OR | BANK 4 */
-#define CPLD_LBMAP_DFLTBANK 0x40 /* BANK OR | BANK0 */
-#define CPLD_LBMAP_RESET 0xFF
-#define CPLD_LBMAP_SHIFT 0x03
-
-#if defined(CONFIG_TARGET_T1042D4RDB)
-#define CPLD_DIU_SEL_DFP 0xc0
-#endif
-
-#define CFG_SYS_CPLD_BASE 0xffdf0000
-#define CFG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CFG_SYS_CPLD_BASE)
-#define CFG_SYS_CSPR2_EXT (0xf)
-#define CFG_SYS_CSPR2 (CSPR_PHYS_ADDR(CFG_SYS_CPLD_BASE_PHYS) \
- | CSPR_PORT_SIZE_8 \
- | CSPR_MSEL_GPCM \
- | CSPR_V)
-#define CFG_SYS_AMASK2 IFC_AMASK(64*1024)
-#define CFG_SYS_CSOR2 0x0
-/* CPLD Timing parameters for IFC CS2 */
-#define CFG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
- FTIM0_GPCM_TEADC(0x0e) | \
- FTIM0_GPCM_TEAHC(0x0e))
-#define CFG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
- FTIM1_GPCM_TRAD(0x1f))
-#define CFG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
- FTIM2_GPCM_TCH(0x8) | \
- FTIM2_GPCM_TWP(0x1f))
-#define CFG_SYS_CS2_FTIM3 0x0
-
-/* NAND Flash on IFC */
-#define CFG_SYS_NAND_BASE 0xff800000
-#define CFG_SYS_NAND_BASE_PHYS (0xf00000000ull | CFG_SYS_NAND_BASE)
-
-#define CFG_SYS_NAND_CSPR_EXT (0xf)
-#define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
- | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
- | CSPR_MSEL_NAND /* MSEL = NAND */ \
- | CSPR_V)
-#define CFG_SYS_NAND_AMASK IFC_AMASK(64*1024)
-
-#define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
- | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
- | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
- | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
- | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
- | CSOR_NAND_SPRZ_224/* Spare size = 224 */ \
- | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
-
-/* ONFI NAND Flash mode0 Timing Params */
-#define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
- FTIM0_NAND_TWP(0x18) | \
- FTIM0_NAND_TWCHT(0x07) | \
- FTIM0_NAND_TWH(0x0a))
-#define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
- FTIM1_NAND_TWBE(0x39) | \
- FTIM1_NAND_TRR(0x0e) | \
- FTIM1_NAND_TRP(0x18))
-#define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
- FTIM2_NAND_TREH(0x0a) | \
- FTIM2_NAND_TWHRE(0x1e))
-#define CFG_SYS_NAND_FTIM3 0x0
-
-#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
-
-#if defined(CONFIG_MTD_RAW_NAND)
-#define CFG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT
-#define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR
-#define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK
-#define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR
-#define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
-#define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
-#define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
-#define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
-#define CFG_SYS_CSPR1_EXT CFG_SYS_NOR_CSPR_EXT
-#define CFG_SYS_CSPR1 CFG_SYS_NOR_CSPR
-#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK
-#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR
-#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0
-#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1
-#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2
-#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3
-#else
-#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR_CSPR_EXT
-#define CFG_SYS_CSPR0 CFG_SYS_NOR_CSPR
-#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK
-#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR
-#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
-#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
-#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
-#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
-#define CFG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT
-#define CFG_SYS_CSPR1 CFG_SYS_NAND_CSPR
-#define CFG_SYS_AMASK1 CFG_SYS_NAND_AMASK
-#define CFG_SYS_CSOR1 CFG_SYS_NAND_CSOR
-#define CFG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0
-#define CFG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1
-#define CFG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2
-#define CFG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3
-#endif
-
-/* define to use L1 as initial stack */
-#define CFG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
-#define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
-#define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
-/* The assembler doesn't like typecast */
-#define CFG_SYS_INIT_RAM_ADDR_PHYS \
- ((CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
- CFG_SYS_INIT_RAM_ADDR_PHYS_LOW)
-#define CFG_SYS_INIT_RAM_SIZE 0x00004000
-
-#define CFG_SYS_INIT_SP_OFFSET (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-
-/* Serial Port - controlled on board with jumper J8
- * open - index 2
- * shorted - index 1
- */
-#if !CONFIG_IS_ENABLED(DM_SERIAL)
-#define CFG_SYS_NS16550_CLK (get_bus_freq(0)/2)
-#endif
-
-#define CFG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-
-#define CFG_SYS_NS16550_COM1 (CFG_SYS_CCSRBAR+0x11C500)
-#define CFG_SYS_NS16550_COM2 (CFG_SYS_CCSRBAR+0x11C600)
-#define CFG_SYS_NS16550_COM3 (CFG_SYS_CCSRBAR+0x11D500)
-#define CFG_SYS_NS16550_COM4 (CFG_SYS_CCSRBAR+0x11D600)
-
-/* I2C bus multiplexer */
-#define I2C_MUX_PCA_ADDR 0x70
-#define I2C_MUX_CH_DEFAULT 0x8
-
-#if defined(CONFIG_TARGET_T1042D4RDB)
-/*
- * RTC configuration
- */
-#define CFG_SYS_I2C_RTC_ADDR 0x68
-
-#endif
-
-/*
- * eSPI - Enhanced SPI
- */
-
-/*
- * General PCI
- * Memory space is mapped 1-1, but I/O space must start from 0.
- */
-
-#ifdef CONFIG_PCI
-/* controller 1, direct to uli, tgtid 3, Base address 20000 */
-#ifdef CONFIG_PCIE1
-#define CFG_SYS_PCIE1_MEM_VIRT 0x80000000
-#define CFG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
-#define CFG_SYS_PCIE1_IO_VIRT 0xf8000000
-#define CFG_SYS_PCIE1_IO_PHYS 0xff8000000ull
-#endif
-
-/* controller 2, Slot 2, tgtid 2, Base address 201000 */
-#ifdef CONFIG_PCIE2
-#define CFG_SYS_PCIE2_MEM_VIRT 0x90000000
-#define CFG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
-#define CFG_SYS_PCIE2_IO_VIRT 0xf8010000
-#define CFG_SYS_PCIE2_IO_PHYS 0xff8010000ull
-#endif
-
-/* controller 3, Slot 1, tgtid 1, Base address 202000 */
-#ifdef CONFIG_PCIE3
-#define CFG_SYS_PCIE3_MEM_VIRT 0xa0000000
-#define CFG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
-#endif
-
-/* controller 4, Base address 203000 */
-#ifdef CONFIG_PCIE4
-#define CFG_SYS_PCIE4_MEM_VIRT 0xb0000000
-#define CFG_SYS_PCIE4_MEM_PHYS 0xc30000000ull
-#endif
-#endif /* CONFIG_PCI */
-
-/*
-* USB
-*/
-
-#ifdef CONFIG_MMC
-#define CFG_SYS_FSL_ESDHC_ADDR CFG_SYS_MPC85xx_ESDHC_ADDR
-#endif
-
-/* Qman/Bman */
-#ifndef CONFIG_NOBQFMAN
-#define CFG_SYS_BMAN_NUM_PORTALS 10
-#define CFG_SYS_BMAN_MEM_BASE 0xf4000000
-#define CFG_SYS_BMAN_MEM_PHYS 0xff4000000ull
-#define CFG_SYS_BMAN_MEM_SIZE 0x02000000
-#define CFG_SYS_BMAN_SP_CENA_SIZE 0x4000
-#define CFG_SYS_BMAN_SP_CINH_SIZE 0x1000
-#define CFG_SYS_BMAN_CENA_BASE CFG_SYS_BMAN_MEM_BASE
-#define CFG_SYS_BMAN_CENA_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1)
-#define CFG_SYS_BMAN_CINH_BASE (CFG_SYS_BMAN_MEM_BASE + \
- CFG_SYS_BMAN_CENA_SIZE)
-#define CFG_SYS_BMAN_CINH_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1)
-#define CFG_SYS_BMAN_SWP_ISDR_REG 0xE08
-#define CFG_SYS_QMAN_NUM_PORTALS 10
-#define CFG_SYS_QMAN_MEM_BASE 0xf6000000
-#define CFG_SYS_QMAN_MEM_PHYS 0xff6000000ull
-#define CFG_SYS_QMAN_MEM_SIZE 0x02000000
-#define CFG_SYS_QMAN_SP_CINH_SIZE 0x1000
-#define CFG_SYS_QMAN_CENA_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1)
-#define CFG_SYS_QMAN_CINH_BASE (CFG_SYS_QMAN_MEM_BASE + \
- CFG_SYS_QMAN_CENA_SIZE)
-#define CFG_SYS_QMAN_CINH_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1)
-#define CFG_SYS_QMAN_SWP_ISDR_REG 0xE08
-#endif /* CONFIG_NOBQFMAN */
-
-#ifdef CONFIG_FMAN_ENET
-#if defined(CONFIG_TARGET_T1042D4RDB)
-#define CFG_SYS_SGMII1_PHY_ADDR 0x02
-#define CFG_SYS_SGMII2_PHY_ADDR 0x03
-#define CFG_SYS_SGMII3_PHY_ADDR 0x01
-#endif
-
-#define CFG_SYS_RGMII1_PHY_ADDR 0x01
-#define CFG_SYS_RGMII2_PHY_ADDR 0x02
-#endif
-
-/*
- * Miscellaneous configurable options
- */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 64 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CFG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
-
-/*
- * Dynamic MTD Partition support with mtdparts
- */
-
-/*
- * Environment Configuration
- */
-
-#define __USB_PHY_TYPE utmi
-#define RAMDISKFILE "t104xrdb/ramdisk.uboot"
-
-#if defined(CONFIG_TARGET_T1042D4RDB)
-#define FDTFILE "t1042rdb/t1042d4rdb.dtb"
-#endif
-
-#define CFG_EXTRA_ENV_SETTINGS \
- "hwconfig=fsl_ddr:bank_intlv=cs0_cs1;" \
- "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
- "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
- "netdev=eth0\0" \
- "uboot=" CONFIG_UBOOTPATH "\0" \
- "ubootaddr=" __stringify(CONFIG_TEXT_BASE) "\0" \
- "tftpflash=tftpboot $loadaddr $uboot && " \
- "protect off $ubootaddr +$filesize && " \
- "erase $ubootaddr +$filesize && " \
- "cp.b $loadaddr $ubootaddr $filesize && " \
- "protect on $ubootaddr +$filesize && " \
- "cmp.b $loadaddr $ubootaddr $filesize\0" \
- "consoledev=ttyS0\0" \
- "ramdiskaddr=2000000\0" \
- "ramdiskfile=" __stringify(RAMDISKFILE) "\0" \
- "fdtaddr=1e00000\0" \
- "fdtfile=" __stringify(FDTFILE) "\0" \
- "bdev=sda3\0"
-
-#include <asm/fsl_secure_boot.h>
-
-#endif /* __CONFIG_H */
--
2.47.3
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH 08/26] powerpc: mpc85xx: Remove P3041 support
2026-10-09 19:36 [PATCH 00/26] powerpc: drop EOL boards and SoCs, take over maintenance Bradley Morgan
` (6 preceding siblings ...)
2026-10-09 19:36 ` [PATCH 07/26] board: powerpc: Remove T1042D4RDB support Bradley Morgan
@ 2026-10-09 19:36 ` Bradley Morgan
2026-10-09 19:36 ` [PATCH 09/26] powerpc: mpc85xx: Remove P4080 support Bradley Morgan
` (17 subsequent siblings)
25 siblings, 0 replies; 31+ messages in thread
From: Bradley Morgan @ 2026-10-09 19:36 UTC (permalink / raw)
To: Tom Rini, u-boot
Cc: Bradley Morgan, Marek Behún, Marek Mojík,
NXP i . MX U-Boot Team, Alexey Charkov, Anshul Dalal,
Daniel Golle, Fabio Estevam, Gaurav Jain, Ilias Apalodimas,
Jaehoon Chung, James Hilliard, Jerome Forissier, Johan Jonker,
Lukasz Majewski, Marek Vasut, Mario Six, Michael Walle,
Michal Simek, Neil Armstrong, Peng Fan, Pengpeng Hou,
Priyanka Jain, Quentin Schulz, Simon Glass, Stefano Babic,
Tanmay Kathpalia, Torsten Rupp, Vincent Jardin, Weijie Gao
The P3041DS was the last user in the tree of ARCH_P3041. NXP lists the processor and development system as no longer manufactured.
Nothing selects the SoC option now. Drop its remaining CPU, SERDES, FM and errata support.
Signed-off-by: Bradley Morgan <brads@mainlining.org>
---
arch/Kconfig.nxp | 3 +-
arch/powerpc/cpu/mpc85xx/Kconfig | 45 +-------
arch/powerpc/cpu/mpc85xx/Makefile | 2 -
arch/powerpc/cpu/mpc85xx/cmd_errata.c | 6 +-
arch/powerpc/cpu/mpc85xx/cpu_init.c | 4 +-
arch/powerpc/cpu/mpc85xx/p3041_ids.c | 112 ------------------
arch/powerpc/cpu/mpc85xx/p3041_serdes.c | 133 ----------------------
arch/powerpc/cpu/mpc85xx/release.S | 2 +-
arch/powerpc/cpu/mpc8xxx/cpu.c | 1 -
arch/powerpc/include/asm/config_mpc85xx.h | 10 --
arch/powerpc/include/asm/immap_85xx.h | 3 +-
arch/powerpc/include/asm/processor.h | 1 -
doc/README.pblimage | 6 +-
drivers/net/Kconfig | 1 -
drivers/net/fm/Makefile | 3 +-
drivers/usb/common/fsl-errata.c | 5 -
16 files changed, 15 insertions(+), 322 deletions(-)
delete mode 100644 arch/powerpc/cpu/mpc85xx/p3041_ids.c
delete mode 100644 arch/powerpc/cpu/mpc85xx/p3041_serdes.c
diff --git a/arch/Kconfig.nxp b/arch/Kconfig.nxp
index 152692e3230..ff645aea0d3 100644
--- a/arch/Kconfig.nxp
+++ b/arch/Kconfig.nxp
@@ -5,8 +5,7 @@ config FSL_TRUST_ARCH_v1
config NXP_ESBC
bool "NXP ESBC (secure boot) functionality"
- select FSL_TRUST_ARCH_v1 if ARCH_P3041 || ARCH_P4080 || \
- ARCH_P5040 || ARCH_P2041
+ select FSL_TRUST_ARCH_v1 if ARCH_P4080 || ARCH_P5040 || ARCH_P2041
help
Enable Freescale Secure Boot feature. Normally selected by defconfig.
If unsure, do not change.
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index 7fee93862c7..ab80a1ab317 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -584,41 +584,6 @@ config ARCH_P2041
select FSL_ELBC
imply CMD_NAND
-config ARCH_P3041
- bool
- select BACKSIDE_L2_CACHE
- select E500MC
- select FSL_CORENET
- select FSL_LAW
- select SYS_CACHE_SHIFT_6
- select SYS_FSL_DDR_VER_44
- select SYS_FSL_ERRATUM_A004510
- select SYS_FSL_ERRATUM_A004849
- select SYS_FSL_ERRATUM_A005275
- select SYS_FSL_ERRATUM_A005812
- select SYS_FSL_ERRATUM_A006261
- select SYS_FSL_ERRATUM_CPU_A003999
- select SYS_FSL_ERRATUM_DDR_A003
- select SYS_FSL_ERRATUM_DDR_A003474
- select SYS_FSL_ERRATUM_ESDHC111
- select SYS_FSL_ERRATUM_I2C_A004447
- select SYS_FSL_ERRATUM_NMG_CPU_A011
- select SYS_FSL_ERRATUM_SRIO_A004034
- select SYS_FSL_ERRATUM_USB14
- select SYS_FSL_HAS_DDR3
- select SYS_FSL_HAS_SEC
- select SYS_FSL_QORIQ_CHASSIS1
- select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22
- select SYS_FSL_SEC_BE
- select SYS_FSL_SEC_COMPAT_4
- select SYS_FSL_USB1_PHY_ENABLE
- select SYS_FSL_USB2_PHY_ENABLE
- select FSL_ELBC
- imply CMD_NAND
- imply SATA
- imply CMD_REGINFO
- imply FSL_SATA
-
config ARCH_P4080
bool
select BACKSIDE_L2_CACHE
@@ -929,7 +894,6 @@ config MAX_CPUS
default 8 if ARCH_P4080
default 4 if ARCH_B4860 || \
ARCH_P2041 || \
- ARCH_P3041 || \
ARCH_P5040 || \
ARCH_T1040 || \
ARCH_T1042 || \
@@ -971,7 +935,6 @@ config SYS_CCSRBAR_DEFAULT
default 0xfe000000 if ARCH_B4420 || \
ARCH_B4860 || \
ARCH_P2041 || \
- ARCH_P3041 || \
ARCH_P4080 || \
ARCH_P5040 || \
ARCH_T1024 || \
@@ -1036,7 +999,7 @@ config SYS_FSL_ERRATUM_A004510_SVR_REV
config SYS_FSL_ERRATUM_A004510_SVR_REV2
hex
- depends on (SYS_FSL_ERRATUM_A004510 && (ARCH_P2041 || ARCH_P3041))
+ depends on (SYS_FSL_ERRATUM_A004510 && ARCH_P2041)
default 0x11
config SYS_FSL_ERRATUM_A005125
@@ -1111,7 +1074,7 @@ config SYS_FSL_A004447_SVR_REV
depends on SYS_FSL_ERRATUM_I2C_A004447
default 0x10 if ARCH_P1010
default 0x11 if ARCH_P1023 || ARCH_P2041 || ARCH_BSC9132
- default 0x20 if ARCH_P3041 || ARCH_P4080
+ default 0x20 if ARCH_P4080
config SYS_FSL_ERRATUM_IFC_A002769
bool
@@ -1188,7 +1151,6 @@ config SYS_FSL_NUM_LAWS
default 32 if ARCH_B4420 || \
ARCH_B4860 || \
ARCH_P2041 || \
- ARCH_P3041 || \
ARCH_P4080 || \
ARCH_P5040 || \
ARCH_T2080 || \
@@ -1353,7 +1315,6 @@ config SYS_FSL_LBC_CLK_DIV
ARCH_MPC8560
default 2 if ARCH_P2041 || \
- ARCH_P3041 || \
ARCH_P4080 || \
ARCH_P5040
default 1
@@ -1416,7 +1377,7 @@ config SYS_FSL_SRIO_LIODN
config SYS_FSL_TBCLK_DIV
int
- default 32 if ARCH_P2041 || ARCH_P3041
+ default 32 if ARCH_P2041
default 16 if ARCH_P4080 || ARCH_P5040 || ARCH_T4240 || ARCH_B4860 || \
ARCH_B4420 || ARCH_T1040 || ARCH_T1042 || \
ARCH_T1024 || ARCH_T2080
diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile
index 6717e2c4578..664e566b06e 100644
--- a/arch/powerpc/cpu/mpc85xx/Makefile
+++ b/arch/powerpc/cpu/mpc85xx/Makefile
@@ -37,7 +37,6 @@ obj-$(CONFIG_SYS_DPAA_QBMAN) += portals.o
# various SoC specific assignments
obj-$(CONFIG_ARCH_P2041) += p2041_ids.o
-obj-$(CONFIG_ARCH_P3041) += p3041_ids.o
obj-$(CONFIG_ARCH_P4080) += p4080_ids.o
obj-$(CONFIG_ARCH_P5040) += p5040_ids.o
obj-$(CONFIG_ARCH_T4240) += t4240_ids.o
@@ -66,7 +65,6 @@ obj-$(CONFIG_ARCH_P1024) += p1021_serdes.o
obj-$(CONFIG_ARCH_P1025) += p1021_serdes.o
obj-$(CONFIG_ARCH_P2020) += p2020_serdes.o
obj-$(CONFIG_ARCH_P2041) += p2041_serdes.o
-obj-$(CONFIG_ARCH_P3041) += p3041_serdes.o
obj-$(CONFIG_ARCH_P4080) += p4080_serdes.o
obj-$(CONFIG_ARCH_P5040) += p5040_serdes.o
obj-$(CONFIG_ARCH_T4240) += t4240_serdes.o
diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
index f91a4d441d3..52de04323c9 100644
--- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
+++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
@@ -25,7 +25,7 @@ static void check_erratum_a4849(uint32_t svr)
void __iomem *dcsr = (void *)CFG_SYS_DCSRBAR + 0xb0000;
unsigned int i;
-#if defined(CONFIG_ARCH_P2041) || defined(CONFIG_ARCH_P3041)
+#ifdef CONFIG_ARCH_P2041
static const uint8_t offsets[] = {
0x50, 0x54, 0x58, 0x90, 0x94, 0x98
};
@@ -44,7 +44,7 @@ static void check_erratum_a4849(uint32_t svr)
}
}
-#if defined(CONFIG_ARCH_P2041) || defined(CONFIG_ARCH_P3041)
+#ifdef CONFIG_ARCH_P2041
x108 = 0x12;
#endif
@@ -162,7 +162,7 @@ static int do_errata(struct cmd_tbl *cmdtp, int flag, int argc,
#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
/*
* NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0
- * also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1
+ * also applies to P2041 rev 1.0, 1.1
* The SVR has been checked by cpu_init_r().
*/
if (enable_cpu_a011_workaround)
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 4390f754809..6d150cb8ba2 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -659,8 +659,8 @@ int cpu_init_r(void)
* CPU22 and NMG_CPU_A011 share the same workaround.
* CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0
* NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0
- * also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1, both
- * fixed in 2.0. NMG_CPU_A011 is activated by default and can
+ * also applies to P2041 rev 1.0, 1.1, fixed in 2.0.
+ * NMG_CPU_A011 is activated by default and can
* be disabled by hwconfig with syntax:
*
* fsl_cpu_a011:disable
diff --git a/arch/powerpc/cpu/mpc85xx/p3041_ids.c b/arch/powerpc/cpu/mpc85xx/p3041_ids.c
deleted file mode 100644
index 0675a59414b..00000000000
--- a/arch/powerpc/cpu/mpc85xx/p3041_ids.c
+++ /dev/null
@@ -1,112 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2010-2011 Freescale Semiconductor, Inc.
- */
-
-#include <config.h>
-#include <linux/kernel.h>
-#include <asm/fsl_portals.h>
-#include <asm/fsl_liodn.h>
-
-#ifdef CONFIG_SYS_DPAA_QBMAN
-struct qportal_info qp_info[CFG_SYS_QMAN_NUM_PORTALS] = {
- /* dqrr liodn, frame data liodn, liodn off, sdest */
- SET_QP_INFO(1, 2, 1, 0),
- SET_QP_INFO(3, 4, 2, 1),
- SET_QP_INFO(5, 6, 3, 2),
- SET_QP_INFO(7, 8, 4, 3),
- SET_QP_INFO(9, 10, 5, 0),
- SET_QP_INFO(1, 12, 6, 1),
- SET_QP_INFO(13, 14, 7, 2),
- SET_QP_INFO(15, 16, 8, 3),
- SET_QP_INFO(17, 18, 9, 0), /* for now sdest to 0 */
- SET_QP_INFO(19, 20, 10, 0), /* for now sdest to 0 */
-};
-#endif
-
-struct srio_liodn_id_table srio_liodn_tbl[] = {
- SET_SRIO_LIODN_2(1, 199, 200),
- SET_SRIO_LIODN_2(2, 201, 202),
-};
-int srio_liodn_tbl_sz = ARRAY_SIZE(srio_liodn_tbl);
-
-struct liodn_id_table liodn_tbl[] = {
-#ifdef CONFIG_SYS_DPAA_QBMAN
- SET_QMAN_LIODN(31),
- SET_BMAN_LIODN(32),
-#endif
-
- SET_SDHC_LIODN(1, 64),
-
- SET_PME_LIODN(117),
-
- SET_USB_LIODN(1, "fsl-usb2-mph", 125),
- SET_USB_LIODN(2, "fsl-usb2-dr", 126),
-
- SET_SATA_LIODN(1, 127),
- SET_SATA_LIODN(2, 128),
-
- SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 1, 193),
- SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 2, 194),
- SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 3, 195),
- SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 4, 196),
-
- SET_DMA_LIODN(1, "fsl,eloplus-dma", 197),
- SET_DMA_LIODN(2, "fsl,eloplus-dma", 198),
-
- SET_GUTS_LIODN("fsl,rapidio-delta", 199, rio1liodnr, 0),
- SET_GUTS_LIODN(NULL, 200, rio2liodnr, 0),
- SET_GUTS_LIODN(NULL, 201, rio1maintliodnr, 0),
- SET_GUTS_LIODN(NULL, 202, rio2maintliodnr, 0),
-};
-int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl);
-
-#ifdef CONFIG_SYS_DPAA_FMAN
-struct fman_liodn_id_table fman1_liodn_tbl[] = {
- SET_FMAN_RX_1G_LIODN(1, 0, 10),
- SET_FMAN_RX_1G_LIODN(1, 1, 11),
- SET_FMAN_RX_1G_LIODN(1, 2, 12),
- SET_FMAN_RX_1G_LIODN(1, 3, 13),
- SET_FMAN_RX_1G_LIODN(1, 4, 14),
- SET_FMAN_RX_10G_LIODN(1, 0, 15),
-};
-int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl);
-#endif
-
-struct liodn_id_table sec_liodn_tbl[] = {
- SET_SEC_JR_LIODN_ENTRY(0, 129, 130),
- SET_SEC_JR_LIODN_ENTRY(1, 131, 132),
- SET_SEC_JR_LIODN_ENTRY(2, 133, 134),
- SET_SEC_JR_LIODN_ENTRY(3, 135, 136),
- SET_SEC_RTIC_LIODN_ENTRY(a, 154),
- SET_SEC_RTIC_LIODN_ENTRY(b, 155),
- SET_SEC_RTIC_LIODN_ENTRY(c, 156),
- SET_SEC_RTIC_LIODN_ENTRY(d, 157),
- SET_SEC_DECO_LIODN_ENTRY(0, 97, 98),
- SET_SEC_DECO_LIODN_ENTRY(1, 99, 100),
-};
-int sec_liodn_tbl_sz = ARRAY_SIZE(sec_liodn_tbl);
-
-#ifdef CONFIG_SYS_DPAA_RMAN
-struct liodn_id_table rman_liodn_tbl[] = {
- /* Set RMan block 0-3 liodn offset */
- SET_RMAN_LIODN(0, 6),
- SET_RMAN_LIODN(1, 7),
- SET_RMAN_LIODN(2, 8),
- SET_RMAN_LIODN(3, 9),
-};
-int rman_liodn_tbl_sz = ARRAY_SIZE(rman_liodn_tbl);
-#endif
-
-struct liodn_id_table liodn_bases[] = {
- [FSL_HW_PORTAL_SEC] = SET_LIODN_BASE_2(64, 100),
-#ifdef CONFIG_SYS_DPAA_FMAN
- [FSL_HW_PORTAL_FMAN1] = SET_LIODN_BASE_1(32),
-#endif
-#ifdef CONFIG_SYS_DPAA_PME
- [FSL_HW_PORTAL_PME] = SET_LIODN_BASE_2(136, 172),
-#endif
-#ifdef CONFIG_SYS_DPAA_RMAN
- [FSL_HW_PORTAL_RMAN] = SET_LIODN_BASE_1(80),
-#endif
-};
diff --git a/arch/powerpc/cpu/mpc85xx/p3041_serdes.c b/arch/powerpc/cpu/mpc85xx/p3041_serdes.c
deleted file mode 100644
index b1586f110e8..00000000000
--- a/arch/powerpc/cpu/mpc85xx/p3041_serdes.c
+++ /dev/null
@@ -1,133 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2009-2011 Freescale Semiconductor, Inc.
- */
-
-#include <asm/fsl_serdes.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include "fsl_corenet_serdes.h"
-
-static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = {
- [0x2] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2,
- PCIE4, AURORA, PCIE3, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3,
- SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2, },
- [0x4] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1,
- PCIE2, AURORA, PCIE3, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3,
- SGMII_FM1_DTSEC4, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, },
- [0xb] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO2, SRIO2, SRIO1, SRIO1,
- PCIE2, AURORA, PCIE3, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3,
- SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2, },
- [0x10] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1,
- AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1,
- NONE, NONE, SATA1, SATA2, },
- [0x11] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2,
- AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
- SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2, },
- [0x13] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2,
- AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
- SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, XAUI_FM1, XAUI_FM1,
- XAUI_FM1, XAUI_FM1, },
- [0x14] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2,
- AURORA, AURORA, PCIE3, PCIE3, PCIE3, PCIE3,
- SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3,
- SGMII_FM1_DTSEC4, },
- [0x15] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2,
- AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1,
- NONE, NONE, SATA1, SATA2, },
- [0x16] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2,
- AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
- SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, SRIO1, SRIO1, SRIO1,
- SRIO1, },
- [0x17] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1,
- AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
- SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2, },
- [0x18] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1,
- AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
- SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5, NONE,
- NONE, NONE, },
- [0x1b] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1,
- AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1,
- NONE, NONE, SATA1, SATA2, },
- [0x1d] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1,
- AURORA, AURORA, PCIE3, PCIE3, PCIE3, PCIE3, NONE, NONE,
- SATA1, SATA2, },
- [0x20] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1,
- AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
- SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, XAUI_FM1, XAUI_FM1,
- XAUI_FM1, XAUI_FM1, },
- [0x21] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1,
- AURORA, AURORA, PCIE3, PCIE3, PCIE3, PCIE3,
- SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3,
- SGMII_FM1_DTSEC4, },
- [0x22] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1,
- AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1,
- NONE, NONE, SATA1, SATA2, },
- [0x23] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO2, SRIO2, SRIO1, SRIO1,
- AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
- SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2, },
- [0x24] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO2, SRIO2, SRIO1, SRIO1,
- AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
- SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5, NONE,
- NONE, NONE, },
- [0x28] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2, PCIE2, PCIE2,
- AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
- SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2, },
- [0x29] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2, PCIE2, PCIE2,
- AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
- SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5, NONE,
- NONE, NONE, },
- [0x2a] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2, PCIE2, PCIE2,
- AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
- SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, XAUI_FM1, XAUI_FM1,
- XAUI_FM1, XAUI_FM1, },
- [0x2b] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2, PCIE2, PCIE2,
- AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1,
- NONE, NONE, SATA1, SATA2, },
- [0x2f] = {PCIE1, PCIE1, PCIE3, PCIE3, SRIO2, SRIO2, SRIO1, SRIO1,
- AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1,
- NONE, NONE, SATA1, SATA2, },
- [0x31] = {PCIE1, PCIE1, PCIE3, PCIE3, SRIO1, SRIO1, SRIO1, SRIO1,
- AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
- SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5, NONE,
- NONE, NONE, },
- [0x33] = {PCIE1, PCIE1, PCIE3, PCIE3, SRIO1, SRIO1, SRIO1, SRIO1,
- AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1,
- NONE, NONE, SATA1, SATA2, },
- [0x34] = {PCIE1, PCIE1, PCIE1, PCIE1, SGMII_FM1_DTSEC1,
- SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, AURORA,
- AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, NONE,
- NONE, SATA1, SATA2, },
- [0x35] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2,
- SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, AURORA, AURORA, XAUI_FM1,
- XAUI_FM1, XAUI_FM1, XAUI_FM1, NONE, NONE, SATA1, SATA2, },
- [0x36] = {PCIE1, PCIE1, PCIE3, PCIE3, SGMII_FM1_DTSEC1,
- SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, AURORA,
- AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, NONE,
- NONE, SATA1, SATA2, },
- [0x37] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2,
- SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, AURORA, AURORA, XAUI_FM1,
- XAUI_FM1, XAUI_FM1, XAUI_FM1, NONE, NONE, SATA1, SATA2, },
-};
-
-enum srds_prtcl serdes_get_prtcl(int cfg, int lane)
-{
- if (!serdes_lane_enabled(lane))
- return NONE;
-
- return serdes_cfg_tbl[cfg][lane];
-}
-
-int is_serdes_prtcl_valid(u32 prtcl) {
- int i;
-
- if (prtcl >= ARRAY_SIZE(serdes_cfg_tbl))
- return 0;
-
- for (i = 0; i < SRDS_MAX_LANES; i++) {
- if (serdes_cfg_tbl[prtcl][i] != NONE)
- return 1;
- }
-
- return 0;
-}
diff --git a/arch/powerpc/cpu/mpc85xx/release.S b/arch/powerpc/cpu/mpc85xx/release.S
index 391751ce1e7..078d8cf3f34 100644
--- a/arch/powerpc/cpu/mpc85xx/release.S
+++ b/arch/powerpc/cpu/mpc85xx/release.S
@@ -208,7 +208,7 @@ __secondary_start_page:
/*
* CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0
* NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0
- * also appleis to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1
+ * also applies to P2041 rev 1.0, 1.1
*/
mfspr r3,SPRN_SVR
rlwinm r6,r3,24,~0x800 /* clear E bit */
diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c
index d64eb7328fe..b8bec9ed2e8 100644
--- a/arch/powerpc/cpu/mpc8xxx/cpu.c
+++ b/arch/powerpc/cpu/mpc8xxx/cpu.c
@@ -56,7 +56,6 @@ static struct cpu_type cpu_type_list[] = {
CPU_TYPE_ENTRY(P2020, P2020, 2),
CPU_TYPE_ENTRY(P2040, P2040, 4),
CPU_TYPE_ENTRY(P2041, P2041, 4),
- CPU_TYPE_ENTRY(P3041, P3041, 4),
CPU_TYPE_ENTRY(P4040, P4040, 4),
CPU_TYPE_ENTRY(P4080, P4080, 8),
CPU_TYPE_ENTRY(P5010, P5010, 1),
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index d7d18c3eeca..07be48d518d 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -44,16 +44,6 @@
#define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5
#define CFG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
-#elif defined(CONFIG_ARCH_P3041)
-#define CFG_SYS_NUM_FMAN 1
-#define CFG_SYS_NUM_FM1_DTSEC 5
-#define CFG_SYS_NUM_FM1_10GEC 1
-#define CFG_SYS_FM_MURAM_SIZE 0x28000
-#define CFG_SYS_FSL_SRIO_MAX_PORTS 2
-#define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9
-#define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5
-#define CFG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
-
#elif defined(CONFIG_ARCH_P4080) /* also supports P4040 */
#define CFG_SYS_NUM_FMAN 2
#define CFG_SYS_NUM_FM1_DTSEC 4
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index 9e082a87a3b..e1d1ca80092 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1522,8 +1522,7 @@ typedef struct ccsr_gur {
#define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC2 0x00080000
#define FSL_CORENET_RCWSR11_EC2_USB2 0x00100000
#endif
-#if defined(CONFIG_ARCH_P2041) || \
- defined(CONFIG_ARCH_P3041)
+#if defined(CONFIG_ARCH_P2041)
#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_RGMII 0x00000000
#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_MII 0x00800000
#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_NONE 0x00c00000
diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h
index 2357734a5be..31d52f3b734 100644
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -1048,7 +1048,6 @@
#define SVR_P2020 0x80E200
#define SVR_P2040 0x821000
#define SVR_P2041 0x821001
-#define SVR_P3041 0x821103
#define SVR_P4040 0x820100
#define SVR_P4080 0x820000
#define SVR_P5010 0x822100
diff --git a/doc/README.pblimage b/doc/README.pblimage
index e99b010d262..7145622b575 100644
--- a/doc/README.pblimage
+++ b/doc/README.pblimage
@@ -14,15 +14,15 @@ Building PBL Boot Image and boot steps
1. Building PBL Boot Image.
The default Image is u-boot.pbl.
- For eSPI boot(available on P2041/P3041/P4080/P5020/P5040/T4240):
+ For eSPI boot(available on P2041/P4080/P5020/P5040/T4240):
To build the eSPI boot image:
make <board_name>_SPIFLASH
- For SD boot(available on P2041/P3041/P4080/P5020/P5040/T4240):
+ For SD boot(available on P2041/P4080/P5020/P5040/T4240):
To build the SD boot image:
make <board_name>_SDCARD
- For Nand boot(available on P2041/P3041/P5020/P5040):
+ For Nand boot(available on P2041/P5020/P5040):
To build the NAND boot image:
make <board_name>_NAND
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index c057504cf66..fb0dc39cf35 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -970,7 +970,6 @@ config SYS_DPAA_QBMAN
ARCH_T2080 || \
ARCH_T4240 || \
ARCH_P4080 || \
- ARCH_P3041 || \
ARCH_P5040 || \
ARCH_LS1043A || \
ARCH_LS1046A
diff --git a/drivers/net/fm/Makefile b/drivers/net/fm/Makefile
index b34209d2b3e..af8fca353a9 100644
--- a/drivers/net/fm/Makefile
+++ b/drivers/net/fm/Makefile
@@ -14,9 +14,8 @@ obj-$(CONFIG_SYS_FMAN_V3) += memac.o
# SoC specific SERDES support
obj-$(CONFIG_ARCH_P1023) += p1023.o
-# The P204x, P304x, and P5020 are the same
+# The P204x and P5020 are the same
obj-$(CONFIG_ARCH_P2041) += p5020.o
-obj-$(CONFIG_ARCH_P3041) += p5020.o
obj-$(CONFIG_ARCH_P4080) += p4080.o
obj-$(CONFIG_ARCH_P5040) += p5040.o
obj-$(CONFIG_ARCH_T1040) += t1040.o
diff --git a/drivers/usb/common/fsl-errata.c b/drivers/usb/common/fsl-errata.c
index 66ff93b2982..e2f0563e33c 100644
--- a/drivers/usb/common/fsl-errata.c
+++ b/drivers/usb/common/fsl-errata.c
@@ -54,7 +54,6 @@ bool has_erratum_a005275(void)
switch (soc) {
#ifdef CONFIG_PPC
- case SVR_P3041:
case SVR_P2041:
case SVR_P2040:
return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 1, 1);
@@ -85,10 +84,6 @@ bool has_erratum_a006261(void)
return IS_SVR_REV(svr, 1, 0) ||
IS_SVR_REV(svr, 1, 1) ||
IS_SVR_REV(svr, 2, 0) || IS_SVR_REV(svr, 2, 1);
- case SVR_P3041:
- return IS_SVR_REV(svr, 1, 0) ||
- IS_SVR_REV(svr, 1, 1) ||
- IS_SVR_REV(svr, 2, 0) || IS_SVR_REV(svr, 2, 1);
case SVR_P5010:
case SVR_P5020:
case SVR_P5021:
--
2.47.3
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH 09/26] powerpc: mpc85xx: Remove P4080 support
2026-10-09 19:36 [PATCH 00/26] powerpc: drop EOL boards and SoCs, take over maintenance Bradley Morgan
` (7 preceding siblings ...)
2026-10-09 19:36 ` [PATCH 08/26] powerpc: mpc85xx: Remove P3041 support Bradley Morgan
@ 2026-10-09 19:36 ` Bradley Morgan
2026-10-09 19:36 ` [PATCH 10/26] powerpc: mpc85xx: Remove P5040 support Bradley Morgan
` (16 subsequent siblings)
25 siblings, 0 replies; 31+ messages in thread
From: Bradley Morgan @ 2026-10-09 19:36 UTC (permalink / raw)
To: Tom Rini, u-boot
Cc: Bradley Morgan, Marek Behún, Marek Mojík,
NXP i . MX U-Boot Team, Alexey Charkov, Anshul Dalal,
Daniel Golle, Fabio Estevam, Gaurav Jain, Ilias Apalodimas,
Jaehoon Chung, James Hilliard, Jerome Forissier, Johan Jonker,
Lukasz Majewski, Marek Vasut, Mario Six, Michael Walle,
Michal Simek, Neil Armstrong, Peng Fan, Pengpeng Hou,
Priyanka Jain, Quentin Schulz, Simon Glass, Stefano Babic,
Tanmay Kathpalia, Torsten Rupp, Vincent Jardin, Weijie Gao
The P4080DS was the last user in the tree of ARCH_P4080. NXP lists both the processor family and development system as end of life.
Nothing selects the option now. Drop its dedicated FM and SERDES support, errata workarounds and remaining platform hooks.
Signed-off-by: Bradley Morgan <brads@mainlining.org>
---
arch/Kconfig.nxp | 2 +-
arch/powerpc/cpu/mpc85xx/Kconfig | 73 +--
arch/powerpc/cpu/mpc85xx/Makefile | 2 -
arch/powerpc/cpu/mpc85xx/cmd_errata.c | 39 +-
arch/powerpc/cpu/mpc85xx/cpu_init.c | 19 +-
arch/powerpc/cpu/mpc85xx/fdt.c | 22 -
arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c | 600 ------------------
arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.h | 4 -
arch/powerpc/cpu/mpc85xx/p4080_ids.c | 112 ----
arch/powerpc/cpu/mpc85xx/p4080_serdes.c | 80 ---
arch/powerpc/cpu/mpc85xx/release.S | 23 +-
arch/powerpc/cpu/mpc8xxx/cpu.c | 1 -
arch/powerpc/include/asm/config_mpc85xx.h | 13 -
arch/powerpc/include/asm/fsl_serdes.h | 3 -
arch/powerpc/include/asm/immap_85xx.h | 16 -
arch/powerpc/include/asm/processor.h | 1 -
doc/README.pblimage | 4 +-
drivers/ddr/fsl/Kconfig | 1 -
drivers/net/Kconfig | 1 -
drivers/net/fm/Makefile | 1 -
drivers/net/fm/p4080.c | 98 ---
drivers/pci/pcie_fsl.c | 23 -
drivers/usb/common/fsl-errata.c | 4 -
drivers/usb/host/Kconfig | 2 +-
24 files changed, 13 insertions(+), 1131 deletions(-)
delete mode 100644 arch/powerpc/cpu/mpc85xx/p4080_ids.c
delete mode 100644 arch/powerpc/cpu/mpc85xx/p4080_serdes.c
delete mode 100644 drivers/net/fm/p4080.c
diff --git a/arch/Kconfig.nxp b/arch/Kconfig.nxp
index ff645aea0d3..6b1ad1795fa 100644
--- a/arch/Kconfig.nxp
+++ b/arch/Kconfig.nxp
@@ -5,7 +5,7 @@ config FSL_TRUST_ARCH_v1
config NXP_ESBC
bool "NXP ESBC (secure boot) functionality"
- select FSL_TRUST_ARCH_v1 if ARCH_P4080 || ARCH_P5040 || ARCH_P2041
+ select FSL_TRUST_ARCH_v1 if ARCH_P5040 || ARCH_P2041
help
Enable Freescale Secure Boot feature. Normally selected by defconfig.
If unsure, do not change.
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index ab80a1ab317..252666cab5f 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -584,49 +584,6 @@ config ARCH_P2041
select FSL_ELBC
imply CMD_NAND
-config ARCH_P4080
- bool
- select BACKSIDE_L2_CACHE
- select E500MC
- select FSL_CORENET
- select FSL_LAW
- select SYS_CACHE_SHIFT_6
- select SYS_FSL_DDR_VER_44
- select SYS_FSL_ERRATUM_A004510
- select SYS_FSL_ERRATUM_A004580
- select SYS_FSL_ERRATUM_A004849
- select SYS_FSL_ERRATUM_A005812
- select SYS_FSL_ERRATUM_A007075
- select SYS_FSL_ERRATUM_CPC_A002
- select SYS_FSL_ERRATUM_CPC_A003
- select SYS_FSL_ERRATUM_CPU_A003999
- select SYS_FSL_ERRATUM_DDR_A003
- select SYS_FSL_ERRATUM_DDR_A003474
- select SYS_FSL_ERRATUM_ELBC_A001
- select SYS_FSL_ERRATUM_ESDHC111
- select SYS_FSL_ERRATUM_ESDHC13
- select SYS_FSL_ERRATUM_ESDHC135
- select SYS_FSL_ERRATUM_I2C_A004447
- select SYS_FSL_ERRATUM_NMG_CPU_A011
- select SYS_FSL_ERRATUM_SRIO_A004034
- select SYS_FSL_PCIE_COMPAT_P4080_PCIE
- select SYS_P4080_ERRATUM_CPU22
- select SYS_P4080_ERRATUM_PCIE_A003
- select SYS_P4080_ERRATUM_SERDES8
- select SYS_P4080_ERRATUM_SERDES9
- select SYS_P4080_ERRATUM_SERDES_A001
- select SYS_P4080_ERRATUM_SERDES_A005
- select SYS_FSL_HAS_DDR3
- select SYS_FSL_HAS_SEC
- select SYS_FSL_QORIQ_CHASSIS1
- select SYS_FSL_RMU
- select SYS_FSL_SEC_BE
- select SYS_FSL_SEC_COMPAT_4
- select FSL_ELBC
- imply SATA
- imply CMD_REGINFO
- imply SATA_SIL
-
config ARCH_P5040
bool
select BACKSIDE_L2_CACHE
@@ -891,7 +848,6 @@ config HETROGENOUS_CLUSTERS
config MAX_CPUS
int "Maximum number of CPUs permitted for MPC85xx"
default 12 if ARCH_T4240
- default 8 if ARCH_P4080
default 4 if ARCH_B4860 || \
ARCH_P2041 || \
ARCH_P5040 || \
@@ -935,7 +891,6 @@ config SYS_CCSRBAR_DEFAULT
default 0xfe000000 if ARCH_B4420 || \
ARCH_B4860 || \
ARCH_P2041 || \
- ARCH_P4080 || \
ARCH_P5040 || \
ARCH_T1024 || \
ARCH_T1040 || \
@@ -994,7 +949,6 @@ config SYS_FSL_ERRATUM_A004510
config SYS_FSL_ERRATUM_A004510_SVR_REV
hex
depends on SYS_FSL_ERRATUM_A004510
- default 0x20 if ARCH_P4080
default 0x10
config SYS_FSL_ERRATUM_A004510_SVR_REV2
@@ -1074,7 +1028,6 @@ config SYS_FSL_A004447_SVR_REV
depends on SYS_FSL_ERRATUM_I2C_A004447
default 0x10 if ARCH_P1010
default 0x11 if ARCH_P1023 || ARCH_P2041 || ARCH_BSC9132
- default 0x20 if ARCH_P4080
config SYS_FSL_ERRATUM_IFC_A002769
bool
@@ -1106,24 +1059,6 @@ config SYS_FSL_ERRATUM_SRIO_A004034
config SYS_FSL_ERRATUM_USB14
bool
-config SYS_P4080_ERRATUM_CPU22
- bool
-
-config SYS_P4080_ERRATUM_PCIE_A003
- bool
-
-config SYS_P4080_ERRATUM_SERDES8
- bool
-
-config SYS_P4080_ERRATUM_SERDES9
- bool
-
-config SYS_P4080_ERRATUM_SERDES_A001
- bool
-
-config SYS_P4080_ERRATUM_SERDES_A005
- bool
-
config FSL_PCIE_DISABLE_ASPM
bool
@@ -1151,7 +1086,6 @@ config SYS_FSL_NUM_LAWS
default 32 if ARCH_B4420 || \
ARCH_B4860 || \
ARCH_P2041 || \
- ARCH_P4080 || \
ARCH_P5040 || \
ARCH_T2080 || \
ARCH_T4240
@@ -1315,7 +1249,6 @@ config SYS_FSL_LBC_CLK_DIV
ARCH_MPC8560
default 2 if ARCH_P2041 || \
- ARCH_P4080 || \
ARCH_P5040
default 1
@@ -1346,9 +1279,6 @@ config SYS_FSL_CPC
config SYS_CACHE_STASHING
bool "Enable cache stashing"
-config SYS_FSL_PCIE_COMPAT_P4080_PCIE
- bool
-
config SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22
bool
@@ -1361,7 +1291,6 @@ config SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v30
config SYS_FSL_PCIE_COMPAT
string
depends on FSL_CORENET
- default "fsl,p4080-pcie" if SYS_FSL_PCIE_COMPAT_P4080_PCIE
default "fsl,qoriq-pcie-v2.2" if SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22
default "fsl,qoriq-pcie-v2.4" if SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24
default "fsl,qoriq-pcie-v3.0" if SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v30
@@ -1378,7 +1307,7 @@ config SYS_FSL_SRIO_LIODN
config SYS_FSL_TBCLK_DIV
int
default 32 if ARCH_P2041
- default 16 if ARCH_P4080 || ARCH_P5040 || ARCH_T4240 || ARCH_B4860 || \
+ default 16 if ARCH_P5040 || ARCH_T4240 || ARCH_B4860 || \
ARCH_B4420 || ARCH_T1040 || ARCH_T1042 || \
ARCH_T1024 || ARCH_T2080
default 8
diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile
index 664e566b06e..a3622d60b16 100644
--- a/arch/powerpc/cpu/mpc85xx/Makefile
+++ b/arch/powerpc/cpu/mpc85xx/Makefile
@@ -37,7 +37,6 @@ obj-$(CONFIG_SYS_DPAA_QBMAN) += portals.o
# various SoC specific assignments
obj-$(CONFIG_ARCH_P2041) += p2041_ids.o
-obj-$(CONFIG_ARCH_P4080) += p4080_ids.o
obj-$(CONFIG_ARCH_P5040) += p5040_ids.o
obj-$(CONFIG_ARCH_T4240) += t4240_ids.o
obj-$(CONFIG_ARCH_B4420) += b4860_ids.o
@@ -65,7 +64,6 @@ obj-$(CONFIG_ARCH_P1024) += p1021_serdes.o
obj-$(CONFIG_ARCH_P1025) += p1021_serdes.o
obj-$(CONFIG_ARCH_P2020) += p2020_serdes.o
obj-$(CONFIG_ARCH_P2041) += p2041_serdes.o
-obj-$(CONFIG_ARCH_P4080) += p4080_serdes.o
obj-$(CONFIG_ARCH_P5040) += p5040_serdes.o
obj-$(CONFIG_ARCH_T4240) += t4240_serdes.o
obj-$(CONFIG_ARCH_B4420) += b4860_serdes.o
diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
index 52de04323c9..73601a884c7 100644
--- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
+++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
@@ -20,7 +20,7 @@
* Array offsets[] contains a list of offsets within DCSR. According to the
* erratum document, the value at each offset should be 2.
*/
-static void check_erratum_a4849(uint32_t svr)
+static void check_erratum_a4849(void)
{
void __iomem *dcsr = (void *)CFG_SYS_DCSRBAR + 0xb0000;
unsigned int i;
@@ -29,11 +29,6 @@ static void check_erratum_a4849(uint32_t svr)
static const uint8_t offsets[] = {
0x50, 0x54, 0x58, 0x90, 0x94, 0x98
};
-#endif
-#ifdef CONFIG_ARCH_P4080
- static const uint8_t offsets[] = {
- 0x60, 0x64, 0x68, 0x6c, 0xa0, 0xa4, 0xa8, 0xac
- };
#endif
uint32_t x108; /* The value that should be at offset 0x108 */
@@ -48,17 +43,6 @@ static void check_erratum_a4849(uint32_t svr)
x108 = 0x12;
#endif
-#ifdef CONFIG_ARCH_P4080
- /*
- * For P4080, the erratum document says that the value at offset 0x108
- * should be 0x12 on rev2, or 0x1c on rev3.
- */
- if (SVR_MAJ(svr) == 2)
- x108 = 0x12;
- if (SVR_MAJ(svr) == 3)
- x108 = 0x1c;
-#endif
-
if (in_be32(dcsr + 0x108) != x108) {
printf("Work-around for Erratum A004849 is not enabled\n");
return;
@@ -146,23 +130,9 @@ static int do_errata(struct cmd_tbl *cmdtp, int flag, int argc,
}
#endif
-#if defined(CONFIG_SYS_P4080_ERRATUM_SERDES8)
- puts("Work-around for Erratum SERDES8 enabled\n");
-#endif
-#if defined(CONFIG_SYS_P4080_ERRATUM_SERDES9)
- puts("Work-around for Erratum SERDES9 enabled\n");
-#endif
-#if defined(CONFIG_SYS_P4080_ERRATUM_SERDES_A005)
- puts("Work-around for Erratum SERDES-A005 enabled\n");
-#endif
-#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22)
- if (SVR_MAJ(svr) < 3)
- puts("Work-around for Erratum CPU22 enabled\n");
-#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
/*
- * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0
- * also applies to P2041 rev 1.0, 1.1
+ * NMG_CPU_A011 applies to P2041 rev 1.0, 1.1, fixed in 2.0.
* The SVR has been checked by cpu_init_r().
*/
if (enable_cpu_a011_workaround)
@@ -258,15 +228,12 @@ static int do_errata(struct cmd_tbl *cmdtp, int flag, int argc,
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_A004849
/* This work-around is implemented in PBI, so just check for it */
- check_erratum_a4849(svr);
+ check_erratum_a4849();
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_A004580
/* This work-around is implemented in PBI, so just check for it */
check_erratum_a4580(svr);
#endif
-#ifdef CONFIG_SYS_P4080_ERRATUM_PCIE_A003
- puts("Work-around for Erratum PCIe-A003 enabled\n");
-#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_USB14
puts("Work-around for Erratum USB14 enabled\n");
#endif
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 6d150cb8ba2..e7e9b3dbd1c 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -653,22 +653,14 @@ int cpu_init_r(void)
#ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571
ccsr_sec_t __iomem *sec = (void *)CFG_SYS_FSL_SEC_ADDR;
#endif
-#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \
- defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011)
+#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
/*
- * CPU22 and NMG_CPU_A011 share the same workaround.
- * CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0
- * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0
- * also applies to P2041 rev 1.0, 1.1, fixed in 2.0.
- * NMG_CPU_A011 is activated by default and can
- * be disabled by hwconfig with syntax:
+ * NMG_CPU_A011 applies to P2041 rev 1.0 and 1.1, fixed in 2.0.
+ * It is enabled by default and can be disabled with:
*
* fsl_cpu_a011:disable
*/
extern int enable_cpu_a011_workaround;
-#ifdef CONFIG_SYS_P4080_ERRATUM_CPU22
- enable_cpu_a011_workaround = (SVR_MAJ(svr) < 3);
-#else
char buffer[HWCONFIG_BUFFER_SIZE];
char *buf = NULL;
int n, res;
@@ -685,11 +677,8 @@ int cpu_init_r(void)
printf("fsl_cpu_a011 was not found. hwconfig variable "
"may be too long\n");
}
- enable_cpu_a011_workaround =
- (SVR_SOC_VER(svr) == SVR_P4080 && SVR_MAJ(svr) < 3) ||
- (SVR_SOC_VER(svr) != SVR_P4080 && SVR_MAJ(svr) < 2);
+ enable_cpu_a011_workaround = SVR_MAJ(svr) < 2;
}
-#endif
if (enable_cpu_a011_workaround) {
flush_dcache();
mtspr(L1CSR2, (mfspr(L1CSR2) | L1CSR2_DCWS));
diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c
index 143b7c624d2..7de6a033ce2 100644
--- a/arch/powerpc/cpu/mpc85xx/fdt.c
+++ b/arch/powerpc/cpu/mpc85xx/fdt.c
@@ -504,27 +504,6 @@ static void ft_fixup_qe_snum(void *blob)
}
#endif
-#if defined(CONFIG_ARCH_P4080)
-static void fdt_fixup_usb(void *fdt)
-{
- ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
- u32 rcwsr11 = in_be32(&gur->rcwsr[11]);
- int off;
-
- off = fdt_node_offset_by_compatible(fdt, -1, "fsl,mpc85xx-usb2-mph");
- if ((rcwsr11 & FSL_CORENET_RCWSR11_EC1) !=
- FSL_CORENET_RCWSR11_EC1_FM1_USB1)
- fdt_status_disabled(fdt, off);
-
- off = fdt_node_offset_by_compatible(fdt, -1, "fsl,mpc85xx-usb2-dr");
- if ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) !=
- FSL_CORENET_RCWSR11_EC2_USB2)
- fdt_status_disabled(fdt, off);
-}
-#else
-#define fdt_fixup_usb(x)
-#endif
-
#if defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T4240)
void fdt_fixup_dma3(void *blob)
{
@@ -719,7 +698,6 @@ void ft_cpu_setup(void *blob, struct bd_info *bd)
do_fixup_by_compat_u32(blob, "fsl,p1010-flexcan",
"clock-frequency", gd->bus_clk/2, 1);
- fdt_fixup_usb(blob);
fdt_fixup_l2_switch(blob);
diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
index f2f854ebc12..0a66f376f86 100644
--- a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
@@ -4,62 +4,17 @@
*/
#include <config.h>
-#include <env.h>
#include <log.h>
#include <time.h>
-#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
-#include <hwconfig.h>
-#endif
#include <asm/fsl_serdes.h>
#include <asm/immap_85xx.h>
#include <asm/io.h>
-#include <asm/processor.h>
-#include <asm/fsl_law.h>
#include <linux/delay.h>
#include <linux/errno.h>
#include "fsl_corenet_serdes.h"
-/*
- * The work-arounds for erratum SERDES8 and SERDES-A001 are linked together.
- * The code is already very complicated as it is, and separating the two
- * completely would just make things worse. We try to keep them as separate
- * as possible, but for now we require SERDES8 if SERDES_A001 is defined.
- */
-#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A001
-#ifndef CONFIG_SYS_P4080_ERRATUM_SERDES8
-#error "CONFIG_SYS_P4080_ERRATUM_SERDES_A001 requires CONFIG_SYS_P4080_ERRATUM_SERDES8"
-#endif
-#endif
-
static u32 serdes_prtcl_map;
-#ifdef DEBUG
-static const char *serdes_prtcl_str[] = {
- [NONE] = "NA",
- [PCIE1] = "PCIE1",
- [PCIE2] = "PCIE2",
- [PCIE3] = "PCIE3",
- [PCIE4] = "PCIE4",
- [SATA1] = "SATA1",
- [SATA2] = "SATA2",
- [SRIO1] = "SRIO1",
- [SRIO2] = "SRIO2",
- [SGMII_FM1_DTSEC1] = "SGMII_FM1_DTSEC1",
- [SGMII_FM1_DTSEC2] = "SGMII_FM1_DTSEC2",
- [SGMII_FM1_DTSEC3] = "SGMII_FM1_DTSEC3",
- [SGMII_FM1_DTSEC4] = "SGMII_FM1_DTSEC4",
- [SGMII_FM1_DTSEC5] = "SGMII_FM1_DTSEC5",
- [SGMII_FM2_DTSEC1] = "SGMII_FM2_DTSEC1",
- [SGMII_FM2_DTSEC2] = "SGMII_FM2_DTSEC2",
- [SGMII_FM2_DTSEC3] = "SGMII_FM2_DTSEC3",
- [SGMII_FM2_DTSEC4] = "SGMII_FM2_DTSEC4",
- [SGMII_FM2_DTSEC5] = "SGMII_FM2_DTSEC5",
- [XAUI_FM1] = "XAUI_FM1",
- [XAUI_FM2] = "XAUI_FM2",
- [AURORA] = "DEBUG",
-};
-#endif
-
static const struct {
int idx;
unsigned int lpd; /* RCW lane powerdown bit */
@@ -79,17 +34,10 @@ static const struct {
{ 17, 163, FSL_SRDS_BANK_2 },
{ 18, 164, FSL_SRDS_BANK_2 },
{ 19, 165, FSL_SRDS_BANK_2 },
-#ifdef CONFIG_ARCH_P4080
- { 20, 170, FSL_SRDS_BANK_3 },
- { 21, 171, FSL_SRDS_BANK_3 },
- { 22, 172, FSL_SRDS_BANK_3 },
- { 23, 173, FSL_SRDS_BANK_3 },
-#else
{ 20, 166, FSL_SRDS_BANK_3 },
{ 21, 167, FSL_SRDS_BANK_3 },
{ 22, 168, FSL_SRDS_BANK_3 },
{ 23, 169, FSL_SRDS_BANK_3 },
-#endif
#if SRDS_MAX_BANK > 3
{ 24, 175, FSL_SRDS_BANK_4 },
{ 25, 176, FSL_SRDS_BANK_4 },
@@ -118,16 +66,6 @@ int serdes_lane_enabled(int lane)
if (in_be32(®s->bank[bank].rstctl) & SRDS_RSTCTL_SDPD)
return 0;
-#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
- /*
- * For banks two and three, use the srds_lpd_b[] array instead of the
- * RCW, because this array contains the real values of SRDS_LPD_B2 and
- * SRDS_LPD_B3.
- */
- if (bank > 0)
- return !(srds_lpd_b[bank] & (8 >> (lane - (6 + 4 * bank))));
-#endif
-
return !(in_be32(&gur->rcwsr[word]) & (0x80000000 >> bit));
}
@@ -180,285 +118,6 @@ int serdes_get_first_lane(enum srds_prtcl device)
return __serdes_get_first_lane(prtcl, device);
}
-#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9
-/*
- * Returns the SERDES bank (1, 2, or 3) that a given device is on for a given
- * SERDES protocol.
- *
- * Returns a negative error code if the given device is not supported for the
- * given SERDES protocol.
- */
-static int serdes_get_bank_by_device(uint32_t prtcl, enum srds_prtcl device)
-{
- int lane;
-
- lane = __serdes_get_first_lane(prtcl, device);
- if (unlikely(lane < 0))
- return lane;
-
- return serdes_get_bank_by_lane(lane);
-}
-
-static uint32_t __serdes_get_lane_count(uint32_t prtcl, enum srds_prtcl device,
- int first)
-{
- int lane;
-
- for (lane = first; lane < SRDS_MAX_LANES; lane++) {
- if (serdes_get_prtcl(prtcl, lane) != device)
- break;
- }
-
- return lane - first;
-}
-
-static void __serdes_reset_rx(serdes_corenet_t *regs,
- uint32_t prtcl,
- enum srds_prtcl device)
-{
- int lane, idx, first, last;
-
- lane = __serdes_get_first_lane(prtcl, device);
- if (unlikely(lane < 0))
- return;
- first = serdes_get_lane_idx(lane);
- last = first + __serdes_get_lane_count(prtcl, device, lane);
-
- /*
- * Set BnGCRy0[RRST] = 0 for each lane in the each bank that is
- * selected as XAUI to place the lane into reset.
- */
- for (idx = first; idx < last; idx++)
- clrbits_be32(®s->lane[idx].gcr0, SRDS_GCR0_RRST);
-
- /* Wait at least 250 ns */
- udelay(1);
-
- /*
- * Set BnGCRy0[RRST] = 1 for each lane in the each bank that is
- * selected as XAUI to bring the lane out of reset.
- */
- for (idx = first; idx < last; idx++)
- setbits_be32(®s->lane[idx].gcr0, SRDS_GCR0_RRST);
-}
-
-void serdes_reset_rx(enum srds_prtcl device)
-{
- u32 prtcl;
- const ccsr_gur_t *gur;
- serdes_corenet_t *regs;
-
- if (unlikely(device == NONE))
- return;
-
- gur = (typeof(gur))CFG_SYS_MPC85xx_GUTS_ADDR;
-
- /* Is serdes enabled at all? */
- if (unlikely((in_be32(&gur->rcwsr[5]) & 0x2000) == 0))
- return;
-
- regs = (typeof(regs))CFG_SYS_FSL_CORENET_SERDES_ADDR;
- prtcl = (in_be32(&gur->rcwsr[4]) & FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26;
-
- __serdes_reset_rx(regs, prtcl, device);
-}
-#endif
-
-#ifndef CFG_SYS_DCSRBAR_PHYS
-#define CFG_SYS_DCSRBAR_PHYS 0x80000000 /* Must be 1GB-aligned for rev1.0 */
-#define CFG_SYS_DCSRBAR 0x80000000
-#define __DCSR_NOT_DEFINED_BY_CONFIG
-#endif
-
-#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
-/*
- * Enable a SERDES bank that was disabled via the RCW
- *
- * We only call this function for SERDES8 and SERDES-A001 in cases we really
- * want to enable the bank, whether we actually want to use the lanes or not,
- * so make sure at least one lane is enabled. We're only enabling this one
- * lane to satisfy errata requirements that the bank be enabled.
- *
- * We use a local variable instead of srds_lpd_b[] because we want drivers to
- * think that the lanes actually are disabled.
- */
-static void enable_bank(ccsr_gur_t *gur, int bank)
-{
- u32 rcw5;
- u32 temp_lpd_b = srds_lpd_b[bank];
-
- /*
- * If we're asked to disable all lanes, just pretend we're doing
- * that.
- */
- if (temp_lpd_b == 0xF)
- temp_lpd_b = 0xE;
-
- /*
- * Enable the lanes SRDS_LPD_Bn. The RCW bits are read-only in
- * CCSR, and read/write in DSCR.
- */
- rcw5 = in_be32(gur->rcwsr + 5);
- if (bank == FSL_SRDS_BANK_2) {
- rcw5 &= ~FSL_CORENET_RCWSRn_SRDS_LPD_B2;
- rcw5 |= temp_lpd_b << 26;
- } else if (bank == FSL_SRDS_BANK_3) {
- rcw5 &= ~FSL_CORENET_RCWSRn_SRDS_LPD_B3;
- rcw5 |= temp_lpd_b << 18;
- } else {
- printf("SERDES: enable_bank: bad bank %d\n", bank + 1);
- return;
- }
-
- /* See similar code in cpu/mpc85xx/cpu_init.c for an explanation
- * of the DCSR mapping.
- */
- {
-#ifdef __DCSR_NOT_DEFINED_BY_CONFIG
- struct law_entry law = find_law(CFG_SYS_DCSRBAR_PHYS);
- int law_index;
- if (law.index == -1)
- law_index = set_next_law(CFG_SYS_DCSRBAR_PHYS,
- LAW_SIZE_1M, LAW_TRGT_IF_DCSR);
- else
- set_law(law.index, CFG_SYS_DCSRBAR_PHYS, LAW_SIZE_1M,
- LAW_TRGT_IF_DCSR);
-#endif
- u32 *p = (void *)CFG_SYS_DCSRBAR + 0x20114;
- out_be32(p, rcw5);
-#ifdef __DCSR_NOT_DEFINED_BY_CONFIG
- if (law.index == -1)
- disable_law(law_index);
- else
- set_law(law.index, law.addr, law.size, law.trgt_id);
-#endif
- }
-}
-
-/*
- * To avoid problems with clock jitter, rev 2 p4080 uses the pll from
- * bank 3 to clock banks 2 and 3, as well as a limited selection of
- * protocol configurations. This requires that banks 2 and 3's lanes be
- * disabled in the RCW, and enabled with some fixup here to re-enable
- * them, and to configure bank 2's clock parameters in bank 3's pll in
- * cases where they differ.
- */
-static void p4080_erratum_serdes8(serdes_corenet_t *regs, ccsr_gur_t *gur,
- u32 devdisr, u32 devdisr2, int cfg)
-{
- int srds_ratio_b2;
- int rfck_sel;
-
- /*
- * The disabled lanes of bank 2 will cause the associated
- * logic blocks to be disabled in DEVDISR. We reverse that here.
- *
- * Note that normally it is not permitted to clear DEVDISR bits
- * once the device has been disabled, but the hardware people
- * say that this special case is OK.
- */
- clrbits_be32(&gur->devdisr, devdisr);
- clrbits_be32(&gur->devdisr2, devdisr2);
-
- /*
- * Some protocols require special handling. There are a few
- * additional protocol configurations that can be used, which are
- * not listed here. See app note 4065 for supported protocol
- * configurations.
- */
- switch (cfg) {
- case 0x19:
- /*
- * Bank 2 has PCIe which wants BWSEL -- tell bank 3's PLL.
- * SGMII on bank 3 should still be usable.
- */
- setbits_be32(®s->bank[FSL_SRDS_BANK_3].pllcr1,
- SRDS_PLLCR1_PLL_BWSEL);
- break;
-
- case 0x0f:
- case 0x10:
- /*
- * Banks 2 (XAUI) and 3 (SGMII) have different clocking
- * requirements in these configurations. Bank 3 cannot
- * be used and should have its lanes (but not the bank
- * itself) disabled in the RCW. We set up bank 3's pll
- * for bank 2's needs here.
- */
- srds_ratio_b2 = (in_be32(&gur->rcwsr[4]) >> 13) & 7;
-
- /* Determine refclock from XAUI ratio */
- switch (srds_ratio_b2) {
- case 1: /* 20:1 */
- rfck_sel = SRDS_PLLCR0_RFCK_SEL_156_25;
- break;
- case 2: /* 25:1 */
- rfck_sel = SRDS_PLLCR0_RFCK_SEL_125;
- break;
- default:
- printf("SERDES: bad SRDS_RATIO_B2 %d\n",
- srds_ratio_b2);
- return;
- }
-
- clrsetbits_be32(®s->bank[FSL_SRDS_BANK_3].pllcr0,
- SRDS_PLLCR0_RFCK_SEL_MASK, rfck_sel);
-
- clrsetbits_be32(®s->bank[FSL_SRDS_BANK_3].pllcr0,
- SRDS_PLLCR0_FRATE_SEL_MASK,
- SRDS_PLLCR0_FRATE_SEL_6_25);
- break;
- }
-
- enable_bank(gur, FSL_SRDS_BANK_3);
-}
-#endif
-
-#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A005
-/*
- * If PCIe is not selected as a protocol for any lanes driven by a given PLL,
- * that PLL should have SRDSBnPLLCR1[PLLBW_SEL] = 0.
- */
-static void p4080_erratum_serdes_a005(serdes_corenet_t *regs, unsigned int cfg)
-{
- enum srds_prtcl device;
-
- switch (cfg) {
- case 0x13:
- case 0x16:
- /*
- * If SRDS_PRTCL = 0x13 or 0x16, set SRDSB1PLLCR1[PLLBW_SEL]
- * to 0.
- */
- clrbits_be32(®s->bank[FSL_SRDS_BANK_1].pllcr1,
- SRDS_PLLCR1_PLL_BWSEL);
- break;
- case 0x19:
- /*
- * If SRDS_PRTCL = 0x19, set SRDSB1PLLCR1[PLLBW_SEL] to 0 and
- * SRDSB3PLLCR1[PLLBW_SEL] to 1.
- */
- clrbits_be32(®s->bank[FSL_SRDS_BANK_1].pllcr1,
- SRDS_PLLCR1_PLL_BWSEL);
- setbits_be32(®s->bank[FSL_SRDS_BANK_3].pllcr1,
- SRDS_PLLCR1_PLL_BWSEL);
- break;
- }
-
- /*
- * Set SRDSBnPLLCR1[PLLBW_SEL] to 0 for each bank that selects XAUI
- * before XAUI is initialized.
- */
- for (device = XAUI_FM1; device <= XAUI_FM2; device++) {
- if (is_serdes_configured(device)) {
- int bank = serdes_get_bank_by_device(cfg, device);
-
- clrbits_be32(®s->bank[bank].pllcr1,
- SRDS_PLLCR1_PLL_BWSEL);
- }
- }
-}
-#endif
/*
* Wait for the RSTDONE bit to get set, or a one-second timeout.
@@ -498,27 +157,6 @@ void fsl_serdes_init(void)
#endif
int lane, bank, idx;
int have_bank[SRDS_MAX_BANK] = {};
-#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
- u32 serdes8_devdisr = 0;
- u32 serdes8_devdisr2 = 0;
- char srds_lpd_opt[16];
- const char *srds_lpd_arg;
- size_t arglen;
-#endif
-#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A001
- int need_serdes_a001; /* true == need work-around for SERDES A001 */
-#endif
-#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
- char buffer[HWCONFIG_BUFFER_SIZE];
- char *buf = NULL;
-
- /*
- * Extract hwconfig from environment since we have not properly setup
- * the environment but need it for ddr config params
- */
- if (env_get_f("hwconfig", buffer, sizeof(buffer)) > 0)
- buf = buffer;
-#endif
if (serdes_prtcl_map & (1 << NONE))
return;
@@ -534,42 +172,6 @@ void fsl_serdes_init(void)
printf("SERDES[PRTCL] = 0x%x is not valid\n", cfg);
return;
}
-
-#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
- /*
- * Display a warning if banks two and three are not disabled in the RCW,
- * since our work-around for SERDES8 depends on these banks being
- * disabled at power-on.
- */
-#define B2_B3 (FSL_CORENET_RCWSRn_SRDS_LPD_B2 | FSL_CORENET_RCWSRn_SRDS_LPD_B3)
- if ((in_be32(&gur->rcwsr[5]) & B2_B3) != B2_B3) {
- printf("Warning: SERDES8 requires banks two and "
- "three to be disabled in the RCW\n");
- }
-
- /*
- * Store the values of the fsl_srds_lpd_b2 and fsl_srds_lpd_b3
- * hwconfig options into the srds_lpd_b[] array. See README.p4080ds
- * for a description of these options.
- */
- for (bank = 1; bank < ARRAY_SIZE(srds_lpd_b); bank++) {
- sprintf(srds_lpd_opt, "fsl_srds_lpd_b%u", bank + 1);
- srds_lpd_arg =
- hwconfig_subarg_f("serdes", srds_lpd_opt, &arglen, buf);
- if (srds_lpd_arg)
- srds_lpd_b[bank] =
- simple_strtoul(srds_lpd_arg, NULL, 0) & 0xf;
- }
-
- if ((cfg == 0xf) || (cfg == 0x10)) {
- /*
- * For SERDES protocols 0xF and 0x10, force bank 3 to be
- * disabled, because it is not supported.
- */
- srds_lpd_b[FSL_SRDS_BANK_3] = 0xF;
- }
-#endif
-
/* Look for banks with all lanes disabled, and power down the bank. */
for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
enum srds_prtcl lane_prtcl = serdes_get_prtcl(cfg, lane);
@@ -612,44 +214,13 @@ void fsl_serdes_init(void)
/* Set the first bit to indicate serdes has been initialized */
serdes_prtcl_map |= (1 << NONE);
-#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
- /*
- * Bank two uses the clock from bank three, so if bank two is enabled,
- * then bank three must also be enabled.
- */
- if (have_bank[FSL_SRDS_BANK_2])
- have_bank[FSL_SRDS_BANK_3] = 1;
-#endif
-
-#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A001
- /*
- * The work-aroud for erratum SERDES-A001 is needed only if bank two
- * is disabled and bank three is enabled. The converse is also true,
- * but SERDES8 ensures that bank 3 is always enabled if bank 2 is
- * enabled, so there's no point in complicating the code to handle
- * that situation.
- */
- need_serdes_a001 =
- !have_bank[FSL_SRDS_BANK_2] && have_bank[FSL_SRDS_BANK_3];
-#endif
/* Power down the banks we're not interested in */
for (bank = 0; bank < SRDS_MAX_BANK; bank++) {
if (!have_bank[bank]) {
printf("SERDES: bank %d disabled\n", bank + 1);
-#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A001
- /*
- * Erratum SERDES-A001 says bank two needs to be powered
- * down after bank three is powered up, so don't power
- * down bank two here.
- */
- if (!need_serdes_a001 || (bank != FSL_SRDS_BANK_2))
- setbits_be32(&srds_regs->bank[bank].rstctl,
- SRDS_RSTCTL_SDPD);
-#else
setbits_be32(&srds_regs->bank[bank].rstctl,
SRDS_RSTCTL_SDPD);
-#endif
}
}
@@ -685,188 +256,17 @@ void fsl_serdes_init(void)
}
#endif
-#if defined(CONFIG_SYS_P4080_ERRATUM_SERDES8) || defined (CONFIG_SYS_P4080_ERRATUM_SERDES9)
- for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
- enum srds_prtcl lane_prtcl;
- idx = serdes_get_lane_idx(lane);
- lane_prtcl = serdes_get_prtcl(cfg, lane);
-
-#ifdef DEBUG
- switch (lane) {
- case 0:
- puts("Bank1: ");
- break;
- case 10:
- puts("\nBank2: ");
- break;
- case 14:
- puts("\nBank3: ");
- break;
- default:
- break;
- }
-
- printf("%s ", serdes_prtcl_str[lane_prtcl]);
-#endif
-
-#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9
- /*
- * Set BnTTLCRy0[FLT_SEL] = 011011 and set BnTTLCRy0[31] = 1
- * for each of the SerDes lanes selected as SGMII, XAUI, SRIO,
- * or AURORA before the device is initialized.
- *
- * Note that this part of the SERDES-9 work-around is
- * redundant if the work-around for A-4580 has already been
- * applied via PBI.
- */
- switch (lane_prtcl) {
- case SGMII_FM1_DTSEC1:
- case SGMII_FM1_DTSEC2:
- case SGMII_FM1_DTSEC3:
- case SGMII_FM1_DTSEC4:
- case SGMII_FM2_DTSEC1:
- case SGMII_FM2_DTSEC2:
- case SGMII_FM2_DTSEC3:
- case SGMII_FM2_DTSEC4:
- case SGMII_FM2_DTSEC5:
- case XAUI_FM1:
- case XAUI_FM2:
- case SRIO1:
- case SRIO2:
- case AURORA:
- out_be32(&srds_regs->lane[idx].ttlcr0,
- SRDS_TTLCR0_FLT_SEL_KFR_26 |
- SRDS_TTLCR0_FLT_SEL_KPH_28 |
- SRDS_TTLCR0_FLT_SEL_750PPM |
- SRDS_TTLCR0_FREQOVD_EN);
- break;
- default:
- break;
- }
-#endif
-
-#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
- switch (lane_prtcl) {
- case PCIE1:
- case PCIE2:
- case PCIE3:
- serdes8_devdisr |= FSL_CORENET_DEVDISR_PCIE1 >>
- (lane_prtcl - PCIE1);
- break;
- case SRIO1:
- case SRIO2:
- serdes8_devdisr |= FSL_CORENET_DEVDISR_SRIO1 >>
- (lane_prtcl - SRIO1);
- break;
- case SGMII_FM1_DTSEC1:
- serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM1 |
- FSL_CORENET_DEVDISR2_DTSEC1_1;
- break;
- case SGMII_FM1_DTSEC2:
- serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM1 |
- FSL_CORENET_DEVDISR2_DTSEC1_2;
- break;
- case SGMII_FM1_DTSEC3:
- serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM1 |
- FSL_CORENET_DEVDISR2_DTSEC1_3;
- break;
- case SGMII_FM1_DTSEC4:
- serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM1 |
- FSL_CORENET_DEVDISR2_DTSEC1_4;
- break;
- case SGMII_FM2_DTSEC1:
- serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 |
- FSL_CORENET_DEVDISR2_DTSEC2_1;
- break;
- case SGMII_FM2_DTSEC2:
- serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 |
- FSL_CORENET_DEVDISR2_DTSEC2_2;
- break;
- case SGMII_FM2_DTSEC3:
- serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 |
- FSL_CORENET_DEVDISR2_DTSEC2_3;
- break;
- case SGMII_FM2_DTSEC4:
- serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 |
- FSL_CORENET_DEVDISR2_DTSEC2_4;
- break;
- case SGMII_FM2_DTSEC5:
- serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 |
- FSL_CORENET_DEVDISR2_DTSEC2_5;
- break;
- case XAUI_FM1:
- serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM1 |
- FSL_CORENET_DEVDISR2_10GEC1;
- break;
- case XAUI_FM2:
- serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 |
- FSL_CORENET_DEVDISR2_10GEC2;
- break;
- case AURORA:
- break;
- default:
- break;
- }
-
-#endif
- }
-#endif
-
-#ifdef DEBUG
- puts("\n");
-#endif
-
-#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A005
- p4080_erratum_serdes_a005(srds_regs, cfg);
-#endif
for (idx = 0; idx < SRDS_MAX_BANK; idx++) {
bank = idx;
-#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
- /*
- * Change bank init order to 0, 2, 1, so that the third bank's
- * PLL is established before we start the second bank. The
- * second bank uses the third bank's PLL.
- */
-
- if (idx == 1)
- bank = FSL_SRDS_BANK_3;
- else if (idx == 2)
- bank = FSL_SRDS_BANK_2;
-#endif
-
/* Skip disabled banks */
if (!have_bank[bank])
continue;
-#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
- if (idx == 1) {
- /*
- * Re-enable devices on banks two and three that were
- * disabled by the RCW, and then enable bank three. The
- * devices need to be enabled before either bank is
- * powered up.
- */
- p4080_erratum_serdes8(srds_regs, gur, serdes8_devdisr,
- serdes8_devdisr2, cfg);
- } else if (idx == 2) {
- /* Enable bank two now that bank three is enabled. */
- enable_bank(gur, FSL_SRDS_BANK_2);
- }
-#endif
-
wait_for_rstdone(bank);
}
-
-#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A001
- if (need_serdes_a001) {
- /* Bank 3 has been enabled, so now we can disable bank 2 */
- setbits_be32(&srds_regs->bank[FSL_SRDS_BANK_2].rstctl,
- SRDS_RSTCTL_SDPD);
- }
-#endif
}
const char *serdes_clock_to_string(u32 clock)
diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.h b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.h
index e95dc485814..553c72a43d6 100644
--- a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.h
+++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.h
@@ -20,8 +20,4 @@ int serdes_get_bank_by_lane(int lane);
int serdes_lane_enabled(int lane);
enum srds_prtcl serdes_get_prtcl(int cfg, int lane);
-#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
-extern uint16_t srds_lpd_b[SRDS_MAX_BANK];
-#endif
-
#endif /* __FSL_CORENET_SERDES_H */
diff --git a/arch/powerpc/cpu/mpc85xx/p4080_ids.c b/arch/powerpc/cpu/mpc85xx/p4080_ids.c
deleted file mode 100644
index 15ab4ac9385..00000000000
--- a/arch/powerpc/cpu/mpc85xx/p4080_ids.c
+++ /dev/null
@@ -1,112 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2010-2011 Freescale Semiconductor, Inc.
- */
-
-#include <config.h>
-#include <linux/kernel.h>
-#include <asm/fsl_portals.h>
-#include <asm/fsl_liodn.h>
-
-#ifdef CONFIG_SYS_DPAA_QBMAN
-struct qportal_info qp_info[CFG_SYS_QMAN_NUM_PORTALS] = {
- /* dqrr liodn, frame data liodn, liodn off, sdest */
- SET_QP_INFO( 1, 2, 1, 0),
- SET_QP_INFO( 3, 4, 2, 1),
- SET_QP_INFO( 5, 6, 3, 2),
- SET_QP_INFO( 7, 8, 4, 3),
- SET_QP_INFO( 9, 10, 5, 4),
- SET_QP_INFO(11, 12, 6, 5),
- SET_QP_INFO(13, 14, 7, 6),
- SET_QP_INFO(15, 16, 8, 7),
- SET_QP_INFO(17, 18, 9, 0), /* for now sdest to 0 */
- SET_QP_INFO(19, 20, 10, 0), /* for now sdest to 0 */
-};
-#endif
-
-struct srio_liodn_id_table srio_liodn_tbl[] = {
- SET_SRIO_LIODN_1(1, 198),
- SET_SRIO_LIODN_1(2, 199),
-};
-int srio_liodn_tbl_sz = ARRAY_SIZE(srio_liodn_tbl);
-
-struct liodn_id_table liodn_tbl[] = {
- SET_USB_LIODN(1, "fsl-usb2-mph", 127),
- SET_USB_LIODN(2, "fsl-usb2-dr", 157),
-
- SET_SDHC_LIODN(1, 156),
-
- SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 1, 193),
- SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 2, 194),
- SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 3, 195),
-
- SET_DMA_LIODN(1, "fsl,eloplus-dma", 196),
- SET_DMA_LIODN(2, "fsl,eloplus-dma", 197),
-
- SET_GUTS_LIODN("fsl,srio-rmu", 200, rmuliodnr, 0xd3000),
-
-#ifdef CONFIG_SYS_DPAA_QBMAN
- SET_QMAN_LIODN(31),
- SET_BMAN_LIODN(32),
-#endif
- SET_PME_LIODN(128),
-};
-int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl);
-
-#ifdef CONFIG_SYS_DPAA_FMAN
-struct fman_liodn_id_table fman1_liodn_tbl[] = {
- SET_FMAN_RX_1G_LIODN(1, 0, 11),
- SET_FMAN_RX_1G_LIODN(1, 1, 12),
- SET_FMAN_RX_1G_LIODN(1, 2, 13),
- SET_FMAN_RX_1G_LIODN(1, 3, 14),
- SET_FMAN_RX_10G_LIODN(1, 0, 15),
-};
-int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl);
-
-#if (CFG_SYS_NUM_FMAN == 2)
-struct fman_liodn_id_table fman2_liodn_tbl[] = {
- SET_FMAN_RX_1G_LIODN(2, 0, 16),
- SET_FMAN_RX_1G_LIODN(2, 1, 17),
- SET_FMAN_RX_1G_LIODN(2, 2, 18),
- SET_FMAN_RX_1G_LIODN(2, 3, 19),
- SET_FMAN_RX_10G_LIODN(2, 0, 20),
-};
-int fman2_liodn_tbl_sz = ARRAY_SIZE(fman2_liodn_tbl);
-#endif
-#endif
-
-struct liodn_id_table sec_liodn_tbl[] = {
- /*
- * We assume currently that all JR are in the same partition
- * and as such they need to represent the same LIODN due to
- * a 4080 rev.2 h/w requirement that DECOs sharing from themselves
- * or from another DECO have the two Non-SEQ LIODN values equal
- */
- SET_SEC_JR_LIODN_ENTRY(0, 146, 154), /* (0, 146, 154), */
- SET_SEC_JR_LIODN_ENTRY(1, 146, 154), /* (1, 147, 155), */
- SET_SEC_JR_LIODN_ENTRY(2, 146, 154), /* (2, 178, 186), */
- SET_SEC_JR_LIODN_ENTRY(3, 146, 154), /* (3, 179, 187), */
- SET_SEC_RTIC_LIODN_ENTRY(a, 144),
- SET_SEC_RTIC_LIODN_ENTRY(b, 145),
- SET_SEC_RTIC_LIODN_ENTRY(c, 176),
- SET_SEC_RTIC_LIODN_ENTRY(d, 177),
- SET_SEC_DECO_LIODN_ENTRY(0, 129, 161),
- SET_SEC_DECO_LIODN_ENTRY(1, 130, 162),
- SET_SEC_DECO_LIODN_ENTRY(2, 131, 163),
- SET_SEC_DECO_LIODN_ENTRY(3, 132, 164),
- SET_SEC_DECO_LIODN_ENTRY(4, 133, 165),
-};
-int sec_liodn_tbl_sz = ARRAY_SIZE(sec_liodn_tbl);
-
-struct liodn_id_table liodn_bases[] = {
- [FSL_HW_PORTAL_SEC] = SET_LIODN_BASE_2(96, 106),
-#ifdef CONFIG_SYS_DPAA_FMAN
- [FSL_HW_PORTAL_FMAN1] = SET_LIODN_BASE_1(32),
-#if (CFG_SYS_NUM_FMAN == 2)
- [FSL_HW_PORTAL_FMAN2] = SET_LIODN_BASE_1(64),
-#endif
-#endif
-#ifdef CONFIG_SYS_DPAA_PME
- [FSL_HW_PORTAL_PME] = SET_LIODN_BASE_2(116, 133),
-#endif
-};
diff --git a/arch/powerpc/cpu/mpc85xx/p4080_serdes.c b/arch/powerpc/cpu/mpc85xx/p4080_serdes.c
deleted file mode 100644
index 438fd446be3..00000000000
--- a/arch/powerpc/cpu/mpc85xx/p4080_serdes.c
+++ /dev/null
@@ -1,80 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2009-2010 Freescale Semiconductor, Inc.
- */
-
-#include <asm/io.h>
-#include <asm/fsl_serdes.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include "fsl_corenet_serdes.h"
-
-static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = {
- [0x2] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1,
- AURORA, AURORA, XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2,
- XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1},
- [0x5] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2,
- AURORA, AURORA, XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2,
- XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1},
- [0x8] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2, PCIE2, PCIE2,
- AURORA, AURORA, XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2,
- XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1},
- [0xd] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, SGMII_FM2_DTSEC3,
- SGMII_FM2_DTSEC4, AURORA, AURORA, XAUI_FM2, XAUI_FM2, XAUI_FM2,
- XAUI_FM2, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1},
- [0xe] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2, SGMII_FM2_DTSEC3,
- SGMII_FM2_DTSEC4, AURORA, AURORA, XAUI_FM2, XAUI_FM2, XAUI_FM2,
- XAUI_FM2, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1},
- [0xf] = {PCIE1, PCIE1, PCIE1, PCIE1, SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
- SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4, AURORA, AURORA, XAUI_FM2,
- XAUI_FM2, XAUI_FM2, XAUI_FM2, NONE, NONE, NONE, NONE},
- [0x10] = {PCIE1, PCIE1, PCIE3, PCIE3, SGMII_FM2_DTSEC1,
- SGMII_FM2_DTSEC2, SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4,
- AURORA, AURORA, XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2,
- NONE, NONE, NONE, NONE},
- [0x13] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1,
- AURORA, AURORA, XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2,
- XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1},
- [0x16] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1,
- AURORA, AURORA, SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
- SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4, SGMII_FM1_DTSEC1,
- SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4},
- [0x19] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1,
- AURORA, AURORA, PCIE3, PCIE3, PCIE3, PCIE3, SGMII_FM1_DTSEC1,
- SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4},
- [0x1d] = {PCIE1, PCIE1, PCIE3, PCIE3, NONE, SRIO2, NONE, SRIO1,
- AURORA, AURORA, XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2,
- XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1},
- [0x22] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1,
- AURORA, AURORA, XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2,
- XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1},
- [0x25] = {PCIE1, PCIE1, PCIE3, PCIE3, SRIO1, SRIO1, SRIO1, SRIO1,
- AURORA, AURORA, XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2,
- XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1},
-};
-
-#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
-uint16_t srds_lpd_b[SRDS_MAX_BANK];
-#endif
-
-enum srds_prtcl serdes_get_prtcl(int cfg, int lane)
-{
- if (!serdes_lane_enabled(lane))
- return NONE;
-
- return serdes_cfg_tbl[cfg][lane];
-}
-
-int is_serdes_prtcl_valid(u32 prtcl) {
- int i;
-
- if (prtcl >= ARRAY_SIZE(serdes_cfg_tbl))
- return 0;
-
- for (i = 0; i < SRDS_MAX_LANES; i++) {
- if (serdes_cfg_tbl[prtcl][i] != NONE)
- return 1;
- }
-
- return 0;
-}
diff --git a/arch/powerpc/cpu/mpc85xx/release.S b/arch/powerpc/cpu/mpc85xx/release.S
index 078d8cf3f34..26110f11592 100644
--- a/arch/powerpc/cpu/mpc85xx/release.S
+++ b/arch/powerpc/cpu/mpc85xx/release.S
@@ -203,32 +203,11 @@ __secondary_start_page:
#endif
#endif /* CONFIG_SYS_FSL_ERRATUM_A007907 */
-#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \
- defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011)
- /*
- * CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0
- * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0
- * also applies to P2041 rev 1.0, 1.1
- */
- mfspr r3,SPRN_SVR
- rlwinm r6,r3,24,~0x800 /* clear E bit */
-
- lis r5,SVR_P4080@h
- ori r5,r5,SVR_P4080@l
- cmpw r6,r5
- bne 1f
-
- rlwinm r3,r3,0,0xf0
- li r5,0x30
- cmpw r3,r5
- bge 2f
-1:
-#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
+#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
lis r3,toreset(enable_cpu_a011_workaround)@ha
lwz r3,toreset(enable_cpu_a011_workaround)@l(r3)
cmpwi r3,0
beq 2f
-#endif
mfspr r3,L1CSR2
oris r3,r3,(L1CSR2_DCWS)@h
mtspr L1CSR2,r3
diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c
index b8bec9ed2e8..8b575e85347 100644
--- a/arch/powerpc/cpu/mpc8xxx/cpu.c
+++ b/arch/powerpc/cpu/mpc8xxx/cpu.c
@@ -57,7 +57,6 @@ static struct cpu_type cpu_type_list[] = {
CPU_TYPE_ENTRY(P2040, P2040, 4),
CPU_TYPE_ENTRY(P2041, P2041, 4),
CPU_TYPE_ENTRY(P4040, P4040, 4),
- CPU_TYPE_ENTRY(P4080, P4080, 8),
CPU_TYPE_ENTRY(P5010, P5010, 1),
CPU_TYPE_ENTRY(P5020, P5020, 2),
CPU_TYPE_ENTRY(P5021, P5021, 2),
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index 07be48d518d..3701f29daa0 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -44,19 +44,6 @@
#define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5
#define CFG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
-#elif defined(CONFIG_ARCH_P4080) /* also supports P4040 */
-#define CFG_SYS_NUM_FMAN 2
-#define CFG_SYS_NUM_FM1_DTSEC 4
-#define CFG_SYS_NUM_FM2_DTSEC 4
-#define CFG_SYS_NUM_FM1_10GEC 1
-#define CFG_SYS_NUM_FM2_10GEC 1
-#define CFG_SYS_FM_MURAM_SIZE 0x28000
-#define CFG_SYS_FSL_SRIO_MAX_PORTS 2
-#define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9
-#define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5
-#define CFG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
-#define CFG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000
-
#elif defined(CONFIG_ARCH_P5040)
#define CFG_SYS_NUM_FMAN 2
#define CFG_SYS_NUM_FM1_DTSEC 5
diff --git a/arch/powerpc/include/asm/fsl_serdes.h b/arch/powerpc/include/asm/fsl_serdes.h
index fdf76115233..6d238115c10 100644
--- a/arch/powerpc/include/asm/fsl_serdes.h
+++ b/arch/powerpc/include/asm/fsl_serdes.h
@@ -118,9 +118,6 @@ enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane);
#else
int serdes_get_first_lane(enum srds_prtcl device);
#endif
-#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9
-void serdes_reset_rx(enum srds_prtcl device);
-#endif
#endif
#endif /* __FSL_SERDES_H */
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index e1d1ca80092..de1ae25440c 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1506,22 +1506,12 @@ typedef struct ccsr_gur {
#define FSL_CORENET_RCWSR5_SRDS_EN 0x00002000
#define FSL_CORENET_RCWSR5_SRDS2_EN 0x00001000
#define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000
-#define FSL_CORENET_RCWSRn_SRDS_LPD_B2 0x3c000000 /* bits 162..165 */
-#define FSL_CORENET_RCWSRn_SRDS_LPD_B3 0x003c0000 /* bits 170..173 */
#endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
#define FSL_CORENET_RCWSR7_MCK_TO_PLAT_RAT 0x00400000
#define FSL_CORENET_RCWSR8_HOST_AGT_B1 0x00e00000
#define FSL_CORENET_RCWSR8_HOST_AGT_B2 0x00100000
#define FSL_CORENET_RCWSR11_EC1 0x00c00000 /* bits 360..361 */
-#ifdef CONFIG_ARCH_P4080
-#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC1 0x00000000
-#define FSL_CORENET_RCWSR11_EC1_FM1_USB1 0x00800000
-#define FSL_CORENET_RCWSR11_EC2 0x001c0000 /* bits 363..365 */
-#define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC1 0x00000000
-#define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC2 0x00080000
-#define FSL_CORENET_RCWSR11_EC2_USB2 0x00100000
-#endif
#if defined(CONFIG_ARCH_P2041)
#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_RGMII 0x00000000
#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_MII 0x00800000
@@ -2313,12 +2303,6 @@ typedef struct serdes_corenet {
#define SRDS_TECR0_TEQ_TYPE_2LVL 0x10000000
u32 res3;
u32 ttlcr0; /* Transition Tracking Loop Ctrl 0 */
-#define SRDS_TTLCR0_FLT_SEL_MASK 0x3f000000
-#define SRDS_TTLCR0_FLT_SEL_KFR_26 0x10000000
-#define SRDS_TTLCR0_FLT_SEL_KPH_28 0x08000000
-#define SRDS_TTLCR0_FLT_SEL_750PPM 0x03000000
-#define SRDS_TTLCR0_PM_DIS 0x00004000
-#define SRDS_TTLCR0_FREQOVD_EN 0x00000001
u32 res4[7];
} lane[24];
u32 res6[384];
diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h
index 31d52f3b734..1ddbf15c410 100644
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -1049,7 +1049,6 @@
#define SVR_P2040 0x821000
#define SVR_P2041 0x821001
#define SVR_P4040 0x820100
-#define SVR_P4080 0x820000
#define SVR_P5010 0x822100
#define SVR_P5020 0x822000
#define SVR_P5021 0x820500
diff --git a/doc/README.pblimage b/doc/README.pblimage
index 7145622b575..f4bdadfb2dd 100644
--- a/doc/README.pblimage
+++ b/doc/README.pblimage
@@ -14,11 +14,11 @@ Building PBL Boot Image and boot steps
1. Building PBL Boot Image.
The default Image is u-boot.pbl.
- For eSPI boot(available on P2041/P4080/P5020/P5040/T4240):
+ For eSPI boot(available on P2041/P5020/P5040/T4240):
To build the eSPI boot image:
make <board_name>_SPIFLASH
- For SD boot(available on P2041/P4080/P5020/P5040/T4240):
+ For SD boot(available on P2041/P5020/P5040/T4240):
To build the SD boot image:
make <board_name>_SDCARD
diff --git a/drivers/ddr/fsl/Kconfig b/drivers/ddr/fsl/Kconfig
index d5c0af7d3b1..c518704d93e 100644
--- a/drivers/ddr/fsl/Kconfig
+++ b/drivers/ddr/fsl/Kconfig
@@ -52,7 +52,6 @@ config SYS_NUM_DDR_CTLRS
ARCH_T4240
default 2 if ARCH_B4860 || \
ARCH_BSC9132 || \
- ARCH_P4080 || \
ARCH_P5040 || \
ARCH_LX2160A || \
ARCH_LX2162A
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index fb0dc39cf35..df243e8fe9b 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -969,7 +969,6 @@ config SYS_DPAA_QBMAN
ARCH_T1042 || \
ARCH_T2080 || \
ARCH_T4240 || \
- ARCH_P4080 || \
ARCH_P5040 || \
ARCH_LS1043A || \
ARCH_LS1046A
diff --git a/drivers/net/fm/Makefile b/drivers/net/fm/Makefile
index af8fca353a9..e6727eeec98 100644
--- a/drivers/net/fm/Makefile
+++ b/drivers/net/fm/Makefile
@@ -16,7 +16,6 @@ obj-$(CONFIG_SYS_FMAN_V3) += memac.o
obj-$(CONFIG_ARCH_P1023) += p1023.o
# The P204x and P5020 are the same
obj-$(CONFIG_ARCH_P2041) += p5020.o
-obj-$(CONFIG_ARCH_P4080) += p4080.o
obj-$(CONFIG_ARCH_P5040) += p5040.o
obj-$(CONFIG_ARCH_T1040) += t1040.o
obj-$(CONFIG_ARCH_T1042) += t1040.o
diff --git a/drivers/net/fm/p4080.c b/drivers/net/fm/p4080.c
deleted file mode 100644
index 6e63e338e5d..00000000000
--- a/drivers/net/fm/p4080.c
+++ /dev/null
@@ -1,98 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2011 Freescale Semiconductor, Inc.
- */
-#include <config.h>
-#include <phy.h>
-#include <fm_eth.h>
-#include <asm/io.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_serdes.h>
-
-static u32 port_to_devdisr[] = {
- [FM1_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC1_1,
- [FM1_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC1_2,
- [FM1_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC1_3,
- [FM1_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC1_4,
- [FM1_10GEC1] = FSL_CORENET_DEVDISR2_10GEC1,
- [FM2_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC2_1,
- [FM2_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC2_2,
- [FM2_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC2_3,
- [FM2_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC2_4,
- [FM2_10GEC1] = FSL_CORENET_DEVDISR2_10GEC2,
-};
-
-static int is_device_disabled(enum fm_port port)
-{
- ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
- u32 devdisr2 = in_be32(&gur->devdisr2);
-
- return port_to_devdisr[port] & devdisr2;
-}
-
-void fman_disable_port(enum fm_port port)
-{
- ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
-
- /* don't allow disabling of DTSEC1 as its needed for MDIO */
- if (port == FM1_DTSEC1)
- return;
-
- setbits_be32(&gur->devdisr2, port_to_devdisr[port]);
-}
-
-void fman_enable_port(enum fm_port port)
-{
- ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
-
- clrbits_be32(&gur->devdisr2, port_to_devdisr[port]);
-}
-
-phy_interface_t fman_port_enet_if(enum fm_port port)
-{
- ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
- u32 rcwsr11 = in_be32(&gur->rcwsr[11]);
-
- if (is_device_disabled(port))
- return PHY_INTERFACE_MODE_NA;
-
- if ((port == FM1_10GEC1) && (is_serdes_configured(XAUI_FM1)))
- return PHY_INTERFACE_MODE_XGMII;
-
- if ((port == FM2_10GEC1) && (is_serdes_configured(XAUI_FM2)))
- return PHY_INTERFACE_MODE_XGMII;
-
- /* handle RGMII first */
- if ((port == FM1_DTSEC1) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC1) ==
- FSL_CORENET_RCWSR11_EC1_FM1_DTSEC1))
- return PHY_INTERFACE_MODE_RGMII;
-
- if ((port == FM1_DTSEC2) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) ==
- FSL_CORENET_RCWSR11_EC2_FM1_DTSEC2))
- return PHY_INTERFACE_MODE_RGMII;
-
- if ((port == FM2_DTSEC1) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) ==
- FSL_CORENET_RCWSR11_EC2_FM2_DTSEC1))
- return PHY_INTERFACE_MODE_RGMII;
-
- switch (port) {
- case FM1_DTSEC1:
- case FM1_DTSEC2:
- case FM1_DTSEC3:
- case FM1_DTSEC4:
- if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1))
- return PHY_INTERFACE_MODE_SGMII;
- break;
- case FM2_DTSEC1:
- case FM2_DTSEC2:
- case FM2_DTSEC3:
- case FM2_DTSEC4:
- if (is_serdes_configured(SGMII_FM2_DTSEC1 + port - FM2_DTSEC1))
- return PHY_INTERFACE_MODE_SGMII;
- break;
- default:
- return PHY_INTERFACE_MODE_NA;
- }
-
- return PHY_INTERFACE_MODE_NA;
-}
diff --git a/drivers/pci/pcie_fsl.c b/drivers/pci/pcie_fsl.c
index 18af23c9504..8d634b42373 100644
--- a/drivers/pci/pcie_fsl.c
+++ b/drivers/pci/pcie_fsl.c
@@ -12,7 +12,6 @@
#include <mapmem.h>
#include <pci.h>
#include <asm/fsl_pci.h>
-#include <asm/fsl_serdes.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <linux/delay.h>
@@ -474,28 +473,6 @@ static int fsl_pcie_init_port(struct fsl_pcie *pcie)
}
#endif
-#ifdef CONFIG_SYS_P4080_ERRATUM_PCIE_A003
- if (!fsl_pcie_link_up(pcie)) {
- serdes_corenet_t *srds_regs;
-
- srds_regs = (void *)CFG_SYS_FSL_CORENET_SERDES_ADDR;
- val_32 = in_be32(&srds_regs->srdspccr0);
-
- if ((val_32 >> 28) == 3) {
- int i;
-
- out_be32(&srds_regs->srdspccr0, 2 << 28);
- setbits_be32(®s->pdb_stat, 0x08000000);
- in_be32(®s->pdb_stat);
- udelay(100);
- clrbits_be32(®s->pdb_stat, 0x08000000);
- asm("sync;isync");
- for (i = 0; i < 100 && !fsl_pcie_link_up(pcie); i++)
- udelay(1000);
- }
- }
-#endif
-
/*
* The Read-Only Write Enable bit defaults to 1 instead of 0.
* Set to 0 to protect the read-only registers.
diff --git a/drivers/usb/common/fsl-errata.c b/drivers/usb/common/fsl-errata.c
index e2f0563e33c..b6fc8182092 100644
--- a/drivers/usb/common/fsl-errata.c
+++ b/drivers/usb/common/fsl-errata.c
@@ -111,8 +111,6 @@ bool has_erratum_a007075(void)
return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0);
case SVR_P1010:
return IS_SVR_REV(svr, 1, 0);
- case SVR_P4080:
- return IS_SVR_REV(svr, 2, 0) || IS_SVR_REV(svr, 3, 0);
#endif
}
return false;
@@ -191,8 +189,6 @@ bool has_erratum_a004477(void)
case SVR_B4860:
case SVR_B4420:
return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0);
- case SVR_P4080:
- return IS_SVR_REV(svr, 2, 0) || IS_SVR_REV(svr, 3, 0);
#endif
}
diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index 6bbed9cb513..ce560a95681 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -309,7 +309,7 @@ config USB_EHCI_FSL
depends on PPC
select EHCI_HCD_INIT_AFTER_RESET
select SYS_FSL_USB_INTERNAL_UTMI_PHY if MPC85xx && \
- !(ARCH_B4860 || ARCH_B4420 || ARCH_P4080 || ARCH_P1020 || ARCH_P2020)
+ !(ARCH_B4860 || ARCH_B4420 || ARCH_P1020 || ARCH_P2020)
help
Enables support for the on-chip EHCI controller on FSL chips.
--
2.47.3
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH 10/26] powerpc: mpc85xx: Remove P5040 support
2026-10-09 19:36 [PATCH 00/26] powerpc: drop EOL boards and SoCs, take over maintenance Bradley Morgan
` (8 preceding siblings ...)
2026-10-09 19:36 ` [PATCH 09/26] powerpc: mpc85xx: Remove P4080 support Bradley Morgan
@ 2026-10-09 19:36 ` Bradley Morgan
2026-10-09 19:36 ` [PATCH 11/26] powerpc: mpc83xx: Remove MPC837x support Bradley Morgan
` (15 subsequent siblings)
25 siblings, 0 replies; 31+ messages in thread
From: Bradley Morgan @ 2026-10-09 19:36 UTC (permalink / raw)
To: Tom Rini, u-boot
Cc: Bradley Morgan, Marek Behún, Marek Mojík,
NXP i . MX U-Boot Team, Alexey Charkov, Anshul Dalal,
Daniel Golle, Fabio Estevam, Gaurav Jain, Ilias Apalodimas,
Jaehoon Chung, James Hilliard, Jerome Forissier, Johan Jonker,
Lukasz Majewski, Marek Vasut, Mario Six, Michael Walle,
Michal Simek, Neil Armstrong, Peng Fan, Pengpeng Hou,
Priyanka Jain, Quentin Schulz, Simon Glass, Stefano Babic,
Tanmay Kathpalia, Torsten Rupp, Vincent Jardin, Weijie Gao
The P5040DS was the last user in the tree of ARCH_P5040. NXP lists the processor as no longer manufactured.
Nothing selects the option now. Drop its SoC specific FM, SERDES and errata support.
Signed-off-by: Bradley Morgan <brads@mainlining.org>
---
arch/Kconfig.nxp | 2 +-
arch/powerpc/cpu/mpc85xx/Kconfig | 42 +------
arch/powerpc/cpu/mpc85xx/Makefile | 2 -
arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c | 65 ----------
arch/powerpc/cpu/mpc85xx/p5040_ids.c | 111 ------------------
arch/powerpc/cpu/mpc85xx/p5040_serdes.c | 99 ----------------
arch/powerpc/cpu/mpc8xxx/cpu.c | 1 -
arch/powerpc/include/asm/config_mpc85xx.h | 9 --
arch/powerpc/include/asm/immap_85xx.h | 12 --
arch/powerpc/include/asm/processor.h | 1 -
doc/README.pblimage | 6 +-
drivers/ddr/fsl/Kconfig | 1 -
drivers/net/Kconfig | 1 -
drivers/net/fm/Makefile | 1 -
drivers/net/fm/p5040.c | 106 -----------------
drivers/usb/common/fsl-errata.c | 4 -
16 files changed, 6 insertions(+), 457 deletions(-)
delete mode 100644 arch/powerpc/cpu/mpc85xx/p5040_ids.c
delete mode 100644 arch/powerpc/cpu/mpc85xx/p5040_serdes.c
delete mode 100644 drivers/net/fm/p5040.c
diff --git a/arch/Kconfig.nxp b/arch/Kconfig.nxp
index 6b1ad1795fa..8b8210224b5 100644
--- a/arch/Kconfig.nxp
+++ b/arch/Kconfig.nxp
@@ -5,7 +5,7 @@ config FSL_TRUST_ARCH_v1
config NXP_ESBC
bool "NXP ESBC (secure boot) functionality"
- select FSL_TRUST_ARCH_v1 if ARCH_P5040 || ARCH_P2041
+ select FSL_TRUST_ARCH_v1 if ARCH_P2041
help
Enable Freescale Secure Boot feature. Normally selected by defconfig.
If unsure, do not change.
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index 252666cab5f..32461cfae50 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -584,37 +584,6 @@ config ARCH_P2041
select FSL_ELBC
imply CMD_NAND
-config ARCH_P5040
- bool
- select BACKSIDE_L2_CACHE
- select E500MC
- select FSL_CORENET
- select FSL_LAW
- select SYS_CACHE_SHIFT_6
- select SYS_FSL_DDR_VER_44
- select SYS_FSL_ERRATUM_A004510
- select SYS_FSL_ERRATUM_A004699
- select SYS_FSL_ERRATUM_A005275
- select SYS_FSL_ERRATUM_A005812
- select SYS_FSL_ERRATUM_A006261
- select SYS_FSL_ERRATUM_DDR_A003
- select SYS_FSL_ERRATUM_DDR_A003474
- select SYS_FSL_ERRATUM_ESDHC111
- select SYS_FSL_ERRATUM_USB14
- select SYS_FSL_HAS_DDR3
- select SYS_FSL_HAS_SEC
- select SYS_FSL_QORIQ_CHASSIS1
- select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24
- select SYS_FSL_SEC_BE
- select SYS_FSL_SEC_COMPAT_4
- select SYS_FSL_USB1_PHY_ENABLE
- select SYS_FSL_USB2_PHY_ENABLE
- select SYS_PPC64
- select FSL_ELBC
- imply SATA
- imply CMD_REGINFO
- imply FSL_SATA
-
config ARCH_QEMU_E500
bool
select SYS_CACHE_SHIFT_5
@@ -850,7 +819,6 @@ config MAX_CPUS
default 12 if ARCH_T4240
default 4 if ARCH_B4860 || \
ARCH_P2041 || \
- ARCH_P5040 || \
ARCH_T1040 || \
ARCH_T1042 || \
ARCH_T2080
@@ -891,7 +859,6 @@ config SYS_CCSRBAR_DEFAULT
default 0xfe000000 if ARCH_B4420 || \
ARCH_B4860 || \
ARCH_P2041 || \
- ARCH_P5040 || \
ARCH_T1024 || \
ARCH_T1040 || \
ARCH_T1042 || \
@@ -937,9 +904,6 @@ config SYS_FSL_ERRATUM_A004508
config SYS_FSL_ERRATUM_A004580
bool
-config SYS_FSL_ERRATUM_A004699
- bool
-
config SYS_FSL_ERRATUM_A004849
bool
@@ -1086,7 +1050,6 @@ config SYS_FSL_NUM_LAWS
default 32 if ARCH_B4420 || \
ARCH_B4860 || \
ARCH_P2041 || \
- ARCH_P5040 || \
ARCH_T2080 || \
ARCH_T4240
default 16 if ARCH_T1024 || \
@@ -1248,8 +1211,7 @@ config SYS_FSL_LBC_CLK_DIV
depends on FSL_ELBC || ARCH_MPC8540 || \
ARCH_MPC8560
- default 2 if ARCH_P2041 || \
- ARCH_P5040
+ default 2 if ARCH_P2041
default 1
help
@@ -1307,7 +1269,7 @@ config SYS_FSL_SRIO_LIODN
config SYS_FSL_TBCLK_DIV
int
default 32 if ARCH_P2041
- default 16 if ARCH_P5040 || ARCH_T4240 || ARCH_B4860 || \
+ default 16 if ARCH_T4240 || ARCH_B4860 || \
ARCH_B4420 || ARCH_T1040 || ARCH_T1042 || \
ARCH_T1024 || ARCH_T2080
default 8
diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile
index a3622d60b16..b4bca7bbe6b 100644
--- a/arch/powerpc/cpu/mpc85xx/Makefile
+++ b/arch/powerpc/cpu/mpc85xx/Makefile
@@ -37,7 +37,6 @@ obj-$(CONFIG_SYS_DPAA_QBMAN) += portals.o
# various SoC specific assignments
obj-$(CONFIG_ARCH_P2041) += p2041_ids.o
-obj-$(CONFIG_ARCH_P5040) += p5040_ids.o
obj-$(CONFIG_ARCH_T4240) += t4240_ids.o
obj-$(CONFIG_ARCH_B4420) += b4860_ids.o
obj-$(CONFIG_ARCH_B4860) += b4860_ids.o
@@ -64,7 +63,6 @@ obj-$(CONFIG_ARCH_P1024) += p1021_serdes.o
obj-$(CONFIG_ARCH_P1025) += p1021_serdes.o
obj-$(CONFIG_ARCH_P2020) += p2020_serdes.o
obj-$(CONFIG_ARCH_P2041) += p2041_serdes.o
-obj-$(CONFIG_ARCH_P5040) += p5040_serdes.o
obj-$(CONFIG_ARCH_T4240) += t4240_serdes.o
obj-$(CONFIG_ARCH_B4420) += b4860_serdes.o
obj-$(CONFIG_ARCH_B4860) += b4860_serdes.o
diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
index 0a66f376f86..3f73a46c282 100644
--- a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
@@ -152,9 +152,6 @@ void fsl_serdes_init(void)
ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
int cfg;
serdes_corenet_t *srds_regs;
-#ifdef CONFIG_ARCH_P5040
- serdes_corenet_t *srds2_regs;
-#endif
int lane, bank, idx;
int have_bank[SRDS_MAX_BANK] = {};
if (serdes_prtcl_map & (1 << NONE))
@@ -181,34 +178,6 @@ void fsl_serdes_init(void)
}
}
-#ifdef CONFIG_ARCH_P5040
- /*
- * Lanes on bank 4 on P5040 are commented-out, but for some SERDES
- * protocols, these lanes are routed to SATA. We use serdes_prtcl_map
- * to decide whether a protocol is supported on a given lane, so SATA
- * will be identified as not supported, and therefore not initialized.
- * So for protocols which use SATA on bank4, we add SATA support in
- * serdes_prtcl_map.
- */
- switch (cfg) {
- case 0x0:
- case 0x1:
- case 0x2:
- case 0x3:
- case 0x4:
- case 0x5:
- case 0x6:
- case 0x7:
- serdes_prtcl_map |= 1 << SATA1 | 1 << SATA2;
- break;
- default:
- srds2_regs = (void *)CFG_SYS_FSL_CORENET_SERDES2_ADDR;
-
- /* We don't need bank 4, so power it down */
- setbits_be32(&srds2_regs->bank[0].rstctl, SRDS_RSTCTL_SDPD);
- }
-#endif
-
soc_serdes_init();
/* Set the first bit to indicate serdes has been initialized */
@@ -224,40 +193,6 @@ void fsl_serdes_init(void)
}
}
-#ifdef CONFIG_SYS_FSL_ERRATUM_A004699
- /*
- * To avoid the situation that resulted in the P4080 erratum
- * SERDES-8, a given SerDes bank will use the PLLs from the previous
- * bank if one of the PLL frequencies is a multiple of the other. For
- * instance, if bank 3 is running at 2.5GHz and bank 2 is at 1.25GHz,
- * then bank 3 will use bank 2's PLL. P5040 Erratum A-004699 says
- * that, in this situation, lane synchronization is not initiated. So
- * when we detect a bank with a "borrowed" PLL, we have to manually
- * initiate lane synchronization.
- */
- for (bank = FSL_SRDS_BANK_2; bank <= FSL_SRDS_BANK_3; bank++) {
- /* Determine the first lane for this bank */
- unsigned int lane;
-
- for (lane = 0; lane < SRDS_MAX_LANES; lane++)
- if (lanes[lane].bank == bank)
- break;
- idx = lanes[lane].idx;
-
- /*
- * Check if the PLL for the bank is borrowed. The UOTHL
- * bit of the first lane will tell us that.
- */
- if (in_be32(&srds_regs->lane[idx].gcr0) & SRDS_GCR0_UOTHL) {
- /* Manually start lane synchronization */
- setbits_be32(&srds_regs->bank[bank].pllcr0,
- SRDS_PLLCR0_PVCOCNT_EN);
- }
- }
-#endif
-
-
-
for (idx = 0; idx < SRDS_MAX_BANK; idx++) {
bank = idx;
diff --git a/arch/powerpc/cpu/mpc85xx/p5040_ids.c b/arch/powerpc/cpu/mpc85xx/p5040_ids.c
deleted file mode 100644
index 0a34e066e94..00000000000
--- a/arch/powerpc/cpu/mpc85xx/p5040_ids.c
+++ /dev/null
@@ -1,111 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2010-2011 Freescale Semiconductor, Inc.
- */
-
-#include <config.h>
-#include <linux/kernel.h>
-#include <asm/fsl_portals.h>
-#include <asm/fsl_liodn.h>
-
-#ifdef CONFIG_SYS_DPAA_QBMAN
-struct qportal_info qp_info[CFG_SYS_QMAN_NUM_PORTALS] = {
- /* dqrr liodn, frame data liodn, liodn off, sdest */
- SET_QP_INFO(1, 2, 1, 0),
- SET_QP_INFO(3, 4, 2, 1),
- SET_QP_INFO(5, 6, 3, 2),
- SET_QP_INFO(7, 8, 4, 3),
- SET_QP_INFO(9, 10, 5, 0),
- SET_QP_INFO(11, 12, 6, 1),
- SET_QP_INFO(13, 14, 7, 2),
- SET_QP_INFO(15, 16, 8, 3),
- SET_QP_INFO(17, 18, 9, 0), /* for now, set sdest to 0 */
- SET_QP_INFO(19, 20, 10, 0), /* for now, set sdest to 0 */
-};
-#endif
-
-struct liodn_id_table liodn_tbl[] = {
-#ifdef CONFIG_SYS_DPAA_QBMAN
- SET_QMAN_LIODN(31),
- SET_BMAN_LIODN(32),
-#endif
-
- SET_SDHC_LIODN(1, 64),
-
- SET_USB_LIODN(1, "fsl-usb2-mph", 93),
- SET_USB_LIODN(2, "fsl-usb2-dr", 94),
-
- SET_SATA_LIODN(1, 95),
- SET_SATA_LIODN(2, 96),
-
- SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 1, 195),
- SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 2, 196),
- SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 3, 197),
-
- SET_DMA_LIODN(1, "fsl,eloplus-dma", 193),
- SET_DMA_LIODN(2, "fsl,eloplus-dma", 194),
-};
-int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl);
-
-#ifdef CONFIG_SYS_DPAA_FMAN
-struct fman_liodn_id_table fman1_liodn_tbl[] = {
- SET_FMAN_RX_1G_LIODN(1, 0, 11),
- SET_FMAN_RX_1G_LIODN(1, 1, 12),
- SET_FMAN_RX_1G_LIODN(1, 2, 13),
- SET_FMAN_RX_1G_LIODN(1, 3, 14),
- SET_FMAN_RX_1G_LIODN(1, 4, 15),
- SET_FMAN_RX_10G_LIODN(1, 0, 16),
-};
-int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl);
-
-#if (CFG_SYS_NUM_FMAN == 2)
-struct fman_liodn_id_table fman2_liodn_tbl[] = {
- SET_FMAN_RX_1G_LIODN(2, 0, 17),
- SET_FMAN_RX_1G_LIODN(2, 1, 18),
- SET_FMAN_RX_1G_LIODN(2, 2, 19),
- SET_FMAN_RX_1G_LIODN(2, 3, 20),
- SET_FMAN_RX_1G_LIODN(2, 4, 21),
- SET_FMAN_RX_10G_LIODN(2, 0, 22),
-};
-int fman2_liodn_tbl_sz = ARRAY_SIZE(fman2_liodn_tbl);
-#endif
-#endif
-
-struct liodn_id_table sec_liodn_tbl[] = {
- SET_SEC_JR_LIODN_ENTRY(0, 129, 130),
- SET_SEC_JR_LIODN_ENTRY(1, 131, 132),
- SET_SEC_JR_LIODN_ENTRY(2, 133, 134),
- SET_SEC_JR_LIODN_ENTRY(3, 135, 136),
- SET_SEC_RTIC_LIODN_ENTRY(a, 89),
- SET_SEC_RTIC_LIODN_ENTRY(b, 90),
- SET_SEC_RTIC_LIODN_ENTRY(c, 91),
- SET_SEC_RTIC_LIODN_ENTRY(d, 92),
- SET_SEC_DECO_LIODN_ENTRY(0, 139, 140),
- SET_SEC_DECO_LIODN_ENTRY(1, 141, 142),
- SET_SEC_DECO_LIODN_ENTRY(2, 143, 144),
- SET_SEC_DECO_LIODN_ENTRY(3, 145, 146),
-};
-int sec_liodn_tbl_sz = ARRAY_SIZE(sec_liodn_tbl);
-
-#ifdef CONFIG_SYS_FSL_RAID_ENGINE
-struct liodn_id_table raide_liodn_tbl[] = {
- SET_RAID_ENGINE_JQ_LIODN_ENTRY(0, 0, 60),
- SET_RAID_ENGINE_JQ_LIODN_ENTRY(0, 1, 61),
- SET_RAID_ENGINE_JQ_LIODN_ENTRY(1, 0, 62),
- SET_RAID_ENGINE_JQ_LIODN_ENTRY(1, 1, 63),
-};
-int raide_liodn_tbl_sz = ARRAY_SIZE(raide_liodn_tbl);
-#endif
-
-struct liodn_id_table liodn_bases[] = {
- [FSL_HW_PORTAL_SEC] = SET_LIODN_BASE_2(64, 101),
-#ifdef CONFIG_SYS_DPAA_FMAN
- [FSL_HW_PORTAL_FMAN1] = SET_LIODN_BASE_1(32),
-#endif
-#if (CFG_SYS_NUM_FMAN == 2)
- [FSL_HW_PORTAL_FMAN2] = SET_LIODN_BASE_1(160),
-#endif
-#ifdef CONFIG_SYS_FSL_RAID_ENGINE
- [FSL_HW_PORTAL_RAID_ENGINE] = SET_LIODN_BASE_1(49),
-#endif
-};
diff --git a/arch/powerpc/cpu/mpc85xx/p5040_serdes.c b/arch/powerpc/cpu/mpc85xx/p5040_serdes.c
deleted file mode 100644
index 409f2ac938d..00000000000
--- a/arch/powerpc/cpu/mpc85xx/p5040_serdes.c
+++ /dev/null
@@ -1,99 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2009-2011 Freescale Semiconductor, Inc.
- */
-
-#include <asm/fsl_serdes.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include "fsl_corenet_serdes.h"
-
-/*
- * Note: For P5040, the fourth SerDes bank (with two lanes) is on SerDes2, but
- * U-Boot only supports one SerDes controller. Therefore, we ignore bank 4 in
- * this table. This works because most of the SerDes code is for errata
- * work-arounds, and there are no P5040 errata that effect bank 4.
- */
-
-static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = {
- [0x00] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2,
- SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4, SGMII_FM1_DTSEC1,
- SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
- XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2, /* SATA1, SATA2, */ },
- [0x01] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2,
- SGMII_FM1_DTSEC3, SGMII_FM2_DTSEC4, XAUI_FM1, XAUI_FM1,
- XAUI_FM1, XAUI_FM1, XAUI_FM2, XAUI_FM2, XAUI_FM2,
- XAUI_FM2, /* SATA1, SATA2 */ },
- [0x02] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, SGMII_FM1_DTSEC3,
- SGMII_FM1_DTSEC4, SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4,
- XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM2, XAUI_FM2,
- XAUI_FM2, XAUI_FM2, /* SATA1, SATA2 */ },
- [0x03] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, SGMII_FM2_DTSEC1,
- SGMII_FM2_DTSEC2, SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4,
- SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3,
- SGMII_FM1_DTSEC4, XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2,
- /* SATA1, SATA2 */ },
- [0x04] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE3, SGMII_FM2_DTSEC1,
- SGMII_FM2_DTSEC2, SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4,
- SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3,
- SGMII_FM1_DTSEC4, XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2,
- /* SATA1, SATA2 */ },
- [0x05] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE3, SGMII_FM1_DTSEC3,
- SGMII_FM1_DTSEC4, SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4,
- XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM2, XAUI_FM2,
- XAUI_FM2, XAUI_FM2, /* SATA1, SATA2 */ },
- [0x06] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1,
- SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4, SGMII_FM1_DTSEC1,
- SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
- XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2, /* SATA1, SATA2 */ },
- [0x07] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1,
- SGMII_FM1_DTSEC3, SGMII_FM2_DTSEC4, XAUI_FM1, XAUI_FM1,
- XAUI_FM1, XAUI_FM1, XAUI_FM2, XAUI_FM2, XAUI_FM2,
- XAUI_FM2, /* SATA1, SATA2 */ },
- [0x11] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2,
- AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
- SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2,
- /* NONE, NONE */ },
- [0x15] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2,
- AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1,
- NONE, NONE, SATA1, SATA2, /* NONE, NONE */ },
- [0x2a] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2, PCIE2, PCIE2,
- AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
- SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, XAUI_FM2, XAUI_FM2,
- XAUI_FM2, XAUI_FM2, /* NONE, NONE */ },
- [0x34] = {PCIE1, PCIE1, PCIE1, PCIE1, SGMII_FM1_DTSEC1,
- SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, AURORA,
- AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, NONE,
- NONE, SATA1, SATA2, /* NONE, NONE */ },
- [0x35] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2,
- SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, AURORA, AURORA, XAUI_FM1,
- XAUI_FM1, XAUI_FM1, XAUI_FM1, NONE, NONE, SATA1, SATA2,
- /* NONE, NONE */ },
- [0x36] = {PCIE1, PCIE1, PCIE3, PCIE3, SGMII_FM1_DTSEC1,
- SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, AURORA,
- AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, NONE,
- NONE, SATA1, SATA2, /* NONE, NONE */ },
-};
-
-enum srds_prtcl serdes_get_prtcl(int cfg, int lane)
-{
- if (!serdes_lane_enabled(lane))
- return NONE;
-
- return serdes_cfg_tbl[cfg][lane];
-}
-
-int is_serdes_prtcl_valid(u32 prtcl)
-{
- int i;
-
- if (prtcl >= ARRAY_SIZE(serdes_cfg_tbl))
- return 0;
-
- for (i = 0; i < SRDS_MAX_LANES; i++) {
- if (serdes_cfg_tbl[prtcl][i] != NONE)
- return 1;
- }
-
- return 0;
-}
diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c
index 8b575e85347..47daf51fc1b 100644
--- a/arch/powerpc/cpu/mpc8xxx/cpu.c
+++ b/arch/powerpc/cpu/mpc8xxx/cpu.c
@@ -60,7 +60,6 @@ static struct cpu_type cpu_type_list[] = {
CPU_TYPE_ENTRY(P5010, P5010, 1),
CPU_TYPE_ENTRY(P5020, P5020, 2),
CPU_TYPE_ENTRY(P5021, P5021, 2),
- CPU_TYPE_ENTRY(P5040, P5040, 4),
CPU_TYPE_ENTRY(T4240, T4240, 0),
CPU_TYPE_ENTRY(T4120, T4120, 0),
CPU_TYPE_ENTRY(T4160, T4160, 0),
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index 3701f29daa0..e5890376df8 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -44,15 +44,6 @@
#define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5
#define CFG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
-#elif defined(CONFIG_ARCH_P5040)
-#define CFG_SYS_NUM_FMAN 2
-#define CFG_SYS_NUM_FM1_DTSEC 5
-#define CFG_SYS_NUM_FM1_10GEC 1
-#define CFG_SYS_NUM_FM2_DTSEC 5
-#define CFG_SYS_NUM_FM2_10GEC 1
-#define CFG_SYS_FM_MURAM_SIZE 0x28000
-#define CFG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
-
#elif defined(CONFIG_ARCH_T4240)
#ifdef CONFIG_ARCH_T4240
#define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4 }
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index de1ae25440c..a9336d73f20 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1521,15 +1521,6 @@ typedef struct ccsr_gur {
#define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_MII 0x00100000
#define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_NONE 0x00180000
#endif
-#if defined(CONFIG_ARCH_P5040)
-#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_RGMII 0x00000000
-#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_MII 0x00800000
-#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_NONE 0x00c00000
-#define FSL_CORENET_RCWSR11_EC2 0x00180000 /* bits 363..364 */
-#define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_RGMII 0x00000000
-#define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_MII 0x00100000
-#define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_NONE 0x00180000
-#endif
#if defined(CONFIG_ARCH_T4240)
#define FSL_CORENET_RCWSR13_EC1 0x60000000 /* bits 417..418 */
#define FSL_CORENET_RCWSR13_EC1_FM2_DTSEC5_RGMII 0x00000000
@@ -2433,7 +2424,6 @@ struct ccsr_pman {
#define CFG_SYS_SFP_OFFSET 0xE8000
#endif
#define CFG_SYS_FSL_CORENET_SERDES_OFFSET 0xEA000
-#define CFG_SYS_FSL_CORENET_SERDES2_OFFSET 0xEB000
#define CFG_SYS_FSL_CORENET_SERDES3_OFFSET 0xEC000
#define CFG_SYS_FSL_CORENET_SERDES4_OFFSET 0xED000
#define CFG_SYS_FSL_CPC_OFFSET 0x10000
@@ -2608,8 +2598,6 @@ struct ccsr_pman {
(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_SERDES2_OFFSET)
#define CFG_SYS_FSL_CORENET_SERDES_ADDR \
(CONFIG_SYS_IMMR + CFG_SYS_FSL_CORENET_SERDES_OFFSET)
-#define CFG_SYS_FSL_CORENET_SERDES2_ADDR \
- (CONFIG_SYS_IMMR + CFG_SYS_FSL_CORENET_SERDES2_OFFSET)
#define CFG_SYS_FSL_CORENET_SERDES3_ADDR \
(CONFIG_SYS_IMMR + CFG_SYS_FSL_CORENET_SERDES3_OFFSET)
#define CFG_SYS_FSL_CORENET_SERDES4_ADDR \
diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h
index 1ddbf15c410..306dfd01346 100644
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -1052,7 +1052,6 @@
#define SVR_P5010 0x822100
#define SVR_P5020 0x822000
#define SVR_P5021 0x820500
-#define SVR_P5040 0x820400
#define SVR_T4240 0x824000
#define SVR_T4120 0x824001
#define SVR_T4160 0x824100
diff --git a/doc/README.pblimage b/doc/README.pblimage
index f4bdadfb2dd..66dc9cb0922 100644
--- a/doc/README.pblimage
+++ b/doc/README.pblimage
@@ -14,15 +14,15 @@ Building PBL Boot Image and boot steps
1. Building PBL Boot Image.
The default Image is u-boot.pbl.
- For eSPI boot(available on P2041/P5020/P5040/T4240):
+ For eSPI boot(available on P2041/P5020/T4240):
To build the eSPI boot image:
make <board_name>_SPIFLASH
- For SD boot(available on P2041/P5020/P5040/T4240):
+ For SD boot(available on P2041/P5020/T4240):
To build the SD boot image:
make <board_name>_SDCARD
- For Nand boot(available on P2041/P5020/P5040):
+ For Nand boot(available on P2041/P5020):
To build the NAND boot image:
make <board_name>_NAND
diff --git a/drivers/ddr/fsl/Kconfig b/drivers/ddr/fsl/Kconfig
index c518704d93e..91b439428ab 100644
--- a/drivers/ddr/fsl/Kconfig
+++ b/drivers/ddr/fsl/Kconfig
@@ -52,7 +52,6 @@ config SYS_NUM_DDR_CTLRS
ARCH_T4240
default 2 if ARCH_B4860 || \
ARCH_BSC9132 || \
- ARCH_P5040 || \
ARCH_LX2160A || \
ARCH_LX2162A
default 1
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index df243e8fe9b..b4224c24040 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -969,7 +969,6 @@ config SYS_DPAA_QBMAN
ARCH_T1042 || \
ARCH_T2080 || \
ARCH_T4240 || \
- ARCH_P5040 || \
ARCH_LS1043A || \
ARCH_LS1046A
help
diff --git a/drivers/net/fm/Makefile b/drivers/net/fm/Makefile
index e6727eeec98..6ec673feec4 100644
--- a/drivers/net/fm/Makefile
+++ b/drivers/net/fm/Makefile
@@ -16,7 +16,6 @@ obj-$(CONFIG_SYS_FMAN_V3) += memac.o
obj-$(CONFIG_ARCH_P1023) += p1023.o
# The P204x and P5020 are the same
obj-$(CONFIG_ARCH_P2041) += p5020.o
-obj-$(CONFIG_ARCH_P5040) += p5040.o
obj-$(CONFIG_ARCH_T1040) += t1040.o
obj-$(CONFIG_ARCH_T1042) += t1040.o
obj-$(CONFIG_ARCH_T1024) += t1024.o
diff --git a/drivers/net/fm/p5040.c b/drivers/net/fm/p5040.c
deleted file mode 100644
index f6ae947ef99..00000000000
--- a/drivers/net/fm/p5040.c
+++ /dev/null
@@ -1,106 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2011 Freescale Semiconductor, Inc.
- */
-#include <config.h>
-#include <phy.h>
-#include <fm_eth.h>
-#include <asm/io.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_serdes.h>
-
-u32 port_to_devdisr[] = {
- [FM1_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC1_1,
- [FM1_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC1_2,
- [FM1_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC1_3,
- [FM1_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC1_4,
- [FM1_DTSEC5] = FSL_CORENET_DEVDISR2_DTSEC1_5,
- [FM1_10GEC1] = FSL_CORENET_DEVDISR2_10GEC1,
- [FM2_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC2_1,
- [FM2_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC2_2,
- [FM2_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC2_3,
- [FM2_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC2_4,
- [FM2_DTSEC5] = FSL_CORENET_DEVDISR2_DTSEC2_5,
- [FM2_10GEC1] = FSL_CORENET_DEVDISR2_10GEC2,
-};
-
-static int is_device_disabled(enum fm_port port)
-{
- ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
- u32 devdisr2 = in_be32(&gur->devdisr2);
-
- return port_to_devdisr[port] & devdisr2;
-}
-
-void fman_disable_port(enum fm_port port)
-{
- ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
-
- /* don't allow disabling of DTSEC1 as its needed for MDIO */
- if (port == FM1_DTSEC1)
- return;
-
- setbits_be32(&gur->devdisr2, port_to_devdisr[port]);
-}
-
-void fman_enable_port(enum fm_port port)
-{
- ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
-
- clrbits_be32(&gur->devdisr2, port_to_devdisr[port]);
-}
-
-phy_interface_t fman_port_enet_if(enum fm_port port)
-{
- ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
- u32 rcwsr11 = in_be32(&gur->rcwsr[11]);
-
- if (is_device_disabled(port))
- return PHY_INTERFACE_MODE_NA;
-
- if ((port == FM1_10GEC1) && (is_serdes_configured(XAUI_FM1)))
- return PHY_INTERFACE_MODE_XGMII;
-
- if ((port == FM2_10GEC1) && (is_serdes_configured(XAUI_FM2)))
- return PHY_INTERFACE_MODE_XGMII;
-
- /* handle RGMII first */
- if ((port == FM1_DTSEC5) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC1) ==
- FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_RGMII))
- return PHY_INTERFACE_MODE_RGMII;
-
- if ((port == FM1_DTSEC5) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC1) ==
- FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_MII))
- return PHY_INTERFACE_MODE_MII;
-
- if ((port == FM2_DTSEC5) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) ==
- FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_RGMII))
- return PHY_INTERFACE_MODE_RGMII;
-
- if ((port == FM2_DTSEC5) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) ==
- FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_MII))
- return PHY_INTERFACE_MODE_MII;
-
- switch (port) {
- case FM1_DTSEC1:
- case FM1_DTSEC2:
- case FM1_DTSEC3:
- case FM1_DTSEC4:
- case FM1_DTSEC5:
- if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1))
- return PHY_INTERFACE_MODE_SGMII;
- break;
- case FM2_DTSEC1:
- case FM2_DTSEC2:
- case FM2_DTSEC3:
- case FM2_DTSEC4:
- case FM2_DTSEC5:
- if (is_serdes_configured(SGMII_FM2_DTSEC1 + port - FM2_DTSEC1))
- return PHY_INTERFACE_MODE_SGMII;
- break;
- default:
- return PHY_INTERFACE_MODE_NA;
- }
-
- return PHY_INTERFACE_MODE_NA;
-}
diff --git a/drivers/usb/common/fsl-errata.c b/drivers/usb/common/fsl-errata.c
index b6fc8182092..1b84614c8f5 100644
--- a/drivers/usb/common/fsl-errata.c
+++ b/drivers/usb/common/fsl-errata.c
@@ -61,7 +61,6 @@ bool has_erratum_a005275(void)
case SVR_P5020:
case SVR_P5021:
return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0);
- case SVR_P5040:
case SVR_P1010:
return IS_SVR_REV(svr, 1, 0);
#endif
@@ -90,9 +89,6 @@ bool has_erratum_a006261(void)
return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0);
case SVR_T4240:
return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0);
- case SVR_P5040:
- return IS_SVR_REV(svr, 1, 0) ||
- IS_SVR_REV(svr, 2, 0) || IS_SVR_REV(svr, 2, 1);
#endif
}
--
2.47.3
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH 11/26] powerpc: mpc83xx: Remove MPC837x support
2026-10-09 19:36 [PATCH 00/26] powerpc: drop EOL boards and SoCs, take over maintenance Bradley Morgan
` (9 preceding siblings ...)
2026-10-09 19:36 ` [PATCH 10/26] powerpc: mpc85xx: Remove P5040 support Bradley Morgan
@ 2026-10-09 19:36 ` Bradley Morgan
2026-10-09 19:36 ` [PATCH 12/26] powerpc: mpc85xx: Remove C29x support Bradley Morgan
` (14 subsequent siblings)
25 siblings, 0 replies; 31+ messages in thread
From: Bradley Morgan @ 2026-10-09 19:36 UTC (permalink / raw)
To: Tom Rini, u-boot
Cc: Bradley Morgan, Marek Behún, Marek Mojík,
NXP i . MX U-Boot Team, Alexey Charkov, Anshul Dalal,
Daniel Golle, Fabio Estevam, Gaurav Jain, Ilias Apalodimas,
Jaehoon Chung, James Hilliard, Jerome Forissier, Johan Jonker,
Lukasz Majewski, Marek Vasut, Mario Six, Michael Walle,
Michal Simek, Neil Armstrong, Peng Fan, Pengpeng Hou,
Priyanka Jain, Quentin Schulz, Simon Glass, Stefano Babic,
Tanmay Kathpalia, Torsten Rupp, Vincent Jardin, Weijie Gao
MPC837XERDB was the last user in the tree of ARCH_MPC837X. NXP lists the MPC8377E and MPC8379E as no longer manufactured, the MPC8378E as end of life, and archives the board.
Nothing selects the SoC option now. Drop its clock, CPU, reset and peripheral support.
Signed-off-by: Bradley Morgan <brads@mainlining.org>
---
arch/powerpc/cpu/mpc83xx/Kconfig | 20 ---
arch/powerpc/cpu/mpc83xx/cpu.c | 3 -
arch/powerpc/cpu/mpc83xx/hid/Kconfig | 4 +-
arch/powerpc/cpu/mpc83xx/hrcw/Kconfig | 52 ++++----
arch/powerpc/cpu/mpc83xx/initreg/Kconfig.spcr | 2 +-
arch/powerpc/cpu/mpc83xx/speed.c | 57 ++-------
arch/powerpc/include/asm/arch-mpc83xx/gpio.h | 2 +-
arch/powerpc/include/asm/arch-mpc83xx/soc.h | 16 +--
arch/powerpc/include/asm/global_data.h | 8 +-
arch/powerpc/include/asm/immap_83xx.h | 45 -------
arch/powerpc/include/asm/mpc8xxx_spi.h | 3 +-
doc/README.sata | 68 ----------
.../clock/fsl,mpc83xx-clk.txt | 3 +-
doc/device-tree-bindings/cpu/fsl,mpc83xx.txt | 3 +-
drivers/clk/mpc83xx_clk.c | 1 -
drivers/clk/mpc83xx_clk.h | 11 +-
drivers/cpu/mpc83xx_cpu.c | 13 --
drivers/cpu/mpc83xx_cpu.h | 11 --
drivers/ram/mpc83xx_sdram.c | 12 +-
include/mpc83xx.h | 120 +-----------------
20 files changed, 58 insertions(+), 396 deletions(-)
delete mode 100644 doc/README.sata
diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig
index 088283d646c..daae933e52e 100644
--- a/arch/powerpc/cpu/mpc83xx/Kconfig
+++ b/arch/powerpc/cpu/mpc83xx/Kconfig
@@ -103,15 +103,9 @@ config MPC83XX_TSEC2_SUPPORT
config MPC83XX_PCIE1_SUPPORT
bool
-config MPC83XX_PCIE2_SUPPORT
- bool
-
config MPC83XX_SDHC_SUPPORT
bool
-config MPC83XX_SATA
- bool
-
config MPC83XX_SECOND_I2C
bool
@@ -162,20 +156,6 @@ config ARCH_MPC8360
select MPC83XX_SECOND_I2C
select SYS_CACHE_SHIFT_5
-config ARCH_MPC837X
- bool
- select MPC83XX_PCI_SUPPORT
- select MPC83XX_TSEC1_SUPPORT
- select MPC83XX_TSEC2_SUPPORT
- select MPC83XX_PCIE1_SUPPORT
- select MPC83XX_PCIE2_SUPPORT
- select MPC83XX_SDHC_SUPPORT
- select MPC83XX_SATA
- select MPC83XX_LDP_PIN
- select MPC83XX_SECOND_I2C
- select SYS_CACHE_SHIFT_5
- select FSL_ELBC
-
source "arch/powerpc/cpu/mpc83xx/hrcw/Kconfig"
source "arch/powerpc/cpu/mpc83xx/bats/Kconfig"
source "arch/powerpc/cpu/mpc83xx/lblaw/Kconfig"
diff --git a/arch/powerpc/cpu/mpc83xx/cpu.c b/arch/powerpc/cpu/mpc83xx/cpu.c
index 3c8cbd4252d..f8e9f716936 100644
--- a/arch/powerpc/cpu/mpc83xx/cpu.c
+++ b/arch/powerpc/cpu/mpc83xx/cpu.c
@@ -61,9 +61,6 @@ int checkcpu(void)
CPU_TYPE_ENTRY(8358_TBGA_),
CPU_TYPE_ENTRY(8358_PBGA_),
CPU_TYPE_ENTRY(8360),
- CPU_TYPE_ENTRY(8377),
- CPU_TYPE_ENTRY(8378),
- CPU_TYPE_ENTRY(8379),
};
immr = (immap_t *)CONFIG_SYS_IMMR;
diff --git a/arch/powerpc/cpu/mpc83xx/hid/Kconfig b/arch/powerpc/cpu/mpc83xx/hid/Kconfig
index 9473213bac4..e733a59d021 100644
--- a/arch/powerpc/cpu/mpc83xx/hid/Kconfig
+++ b/arch/powerpc/cpu/mpc83xx/hid/Kconfig
@@ -434,7 +434,7 @@ config HID2_IWLCK_1
config HID2_IWLCK_2
bool "Way 0 through 2 locked"
-if ARCH_MPC8360 || ARCH_MPC837X
+if ARCH_MPC8360
config HID2_IWLCK_3
bool "Way 0 through 3 locked"
@@ -470,7 +470,7 @@ config HID2_DWLCK_1
config HID2_DWLCK_2
bool "Way 0 through 2 locked"
-if ARCH_MPC8360 || ARCH_MPC837X
+if ARCH_MPC8360
config HID2_DWLCK_3
bool "Way 0 through 3 locked"
diff --git a/arch/powerpc/cpu/mpc83xx/hrcw/Kconfig b/arch/powerpc/cpu/mpc83xx/hrcw/Kconfig
index 0fc3b7765f2..49d5db098f7 100644
--- a/arch/powerpc/cpu/mpc83xx/hrcw/Kconfig
+++ b/arch/powerpc/cpu/mpc83xx/hrcw/Kconfig
@@ -7,7 +7,7 @@ config LBMC_CLOCK_MODE_1_1
bool "1 : 1"
config LBMC_CLOCK_MODE_1_2
- depends on ARCH_MPC8360 || ARCH_MPC837X
+ depends on ARCH_MPC8360
bool "1 : 2"
endchoice
@@ -19,7 +19,7 @@ config DDR_MC_CLOCK_MODE_1_2
bool "1 : 2"
config DDR_MC_CLOCK_MODE_1_1
- depends on ARCH_MPC8360 || ARCH_MPC837X
+ depends on ARCH_MPC8360
bool "1 : 1"
endchoice
@@ -30,7 +30,6 @@ choice
prompt "System PLL VCO division"
config SYSTEM_PLL_VCO_DIV_1
- depends on !ARCH_MPC837X
bool "1"
config SYSTEM_PLL_VCO_DIV_2
@@ -67,39 +66,39 @@ config SYSTEM_PLL_FACTOR_6_1
bool "6 : 1"
config SYSTEM_PLL_FACTOR_7_1
- depends on ARCH_MPC8360 || ARCH_MPC837X
+ depends on ARCH_MPC8360
bool "7 : 1"
config SYSTEM_PLL_FACTOR_8_1
- depends on ARCH_MPC8360 || ARCH_MPC837X
+ depends on ARCH_MPC8360
bool "8 : 1"
config SYSTEM_PLL_FACTOR_9_1
- depends on ARCH_MPC8360 || ARCH_MPC837X
+ depends on ARCH_MPC8360
bool "9 : 1"
config SYSTEM_PLL_FACTOR_10_1
- depends on ARCH_MPC8360 || ARCH_MPC837X
+ depends on ARCH_MPC8360
bool "10 : 1"
config SYSTEM_PLL_FACTOR_11_1
- depends on ARCH_MPC8360 || ARCH_MPC837X
+ depends on ARCH_MPC8360
bool "11 : 1"
config SYSTEM_PLL_FACTOR_12_1
- depends on ARCH_MPC8360 || ARCH_MPC837X
+ depends on ARCH_MPC8360
bool "12 : 1"
config SYSTEM_PLL_FACTOR_13_1
- depends on ARCH_MPC8360 || ARCH_MPC837X
+ depends on ARCH_MPC8360
bool "13 : 1"
config SYSTEM_PLL_FACTOR_14_1
- depends on ARCH_MPC8360 || ARCH_MPC837X
+ depends on ARCH_MPC8360
bool "14 : 1"
config SYSTEM_PLL_FACTOR_15_1
- depends on ARCH_MPC8360 || ARCH_MPC837X
+ depends on ARCH_MPC8360
bool "15 : 1"
config SYSTEM_PLL_FACTOR_16_1
@@ -391,10 +390,6 @@ config BOOT_ROM_INTERFACE_PCI1
depends on MPC83XX_PCI_SUPPORT
bool "PCI1"
-config BOOT_ROM_INTERFACE_ON_CHIP_BOOT_ROM
- depends on ARCH_MPC837X
- bool "PCI2"
-
config BOOT_ROM_INTERFACE_GPCM_8BIT
bool "Local bus GPCM - 8-bit ROM"
@@ -402,7 +397,7 @@ config BOOT_ROM_INTERFACE_GPCM_16BIT
bool "Local bus GPCM - 16-bit ROM"
config BOOT_ROM_INTERFACE_GPCM_32BIT
- depends on ARCH_MPC8360 || ARCH_MPC837X
+ depends on ARCH_MPC8360
bool "Local bus GPCM - 32-bit ROM"
config BOOT_ROM_INTERFACE_NAND_FLASH_8BIT_SMALL
@@ -431,11 +426,11 @@ config TSEC1_MODE_RGMII
bool "RGMII"
config TSEC1_MODE_RTBI
- depends on ARCH_MPC831X || ARCH_MPC837X
+ depends on ARCH_MPC831X
bool "RTBI"
config TSEC1_MODE_SGMII
- depends on ARCH_MPC831X || ARCH_MPC837X
+ depends on ARCH_MPC831X
bool "SGMII"
endchoice
@@ -458,11 +453,11 @@ config TSEC2_MODE_RGMII
bool "RGMII"
config TSEC2_MODE_RTBI
- depends on ARCH_MPC831X || ARCH_MPC837X
+ depends on ARCH_MPC831X
bool "RTBI"
config TSEC2_MODE_SGMII
- depends on ARCH_MPC831X || ARCH_MPC837X
+ depends on ARCH_MPC831X
bool "SGMII"
endchoice
@@ -540,12 +535,12 @@ config DDR_MC_CLOCK_MODE
config SYSTEM_PLL_VCO_DIV
int
default 2 if ARCH_MPC8313 || ARCH_MPC832X
- default 0 if SYSTEM_PLL_VCO_DIV_2 && !ARCH_MPC8360 && !ARCH_MPC837X
- default 1 if SYSTEM_PLL_VCO_DIV_4 && !ARCH_MPC8360 && !ARCH_MPC837X
- default 2 if SYSTEM_PLL_VCO_DIV_8 && !ARCH_MPC8360 && !ARCH_MPC837X
- default 0 if SYSTEM_PLL_VCO_DIV_4 && (ARCH_MPC8360 || ARCH_MPC837X)
- default 1 if SYSTEM_PLL_VCO_DIV_8 && (ARCH_MPC8360 || ARCH_MPC837X)
- default 2 if SYSTEM_PLL_VCO_DIV_2 && (ARCH_MPC8360 || ARCH_MPC837X)
+ default 0 if SYSTEM_PLL_VCO_DIV_2 && !ARCH_MPC8360
+ default 1 if SYSTEM_PLL_VCO_DIV_4 && !ARCH_MPC8360
+ default 2 if SYSTEM_PLL_VCO_DIV_8 && !ARCH_MPC8360
+ default 0 if SYSTEM_PLL_VCO_DIV_4 && ARCH_MPC8360
+ default 1 if SYSTEM_PLL_VCO_DIV_8 && ARCH_MPC8360
+ default 2 if SYSTEM_PLL_VCO_DIV_2 && ARCH_MPC8360
default 3 if SYSTEM_PLL_VCO_DIV_1
config SYSTEM_PLL_FACTOR
@@ -610,7 +605,6 @@ config BOOT_ROM_INTERFACE
hex
default 0x0 if BOOT_ROM_INTERFACE_DDR_SDRAM
default 0x4 if BOOT_ROM_INTERFACE_PCI1
- default 0xc if BOOT_ROM_INTERFACE_ON_CHIP_BOOT_ROM
default 0x14 if BOOT_ROM_INTERFACE_GPCM_8BIT
default 0x18 if BOOT_ROM_INTERFACE_GPCM_16BIT
default 0x1c if BOOT_ROM_INTERFACE_GPCM_32BIT
@@ -648,7 +642,7 @@ config TRUE_LITTLE_ENDIAN
config LALE_TIMING
int
- default 0 if ARCH_MPC830X || ARCH_MPC837X
+ default 0 if ARCH_MPC830X
default 0 if LALE_TIMING_NORMAL
default 1 if LALE_TIMING_EARLIER
diff --git a/arch/powerpc/cpu/mpc83xx/initreg/Kconfig.spcr b/arch/powerpc/cpu/mpc83xx/initreg/Kconfig.spcr
index 33e1295df14..91686b3b8b4 100644
--- a/arch/powerpc/cpu/mpc83xx/initreg/Kconfig.spcr
+++ b/arch/powerpc/cpu/mpc83xx/initreg/Kconfig.spcr
@@ -14,7 +14,7 @@ config SPCR_OPT_SPEC_READ
endchoice
-if ARCH_MPC8308 || ARCH_MPC831X || ARCH_MPC837X
+if ARCH_MPC8308 || ARCH_MPC831X
choice
prompt "TSEC emergency priority"
diff --git a/arch/powerpc/cpu/mpc83xx/speed.c b/arch/powerpc/cpu/mpc83xx/speed.c
index 0185ab50ad9..a2343c67f28 100644
--- a/arch/powerpc/cpu/mpc83xx/speed.c
+++ b/arch/powerpc/cpu/mpc83xx/speed.c
@@ -88,7 +88,7 @@ int get_clocks(void)
u32 csb_clk;
#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
- defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X)
+ defined(CONFIG_ARCH_MPC834X)
u32 tsec1_clk;
u32 tsec2_clk;
u32 usbdr_clk;
@@ -117,14 +117,10 @@ int get_clocks(void)
u32 qe_clk;
u32 brg_clk;
#endif
-#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
- defined(CONFIG_ARCH_MPC837X)
+#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X)
u32 pciexp1_clk;
u32 pciexp2_clk;
#endif
-#if defined(CONFIG_ARCH_MPC837X)
- u32 sata_clk;
-#endif
if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
return -1;
@@ -151,7 +147,7 @@ int get_clocks(void)
sccr = im->clk.sccr;
#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
- defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X)
+ defined(CONFIG_ARCH_MPC834X)
switch ((sccr & SCCR_TSEC1CM) >> SCCR_TSEC1CM_SHIFT) {
case 0:
tsec1_clk = 0;
@@ -172,7 +168,7 @@ int get_clocks(void)
#endif
#if defined(CONFIG_ARCH_MPC830X) || defined(CONFIG_ARCH_MPC831X) || \
- defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X)
+ defined(CONFIG_ARCH_MPC834X)
switch ((sccr & SCCR_USBDRCM) >> SCCR_USBDRCM_SHIFT) {
case 0:
usbdr_clk = 0;
@@ -192,8 +188,7 @@ int get_clocks(void)
}
#endif
-#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC834X) || \
- defined(CONFIG_ARCH_MPC837X)
+#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC834X)
switch ((sccr & SCCR_TSEC2CM) >> SCCR_TSEC2CM_SHIFT) {
case 0:
tsec2_clk = 0;
@@ -295,15 +290,12 @@ int get_clocks(void)
i2c1_clk = enc_clk;
#elif defined(CONFIG_FSL_ESDHC)
i2c1_clk = sdhc_clk;
-#elif defined(CONFIG_ARCH_MPC837X)
- i2c1_clk = enc_clk;
#endif
#if !defined(CONFIG_ARCH_MPC832X)
i2c2_clk = csb_clk; /* i2c-2 clk is equal to csb clk */
#endif
-#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
- defined(CONFIG_ARCH_MPC837X)
+#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X)
switch ((sccr & SCCR_PCIEXP1CM) >> SCCR_PCIEXP1CM_SHIFT) {
case 0:
pciexp1_clk = 0;
@@ -341,26 +333,6 @@ int get_clocks(void)
}
#endif
-#if defined(CONFIG_ARCH_MPC837X)
- switch ((sccr & SCCR_SATA1CM) >> SCCR_SATA1CM_SHIFT) {
- case 0:
- sata_clk = 0;
- break;
- case 1:
- sata_clk = csb_clk;
- break;
- case 2:
- sata_clk = csb_clk / 2;
- break;
- case 3:
- sata_clk = csb_clk / 3;
- break;
- default:
- /* unknown SCCR_SATA1CM value */
- return -11;
- }
-#endif
-
lbiu_clk = csb_clk *
(1 + ((im->clk.spmr & SPMR_LBIUCM) >> SPMR_LBIUCM_SHIFT));
lcrr = (im->im_lbc.lcrr & LCRR_CLKDIV) >> LCRR_CLKDIV_SHIFT;
@@ -421,7 +393,7 @@ int get_clocks(void)
gd->arch.csb_clk = csb_clk;
#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
- defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X)
+ defined(CONFIG_ARCH_MPC834X)
gd->arch.tsec1_clk = tsec1_clk;
gd->arch.tsec2_clk = tsec2_clk;
gd->arch.usbdr_clk = usbdr_clk;
@@ -448,13 +420,9 @@ int get_clocks(void)
gd->arch.qe_clk = qe_clk;
gd->arch.brg_clk = brg_clk;
#endif
-#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
- defined(CONFIG_ARCH_MPC837X)
+#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X)
gd->arch.pciexp1_clk = pciexp1_clk;
gd->arch.pciexp2_clk = pciexp2_clk;
-#endif
-#if defined(CONFIG_ARCH_MPC837X)
- gd->arch.sata_clk = sata_clk;
#endif
gd->arch.pci_clk = pci_sync_in;
gd->cpu_clk = gd->arch.core_clk;
@@ -524,7 +492,7 @@ static int do_clocks(struct cmd_tbl *cmdtp, int flag, int argc,
strmhz(buf, gd->arch.sdhc_clk));
#endif
#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
- defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X)
+ defined(CONFIG_ARCH_MPC834X)
printf(" TSEC1: %-4s MHz\n",
strmhz(buf, gd->arch.tsec1_clk));
printf(" TSEC2: %-4s MHz\n",
@@ -536,16 +504,11 @@ static int do_clocks(struct cmd_tbl *cmdtp, int flag, int argc,
printf(" USB MPH: %-4s MHz\n",
strmhz(buf, gd->arch.usbmph_clk));
#endif
-#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
- defined(CONFIG_ARCH_MPC837X)
+#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X)
printf(" PCIEXP1: %-4s MHz\n",
strmhz(buf, gd->arch.pciexp1_clk));
printf(" PCIEXP2: %-4s MHz\n",
strmhz(buf, gd->arch.pciexp2_clk));
-#endif
-#if defined(CONFIG_ARCH_MPC837X)
- printf(" SATA: %-4s MHz\n",
- strmhz(buf, gd->arch.sata_clk));
#endif
return 0;
}
diff --git a/arch/powerpc/include/asm/arch-mpc83xx/gpio.h b/arch/powerpc/include/asm/arch-mpc83xx/gpio.h
index df95d2238fd..dd368af7b91 100644
--- a/arch/powerpc/include/asm/arch-mpc83xx/gpio.h
+++ b/arch/powerpc/include/asm/arch-mpc83xx/gpio.h
@@ -8,7 +8,7 @@
*/
#if defined(CONFIG_ARCH_MPC8313) || defined(CONFIG_ARCH_MPC8308)
#define MPC83XX_GPIO_CTRLRS 1
-#elif defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X)
+#elif defined(CONFIG_ARCH_MPC834X)
#define MPC83XX_GPIO_CTRLRS 2
#else
#define MPC83XX_GPIO_CTRLRS 0
diff --git a/arch/powerpc/include/asm/arch-mpc83xx/soc.h b/arch/powerpc/include/asm/arch-mpc83xx/soc.h
index ce54f9bebbe..d61d3a944f1 100644
--- a/arch/powerpc/include/asm/arch-mpc83xx/soc.h
+++ b/arch/powerpc/include/asm/arch-mpc83xx/soc.h
@@ -15,14 +15,12 @@ enum soc_type {
SOC_MPC832X,
SOC_MPC8349,
SOC_MPC8360,
- SOC_MPC8379,
};
static inline bool mpc83xx_has_sdhc(int type)
{
return (type == SOC_MPC8308) ||
- (type == SOC_MPC8309) ||
- (type == SOC_MPC8379);
+ (type == SOC_MPC8309);
}
static inline bool mpc83xx_has_tsec(int type)
@@ -30,27 +28,23 @@ static inline bool mpc83xx_has_tsec(int type)
return (type == SOC_MPC8308) ||
(type == SOC_MPC8313) ||
(type == SOC_MPC8315) ||
- (type == SOC_MPC8349) ||
- (type == SOC_MPC8379);
+ (type == SOC_MPC8349);
}
static inline bool mpc83xx_has_pcie1(int type)
{
return (type == SOC_MPC8308) ||
- (type == SOC_MPC8315) ||
- (type == SOC_MPC8379);
+ (type == SOC_MPC8315);
}
static inline bool mpc83xx_has_pcie2(int type)
{
- return (type == SOC_MPC8315) ||
- (type == SOC_MPC8379);
+ return type == SOC_MPC8315;
}
static inline bool mpc83xx_has_sata(int type)
{
- return (type == SOC_MPC8315) ||
- (type == SOC_MPC8379);
+ return type == SOC_MPC8315;
}
static inline bool mpc83xx_has_pci(int type)
diff --git a/arch/powerpc/include/asm/global_data.h b/arch/powerpc/include/asm/global_data.h
index 26cbc7854d9..608e49667af 100644
--- a/arch/powerpc/include/asm/global_data.h
+++ b/arch/powerpc/include/asm/global_data.h
@@ -27,7 +27,7 @@ struct arch_global_data {
/* There are other clocks in the MPC83XX */
u32 csb_clk;
# if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
- defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X)
+ defined(CONFIG_ARCH_MPC834X)
u32 tsec1_clk;
u32 tsec2_clk;
u32 usbdr_clk;
@@ -39,14 +39,10 @@ struct arch_global_data {
u32 enc_clk;
u32 lbiu_clk;
u32 lclk_clk;
-# if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
- defined(CONFIG_ARCH_MPC837X)
+# if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X)
u32 pciexp1_clk;
u32 pciexp2_clk;
# endif
-# if defined(CONFIG_ARCH_MPC837X)
- u32 sata_clk;
-# endif
# if defined(CONFIG_ARCH_MPC8360)
u32 mem_sec_clk;
# endif /* CONFIG_ARCH_MPC8360 */
diff --git a/arch/powerpc/include/asm/immap_83xx.h b/arch/powerpc/include/asm/immap_83xx.h
index 1fa6073b268..2eff504a80d 100644
--- a/arch/powerpc/include/asm/immap_83xx.h
+++ b/arch/powerpc/include/asm/immap_83xx.h
@@ -760,51 +760,6 @@ typedef struct immap {
} immap_t;
static_assert(sizeof(immap_t) == 0x100000);
-#elif defined(CONFIG_ARCH_MPC837X)
-typedef struct immap {
- sysconf83xx_t sysconf; /* System configuration */
- wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
- rtclk83xx_t rtc; /* Real Time Clock Module Registers */
- rtclk83xx_t pit; /* Periodic Interval Timer */
- gtm83xx_t gtm[2]; /* Global Timers Module */
- ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
- arbiter83xx_t arbiter; /* System Arbiter Registers */
- reset83xx_t reset; /* Reset Module */
- clk83xx_t clk; /* System Clock Module */
- pmc83xx_t pmc; /* Power Management Control Module */
- gpio83xx_t gpio[2]; /* General purpose I/O module */
- u8 res0[0x1200];
- ddr83xx_t ddr; /* DDR Memory Controller Memory */
- fsl_i2c_t i2c[2]; /* I2C Controllers */
- u8 res1[0x1300];
- duart83xx_t duart[2]; /* DUART */
- u8 res2[0x900];
- fsl_lbc_t im_lbc; /* Local Bus Controller Regs */
- u8 res3[0x1000];
- spi8xxx_t spi; /* Serial Peripheral Interface */
- dma83xx_t dma; /* DMA */
- pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */
- u8 res4[0x80];
- ios83xx_t ios; /* Sequencer */
- pcictrl83xx_t pci_ctrl[1]; /* PCI Controller Control and Status Registers */
- u8 res5[0xa00];
- pex83xx_t pciexp[2]; /* PCI Express Controller */
- u8 res6[0xd000];
- sata83xx_t sata[4]; /* SATA Controller */
- u8 res7[0x7000];
- usb83xx_t usb[1]; /* USB DR Controller */
- tsec83xx_t tsec[2];
- u8 res8[0x8000];
- sdhc83xx_t sdhc; /* SDHC Controller */
- u8 res9[0x1000];
- security83xx_t security;
- u8 res10[0xA3000];
- serdes83xx_t serdes[2]; /* SerDes Registers */
- u8 res11[0xCE00];
- rom83xx_t rom; /* On Chip ROM */
-} immap_t;
-static_assert(sizeof(immap_t) == 0x100000);
-
#elif defined(CONFIG_ARCH_MPC8360)
typedef struct immap {
sysconf83xx_t sysconf; /* System configuration */
diff --git a/arch/powerpc/include/asm/mpc8xxx_spi.h b/arch/powerpc/include/asm/mpc8xxx_spi.h
index 2b2095ad481..c136b3fb4af 100644
--- a/arch/powerpc/include/asm/mpc8xxx_spi.h
+++ b/arch/powerpc/include/asm/mpc8xxx_spi.h
@@ -13,8 +13,7 @@
#if defined(CONFIG_ARCH_MPC8308) || \
defined(CONFIG_ARCH_MPC8313) || \
defined(CONFIG_ARCH_MPC832X) || \
- defined(CONFIG_ARCH_MPC834X) || \
- defined(CONFIG_ARCH_MPC837X)
+ defined(CONFIG_ARCH_MPC834X)
typedef struct spi8xxx {
u8 res0[0x20]; /* 0x0-0x01f reserved */
diff --git a/doc/README.sata b/doc/README.sata
deleted file mode 100644
index b1104bbd3b9..00000000000
--- a/doc/README.sata
+++ /dev/null
@@ -1,68 +0,0 @@
-1. SATA usage in U-Boot
-
- There are two ways to operate the hard disk
-
- * Read/write raw blocks from/to SATA hard disk
- * ext2load to read a file from ext2 file system
-
-1.0 How to read the SATA hard disk's information?
-
- => sata info
-
-SATA device 0: Model: ST3320620AS Firm: 3.AAD Ser#: 4QF01ZTN
- Type: Hard Disk
- Supports 48-bit addressing
- Capacity: 305245.3 MB = 298.0 GB (625142448 x 512)
-
-1.1 How to raw write the kernel, file system, dtb to a SATA hard disk?
-
- Notes: Hard disk sectors are normally 512 bytes, so
- 0x1000 sectors = 2 MBytes
-
- write kernel
- => tftp 40000 /tftpboot/uImage.837x
- => sata write 40000 0 2000
-
- write ramdisk
- => tftp 40000 /tftpboot/ramdisk.837x
- => sata write 40000 2000 8000
-
- write dtb
- => tftp 40000 /tftpboot/mpc837xemds.dtb
- => sata write 40000 a000 1000
-
-1.2 How to raw read the kernel, file system, dtb from a SATA hard disk?
-
- load kernel
- => sata read 200000 0 2000
-
- load ramdisk
- => sata read 1000000 2000 8000
-
- load dtb
- => sata read 2000000 a000 1000
-
- boot
- => bootm 200000 1000000 2000000
-
-1.3 How to load an image from an ext2 file system in U-Boot?
-
- U-Boot doesn't support writing to an ext2 file system, so the
- files must be written by other means (e.g. linux).
-
- => ext2ls sata 0:1 /
- <DIR> 4096 .
- <DIR> 4096 ..
- <DIR> 16384 lost+found
- 1352023 uImage.837x
- 3646377 ramdisk.837x
- 12288 mpc837xemds.dtb
- 12 hello.txt
-
- => ext2load sata 0:1 200000 /uImage.837x
-
- => ext2load sata 0:1 1000000 /ramdisk.837x
-
- => ext2load sata 0:1 2000000 /mpc837xemds.dtb
-
- => bootm 200000 1000000 2000000
diff --git a/doc/device-tree-bindings/clock/fsl,mpc83xx-clk.txt b/doc/device-tree-bindings/clock/fsl,mpc83xx-clk.txt
index 8313da85076..065575d87f0 100644
--- a/doc/device-tree-bindings/clock/fsl,mpc83xx-clk.txt
+++ b/doc/device-tree-bindings/clock/fsl,mpc83xx-clk.txt
@@ -10,8 +10,7 @@ Required properties:
"fsl,mpc8315-clk",
"fsl,mpc832x-clk",
"fsl,mpc8349-clk",
- "fsl,mpc8360-clk",
- "fsl,mpc8379-clk"
+ "fsl,mpc8360-clk"
depending on which SoC is employed
- #clock-cells: Must be 1
diff --git a/doc/device-tree-bindings/cpu/fsl,mpc83xx.txt b/doc/device-tree-bindings/cpu/fsl,mpc83xx.txt
index ac563d906ac..efdcdfbdba0 100644
--- a/doc/device-tree-bindings/cpu/fsl,mpc83xx.txt
+++ b/doc/device-tree-bindings/cpu/fsl,mpc83xx.txt
@@ -10,8 +10,7 @@ Required properties:
"fsl,mpc8315",
"fsl,mpc832x",
"fsl,mpc8349",
- "fsl,mpc8360",
- "fsl,mpc8379"
+ "fsl,mpc8360"
- clocks: has to have two entries, which must be the core clock at index 0 and
the CSB (Coherent System Bus) clock at index 1. Both are given by a suitable
"fsl,mpc83xx-clk" device
diff --git a/drivers/clk/mpc83xx_clk.c b/drivers/clk/mpc83xx_clk.c
index a43fff2e7ed..20f77a983da 100644
--- a/drivers/clk/mpc83xx_clk.c
+++ b/drivers/clk/mpc83xx_clk.c
@@ -326,7 +326,6 @@ static const struct udevice_id mpc83xx_clk_match[] = {
{ .compatible = "fsl,mpc832x-clk", .data = SOC_MPC832X },
{ .compatible = "fsl,mpc8349-clk", .data = SOC_MPC8349 },
{ .compatible = "fsl,mpc8360-clk", .data = SOC_MPC8360 },
- { .compatible = "fsl,mpc8379-clk", .data = SOC_MPC8379 },
{ /* sentinel */ }
};
diff --git a/drivers/clk/mpc83xx_clk.h b/drivers/clk/mpc83xx_clk.h
index 6b74fc5f16b..b9486a4c202 100644
--- a/drivers/clk/mpc83xx_clk.h
+++ b/drivers/clk/mpc83xx_clk.h
@@ -244,15 +244,8 @@ static int retrieve_mode(int clk, int soc_type, struct clk_mode *mode)
break;
case MPC83XX_CLK_SATA:
/* FIXME(mario.six@gdsys.cc): All SATA controllers must have the same clock ratio */
- if (soc_type == SOC_MPC8379) {
- set_mode(mode, 24, 25, TYPE_SCCR_STANDARD);
- set_mode(mode, 26, 27, TYPE_SCCR_STANDARD);
- set_mode(mode, 28, 29, TYPE_SCCR_STANDARD);
- set_mode(mode, 30, 31, TYPE_SCCR_STANDARD);
- } else {
- set_mode(mode, 18, 19, TYPE_SCCR_STANDARD);
- set_mode(mode, 20, 21, TYPE_SCCR_STANDARD);
- }
+ set_mode(mode, 18, 19, TYPE_SCCR_STANDARD);
+ set_mode(mode, 20, 21, TYPE_SCCR_STANDARD);
break;
case MPC83XX_CLK_TDM:
set_mode(mode, 26, 27, TYPE_SCCR_STANDARD);
diff --git a/drivers/cpu/mpc83xx_cpu.c b/drivers/cpu/mpc83xx_cpu.c
index 127d3c3af08..780b08f0885 100644
--- a/drivers/cpu/mpc83xx_cpu.c
+++ b/drivers/cpu/mpc83xx_cpu.c
@@ -82,9 +82,6 @@ static inline void determine_family(const struct udevice *dev)
case 0x804:
priv->family = FAMILY_836X;
break;
- case 0x80C:
- priv->family = FAMILY_837X;
- break;
default:
priv->family = FAMILY_UNKNOWN;
}
@@ -150,15 +147,6 @@ static inline void determine_type(const struct udevice *dev)
case 0x8048:
priv->type = TYPE_8360;
break;
- case 0x80C6:
- priv->type = TYPE_8377;
- break;
- case 0x80C4:
- priv->type = TYPE_8378;
- break;
- case 0x80C2:
- priv->type = TYPE_8379;
- break;
default:
priv->type = TYPE_UNKNOWN;
}
@@ -338,7 +326,6 @@ static const struct udevice_id mpc83xx_cpu_ids[] = {
{ .compatible = "fsl,mpc832x", },
{ .compatible = "fsl,mpc8349", },
{ .compatible = "fsl,mpc8360", },
- { .compatible = "fsl,mpc8379", },
{ /* sentinel */ }
};
diff --git a/drivers/cpu/mpc83xx_cpu.h b/drivers/cpu/mpc83xx_cpu.h
index 2aaa4e18844..20579cecf5e 100644
--- a/drivers/cpu/mpc83xx_cpu.h
+++ b/drivers/cpu/mpc83xx_cpu.h
@@ -39,7 +39,6 @@ static const char * const e300_names[] = {
* @FAMILY_832X: Identifier for the MPC832x CPU family
* @FAMILY_834X: Identifier for the MPC834x CPU family
* @FAMILY_836X: Identifier for the MPC836x CPU family
- * @FAMILY_837X: Identifier for the MPC837x CPU family
* @FAMILY_UNKNOWN: Identifier for an unknown MPC83xx CPU family
*/
enum mpc83xx_cpu_family {
@@ -48,7 +47,6 @@ enum mpc83xx_cpu_family {
FAMILY_832X,
FAMILY_834X,
FAMILY_836X,
- FAMILY_837X,
FAMILY_UNKNOWN,
};
@@ -73,9 +71,6 @@ enum mpc83xx_cpu_family {
* @TYPE_8358_PBGA: Identifier for the MPC8358 CPU type (Plastic Ball Grid Array
* version)
* @TYPE_8360: Identifier for the MPC8360 CPU type
- * @TYPE_8377: Identifier for the MPC8377 CPU type
- * @TYPE_8378: Identifier for the MPC8378 CPU type
- * @TYPE_8379: Identifier for the MPC8379 CPU type
* @TYPE_UNKNOWN: Identifier for an unknown MPC83xx CPU type
*/
enum mpc83xx_cpu_type {
@@ -94,9 +89,6 @@ enum mpc83xx_cpu_type {
TYPE_8358_TBGA,
TYPE_8358_PBGA,
TYPE_8360,
- TYPE_8377,
- TYPE_8378,
- TYPE_8379,
TYPE_UNKNOWN,
};
@@ -117,9 +109,6 @@ static const char * const cpu_type_names[] = {
[TYPE_8358_TBGA] = "8358_TBGA",
[TYPE_8358_PBGA] = "8358_PBGA",
[TYPE_8360] = "8360",
- [TYPE_8377] = "8377",
- [TYPE_8378] = "8378",
- [TYPE_8379] = "8379",
[TYPE_UNKNOWN] = "Unknown CPU",
};
diff --git a/drivers/ram/mpc83xx_sdram.c b/drivers/ram/mpc83xx_sdram.c
index 28a663289a2..d45c4e6264e 100644
--- a/drivers/ram/mpc83xx_sdram.c
+++ b/drivers/ram/mpc83xx_sdram.c
@@ -167,8 +167,7 @@ static int mpc83xx_sdram_static_init(ofnode node, u32 cs, u32 mapaddr, u32 size)
odt_rd_cfg = ofnode_read_u32_default(node, "odt_rd_cfg", 0);
switch (odt_rd_cfg) {
case ODT_RD_ONLY_OTHER_DIMM:
- if (!IS_ENABLED(CONFIG_ARCH_MPC8360) &&
- !IS_ENABLED(CONFIG_ARCH_MPC837X)) {
+ if (!IS_ENABLED(CONFIG_ARCH_MPC8360)) {
debug("%s: odt_rd_cfg value %d invalid.\n",
ofnode_get_name(node), odt_rd_cfg);
return -EINVAL;
@@ -179,8 +178,7 @@ static int mpc83xx_sdram_static_init(ofnode node, u32 cs, u32 mapaddr, u32 size)
case ODT_RD_ONLY_OTHER_CS:
if (!IS_ENABLED(CONFIG_ARCH_MPC830X) &&
!IS_ENABLED(CONFIG_ARCH_MPC831X) &&
- !IS_ENABLED(CONFIG_ARCH_MPC8360) &&
- !IS_ENABLED(CONFIG_ARCH_MPC837X)) {
+ !IS_ENABLED(CONFIG_ARCH_MPC8360)) {
debug("%s: odt_rd_cfg value %d invalid.\n",
ofnode_get_name(node), odt_rd_cfg);
return -EINVAL;
@@ -198,8 +196,7 @@ static int mpc83xx_sdram_static_init(ofnode node, u32 cs, u32 mapaddr, u32 size)
odt_wr_cfg = ofnode_read_u32_default(node, "odt_wr_cfg", 0);
switch (odt_wr_cfg) {
case ODT_WR_ONLY_OTHER_DIMM:
- if (!IS_ENABLED(CONFIG_ARCH_MPC8360) &&
- !IS_ENABLED(CONFIG_ARCH_MPC837X)) {
+ if (!IS_ENABLED(CONFIG_ARCH_MPC8360)) {
debug("%s: odt_wr_cfg value %d invalid.\n",
ofnode_get_name(node), odt_wr_cfg);
return -EINVAL;
@@ -210,8 +207,7 @@ static int mpc83xx_sdram_static_init(ofnode node, u32 cs, u32 mapaddr, u32 size)
case ODT_WR_ONLY_OTHER_CS:
if (!IS_ENABLED(CONFIG_ARCH_MPC830X) &&
!IS_ENABLED(CONFIG_ARCH_MPC831X) &&
- !IS_ENABLED(CONFIG_ARCH_MPC8360) &&
- !IS_ENABLED(CONFIG_ARCH_MPC837X)) {
+ !IS_ENABLED(CONFIG_ARCH_MPC8360)) {
debug("%s: odt_wr_cfg value %d invalid.\n",
ofnode_get_name(node), odt_wr_cfg);
return -EINVAL;
diff --git a/include/mpc83xx.h b/include/mpc83xx.h
index aa8803413cd..b8d2c3edd56 100644
--- a/include/mpc83xx.h
+++ b/include/mpc83xx.h
@@ -74,11 +74,6 @@
#define SPR_8358_TBGA_ 0x804A
#define SPR_8358_PBGA_ 0x804E
#define SPR_8360 0x8048
-#define SPR_837X_FAMILY 0x80C
-#define SPR_8377 0x80C6
-#define SPR_8378 0x80C4
-#define SPR_8379 0x80C2
-
/*
* SPCR - System Priority Configuration Register
*/
@@ -118,9 +113,8 @@
#define SPCR_TSEC2EP 0x00000003
#define SPCR_TSEC2EP_SHIFT (31-31)
-#elif defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
- defined(CONFIG_ARCH_MPC837X)
-/* SPCR bits - MPC8308, MPC831x and MPC837X specific */
+#elif defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X)
+/* SPCR bits - MPC8308 and MPC831x specific */
/* TSEC data priority */
#define SPCR_TSECDP 0x00003000
#define SPCR_TSECDP_SHIFT (31-19)
@@ -237,59 +231,6 @@
#define SICRH_TSOBI1 0x00000002
#define SICRH_TSOBI2 0x00000001
-#elif defined(CONFIG_ARCH_MPC837X)
-/* SICRL bits - MPC837X specific */
-#define SICRL_USB_A 0xC0000000
-#define SICRL_USB_B 0x30000000
-#define SICRL_USB_B_SD 0x20000000
-#define SICRL_UART 0x0C000000
-#define SICRL_GPIO_A 0x02000000
-#define SICRL_GPIO_B 0x01000000
-#define SICRL_GPIO_C 0x00800000
-#define SICRL_GPIO_D 0x00400000
-#define SICRL_GPIO_E 0x00200000
-#define SICRL_GPIO_F 0x00180000
-#define SICRL_GPIO_G 0x00040000
-#define SICRL_GPIO_H 0x00020000
-#define SICRL_GPIO_I 0x00010000
-#define SICRL_GPIO_J 0x00008000
-#define SICRL_GPIO_K 0x00004000
-#define SICRL_GPIO_L 0x00003000
-#define SICRL_DMA_A 0x00000800
-#define SICRL_DMA_B 0x00000400
-#define SICRL_DMA_C 0x00000200
-#define SICRL_DMA_D 0x00000100
-#define SICRL_DMA_E 0x00000080
-#define SICRL_DMA_F 0x00000040
-#define SICRL_DMA_G 0x00000020
-#define SICRL_DMA_H 0x00000010
-#define SICRL_DMA_I 0x00000008
-#define SICRL_DMA_J 0x00000004
-#define SICRL_LDP_A 0x00000002
-#define SICRL_LDP_B 0x00000001
-
-/* SICRH bits - MPC837X specific */
-#define SICRH_DDR 0x80000000
-#define SICRH_TSEC1_A 0x10000000
-#define SICRH_TSEC1_B 0x08000000
-#define SICRH_TSEC2_A 0x00400000
-#define SICRH_TSEC2_B 0x00200000
-#define SICRH_TSEC2_C 0x00100000
-#define SICRH_TSEC2_D 0x00080000
-#define SICRH_TSEC2_E 0x00040000
-#define SICRH_TMR 0x00010000
-#define SICRH_GPIO2_A 0x00008000
-#define SICRH_GPIO2_B 0x00004000
-#define SICRH_GPIO2_C 0x00002000
-#define SICRH_GPIO2_D 0x00001000
-#define SICRH_GPIO2_E 0x00000C00
-#define SICRH_GPIO2_E_SD 0x00000800
-#define SICRH_GPIO2_F 0x00000300
-#define SICRH_GPIO2_G 0x000000C0
-#define SICRH_GPIO2_H 0x00000030
-#define SICRH_SPI 0x00000003
-#define SICRH_SPI_SD 0x00000001
-
#elif defined(CONFIG_ARCH_MPC8308)
/* SICRL bits - MPC8308 specific */
#define SICRL_SPI_PF0 (0 << 28)
@@ -522,13 +463,6 @@
#define HRCWL_SVCOD_DIV_8 0x20000000
#define HRCWL_SVCOD_DIV_1 0x30000000
-#elif defined(CONFIG_ARCH_MPC837X)
-#define HRCWL_SVCOD 0x30000000
-#define HRCWL_SVCOD_SHIFT 28
-#define HRCWL_SVCOD_DIV_4 0x00000000
-#define HRCWL_SVCOD_DIV_8 0x10000000
-#define HRCWL_SVCOD_DIV_2 0x20000000
-#define HRCWL_SVCOD_DIV_1 0x30000000
#endif
/*
@@ -576,15 +510,11 @@
#if defined(CONFIG_ARCH_MPC834X)
#define HRCWH_ROM_LOC_PCI2 0x00200000
#endif
-#if defined(CONFIG_ARCH_MPC837X)
-#define HRCWH_ROM_LOC_ON_CHIP_ROM 0x00300000
-#endif
#define HRCWH_ROM_LOC_LOCAL_8BIT 0x00500000
#define HRCWH_ROM_LOC_LOCAL_16BIT 0x00600000
#define HRCWH_ROM_LOC_LOCAL_32BIT 0x00700000
-#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
- defined(CONFIG_ARCH_MPC837X)
+#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X)
#define HRCWH_ROM_LOC_NAND_SP_8BIT 0x00100000
#define HRCWH_ROM_LOC_NAND_SP_16BIT 0x00200000
#define HRCWH_ROM_LOC_NAND_LP_8BIT 0x00500000
@@ -636,8 +566,7 @@
/*
* RSR - Reset Status Register
*/
-#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
- defined(CONFIG_ARCH_MPC837X)
+#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X)
#define RSR_RSTSRC 0xF0000000 /* Reset source */
#define RSR_RSTSRC_SHIFT 28
#else
@@ -850,45 +779,6 @@
#define SCCR_TDMCM_2 0x00000020
#define SCCR_TDMCM_3 0x00000030
-#elif defined(CONFIG_ARCH_MPC837X)
-/* SCCR bits - MPC837X specific */
-#define SCCR_TSEC1CM 0xc0000000
-#define SCCR_TSEC1CM_SHIFT 30
-#define SCCR_TSEC1CM_0 0x00000000
-#define SCCR_TSEC1CM_1 0x40000000
-#define SCCR_TSEC1CM_2 0x80000000
-#define SCCR_TSEC1CM_3 0xC0000000
-
-#define SCCR_TSEC2CM 0x30000000
-#define SCCR_TSEC2CM_SHIFT 28
-#define SCCR_TSEC2CM_0 0x00000000
-#define SCCR_TSEC2CM_1 0x10000000
-#define SCCR_TSEC2CM_2 0x20000000
-#define SCCR_TSEC2CM_3 0x30000000
-
-#define SCCR_SDHCCM 0x0c000000
-#define SCCR_SDHCCM_SHIFT 26
-#define SCCR_SDHCCM_0 0x00000000
-#define SCCR_SDHCCM_1 0x04000000
-#define SCCR_SDHCCM_2 0x08000000
-#define SCCR_SDHCCM_3 0x0c000000
-
-#define SCCR_USBDRCM 0x00c00000
-#define SCCR_USBDRCM_SHIFT 22
-#define SCCR_USBDRCM_0 0x00000000
-#define SCCR_USBDRCM_1 0x00400000
-#define SCCR_USBDRCM_2 0x00800000
-#define SCCR_USBDRCM_3 0x00c00000
-
-/* All of the four SATA controllers must have the same clock ratio */
-#define SCCR_SATA1CM 0x000000c0
-#define SCCR_SATA1CM_SHIFT 6
-#define SCCR_SATACM 0x000000ff
-#define SCCR_SATACM_SHIFT 0
-#define SCCR_SATACM_0 0x00000000
-#define SCCR_SATACM_1 0x00000055
-#define SCCR_SATACM_2 0x000000aa
-#define SCCR_SATACM_3 0x000000ff
#endif
#define SCCR_PCIEXP1CM 0x00300000
@@ -932,7 +822,7 @@
#elif defined(CONFIG_ARCH_MPC832X)
#define CSCONFIG_ODT_RD_CFG 0x00400000
#define CSCONFIG_ODT_WR_CFG 0x00040000
-#elif defined(CONFIG_ARCH_MPC8360) || defined(CONFIG_ARCH_MPC837X)
+#elif defined(CONFIG_ARCH_MPC8360)
#define CSCONFIG_ODT_RD_NEVER 0x00000000
#define CSCONFIG_ODT_RD_ONLY_CURRENT 0x00100000
#define CSCONFIG_ODT_RD_ONLY_OTHER_CS 0x00200000
--
2.47.3
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH 12/26] powerpc: mpc85xx: Remove C29x support
2026-10-09 19:36 [PATCH 00/26] powerpc: drop EOL boards and SoCs, take over maintenance Bradley Morgan
` (10 preceding siblings ...)
2026-10-09 19:36 ` [PATCH 11/26] powerpc: mpc83xx: Remove MPC837x support Bradley Morgan
@ 2026-10-09 19:36 ` Bradley Morgan
2026-10-09 19:36 ` [PATCH 13/26] powerpc: mpc85xx: Remove P1011 support Bradley Morgan
` (13 subsequent siblings)
25 siblings, 0 replies; 31+ messages in thread
From: Bradley Morgan @ 2026-10-09 19:36 UTC (permalink / raw)
To: Tom Rini, u-boot
Cc: Bradley Morgan, Marek Behún, Marek Mojík,
NXP i . MX U-Boot Team, Alexey Charkov, Anshul Dalal,
Daniel Golle, Fabio Estevam, Gaurav Jain, Ilias Apalodimas,
Jaehoon Chung, James Hilliard, Jerome Forissier, Johan Jonker,
Lukasz Majewski, Marek Vasut, Mario Six, Michael Walle,
Michal Simek, Neil Armstrong, Peng Fan, Pengpeng Hou,
Priyanka Jain, Quentin Schulz, Simon Glass, Stefano Babic,
Tanmay Kathpalia, Torsten Rupp, Vincent Jardin, Weijie Gao
NXP lists the C29x family as end of life, and no board in the tree selects
ARCH_C29X. Remove the unused platform support and its C29x specific
crypto, clocking and SERDES setup.
Signed-off-by: Bradley Morgan <brads@mainlining.org>
---
arch/Kconfig.nxp | 4 +-
arch/powerpc/cpu/mpc85xx/Kconfig | 22 +------
arch/powerpc/cpu/mpc85xx/Makefile | 1 -
arch/powerpc/cpu/mpc85xx/c29x_serdes.c | 70 -----------------------
arch/powerpc/cpu/mpc85xx/cpu_init.c | 11 ----
arch/powerpc/include/asm/config_mpc85xx.h | 3 -
arch/powerpc/include/asm/immap_85xx.h | 22 -------
arch/powerpc/include/asm/processor.h | 3 -
drivers/crypto/fsl/jr.c | 14 +----
drivers/mmc/Kconfig | 3 +-
include/fsl_sec.h | 3 -
11 files changed, 7 insertions(+), 149 deletions(-)
delete mode 100644 arch/powerpc/cpu/mpc85xx/c29x_serdes.c
diff --git a/arch/Kconfig.nxp b/arch/Kconfig.nxp
index 8b8210224b5..4ce12613131 100644
--- a/arch/Kconfig.nxp
+++ b/arch/Kconfig.nxp
@@ -286,14 +286,14 @@ config SYS_FSL_IFC_BANK_COUNT
depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A || \
ARCH_LS1088A || ARCH_LS1021A || ARCH_B4860 || ARCH_B4420 || \
ARCH_T4240 || ARCH_T1040 || ARCH_T1042 || ARCH_T1024 || \
- ARCH_T2080 || ARCH_C29X || ARCH_P1010 || ARCH_BSC9131 || \
+ ARCH_T2080 || ARCH_P1010 || ARCH_BSC9131 || \
ARCH_BSC9132
default 3 if ARCH_BSC9131 || ARCH_BSC9132
default 4 if ARCH_LS1043A || ARCH_LS1046A || ARCH_B4860 || \
ARCH_B4420 || ARCH_P1010
default 8 if ARCH_LS2080A || ARCH_LS1088A || ARCH_LS1021A || \
ARCH_T4240 || ARCH_T1040 || ARCH_T1042 || \
- ARCH_T1024 || ARCH_T2080 || ARCH_C29X
+ ARCH_T1024 || ARCH_T2080
config FSL_QIXIS
bool "Enable QIXIS support"
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index 32461cfae50..b1b134ca990 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -321,23 +321,6 @@ config ARCH_BSC9132
imply CMD_PCI
imply CMD_REGINFO
-config ARCH_C29X
- bool
- select FSL_LAW
- select SYS_FSL_DDR_VER_46
- select SYS_FSL_ERRATUM_A005125
- select SYS_FSL_ERRATUM_ESDHC111
- select FSL_PCIE_RESET
- select SYS_FSL_HAS_DDR3
- select SYS_FSL_HAS_SEC
- select SYS_FSL_SEC_BE
- select SYS_FSL_SEC_COMPAT_6
- select SYS_PPC_E500_USE_DEBUG_TLB
- select FSL_IFC
- imply CMD_NAND
- imply CMD_PCI
- imply CMD_REGINFO
-
config ARCH_MPC8536
bool
select FSL_LAW
@@ -843,7 +826,6 @@ config SYS_CCSRBAR_DEFAULT
hex "Default CCSRBAR address"
default 0xff700000 if ARCH_BSC9131 || \
ARCH_BSC9132 || \
- ARCH_C29X || \
ARCH_MPC8536 || \
ARCH_MPC8540 || \
ARCH_MPC8544 || \
@@ -1057,7 +1039,6 @@ config SYS_FSL_NUM_LAWS
ARCH_T1042
default 12 if ARCH_BSC9131 || \
ARCH_BSC9132 || \
- ARCH_C29X || \
ARCH_MPC8536 || \
ARCH_P1010 || \
ARCH_P1011 || \
@@ -1182,8 +1163,7 @@ config SYS_PPC_E500_DEBUG_TLB
ARCH_P1025 || \
ARCH_P2020
default 3 if ARCH_P1010 || \
- ARCH_BSC9132 || \
- ARCH_C29X
+ ARCH_BSC9132
help
Select a temporary TLB entry to be used during boot to work
around limitations in e500v1 and e500v2 external debugger
diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile
index b4bca7bbe6b..93b0c28ca03 100644
--- a/arch/powerpc/cpu/mpc85xx/Makefile
+++ b/arch/powerpc/cpu/mpc85xx/Makefile
@@ -51,7 +51,6 @@ obj-$(CONFIG_SYS_FSL_QORIQ_CHASSIS1) += fsl_corenet_serdes.o
obj-$(CONFIG_SYS_FSL_QORIQ_CHASSIS2) += fsl_corenet2_serdes.o
# SoC specific SERDES support
-obj-$(CONFIG_ARCH_C29X) += c29x_serdes.o
obj-$(CONFIG_ARCH_MPC8536) += mpc8536_serdes.o
obj-$(CONFIG_ARCH_MPC8544) += mpc8544_serdes.o
obj-$(CONFIG_ARCH_P1010) += p1010_serdes.o
diff --git a/arch/powerpc/cpu/mpc85xx/c29x_serdes.c b/arch/powerpc/cpu/mpc85xx/c29x_serdes.c
deleted file mode 100644
index bbe4a0dd62b..00000000000
--- a/arch/powerpc/cpu/mpc85xx/c29x_serdes.c
+++ /dev/null
@@ -1,70 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-#include <config.h>
-#include <log.h>
-#include <asm/io.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_serdes.h>
-
-#define SRDS1_MAX_LANES 4
-
-static u32 serdes1_prtcl_map;
-
-struct serdes_config {
- u32 protocol;
- u8 lanes[SRDS1_MAX_LANES];
-};
-
-static const struct serdes_config serdes1_cfg_tbl[] = {
- /* SerDes 1 */
- {1, {PCIE1, PCIE1, PCIE1, PCIE1} },
- {2, {PCIE1, PCIE1, PCIE1, PCIE1} },
- {3, {PCIE1, PCIE1, NONE, NONE} },
- {4, {PCIE1, PCIE1, NONE, NONE} },
- {5, {PCIE1, NONE, NONE, NONE} },
- {6, {PCIE1, NONE, NONE, NONE} },
- {}
-};
-
-int is_serdes_configured(enum srds_prtcl device)
-{
- if (!(serdes1_prtcl_map & (1 << NONE)))
- fsl_serdes_init();
-
- return (1 << device) & serdes1_prtcl_map;
-}
-
-void fsl_serdes_init(void)
-{
- ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR;
- u32 pordevsr = in_be32(&gur->pordevsr);
- u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
- MPC85xx_PORDEVSR_IO_SEL_SHIFT;
- const struct serdes_config *ptr;
- int lane;
-
- if (serdes1_prtcl_map & (1 << NONE))
- return;
-
- debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
-
- if (srds_cfg > ARRAY_SIZE(serdes1_cfg_tbl)) {
- printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
- return;
- }
-
- ptr = &serdes1_cfg_tbl[srds_cfg];
- if (!ptr->protocol)
- return;
-
- for (lane = 0; lane < SRDS1_MAX_LANES; lane++) {
- enum srds_prtcl lane_prtcl = ptr->lanes[lane];
- serdes1_prtcl_map |= (1 << lane_prtcl);
- }
-
- /* Set the first bit to indicate serdes has been initialized */
- serdes1_prtcl_map |= (1 << NONE);
-}
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index e7e9b3dbd1c..710b3b31354 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -881,17 +881,6 @@ int cpu_init_r(void)
pamu_init();
#endif
-#ifdef CONFIG_FSL_CAAM
-#if defined(CONFIG_ARCH_C29X)
- if ((SVR_SOC_VER(svr) == SVR_C292) ||
- (SVR_SOC_VER(svr) == SVR_C293))
- sec_init_idx(1);
-
- if (SVR_SOC_VER(svr) == SVR_C293)
- sec_init_idx(2);
-#endif
-#endif
-
#if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_SYS_FSL_ERRATUM_SATA_A001)
/*
* For P1022/1013 Rev1.0 silicon, after power on SATA host
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index e5890376df8..f115dcce76a 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -126,9 +126,6 @@
#define CFG_SYS_FM1_CLK 0
#define CFG_SYS_FM_MURAM_SIZE 0x28000
-#elif defined(CONFIG_ARCH_C29X)
-#define CFG_SYS_FSL_SEC_IDX_OFFSET 0x20000
-
#endif
#endif /* _ASM_MPC85xx_CONFIG_H_ */
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index a9336d73f20..489fcd43351 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1768,11 +1768,6 @@ typedef struct ccsr_gur {
#ifdef CONFIG_ARCH_MPC8536
#define MPC85xx_PORPLLSR_DDR_RATIO 0x3e000000
#define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT 25
-#elif defined(CONFIG_ARCH_C29X)
-#define MPC85xx_PORPLLSR_DDR_RATIO 0x00003f00
-#define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT (9 - ((gur->pordevsr2 \
- & MPC85xx_PORDEVSR2_DDR_SPD_0) \
- >> MPC85xx_PORDEVSR2_DDR_SPD_0_SHIFT))
#else
#if defined(CONFIG_ARCH_BSC9131) || defined(CONFIG_ARCH_BSC9132)
#define MPC85xx_PORPLLSR_DDR_RATIO 0x00003f00
@@ -1817,9 +1812,6 @@ typedef struct ccsr_gur {
#elif defined(CONFIG_ARCH_BSC9132)
#define MPC85xx_PORDEVSR_IO_SEL 0x00FE0000
#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 17
-#elif defined(CONFIG_ARCH_C29X)
-#define MPC85xx_PORDEVSR_IO_SEL 0x00e00000
-#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 21
#else
#define MPC85xx_PORDEVSR_IO_SEL 0x00780000
#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 19
@@ -1835,10 +1827,6 @@ typedef struct ccsr_gur {
#define MPC85xx_PORDEVSR_RIO_DEV_ID 0x00000007
u32 pordbgmsr; /* POR debug mode status */
u32 pordevsr2; /* POR I/O device status 2 */
-#if defined(CONFIG_ARCH_C29X)
-#define MPC85xx_PORDEVSR2_DDR_SPD_0 0x00000008
-#define MPC85xx_PORDEVSR2_DDR_SPD_0_SHIFT 3
-#endif
#define MPC85xx_PORDEVSR2_SBC_MASK 0x10000000
/* The 8544 RM says this is bit 26, but it's really bit 24 */
#define MPC85xx_PORDEVSR2_SEC_CFG 0x00000080
@@ -1972,11 +1960,6 @@ typedef struct ccsr_gur {
#ifdef CONFIG_ARCH_BSC9132
#define MPC85xx_PMUXCR0_SIM_SEL_MASK 0x0003b000
#define MPC85xx_PMUXCR0_SIM_SEL 0x00014000
-#endif
-#if defined(CONFIG_ARCH_C29X)
-#define MPC85xx_PMUXCR_SPI_MASK 0x00000300
-#define MPC85xx_PMUXCR_SPI 0x00000000
-#define MPC85xx_PMUXCR_SPI_GPIO 0x00000100
#endif
u32 pmuxcr2; /* Alt. function signal multiplex control 2 */
#if defined(CONFIG_ARCH_P1010)
@@ -2515,13 +2498,8 @@ struct ccsr_pman {
#define CFG_SYS_MPC85xx_USB2_PHY_OFFSET 0xE5100
#define CFG_SYS_MDIO1_OFFSET 0x24000
#define CFG_SYS_MPC85xx_ESDHC_OFFSET 0x2e000
-#if defined(CONFIG_ARCH_C29X)
-#define CFG_SYS_FSL_SEC_OFFSET 0x80000
-#define CFG_SYS_FSL_JR0_OFFSET 0x81000
-#else
#define CFG_SYS_FSL_SEC_OFFSET 0x30000
#define CFG_SYS_FSL_JR0_OFFSET 0x31000
-#endif
#define CFG_SYS_MPC85xx_SERDES2_OFFSET 0xE3100
#define CFG_SYS_MPC85xx_SERDES1_OFFSET 0xE3000
#define CFG_SYS_SEC_MON_OFFSET 0xE6000
diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h
index 306dfd01346..1d6f960be94 100644
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -1056,9 +1056,6 @@
#define SVR_T4120 0x824001
#define SVR_T4160 0x824100
#define SVR_T4080 0x824102
-#define SVR_C291 0x850000
-#define SVR_C292 0x850020
-#define SVR_C293 0x850030
#define SVR_B4860 0x868000
#define SVR_G4860 0x868001
#define SVR_B4460 0x868003
diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c
index 3a5032bcaf6..ed69ba92750 100644
--- a/drivers/crypto/fsl/jr.c
+++ b/drivers/crypto/fsl/jr.c
@@ -30,22 +30,14 @@
#define CIRC_CNT(head, tail, size) (((head) - (tail)) & (size - 1))
#define CIRC_SPACE(head, tail, size) CIRC_CNT((tail), (head) + 1, (size))
-uint32_t sec_offset[CONFIG_SYS_FSL_MAX_NUM_OF_SEC] = {
- 0,
-#if defined(CONFIG_ARCH_C29X)
- CFG_SYS_FSL_SEC_IDX_OFFSET,
- 2 * CFG_SYS_FSL_SEC_IDX_OFFSET
-#endif
-};
-
#if CONFIG_IS_ENABLED(DM)
struct udevice *caam_dev;
#else
#define SEC_ADDR(idx) \
- (ulong)((CFG_SYS_FSL_SEC_ADDR + sec_offset[idx]))
+ (ulong)CFG_SYS_FSL_SEC_ADDR
#define SEC_JR0_ADDR(idx) \
- (ulong)(SEC_ADDR(idx) + \
+ (ulong)(CFG_SYS_FSL_SEC_ADDR + \
(CFG_SYS_FSL_JR0_OFFSET - CFG_SYS_FSL_SEC_OFFSET))
struct caam_regs caam_st;
#endif
@@ -688,7 +680,7 @@ static void jr_setown_non_trusted(ccsr_sec_t *sec)
}
#endif
-int sec_init_idx(uint8_t sec_idx)
+static int sec_init_idx(uint8_t sec_idx)
{
int ret = 0;
struct caam_regs *caam;
diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index b3731dfe4a1..4eb5d80e336 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -911,8 +911,7 @@ config FSL_SDHC_V2_3
config FSL_ESDHC
bool "Freescale/NXP eSDHC controller support"
depends on ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3 || PPC
- select FSL_SDHC_V2_3 if ARCH_P1010 || ARCH_BSC9131 || ARCH_BSC9132 \
- || ARCH_C29X
+ select FSL_SDHC_V2_3 if ARCH_P1010 || ARCH_BSC9131 || ARCH_BSC9132
help
This selects support for the eSDHC (Enhanced Secure Digital Host
Controller) found on numerous Freescale/NXP SoCs.
diff --git a/include/fsl_sec.h b/include/fsl_sec.h
index 8c5e59c5b1c..4b769759593 100644
--- a/include/fsl_sec.h
+++ b/include/fsl_sec.h
@@ -374,9 +374,6 @@ int gen_mppubk(u8 *dst);
int sign_mppubk(const u8 *m, int data_size, u8 *dgst, u8 *c, u8 *d);
-#if defined(CONFIG_ARCH_C29X)
-int sec_init_idx(uint8_t);
-#endif
int sec_init(void);
u8 caam_get_era(void);
--
2.47.3
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH 13/26] powerpc: mpc85xx: Remove P1011 support
2026-10-09 19:36 [PATCH 00/26] powerpc: drop EOL boards and SoCs, take over maintenance Bradley Morgan
` (11 preceding siblings ...)
2026-10-09 19:36 ` [PATCH 12/26] powerpc: mpc85xx: Remove C29x support Bradley Morgan
@ 2026-10-09 19:36 ` Bradley Morgan
2026-10-09 19:36 ` [PATCH 14/26] powerpc: mpc85xx: Remove P1023 support Bradley Morgan
` (12 subsequent siblings)
25 siblings, 0 replies; 31+ messages in thread
From: Bradley Morgan @ 2026-10-09 19:36 UTC (permalink / raw)
To: Tom Rini, u-boot
Cc: Bradley Morgan, Marek Behún, Marek Mojík,
NXP i . MX U-Boot Team, Alexey Charkov, Anshul Dalal,
Daniel Golle, Fabio Estevam, Gaurav Jain, Ilias Apalodimas,
Jaehoon Chung, James Hilliard, Jerome Forissier, Johan Jonker,
Lukasz Majewski, Marek Vasut, Mario Six, Michael Walle,
Michal Simek, Neil Armstrong, Peng Fan, Pengpeng Hou,
Priyanka Jain, Quentin Schulz, Simon Glass, Stefano Babic,
Tanmay Kathpalia, Torsten Rupp, Vincent Jardin, Weijie Gao
NXP lists the P1011 parts as end of life, and no board in the tree
selects ARCH_P1011. Remove the unused SoC configuration, CPU
identification, and stale boot documentation entry.
Signed-off-by: Bradley Morgan <brads@mainlining.org>
---
arch/Kconfig | 2 +-
arch/powerpc/cpu/mpc85xx/Kconfig | 20 +-------------------
arch/powerpc/cpu/mpc85xx/Makefile | 1 -
arch/powerpc/cpu/mpc8xxx/cpu.c | 1 -
arch/powerpc/include/asm/processor.h | 1 -
doc/README.mpc85xx-sd-spi-boot | 1 -
6 files changed, 2 insertions(+), 24 deletions(-)
diff --git a/arch/Kconfig b/arch/Kconfig
index 8d63afeb138..07214f2af7c 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -470,7 +470,7 @@ config SYS_IMMR
default 0xF0000000 if ARCH_MPC8313
default 0xE0000000 if MPC83xx && !ARCH_MPC8313
default 0x01000000 if ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3
- default 0xFFE00000 if ARCH_P1010 || ARCH_P1011 || ARCH_P1020 || \
+ default 0xFFE00000 if ARCH_P1010 || ARCH_P1020 || \
ARCH_P1021 || ARCH_P1024 || ARCH_P1025 || \
ARCH_P2020
default SYS_CCSRBAR_DEFAULT
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index b1b134ca990..ab66ffadebd 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -399,21 +399,6 @@ config ARCH_P1010
imply FSL_SATA
imply TIMESTAMP
-config ARCH_P1011
- bool
- select FSL_LAW
- select SYS_FSL_ERRATUM_A004508
- select SYS_FSL_ERRATUM_A005125
- select SYS_FSL_ERRATUM_ELBC_A001
- select SYS_FSL_ERRATUM_ESDHC111
- select FSL_PCIE_DISABLE_ASPM
- select SYS_FSL_HAS_DDR3
- select SYS_FSL_HAS_SEC
- select SYS_FSL_SEC_BE
- select SYS_FSL_SEC_COMPAT_2
- select SYS_PPC_E500_USE_DEBUG_TLB
- select FSL_ELBC
-
config ARCH_P1020
bool
select BTB
@@ -831,7 +816,6 @@ config SYS_CCSRBAR_DEFAULT
ARCH_MPC8544 || \
ARCH_MPC8560 || \
ARCH_P1010 || \
- ARCH_P1011 || \
ARCH_P1020 || \
ARCH_P1021 || \
ARCH_P1024 || \
@@ -1041,7 +1025,6 @@ config SYS_FSL_NUM_LAWS
ARCH_BSC9132 || \
ARCH_MPC8536 || \
ARCH_P1010 || \
- ARCH_P1011 || \
ARCH_P1020 || \
ARCH_P1021 || \
ARCH_P1023 || \
@@ -1156,8 +1139,7 @@ config SYS_PPC_E500_DEBUG_TLB
depends on SYS_PPC_E500_USE_DEBUG_TLB
default 0 if ARCH_MPC8544
default 1 if ARCH_MPC8536
- default 2 if ARCH_P1011 || \
- ARCH_P1020 || \
+ default 2 if ARCH_P1020 || \
ARCH_P1021 || \
ARCH_P1024 || \
ARCH_P1025 || \
diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile
index 93b0c28ca03..f78131dd61a 100644
--- a/arch/powerpc/cpu/mpc85xx/Makefile
+++ b/arch/powerpc/cpu/mpc85xx/Makefile
@@ -54,7 +54,6 @@ obj-$(CONFIG_SYS_FSL_QORIQ_CHASSIS2) += fsl_corenet2_serdes.o
obj-$(CONFIG_ARCH_MPC8536) += mpc8536_serdes.o
obj-$(CONFIG_ARCH_MPC8544) += mpc8544_serdes.o
obj-$(CONFIG_ARCH_P1010) += p1010_serdes.o
-obj-$(CONFIG_ARCH_P1011) += p1021_serdes.o
obj-$(CONFIG_ARCH_P1020) += p1021_serdes.o
obj-$(CONFIG_ARCH_P1021) += p1021_serdes.o
obj-$(CONFIG_ARCH_P1023) += p1023_serdes.o
diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c
index 47daf51fc1b..641d2a199f8 100644
--- a/arch/powerpc/cpu/mpc8xxx/cpu.c
+++ b/arch/powerpc/cpu/mpc8xxx/cpu.c
@@ -41,7 +41,6 @@ static struct cpu_type cpu_type_list[] = {
CPU_TYPE_ENTRY(8569, 8569, 1),
CPU_TYPE_ENTRY(8572, 8572, 2),
CPU_TYPE_ENTRY(P1010, P1010, 1),
- CPU_TYPE_ENTRY(P1011, P1011, 1),
CPU_TYPE_ENTRY(P1012, P1012, 1),
CPU_TYPE_ENTRY(P1013, P1013, 1),
CPU_TYPE_ENTRY(P1014, P1014, 1),
diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h
index 1d6f960be94..36d8660cddc 100644
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -1033,7 +1033,6 @@
#define SVR_8569 0x808000
#define SVR_8572 0x80E000
#define SVR_P1010 0x80F100
-#define SVR_P1011 0x80E500
#define SVR_P1012 0x80E501
#define SVR_P1013 0x80E700
#define SVR_P1014 0x80F101
diff --git a/doc/README.mpc85xx-sd-spi-boot b/doc/README.mpc85xx-sd-spi-boot
index 8e98fc9f659..086c8f9e49b 100644
--- a/doc/README.mpc85xx-sd-spi-boot
+++ b/doc/README.mpc85xx-sd-spi-boot
@@ -60,7 +60,6 @@ P2020DS config_sram_p2020ds.dat
P1020RDB config_ddr2_1g_p1020rdb_533M.dat
P1020RDB config_ddr2_1g_p1020rdb_667M.dat
P1020RDB config_ddr3_1gb_p1_p2_rdb_pc_800M.dat
-P1011RDB config_ddr3_1gb_p1_p2_rdb_pc_800M.dat
P1010RDB config_ddr3_1gb_p1010rdb_800M.dat
P1021RDB config_ddr3_1gb_p1_p2_rdb_pc_800M.dat
P1022DS config_ddr3_2gb_p1022ds.dat
--
2.47.3
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH 14/26] powerpc: mpc85xx: Remove P1023 support
2026-10-09 19:36 [PATCH 00/26] powerpc: drop EOL boards and SoCs, take over maintenance Bradley Morgan
` (12 preceding siblings ...)
2026-10-09 19:36 ` [PATCH 13/26] powerpc: mpc85xx: Remove P1011 support Bradley Morgan
@ 2026-10-09 19:36 ` Bradley Morgan
2026-10-09 19:36 ` [PATCH 15/26] powerpc: mpc85xx: Remove P1025 support Bradley Morgan
` (11 subsequent siblings)
25 siblings, 0 replies; 31+ messages in thread
From: Bradley Morgan @ 2026-10-09 19:36 UTC (permalink / raw)
To: Tom Rini, u-boot
Cc: Bradley Morgan, Marek Behún, Marek Mojík,
NXP i . MX U-Boot Team, Alexey Charkov, Anshul Dalal,
Daniel Golle, Fabio Estevam, Gaurav Jain, Ilias Apalodimas,
Jaehoon Chung, James Hilliard, Jerome Forissier, Johan Jonker,
Lukasz Majewski, Marek Vasut, Mario Six, Michael Walle,
Michal Simek, Neil Armstrong, Peng Fan, Pengpeng Hou,
Priyanka Jain, Quentin Schulz, Simon Glass, Stefano Babic,
Tanmay Kathpalia, Torsten Rupp, Vincent Jardin, Weijie Gao
NXP lists the P1023/P1017 family as no longer manufactured. No board in the tree selects ARCH_P1023, so remove the unused SoC, FMan, and SERDES
support.
Signed-off-by: Bradley Morgan <brads@mainlining.org>
---
arch/powerpc/cpu/mpc85xx/Kconfig | 19 +-----
arch/powerpc/cpu/mpc85xx/Makefile | 1 -
arch/powerpc/cpu/mpc85xx/p1023_serdes.c | 59 -------------------
arch/powerpc/cpu/mpc8xxx/cpu.c | 1 -
arch/powerpc/include/asm/config_mpc85xx.h | 7 ---
arch/powerpc/include/asm/immap_85xx.h | 15 -----
arch/powerpc/include/asm/processor.h | 1 -
drivers/net/Kconfig | 1 -
drivers/net/fm/Makefile | 1 -
drivers/net/fm/fm.h | 4 --
drivers/net/fm/p1023.c | 72 -----------------------
11 files changed, 1 insertion(+), 180 deletions(-)
delete mode 100644 arch/powerpc/cpu/mpc85xx/p1023_serdes.c
delete mode 100644 drivers/net/fm/p1023.c
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index ab66ffadebd..f4e34adbaea 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -443,20 +443,6 @@ config ARCH_P1021
imply CMD_REGINFO
imply SATA_SIL
-config ARCH_P1023
- bool
- select FSL_LAW
- select SYS_FSL_ERRATUM_A004508
- select SYS_FSL_ERRATUM_A005125
- select SYS_FSL_ERRATUM_I2C_A004447
- select FSL_PCIE_RESET
- select SYS_FSL_HAS_DDR3
- select SYS_FSL_HAS_SEC
- select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22
- select SYS_FSL_SEC_BE
- select SYS_FSL_SEC_COMPAT_4
- select FSL_ELBC
-
config ARCH_P1024
bool
select FSL_LAW
@@ -794,7 +780,6 @@ config MAX_CPUS
ARCH_BSC9132 || \
ARCH_P1020 || \
ARCH_P1021 || \
- ARCH_P1023 || \
ARCH_P1024 || \
ARCH_P1025 || \
ARCH_P2020 || \
@@ -821,7 +806,6 @@ config SYS_CCSRBAR_DEFAULT
ARCH_P1024 || \
ARCH_P1025 || \
ARCH_P2020
- default 0xff600000 if ARCH_P1023
default 0xfe000000 if ARCH_B4420 || \
ARCH_B4860 || \
ARCH_P2041 || \
@@ -957,7 +941,7 @@ config SYS_FSL_A004447_SVR_REV
hex
depends on SYS_FSL_ERRATUM_I2C_A004447
default 0x10 if ARCH_P1010
- default 0x11 if ARCH_P1023 || ARCH_P2041 || ARCH_BSC9132
+ default 0x11 if ARCH_P2041 || ARCH_BSC9132
config SYS_FSL_ERRATUM_IFC_A002769
bool
@@ -1027,7 +1011,6 @@ config SYS_FSL_NUM_LAWS
ARCH_P1010 || \
ARCH_P1020 || \
ARCH_P1021 || \
- ARCH_P1023 || \
ARCH_P1024 || \
ARCH_P1025 || \
ARCH_P2020
diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile
index f78131dd61a..c40558880ea 100644
--- a/arch/powerpc/cpu/mpc85xx/Makefile
+++ b/arch/powerpc/cpu/mpc85xx/Makefile
@@ -56,7 +56,6 @@ obj-$(CONFIG_ARCH_MPC8544) += mpc8544_serdes.o
obj-$(CONFIG_ARCH_P1010) += p1010_serdes.o
obj-$(CONFIG_ARCH_P1020) += p1021_serdes.o
obj-$(CONFIG_ARCH_P1021) += p1021_serdes.o
-obj-$(CONFIG_ARCH_P1023) += p1023_serdes.o
obj-$(CONFIG_ARCH_P1024) += p1021_serdes.o
obj-$(CONFIG_ARCH_P1025) += p1021_serdes.o
obj-$(CONFIG_ARCH_P2020) += p2020_serdes.o
diff --git a/arch/powerpc/cpu/mpc85xx/p1023_serdes.c b/arch/powerpc/cpu/mpc85xx/p1023_serdes.c
deleted file mode 100644
index 6d306d99c32..00000000000
--- a/arch/powerpc/cpu/mpc85xx/p1023_serdes.c
+++ /dev/null
@@ -1,59 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2010-2011 Freescale Semiconductor, Inc.
- * Author: Roy Zang <tie-fei.zang@freescale.com>
- */
-
-#include <config.h>
-#include <log.h>
-#include <asm/io.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_serdes.h>
-
-#define SRDS1_MAX_LANES 4
-
-static u32 serdes1_prtcl_map;
-
-static const u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = {
- [0x00] = {PCIE1, PCIE2, NONE, NONE},
- [0x01] = {PCIE1, PCIE2, PCIE3, NONE},
- [0x02] = {PCIE1, PCIE2, PCIE3, SGMII_FM1_DTSEC2},
- [0x03] = {PCIE1, PCIE2, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2},
-};
-
-int is_serdes_configured(enum srds_prtcl device)
-{
- int ret;
-
- if (!(serdes1_prtcl_map & (1 << NONE)))
- fsl_serdes_init();
-
- ret = (1 << device) & serdes1_prtcl_map;
- return ret;
-}
-
-void fsl_serdes_init(void)
-{
- ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR;
- u32 pordevsr = in_be32(&gur->pordevsr);
- u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
- MPC85xx_PORDEVSR_IO_SEL_SHIFT;
- int lane;
-
- if (serdes1_prtcl_map & (1 << NONE))
- return;
-
- debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
-
- if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) {
- printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
- return;
- }
- for (lane = 0; lane < SRDS1_MAX_LANES; lane++) {
- enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane];
- serdes1_prtcl_map |= (1 << lane_prtcl);
- }
-
- /* Set the first bit to indicate serdes has been initialized */
- serdes1_prtcl_map |= (1 << NONE);
-}
diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c
index 641d2a199f8..52817a4fc2a 100644
--- a/arch/powerpc/cpu/mpc8xxx/cpu.c
+++ b/arch/powerpc/cpu/mpc8xxx/cpu.c
@@ -48,7 +48,6 @@ static struct cpu_type cpu_type_list[] = {
CPU_TYPE_ENTRY(P1020, P1020, 2),
CPU_TYPE_ENTRY(P1021, P1021, 2),
CPU_TYPE_ENTRY(P1022, P1022, 2),
- CPU_TYPE_ENTRY(P1023, P1023, 2),
CPU_TYPE_ENTRY(P1024, P1024, 2),
CPU_TYPE_ENTRY(P1025, P1025, 2),
CPU_TYPE_ENTRY(P2010, P2010, 1),
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index f115dcce76a..67804ada5ed 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -15,13 +15,6 @@
#define MAX_QE_RISC 1
#define QE_NUM_OF_SNUM 28
-#elif defined(CONFIG_ARCH_P1023)
-#define CFG_SYS_NUM_FMAN 1
-#define CFG_SYS_NUM_FM1_DTSEC 2
-#define CFG_SYS_QMAN_NUM_PORTALS 3
-#define CFG_SYS_BMAN_NUM_PORTALS 3
-#define CFG_SYS_FM_MURAM_SIZE 0x10000
-
/* P1025 is lower end variant of P1021 */
#elif defined(CONFIG_ARCH_P1025)
#define QE_MURAM_SIZE 0x6000UL
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index 489fcd43351..39ddfcfe308 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1790,22 +1790,12 @@ typedef struct ccsr_gur {
#define PORBMSR_ROMLOC_NOR 0xf
u32 porimpscr; /* POR I/O impedance status & control */
u32 pordevsr; /* POR I/O device status regsiter */
-#if defined(CONFIG_ARCH_P1023)
-#define MPC85xx_PORDEVSR_SGMII1_DIS 0x10000000
-#define MPC85xx_PORDEVSR_SGMII2_DIS 0x08000000
-#define MPC85xx_PORDEVSR_TSEC1_PRTC 0x02000000
-#else
#define MPC85xx_PORDEVSR_SGMII1_DIS 0x20000000
#define MPC85xx_PORDEVSR_SGMII2_DIS 0x10000000
-#endif
#define MPC85xx_PORDEVSR_SGMII3_DIS 0x08000000
#define MPC85xx_PORDEVSR_SGMII4_DIS 0x04000000
#define MPC85xx_PORDEVSR_SRDS2_IO_SEL 0x38000000
#define MPC85xx_PORDEVSR_PCI1 0x00800000
-#if defined(CONFIG_ARCH_P1023)
-#define MPC85xx_PORDEVSR_IO_SEL 0x00600000
-#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 21
-#else
#if defined(CONFIG_ARCH_P1010)
#define MPC85xx_PORDEVSR_IO_SEL 0x00600000
#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 21
@@ -1816,7 +1806,6 @@ typedef struct ccsr_gur {
#define MPC85xx_PORDEVSR_IO_SEL 0x00780000
#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 19
#endif /* if defined(CONFIG_ARCH_P1010) */
-#endif
#define MPC85xx_PORDEVSR_PCI2_ARB 0x00040000
#define MPC85xx_PORDEVSR_PCI1_ARB 0x00020000
#define MPC85xx_PORDEVSR_PCI1_PCI32 0x00010000
@@ -1891,9 +1880,6 @@ typedef struct ccsr_gur {
#define MPC85xx_PMUXCR_CAN2_TDM 0x00000002
#define MPC85xx_PMUXCR_CAN2_RES 0x00000003
#endif
-#if defined(CONFIG_ARCH_P1023)
-#define MPC85xx_PMUXCR_TSEC1_1 0x10000000
-#else
#define MPC85xx_PMUXCR_SD_DATA 0x80000000
#define MPC85xx_PMUXCR_SDHC_CD 0x40000000
#define MPC85xx_PMUXCR_SDHC_WP 0x20000000
@@ -1912,7 +1898,6 @@ typedef struct ccsr_gur {
#define MPC85xx_PMUXCR_QE10 0x00000020
#define MPC85xx_PMUXCR_QE11 0x00000010
#define MPC85xx_PMUXCR_QE12 0x00000008
-#endif
#if defined(CONFIG_ARCH_BSC9131)
#define MPC85xx_PMUXCR_TSEC2_DMA_GPIO_IRQ 0x40000000
#define MPC85xx_PMUXCR_TSEC2_USB 0xC0000000
diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h
index 36d8660cddc..2612f182a4c 100644
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -1040,7 +1040,6 @@
#define SVR_P1020 0x80E400
#define SVR_P1021 0x80E401
#define SVR_P1022 0x80E600
-#define SVR_P1023 0x80F600
#define SVR_P1024 0x80E402
#define SVR_P1025 0x80E403
#define SVR_P2010 0x80E300
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index b4224c24040..ac201ba45c2 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -962,7 +962,6 @@ config SYS_DPAA_QBMAN
depends on ARM || PPC
default y if ARCH_B4860 || \
ARCH_B4420 || \
- ARCH_P1023 || \
ARCH_P2041 || \
ARCH_T1024 || \
ARCH_T1040 || \
diff --git a/drivers/net/fm/Makefile b/drivers/net/fm/Makefile
index 6ec673feec4..847c1cbe340 100644
--- a/drivers/net/fm/Makefile
+++ b/drivers/net/fm/Makefile
@@ -13,7 +13,6 @@ obj-y += tgec_phy.o
obj-$(CONFIG_SYS_FMAN_V3) += memac.o
# SoC specific SERDES support
-obj-$(CONFIG_ARCH_P1023) += p1023.o
# The P204x and P5020 are the same
obj-$(CONFIG_ARCH_P2041) += p5020.o
obj-$(CONFIG_ARCH_T1040) += t1040.o
diff --git a/drivers/net/fm/fm.h b/drivers/net/fm/fm.h
index 5c45ad56d0a..cafdaf89014 100644
--- a/drivers/net/fm/fm.h
+++ b/drivers/net/fm/fm.h
@@ -96,11 +96,7 @@ struct fm_port_global_pram {
#define PRAM_MODE_GLOBAL 0x20000000
#define PRAM_MODE_GRACEFUL_STOP 0x00800000
-#if defined(CONFIG_ARCH_P1023)
-#define FM_FREE_POOL_SIZE 0x2000 /* 8K bytes */
-#else
#define FM_FREE_POOL_SIZE 0x20000 /* 128K bytes */
-#endif
#define FM_FREE_POOL_ALIGN 256
void *fm_muram_alloc(int fm_idx, size_t size, ulong align);
diff --git a/drivers/net/fm/p1023.c b/drivers/net/fm/p1023.c
deleted file mode 100644
index 362bc9f30a1..00000000000
--- a/drivers/net/fm/p1023.c
+++ /dev/null
@@ -1,72 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2011 Freescale Semiconductor, Inc.
- */
-#include <config.h>
-#include <phy.h>
-#include <fm_eth.h>
-#include <asm/io.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_serdes.h>
-
-static u32 port_to_devdisr[] = {
- [FM1_DTSEC1] = MPC85xx_DEVDISR_TSEC1,
- [FM1_DTSEC2] = MPC85xx_DEVDISR_TSEC2,
-};
-
-static int is_device_disabled(enum fm_port port)
-{
- ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
- u32 devdisr = in_be32(&gur->devdisr);
-
- return port_to_devdisr[port] & devdisr;
-}
-
-void fman_disable_port(enum fm_port port)
-{
- ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
-
- /* don't allow disabling of DTSEC1 as its needed for MDIO */
- if (port == FM1_DTSEC1)
- return;
-
- setbits_be32(&gur->devdisr, port_to_devdisr[port]);
-}
-
-void fman_enable_port(enum fm_port port)
-{
- ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
-
- clrbits_be32(&gur->devdisr, port_to_devdisr[port]);
-}
-
-phy_interface_t fman_port_enet_if(enum fm_port port)
-{
- ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
- u32 pordevsr = in_be32(&gur->pordevsr);
-
- if (is_device_disabled(port))
- return PHY_INTERFACE_MODE_NA;
-
- /* DTSEC1 can be SGMII, RGMII or RMII */
- if (port == FM1_DTSEC1) {
- if (is_serdes_configured(SGMII_FM1_DTSEC1))
- return PHY_INTERFACE_MODE_SGMII;
- if (pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS) {
- if (pordevsr & MPC85xx_PORDEVSR_TSEC1_PRTC)
- return PHY_INTERFACE_MODE_RGMII;
- else
- return PHY_INTERFACE_MODE_RMII;
- }
- }
-
- /* DTSEC2 only supports SGMII or RGMII */
- if (port == FM1_DTSEC2) {
- if (is_serdes_configured(SGMII_FM1_DTSEC2))
- return PHY_INTERFACE_MODE_SGMII;
- if (pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS)
- return PHY_INTERFACE_MODE_RGMII;
- }
-
- return PHY_INTERFACE_MODE_NA;
-}
--
2.47.3
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH 15/26] powerpc: mpc85xx: Remove P1025 support
2026-10-09 19:36 [PATCH 00/26] powerpc: drop EOL boards and SoCs, take over maintenance Bradley Morgan
` (13 preceding siblings ...)
2026-10-09 19:36 ` [PATCH 14/26] powerpc: mpc85xx: Remove P1023 support Bradley Morgan
@ 2026-10-09 19:36 ` Bradley Morgan
2026-10-09 19:36 ` [PATCH 16/26] powerpc: mpc85xx: Remove MPC8536 support Bradley Morgan
` (10 subsequent siblings)
25 siblings, 0 replies; 31+ messages in thread
From: Bradley Morgan @ 2026-10-09 19:36 UTC (permalink / raw)
To: Tom Rini, u-boot
Cc: Bradley Morgan, Marek Behún, Marek Mojík,
NXP i . MX U-Boot Team, Alexey Charkov, Anshul Dalal,
Daniel Golle, Fabio Estevam, Gaurav Jain, Ilias Apalodimas,
Jaehoon Chung, James Hilliard, Jerome Forissier, Johan Jonker,
Lukasz Majewski, Marek Vasut, Mario Six, Michael Walle,
Michal Simek, Neil Armstrong, Peng Fan, Pengpeng Hou,
Priyanka Jain, Quentin Schulz, Simon Glass, Stefano Babic,
Tanmay Kathpalia, Torsten Rupp, Vincent Jardin, Weijie Gao
NXP lists the P1025/P1016 family as no longer manufactured. No board in the tree selects ARCH_P1025, so remove its configuration and variant specific
code while retaining the shared P1021 support.
Signed-off-by: Bradley Morgan <brads@mainlining.org>
---
arch/Kconfig | 2 +-
arch/powerpc/cpu/mpc85xx/Kconfig | 22 ----------------------
arch/powerpc/cpu/mpc85xx/Makefile | 1 -
arch/powerpc/cpu/mpc85xx/speed.c | 2 +-
arch/powerpc/cpu/mpc8xxx/cpu.c | 1 -
arch/powerpc/include/asm/config_mpc85xx.h | 6 ------
arch/powerpc/include/asm/immap_85xx.h | 2 +-
arch/powerpc/include/asm/processor.h | 1 -
doc/README.mpc85xx-sd-spi-boot | 2 --
drivers/qe/Kconfig | 3 +--
10 files changed, 4 insertions(+), 38 deletions(-)
diff --git a/arch/Kconfig b/arch/Kconfig
index 07214f2af7c..e806fa2e3e7 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -471,7 +471,7 @@ config SYS_IMMR
default 0xE0000000 if MPC83xx && !ARCH_MPC8313
default 0x01000000 if ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3
default 0xFFE00000 if ARCH_P1010 || ARCH_P1020 || \
- ARCH_P1021 || ARCH_P1024 || ARCH_P1025 || \
+ ARCH_P1021 || ARCH_P1024 || \
ARCH_P2020
default SYS_CCSRBAR_DEFAULT
help
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index f4e34adbaea..6ca0ccd65e7 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -466,24 +466,6 @@ config ARCH_P1024
imply CMD_REGINFO
imply SATA_SIL
-config ARCH_P1025
- bool
- select FSL_LAW
- select SYS_FSL_ERRATUM_A004508
- select SYS_FSL_ERRATUM_A005125
- select SYS_FSL_ERRATUM_ELBC_A001
- select SYS_FSL_ERRATUM_ESDHC111
- select FSL_PCIE_DISABLE_ASPM
- select FSL_PCIE_RESET
- select SYS_FSL_HAS_DDR3
- select SYS_FSL_HAS_SEC
- select SYS_FSL_SEC_BE
- select SYS_FSL_SEC_COMPAT_2
- select SYS_PPC_E500_USE_DEBUG_TLB
- select FSL_ELBC
- imply SATA
- imply CMD_REGINFO
-
config ARCH_P2020
bool
select BTB
@@ -781,7 +763,6 @@ config MAX_CPUS
ARCH_P1020 || \
ARCH_P1021 || \
ARCH_P1024 || \
- ARCH_P1025 || \
ARCH_P2020 || \
ARCH_T1024
default 1
@@ -804,7 +785,6 @@ config SYS_CCSRBAR_DEFAULT
ARCH_P1020 || \
ARCH_P1021 || \
ARCH_P1024 || \
- ARCH_P1025 || \
ARCH_P2020
default 0xfe000000 if ARCH_B4420 || \
ARCH_B4860 || \
@@ -1012,7 +992,6 @@ config SYS_FSL_NUM_LAWS
ARCH_P1020 || \
ARCH_P1021 || \
ARCH_P1024 || \
- ARCH_P1025 || \
ARCH_P2020
default 10 if ARCH_MPC8544
default 8 if ARCH_MPC8540 || \
@@ -1125,7 +1104,6 @@ config SYS_PPC_E500_DEBUG_TLB
default 2 if ARCH_P1020 || \
ARCH_P1021 || \
ARCH_P1024 || \
- ARCH_P1025 || \
ARCH_P2020
default 3 if ARCH_P1010 || \
ARCH_BSC9132
diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile
index c40558880ea..3746d5c6fdb 100644
--- a/arch/powerpc/cpu/mpc85xx/Makefile
+++ b/arch/powerpc/cpu/mpc85xx/Makefile
@@ -57,7 +57,6 @@ obj-$(CONFIG_ARCH_P1010) += p1010_serdes.o
obj-$(CONFIG_ARCH_P1020) += p1021_serdes.o
obj-$(CONFIG_ARCH_P1021) += p1021_serdes.o
obj-$(CONFIG_ARCH_P1024) += p1021_serdes.o
-obj-$(CONFIG_ARCH_P1025) += p1021_serdes.o
obj-$(CONFIG_ARCH_P2020) += p2020_serdes.o
obj-$(CONFIG_ARCH_P2041) += p2041_serdes.o
obj-$(CONFIG_ARCH_T4240) += t4240_serdes.o
diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c
index d17a19026dd..01fe85ffd57 100644
--- a/arch/powerpc/cpu/mpc85xx/speed.c
+++ b/arch/powerpc/cpu/mpc85xx/speed.c
@@ -544,7 +544,7 @@ void get_sys_info(sys_info_t *sys_info)
#endif
#ifdef CONFIG_QE
-#if defined(CONFIG_ARCH_P1021) || defined(CONFIG_ARCH_P1025)
+#if defined(CONFIG_ARCH_P1021)
sys_info->freq_qe = sys_info->freq_systembus;
#else
qe_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_QE_RATIO)
diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c
index 52817a4fc2a..8c02893f63b 100644
--- a/arch/powerpc/cpu/mpc8xxx/cpu.c
+++ b/arch/powerpc/cpu/mpc8xxx/cpu.c
@@ -49,7 +49,6 @@ static struct cpu_type cpu_type_list[] = {
CPU_TYPE_ENTRY(P1021, P1021, 2),
CPU_TYPE_ENTRY(P1022, P1022, 2),
CPU_TYPE_ENTRY(P1024, P1024, 2),
- CPU_TYPE_ENTRY(P1025, P1025, 2),
CPU_TYPE_ENTRY(P2010, P2010, 1),
CPU_TYPE_ENTRY(P2020, P2020, 2),
CPU_TYPE_ENTRY(P2040, P2040, 4),
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index 67804ada5ed..3cc952797a7 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -15,12 +15,6 @@
#define MAX_QE_RISC 1
#define QE_NUM_OF_SNUM 28
-/* P1025 is lower end variant of P1021 */
-#elif defined(CONFIG_ARCH_P1025)
-#define QE_MURAM_SIZE 0x6000UL
-#define MAX_QE_RISC 1
-#define QE_NUM_OF_SNUM 28
-
#elif defined(CONFIG_ARCH_P2020)
#define CFG_SYS_FSL_SRIO_MAX_PORTS 2
#define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index 39ddfcfe308..9f5e9a7cfcd 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -2077,7 +2077,7 @@ typedef struct ccsr_gur {
u32 svr; /* System version */
u8 res10[8];
u32 rstcr; /* Reset control */
-#if defined(CONFIG_ARCH_P1021) || defined(CONFIG_ARCH_P1025)
+#if defined(CONFIG_ARCH_P1021)
u8 res11a[12];
u32 iovselsr;
u8 res11b[60];
diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h
index 2612f182a4c..748cf1a3f54 100644
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -1041,7 +1041,6 @@
#define SVR_P1021 0x80E401
#define SVR_P1022 0x80E600
#define SVR_P1024 0x80E402
-#define SVR_P1025 0x80E403
#define SVR_P2010 0x80E300
#define SVR_P2020 0x80E200
#define SVR_P2040 0x821000
diff --git a/doc/README.mpc85xx-sd-spi-boot b/doc/README.mpc85xx-sd-spi-boot
index 086c8f9e49b..7a5748f5df3 100644
--- a/doc/README.mpc85xx-sd-spi-boot
+++ b/doc/README.mpc85xx-sd-spi-boot
@@ -64,8 +64,6 @@ P1010RDB config_ddr3_1gb_p1010rdb_800M.dat
P1021RDB config_ddr3_1gb_p1_p2_rdb_pc_800M.dat
P1022DS config_ddr3_2gb_p1022ds.dat
P1024RDB config_ddr3_1gb_p1_p2_rdb_pc_667M.dat
-P1025RDB config_ddr3_1gb_p1_p2_rdb_pc_667M.dat
-P1016RDB config_ddr3_1gb_p1_p2_rdb_pc_667M.dat
P1020UTM config_ddr3_1gb_p1_p2_rdb_pc_800M.dat
P1020MBG config_ddr3_1gb_p1_p2_rdb_pc_800M.dat
MPC8536DS config_ddr2_512m_mpc8536ds_667M.dat
diff --git a/drivers/qe/Kconfig b/drivers/qe/Kconfig
index 22ed80bfc66..1d10422dd37 100644
--- a/drivers/qe/Kconfig
+++ b/drivers/qe/Kconfig
@@ -4,8 +4,7 @@
config QE
bool "Enable support for QUICC Engine"
depends on PPC
- default y if ARCH_T1040 || ARCH_T1042 || ARCH_T1024 || ARCH_P1021 \
- || ARCH_P1025
+ default y if ARCH_T1040 || ARCH_T1042 || ARCH_T1024 || ARCH_P1021
help
Chose this option to add support for the QUICC Engine.
--
2.47.3
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH 16/26] powerpc: mpc85xx: Remove MPC8536 support
2026-10-09 19:36 [PATCH 00/26] powerpc: drop EOL boards and SoCs, take over maintenance Bradley Morgan
` (14 preceding siblings ...)
2026-10-09 19:36 ` [PATCH 15/26] powerpc: mpc85xx: Remove P1025 support Bradley Morgan
@ 2026-10-09 19:36 ` Bradley Morgan
2026-10-09 19:36 ` [PATCH 17/26] powerpc: mpc85xx: Remove MPC8540 support Bradley Morgan
` (9 subsequent siblings)
25 siblings, 0 replies; 31+ messages in thread
From: Bradley Morgan @ 2026-10-09 19:36 UTC (permalink / raw)
To: Tom Rini, u-boot
Cc: Bradley Morgan, Marek Behún, Marek Mojík,
NXP i . MX U-Boot Team, Alexey Charkov, Anshul Dalal,
Daniel Golle, Fabio Estevam, Gaurav Jain, Ilias Apalodimas,
Jaehoon Chung, James Hilliard, Jerome Forissier, Johan Jonker,
Lukasz Majewski, Marek Vasut, Mario Six, Michael Walle,
Michal Simek, Neil Armstrong, Peng Fan, Pengpeng Hou,
Priyanka Jain, Quentin Schulz, Simon Glass, Stefano Babic,
Tanmay Kathpalia, Torsten Rupp, Vincent Jardin, Weijie Gao
NXP lists MPC8536 as no longer manufactured, and no board in the tree selects
ARCH_MPC8536. Remove the unused SoC configuration, SERDES setup, and
CPU identification.
Signed-off-by: Bradley Morgan <brads@mainlining.org>
---
arch/powerpc/cpu/mpc85xx/Kconfig | 20 --
arch/powerpc/cpu/mpc85xx/Makefile | 1 -
arch/powerpc/cpu/mpc85xx/mpc8536_serdes.c | 250 ----------------------
arch/powerpc/cpu/mpc8xxx/cpu.c | 1 -
arch/powerpc/include/asm/immap_85xx.h | 10 -
arch/powerpc/include/asm/processor.h | 5 -
doc/README.mpc85xx-sd-spi-boot | 1 -
7 files changed, 288 deletions(-)
delete mode 100644 arch/powerpc/cpu/mpc85xx/mpc8536_serdes.c
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index 6ca0ccd65e7..8391ea23cdb 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -321,23 +321,6 @@ config ARCH_BSC9132
imply CMD_PCI
imply CMD_REGINFO
-config ARCH_MPC8536
- bool
- select FSL_LAW
- select SYS_FSL_ERRATUM_A004508
- select SYS_FSL_ERRATUM_A005125
- select FSL_PCIE_RESET
- select SYS_FSL_HAS_DDR2
- select SYS_FSL_HAS_DDR3
- select SYS_FSL_HAS_SEC
- select SYS_FSL_SEC_BE
- select SYS_FSL_SEC_COMPAT_2
- select SYS_PPC_E500_USE_DEBUG_TLB
- select FSL_ELBC
- imply CMD_NAND
- imply SATA
- imply CMD_REGINFO
-
config ARCH_MPC8540
bool
select FSL_LAW
@@ -777,7 +760,6 @@ config SYS_CCSRBAR_DEFAULT
hex "Default CCSRBAR address"
default 0xff700000 if ARCH_BSC9131 || \
ARCH_BSC9132 || \
- ARCH_MPC8536 || \
ARCH_MPC8540 || \
ARCH_MPC8544 || \
ARCH_MPC8560 || \
@@ -987,7 +969,6 @@ config SYS_FSL_NUM_LAWS
ARCH_T1042
default 12 if ARCH_BSC9131 || \
ARCH_BSC9132 || \
- ARCH_MPC8536 || \
ARCH_P1010 || \
ARCH_P1020 || \
ARCH_P1021 || \
@@ -1100,7 +1081,6 @@ config SYS_PPC_E500_DEBUG_TLB
int "Temporary TLB entry for external debugger"
depends on SYS_PPC_E500_USE_DEBUG_TLB
default 0 if ARCH_MPC8544
- default 1 if ARCH_MPC8536
default 2 if ARCH_P1020 || \
ARCH_P1021 || \
ARCH_P1024 || \
diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile
index 3746d5c6fdb..43a5b5b67a4 100644
--- a/arch/powerpc/cpu/mpc85xx/Makefile
+++ b/arch/powerpc/cpu/mpc85xx/Makefile
@@ -51,7 +51,6 @@ obj-$(CONFIG_SYS_FSL_QORIQ_CHASSIS1) += fsl_corenet_serdes.o
obj-$(CONFIG_SYS_FSL_QORIQ_CHASSIS2) += fsl_corenet2_serdes.o
# SoC specific SERDES support
-obj-$(CONFIG_ARCH_MPC8536) += mpc8536_serdes.o
obj-$(CONFIG_ARCH_MPC8544) += mpc8544_serdes.o
obj-$(CONFIG_ARCH_P1010) += p1010_serdes.o
obj-$(CONFIG_ARCH_P1020) += p1021_serdes.o
diff --git a/arch/powerpc/cpu/mpc85xx/mpc8536_serdes.c b/arch/powerpc/cpu/mpc85xx/mpc8536_serdes.c
deleted file mode 100644
index bafff2083b3..00000000000
--- a/arch/powerpc/cpu/mpc85xx/mpc8536_serdes.c
+++ /dev/null
@@ -1,250 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2008,2010 Freescale Semiconductor, Inc.
- * Dave Liu <daveliu@freescale.com>
- */
-
-#include <config.h>
-#include <log.h>
-#include <asm/io.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_serdes.h>
-
-/* PORDEVSR register */
-#define GUTS_PORDEVSR_OFFS 0xc
-#define GUTS_PORDEVSR_SERDES2_IO_SEL 0x38000000
-#define GUTS_PORDEVSR_SERDES2_IO_SEL_SHIFT 27
-
-/* SerDes CR0 register */
-#define FSL_SRDSCR0_OFFS 0x0
-#define FSL_SRDSCR0_TXEQA_MASK 0x00007000
-#define FSL_SRDSCR0_TXEQA_SGMII 0x00004000
-#define FSL_SRDSCR0_TXEQA_SATA 0x00001000
-#define FSL_SRDSCR0_TXEQE_MASK 0x00000700
-#define FSL_SRDSCR0_TXEQE_SGMII 0x00000400
-#define FSL_SRDSCR0_TXEQE_SATA 0x00000100
-
-/* SerDes CR1 register */
-#define FSL_SRDSCR1_OFFS 0x4
-#define FSL_SRDSCR1_LANEA_MASK 0x80200000
-#define FSL_SRDSCR1_LANEA_OFF 0x80200000
-#define FSL_SRDSCR1_LANEE_MASK 0x08020000
-#define FSL_SRDSCR1_LANEE_OFF 0x08020000
-
-/* SerDes CR2 register */
-#define FSL_SRDSCR2_OFFS 0x8
-#define FSL_SRDSCR2_EICA_MASK 0x00001f00
-#define FSL_SRDSCR2_EICA_SGMII 0x00000400
-#define FSL_SRDSCR2_EICA_SATA 0x00001400
-#define FSL_SRDSCR2_EICE_MASK 0x0000001f
-#define FSL_SRDSCR2_EICE_SGMII 0x00000004
-#define FSL_SRDSCR2_EICE_SATA 0x00000014
-
-/* SerDes CR3 register */
-#define FSL_SRDSCR3_OFFS 0xc
-#define FSL_SRDSCR3_LANEA_MASK 0x3f000700
-#define FSL_SRDSCR3_LANEA_SGMII 0x00000000
-#define FSL_SRDSCR3_LANEA_SATA 0x15000500
-#define FSL_SRDSCR3_LANEE_MASK 0x003f0007
-#define FSL_SRDSCR3_LANEE_SGMII 0x00000000
-#define FSL_SRDSCR3_LANEE_SATA 0x00150005
-
-#define SRDS1_MAX_LANES 8
-#define SRDS2_MAX_LANES 2
-
-static u32 serdes1_prtcl_map, serdes2_prtcl_map;
-
-static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = {
- [0x2] = {PCIE1, PCIE1, PCIE1, PCIE1, NONE, NONE, NONE, NONE},
- [0x3] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1},
- [0x5] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2},
- [0x7] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE3, PCIE3},
-};
-
-static u8 serdes2_cfg_tbl[][SRDS2_MAX_LANES] = {
- [0x1] = {SATA1, SATA2},
- [0x3] = {SATA1, NONE},
- [0x4] = {SGMII_TSEC1, SGMII_TSEC3},
- [0x6] = {SGMII_TSEC1, NONE},
-};
-
-int is_serdes_configured(enum srds_prtcl device)
-{
- int ret;
-
- if (!(serdes1_prtcl_map & (1 << NONE)))
- fsl_serdes_init();
-
- ret = (1 << device) & serdes1_prtcl_map;
-
- if (ret)
- return ret;
-
- if (!(serdes2_prtcl_map & (1 << NONE)))
- fsl_serdes_init();
-
- return (1 << device) & serdes2_prtcl_map;
-}
-
-void fsl_serdes_init(void)
-{
- void *guts = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
- void *sd = (void *)CFG_SYS_MPC85xx_SERDES2_ADDR;
- u32 pordevsr = in_be32(guts + GUTS_PORDEVSR_OFFS);
- u32 srds1_io_sel, srds2_io_sel;
- u32 tmp;
- int lane;
-
- if (serdes1_prtcl_map & (1 << NONE) &&
- serdes2_prtcl_map & (1 << NONE))
- return;
-
- srds1_io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
- MPC85xx_PORDEVSR_IO_SEL_SHIFT;
-
- /* parse the SRDS2_IO_SEL of PORDEVSR */
- srds2_io_sel = (pordevsr & GUTS_PORDEVSR_SERDES2_IO_SEL)
- >> GUTS_PORDEVSR_SERDES2_IO_SEL_SHIFT;
-
- debug("PORDEVSR[SRDS1_IO_SEL] = %x\n", srds1_io_sel);
- debug("PORDEVSR[SRDS2_IO_SEL] = %x\n", srds2_io_sel);
-
- switch (srds2_io_sel) {
- case 1: /* Lane A - SATA1, Lane E - SATA2 */
- /* CR 0 */
- tmp = in_be32(sd + FSL_SRDSCR0_OFFS);
- tmp &= ~FSL_SRDSCR0_TXEQA_MASK;
- tmp |= FSL_SRDSCR0_TXEQA_SATA;
- tmp &= ~FSL_SRDSCR0_TXEQE_MASK;
- tmp |= FSL_SRDSCR0_TXEQE_SATA;
- out_be32(sd + FSL_SRDSCR0_OFFS, tmp);
- /* CR 1 */
- tmp = in_be32(sd + FSL_SRDSCR1_OFFS);
- tmp &= ~FSL_SRDSCR1_LANEA_MASK;
- tmp &= ~FSL_SRDSCR1_LANEE_MASK;
- out_be32(sd + FSL_SRDSCR1_OFFS, tmp);
- /* CR 2 */
- tmp = in_be32(sd + FSL_SRDSCR2_OFFS);
- tmp &= ~FSL_SRDSCR2_EICA_MASK;
- tmp |= FSL_SRDSCR2_EICA_SATA;
- tmp &= ~FSL_SRDSCR2_EICE_MASK;
- tmp |= FSL_SRDSCR2_EICE_SATA;
- out_be32(sd + FSL_SRDSCR2_OFFS, tmp);
- /* CR 3 */
- tmp = in_be32(sd + FSL_SRDSCR3_OFFS);
- tmp &= ~FSL_SRDSCR3_LANEA_MASK;
- tmp |= FSL_SRDSCR3_LANEA_SATA;
- tmp &= ~FSL_SRDSCR3_LANEE_MASK;
- tmp |= FSL_SRDSCR3_LANEE_SATA;
- out_be32(sd + FSL_SRDSCR3_OFFS, tmp);
- break;
- case 3: /* Lane A - SATA1, Lane E - disabled */
- /* CR 0 */
- tmp = in_be32(sd + FSL_SRDSCR0_OFFS);
- tmp &= ~FSL_SRDSCR0_TXEQA_MASK;
- tmp |= FSL_SRDSCR0_TXEQA_SATA;
- out_be32(sd + FSL_SRDSCR0_OFFS, tmp);
- /* CR 1 */
- tmp = in_be32(sd + FSL_SRDSCR1_OFFS);
- tmp &= ~FSL_SRDSCR1_LANEE_MASK;
- tmp |= FSL_SRDSCR1_LANEE_OFF;
- out_be32(sd + FSL_SRDSCR1_OFFS, tmp);
- /* CR 2 */
- tmp = in_be32(sd + FSL_SRDSCR2_OFFS);
- tmp &= ~FSL_SRDSCR2_EICA_MASK;
- tmp |= FSL_SRDSCR2_EICA_SATA;
- out_be32(sd + FSL_SRDSCR2_OFFS, tmp);
- /* CR 3 */
- tmp = in_be32(sd + FSL_SRDSCR3_OFFS);
- tmp &= ~FSL_SRDSCR3_LANEA_MASK;
- tmp |= FSL_SRDSCR3_LANEA_SATA;
- out_be32(sd + FSL_SRDSCR3_OFFS, tmp);
- break;
- case 4: /* Lane A - eTSEC1 SGMII, Lane E - eTSEC3 SGMII */
- /* CR 0 */
- tmp = in_be32(sd + FSL_SRDSCR0_OFFS);
- tmp &= ~FSL_SRDSCR0_TXEQA_MASK;
- tmp |= FSL_SRDSCR0_TXEQA_SGMII;
- tmp &= ~FSL_SRDSCR0_TXEQE_MASK;
- tmp |= FSL_SRDSCR0_TXEQE_SGMII;
- out_be32(sd + FSL_SRDSCR0_OFFS, tmp);
- /* CR 1 */
- tmp = in_be32(sd + FSL_SRDSCR1_OFFS);
- tmp &= ~FSL_SRDSCR1_LANEA_MASK;
- tmp &= ~FSL_SRDSCR1_LANEE_MASK;
- out_be32(sd + FSL_SRDSCR1_OFFS, tmp);
- /* CR 2 */
- tmp = in_be32(sd + FSL_SRDSCR2_OFFS);
- tmp &= ~FSL_SRDSCR2_EICA_MASK;
- tmp |= FSL_SRDSCR2_EICA_SGMII;
- tmp &= ~FSL_SRDSCR2_EICE_MASK;
- tmp |= FSL_SRDSCR2_EICE_SGMII;
- out_be32(sd + FSL_SRDSCR2_OFFS, tmp);
- /* CR 3 */
- tmp = in_be32(sd + FSL_SRDSCR3_OFFS);
- tmp &= ~FSL_SRDSCR3_LANEA_MASK;
- tmp |= FSL_SRDSCR3_LANEA_SGMII;
- tmp &= ~FSL_SRDSCR3_LANEE_MASK;
- tmp |= FSL_SRDSCR3_LANEE_SGMII;
- out_be32(sd + FSL_SRDSCR3_OFFS, tmp);
- break;
- case 6: /* Lane A - eTSEC1 SGMII, Lane E - disabled */
- /* CR 0 */
- tmp = in_be32(sd + FSL_SRDSCR0_OFFS);
- tmp &= ~FSL_SRDSCR0_TXEQA_MASK;
- tmp |= FSL_SRDSCR0_TXEQA_SGMII;
- out_be32(sd + FSL_SRDSCR0_OFFS, tmp);
- /* CR 1 */
- tmp = in_be32(sd + FSL_SRDSCR1_OFFS);
- tmp &= ~FSL_SRDSCR1_LANEE_MASK;
- tmp |= FSL_SRDSCR1_LANEE_OFF;
- out_be32(sd + FSL_SRDSCR1_OFFS, tmp);
- /* CR 2 */
- tmp = in_be32(sd + FSL_SRDSCR2_OFFS);
- tmp &= ~FSL_SRDSCR2_EICA_MASK;
- tmp |= FSL_SRDSCR2_EICA_SGMII;
- out_be32(sd + FSL_SRDSCR2_OFFS, tmp);
- /* CR 3 */
- tmp = in_be32(sd + FSL_SRDSCR3_OFFS);
- tmp &= ~FSL_SRDSCR3_LANEA_MASK;
- tmp |= FSL_SRDSCR3_LANEA_SGMII;
- out_be32(sd + FSL_SRDSCR3_OFFS, tmp);
- break;
- case 7: /* Lane A - disabled, Lane E - disabled */
- /* CR 1 */
- tmp = in_be32(sd + FSL_SRDSCR1_OFFS);
- tmp &= ~FSL_SRDSCR1_LANEA_MASK;
- tmp |= FSL_SRDSCR1_LANEA_OFF;
- tmp &= ~FSL_SRDSCR1_LANEE_MASK;
- tmp |= FSL_SRDSCR1_LANEE_OFF;
- out_be32(sd + FSL_SRDSCR1_OFFS, tmp);
- break;
- default:
- break;
- }
-
- if (srds1_io_sel >= ARRAY_SIZE(serdes1_cfg_tbl)) {
- printf("Invalid PORDEVSR[SRDS1_IO_SEL] = %d\n", srds1_io_sel);
- return;
- }
- for (lane = 0; lane < SRDS1_MAX_LANES; lane++) {
- enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds1_io_sel][lane];
- serdes1_prtcl_map |= (1 << lane_prtcl);
- }
-
- /* Set the first bit to indicate serdes has been initialized */
- serdes1_prtcl_map |= (1 << NONE);
-
- if (srds2_io_sel >= ARRAY_SIZE(serdes2_cfg_tbl)) {
- printf("Invalid PORDEVSR[SRDS2_IO_SEL] = %d\n", srds2_io_sel);
- return;
- }
-
- for (lane = 0; lane < SRDS2_MAX_LANES; lane++) {
- enum srds_prtcl lane_prtcl = serdes2_cfg_tbl[srds2_io_sel][lane];
- serdes2_prtcl_map |= (1 << lane_prtcl);
- }
-
- /* Set the first bit to indicate serdes has been initialized */
- serdes2_prtcl_map |= (1 << NONE);
-}
diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c
index 8c02893f63b..5ef82e84324 100644
--- a/arch/powerpc/cpu/mpc8xxx/cpu.c
+++ b/arch/powerpc/cpu/mpc8xxx/cpu.c
@@ -26,7 +26,6 @@ static struct cpu_type cpu_type_list[] = {
#if defined(CONFIG_MPC85xx)
CPU_TYPE_ENTRY(8533, 8533, 1),
CPU_TYPE_ENTRY(8535, 8535, 1),
- CPU_TYPE_ENTRY(8536, 8536, 1),
CPU_TYPE_ENTRY(8540, 8540, 1),
CPU_TYPE_ENTRY(8541, 8541, 1),
CPU_TYPE_ENTRY(8543, 8543, 1),
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index 9f5e9a7cfcd..695c89f2237 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1765,17 +1765,12 @@ typedef struct ccsr_rcpm {
#else
typedef struct ccsr_gur {
u32 porpllsr; /* POR PLL ratio status */
-#ifdef CONFIG_ARCH_MPC8536
-#define MPC85xx_PORPLLSR_DDR_RATIO 0x3e000000
-#define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT 25
-#else
#if defined(CONFIG_ARCH_BSC9131) || defined(CONFIG_ARCH_BSC9132)
#define MPC85xx_PORPLLSR_DDR_RATIO 0x00003f00
#else
#define MPC85xx_PORPLLSR_DDR_RATIO 0x00003e00
#endif
#define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT 9
-#endif
#define MPC85xx_PORPLLSR_QE_RATIO 0x3e000000
#define MPC85xx_PORPLLSR_QE_RATIO_SHIFT 25
#define MPC85xx_PORPLLSR_PLAT_RATIO 0x0000003e
@@ -1822,12 +1817,7 @@ typedef struct ccsr_gur {
u8 res1[8];
u32 gpporcr; /* General-purpose POR configuration */
u8 res2[12];
-#if defined(CONFIG_ARCH_MPC8536)
- u32 gencfgr; /* General Configuration Register */
-#define MPC85xx_GENCFGR_SDHC_WP_INV 0x20000000
-#else
u32 gpiocr; /* GPIO control */
-#endif
u8 res3[12];
u32 gpoutdr; /* General-purpose output data */
u8 res4[12];
diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h
index 748cf1a3f54..e11498c6e78 100644
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -990,11 +990,7 @@
#define SVR_FAM(svr) (((svr) >> 20) & 0xFFF) /* Family field */
#define SVR_MEM(svr) (((svr) >> 16) & 0xF) /* Member field */
-#ifdef CONFIG_ARCH_MPC8536
-#define SVR_MAJ(svr) (((svr) >> 4) & 0x7) /* Major revision field*/
-#else
#define SVR_MAJ(svr) (((svr) >> 4) & 0xF) /* Major revision field*/
-#endif
#define SVR_MIN(svr) (((svr) >> 0) & 0xF) /* Minor revision field*/
/* Some parts define SVR[0:23] as the SOC version */
@@ -1018,7 +1014,6 @@
#define SVR_8533 0x803400
#define SVR_8535 0x803701
-#define SVR_8536 0x803700
#define SVR_8540 0x803000
#define SVR_8541 0x807200
#define SVR_8543 0x803200
diff --git a/doc/README.mpc85xx-sd-spi-boot b/doc/README.mpc85xx-sd-spi-boot
index 7a5748f5df3..c382e9bf7aa 100644
--- a/doc/README.mpc85xx-sd-spi-boot
+++ b/doc/README.mpc85xx-sd-spi-boot
@@ -66,4 +66,3 @@ P1022DS config_ddr3_2gb_p1022ds.dat
P1024RDB config_ddr3_1gb_p1_p2_rdb_pc_667M.dat
P1020UTM config_ddr3_1gb_p1_p2_rdb_pc_800M.dat
P1020MBG config_ddr3_1gb_p1_p2_rdb_pc_800M.dat
-MPC8536DS config_ddr2_512m_mpc8536ds_667M.dat
--
2.47.3
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH 17/26] powerpc: mpc85xx: Remove MPC8540 support
2026-10-09 19:36 [PATCH 00/26] powerpc: drop EOL boards and SoCs, take over maintenance Bradley Morgan
` (15 preceding siblings ...)
2026-10-09 19:36 ` [PATCH 16/26] powerpc: mpc85xx: Remove MPC8536 support Bradley Morgan
@ 2026-10-09 19:36 ` Bradley Morgan
2026-10-09 19:36 ` [PATCH 18/26] powerpc: mpc85xx: Remove MPC8560 support Bradley Morgan
` (8 subsequent siblings)
25 siblings, 0 replies; 31+ messages in thread
From: Bradley Morgan @ 2026-10-09 19:36 UTC (permalink / raw)
To: Tom Rini, u-boot
Cc: Bradley Morgan, Marek Behún, Marek Mojík,
NXP i . MX U-Boot Team, Alexey Charkov, Anshul Dalal,
Daniel Golle, Fabio Estevam, Gaurav Jain, Ilias Apalodimas,
Jaehoon Chung, James Hilliard, Jerome Forissier, Johan Jonker,
Lukasz Majewski, Marek Vasut, Mario Six, Michael Walle,
Michal Simek, Neil Armstrong, Peng Fan, Pengpeng Hou,
Priyanka Jain, Quentin Schulz, Simon Glass, Stefano Babic,
Tanmay Kathpalia, Torsten Rupp, Vincent Jardin, Weijie Gao
NXP lists MPC8540 as no longer manufactured, and no board in the tree selects
ARCH_MPC8540. Remove its architecture configuration, DUART definitions,
and CPU specific cache handling.
Signed-off-by: Bradley Morgan <brads@mainlining.org>
---
README | 2 +-
arch/powerpc/cpu/mpc85xx/Kconfig | 12 ++-------
arch/powerpc/cpu/mpc85xx/cpu.c | 2 +-
arch/powerpc/cpu/mpc85xx/cpu_init.c | 4 +--
arch/powerpc/cpu/mpc85xx/fdt.c | 4 +--
arch/powerpc/cpu/mpc85xx/speed.c | 2 +-
arch/powerpc/cpu/mpc8xxx/cpu.c | 1 -
arch/powerpc/include/asm/fsl_lbc.h | 3 +--
arch/powerpc/include/asm/immap_85xx.h | 35 ---------------------------
arch/powerpc/include/asm/processor.h | 1 -
10 files changed, 10 insertions(+), 56 deletions(-)
diff --git a/README b/README
index 7060bc5ac0c..830aa9b722f 100644
--- a/README
+++ b/README
@@ -137,7 +137,7 @@ The following options need to be configured:
- CPU Type: Define exactly one, e.g. CONFIG_MPC85XX.
-- Board Type: Define exactly one, e.g. CONFIG_MPC8540ADS.
+- Board Type: Define exactly one.
- 85xx CPU Options:
CONFIG_SYS_PPC64
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index 8391ea23cdb..2d405501c57 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -321,11 +321,6 @@ config ARCH_BSC9132
imply CMD_PCI
imply CMD_REGINFO
-config ARCH_MPC8540
- bool
- select FSL_LAW
- select SYS_FSL_HAS_DDR1
-
config ARCH_MPC8544
bool
select BTB
@@ -760,7 +755,6 @@ config SYS_CCSRBAR_DEFAULT
hex "Default CCSRBAR address"
default 0xff700000 if ARCH_BSC9131 || \
ARCH_BSC9132 || \
- ARCH_MPC8540 || \
ARCH_MPC8544 || \
ARCH_MPC8560 || \
ARCH_P1010 || \
@@ -975,8 +969,7 @@ config SYS_FSL_NUM_LAWS
ARCH_P1024 || \
ARCH_P2020
default 10 if ARCH_MPC8544
- default 8 if ARCH_MPC8540 || \
- ARCH_MPC8560
+ default 8 if ARCH_MPC8560
help
Number of local access windows. This is fixed per SoC.
If not sure, do not change.
@@ -1111,8 +1104,7 @@ config SYS_FSL_IFC_CLK_DIV
config SYS_FSL_LBC_CLK_DIV
int "Divider of platform clock"
- depends on FSL_ELBC || ARCH_MPC8540 || \
- ARCH_MPC8560
+ depends on FSL_ELBC || ARCH_MPC8560
default 2 if ARCH_P2041
default 1
diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c
index ab4ef154729..c33250faac6 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu.c
@@ -302,7 +302,7 @@ int checkcpu (void)
int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
/* Everything after the first generation of PQ3 parts has RSTCR */
-#if defined(CONFIG_ARCH_MPC8540) || defined(CONFIG_ARCH_MPC8560)
+#if defined(CONFIG_ARCH_MPC8560)
unsigned long val, msr;
/*
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 710b3b31354..c6923a797f9 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -546,7 +546,7 @@ int l2cache_init(void)
return -1;
break;
case 0x1:
- if (ver == SVR_8540 || ver == SVR_8560 ||
+ if (ver == SVR_8560 ||
ver == SVR_8541 || ver == SVR_8555) {
puts("128 KiB ");
/* set L2E=1, L2I=1, & L2BLKSZ=1 (128 KiBibyte) */
@@ -557,7 +557,7 @@ int l2cache_init(void)
}
break;
case 0x2:
- if (ver == SVR_8540 || ver == SVR_8560 ||
+ if (ver == SVR_8560 ||
ver == SVR_8541 || ver == SVR_8555) {
puts("256 KiB ");
/* set L2E=1, L2I=1, & L2BLKSZ=2 (256 KiBibyte) */
diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c
index 7de6a033ce2..e115c19cf8d 100644
--- a/arch/powerpc/cpu/mpc85xx/fdt.c
+++ b/arch/powerpc/cpu/mpc85xx/fdt.c
@@ -229,14 +229,14 @@ static inline u32 l2cache_size(void)
case 0x0:
break;
case 0x1:
- if (ver == SVR_8540 || ver == SVR_8560 ||
+ if (ver == SVR_8560 ||
ver == SVR_8541 || ver == SVR_8555)
return 128;
else
return 256;
break;
case 0x2:
- if (ver == SVR_8540 || ver == SVR_8560 ||
+ if (ver == SVR_8560 ||
ver == SVR_8541 || ver == SVR_8555)
return 256;
else
diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c
index 01fe85ffd57..8e9808953dc 100644
--- a/arch/powerpc/cpu/mpc85xx/speed.c
+++ b/arch/powerpc/cpu/mpc85xx/speed.c
@@ -593,7 +593,7 @@ int get_clocks(void)
* for that SOC. This information is taken from application note
* AN2919.
*/
-#if defined(CONFIG_ARCH_MPC8540) || defined(CONFIG_ARCH_MPC8560)
+#if defined(CONFIG_ARCH_MPC8560)
gd->arch.i2c1_clk = sys_info.freq_systembus;
#elif defined(CONFIG_ARCH_MPC8544)
/*
diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c
index 5ef82e84324..8d652e36d17 100644
--- a/arch/powerpc/cpu/mpc8xxx/cpu.c
+++ b/arch/powerpc/cpu/mpc8xxx/cpu.c
@@ -26,7 +26,6 @@ static struct cpu_type cpu_type_list[] = {
#if defined(CONFIG_MPC85xx)
CPU_TYPE_ENTRY(8533, 8533, 1),
CPU_TYPE_ENTRY(8535, 8535, 1),
- CPU_TYPE_ENTRY(8540, 8540, 1),
CPU_TYPE_ENTRY(8541, 8541, 1),
CPU_TYPE_ENTRY(8543, 8543, 1),
CPU_TYPE_ENTRY(8544, 8544, 1),
diff --git a/arch/powerpc/include/asm/fsl_lbc.h b/arch/powerpc/include/asm/fsl_lbc.h
index f07535cb5ea..d98673c40b3 100644
--- a/arch/powerpc/include/asm/fsl_lbc.h
+++ b/arch/powerpc/include/asm/fsl_lbc.h
@@ -321,8 +321,7 @@ void lbc_sdram_init(void);
*/
#define LCRR_CLKDIV 0x0000001F
#define LCRR_CLKDIV_SHIFT 0
-#if defined(CONFIG_MPC83xx) || defined(CONFIG_ARCH_MPC8540) || \
- defined(CONFIG_ARCH_MPC8560)
+#if defined(CONFIG_MPC83xx) || defined(CONFIG_ARCH_MPC8560)
#define LCRR_CLKDIV_2 0x00000002
#define LCRR_CLKDIV_4 0x00000004
#define LCRR_CLKDIV_8 0x00000008
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index 695c89f2237..4479ef813c8 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -123,44 +123,9 @@ typedef struct ccsr_i2c {
u8 res[4096 - 1 * sizeof(struct fsl_i2c_base)];
} ccsr_i2c_t;
-#if defined(CONFIG_ARCH_MPC8540)
-/* DUART Registers */
-typedef struct ccsr_duart {
- u8 res1[1280];
-/* URBR1, UTHR1, UDLB1 with the same addr */
- u8 urbr1_uthr1_udlb1;
-/* UIER1, UDMB1 with the same addr01 */
- u8 uier1_udmb1;
-/* UIIR1, UFCR1, UAFR1 with the same addr */
- u8 uiir1_ufcr1_uafr1;
- u8 ulcr1; /* UART1 Line Control */
- u8 umcr1; /* UART1 Modem Control */
- u8 ulsr1; /* UART1 Line Status */
- u8 umsr1; /* UART1 Modem Status */
- u8 uscr1; /* UART1 Scratch */
- u8 res2[8];
- u8 udsr1; /* UART1 DMA Status */
- u8 res3[239];
-/* URBR2, UTHR2, UDLB2 with the same addr */
- u8 urbr2_uthr2_udlb2;
-/* UIER2, UDMB2 with the same addr */
- u8 uier2_udmb2;
-/* UIIR2, UFCR2, UAFR2 with the same addr */
- u8 uiir2_ufcr2_uafr2;
- u8 ulcr2; /* UART2 Line Control */
- u8 umcr2; /* UART2 Modem Control */
- u8 ulsr2; /* UART2 Line Status */
- u8 umsr2; /* UART2 Modem Status */
- u8 uscr2; /* UART2 Scratch */
- u8 res4[8];
- u8 udsr2; /* UART2 DMA Status */
- u8 res5[2543];
-} ccsr_duart_t;
-#else /* MPC8560 uses UART on its CPM */
typedef struct ccsr_duart {
u8 res[4096];
} ccsr_duart_t;
-#endif
/* eSPI Registers */
typedef struct ccsr_espi {
diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h
index e11498c6e78..77414c05aba 100644
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -1014,7 +1014,6 @@
#define SVR_8533 0x803400
#define SVR_8535 0x803701
-#define SVR_8540 0x803000
#define SVR_8541 0x807200
#define SVR_8543 0x803200
#define SVR_8544 0x803401
--
2.47.3
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH 18/26] powerpc: mpc85xx: Remove MPC8560 support
2026-10-09 19:36 [PATCH 00/26] powerpc: drop EOL boards and SoCs, take over maintenance Bradley Morgan
` (16 preceding siblings ...)
2026-10-09 19:36 ` [PATCH 17/26] powerpc: mpc85xx: Remove MPC8540 support Bradley Morgan
@ 2026-10-09 19:36 ` Bradley Morgan
2026-10-09 19:36 ` [PATCH 19/26] powerpc: mpc85xx: Remove BSC9132 support Bradley Morgan
` (7 subsequent siblings)
25 siblings, 0 replies; 31+ messages in thread
From: Bradley Morgan @ 2026-10-09 19:36 UTC (permalink / raw)
To: Tom Rini, u-boot
Cc: Bradley Morgan, Marek Behún, Marek Mojík,
NXP i . MX U-Boot Team, Alexey Charkov, Anshul Dalal,
Daniel Golle, Fabio Estevam, Gaurav Jain, Ilias Apalodimas,
Jaehoon Chung, James Hilliard, Jerome Forissier, Johan Jonker,
Lukasz Majewski, Marek Vasut, Mario Six, Michael Walle,
Michal Simek, Neil Armstrong, Peng Fan, Pengpeng Hou,
Priyanka Jain, Quentin Schulz, Simon Glass, Stefano Babic,
Tanmay Kathpalia, Torsten Rupp, Vincent Jardin, Weijie Gao
NXP lists MPC8560 as no longer manufactured, and no board in the tree selects
ARCH_MPC8560. Remove the unused architecture configuration, reset and
clock handling, and CPU identification.
Signed-off-by: Bradley Morgan <brads@mainlining.org>
---
arch/powerpc/cpu/mpc85xx/Kconfig | 9 +--------
arch/powerpc/cpu/mpc85xx/cpu.c | 17 -----------------
arch/powerpc/cpu/mpc85xx/cpu_init.c | 6 ++----
arch/powerpc/cpu/mpc85xx/fdt.c | 6 ++----
arch/powerpc/cpu/mpc85xx/speed.c | 4 +---
arch/powerpc/cpu/mpc8xxx/cpu.c | 1 -
arch/powerpc/include/asm/fsl_lbc.h | 2 +-
arch/powerpc/include/asm/immap_85xx.h | 4 ----
arch/powerpc/include/asm/processor.h | 1 -
9 files changed, 7 insertions(+), 43 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index 2d405501c57..bcdeef59fe7 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -335,11 +335,6 @@ config ARCH_MPC8544
select SYS_PPC_E500_USE_DEBUG_TLB
select FSL_ELBC
-config ARCH_MPC8560
- bool
- select FSL_LAW
- select SYS_FSL_HAS_DDR1
-
config ARCH_P1010
bool
select A003399_NOR_WORKAROUND if SYS_FSL_ERRATUM_IFC_A003399 && !SPL
@@ -756,7 +751,6 @@ config SYS_CCSRBAR_DEFAULT
default 0xff700000 if ARCH_BSC9131 || \
ARCH_BSC9132 || \
ARCH_MPC8544 || \
- ARCH_MPC8560 || \
ARCH_P1010 || \
ARCH_P1020 || \
ARCH_P1021 || \
@@ -969,7 +963,6 @@ config SYS_FSL_NUM_LAWS
ARCH_P1024 || \
ARCH_P2020
default 10 if ARCH_MPC8544
- default 8 if ARCH_MPC8560
help
Number of local access windows. This is fixed per SoC.
If not sure, do not change.
@@ -1104,7 +1097,7 @@ config SYS_FSL_IFC_CLK_DIV
config SYS_FSL_LBC_CLK_DIV
int "Divider of platform clock"
- depends on FSL_ELBC || ARCH_MPC8560
+ depends on FSL_ELBC
default 2 if ARCH_P2041
default 1
diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c
index c33250faac6..b4e9f6aac66 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu.c
@@ -301,22 +301,6 @@ int checkcpu (void)
int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
-/* Everything after the first generation of PQ3 parts has RSTCR */
-#if defined(CONFIG_ARCH_MPC8560)
- unsigned long val, msr;
-
- /*
- * Initiate hard reset in debug control register DBCR0
- * Make sure MSR[DE] = 1. This only resets the core.
- */
- msr = mfmsr ();
- msr |= MSR_DE;
- mtmsr (msr);
-
- val = mfspr(DBCR0);
- val |= 0x70000000;
- mtspr(DBCR0,val);
-#else
volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
/* Call board-specific preparation for reset */
@@ -331,7 +315,6 @@ int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
/* Attempt last-stage board-specific reset */
board_reset_last();
-#endif
return 1;
}
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index c6923a797f9..7970c296e5a 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -546,8 +546,7 @@ int l2cache_init(void)
return -1;
break;
case 0x1:
- if (ver == SVR_8560 ||
- ver == SVR_8541 || ver == SVR_8555) {
+ if (ver == SVR_8541 || ver == SVR_8555) {
puts("128 KiB ");
/* set L2E=1, L2I=1, & L2BLKSZ=1 (128 KiBibyte) */
cache_ctl = 0xc4000000;
@@ -557,8 +556,7 @@ int l2cache_init(void)
}
break;
case 0x2:
- if (ver == SVR_8560 ||
- ver == SVR_8541 || ver == SVR_8555) {
+ if (ver == SVR_8541 || ver == SVR_8555) {
puts("256 KiB ");
/* set L2E=1, L2I=1, & L2BLKSZ=2 (256 KiBibyte) */
cache_ctl = 0xc8000000;
diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c
index e115c19cf8d..e7d1d9473d2 100644
--- a/arch/powerpc/cpu/mpc85xx/fdt.c
+++ b/arch/powerpc/cpu/mpc85xx/fdt.c
@@ -229,15 +229,13 @@ static inline u32 l2cache_size(void)
case 0x0:
break;
case 0x1:
- if (ver == SVR_8560 ||
- ver == SVR_8541 || ver == SVR_8555)
+ if (ver == SVR_8541 || ver == SVR_8555)
return 128;
else
return 256;
break;
case 0x2:
- if (ver == SVR_8560 ||
- ver == SVR_8541 || ver == SVR_8555)
+ if (ver == SVR_8541 || ver == SVR_8555)
return 256;
else
return 512;
diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c
index 8e9808953dc..ed4ae33e6a8 100644
--- a/arch/powerpc/cpu/mpc85xx/speed.c
+++ b/arch/powerpc/cpu/mpc85xx/speed.c
@@ -593,9 +593,7 @@ int get_clocks(void)
* for that SOC. This information is taken from application note
* AN2919.
*/
-#if defined(CONFIG_ARCH_MPC8560)
- gd->arch.i2c1_clk = sys_info.freq_systembus;
-#elif defined(CONFIG_ARCH_MPC8544)
+#if defined(CONFIG_ARCH_MPC8544)
/*
* On the 8544, the I2C clock is the same as the SEC clock. This can be
* either CCB/2 or CCB/3, depending on the value of cfg_sec_freq. See
diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c
index 8d652e36d17..3594c1e3de2 100644
--- a/arch/powerpc/cpu/mpc8xxx/cpu.c
+++ b/arch/powerpc/cpu/mpc8xxx/cpu.c
@@ -33,7 +33,6 @@ static struct cpu_type cpu_type_list[] = {
CPU_TYPE_ENTRY(8547, 8547, 1),
CPU_TYPE_ENTRY(8548, 8548, 1),
CPU_TYPE_ENTRY(8555, 8555, 1),
- CPU_TYPE_ENTRY(8560, 8560, 1),
CPU_TYPE_ENTRY(8567, 8567, 1),
CPU_TYPE_ENTRY(8568, 8568, 1),
CPU_TYPE_ENTRY(8569, 8569, 1),
diff --git a/arch/powerpc/include/asm/fsl_lbc.h b/arch/powerpc/include/asm/fsl_lbc.h
index d98673c40b3..9efb6ae6cd0 100644
--- a/arch/powerpc/include/asm/fsl_lbc.h
+++ b/arch/powerpc/include/asm/fsl_lbc.h
@@ -321,7 +321,7 @@ void lbc_sdram_init(void);
*/
#define LCRR_CLKDIV 0x0000001F
#define LCRR_CLKDIV_SHIFT 0
-#if defined(CONFIG_MPC83xx) || defined(CONFIG_ARCH_MPC8560)
+#if defined(CONFIG_MPC83xx)
#define LCRR_CLKDIV_2 0x00000002
#define LCRR_CLKDIV_4 0x00000004
#define LCRR_CLKDIV_8 0x00000008
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index 4479ef813c8..b646d24bc6b 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -123,10 +123,6 @@ typedef struct ccsr_i2c {
u8 res[4096 - 1 * sizeof(struct fsl_i2c_base)];
} ccsr_i2c_t;
-typedef struct ccsr_duart {
- u8 res[4096];
-} ccsr_duart_t;
-
/* eSPI Registers */
typedef struct ccsr_espi {
u32 mode; /* eSPI mode */
diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h
index 77414c05aba..b78a726445d 100644
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -1021,7 +1021,6 @@
#define SVR_8547 0x803101
#define SVR_8548 0x803100
#define SVR_8555 0x807100
-#define SVR_8560 0x807000
#define SVR_8567 0x807501
#define SVR_8568 0x807500
#define SVR_8569 0x808000
--
2.47.3
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH 19/26] powerpc: mpc85xx: Remove BSC9132 support
2026-10-09 19:36 [PATCH 00/26] powerpc: drop EOL boards and SoCs, take over maintenance Bradley Morgan
` (17 preceding siblings ...)
2026-10-09 19:36 ` [PATCH 18/26] powerpc: mpc85xx: Remove MPC8560 support Bradley Morgan
@ 2026-10-09 19:36 ` Bradley Morgan
2026-10-09 19:36 ` [PATCH 20/26] powerpc: mpc83xx: Remove MPC831x support Bradley Morgan
` (6 subsequent siblings)
25 siblings, 0 replies; 31+ messages in thread
From: Bradley Morgan @ 2026-10-09 19:36 UTC (permalink / raw)
To: Tom Rini, u-boot
Cc: Bradley Morgan, Marek Behún, Marek Mojík,
NXP i . MX U-Boot Team, Alexey Charkov, Anshul Dalal,
Daniel Golle, Fabio Estevam, Gaurav Jain, Ilias Apalodimas,
Jaehoon Chung, James Hilliard, Jerome Forissier, Johan Jonker,
Lukasz Majewski, Marek Vasut, Mario Six, Michael Walle,
Michal Simek, Neil Armstrong, Peng Fan, Pengpeng Hou,
Priyanka Jain, Quentin Schulz, Simon Glass, Stefano Babic,
Tanmay Kathpalia, Torsten Rupp, Vincent Jardin, Weijie Gao
NXP lists BSC9132 as no longer manufactured, and no board in the tree selects
ARCH_BSC9132. Remove its SoC and SERDES configuration, register
code and errata paths.
Signed-off-by: Bradley Morgan <brads@mainlining.org>
---
arch/Kconfig.nxp | 5 +-
arch/powerpc/cpu/mpc85xx/Kconfig | 32 +------
arch/powerpc/cpu/mpc85xx/Makefile | 1 -
arch/powerpc/cpu/mpc85xx/bsc9132_serdes.c | 101 ----------------------
arch/powerpc/cpu/mpc8xxx/cpu.c | 1 -
arch/powerpc/include/asm/fsl_law.h | 6 +-
arch/powerpc/include/asm/immap_85xx.h | 19 +---
arch/powerpc/include/asm/processor.h | 1 -
board/nxp/common/sdhc_boot.c | 2 +-
boot/Kconfig | 2 +-
drivers/ddr/fsl/Kconfig | 1 -
drivers/mmc/Kconfig | 2 +-
drivers/usb/common/fsl-errata.c | 2 -
13 files changed, 9 insertions(+), 166 deletions(-)
delete mode 100644 arch/powerpc/cpu/mpc85xx/bsc9132_serdes.c
diff --git a/arch/Kconfig.nxp b/arch/Kconfig.nxp
index 4ce12613131..15e56ffb35a 100644
--- a/arch/Kconfig.nxp
+++ b/arch/Kconfig.nxp
@@ -286,9 +286,8 @@ config SYS_FSL_IFC_BANK_COUNT
depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A || \
ARCH_LS1088A || ARCH_LS1021A || ARCH_B4860 || ARCH_B4420 || \
ARCH_T4240 || ARCH_T1040 || ARCH_T1042 || ARCH_T1024 || \
- ARCH_T2080 || ARCH_P1010 || ARCH_BSC9131 || \
- ARCH_BSC9132
- default 3 if ARCH_BSC9131 || ARCH_BSC9132
+ ARCH_T2080 || ARCH_P1010 || ARCH_BSC9131
+ default 3 if ARCH_BSC9131
default 4 if ARCH_LS1043A || ARCH_LS1046A || ARCH_B4860 || \
ARCH_B4420 || ARCH_P1010
default 8 if ARCH_LS2080A || ARCH_LS1088A || ARCH_LS1021A || \
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index bcdeef59fe7..fe1592d75aa 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -297,30 +297,6 @@ config ARCH_BSC9131
imply CMD_NAND
imply CMD_REGINFO
-config ARCH_BSC9132
- bool
- select FSL_LAW
- select SYS_FSL_DDR_VER_46
- select SYS_FSL_ERRATUM_A004477
- select SYS_FSL_ERRATUM_A005125
- select SYS_FSL_ERRATUM_A005434
- select SYS_FSL_ERRATUM_ESDHC111
- select SYS_FSL_ERRATUM_I2C_A004447
- select SYS_FSL_ERRATUM_IFC_A002769
- select FSL_PCIE_RESET
- select SYS_FSL_HAS_DDR3
- select SYS_FSL_HAS_SEC
- select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22
- select SYS_FSL_SEC_BE
- select SYS_FSL_SEC_COMPAT_4
- select SYS_PPC_E500_USE_DEBUG_TLB
- select FSL_IFC
- imply CMD_EEPROM
- imply CMD_MTDPARTS
- imply CMD_NAND
- imply CMD_PCI
- imply CMD_REGINFO
-
config ARCH_MPC8544
bool
select BTB
@@ -732,7 +708,6 @@ config MAX_CPUS
ARCH_T1042 || \
ARCH_T2080
default 2 if ARCH_B4420 || \
- ARCH_BSC9132 || \
ARCH_P1020 || \
ARCH_P1021 || \
ARCH_P1024 || \
@@ -749,7 +724,6 @@ config MAX_CPUS
config SYS_CCSRBAR_DEFAULT
hex "Default CCSRBAR address"
default 0xff700000 if ARCH_BSC9131 || \
- ARCH_BSC9132 || \
ARCH_MPC8544 || \
ARCH_P1010 || \
ARCH_P1020 || \
@@ -891,7 +865,7 @@ config SYS_FSL_A004447_SVR_REV
hex
depends on SYS_FSL_ERRATUM_I2C_A004447
default 0x10 if ARCH_P1010
- default 0x11 if ARCH_P2041 || ARCH_BSC9132
+ default 0x11 if ARCH_P2041
config SYS_FSL_ERRATUM_IFC_A002769
bool
@@ -956,7 +930,6 @@ config SYS_FSL_NUM_LAWS
ARCH_T1040 || \
ARCH_T1042
default 12 if ARCH_BSC9131 || \
- ARCH_BSC9132 || \
ARCH_P1010 || \
ARCH_P1020 || \
ARCH_P1021 || \
@@ -1071,8 +1044,7 @@ config SYS_PPC_E500_DEBUG_TLB
ARCH_P1021 || \
ARCH_P1024 || \
ARCH_P2020
- default 3 if ARCH_P1010 || \
- ARCH_BSC9132
+ default 3 if ARCH_P1010
help
Select a temporary TLB entry to be used during boot to work
around limitations in e500v1 and e500v2 external debugger
diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile
index 43a5b5b67a4..9b7c02eae5f 100644
--- a/arch/powerpc/cpu/mpc85xx/Makefile
+++ b/arch/powerpc/cpu/mpc85xx/Makefile
@@ -61,7 +61,6 @@ obj-$(CONFIG_ARCH_P2041) += p2041_serdes.o
obj-$(CONFIG_ARCH_T4240) += t4240_serdes.o
obj-$(CONFIG_ARCH_B4420) += b4860_serdes.o
obj-$(CONFIG_ARCH_B4860) += b4860_serdes.o
-obj-$(CONFIG_ARCH_BSC9132) += bsc9132_serdes.o
obj-$(CONFIG_ARCH_T1040) += t1040_serdes.o
obj-$(CONFIG_ARCH_T1042) += t1040_serdes.o
obj-$(CONFIG_ARCH_T1024) += t1024_serdes.o
diff --git a/arch/powerpc/cpu/mpc85xx/bsc9132_serdes.c b/arch/powerpc/cpu/mpc85xx/bsc9132_serdes.c
deleted file mode 100644
index 9ebb3d838fa..00000000000
--- a/arch/powerpc/cpu/mpc85xx/bsc9132_serdes.c
+++ /dev/null
@@ -1,101 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- * Author: Prabhakar Kushwaha <prabhakar@freescale.com>
- */
-
-#include <config.h>
-#include <log.h>
-#include <asm/io.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_serdes.h>
-
-#define SRDS1_MAX_LANES 4
-
-static u32 serdes1_prtcl_map;
-
-static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = {
- [0] = {NONE, NONE, NONE, NONE},
- [1] = {PCIE1, PCIE2, CPRI2, CPRI1},
- [2] = {PCIE1, PCIE2, CPRI2, CPRI1},
- [3] = {PCIE1, PCIE2, CPRI2, CPRI1},
- [4] = {PCIE1, PCIE2, CPRI2, CPRI1},
- [5] = {PCIE1, PCIE2, CPRI2, CPRI1},
- [6] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
- [7] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
- [8] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
- [9] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
- [10] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
- [11] = {PCIE1, PCIE2, SGMII_TSEC1, SGMII_TSEC2},
- [12] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
- [13] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
- [14] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
- [15] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
- [16] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
- [17] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
- [18] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
- [19] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
- [20] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
- [21] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
- [22] = {PCIE1, PCIE2, CPRI2, CPRI1},
- [23] = {PCIE1, PCIE2, CPRI2, CPRI1},
- [24] = {PCIE1, PCIE2, CPRI2, CPRI1},
- [25] = {PCIE1, PCIE2, CPRI2, CPRI1},
- [26] = {PCIE1, PCIE2, CPRI2, CPRI1},
- [27] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
- [28] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
- [29] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
- [30] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
- [31] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
- [32] = {PCIE1, PCIE2, SGMII_TSEC1, SGMII_TSEC2},
- [33] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
- [34] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
- [35] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
- [36] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
- [37] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
- [38] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
- [39] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
- [40] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
- [41] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
- [42] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
- [43] = {SGMII_TSEC1, SGMII_TSEC2, CPRI2, CPRI1},
- [44] = {SGMII_TSEC1, SGMII_TSEC2, CPRI2, CPRI1},
- [45] = {SGMII_TSEC1, SGMII_TSEC2, CPRI2, CPRI1},
- [46] = {SGMII_TSEC1, SGMII_TSEC2, CPRI2, CPRI1},
- [47] = {SGMII_TSEC1, SGMII_TSEC2, CPRI2, CPRI1},
-};
-
-int is_serdes_configured(enum srds_prtcl prtcl)
-{
- if (!(serdes1_prtcl_map & (1 << NONE)))
- fsl_serdes_init();
-
- return (1 << prtcl) & serdes1_prtcl_map;
-}
-
-void fsl_serdes_init(void)
-{
- ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
- u32 pordevsr = in_be32(&gur->pordevsr);
- u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
- MPC85xx_PORDEVSR_IO_SEL_SHIFT;
- int lane;
-
- if (serdes1_prtcl_map & (1 << NONE))
- return;
-
- debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
-
- if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) {
- printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
- return;
- }
-
- for (lane = 0; lane < SRDS1_MAX_LANES; lane++) {
- enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane];
- serdes1_prtcl_map |= (1 << lane_prtcl);
- }
-
- /* Set the first bit to indicate serdes has been initialized */
- serdes1_prtcl_map |= (1 << NONE);
-}
diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c
index 3594c1e3de2..046ab063700 100644
--- a/arch/powerpc/cpu/mpc8xxx/cpu.c
+++ b/arch/powerpc/cpu/mpc8xxx/cpu.c
@@ -79,7 +79,6 @@ static struct cpu_type cpu_type_list[] = {
CPU_TYPE_ENTRY(T2081, T2081, 0),
CPU_TYPE_ENTRY(BSC9130, 9130, 1),
CPU_TYPE_ENTRY(BSC9131, 9131, 1),
- CPU_TYPE_ENTRY(BSC9132, 9132, 2),
CPU_TYPE_ENTRY(BSC9232, 9232, 2),
CPU_TYPE_ENTRY(C291, C291, 1),
CPU_TYPE_ENTRY(C292, C292, 1),
diff --git a/arch/powerpc/include/asm/fsl_law.h b/arch/powerpc/include/asm/fsl_law.h
index d1cd7283971..bdef61bc80f 100644
--- a/arch/powerpc/include/asm/fsl_law.h
+++ b/arch/powerpc/include/asm/fsl_law.h
@@ -79,7 +79,7 @@ enum law_trgt_if {
LAW_TRGT_IF_PCI = 0x00,
LAW_TRGT_IF_PCI_2 = 0x01,
LAW_TRGT_IF_PCIE_1 = 0x02,
-#if defined(CONFIG_ARCH_BSC9131) || defined(CONFIG_ARCH_BSC9132)
+#if defined(CONFIG_ARCH_BSC9131)
LAW_TRGT_IF_OCN_DSP = 0x03,
#else
#if !defined(CONFIG_ARCH_P2020)
@@ -92,11 +92,7 @@ enum law_trgt_if {
LAW_TRGT_IF_PLATFORM_SRAM = 0x0a,
LAW_TRGT_IF_DDR_INTRLV = 0x0b,
LAW_TRGT_IF_RIO = 0x0c,
-#if defined(CONFIG_ARCH_BSC9132)
- LAW_TRGT_IF_CLASS_DSP = 0x0d,
-#else
LAW_TRGT_IF_RIO_2 = 0x0d,
-#endif
LAW_TRGT_IF_DPAA_SWP_SRAM = 0x0e,
LAW_TRGT_IF_DDR = 0x0f,
LAW_TRGT_IF_DDR_2 = 0x16, /* 2nd controller */
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index b646d24bc6b..e1167dbb3d7 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1726,7 +1726,7 @@ typedef struct ccsr_rcpm {
#else
typedef struct ccsr_gur {
u32 porpllsr; /* POR PLL ratio status */
-#if defined(CONFIG_ARCH_BSC9131) || defined(CONFIG_ARCH_BSC9132)
+#if defined(CONFIG_ARCH_BSC9131)
#define MPC85xx_PORPLLSR_DDR_RATIO 0x00003f00
#else
#define MPC85xx_PORPLLSR_DDR_RATIO 0x00003e00
@@ -1755,9 +1755,6 @@ typedef struct ccsr_gur {
#if defined(CONFIG_ARCH_P1010)
#define MPC85xx_PORDEVSR_IO_SEL 0x00600000
#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 21
-#elif defined(CONFIG_ARCH_BSC9132)
-#define MPC85xx_PORDEVSR_IO_SEL 0x00FE0000
-#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 17
#else
#define MPC85xx_PORDEVSR_IO_SEL 0x00780000
#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 19
@@ -1892,10 +1889,6 @@ typedef struct ccsr_gur {
#define MPC85xx_PMUXCR_SPI1_CS3_ANT_TCXO_PWM 0x00000001
#define MPC85xx_PMUXCR_SPI1_CS3_dbg_adi2_rxen 0x00000002
#define MPC85xx_PMUXCR_SPI1_CS3_GPO76 0x00000003
-#endif
-#ifdef CONFIG_ARCH_BSC9132
-#define MPC85xx_PMUXCR0_SIM_SEL_MASK 0x0003b000
-#define MPC85xx_PMUXCR0_SIM_SEL 0x00014000
#endif
u32 pmuxcr2; /* Alt. function signal multiplex control 2 */
#if defined(CONFIG_ARCH_P1010)
@@ -1923,7 +1916,6 @@ typedef struct ccsr_gur {
#define MPC85xx_PMUXCR2_DEBUG_MUX_SEL_USBPHY 0x00002000
#define MPC85xx_PMUXCR2_PLL_LKDT_EXPOSE 0x00001000
#endif
-#if defined(CONFIG_ARCH_BSC9131) || defined(CONFIG_ARCH_BSC9132)
#if defined(CONFIG_ARCH_BSC9131)
#define MPC85xx_PMUXCR2_UART_CTS_B0_SIM_PD 0x40000000
#define MPC85xx_PMUXCR2_UART_CTS_B0_DSP_TMS 0x80000000
@@ -1967,9 +1959,7 @@ typedef struct ccsr_gur {
#define MPC85xx_PMUXCR2_ANT3_AGC_GPO53 0x00000004
#define MPC85xx_PMUXCR2_ANT3_DO_TDM 0x00000001
#define MPC85xx_PMUXCR2_ANT3_DO_GPIO46_49 0x00000002
-#endif
u32 pmuxcr3;
-#if defined(CONFIG_ARCH_BSC9131)
#define MPC85xx_PMUXCR3_ANT3_DO4_5_TDM 0x40000000
#define MPC85xx_PMUXCR3_ANT3_DO4_5_GPIO_50_51 0x80000000
#define MPC85xx_PMUXCR3_ANT3_DO6_7_TRIG_IN_SRESET_B 0x10000000
@@ -1984,13 +1974,6 @@ typedef struct ccsr_gur {
#define MPC85xx_PMUXCR3_SPI2_CS3_GPO94 0x00040000
#define MPC85xx_PMUXCR3_ANT2_AGC_RSVD 0x00010000
#define MPC85xx_PMUXCR3_ANT2_GPO89 0x00030000
-#endif
-#ifdef CONFIG_ARCH_BSC9132
-#define MPC85xx_PMUXCR3_USB_SEL_MASK 0x0000ff00
-#define MPC85xx_PMUXCR3_UART2_SEL 0x00005000
-#define MPC85xx_PMUXCR3_UART3_SEL_MASK 0xc0000000
-#define MPC85xx_PMUXCR3_UART3_SEL 0x40000000
-#endif
u32 pmuxcr4;
#else
u8 res6[8];
diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h
index b78a726445d..01228bee20f 100644
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -1072,7 +1072,6 @@
#define SVR_9130 0x860001
#define SVR_9131 0x860000
-#define SVR_9132 0x861000
#define SVR_9232 0x861400
#define SVR_Unknown 0xFFFFFF
diff --git a/board/nxp/common/sdhc_boot.c b/board/nxp/common/sdhc_boot.c
index 0c2532a8595..16b6f0fc343 100644
--- a/board/nxp/common/sdhc_boot.c
+++ b/board/nxp/common/sdhc_boot.c
@@ -45,7 +45,7 @@ int mmc_get_env_addr(struct mmc *mmc, int copy, u64 *env_addr)
#ifdef CONFIG_ESDHC_HC_BLK_ADDR
/*
- * On soc BSC9131, BSC9132:
+ * On P1010 and BSC9131:
* In High Capacity SD Cards (> 2 GBytes), the 32-bit source address and
* code length of these soc specify the memory address in block address
* format. Block length is fixed to 512 bytes as per the SD High
diff --git a/boot/Kconfig b/boot/Kconfig
index 11b5036caad..0fc550c3e01 100644
--- a/boot/Kconfig
+++ b/boot/Kconfig
@@ -1199,7 +1199,7 @@ config FSL_FIXED_MMC_LOCATION
config ESDHC_HC_BLK_ADDR
def_bool y
- depends on FSL_FIXED_MMC_LOCATION && (ARCH_BSC9131 || ARCH_BSC9132 || ARCH_P1010)
+ depends on FSL_FIXED_MMC_LOCATION && (ARCH_BSC9131 || ARCH_P1010)
help
In High Capacity SD Cards (> 2 GBytes), the 32-bit source address and
code length of these soc specify the memory address in block address
diff --git a/drivers/ddr/fsl/Kconfig b/drivers/ddr/fsl/Kconfig
index 91b439428ab..7a3aa7e2087 100644
--- a/drivers/ddr/fsl/Kconfig
+++ b/drivers/ddr/fsl/Kconfig
@@ -51,7 +51,6 @@ config SYS_NUM_DDR_CTLRS
default 3 if ARCH_LS2080A || \
ARCH_T4240
default 2 if ARCH_B4860 || \
- ARCH_BSC9132 || \
ARCH_LX2160A || \
ARCH_LX2162A
default 1
diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index 4eb5d80e336..671cae7aaf2 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -911,7 +911,7 @@ config FSL_SDHC_V2_3
config FSL_ESDHC
bool "Freescale/NXP eSDHC controller support"
depends on ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3 || PPC
- select FSL_SDHC_V2_3 if ARCH_P1010 || ARCH_BSC9131 || ARCH_BSC9132
+ select FSL_SDHC_V2_3 if ARCH_P1010 || ARCH_BSC9131
help
This selects support for the eSDHC (Enhanced Secure Digital Host
Controller) found on numerous Freescale/NXP SoCs.
diff --git a/drivers/usb/common/fsl-errata.c b/drivers/usb/common/fsl-errata.c
index 1b84614c8f5..09dc905abe7 100644
--- a/drivers/usb/common/fsl-errata.c
+++ b/drivers/usb/common/fsl-errata.c
@@ -155,7 +155,6 @@ bool has_erratum_a005697(void)
switch (soc) {
#ifdef CONFIG_PPC
case SVR_9131:
- case SVR_9132:
return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 1, 1);
#endif
#ifdef ONFIG_ARM64
@@ -177,7 +176,6 @@ bool has_erratum_a004477(void)
return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0);
case SVR_P1022:
case SVR_9131:
- case SVR_9132:
return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 1, 1);
case SVR_P2020:
return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0) ||
--
2.47.3
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH 20/26] powerpc: mpc83xx: Remove MPC831x support
2026-10-09 19:36 [PATCH 00/26] powerpc: drop EOL boards and SoCs, take over maintenance Bradley Morgan
` (18 preceding siblings ...)
2026-10-09 19:36 ` [PATCH 19/26] powerpc: mpc85xx: Remove BSC9132 support Bradley Morgan
@ 2026-10-09 19:36 ` Bradley Morgan
2026-10-09 19:36 ` [PATCH 21/26] powerpc: mpc83xx: Remove MPC834x support Bradley Morgan
` (5 subsequent siblings)
25 siblings, 0 replies; 31+ messages in thread
From: Bradley Morgan @ 2026-10-09 19:36 UTC (permalink / raw)
To: Tom Rini, u-boot
Cc: Bradley Morgan, Marek Behún, Marek Mojík,
NXP i . MX U-Boot Team, Alexey Charkov, Anshul Dalal,
Daniel Golle, Fabio Estevam, Gaurav Jain, Ilias Apalodimas,
Jaehoon Chung, James Hilliard, Jerome Forissier, Johan Jonker,
Lukasz Majewski, Marek Vasut, Mario Six, Michael Walle,
Michal Simek, Neil Armstrong, Peng Fan, Pengpeng Hou,
Priyanka Jain, Quentin Schulz, Simon Glass, Stefano Babic,
Tanmay Kathpalia, Torsten Rupp, Vincent Jardin, Weijie Gao
NXP no longer manufactures the MPC8313 and lists the MPC8314 and MPC8315 as end of life. No target in the tree selects ARCH_MPC831X, so remove the orphaned family support and its register and device tree handling.
Signed-off-by: Bradley Morgan <brads@mainlining.org>
---
arch/Kconfig | 3 +-
arch/powerpc/cpu/mpc83xx/Kconfig | 13 ----
arch/powerpc/cpu/mpc83xx/cpu.c | 6 +-
arch/powerpc/cpu/mpc83xx/cpu_init.c | 14 +---
arch/powerpc/cpu/mpc83xx/fdt.c | 42 +----------
arch/powerpc/cpu/mpc83xx/hid/hid.h | 5 --
arch/powerpc/cpu/mpc83xx/hrcw/Kconfig | 38 +---------
arch/powerpc/cpu/mpc83xx/initreg/Kconfig.lcrr | 2 +-
arch/powerpc/cpu/mpc83xx/initreg/Kconfig.spcr | 2 +-
arch/powerpc/cpu/mpc83xx/spd_sdram.c | 2 +-
arch/powerpc/cpu/mpc83xx/speed.c | 27 +++----
arch/powerpc/include/asm/arch-mpc83xx/gpio.h | 2 +-
arch/powerpc/include/asm/arch-mpc83xx/soc.h | 20 +-----
arch/powerpc/include/asm/global_data.h | 4 +-
arch/powerpc/include/asm/immap_83xx.h | 35 ---------
arch/powerpc/include/asm/mpc8xxx_spi.h | 1 -
.../clock/fsl,mpc83xx-clk.txt | 2 -
doc/device-tree-bindings/cpu/fsl,mpc83xx.txt | 8 +--
drivers/clk/mpc83xx_clk.c | 8 +--
drivers/clk/mpc83xx_clk.h | 8 +--
drivers/cpu/mpc83xx_cpu.c | 17 -----
drivers/cpu/mpc83xx_cpu.h | 14 ----
drivers/ram/mpc83xx_sdram.c | 2 -
include/mpc83xx.h | 72 ++-----------------
24 files changed, 42 insertions(+), 305 deletions(-)
diff --git a/arch/Kconfig b/arch/Kconfig
index e806fa2e3e7..8ea591cba4f 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -467,8 +467,7 @@ config SYS_IMMR
hex "Address for the Internal Memory-Mapped Registers (IMMR) window"
depends on PPC || FSL_LSCH2 || FSL_LSCH3 || ARCH_LS1021A
default 0xFF000000 if MPC8xx
- default 0xF0000000 if ARCH_MPC8313
- default 0xE0000000 if MPC83xx && !ARCH_MPC8313
+ default 0xE0000000 if MPC83xx
default 0x01000000 if ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3
default 0xFFE00000 if ARCH_P1010 || ARCH_P1020 || \
ARCH_P1021 || ARCH_P1024 || \
diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig
index daae933e52e..06d84c2d945 100644
--- a/arch/powerpc/cpu/mpc83xx/Kconfig
+++ b/arch/powerpc/cpu/mpc83xx/Kconfig
@@ -125,19 +125,6 @@ config ARCH_MPC8308
select MPC83XX_PCIE1_SUPPORT
select MPC83XX_SECOND_I2C
-config ARCH_MPC831X
- bool
- select MPC83XX_PCI_SUPPORT
- select MPC83XX_TSEC1_SUPPORT
- select MPC83XX_TSEC2_SUPPORT
- select SYS_CACHE_SHIFT_5
-
-config ARCH_MPC8313
- bool
- select ARCH_MPC831X
- select MPC83XX_SECOND_I2C
- select FSL_ELBC
-
config ARCH_MPC832X
bool
select MPC83XX_QUICC_ENGINE
diff --git a/arch/powerpc/cpu/mpc83xx/cpu.c b/arch/powerpc/cpu/mpc83xx/cpu.c
index f8e9f716936..e1f70f40fec 100644
--- a/arch/powerpc/cpu/mpc83xx/cpu.c
+++ b/arch/powerpc/cpu/mpc83xx/cpu.c
@@ -24,7 +24,7 @@
#include <tsec.h>
#include <netdev.h>
#include <fsl_esdhc.h>
-#if defined(CONFIG_BOOTCOUNT_LIMIT) && !defined(CONFIG_ARCH_MPC831X)
+#if defined(CONFIG_BOOTCOUNT_LIMIT)
#include <linux/immap_qe.h>
#include <asm/io.h>
#endif
@@ -48,10 +48,6 @@ int checkcpu(void)
} cpu_type_list [] = {
CPU_TYPE_ENTRY(8308),
CPU_TYPE_ENTRY(8309),
- CPU_TYPE_ENTRY(8311),
- CPU_TYPE_ENTRY(8313),
- CPU_TYPE_ENTRY(8314),
- CPU_TYPE_ENTRY(8315),
CPU_TYPE_ENTRY(8321),
CPU_TYPE_ENTRY(8323),
CPU_TYPE_ENTRY(8343),
diff --git a/arch/powerpc/cpu/mpc83xx/cpu_init.c b/arch/powerpc/cpu/mpc83xx/cpu_init.c
index 340f9a0da56..555dd502b36 100644
--- a/arch/powerpc/cpu/mpc83xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc83xx/cpu_init.c
@@ -84,12 +84,6 @@ void cpu_init_f (volatile immap_t * im)
#ifdef CFG_SYS_SCCR_TSEC2CM /* TSEC2 clock mode */
SCCR_TSEC2CM |
#endif
-#ifdef CONFIG_SYS_SCCR_TSEC1ON /* TSEC1 clock switch */
- SCCR_TSEC1ON |
-#endif
-#ifdef CONFIG_SYS_SCCR_TSEC2ON /* TSEC2 clock switch */
- SCCR_TSEC2ON |
-#endif
#ifdef CONFIG_SYS_SCCR_USBMPHCM /* USB MPH clock mode */
SCCR_USBMPHCM |
#endif
@@ -122,12 +116,6 @@ void cpu_init_f (volatile immap_t * im)
#ifdef CFG_SYS_SCCR_TSEC2CM /* TSEC2 clock mode */
(CFG_SYS_SCCR_TSEC2CM << SCCR_TSEC2CM_SHIFT) |
#endif
-#ifdef CONFIG_SYS_SCCR_TSEC1ON /* TSEC1 clock switch */
- (CONFIG_SYS_SCCR_TSEC1ON << SCCR_TSEC1ON_SHIFT) |
-#endif
-#ifdef CONFIG_SYS_SCCR_TSEC2ON /* TSEC2 clock switch */
- (CONFIG_SYS_SCCR_TSEC2ON << SCCR_TSEC2ON_SHIFT) |
-#endif
#ifdef CONFIG_SYS_SCCR_USBMPHCM /* USB MPH clock mode */
(CONFIG_SYS_SCCR_USBMPHCM << SCCR_USBMPHCM_SHIFT) |
#endif
@@ -177,7 +165,7 @@ void cpu_init_f (volatile immap_t * im)
/* System General Purpose Register */
#ifdef CFG_SYS_SICRH
-#if defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC8313)
+#if defined(CONFIG_ARCH_MPC834X)
/* regarding to MPC34x manual rev.1 bits 28..29 must be preserved */
__raw_writel((im->sysconf.sicrh & 0x0000000C) | CFG_SYS_SICRH,
&im->sysconf.sicrh);
diff --git a/arch/powerpc/cpu/mpc83xx/fdt.c b/arch/powerpc/cpu/mpc83xx/fdt.c
index 1bd4f2b3449..08c3e783597 100644
--- a/arch/powerpc/cpu/mpc83xx/fdt.c
+++ b/arch/powerpc/cpu/mpc83xx/fdt.c
@@ -17,7 +17,7 @@ extern void ft_qe_setup(void *blob);
DECLARE_GLOBAL_DATA_PTR;
#if defined(CONFIG_BOOTCOUNT_LIMIT) && \
- (defined(CONFIG_QE) && !defined(CONFIG_ARCH_MPC831X))
+ defined(CONFIG_QE)
#include <linux/immap_qe.h>
void fdt_fixup_muram (void *blob)
@@ -50,44 +50,6 @@ void ft_cpu_setup(void *blob, struct bd_info *bd)
REVID_MAJOR(spridr) >= 2)
fdt_fixup_crypto_node(blob, 0x0204);
-#ifdef CONFIG_ARCH_MPC8313
- /*
- * mpc8313e erratum IPIC1 swapped TSEC interrupt ID numbers on rev. 1
- * h/w (see AN3545). The base device tree in use has rev. 1 ID numbers,
- * so if on Rev. 2 (and higher) h/w, we fix them up here
- */
- if (REVID_MAJOR(immr->sysconf.spridr) >= 2) {
- int nodeoffset, path;
- const char *prop;
-
- nodeoffset = fdt_path_offset(blob, "/aliases");
- if (nodeoffset >= 0) {
- prop = fdt_getprop(blob, nodeoffset, "ethernet0", NULL);
- if (prop) {
- u32 tmp[] = { 32, 0x8, 33, 0x8, 34, 0x8 };
-
- path = fdt_path_offset(blob, prop);
- prop = fdt_getprop(blob, path, "interrupts",
- NULL);
- if (prop)
- fdt_setprop(blob, path, "interrupts",
- &tmp, sizeof(tmp));
- }
- prop = fdt_getprop(blob, nodeoffset, "ethernet1", NULL);
- if (prop) {
- u32 tmp[] = { 35, 0x8, 36, 0x8, 37, 0x8 };
-
- path = fdt_path_offset(blob, prop);
- prop = fdt_getprop(blob, path, "interrupts",
- NULL);
- if (prop)
- fdt_setprop(blob, path, "interrupts",
- &tmp, sizeof(tmp));
- }
- }
- }
-#endif
-
do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
"timebase-frequency", (bd->bi_busfreq / 4), 1);
do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
@@ -116,7 +78,7 @@ void ft_cpu_setup(void *blob, struct bd_info *bd)
fdt_fixup_memory(blob, (u64)gd->ram_base, (u64)gd->ram_size);
#if defined(CONFIG_BOOTCOUNT_LIMIT) && \
- (defined(CONFIG_QE) && !defined(CONFIG_ARCH_MPC831X))
+ defined(CONFIG_QE)
fdt_fixup_muram (blob);
#endif
}
diff --git a/arch/powerpc/cpu/mpc83xx/hid/hid.h b/arch/powerpc/cpu/mpc83xx/hid/hid.h
index 089d1d77f0b..0ae528af878 100644
--- a/arch/powerpc/cpu/mpc83xx/hid/hid.h
+++ b/arch/powerpc/cpu/mpc83xx/hid/hid.h
@@ -48,12 +48,7 @@
CONFIG_HID0_INIT_SLEEP_BIT \
)
-#ifdef CONFIG_TARGET_IDS8313
-/* IDS8313 defines a reserved bit; keep to not break compatibility */
-#define CFG_HID2_SPECIAL 0x00020000
-#else
#define CFG_HID2_SPECIAL 0x0
-#endif
#define CFG_SYS_HID2 ( \
CONFIG_HID2_LET_BIT |\
diff --git a/arch/powerpc/cpu/mpc83xx/hrcw/Kconfig b/arch/powerpc/cpu/mpc83xx/hrcw/Kconfig
index 49d5db098f7..eef39021354 100644
--- a/arch/powerpc/cpu/mpc83xx/hrcw/Kconfig
+++ b/arch/powerpc/cpu/mpc83xx/hrcw/Kconfig
@@ -24,7 +24,7 @@ config DDR_MC_CLOCK_MODE_1_1
endchoice
-if !ARCH_MPC8313 && !ARCH_MPC832X
+if !ARCH_MPC832X
choice
prompt "System PLL VCO division"
@@ -36,11 +36,9 @@ config SYSTEM_PLL_VCO_DIV_2
bool "2"
config SYSTEM_PLL_VCO_DIV_4
- depends on !ARCH_MPC831X
bool "4"
config SYSTEM_PLL_VCO_DIV_8
- depends on !ARCH_MPC831X
bool "8"
endchoice
@@ -418,21 +416,9 @@ choice
config TSEC1_MODE_MII
bool "MII"
-config TSEC1_MODE_RMII
- depends on ARCH_MPC831X
- bool "RMII"
-
config TSEC1_MODE_RGMII
bool "RGMII"
-config TSEC1_MODE_RTBI
- depends on ARCH_MPC831X
- bool "RTBI"
-
-config TSEC1_MODE_SGMII
- depends on ARCH_MPC831X
- bool "SGMII"
-
endchoice
endif
@@ -445,21 +431,9 @@ choice
config TSEC2_MODE_MII
bool "MII"
-config TSEC2_MODE_RMII
- depends on ARCH_MPC831X
- bool "RMII"
-
config TSEC2_MODE_RGMII
bool "RGMII"
-config TSEC2_MODE_RTBI
- depends on ARCH_MPC831X
- bool "RTBI"
-
-config TSEC2_MODE_SGMII
- depends on ARCH_MPC831X
- bool "SGMII"
-
endchoice
endif
@@ -490,7 +464,7 @@ endchoice
endif
-if ARCH_MPC831X || ARCH_MPC832X || ARCH_MPC8360
+if ARCH_MPC832X || ARCH_MPC8360
choice
prompt "LALE timing"
@@ -534,7 +508,7 @@ config DDR_MC_CLOCK_MODE
config SYSTEM_PLL_VCO_DIV
int
- default 2 if ARCH_MPC8313 || ARCH_MPC832X
+ default 2 if ARCH_MPC832X
default 0 if SYSTEM_PLL_VCO_DIV_2 && !ARCH_MPC8360
default 1 if SYSTEM_PLL_VCO_DIV_4 && !ARCH_MPC8360
default 2 if SYSTEM_PLL_VCO_DIV_8 && !ARCH_MPC8360
@@ -615,19 +589,13 @@ config TSEC1_MODE
hex
default 0x0 if !MPC83XX_TSEC1_SUPPORT
default 0x0 if TSEC1_MODE_MII
- default 0x1 if TSEC1_MODE_RMII
default 0x3 if TSEC1_MODE_RGMII
- default 0x5 if TSEC1_MODE_RTBI
- default 0x6 if TSEC1_MODE_SGMII
config TSEC2_MODE
hex
default 0x0 if !MPC83XX_TSEC2_SUPPORT
default 0x0 if TSEC2_MODE_MII
- default 0x1 if TSEC2_MODE_RMII
default 0x3 if TSEC2_MODE_RGMII
- default 0x5 if TSEC2_MODE_RTBI
- default 0x6 if TSEC2_MODE_SGMII
config SECONDARY_DDR_IO
int
diff --git a/arch/powerpc/cpu/mpc83xx/initreg/Kconfig.lcrr b/arch/powerpc/cpu/mpc83xx/initreg/Kconfig.lcrr
index 86c5f42dd37..a85e698a867 100644
--- a/arch/powerpc/cpu/mpc83xx/initreg/Kconfig.lcrr
+++ b/arch/powerpc/cpu/mpc83xx/initreg/Kconfig.lcrr
@@ -1,6 +1,6 @@
menu "LCRR - Clock Ratio Register register"
-if !ARCH_MPC831X && !ARCH_MPC832X
+if !ARCH_MPC832X
choice
prompt "DLL bypass"
diff --git a/arch/powerpc/cpu/mpc83xx/initreg/Kconfig.spcr b/arch/powerpc/cpu/mpc83xx/initreg/Kconfig.spcr
index 91686b3b8b4..7bf7bda09e0 100644
--- a/arch/powerpc/cpu/mpc83xx/initreg/Kconfig.spcr
+++ b/arch/powerpc/cpu/mpc83xx/initreg/Kconfig.spcr
@@ -14,7 +14,7 @@ config SPCR_OPT_SPEC_READ
endchoice
-if ARCH_MPC8308 || ARCH_MPC831X
+if ARCH_MPC8308
choice
prompt "TSEC emergency priority"
diff --git a/arch/powerpc/cpu/mpc83xx/spd_sdram.c b/arch/powerpc/cpu/mpc83xx/spd_sdram.c
index e847c03f378..949efc8e828 100644
--- a/arch/powerpc/cpu/mpc83xx/spd_sdram.c
+++ b/arch/powerpc/cpu/mpc83xx/spd_sdram.c
@@ -37,7 +37,7 @@ void board_add_ram_info(int use_default)
printf(" (DDR%d", ((ddr->sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK)
>> SDRAM_CFG_SDRAM_TYPE_SHIFT) - 1);
-#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X)
+#if defined(CONFIG_ARCH_MPC8308)
if ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK) == SDRAM_CFG_DBW_16)
puts(", 16-bit");
else if ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK) == SDRAM_CFG_DBW_32)
diff --git a/arch/powerpc/cpu/mpc83xx/speed.c b/arch/powerpc/cpu/mpc83xx/speed.c
index a2343c67f28..e2ed3caf022 100644
--- a/arch/powerpc/cpu/mpc83xx/speed.c
+++ b/arch/powerpc/cpu/mpc83xx/speed.c
@@ -87,7 +87,7 @@ int get_clocks(void)
u32 lcrr;
u32 csb_clk;
-#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
+#if defined(CONFIG_ARCH_MPC8308) || \
defined(CONFIG_ARCH_MPC834X)
u32 tsec1_clk;
u32 tsec2_clk;
@@ -117,7 +117,7 @@ int get_clocks(void)
u32 qe_clk;
u32 brg_clk;
#endif
-#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X)
+#if defined(CONFIG_ARCH_MPC8308)
u32 pciexp1_clk;
u32 pciexp2_clk;
#endif
@@ -146,7 +146,7 @@ int get_clocks(void)
sccr = im->clk.sccr;
-#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
+#if defined(CONFIG_ARCH_MPC8308) || \
defined(CONFIG_ARCH_MPC834X)
switch ((sccr & SCCR_TSEC1CM) >> SCCR_TSEC1CM_SHIFT) {
case 0:
@@ -167,7 +167,7 @@ int get_clocks(void)
}
#endif
-#if defined(CONFIG_ARCH_MPC830X) || defined(CONFIG_ARCH_MPC831X) || \
+#if defined(CONFIG_ARCH_MPC830X) || \
defined(CONFIG_ARCH_MPC834X)
switch ((sccr & SCCR_USBDRCM) >> SCCR_USBDRCM_SHIFT) {
case 0:
@@ -206,13 +206,6 @@ int get_clocks(void)
/* unknown SCCR_TSEC2CM value */
return -4;
}
-#elif defined(CONFIG_ARCH_MPC8313)
- tsec2_clk = tsec1_clk;
-
- if (!(sccr & SCCR_TSEC1ON))
- tsec1_clk = 0;
- if (!(sccr & SCCR_TSEC2ON))
- tsec2_clk = 0;
#endif
#if defined(CONFIG_ARCH_MPC834X)
@@ -286,7 +279,7 @@ int get_clocks(void)
i2c1_clk = csb_clk;
#elif defined(CONFIG_ARCH_MPC832X)
i2c1_clk = enc_clk;
-#elif defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X)
+#elif defined(CONFIG_ARCH_MPC8308)
i2c1_clk = enc_clk;
#elif defined(CONFIG_FSL_ESDHC)
i2c1_clk = sdhc_clk;
@@ -295,7 +288,7 @@ int get_clocks(void)
i2c2_clk = csb_clk; /* i2c-2 clk is equal to csb clk */
#endif
-#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X)
+#if defined(CONFIG_ARCH_MPC8308)
switch ((sccr & SCCR_PCIEXP1CM) >> SCCR_PCIEXP1CM_SHIFT) {
case 0:
pciexp1_clk = 0;
@@ -392,7 +385,7 @@ int get_clocks(void)
#endif
gd->arch.csb_clk = csb_clk;
-#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
+#if defined(CONFIG_ARCH_MPC8308) || \
defined(CONFIG_ARCH_MPC834X)
gd->arch.tsec1_clk = tsec1_clk;
gd->arch.tsec2_clk = tsec2_clk;
@@ -420,7 +413,7 @@ int get_clocks(void)
gd->arch.qe_clk = qe_clk;
gd->arch.brg_clk = brg_clk;
#endif
-#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X)
+#if defined(CONFIG_ARCH_MPC8308)
gd->arch.pciexp1_clk = pciexp1_clk;
gd->arch.pciexp2_clk = pciexp2_clk;
#endif
@@ -491,7 +484,7 @@ static int do_clocks(struct cmd_tbl *cmdtp, int flag, int argc,
printf(" SDHC: %-4s MHz\n",
strmhz(buf, gd->arch.sdhc_clk));
#endif
-#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
+#if defined(CONFIG_ARCH_MPC8308) || \
defined(CONFIG_ARCH_MPC834X)
printf(" TSEC1: %-4s MHz\n",
strmhz(buf, gd->arch.tsec1_clk));
@@ -504,7 +497,7 @@ static int do_clocks(struct cmd_tbl *cmdtp, int flag, int argc,
printf(" USB MPH: %-4s MHz\n",
strmhz(buf, gd->arch.usbmph_clk));
#endif
-#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X)
+#if defined(CONFIG_ARCH_MPC8308)
printf(" PCIEXP1: %-4s MHz\n",
strmhz(buf, gd->arch.pciexp1_clk));
printf(" PCIEXP2: %-4s MHz\n",
diff --git a/arch/powerpc/include/asm/arch-mpc83xx/gpio.h b/arch/powerpc/include/asm/arch-mpc83xx/gpio.h
index dd368af7b91..6449fded125 100644
--- a/arch/powerpc/include/asm/arch-mpc83xx/gpio.h
+++ b/arch/powerpc/include/asm/arch-mpc83xx/gpio.h
@@ -6,7 +6,7 @@
/*
* The MCP83xx's 1-2 GPIO controllers each with 32 bits.
*/
-#if defined(CONFIG_ARCH_MPC8313) || defined(CONFIG_ARCH_MPC8308)
+#if defined(CONFIG_ARCH_MPC8308)
#define MPC83XX_GPIO_CTRLRS 1
#elif defined(CONFIG_ARCH_MPC834X)
#define MPC83XX_GPIO_CTRLRS 2
diff --git a/arch/powerpc/include/asm/arch-mpc83xx/soc.h b/arch/powerpc/include/asm/arch-mpc83xx/soc.h
index d61d3a944f1..0eeaa23b190 100644
--- a/arch/powerpc/include/asm/arch-mpc83xx/soc.h
+++ b/arch/powerpc/include/asm/arch-mpc83xx/soc.h
@@ -10,8 +10,6 @@
enum soc_type {
SOC_MPC8308,
SOC_MPC8309,
- SOC_MPC8313,
- SOC_MPC8315,
SOC_MPC832X,
SOC_MPC8349,
SOC_MPC8360,
@@ -26,25 +24,12 @@ static inline bool mpc83xx_has_sdhc(int type)
static inline bool mpc83xx_has_tsec(int type)
{
return (type == SOC_MPC8308) ||
- (type == SOC_MPC8313) ||
- (type == SOC_MPC8315) ||
(type == SOC_MPC8349);
}
static inline bool mpc83xx_has_pcie1(int type)
{
- return (type == SOC_MPC8308) ||
- (type == SOC_MPC8315);
-}
-
-static inline bool mpc83xx_has_pcie2(int type)
-{
- return type == SOC_MPC8315;
-}
-
-static inline bool mpc83xx_has_sata(int type)
-{
- return type == SOC_MPC8315;
+ return type == SOC_MPC8308;
}
static inline bool mpc83xx_has_pci(int type)
@@ -54,8 +39,7 @@ static inline bool mpc83xx_has_pci(int type)
static inline bool mpc83xx_has_second_i2c(int type)
{
- return (type != SOC_MPC8315) &&
- (type != SOC_MPC832X);
+ return type != SOC_MPC832X;
}
static inline bool mpc83xx_has_quicc_engine(int type)
diff --git a/arch/powerpc/include/asm/global_data.h b/arch/powerpc/include/asm/global_data.h
index 608e49667af..168eb55b497 100644
--- a/arch/powerpc/include/asm/global_data.h
+++ b/arch/powerpc/include/asm/global_data.h
@@ -26,7 +26,7 @@ struct arch_global_data {
#else
/* There are other clocks in the MPC83XX */
u32 csb_clk;
-# if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
+# if defined(CONFIG_ARCH_MPC8308) || \
defined(CONFIG_ARCH_MPC834X)
u32 tsec1_clk;
u32 tsec2_clk;
@@ -39,7 +39,7 @@ struct arch_global_data {
u32 enc_clk;
u32 lbiu_clk;
u32 lclk_clk;
-# if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X)
+# if defined(CONFIG_ARCH_MPC8308)
u32 pciexp1_clk;
u32 pciexp2_clk;
# endif
diff --git a/arch/powerpc/include/asm/immap_83xx.h b/arch/powerpc/include/asm/immap_83xx.h
index 2eff504a80d..c7e7616529d 100644
--- a/arch/powerpc/include/asm/immap_83xx.h
+++ b/arch/powerpc/include/asm/immap_83xx.h
@@ -688,41 +688,6 @@ typedef struct immap {
u8 res7[0xC0000];
} immap_t;
-#elif defined(CONFIG_ARCH_MPC8313)
-typedef struct immap {
- sysconf83xx_t sysconf; /* System configuration */
- wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
- rtclk83xx_t rtc; /* Real Time Clock Module Registers */
- rtclk83xx_t pit; /* Periodic Interval Timer */
- gtm83xx_t gtm[2]; /* Global Timers Module */
- ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
- arbiter83xx_t arbiter; /* System Arbiter Registers */
- reset83xx_t reset; /* Reset Module */
- clk83xx_t clk; /* System Clock Module */
- pmc83xx_t pmc; /* Power Management Control Module */
- gpio83xx_t gpio[1]; /* General purpose I/O module */
- u8 res0[0x1300];
- ddr83xx_t ddr; /* DDR Memory Controller Memory */
- fsl_i2c_t i2c[2]; /* I2C Controllers */
- u8 res1[0x1300];
- duart83xx_t duart[2]; /* DUART */
- u8 res2[0x900];
- fsl_lbc_t im_lbc; /* Local Bus Controller Regs */
- u8 res3[0x1000];
- spi8xxx_t spi; /* Serial Peripheral Interface */
- dma83xx_t dma; /* DMA */
- pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */
- u8 res4[0x80];
- ios83xx_t ios; /* Sequencer */
- pcictrl83xx_t pci_ctrl[1]; /* PCI Controller Control and Status Registers */
- u8 res5[0x1aa00];
- usb83xx_t usb[1];
- tsec83xx_t tsec[2];
- u8 res6[0xA000];
- security83xx_t security;
- u8 res7[0xC0000];
-} immap_t;
-
#elif defined(CONFIG_ARCH_MPC8308)
typedef struct immap {
sysconf83xx_t sysconf; /* System configuration */
diff --git a/arch/powerpc/include/asm/mpc8xxx_spi.h b/arch/powerpc/include/asm/mpc8xxx_spi.h
index c136b3fb4af..5d8d7db2933 100644
--- a/arch/powerpc/include/asm/mpc8xxx_spi.h
+++ b/arch/powerpc/include/asm/mpc8xxx_spi.h
@@ -11,7 +11,6 @@
#include <asm/types.h>
#if defined(CONFIG_ARCH_MPC8308) || \
- defined(CONFIG_ARCH_MPC8313) || \
defined(CONFIG_ARCH_MPC832X) || \
defined(CONFIG_ARCH_MPC834X)
diff --git a/doc/device-tree-bindings/clock/fsl,mpc83xx-clk.txt b/doc/device-tree-bindings/clock/fsl,mpc83xx-clk.txt
index 065575d87f0..baaacb62846 100644
--- a/doc/device-tree-bindings/clock/fsl,mpc83xx-clk.txt
+++ b/doc/device-tree-bindings/clock/fsl,mpc83xx-clk.txt
@@ -6,8 +6,6 @@ system.
Required properties:
- compatible: must be one of "fsl,mpc8308-clk",
"fsl,mpc8309-clk",
- "fsl,mpc8313-clk",
- "fsl,mpc8315-clk",
"fsl,mpc832x-clk",
"fsl,mpc8349-clk",
"fsl,mpc8360-clk"
diff --git a/doc/device-tree-bindings/cpu/fsl,mpc83xx.txt b/doc/device-tree-bindings/cpu/fsl,mpc83xx.txt
index efdcdfbdba0..5bdbd309fbf 100644
--- a/doc/device-tree-bindings/cpu/fsl,mpc83xx.txt
+++ b/doc/device-tree-bindings/cpu/fsl,mpc83xx.txt
@@ -6,8 +6,6 @@ Required properties:
- compatible: must be one of "fsl,mpc83xx",
"fsl,mpc8308",
"fsl,mpc8309",
- "fsl,mpc8313",
- "fsl,mpc8315",
"fsl,mpc832x",
"fsl,mpc8349",
"fsl,mpc8360"
@@ -18,15 +16,15 @@ Required properties:
Example:
socclocks: clocks {
- compatible = "fsl,mpc8315-clk";
+ compatible = "fsl,mpc832x-clk";
#clock-cells = <1>;
};
cpus {
compatible = "cpu_bus";
- PowerPC,8315@0 {
- compatible = "fsl,mpc8315";
+ PowerPC,8321@0 {
+ compatible = "fsl,mpc832x";
clocks = <&socclocks MPC83XX_CLK_CORE
&socclocks MPC83XX_CLK_CSB>;
};
diff --git a/drivers/clk/mpc83xx_clk.c b/drivers/clk/mpc83xx_clk.c
index 20f77a983da..bca09f17d5f 100644
--- a/drivers/clk/mpc83xx_clk.c
+++ b/drivers/clk/mpc83xx_clk.c
@@ -51,7 +51,7 @@ static inline bool is_clk_valid(struct udevice *clk, int id)
case MPC83XX_CLK_I2C1:
return true;
case MPC83XX_CLK_TDM:
- return type == SOC_MPC8315;
+ return false;
case MPC83XX_CLK_SDHC:
return mpc83xx_has_sdhc(type);
case MPC83XX_CLK_TSEC1:
@@ -64,9 +64,9 @@ static inline bool is_clk_valid(struct udevice *clk, int id)
case MPC83XX_CLK_PCIEXP1:
return mpc83xx_has_pcie1(type);
case MPC83XX_CLK_PCIEXP2:
- return mpc83xx_has_pcie2(type);
+ return false;
case MPC83XX_CLK_SATA:
- return mpc83xx_has_sata(type);
+ return false;
case MPC83XX_CLK_DMAC:
return (type == SOC_MPC8308) || (type == SOC_MPC8309);
case MPC83XX_CLK_PCI:
@@ -321,8 +321,6 @@ const struct clk_ops mpc83xx_clk_ops = {
static const struct udevice_id mpc83xx_clk_match[] = {
{ .compatible = "fsl,mpc8308-clk", .data = SOC_MPC8308 },
{ .compatible = "fsl,mpc8309-clk", .data = SOC_MPC8309 },
- { .compatible = "fsl,mpc8313-clk", .data = SOC_MPC8313 },
- { .compatible = "fsl,mpc8315-clk", .data = SOC_MPC8315 },
{ .compatible = "fsl,mpc832x-clk", .data = SOC_MPC832X },
{ .compatible = "fsl,mpc8349-clk", .data = SOC_MPC8349 },
{ .compatible = "fsl,mpc8360-clk", .data = SOC_MPC8360 },
diff --git a/drivers/clk/mpc83xx_clk.h b/drivers/clk/mpc83xx_clk.h
index b9486a4c202..ce3683f3932 100644
--- a/drivers/clk/mpc83xx_clk.h
+++ b/drivers/clk/mpc83xx_clk.h
@@ -204,10 +204,8 @@ static int retrieve_mode(int clk, int soc_type, struct clk_mode *mode)
set_mode(mode, 0, 1, TYPE_SCCR_STANDARD);
break;
case MPC83XX_CLK_TSEC2:
- if (soc_type == SOC_MPC8313) /* I2C and TSEC2 are the same register */
- set_mode(mode, 2, 3, TYPE_SCCR_STANDARD);
- else /* FIXME(mario.six@gdsys.cc): This has separate enable/disable bit! */
- set_mode(mode, 0, 1, TYPE_SCCR_STANDARD);
+ /* FIXME(mario.six@gdsys.cc): This has separate enable/disable bit! */
+ set_mode(mode, 0, 1, TYPE_SCCR_STANDARD);
break;
case MPC83XX_CLK_SDHC:
set_mode(mode, 4, 5, TYPE_SCCR_STANDARD);
@@ -228,7 +226,7 @@ static int retrieve_mode(int clk, int soc_type, struct clk_mode *mode)
set_mode(mode, 12, 13, TYPE_SCCR_STANDARD);
break;
case MPC83XX_CLK_USBDR:
- if (soc_type == SOC_MPC8313 || soc_type == SOC_MPC8349)
+ if (soc_type == SOC_MPC8349)
set_mode(mode, 10, 11, TYPE_SCCR_STANDARD);
else
set_mode(mode, 8, 9, TYPE_SCCR_STANDARD);
diff --git a/drivers/cpu/mpc83xx_cpu.c b/drivers/cpu/mpc83xx_cpu.c
index 780b08f0885..01ac307c821 100644
--- a/drivers/cpu/mpc83xx_cpu.c
+++ b/drivers/cpu/mpc83xx_cpu.c
@@ -70,9 +70,6 @@ static inline void determine_family(const struct udevice *dev)
case 0x811:
priv->family = FAMILY_830X;
break;
- case 0x80B:
- priv->family = FAMILY_831X;
- break;
case 0x806:
priv->family = FAMILY_832X;
break;
@@ -108,18 +105,6 @@ static inline void determine_type(const struct udevice *dev)
case 0x8110:
priv->type = TYPE_8309;
break;
- case 0x80B2:
- priv->type = TYPE_8311;
- break;
- case 0x80B0:
- priv->type = TYPE_8313;
- break;
- case 0x80B6:
- priv->type = TYPE_8314;
- break;
- case 0x80B4:
- priv->type = TYPE_8315;
- break;
case 0x8066:
priv->type = TYPE_8321;
break;
@@ -321,8 +306,6 @@ static const struct udevice_id mpc83xx_cpu_ids[] = {
{ .compatible = "fsl,mpc83xx", },
{ .compatible = "fsl,mpc8308", },
{ .compatible = "fsl,mpc8309", },
- { .compatible = "fsl,mpc8313", },
- { .compatible = "fsl,mpc8315", },
{ .compatible = "fsl,mpc832x", },
{ .compatible = "fsl,mpc8349", },
{ .compatible = "fsl,mpc8360", },
diff --git a/drivers/cpu/mpc83xx_cpu.h b/drivers/cpu/mpc83xx_cpu.h
index 20579cecf5e..d9773d893f1 100644
--- a/drivers/cpu/mpc83xx_cpu.h
+++ b/drivers/cpu/mpc83xx_cpu.h
@@ -35,7 +35,6 @@ static const char * const e300_names[] = {
/**
* enum mpc83xx_cpu_family - Identifiers for MPC83xx CPU families
* @FAMILY_830X: Identifier for the MPC830x CPU family
- * @FAMILY_831X: Identifier for the MPC831x CPU family
* @FAMILY_832X: Identifier for the MPC832x CPU family
* @FAMILY_834X: Identifier for the MPC834x CPU family
* @FAMILY_836X: Identifier for the MPC836x CPU family
@@ -43,7 +42,6 @@ static const char * const e300_names[] = {
*/
enum mpc83xx_cpu_family {
FAMILY_830X,
- FAMILY_831X,
FAMILY_832X,
FAMILY_834X,
FAMILY_836X,
@@ -54,10 +52,6 @@ enum mpc83xx_cpu_family {
* enum mpc83xx_cpu_type - Identifiers for MPC83xx CPU types
* @TYPE_8308: Identifier for the MPC8308 CPU type
* @TYPE_8309: Identifier for the MPC8309 CPU type
- * @TYPE_8311: Identifier for the MPC8311 CPU type
- * @TYPE_8313: Identifier for the MPC8313 CPU type
- * @TYPE_8314: Identifier for the MPC8314 CPU type
- * @TYPE_8315: Identifier for the MPC8315 CPU type
* @TYPE_8321: Identifier for the MPC8321 CPU type
* @TYPE_8323: Identifier for the MPC8323 CPU type
* @TYPE_8343: Identifier for the MPC8343 CPU type
@@ -76,10 +70,6 @@ enum mpc83xx_cpu_family {
enum mpc83xx_cpu_type {
TYPE_8308,
TYPE_8309,
- TYPE_8311,
- TYPE_8313,
- TYPE_8314,
- TYPE_8315,
TYPE_8321,
TYPE_8323,
TYPE_8343,
@@ -96,10 +86,6 @@ enum mpc83xx_cpu_type {
static const char * const cpu_type_names[] = {
[TYPE_8308] = "8308",
[TYPE_8309] = "8309",
- [TYPE_8311] = "8311",
- [TYPE_8313] = "8313",
- [TYPE_8314] = "8314",
- [TYPE_8315] = "8315",
[TYPE_8321] = "8321",
[TYPE_8323] = "8323",
[TYPE_8343] = "8343",
diff --git a/drivers/ram/mpc83xx_sdram.c b/drivers/ram/mpc83xx_sdram.c
index d45c4e6264e..888fec949df 100644
--- a/drivers/ram/mpc83xx_sdram.c
+++ b/drivers/ram/mpc83xx_sdram.c
@@ -177,7 +177,6 @@ static int mpc83xx_sdram_static_init(ofnode node, u32 cs, u32 mapaddr, u32 size)
case ODT_RD_ONLY_CURRENT:
case ODT_RD_ONLY_OTHER_CS:
if (!IS_ENABLED(CONFIG_ARCH_MPC830X) &&
- !IS_ENABLED(CONFIG_ARCH_MPC831X) &&
!IS_ENABLED(CONFIG_ARCH_MPC8360)) {
debug("%s: odt_rd_cfg value %d invalid.\n",
ofnode_get_name(node), odt_rd_cfg);
@@ -206,7 +205,6 @@ static int mpc83xx_sdram_static_init(ofnode node, u32 cs, u32 mapaddr, u32 size)
case ODT_WR_ONLY_CURRENT:
case ODT_WR_ONLY_OTHER_CS:
if (!IS_ENABLED(CONFIG_ARCH_MPC830X) &&
- !IS_ENABLED(CONFIG_ARCH_MPC831X) &&
!IS_ENABLED(CONFIG_ARCH_MPC8360)) {
debug("%s: odt_wr_cfg value %d invalid.\n",
ofnode_get_name(node), odt_wr_cfg);
diff --git a/include/mpc83xx.h b/include/mpc83xx.h
index b8d2c3edd56..8a1a9e7a9b9 100644
--- a/include/mpc83xx.h
+++ b/include/mpc83xx.h
@@ -57,11 +57,6 @@
#define SPR_8308 0x8100
#define SPR_8309 0x8110
-#define SPR_831X_FAMILY 0x80B
-#define SPR_8311 0x80B2
-#define SPR_8313 0x80B0
-#define SPR_8314 0x80B6
-#define SPR_8315 0x80B4
#define SPR_832X_FAMILY 0x806
#define SPR_8321 0x8066
#define SPR_8323 0x8062
@@ -113,8 +108,8 @@
#define SPCR_TSEC2EP 0x00000003
#define SPCR_TSEC2EP_SHIFT (31-31)
-#elif defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X)
-/* SPCR bits - MPC8308 and MPC831x specific */
+#elif defined(CONFIG_ARCH_MPC8308)
+/* SPCR bits - MPC8308 specific */
/* TSEC data priority */
#define SPCR_TSECDP 0x00003000
#define SPCR_TSECDP_SHIFT (31-19)
@@ -199,38 +194,6 @@
#define SICRL_URT_CTPR 0x06000000
#define SICRL_IRQ_CTPR 0x00C00000
-#elif defined(CONFIG_ARCH_MPC8313)
-/* SICRL bits - MPC8313 specific */
-#define SICRL_LBC 0x30000000
-#define SICRL_UART 0x0C000000
-#define SICRL_SPI_A 0x03000000
-#define SICRL_SPI_B 0x00C00000
-#define SICRL_SPI_C 0x00300000
-#define SICRL_SPI_D 0x000C0000
-#define SICRL_USBDR_11 0x00000C00
-#define SICRL_USBDR_10 0x00000800
-#define SICRL_USBDR_01 0x00000400
-#define SICRL_USBDR_00 0x00000000
-#define SICRL_ETSEC1_A 0x0000000C
-#define SICRL_ETSEC2_A 0x00000003
-
-/* SICRH bits - MPC8313 specific */
-#define SICRH_INTR_A 0x02000000
-#define SICRH_INTR_B 0x00C00000
-#define SICRH_IIC 0x00300000
-#define SICRH_ETSEC2_B 0x000C0000
-#define SICRH_ETSEC2_C 0x00030000
-#define SICRH_ETSEC2_D 0x0000C000
-#define SICRH_ETSEC2_E 0x00003000
-#define SICRH_ETSEC2_F 0x00000C00
-#define SICRH_ETSEC2_G 0x00000300
-#define SICRH_ETSEC1_B 0x00000080
-#define SICRH_ETSEC1_C 0x00000060
-#define SICRH_GTX1_DLY 0x00000008
-#define SICRH_GTX2_DLY 0x00000004
-#define SICRH_TSOBI1 0x00000002
-#define SICRH_TSOBI2 0x00000001
-
#elif defined(CONFIG_ARCH_MPC8308)
/* SICRL bits - MPC8308 specific */
#define SICRL_SPI_PF0 (0 << 28)
@@ -514,7 +477,7 @@
#define HRCWH_ROM_LOC_LOCAL_16BIT 0x00600000
#define HRCWH_ROM_LOC_LOCAL_32BIT 0x00700000
-#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X)
+#if defined(CONFIG_ARCH_MPC8308)
#define HRCWH_ROM_LOC_NAND_SP_8BIT 0x00100000
#define HRCWH_ROM_LOC_NAND_SP_16BIT 0x00200000
#define HRCWH_ROM_LOC_NAND_LP_8BIT 0x00500000
@@ -566,7 +529,7 @@
/*
* RSR - Reset Status Register
*/
-#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X)
+#if defined(CONFIG_ARCH_MPC8308)
#define RSR_RSTSRC 0xF0000000 /* Reset source */
#define RSR_RSTSRC_SHIFT 28
#else
@@ -712,29 +675,8 @@
#define SCCR_USBCM_2 0x00A00000
#define SCCR_USBCM_3 0x00F00000
-#elif defined(CONFIG_ARCH_MPC8313)
-/* TSEC1 bits are for TSEC2 as well */
-#define SCCR_TSEC1CM 0xc0000000
-#define SCCR_TSEC1CM_SHIFT 30
-#define SCCR_TSEC1CM_0 0x00000000
-#define SCCR_TSEC1CM_1 0x40000000
-#define SCCR_TSEC1CM_2 0x80000000
-#define SCCR_TSEC1CM_3 0xC0000000
-
-#define SCCR_TSEC1ON 0x20000000
-#define SCCR_TSEC1ON_SHIFT 29
-#define SCCR_TSEC2ON 0x10000000
-#define SCCR_TSEC2ON_SHIFT 28
-
-#define SCCR_USBDRCM 0x00300000
-#define SCCR_USBDRCM_SHIFT 20
-#define SCCR_USBDRCM_0 0x00000000
-#define SCCR_USBDRCM_1 0x00100000
-#define SCCR_USBDRCM_2 0x00200000
-#define SCCR_USBDRCM_3 0x00300000
-
#elif defined(CONFIG_ARCH_MPC8308)
-/* SCCR bits - MPC8315/MPC8308 specific */
+/* SCCR bits - MPC8308 specific */
#define SCCR_TSEC1CM 0xc0000000
#define SCCR_TSEC1CM_SHIFT 30
#define SCCR_TSEC1CM_0 0x00000000
@@ -810,7 +752,7 @@
*/
#define CSCONFIG_EN 0x80000000
#define CSCONFIG_AP 0x00800000
-#if defined(CONFIG_ARCH_MPC830X) || defined(CONFIG_ARCH_MPC831X)
+#if defined(CONFIG_ARCH_MPC830X)
#define CSCONFIG_ODT_RD_NEVER 0x00000000
#define CSCONFIG_ODT_RD_ONLY_CURRENT 0x00100000
#define CSCONFIG_ODT_RD_ONLY_OTHER_CS 0x00200000
@@ -932,7 +874,7 @@
#define SDRAM_CFG_SDRAM_TYPE_MASK 0x07000000
#define SDRAM_CFG_SDRAM_TYPE_SHIFT 24
#define SDRAM_CFG_DYN_PWR 0x00200000
-#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X)
+#if defined(CONFIG_ARCH_MPC8308)
#define SDRAM_CFG_DBW_MASK 0x00180000
#define SDRAM_CFG_DBW_16 0x00100000
#define SDRAM_CFG_DBW_32 0x00080000
--
2.47.3
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH 21/26] powerpc: mpc83xx: Remove MPC834x support
2026-10-09 19:36 [PATCH 00/26] powerpc: drop EOL boards and SoCs, take over maintenance Bradley Morgan
` (19 preceding siblings ...)
2026-10-09 19:36 ` [PATCH 20/26] powerpc: mpc83xx: Remove MPC831x support Bradley Morgan
@ 2026-10-09 19:36 ` Bradley Morgan
2026-10-09 19:37 ` [PATCH 22/26] powerpc: mpc85xx: Remove P1024 support Bradley Morgan
` (4 subsequent siblings)
25 siblings, 0 replies; 31+ messages in thread
From: Bradley Morgan @ 2026-10-09 19:36 UTC (permalink / raw)
To: Tom Rini, u-boot
Cc: Bradley Morgan, Marek Behún, Marek Mojík,
NXP i . MX U-Boot Team, Alexey Charkov, Anshul Dalal,
Daniel Golle, Fabio Estevam, Gaurav Jain, Ilias Apalodimas,
Jaehoon Chung, James Hilliard, Jerome Forissier, Johan Jonker,
Lukasz Majewski, Marek Vasut, Mario Six, Michael Walle,
Michal Simek, Neil Armstrong, Peng Fan, Pengpeng Hou,
Priyanka Jain, Quentin Schulz, Simon Glass, Stefano Babic,
Tanmay Kathpalia, Torsten Rupp, Vincent Jardin, Weijie Gao
NXP marks the MPC8343, MPC8347 and MPC8349 no longer manufactured.
No board selects ARCH_MPC834X, so none of its clock, register or CPU
ID paths has a consumer.
Remove the family code.
Signed-off-by: Bradley Morgan <brads@mainlining.org>
---
arch/powerpc/cpu/mpc83xx/Kconfig | 4 -
arch/powerpc/cpu/mpc83xx/cpu.c | 7 +-
arch/powerpc/cpu/mpc83xx/cpu_init.c | 12 --
arch/powerpc/cpu/mpc83xx/fdt.c | 5 +-
arch/powerpc/cpu/mpc83xx/initreg/Kconfig.lcrr | 4 +-
arch/powerpc/cpu/mpc83xx/pci.c | 2 -
arch/powerpc/cpu/mpc83xx/spd_sdram.c | 2 +-
arch/powerpc/cpu/mpc83xx/speed.c | 58 +-----
arch/powerpc/cpu/mpc83xx/traps.c | 1 -
arch/powerpc/include/asm/arch-mpc83xx/gpio.h | 2 -
arch/powerpc/include/asm/arch-mpc83xx/soc.h | 4 +-
arch/powerpc/include/asm/fsl_lbc.h | 10 +-
arch/powerpc/include/asm/global_data.h | 6 +-
arch/powerpc/include/asm/immap_83xx.h | 43 +----
arch/powerpc/include/asm/mpc8349_pci.h | 165 ------------------
arch/powerpc/include/asm/mpc8xxx_spi.h | 3 +-
doc/README.mpc83xxads | 97 ----------
.../clock/fsl,mpc83xx-clk.txt | 1 -
doc/device-tree-bindings/cpu/fsl,mpc83xx.txt | 1 -
drivers/clk/mpc83xx_clk.c | 3 -
drivers/clk/mpc83xx_clk.h | 13 +-
drivers/cpu/mpc83xx_cpu.c | 28 +--
drivers/cpu/mpc83xx_cpu.h | 16 --
drivers/pci/pci_auto.c | 14 --
include/dt-bindings/clk/mpc83xx-clk.h | 1 -
include/mpc83xx.h | 136 +--------------
26 files changed, 28 insertions(+), 610 deletions(-)
delete mode 100644 arch/powerpc/include/asm/mpc8349_pci.h
delete mode 100644 doc/README.mpc83xxads
diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig
index 06d84c2d945..4b8e2181757 100644
--- a/arch/powerpc/cpu/mpc83xx/Kconfig
+++ b/arch/powerpc/cpu/mpc83xx/Kconfig
@@ -131,10 +131,6 @@ config ARCH_MPC832X
select MPC83XX_PCI_SUPPORT
select SYS_CACHE_SHIFT_5
-config ARCH_MPC834X
- bool
- select SYS_CACHE_SHIFT_5
-
config ARCH_MPC8360
bool
select MPC83XX_QUICC_ENGINE
diff --git a/arch/powerpc/cpu/mpc83xx/cpu.c b/arch/powerpc/cpu/mpc83xx/cpu.c
index e1f70f40fec..7583121eb12 100644
--- a/arch/powerpc/cpu/mpc83xx/cpu.c
+++ b/arch/powerpc/cpu/mpc83xx/cpu.c
@@ -50,10 +50,6 @@ int checkcpu(void)
CPU_TYPE_ENTRY(8309),
CPU_TYPE_ENTRY(8321),
CPU_TYPE_ENTRY(8323),
- CPU_TYPE_ENTRY(8343),
- CPU_TYPE_ENTRY(8347_TBGA_),
- CPU_TYPE_ENTRY(8347_PBGA_),
- CPU_TYPE_ENTRY(8349),
CPU_TYPE_ENTRY(8358_TBGA_),
CPU_TYPE_ENTRY(8358_PBGA_),
CPU_TYPE_ENTRY(8360),
@@ -96,8 +92,7 @@ int checkcpu(void)
puts(cpu_type_list[i].name);
if (IS_E_PROCESSOR(spridr))
puts("E");
- if ((SPR_FAMILY(spridr) == SPR_834X_FAMILY ||
- SPR_FAMILY(spridr) == SPR_836X_FAMILY) &&
+ if (SPR_FAMILY(spridr) == SPR_836X_FAMILY &&
REVID_MAJOR(spridr) >= 2)
puts("A");
printf(", Rev: %d.%d", REVID_MAJOR(spridr),
diff --git a/arch/powerpc/cpu/mpc83xx/cpu_init.c b/arch/powerpc/cpu/mpc83xx/cpu_init.c
index 555dd502b36..6c34bdeac7b 100644
--- a/arch/powerpc/cpu/mpc83xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc83xx/cpu_init.c
@@ -84,9 +84,6 @@ void cpu_init_f (volatile immap_t * im)
#ifdef CFG_SYS_SCCR_TSEC2CM /* TSEC2 clock mode */
SCCR_TSEC2CM |
#endif
-#ifdef CONFIG_SYS_SCCR_USBMPHCM /* USB MPH clock mode */
- SCCR_USBMPHCM |
-#endif
#ifdef CFG_SYS_SCCR_USBDRCM /* USB DR clock mode */
SCCR_USBDRCM |
#endif
@@ -116,9 +113,6 @@ void cpu_init_f (volatile immap_t * im)
#ifdef CFG_SYS_SCCR_TSEC2CM /* TSEC2 clock mode */
(CFG_SYS_SCCR_TSEC2CM << SCCR_TSEC2CM_SHIFT) |
#endif
-#ifdef CONFIG_SYS_SCCR_USBMPHCM /* USB MPH clock mode */
- (CONFIG_SYS_SCCR_USBMPHCM << SCCR_USBMPHCM_SHIFT) |
-#endif
#ifdef CFG_SYS_SCCR_USBDRCM /* USB DR clock mode */
(CFG_SYS_SCCR_USBDRCM << SCCR_USBDRCM_SHIFT) |
#endif
@@ -165,14 +159,8 @@ void cpu_init_f (volatile immap_t * im)
/* System General Purpose Register */
#ifdef CFG_SYS_SICRH
-#if defined(CONFIG_ARCH_MPC834X)
- /* regarding to MPC34x manual rev.1 bits 28..29 must be preserved */
- __raw_writel((im->sysconf.sicrh & 0x0000000C) | CFG_SYS_SICRH,
- &im->sysconf.sicrh);
-#else
__raw_writel(CFG_SYS_SICRH, &im->sysconf.sicrh);
#endif
-#endif
#ifdef CFG_SYS_SICRL
__raw_writel(CFG_SYS_SICRL, &im->sysconf.sicrl);
#endif
diff --git a/arch/powerpc/cpu/mpc83xx/fdt.c b/arch/powerpc/cpu/mpc83xx/fdt.c
index 08c3e783597..1eaff5e5aad 100644
--- a/arch/powerpc/cpu/mpc83xx/fdt.c
+++ b/arch/powerpc/cpu/mpc83xx/fdt.c
@@ -38,15 +38,14 @@ void ft_cpu_setup(void *blob, struct bd_info *bd)
/*
* delete crypto node if not on an E-processor
- * initial revisions of the MPC834xE/6xE have the original SEC 2.0.
+ * Initial revisions of the MPC836xE have the original SEC 2.0.
* EA revisions got the SEC uprevved to 2.4 but since the default device
* tree contains SEC 2.0 properties we uprev them here.
*/
if (!IS_E_PROCESSOR(spridr))
fdt_fixup_crypto_node(blob, 0);
else if (IS_E_PROCESSOR(spridr) &&
- (SPR_FAMILY(spridr) == SPR_834X_FAMILY ||
- SPR_FAMILY(spridr) == SPR_836X_FAMILY) &&
+ SPR_FAMILY(spridr) == SPR_836X_FAMILY &&
REVID_MAJOR(spridr) >= 2)
fdt_fixup_crypto_node(blob, 0x0204);
diff --git a/arch/powerpc/cpu/mpc83xx/initreg/Kconfig.lcrr b/arch/powerpc/cpu/mpc83xx/initreg/Kconfig.lcrr
index a85e698a867..f62bdd62bb2 100644
--- a/arch/powerpc/cpu/mpc83xx/initreg/Kconfig.lcrr
+++ b/arch/powerpc/cpu/mpc83xx/initreg/Kconfig.lcrr
@@ -18,7 +18,7 @@ endchoice
endif
-if ARCH_MPC834X || ARCH_MPC8360
+if ARCH_MPC8360
choice
prompt "Additional delay cycles for SDRAM control signals"
@@ -60,7 +60,7 @@ config LCRR_ECL_7
endchoice
-endif # ARCH_MPC834X || ARCH_MPC8360
+endif # ARCH_MPC8360
if !ARCH_MPC8308
diff --git a/arch/powerpc/cpu/mpc83xx/pci.c b/arch/powerpc/cpu/mpc83xx/pci.c
index aef1123a2b7..76023ae698b 100644
--- a/arch/powerpc/cpu/mpc83xx/pci.c
+++ b/arch/powerpc/cpu/mpc83xx/pci.c
@@ -17,8 +17,6 @@
#include <fdt_support.h>
#endif
-#include <asm/mpc8349_pci.h>
-
#define MAX_BUSES 2
DECLARE_GLOBAL_DATA_PTR;
diff --git a/arch/powerpc/cpu/mpc83xx/spd_sdram.c b/arch/powerpc/cpu/mpc83xx/spd_sdram.c
index 949efc8e828..6b3e59143fe 100644
--- a/arch/powerpc/cpu/mpc83xx/spd_sdram.c
+++ b/arch/powerpc/cpu/mpc83xx/spd_sdram.c
@@ -432,7 +432,7 @@ long int spd_sdram()
/*
* Errata DDR6 work around: input enable 2 cycles earlier.
- * including MPC834X Rev1.0/1.1 and MPC8360 Rev1.1/1.2.
+ * including MPC8360 Rev1.1/1.2.
*/
if(PVR_MAJ(pvr) <= 1 && spd.mem_type == SPD_MEMTYPE_DDR){
if (caslat == 2)
diff --git a/arch/powerpc/cpu/mpc83xx/speed.c b/arch/powerpc/cpu/mpc83xx/speed.c
index e2ed3caf022..c0eeff1e0a5 100644
--- a/arch/powerpc/cpu/mpc83xx/speed.c
+++ b/arch/powerpc/cpu/mpc83xx/speed.c
@@ -87,14 +87,10 @@ int get_clocks(void)
u32 lcrr;
u32 csb_clk;
-#if defined(CONFIG_ARCH_MPC8308) || \
- defined(CONFIG_ARCH_MPC834X)
+#if defined(CONFIG_ARCH_MPC8308)
u32 tsec1_clk;
u32 tsec2_clk;
u32 usbdr_clk;
-#endif
-#ifdef CONFIG_ARCH_MPC834X
- u32 usbmph_clk;
#endif
u32 core_clk;
u32 i2c1_clk;
@@ -146,8 +142,7 @@ int get_clocks(void)
sccr = im->clk.sccr;
-#if defined(CONFIG_ARCH_MPC8308) || \
- defined(CONFIG_ARCH_MPC834X)
+#if defined(CONFIG_ARCH_MPC8308)
switch ((sccr & SCCR_TSEC1CM) >> SCCR_TSEC1CM_SHIFT) {
case 0:
tsec1_clk = 0;
@@ -167,8 +162,7 @@ int get_clocks(void)
}
#endif
-#if defined(CONFIG_ARCH_MPC830X) || \
- defined(CONFIG_ARCH_MPC834X)
+#if defined(CONFIG_ARCH_MPC830X)
switch ((sccr & SCCR_USBDRCM) >> SCCR_USBDRCM_SHIFT) {
case 0:
usbdr_clk = 0;
@@ -188,7 +182,7 @@ int get_clocks(void)
}
#endif
-#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC834X)
+#if defined(CONFIG_ARCH_MPC8308)
switch ((sccr & SCCR_TSEC2CM) >> SCCR_TSEC2CM_SHIFT) {
case 0:
tsec2_clk = 0;
@@ -208,33 +202,6 @@ int get_clocks(void)
}
#endif
-#if defined(CONFIG_ARCH_MPC834X)
- switch ((sccr & SCCR_USBMPHCM) >> SCCR_USBMPHCM_SHIFT) {
- case 0:
- usbmph_clk = 0;
- break;
- case 1:
- usbmph_clk = csb_clk;
- break;
- case 2:
- usbmph_clk = csb_clk / 2;
- break;
- case 3:
- usbmph_clk = csb_clk / 3;
- break;
- default:
- /* unknown SCCR_USBMPHCM value */
- return -5;
- }
-
- if (usbmph_clk != 0 && usbdr_clk != 0 && usbmph_clk != usbdr_clk) {
- /* if USB MPH clock is not disabled and
- * USB DR clock is not disabled then
- * USB MPH & USB DR must have the same rate
- */
- return -6;
- }
-#endif
switch ((sccr & SCCR_ENCCM) >> SCCR_ENCCM_SHIFT) {
case 0:
enc_clk = 0;
@@ -273,9 +240,7 @@ int get_clocks(void)
}
#endif
-#if defined(CONFIG_ARCH_MPC834X)
- i2c1_clk = tsec2_clk;
-#elif defined(CONFIG_ARCH_MPC8360)
+#if defined(CONFIG_ARCH_MPC8360)
i2c1_clk = csb_clk;
#elif defined(CONFIG_ARCH_MPC832X)
i2c1_clk = enc_clk;
@@ -385,15 +350,11 @@ int get_clocks(void)
#endif
gd->arch.csb_clk = csb_clk;
-#if defined(CONFIG_ARCH_MPC8308) || \
- defined(CONFIG_ARCH_MPC834X)
+#if defined(CONFIG_ARCH_MPC8308)
gd->arch.tsec1_clk = tsec1_clk;
gd->arch.tsec2_clk = tsec2_clk;
gd->arch.usbdr_clk = usbdr_clk;
#endif
-#if defined(CONFIG_ARCH_MPC834X)
- gd->arch.usbmph_clk = usbmph_clk;
-#endif
#if defined(CONFIG_FSL_ESDHC)
gd->arch.sdhc_clk = sdhc_clk;
#endif
@@ -484,8 +445,7 @@ static int do_clocks(struct cmd_tbl *cmdtp, int flag, int argc,
printf(" SDHC: %-4s MHz\n",
strmhz(buf, gd->arch.sdhc_clk));
#endif
-#if defined(CONFIG_ARCH_MPC8308) || \
- defined(CONFIG_ARCH_MPC834X)
+#if defined(CONFIG_ARCH_MPC8308)
printf(" TSEC1: %-4s MHz\n",
strmhz(buf, gd->arch.tsec1_clk));
printf(" TSEC2: %-4s MHz\n",
@@ -493,10 +453,6 @@ static int do_clocks(struct cmd_tbl *cmdtp, int flag, int argc,
printf(" USB DR: %-4s MHz\n",
strmhz(buf, gd->arch.usbdr_clk));
#endif
-#if defined(CONFIG_ARCH_MPC834X)
- printf(" USB MPH: %-4s MHz\n",
- strmhz(buf, gd->arch.usbmph_clk));
-#endif
#if defined(CONFIG_ARCH_MPC8308)
printf(" PCIEXP1: %-4s MHz\n",
strmhz(buf, gd->arch.pciexp1_clk));
diff --git a/arch/powerpc/cpu/mpc83xx/traps.c b/arch/powerpc/cpu/mpc83xx/traps.c
index d50499ceb7c..d68c0a23f18 100644
--- a/arch/powerpc/cpu/mpc83xx/traps.c
+++ b/arch/powerpc/cpu/mpc83xx/traps.c
@@ -16,7 +16,6 @@
#include <command.h>
#include <kgdb.h>
#include <asm/processor.h>
-#include <asm/mpc8349_pci.h>
DECLARE_GLOBAL_DATA_PTR;
diff --git a/arch/powerpc/include/asm/arch-mpc83xx/gpio.h b/arch/powerpc/include/asm/arch-mpc83xx/gpio.h
index 6449fded125..7657471b99f 100644
--- a/arch/powerpc/include/asm/arch-mpc83xx/gpio.h
+++ b/arch/powerpc/include/asm/arch-mpc83xx/gpio.h
@@ -8,8 +8,6 @@
*/
#if defined(CONFIG_ARCH_MPC8308)
#define MPC83XX_GPIO_CTRLRS 1
-#elif defined(CONFIG_ARCH_MPC834X)
-#define MPC83XX_GPIO_CTRLRS 2
#else
#define MPC83XX_GPIO_CTRLRS 0
#endif
diff --git a/arch/powerpc/include/asm/arch-mpc83xx/soc.h b/arch/powerpc/include/asm/arch-mpc83xx/soc.h
index 0eeaa23b190..0473389bc7d 100644
--- a/arch/powerpc/include/asm/arch-mpc83xx/soc.h
+++ b/arch/powerpc/include/asm/arch-mpc83xx/soc.h
@@ -11,7 +11,6 @@ enum soc_type {
SOC_MPC8308,
SOC_MPC8309,
SOC_MPC832X,
- SOC_MPC8349,
SOC_MPC8360,
};
@@ -23,8 +22,7 @@ static inline bool mpc83xx_has_sdhc(int type)
static inline bool mpc83xx_has_tsec(int type)
{
- return (type == SOC_MPC8308) ||
- (type == SOC_MPC8349);
+ return type == SOC_MPC8308;
}
static inline bool mpc83xx_has_pcie1(int type)
diff --git a/arch/powerpc/include/asm/fsl_lbc.h b/arch/powerpc/include/asm/fsl_lbc.h
index 9efb6ae6cd0..37da14c45f1 100644
--- a/arch/powerpc/include/asm/fsl_lbc.h
+++ b/arch/powerpc/include/asm/fsl_lbc.h
@@ -40,10 +40,10 @@ void lbc_sdram_init(void);
#define BR_MSEL 0x000000E0
#define BR_MSEL_SHIFT 5
#define BR_MS_GPCM 0x00000000 /* GPCM */
-#if !defined(CONFIG_ARCH_MPC834X) && !defined(CONFIG_ARCH_MPC8360)
+#if !defined(CONFIG_ARCH_MPC8360)
#define BR_MS_FCM 0x00000020 /* FCM */
#endif
-#if defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC8360)
+#if defined(CONFIG_ARCH_MPC8360)
#define BR_MS_SDRAM 0x00000060 /* SDRAM */
#elif defined(CONFIG_MPC85xx)
#define BR_MS_SDRAM 0x00000000 /* SDRAM */
@@ -51,10 +51,8 @@ void lbc_sdram_init(void);
#define BR_MS_UPMA 0x00000080 /* UPMA */
#define BR_MS_UPMB 0x000000A0 /* UPMB */
#define BR_MS_UPMC 0x000000C0 /* UPMC */
-#if !defined(CONFIG_ARCH_MPC834X)
#define BR_ATOM 0x0000000C
#define BR_ATOM_SHIFT 2
-#endif
#define BR_V 0x00000001
#define BR_V_SHIFT 0
@@ -64,11 +62,7 @@ void lbc_sdram_init(void);
#define UPMB 1
#define UPMC 2
-#if defined(CONFIG_ARCH_MPC834X)
-#define BR_RES ~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_V)
-#else
#define BR_RES ~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_ATOM | BR_V)
-#endif
/* Convert an address into the right format for the BR registers */
#if defined(CONFIG_PHYS_64BIT) && !defined(CONFIG_FSL_ELBC)
diff --git a/arch/powerpc/include/asm/global_data.h b/arch/powerpc/include/asm/global_data.h
index 168eb55b497..710d538dad9 100644
--- a/arch/powerpc/include/asm/global_data.h
+++ b/arch/powerpc/include/asm/global_data.h
@@ -26,15 +26,11 @@ struct arch_global_data {
#else
/* There are other clocks in the MPC83XX */
u32 csb_clk;
-# if defined(CONFIG_ARCH_MPC8308) || \
- defined(CONFIG_ARCH_MPC834X)
+# if defined(CONFIG_ARCH_MPC8308)
u32 tsec1_clk;
u32 tsec2_clk;
u32 usbdr_clk;
# endif
-# if defined(CONFIG_ARCH_MPC834X)
- u32 usbmph_clk;
-# endif /* CONFIG_ARCH_MPC834X */
u32 core_clk;
u32 enc_clk;
u32 lbiu_clk;
diff --git a/arch/powerpc/include/asm/immap_83xx.h b/arch/powerpc/include/asm/immap_83xx.h
index c7e7616529d..428839ad1a5 100644
--- a/arch/powerpc/include/asm/immap_83xx.h
+++ b/arch/powerpc/include/asm/immap_83xx.h
@@ -647,48 +647,7 @@ typedef struct tdmdmac83xx {
} tdmdmac83xx_t;
static_assert(sizeof(tdmdmac83xx_t) == 0x2000);
-#if defined(CONFIG_ARCH_MPC834X)
-typedef struct immap {
- sysconf83xx_t sysconf; /* System configuration */
- wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
- rtclk83xx_t rtc; /* Real Time Clock Module Registers */
- rtclk83xx_t pit; /* Periodic Interval Timer */
- gtm83xx_t gtm[2]; /* Global Timers Module */
- ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
- arbiter83xx_t arbiter; /* System Arbiter Registers */
- reset83xx_t reset; /* Reset Module */
- clk83xx_t clk; /* System Clock Module */
- pmc83xx_t pmc; /* Power Management Control Module */
- gpio83xx_t gpio[2]; /* General purpose I/O module */
- u8 res0[0x200];
- u8 dll_ddr[0x100];
- u8 dll_lbc[0x100];
- u8 res1[0xE00];
-#if defined(CONFIG_SYS_FSL_DDR2) || defined(CONFIG_SYS_FSL_DDR3)
- struct ccsr_ddr ddr; /* DDR Memory Controller Memory */
-#else
- ddr83xx_t ddr; /* DDR Memory Controller Memory */
-#endif
- fsl_i2c_t i2c[2]; /* I2C Controllers */
- u8 res2[0x1300];
- duart83xx_t duart[2]; /* DUART */
- u8 res3[0x900];
- fsl_lbc_t im_lbc; /* Local Bus Controller Regs */
- u8 res4[0x1000];
- spi8xxx_t spi; /* Serial Peripheral Interface */
- dma83xx_t dma; /* DMA */
- pciconf83xx_t pci_conf[2]; /* PCI Software Configuration Registers */
- ios83xx_t ios; /* Sequencer */
- pcictrl83xx_t pci_ctrl[2]; /* PCI Controller Control and Status Registers */
- u8 res5[0x19900];
- usb83xx_t usb[2];
- tsec83xx_t tsec[2];
- u8 res6[0xA000];
- security83xx_t security;
- u8 res7[0xC0000];
-} immap_t;
-
-#elif defined(CONFIG_ARCH_MPC8308)
+#if defined(CONFIG_ARCH_MPC8308)
typedef struct immap {
sysconf83xx_t sysconf; /* System configuration */
wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
diff --git a/arch/powerpc/include/asm/mpc8349_pci.h b/arch/powerpc/include/asm/mpc8349_pci.h
deleted file mode 100644
index 3d920c25ade..00000000000
--- a/arch/powerpc/include/asm/mpc8349_pci.h
+++ /dev/null
@@ -1,165 +0,0 @@
-#ifndef _PPC_KERNEL_MPC8349_PCI_H
-#define _PPC_KERNEL_MPC8349_PCI_H
-
-#define M8265_PCIBR0 0x101ac
-#define M8265_PCIBR1 0x101b0
-#define M8265_PCIMSK0 0x101c4
-#define M8265_PCIMSK1 0x101c8
-
-/* Bit definitions for PCIBR registers */
-
-#define PCIBR_ENABLE 0x00000001
-
-/* Bit definitions for PCIMSK registers */
-
-#define PCIMSK_32KB 0xFFFF8000 /* Size of window, smallest */
-#define PCIMSK_64KB 0xFFFF0000
-#define PCIMSK_128KB 0xFFFE0000
-#define PCIMSK_256KB 0xFFFC0000
-#define PCIMSK_512KB 0xFFF80000
-#define PCIMSK_1MB 0xFFF00000
-#define PCIMSK_2MB 0xFFE00000
-#define PCIMSK_4MB 0xFFC00000
-#define PCIMSK_8MB 0xFF800000
-#define PCIMSK_16MB 0xFF000000
-#define PCIMSK_32MB 0xFE000000
-#define PCIMSK_64MB 0xFC000000
-#define PCIMSK_128MB 0xF8000000
-#define PCIMSK_256MB 0xF0000000
-#define PCIMSK_512MB 0xE0000000
-#define PCIMSK_1GB 0xC0000000 /* Size of window, largest */
-
-#define M826X_SCCR_PCI_MODE_EN 0x100
-
-/*
- * Outbound ATU registers (3 sets). These registers control how 60x bus
- * (local) addresses are translated to PCI addresses when the MPC826x is
- * a PCI bus master (initiator).
- */
-
-#define POTAR_REG0 0x10800 /* PCI Outbound Translation Addr registers */
-#define POTAR_REG1 0x10818
-#define POTAR_REG2 0x10830
-
-#define POBAR_REG0 0x10808 /* PCI Outbound Base Addr registers */
-#define POBAR_REG1 0x10820
-#define POBAR_REG2 0x10838
-
-#define POCMR_REG0 0x10810 /* PCI Outbound Comparison Mask registers */
-#define POCMR_REG1 0x10828
-#define POCMR_REG2 0x10840
-
-/* Bit definitions for POMCR registers */
-
-#define POCMR_MASK_4KB 0x000FFFFF
-#define POCMR_MASK_8KB 0x000FFFFE
-#define POCMR_MASK_16KB 0x000FFFFC
-#define POCMR_MASK_32KB 0x000FFFF8
-#define POCMR_MASK_64KB 0x000FFFF0
-#define POCMR_MASK_128KB 0x000FFFE0
-#define POCMR_MASK_256KB 0x000FFFC0
-#define POCMR_MASK_512KB 0x000FFF80
-#define POCMR_MASK_1MB 0x000FFF00
-#define POCMR_MASK_2MB 0x000FFE00
-#define POCMR_MASK_4MB 0x000FFC00
-#define POCMR_MASK_8MB 0x000FF800
-#define POCMR_MASK_16MB 0x000FF000
-#define POCMR_MASK_32MB 0x000FE000
-#define POCMR_MASK_64MB 0x000FC000
-#define POCMR_MASK_128MB 0x000F8000
-#define POCMR_MASK_256MB 0x000F0000
-#define POCMR_MASK_512MB 0x000E0000
-#define POCMR_MASK_1GB 0x000C0000
-
-#define POCMR_ENABLE 0x80000000
-#define POCMR_PCI_IO 0x40000000
-#define POCMR_PREFETCH_EN 0x20000000
-#define POCMR_PCI2 0x10000000
-
-/* Soft PCI reset */
-
-#define PCI_GCR_REG 0x10880
-
-/* Bit definitions for PCI_GCR registers */
-
-#define PCIGCR_PCI_BUS_EN 0x1
-
-/*
- * Inbound ATU registers (2 sets). These registers control how PCI
- * addresses are translated to 60x bus (local) addresses when the
- * MPC826x is a PCI bus target.
- */
-
-#define PITAR_REG1 0x108D0
-#define PIBAR_REG1 0x108D8
-#define PICMR_REG1 0x108E0
-#define PITAR_REG0 0x108E8
-#define PIBAR_REG0 0x108F0
-#define PICMR_REG0 0x108F8
-
-/* Bit definitions for PCI Inbound Comparison Mask registers */
-
-#define PICMR_MASK_4KB 0x000FFFFF
-#define PICMR_MASK_8KB 0x000FFFFE
-#define PICMR_MASK_16KB 0x000FFFFC
-#define PICMR_MASK_32KB 0x000FFFF8
-#define PICMR_MASK_64KB 0x000FFFF0
-#define PICMR_MASK_128KB 0x000FFFE0
-#define PICMR_MASK_256KB 0x000FFFC0
-#define PICMR_MASK_512KB 0x000FFF80
-#define PICMR_MASK_1MB 0x000FFF00
-#define PICMR_MASK_2MB 0x000FFE00
-#define PICMR_MASK_4MB 0x000FFC00
-#define PICMR_MASK_8MB 0x000FF800
-#define PICMR_MASK_16MB 0x000FF000
-#define PICMR_MASK_32MB 0x000FE000
-#define PICMR_MASK_64MB 0x000FC000
-#define PICMR_MASK_128MB 0x000F8000
-#define PICMR_MASK_256MB 0x000F0000
-#define PICMR_MASK_512MB 0x000E0000
-#define PICMR_MASK_1GB 0x000C0000
-
-#define PICMR_ENABLE 0x80000000
-#define PICMR_NO_SNOOP_EN 0x40000000
-#define PICMR_PREFETCH_EN 0x20000000
-
-/* PCI error Registers */
-
-#define PCI_ERROR_STATUS_REG 0x10884
-#define PCI_ERROR_MASK_REG 0x10888
-#define PCI_ERROR_CONTROL_REG 0x1088C
-#define PCI_ERROR_ADRS_CAPTURE_REG 0x10890
-#define PCI_ERROR_DATA_CAPTURE_REG 0x10898
-#define PCI_ERROR_CTRL_CAPTURE_REG 0x108A0
-
-/* PCI error Register bit defines */
-
-#define PCI_ERROR_PCI_ADDR_PAR 0x00000001
-#define PCI_ERROR_PCI_DATA_PAR_WR 0x00000002
-#define PCI_ERROR_PCI_DATA_PAR_RD 0x00000004
-#define PCI_ERROR_PCI_NO_RSP 0x00000008
-#define PCI_ERROR_PCI_TAR_ABT 0x00000010
-#define PCI_ERROR_PCI_SERR 0x00000020
-#define PCI_ERROR_PCI_PERR_RD 0x00000040
-#define PCI_ERROR_PCI_PERR_WR 0x00000080
-#define PCI_ERROR_I2O_OFQO 0x00000100
-#define PCI_ERROR_I2O_IPQO 0x00000200
-#define PCI_ERROR_IRA 0x00000400
-#define PCI_ERROR_NMI 0x00000800
-#define PCI_ERROR_I2O_DBMC 0x00001000
-
-/*
- * Register pair used to generate configuration cycles on the PCI bus
- * and access the MPC826x's own PCI configuration registers.
- */
-
-#define PCI_CFG_ADDR_REG 0x10900
-#define PCI_CFG_DATA_REG 0x10904
-
-/* Bus parking decides where the bus control sits when idle */
-/* If modifying memory controllers for PCI park on the core */
-
-#define PPC_ACR_BUS_PARK_CORE 0x6
-#define PPC_ACR_BUS_PARK_PCI 0x3
-
-#endif /* _PPC_KERNEL_M8260_PCI_H */
diff --git a/arch/powerpc/include/asm/mpc8xxx_spi.h b/arch/powerpc/include/asm/mpc8xxx_spi.h
index 5d8d7db2933..f057040dfbc 100644
--- a/arch/powerpc/include/asm/mpc8xxx_spi.h
+++ b/arch/powerpc/include/asm/mpc8xxx_spi.h
@@ -11,8 +11,7 @@
#include <asm/types.h>
#if defined(CONFIG_ARCH_MPC8308) || \
- defined(CONFIG_ARCH_MPC832X) || \
- defined(CONFIG_ARCH_MPC834X)
+ defined(CONFIG_ARCH_MPC832X)
typedef struct spi8xxx {
u8 res0[0x20]; /* 0x0-0x01f reserved */
diff --git a/doc/README.mpc83xxads b/doc/README.mpc83xxads
deleted file mode 100644
index 372fdd9ce85..00000000000
--- a/doc/README.mpc83xxads
+++ /dev/null
@@ -1,97 +0,0 @@
-Freescale MPC83xx ADS Boards
------------------------------------------
-
-0. Toolchain / Building
-
- $ PATH=$PATH:/usr/powerpc/bin
- $ CROSS_COMPILE=powerpc-linux-
- $ export PATH CROSS_COMPILE
-
- $ powerpc-linux-gcc -v
- Reading specs from /usr/powerpc/lib/gcc/powerpc-linux/3.4.3/specs
- Configured with: ../configure --prefix=/usr/powerpc
- --exec-prefix=/usr/powerpc --target=powerpc-linux --enable-shared
- --disable-nls --disable-multilib --enable-languages=c,c++,ada,f77,objc
- Thread model: posix
- gcc version 3.4.3 (Debian)
-
- $ powerpc-linux-as -v
- GNU assembler version 2.15 (powerpc-linux) using BFD version 2.15
-
-
- $ make MPC8349ADS_config
- Configuring for MPC8349ADS board...
-
- $ make
-
-
-1. Board Switches and Jumpers
-
-
-2. Memory Map
-
-2.1. The memory map should look pretty much like this:
-
- 0x0000_0000 0x7fff_ffff DDR 2G
- 0x8000_0000 0x9fff_ffff PCI MEM 512M
- 0xc000_0000 0xdfff_ffff Rapid IO 512M
- 0xe000_0000 0xe00f_ffff CCSR 1M
- 0xe200_0000 0xe2ff_ffff PCI IO 16M
- 0xf000_0000 0xf7ff_ffff SDRAM 128M
- 0xf800_0000 0xf80f_ffff BCSR 1M
- 0xfe00_0000 0xffff_ffff FLASH (boot bank) 16M
-
-
-3. Definitions
-
-3.1 Explanation of NEW definitions in:
-
- include/configs/MPC8349ADS.h
-
- CONFIG_MPC83xx MPC83xx family
- CONFIG_MPC8349 MPC8349 specific
- CONFIG_TSEC_ENET Use on-chip 10/100/1000 ethernet
-
-
-4. Compilation
-
- Assuming you're using BASH shell:
-
- export CROSS_COMPILE=your-cross-compile-prefix
- cd u-boot
- make distclean
- make MPC8349ADS_config
- make
-
-5. Downloading and Flashing Images
-
-5.0 Download over serial line using Kermit:
-
- loadb
- [Drop to kermit:
- ^\c
- send <u-boot-bin-image>
- c
- ]
-
-
- Or via tftp:
-
- tftp 10000 u-boot.bin
-
-5.1 Reflash U-Boot Image using U-Boot
-
- tftp 10000 u-boot.bin
- protect off fe000000 fe09ffff
- erase fe000000 fe09ffff
-
- cp.b 10000 fe000000 xxxx
-or
- cp.b 10000 fe000000 a0000
-
-You might have to supply the correct byte count for 'xxxx' from
-the TFTP. Maybe a0000 will work too, that corresponds to the
-erased sectors.
-
-
-6. Notes
diff --git a/doc/device-tree-bindings/clock/fsl,mpc83xx-clk.txt b/doc/device-tree-bindings/clock/fsl,mpc83xx-clk.txt
index baaacb62846..213123dbab4 100644
--- a/doc/device-tree-bindings/clock/fsl,mpc83xx-clk.txt
+++ b/doc/device-tree-bindings/clock/fsl,mpc83xx-clk.txt
@@ -7,7 +7,6 @@ Required properties:
- compatible: must be one of "fsl,mpc8308-clk",
"fsl,mpc8309-clk",
"fsl,mpc832x-clk",
- "fsl,mpc8349-clk",
"fsl,mpc8360-clk"
depending on which SoC is employed
- #clock-cells: Must be 1
diff --git a/doc/device-tree-bindings/cpu/fsl,mpc83xx.txt b/doc/device-tree-bindings/cpu/fsl,mpc83xx.txt
index 5bdbd309fbf..5acb2c403c9 100644
--- a/doc/device-tree-bindings/cpu/fsl,mpc83xx.txt
+++ b/doc/device-tree-bindings/cpu/fsl,mpc83xx.txt
@@ -7,7 +7,6 @@ Required properties:
"fsl,mpc8308",
"fsl,mpc8309",
"fsl,mpc832x",
- "fsl,mpc8349",
"fsl,mpc8360"
- clocks: has to have two entries, which must be the core clock at index 0 and
the CSB (Coherent System Bus) clock at index 1. Both are given by a suitable
diff --git a/drivers/clk/mpc83xx_clk.c b/drivers/clk/mpc83xx_clk.c
index bca09f17d5f..4b2f1705b64 100644
--- a/drivers/clk/mpc83xx_clk.c
+++ b/drivers/clk/mpc83xx_clk.c
@@ -59,8 +59,6 @@ static inline bool is_clk_valid(struct udevice *clk, int id)
return mpc83xx_has_tsec(type);
case MPC83XX_CLK_USBDR:
return type == SOC_MPC8360;
- case MPC83XX_CLK_USBMPH:
- return type == SOC_MPC8349;
case MPC83XX_CLK_PCIEXP1:
return mpc83xx_has_pcie1(type);
case MPC83XX_CLK_PCIEXP2:
@@ -322,7 +320,6 @@ static const struct udevice_id mpc83xx_clk_match[] = {
{ .compatible = "fsl,mpc8308-clk", .data = SOC_MPC8308 },
{ .compatible = "fsl,mpc8309-clk", .data = SOC_MPC8309 },
{ .compatible = "fsl,mpc832x-clk", .data = SOC_MPC832X },
- { .compatible = "fsl,mpc8349-clk", .data = SOC_MPC8349 },
{ .compatible = "fsl,mpc8360-clk", .data = SOC_MPC8360 },
{ /* sentinel */ }
};
diff --git a/drivers/clk/mpc83xx_clk.h b/drivers/clk/mpc83xx_clk.h
index ce3683f3932..ba7ea9dd741 100644
--- a/drivers/clk/mpc83xx_clk.h
+++ b/drivers/clk/mpc83xx_clk.h
@@ -125,7 +125,6 @@ static const char * const names[] = {
[MPC83XX_CLK_TSEC1] = "TSEC1",
[MPC83XX_CLK_TSEC2] = "TSEC2",
[MPC83XX_CLK_USBDR] = "USB DR",
- [MPC83XX_CLK_USBMPH] = "USB MPH",
[MPC83XX_CLK_PCIEXP1] = "PCIEXP1",
[MPC83XX_CLK_PCIEXP2] = "PCIEXP2",
[MPC83XX_CLK_SATA] = "SATA",
@@ -214,10 +213,8 @@ static int retrieve_mode(int clk, int soc_type, struct clk_mode *mode)
set_mode(mode, 6, 7, TYPE_SCCR_STANDARD);
break;
case MPC83XX_CLK_I2C1:
- if (soc_type == SOC_MPC8349)
- set_mode(mode, 2, 3, TYPE_SCCR_STANDARD);
- else /* I2C and ENC are the same register */
- set_mode(mode, 6, 7, TYPE_SCCR_STANDARD);
+ /* I2C and ENC use the same register */
+ set_mode(mode, 6, 7, TYPE_SCCR_STANDARD);
break;
case MPC83XX_CLK_PCIEXP1:
set_mode(mode, 10, 11, TYPE_SCCR_STANDARD);
@@ -226,12 +223,6 @@ static int retrieve_mode(int clk, int soc_type, struct clk_mode *mode)
set_mode(mode, 12, 13, TYPE_SCCR_STANDARD);
break;
case MPC83XX_CLK_USBDR:
- if (soc_type == SOC_MPC8349)
- set_mode(mode, 10, 11, TYPE_SCCR_STANDARD);
- else
- set_mode(mode, 8, 9, TYPE_SCCR_STANDARD);
- break;
- case MPC83XX_CLK_USBMPH:
set_mode(mode, 8, 9, TYPE_SCCR_STANDARD);
break;
case MPC83XX_CLK_PCI:
diff --git a/drivers/cpu/mpc83xx_cpu.c b/drivers/cpu/mpc83xx_cpu.c
index 01ac307c821..56b192ca153 100644
--- a/drivers/cpu/mpc83xx_cpu.c
+++ b/drivers/cpu/mpc83xx_cpu.c
@@ -73,9 +73,6 @@ static inline void determine_family(const struct udevice *dev)
case 0x806:
priv->family = FAMILY_832X;
break;
- case 0x803:
- priv->family = FAMILY_834X;
- break;
case 0x804:
priv->family = FAMILY_836X;
break;
@@ -111,18 +108,6 @@ static inline void determine_type(const struct udevice *dev)
case 0x8062:
priv->type = TYPE_8323;
break;
- case 0x8036:
- priv->type = TYPE_8343;
- break;
- case 0x8032:
- priv->type = TYPE_8347_TBGA;
- break;
- case 0x8034:
- priv->type = TYPE_8347_PBGA;
- break;
- case 0x8030:
- priv->type = TYPE_8349;
- break;
case 0x804A:
priv->type = TYPE_8358_TBGA;
break;
@@ -177,13 +162,8 @@ static inline void determine_revid(const struct udevice *dev)
u32 REVID_MINOR_MASK;
u32 spridr = get_spridr();
- if (priv->family == FAMILY_834X) {
- REVID_MAJOR_MASK = 0x0000FF00;
- REVID_MINOR_MASK = 0x000000FF;
- } else {
- REVID_MAJOR_MASK = 0x000000F0;
- REVID_MINOR_MASK = 0x0000000F;
- }
+ REVID_MAJOR_MASK = 0x000000F0;
+ REVID_MINOR_MASK = 0x0000000F;
priv->revid.major = bitfield_extract_by_mask(spridr, REVID_MAJOR_MASK);
priv->revid.minor = bitfield_extract_by_mask(spridr, REVID_MINOR_MASK);
@@ -204,8 +184,7 @@ static void determine_cpu_data(const struct udevice *dev)
determine_e300_type(dev);
determine_revid(dev);
- if ((priv->family == FAMILY_834X ||
- priv->family == FAMILY_836X) && priv->revid.major >= 2)
+ if (priv->family == FAMILY_836X && priv->revid.major >= 2)
priv->is_a_variant = true;
priv->is_e_processor = !bitfield_extract_by_mask(spridr, E_FLAG_MASK);
@@ -307,7 +286,6 @@ static const struct udevice_id mpc83xx_cpu_ids[] = {
{ .compatible = "fsl,mpc8308", },
{ .compatible = "fsl,mpc8309", },
{ .compatible = "fsl,mpc832x", },
- { .compatible = "fsl,mpc8349", },
{ .compatible = "fsl,mpc8360", },
{ /* sentinel */ }
};
diff --git a/drivers/cpu/mpc83xx_cpu.h b/drivers/cpu/mpc83xx_cpu.h
index d9773d893f1..f86b36114ab 100644
--- a/drivers/cpu/mpc83xx_cpu.h
+++ b/drivers/cpu/mpc83xx_cpu.h
@@ -36,14 +36,12 @@ static const char * const e300_names[] = {
* enum mpc83xx_cpu_family - Identifiers for MPC83xx CPU families
* @FAMILY_830X: Identifier for the MPC830x CPU family
* @FAMILY_832X: Identifier for the MPC832x CPU family
- * @FAMILY_834X: Identifier for the MPC834x CPU family
* @FAMILY_836X: Identifier for the MPC836x CPU family
* @FAMILY_UNKNOWN: Identifier for an unknown MPC83xx CPU family
*/
enum mpc83xx_cpu_family {
FAMILY_830X,
FAMILY_832X,
- FAMILY_834X,
FAMILY_836X,
FAMILY_UNKNOWN,
};
@@ -54,12 +52,6 @@ enum mpc83xx_cpu_family {
* @TYPE_8309: Identifier for the MPC8309 CPU type
* @TYPE_8321: Identifier for the MPC8321 CPU type
* @TYPE_8323: Identifier for the MPC8323 CPU type
- * @TYPE_8343: Identifier for the MPC8343 CPU type
- * @TYPE_8347_TBGA: Identifier for the MPC8347 CPU type (Tape Ball Grid Array
- * version)
- * @TYPE_8347_PBGA: Identifier for the MPC8347 CPU type (Plastic Ball Grid Array
- * version)
- * @TYPE_8349: Identifier for the MPC8349 CPU type
* @TYPE_8358_TBGA: Identifier for the MPC8358 CPU type (Tape Ball Grid Array
* version)
* @TYPE_8358_PBGA: Identifier for the MPC8358 CPU type (Plastic Ball Grid Array
@@ -72,10 +64,6 @@ enum mpc83xx_cpu_type {
TYPE_8309,
TYPE_8321,
TYPE_8323,
- TYPE_8343,
- TYPE_8347_TBGA,
- TYPE_8347_PBGA,
- TYPE_8349,
TYPE_8358_TBGA,
TYPE_8358_PBGA,
TYPE_8360,
@@ -88,10 +76,6 @@ static const char * const cpu_type_names[] = {
[TYPE_8309] = "8309",
[TYPE_8321] = "8321",
[TYPE_8323] = "8323",
- [TYPE_8343] = "8343",
- [TYPE_8347_TBGA] = "8347_TBGA",
- [TYPE_8347_PBGA] = "8347_PBGA",
- [TYPE_8349] = "8349",
[TYPE_8358_TBGA] = "8358_TBGA",
[TYPE_8358_PBGA] = "8358_PBGA",
[TYPE_8360] = "8360",
diff --git a/drivers/pci/pci_auto.c b/drivers/pci/pci_auto.c
index 4a1c782be36..e1e1fb21e08 100644
--- a/drivers/pci/pci_auto.c
+++ b/drivers/pci/pci_auto.c
@@ -567,20 +567,6 @@ int dm_pciauto_config_device(struct udevice *dev)
PCI_DEV(dm_pci_get_bdf(dev)));
break;
#endif
-#if defined(CONFIG_ARCH_MPC834X)
- case PCI_CLASS_BRIDGE_OTHER:
- /*
- * The host/PCI bridge 1 seems broken in 8349 - it presents
- * itself as 'PCI_CLASS_BRIDGE_OTHER' and appears as an _agent_
- * device claiming resources io/mem/irq.. we only allow for
- * the PIMMR window to be allocated (BAR0 - 1MB size)
- */
- debug("PCI Autoconfig: Broken bridge found, only minimal config\n");
- dm_pciauto_setup_device(dev, 0, hose->pci_mem,
- hose->pci_prefetch, hose->pci_io);
- break;
-#endif
-
default:
dm_pciauto_setup_device(dev, pci_mem, pci_prefetch, pci_io);
break;
diff --git a/include/dt-bindings/clk/mpc83xx-clk.h b/include/dt-bindings/clk/mpc83xx-clk.h
index db4ea15cf42..86d7101ef1c 100644
--- a/include/dt-bindings/clk/mpc83xx-clk.h
+++ b/include/dt-bindings/clk/mpc83xx-clk.h
@@ -22,7 +22,6 @@
#define MPC83XX_CLK_TSEC1 13
#define MPC83XX_CLK_TSEC2 14
#define MPC83XX_CLK_USBDR 15
-#define MPC83XX_CLK_USBMPH 16
#define MPC83XX_CLK_PCIEXP1 17
#define MPC83XX_CLK_PCIEXP2 18
#define MPC83XX_CLK_SATA 19
diff --git a/include/mpc83xx.h b/include/mpc83xx.h
index 8a1a9e7a9b9..d570ba61b7f 100644
--- a/include/mpc83xx.h
+++ b/include/mpc83xx.h
@@ -44,13 +44,8 @@
#define SPRIDR_PARTID 0xFFFF0000 /* Part Id */
#define SPRIDR_REVID 0x0000FFFF /* Revision Id */
-#if defined(CONFIG_ARCH_MPC834X)
-#define REVID_MAJOR(spridr) ((spridr & 0x0000FF00) >> 8)
-#define REVID_MINOR(spridr) (spridr & 0x000000FF)
-#else
#define REVID_MAJOR(spridr) ((spridr & 0x000000F0) >> 4)
#define REVID_MINOR(spridr) (spridr & 0x0000000F)
-#endif
#define PARTID_NO_E(spridr) ((spridr & 0xFFFE0000) >> 16)
#define SPR_FAMILY(spridr) ((spridr & 0xFFF00000) >> 20)
@@ -60,11 +55,6 @@
#define SPR_832X_FAMILY 0x806
#define SPR_8321 0x8066
#define SPR_8323 0x8062
-#define SPR_834X_FAMILY 0x803
-#define SPR_8343 0x8036
-#define SPR_8347_TBGA_ 0x8032
-#define SPR_8347_PBGA_ 0x8034
-#define SPR_8349 0x8030
#define SPR_836X_FAMILY 0x804
#define SPR_8358_TBGA_ 0x804A
#define SPR_8358_PBGA_ 0x804E
@@ -87,28 +77,7 @@
#define SPCR_COREPR 0x00300000
#define SPCR_COREPR_SHIFT (31-11)
-#if defined(CONFIG_ARCH_MPC834X)
-/* SPCR bits - MPC8349 specific */
-/* TSEC1 data priority */
-#define SPCR_TSEC1DP 0x00003000
-#define SPCR_TSEC1DP_SHIFT (31-19)
-/* TSEC1 buffer descriptor priority */
-#define SPCR_TSEC1BDP 0x00000C00
-#define SPCR_TSEC1BDP_SHIFT (31-21)
-/* TSEC1 emergency priority */
-#define SPCR_TSEC1EP 0x00000300
-#define SPCR_TSEC1EP_SHIFT (31-23)
-/* TSEC2 data priority */
-#define SPCR_TSEC2DP 0x00000030
-#define SPCR_TSEC2DP_SHIFT (31-27)
-/* TSEC2 buffer descriptor priority */
-#define SPCR_TSEC2BDP 0x0000000C
-#define SPCR_TSEC2BDP_SHIFT (31-29)
-/* TSEC2 emergency priority */
-#define SPCR_TSEC2EP 0x00000003
-#define SPCR_TSEC2EP_SHIFT (31-31)
-
-#elif defined(CONFIG_ARCH_MPC8308)
+#if defined(CONFIG_ARCH_MPC8308)
/* SPCR bits - MPC8308 specific */
/* TSEC data priority */
#define SPCR_TSECDP 0x00003000
@@ -123,53 +92,7 @@
/* SICRL/H - System I/O Configuration Register Low/High
*/
-#if defined(CONFIG_ARCH_MPC834X)
-/* SICRL bits - MPC8349 specific */
-#define SICRL_LDP_A 0x80000000
-#define SICRL_USB1 0x40000000
-#define SICRL_USB0 0x20000000
-#define SICRL_UART 0x0C000000
-#define SICRL_GPIO1_A 0x02000000
-#define SICRL_GPIO1_B 0x01000000
-#define SICRL_GPIO1_C 0x00800000
-#define SICRL_GPIO1_D 0x00400000
-#define SICRL_GPIO1_E 0x00200000
-#define SICRL_GPIO1_F 0x00180000
-#define SICRL_GPIO1_G 0x00040000
-#define SICRL_GPIO1_H 0x00020000
-#define SICRL_GPIO1_I 0x00010000
-#define SICRL_GPIO1_J 0x00008000
-#define SICRL_GPIO1_K 0x00004000
-#define SICRL_GPIO1_L 0x00003000
-
-/* SICRH bits - MPC8349 specific */
-#define SICRH_DDR 0x80000000
-#define SICRH_TSEC1_A 0x10000000
-#define SICRH_TSEC1_B 0x08000000
-#define SICRH_TSEC1_C 0x04000000
-#define SICRH_TSEC1_D 0x02000000
-#define SICRH_TSEC1_E 0x01000000
-#define SICRH_TSEC1_F 0x00800000
-#define SICRH_TSEC2_A 0x00400000
-#define SICRH_TSEC2_B 0x00200000
-#define SICRH_TSEC2_C 0x00100000
-#define SICRH_TSEC2_D 0x00080000
-#define SICRH_TSEC2_E 0x00040000
-#define SICRH_TSEC2_F 0x00020000
-#define SICRH_TSEC2_G 0x00010000
-#define SICRH_TSEC2_H 0x00008000
-#define SICRH_GPIO2_A 0x00004000
-#define SICRH_GPIO2_B 0x00002000
-#define SICRH_GPIO2_C 0x00001000
-#define SICRH_GPIO2_D 0x00000800
-#define SICRH_GPIO2_E 0x00000400
-#define SICRH_GPIO2_F 0x00000200
-#define SICRH_GPIO2_G 0x00000180
-#define SICRH_GPIO2_H 0x00000060
-#define SICRH_TSOBI1 0x00000002
-#define SICRH_TSOBI2 0x00000001
-
-#elif defined(CONFIG_ARCH_MPC8360)
+#if defined(CONFIG_ARCH_MPC8360)
/* SICRL bits - MPC8360 specific */
#define SICRL_LDP_A 0xC0000000
#define SICRL_LCLK_1 0x10000000
@@ -435,22 +358,13 @@
#define HRCWH_PCI_HOST_SHIFT 31
#define HRCWH_PCI_AGENT 0x00000000
-#if defined(CONFIG_ARCH_MPC834X)
-#define HRCWH_32_BIT_PCI 0x00000000
-#define HRCWH_64_BIT_PCI 0x40000000
-#endif
-
#define HRCWH_PCI1_ARBITER_DISABLE 0x00000000
#define HRCWH_PCI1_ARBITER_ENABLE 0x20000000
#define HRCWH_PCI_ARBITER_DISABLE 0x00000000
#define HRCWH_PCI_ARBITER_ENABLE 0x20000000
-#if defined(CONFIG_ARCH_MPC834X)
-#define HRCWH_PCI2_ARBITER_DISABLE 0x00000000
-#define HRCWH_PCI2_ARBITER_ENABLE 0x10000000
-
-#elif defined(CONFIG_ARCH_MPC8360)
+#if defined(CONFIG_ARCH_MPC8360)
#define HRCWH_PCICKDRV_DISABLE 0x00000000
#define HRCWH_PCICKDRV_ENABLE 0x10000000
#endif
@@ -470,9 +384,6 @@
#define HRCWH_ROM_LOC_DDR_SDRAM 0x00000000
#define HRCWH_ROM_LOC_PCI1 0x00100000
-#if defined(CONFIG_ARCH_MPC834X)
-#define HRCWH_ROM_LOC_PCI2 0x00200000
-#endif
#define HRCWH_ROM_LOC_LOCAL_8BIT 0x00500000
#define HRCWH_ROM_LOC_LOCAL_16BIT 0x00600000
#define HRCWH_ROM_LOC_LOCAL_32BIT 0x00700000
@@ -501,17 +412,6 @@
#define HRCWH_TSEC2M_IN_SGMII 0x00001800
#endif
-#if defined(CONFIG_ARCH_MPC834X)
-#define HRCWH_TSEC1M_IN_RGMII 0x00000000
-#define HRCWH_TSEC1M_IN_RTBI 0x00004000
-#define HRCWH_TSEC1M_IN_GMII 0x00008000
-#define HRCWH_TSEC1M_IN_TBI 0x0000C000
-#define HRCWH_TSEC2M_IN_RGMII 0x00000000
-#define HRCWH_TSEC2M_IN_RTBI 0x00001000
-#define HRCWH_TSEC2M_IN_GMII 0x00002000
-#define HRCWH_TSEC2M_IN_TBI 0x00003000
-#endif
-
#if defined(CONFIG_ARCH_MPC8360)
#define HRCWH_SECONDARY_DDR_DISABLE 0x00000000
#define HRCWH_SECONDARY_DDR_ENABLE 0x00000010
@@ -647,35 +547,7 @@
#define SCCR_PCICM 0x00010000
#define SCCR_PCICM_SHIFT 16
-#if defined(CONFIG_ARCH_MPC834X)
-/* SCCR bits - MPC834X specific */
-#define SCCR_TSEC1CM 0xc0000000
-#define SCCR_TSEC1CM_SHIFT 30
-#define SCCR_TSEC1CM_0 0x00000000
-#define SCCR_TSEC1CM_1 0x40000000
-#define SCCR_TSEC1CM_2 0x80000000
-#define SCCR_TSEC1CM_3 0xC0000000
-
-#define SCCR_TSEC2CM 0x30000000
-#define SCCR_TSEC2CM_SHIFT 28
-#define SCCR_TSEC2CM_0 0x00000000
-#define SCCR_TSEC2CM_1 0x10000000
-#define SCCR_TSEC2CM_2 0x20000000
-#define SCCR_TSEC2CM_3 0x30000000
-
-/* The MPH must have the same clock ratio as DR, unless its clock disabled */
-#define SCCR_USBMPHCM 0x00c00000
-#define SCCR_USBMPHCM_SHIFT 22
-#define SCCR_USBDRCM 0x00300000
-#define SCCR_USBDRCM_SHIFT 20
-#define SCCR_USBCM 0x00f00000
-#define SCCR_USBCM_SHIFT 20
-#define SCCR_USBCM_0 0x00000000
-#define SCCR_USBCM_1 0x00500000
-#define SCCR_USBCM_2 0x00A00000
-#define SCCR_USBCM_3 0x00F00000
-
-#elif defined(CONFIG_ARCH_MPC8308)
+#if defined(CONFIG_ARCH_MPC8308)
/* SCCR bits - MPC8308 specific */
#define SCCR_TSEC1CM 0xc0000000
#define SCCR_TSEC1CM_SHIFT 30
--
2.47.3
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH 22/26] powerpc: mpc85xx: Remove P1024 support
2026-10-09 19:36 [PATCH 00/26] powerpc: drop EOL boards and SoCs, take over maintenance Bradley Morgan
` (20 preceding siblings ...)
2026-10-09 19:36 ` [PATCH 21/26] powerpc: mpc83xx: Remove MPC834x support Bradley Morgan
@ 2026-10-09 19:37 ` Bradley Morgan
2026-10-09 19:37 ` [PATCH 23/26] powerpc: mpc85xx: Remove BSC9131 support Bradley Morgan
` (3 subsequent siblings)
25 siblings, 0 replies; 31+ messages in thread
From: Bradley Morgan @ 2026-10-09 19:37 UTC (permalink / raw)
To: Tom Rini, u-boot
Cc: Bradley Morgan, Marek Behún, Marek Mojík,
NXP i . MX U-Boot Team, Alexey Charkov, Anshul Dalal,
Daniel Golle, Fabio Estevam, Gaurav Jain, Ilias Apalodimas,
Jaehoon Chung, James Hilliard, Jerome Forissier, Johan Jonker,
Lukasz Majewski, Marek Vasut, Mario Six, Michael Walle,
Michal Simek, Neil Armstrong, Peng Fan, Pengpeng Hou,
Priyanka Jain, Quentin Schulz, Simon Glass, Stefano Babic,
Tanmay Kathpalia, Torsten Rupp, Vincent Jardin, Weijie Gao
NXP marks P1024 End of Life, and no target in the tree selects
ARCH_P1024. Its old RDB timing branch and SoC defaults still hang
around in the shared P1020 code.
Drop those paths.
Signed-off-by: Bradley Morgan <brads@mainlining.org>
---
arch/Kconfig | 2 +-
arch/powerpc/cpu/mpc85xx/Kconfig | 27 --------------------
arch/powerpc/cpu/mpc85xx/Makefile | 1 -
arch/powerpc/cpu/mpc8xxx/cpu.c | 1 -
arch/powerpc/include/asm/processor.h | 1 -
board/nxp/p1_p2_rdb_pc/README | 1 -
board/nxp/p1_p2_rdb_pc/ddr.c | 37 ----------------------------
doc/README.mpc85xx-sd-spi-boot | 1 -
8 files changed, 1 insertion(+), 70 deletions(-)
diff --git a/arch/Kconfig b/arch/Kconfig
index 8ea591cba4f..cb808df07f4 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -470,7 +470,7 @@ config SYS_IMMR
default 0xE0000000 if MPC83xx
default 0x01000000 if ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3
default 0xFFE00000 if ARCH_P1010 || ARCH_P1020 || \
- ARCH_P1021 || ARCH_P1024 || \
+ ARCH_P1021 || \
ARCH_P2020
default SYS_CCSRBAR_DEFAULT
help
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index fe1592d75aa..6cb37b8a378 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -392,29 +392,6 @@ config ARCH_P1021
imply CMD_REGINFO
imply SATA_SIL
-config ARCH_P1024
- bool
- select FSL_LAW
- select SYS_FSL_ERRATUM_A004508
- select SYS_FSL_ERRATUM_A005125
- select SYS_FSL_ERRATUM_ELBC_A001
- select SYS_FSL_ERRATUM_ESDHC111
- select FSL_PCIE_DISABLE_ASPM
- select FSL_PCIE_RESET
- select SYS_FSL_HAS_DDR3
- select SYS_FSL_HAS_SEC
- select SYS_FSL_RMU
- select SYS_FSL_SEC_BE
- select SYS_FSL_SEC_COMPAT_2
- select SYS_PPC_E500_USE_DEBUG_TLB
- select FSL_ELBC
- imply CMD_EEPROM
- imply CMD_NAND
- imply SATA
- imply CMD_PCI
- imply CMD_REGINFO
- imply SATA_SIL
-
config ARCH_P2020
bool
select BTB
@@ -710,7 +687,6 @@ config MAX_CPUS
default 2 if ARCH_B4420 || \
ARCH_P1020 || \
ARCH_P1021 || \
- ARCH_P1024 || \
ARCH_P2020 || \
ARCH_T1024
default 1
@@ -728,7 +704,6 @@ config SYS_CCSRBAR_DEFAULT
ARCH_P1010 || \
ARCH_P1020 || \
ARCH_P1021 || \
- ARCH_P1024 || \
ARCH_P2020
default 0xfe000000 if ARCH_B4420 || \
ARCH_B4860 || \
@@ -933,7 +908,6 @@ config SYS_FSL_NUM_LAWS
ARCH_P1010 || \
ARCH_P1020 || \
ARCH_P1021 || \
- ARCH_P1024 || \
ARCH_P2020
default 10 if ARCH_MPC8544
help
@@ -1042,7 +1016,6 @@ config SYS_PPC_E500_DEBUG_TLB
default 0 if ARCH_MPC8544
default 2 if ARCH_P1020 || \
ARCH_P1021 || \
- ARCH_P1024 || \
ARCH_P2020
default 3 if ARCH_P1010
help
diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile
index 9b7c02eae5f..5861f4bbe63 100644
--- a/arch/powerpc/cpu/mpc85xx/Makefile
+++ b/arch/powerpc/cpu/mpc85xx/Makefile
@@ -55,7 +55,6 @@ obj-$(CONFIG_ARCH_MPC8544) += mpc8544_serdes.o
obj-$(CONFIG_ARCH_P1010) += p1010_serdes.o
obj-$(CONFIG_ARCH_P1020) += p1021_serdes.o
obj-$(CONFIG_ARCH_P1021) += p1021_serdes.o
-obj-$(CONFIG_ARCH_P1024) += p1021_serdes.o
obj-$(CONFIG_ARCH_P2020) += p2020_serdes.o
obj-$(CONFIG_ARCH_P2041) += p2041_serdes.o
obj-$(CONFIG_ARCH_T4240) += t4240_serdes.o
diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c
index 046ab063700..3840cb42b76 100644
--- a/arch/powerpc/cpu/mpc8xxx/cpu.c
+++ b/arch/powerpc/cpu/mpc8xxx/cpu.c
@@ -45,7 +45,6 @@ static struct cpu_type cpu_type_list[] = {
CPU_TYPE_ENTRY(P1020, P1020, 2),
CPU_TYPE_ENTRY(P1021, P1021, 2),
CPU_TYPE_ENTRY(P1022, P1022, 2),
- CPU_TYPE_ENTRY(P1024, P1024, 2),
CPU_TYPE_ENTRY(P2010, P2010, 1),
CPU_TYPE_ENTRY(P2020, P2020, 2),
CPU_TYPE_ENTRY(P2040, P2040, 4),
diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h
index 01228bee20f..6c274c9ceef 100644
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -1033,7 +1033,6 @@
#define SVR_P1020 0x80E400
#define SVR_P1021 0x80E401
#define SVR_P1022 0x80E600
-#define SVR_P1024 0x80E402
#define SVR_P2010 0x80E300
#define SVR_P2020 0x80E200
#define SVR_P2040 0x821000
diff --git a/board/nxp/p1_p2_rdb_pc/README b/board/nxp/p1_p2_rdb_pc/README
index 5bf27816ab2..73226bd1a53 100644
--- a/board/nxp/p1_p2_rdb_pc/README
+++ b/board/nxp/p1_p2_rdb_pc/README
@@ -5,7 +5,6 @@ P1_P2_RDB_PC represents a set of boards including
P1020RDB-PC
P1020RDB-PD
P1021RDB-PC
- P1024RDB
They have similar design of P1020RDB but have DDR3 instead of DDR2.
diff --git a/board/nxp/p1_p2_rdb_pc/ddr.c b/board/nxp/p1_p2_rdb_pc/ddr.c
index 74c9c78c4e1..17138d92b0b 100644
--- a/board/nxp/p1_p2_rdb_pc/ddr.c
+++ b/board/nxp/p1_p2_rdb_pc/ddr.c
@@ -114,43 +114,6 @@ dimm_params_t ddr_raw_timing = {
.refresh_rate_ps = 7800000,
.tfaw_ps = 37500,
};
-#elif defined(CONFIG_TARGET_P1024RDB)
-/*
- * Samsung K4B2G0846C-HCH9
- * The following timing are for "downshift"
- * i.e. to use CL9 part as CL7
- * otherwise, tAA, tRCD, tRP will be 13500ps
- * and tRC will be 49500ps
- */
-dimm_params_t ddr_raw_timing = {
- .n_ranks = 1,
- .rank_density = 1073741824u,
- .capacity = 1073741824u,
- .primary_sdram_width = 32,
- .ec_sdram_width = 0,
- .registered_dimm = 0,
- .mirrored_dimm = 0,
- .n_row_addr = 15,
- .n_col_addr = 10,
- .n_banks_per_sdram_device = 8,
- .edc_config = 0,
- .burst_lengths_bitmask = 0x0c,
-
- .tckmin_x_ps = 1500,
- .caslat_x = 0x3e << 4, /* 5,6,7,8,9 */
- .taa_ps = 13125,
- .twr_ps = 15000,
- .trcd_ps = 13125,
- .trrd_ps = 6000,
- .trp_ps = 13125,
- .tras_ps = 36000,
- .trc_ps = 49125,
- .trfc_ps = 160000,
- .twtr_ps = 7500,
- .trtp_ps = 7500,
- .refresh_rate_ps = 7800000,
- .tfaw_ps = 30000,
-};
#else
#error Missing raw timing data for this board
#endif
diff --git a/doc/README.mpc85xx-sd-spi-boot b/doc/README.mpc85xx-sd-spi-boot
index c382e9bf7aa..ace40b2c7cf 100644
--- a/doc/README.mpc85xx-sd-spi-boot
+++ b/doc/README.mpc85xx-sd-spi-boot
@@ -63,6 +63,5 @@ P1020RDB config_ddr3_1gb_p1_p2_rdb_pc_800M.dat
P1010RDB config_ddr3_1gb_p1010rdb_800M.dat
P1021RDB config_ddr3_1gb_p1_p2_rdb_pc_800M.dat
P1022DS config_ddr3_2gb_p1022ds.dat
-P1024RDB config_ddr3_1gb_p1_p2_rdb_pc_667M.dat
P1020UTM config_ddr3_1gb_p1_p2_rdb_pc_800M.dat
P1020MBG config_ddr3_1gb_p1_p2_rdb_pc_800M.dat
--
2.47.3
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH 23/26] powerpc: mpc85xx: Remove BSC9131 support
2026-10-09 19:36 [PATCH 00/26] powerpc: drop EOL boards and SoCs, take over maintenance Bradley Morgan
` (21 preceding siblings ...)
2026-10-09 19:37 ` [PATCH 22/26] powerpc: mpc85xx: Remove P1024 support Bradley Morgan
@ 2026-10-09 19:37 ` Bradley Morgan
2026-10-09 19:37 ` [PATCH 24/26] powerpc: mpc83xx: Remove MPC8309 support Bradley Morgan
` (2 subsequent siblings)
25 siblings, 0 replies; 31+ messages in thread
From: Bradley Morgan @ 2026-10-09 19:37 UTC (permalink / raw)
To: Tom Rini, u-boot
Cc: Bradley Morgan, Marek Behún, Marek Mojík,
NXP i . MX U-Boot Team, Alexey Charkov, Anshul Dalal,
Daniel Golle, Fabio Estevam, Gaurav Jain, Ilias Apalodimas,
Jaehoon Chung, James Hilliard, Jerome Forissier, Johan Jonker,
Lukasz Majewski, Marek Vasut, Mario Six, Michael Walle,
Michal Simek, Neil Armstrong, Peng Fan, Pengpeng Hou,
Priyanka Jain, Quentin Schulz, Simon Glass, Stefano Babic,
Tanmay Kathpalia, Torsten Rupp, Vincent Jardin, Weijie Gao
NXP marks each BSC9131 part number End of Life. No target selects
ARCH_BSC9131, so its mux, LAW and reset register paths have no users.
Remove that family support.
Signed-off-by: Bradley Morgan <brads@mainlining.org>
---
arch/Kconfig.nxp | 3 +-
arch/powerpc/cpu/mpc85xx/Kconfig | 22 +----
arch/powerpc/cpu/mpc8xxx/cpu.c | 1 -
arch/powerpc/include/asm/fsl_law.h | 4 -
arch/powerpc/include/asm/immap_85xx.h | 116 --------------------------
board/nxp/common/sdhc_boot.c | 2 +-
boot/Kconfig | 2 +-
drivers/mmc/Kconfig | 2 +-
8 files changed, 6 insertions(+), 146 deletions(-)
diff --git a/arch/Kconfig.nxp b/arch/Kconfig.nxp
index 15e56ffb35a..e52ed3ddb21 100644
--- a/arch/Kconfig.nxp
+++ b/arch/Kconfig.nxp
@@ -286,8 +286,7 @@ config SYS_FSL_IFC_BANK_COUNT
depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A || \
ARCH_LS1088A || ARCH_LS1021A || ARCH_B4860 || ARCH_B4420 || \
ARCH_T4240 || ARCH_T1040 || ARCH_T1042 || ARCH_T1024 || \
- ARCH_T2080 || ARCH_P1010 || ARCH_BSC9131
- default 3 if ARCH_BSC9131
+ ARCH_T2080 || ARCH_P1010
default 4 if ARCH_LS1043A || ARCH_LS1046A || ARCH_B4860 || \
ARCH_B4420 || ARCH_P1010
default 8 if ARCH_LS2080A || ARCH_LS1088A || ARCH_LS1021A || \
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index 6cb37b8a378..6d5e81f47ac 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -281,22 +281,6 @@ config ARCH_B4860
imply CMD_NAND
imply CMD_REGINFO
-config ARCH_BSC9131
- bool
- select FSL_LAW
- select SYS_FSL_DDR_VER_44
- select SYS_FSL_ERRATUM_A004477
- select SYS_FSL_ERRATUM_A005125
- select SYS_FSL_ERRATUM_ESDHC111
- select SYS_FSL_HAS_DDR3
- select SYS_FSL_HAS_SEC
- select SYS_FSL_SEC_BE
- select SYS_FSL_SEC_COMPAT_4
- select FSL_IFC
- imply CMD_EEPROM
- imply CMD_NAND
- imply CMD_REGINFO
-
config ARCH_MPC8544
bool
select BTB
@@ -699,8 +683,7 @@ config MAX_CPUS
config SYS_CCSRBAR_DEFAULT
hex "Default CCSRBAR address"
- default 0xff700000 if ARCH_BSC9131 || \
- ARCH_MPC8544 || \
+ default 0xff700000 if ARCH_MPC8544 || \
ARCH_P1010 || \
ARCH_P1020 || \
ARCH_P1021 || \
@@ -904,8 +887,7 @@ config SYS_FSL_NUM_LAWS
default 16 if ARCH_T1024 || \
ARCH_T1040 || \
ARCH_T1042
- default 12 if ARCH_BSC9131 || \
- ARCH_P1010 || \
+ default 12 if ARCH_P1010 || \
ARCH_P1020 || \
ARCH_P1021 || \
ARCH_P2020
diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c
index 3840cb42b76..8ebef9d5991 100644
--- a/arch/powerpc/cpu/mpc8xxx/cpu.c
+++ b/arch/powerpc/cpu/mpc8xxx/cpu.c
@@ -77,7 +77,6 @@ static struct cpu_type cpu_type_list[] = {
CPU_TYPE_ENTRY(T2080, T2080, 0),
CPU_TYPE_ENTRY(T2081, T2081, 0),
CPU_TYPE_ENTRY(BSC9130, 9130, 1),
- CPU_TYPE_ENTRY(BSC9131, 9131, 1),
CPU_TYPE_ENTRY(BSC9232, 9232, 2),
CPU_TYPE_ENTRY(C291, C291, 1),
CPU_TYPE_ENTRY(C292, C292, 1),
diff --git a/arch/powerpc/include/asm/fsl_law.h b/arch/powerpc/include/asm/fsl_law.h
index bdef61bc80f..ce40fe31742 100644
--- a/arch/powerpc/include/asm/fsl_law.h
+++ b/arch/powerpc/include/asm/fsl_law.h
@@ -79,12 +79,8 @@ enum law_trgt_if {
LAW_TRGT_IF_PCI = 0x00,
LAW_TRGT_IF_PCI_2 = 0x01,
LAW_TRGT_IF_PCIE_1 = 0x02,
-#if defined(CONFIG_ARCH_BSC9131)
- LAW_TRGT_IF_OCN_DSP = 0x03,
-#else
#if !defined(CONFIG_ARCH_P2020)
LAW_TRGT_IF_PCIE_3 = 0x03,
-#endif
#endif
LAW_TRGT_IF_LBC = 0x04,
LAW_TRGT_IF_CCSR = 0x08,
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index e1167dbb3d7..45f96fefc62 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1726,11 +1726,7 @@ typedef struct ccsr_rcpm {
#else
typedef struct ccsr_gur {
u32 porpllsr; /* POR PLL ratio status */
-#if defined(CONFIG_ARCH_BSC9131)
-#define MPC85xx_PORPLLSR_DDR_RATIO 0x00003f00
-#else
#define MPC85xx_PORPLLSR_DDR_RATIO 0x00003e00
-#endif
#define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT 9
#define MPC85xx_PORPLLSR_QE_RATIO 0x3e000000
#define MPC85xx_PORPLLSR_QE_RATIO_SHIFT 25
@@ -1846,50 +1842,6 @@ typedef struct ccsr_gur {
#define MPC85xx_PMUXCR_QE10 0x00000020
#define MPC85xx_PMUXCR_QE11 0x00000010
#define MPC85xx_PMUXCR_QE12 0x00000008
-#if defined(CONFIG_ARCH_BSC9131)
-#define MPC85xx_PMUXCR_TSEC2_DMA_GPIO_IRQ 0x40000000
-#define MPC85xx_PMUXCR_TSEC2_USB 0xC0000000
-#define MPC85xx_PMUXCR_TSEC2_1588_PPS 0x10000000
-#define MPC85xx_PMUXCR_TSEC2_1588_RSVD 0x30000000
-#define MPC85xx_PMUXCR_IFC_AD_GPIO 0x04000000
-#define MPC85xx_PMUXCR_IFC_AD_GPIO_MASK 0x0C000000
-#define MPC85xx_PMUXCR_IFC_AD15_GPIO 0x01000000
-#define MPC85xx_PMUXCR_IFC_AD15_TIMER2 0x02000000
-#define MPC85xx_PMUXCR_IFC_AD16_GPO8 0x00400000
-#define MPC85xx_PMUXCR_IFC_AD16_MSRCID0 0x00800000
-#define MPC85xx_PMUXCR_IFC_AD17_GPO 0x00100000
-#define MPC85xx_PMUXCR_IFC_AD17_GPO_MASK 0x00300000
-#define MPC85xx_PMUXCR_IFC_AD17_MSRCID_DSP 0x00200000
-#define MPC85xx_PMUXCR_IFC_CS2_GPO65 0x00040000
-#define MPC85xx_PMUXCR_IFC_CS2_DSP_TDI 0x00080000
-#define MPC85xx_PMUXCR_SDHC_USIM 0x00010000
-#define MPC85xx_PMUXCR_SDHC_TDM_RFS_RCK 0x00020000
-#define MPC85xx_PMUXCR_SDHC_GPIO77 0x00030000
-#define MPC85xx_PMUXCR_SDHC_RESV 0x00004000
-#define MPC85xx_PMUXCR_SDHC_TDM_TXD_RXD 0x00008000
-#define MPC85xx_PMUXCR_SDHC_GPIO_TIMER4 0x0000C000
-#define MPC85xx_PMUXCR_USB_CLK_UART_SIN 0x00001000
-#define MPC85xx_PMUXCR_USB_CLK_GPIO69 0x00002000
-#define MPC85xx_PMUXCR_USB_CLK_TIMER3 0x00003000
-#define MPC85xx_PMUXCR_USB_UART_GPIO0 0x00000400
-#define MPC85xx_PMUXCR_USB_RSVD 0x00000C00
-#define MPC85xx_PMUXCR_USB_GPIO62_TRIG_IN 0x00000800
-#define MPC85xx_PMUXCR_USB_D1_2_IIC2_SDA_SCL 0x00000100
-#define MPC85xx_PMUXCR_USB_D1_2_GPIO71_72 0x00000200
-#define MPC85xx_PMUXCR_USB_D1_2_RSVD 0x00000300
-#define MPC85xx_PMUXCR_USB_DIR_GPIO2 0x00000040
-#define MPC85xx_PMUXCR_USB_DIR_TIMER1 0x00000080
-#define MPC85xx_PMUXCR_USB_DIR_MCP_B 0x000000C0
-#define MPC85xx_PMUXCR_SPI1_UART3 0x00000010
-#define MPC85xx_PMUXCR_SPI1_SIM 0x00000020
-#define MPC85xx_PMUXCR_SPI1_CKSTP_IN_GPO74 0x00000030
-#define MPC85xx_PMUXCR_SPI1_CS2_CKSTP_OUT_B 0x00000004
-#define MPC85xx_PMUXCR_SPI1_CS2_dbg_adi1_rxen 0x00000008
-#define MPC85xx_PMUXCR_SPI1_CS2_GPO75 0x0000000C
-#define MPC85xx_PMUXCR_SPI1_CS3_ANT_TCXO_PWM 0x00000001
-#define MPC85xx_PMUXCR_SPI1_CS3_dbg_adi2_rxen 0x00000002
-#define MPC85xx_PMUXCR_SPI1_CS3_GPO76 0x00000003
-#endif
u32 pmuxcr2; /* Alt. function signal multiplex control 2 */
#if defined(CONFIG_ARCH_P1010)
#define MPC85xx_PMUXCR2_UART_GPIO 0x40000000
@@ -1916,68 +1868,7 @@ typedef struct ccsr_gur {
#define MPC85xx_PMUXCR2_DEBUG_MUX_SEL_USBPHY 0x00002000
#define MPC85xx_PMUXCR2_PLL_LKDT_EXPOSE 0x00001000
#endif
-#if defined(CONFIG_ARCH_BSC9131)
-#define MPC85xx_PMUXCR2_UART_CTS_B0_SIM_PD 0x40000000
-#define MPC85xx_PMUXCR2_UART_CTS_B0_DSP_TMS 0x80000000
-#define MPC85xx_PMUXCR2_UART_CTS_B0_GPIO42 0xC0000000
-#define MPC85xx_PMUXCR2_UART_RTS_B0_PWM2 0x10000000
-#define MPC85xx_PMUXCR2_UART_RTS_B0_DSP_TCK 0x20000000
-#define MPC85xx_PMUXCR2_UART_RTS_B0_GPIO43 0x30000000
-#define MPC85xx_PMUXCR2_UART_CTS_B1_SIM_PD 0x04000000
-#define MPC85xx_PMUXCR2_UART_CTS_B1_SRESET_B 0x08000000
-#define MPC85xx_PMUXCR2_UART_CTS_B1_GPIO44 0x0C000000
-#define MPC85xx_PMUXCR2_UART_RTS_B1_PPS_LED 0x01000000
-#define MPC85xx_PMUXCR2_UART_RTS_B1_RSVD 0x02000000
-#define MPC85xx_PMUXCR2_UART_RTS_B1_GPIO45 0x03000000
-#define MPC85xx_PMUXCR2_TRIG_OUT_ASLEEP 0x00400000
-#define MPC85xx_PMUXCR2_TRIG_OUT_DSP_TRST_B 0x00800000
-#define MPC85xx_PMUXCR2_ANT1_TIMER5 0x00100000
-#define MPC85xx_PMUXCR2_ANT1_TSEC_1588 0x00200000
-#define MPC85xx_PMUXCR2_ANT1_GPIO95_19 0x00300000
-#define MPC85xx_PMUXCR2_ANT1_TX_RX_FRAME_MAX3_LOCK 0x00040000
-#define MPC85xx_PMUXCR2_ANT1_TX_RX_FRAME_RSVD 0x00080000
-#define MPC85xx_PMUXCR2_ANT1_TX_RX_FRAME_GPIO80_20 0x000C0000
-#define MPC85xx_PMUXCR2_ANT1_DIO0_3_SPI3_CS0 0x00010000
-#define MPC85xx_PMUXCR2_ANT1_DIO0_3_ANT2_DO_3 0x00020000
-#define MPC85xx_PMUXCR2_ANT1_DIO0_3_GPIO81_84 0x00030000
-#define MPC85xx_PMUXCR2_ANT1_DIO4_7_SPI4 0x00004000
-#define MPC85xx_PMUXCR2_ANT1_DIO4_7_ANT2_DO4_7 0x00008000
-#define MPC85xx_PMUXCR2_ANT1_DIO4_7_GPIO85_88 0x0000C000
-#define MPC85xx_PMUXCR2_ANT1_DIO8_9_MAX2_1_LOCK 0x00001000
-#define MPC85xx_PMUXCR2_ANT1_DIO8_9_ANT2_DO8_9 0x00002000
-#define MPC85xx_PMUXCR2_ANT1_DIO8_9_GPIO21_22 0x00003000
-#define MPC85xx_PMUXCR2_ANT1_DIO10_11_TIMER6_7 0x00000400
-#define MPC85xx_PMUXCR2_ANT1_DIO10_11_ANT2_DO10_11 0x00000800
-#define MPC85xx_PMUXCR2_ANT1_DIO10_11_GPIO23_24 0x00000C00
-#define MPC85xx_PMUXCR2_ANT2_RSVD 0x00000100
-#define MPC85xx_PMUXCR2_ANT2_GPO90_91_DMA 0x00000300
-#define MPC85xx_PMUXCR2_ANT2_ENABLE_DIO0_10_USB 0x00000040
-#define MPC85xx_PMUXCR2_ANT2_ENABLE_DIO0_10_GPIO 0x000000C0
-#define MPC85xx_PMUXCR2_ANT2_DIO11_RSVD 0x00000010
-#define MPC85xx_PMUXCR2_ANT2_DIO11_TIMER8 0x00000020
-#define MPC85xx_PMUXCR2_ANT2_DIO11_GPIO61 0x00000030
-#define MPC85xx_PMUXCR2_ANT3_AGC_GPO53 0x00000004
-#define MPC85xx_PMUXCR2_ANT3_DO_TDM 0x00000001
-#define MPC85xx_PMUXCR2_ANT3_DO_GPIO46_49 0x00000002
- u32 pmuxcr3;
-#define MPC85xx_PMUXCR3_ANT3_DO4_5_TDM 0x40000000
-#define MPC85xx_PMUXCR3_ANT3_DO4_5_GPIO_50_51 0x80000000
-#define MPC85xx_PMUXCR3_ANT3_DO6_7_TRIG_IN_SRESET_B 0x10000000
-#define MPC85xx_PMUXCR3_ANT3_DO6_7_GPIO_52_53 0x20000000
-#define MPC85xx_PMUXCR3_ANT3_DO8_MCP_B 0x04000000
-#define MPC85xx_PMUXCR3_ANT3_DO8_GPIO54 0x08000000
-#define MPC85xx_PMUXCR3_ANT3_DO9_10_CKSTP_IN_OUT 0x01000000
-#define MPC85xx_PMUXCR3_ANT3_DO9_10_GPIO55_56 0x02000000
-#define MPC85xx_PMUXCR3_ANT3_DO11_IRQ_OUT 0x00400000
-#define MPC85xx_PMUXCR3_ANT3_DO11_GPIO57 0x00800000
-#define MPC85xx_PMUXCR3_SPI2_CS2_GPO93 0x00100000
-#define MPC85xx_PMUXCR3_SPI2_CS3_GPO94 0x00040000
-#define MPC85xx_PMUXCR3_ANT2_AGC_RSVD 0x00010000
-#define MPC85xx_PMUXCR3_ANT2_GPO89 0x00030000
- u32 pmuxcr4;
-#else
u8 res6[8];
-#endif
u32 devdisr; /* Device disable control */
#define MPC85xx_DEVDISR_PCI1 0x80000000
#define MPC85xx_DEVDISR_PCI2 0x40000000
@@ -2027,14 +1918,7 @@ typedef struct ccsr_gur {
u32 ddrdllcr; /* DDR DLL control */
u8 res14[12];
u32 lbcdllcr; /* LBC DLL control */
-#if defined(CONFIG_ARCH_BSC9131)
- u8 res15[12];
- u32 halt_req_mask;
-#define HALTED_TO_HALT_REQ_MASK_0 0x80000000
- u8 res18[232];
-#else
u8 res15[248];
-#endif
u32 lbiuiplldcr0; /* LBIU PLL Debug Reg 0 */
u32 lbiuiplldcr1; /* LBIU PLL Debug Reg 1 */
u32 ddrioovcr; /* DDR IO Override Control */
diff --git a/board/nxp/common/sdhc_boot.c b/board/nxp/common/sdhc_boot.c
index 16b6f0fc343..d49064f23f0 100644
--- a/board/nxp/common/sdhc_boot.c
+++ b/board/nxp/common/sdhc_boot.c
@@ -45,7 +45,7 @@ int mmc_get_env_addr(struct mmc *mmc, int copy, u64 *env_addr)
#ifdef CONFIG_ESDHC_HC_BLK_ADDR
/*
- * On P1010 and BSC9131:
+ * On P1010:
* In High Capacity SD Cards (> 2 GBytes), the 32-bit source address and
* code length of these soc specify the memory address in block address
* format. Block length is fixed to 512 bytes as per the SD High
diff --git a/boot/Kconfig b/boot/Kconfig
index 0fc550c3e01..63828e5e005 100644
--- a/boot/Kconfig
+++ b/boot/Kconfig
@@ -1199,7 +1199,7 @@ config FSL_FIXED_MMC_LOCATION
config ESDHC_HC_BLK_ADDR
def_bool y
- depends on FSL_FIXED_MMC_LOCATION && (ARCH_BSC9131 || ARCH_P1010)
+ depends on FSL_FIXED_MMC_LOCATION && ARCH_P1010
help
In High Capacity SD Cards (> 2 GBytes), the 32-bit source address and
code length of these soc specify the memory address in block address
diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index 671cae7aaf2..7a690721b91 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -911,7 +911,7 @@ config FSL_SDHC_V2_3
config FSL_ESDHC
bool "Freescale/NXP eSDHC controller support"
depends on ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3 || PPC
- select FSL_SDHC_V2_3 if ARCH_P1010 || ARCH_BSC9131
+ select FSL_SDHC_V2_3 if ARCH_P1010
help
This selects support for the eSDHC (Enhanced Secure Digital Host
Controller) found on numerous Freescale/NXP SoCs.
--
2.47.3
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH 24/26] powerpc: mpc83xx: Remove MPC8309 support
2026-10-09 19:36 [PATCH 00/26] powerpc: drop EOL boards and SoCs, take over maintenance Bradley Morgan
` (22 preceding siblings ...)
2026-10-09 19:37 ` [PATCH 23/26] powerpc: mpc85xx: Remove BSC9131 support Bradley Morgan
@ 2026-10-09 19:37 ` Bradley Morgan
2026-10-09 19:37 ` [PATCH 25/26] powerpc: Remove MPC86xx support Bradley Morgan
2026-10-09 19:37 ` [PATCH 26/26] MAINTAINERS: powerpc: Add me as PowerPC maintainer Bradley Morgan
25 siblings, 0 replies; 31+ messages in thread
From: Bradley Morgan @ 2026-10-09 19:37 UTC (permalink / raw)
To: Tom Rini, u-boot
Cc: Bradley Morgan, Marek Behún, Marek Mojík,
NXP i . MX U-Boot Team, Alexey Charkov, Anshul Dalal,
Daniel Golle, Fabio Estevam, Gaurav Jain, Ilias Apalodimas,
Jaehoon Chung, James Hilliard, Jerome Forissier, Johan Jonker,
Lukasz Majewski, Marek Vasut, Mario Six, Michael Walle,
Michal Simek, Neil Armstrong, Peng Fan, Pengpeng Hou,
Priyanka Jain, Quentin Schulz, Simon Glass, Stefano Babic,
Tanmay Kathpalia, Torsten Rupp, Vincent Jardin, Weijie Gao
NXP marks MPC8309 End of Life. No board selects this SoC, but the
CPU, clock and GPIO match tables still accepted it.
Remove those stale entries.
Signed-off-by: Bradley Morgan <brads@mainlining.org>
---
arch/powerpc/cpu/mpc83xx/cpu.c | 1 -
arch/powerpc/include/asm/arch-mpc83xx/soc.h | 7 ++-----
doc/device-tree-bindings/clock/fsl,mpc83xx-clk.txt | 1 -
doc/device-tree-bindings/cpu/fsl,mpc83xx.txt | 1 -
doc/device-tree-bindings/gpio/fsl,mpc83xx-spisel-boot.txt | 4 ++--
drivers/clk/mpc83xx_clk.c | 7 +++----
drivers/cpu/mpc83xx_cpu.c | 4 ----
drivers/cpu/mpc83xx_cpu.h | 3 ---
drivers/gpio/mpc83xx_spisel_boot.c | 1 -
drivers/qe/qe.c | 1 -
include/mpc83xx.h | 1 -
11 files changed, 7 insertions(+), 24 deletions(-)
diff --git a/arch/powerpc/cpu/mpc83xx/cpu.c b/arch/powerpc/cpu/mpc83xx/cpu.c
index 7583121eb12..4117f3aa6af 100644
--- a/arch/powerpc/cpu/mpc83xx/cpu.c
+++ b/arch/powerpc/cpu/mpc83xx/cpu.c
@@ -47,7 +47,6 @@ int checkcpu(void)
u32 partid;
} cpu_type_list [] = {
CPU_TYPE_ENTRY(8308),
- CPU_TYPE_ENTRY(8309),
CPU_TYPE_ENTRY(8321),
CPU_TYPE_ENTRY(8323),
CPU_TYPE_ENTRY(8358_TBGA_),
diff --git a/arch/powerpc/include/asm/arch-mpc83xx/soc.h b/arch/powerpc/include/asm/arch-mpc83xx/soc.h
index 0473389bc7d..eb82bb9e810 100644
--- a/arch/powerpc/include/asm/arch-mpc83xx/soc.h
+++ b/arch/powerpc/include/asm/arch-mpc83xx/soc.h
@@ -9,15 +9,13 @@
enum soc_type {
SOC_MPC8308,
- SOC_MPC8309,
SOC_MPC832X,
SOC_MPC8360,
};
static inline bool mpc83xx_has_sdhc(int type)
{
- return (type == SOC_MPC8308) ||
- (type == SOC_MPC8309);
+ return type == SOC_MPC8308;
}
static inline bool mpc83xx_has_tsec(int type)
@@ -42,8 +40,7 @@ static inline bool mpc83xx_has_second_i2c(int type)
static inline bool mpc83xx_has_quicc_engine(int type)
{
- return (type == SOC_MPC8309) ||
- (type == SOC_MPC832X) ||
+ return (type == SOC_MPC832X) ||
(type == SOC_MPC8360);
}
diff --git a/doc/device-tree-bindings/clock/fsl,mpc83xx-clk.txt b/doc/device-tree-bindings/clock/fsl,mpc83xx-clk.txt
index 213123dbab4..6c38a3254e8 100644
--- a/doc/device-tree-bindings/clock/fsl,mpc83xx-clk.txt
+++ b/doc/device-tree-bindings/clock/fsl,mpc83xx-clk.txt
@@ -5,7 +5,6 @@ system.
Required properties:
- compatible: must be one of "fsl,mpc8308-clk",
- "fsl,mpc8309-clk",
"fsl,mpc832x-clk",
"fsl,mpc8360-clk"
depending on which SoC is employed
diff --git a/doc/device-tree-bindings/cpu/fsl,mpc83xx.txt b/doc/device-tree-bindings/cpu/fsl,mpc83xx.txt
index 5acb2c403c9..6e0052869d3 100644
--- a/doc/device-tree-bindings/cpu/fsl,mpc83xx.txt
+++ b/doc/device-tree-bindings/cpu/fsl,mpc83xx.txt
@@ -5,7 +5,6 @@ MPC83xx SoCs contain a e300 core as their main processor.
Required properties:
- compatible: must be one of "fsl,mpc83xx",
"fsl,mpc8308",
- "fsl,mpc8309",
"fsl,mpc832x",
"fsl,mpc8360"
- clocks: has to have two entries, which must be the core clock at index 0 and
diff --git a/doc/device-tree-bindings/gpio/fsl,mpc83xx-spisel-boot.txt b/doc/device-tree-bindings/gpio/fsl,mpc83xx-spisel-boot.txt
index 52d8bb0a5cb..bdec12d1035 100644
--- a/doc/device-tree-bindings/gpio/fsl,mpc83xx-spisel-boot.txt
+++ b/doc/device-tree-bindings/gpio/fsl,mpc83xx-spisel-boot.txt
@@ -7,14 +7,14 @@ The SPISEL_BOOT signal is always an output.
Required properties:
-- compatible: must be "fsl,mpc83xx-spisel-boot" or "fsl,mpc8309-spisel-boot".
+- compatible: must be "fsl,mpc83xx-spisel-boot".
- reg: must point to the SPI_CS register in the SoC register map.
- ngpios: number of gpios provided by driver, normally 1.
Example:
spisel_boot: spisel_boot@14c {
- compatible = "fsl,mpc8309-spisel-boot";
+ compatible = "fsl,mpc83xx-spisel-boot";
reg = <0x14c 0x04>;
#gpio-cells = <2>;
device_type = "gpio";
diff --git a/drivers/clk/mpc83xx_clk.c b/drivers/clk/mpc83xx_clk.c
index 4b2f1705b64..924c0d452a3 100644
--- a/drivers/clk/mpc83xx_clk.c
+++ b/drivers/clk/mpc83xx_clk.c
@@ -47,7 +47,7 @@ static inline bool is_clk_valid(struct udevice *clk, int id)
case MPC83XX_CLK_MEM_SEC:
return type == SOC_MPC8360;
case MPC83XX_CLK_ENC:
- return (type == SOC_MPC8308) || (type == SOC_MPC8309);
+ return type == SOC_MPC8308;
case MPC83XX_CLK_I2C1:
return true;
case MPC83XX_CLK_TDM:
@@ -66,7 +66,7 @@ static inline bool is_clk_valid(struct udevice *clk, int id)
case MPC83XX_CLK_SATA:
return false;
case MPC83XX_CLK_DMAC:
- return (type == SOC_MPC8308) || (type == SOC_MPC8309);
+ return type == SOC_MPC8308;
case MPC83XX_CLK_PCI:
/*
* FIXME: implement proper support for this.
@@ -78,7 +78,7 @@ static inline bool is_clk_valid(struct udevice *clk, int id)
return mpc83xx_has_second_i2c(type);
case MPC83XX_CLK_QE:
case MPC83XX_CLK_BRG:
- return mpc83xx_has_quicc_engine(type) && (type != SOC_MPC8309);
+ return mpc83xx_has_quicc_engine(type);
case MPC83XX_CLK_LCLK:
case MPC83XX_CLK_LBIU:
case MPC83XX_CLK_CORE:
@@ -318,7 +318,6 @@ const struct clk_ops mpc83xx_clk_ops = {
static const struct udevice_id mpc83xx_clk_match[] = {
{ .compatible = "fsl,mpc8308-clk", .data = SOC_MPC8308 },
- { .compatible = "fsl,mpc8309-clk", .data = SOC_MPC8309 },
{ .compatible = "fsl,mpc832x-clk", .data = SOC_MPC832X },
{ .compatible = "fsl,mpc8360-clk", .data = SOC_MPC8360 },
{ /* sentinel */ }
diff --git a/drivers/cpu/mpc83xx_cpu.c b/drivers/cpu/mpc83xx_cpu.c
index 56b192ca153..5d5611bd0e4 100644
--- a/drivers/cpu/mpc83xx_cpu.c
+++ b/drivers/cpu/mpc83xx_cpu.c
@@ -99,9 +99,6 @@ static inline void determine_type(const struct udevice *dev)
case 0x8100:
priv->type = TYPE_8308;
break;
- case 0x8110:
- priv->type = TYPE_8309;
- break;
case 0x8066:
priv->type = TYPE_8321;
break;
@@ -284,7 +281,6 @@ static int mpc83xx_cpu_probe(struct udevice *dev)
static const struct udevice_id mpc83xx_cpu_ids[] = {
{ .compatible = "fsl,mpc83xx", },
{ .compatible = "fsl,mpc8308", },
- { .compatible = "fsl,mpc8309", },
{ .compatible = "fsl,mpc832x", },
{ .compatible = "fsl,mpc8360", },
{ /* sentinel */ }
diff --git a/drivers/cpu/mpc83xx_cpu.h b/drivers/cpu/mpc83xx_cpu.h
index f86b36114ab..002e753734f 100644
--- a/drivers/cpu/mpc83xx_cpu.h
+++ b/drivers/cpu/mpc83xx_cpu.h
@@ -49,7 +49,6 @@ enum mpc83xx_cpu_family {
/**
* enum mpc83xx_cpu_type - Identifiers for MPC83xx CPU types
* @TYPE_8308: Identifier for the MPC8308 CPU type
- * @TYPE_8309: Identifier for the MPC8309 CPU type
* @TYPE_8321: Identifier for the MPC8321 CPU type
* @TYPE_8323: Identifier for the MPC8323 CPU type
* @TYPE_8358_TBGA: Identifier for the MPC8358 CPU type (Tape Ball Grid Array
@@ -61,7 +60,6 @@ enum mpc83xx_cpu_family {
*/
enum mpc83xx_cpu_type {
TYPE_8308,
- TYPE_8309,
TYPE_8321,
TYPE_8323,
TYPE_8358_TBGA,
@@ -73,7 +71,6 @@ enum mpc83xx_cpu_type {
/* Array mapping the MCP83xx CPUs to their human-readable names */
static const char * const cpu_type_names[] = {
[TYPE_8308] = "8308",
- [TYPE_8309] = "8309",
[TYPE_8321] = "8321",
[TYPE_8323] = "8323",
[TYPE_8358_TBGA] = "8358_TBGA",
diff --git a/drivers/gpio/mpc83xx_spisel_boot.c b/drivers/gpio/mpc83xx_spisel_boot.c
index 2be8c73ae3d..220e04218e0 100644
--- a/drivers/gpio/mpc83xx_spisel_boot.c
+++ b/drivers/gpio/mpc83xx_spisel_boot.c
@@ -129,7 +129,6 @@ static const struct dm_gpio_ops mpc83xx_spisel_boot_ops = {
};
static const struct udevice_id mpc83xx_spisel_boot_ids[] = {
- { .compatible = "fsl,mpc8309-spisel-boot" },
{ .compatible = "fsl,mpc83xx-spisel-boot" },
{ /* sentinel */ }
};
diff --git a/drivers/qe/qe.c b/drivers/qe/qe.c
index 25880db37cf..107a3e78f99 100644
--- a/drivers/qe/qe.c
+++ b/drivers/qe/qe.c
@@ -120,7 +120,6 @@ static void qe_sdma_init(void)
* we just need to know what the SNUMs are for the threads.
*/
static u8 thread_snum[] = {
-/* Evthreads 16-29 are not supported in MPC8309 */
0x04, 0x05, 0x0c, 0x0d,
0x14, 0x15, 0x1c, 0x1d,
0x24, 0x25, 0x2c, 0x2d,
diff --git a/include/mpc83xx.h b/include/mpc83xx.h
index d570ba61b7f..b46c038f16e 100644
--- a/include/mpc83xx.h
+++ b/include/mpc83xx.h
@@ -51,7 +51,6 @@
#define SPR_FAMILY(spridr) ((spridr & 0xFFF00000) >> 20)
#define SPR_8308 0x8100
-#define SPR_8309 0x8110
#define SPR_832X_FAMILY 0x806
#define SPR_8321 0x8066
#define SPR_8323 0x8062
--
2.47.3
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH 25/26] powerpc: Remove MPC86xx support
2026-10-09 19:36 [PATCH 00/26] powerpc: drop EOL boards and SoCs, take over maintenance Bradley Morgan
` (23 preceding siblings ...)
2026-10-09 19:37 ` [PATCH 24/26] powerpc: mpc83xx: Remove MPC8309 support Bradley Morgan
@ 2026-10-09 19:37 ` Bradley Morgan
2026-10-09 19:37 ` [PATCH 26/26] MAINTAINERS: powerpc: Add me as PowerPC maintainer Bradley Morgan
25 siblings, 0 replies; 31+ messages in thread
From: Bradley Morgan @ 2026-10-09 19:37 UTC (permalink / raw)
To: Tom Rini, u-boot
Cc: Bradley Morgan, Marek Behún, Marek Mojík,
NXP i . MX U-Boot Team, Alexey Charkov, Anshul Dalal,
Daniel Golle, Fabio Estevam, Gaurav Jain, Ilias Apalodimas,
Jaehoon Chung, James Hilliard, Jerome Forissier, Johan Jonker,
Lukasz Majewski, Marek Vasut, Mario Six, Michael Walle,
Michal Simek, Neil Armstrong, Peng Fan, Pengpeng Hou,
Priyanka Jain, Quentin Schulz, Simon Glass, Stefano Babic,
Tanmay Kathpalia, Torsten Rupp, Vincent Jardin, Weijie Gao
No target in the tree selects MPC86xx, and NXP lists the MPC8610 as End of Life and the MPC8641D as No Longer Manufactured. Its CPU, PCI and DMA paths have no consumer. Remove them.
Signed-off-by: Bradley Morgan <brads@mainlining.org>
---
api/api_platform-powerpc.c | 2 +-
arch/powerpc/cpu/Makefile | 1 -
arch/powerpc/cpu/mpc8xxx/Makefile | 1 -
arch/powerpc/cpu/mpc8xxx/cpu.c | 8 +-------
arch/powerpc/cpu/mpc8xxx/fdt.c | 8 +++-----
arch/powerpc/cpu/mpc8xxx/srio.c | 6 ------
arch/powerpc/include/asm/config.h | 1 -
arch/powerpc/include/asm/fsl_lbc.h | 2 +-
arch/powerpc/include/asm/fsl_pci.h | 7 -------
arch/powerpc/include/asm/global_data.h | 7 +++----
arch/powerpc/include/asm/ppc.h | 14 +-------------
arch/powerpc/include/asm/processor.h | 18 ++----------------
arch/powerpc/lib/bdinfo.c | 2 +-
arch/powerpc/lib/bootm.c | 7 -------
arch/powerpc/lib/ppccache.S | 4 ++--
arch/powerpc/lib/stack.c | 2 +-
common/board_r.c | 2 +-
drivers/ddr/fsl/Kconfig | 3 +--
drivers/ddr/fsl/ctrl_regs.c | 1 -
drivers/dma/fsl_dma.c | 4 ----
drivers/gpio/mpc8xxx_gpio.c | 1 -
drivers/pci/Kconfig | 2 +-
env/Kconfig | 2 +-
include/asm-generic/u-boot.h | 2 +-
include/fsl_immap.h | 2 +-
include/pci_ids.h | 4 ----
include/serial.h | 1 -
27 files changed, 22 insertions(+), 92 deletions(-)
diff --git a/api/api_platform-powerpc.c b/api/api_platform-powerpc.c
index 2c1ab043af6..f789cf40ba1 100644
--- a/api/api_platform-powerpc.c
+++ b/api/api_platform-powerpc.c
@@ -28,7 +28,7 @@ int platform_sys_info(struct sys_info *si)
si->clk_bus = gd->bus_clk;
si->clk_cpu = gd->cpu_clk;
-#if defined(CONFIG_MPC8xx) || defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
+#if defined(CONFIG_MPC8xx) || defined(CONFIG_E500)
#define bi_bar bi_immr_base
#elif defined(CONFIG_MPC83xx)
#define bi_bar bi_immrbar
diff --git a/arch/powerpc/cpu/Makefile b/arch/powerpc/cpu/Makefile
index e7f64059277..1a2b6fafa4b 100644
--- a/arch/powerpc/cpu/Makefile
+++ b/arch/powerpc/cpu/Makefile
@@ -2,4 +2,3 @@
obj-$(CONFIG_MPC83xx) += mpc8xxx/
obj-$(CONFIG_MPC85xx) += mpc8xxx/
-obj-$(CONFIG_MPC86xx) += mpc8xxx/
diff --git a/arch/powerpc/cpu/mpc8xxx/Makefile b/arch/powerpc/cpu/mpc8xxx/Makefile
index a44b5165d74..5373398cf6f 100644
--- a/arch/powerpc/cpu/mpc8xxx/Makefile
+++ b/arch/powerpc/cpu/mpc8xxx/Makefile
@@ -18,7 +18,6 @@ obj-$(CONFIG_FSL_LAW) += law.o
else
obj-$(CONFIG_MPC85xx) += cpu.o
-obj-$(CONFIG_MPC86xx) += cpu.o
obj-$(CONFIG_OF_LIBFDT) += fdt.o
obj-$(CONFIG_FSL_LBC) += fsl_lbc.o
diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c
index 8ebef9d5991..f87fb1b807e 100644
--- a/arch/powerpc/cpu/mpc8xxx/cpu.c
+++ b/arch/powerpc/cpu/mpc8xxx/cpu.c
@@ -2,9 +2,7 @@
/*
* Copyright 2009-2012 Freescale Semiconductor, Inc.
*
- * This file is derived from arch/powerpc/cpu/mpc85xx/cpu.c and
- * arch/powerpc/cpu/mpc86xx/cpu.c. Basically this file contains
- * cpu specific common code for 85xx/86xx processors.
+ * This file contains CPU-specific code for MPC85xx processors.
*/
#include <config.h>
@@ -81,10 +79,6 @@ static struct cpu_type cpu_type_list[] = {
CPU_TYPE_ENTRY(C291, C291, 1),
CPU_TYPE_ENTRY(C292, C292, 1),
CPU_TYPE_ENTRY(C293, C293, 1),
-#elif defined(CONFIG_MPC86xx)
- CPU_TYPE_ENTRY(8610, 8610, 1),
- CPU_TYPE_ENTRY(8641, 8641, 2),
- CPU_TYPE_ENTRY(8641D, 8641D, 2),
#endif
};
diff --git a/arch/powerpc/cpu/mpc8xxx/fdt.c b/arch/powerpc/cpu/mpc8xxx/fdt.c
index f1c1cbc1c3c..692f89e04c6 100644
--- a/arch/powerpc/cpu/mpc8xxx/fdt.c
+++ b/arch/powerpc/cpu/mpc8xxx/fdt.c
@@ -3,9 +3,7 @@
* Copyright 2009-2014 Freescale Semiconductor, Inc.
* Copyright 2020 NXP
*
- * This file is derived from arch/powerpc/cpu/mpc85xx/cpu.c and
- * arch/powerpc/cpu/mpc86xx/cpu.c. Basically this file contains
- * cpu specific common code for 85xx/86xx processors.
+ * This file contains CPU-specific common code for MPC85xx processors.
*/
#include <cpu_func.h>
@@ -16,7 +14,7 @@
#include <phy.h>
#include <hwconfig.h>
-#if defined(CONFIG_MP) && (defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx))
+#if defined(CONFIG_MP) && defined(CONFIG_MPC85xx)
static int ft_del_cpuhandle(void *blob, int cpuhandle)
{
int off, ret = -FDT_ERR_NOTFOUND;
@@ -68,7 +66,7 @@ void ft_fixup_num_cores(void *blob) {
debug ("deleted %d extra core entry entries from device tree\n",
del_cores);
}
-#endif /* defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) */
+#endif /* defined(CONFIG_MP) && defined(CONFIG_MPC85xx) */
int fdt_fixup_phy_connection(void *blob, int offset, phy_interface_t phyc)
{
diff --git a/arch/powerpc/cpu/mpc8xxx/srio.c b/arch/powerpc/cpu/mpc8xxx/srio.c
index 0c7288c7574..652411fc3b3 100644
--- a/arch/powerpc/cpu/mpc8xxx/srio.c
+++ b/arch/powerpc/cpu/mpc8xxx/srio.c
@@ -39,12 +39,6 @@
#define _DEVDISR_SRIO2 MPC85xx_DEVDISR_SRIO
#define _DEVDISR_RMU MPC85xx_DEVDISR_RMSG
#define CFG_SYS_MPC8xxx_GUTS_ADDR CFG_SYS_MPC85xx_GUTS_ADDR
-#elif defined(CONFIG_MPC86xx)
- #define _DEVDISR_SRIO1 MPC86xx_DEVDISR_SRIO
- #define _DEVDISR_SRIO2 MPC86xx_DEVDISR_SRIO
- #define _DEVDISR_RMU MPC86xx_DEVDISR_RMSG
- #define CFG_SYS_MPC8xxx_GUTS_ADDR \
- (&((immap_t *)CONFIG_SYS_IMMR)->im_gur)
#else
#error "No defines for DEVDISR_SRIO"
#endif
diff --git a/arch/powerpc/include/asm/config.h b/arch/powerpc/include/asm/config.h
index 7e53dcf8af5..6dee08c0493 100644
--- a/arch/powerpc/include/asm/config.h
+++ b/arch/powerpc/include/asm/config.h
@@ -16,7 +16,6 @@
#ifndef CFG_MAX_MEM_MAPPED
#if defined(CONFIG_E500) || \
- defined(CONFIG_MPC86xx) || \
defined(CONFIG_E300)
#define CFG_MAX_MEM_MAPPED ((phys_size_t)2 << 30)
#else
diff --git a/arch/powerpc/include/asm/fsl_lbc.h b/arch/powerpc/include/asm/fsl_lbc.h
index 37da14c45f1..19dd5c94d60 100644
--- a/arch/powerpc/include/asm/fsl_lbc.h
+++ b/arch/powerpc/include/asm/fsl_lbc.h
@@ -310,7 +310,7 @@ void lbc_sdram_init(void);
#define LCRR_EADC_2 0x00020000
#define LCRR_EADC_3 0x00030000
#define LCRR_EADC_4 0x00000000
-/* CLKDIV is five bits only on 8536, 8572, and 8610, so far, but the fifth bit
+/* CLKDIV is five bits only on 8536 and 8572, so far, but the fifth bit
* should always be zero on older parts that have a four bit CLKDIV.
*/
#define LCRR_CLKDIV 0x0000001F
diff --git a/arch/powerpc/include/asm/fsl_pci.h b/arch/powerpc/include/asm/fsl_pci.h
index 6c6e436b6ee..fc7b1779230 100644
--- a/arch/powerpc/include/asm/fsl_pci.h
+++ b/arch/powerpc/include/asm/fsl_pci.h
@@ -258,13 +258,6 @@ int fsl_pcie_init_board(int busno);
FT_FSL_PCIE1_SETUP; \
FT_FSL_PCIE2_SETUP; \
FT_FSL_PCIE3_SETUP;
-#elif defined(CONFIG_MPC86xx)
-#define FSL_PCI_COMPAT "fsl,mpc8610-pci"
-#define FSL_PCIE_COMPAT "fsl,mpc8641-pcie"
-#define FT_FSL_PCI_SETUP \
- FT_FSL_PCI1_SETUP; \
- FT_FSL_PCIE1_SETUP; \
- FT_FSL_PCIE2_SETUP;
#else
#error FT_FSL_PCI_SETUP not defined
#endif
diff --git a/arch/powerpc/include/asm/global_data.h b/arch/powerpc/include/asm/global_data.h
index 710d538dad9..0d091fad418 100644
--- a/arch/powerpc/include/asm/global_data.h
+++ b/arch/powerpc/include/asm/global_data.h
@@ -44,12 +44,11 @@ struct arch_global_data {
# endif /* CONFIG_ARCH_MPC8360 */
#endif
#endif
-#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
+#if defined(CONFIG_MPC85xx)
u32 lbc_clk;
void *cpu;
-#endif /* CONFIG_MPC85xx || CONFIG_MPC86xx */
-#if defined(CONFIG_MPC83xx) || defined(CONFIG_MPC85xx) || \
- defined(CONFIG_MPC86xx)
+#endif /* CONFIG_MPC85xx */
+#if defined(CONFIG_MPC83xx) || defined(CONFIG_MPC85xx)
u32 i2c1_clk;
u32 i2c2_clk;
#endif
diff --git a/arch/powerpc/include/asm/ppc.h b/arch/powerpc/include/asm/ppc.h
index 2923350bd7b..740bcd910eb 100644
--- a/arch/powerpc/include/asm/ppc.h
+++ b/arch/powerpc/include/asm/ppc.h
@@ -50,9 +50,7 @@ static inline uint get_svr(void)
return mfspr(SVR);
}
-#if defined(CONFIG_MPC85xx) || \
- defined(CONFIG_MPC86xx) || \
- defined(CONFIG_MPC83xx)
+#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC83xx)
unsigned char in8(unsigned int);
void out8(unsigned int, unsigned char);
unsigned short in16(unsigned int);
@@ -84,17 +82,7 @@ void get_sys_info(sys_info_t *);
void ft_fixup_cpu(void *, u64);
void ft_fixup_num_cores(void *);
#endif
-#if defined(CONFIG_MPC86xx)
-ulong get_bus_freq(ulong);
-typedef MPC86xx_SYS_INFO sys_info_t;
-void get_sys_info(sys_info_t *);
-static inline ulong get_ddr_freq(ulong dummy)
-{
- return get_bus_freq(dummy);
-}
-#else
ulong get_ddr_freq(ulong);
-#endif
static inline unsigned long get_msr(void)
{
diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h
index 6c274c9ceef..59c9e7a76a6 100644
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -569,11 +569,6 @@
#define MCSR_IMPE 0x00800000 /* Imprecise Machine Check Exception */
#define ESR_ST 0x00800000 /* Store Operation */
-#if defined(CONFIG_MPC86xx)
-#define SPRN_MSSCR0 0x3f6
-#define SPRN_MSSSR0 0x3f7
-#endif
-
#define SPRN_HDBCR0 0x3d0
#define SPRN_HDBCR1 0x3d1
#define SPRN_HDBCR2 0x3d2
@@ -646,10 +641,7 @@
#define L2CR SPRN_L2CR /* PPC 750 L2 control register */
#define LR SPRN_LR
#define MBAR SPRN_MBAR /* System memory base address */
-#if defined(CONFIG_MPC86xx)
-#define MSSCR0 SPRN_MSSCR0
-#endif
-#if defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
+#if defined(CONFIG_E500)
#define PIR SPRN_PIR
#endif
#define SVR SPRN_SVR /* System-On-Chip Version Register */
@@ -959,8 +951,6 @@
#define PVR_VER_E5500 0x8024
#define PVR_VER_E6500 0x8040
-#define PVR_86xx 0x80040000
-
#define PVR_VIRTEX5 0x7ff21912
/*
@@ -1065,10 +1055,6 @@
#define SVR_T2080 0x853000
#define SVR_T2081 0x853100
-#define SVR_8610 0x80A000
-#define SVR_8641 0x809000
-#define SVR_8641D 0x809001
-
#define SVR_9130 0x860001
#define SVR_9131 0x860000
#define SVR_9232 0x861400
@@ -1138,7 +1124,7 @@ int fixup_cpu(void);
int fsl_qoriq_core_to_cluster(unsigned int core);
int fsl_qoriq_dsp_core_to_cluster(unsigned int core);
-#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
+#if defined(CONFIG_MPC85xx)
#define CPU_TYPE_ENTRY(n, v, nc) \
{ .name = #n, .soc_ver = SVR_##v, .num_cores = (nc), \
.mask = (1 << (nc)) - 1 }
diff --git a/arch/powerpc/lib/bdinfo.c b/arch/powerpc/lib/bdinfo.c
index 6491c210f4e..7c2b1746d0d 100644
--- a/arch/powerpc/lib/bdinfo.c
+++ b/arch/powerpc/lib/bdinfo.c
@@ -15,7 +15,7 @@ int arch_setup_bdinfo(void)
{
struct bd_info *bd = gd->bd;
-#if defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
+#if defined(CONFIG_E500)
bd->bi_immr_base = CONFIG_SYS_IMMR; /* base of IMMR register */
#endif
diff --git a/arch/powerpc/lib/bootm.c b/arch/powerpc/lib/bootm.c
index f9351a17a48..9b0ce9c4b81 100644
--- a/arch/powerpc/lib/bootm.c
+++ b/arch/powerpc/lib/bootm.c
@@ -21,7 +21,6 @@
#include <u-boot/zlib.h>
#include <bzlib.h>
#include <asm/byteorder.h>
-#include <asm/mp.h>
#include <bootm.h>
#include <vxworks.h>
@@ -237,12 +236,6 @@ void boot_prep_vxworks(struct bootm_headers *images)
#if defined(CONFIG_MPC85xx)
ft_fixup_cpu(images->ft_addr, base + size);
ft_fixup_num_cores(images->ft_addr);
-#elif defined(CONFIG_MPC86xx)
- off = fdt_add_mem_rsv(images->ft_addr,
- determine_mp_bootpg(NULL), (u64)4096);
- if (off < 0)
- printf("## WARNING %s: %s\n", __func__, fdt_strerror(off));
- ft_fixup_num_cores(images->ft_addr);
#endif
flush_cache((unsigned long)images->ft_addr, images->ft_len);
#endif
diff --git a/arch/powerpc/lib/ppccache.S b/arch/powerpc/lib/ppccache.S
index e94b40ead63..b2bed5c17fb 100644
--- a/arch/powerpc/lib/ppccache.S
+++ b/arch/powerpc/lib/ppccache.S
@@ -64,7 +64,7 @@ ppcSync:
* flush_dcache_range(unsigned long start, unsigned long stop)
*/
_GLOBAL(flush_dcache_range)
-#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
+#if defined(CONFIG_MPC85xx)
li r5,L1_CACHE_BYTES-1
andc r3,r3,r5
subf r4,r3,r4
@@ -88,7 +88,7 @@ _GLOBAL(flush_dcache_range)
* invalidate_dcache_range(unsigned long start, unsigned long stop)
*/
_GLOBAL(invalidate_dcache_range)
-#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
+#if defined(CONFIG_MPC85xx)
li r5,L1_CACHE_BYTES-1
andc r3,r3,r5
subf r4,r3,r4
diff --git a/arch/powerpc/lib/stack.c b/arch/powerpc/lib/stack.c
index afd869e4ac3..232f9758bf5 100644
--- a/arch/powerpc/lib/stack.c
+++ b/arch/powerpc/lib/stack.c
@@ -33,7 +33,7 @@ int arch_reserve_stacks(void)
int arch_setup_dest_addr(void)
{
-#if defined(CONFIG_MP) && (defined(CONFIG_MPC86xx) || defined(CONFIG_E500))
+#if defined(CONFIG_MP) && defined(CONFIG_E500)
/*
* We need to make sure the location we intend to put secondary core
* boot code is reserved and not used by any part of u-boot
diff --git a/common/board_r.c b/common/board_r.c
index a397e20959d..d1b9663aa5b 100644
--- a/common/board_r.c
+++ b/common/board_r.c
@@ -129,7 +129,7 @@ static int initr_reloc_global_data(void)
#elif !defined(CONFIG_SANDBOX) && !defined(CONFIG_NIOS2)
monitor_flash_len = (ulong)__init_end - gd->relocaddr;
#endif
-#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
+#if defined(CONFIG_MPC85xx)
/*
* The gd->cpu pointer is set to an address in flash before relocation.
* We need to update it to point to the same CPU entry in RAM.
diff --git a/drivers/ddr/fsl/Kconfig b/drivers/ddr/fsl/Kconfig
index 7a3aa7e2087..c4b7ec768e8 100644
--- a/drivers/ddr/fsl/Kconfig
+++ b/drivers/ddr/fsl/Kconfig
@@ -93,7 +93,6 @@ config SYS_FSL_DDRC_GEN1
config SYS_FSL_DDRC_GEN2
bool
- depends on !MPC86xx
help
Enable Freescale DDR2 controller.
@@ -150,7 +149,7 @@ config SYS_FSL_DDR2
bool "Freescale DDR2 controller"
depends on SYS_FSL_HAS_DDR2
imply DDR_SPD
- select SYS_FSL_DDRC_GEN2 if (!MPC86xx && !SYS_FSL_DDRC_GEN3)
+ select SYS_FSL_DDRC_GEN2 if !SYS_FSL_DDRC_GEN3
config SYS_FSL_DDR1
bool "Freescale DDR1 controller"
diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c
index fea08c9000f..e8dc6890330 100644
--- a/drivers/ddr/fsl/ctrl_regs.c
+++ b/drivers/ddr/fsl/ctrl_regs.c
@@ -42,7 +42,6 @@
* 4 = 20 ohm
* 5 = 30 ohm
*
- * FIXME: Apparently 8641 needs a value of 2
* FIXME: Old code seys if 667 MHz or higher, use 3 on 8572
*
* FIXME: There was some effort down this line earlier:
diff --git a/drivers/dma/fsl_dma.c b/drivers/dma/fsl_dma.c
index e5d242f4f8f..44ba63f2930 100644
--- a/drivers/dma/fsl_dma.c
+++ b/drivers/dma/fsl_dma.c
@@ -25,8 +25,6 @@
dma83xx_t *dma_base = (void *)(CFG_SYS_MPC83xx_DMA_ADDR);
#elif defined(CONFIG_MPC85xx)
ccsr_dma_t *dma_base = (void *)(CFG_SYS_MPC85xx_DMA_ADDR);
-#elif defined(CONFIG_MPC86xx)
-ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC86xx_DMA_ADDR);
#else
#error "Freescale DMA engine not supported on your processor"
#endif
@@ -35,8 +33,6 @@ static void dma_sync(void)
{
#if defined(CONFIG_MPC85xx)
asm("sync; isync; msync");
-#elif defined(CONFIG_MPC86xx)
- asm("sync; isync");
#endif
}
diff --git a/drivers/gpio/mpc8xxx_gpio.c b/drivers/gpio/mpc8xxx_gpio.c
index 40646407369..bfa62be9dc7 100644
--- a/drivers/gpio/mpc8xxx_gpio.c
+++ b/drivers/gpio/mpc8xxx_gpio.c
@@ -316,7 +316,6 @@ static const struct udevice_id mpc8xxx_gpio_ids[] = {
{ .compatible = "fsl,mpc8308-gpio", .data = MPC8XXX_GPIO_TYPE },
{ .compatible = "fsl,mpc8349-gpio", .data = MPC8XXX_GPIO_TYPE },
{ .compatible = "fsl,mpc8572-gpio", .data = MPC8XXX_GPIO_TYPE},
- { .compatible = "fsl,mpc8610-gpio", .data = MPC8XXX_GPIO_TYPE},
{ .compatible = "fsl,mpc5121-gpio", .data = MPC5121_GPIO_TYPE, },
{ .compatible = "fsl,qoriq-gpio", .data = MPC8XXX_GPIO_TYPE },
{ /* sentinel */ }
diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index 86fafc5a3c7..c32cf344f81 100644
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -187,7 +187,7 @@ config PCIE_FSL
depends on PPC
help
Say Y here if you want to enable PCIe controller support on FSL
- PowerPC MPC85xx, MPC86xx, B series, P series and T series SoCs.
+ PowerPC MPC85xx, B series, P series and T series SoCs.
This driver does not support SRIO_PCIE_BOOT feature.
config PCI_MPC85XX
diff --git a/env/Kconfig b/env/Kconfig
index fa4cf30af39..08fa5a4ecd0 100644
--- a/env/Kconfig
+++ b/env/Kconfig
@@ -155,7 +155,7 @@ config ENV_IS_IN_FLASH
default y if ARCH_INTEGRATOR_CP
default y if M548x || M547x || M5282
default y if MCF532x || MCF52x2
- default y if MPC86xx || MPC83xx
+ default y if MPC83xx
default y if SH && !CPU_SH4
help
Define this if you have a flash device which you want to use for the
diff --git a/include/asm-generic/u-boot.h b/include/asm-generic/u-boot.h
index 931fe2f3274..ead690f6c65 100644
--- a/include/asm-generic/u-boot.h
+++ b/include/asm-generic/u-boot.h
@@ -35,7 +35,7 @@ struct bd_info {
unsigned long bi_dsp_freq; /* dsp core frequency */
unsigned long bi_ddr_freq; /* ddr frequency */
#endif
-#if defined(CONFIG_MPC8xx) || defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
+#if defined(CONFIG_MPC8xx) || defined(CONFIG_E500)
unsigned long bi_immr_base; /* base of IMMR register */
#endif
#if defined(CONFIG_M68K)
diff --git a/include/fsl_immap.h b/include/fsl_immap.h
index 54d6e0ab377..ea5d214e499 100644
--- a/include/fsl_immap.h
+++ b/include/fsl_immap.h
@@ -12,7 +12,7 @@
/*
* DDR memory controller registers
- * This structure works for mpc83xx (DDR2 and DDR3), mpc85xx, mpc86xx.
+ * This structure works for mpc83xx (DDR2 and DDR3) and mpc85xx.
*/
struct ccsr_ddr {
u32 cs0_bnds; /* Chip Select 0 Memory Bounds */
diff --git a/include/pci_ids.h b/include/pci_ids.h
index cfff275daba..96e84a779ff 100644
--- a/include/pci_ids.h
+++ b/include/pci_ids.h
@@ -2509,10 +2509,6 @@
#define PCI_DEVICE_ID_P5020 0x0421
#define PCI_DEVICE_ID_P5010E 0x0428
#define PCI_DEVICE_ID_P5010 0x0429
-#define PCI_DEVICE_ID_MPC8641 0x7010
-#define PCI_DEVICE_ID_MPC8641D 0x7011
-#define PCI_DEVICE_ID_MPC8610 0x7018
-
#define PCI_VENDOR_ID_PASEMI 0x1959
#define PCI_VENDOR_ID_ATTANSIC 0x1969
diff --git a/include/serial.h b/include/serial.h
index 0a707ca730d..0b0179e6c0b 100644
--- a/include/serial.h
+++ b/include/serial.h
@@ -28,7 +28,6 @@ extern struct serial_device serial_scc_device;
extern struct serial_device *default_serial_console(void);
#if defined(CONFIG_MPC83xx) || defined(CONFIG_MPC85xx) || \
- defined(CONFIG_MPC86xx) || \
defined(CONFIG_ARCH_TEGRA) || defined(CONFIG_SYS_COREBOOT) || \
defined(CONFIG_MICROBLAZE)
extern struct serial_device serial0_device;
--
2.47.3
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH 26/26] MAINTAINERS: powerpc: Add me as PowerPC maintainer
2026-10-09 19:36 [PATCH 00/26] powerpc: drop EOL boards and SoCs, take over maintenance Bradley Morgan
` (24 preceding siblings ...)
2026-10-09 19:37 ` [PATCH 25/26] powerpc: Remove MPC86xx support Bradley Morgan
@ 2026-10-09 19:37 ` Bradley Morgan
25 siblings, 0 replies; 31+ messages in thread
From: Bradley Morgan @ 2026-10-09 19:37 UTC (permalink / raw)
To: Tom Rini, u-boot
Cc: Bradley Morgan, Marek Behún, Marek Mojík,
NXP i . MX U-Boot Team, Alexey Charkov, Anshul Dalal,
Daniel Golle, Fabio Estevam, Gaurav Jain, Ilias Apalodimas,
Jaehoon Chung, James Hilliard, Jerome Forissier, Johan Jonker,
Lukasz Majewski, Marek Vasut, Mario Six, Michael Walle,
Michal Simek, Neil Armstrong, Peng Fan, Pengpeng Hou,
Priyanka Jain, Quentin Schulz, Simon Glass, Stefano Babic,
Tanmay Kathpalia, Torsten Rupp, Vincent Jardin, Weijie Gao
PowerPC has been orphaned since 2022. Add me as maintainer.
Signed-off-by: Bradley Morgan <brads@mainlining.org>
---
MAINTAINERS | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index d1f51d9197d..1d331ce92d1 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1450,7 +1450,8 @@ F: drivers/power/
F: include/power/
POWERPC
-S: Orphan (Since 2022-10-21)
+M: Bradley Morgan <brads@mainlining.org>
+S: Maintained
F: arch/powerpc/
POWERPC MPC8XX
--
2.47.3
^ permalink raw reply related [flat|nested] 31+ messages in thread
* Re: [PATCH 02/26] board: powerpc: Remove MPC837XERDB support
2026-10-09 19:36 ` [PATCH 02/26] board: powerpc: Remove MPC837XERDB support Bradley Morgan
@ 2026-10-09 20:18 ` Bradley Morgan
0 siblings, 0 replies; 31+ messages in thread
From: Bradley Morgan @ 2026-10-09 20:18 UTC (permalink / raw)
To: Tom Rini, u-boot
Cc: Marek Behún, Marek Mojík, NXP i . MX U-Boot Team,
Alexey Charkov, Anshul Dalal, Daniel Golle, Fabio Estevam,
Gaurav Jain, Ilias Apalodimas, Jaehoon Chung, James Hilliard,
Jerome Forissier, Johan Jonker, Lukasz Majewski, Marek Vasut,
Mario Six, Michael Walle, Michal Simek, Neil Armstrong, Peng Fan,
Pengpeng Hou, Priyanka Jain, Quentin Schulz, Simon Glass,
Stefano Babic, Tanmay Kathpalia, Torsten Rupp, Vincent Jardin,
Weijie Gao, sinan
On 9 October 2026 20:36:40 BST, Bradley Morgan <brads@mainlining.org>
wrote:
>NXP marks the MPC8377ERDB as archived and no longer manufactured. Drop
>this target and its board files.
>
+ Cc sinan@writeme.com
>Signed-off-by: Bradley Morgan <brads@mainlining.org>
>---
> arch/powerpc/cpu/mpc83xx/Kconfig | 7 -
> arch/powerpc/dts/Makefile | 1 -
> arch/powerpc/dts/mpc8379erdb.dts | 153 ------------------
> board/nxp/mpc837xerdb/Kconfig | 15 --
> board/nxp/mpc837xerdb/MAINTAINERS | 6 -
> board/nxp/mpc837xerdb/Makefile | 6 -
> board/nxp/mpc837xerdb/README | 97 -----------
> board/nxp/mpc837xerdb/mpc837xerdb.c | 242 ----------------------------
> configs/MPC837XERDB_defconfig | 193 ----------------------
> include/configs/MPC837XERDB.h | 218 -------------------------
> 10 files changed, 938 deletions(-)
> delete mode 100644 arch/powerpc/dts/mpc8379erdb.dts
> delete mode 100644 board/nxp/mpc837xerdb/Kconfig
> delete mode 100644 board/nxp/mpc837xerdb/MAINTAINERS
> delete mode 100644 board/nxp/mpc837xerdb/Makefile
> delete mode 100644 board/nxp/mpc837xerdb/README
> delete mode 100644 board/nxp/mpc837xerdb/mpc837xerdb.c
> delete mode 100644 configs/MPC837XERDB_defconfig
> delete mode 100644 include/configs/MPC837XERDB.h
>
>diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig
>index 0dc72c87423..088283d646c 100644
>--- a/arch/powerpc/cpu/mpc83xx/Kconfig
>+++ b/arch/powerpc/cpu/mpc83xx/Kconfig
>@@ -24,12 +24,6 @@ config TARGET_CMPCPRO
> bool "Support CMPCPRO board from CSSI"
> select ARCH_MPC832X
>
>-config TARGET_MPC837XERDB
>- bool "Support MPC837XERDB"
>- select ARCH_MPC837X
>- select BOARD_EARLY_INIT_F
>- select SYS_83XX_DDR_USES_CS0
>-
> config TARGET_KMETER1
> bool "Support kmeter1"
> select VENDOR_KM
>@@ -208,7 +202,6 @@ config FSL_SERDES
> config NEVER_ASSERT_ODT_TO_CPU
> bool "Never assert ODT to internal IOs"
>
>-source "board/nxp/mpc837xerdb/Kconfig"
> source "board/gdsys/mpc8308/Kconfig"
> source "board/cssi/cmpcpro/Kconfig"
>
>diff --git a/arch/powerpc/dts/Makefile b/arch/powerpc/dts/Makefile
>index 2540684307e..01191273269 100644
>--- a/arch/powerpc/dts/Makefile
>+++ b/arch/powerpc/dts/Makefile
>@@ -7,7 +7,6 @@ dtb-$(CONFIG_TARGET_KMOPTI2) += kmopti2.dtb
> dtb-$(CONFIG_TARGET_KMSUPX5) += kmsupc5.dtb kmsupm5.dtb
> dtb-$(CONFIG_TARGET_KMTEGR1) += kmtegr1.dtb
> dtb-$(CONFIG_TARGET_KMTEPR2) += kmtepr2.dtb
>-dtb-$(CONFIG_TARGET_MPC837XERDB) += mpc8379erdb.dtb
> dtb-$(CONFIG_TARGET_P1010RDB_PA) += p1010rdb-pa.dtb p1010rdb-pa_36b.dtb
> dtb-$(CONFIG_TARGET_P1010RDB_PB) += p1010rdb-pb.dtb p1010rdb-pb_36b.dtb
> dtb-$(CONFIG_TARGET_P1020RDB_PC) += p1020rdb-pc.dtb p1020rdb-pc_36b.dtb
>diff --git a/arch/powerpc/dts/mpc8379erdb.dts b/arch/powerpc/dts/mpc8379erdb.dts
>deleted file mode 100644
>index 3db5ececaec..00000000000
>--- a/arch/powerpc/dts/mpc8379erdb.dts
>+++ /dev/null
>@@ -1,153 +0,0 @@
>-// SPDX-License-Identifier: GPL-2.0+ OR X11
>-/*
>- * MPC8379E RDB Device Tree Source
>- *
>- * Copyright 2020 NXP
>- */
>-
>-/dts-v1/;
>-
>-/ {
>- compatible = "fsl,mpc8379erdb";
>-
>- #address-cells = <1>;
>- #size-cells = <1>;
>-
>- aliases {
>- serial0 = &serial0;
>- serial1 = &serial1;
>- };
>-
>- cpus {
>- #address-cells = <1>;
>- #size-cells = <0>;
>-
>- PowerPC,8379@0 {
>- device_type = "cpu";
>- reg = <0x0>;
>- d-cache-line-size = <32>;
>- i-cache-line-size = <32>;
>- d-cache-size = <32768>;
>- i-cache-size = <32768>;
>- timebase-frequency = <0>;
>- bus-frequency = <0>;
>- clock-frequency = <0>;
>- };
>- };
>-
>- memory {
>- device_type = "memory";
>- reg = <0x00000000 0x10000000>; // 256MB at 0
>- };
>-
>- localbus@e0005000 {
>- #address-cells = <2>;
>- #size-cells = <1>;
>- compatible = "fsl,elbc", "simple-bus";
>- reg = <0xe0005000 0x1000>;
>- interrupts = <77 0x8>;
>- interrupt-parent = <&ipic>;
>- };
>-
>- immr@e0000000 {
>- #address-cells = <1>;
>- #size-cells = <1>;
>- device_type = "soc";
>- compatible = "simple-bus";
>- ranges = <0 0xe0000000 0x00100000>;
>- reg = <0xe0000000 0x00000200>;
>- bus-frequency = <0>;
>-
>- sdhc@2e000 {
>- compatible = "fsl,esdhc";
>- reg = <0x2e000 0x1000>;
>- bus-width = <0x4>;
>- clock-frequency = <0>;
>- };
>-
>- serial0: serial@4500 {
>- cell-index = <0>;
>- device_type = "serial";
>- compatible = "fsl,ns16550", "ns16550";
>- reg = <0x4500 0x100>;
>- clock-frequency = <333333000>;
>- interrupts = <9 0x8>;
>- interrupt-parent = <&ipic>;
>- bootph-all;
>- };
>-
>- serial1: serial@4600 {
>- cell-index = <1>;
>- device_type = "serial";
>- compatible = "fsl,ns16550", "ns16550";
>- reg = <0x4600 0x100>;
>- clock-frequency = <333333000>;
>- interrupts = <10 0x8>;
>- interrupt-parent = <&ipic>;
>- bootph-all;
>- };
>-
>- ipic: interrupt-controller@700 {
>- compatible = "fsl,ipic";
>- interrupt-controller;
>- #address-cells = <0>;
>- #interrupt-cells = <2>;
>- reg = <0x700 0x100>;
>- device_type = "ipic";
>- };
>-
>- usb@23000 {
>- compatible = "fsl-usb2-dr";
>- reg = <0x23000 0x1000>;
>- #address-cells = <1>;
>- #size-cells = <0>;
>- interrupt-parent = <&ipic>;
>- interrupts = <38 0x8>;
>- phy_type = "ulpi";
>- };
>-
>- enet0: ethernet@24000 {
>- #address-cells = <1>;
>- #size-cells = <1>;
>- cell-index = <0>;
>- device_type = "network";
>- model = "eTSEC";
>- compatible = "fsl,etsec2";
>- reg = <0x24000 0x1000>;
>- ranges = <0x0 0x24000 0x1000>;
>- local-mac-address = [ 00 00 00 00 00 00 ];
>- interrupts = <32 0x8 33 0x8 34 0x8>;
>- phy-connection-type = "mii";
>- interrupt-parent = <&ipic>;
>- fixed-link = <1 0 1000 0 0>;
>- phy-handle = <&phy>;
>- fsl,magic-packet;
>-
>- mdio@520 {
>- #address-cells = <1>;
>- #size-cells = <0>;
>- compatible = "fsl,etsec2-mdio";
>- reg = <0x520 0x20>;
>-
>- phy: ethernet-phy@2 {
>- interrupt-parent = <&ipic>;
>- interrupts = <17 0x8>;
>- reg = <0x2>;
>- device_type = "ethernet-phy";
>- };
>- };
>- };
>-
>- pci0: pci@e0008300 {
>- #address-cells = <3>;
>- #size-cells = <2>;
>- #interrupt-cells = <1>;
>- device_type = "pci";
>- reg = <0x0 0xe0008300 0x0 0x00000fff>;
>- compatible = "fsl,mpc837x-pci";
>- clock-frequency = <0>;
>- };
>-
>- };
>-
>-};
>diff --git a/board/nxp/mpc837xerdb/Kconfig b/board/nxp/mpc837xerdb/Kconfig
>deleted file mode 100644
>index f11f6f5bfea..00000000000
>--- a/board/nxp/mpc837xerdb/Kconfig
>+++ /dev/null
>@@ -1,15 +0,0 @@
>-if TARGET_MPC837XERDB
>-
>-config PCIE
>- def_bool y
>-
>-config SYS_BOARD
>- default "mpc837xerdb"
>-
>-config SYS_VENDOR
>- default "nxp"
>-
>-config SYS_CONFIG_NAME
>- default "MPC837XERDB"
>-
>-endif
>diff --git a/board/nxp/mpc837xerdb/MAINTAINERS b/board/nxp/mpc837xerdb/MAINTAINERS
>deleted file mode 100644
>index cc0a6acd8c3..00000000000
>--- a/board/nxp/mpc837xerdb/MAINTAINERS
>+++ /dev/null
>@@ -1,6 +0,0 @@
>-MPC837XERDB BOARD
>-M: Sinan Akman <sinan@writeme.com>
>-S: Maintained
>-F: board/nxp/mpc837xerdb/
>-F: include/configs/MPC837XERDB.h
>-F: configs/MPC837XERDB_defconfig
>diff --git a/board/nxp/mpc837xerdb/Makefile b/board/nxp/mpc837xerdb/Makefile
>deleted file mode 100644
>index 4661e4cf232..00000000000
>--- a/board/nxp/mpc837xerdb/Makefile
>+++ /dev/null
>@@ -1,6 +0,0 @@
>-# SPDX-License-Identifier: GPL-2.0+
>-#
>-# (C) Copyright 2006
>-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
>-
>-obj-y += mpc837xerdb.o
>diff --git a/board/nxp/mpc837xerdb/README b/board/nxp/mpc837xerdb/README
>deleted file mode 100644
>index 12df2f2e756..00000000000
>--- a/board/nxp/mpc837xerdb/README
>+++ /dev/null
>@@ -1,97 +0,0 @@
>-Freescale MPC837xE-RDB Board
>------------------------------------------
>-
>-1. Board Description
>-
>- The MPC837xE-RDB are reference boards featuring the Freescale MPC8377E,
>- MPC8378E, and the MPC8379E processors in a Mini-ITX form factor.
>-
>- The MPC837xE-RDB's have the following common features:
>-
>- A) 256-MBytes on-board DDR2 unbuffered SDRAM
>- B) 8-Mbytes NOR Flash
>- C) 32-MBytes NAND Flash
>- D) 1 Secure Digital High Speed Card (SDHC) Interface
>- E) 1 Gigabit Ethernet
>- F) 5-port Ethernet switch (Vitesse 7385)
>- G) 1 32-bit, 3.3 V, PCI slot
>- H) 1 32-bit, 3.3 V, Mini-PCI slot
>- I) 4-port USB 2.0 Hub
>- J) 1-port OTG USB
>- K) 2 serial ports (top main console)
>- L) on board Oscillator: 66M
>-
>- The MPC837xE-RDB's have the following differences:
>-
>- MPC8377E-RDB MPC8378E-RDB MPC8379E-RDB
>- SATA controllers 2 0 4
>- PCI-Express (mini) 2 2 0
>- SGMII Ports 0 2 0
>-
>-
>-2. Memory Map
>-
>-2.1. The memory map should look pretty much like this:
>-
>- Address Range Device Size Port Size
>- (Bytes) (Bits)
>- =========================== ================= ======= =========
>- 0x0000_0000 0x0fff_ffff DDR 256M 64
>- 0x1000_0000 0x7fff_ffff Empty 1.75G -
>- 0x8000_0000 0x8fff_ffff PCI MEM prefetch 256M 32
>- 0x9000_0000 0x9fff_ffff PCI MEM non-prefetch 256M 32
>- 0xe030_0000 0xe03f_ffff PCI I/O space 1M 32
>- 0xe000_0000 0xe00f_ffff Int Mem Reg Space 1M -
>- 0xe060_0000 0xe060_7fff NAND Flash 32K 8
>- 0xfe00_0000 0xfe7f_ffff NOR Flash on CS0 8M 16
>-
>-
>-3. Definitions
>-
>-3.1 Explanation of NEW definitions in:
>-
>- include/configs/MPC837XERDB.h
>-
>- CONFIG_MPC83xx MPC83xx family for both MPC8349 and MPC8360
>- CONFIG_MPC837x MPC837x specific
>- CONFIG_MPC837XERDB MPC837xE-RDB board specific
>-
>-
>-4. Compilation
>-
>- Assuming you're using BASH shell:
>-
>- export CROSS_COMPILE=your-cross-compile-prefix
>- cd u-boot
>- make distclean
>- make MPC837XERDB_config
>- make
>-
>-
>-5. Downloading and Flashing Images
>-
>-5.0 Download over serial line using Kermit:
>-
>- loadb $loadaddr
>- [Drop to kermit:
>- ^\c
>- send <u-boot-bin-image>
>- c
>- ]
>-
>-
>- Or via tftp:
>-
>- tftp $loadaddr u-boot.bin
>-
>-5.1 Reflash U-Boot Image using U-Boot
>-
>- tftp $loadaddr u-boot.bin
>- protect off fe000000 fe0fffff
>- erase fe000000 fe0fffff
>- cp.b $loadaddr fe000000 $filesize
>-
>-
>-6. Additional Notes:
>- 1) The console is connected to the top RS-232 connector and the
>- baudrate for MPC837XE-RDB is 115200bps.
>diff --git a/board/nxp/mpc837xerdb/mpc837xerdb.c b/board/nxp/mpc837xerdb/mpc837xerdb.c
>deleted file mode 100644
>index 55299745a3c..00000000000
>--- a/board/nxp/mpc837xerdb/mpc837xerdb.c
>+++ /dev/null
>@@ -1,242 +0,0 @@
>-// SPDX-License-Identifier: GPL-2.0+
>-/*
>- * Copyright (C) 2007 Freescale Semiconductor, Inc.
>- * Kevin Lam <kevin.lam@freescale.com>
>- * Joe D'Abbraccio <joe.d'abbraccio@freescale.com>
>- */
>-
>-#include <config.h>
>-#include <env.h>
>-#include <hwconfig.h>
>-#include <i2c.h>
>-#include <init.h>
>-#include <asm/bitops.h>
>-#include <asm/global_data.h>
>-#include <asm/io.h>
>-#include <asm/fsl_mpc83xx_serdes.h>
>-#include <fdt_support.h>
>-#include <spd_sdram.h>
>-#include <vsc7385.h>
>-#include <fsl_esdhc.h>
>-#include <linux/delay.h>
>-
>-DECLARE_GLOBAL_DATA_PTR;
>-
>-#if defined(CFG_SYS_DRAM_TEST)
>-int
>-testdram(void)
>-{
>- uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
>- uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
>- uint *p;
>-
>- printf("Testing DRAM from 0x%08x to 0x%08x\n",
>- CONFIG_SYS_MEMTEST_START,
>- CONFIG_SYS_MEMTEST_END);
>-
>- printf("DRAM test phase 1:\n");
>- for (p = pstart; p < pend; p++)
>- *p = 0xaaaaaaaa;
>-
>- for (p = pstart; p < pend; p++) {
>- if (*p != 0xaaaaaaaa) {
>- printf("DRAM test fails at: %08x\n", (uint) p);
>- return 1;
>- }
>- }
>-
>- printf("DRAM test phase 2:\n");
>- for (p = pstart; p < pend; p++)
>- *p = 0x55555555;
>-
>- for (p = pstart; p < pend; p++) {
>- if (*p != 0x55555555) {
>- printf("DRAM test fails at: %08x\n", (uint) p);
>- return 1;
>- }
>- }
>-
>- printf("DRAM test passed.\n");
>- return 0;
>-}
>-#endif
>-
>-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
>-void ddr_enable_ecc(unsigned int dram_size);
>-#endif
>-int fixed_sdram(void);
>-
>-int dram_init(void)
>-{
>- immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
>- u32 msize = 0;
>-
>- if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
>- return -ENXIO;
>-
>-#if defined(CONFIG_SPD_EEPROM)
>- msize = spd_sdram();
>-#else
>- msize = fixed_sdram();
>-#endif
>-
>-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
>- /* Initialize DDR ECC byte */
>- ddr_enable_ecc(msize * 1024 * 1024);
>-#endif
>- /* return total bus DDR size(bytes) */
>- gd->ram_size = msize * 1024 * 1024;
>-
>- return 0;
>-}
>-
>-#if !defined(CONFIG_SPD_EEPROM)
>-/*************************************************************************
>- * fixed sdram init -- doesn't use serial presence detect.
>- ************************************************************************/
>-int fixed_sdram(void)
>-{
>- immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
>- u32 msize = CFG_SYS_SDRAM_SIZE;
>- u32 msize_log2 = __ilog2(msize);
>-
>- im->sysconf.ddrlaw[0].bar = CFG_SYS_SDRAM_BASE & 0xfffff000;
>- im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
>-
>- im->sysconf.ddrcdr = CFG_SYS_DDRCDR_VALUE;
>- udelay(50000);
>-
>- im->ddr.sdram_clk_cntl = CFG_SYS_DDR_SDRAM_CLK_CNTL;
>- udelay(1000);
>-
>- im->ddr.csbnds[0].csbnds = CFG_SYS_DDR_CS0_BNDS;
>- im->ddr.cs_config[0] = CFG_SYS_DDR_CS0_CONFIG;
>- udelay(1000);
>-
>- im->ddr.timing_cfg_0 = CFG_SYS_DDR_TIMING_0;
>- im->ddr.timing_cfg_1 = CFG_SYS_DDR_TIMING_1;
>- im->ddr.timing_cfg_2 = CFG_SYS_DDR_TIMING_2;
>- im->ddr.timing_cfg_3 = CFG_SYS_DDR_TIMING_3;
>- im->ddr.sdram_cfg = CFG_SYS_DDR_SDRAM_CFG;
>- im->ddr.sdram_cfg2 = CFG_SYS_DDR_SDRAM_CFG2;
>- im->ddr.sdram_mode = CFG_SYS_DDR_MODE;
>- im->ddr.sdram_mode2 = CFG_SYS_DDR_MODE2;
>- im->ddr.sdram_interval = CFG_SYS_DDR_INTERVAL;
>- sync();
>- udelay(1000);
>-
>- im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
>- udelay(2000);
>- return CFG_SYS_SDRAM_SIZE >> 20;
>-}
>-#endif /*!CONFIG_SYS_SPD_EEPROM */
>-
>-int checkboard(void)
>-{
>- puts("Board: Freescale MPC837xERDB\n");
>- return 0;
>-}
>-
>-int board_early_init_f(void)
>-{
>- immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
>-#ifdef CONFIG_FSL_SERDES
>- u32 spridr = in_be32(&immr->sysconf.spridr);
>-
>- /* we check only part num, and don't look for CPU revisions */
>- switch (PARTID_NO_E(spridr)) {
>- case SPR_8377:
>- fsl_setup_serdes(CFG_FSL_SERDES1, FSL_SERDES_PROTO_SATA,
>- FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
>- fsl_setup_serdes(CFG_FSL_SERDES2, FSL_SERDES_PROTO_PEX,
>- FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
>- break;
>- case SPR_8378:
>- fsl_setup_serdes(CFG_FSL_SERDES2, FSL_SERDES_PROTO_PEX,
>- FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
>- break;
>- case SPR_8379:
>- fsl_setup_serdes(CFG_FSL_SERDES1, FSL_SERDES_PROTO_SATA,
>- FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
>- fsl_setup_serdes(CFG_FSL_SERDES2, FSL_SERDES_PROTO_SATA,
>- FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
>- break;
>- default:
>- printf("serdes not configured: unknown CPU part number: "
>- "%04x\n", spridr >> 16);
>- break;
>- }
>-#endif /* CONFIG_FSL_SERDES */
>-
>-#ifdef CONFIG_FSL_ESDHC
>- clrsetbits_be32(&immr->sysconf.sicrl, SICRL_USB_B, SICRL_USB_B_SD);
>- clrsetbits_be32(&immr->sysconf.sicrh, SICRH_SPI, SICRH_SPI_SD);
>-#endif
>- return 0;
>-}
>-
>-#ifdef CONFIG_FSL_ESDHC
>-#if !(CONFIG_IS_ENABLED(DM_MMC) || CONFIG_IS_ENABLED(DM_USB))
>-int board_mmc_init(struct bd_info *bd)
>-{
>- struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR;
>- char buffer[HWCONFIG_BUFFER_SIZE] = {0};
>- int esdhc_hwconfig_enabled = 0;
>-
>- if (env_get_f("hwconfig", buffer, sizeof(buffer)) > 0)
>- esdhc_hwconfig_enabled = hwconfig_f("esdhc", buffer);
>-
>- if (esdhc_hwconfig_enabled == 0)
>- return 0;
>-
>- clrsetbits_be32(&im->sysconf.sicrl, SICRL_USB_B, SICRL_USB_B_SD);
>- clrsetbits_be32(&im->sysconf.sicrh, SICRH_SPI, SICRH_SPI_SD);
>-
>- return fsl_esdhc_mmc_init(bd);
>-}
>-#endif
>-#endif
>-
>-/*
>- * Miscellaneous late-boot configurations
>- *
>- * If a VSC7385 microcode image is present, then upload it.
>-*/
>-int misc_init_r(void)
>-{
>- int rc = 0;
>-
>-#ifdef CFG_VSC7385_IMAGE
>- if (vsc7385_upload_firmware((void *) CFG_VSC7385_IMAGE,
>- CFG_VSC7385_IMAGE_SIZE)) {
>- puts("Failure uploading VSC7385 microcode.\n");
>- rc = 1;
>- }
>-#endif
>-
>- return rc;
>-}
>-
>-int board_late_init(void)
>-{
>- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
>-#ifdef CONFIG_USB_HOST
>- clrsetbits_be32(&immap->sysconf.sicrl, SICRL_USB_A, 0x40000000);
>-#endif
>- return 0;
>-}
>-
>-#if defined(CONFIG_OF_BOARD_SETUP)
>-
>-int ft_board_setup(void *blob, struct bd_info *bd)
>-{
>-#ifdef CONFIG_PCI
>- ft_pci_setup(blob, bd);
>-#endif
>- ft_cpu_setup(blob, bd);
>- fsl_fdt_fixup_dr_usb(blob, bd);
>- fdt_fixup_esdhc(blob, bd);
>-
>- return 0;
>-}
>-#endif /* CONFIG_OF_BOARD_SETUP */
>diff --git a/configs/MPC837XERDB_defconfig b/configs/MPC837XERDB_defconfig
>deleted file mode 100644
>index a9d06785186..00000000000
>--- a/configs/MPC837XERDB_defconfig
>+++ /dev/null
>@@ -1,193 +0,0 @@
>-CONFIG_PPC=y
>-CONFIG_TEXT_BASE=0xFE000000
>-CONFIG_SYS_MALLOC_LEN=0x80000
>-CONFIG_ENV_SIZE=0x4000
>-CONFIG_ENV_SECT_SIZE=0x10000
>-CONFIG_DEFAULT_DEVICE_TREE="mpc8379erdb"
>-CONFIG_SYS_MONITOR_LEN=524288
>-CONFIG_DEBUG_UART_BASE=0xe0004500
>-CONFIG_DEBUG_UART_CLOCK=333333000
>-CONFIG_SYS_CLK_FREQ=66666667
>-CONFIG_ENV_ADDR=0xFE080000
>-# CONFIG_SYS_PCI_64BIT is not set
>-CONFIG_MPC83xx=y
>-CONFIG_HIGH_BATS=y
>-CONFIG_SYS_INIT_RAM_LOCK=y
>-CONFIG_TARGET_MPC837XERDB=y
>-CONFIG_DDR_MC_CLOCK_MODE_1_1=y
>-CONFIG_SYSTEM_PLL_FACTOR_5_1=y
>-CONFIG_CORE_PLL_RATIO_2_1=y
>-CONFIG_PCI_HOST_MODE_ENABLE=y
>-CONFIG_PCI_INT_ARBITER1_ENABLE=y
>-CONFIG_BOOT_MEMORY_SPACE_LOW=y
>-CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
>-CONFIG_TSEC1_MODE_RGMII=y
>-CONFIG_TSEC2_MODE_RGMII=y
>-CONFIG_LDP_PIN_MUX_STATE_0=y
>-CONFIG_BAT0=y
>-CONFIG_BAT0_NAME="SDRAM_LOWER"
>-CONFIG_BAT0_BASE=0x00000000
>-CONFIG_BAT0_LENGTH_256_MBYTES=y
>-CONFIG_BAT0_ACCESS_RW=y
>-CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
>-CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
>-CONFIG_BAT0_USER_MODE_VALID=y
>-CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
>-CONFIG_BAT1=y
>-CONFIG_BAT1_NAME="SDRAM_UPPER"
>-CONFIG_BAT1_BASE=0x10000000
>-CONFIG_BAT1_LENGTH_256_MBYTES=y
>-CONFIG_BAT1_ACCESS_RW=y
>-CONFIG_BAT1_ICACHE_MEMORYCOHERENCE=y
>-CONFIG_BAT1_DCACHE_MEMORYCOHERENCE=y
>-CONFIG_BAT1_USER_MODE_VALID=y
>-CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
>-CONFIG_BAT2=y
>-CONFIG_BAT2_NAME="IMMR"
>-CONFIG_BAT2_BASE=0xE0000000
>-CONFIG_BAT2_LENGTH_8_MBYTES=y
>-CONFIG_BAT2_ACCESS_RW=y
>-CONFIG_BAT2_ICACHE_INHIBITED=y
>-CONFIG_BAT2_DCACHE_INHIBITED=y
>-CONFIG_BAT2_DCACHE_GUARDED=y
>-CONFIG_BAT2_USER_MODE_VALID=y
>-CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
>-CONFIG_BAT3=y
>-CONFIG_BAT3_NAME="L2_SWITCH"
>-CONFIG_BAT3_BASE=0xF0000000
>-CONFIG_BAT3_ACCESS_RW=y
>-CONFIG_BAT3_ICACHE_INHIBITED=y
>-CONFIG_BAT3_DCACHE_INHIBITED=y
>-CONFIG_BAT3_DCACHE_GUARDED=y
>-CONFIG_BAT3_USER_MODE_VALID=y
>-CONFIG_BAT3_SUPERVISOR_MODE_VALID=y
>-CONFIG_BAT4=y
>-CONFIG_BAT4_NAME="FLASH"
>-CONFIG_BAT4_BASE=0xFE000000
>-CONFIG_BAT4_LENGTH_32_MBYTES=y
>-CONFIG_BAT4_ACCESS_RW=y
>-CONFIG_BAT4_ICACHE_MEMORYCOHERENCE=y
>-CONFIG_BAT4_DCACHE_INHIBITED=y
>-CONFIG_BAT4_DCACHE_GUARDED=y
>-CONFIG_BAT4_USER_MODE_VALID=y
>-CONFIG_BAT4_SUPERVISOR_MODE_VALID=y
>-CONFIG_BAT5=y
>-CONFIG_BAT5_NAME="STACH_IN_DCACHE"
>-CONFIG_BAT5_BASE=0xE6000000
>-CONFIG_BAT5_ACCESS_RW=y
>-CONFIG_BAT5_USER_MODE_VALID=y
>-CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
>-CONFIG_BAT6=y
>-CONFIG_BAT6_NAME="PCI_MEM"
>-CONFIG_BAT6_BASE=0x80000000
>-CONFIG_BAT6_LENGTH_256_MBYTES=y
>-CONFIG_BAT6_ACCESS_RW=y
>-CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y
>-CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y
>-CONFIG_BAT6_USER_MODE_VALID=y
>-CONFIG_BAT6_SUPERVISOR_MODE_VALID=y
>-CONFIG_BAT7=y
>-CONFIG_BAT7_NAME="PCI_MMIO"
>-CONFIG_BAT7_BASE=0x90000000
>-CONFIG_BAT7_LENGTH_256_MBYTES=y
>-CONFIG_BAT7_ACCESS_RW=y
>-CONFIG_BAT7_ICACHE_INHIBITED=y
>-CONFIG_BAT7_DCACHE_INHIBITED=y
>-CONFIG_BAT7_DCACHE_GUARDED=y
>-CONFIG_BAT7_USER_MODE_VALID=y
>-CONFIG_BAT7_SUPERVISOR_MODE_VALID=y
>-CONFIG_LBLAW0=y
>-CONFIG_LBLAW0_BASE=0xFE000000
>-CONFIG_LBLAW0_NAME="FLASH"
>-CONFIG_LBLAW0_LENGTH_8_MBYTES=y
>-CONFIG_LBLAW1=y
>-CONFIG_LBLAW1_BASE=0xE0600000
>-CONFIG_LBLAW1_NAME="NAND"
>-CONFIG_LBLAW1_LENGTH_32_KBYTES=y
>-CONFIG_LBLAW2=y
>-CONFIG_LBLAW2_BASE=0xF0000000
>-CONFIG_LBLAW2_NAME="VSC7385"
>-CONFIG_LBLAW2_LENGTH_128_KBYTES=y
>-CONFIG_HID0_FINAL_EMCP=y
>-CONFIG_HID0_FINAL_ICE=y
>-CONFIG_HID2_HBE=y
>-CONFIG_ACR_PIPE_DEP_4=y
>-CONFIG_ACR_RPTCNT_4=y
>-CONFIG_SPCR_TSECEP_3=y
>-CONFIG_LCRR_DBYP_PLL_BYPASSED=y
>-CONFIG_LCRR_CLKDIV_8=y
>-CONFIG_FSL_SERDES=y
>-CONFIG_USE_UBOOTPATH=y
>-CONFIG_DEBUG_UART=y
>-CONFIG_BOOTDELAY=6
>-CONFIG_OF_BOARD_SETUP=y
>-CONFIG_OF_STDOUT_VIA_ALIAS=y
>-CONFIG_SYS_PBSIZE=276
>-CONFIG_BOARD_LATE_INIT=y
>-CONFIG_MISC_INIT_R=y
>-CONFIG_PCI_INIT_R=y
>-CONFIG_HUSH_PARSER=y
>-CONFIG_CMD_IMLS=y
>-CONFIG_CMD_I2C=y
>-CONFIG_LOADS_ECHO=y
>-CONFIG_SYS_LOADS_BAUD_CHANGE=y
>-CONFIG_CMD_MMC=y
>-CONFIG_CMD_PCI=y
>-CONFIG_CMD_USB=y
>-# CONFIG_CMD_SETEXPR is not set
>-CONFIG_BOOTP_BOOTFILESIZE=y
>-CONFIG_CMD_MII=y
>-CONFIG_CMD_PING=y
>-CONFIG_CMD_EXT2=y
>-CONFIG_CMD_FAT=y
>-CONFIG_OF_CONTROL=y
>-CONFIG_ENV_OVERWRITE=y
>-CONFIG_USE_BOOTFILE=y
>-CONFIG_BOOTFILE="uImage"
>-CONFIG_USE_ETHPRIME=y
>-CONFIG_ETHPRIME="TSEC0"
>-CONFIG_USE_HOSTNAME=y
>-CONFIG_HOSTNAME="mpc837x_rdb"
>-CONFIG_USE_ROOTPATH=y
>-CONFIG_ROOTPATH="/nfsroot"
>-CONFIG_SATA=y
>-CONFIG_FSL_SATA=y
>-CONFIG_SYS_SATA_MAX_DEVICE=2
>-CONFIG_SYS_BR0_PRELIM_BOOL=y
>-CONFIG_SYS_BR0_PRELIM=0xFE001001
>-CONFIG_SYS_OR0_PRELIM=0xFF800193
>-CONFIG_SYS_BR1_PRELIM_BOOL=y
>-CONFIG_SYS_BR1_PRELIM=0xE0600C21
>-CONFIG_SYS_OR1_PRELIM=0xFFFF8396
>-CONFIG_SYS_BR2_PRELIM_BOOL=y
>-CONFIG_SYS_BR2_PRELIM=0xF0000801
>-CONFIG_SYS_OR2_PRELIM=0xFFFE09FF
>-CONFIG_SYS_I2C_LEGACY=y
>-CONFIG_SYS_I2C_FSL=y
>-CONFIG_SYS_FSL_I2C_OFFSET=0x3000
>-CONFIG_SYS_I2C_SLAVE=0x7F
>-CONFIG_SYS_I2C_SPEED=400000
>-CONFIG_FSL_ESDHC=y
>-CONFIG_FSL_ESDHC_PIN_MUX=y
>-CONFIG_MTD=y
>-CONFIG_MTD_NOR_FLASH=y
>-CONFIG_FLASH_CFI_DRIVER=y
>-CONFIG_FLASH_SHOW_PROGRESS=0
>-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
>-CONFIG_SYS_FLASH_EMPTY_INFO=y
>-CONFIG_SYS_FLASH_PROTECTION=y
>-CONFIG_SYS_FLASH_CFI=y
>-CONFIG_SYS_MAX_FLASH_SECT=256
>-CONFIG_DM_MDIO=y
>-CONFIG_DM_ETH_PHY=y
>-CONFIG_RGMII=y
>-CONFIG_MII=y
>-CONFIG_VSC7385_ENET=y
>-CONFIG_TSEC_ENET=y
>-CONFIG_RTC_DS1374=y
>-CONFIG_SPECIFY_CONSOLE_INDEX=y
>-CONFIG_DM_SERIAL=y
>-CONFIG_SYS_NS16550=y
>-CONFIG_USB=y
>-CONFIG_USB_EHCI_HCD=y
>-CONFIG_USB_EHCI_FSL=y
>diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h
>deleted file mode 100644
>index b22c720d07f..00000000000
>--- a/include/configs/MPC837XERDB.h
>+++ /dev/null
>@@ -1,218 +0,0 @@
>-/* SPDX-License-Identifier: GPL-2.0+ */
>-/*
>- * Copyright (C) 2007 Freescale Semiconductor, Inc.
>- * Kevin Lam <kevin.lam@freescale.com>
>- * Joe D'Abbraccio <joe.d'abbraccio@freescale.com>
>- */
>-
>-#ifndef __CONFIG_H
>-#define __CONFIG_H
>-
>-#include <linux/stringify.h>
>-
>-/*
>- * High Level Configuration Options
>- */
>-
>-/* System performance - define the value i.e. CONFIG_SYS_XXX
>-*/
>-
>-/* System Clock Configuration Register */
>-#define CFG_SYS_SCCR_TSEC1CM 1 /* eTSEC1 clock mode (0-3) */
>-#define CFG_SYS_SCCR_TSEC2CM 1 /* eTSEC2 clock mode (0-3) */
>-#define CFG_SYS_SCCR_SATACM SCCR_SATACM_2 /* SATA1-4 clock mode (0-3) */
>-
>-/*
>- * System IO Config
>- */
>-#define CFG_SYS_SICRH 0x08200000
>-#define CFG_SYS_SICRL 0x00000000
>-
>-/*
>- * Output Buffer Impedance
>- */
>-#define CFG_SYS_OBIR 0x30100000
>-
>-/*
>- * Device configurations
>- */
>-
>-/* Vitesse 7385 */
>-
>-#ifdef CONFIG_VSC7385_ENET
>-
>-/* The flash address and size of the VSC7385 firmware image */
>-#define CFG_VSC7385_IMAGE 0xFE7FE000
>-#define CFG_VSC7385_IMAGE_SIZE 8192
>-
>-#endif
>-
>-/*
>- * DDR Setup
>- */
>-#define CFG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */
>-#define CFG_SYS_DDR_SDRAM_CLK_CNTL 0x03000000
>-
>-#define CFG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN | DDRCDR_ODT | DDRCDR_Q_DRN)
>-
>-/*
>- * Manually set up DDR parameters
>- */
>-#define CFG_SYS_SDRAM_SIZE 0x10000000 /* 256 MiB */
>-#define CFG_SYS_DDR_CS0_BNDS 0x0000000f
>-#define CFG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
>- | CSCONFIG_ODT_WR_ONLY_CURRENT \
>- | CSCONFIG_ROW_BIT_13 \
>- | CSCONFIG_COL_BIT_10)
>-
>-#define CFG_SYS_DDR_TIMING_3 0x00000000
>-#define CFG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
>- | (0 << TIMING_CFG0_WRT_SHIFT) \
>- | (0 << TIMING_CFG0_RRT_SHIFT) \
>- | (0 << TIMING_CFG0_WWT_SHIFT) \
>- | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
>- | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
>- | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
>- | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
>- /* 0x00260802 */ /* DDR400 */
>-#define CFG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
>- | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
>- | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
>- | (7 << TIMING_CFG1_CASLAT_SHIFT) \
>- | (13 << TIMING_CFG1_REFREC_SHIFT) \
>- | (3 << TIMING_CFG1_WRREC_SHIFT) \
>- | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
>- | (2 << TIMING_CFG1_WRTORD_SHIFT))
>- /* 0x3937d322 */
>-#define CFG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
>- | (5 << TIMING_CFG2_CPO_SHIFT) \
>- | (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
>- | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
>- | (3 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
>- | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
>- | (8 << TIMING_CFG2_FOUR_ACT_SHIFT))
>- /* 0x02984cc8 */
>-
>-#define CFG_SYS_DDR_INTERVAL ((1024 << SDRAM_INTERVAL_REFINT_SHIFT) \
>- | (0 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
>- /* 0x06090100 */
>-
>-#define CFG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
>- | SDRAM_CFG_SDRAM_TYPE_DDR2)
>- /* 0x43000000 */
>-#define CFG_SYS_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */
>-#define CFG_SYS_DDR_MODE ((0x0406 << SDRAM_MODE_ESD_SHIFT) \
>- | (0x0442 << SDRAM_MODE_SD_SHIFT))
>- /* 0x04400442 */ /* DDR400 */
>-#define CFG_SYS_DDR_MODE2 0x00000000
>-
>-/*
>- * Memory test
>- */
>-#undef CFG_SYS_DRAM_TEST /* memory test, takes time */
>-
>-/*
>- * The reserved memory
>- */
>-
>-/*
>- * Initial RAM Base Address Setup
>- */
>-#define CFG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
>-#define CFG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
>-
>-/*
>- * FLASH on the Local Bus
>- */
>-#define CFG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
>-#define CFG_SYS_FLASH_SIZE 8 /* max FLASH size is 32M */
>-
>-/*
>- * NAND Flash on the Local Bus
>- */
>-#define CFG_SYS_NAND_BASE 0xE0600000
>-
>-/* Vitesse 7385 */
>-
>-#define CFG_SYS_VSC7385_BASE 0xF0000000
>-
>-#define CFG_SYS_BAUDRATE_TABLE \
>- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
>-
>-#define CFG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
>-#define CFG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
>-
>-/* SERDES */
>-#define CFG_FSL_SERDES1 0xe3000
>-#define CFG_FSL_SERDES2 0xe3100
>-
>-/* I2C */
>-#define CFG_SYS_I2C_NOPROBES { {0, 0x51} }
>-
>-/*
>- * Config on-board RTC
>- */
>-#define CFG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
>-
>-/*
>- * General PCI
>- * Addresses are mapped 1-1.
>- */
>-#define CFG_SYS_PCIE1_CFG_BASE 0xA0000000
>-#define CFG_SYS_PCIE1_CFG_SIZE 0x08000000
>-#define CFG_SYS_PCIE1_MEM_PHYS 0xA8000000
>-#define CFG_SYS_PCIE1_IO_PHYS 0xB8000000
>-
>-#define CFG_SYS_PCIE2_CFG_BASE 0xC0000000
>-#define CFG_SYS_PCIE2_CFG_SIZE 0x08000000
>-#define CFG_SYS_PCIE2_MEM_PHYS 0xC8000000
>-#define CFG_SYS_PCIE2_IO_PHYS 0xD8000000
>-
>-#ifdef CONFIG_MMC
>-#define CFG_SYS_FSL_ESDHC_ADDR CFG_SYS_MPC83xx_ESDHC_ADDR
>-#endif
>-
>-/*
>- * Miscellaneous configurable options
>- */
>-
>-/*
>- * For booting Linux, the board info and command line data
>- * have to be in the first 256 MB of memory, since this is
>- * the maximum mapped by the Linux kernel during initialization.
>- */
>-#define CFG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
>-
>-/*
>- * Environment Configuration
>- */
>-
>-#define FDTFILE "mpc8379_rdb.dtb"
>-
>-#define CFG_EXTRA_ENV_SETTINGS \
>- "netdev=eth1\0" \
>- "uboot=" CONFIG_UBOOTPATH "\0" \
>- "tftpflash=tftp $loadaddr $uboot;" \
>- "protect off " __stringify(CONFIG_TEXT_BASE) \
>- " +$filesize; " \
>- "erase " __stringify(CONFIG_TEXT_BASE) \
>- " +$filesize; " \
>- "cp.b $loadaddr " __stringify(CONFIG_TEXT_BASE) \
>- " $filesize; " \
>- "protect on " __stringify(CONFIG_TEXT_BASE) \
>- " +$filesize; " \
>- "cmp.b $loadaddr " __stringify(CONFIG_TEXT_BASE) \
>- " $filesize\0" \
>- "fdtaddr=780000\0" \
>- "fdtfile=" FDTFILE "\0" \
>- "ramdiskaddr=1000000\0" \
>- "ramdiskfile=rootfs.ext2.gz.uboot\0" \
>- "console=ttyS0\0" \
>- "setbootargs=setenv bootargs " \
>- "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
>- "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
>- "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
>- "$netdev:off " \
>- "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
>-
>-#endif /* __CONFIG_H */
>
--- Thanks!
"I'm not a very positive person" - Linus torvalds
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH 01/26] board: powerpc: Remove MPC8548CDS support
2026-10-09 19:36 ` [PATCH 01/26] board: powerpc: Remove MPC8548CDS support Bradley Morgan
@ 2026-10-09 21:55 ` Tom Rini
2026-10-10 10:51 ` Łukasz Majewski
0 siblings, 1 reply; 31+ messages in thread
From: Tom Rini @ 2026-10-09 21:55 UTC (permalink / raw)
To: Bradley Morgan
Cc: u-boot, Marek Behún, Marek Mojík,
NXP i . MX U-Boot Team, Alexey Charkov, Anshul Dalal,
Daniel Golle, Fabio Estevam, Gaurav Jain, Ilias Apalodimas,
Jaehoon Chung, James Hilliard, Jerome Forissier, Johan Jonker,
Lukasz Majewski, Marek Vasut, Mario Six, Michael Walle,
Michal Simek, Neil Armstrong, Peng Fan, Pengpeng Hou,
Priyanka Jain, Quentin Schulz, Simon Glass, Stefano Babic,
Tanmay Kathpalia, Torsten Rupp, Vincent Jardin, Weijie Gao
[-- Attachment #1: Type: text/plain, Size: 860 bytes --]
On Fri, Oct 09, 2026 at 07:36:39PM +0000, Bradley Morgan wrote:
> MPC8548 silicon is no longer manufactured, and the MPC8548CDS board is
> obsolete. Remove the board and its SoC support.
>
> Signed-off-by: Bradley Morgan <brads@mainlining.org>
So, globally. As has been discussed on IRC already, please take a more
neutral removal message in v2. The problem isn't that the boards aren't
manufactured, it's that (likely) they aren't being actively tested and
maintained in the community. We're fine with "obsolete" hardware if
someone is maintaining it. Also, please rework the CC list (outside the
cover letter) to include the listed board maintainers, and then only
people that have touched the relevant code recently, perhaps with a
manual audit or exclude some global or common files, when looking for
who else to CC. Thanks.
--
Tom
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH 01/26] board: powerpc: Remove MPC8548CDS support
2026-10-09 21:55 ` Tom Rini
@ 2026-10-10 10:51 ` Łukasz Majewski
2026-10-10 10:58 ` Bradley Morgan
0 siblings, 1 reply; 31+ messages in thread
From: Łukasz Majewski @ 2026-10-10 10:51 UTC (permalink / raw)
To: Tom Rini
Cc: Bradley Morgan, u-boot, Marek Behún, Marek Mojík,
NXP i . MX U-Boot Team, Alexey Charkov, Anshul Dalal,
Daniel Golle, Fabio Estevam, Gaurav Jain, Ilias Apalodimas,
Jaehoon Chung, James Hilliard, Jerome Forissier, Johan Jonker,
Marek Vasut, Mario Six, Michael Walle, Michal Simek,
Neil Armstrong, Peng Fan, Pengpeng Hou, Priyanka Jain,
Quentin Schulz, Simon Glass, Stefano Babic, Tanmay Kathpalia,
Torsten Rupp, Vincent Jardin, Weijie Gao
Hi Tom, Bradley,
> On Fri, Oct 09, 2026 at 07:36:39PM +0000, Bradley Morgan wrote:
>
> > MPC8548 silicon is no longer manufactured, and the MPC8548CDS board
> > is obsolete. Remove the board and its SoC support.
> >
> > Signed-off-by: Bradley Morgan <brads@mainlining.org>
>
> So, globally. As has been discussed on IRC already, please take a more
> neutral removal message in v2. The problem isn't that the boards
> aren't manufactured, it's that (likely) they aren't being actively
> tested and maintained in the community. We're fine with "obsolete"
> hardware if someone is maintaining it. Also, please rework the CC
> list (outside the cover letter) to include the listed board
> maintainers, and then only people that have touched the relevant code
> recently, perhaps with a manual audit or exclude some global or
> common files, when looking for who else to CC. Thanks.
>
Maybe I would add my 2 cents...
There are a lot of MPC85xx systems out there - and probably (my guess)
is that at some point some customers would be "forced" to refurbish
them.
Some companies need very long time to realize that their crucial legacy
products may be removed from u-boot. I would opt for longer and more
"broadcast" obsolence process.
I had similar situation in the past when some Samsung SoCs were removed
from u-boot - nobody was willing to pay for re-adding them upstrem -
this means that they were kept out of tree.
--
Best regards,
Lukasz Majewski
--
Nabla Software Engineering GmbH
HRB 40522 Augsburg
Phone: +49 821 45592596
E-Mail: office@nabladev.com
Managing Director : Stefano Babic
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH 01/26] board: powerpc: Remove MPC8548CDS support
2026-10-10 10:51 ` Łukasz Majewski
@ 2026-10-10 10:58 ` Bradley Morgan
0 siblings, 0 replies; 31+ messages in thread
From: Bradley Morgan @ 2026-10-10 10:58 UTC (permalink / raw)
To: Łukasz Majewski, Tom Rini
Cc: u-boot, Marek Behún, Marek Mojík,
NXP i . MX U-Boot Team, Alexey Charkov, Anshul Dalal,
Daniel Golle, Fabio Estevam, Gaurav Jain, Ilias Apalodimas,
Jaehoon Chung, James Hilliard, Jerome Forissier, Johan Jonker,
Marek Vasut, Mario Six, Michael Walle, Michal Simek,
Neil Armstrong, Peng Fan, Pengpeng Hou, Priyanka Jain,
Quentin Schulz, Simon Glass, Stefano Babic, Tanmay Kathpalia,
Torsten Rupp, Vincent Jardin, Weijie Gao
On 10 October 2026 11:51:49 BST, "Łukasz Majewski" <lukma@nabladev.com>
wrote:
>Hi Tom, Bradley,
>
>> On Fri, Oct 09, 2026 at 07:36:39PM +0000, Bradley Morgan wrote:
>>
>> > MPC8548 silicon is no longer manufactured, and the MPC8548CDS board
>> > is obsolete. Remove the board and its SoC support.
>> >
>> > Signed-off-by: Bradley Morgan <brads@mainlining.org>
>>
>> So, globally. As has been discussed on IRC already, please take a more
>> neutral removal message in v2. The problem isn't that the boards
>> aren't manufactured, it's that (likely) they aren't being actively
>> tested and maintained in the community. We're fine with "obsolete"
>> hardware if someone is maintaining it. Also, please rework the CC
>> list (outside the cover letter) to include the listed board
>> maintainers, and then only people that have touched the relevant code
>> recently, perhaps with a manual audit or exclude some global or
>> common files, when looking for who else to CC. Thanks.
>>
>
>Maybe I would add my 2 cents...
>
>There are a lot of MPC85xx systems out there - and probably (my guess)
>is that at some point some customers would be "forced" to refurbish
>them.
>
>Some companies need very long time to realize that their crucial legacy
>products may be removed from u-boot. I would opt for longer and more
>"broadcast" obsolence process.
>
>
>I had similar situation in the past when some Samsung SoCs were removed
>from u-boot - nobody was willing to pay for re-adding them upstrem -
>this means that they were kept out of tree.
This opinion was basically said in IRC, that devices that weren't on Linux
AND eol should go.
The V2 series is submitted, with a pick structure, so every "EOL" board
gets deleted. You wouldn't have to merge them all.
>
>
>
>
--- Thanks!
"I'm not a very positive person" - Linus torvalds
^ permalink raw reply [flat|nested] 31+ messages in thread
end of thread, other threads:[~2026-10-10 13:14 UTC | newest]
Thread overview: 31+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2026-10-09 19:36 [PATCH 00/26] powerpc: drop EOL boards and SoCs, take over maintenance Bradley Morgan
2026-10-09 19:36 ` [PATCH 01/26] board: powerpc: Remove MPC8548CDS support Bradley Morgan
2026-10-09 21:55 ` Tom Rini
2026-10-10 10:51 ` Łukasz Majewski
2026-10-10 10:58 ` Bradley Morgan
2026-10-09 19:36 ` [PATCH 02/26] board: powerpc: Remove MPC837XERDB support Bradley Morgan
2026-10-09 20:18 ` Bradley Morgan
2026-10-09 19:36 ` [PATCH 03/26] board: powerpc: Remove P2020RDB-PC support Bradley Morgan
2026-10-09 19:36 ` [PATCH 04/26] board: powerpc: Remove P3041DS support Bradley Morgan
2026-10-09 19:36 ` [PATCH 05/26] board: powerpc: Remove P4080DS support Bradley Morgan
2026-10-09 19:36 ` [PATCH 06/26] board: powerpc: Remove P5040DS support Bradley Morgan
2026-10-09 19:36 ` [PATCH 07/26] board: powerpc: Remove T1042D4RDB support Bradley Morgan
2026-10-09 19:36 ` [PATCH 08/26] powerpc: mpc85xx: Remove P3041 support Bradley Morgan
2026-10-09 19:36 ` [PATCH 09/26] powerpc: mpc85xx: Remove P4080 support Bradley Morgan
2026-10-09 19:36 ` [PATCH 10/26] powerpc: mpc85xx: Remove P5040 support Bradley Morgan
2026-10-09 19:36 ` [PATCH 11/26] powerpc: mpc83xx: Remove MPC837x support Bradley Morgan
2026-10-09 19:36 ` [PATCH 12/26] powerpc: mpc85xx: Remove C29x support Bradley Morgan
2026-10-09 19:36 ` [PATCH 13/26] powerpc: mpc85xx: Remove P1011 support Bradley Morgan
2026-10-09 19:36 ` [PATCH 14/26] powerpc: mpc85xx: Remove P1023 support Bradley Morgan
2026-10-09 19:36 ` [PATCH 15/26] powerpc: mpc85xx: Remove P1025 support Bradley Morgan
2026-10-09 19:36 ` [PATCH 16/26] powerpc: mpc85xx: Remove MPC8536 support Bradley Morgan
2026-10-09 19:36 ` [PATCH 17/26] powerpc: mpc85xx: Remove MPC8540 support Bradley Morgan
2026-10-09 19:36 ` [PATCH 18/26] powerpc: mpc85xx: Remove MPC8560 support Bradley Morgan
2026-10-09 19:36 ` [PATCH 19/26] powerpc: mpc85xx: Remove BSC9132 support Bradley Morgan
2026-10-09 19:36 ` [PATCH 20/26] powerpc: mpc83xx: Remove MPC831x support Bradley Morgan
2026-10-09 19:36 ` [PATCH 21/26] powerpc: mpc83xx: Remove MPC834x support Bradley Morgan
2026-10-09 19:37 ` [PATCH 22/26] powerpc: mpc85xx: Remove P1024 support Bradley Morgan
2026-10-09 19:37 ` [PATCH 23/26] powerpc: mpc85xx: Remove BSC9131 support Bradley Morgan
2026-10-09 19:37 ` [PATCH 24/26] powerpc: mpc83xx: Remove MPC8309 support Bradley Morgan
2026-10-09 19:37 ` [PATCH 25/26] powerpc: Remove MPC86xx support Bradley Morgan
2026-10-09 19:37 ` [PATCH 26/26] MAINTAINERS: powerpc: Add me as PowerPC maintainer Bradley Morgan
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