[PATCH v1 0/3] net: mtk_eth: an8855: fix packet loss and sync with Linux

[PATCH v1 0/3] net: mtk_eth: an8855: fix packet loss and sync with Linux

[Mikhail Zhilkin]

This patch series aligns the U-Boot Airoha AN8855 switch initialization
code with the upstream Linux DSA driver
(drivers/net/dsa/airoha/an8855.c), fixing several register configuration
bugs and improving overall signal integrity.

The current default U-Boot configuration leaves the SerDes with marginal
drive characteristics. On some hardware iterations, this results in
severe packet loss (50-60%) and timeouts during TFTP recovery. This drop
occurs because of marginal signal integrity on the internal 2500Base-X
link connecting the switch to the CPU.

By correcting a bitwise shift overlap, enabling link error recovery, and
applying the proper TX FIR / RX CDR analog tuning parameters used in
Linux, this series ensures a stable physical link between the CPU and
switch across different boards.

These changes have been run-tested on the CMCC RAX3000ME and Xiaomi
AX3000T, both featuring the AN8855 switch, confirming stable network
operation and reliable gigabit TFTP recovery.

Patch summary:
- Patch 1 fixes a bitwise collision bug in the AN8855_RX_CTRL_8 register
  that was accidentally overwriting previously set bits.
- Patch 2 enables graceful link error recovery in AN8855_RX_CTRL_26
  instead of explicitly disabling it.
- Patch 3 ports the SerDes analog tuning parameters (TX Eye and RX
  Jitter Tolerance) from Linux, resolving the packet loss issue on the
  internal 2.5G CPU port.

Mikhail Zhilkin (3):
  net: mtk_eth: an8855: fix bitwise collision in RX_CTRL_8 register
  net: mtk_eth: an8855: enable link error recovery
  net: mtk_eth: an8855: sync SerDes analog tuning with Linux driver

 drivers/net/mtk_eth/an8855.c | 31 ++++++++++++++++++++++++++++---
 1 file changed, 28 insertions(+), 3 deletions(-)

-- 
2.53.0

[PATCH v1 1/3] net: mtk_eth: an8855: fix bitwise collision in RX_CTRL_8 register

[Mikhail Zhilkin]

In an8855_port_sgmii_init(), the bitwise operations for
the AN8855_RX_CTRL_8 register contain a shifting error. The code
attempts to set a value at shift 16 (0x200 << 16), but subsequently
applies a mask and value shifted by 14 (0xfff << 14). This creates a
bitwise collision where the second operation overlaps and overwrites the
bits configured by the first operation, resulting in unintended register
values.

Fix the shift offset for the lower bits from 14 to 0 to prevent
overlap and correctly apply the exact values used in the upstream
Linux driver.

Signed-off-by: Mikhail Zhilkin <csharper2005@gmail.com>
---
 drivers/net/mtk_eth/an8855.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/net/mtk_eth/an8855.c b/drivers/net/mtk_eth/an8855.c
index a2589a2ad31..eb037ec1382 100644
--- a/drivers/net/mtk_eth/an8855.c
+++ b/drivers/net/mtk_eth/an8855.c
@@ -627,8 +627,8 @@ static int an8855_port_sgmii_init(struct an8855_switch_priv *priv, u32 port)
 	an8855_reg_read(priv, AN8855_RX_CTRL_8, &val);
 	val &= ~(0xfff << 16);
 	val |= (0x200 << 16);
-	val &= ~(0x7fff << 14);
-	val |= (0xfff << 14);
+	val &= ~(0x7fff << 0);
+	val |= (0xfff << 0);
 	an8855_reg_write(priv, AN8855_RX_CTRL_8, val);
 
 	/* Frequency memter */
-- 
2.53.0

[PATCH v1 2/3] net: mtk_eth: an8855: enable link error recovery

[Mikhail Zhilkin]

Sync the Link Error Recovery configuration with the upstream Linux
driver.

Currently, the U-Boot driver explicitly clears the
AN8855_RG_LINK_ERRO_EN bit (bit 23) in the AN8855_RX_CTRL_26 register
during SGMII initialization. Setting this bit instead of clearing it
matches the Linux driver behavior, allowing the MAC/PCS to gracefully
recover from momentary link errors on marginal hardware rather than
dropping packets or the entire link.

Signed-off-by: Mikhail Zhilkin <csharper2005@gmail.com>
---
 drivers/net/mtk_eth/an8855.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/mtk_eth/an8855.c b/drivers/net/mtk_eth/an8855.c
index eb037ec1382..513f4534701 100644
--- a/drivers/net/mtk_eth/an8855.c
+++ b/drivers/net/mtk_eth/an8855.c
@@ -599,7 +599,7 @@ static int an8855_port_sgmii_init(struct an8855_switch_priv *priv, u32 port)
 	an8855_reg_write(priv, AN8855_PLL_CTRL_0, val);
 
 	an8855_reg_read(priv, AN8855_RX_CTRL_26, &val);
-	val &= ~BIT(23);
+	val |= BIT(23);
 	val |= BIT(26);
 	an8855_reg_write(priv, AN8855_RX_CTRL_26, val);
 
-- 
2.53.0

[PATCH v1 3/3] net: mtk_eth: an8855: sync SerDes analog tuning with Linux driver

[Mikhail Zhilkin]

Port the TX FIR (TX Eye) and RX CDR (RX Jitter Tolerance) analog
tuning parameters from the upstream Linux Airoha AN8855 DSA driver
(drivers/net/dsa/airoha/an8855.c).

The default U-Boot configuration omits these register writes, leaving
the SerDes with inferior default drive characteristics. On hardware
iterations with minor silicon or trace variances, this marginal signal
integrity leads to severe packet loss (50-60%) during TFTP recovery
over the 2500Base-X link. Explicitly configuring AN8855_INTF_CTRL_10,
AN8855_INTF_CTRL_11, and AN8855_RG_QP_CDR_LPF_BOT_LIM ensures a
stable physical link across boards.

Signed-off-by: Mikhail Zhilkin <csharper2005@gmail.com>
---
 drivers/net/mtk_eth/an8855.c | 25 +++++++++++++++++++++++++
 1 file changed, 25 insertions(+)

diff --git a/drivers/net/mtk_eth/an8855.c b/drivers/net/mtk_eth/an8855.c
index 513f4534701..f8f004e0914 100644
--- a/drivers/net/mtk_eth/an8855.c
+++ b/drivers/net/mtk_eth/an8855.c
@@ -96,6 +96,8 @@
 #define AN8855_SS_LCPLL_TDC_PCW_1		(AN8855_QP_PMA_TOP_BASE + 0x248)
 #define AN8855_INTF_CTRL_8			(AN8855_QP_PMA_TOP_BASE + 0x320)
 #define AN8855_INTF_CTRL_9			(AN8855_QP_PMA_TOP_BASE + 0x324)
+#define AN8855_INTF_CTRL_10			(AN8855_QP_PMA_TOP_BASE + 0x328)
+#define AN8855_INTF_CTRL_11			(AN8855_QP_PMA_TOP_BASE + 0x32c)
 #define AN8855_PLL_CTRL_0			(AN8855_QP_PMA_TOP_BASE + 0x400)
 #define AN8855_PLL_CTRL_2			(AN8855_QP_PMA_TOP_BASE + 0x408)
 #define AN8855_PLL_CTRL_3			(AN8855_QP_PMA_TOP_BASE + 0x40c)
@@ -113,6 +115,7 @@
 #define AN8855_QP_ANA_CSR_BASE			0x1022f000
 #define AN8855_RG_QP_RX_DAC_EN			(AN8855_QP_ANA_CSR_BASE + 0x00)
 #define AN8855_RG_QP_RXAFE_RESERVE		(AN8855_QP_ANA_CSR_BASE + 0x04)
+#define AN8855_RG_QP_CDR_LPF_BOT_LIM		(AN8855_QP_ANA_CSR_BASE + 0x08)
 #define AN8855_RG_QP_CDR_LPF_MJV_LIM		(AN8855_QP_ANA_CSR_BASE + 0x0c)
 #define AN8855_RG_QP_CDR_LPF_SETVALUE		(AN8855_QP_ANA_CSR_BASE + 0x14)
 #define AN8855_RG_QP_CDR_PR_CKREF_DIV1		(AN8855_QP_ANA_CSR_BASE + 0x18)
@@ -678,6 +681,28 @@ static int an8855_port_sgmii_init(struct an8855_switch_priv *priv, u32 port)
 	an8855_reg_write(priv, AN8855_MSG_RX_LIK_STS_0, 0x01010107);
 	an8855_reg_write(priv, AN8855_MSG_RX_LIK_STS_2, 0x00000EEF);
 
+	/* TX FIR - improve TX EYE */
+	an8855_reg_read(priv, AN8855_INTF_CTRL_10, &val);
+	val &= ~(0x1f << 24);
+	val |= (0x04 << 24);
+	val &= ~(0x1f << 16);
+	val |= (0x00 << 16);
+	val |= BIT(29) | BIT(21);
+	an8855_reg_write(priv, AN8855_INTF_CTRL_10, val);
+
+	an8855_reg_read(priv, AN8855_INTF_CTRL_11, &val);
+	val &= ~(0x3f << 0);
+	val |= BIT(6);
+	an8855_reg_write(priv, AN8855_INTF_CTRL_11, val);
+
+	/* RX CDR - improve RX Jitter Tolerance */
+	an8855_reg_read(priv, AN8855_RG_QP_CDR_LPF_BOT_LIM, &val);
+	val &= ~(0x7 << 24);
+	val |= (0x5 << 24);
+	val &= ~(0x7 << 20);
+	val |= (0x5 << 20);
+	an8855_reg_write(priv, AN8855_RG_QP_CDR_LPF_BOT_LIM, val);
+
 	return 0;
 }
 
-- 
2.53.0

Re: [PATCH v1 0/3] net: mtk_eth: an8855: fix packet loss and sync with Linux

[David Lechner]

On 11/7/26 8:24 AM, Mikhail Zhilkin wrote:
> This patch series aligns the U-Boot Airoha AN8855 switch initialization
> code with the upstream Linux DSA driver
> (drivers/net/dsa/airoha/an8855.c), fixing several register configuration
> bugs and improving overall signal integrity.

I don't see this in linux-next, so I'm guessing you mean the proposed driver
(not accepted yet) [1]? We should state that clearly.

[1]: https://lore.kernel.org/all/20261009161102.38961-11-ansuelsmth@gmail.com/

> 
> The current default U-Boot configuration leaves the SerDes with marginal
> drive characteristics. On some hardware iterations, this results in
> severe packet loss (50-60%) and timeouts during TFTP recovery. This drop
> occurs because of marginal signal integrity on the internal 2500Base-X
> link connecting the switch to the CPU.
> 
> By correcting a bitwise shift overlap, enabling link error recovery, and
> applying the proper TX FIR / RX CDR analog tuning parameters used in
> Linux, this series ensures a stable physical link between the CPU and
> switch across different boards.
> 
> These changes have been run-tested on the CMCC RAX3000ME and Xiaomi
> AX3000T, both featuring the AN8855 switch, confirming stable network
> operation and reliable gigabit TFTP recovery.
> 

These sounds like real fixes, so each patch should have a Fixes tag.

Fixes: cedafee9ff39 ("net: mediatek: add support for Airoha AN8855 ethernet switch")


> Patch summary:
> - Patch 1 fixes a bitwise collision bug in the AN8855_RX_CTRL_8 register
>   that was accidentally overwriting previously set bits.
> - Patch 2 enables graceful link error recovery in AN8855_RX_CTRL_26
>   instead of explicitly disabling it.
> - Patch 3 ports the SerDes analog tuning parameters (TX Eye and RX
>   Jitter Tolerance) from Linux, resolving the packet loss issue on the
>   internal 2.5G CPU port.
> 
> Mikhail Zhilkin (3):
>   net: mtk_eth: an8855: fix bitwise collision in RX_CTRL_8 register
>   net: mtk_eth: an8855: enable link error recovery
>   net: mtk_eth: an8855: sync SerDes analog tuning with Linux driver
> 
>  drivers/net/mtk_eth/an8855.c | 31 ++++++++++++++++++++++++++++---
>  1 file changed, 28 insertions(+), 3 deletions(-)
> 

Re: [PATCH v1 1/3] net: mtk_eth: an8855: fix bitwise collision in RX_CTRL_8 register

[David Lechner]

On 11/7/26 8:24 AM, Mikhail Zhilkin wrote:
> In an8855_port_sgmii_init(), the bitwise operations for
> the AN8855_RX_CTRL_8 register contain a shifting error. The code
> attempts to set a value at shift 16 (0x200 << 16), but subsequently
> applies a mask and value shifted by 14 (0xfff << 14). This creates a
> bitwise collision where the second operation overlaps and overwrites the
> bits configured by the first operation, resulting in unintended register
> values.
> 
> Fix the shift offset for the lower bits from 14 to 0 to prevent
> overlap and correctly apply the exact values used in the upstream
> Linux driver.
> 
> Signed-off-by: Mikhail Zhilkin <csharper2005@gmail.com>
> ---
>  drivers/net/mtk_eth/an8855.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/net/mtk_eth/an8855.c b/drivers/net/mtk_eth/an8855.c
> index a2589a2ad31..eb037ec1382 100644
> --- a/drivers/net/mtk_eth/an8855.c
> +++ b/drivers/net/mtk_eth/an8855.c
> @@ -627,8 +627,8 @@ static int an8855_port_sgmii_init(struct an8855_switch_priv *priv, u32 port)
>  	an8855_reg_read(priv, AN8855_RX_CTRL_8, &val);
>  	val &= ~(0xfff << 16);
>  	val |= (0x200 << 16);
> -	val &= ~(0x7fff << 14);
> -	val |= (0xfff << 14);
> +	val &= ~(0x7fff << 0);
> +	val |= (0xfff << 0);

nit: we could drop the << 0 and ().

>  	an8855_reg_write(priv, AN8855_RX_CTRL_8, val);
>  
>  	/* Frequency memter */

Re: [PATCH v1 2/3] net: mtk_eth: an8855: enable link error recovery

[David Lechner]

On 11/7/26 8:24 AM, Mikhail Zhilkin wrote:
> Sync the Link Error Recovery configuration with the upstream Linux
> driver.
> 
> Currently, the U-Boot driver explicitly clears the
> AN8855_RG_LINK_ERRO_EN bit (bit 23) in the AN8855_RX_CTRL_26 register
> during SGMII initialization. Setting this bit instead of clearing it
> matches the Linux driver behavior, allowing the MAC/PCS to gracefully
> recover from momentary link errors on marginal hardware rather than
> dropping packets or the entire link.
> 
> Signed-off-by: Mikhail Zhilkin <csharper2005@gmail.com>
> ---
>  drivers/net/mtk_eth/an8855.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/net/mtk_eth/an8855.c b/drivers/net/mtk_eth/an8855.c
> index eb037ec1382..513f4534701 100644
> --- a/drivers/net/mtk_eth/an8855.c
> +++ b/drivers/net/mtk_eth/an8855.c
> @@ -599,7 +599,7 @@ static int an8855_port_sgmii_init(struct an8855_switch_priv *priv, u32 port)
>  	an8855_reg_write(priv, AN8855_PLL_CTRL_0, val);
>  
>  	an8855_reg_read(priv, AN8855_RX_CTRL_26, &val);
> -	val &= ~BIT(23);
> +	val |= BIT(23);

It looks like the proposed Linux patch also clears BIT(24) here.

>  	val |= BIT(26);
>  	an8855_reg_write(priv, AN8855_RX_CTRL_26, val);
>  

Re: [PATCH v1 3/3] net: mtk_eth: an8855: sync SerDes analog tuning with Linux driver

[David Lechner]

On 11/7/26 8:24 AM, Mikhail Zhilkin wrote:
> Port the TX FIR (TX Eye) and RX CDR (RX Jitter Tolerance) analog
> tuning parameters from the upstream Linux Airoha AN8855 DSA driver
> (drivers/net/dsa/airoha/an8855.c).
> 
> The default U-Boot configuration omits these register writes, leaving
> the SerDes with inferior default drive characteristics. On hardware
> iterations with minor silicon or trace variances, this marginal signal
> integrity leads to severe packet loss (50-60%) during TFTP recovery
> over the 2500Base-X link. Explicitly configuring AN8855_INTF_CTRL_10,
> AN8855_INTF_CTRL_11, and AN8855_RG_QP_CDR_LPF_BOT_LIM ensures a
> stable physical link across boards.
> 
> Signed-off-by: Mikhail Zhilkin <csharper2005@gmail.com>
> ---
>  drivers/net/mtk_eth/an8855.c | 25 +++++++++++++++++++++++++
>  1 file changed, 25 insertions(+)
> 
> diff --git a/drivers/net/mtk_eth/an8855.c b/drivers/net/mtk_eth/an8855.c
> index 513f4534701..f8f004e0914 100644
> --- a/drivers/net/mtk_eth/an8855.c
> +++ b/drivers/net/mtk_eth/an8855.c
> @@ -96,6 +96,8 @@
>  #define AN8855_SS_LCPLL_TDC_PCW_1		(AN8855_QP_PMA_TOP_BASE + 0x248)
>  #define AN8855_INTF_CTRL_8			(AN8855_QP_PMA_TOP_BASE + 0x320)
>  #define AN8855_INTF_CTRL_9			(AN8855_QP_PMA_TOP_BASE + 0x324)
> +#define AN8855_INTF_CTRL_10			(AN8855_QP_PMA_TOP_BASE + 0x328)
> +#define AN8855_INTF_CTRL_11			(AN8855_QP_PMA_TOP_BASE + 0x32c)
>  #define AN8855_PLL_CTRL_0			(AN8855_QP_PMA_TOP_BASE + 0x400)
>  #define AN8855_PLL_CTRL_2			(AN8855_QP_PMA_TOP_BASE + 0x408)
>  #define AN8855_PLL_CTRL_3			(AN8855_QP_PMA_TOP_BASE + 0x40c)
> @@ -113,6 +115,7 @@
>  #define AN8855_QP_ANA_CSR_BASE			0x1022f000
>  #define AN8855_RG_QP_RX_DAC_EN			(AN8855_QP_ANA_CSR_BASE + 0x00)
>  #define AN8855_RG_QP_RXAFE_RESERVE		(AN8855_QP_ANA_CSR_BASE + 0x04)
> +#define AN8855_RG_QP_CDR_LPF_BOT_LIM		(AN8855_QP_ANA_CSR_BASE + 0x08)
>  #define AN8855_RG_QP_CDR_LPF_MJV_LIM		(AN8855_QP_ANA_CSR_BASE + 0x0c)
>  #define AN8855_RG_QP_CDR_LPF_SETVALUE		(AN8855_QP_ANA_CSR_BASE + 0x14)
>  #define AN8855_RG_QP_CDR_PR_CKREF_DIV1		(AN8855_QP_ANA_CSR_BASE + 0x18)
> @@ -678,6 +681,28 @@ static int an8855_port_sgmii_init(struct an8855_switch_priv *priv, u32 port)
>  	an8855_reg_write(priv, AN8855_MSG_RX_LIK_STS_0, 0x01010107);
>  	an8855_reg_write(priv, AN8855_MSG_RX_LIK_STS_2, 0x00000EEF);
>  
> +	/* TX FIR - improve TX EYE */

Probably should mention in this comment that these are 2500BASE-X values.

> +	an8855_reg_read(priv, AN8855_INTF_CTRL_10, &val);
> +	val &= ~(0x1f << 24);
> +	val |= (0x04 << 24);
> +	val &= ~(0x1f << 16);
> +	val |= (0x00 << 16);

nit: don't really need this line - unless we are going to follow up later
with macros to give all of these names. And using GENMAK/FIELD_PREP/etc
in a followup would be nice too. Don't combine that with fixes patches
though.

> +	val |= BIT(29) | BIT(21);
> +	an8855_reg_write(priv, AN8855_INTF_CTRL_10, val);
> +
> +	an8855_reg_read(priv, AN8855_INTF_CTRL_11, &val);
> +	val &= ~(0x3f << 0);
> +	val |= BIT(6);
> +	an8855_reg_write(priv, AN8855_INTF_CTRL_11, val);
> +
> +	/* RX CDR - improve RX Jitter Tolerance */
> +	an8855_reg_read(priv, AN8855_RG_QP_CDR_LPF_BOT_LIM, &val);
> +	val &= ~(0x7 << 24);
> +	val |= (0x5 << 24);
> +	val &= ~(0x7 << 20);
> +	val |= (0x5 << 20);
> +	an8855_reg_write(priv, AN8855_RG_QP_CDR_LPF_BOT_LIM, val);
> +

I don't know if order matters here, but it looks like the proposed Linux
driver does this at the beginning of the init sequence rather than at the
end.

>  	return 0;
>  }
>