From: "qinjian[覃健]" <qinjian@cqplus1.com>
To: Arnd Bergmann <arnd@arndb.de>
Cc: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>,
Rob Herring <robh+dt@kernel.org>,
Michael Turquette <mturquette@baylibre.com>,
"Stephen Boyd" <sboyd@kernel.org>,
Thomas Gleixner <tglx@linutronix.de>,
Marc Zyngier <maz@kernel.org>,
Philipp Zabel <p.zabel@pengutronix.de>,
"Russell King - ARM Linux" <linux@armlinux.org.uk>,
Linux ARM <linux-arm-kernel@lists.infradead.org>,
DTML <devicetree@vger.kernel.org>,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
linux-clk <linux-clk@vger.kernel.org>
Subject: RE: [PATCH v12 5/9] clk: Add Sunplus SP7021 clock driver
Date: Fri, 1 Apr 2022 09:47:48 +0000 [thread overview]
Message-ID: <2fa0ce6048f6449d883e2454ceea9540@cqplus1.com> (raw)
In-Reply-To: <CAK8P3a0OGM4aiaE2Nfc=7XGkGwAbnB99-j3PhVUmuA1z2FWeKg@mail.gmail.com>
>
> > +static int sp_pll_enable(struct clk_hw *hw)
> > +{
> > + struct sp_pll *clk = to_sp_pll(hw);
> > + unsigned long flags;
> > +
> > + spin_lock_irqsave(clk->lock, flags);
> > + writel(BIT(clk->pd_bit + 16) | BIT(clk->pd_bit), clk->reg); /* power up */
> > + spin_unlock_irqrestore(clk->lock, flags);
> > +
> > + return 0;
> > +}
> > +
> > +static void sp_pll_disable(struct clk_hw *hw)
> > +{
> > + struct sp_pll *clk = to_sp_pll(hw);
> > + unsigned long flags;
> > +
> > + spin_lock_irqsave(clk->lock, flags);
> > + writel(BIT(clk->pd_bit + 16), clk->reg); /* power down */
> > + spin_unlock_irqrestore(clk->lock, flags);
> > +}
>
> What does the spinlock actually protect here? As writel() is posted, it
> can already leak of of the lock, and the inputs would appear to be
> constant.
>
These code is refered from other clk driver.
But, other driver need read then write, so need lock protected.
Our HW is HIWORD_MASKED_REG, means modify bits no need to read, just 1 write only.
So, the lock is useless.
Did I right?
> > + /* This memory region include multi HW regs in discontinuous order.
> > + * clk driver used some discontinuous areas in the memory region.
> > + * Using devm_platform_ioremap_resource() would conflicted with other drivers.
> > + */
> > + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > + sp_clk_base = devm_ioremap(dev, res->start, resource_size(res));
> > + if (!sp_clk_base)
> > + return -ENXIO;
>
> Can you explain this comment in more detail? Generally, the 'reg' properties
> of drivers should not overlap, so it is supposed to be safe to call
> devm_platform_ioremap_resource() here.
>
> We discussed this in the context of the iop driver that did have overlapping
> registers with this driver, and that was incorrect. Are there any other drivers
> that conflict with the clk driver?
>
> Arnd
I means, I must split up the origin reg region into 4 small pieces,
and call devm_platform_ioremap_resource() 4 times.
Did I should follow this way?
WARNING: multiple messages have this Message-ID (diff)
From: "qinjian[覃健]" <qinjian@cqplus1.com>
To: Arnd Bergmann <arnd@arndb.de>
Cc: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>,
Rob Herring <robh+dt@kernel.org>,
Michael Turquette <mturquette@baylibre.com>,
"Stephen Boyd" <sboyd@kernel.org>,
Thomas Gleixner <tglx@linutronix.de>,
Marc Zyngier <maz@kernel.org>,
Philipp Zabel <p.zabel@pengutronix.de>,
"Russell King - ARM Linux" <linux@armlinux.org.uk>,
Linux ARM <linux-arm-kernel@lists.infradead.org>,
DTML <devicetree@vger.kernel.org>,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
linux-clk <linux-clk@vger.kernel.org>
Subject: RE: [PATCH v12 5/9] clk: Add Sunplus SP7021 clock driver
Date: Fri, 1 Apr 2022 09:47:48 +0000 [thread overview]
Message-ID: <2fa0ce6048f6449d883e2454ceea9540@cqplus1.com> (raw)
In-Reply-To: <CAK8P3a0OGM4aiaE2Nfc=7XGkGwAbnB99-j3PhVUmuA1z2FWeKg@mail.gmail.com>
>
> > +static int sp_pll_enable(struct clk_hw *hw)
> > +{
> > + struct sp_pll *clk = to_sp_pll(hw);
> > + unsigned long flags;
> > +
> > + spin_lock_irqsave(clk->lock, flags);
> > + writel(BIT(clk->pd_bit + 16) | BIT(clk->pd_bit), clk->reg); /* power up */
> > + spin_unlock_irqrestore(clk->lock, flags);
> > +
> > + return 0;
> > +}
> > +
> > +static void sp_pll_disable(struct clk_hw *hw)
> > +{
> > + struct sp_pll *clk = to_sp_pll(hw);
> > + unsigned long flags;
> > +
> > + spin_lock_irqsave(clk->lock, flags);
> > + writel(BIT(clk->pd_bit + 16), clk->reg); /* power down */
> > + spin_unlock_irqrestore(clk->lock, flags);
> > +}
>
> What does the spinlock actually protect here? As writel() is posted, it
> can already leak of of the lock, and the inputs would appear to be
> constant.
>
These code is refered from other clk driver.
But, other driver need read then write, so need lock protected.
Our HW is HIWORD_MASKED_REG, means modify bits no need to read, just 1 write only.
So, the lock is useless.
Did I right?
> > + /* This memory region include multi HW regs in discontinuous order.
> > + * clk driver used some discontinuous areas in the memory region.
> > + * Using devm_platform_ioremap_resource() would conflicted with other drivers.
> > + */
> > + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > + sp_clk_base = devm_ioremap(dev, res->start, resource_size(res));
> > + if (!sp_clk_base)
> > + return -ENXIO;
>
> Can you explain this comment in more detail? Generally, the 'reg' properties
> of drivers should not overlap, so it is supposed to be safe to call
> devm_platform_ioremap_resource() here.
>
> We discussed this in the context of the iop driver that did have overlapping
> registers with this driver, and that was incorrect. Are there any other drivers
> that conflict with the clk driver?
>
> Arnd
I means, I must split up the origin reg region into 4 small pieces,
and call devm_platform_ioremap_resource() 4 times.
Did I should follow this way?
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next prev parent reply other threads:[~2022-04-01 9:49 UTC|newest]
Thread overview: 58+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-03-31 8:29 [PATCH v12 0/9] Add Sunplus SP7021 SoC Support Qin Jian
2022-03-31 8:29 ` Qin Jian
2022-03-31 8:29 ` [PATCH v12 1/9] dt-bindings: arm: sunplus: Add bindings for Sunplus SP7021 SoC boards Qin Jian
2022-03-31 8:29 ` Qin Jian
2022-03-31 8:29 ` [PATCH v12 2/9] dt-bindings: reset: Add bindings for SP7021 reset driver Qin Jian
2022-03-31 8:29 ` Qin Jian
2022-03-31 8:58 ` Arnd Bergmann
2022-03-31 8:58 ` Arnd Bergmann
2022-04-01 8:24 ` qinjian[覃健]
2022-04-01 8:24 ` qinjian[覃健]
2022-03-31 8:29 ` [PATCH v12 3/9] reset: Add Sunplus " Qin Jian
2022-03-31 8:29 ` Qin Jian
2022-03-31 8:59 ` Arnd Bergmann
2022-03-31 8:59 ` Arnd Bergmann
2022-03-31 8:29 ` [PATCH v12 4/9] dt-bindings: clock: Add bindings for SP7021 clock driver Qin Jian
2022-03-31 8:29 ` Qin Jian
2022-03-31 20:21 ` Krzysztof Kozlowski
2022-03-31 20:21 ` Krzysztof Kozlowski
2022-04-01 9:19 ` qinjian[覃健]
2022-04-01 9:19 ` qinjian[覃健]
2022-04-01 9:32 ` Krzysztof Kozlowski
2022-04-01 9:32 ` Krzysztof Kozlowski
2022-03-31 8:29 ` [PATCH v12 5/9] clk: Add Sunplus " Qin Jian
2022-03-31 8:29 ` Qin Jian
2022-03-31 9:22 ` Arnd Bergmann
2022-03-31 9:22 ` Arnd Bergmann
2022-04-01 9:47 ` qinjian[覃健] [this message]
2022-04-01 9:47 ` qinjian[覃健]
2022-04-01 10:09 ` Arnd Bergmann
2022-04-01 10:09 ` Arnd Bergmann
2022-04-02 3:37 ` qinjian[覃健]
2022-04-02 3:37 ` qinjian[覃健]
2022-03-31 8:29 ` [PATCH v12 6/9] dt-bindings: interrupt-controller: Add bindings for SP7021 interrupt controller Qin Jian
2022-03-31 8:29 ` Qin Jian
2022-03-31 20:44 ` Rob Herring
2022-03-31 20:44 ` Rob Herring
2022-04-01 2:29 ` qinjian[覃健]
2022-04-01 2:29 ` qinjian[覃健]
2022-04-01 17:53 ` Rob Herring
2022-04-01 17:53 ` Rob Herring
2022-04-02 2:43 ` qinjian[覃健]
2022-04-02 2:43 ` qinjian[覃健]
2022-03-31 8:29 ` [PATCH v12 7/9] irqchip: Add Sunplus SP7021 interrupt controller driver Qin Jian
2022-03-31 8:29 ` Qin Jian
2022-03-31 9:17 ` Arnd Bergmann
2022-03-31 9:17 ` Arnd Bergmann
2022-04-01 7:17 ` qinjian[覃健]
2022-04-01 7:17 ` qinjian[覃健]
2022-03-31 8:29 ` [PATCH v12 8/9] ARM: sunplus: Add initial support for Sunplus SP7021 SoC Qin Jian
2022-03-31 8:29 ` Qin Jian
2022-03-31 9:03 ` Arnd Bergmann
2022-03-31 9:03 ` Arnd Bergmann
2022-03-31 8:29 ` [PATCH v12 9/9] ARM: sp7021_defconfig: Add Sunplus SP7021 defconfig Qin Jian
2022-03-31 8:29 ` Qin Jian
2022-03-31 9:09 ` Arnd Bergmann
2022-03-31 9:09 ` Arnd Bergmann
2022-04-01 7:08 ` qinjian[覃健]
2022-04-01 7:08 ` qinjian[覃健]
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