* [PATCH] arm: irq: l2c: do not print error in case of missing l2c from dtb @ 2016-01-12 6:34 ` Andi Shyti 0 siblings, 0 replies; 16+ messages in thread From: Andi Shyti @ 2016-01-12 6:34 UTC (permalink / raw) To: linux-arm-kernel In some architectures the L2 cache controller is integrated in the processor's block itself and it doesn't use any external cache controller. This means that an entry in the board's dtb related to the l2c is not necessary. Distinguish between error codes and print just an information in case of -ENODEV. This patch converts the following error message: L2C: failed to init: -19 to the following info: no L2C controller entry found in the dtb on boards like odroid-xu4, cortex A7/A15, which don't have external cache controller. Signed-off-by: Andi Shyti <andi.shyti@samsung.com> Reported-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> --- arch/arm/kernel/irq.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm/kernel/irq.c b/arch/arm/kernel/irq.c index 1d45320..abe1ad8 100644 --- a/arch/arm/kernel/irq.c +++ b/arch/arm/kernel/irq.c @@ -95,7 +95,9 @@ void __init init_IRQ(void) outer_cache.write_sec = machine_desc->l2c_write_sec; ret = l2x0_of_init(machine_desc->l2c_aux_val, machine_desc->l2c_aux_mask); - if (ret) + if (ret == -ENODEV) + pr_info("no L2C controller entry found in the dtb\n"); + else if (ret) pr_err("L2C: failed to init: %d\n", ret); } -- 2.6.4 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH] arm: irq: l2c: do not print error in case of missing l2c from dtb @ 2016-01-12 6:34 ` Andi Shyti 0 siblings, 0 replies; 16+ messages in thread From: Andi Shyti @ 2016-01-12 6:34 UTC (permalink / raw) To: linux-arm-kernel Cc: linux, tony, robh, tglx, olof, tomasz.figa, jiang.liu, yamada.masahiro, linux-kernel, k.kozlowski, m.szyprowski, andi.shyti, andi In some architectures the L2 cache controller is integrated in the processor's block itself and it doesn't use any external cache controller. This means that an entry in the board's dtb related to the l2c is not necessary. Distinguish between error codes and print just an information in case of -ENODEV. This patch converts the following error message: L2C: failed to init: -19 to the following info: no L2C controller entry found in the dtb on boards like odroid-xu4, cortex A7/A15, which don't have external cache controller. Signed-off-by: Andi Shyti <andi.shyti@samsung.com> Reported-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> --- arch/arm/kernel/irq.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm/kernel/irq.c b/arch/arm/kernel/irq.c index 1d45320..abe1ad8 100644 --- a/arch/arm/kernel/irq.c +++ b/arch/arm/kernel/irq.c @@ -95,7 +95,9 @@ void __init init_IRQ(void) outer_cache.write_sec = machine_desc->l2c_write_sec; ret = l2x0_of_init(machine_desc->l2c_aux_val, machine_desc->l2c_aux_mask); - if (ret) + if (ret == -ENODEV) + pr_info("no L2C controller entry found in the dtb\n"); + else if (ret) pr_err("L2C: failed to init: %d\n", ret); } -- 2.6.4 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH] arm: irq: l2c: do not print error in case of missing l2c from dtb 2016-01-12 6:34 ` Andi Shyti @ 2016-01-12 7:11 ` Joe Perches -1 siblings, 0 replies; 16+ messages in thread From: Joe Perches @ 2016-01-12 7:11 UTC (permalink / raw) To: linux-arm-kernel On Tue, 2016-01-12 at 15:34 +0900, Andi Shyti wrote: > In some architectures the L2 cache controller is integrated in the > processor's block itself and it doesn't use any external cache > controller. This means that an entry in the board's dtb related > to the l2c is not necessary. > > Distinguish between error codes and print just an information in > case of -ENODEV. trivia: > diff --git a/arch/arm/kernel/irq.c b/arch/arm/kernel/irq.c [] > @@ -95,7 +95,9 @@ void __init init_IRQ(void) > ? outer_cache.write_sec = machine_desc->l2c_write_sec; > ? ret = l2x0_of_init(machine_desc->l2c_aux_val, > ? ???machine_desc->l2c_aux_mask); > - if (ret) > + if (ret == -ENODEV) > + pr_info("no L2C controller entry found in the dtb\n"); Perhaps this would be more consistent if it was pr_info("L2C: no controller entry found in the dtb\n"); > > + else if (ret) > ? pr_err("L2C: failed to init: %d\n", ret); > ? } > ? ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH] arm: irq: l2c: do not print error in case of missing l2c from dtb @ 2016-01-12 7:11 ` Joe Perches 0 siblings, 0 replies; 16+ messages in thread From: Joe Perches @ 2016-01-12 7:11 UTC (permalink / raw) To: Andi Shyti, linux-arm-kernel Cc: linux, tony, robh, tglx, olof, tomasz.figa, jiang.liu, yamada.masahiro, linux-kernel, k.kozlowski, m.szyprowski, andi On Tue, 2016-01-12 at 15:34 +0900, Andi Shyti wrote: > In some architectures the L2 cache controller is integrated in the > processor's block itself and it doesn't use any external cache > controller. This means that an entry in the board's dtb related > to the l2c is not necessary. > > Distinguish between error codes and print just an information in > case of -ENODEV. trivia: > diff --git a/arch/arm/kernel/irq.c b/arch/arm/kernel/irq.c [] > @@ -95,7 +95,9 @@ void __init init_IRQ(void) > outer_cache.write_sec = machine_desc->l2c_write_sec; > ret = l2x0_of_init(machine_desc->l2c_aux_val, > machine_desc->l2c_aux_mask); > - if (ret) > + if (ret == -ENODEV) > + pr_info("no L2C controller entry found in the dtb\n"); Perhaps this would be more consistent if it was pr_info("L2C: no controller entry found in the dtb\n"); > > + else if (ret) > pr_err("L2C: failed to init: %d\n", ret); > } > ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v2] arm: irq: l2c: do not print error in case of missing l2c from dtb 2016-01-12 7:11 ` Joe Perches @ 2016-01-12 7:24 ` Andi Shyti -1 siblings, 0 replies; 16+ messages in thread From: Andi Shyti @ 2016-01-12 7:24 UTC (permalink / raw) To: linux-arm-kernel In some architectures the L2 cache controller is integrated in the processor's block itself and it doesn't use any external cache controller. This means that an entry in the board's dtb related to the l2c is not necessary. Distinguish between error codes and print just an information in case of -ENODEV. This patch converts the following error message: L2C: failed to init: -19 to the following info: L2C: no controller entry found in the dtb on boards like odroid-xu4, cortex A7/A15, which don't have external cache controller. Signed-off-by: Andi Shyti <andi.shyti@samsung.com> Reported-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> --- Thanks Joe, makes sense! Andi arch/arm/kernel/irq.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm/kernel/irq.c b/arch/arm/kernel/irq.c index 1d45320..714b5d6 100644 --- a/arch/arm/kernel/irq.c +++ b/arch/arm/kernel/irq.c @@ -95,7 +95,9 @@ void __init init_IRQ(void) outer_cache.write_sec = machine_desc->l2c_write_sec; ret = l2x0_of_init(machine_desc->l2c_aux_val, machine_desc->l2c_aux_mask); - if (ret) + if (ret == -ENODEV) + pr_info("L2C: no controller entry found in the dtb\n"); + else if (ret) pr_err("L2C: failed to init: %d\n", ret); } -- 2.6.4 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v2] arm: irq: l2c: do not print error in case of missing l2c from dtb @ 2016-01-12 7:24 ` Andi Shyti 0 siblings, 0 replies; 16+ messages in thread From: Andi Shyti @ 2016-01-12 7:24 UTC (permalink / raw) To: linux-arm-kernel Cc: linux, tony, robh, tglx, olof, tomasz.figa, jiang.liu, yamada.masahiro, linux-kernel, k.kozlowski, m.szyprowski, andi.shyti, andi In some architectures the L2 cache controller is integrated in the processor's block itself and it doesn't use any external cache controller. This means that an entry in the board's dtb related to the l2c is not necessary. Distinguish between error codes and print just an information in case of -ENODEV. This patch converts the following error message: L2C: failed to init: -19 to the following info: L2C: no controller entry found in the dtb on boards like odroid-xu4, cortex A7/A15, which don't have external cache controller. Signed-off-by: Andi Shyti <andi.shyti@samsung.com> Reported-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> --- Thanks Joe, makes sense! Andi arch/arm/kernel/irq.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm/kernel/irq.c b/arch/arm/kernel/irq.c index 1d45320..714b5d6 100644 --- a/arch/arm/kernel/irq.c +++ b/arch/arm/kernel/irq.c @@ -95,7 +95,9 @@ void __init init_IRQ(void) outer_cache.write_sec = machine_desc->l2c_write_sec; ret = l2x0_of_init(machine_desc->l2c_aux_val, machine_desc->l2c_aux_mask); - if (ret) + if (ret == -ENODEV) + pr_info("L2C: no controller entry found in the dtb\n"); + else if (ret) pr_err("L2C: failed to init: %d\n", ret); } -- 2.6.4 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v2] arm: irq: l2c: do not print error in case of missing l2c from dtb 2016-01-12 7:24 ` Andi Shyti @ 2016-01-12 8:28 ` Krzysztof Kozlowski -1 siblings, 0 replies; 16+ messages in thread From: Krzysztof Kozlowski @ 2016-01-12 8:28 UTC (permalink / raw) To: linux-arm-kernel On 12.01.2016 16:24, Andi Shyti wrote: > In some architectures the L2 cache controller is integrated in the > processor's block itself and it doesn't use any external cache > controller. This means that an entry in the board's dtb related > to the l2c is not necessary. > > Distinguish between error codes and print just an information in > case of -ENODEV. > > This patch converts the following error message: > > L2C: failed to init: -19 > > to the following info: > > L2C: no controller entry found in the dtb > > on boards like odroid-xu4, cortex A7/A15, which don't have > external cache controller. > > Signed-off-by: Andi Shyti <andi.shyti@samsung.com> > Reported-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> > --- > > Thanks Joe, > > makes sense! > > Andi > > arch/arm/kernel/irq.c | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) Works (Odroid XU3, Exynos5422) and looks good for me: Tested-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Best regards, Krzysztof ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v2] arm: irq: l2c: do not print error in case of missing l2c from dtb @ 2016-01-12 8:28 ` Krzysztof Kozlowski 0 siblings, 0 replies; 16+ messages in thread From: Krzysztof Kozlowski @ 2016-01-12 8:28 UTC (permalink / raw) To: Andi Shyti, linux-arm-kernel Cc: linux, tony, robh, tglx, olof, tomasz.figa, jiang.liu, yamada.masahiro, linux-kernel, m.szyprowski, andi On 12.01.2016 16:24, Andi Shyti wrote: > In some architectures the L2 cache controller is integrated in the > processor's block itself and it doesn't use any external cache > controller. This means that an entry in the board's dtb related > to the l2c is not necessary. > > Distinguish between error codes and print just an information in > case of -ENODEV. > > This patch converts the following error message: > > L2C: failed to init: -19 > > to the following info: > > L2C: no controller entry found in the dtb > > on boards like odroid-xu4, cortex A7/A15, which don't have > external cache controller. > > Signed-off-by: Andi Shyti <andi.shyti@samsung.com> > Reported-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> > --- > > Thanks Joe, > > makes sense! > > Andi > > arch/arm/kernel/irq.c | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) Works (Odroid XU3, Exynos5422) and looks good for me: Tested-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Best regards, Krzysztof ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH] arm: irq: l2c: do not print error in case of missing l2c from dtb 2016-01-12 7:11 ` Joe Perches @ 2016-01-12 8:35 ` Marek Szyprowski -1 siblings, 0 replies; 16+ messages in thread From: Marek Szyprowski @ 2016-01-12 8:35 UTC (permalink / raw) To: linux-arm-kernel Hello, On 2016-01-12 08:11, Joe Perches wrote: > On Tue, 2016-01-12 at 15:34 +0900, Andi Shyti wrote: >> In some architectures the L2 cache controller is integrated in the >> processor's block itself and it doesn't use any external cache >> controller. This means that an entry in the board's dtb related >> to the l2c is not necessary. >> >> Distinguish between error codes and print just an information in >> case of -ENODEV. > trivia: > >> diff --git a/arch/arm/kernel/irq.c b/arch/arm/kernel/irq.c > [] >> @@ -95,7 +95,9 @@ void __init init_IRQ(void) >> outer_cache.write_sec = machine_desc->l2c_write_sec; >> ret = l2x0_of_init(machine_desc->l2c_aux_val, >> machine_desc->l2c_aux_mask); >> - if (ret) >> + if (ret == -ENODEV) >> + pr_info("no L2C controller entry found in the dtb\n"); > Perhaps this would be more consistent if it was > pr_info("L2C: no controller entry found in the dtb\n"); Frankly I see no benefit of such message. It still might confuse users that there is something wrong with your DT. When driver initialization fails with -ENODEV, then no message is usually displayed. >> + else if (ret) >> pr_err("L2C: failed to init: %d\n", ret); >> } >> > > Best regards -- Marek Szyprowski, PhD Samsung R&D Institute Poland ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH] arm: irq: l2c: do not print error in case of missing l2c from dtb @ 2016-01-12 8:35 ` Marek Szyprowski 0 siblings, 0 replies; 16+ messages in thread From: Marek Szyprowski @ 2016-01-12 8:35 UTC (permalink / raw) To: Joe Perches, Andi Shyti, linux-arm-kernel Cc: linux, tony, robh, tglx, olof, tomasz.figa, jiang.liu, yamada.masahiro, linux-kernel, k.kozlowski, andi Hello, On 2016-01-12 08:11, Joe Perches wrote: > On Tue, 2016-01-12 at 15:34 +0900, Andi Shyti wrote: >> In some architectures the L2 cache controller is integrated in the >> processor's block itself and it doesn't use any external cache >> controller. This means that an entry in the board's dtb related >> to the l2c is not necessary. >> >> Distinguish between error codes and print just an information in >> case of -ENODEV. > trivia: > >> diff --git a/arch/arm/kernel/irq.c b/arch/arm/kernel/irq.c > [] >> @@ -95,7 +95,9 @@ void __init init_IRQ(void) >> outer_cache.write_sec = machine_desc->l2c_write_sec; >> ret = l2x0_of_init(machine_desc->l2c_aux_val, >> machine_desc->l2c_aux_mask); >> - if (ret) >> + if (ret == -ENODEV) >> + pr_info("no L2C controller entry found in the dtb\n"); > Perhaps this would be more consistent if it was > pr_info("L2C: no controller entry found in the dtb\n"); Frankly I see no benefit of such message. It still might confuse users that there is something wrong with your DT. When driver initialization fails with -ENODEV, then no message is usually displayed. >> + else if (ret) >> pr_err("L2C: failed to init: %d\n", ret); >> } >> > > Best regards -- Marek Szyprowski, PhD Samsung R&D Institute Poland ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v3] arm: irq: l2c: do not print error in case of missing l2c from dtb 2016-01-12 8:35 ` Marek Szyprowski @ 2016-01-12 10:11 ` Andi Shyti -1 siblings, 0 replies; 16+ messages in thread From: Andi Shyti @ 2016-01-12 10:11 UTC (permalink / raw) To: linux-arm-kernel In some architectures the L2 cache controller is integrated in the processor's block itself and it doesn't use any external cache controller. This means that an entry in the board's dtb related to the l2c is not necessary. Distinguish between error codes and do not print anything in case l2x0_of_init() doesn't find any L2C DTB entry and returns -ENODEV. This patch mutes the following error message: L2C: failed to init: -19 on boards like odroid-xu4, cortex A7/A15, which don't have external cache controller. Signed-off-by: Andi Shyti <andi.shyti@samsung.com> Reported-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> --- Hi, here is a second version. An alternative would be to print with pr_dbg, but then it's a matter of taste. V1, and V2 print a message in case the l2c dtb entry is not found (the V2 has a better print rephrase suggested by Joe) V3 ignores the case of -enodev for l2c and doesn't print anything Thanks, Andi arch/arm/kernel/irq.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/kernel/irq.c b/arch/arm/kernel/irq.c index 1d45320..ece04a4 100644 --- a/arch/arm/kernel/irq.c +++ b/arch/arm/kernel/irq.c @@ -95,7 +95,7 @@ void __init init_IRQ(void) outer_cache.write_sec = machine_desc->l2c_write_sec; ret = l2x0_of_init(machine_desc->l2c_aux_val, machine_desc->l2c_aux_mask); - if (ret) + if (ret && ret != -ENODEV) pr_err("L2C: failed to init: %d\n", ret); } -- 2.6.4 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v3] arm: irq: l2c: do not print error in case of missing l2c from dtb @ 2016-01-12 10:11 ` Andi Shyti 0 siblings, 0 replies; 16+ messages in thread From: Andi Shyti @ 2016-01-12 10:11 UTC (permalink / raw) To: linux-arm-kernel Cc: linux, tony, robh, tglx, olof, tomasz.figa, jiang.liu, yamada.masahiro, linux-kernel, k.kozlowski, m.szyprowski, andi.shyti, andi In some architectures the L2 cache controller is integrated in the processor's block itself and it doesn't use any external cache controller. This means that an entry in the board's dtb related to the l2c is not necessary. Distinguish between error codes and do not print anything in case l2x0_of_init() doesn't find any L2C DTB entry and returns -ENODEV. This patch mutes the following error message: L2C: failed to init: -19 on boards like odroid-xu4, cortex A7/A15, which don't have external cache controller. Signed-off-by: Andi Shyti <andi.shyti@samsung.com> Reported-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> --- Hi, here is a second version. An alternative would be to print with pr_dbg, but then it's a matter of taste. V1, and V2 print a message in case the l2c dtb entry is not found (the V2 has a better print rephrase suggested by Joe) V3 ignores the case of -enodev for l2c and doesn't print anything Thanks, Andi arch/arm/kernel/irq.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/kernel/irq.c b/arch/arm/kernel/irq.c index 1d45320..ece04a4 100644 --- a/arch/arm/kernel/irq.c +++ b/arch/arm/kernel/irq.c @@ -95,7 +95,7 @@ void __init init_IRQ(void) outer_cache.write_sec = machine_desc->l2c_write_sec; ret = l2x0_of_init(machine_desc->l2c_aux_val, machine_desc->l2c_aux_mask); - if (ret) + if (ret && ret != -ENODEV) pr_err("L2C: failed to init: %d\n", ret); } -- 2.6.4 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v3] arm: irq: l2c: do not print error in case of missing l2c from dtb 2016-01-12 10:11 ` Andi Shyti @ 2016-01-12 23:55 ` Krzysztof Kozlowski -1 siblings, 0 replies; 16+ messages in thread From: Krzysztof Kozlowski @ 2016-01-12 23:55 UTC (permalink / raw) To: linux-arm-kernel On 12.01.2016 19:11, Andi Shyti wrote: > In some architectures the L2 cache controller is integrated in the > processor's block itself and it doesn't use any external cache > controller. This means that an entry in the board's dtb related > to the l2c is not necessary. > > Distinguish between error codes and do not print anything in case > l2x0_of_init() doesn't find any L2C DTB entry and returns -ENODEV. > > This patch mutes the following error message: > > L2C: failed to init: -19 > > on boards like odroid-xu4, cortex A7/A15, which don't have > external cache controller. > > Signed-off-by: Andi Shyti <andi.shyti@samsung.com> > Reported-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> > Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> > --- > Hi, > > here is a second version. An alternative would be to print with > pr_dbg, but then it's a matter of taste. > > V1, and V2 print a message in case the l2c dtb entry is not found > (the V2 has a better print rephrase suggested by Joe) > > V3 ignores the case of -enodev for l2c and doesn't print anything > > Thanks, > Andi Looks good to me, as v2 did. Works fine: Tested-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> BR, KRzysztof ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v3] arm: irq: l2c: do not print error in case of missing l2c from dtb @ 2016-01-12 23:55 ` Krzysztof Kozlowski 0 siblings, 0 replies; 16+ messages in thread From: Krzysztof Kozlowski @ 2016-01-12 23:55 UTC (permalink / raw) To: Andi Shyti, linux-arm-kernel Cc: linux, tony, robh, tglx, olof, tomasz.figa, jiang.liu, yamada.masahiro, linux-kernel, m.szyprowski, andi On 12.01.2016 19:11, Andi Shyti wrote: > In some architectures the L2 cache controller is integrated in the > processor's block itself and it doesn't use any external cache > controller. This means that an entry in the board's dtb related > to the l2c is not necessary. > > Distinguish between error codes and do not print anything in case > l2x0_of_init() doesn't find any L2C DTB entry and returns -ENODEV. > > This patch mutes the following error message: > > L2C: failed to init: -19 > > on boards like odroid-xu4, cortex A7/A15, which don't have > external cache controller. > > Signed-off-by: Andi Shyti <andi.shyti@samsung.com> > Reported-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> > Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> > --- > Hi, > > here is a second version. An alternative would be to print with > pr_dbg, but then it's a matter of taste. > > V1, and V2 print a message in case the l2c dtb entry is not found > (the V2 has a better print rephrase suggested by Joe) > > V3 ignores the case of -enodev for l2c and doesn't print anything > > Thanks, > Andi Looks good to me, as v2 did. Works fine: Tested-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> BR, KRzysztof ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v3] arm: irq: l2c: do not print error in case of missing l2c from dtb 2016-01-12 10:11 ` Andi Shyti @ 2016-01-20 18:02 ` Javier Martinez Canillas -1 siblings, 0 replies; 16+ messages in thread From: Javier Martinez Canillas @ 2016-01-20 18:02 UTC (permalink / raw) To: linux-arm-kernel Hello Andi, On Tue, Jan 12, 2016 at 7:11 AM, Andi Shyti <andi.shyti@samsung.com> wrote: > In some architectures the L2 cache controller is integrated in the > processor's block itself and it doesn't use any external cache > controller. This means that an entry in the board's dtb related > to the l2c is not necessary. > > Distinguish between error codes and do not print anything in case > l2x0_of_init() doesn't find any L2C DTB entry and returns -ENODEV. > > This patch mutes the following error message: > > L2C: failed to init: -19 > > on boards like odroid-xu4, cortex A7/A15, which don't have > external cache controller. > The patch also looks good to me and makes the error message to go away in my Exynos5800 Peach Pi. Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com> Tested-by: Javier Martinez Canillas <javier@osg.samsung.com> Best regards, Javier ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v3] arm: irq: l2c: do not print error in case of missing l2c from dtb @ 2016-01-20 18:02 ` Javier Martinez Canillas 0 siblings, 0 replies; 16+ messages in thread From: Javier Martinez Canillas @ 2016-01-20 18:02 UTC (permalink / raw) To: Andi Shyti Cc: linux-arm-kernel@lists.infradead.org, Krzysztof Kozłowski, Russell King, Tony Lindgren, Tomasz Figa, Linux Kernel, yamada.masahiro, andi, Olof Johansson, Thomas Gleixner, Jiang Liu, Marek Szyprowski Hello Andi, On Tue, Jan 12, 2016 at 7:11 AM, Andi Shyti <andi.shyti@samsung.com> wrote: > In some architectures the L2 cache controller is integrated in the > processor's block itself and it doesn't use any external cache > controller. This means that an entry in the board's dtb related > to the l2c is not necessary. > > Distinguish between error codes and do not print anything in case > l2x0_of_init() doesn't find any L2C DTB entry and returns -ENODEV. > > This patch mutes the following error message: > > L2C: failed to init: -19 > > on boards like odroid-xu4, cortex A7/A15, which don't have > external cache controller. > The patch also looks good to me and makes the error message to go away in my Exynos5800 Peach Pi. Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com> Tested-by: Javier Martinez Canillas <javier@osg.samsung.com> Best regards, Javier ^ permalink raw reply [flat|nested] 16+ messages in thread
end of thread, other threads:[~2016-01-20 18:02 UTC | newest] Thread overview: 16+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2016-01-12 6:34 [PATCH] arm: irq: l2c: do not print error in case of missing l2c from dtb Andi Shyti 2016-01-12 6:34 ` Andi Shyti 2016-01-12 7:11 ` Joe Perches 2016-01-12 7:11 ` Joe Perches 2016-01-12 7:24 ` [PATCH v2] " Andi Shyti 2016-01-12 7:24 ` Andi Shyti 2016-01-12 8:28 ` Krzysztof Kozlowski 2016-01-12 8:28 ` Krzysztof Kozlowski 2016-01-12 8:35 ` [PATCH] " Marek Szyprowski 2016-01-12 8:35 ` Marek Szyprowski 2016-01-12 10:11 ` [PATCH v3] " Andi Shyti 2016-01-12 10:11 ` Andi Shyti 2016-01-12 23:55 ` Krzysztof Kozlowski 2016-01-12 23:55 ` Krzysztof Kozlowski 2016-01-20 18:02 ` Javier Martinez Canillas 2016-01-20 18:02 ` Javier Martinez Canillas
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.