From: Shameerali Kolothum Thodi via <qemu-arm@nongnu.org>
To: "Daniel P. Berrangé" <berrange@redhat.com>
Cc: Donald Dutile <ddutile@redhat.com>,
Markus Armbruster <armbru@redhat.com>,
Shameer Kolothum via <qemu-devel@nongnu.org>,
"qemu-arm@nongnu.org" <qemu-arm@nongnu.org>,
"eric.auger@redhat.com" <eric.auger@redhat.com>,
"peter.maydell@linaro.org" <peter.maydell@linaro.org>,
"jgg@nvidia.com" <jgg@nvidia.com>,
"nicolinc@nvidia.com" <nicolinc@nvidia.com>,
"nathanc@nvidia.com" <nathanc@nvidia.com>,
"mochs@nvidia.com" <mochs@nvidia.com>,
"smostafa@google.com" <smostafa@google.com>,
Linuxarm <linuxarm@huawei.com>,
"Wangzhou (B)" <wangzhou1@hisilicon.com>,
jiangkunkun <jiangkunkun@huawei.com>,
Jonathan Cameron <jonathan.cameron@huawei.com>,
"zhangfei.gao@linaro.org" <zhangfei.gao@linaro.org>
Subject: RE: [PATCH v2 1/6] hw/arm/smmuv3: Add support to associate a PCIe RC
Date: Fri, 9 May 2025 08:18:11 +0000 [thread overview]
Message-ID: <5b46c81a412f410494f28a2f9ebb9430@huawei.com> (raw)
In-Reply-To: <aB25ZRu7pCJNpamt@redhat.com>
> -----Original Message-----
> From: Daniel P. Berrangé <berrange@redhat.com>
> Sent: Friday, May 9, 2025 9:14 AM
> To: Shameerali Kolothum Thodi <shameerali.kolothum.thodi@huawei.com>
> Cc: Donald Dutile <ddutile@redhat.com>; Markus Armbruster
> <armbru@redhat.com>; Shameer Kolothum via <qemu-
> devel@nongnu.org>; qemu-arm@nongnu.org; eric.auger@redhat.com;
> peter.maydell@linaro.org; jgg@nvidia.com; nicolinc@nvidia.com;
> nathanc@nvidia.com; mochs@nvidia.com; smostafa@google.com; Linuxarm
> <linuxarm@huawei.com>; Wangzhou (B) <wangzhou1@hisilicon.com>;
> jiangkunkun <jiangkunkun@huawei.com>; Jonathan Cameron
> <jonathan.cameron@huawei.com>; zhangfei.gao@linaro.org
> Subject: Re: [PATCH v2 1/6] hw/arm/smmuv3: Add support to associate a
> PCIe RC
>
[...]
> > > - bus pcie, id=pcie.<num>
> > > - device iommu=[intel_iommu|smmuv3|amd_iommu], bus=[sysbus |
> > > pcie.<num>], id=iommu.<num>
> > > [Yes, I'm sticking with 'iommu' as the generic naming... everyone thinks
> of
> > > device SMMUs as IOMMUs,
> > > and QEMU should have a more arch-agnostic naming of these system
> > > functions. ]
> >
> > Ok. But to circle back to what originally started this discussion—how
> important
> > is it to rely on the default "bus" in this case? As Markus pointed out,
> SMMUv3
> > is a platform device on the sysbus, so its default bus type can’t point to
> something
> > like PCIe. QEMU doesn’t currently support that.
> >
> > The main motivation for using the default "bus" so far has been to have
> better
> > compatibility with libvirt. Would libvirt be flexible enough if we switched
> to using
> > something like a "primary-bus" property instead?
>
> Sorry if my previous comments misled you, when I previously talked about
> linking via a "bus" property I was not considering the fact that "bus"
> is a special property inside QEMU. From a libvirt POV we don't care what
> the property is call - it was just intended to be a general illustration
> of cross-referencing the iommu with the PCI bus it needed to be associated
> with.
Cool. That makes life easier 😊
Thanks,
Shameer
WARNING: multiple messages have this Message-ID (diff)
From: Shameerali Kolothum Thodi via <qemu-devel@nongnu.org>
To: "Daniel P. Berrangé" <berrange@redhat.com>
Cc: Donald Dutile <ddutile@redhat.com>,
Markus Armbruster <armbru@redhat.com>,
Shameer Kolothum via <qemu-devel@nongnu.org>,
"qemu-arm@nongnu.org" <qemu-arm@nongnu.org>,
"eric.auger@redhat.com" <eric.auger@redhat.com>,
"peter.maydell@linaro.org" <peter.maydell@linaro.org>,
"jgg@nvidia.com" <jgg@nvidia.com>,
"nicolinc@nvidia.com" <nicolinc@nvidia.com>,
"nathanc@nvidia.com" <nathanc@nvidia.com>,
"mochs@nvidia.com" <mochs@nvidia.com>,
"smostafa@google.com" <smostafa@google.com>,
Linuxarm <linuxarm@huawei.com>,
"Wangzhou (B)" <wangzhou1@hisilicon.com>,
jiangkunkun <jiangkunkun@huawei.com>,
Jonathan Cameron <jonathan.cameron@huawei.com>,
"zhangfei.gao@linaro.org" <zhangfei.gao@linaro.org>
Subject: RE: [PATCH v2 1/6] hw/arm/smmuv3: Add support to associate a PCIe RC
Date: Fri, 9 May 2025 08:18:11 +0000 [thread overview]
Message-ID: <5b46c81a412f410494f28a2f9ebb9430@huawei.com> (raw)
In-Reply-To: <aB25ZRu7pCJNpamt@redhat.com>
> -----Original Message-----
> From: Daniel P. Berrangé <berrange@redhat.com>
> Sent: Friday, May 9, 2025 9:14 AM
> To: Shameerali Kolothum Thodi <shameerali.kolothum.thodi@huawei.com>
> Cc: Donald Dutile <ddutile@redhat.com>; Markus Armbruster
> <armbru@redhat.com>; Shameer Kolothum via <qemu-
> devel@nongnu.org>; qemu-arm@nongnu.org; eric.auger@redhat.com;
> peter.maydell@linaro.org; jgg@nvidia.com; nicolinc@nvidia.com;
> nathanc@nvidia.com; mochs@nvidia.com; smostafa@google.com; Linuxarm
> <linuxarm@huawei.com>; Wangzhou (B) <wangzhou1@hisilicon.com>;
> jiangkunkun <jiangkunkun@huawei.com>; Jonathan Cameron
> <jonathan.cameron@huawei.com>; zhangfei.gao@linaro.org
> Subject: Re: [PATCH v2 1/6] hw/arm/smmuv3: Add support to associate a
> PCIe RC
>
[...]
> > > - bus pcie, id=pcie.<num>
> > > - device iommu=[intel_iommu|smmuv3|amd_iommu], bus=[sysbus |
> > > pcie.<num>], id=iommu.<num>
> > > [Yes, I'm sticking with 'iommu' as the generic naming... everyone thinks
> of
> > > device SMMUs as IOMMUs,
> > > and QEMU should have a more arch-agnostic naming of these system
> > > functions. ]
> >
> > Ok. But to circle back to what originally started this discussion—how
> important
> > is it to rely on the default "bus" in this case? As Markus pointed out,
> SMMUv3
> > is a platform device on the sysbus, so its default bus type can’t point to
> something
> > like PCIe. QEMU doesn’t currently support that.
> >
> > The main motivation for using the default "bus" so far has been to have
> better
> > compatibility with libvirt. Would libvirt be flexible enough if we switched
> to using
> > something like a "primary-bus" property instead?
>
> Sorry if my previous comments misled you, when I previously talked about
> linking via a "bus" property I was not considering the fact that "bus"
> is a special property inside QEMU. From a libvirt POV we don't care what
> the property is call - it was just intended to be a general illustration
> of cross-referencing the iommu with the PCI bus it needed to be associated
> with.
Cool. That makes life easier 😊
Thanks,
Shameer
next prev parent reply other threads:[~2025-05-09 8:19 UTC|newest]
Thread overview: 67+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-05-02 10:27 [PATCH v2 0/6] Add support for user creatable SMMUv3 device Shameer Kolothum via
2025-05-02 10:27 ` Shameer Kolothum via
2025-05-02 10:27 ` [PATCH v2 1/6] hw/arm/smmuv3: Add support to associate a PCIe RC Shameer Kolothum via
2025-05-02 10:27 ` Shameer Kolothum via
2025-05-02 17:22 ` Nicolin Chen
2025-05-06 8:14 ` Shameerali Kolothum Thodi via
2025-05-06 8:14 ` Shameerali Kolothum Thodi via
2025-05-02 18:16 ` Donald Dutile
2025-05-05 8:19 ` Eric Auger
2025-05-06 9:07 ` Shameerali Kolothum Thodi
2025-05-06 9:07 ` Shameerali Kolothum Thodi via
2025-05-06 9:35 ` Eric Auger
2025-05-06 8:42 ` Shameerali Kolothum Thodi via
2025-05-06 11:47 ` Markus Armbruster
2025-05-06 12:20 ` Shameerali Kolothum Thodi via
2025-05-06 20:48 ` Donald Dutile
2025-05-07 7:17 ` Markus Armbruster
2025-05-07 8:50 ` Shameerali Kolothum Thodi via
2025-05-07 8:50 ` Shameerali Kolothum Thodi via
2025-05-08 13:45 ` Donald Dutile
2025-05-08 13:57 ` Peter Maydell
2025-05-09 7:57 ` Markus Armbruster
2025-05-09 8:00 ` Shameerali Kolothum Thodi via
2025-05-09 8:00 ` Shameerali Kolothum Thodi via
2025-05-09 10:37 ` Peter Maydell
2025-05-09 10:46 ` Daniel P. Berrangé
2025-05-09 11:43 ` Peter Maydell
2025-05-22 7:39 ` Shameerali Kolothum Thodi via
2025-05-22 7:39 ` Shameerali Kolothum Thodi via
2025-05-16 20:53 ` Donald Dutile
2025-05-09 7:29 ` Shameerali Kolothum Thodi via
2025-05-09 7:29 ` Shameerali Kolothum Thodi via
2025-05-09 8:14 ` Daniel P. Berrangé
2025-05-09 8:18 ` Shameerali Kolothum Thodi via [this message]
2025-05-09 8:18 ` Shameerali Kolothum Thodi via
2025-05-09 8:44 ` Eric Auger
2025-05-02 10:27 ` [PATCH v2 2/6] hw/arm/virt-acpi-build: Update IORT for multiple smmuv3 devices Shameer Kolothum via
2025-05-02 10:27 ` Shameer Kolothum via
2025-05-02 17:13 ` Nicolin Chen
2025-05-02 18:18 ` Donald Dutile
2025-05-06 8:43 ` Shameerali Kolothum Thodi via
2025-05-06 8:00 ` Shameerali Kolothum Thodi via
2025-05-06 8:00 ` Shameerali Kolothum Thodi via
2025-05-05 8:39 ` Eric Auger
2025-05-06 9:12 ` Shameerali Kolothum Thodi via
2025-05-06 9:12 ` Shameerali Kolothum Thodi via
2025-05-02 10:27 ` [PATCH v2 3/6] hw/arm/virt: Factor out common SMMUV3 dt bindings code Shameer Kolothum via
2025-05-02 10:27 ` Shameer Kolothum via
2025-05-02 17:15 ` Nicolin Chen
2025-05-05 9:01 ` Eric Auger
2025-05-06 9:19 ` Shameerali Kolothum Thodi via
2025-05-06 9:19 ` Shameerali Kolothum Thodi via
2025-05-02 10:27 ` [PATCH v2 4/6] hw/arm/virt: Add an SMMU_IO_LEN macro Shameer Kolothum via
2025-05-02 10:27 ` Shameer Kolothum via
2025-05-02 18:20 ` Donald Dutile
2025-05-05 9:03 ` Eric Auger
2025-05-02 10:27 ` [PATCH v2 5/6] hw/arm/virt: Add support for smmuv3 device Shameer Kolothum via
2025-05-02 10:27 ` Shameer Kolothum via
2025-05-02 17:54 ` Nicolin Chen
2025-05-06 8:36 ` Shameerali Kolothum Thodi via
2025-05-05 10:12 ` Eric Auger
2025-05-06 9:29 ` Shameerali Kolothum Thodi via
2025-05-02 10:27 ` [PATCH v2 6/6] hw/arm/smmuv3: Enable smmuv3 device creation Shameer Kolothum via
2025-05-02 10:27 ` Shameer Kolothum via
2025-05-02 18:00 ` Nicolin Chen
2025-05-05 10:13 ` Eric Auger
2025-05-02 18:11 ` [PATCH v2 0/6] Add support for user creatable SMMUv3 device Donald Dutile
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