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From: Miquel Raynal <miquel.raynal@bootlin.com>
To: Tudor Ambarus <tudor.ambarus@linaro.org>
Cc: Richard Weinberger <richard@nod.at>,
	 Vignesh Raghavendra <vigneshr@ti.com>,
	 Pratyush Yadav <pratyush@kernel.org>,
	 Michael Walle <michael@walle.cc>,
	 linux-mtd@lists.infradead.org,  Mark Brown <broonie@kernel.org>,
	 linux-spi@vger.kernel.org,  Steam Lin <stlin2@winbond.com>,
	 Thomas Petazzoni <thomas.petazzoni@bootlin.com>,
	Sanjay R Mehta <sanju.mehta@amd.com>,  Han Xu <han.xu@nxp.com>,
	 Conor Dooley <conor.dooley@microchip.com>,
	 Daire McNamara <daire.mcnamara@microchip.com>,
	 Matthias Brugger <matthias.bgg@gmail.com>,
	 AngeloGioacchino Del Regno
	<angelogioacchino.delregno@collabora.com>,
	 Haibo Chen <haibo.chen@nxp.com>,
	 Yogesh Gaur <yogeshgaur.83@gmail.com>,
	 Heiko Stuebner <heiko@sntech.de>,
	 Michal Simek <michal.simek@amd.com>
Subject: Re: [PATCH 24/24] mtd: spinand: winbond: Add support for DTR operations
Date: Mon, 23 Dec 2024 19:22:12 +0100	[thread overview]
Message-ID: <87o712uunf.fsf@bootlin.com> (raw)
In-Reply-To: <6029a01f-dc4d-4a35-ad21-fd17e3fed9fc@linaro.org> (Tudor Ambarus's message of "Mon, 11 Nov 2024 14:40:59 +0000")

Hello Tudor,

On 11/11/2024 at 14:40:59 GMT, Tudor Ambarus <tudor.ambarus@linaro.org> wrote:

> On 10/25/24 5:15 PM, Miquel Raynal wrote:
>> W25N01JW and W25N02JW support many DTR read modes in single, dual and
>> quad configurations.
>> 
>> DTR modes however cannot be used at 166MHz, as the bus frequency in
>> this case must be lowered to 80MHz.
>
> ha, what's the benefit then? Aren't we better of with non dtr modes
> then? 80 MHz * 2 < 166 MHz?

This is actually a good question, and you are right DDR in this case
does not bring better throughputs, it can even make it a little bit
slower. I think however we should expect some gains at the PCB design
step, which may be way simpler as routing 8 166MHz lines might
apparently be challenging. It is common to have PCB limitations on the
frequency, so enabling DDR can be a great way to keep signal integrity
while definitely improving the performances. However, you're right, I
should probably move these definitions lower in the table to make sure
we run at 166MHz if that's possible.

Thanks,
Miquèl

______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/

WARNING: multiple messages have this Message-ID (diff)
From: Miquel Raynal <miquel.raynal@bootlin.com>
To: Tudor Ambarus <tudor.ambarus@linaro.org>
Cc: Richard Weinberger <richard@nod.at>,
	 Vignesh Raghavendra <vigneshr@ti.com>,
	 Pratyush Yadav <pratyush@kernel.org>,
	 Michael Walle <michael@walle.cc>,
	 linux-mtd@lists.infradead.org,  Mark Brown <broonie@kernel.org>,
	 linux-spi@vger.kernel.org,  Steam Lin <stlin2@winbond.com>,
	 Thomas Petazzoni <thomas.petazzoni@bootlin.com>,
	Sanjay R Mehta <sanju.mehta@amd.com>,  Han Xu <han.xu@nxp.com>,
	 Conor Dooley <conor.dooley@microchip.com>,
	 Daire McNamara <daire.mcnamara@microchip.com>,
	 Matthias Brugger <matthias.bgg@gmail.com>,
	 AngeloGioacchino Del Regno
	<angelogioacchino.delregno@collabora.com>,
	 Haibo Chen <haibo.chen@nxp.com>,
	 Yogesh Gaur <yogeshgaur.83@gmail.com>,
	 Heiko Stuebner <heiko@sntech.de>,
	 Michal Simek <michal.simek@amd.com>
Subject: Re: [PATCH 24/24] mtd: spinand: winbond: Add support for DTR operations
Date: Mon, 23 Dec 2024 19:22:12 +0100	[thread overview]
Message-ID: <87o712uunf.fsf@bootlin.com> (raw)
In-Reply-To: <6029a01f-dc4d-4a35-ad21-fd17e3fed9fc@linaro.org> (Tudor Ambarus's message of "Mon, 11 Nov 2024 14:40:59 +0000")

Hello Tudor,

On 11/11/2024 at 14:40:59 GMT, Tudor Ambarus <tudor.ambarus@linaro.org> wrote:

> On 10/25/24 5:15 PM, Miquel Raynal wrote:
>> W25N01JW and W25N02JW support many DTR read modes in single, dual and
>> quad configurations.
>> 
>> DTR modes however cannot be used at 166MHz, as the bus frequency in
>> this case must be lowered to 80MHz.
>
> ha, what's the benefit then? Aren't we better of with non dtr modes
> then? 80 MHz * 2 < 166 MHz?

This is actually a good question, and you are right DDR in this case
does not bring better throughputs, it can even make it a little bit
slower. I think however we should expect some gains at the PCB design
step, which may be way simpler as routing 8 166MHz lines might
apparently be challenging. It is common to have PCB limitations on the
frequency, so enabling DDR can be a great way to keep signal integrity
while definitely improving the performances. However, you're right, I
should probably move these definitions lower in the table to make sure
we run at 166MHz if that's possible.

Thanks,
Miquèl

  reply	other threads:[~2024-12-23 18:22 UTC|newest]

Thread overview: 142+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-10-25 16:14 [PATCH 00/24] spi-nand/spi-mem DTR support Miquel Raynal
2024-10-25 16:14 ` Miquel Raynal
2024-10-25 16:14 ` [PATCH 01/24] spi: spi-mem: Extend spi-mem operations with a per-operation maximum frequency Miquel Raynal
2024-10-25 16:14   ` Miquel Raynal
2024-10-30 20:52   ` Han Xu
2024-10-30 20:52     ` Han Xu
2024-10-31  6:45     ` Tudor Ambarus
2024-10-31  6:45       ` Tudor Ambarus
2024-11-11 13:07   ` Tudor Ambarus
2024-11-11 13:07     ` Tudor Ambarus
2024-12-13 10:46     ` Miquel Raynal
2024-12-13 10:46       ` Miquel Raynal
2024-12-18  8:07       ` Tudor Ambarus
2024-12-18  8:07         ` Tudor Ambarus
2024-12-18  9:37         ` Miquel Raynal
2024-12-18  9:37           ` Miquel Raynal
2024-12-18 10:03           ` Tudor Ambarus
2024-12-18 10:03             ` Tudor Ambarus
2024-12-18 10:13             ` Tudor Ambarus
2024-12-18 10:13               ` Tudor Ambarus
2024-12-23 19:08               ` Miquel Raynal
2024-12-23 19:08                 ` Miquel Raynal
2024-11-25 16:05   ` Pratyush Yadav
2024-11-25 16:05     ` Pratyush Yadav
2024-10-25 16:14 ` [PATCH 02/24] spi: spi-mem: Add a new controller capability Miquel Raynal
2024-10-25 16:14   ` Miquel Raynal
2024-10-28 21:10   ` Mark Brown
2024-10-28 21:10     ` Mark Brown
2024-11-01 20:17   ` Mark Brown
2024-11-01 20:17     ` Mark Brown
2024-11-07 10:40     ` Miquel Raynal
2024-11-07 10:40       ` Miquel Raynal
2024-11-07 17:15       ` Mark Brown
2024-11-07 17:15         ` Mark Brown
2024-11-08  8:55         ` Miquel Raynal
2024-11-08  8:55           ` Miquel Raynal
2024-11-08 12:59           ` Mark Brown
2024-11-08 12:59             ` Mark Brown
2024-11-11 13:18   ` Tudor Ambarus
2024-11-11 13:18     ` Tudor Ambarus
2024-12-13 11:00     ` Miquel Raynal
2024-12-13 11:00       ` Miquel Raynal
2024-10-25 16:14 ` [PATCH 03/24] spi: amd: Support per spi-mem operation frequency switches Miquel Raynal
2024-10-25 16:14   ` Miquel Raynal
2024-11-11 13:36   ` Tudor Ambarus
2024-11-11 13:36     ` Tudor Ambarus
2024-12-13 11:20     ` Miquel Raynal
2024-12-13 11:20       ` Miquel Raynal
2024-10-25 16:14 ` [PATCH 04/24] spi: amlogic-spifc-a1: " Miquel Raynal
2024-10-25 16:14   ` Miquel Raynal
2024-11-11 13:42   ` Tudor Ambarus
2024-11-11 13:42     ` Tudor Ambarus
2024-12-13 11:44     ` Miquel Raynal
2024-12-13 11:44       ` Miquel Raynal
2024-12-18  8:09       ` Tudor Ambarus
2024-12-18  8:09         ` Tudor Ambarus
2024-10-25 16:14 ` [PATCH 05/24] spi: cadence-qspi: " Miquel Raynal
2024-10-25 16:14   ` Miquel Raynal
2024-11-11 13:50   ` Tudor Ambarus
2024-11-11 13:50     ` Tudor Ambarus
2024-10-25 16:14 ` [PATCH 06/24] spi: dw: " Miquel Raynal
2024-10-25 16:14   ` Miquel Raynal
2024-11-11 14:05   ` Tudor Ambarus
2024-11-11 14:05     ` Tudor Ambarus
2024-10-25 16:14 ` [PATCH 07/24] spi: fsl-qspi: " Miquel Raynal
2024-10-25 16:14   ` Miquel Raynal
2024-10-25 16:14 ` [PATCH 08/24] spi: microchip-core-qspi: " Miquel Raynal
2024-10-25 16:14   ` Miquel Raynal
2024-10-25 16:14 ` [PATCH 09/24] spi: mt65xx: " Miquel Raynal
2024-10-25 16:14   ` Miquel Raynal
2024-10-25 16:14 ` [PATCH 10/24] spi: mxic: " Miquel Raynal
2024-10-25 16:14   ` Miquel Raynal
2024-10-25 16:14 ` [PATCH 11/24] spi: nxp-fspi: " Miquel Raynal
2024-10-25 16:14   ` Miquel Raynal
2024-10-25 16:14 ` [PATCH 12/24] spi: rockchip-sfc: " Miquel Raynal
2024-10-25 16:14   ` Miquel Raynal
2024-10-25 16:14 ` [PATCH 13/24] spi: spi-sn-f-ospi: " Miquel Raynal
2024-10-25 16:14   ` Miquel Raynal
2024-10-25 16:14 ` [PATCH 14/24] spi: spi-ti-qspi: " Miquel Raynal
2024-10-25 16:14   ` Miquel Raynal
2024-10-25 16:14 ` [PATCH 15/24] spi: zynq-qspi: " Miquel Raynal
2024-10-25 16:14   ` Miquel Raynal
2024-10-25 16:14 ` [PATCH 16/24] spi: zynqmp-gqspi: " Miquel Raynal
2024-10-25 16:14   ` Miquel Raynal
2024-10-25 16:14 ` [PATCH 17/24] mtd: spinand: Create distinct fast and slow read from cache variants Miquel Raynal
2024-10-25 16:14   ` Miquel Raynal
2024-11-11 14:14   ` Tudor Ambarus
2024-11-11 14:14     ` Tudor Ambarus
2024-10-25 16:14 ` [PATCH 18/24] mtd: spinand: Add an optional frequency to read from cache macros Miquel Raynal
2024-10-25 16:14   ` Miquel Raynal
2024-11-11 14:17   ` Tudor Ambarus
2024-11-11 14:17     ` Tudor Ambarus
2024-12-13 11:56     ` Miquel Raynal
2024-12-13 11:56       ` Miquel Raynal
2024-10-25 16:14 ` [PATCH 19/24] mtd: spinand: winbond: Fix the *JW chip definitions Miquel Raynal
2024-10-25 16:14   ` Miquel Raynal
2024-11-11 14:27   ` Tudor Ambarus
2024-11-11 14:27     ` Tudor Ambarus
2024-12-18  8:16     ` Tudor Ambarus
2024-12-18  8:16       ` Tudor Ambarus
2024-12-18  9:34       ` Miquel Raynal
2024-12-18  9:34         ` Miquel Raynal
2024-10-25 16:14 ` [PATCH 20/24] spi: spi-mem: Reorder SPI_MEM_OP_CMD internals Miquel Raynal
2024-10-25 16:14   ` Miquel Raynal
2024-11-11 14:32   ` Tudor Ambarus
2024-11-11 14:32     ` Tudor Ambarus
2024-12-13 12:05     ` Miquel Raynal
2024-12-13 12:05       ` Miquel Raynal
2024-10-25 16:14 ` [PATCH 21/24] spi: spi-mem: Create macros for DTR operation Miquel Raynal
2024-10-25 16:14   ` Miquel Raynal
2024-10-25 16:14 ` [PATCH 22/24] mtd: spinand: Add support for read DTR operations Miquel Raynal
2024-10-25 16:14   ` Miquel Raynal
2024-11-11 14:35   ` Tudor Ambarus
2024-11-11 14:35     ` Tudor Ambarus
2024-12-13 12:08     ` Miquel Raynal
2024-12-13 12:08       ` Miquel Raynal
2024-12-18  8:10       ` Tudor Ambarus
2024-12-18  8:10         ` Tudor Ambarus
2024-10-25 16:15 ` [PATCH 23/24] mtd: spinand: winbond: Add comment about naming Miquel Raynal
2024-10-25 16:15   ` Miquel Raynal
2024-11-11 14:38   ` Tudor Ambarus
2024-11-11 14:38     ` Tudor Ambarus
2024-11-13  9:46     ` Tudor Ambarus
2024-11-13  9:46       ` Tudor Ambarus
2024-12-13 12:25     ` Miquel Raynal
2024-12-13 12:25       ` Miquel Raynal
2024-12-18  8:14       ` Tudor Ambarus
2024-12-18  8:14         ` Tudor Ambarus
2024-12-18  9:33         ` Miquel Raynal
2024-12-18  9:33           ` Miquel Raynal
2024-12-18 10:21           ` Tudor Ambarus
2024-12-18 10:21             ` Tudor Ambarus
2024-10-25 16:15 ` [PATCH 24/24] mtd: spinand: winbond: Add support for DTR operations Miquel Raynal
2024-10-25 16:15   ` Miquel Raynal
2024-11-11 14:40   ` Tudor Ambarus
2024-11-11 14:40     ` Tudor Ambarus
2024-12-23 18:22     ` Miquel Raynal [this message]
2024-12-23 18:22       ` Miquel Raynal
2024-12-24  9:38       ` Miquel Raynal
2024-12-24  9:38         ` Miquel Raynal
2025-01-10 15:47 ` (subset) [PATCH 00/24] spi-nand/spi-mem DTR support Mark Brown
2025-01-10 15:47   ` Mark Brown

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