From: Miquel Raynal <miquel.raynal@bootlin.com>
To: Tudor Ambarus <tudor.ambarus@linaro.org>
Cc: Richard Weinberger <richard@nod.at>,
Vignesh Raghavendra <vigneshr@ti.com>,
Pratyush Yadav <pratyush@kernel.org>,
Michael Walle <michael@walle.cc>,
linux-mtd@lists.infradead.org, Mark Brown <broonie@kernel.org>,
linux-spi@vger.kernel.org, Steam Lin <stlin2@winbond.com>,
Thomas Petazzoni <thomas.petazzoni@bootlin.com>,
Sanjay R Mehta <sanju.mehta@amd.com>, Han Xu <han.xu@nxp.com>,
Conor Dooley <conor.dooley@microchip.com>,
Daire McNamara <daire.mcnamara@microchip.com>,
Matthias Brugger <matthias.bgg@gmail.com>,
AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com>,
Haibo Chen <haibo.chen@nxp.com>,
Yogesh Gaur <yogeshgaur.83@gmail.com>,
Heiko Stuebner <heiko@sntech.de>,
Michal Simek <michal.simek@amd.com>
Subject: Re: [PATCH 03/24] spi: amd: Support per spi-mem operation frequency switches
Date: Fri, 13 Dec 2024 12:20:25 +0100 [thread overview]
Message-ID: <87zfkzn81y.fsf@bootlin.com> (raw)
In-Reply-To: <64ade17d-3800-4afc-847c-b8e5fc5d7360@linaro.org> (Tudor Ambarus's message of "Mon, 11 Nov 2024 13:36:15 +0000")
Hi Tudor,
On 11/11/2024 at 13:36:15 GMT, Tudor Ambarus <tudor.ambarus@linaro.org> wrote:
> On 10/25/24 5:14 PM, Miquel Raynal wrote:
>> Every ->exec_op() call correctly configures the spi bus speed to the
>> maximum allowed frequency for the memory using the constant spi default
>> parameter. Since we can now have per-operation constraints, let's use
>> the value that comes from the spi-mem operation structure instead. In
>> case there is no specific limitation for this operation, the default spi
>> device value will be given anyway.
>>
>> This controller however performed a frequency check, which is also
>> observed during the ->check_op() phase.
>>
>> The per-operation frequency capability is thus advertised to the spi-mem
>> core.
>>
>> Cc: Sanjay R Mehta <sanju.mehta@amd.com>
>> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
>> ---
>> drivers/spi/spi-amd.c | 10 +++++++++-
>> 1 file changed, 9 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/spi/spi-amd.c b/drivers/spi/spi-amd.c
>> index 2245ad54b03a..f58dc6375582 100644
>> --- a/drivers/spi/spi-amd.c
>> +++ b/drivers/spi/spi-amd.c
>> @@ -368,6 +368,9 @@ static bool amd_spi_supports_op(struct spi_mem *mem,
>> op->data.buswidth > 1 || op->data.nbytes > AMD_SPI_MAX_DATA)
>> return false;
>>
>> + if (op->max_freq < AMD_SPI_MIN_HZ)
>
> How about using mem->spi->controller->min_speed_hz intead?
Good idea. I think I used AMD_SPI_MIN_HZ to follow what was done
somewhere else, but that's fine.
>
>> + return false;
>
> I find the check fine here, but I see however that amd_set_spi_freq()
> duplicates the same, returning -EINVAL when speed_hz < AMD_SPI_MIN_HZ
This one is useless, the spi core already takes care of this check, I'll
drop it in a separate patch.
>> +
>> return spi_mem_default_supports_op(mem, op);
>> }
>>
>> @@ -443,7 +446,7 @@ static int amd_spi_exec_mem_op(struct spi_mem *mem,
>>
>> amd_spi = spi_controller_get_devdata(mem->spi->controller);
>>
>> - ret = amd_set_spi_freq(amd_spi, mem->spi->max_speed_hz);
>> + ret = amd_set_spi_freq(amd_spi, op->max_freq);
>> if (ret)
>> return ret;
>
> however the return code is checked just on this call, and completely
> ignored in the 2 other calls. I find the code a bit ugly for the non
> SPIMEM case, but maybe something for the amd owner to address.
Once the above check removed (it does not make much sense there), the
function can return void.
Cheers,
Miquèl
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
WARNING: multiple messages have this Message-ID (diff)
From: Miquel Raynal <miquel.raynal@bootlin.com>
To: Tudor Ambarus <tudor.ambarus@linaro.org>
Cc: Richard Weinberger <richard@nod.at>,
Vignesh Raghavendra <vigneshr@ti.com>,
Pratyush Yadav <pratyush@kernel.org>,
Michael Walle <michael@walle.cc>,
linux-mtd@lists.infradead.org, Mark Brown <broonie@kernel.org>,
linux-spi@vger.kernel.org, Steam Lin <stlin2@winbond.com>,
Thomas Petazzoni <thomas.petazzoni@bootlin.com>,
Sanjay R Mehta <sanju.mehta@amd.com>, Han Xu <han.xu@nxp.com>,
Conor Dooley <conor.dooley@microchip.com>,
Daire McNamara <daire.mcnamara@microchip.com>,
Matthias Brugger <matthias.bgg@gmail.com>,
AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com>,
Haibo Chen <haibo.chen@nxp.com>,
Yogesh Gaur <yogeshgaur.83@gmail.com>,
Heiko Stuebner <heiko@sntech.de>,
Michal Simek <michal.simek@amd.com>
Subject: Re: [PATCH 03/24] spi: amd: Support per spi-mem operation frequency switches
Date: Fri, 13 Dec 2024 12:20:25 +0100 [thread overview]
Message-ID: <87zfkzn81y.fsf@bootlin.com> (raw)
In-Reply-To: <64ade17d-3800-4afc-847c-b8e5fc5d7360@linaro.org> (Tudor Ambarus's message of "Mon, 11 Nov 2024 13:36:15 +0000")
Hi Tudor,
On 11/11/2024 at 13:36:15 GMT, Tudor Ambarus <tudor.ambarus@linaro.org> wrote:
> On 10/25/24 5:14 PM, Miquel Raynal wrote:
>> Every ->exec_op() call correctly configures the spi bus speed to the
>> maximum allowed frequency for the memory using the constant spi default
>> parameter. Since we can now have per-operation constraints, let's use
>> the value that comes from the spi-mem operation structure instead. In
>> case there is no specific limitation for this operation, the default spi
>> device value will be given anyway.
>>
>> This controller however performed a frequency check, which is also
>> observed during the ->check_op() phase.
>>
>> The per-operation frequency capability is thus advertised to the spi-mem
>> core.
>>
>> Cc: Sanjay R Mehta <sanju.mehta@amd.com>
>> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
>> ---
>> drivers/spi/spi-amd.c | 10 +++++++++-
>> 1 file changed, 9 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/spi/spi-amd.c b/drivers/spi/spi-amd.c
>> index 2245ad54b03a..f58dc6375582 100644
>> --- a/drivers/spi/spi-amd.c
>> +++ b/drivers/spi/spi-amd.c
>> @@ -368,6 +368,9 @@ static bool amd_spi_supports_op(struct spi_mem *mem,
>> op->data.buswidth > 1 || op->data.nbytes > AMD_SPI_MAX_DATA)
>> return false;
>>
>> + if (op->max_freq < AMD_SPI_MIN_HZ)
>
> How about using mem->spi->controller->min_speed_hz intead?
Good idea. I think I used AMD_SPI_MIN_HZ to follow what was done
somewhere else, but that's fine.
>
>> + return false;
>
> I find the check fine here, but I see however that amd_set_spi_freq()
> duplicates the same, returning -EINVAL when speed_hz < AMD_SPI_MIN_HZ
This one is useless, the spi core already takes care of this check, I'll
drop it in a separate patch.
>> +
>> return spi_mem_default_supports_op(mem, op);
>> }
>>
>> @@ -443,7 +446,7 @@ static int amd_spi_exec_mem_op(struct spi_mem *mem,
>>
>> amd_spi = spi_controller_get_devdata(mem->spi->controller);
>>
>> - ret = amd_set_spi_freq(amd_spi, mem->spi->max_speed_hz);
>> + ret = amd_set_spi_freq(amd_spi, op->max_freq);
>> if (ret)
>> return ret;
>
> however the return code is checked just on this call, and completely
> ignored in the 2 other calls. I find the code a bit ugly for the non
> SPIMEM case, but maybe something for the amd owner to address.
Once the above check removed (it does not make much sense there), the
function can return void.
Cheers,
Miquèl
next prev parent reply other threads:[~2024-12-13 11:21 UTC|newest]
Thread overview: 142+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-10-25 16:14 [PATCH 00/24] spi-nand/spi-mem DTR support Miquel Raynal
2024-10-25 16:14 ` Miquel Raynal
2024-10-25 16:14 ` [PATCH 01/24] spi: spi-mem: Extend spi-mem operations with a per-operation maximum frequency Miquel Raynal
2024-10-25 16:14 ` Miquel Raynal
2024-10-30 20:52 ` Han Xu
2024-10-30 20:52 ` Han Xu
2024-10-31 6:45 ` Tudor Ambarus
2024-10-31 6:45 ` Tudor Ambarus
2024-11-11 13:07 ` Tudor Ambarus
2024-11-11 13:07 ` Tudor Ambarus
2024-12-13 10:46 ` Miquel Raynal
2024-12-13 10:46 ` Miquel Raynal
2024-12-18 8:07 ` Tudor Ambarus
2024-12-18 8:07 ` Tudor Ambarus
2024-12-18 9:37 ` Miquel Raynal
2024-12-18 9:37 ` Miquel Raynal
2024-12-18 10:03 ` Tudor Ambarus
2024-12-18 10:03 ` Tudor Ambarus
2024-12-18 10:13 ` Tudor Ambarus
2024-12-18 10:13 ` Tudor Ambarus
2024-12-23 19:08 ` Miquel Raynal
2024-12-23 19:08 ` Miquel Raynal
2024-11-25 16:05 ` Pratyush Yadav
2024-11-25 16:05 ` Pratyush Yadav
2024-10-25 16:14 ` [PATCH 02/24] spi: spi-mem: Add a new controller capability Miquel Raynal
2024-10-25 16:14 ` Miquel Raynal
2024-10-28 21:10 ` Mark Brown
2024-10-28 21:10 ` Mark Brown
2024-11-01 20:17 ` Mark Brown
2024-11-01 20:17 ` Mark Brown
2024-11-07 10:40 ` Miquel Raynal
2024-11-07 10:40 ` Miquel Raynal
2024-11-07 17:15 ` Mark Brown
2024-11-07 17:15 ` Mark Brown
2024-11-08 8:55 ` Miquel Raynal
2024-11-08 8:55 ` Miquel Raynal
2024-11-08 12:59 ` Mark Brown
2024-11-08 12:59 ` Mark Brown
2024-11-11 13:18 ` Tudor Ambarus
2024-11-11 13:18 ` Tudor Ambarus
2024-12-13 11:00 ` Miquel Raynal
2024-12-13 11:00 ` Miquel Raynal
2024-10-25 16:14 ` [PATCH 03/24] spi: amd: Support per spi-mem operation frequency switches Miquel Raynal
2024-10-25 16:14 ` Miquel Raynal
2024-11-11 13:36 ` Tudor Ambarus
2024-11-11 13:36 ` Tudor Ambarus
2024-12-13 11:20 ` Miquel Raynal [this message]
2024-12-13 11:20 ` Miquel Raynal
2024-10-25 16:14 ` [PATCH 04/24] spi: amlogic-spifc-a1: " Miquel Raynal
2024-10-25 16:14 ` Miquel Raynal
2024-11-11 13:42 ` Tudor Ambarus
2024-11-11 13:42 ` Tudor Ambarus
2024-12-13 11:44 ` Miquel Raynal
2024-12-13 11:44 ` Miquel Raynal
2024-12-18 8:09 ` Tudor Ambarus
2024-12-18 8:09 ` Tudor Ambarus
2024-10-25 16:14 ` [PATCH 05/24] spi: cadence-qspi: " Miquel Raynal
2024-10-25 16:14 ` Miquel Raynal
2024-11-11 13:50 ` Tudor Ambarus
2024-11-11 13:50 ` Tudor Ambarus
2024-10-25 16:14 ` [PATCH 06/24] spi: dw: " Miquel Raynal
2024-10-25 16:14 ` Miquel Raynal
2024-11-11 14:05 ` Tudor Ambarus
2024-11-11 14:05 ` Tudor Ambarus
2024-10-25 16:14 ` [PATCH 07/24] spi: fsl-qspi: " Miquel Raynal
2024-10-25 16:14 ` Miquel Raynal
2024-10-25 16:14 ` [PATCH 08/24] spi: microchip-core-qspi: " Miquel Raynal
2024-10-25 16:14 ` Miquel Raynal
2024-10-25 16:14 ` [PATCH 09/24] spi: mt65xx: " Miquel Raynal
2024-10-25 16:14 ` Miquel Raynal
2024-10-25 16:14 ` [PATCH 10/24] spi: mxic: " Miquel Raynal
2024-10-25 16:14 ` Miquel Raynal
2024-10-25 16:14 ` [PATCH 11/24] spi: nxp-fspi: " Miquel Raynal
2024-10-25 16:14 ` Miquel Raynal
2024-10-25 16:14 ` [PATCH 12/24] spi: rockchip-sfc: " Miquel Raynal
2024-10-25 16:14 ` Miquel Raynal
2024-10-25 16:14 ` [PATCH 13/24] spi: spi-sn-f-ospi: " Miquel Raynal
2024-10-25 16:14 ` Miquel Raynal
2024-10-25 16:14 ` [PATCH 14/24] spi: spi-ti-qspi: " Miquel Raynal
2024-10-25 16:14 ` Miquel Raynal
2024-10-25 16:14 ` [PATCH 15/24] spi: zynq-qspi: " Miquel Raynal
2024-10-25 16:14 ` Miquel Raynal
2024-10-25 16:14 ` [PATCH 16/24] spi: zynqmp-gqspi: " Miquel Raynal
2024-10-25 16:14 ` Miquel Raynal
2024-10-25 16:14 ` [PATCH 17/24] mtd: spinand: Create distinct fast and slow read from cache variants Miquel Raynal
2024-10-25 16:14 ` Miquel Raynal
2024-11-11 14:14 ` Tudor Ambarus
2024-11-11 14:14 ` Tudor Ambarus
2024-10-25 16:14 ` [PATCH 18/24] mtd: spinand: Add an optional frequency to read from cache macros Miquel Raynal
2024-10-25 16:14 ` Miquel Raynal
2024-11-11 14:17 ` Tudor Ambarus
2024-11-11 14:17 ` Tudor Ambarus
2024-12-13 11:56 ` Miquel Raynal
2024-12-13 11:56 ` Miquel Raynal
2024-10-25 16:14 ` [PATCH 19/24] mtd: spinand: winbond: Fix the *JW chip definitions Miquel Raynal
2024-10-25 16:14 ` Miquel Raynal
2024-11-11 14:27 ` Tudor Ambarus
2024-11-11 14:27 ` Tudor Ambarus
2024-12-18 8:16 ` Tudor Ambarus
2024-12-18 8:16 ` Tudor Ambarus
2024-12-18 9:34 ` Miquel Raynal
2024-12-18 9:34 ` Miquel Raynal
2024-10-25 16:14 ` [PATCH 20/24] spi: spi-mem: Reorder SPI_MEM_OP_CMD internals Miquel Raynal
2024-10-25 16:14 ` Miquel Raynal
2024-11-11 14:32 ` Tudor Ambarus
2024-11-11 14:32 ` Tudor Ambarus
2024-12-13 12:05 ` Miquel Raynal
2024-12-13 12:05 ` Miquel Raynal
2024-10-25 16:14 ` [PATCH 21/24] spi: spi-mem: Create macros for DTR operation Miquel Raynal
2024-10-25 16:14 ` Miquel Raynal
2024-10-25 16:14 ` [PATCH 22/24] mtd: spinand: Add support for read DTR operations Miquel Raynal
2024-10-25 16:14 ` Miquel Raynal
2024-11-11 14:35 ` Tudor Ambarus
2024-11-11 14:35 ` Tudor Ambarus
2024-12-13 12:08 ` Miquel Raynal
2024-12-13 12:08 ` Miquel Raynal
2024-12-18 8:10 ` Tudor Ambarus
2024-12-18 8:10 ` Tudor Ambarus
2024-10-25 16:15 ` [PATCH 23/24] mtd: spinand: winbond: Add comment about naming Miquel Raynal
2024-10-25 16:15 ` Miquel Raynal
2024-11-11 14:38 ` Tudor Ambarus
2024-11-11 14:38 ` Tudor Ambarus
2024-11-13 9:46 ` Tudor Ambarus
2024-11-13 9:46 ` Tudor Ambarus
2024-12-13 12:25 ` Miquel Raynal
2024-12-13 12:25 ` Miquel Raynal
2024-12-18 8:14 ` Tudor Ambarus
2024-12-18 8:14 ` Tudor Ambarus
2024-12-18 9:33 ` Miquel Raynal
2024-12-18 9:33 ` Miquel Raynal
2024-12-18 10:21 ` Tudor Ambarus
2024-12-18 10:21 ` Tudor Ambarus
2024-10-25 16:15 ` [PATCH 24/24] mtd: spinand: winbond: Add support for DTR operations Miquel Raynal
2024-10-25 16:15 ` Miquel Raynal
2024-11-11 14:40 ` Tudor Ambarus
2024-11-11 14:40 ` Tudor Ambarus
2024-12-23 18:22 ` Miquel Raynal
2024-12-23 18:22 ` Miquel Raynal
2024-12-24 9:38 ` Miquel Raynal
2024-12-24 9:38 ` Miquel Raynal
2025-01-10 15:47 ` (subset) [PATCH 00/24] spi-nand/spi-mem DTR support Mark Brown
2025-01-10 15:47 ` Mark Brown
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