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From: Miquel Raynal <miquel.raynal@bootlin.com>
To: Tudor Ambarus <tudor.ambarus@linaro.org>
Cc: Richard Weinberger <richard@nod.at>,
	 Vignesh Raghavendra <vigneshr@ti.com>,
	 Pratyush Yadav <pratyush@kernel.org>,
	 Michael Walle <michael@walle.cc>,
	 linux-mtd@lists.infradead.org,  Mark Brown <broonie@kernel.org>,
	 linux-spi@vger.kernel.org,  Steam Lin <stlin2@winbond.com>,
	 Thomas Petazzoni <thomas.petazzoni@bootlin.com>,
	Sanjay R Mehta <sanju.mehta@amd.com>,  Han Xu <han.xu@nxp.com>,
	 Conor Dooley <conor.dooley@microchip.com>,
	 Daire McNamara <daire.mcnamara@microchip.com>,
	 Matthias Brugger <matthias.bgg@gmail.com>,
	 AngeloGioacchino Del Regno
	<angelogioacchino.delregno@collabora.com>,
	 Haibo Chen <haibo.chen@nxp.com>,
	 Yogesh Gaur <yogeshgaur.83@gmail.com>,
	 Heiko Stuebner <heiko@sntech.de>,
	 Michal Simek <michal.simek@amd.com>
Subject: Re: [PATCH 23/24] mtd: spinand: winbond: Add comment about naming
Date: Fri, 13 Dec 2024 13:25:05 +0100	[thread overview]
Message-ID: <87wmg3kbxa.fsf@bootlin.com> (raw)
In-Reply-To: <71d0cf83-6866-46be-b76f-291a8a6a1346@linaro.org> (Tudor Ambarus's message of "Mon, 11 Nov 2024 14:38:53 +0000")

On 11/11/2024 at 14:38:53 GMT, Tudor Ambarus <tudor.ambarus@linaro.org> wrote:

> On 10/25/24 5:15 PM, Miquel Raynal wrote:
>> Make the link between the core macros and the datasheet.
>> 
>> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
>> ---
>>  drivers/mtd/nand/spi/winbond.c | 5 +++++
>>  1 file changed, 5 insertions(+)
>> 
>> diff --git a/drivers/mtd/nand/spi/winbond.c b/drivers/mtd/nand/spi/winbond.c
>> index 686e872fe0ff..9e2562805d23 100644
>> --- a/drivers/mtd/nand/spi/winbond.c
>> +++ b/drivers/mtd/nand/spi/winbond.c
>> @@ -18,6 +18,11 @@
>>  
>>  #define W25N04KV_STATUS_ECC_5_8_BITFLIPS	(3 << 4)
>>  
>> +/*
>> + * "X2" in the core is equivalent to "dual output" in the datasheets,
>> + * "X4" in the core is equivalent to "quad output" in the datasheets.
>> + */
>
> doesn't help great for an outsider like me. Is quad referring to cmd,
> addr or data? Or maybe of all? I need to read the code anyway.

I also don't like these terms. IIRC "output" is referring to the data cycles,
otherwise it means address (dummy) and data cycles.

In single, dual or quad mode the naming is unclear but "okay". But octal
DDR modes can require the opcode to be sent in octal mode as well, which
is new. If we support that, I'll take care of using a more
understandable naming for all macros like Xy-Xy-Xy, X being the
buswidth, y being S (sdr) or D (ddr) and the three members being
Command-Address-Data. I might even be tempted to include dummy cycles as
well, because it is important to be clear if eg. in octal mode "1" means
"1 cycle" or "8 cycles".

>> +
>>  static SPINAND_OP_VARIANTS(read_cache_dtr_variants,
>>  		SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0),
>>  		SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),

Thanks,
Miquèl

______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/

WARNING: multiple messages have this Message-ID (diff)
From: Miquel Raynal <miquel.raynal@bootlin.com>
To: Tudor Ambarus <tudor.ambarus@linaro.org>
Cc: Richard Weinberger <richard@nod.at>,
	 Vignesh Raghavendra <vigneshr@ti.com>,
	 Pratyush Yadav <pratyush@kernel.org>,
	 Michael Walle <michael@walle.cc>,
	 linux-mtd@lists.infradead.org,  Mark Brown <broonie@kernel.org>,
	 linux-spi@vger.kernel.org,  Steam Lin <stlin2@winbond.com>,
	 Thomas Petazzoni <thomas.petazzoni@bootlin.com>,
	Sanjay R Mehta <sanju.mehta@amd.com>,  Han Xu <han.xu@nxp.com>,
	 Conor Dooley <conor.dooley@microchip.com>,
	 Daire McNamara <daire.mcnamara@microchip.com>,
	 Matthias Brugger <matthias.bgg@gmail.com>,
	 AngeloGioacchino Del Regno
	<angelogioacchino.delregno@collabora.com>,
	 Haibo Chen <haibo.chen@nxp.com>,
	 Yogesh Gaur <yogeshgaur.83@gmail.com>,
	 Heiko Stuebner <heiko@sntech.de>,
	 Michal Simek <michal.simek@amd.com>
Subject: Re: [PATCH 23/24] mtd: spinand: winbond: Add comment about naming
Date: Fri, 13 Dec 2024 13:25:05 +0100	[thread overview]
Message-ID: <87wmg3kbxa.fsf@bootlin.com> (raw)
In-Reply-To: <71d0cf83-6866-46be-b76f-291a8a6a1346@linaro.org> (Tudor Ambarus's message of "Mon, 11 Nov 2024 14:38:53 +0000")

On 11/11/2024 at 14:38:53 GMT, Tudor Ambarus <tudor.ambarus@linaro.org> wrote:

> On 10/25/24 5:15 PM, Miquel Raynal wrote:
>> Make the link between the core macros and the datasheet.
>> 
>> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
>> ---
>>  drivers/mtd/nand/spi/winbond.c | 5 +++++
>>  1 file changed, 5 insertions(+)
>> 
>> diff --git a/drivers/mtd/nand/spi/winbond.c b/drivers/mtd/nand/spi/winbond.c
>> index 686e872fe0ff..9e2562805d23 100644
>> --- a/drivers/mtd/nand/spi/winbond.c
>> +++ b/drivers/mtd/nand/spi/winbond.c
>> @@ -18,6 +18,11 @@
>>  
>>  #define W25N04KV_STATUS_ECC_5_8_BITFLIPS	(3 << 4)
>>  
>> +/*
>> + * "X2" in the core is equivalent to "dual output" in the datasheets,
>> + * "X4" in the core is equivalent to "quad output" in the datasheets.
>> + */
>
> doesn't help great for an outsider like me. Is quad referring to cmd,
> addr or data? Or maybe of all? I need to read the code anyway.

I also don't like these terms. IIRC "output" is referring to the data cycles,
otherwise it means address (dummy) and data cycles.

In single, dual or quad mode the naming is unclear but "okay". But octal
DDR modes can require the opcode to be sent in octal mode as well, which
is new. If we support that, I'll take care of using a more
understandable naming for all macros like Xy-Xy-Xy, X being the
buswidth, y being S (sdr) or D (ddr) and the three members being
Command-Address-Data. I might even be tempted to include dummy cycles as
well, because it is important to be clear if eg. in octal mode "1" means
"1 cycle" or "8 cycles".

>> +
>>  static SPINAND_OP_VARIANTS(read_cache_dtr_variants,
>>  		SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0),
>>  		SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),

Thanks,
Miquèl

  parent reply	other threads:[~2024-12-13 12:25 UTC|newest]

Thread overview: 142+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-10-25 16:14 [PATCH 00/24] spi-nand/spi-mem DTR support Miquel Raynal
2024-10-25 16:14 ` Miquel Raynal
2024-10-25 16:14 ` [PATCH 01/24] spi: spi-mem: Extend spi-mem operations with a per-operation maximum frequency Miquel Raynal
2024-10-25 16:14   ` Miquel Raynal
2024-10-30 20:52   ` Han Xu
2024-10-30 20:52     ` Han Xu
2024-10-31  6:45     ` Tudor Ambarus
2024-10-31  6:45       ` Tudor Ambarus
2024-11-11 13:07   ` Tudor Ambarus
2024-11-11 13:07     ` Tudor Ambarus
2024-12-13 10:46     ` Miquel Raynal
2024-12-13 10:46       ` Miquel Raynal
2024-12-18  8:07       ` Tudor Ambarus
2024-12-18  8:07         ` Tudor Ambarus
2024-12-18  9:37         ` Miquel Raynal
2024-12-18  9:37           ` Miquel Raynal
2024-12-18 10:03           ` Tudor Ambarus
2024-12-18 10:03             ` Tudor Ambarus
2024-12-18 10:13             ` Tudor Ambarus
2024-12-18 10:13               ` Tudor Ambarus
2024-12-23 19:08               ` Miquel Raynal
2024-12-23 19:08                 ` Miquel Raynal
2024-11-25 16:05   ` Pratyush Yadav
2024-11-25 16:05     ` Pratyush Yadav
2024-10-25 16:14 ` [PATCH 02/24] spi: spi-mem: Add a new controller capability Miquel Raynal
2024-10-25 16:14   ` Miquel Raynal
2024-10-28 21:10   ` Mark Brown
2024-10-28 21:10     ` Mark Brown
2024-11-01 20:17   ` Mark Brown
2024-11-01 20:17     ` Mark Brown
2024-11-07 10:40     ` Miquel Raynal
2024-11-07 10:40       ` Miquel Raynal
2024-11-07 17:15       ` Mark Brown
2024-11-07 17:15         ` Mark Brown
2024-11-08  8:55         ` Miquel Raynal
2024-11-08  8:55           ` Miquel Raynal
2024-11-08 12:59           ` Mark Brown
2024-11-08 12:59             ` Mark Brown
2024-11-11 13:18   ` Tudor Ambarus
2024-11-11 13:18     ` Tudor Ambarus
2024-12-13 11:00     ` Miquel Raynal
2024-12-13 11:00       ` Miquel Raynal
2024-10-25 16:14 ` [PATCH 03/24] spi: amd: Support per spi-mem operation frequency switches Miquel Raynal
2024-10-25 16:14   ` Miquel Raynal
2024-11-11 13:36   ` Tudor Ambarus
2024-11-11 13:36     ` Tudor Ambarus
2024-12-13 11:20     ` Miquel Raynal
2024-12-13 11:20       ` Miquel Raynal
2024-10-25 16:14 ` [PATCH 04/24] spi: amlogic-spifc-a1: " Miquel Raynal
2024-10-25 16:14   ` Miquel Raynal
2024-11-11 13:42   ` Tudor Ambarus
2024-11-11 13:42     ` Tudor Ambarus
2024-12-13 11:44     ` Miquel Raynal
2024-12-13 11:44       ` Miquel Raynal
2024-12-18  8:09       ` Tudor Ambarus
2024-12-18  8:09         ` Tudor Ambarus
2024-10-25 16:14 ` [PATCH 05/24] spi: cadence-qspi: " Miquel Raynal
2024-10-25 16:14   ` Miquel Raynal
2024-11-11 13:50   ` Tudor Ambarus
2024-11-11 13:50     ` Tudor Ambarus
2024-10-25 16:14 ` [PATCH 06/24] spi: dw: " Miquel Raynal
2024-10-25 16:14   ` Miquel Raynal
2024-11-11 14:05   ` Tudor Ambarus
2024-11-11 14:05     ` Tudor Ambarus
2024-10-25 16:14 ` [PATCH 07/24] spi: fsl-qspi: " Miquel Raynal
2024-10-25 16:14   ` Miquel Raynal
2024-10-25 16:14 ` [PATCH 08/24] spi: microchip-core-qspi: " Miquel Raynal
2024-10-25 16:14   ` Miquel Raynal
2024-10-25 16:14 ` [PATCH 09/24] spi: mt65xx: " Miquel Raynal
2024-10-25 16:14   ` Miquel Raynal
2024-10-25 16:14 ` [PATCH 10/24] spi: mxic: " Miquel Raynal
2024-10-25 16:14   ` Miquel Raynal
2024-10-25 16:14 ` [PATCH 11/24] spi: nxp-fspi: " Miquel Raynal
2024-10-25 16:14   ` Miquel Raynal
2024-10-25 16:14 ` [PATCH 12/24] spi: rockchip-sfc: " Miquel Raynal
2024-10-25 16:14   ` Miquel Raynal
2024-10-25 16:14 ` [PATCH 13/24] spi: spi-sn-f-ospi: " Miquel Raynal
2024-10-25 16:14   ` Miquel Raynal
2024-10-25 16:14 ` [PATCH 14/24] spi: spi-ti-qspi: " Miquel Raynal
2024-10-25 16:14   ` Miquel Raynal
2024-10-25 16:14 ` [PATCH 15/24] spi: zynq-qspi: " Miquel Raynal
2024-10-25 16:14   ` Miquel Raynal
2024-10-25 16:14 ` [PATCH 16/24] spi: zynqmp-gqspi: " Miquel Raynal
2024-10-25 16:14   ` Miquel Raynal
2024-10-25 16:14 ` [PATCH 17/24] mtd: spinand: Create distinct fast and slow read from cache variants Miquel Raynal
2024-10-25 16:14   ` Miquel Raynal
2024-11-11 14:14   ` Tudor Ambarus
2024-11-11 14:14     ` Tudor Ambarus
2024-10-25 16:14 ` [PATCH 18/24] mtd: spinand: Add an optional frequency to read from cache macros Miquel Raynal
2024-10-25 16:14   ` Miquel Raynal
2024-11-11 14:17   ` Tudor Ambarus
2024-11-11 14:17     ` Tudor Ambarus
2024-12-13 11:56     ` Miquel Raynal
2024-12-13 11:56       ` Miquel Raynal
2024-10-25 16:14 ` [PATCH 19/24] mtd: spinand: winbond: Fix the *JW chip definitions Miquel Raynal
2024-10-25 16:14   ` Miquel Raynal
2024-11-11 14:27   ` Tudor Ambarus
2024-11-11 14:27     ` Tudor Ambarus
2024-12-18  8:16     ` Tudor Ambarus
2024-12-18  8:16       ` Tudor Ambarus
2024-12-18  9:34       ` Miquel Raynal
2024-12-18  9:34         ` Miquel Raynal
2024-10-25 16:14 ` [PATCH 20/24] spi: spi-mem: Reorder SPI_MEM_OP_CMD internals Miquel Raynal
2024-10-25 16:14   ` Miquel Raynal
2024-11-11 14:32   ` Tudor Ambarus
2024-11-11 14:32     ` Tudor Ambarus
2024-12-13 12:05     ` Miquel Raynal
2024-12-13 12:05       ` Miquel Raynal
2024-10-25 16:14 ` [PATCH 21/24] spi: spi-mem: Create macros for DTR operation Miquel Raynal
2024-10-25 16:14   ` Miquel Raynal
2024-10-25 16:14 ` [PATCH 22/24] mtd: spinand: Add support for read DTR operations Miquel Raynal
2024-10-25 16:14   ` Miquel Raynal
2024-11-11 14:35   ` Tudor Ambarus
2024-11-11 14:35     ` Tudor Ambarus
2024-12-13 12:08     ` Miquel Raynal
2024-12-13 12:08       ` Miquel Raynal
2024-12-18  8:10       ` Tudor Ambarus
2024-12-18  8:10         ` Tudor Ambarus
2024-10-25 16:15 ` [PATCH 23/24] mtd: spinand: winbond: Add comment about naming Miquel Raynal
2024-10-25 16:15   ` Miquel Raynal
2024-11-11 14:38   ` Tudor Ambarus
2024-11-11 14:38     ` Tudor Ambarus
2024-11-13  9:46     ` Tudor Ambarus
2024-11-13  9:46       ` Tudor Ambarus
2024-12-13 12:25     ` Miquel Raynal [this message]
2024-12-13 12:25       ` Miquel Raynal
2024-12-18  8:14       ` Tudor Ambarus
2024-12-18  8:14         ` Tudor Ambarus
2024-12-18  9:33         ` Miquel Raynal
2024-12-18  9:33           ` Miquel Raynal
2024-12-18 10:21           ` Tudor Ambarus
2024-12-18 10:21             ` Tudor Ambarus
2024-10-25 16:15 ` [PATCH 24/24] mtd: spinand: winbond: Add support for DTR operations Miquel Raynal
2024-10-25 16:15   ` Miquel Raynal
2024-11-11 14:40   ` Tudor Ambarus
2024-11-11 14:40     ` Tudor Ambarus
2024-12-23 18:22     ` Miquel Raynal
2024-12-23 18:22       ` Miquel Raynal
2024-12-24  9:38       ` Miquel Raynal
2024-12-24  9:38         ` Miquel Raynal
2025-01-10 15:47 ` (subset) [PATCH 00/24] spi-nand/spi-mem DTR support Mark Brown
2025-01-10 15:47   ` Mark Brown

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