[PATCH] x86, hvm: Allow delivery of timer interrupts to VCPUs != 0.

[PATCH] x86, hvm: Allow delivery of timer interrupts to VCPUs != 0.

[Kouya Shimura]

[-- Attachment #1: message body text --]
[-- Type: text/plain, Size: 120 bytes --]

This patch is needed for kexec/kdump since kdump may halt VCPU#0.

Signed-off-by: Kouya Shimura <kouya@jp.fujitsu.com>


[-- Attachment #2: virt_wire_pt.patch --]
[-- Type: text/x-patch, Size: 4639 bytes --]

diff -r 80839a223746 xen/arch/x86/hvm/i8254.c
--- a/xen/arch/x86/hvm/i8254.c	Wed Jul 01 20:22:29 2009 +0100
+++ b/xen/arch/x86/hvm/i8254.c	Fri Jul 03 13:17:44 2009 +0900
@@ -42,7 +42,7 @@
 #define vcpu_vpit(vcpu)  (domain_vpit((vcpu)->domain))
 #define vpit_domain(pit) (container_of((pit), struct domain, \
                                        arch.hvm_domain.pl_time.vpit))
-#define vpit_vcpu(pit)   (vpit_domain(pit)->vcpu[0])
+#define vpit_vcpu(pit)   (pit->pt0.vcpu ? : pt_i8259_target(vpit_domain(pit)))
 
 #define RW_STATE_LSB 1
 #define RW_STATE_MSB 2
diff -r 80839a223746 xen/arch/x86/hvm/rtc.c
--- a/xen/arch/x86/hvm/rtc.c	Wed Jul 01 20:22:29 2009 +0100
+++ b/xen/arch/x86/hvm/rtc.c	Fri Jul 03 13:17:44 2009 +0900
@@ -32,7 +32,7 @@
 #define vcpu_vrtc(vcpu)  (domain_vrtc((vcpu)->domain))
 #define vrtc_domain(rtc) (container_of((rtc), struct domain, \
                                        arch.hvm_domain.pl_time.vrtc))
-#define vrtc_vcpu(rtc)   (vrtc_domain(rtc)->vcpu[0])
+#define vrtc_vcpu(rtc)   (rtc->pt.vcpu ? : pt_i8259_target(vrtc_domain(rtc)))
 
 static void rtc_periodic_cb(struct vcpu *v, void *opaque)
 {
diff -r 80839a223746 xen/arch/x86/hvm/vlapic.c
--- a/xen/arch/x86/hvm/vlapic.c	Wed Jul 01 20:22:29 2009 +0100
+++ b/xen/arch/x86/hvm/vlapic.c	Fri Jul 03 13:17:44 2009 +0900
@@ -809,7 +809,10 @@ void vlapic_adjust_i8259_target(struct d
 
     for_each_vcpu ( d, v )
         if ( __vlapic_accept_pic_intr(v) )
+        {
+            pt_adjust_i8259_target(v);
             goto found;
+        }
 
     v = d->vcpu ? d->vcpu[0] : NULL;
 
diff -r 80839a223746 xen/arch/x86/hvm/vpt.c
--- a/xen/arch/x86/hvm/vpt.c	Wed Jul 01 20:22:29 2009 +0100
+++ b/xen/arch/x86/hvm/vpt.c	Fri Jul 03 13:17:44 2009 +0900
@@ -419,13 +419,16 @@ void create_periodic_time(
     spin_unlock(&v->arch.hvm_vcpu.tm_lock);
 }
 
-void destroy_periodic_time(struct periodic_time *pt)
+int destroy_periodic_time(struct periodic_time *pt)
 {
+    int on_list;
+
     /* Was this structure previously initialised by create_periodic_time()? */
     if ( pt->vcpu == NULL )
-        return;
+        return 0;
 
     pt_lock(pt);
+    on_list = pt->on_list;
     if ( pt->on_list )
         list_del(&pt->list);
     pt->on_list = 0;
@@ -436,4 +439,53 @@ void destroy_periodic_time(struct period
      * outside pt_lock() otherwise we can deadlock with pt_timer_fn().
      */
     kill_timer(&pt->timer);
+    return on_list;
 }
+
+static void pt_adjust_vcpu(struct periodic_time *pt, struct vcpu *v)
+{
+    int on_list;
+
+    ASSERT(pt->source == PTSRC_isa);
+
+    if ( pt->vcpu == NULL || pt->vcpu == v )
+        return;
+
+    on_list = destroy_periodic_time(pt);
+
+    spin_lock(&v->arch.hvm_vcpu.tm_lock);
+    pt->vcpu = v;
+    if ( on_list )
+    {
+        pt->last_plt_gtime = hvm_get_guest_time(v);
+
+        pt->on_list = 1;
+        list_add(&pt->list, &v->arch.hvm_vcpu.tm_list);
+
+        migrate_timer(&pt->timer, v->processor);
+    }
+    spin_unlock(&v->arch.hvm_vcpu.tm_lock);
+}
+
+void pt_adjust_i8259_target(struct vcpu *v)
+{
+    struct pl_time *pl_time = &v->domain->arch.hvm_domain.pl_time;
+    int i;
+
+    spin_lock(&pl_time->vpit.lock);
+    pt_adjust_vcpu(&pl_time->vpit.pt0, v);
+    spin_unlock(&pl_time->vpit.lock);
+
+    spin_lock(&pl_time->vrtc.lock);
+    pt_adjust_vcpu(&pl_time->vrtc.pt, v);
+    spin_unlock(&pl_time->vrtc.lock);
+
+    spin_lock(&pl_time->vhpet.lock);
+    if ( pl_time->vhpet.vcpu != v )
+    {
+        pl_time->vhpet.vcpu = v;
+        for ( i = 0; i < HPET_TIMER_NUM; i++ )
+            pt_adjust_vcpu(&pl_time->vhpet.pt[i], v);
+    }
+    spin_unlock(&pl_time->vhpet.lock);
+}
diff -r 80839a223746 xen/include/asm-x86/hvm/vpt.h
--- a/xen/include/asm-x86/hvm/vpt.h	Wed Jul 01 20:22:29 2009 +0100
+++ b/xen/include/asm-x86/hvm/vpt.h	Fri Jul 03 13:17:44 2009 +0900
@@ -142,6 +142,10 @@ void pt_intr_post(struct vcpu *v, struct
 void pt_intr_post(struct vcpu *v, struct hvm_intack intack);
 void pt_reset(struct vcpu *v);
 void pt_migrate(struct vcpu *v);
+void pt_adjust_i8259_target(struct vcpu *v);
+
+#define pt_i8259_target(d) \
+    ((d)->arch.hvm_domain.i8259_target ? : (d)->vcpu[0])
 
 /* Is given periodic timer active? */
 #define pt_active(pt) ((pt)->on_list)
@@ -158,7 +162,7 @@ void create_periodic_time(
 void create_periodic_time(
     struct vcpu *v, struct periodic_time *pt, uint64_t delta,
     uint64_t period, uint8_t irq, time_cb *cb, void *data);
-void destroy_periodic_time(struct periodic_time *pt);
+int destroy_periodic_time(struct periodic_time *pt);
 
 int pv_pit_handler(int port, int data, int write);
 void pit_reset(struct domain *d);

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Re: [PATCH] x86, hvm: Allow delivery of timer interrupts to VCPUs != 0.

[Keir Fraser]

This doesn't look too bad, given the current vpt interface we have. My main
comment is regarding vpit_vcpu(), vrtc_vcpu() and vhpet.vcpu. Seems all of
these could unconditionally use i8259_target. I suggest also introducing
vhpet_vcpu(), and then pointing all three *_vcpu() macros at
pt_i8259_target() only. And get rid of the vhpet.vcpu field.

Would that work okay?

 -- Keir

On 03/07/2009 05:27, "Kouya Shimura" <kouya@jp.fujitsu.com> wrote:

> This patch is needed for kexec/kdump since kdump may halt VCPU#0.
> 
> Signed-off-by: Kouya Shimura <kouya@jp.fujitsu.com>
> 

Re: [PATCH] x86, hvm: Allow delivery of timer interrupts to VCPUs != 0.

[Kouya Shimura]

Keir Fraser writes:
> This doesn't look too bad, given the current vpt interface we have. My main
> comment is regarding vpit_vcpu(), vrtc_vcpu() and vhpet.vcpu. Seems all of
> these could unconditionally use i8259_target. I suggest also introducing
> vhpet_vcpu(), and then pointing all three *_vcpu() macros at
> pt_i8259_target() only. And get rid of the vhpet.vcpu field.
> 
> Would that work okay?

Probably no problem, but may I modify vlapic.c as follows?

diff -r 80839a223746 xen/arch/x86/hvm/vlapic.c
--- a/xen/arch/x86/hvm/vlapic.c	Wed Jul 01 20:22:29 2009 +0100
+++ b/xen/arch/x86/hvm/vlapic.c	Fri Jul 03 15:59:56 2009 +0900
@@ -809,12 +809,11 @@ void vlapic_adjust_i8259_target(struct d
     for_each_vcpu ( d, v )
         if ( __vlapic_accept_pic_intr(v) )
-            goto found;
-
-    v = d->vcpu ? d->vcpu[0] : NULL;
-
- found:
-    d->arch.hvm_domain.i8259_target = v;
+        {
+            d->arch.hvm_domain.i8259_target = v;
+            return;
+        }
 }

The reasons are:
- I'm afraid that d->arch.hvm_domain.i8259_target == NULL
- if vcpu[0] is halted and all vlapic.LVT0 are masked,
  timer doesn't work even when vlapic will be unmasked
  not as ExtINT mode.

So, I think that the last __vlapic_accept_pic_intr'ed vcpu
should be reserved in d->arch.hvm_domain.i8259_target.

Thanks,
Kouya

Re: [PATCH] x86, hvm: Allow delivery of timer interrupts to VCPUs != 0.

[Keir Fraser]

On 03/07/2009 08:57, "Kouya Shimura" <kouya@jp.fujitsu.com> wrote:

> - I'm afraid that d->arch.hvm_domain.i8259_target == NULL

If VCPUj is != NULL then VCPUi is also != NULL for all i < j. So this is not
a concern: there's always a VCPU0 if there are any VCPUs at all.

> - if vcpu[0] is halted and all vlapic.LVT0 are masked,
>   timer doesn't work even when vlapic will be unmasked
>   not as ExtINT mode.

Not sure what you mean? If legacy IRQs are routed through the IOAPIC then it
does not matter whether LAPIC.LVT0 is masked. And __vlapic_accept_pic_intr()
correctly handles that. If virtual wire mode is not through the IOAPIC then
of course LVT0 mask does matter, but I think we have that case correct too.

> So, I think that the last __vlapic_accept_pic_intr'ed vcpu
> should be reserved in d->arch.hvm_domain.i8259_target.

I don't think the logic needs to change.

 -- Keir

Re: [PATCH] x86, hvm: Allow delivery of timer interrupts to VCPUs != 0.

[Kouya Shimura]

Hi Keir,

You are correct. I misunderstood the issue. 
With your suggestion (always use i8259_target), i8259_target in kdump
transits as: NULL=>vcpu1=>vcpu0=>vcpu1.
In this case, timer interrupts were missed in my previous patch, but
that was my fault. (I felt weird that i8259_target points vcpu0 in
spite of the halt)

I'll post two patches per your suggestion. one is cleanup of hpet.c
and the other is for delivery of timer interrupts.

Thanks,
Kouya

Keir Fraser writes:
> On 03/07/2009 08:57, "Kouya Shimura" <kouya@jp.fujitsu.com> wrote:
> 
> > - I'm afraid that d->arch.hvm_domain.i8259_target == NULL
> 
> If VCPUj is != NULL then VCPUi is also != NULL for all i < j. So this is not
> a concern: there's always a VCPU0 if there are any VCPUs at all.
> 
> > - if vcpu[0] is halted and all vlapic.LVT0 are masked,
> >   timer doesn't work even when vlapic will be unmasked
> >   not as ExtINT mode.
> 
> Not sure what you mean? If legacy IRQs are routed through the IOAPIC then it
> does not matter whether LAPIC.LVT0 is masked. And __vlapic_accept_pic_intr()
> correctly handles that. If virtual wire mode is not through the IOAPIC then
> of course LVT0 mask does matter, but I think we have that case correct too.
> 
> > So, I think that the last __vlapic_accept_pic_intr'ed vcpu
> > should be reserved in d->arch.hvm_domain.i8259_target.
> 
> I don't think the logic needs to change.
> 
>  -- Keir
> 

[PATCH 1/2] x86, hvm: cleanup hpet.c as well as i8254.c or rtc.c

[Kouya Shimura]

[-- Attachment #1: cleanup_hpet.patch --]
[-- Type: text/x-patch, Size: 6430 bytes --]

# HG changeset patch
# User Kouya Shimura <kouya@jp.fujitsu.com>
# Date 1246859649 -32400
# Node ID 73e220236f6e50ac8de2470e88e91b75e3c2d01f
# Parent  c23d71600634232c08da32086a17679634c13d4b
x86,hvm: cleanup hpet.c as well as i8254.c or rtc.c

- introduce macros: domain_vhpet, vcpu_vhpet, vhpet_domain, vhpet_vcpu
- remove *vcpu field from struct HPETState
- modify guest_time_hpet() takes *vhpet instead of *vcpu as 1st argument

Signed-off-by: Kouya Shimura <kouya@jp.fujitsu.com>

diff -r c23d71600634 -r 73e220236f6e xen/arch/x86/hvm/hpet.c
--- a/xen/arch/x86/hvm/hpet.c	Fri Jul 03 08:54:51 2009 +0100
+++ b/xen/arch/x86/hvm/hpet.c	Mon Jul 06 14:54:09 2009 +0900
@@ -24,6 +24,12 @@
 #include <xen/sched.h>
 #include <xen/event.h>
 
+#define domain_vhpet(d)    (&(d)->arch.hvm_domain.pl_time.vhpet)
+#define vcpu_vhpet(vcpu)   (domain_vhpet((vcpu)->domain))
+#define vhpet_domain(hpet) (container_of((hpet), struct domain, \
+                                         arch.hvm_domain.pl_time.vhpet))
+#define vhpet_vcpu(hpet)   (vhpet_domain(hpet)->vcpu[0])
+
 #define HPET_BASE_ADDRESS   0xfed00000ULL
 #define HPET_MMAP_SIZE      1024
 #define S_TO_NS  1000000000ULL           /* 1s  = 10^9  ns */
@@ -31,7 +37,8 @@
 
 /* Frequency_of_Xen_systeme_time / frequency_of_HPET = 16 */
 #define STIME_PER_HPET_TICK 16
-#define guest_time_hpet(v) (hvm_get_guest_time(v) / STIME_PER_HPET_TICK)
+#define guest_time_hpet(hpet) \
+    (hvm_get_guest_time(vhpet_vcpu(hpet)) / STIME_PER_HPET_TICK)
 
 #define HPET_ID         0x000
 #define HPET_PERIOD     0x004
@@ -94,7 +101,7 @@ static inline uint64_t hpet_read_maincou
     ASSERT(spin_is_locked(&h->lock));
 
     if ( hpet_enabled(h) )
-        return guest_time_hpet(h->vcpu) + h->mc_offset;
+        return guest_time_hpet(h) + h->mc_offset;
     else 
         return h->hpet.mc64;
 }
@@ -176,7 +183,7 @@ static int hpet_read(
     struct vcpu *v, unsigned long addr, unsigned long length,
     unsigned long *pval)
 {
-    HPETState *h = &v->domain->arch.hvm_domain.pl_time.vhpet;
+    HPETState *h = vcpu_vhpet(v);
     unsigned long result;
     uint64_t val;
 
@@ -230,7 +237,7 @@ static void hpet_set_timer(HPETState *h,
     {
         /* HPET specification requires PIT shouldn't generate
          * interrupts if LegacyReplacementRoute is set for timer0 */
-        PITState *pit = &h->vcpu->domain->arch.hvm_domain.pl_time.vpit;
+        PITState *pit = &vhpet_domain(h)->arch.hvm_domain.pl_time.vpit;
         pit_stop_channel0_irq(pit);
     }
 
@@ -272,7 +279,7 @@ static void hpet_set_timer(HPETState *h,
      * being enabled (now).
      */
     oneshot = !timer_is_periodic(h, tn);
-    create_periodic_time(h->vcpu, &h->pt[tn],
+    create_periodic_time(vhpet_vcpu(h), &h->pt[tn],
                          hpet_tick_to_ns(h, diff),
                          oneshot ? 0 : hpet_tick_to_ns(h, h->hpet.period[tn]),
                          irq, NULL, NULL);
@@ -290,7 +297,7 @@ static int hpet_write(
     struct vcpu *v, unsigned long addr,
     unsigned long length, unsigned long val)
 {
-    HPETState *h = &v->domain->arch.hvm_domain.pl_time.vhpet;
+    HPETState *h = vcpu_vhpet(v);
     uint64_t old_val, new_val;
     int tn, i;
 
@@ -323,7 +330,7 @@ static int hpet_write(
         if ( !(old_val & HPET_CFG_ENABLE) && (new_val & HPET_CFG_ENABLE) )
         {
             /* Enable main counter and interrupt generation. */
-            h->mc_offset = h->hpet.mc64 - guest_time_hpet(h->vcpu);
+            h->mc_offset = h->hpet.mc64 - guest_time_hpet(h);
             for ( i = 0; i < HPET_TIMER_NUM; i++ )
             {
                 h->hpet.comparator64[i] =
@@ -337,7 +344,7 @@ static int hpet_write(
         else if ( (old_val & HPET_CFG_ENABLE) && !(new_val & HPET_CFG_ENABLE) )
         {
             /* Halt main counter and disable interrupt generation. */
-            h->hpet.mc64 = h->mc_offset + guest_time_hpet(h->vcpu);
+            h->hpet.mc64 = h->mc_offset + guest_time_hpet(h);
             for ( i = 0; i < HPET_TIMER_NUM; i++ )
                 if ( timer_enabled(h, i) )
                     set_stop_timer(i);
@@ -487,13 +494,13 @@ struct hvm_mmio_handler hpet_mmio_handle
 
 static int hpet_save(struct domain *d, hvm_domain_context_t *h)
 {
-    HPETState *hp = &d->arch.hvm_domain.pl_time.vhpet;
+    HPETState *hp = domain_vhpet(d);
     int rc;
 
     spin_lock(&hp->lock);
 
     /* Write the proper value into the main counter */
-    hp->hpet.mc64 = hp->mc_offset + guest_time_hpet(hp->vcpu);
+    hp->hpet.mc64 = hp->mc_offset + guest_time_hpet(hp);
 
     /* Save the HPET registers */
     rc = _hvm_init_entry(h, HVM_SAVE_CODE(HPET), 0, HVM_SAVE_LENGTH(HPET));
@@ -531,7 +538,7 @@ static int hpet_save(struct domain *d, h
 
 static int hpet_load(struct domain *d, hvm_domain_context_t *h)
 {
-    HPETState *hp = &d->arch.hvm_domain.pl_time.vhpet;
+    HPETState *hp = domain_vhpet(d);
     struct hvm_hw_hpet *rec;
     uint64_t cmp;
     int i;
@@ -572,7 +579,7 @@ static int hpet_load(struct domain *d, h
 #undef C
     
     /* Recalculate the offset between the main counter and guest time */
-    hp->mc_offset = hp->hpet.mc64 - guest_time_hpet(hp->vcpu);
+    hp->mc_offset = hp->hpet.mc64 - guest_time_hpet(hp);
 
     /* restart all timers */
 
@@ -590,14 +597,13 @@ HVM_REGISTER_SAVE_RESTORE(HPET, hpet_sav
 
 void hpet_init(struct vcpu *v)
 {
-    HPETState *h = &v->domain->arch.hvm_domain.pl_time.vhpet;
+    HPETState *h = vcpu_vhpet(v);
     int i;
 
     memset(h, 0, sizeof(HPETState));
 
     spin_lock_init(&h->lock);
 
-    h->vcpu = v;
     h->stime_freq = S_TO_NS;
 
     h->hpet_to_ns_scale = ((S_TO_NS * STIME_PER_HPET_TICK) << 10) / h->stime_freq;
@@ -622,7 +628,7 @@ void hpet_deinit(struct domain *d)
 void hpet_deinit(struct domain *d)
 {
     int i;
-    HPETState *h = &d->arch.hvm_domain.pl_time.vhpet;
+    HPETState *h = domain_vhpet(d);
 
     spin_lock(&h->lock);
 
diff -r c23d71600634 -r 73e220236f6e xen/include/asm-x86/hvm/vpt.h
--- a/xen/include/asm-x86/hvm/vpt.h	Fri Jul 03 08:54:51 2009 +0100
+++ b/xen/include/asm-x86/hvm/vpt.h	Mon Jul 06 14:54:09 2009 +0900
@@ -92,7 +92,6 @@ struct hpet_registers {
 
 typedef struct HPETState {
     struct hpet_registers hpet;
-    struct vcpu *vcpu;
     uint64_t stime_freq;
     uint64_t hpet_to_ns_scale; /* hpet ticks to ns (multiplied by 2^10) */
     uint64_t hpet_to_ns_limit; /* max hpet ticks convertable to ns      */


[-- Attachment #2: Type: text/plain, Size: 138 bytes --]

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[PATCH 2/2] x86, hvm: Allow delivery of timer interrupts to VCPUs != 0

[Kouya Shimura]

[-- Attachment #1: kdump_vpt.patch --]
[-- Type: text/x-patch, Size: 4725 bytes --]

# HG changeset patch
# User Kouya Shimura <kouya@jp.fujitsu.com>
# Date 1246862381 -32400
# Node ID a0d51bbdca910b3ea25cdb8e6f533a01af332a8e
# Parent  73e220236f6e50ac8de2470e88e91b75e3c2d01f
x86,hvm: Allow delivery of timer interrupts to VCPUs != 0

This patch is needed for kexec/kdump since VCPU#0 is halted.

Signed-off-by: Kouya Shimura <kouya@jp.fujitsu.com>

diff -r 73e220236f6e -r a0d51bbdca91 xen/arch/x86/hvm/hpet.c
--- a/xen/arch/x86/hvm/hpet.c	Mon Jul 06 14:54:09 2009 +0900
+++ b/xen/arch/x86/hvm/hpet.c	Mon Jul 06 15:39:41 2009 +0900
@@ -28,7 +28,7 @@
 #define vcpu_vhpet(vcpu)   (domain_vhpet((vcpu)->domain))
 #define vhpet_domain(hpet) (container_of((hpet), struct domain, \
                                          arch.hvm_domain.pl_time.vhpet))
-#define vhpet_vcpu(hpet)   (vhpet_domain(hpet)->vcpu[0])
+#define vhpet_vcpu(hpet)   (pt_i8259_target(vhpet_domain(hpet)))
 
 #define HPET_BASE_ADDRESS   0xfed00000ULL
 #define HPET_MMAP_SIZE      1024
diff -r 73e220236f6e -r a0d51bbdca91 xen/arch/x86/hvm/i8254.c
--- a/xen/arch/x86/hvm/i8254.c	Mon Jul 06 14:54:09 2009 +0900
+++ b/xen/arch/x86/hvm/i8254.c	Mon Jul 06 15:39:41 2009 +0900
@@ -42,7 +42,7 @@
 #define vcpu_vpit(vcpu)  (domain_vpit((vcpu)->domain))
 #define vpit_domain(pit) (container_of((pit), struct domain, \
                                        arch.hvm_domain.pl_time.vpit))
-#define vpit_vcpu(pit)   (vpit_domain(pit)->vcpu[0])
+#define vpit_vcpu(pit)   (pt_i8259_target(vpit_domain(pit)))
 
 #define RW_STATE_LSB 1
 #define RW_STATE_MSB 2
diff -r 73e220236f6e -r a0d51bbdca91 xen/arch/x86/hvm/rtc.c
--- a/xen/arch/x86/hvm/rtc.c	Mon Jul 06 14:54:09 2009 +0900
+++ b/xen/arch/x86/hvm/rtc.c	Mon Jul 06 15:39:41 2009 +0900
@@ -32,7 +32,7 @@
 #define vcpu_vrtc(vcpu)  (domain_vrtc((vcpu)->domain))
 #define vrtc_domain(rtc) (container_of((rtc), struct domain, \
                                        arch.hvm_domain.pl_time.vrtc))
-#define vrtc_vcpu(rtc)   (vrtc_domain(rtc)->vcpu[0])
+#define vrtc_vcpu(rtc)   (pt_i8259_target(vrtc_domain(rtc)))
 
 static void rtc_periodic_cb(struct vcpu *v, void *opaque)
 {
diff -r 73e220236f6e -r a0d51bbdca91 xen/arch/x86/hvm/vlapic.c
--- a/xen/arch/x86/hvm/vlapic.c	Mon Jul 06 14:54:09 2009 +0900
+++ b/xen/arch/x86/hvm/vlapic.c	Mon Jul 06 15:39:41 2009 +0900
@@ -814,7 +814,11 @@ void vlapic_adjust_i8259_target(struct d
     v = d->vcpu ? d->vcpu[0] : NULL;
 
  found:
-    d->arch.hvm_domain.i8259_target = v;
+    if ( d->arch.hvm_domain.i8259_target != v )
+    {
+        d->arch.hvm_domain.i8259_target = v;
+        pt_adjust_i8259_target(v);
+    }
 }
 
 int vlapic_has_pending_irq(struct vcpu *v)
diff -r 73e220236f6e -r a0d51bbdca91 xen/arch/x86/hvm/vpt.c
--- a/xen/arch/x86/hvm/vpt.c	Mon Jul 06 14:54:09 2009 +0900
+++ b/xen/arch/x86/hvm/vpt.c	Mon Jul 06 15:39:41 2009 +0900
@@ -437,3 +437,53 @@ void destroy_periodic_time(struct period
      */
     kill_timer(&pt->timer);
 }
+
+static void pt_adjust_vcpu(struct periodic_time *pt, struct vcpu *v)
+{
+    int on_list;
+
+    ASSERT(pt->source == PTSRC_isa);
+
+    if ( pt->vcpu == NULL )
+        return;
+
+    pt_lock(pt);
+    on_list = pt->on_list;
+    if ( pt->on_list )
+        list_del(&pt->list);
+    pt->on_list = 0;
+    pt_unlock(pt);
+
+    spin_lock(&v->arch.hvm_vcpu.tm_lock);
+    pt->vcpu = v;
+    if ( on_list )
+    {
+        pt->on_list = 1;
+        list_add(&pt->list, &v->arch.hvm_vcpu.tm_list);
+
+        migrate_timer(&pt->timer, v->processor);
+    }
+    spin_unlock(&v->arch.hvm_vcpu.tm_lock);
+}
+
+void pt_adjust_i8259_target(struct vcpu *v)
+{
+    struct pl_time *pl_time = &v->domain->arch.hvm_domain.pl_time;
+    int i;
+
+    if ( v == NULL )
+        return;
+
+    spin_lock(&pl_time->vpit.lock);
+    pt_adjust_vcpu(&pl_time->vpit.pt0, v);
+    spin_unlock(&pl_time->vpit.lock);
+
+    spin_lock(&pl_time->vrtc.lock);
+    pt_adjust_vcpu(&pl_time->vrtc.pt, v);
+    spin_unlock(&pl_time->vrtc.lock);
+
+    spin_lock(&pl_time->vhpet.lock);
+    for ( i = 0; i < HPET_TIMER_NUM; i++ )
+        pt_adjust_vcpu(&pl_time->vhpet.pt[i], v);
+    spin_unlock(&pl_time->vhpet.lock);
+}
diff -r 73e220236f6e -r a0d51bbdca91 xen/include/asm-x86/hvm/vpt.h
--- a/xen/include/asm-x86/hvm/vpt.h	Mon Jul 06 14:54:09 2009 +0900
+++ b/xen/include/asm-x86/hvm/vpt.h	Mon Jul 06 15:39:41 2009 +0900
@@ -141,6 +141,10 @@ void pt_intr_post(struct vcpu *v, struct
 void pt_intr_post(struct vcpu *v, struct hvm_intack intack);
 void pt_reset(struct vcpu *v);
 void pt_migrate(struct vcpu *v);
+void pt_adjust_i8259_target(struct vcpu *v);
+
+#define pt_i8259_target(d) \
+    ((d)->arch.hvm_domain.i8259_target ? : (d)->vcpu[0])
 
 /* Is given periodic timer active? */
 #define pt_active(pt) ((pt)->on_list)


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Re: [PATCH 2/2] x86, hvm: Allow delivery of timer interrupts to VCPUs != 0

[Keir Fraser]

I applied your patches, thanks. Feel free to submit something similar for
passthrough IRQ handling.

 -- Keir