* [RFC PATCH 00/56] disas/riscv: Reorganize the disassembler
@ 2026-08-09 22:34 Richard Henderson
2026-08-09 22:34 ` [PATCH 01/56] disas/riscv: Fix th.srri decoding Richard Henderson
` (55 more replies)
0 siblings, 56 replies; 119+ messages in thread
From: Richard Henderson @ 2026-08-09 22:34 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-riscv
One of my pet peeves is the non-automatic addition of indexes to rv_op
which must match entries in rvi_opcode_data[].
Reorganize the disassembler to pass around pointers to individual opcodes
rather than pointer to table + index. To do that, rewrite how pseudo ops
are processed, replacing indexes with pointers. Merge the decompression
of compressed opcodes into the pseudo ops mechanism.
Fix quite a few bugs found in the process, mostly related to isa level.
I grabbed Tiancheng's bug fixes to start, to avoid reworking those.
r~
Richard Henderson (51):
disas/riscv: Move operand extractors earlier in file
disas/riscv: Reduce rv_insn to uint32_t
disas/riscv: Tidy dec initialization in disasm_inst
disas/riscv: Pass rv_opcode_data pointer to decode_inst_operands
disas/riscv: Pass rv_opcode_data pointer to/from
decode_inst_decompress
disas/riscv: Pass rv_opcode_data pointer to/from
decode_inst_lift_pseudo
disas/riscv: Pass rv_opcode_data pointer to format_inst
disas/riscv: Tidy disasm_inst main loop
disas/riscv: Set dec->opcode_data in decode function
disas/riscv: Drop explicit zero of rv_opcode_data fields
disas/riscv: Drop useless const in structures
disas/riscv: Drop codec from rv_decode
disas/riscv: Handle c.addi4spn imm != 0 during decode
disas/riscv: Simplify c.addi
disas/riscv: Handle c.lui imm != 0 during decode
disas/riscv: Handle c.{srli,srai} imm during decode
disas/riscv: Handle c.slli imm != 0 during decode
disas/riscv: Do not recognize c.{addw,subw} with rv32
disas/riscv: Remove rvcd_imm_nz
disas/riscv: Unify decomp_rv{32,64,128}
disas/riscv: Drop always true branch psudeos
disas/riscv: Handle aliases of csrrw during decode
disas/riscv: Handle aliases of csrrs during decode
disas/riscv: Handle aliases of csrrwi during decode
disas/riscv: Break pseudo loop for jal and jalr
disas/riscv: Allow decode_inst_lift_pseudo to loop
disas/riscv: Handle decompression via decode_inst_lift_pseudo
disas/riscv: Drop format from DECOMP insns
disas/riscv: Tidy rv_comp_data terminators
disas/riscv: Chain "ret" pseudo off "jr" pseudo
disas/riscv: Chain "nop" pseudo off "mv" pseudo
disas/riscv: Use rv_codec_illegal for pseudos
disas/riscv: Simplify some insn decompressions
disas/riscv: Store op pointer in rv_comp_data
disas/riscv: Return rv_opcode_data pointer from decoders
disas/riscv: Reject all of OP-32 and OP-IMM-32 for RV32
disas/riscv: Fix rv32 encoding of zext.h
disas/riscv: Fix isa decoding of rev8
disas/riscv: Fix typo in th.lbib format
disas/riscv: Split ventana_opcode_data
disas/riscv: Split xlrbr_opcode_data
disas/riscv: Split xthead_opcode_data
disas/riscv: Move rv_op_illegal to riscv.c
disas/riscv: Split out riscv-op.c.inc
disas/riscv: Merge all mop.r.n to one pattern
disas/riscv: Merge all mop.rr.n to one pattern
disas/riscv: Merge all c.mop.n to one pattern
disas/riscv: Tidy decode of c.mop.n
disas/riscv: Tidy decode of mop.r.n and mop.rr.n
disas/riscv: Split rvi_opcode_data
disas/riscv: Sort riscv-op.c.inc
TANG Tiancheng (5):
disas/riscv: Fix th.srri decoding
disas/riscv: Fix 6-bit immediate extraction
disas/riscv: Use signed type for vector immediates
disas/riscv: Decode unsigned vector immediates as unsigned
disas/riscv: Use extract helpers for operand fields
disas/riscv-xlrbr.h | 4 +-
disas/riscv-xthead.h | 24 +-
disas/riscv-xventana.h | 4 +-
disas/riscv.h | 47 +-
disas/riscv-xlrbr.c | 57 +-
disas/riscv-xthead.c | 507 +---
disas/riscv-xventana.c | 23 +-
disas/riscv.c | 5255 ++++++++++-----------------------
disas/riscv-op.c.inc | 913 ++++++
disas/riscv-xlrbr-op.c.inc | 8 +
disas/riscv-xthead-op.c.inc | 125 +
disas/riscv-xventana-op.c.inc | 2 +
12 files changed, 2852 insertions(+), 4117 deletions(-)
create mode 100644 disas/riscv-op.c.inc
create mode 100644 disas/riscv-xlrbr-op.c.inc
create mode 100644 disas/riscv-xthead-op.c.inc
create mode 100644 disas/riscv-xventana-op.c.inc
--
2.43.0
^ permalink raw reply [flat|nested] 119+ messages in thread
* [PATCH 01/56] disas/riscv: Fix th.srri decoding
2026-08-09 22:34 [RFC PATCH 00/56] disas/riscv: Reorganize the disassembler Richard Henderson
@ 2026-08-09 22:34 ` Richard Henderson
2026-08-11 19:54 ` Alistair
2026-08-09 22:34 ` [PATCH 02/56] disas/riscv: Fix 6-bit immediate extraction Richard Henderson
` (54 subsequent siblings)
55 siblings, 1 reply; 119+ messages in thread
From: Richard Henderson @ 2026-08-09 22:34 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, TANG Tiancheng, LIU Zhiwei, Daniel Henrique Barboza
From: TANG Tiancheng <lyndra@linux.alibaba.com>
target/riscv/xthead.decode defines th.srri as funct6=000100 in
bits 31:26, with the 6-bit immediate in bits 25:20.
decode_xtheadbb() switches on bits 31:25, i.e. funct6 plus imm[5].
Therefore valid th.srri encodings are 0001000 and 0001001. The
current 0000100 and 0000101 cases use the wrong funct6 value and
decode valid th.srri instructions as illegal.
Fix the cases to match funct6=000100 with both imm[5] values.
Fixes: 318df7238b9f ("disas/riscv: Add support for XThead* instructions")
Signed-off-by: TANG Tiancheng <lyndra@linux.alibaba.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
Message-Id: <20260703-b4-disas-xthead-fix-riscv-next-v4-1-84c566330bc7@linux.alibaba.com>
---
disas/riscv-xthead.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/disas/riscv-xthead.c b/disas/riscv-xthead.c
index fcca326d1c..2f2ddb8dd9 100644
--- a/disas/riscv-xthead.c
+++ b/disas/riscv-xthead.c
@@ -315,8 +315,10 @@ void decode_xtheadbb(rv_decode *dec, rv_isa isa)
op = rv_op_th_revw;
}
break;
- case 0b0000100:
- case 0b0000101: op = rv_op_th_srri; break;
+ case 0b0001000:
+ case 0b0001001:
+ op = rv_op_th_srri;
+ break;
}
break;
case 2: op = rv_op_th_ext; break;
--
2.43.0
^ permalink raw reply related [flat|nested] 119+ messages in thread
* [PATCH 02/56] disas/riscv: Fix 6-bit immediate extraction
2026-08-09 22:34 [RFC PATCH 00/56] disas/riscv: Reorganize the disassembler Richard Henderson
2026-08-09 22:34 ` [PATCH 01/56] disas/riscv: Fix th.srri decoding Richard Henderson
@ 2026-08-09 22:34 ` Richard Henderson
2026-08-11 19:55 ` Alistair
2026-08-09 22:34 ` [PATCH 03/56] disas/riscv: Use signed type for vector immediates Richard Henderson
` (53 subsequent siblings)
55 siblings, 1 reply; 119+ messages in thread
From: Richard Henderson @ 2026-08-09 22:34 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, TANG Tiancheng, Alex Bennée, LIU Zhiwei,
Daniel Henrique Barboza
From: TANG Tiancheng <lyndra@linux.alibaba.com>
rv_codec_r2_imm6 is used for XThead instructions whose 6-bit
immediate field is encoded in bits 25:20. The old expression
left-shifted by 38 and then right-shifted by 60, so it kept only
bits 25:22.
Use extract32() to decode bits 25:20 directly. This fixes the
immediate printed for th.srri and th.tst.
Fixes: 318df7238b9f ("disas/riscv: Add support for XThead* instructions")
Suggested-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: TANG Tiancheng <lyndra@linux.alibaba.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
Message-Id: <20260703-b4-disas-xthead-fix-riscv-next-v4-2-84c566330bc7@linux.alibaba.com>
---
disas/riscv.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/disas/riscv.c b/disas/riscv.c
index 7f1b262773..fdf75a12ef 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -4546,7 +4546,7 @@ static uint32_t operand_zcmp_rlist(rv_inst inst)
static uint32_t operand_imm6(rv_inst inst)
{
- return (inst << 38) >> 60;
+ return extract32(inst, 20, 6);
}
static uint32_t operand_imm2(rv_inst inst)
--
2.43.0
^ permalink raw reply related [flat|nested] 119+ messages in thread
* [PATCH 03/56] disas/riscv: Use signed type for vector immediates
2026-08-09 22:34 [RFC PATCH 00/56] disas/riscv: Reorganize the disassembler Richard Henderson
2026-08-09 22:34 ` [PATCH 01/56] disas/riscv: Fix th.srri decoding Richard Henderson
2026-08-09 22:34 ` [PATCH 02/56] disas/riscv: Fix 6-bit immediate extraction Richard Henderson
@ 2026-08-09 22:34 ` Richard Henderson
2026-08-10 2:53 ` Philippe Mathieu-Daudé
2026-08-11 19:56 ` Alistair
2026-08-09 22:34 ` [PATCH 04/56] disas/riscv: Decode unsigned vector immediates as unsigned Richard Henderson
` (52 subsequent siblings)
55 siblings, 2 replies; 119+ messages in thread
From: Richard Henderson @ 2026-08-09 22:34 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-riscv, TANG Tiancheng, LIU Zhiwei
From: TANG Tiancheng <lyndra@linux.alibaba.com>
operand_vimm() sign-extends the 5-bit vector immediate field in bits
19:15, but returns uint32_t. This sends negative immediates through an
unsigned type before they are assigned to rv_decode.imm.
Return int32_t to match the signed value extracted by the helper.
Signed-off-by: TANG Tiancheng <lyndra@linux.alibaba.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Message-Id: <20260703-b4-disas-xthead-fix-riscv-next-v4-3-84c566330bc7@linux.alibaba.com>
---
disas/riscv.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/disas/riscv.c b/disas/riscv.c
index fdf75a12ef..967739bdbb 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -4487,7 +4487,7 @@ static uint32_t operand_cimmq(rv_inst inst)
((inst << 57) >> 62) << 6;
}
-static uint32_t operand_vimm(rv_inst inst)
+static int32_t operand_vimm(rv_inst inst)
{
return (int64_t)(inst << 44) >> 59;
}
--
2.43.0
^ permalink raw reply related [flat|nested] 119+ messages in thread
* [PATCH 04/56] disas/riscv: Decode unsigned vector immediates as unsigned
2026-08-09 22:34 [RFC PATCH 00/56] disas/riscv: Reorganize the disassembler Richard Henderson
` (2 preceding siblings ...)
2026-08-09 22:34 ` [PATCH 03/56] disas/riscv: Use signed type for vector immediates Richard Henderson
@ 2026-08-09 22:34 ` Richard Henderson
2026-08-11 19:57 ` Alistair
2026-08-09 22:34 ` [PATCH 05/56] disas/riscv: Use extract helpers for operand fields Richard Henderson
` (51 subsequent siblings)
55 siblings, 1 reply; 119+ messages in thread
From: Richard Henderson @ 2026-08-09 22:34 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-riscv, TANG Tiancheng, LIU Zhiwei
From: TANG Tiancheng <lyndra@linux.alibaba.com>
rv_codec_v_i decodes all .vi operands with operand_vimm(), which
sign-extends bits 19:15. That matches spec operands named imm, but not the
.vi forms whose operand is uimm; uimm=31 is decoded as -1 and printed by
the shared 6-bit 'u' formatter as 63.
Add rv_codec_v_i_u/operand_vuimm() for the 5-bit uimm forms: vsll.vi,
vsrl.vi, vsra.vi, vnsrl.wi, vnsra.wi, vssrl.vi, vssra.vi, vnclipu.wi,
vnclip.wi, vslideup.vi, vslidedown.vi, vrgather.vi, vaeskf1.vi,
vaeskf2.vi, vsm3c.vi, vsm4k.vi and vwsll.vi. The remaining rv_codec_v_i
entries are the signed imm forms.
Fixes: 07f4964d1785 ("disas/riscv.c: rvv: Add disas support for vector instructions")
Fixes: 9d92f56d4a44 ("disas/riscv: Add support for vector crypto extensions")
Signed-off-by: TANG Tiancheng <lyndra@linux.alibaba.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Message-Id: <20260703-b4-disas-xthead-fix-riscv-next-v4-4-84c566330bc7@linux.alibaba.com>
---
disas/riscv.h | 1 +
disas/riscv.c | 45 ++++++++++++++++++++++++++++-----------------
2 files changed, 29 insertions(+), 17 deletions(-)
diff --git a/disas/riscv.h b/disas/riscv.h
index 379e642ec8..91ada8b531 100644
--- a/disas/riscv.h
+++ b/disas/riscv.h
@@ -149,6 +149,7 @@ typedef enum {
rv_codec_v_r,
rv_codec_v_ldst,
rv_codec_v_i,
+ rv_codec_v_i_u,
rv_codec_vsetvli,
rv_codec_vsetivli,
rv_codec_vror_vi,
diff --git a/disas/riscv.c b/disas/riscv.c
index 967739bdbb..82b962dc71 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -1803,19 +1803,19 @@ const rv_opcode_data rvi_opcode_data[] = {
{ "vxor.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 },
{ "vsll.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
{ "vsll.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
- { "vsll.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 },
+ { "vsll.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 },
{ "vsrl.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
{ "vsrl.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
- { "vsrl.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 },
+ { "vsrl.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 },
{ "vsra.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
{ "vsra.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
- { "vsra.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 },
+ { "vsra.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 },
{ "vnsrl.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
{ "vnsrl.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
- { "vnsrl.wi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 },
+ { "vnsrl.wi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 },
{ "vnsra.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
{ "vnsra.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
- { "vnsra.wi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 },
+ { "vnsra.wi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 },
{ "vmseq.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
{ "vmseq.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
{ "vmseq.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 },
@@ -1909,16 +1909,16 @@ const rv_opcode_data rvi_opcode_data[] = {
{ "vsmul.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
{ "vssrl.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
{ "vssrl.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
- { "vssrl.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 },
+ { "vssrl.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 },
{ "vssra.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
{ "vssra.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
- { "vssra.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 },
+ { "vssra.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 },
{ "vnclipu.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
{ "vnclipu.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
- { "vnclipu.wi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 },
+ { "vnclipu.wi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 },
{ "vnclip.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
{ "vnclip.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
- { "vnclip.wi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 },
+ { "vnclip.wi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 },
{ "vfadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
{ "vfadd.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
{ "vfsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
@@ -2048,15 +2048,15 @@ const rv_opcode_data rvi_opcode_data[] = {
{ "vfmv.f.s", rv_codec_v_r, rv_fmt_fd_vs2, NULL, 0, 0, 0 },
{ "vfmv.s.f", rv_codec_v_r, rv_fmt_vd_fs1, NULL, 0, 0, 0 },
{ "vslideup.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
- { "vslideup.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 },
+ { "vslideup.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 },
{ "vslide1up.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
{ "vslidedown.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
- { "vslidedown.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 },
+ { "vslidedown.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 },
{ "vslide1down.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
{ "vrgather.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
{ "vrgatherei16.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
{ "vrgather.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
- { "vrgather.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 },
+ { "vrgather.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 },
{ "vcompress.vm", rv_codec_v_r, rv_fmt_vd_vs2_vs1, NULL, 0, 0, 0 },
{ "vmv1r.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
{ "vmv2r.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
@@ -2144,8 +2144,8 @@ const rv_opcode_data rvi_opcode_data[] = {
{ "vaesef.vs", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
{ "vaesem.vv", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
{ "vaesem.vs", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
- { "vaeskf1.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm, NULL, 0, 0, 0 },
- { "vaeskf2.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm, NULL, 0, 0, 0 },
+ { "vaeskf1.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm, NULL, 0, 0, 0 },
+ { "vaeskf2.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm, NULL, 0, 0, 0 },
{ "vaesz.vs", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
{ "vandn.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
{ "vandn.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
@@ -2169,14 +2169,14 @@ const rv_opcode_data rvi_opcode_data[] = {
{ "vsha2ch.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1, NULL, 0, 0, 0 },
{ "vsha2cl.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1, NULL, 0, 0, 0 },
{ "vsha2ms.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1, NULL, 0, 0, 0 },
- { "vsm3c.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm, NULL, 0, 0, 0 },
+ { "vsm3c.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm, NULL, 0, 0, 0 },
{ "vsm3me.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1, NULL, 0, 0, 0 },
- { "vsm4k.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm, NULL, 0, 0, 0 },
+ { "vsm4k.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm, NULL, 0, 0, 0 },
{ "vsm4r.vv", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
{ "vsm4r.vs", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
{ "vwsll.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
{ "vwsll.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
- { "vwsll.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 },
+ { "vwsll.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 },
{ "amocas.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
{ "amocas.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
{ "amocas.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
@@ -4492,6 +4492,11 @@ static int32_t operand_vimm(rv_inst inst)
return (int64_t)(inst << 44) >> 59;
}
+static uint32_t operand_vuimm(rv_inst inst)
+{
+ return extract32(inst, 15, 5);
+}
+
static uint32_t operand_vzimm11(rv_inst inst)
{
return (inst << 33) >> 53;
@@ -4895,6 +4900,12 @@ static void decode_inst_operands(rv_decode *dec, rv_isa isa)
dec->imm = operand_vimm(inst);
dec->vm = operand_vm(inst);
break;
+ case rv_codec_v_i_u:
+ dec->rd = operand_rd(inst);
+ dec->rs2 = operand_rs2(inst);
+ dec->imm = operand_vuimm(inst);
+ dec->vm = operand_vm(inst);
+ break;
case rv_codec_vror_vi:
dec->rd = operand_rd(inst);
dec->rs2 = operand_rs2(inst);
--
2.43.0
^ permalink raw reply related [flat|nested] 119+ messages in thread
* [PATCH 05/56] disas/riscv: Use extract helpers for operand fields
2026-08-09 22:34 [RFC PATCH 00/56] disas/riscv: Reorganize the disassembler Richard Henderson
` (3 preceding siblings ...)
2026-08-09 22:34 ` [PATCH 04/56] disas/riscv: Decode unsigned vector immediates as unsigned Richard Henderson
@ 2026-08-09 22:34 ` Richard Henderson
2026-08-11 19:58 ` Alistair
2026-08-09 22:34 ` [PATCH 06/56] disas/riscv: Move operand extractors earlier in file Richard Henderson
` (50 subsequent siblings)
55 siblings, 1 reply; 119+ messages in thread
From: Richard Henderson @ 2026-08-09 22:34 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-riscv, TANG Tiancheng, LIU Zhiwei
From: TANG Tiancheng <lyndra@linux.alibaba.com>
Replace shift-based operand extraction with extract32() and sextract32().
For signed immediates, use sextract32() on the field that carries the sign
bit and combine it with the remaining extract32() fields.
The RISC-V disassembler currently follows target/riscv/internals.h:
insn_len() and decodes only 16-bit or 32-bit instruction lengths, so the
converted fields are all in the low 32 bits of rv_inst.
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: TANG Tiancheng <lyndra@linux.alibaba.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Message-Id: <20260703-b4-disas-xthead-fix-riscv-next-v4-5-84c566330bc7@linux.alibaba.com>
---
disas/riscv.c | 214 +++++++++++++++++++++++++-------------------------
1 file changed, 107 insertions(+), 107 deletions(-)
diff --git a/disas/riscv.c b/disas/riscv.c
index 82b962dc71..2ba0a6a73a 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -4202,82 +4202,82 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
static uint32_t operand_rd(rv_inst inst)
{
- return (inst << 52) >> 59;
+ return extract32(inst, 7, 5);
}
static uint32_t operand_rs1(rv_inst inst)
{
- return (inst << 44) >> 59;
+ return extract32(inst, 15, 5);
}
static uint32_t operand_rs2(rv_inst inst)
{
- return (inst << 39) >> 59;
+ return extract32(inst, 20, 5);
}
static uint32_t operand_rs3(rv_inst inst)
{
- return (inst << 32) >> 59;
+ return extract32(inst, 27, 5);
}
static uint32_t operand_aq(rv_inst inst)
{
- return (inst << 37) >> 63;
+ return extract32(inst, 26, 1);
}
static uint32_t operand_rl(rv_inst inst)
{
- return (inst << 38) >> 63;
+ return extract32(inst, 25, 1);
}
static uint32_t operand_pred(rv_inst inst)
{
- return (inst << 36) >> 60;
+ return extract32(inst, 24, 4);
}
static uint32_t operand_succ(rv_inst inst)
{
- return (inst << 40) >> 60;
+ return extract32(inst, 20, 4);
}
static uint32_t operand_rm(rv_inst inst)
{
- return (inst << 49) >> 61;
+ return extract32(inst, 12, 3);
}
static uint32_t operand_shamt5(rv_inst inst)
{
- return (inst << 39) >> 59;
+ return extract32(inst, 20, 5);
}
static uint32_t operand_shamt6(rv_inst inst)
{
- return (inst << 38) >> 58;
+ return extract32(inst, 20, 6);
}
static uint32_t operand_shamt7(rv_inst inst)
{
- return (inst << 37) >> 57;
+ return extract32(inst, 20, 7);
}
static uint32_t operand_crdq(rv_inst inst)
{
- return (inst << 59) >> 61;
+ return extract32(inst, 2, 3);
}
static uint32_t operand_crs1q(rv_inst inst)
{
- return (inst << 54) >> 61;
+ return extract32(inst, 7, 3);
}
static uint32_t operand_crs1rdq(rv_inst inst)
{
- return (inst << 54) >> 61;
+ return extract32(inst, 7, 3);
}
static uint32_t operand_crs2q(rv_inst inst)
{
- return (inst << 59) >> 61;
+ return extract32(inst, 2, 3);
}
static uint32_t calculate_xreg(uint32_t sreg)
@@ -4287,80 +4287,80 @@ static uint32_t calculate_xreg(uint32_t sreg)
static uint32_t operand_sreg1(rv_inst inst)
{
- return calculate_xreg((inst << 54) >> 61);
+ return calculate_xreg(extract32(inst, 7, 3));
}
static uint32_t operand_sreg2(rv_inst inst)
{
- return calculate_xreg((inst << 59) >> 61);
+ return calculate_xreg(extract32(inst, 2, 3));
}
static uint32_t operand_crd(rv_inst inst)
{
- return (inst << 52) >> 59;
+ return extract32(inst, 7, 5);
}
static uint32_t operand_crs1(rv_inst inst)
{
- return (inst << 52) >> 59;
+ return extract32(inst, 7, 5);
}
static uint32_t operand_crs1rd(rv_inst inst)
{
- return (inst << 52) >> 59;
+ return extract32(inst, 7, 5);
}
static uint32_t operand_crs2(rv_inst inst)
{
- return (inst << 57) >> 59;
+ return extract32(inst, 2, 5);
}
static uint32_t operand_cimmsh5(rv_inst inst)
{
- return (inst << 57) >> 59;
+ return extract32(inst, 2, 5);
}
static uint32_t operand_csr12(rv_inst inst)
{
- return (inst << 32) >> 52;
+ return extract32(inst, 20, 12);
}
static int32_t operand_imm12(rv_inst inst)
{
- return ((int64_t)inst << 32) >> 52;
+ return sextract32(inst, 20, 12);
}
static int32_t operand_imm20(rv_inst inst)
{
- return (((int64_t)inst << 32) >> 44) << 12;
+ return sextract32(inst, 12, 20) << 12;
}
static int32_t operand_jimm20(rv_inst inst)
{
- return (((int64_t)inst << 32) >> 63) << 20 |
- ((inst << 33) >> 54) << 1 |
- ((inst << 43) >> 63) << 11 |
- ((inst << 44) >> 56) << 12;
+ return sextract32(inst, 31, 1) << 20 |
+ extract32(inst, 21, 10) << 1 |
+ extract32(inst, 20, 1) << 11 |
+ extract32(inst, 12, 8) << 12;
}
static int32_t operand_simm12(rv_inst inst)
{
- return (((int64_t)inst << 32) >> 57) << 5 |
- (inst << 52) >> 59;
+ return sextract32(inst, 25, 7) << 5 |
+ extract32(inst, 7, 5);
}
static int32_t operand_sbimm12(rv_inst inst)
{
- return (((int64_t)inst << 32) >> 63) << 12 |
- ((inst << 33) >> 58) << 5 |
- ((inst << 52) >> 60) << 1 |
- ((inst << 56) >> 63) << 11;
+ return sextract32(inst, 31, 1) << 12 |
+ extract32(inst, 25, 6) << 5 |
+ extract32(inst, 8, 4) << 1 |
+ extract32(inst, 7, 1) << 11;
}
static uint32_t operand_cimmshl6(rv_inst inst, rv_isa isa)
{
- int imm = ((inst << 51) >> 63) << 5 |
- (inst << 57) >> 59;
+ int imm = extract32(inst, 12, 1) << 5 |
+ extract32(inst, 2, 5);
if (isa == rv128) {
imm = imm ? imm : 64;
}
@@ -4369,8 +4369,8 @@ static uint32_t operand_cimmshl6(rv_inst inst, rv_isa isa)
static uint32_t operand_cimmshr6(rv_inst inst, rv_isa isa)
{
- int imm = ((inst << 51) >> 63) << 5 |
- (inst << 57) >> 59;
+ int imm = extract32(inst, 12, 1) << 5 |
+ extract32(inst, 2, 5);
if (isa == rv128) {
imm = imm | (imm & 32) << 1;
imm = imm ? imm : 64;
@@ -4380,116 +4380,116 @@ static uint32_t operand_cimmshr6(rv_inst inst, rv_isa isa)
static int32_t operand_cimmi(rv_inst inst)
{
- return (((int64_t)inst << 51) >> 63) << 5 |
- (inst << 57) >> 59;
+ return sextract32(inst, 12, 1) << 5 |
+ extract32(inst, 2, 5);
}
static int32_t operand_cimmui(rv_inst inst)
{
- return (((int64_t)inst << 51) >> 63) << 17 |
- ((inst << 57) >> 59) << 12;
+ return sextract32(inst, 12, 1) << 17 |
+ extract32(inst, 2, 5) << 12;
}
static uint32_t operand_cimmlwsp(rv_inst inst)
{
- return ((inst << 51) >> 63) << 5 |
- ((inst << 57) >> 61) << 2 |
- ((inst << 60) >> 62) << 6;
+ return extract32(inst, 12, 1) << 5 |
+ extract32(inst, 4, 3) << 2 |
+ extract32(inst, 2, 2) << 6;
}
static uint32_t operand_cimmldsp(rv_inst inst)
{
- return ((inst << 51) >> 63) << 5 |
- ((inst << 57) >> 62) << 3 |
- ((inst << 59) >> 61) << 6;
+ return extract32(inst, 12, 1) << 5 |
+ extract32(inst, 5, 2) << 3 |
+ extract32(inst, 2, 3) << 6;
}
static uint32_t operand_cimmlqsp(rv_inst inst)
{
- return ((inst << 51) >> 63) << 5 |
- ((inst << 57) >> 63) << 4 |
- ((inst << 58) >> 60) << 6;
+ return extract32(inst, 12, 1) << 5 |
+ extract32(inst, 6, 1) << 4 |
+ extract32(inst, 2, 4) << 6;
}
static int32_t operand_cimm16sp(rv_inst inst)
{
- return (((int64_t)inst << 51) >> 63) << 9 |
- ((inst << 57) >> 63) << 4 |
- ((inst << 58) >> 63) << 6 |
- ((inst << 59) >> 62) << 7 |
- ((inst << 61) >> 63) << 5;
+ return sextract32(inst, 12, 1) << 9 |
+ extract32(inst, 6, 1) << 4 |
+ extract32(inst, 5, 1) << 6 |
+ extract32(inst, 3, 2) << 7 |
+ extract32(inst, 2, 1) << 5;
}
static int32_t operand_cimmj(rv_inst inst)
{
- return (((int64_t)inst << 51) >> 63) << 11 |
- ((inst << 52) >> 63) << 4 |
- ((inst << 53) >> 62) << 8 |
- ((inst << 55) >> 63) << 10 |
- ((inst << 56) >> 63) << 6 |
- ((inst << 57) >> 63) << 7 |
- ((inst << 58) >> 61) << 1 |
- ((inst << 61) >> 63) << 5;
+ return sextract32(inst, 12, 1) << 11 |
+ extract32(inst, 11, 1) << 4 |
+ extract32(inst, 9, 2) << 8 |
+ extract32(inst, 8, 1) << 10 |
+ extract32(inst, 7, 1) << 6 |
+ extract32(inst, 6, 1) << 7 |
+ extract32(inst, 3, 3) << 1 |
+ extract32(inst, 2, 1) << 5;
}
static int32_t operand_cimmb(rv_inst inst)
{
- return (((int64_t)inst << 51) >> 63) << 8 |
- ((inst << 52) >> 62) << 3 |
- ((inst << 57) >> 62) << 6 |
- ((inst << 59) >> 62) << 1 |
- ((inst << 61) >> 63) << 5;
+ return sextract32(inst, 12, 1) << 8 |
+ extract32(inst, 10, 2) << 3 |
+ extract32(inst, 5, 2) << 6 |
+ extract32(inst, 3, 2) << 1 |
+ extract32(inst, 2, 1) << 5;
}
static uint32_t operand_cimmswsp(rv_inst inst)
{
- return ((inst << 51) >> 60) << 2 |
- ((inst << 55) >> 62) << 6;
+ return extract32(inst, 9, 4) << 2 |
+ extract32(inst, 7, 2) << 6;
}
static uint32_t operand_cimmsdsp(rv_inst inst)
{
- return ((inst << 51) >> 61) << 3 |
- ((inst << 54) >> 61) << 6;
+ return extract32(inst, 10, 3) << 3 |
+ extract32(inst, 7, 3) << 6;
}
static uint32_t operand_cimmsqsp(rv_inst inst)
{
- return ((inst << 51) >> 62) << 4 |
- ((inst << 53) >> 60) << 6;
+ return extract32(inst, 11, 2) << 4 |
+ extract32(inst, 7, 4) << 6;
}
static uint32_t operand_cimm4spn(rv_inst inst)
{
- return ((inst << 51) >> 62) << 4 |
- ((inst << 53) >> 60) << 6 |
- ((inst << 57) >> 63) << 2 |
- ((inst << 58) >> 63) << 3;
+ return extract32(inst, 11, 2) << 4 |
+ extract32(inst, 7, 4) << 6 |
+ extract32(inst, 6, 1) << 2 |
+ extract32(inst, 5, 1) << 3;
}
static uint32_t operand_cimmw(rv_inst inst)
{
- return ((inst << 51) >> 61) << 3 |
- ((inst << 57) >> 63) << 2 |
- ((inst << 58) >> 63) << 6;
+ return extract32(inst, 10, 3) << 3 |
+ extract32(inst, 6, 1) << 2 |
+ extract32(inst, 5, 1) << 6;
}
static uint32_t operand_cimmd(rv_inst inst)
{
- return ((inst << 51) >> 61) << 3 |
- ((inst << 57) >> 62) << 6;
+ return extract32(inst, 10, 3) << 3 |
+ extract32(inst, 5, 2) << 6;
}
static uint32_t operand_cimmq(rv_inst inst)
{
- return ((inst << 51) >> 62) << 4 |
- ((inst << 53) >> 63) << 8 |
- ((inst << 57) >> 62) << 6;
+ return extract32(inst, 11, 2) << 4 |
+ extract32(inst, 10, 1) << 8 |
+ extract32(inst, 5, 2) << 6;
}
static int32_t operand_vimm(rv_inst inst)
{
- return (int64_t)(inst << 44) >> 59;
+ return sextract32(inst, 15, 5);
}
static uint32_t operand_vuimm(rv_inst inst)
@@ -4499,54 +4499,54 @@ static uint32_t operand_vuimm(rv_inst inst)
static uint32_t operand_vzimm11(rv_inst inst)
{
- return (inst << 33) >> 53;
+ return extract32(inst, 20, 11);
}
static uint32_t operand_vzimm10(rv_inst inst)
{
- return (inst << 34) >> 54;
+ return extract32(inst, 20, 10);
}
static uint32_t operand_vzimm6(rv_inst inst)
{
- return ((inst << 37) >> 63) << 5 |
- ((inst << 44) >> 59);
+ return extract32(inst, 26, 1) << 5 |
+ extract32(inst, 15, 5);
}
static uint32_t operand_bs(rv_inst inst)
{
- return (inst << 32) >> 62;
+ return extract32(inst, 30, 2);
}
static uint32_t operand_rnum(rv_inst inst)
{
- return (inst << 40) >> 60;
+ return extract32(inst, 20, 4);
}
static uint32_t operand_vm(rv_inst inst)
{
- return (inst << 38) >> 63;
+ return extract32(inst, 25, 1);
}
static uint32_t operand_uimm_c_lb(rv_inst inst)
{
- return (((inst << 58) >> 63) << 1) |
- ((inst << 57) >> 63);
+ return extract32(inst, 5, 1) << 1 |
+ extract32(inst, 6, 1);
}
static uint32_t operand_uimm_c_lh(rv_inst inst)
{
- return (((inst << 58) >> 63) << 1);
+ return extract32(inst, 5, 1) << 1;
}
static uint32_t operand_zcmp_spimm(rv_inst inst)
{
- return ((inst << 60) >> 62) << 4;
+ return extract32(inst, 2, 2) << 4;
}
static uint32_t operand_zcmp_rlist(rv_inst inst)
{
- return ((inst << 56) >> 60);
+ return extract32(inst, 4, 4);
}
static uint32_t operand_imm6(rv_inst inst)
@@ -4556,17 +4556,17 @@ static uint32_t operand_imm6(rv_inst inst)
static uint32_t operand_imm2(rv_inst inst)
{
- return (inst << 37) >> 62;
+ return extract32(inst, 25, 2);
}
static uint32_t operand_immh(rv_inst inst)
{
- return (inst << 32) >> 58;
+ return extract32(inst, 26, 6);
}
static uint32_t operand_imml(rv_inst inst)
{
- return (inst << 38) >> 58;
+ return extract32(inst, 20, 6);
}
static uint32_t calculate_stack_adj(rv_isa isa, uint32_t rlist, uint32_t spimm)
@@ -4585,12 +4585,12 @@ static uint32_t operand_zcmp_stack_adj(rv_inst inst, rv_isa isa)
static uint32_t operand_tbl_index(rv_inst inst)
{
- return ((inst << 54) >> 56);
+ return extract32(inst, 2, 8);
}
static uint32_t operand_lpl(rv_inst inst)
{
- return inst >> 12;
+ return extract32(inst, 12, 20);
}
/* decode operands */
--
2.43.0
^ permalink raw reply related [flat|nested] 119+ messages in thread
* [PATCH 06/56] disas/riscv: Move operand extractors earlier in file
2026-08-09 22:34 [RFC PATCH 00/56] disas/riscv: Reorganize the disassembler Richard Henderson
` (4 preceding siblings ...)
2026-08-09 22:34 ` [PATCH 05/56] disas/riscv: Use extract helpers for operand fields Richard Henderson
@ 2026-08-09 22:34 ` Richard Henderson
2026-08-11 19:59 ` Alistair
2026-08-09 22:34 ` [PATCH 07/56] disas/riscv: Reduce rv_insn to uint32_t Richard Henderson
` (49 subsequent siblings)
55 siblings, 1 reply; 119+ messages in thread
From: Richard Henderson @ 2026-08-09 22:34 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-riscv
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
disas/riscv.c | 790 +++++++++++++++++++++++++-------------------------
1 file changed, 395 insertions(+), 395 deletions(-)
diff --git a/disas/riscv.c b/disas/riscv.c
index 2ba0a6a73a..e3fbc26626 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -1259,6 +1259,401 @@ static const rv_comp_data rvcp_fsgnjx_q[] = {
{ rv_op_illegal, NULL }
};
+/* operand extractors */
+
+static uint32_t operand_rd(rv_inst inst)
+{
+ return extract32(inst, 7, 5);
+}
+
+static uint32_t operand_rs1(rv_inst inst)
+{
+ return extract32(inst, 15, 5);
+}
+
+static uint32_t operand_rs2(rv_inst inst)
+{
+ return extract32(inst, 20, 5);
+}
+
+static uint32_t operand_rs3(rv_inst inst)
+{
+ return extract32(inst, 27, 5);
+}
+
+static uint32_t operand_aq(rv_inst inst)
+{
+ return extract32(inst, 26, 1);
+}
+
+static uint32_t operand_rl(rv_inst inst)
+{
+ return extract32(inst, 25, 1);
+}
+
+static uint32_t operand_pred(rv_inst inst)
+{
+ return extract32(inst, 24, 4);
+}
+
+static uint32_t operand_succ(rv_inst inst)
+{
+ return extract32(inst, 20, 4);
+}
+
+static uint32_t operand_rm(rv_inst inst)
+{
+ return extract32(inst, 12, 3);
+}
+
+static uint32_t operand_shamt5(rv_inst inst)
+{
+ return extract32(inst, 20, 5);
+}
+
+static uint32_t operand_shamt6(rv_inst inst)
+{
+ return extract32(inst, 20, 6);
+}
+
+static uint32_t operand_shamt7(rv_inst inst)
+{
+ return extract32(inst, 20, 7);
+}
+
+static uint32_t operand_crdq(rv_inst inst)
+{
+ return extract32(inst, 2, 3);
+}
+
+static uint32_t operand_crs1q(rv_inst inst)
+{
+ return extract32(inst, 7, 3);
+}
+
+static uint32_t operand_crs1rdq(rv_inst inst)
+{
+ return extract32(inst, 7, 3);
+}
+
+static uint32_t operand_crs2q(rv_inst inst)
+{
+ return extract32(inst, 2, 3);
+}
+
+static uint32_t calculate_xreg(uint32_t sreg)
+{
+ return sreg < 2 ? sreg + 8 : sreg + 16;
+}
+
+static uint32_t operand_sreg1(rv_inst inst)
+{
+ return calculate_xreg(extract32(inst, 7, 3));
+}
+
+static uint32_t operand_sreg2(rv_inst inst)
+{
+ return calculate_xreg(extract32(inst, 2, 3));
+}
+
+static uint32_t operand_crd(rv_inst inst)
+{
+ return extract32(inst, 7, 5);
+}
+
+static uint32_t operand_crs1(rv_inst inst)
+{
+ return extract32(inst, 7, 5);
+}
+
+static uint32_t operand_crs1rd(rv_inst inst)
+{
+ return extract32(inst, 7, 5);
+}
+
+static uint32_t operand_crs2(rv_inst inst)
+{
+ return extract32(inst, 2, 5);
+}
+
+static uint32_t operand_cimmsh5(rv_inst inst)
+{
+ return extract32(inst, 2, 5);
+}
+
+static uint32_t operand_csr12(rv_inst inst)
+{
+ return extract32(inst, 20, 12);
+}
+
+static int32_t operand_imm12(rv_inst inst)
+{
+ return sextract32(inst, 20, 12);
+}
+
+static int32_t operand_imm20(rv_inst inst)
+{
+ return sextract32(inst, 12, 20) << 12;
+}
+
+static int32_t operand_jimm20(rv_inst inst)
+{
+ return sextract32(inst, 31, 1) << 20 |
+ extract32(inst, 21, 10) << 1 |
+ extract32(inst, 20, 1) << 11 |
+ extract32(inst, 12, 8) << 12;
+}
+
+static int32_t operand_simm12(rv_inst inst)
+{
+ return sextract32(inst, 25, 7) << 5 |
+ extract32(inst, 7, 5);
+}
+
+static int32_t operand_sbimm12(rv_inst inst)
+{
+ return sextract32(inst, 31, 1) << 12 |
+ extract32(inst, 25, 6) << 5 |
+ extract32(inst, 8, 4) << 1 |
+ extract32(inst, 7, 1) << 11;
+}
+
+static uint32_t operand_cimmshl6(rv_inst inst, rv_isa isa)
+{
+ int imm = extract32(inst, 12, 1) << 5 |
+ extract32(inst, 2, 5);
+ if (isa == rv128) {
+ imm = imm ? imm : 64;
+ }
+ return imm;
+}
+
+static uint32_t operand_cimmshr6(rv_inst inst, rv_isa isa)
+{
+ int imm = extract32(inst, 12, 1) << 5 |
+ extract32(inst, 2, 5);
+ if (isa == rv128) {
+ imm = imm | (imm & 32) << 1;
+ imm = imm ? imm : 64;
+ }
+ return imm;
+}
+
+static int32_t operand_cimmi(rv_inst inst)
+{
+ return sextract32(inst, 12, 1) << 5 |
+ extract32(inst, 2, 5);
+}
+
+static int32_t operand_cimmui(rv_inst inst)
+{
+ return sextract32(inst, 12, 1) << 17 |
+ extract32(inst, 2, 5) << 12;
+}
+
+static uint32_t operand_cimmlwsp(rv_inst inst)
+{
+ return extract32(inst, 12, 1) << 5 |
+ extract32(inst, 4, 3) << 2 |
+ extract32(inst, 2, 2) << 6;
+}
+
+static uint32_t operand_cimmldsp(rv_inst inst)
+{
+ return extract32(inst, 12, 1) << 5 |
+ extract32(inst, 5, 2) << 3 |
+ extract32(inst, 2, 3) << 6;
+}
+
+static uint32_t operand_cimmlqsp(rv_inst inst)
+{
+ return extract32(inst, 12, 1) << 5 |
+ extract32(inst, 6, 1) << 4 |
+ extract32(inst, 2, 4) << 6;
+}
+
+static int32_t operand_cimm16sp(rv_inst inst)
+{
+ return sextract32(inst, 12, 1) << 9 |
+ extract32(inst, 6, 1) << 4 |
+ extract32(inst, 5, 1) << 6 |
+ extract32(inst, 3, 2) << 7 |
+ extract32(inst, 2, 1) << 5;
+}
+
+static int32_t operand_cimmj(rv_inst inst)
+{
+ return sextract32(inst, 12, 1) << 11 |
+ extract32(inst, 11, 1) << 4 |
+ extract32(inst, 9, 2) << 8 |
+ extract32(inst, 8, 1) << 10 |
+ extract32(inst, 7, 1) << 6 |
+ extract32(inst, 6, 1) << 7 |
+ extract32(inst, 3, 3) << 1 |
+ extract32(inst, 2, 1) << 5;
+}
+
+static int32_t operand_cimmb(rv_inst inst)
+{
+ return sextract32(inst, 12, 1) << 8 |
+ extract32(inst, 10, 2) << 3 |
+ extract32(inst, 5, 2) << 6 |
+ extract32(inst, 3, 2) << 1 |
+ extract32(inst, 2, 1) << 5;
+}
+
+static uint32_t operand_cimmswsp(rv_inst inst)
+{
+ return extract32(inst, 9, 4) << 2 |
+ extract32(inst, 7, 2) << 6;
+}
+
+static uint32_t operand_cimmsdsp(rv_inst inst)
+{
+ return extract32(inst, 10, 3) << 3 |
+ extract32(inst, 7, 3) << 6;
+}
+
+static uint32_t operand_cimmsqsp(rv_inst inst)
+{
+ return extract32(inst, 11, 2) << 4 |
+ extract32(inst, 7, 4) << 6;
+}
+
+static uint32_t operand_cimm4spn(rv_inst inst)
+{
+ return extract32(inst, 11, 2) << 4 |
+ extract32(inst, 7, 4) << 6 |
+ extract32(inst, 6, 1) << 2 |
+ extract32(inst, 5, 1) << 3;
+}
+
+static uint32_t operand_cimmw(rv_inst inst)
+{
+ return extract32(inst, 10, 3) << 3 |
+ extract32(inst, 6, 1) << 2 |
+ extract32(inst, 5, 1) << 6;
+}
+
+static uint32_t operand_cimmd(rv_inst inst)
+{
+ return extract32(inst, 10, 3) << 3 |
+ extract32(inst, 5, 2) << 6;
+}
+
+static uint32_t operand_cimmq(rv_inst inst)
+{
+ return extract32(inst, 11, 2) << 4 |
+ extract32(inst, 10, 1) << 8 |
+ extract32(inst, 5, 2) << 6;
+}
+
+static int32_t operand_vimm(rv_inst inst)
+{
+ return sextract32(inst, 15, 5);
+}
+
+static uint32_t operand_vuimm(rv_inst inst)
+{
+ return extract32(inst, 15, 5);
+}
+
+static uint32_t operand_vzimm11(rv_inst inst)
+{
+ return extract32(inst, 20, 11);
+}
+
+static uint32_t operand_vzimm10(rv_inst inst)
+{
+ return extract32(inst, 20, 10);
+}
+
+static uint32_t operand_vzimm6(rv_inst inst)
+{
+ return extract32(inst, 26, 1) << 5 |
+ extract32(inst, 15, 5);
+}
+
+static uint32_t operand_bs(rv_inst inst)
+{
+ return extract32(inst, 30, 2);
+}
+
+static uint32_t operand_rnum(rv_inst inst)
+{
+ return extract32(inst, 20, 4);
+}
+
+static uint32_t operand_vm(rv_inst inst)
+{
+ return extract32(inst, 25, 1);
+}
+
+static uint32_t operand_uimm_c_lb(rv_inst inst)
+{
+ return extract32(inst, 5, 1) << 1 |
+ extract32(inst, 6, 1);
+}
+
+static uint32_t operand_uimm_c_lh(rv_inst inst)
+{
+ return extract32(inst, 5, 1) << 1;
+}
+
+static uint32_t operand_zcmp_spimm(rv_inst inst)
+{
+ return extract32(inst, 2, 2) << 4;
+}
+
+static uint32_t operand_zcmp_rlist(rv_inst inst)
+{
+ return extract32(inst, 4, 4);
+}
+
+static uint32_t operand_imm6(rv_inst inst)
+{
+ return extract32(inst, 20, 6);
+}
+
+static uint32_t operand_imm2(rv_inst inst)
+{
+ return extract32(inst, 25, 2);
+}
+
+static uint32_t operand_immh(rv_inst inst)
+{
+ return extract32(inst, 26, 6);
+}
+
+static uint32_t operand_imml(rv_inst inst)
+{
+ return extract32(inst, 20, 6);
+}
+
+static uint32_t calculate_stack_adj(rv_isa isa, uint32_t rlist, uint32_t spimm)
+{
+ int xlen_bytes_log2 = isa == rv64 ? 3 : 2;
+ int regs = rlist == 15 ? 13 : rlist - 3;
+ uint32_t stack_adj_base = ROUND_UP(regs << xlen_bytes_log2, 16);
+ return stack_adj_base + spimm;
+}
+
+static uint32_t operand_zcmp_stack_adj(rv_inst inst, rv_isa isa)
+{
+ return calculate_stack_adj(isa, operand_zcmp_rlist(inst),
+ operand_zcmp_spimm(inst));
+}
+
+static uint32_t operand_tbl_index(rv_inst inst)
+{
+ return extract32(inst, 2, 8);
+}
+
+static uint32_t operand_lpl(rv_inst inst)
+{
+ return extract32(inst, 12, 20);
+}
+
/* instruction metadata */
const rv_opcode_data rvi_opcode_data[] = {
@@ -4198,401 +4593,6 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
dec->op = op;
}
-/* operand extractors */
-
-static uint32_t operand_rd(rv_inst inst)
-{
- return extract32(inst, 7, 5);
-}
-
-static uint32_t operand_rs1(rv_inst inst)
-{
- return extract32(inst, 15, 5);
-}
-
-static uint32_t operand_rs2(rv_inst inst)
-{
- return extract32(inst, 20, 5);
-}
-
-static uint32_t operand_rs3(rv_inst inst)
-{
- return extract32(inst, 27, 5);
-}
-
-static uint32_t operand_aq(rv_inst inst)
-{
- return extract32(inst, 26, 1);
-}
-
-static uint32_t operand_rl(rv_inst inst)
-{
- return extract32(inst, 25, 1);
-}
-
-static uint32_t operand_pred(rv_inst inst)
-{
- return extract32(inst, 24, 4);
-}
-
-static uint32_t operand_succ(rv_inst inst)
-{
- return extract32(inst, 20, 4);
-}
-
-static uint32_t operand_rm(rv_inst inst)
-{
- return extract32(inst, 12, 3);
-}
-
-static uint32_t operand_shamt5(rv_inst inst)
-{
- return extract32(inst, 20, 5);
-}
-
-static uint32_t operand_shamt6(rv_inst inst)
-{
- return extract32(inst, 20, 6);
-}
-
-static uint32_t operand_shamt7(rv_inst inst)
-{
- return extract32(inst, 20, 7);
-}
-
-static uint32_t operand_crdq(rv_inst inst)
-{
- return extract32(inst, 2, 3);
-}
-
-static uint32_t operand_crs1q(rv_inst inst)
-{
- return extract32(inst, 7, 3);
-}
-
-static uint32_t operand_crs1rdq(rv_inst inst)
-{
- return extract32(inst, 7, 3);
-}
-
-static uint32_t operand_crs2q(rv_inst inst)
-{
- return extract32(inst, 2, 3);
-}
-
-static uint32_t calculate_xreg(uint32_t sreg)
-{
- return sreg < 2 ? sreg + 8 : sreg + 16;
-}
-
-static uint32_t operand_sreg1(rv_inst inst)
-{
- return calculate_xreg(extract32(inst, 7, 3));
-}
-
-static uint32_t operand_sreg2(rv_inst inst)
-{
- return calculate_xreg(extract32(inst, 2, 3));
-}
-
-static uint32_t operand_crd(rv_inst inst)
-{
- return extract32(inst, 7, 5);
-}
-
-static uint32_t operand_crs1(rv_inst inst)
-{
- return extract32(inst, 7, 5);
-}
-
-static uint32_t operand_crs1rd(rv_inst inst)
-{
- return extract32(inst, 7, 5);
-}
-
-static uint32_t operand_crs2(rv_inst inst)
-{
- return extract32(inst, 2, 5);
-}
-
-static uint32_t operand_cimmsh5(rv_inst inst)
-{
- return extract32(inst, 2, 5);
-}
-
-static uint32_t operand_csr12(rv_inst inst)
-{
- return extract32(inst, 20, 12);
-}
-
-static int32_t operand_imm12(rv_inst inst)
-{
- return sextract32(inst, 20, 12);
-}
-
-static int32_t operand_imm20(rv_inst inst)
-{
- return sextract32(inst, 12, 20) << 12;
-}
-
-static int32_t operand_jimm20(rv_inst inst)
-{
- return sextract32(inst, 31, 1) << 20 |
- extract32(inst, 21, 10) << 1 |
- extract32(inst, 20, 1) << 11 |
- extract32(inst, 12, 8) << 12;
-}
-
-static int32_t operand_simm12(rv_inst inst)
-{
- return sextract32(inst, 25, 7) << 5 |
- extract32(inst, 7, 5);
-}
-
-static int32_t operand_sbimm12(rv_inst inst)
-{
- return sextract32(inst, 31, 1) << 12 |
- extract32(inst, 25, 6) << 5 |
- extract32(inst, 8, 4) << 1 |
- extract32(inst, 7, 1) << 11;
-}
-
-static uint32_t operand_cimmshl6(rv_inst inst, rv_isa isa)
-{
- int imm = extract32(inst, 12, 1) << 5 |
- extract32(inst, 2, 5);
- if (isa == rv128) {
- imm = imm ? imm : 64;
- }
- return imm;
-}
-
-static uint32_t operand_cimmshr6(rv_inst inst, rv_isa isa)
-{
- int imm = extract32(inst, 12, 1) << 5 |
- extract32(inst, 2, 5);
- if (isa == rv128) {
- imm = imm | (imm & 32) << 1;
- imm = imm ? imm : 64;
- }
- return imm;
-}
-
-static int32_t operand_cimmi(rv_inst inst)
-{
- return sextract32(inst, 12, 1) << 5 |
- extract32(inst, 2, 5);
-}
-
-static int32_t operand_cimmui(rv_inst inst)
-{
- return sextract32(inst, 12, 1) << 17 |
- extract32(inst, 2, 5) << 12;
-}
-
-static uint32_t operand_cimmlwsp(rv_inst inst)
-{
- return extract32(inst, 12, 1) << 5 |
- extract32(inst, 4, 3) << 2 |
- extract32(inst, 2, 2) << 6;
-}
-
-static uint32_t operand_cimmldsp(rv_inst inst)
-{
- return extract32(inst, 12, 1) << 5 |
- extract32(inst, 5, 2) << 3 |
- extract32(inst, 2, 3) << 6;
-}
-
-static uint32_t operand_cimmlqsp(rv_inst inst)
-{
- return extract32(inst, 12, 1) << 5 |
- extract32(inst, 6, 1) << 4 |
- extract32(inst, 2, 4) << 6;
-}
-
-static int32_t operand_cimm16sp(rv_inst inst)
-{
- return sextract32(inst, 12, 1) << 9 |
- extract32(inst, 6, 1) << 4 |
- extract32(inst, 5, 1) << 6 |
- extract32(inst, 3, 2) << 7 |
- extract32(inst, 2, 1) << 5;
-}
-
-static int32_t operand_cimmj(rv_inst inst)
-{
- return sextract32(inst, 12, 1) << 11 |
- extract32(inst, 11, 1) << 4 |
- extract32(inst, 9, 2) << 8 |
- extract32(inst, 8, 1) << 10 |
- extract32(inst, 7, 1) << 6 |
- extract32(inst, 6, 1) << 7 |
- extract32(inst, 3, 3) << 1 |
- extract32(inst, 2, 1) << 5;
-}
-
-static int32_t operand_cimmb(rv_inst inst)
-{
- return sextract32(inst, 12, 1) << 8 |
- extract32(inst, 10, 2) << 3 |
- extract32(inst, 5, 2) << 6 |
- extract32(inst, 3, 2) << 1 |
- extract32(inst, 2, 1) << 5;
-}
-
-static uint32_t operand_cimmswsp(rv_inst inst)
-{
- return extract32(inst, 9, 4) << 2 |
- extract32(inst, 7, 2) << 6;
-}
-
-static uint32_t operand_cimmsdsp(rv_inst inst)
-{
- return extract32(inst, 10, 3) << 3 |
- extract32(inst, 7, 3) << 6;
-}
-
-static uint32_t operand_cimmsqsp(rv_inst inst)
-{
- return extract32(inst, 11, 2) << 4 |
- extract32(inst, 7, 4) << 6;
-}
-
-static uint32_t operand_cimm4spn(rv_inst inst)
-{
- return extract32(inst, 11, 2) << 4 |
- extract32(inst, 7, 4) << 6 |
- extract32(inst, 6, 1) << 2 |
- extract32(inst, 5, 1) << 3;
-}
-
-static uint32_t operand_cimmw(rv_inst inst)
-{
- return extract32(inst, 10, 3) << 3 |
- extract32(inst, 6, 1) << 2 |
- extract32(inst, 5, 1) << 6;
-}
-
-static uint32_t operand_cimmd(rv_inst inst)
-{
- return extract32(inst, 10, 3) << 3 |
- extract32(inst, 5, 2) << 6;
-}
-
-static uint32_t operand_cimmq(rv_inst inst)
-{
- return extract32(inst, 11, 2) << 4 |
- extract32(inst, 10, 1) << 8 |
- extract32(inst, 5, 2) << 6;
-}
-
-static int32_t operand_vimm(rv_inst inst)
-{
- return sextract32(inst, 15, 5);
-}
-
-static uint32_t operand_vuimm(rv_inst inst)
-{
- return extract32(inst, 15, 5);
-}
-
-static uint32_t operand_vzimm11(rv_inst inst)
-{
- return extract32(inst, 20, 11);
-}
-
-static uint32_t operand_vzimm10(rv_inst inst)
-{
- return extract32(inst, 20, 10);
-}
-
-static uint32_t operand_vzimm6(rv_inst inst)
-{
- return extract32(inst, 26, 1) << 5 |
- extract32(inst, 15, 5);
-}
-
-static uint32_t operand_bs(rv_inst inst)
-{
- return extract32(inst, 30, 2);
-}
-
-static uint32_t operand_rnum(rv_inst inst)
-{
- return extract32(inst, 20, 4);
-}
-
-static uint32_t operand_vm(rv_inst inst)
-{
- return extract32(inst, 25, 1);
-}
-
-static uint32_t operand_uimm_c_lb(rv_inst inst)
-{
- return extract32(inst, 5, 1) << 1 |
- extract32(inst, 6, 1);
-}
-
-static uint32_t operand_uimm_c_lh(rv_inst inst)
-{
- return extract32(inst, 5, 1) << 1;
-}
-
-static uint32_t operand_zcmp_spimm(rv_inst inst)
-{
- return extract32(inst, 2, 2) << 4;
-}
-
-static uint32_t operand_zcmp_rlist(rv_inst inst)
-{
- return extract32(inst, 4, 4);
-}
-
-static uint32_t operand_imm6(rv_inst inst)
-{
- return extract32(inst, 20, 6);
-}
-
-static uint32_t operand_imm2(rv_inst inst)
-{
- return extract32(inst, 25, 2);
-}
-
-static uint32_t operand_immh(rv_inst inst)
-{
- return extract32(inst, 26, 6);
-}
-
-static uint32_t operand_imml(rv_inst inst)
-{
- return extract32(inst, 20, 6);
-}
-
-static uint32_t calculate_stack_adj(rv_isa isa, uint32_t rlist, uint32_t spimm)
-{
- int xlen_bytes_log2 = isa == rv64 ? 3 : 2;
- int regs = rlist == 15 ? 13 : rlist - 3;
- uint32_t stack_adj_base = ROUND_UP(regs << xlen_bytes_log2, 16);
- return stack_adj_base + spimm;
-}
-
-static uint32_t operand_zcmp_stack_adj(rv_inst inst, rv_isa isa)
-{
- return calculate_stack_adj(isa, operand_zcmp_rlist(inst),
- operand_zcmp_spimm(inst));
-}
-
-static uint32_t operand_tbl_index(rv_inst inst)
-{
- return extract32(inst, 2, 8);
-}
-
-static uint32_t operand_lpl(rv_inst inst)
-{
- return extract32(inst, 12, 20);
-}
-
/* decode operands */
static void decode_inst_operands(rv_decode *dec, rv_isa isa)
--
2.43.0
^ permalink raw reply related [flat|nested] 119+ messages in thread
* [PATCH 07/56] disas/riscv: Reduce rv_insn to uint32_t
2026-08-09 22:34 [RFC PATCH 00/56] disas/riscv: Reorganize the disassembler Richard Henderson
` (5 preceding siblings ...)
2026-08-09 22:34 ` [PATCH 06/56] disas/riscv: Move operand extractors earlier in file Richard Henderson
@ 2026-08-09 22:34 ` Richard Henderson
2026-08-10 2:54 ` Philippe Mathieu-Daudé
2026-08-11 19:59 ` Alistair
2026-08-09 22:34 ` [PATCH 08/56] disas/riscv: Tidy dec initialization in disasm_inst Richard Henderson
` (48 subsequent siblings)
55 siblings, 2 replies; 119+ messages in thread
From: Richard Henderson @ 2026-08-09 22:34 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-riscv
Since 758dce9c98a, the only possible values for
instruction length are 2 and 4.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
disas/riscv.h | 2 +-
disas/riscv.c | 12 +++---------
2 files changed, 4 insertions(+), 10 deletions(-)
diff --git a/disas/riscv.h b/disas/riscv.h
index 91ada8b531..eabe193b4f 100644
--- a/disas/riscv.h
+++ b/disas/riscv.h
@@ -11,7 +11,7 @@
/* types */
-typedef uint64_t rv_inst;
+typedef uint32_t rv_inst;
typedef uint16_t rv_opcode;
/* enums */
diff --git a/disas/riscv.c b/disas/riscv.c
index e3fbc26626..012f90fce6 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -5491,10 +5491,8 @@ static GString *disasm_inst(rv_isa isa, uint64_t pc, rv_inst inst,
return format_inst(24, &dec);
}
-#define INST_FMT_2 "%04" PRIx64 " "
-#define INST_FMT_4 "%08" PRIx64 " "
-#define INST_FMT_6 "%012" PRIx64 " "
-#define INST_FMT_8 "%016" PRIx64 " "
+#define INST_FMT_2 "%04x "
+#define INST_FMT_4 "%08x "
static int
print_insn_riscv(bfd_vma memaddr, struct disassemble_info *info, rv_isa isa)
@@ -5530,12 +5528,8 @@ print_insn_riscv(bfd_vma memaddr, struct disassemble_info *info, rv_isa isa)
case 4:
(*info->fprintf_func)(info->stream, INST_FMT_4, inst);
break;
- case 6:
- (*info->fprintf_func)(info->stream, INST_FMT_6, inst);
- break;
default:
- (*info->fprintf_func)(info->stream, INST_FMT_8, inst);
- break;
+ g_assert_not_reached();
}
}
--
2.43.0
^ permalink raw reply related [flat|nested] 119+ messages in thread
* [PATCH 08/56] disas/riscv: Tidy dec initialization in disasm_inst
2026-08-09 22:34 [RFC PATCH 00/56] disas/riscv: Reorganize the disassembler Richard Henderson
` (6 preceding siblings ...)
2026-08-09 22:34 ` [PATCH 07/56] disas/riscv: Reduce rv_insn to uint32_t Richard Henderson
@ 2026-08-09 22:34 ` Richard Henderson
2026-08-10 2:54 ` Philippe Mathieu-Daudé
2026-08-11 20:00 ` Alistair
2026-08-09 22:34 ` [PATCH 09/56] disas/riscv: Pass rv_opcode_data pointer to decode_inst_operands Richard Henderson
` (47 subsequent siblings)
55 siblings, 2 replies; 119+ messages in thread
From: Richard Henderson @ 2026-08-09 22:34 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-riscv
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
disas/riscv.c | 9 +++++----
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/disas/riscv.c b/disas/riscv.c
index 012f90fce6..986dc6b752 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -5441,10 +5441,11 @@ static void decode_inst_decompress(rv_decode *dec, rv_isa isa)
static GString *disasm_inst(rv_isa isa, uint64_t pc, rv_inst inst,
const RISCVCPUConfig *cfg)
{
- rv_decode dec = { 0 };
- dec.pc = pc;
- dec.inst = inst;
- dec.cfg = cfg;
+ rv_decode dec = {
+ .pc = pc,
+ .inst = inst,
+ .cfg = cfg,
+ };
static const struct {
bool (*guard_func)(const RISCVCPUConfig *);
--
2.43.0
^ permalink raw reply related [flat|nested] 119+ messages in thread
* [PATCH 09/56] disas/riscv: Pass rv_opcode_data pointer to decode_inst_operands
2026-08-09 22:34 [RFC PATCH 00/56] disas/riscv: Reorganize the disassembler Richard Henderson
` (7 preceding siblings ...)
2026-08-09 22:34 ` [PATCH 08/56] disas/riscv: Tidy dec initialization in disasm_inst Richard Henderson
@ 2026-08-09 22:34 ` Richard Henderson
2026-08-11 20:02 ` Alistair
2026-08-09 22:34 ` [PATCH 10/56] disas/riscv: Pass rv_opcode_data pointer to/from decode_inst_decompress Richard Henderson
` (46 subsequent siblings)
55 siblings, 1 reply; 119+ messages in thread
From: Richard Henderson @ 2026-08-09 22:34 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-riscv
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
disas/riscv.c | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/disas/riscv.c b/disas/riscv.c
index 986dc6b752..af43940732 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -4595,11 +4595,12 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
/* decode operands */
-static void decode_inst_operands(rv_decode *dec, rv_isa isa)
+static void decode_inst_operands(rv_decode *dec, rv_isa isa,
+ const rv_opcode_data *op)
{
- const rv_opcode_data *opcode_data = dec->opcode_data;
rv_inst inst = dec->inst;
- dec->codec = opcode_data[dec->op].codec;
+
+ dec->codec = op->codec;
switch (dec->codec) {
case rv_codec_none:
dec->rd = dec->rs1 = dec->rs2 = rv_ireg_zero;
@@ -5468,6 +5469,8 @@ static GString *disasm_inst(rv_isa isa, uint64_t pc, rv_inst inst,
{ has_xlrbr_p, rv_xlrbr_opcode_data, decode_xlrbr },
};
+ const rv_opcode_data *op;
+
for (size_t i = 0; i < ARRAY_SIZE(decoders); i++) {
bool (*guard_func)(const RISCVCPUConfig *) = decoders[i].guard_func;
const rv_opcode_data *opcode_data = decoders[i].opcode_data;
@@ -5486,7 +5489,8 @@ static GString *disasm_inst(rv_isa isa, uint64_t pc, rv_inst inst,
dec.opcode_data = rvi_opcode_data;
}
- decode_inst_operands(&dec, isa);
+ op = &dec.opcode_data[dec.op];
+ decode_inst_operands(&dec, isa, op);
decode_inst_decompress(&dec, isa);
decode_inst_lift_pseudo(&dec);
return format_inst(24, &dec);
--
2.43.0
^ permalink raw reply related [flat|nested] 119+ messages in thread
* [PATCH 10/56] disas/riscv: Pass rv_opcode_data pointer to/from decode_inst_decompress
2026-08-09 22:34 [RFC PATCH 00/56] disas/riscv: Reorganize the disassembler Richard Henderson
` (8 preceding siblings ...)
2026-08-09 22:34 ` [PATCH 09/56] disas/riscv: Pass rv_opcode_data pointer to decode_inst_operands Richard Henderson
@ 2026-08-09 22:34 ` Richard Henderson
2026-08-11 20:04 ` Alistair
2026-08-09 22:35 ` [PATCH 11/56] disas/riscv: Pass rv_opcode_data pointer to/from decode_inst_lift_pseudo Richard Henderson
` (45 subsequent siblings)
55 siblings, 1 reply; 119+ messages in thread
From: Richard Henderson @ 2026-08-09 22:34 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-riscv
Unify 4 functions, sharing code.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
disas/riscv.c | 70 ++++++++++++++++-----------------------------------
1 file changed, 21 insertions(+), 49 deletions(-)
diff --git a/disas/riscv.c b/disas/riscv.c
index af43940732..47fae7316c 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -5377,64 +5377,36 @@ static void decode_inst_lift_pseudo(rv_decode *dec)
/* decompress instruction */
-static void decode_inst_decompress_rv32(rv_decode *dec)
+static const rv_opcode_data *decode_inst_decompress(rv_decode *dec, rv_isa isa,
+ const rv_opcode_data *op)
{
- const rv_opcode_data *opcode_data = dec->opcode_data;
- int decomp_op = opcode_data[dec->op].decomp_rv32;
- if (decomp_op != rv_op_illegal) {
- if ((opcode_data[dec->op].decomp_data & rvcd_imm_nz)
- && dec->imm == 0) {
- dec->op = rv_op_illegal;
- } else {
- dec->op = decomp_op;
- dec->codec = opcode_data[decomp_op].codec;
- }
- }
-}
+ int decomp_op;
-static void decode_inst_decompress_rv64(rv_decode *dec)
-{
- const rv_opcode_data *opcode_data = dec->opcode_data;
- int decomp_op = opcode_data[dec->op].decomp_rv64;
- if (decomp_op != rv_op_illegal) {
- if ((opcode_data[dec->op].decomp_data & rvcd_imm_nz)
- && dec->imm == 0) {
- dec->op = rv_op_illegal;
- } else {
- dec->op = decomp_op;
- dec->codec = opcode_data[decomp_op].codec;
- }
- }
-}
-
-static void decode_inst_decompress_rv128(rv_decode *dec)
-{
- const rv_opcode_data *opcode_data = dec->opcode_data;
- int decomp_op = opcode_data[dec->op].decomp_rv128;
- if (decomp_op != rv_op_illegal) {
- if ((opcode_data[dec->op].decomp_data & rvcd_imm_nz)
- && dec->imm == 0) {
- dec->op = rv_op_illegal;
- } else {
- dec->op = decomp_op;
- dec->codec = opcode_data[decomp_op].codec;
- }
- }
-}
-
-static void decode_inst_decompress(rv_decode *dec, rv_isa isa)
-{
switch (isa) {
case rv32:
- decode_inst_decompress_rv32(dec);
+ decomp_op = op->decomp_rv32;
break;
case rv64:
- decode_inst_decompress_rv64(dec);
+ decomp_op = op->decomp_rv64;
break;
case rv128:
- decode_inst_decompress_rv128(dec);
+ decomp_op = op->decomp_rv128;
break;
+ default:
+ g_assert_not_reached();
}
+
+ if (decomp_op != rv_op_illegal) {
+ if ((op->decomp_data & rvcd_imm_nz) && dec->imm == 0) {
+ dec->opcode_data = rvi_opcode_data;
+ dec->op = rv_op_illegal;
+ } else {
+ dec->op = decomp_op;
+ }
+ op = &dec->opcode_data[decomp_op];
+ dec->codec = op->codec;
+ }
+ return op;
}
/* disassemble instruction */
@@ -5491,7 +5463,7 @@ static GString *disasm_inst(rv_isa isa, uint64_t pc, rv_inst inst,
op = &dec.opcode_data[dec.op];
decode_inst_operands(&dec, isa, op);
- decode_inst_decompress(&dec, isa);
+ op = decode_inst_decompress(&dec, isa, op);
decode_inst_lift_pseudo(&dec);
return format_inst(24, &dec);
}
--
2.43.0
^ permalink raw reply related [flat|nested] 119+ messages in thread
* [PATCH 11/56] disas/riscv: Pass rv_opcode_data pointer to/from decode_inst_lift_pseudo
2026-08-09 22:34 [RFC PATCH 00/56] disas/riscv: Reorganize the disassembler Richard Henderson
` (9 preceding siblings ...)
2026-08-09 22:34 ` [PATCH 10/56] disas/riscv: Pass rv_opcode_data pointer to/from decode_inst_decompress Richard Henderson
@ 2026-08-09 22:35 ` Richard Henderson
2026-08-11 20:05 ` Alistair
2026-08-09 22:35 ` [PATCH 12/56] disas/riscv: Pass rv_opcode_data pointer to format_inst Richard Henderson
` (44 subsequent siblings)
55 siblings, 1 reply; 119+ messages in thread
From: Richard Henderson @ 2026-08-09 22:35 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-riscv
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
disas/riscv.c | 27 ++++++++++++++-------------
1 file changed, 14 insertions(+), 13 deletions(-)
diff --git a/disas/riscv.c b/disas/riscv.c
index 47fae7316c..0be2f07612 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -5358,21 +5358,22 @@ static GString *format_inst(size_t tab, rv_decode *dec)
/* lift instruction to pseudo-instruction */
-static void decode_inst_lift_pseudo(rv_decode *dec)
+static const rv_opcode_data *decode_inst_lift_pseudo(rv_decode *dec,
+ const rv_opcode_data *op)
{
- const rv_opcode_data *opcode_data = dec->opcode_data;
- const rv_comp_data *comp_data = opcode_data[dec->op].pseudo;
- if (!comp_data) {
- return;
- }
- while (comp_data->constraints) {
- if (check_constraints(dec, comp_data->constraints)) {
- dec->op = comp_data->op;
- dec->codec = opcode_data[dec->op].codec;
- return;
+ const rv_comp_data *comp_data = op->pseudo;
+ if (comp_data) {
+ while (comp_data->constraints) {
+ if (check_constraints(dec, comp_data->constraints)) {
+ dec->op = comp_data->op;
+ op = &dec->opcode_data[dec->op];
+ dec->codec = op->codec;
+ break;
+ }
+ comp_data++;
}
- comp_data++;
}
+ return op;
}
/* decompress instruction */
@@ -5464,7 +5465,7 @@ static GString *disasm_inst(rv_isa isa, uint64_t pc, rv_inst inst,
op = &dec.opcode_data[dec.op];
decode_inst_operands(&dec, isa, op);
op = decode_inst_decompress(&dec, isa, op);
- decode_inst_lift_pseudo(&dec);
+ op = decode_inst_lift_pseudo(&dec, op);
return format_inst(24, &dec);
}
--
2.43.0
^ permalink raw reply related [flat|nested] 119+ messages in thread
* [PATCH 12/56] disas/riscv: Pass rv_opcode_data pointer to format_inst
2026-08-09 22:34 [RFC PATCH 00/56] disas/riscv: Reorganize the disassembler Richard Henderson
` (10 preceding siblings ...)
2026-08-09 22:35 ` [PATCH 11/56] disas/riscv: Pass rv_opcode_data pointer to/from decode_inst_lift_pseudo Richard Henderson
@ 2026-08-09 22:35 ` Richard Henderson
2026-08-11 20:06 ` Alistair
2026-08-09 22:35 ` [PATCH 13/56] disas/riscv: Tidy disasm_inst main loop Richard Henderson
` (43 subsequent siblings)
55 siblings, 1 reply; 119+ messages in thread
From: Richard Henderson @ 2026-08-09 22:35 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-riscv
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
disas/riscv.c | 11 +++++------
1 file changed, 5 insertions(+), 6 deletions(-)
diff --git a/disas/riscv.c b/disas/riscv.c
index 0be2f07612..70ea41f125 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -5111,17 +5111,16 @@ static size_t inst_length(rv_inst inst)
/* format instruction */
-static GString *format_inst(size_t tab, rv_decode *dec)
+static GString *format_inst(size_t tab, rv_decode *dec,
+ const rv_opcode_data *op)
{
- const rv_opcode_data *opcode_data = dec->opcode_data;
GString *buf = g_string_sized_new(64);
- const char *fmt;
+ const char *fmt = op->format;
- fmt = opcode_data[dec->op].format;
while (*fmt) {
switch (*fmt) {
case 'O':
- g_string_append(buf, opcode_data[dec->op].name);
+ g_string_append(buf, op->name);
break;
case '(':
case ',':
@@ -5466,7 +5465,7 @@ static GString *disasm_inst(rv_isa isa, uint64_t pc, rv_inst inst,
decode_inst_operands(&dec, isa, op);
op = decode_inst_decompress(&dec, isa, op);
op = decode_inst_lift_pseudo(&dec, op);
- return format_inst(24, &dec);
+ return format_inst(24, &dec, op);
}
#define INST_FMT_2 "%04x "
--
2.43.0
^ permalink raw reply related [flat|nested] 119+ messages in thread
* [PATCH 13/56] disas/riscv: Tidy disasm_inst main loop
2026-08-09 22:34 [RFC PATCH 00/56] disas/riscv: Reorganize the disassembler Richard Henderson
` (11 preceding siblings ...)
2026-08-09 22:35 ` [PATCH 12/56] disas/riscv: Pass rv_opcode_data pointer to format_inst Richard Henderson
@ 2026-08-09 22:35 ` Richard Henderson
2026-08-11 20:08 ` Alistair
2026-08-09 22:35 ` [PATCH 14/56] disas/riscv: Set dec->opcode_data in decode function Richard Henderson
` (42 subsequent siblings)
55 siblings, 1 reply; 119+ messages in thread
From: Richard Henderson @ 2026-08-09 22:35 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-riscv
Unroll first iteration, so that always_true_p is not used,
Drop some local variables and use 'decoders' directly.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
disas/riscv.c | 63 +++++++++++++++++++++++++--------------------------
1 file changed, 31 insertions(+), 32 deletions(-)
diff --git a/disas/riscv.c b/disas/riscv.c
index 70ea41f125..9880b8de20 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -5419,41 +5419,40 @@ static GString *disasm_inst(rv_isa isa, uint64_t pc, rv_inst inst,
.inst = inst,
.cfg = cfg,
};
-
- static const struct {
- bool (*guard_func)(const RISCVCPUConfig *);
- const rv_opcode_data *opcode_data;
- void (*decode_func)(rv_decode *, rv_isa);
- } decoders[] = {
- { always_true_p, rvi_opcode_data, decode_inst_opcode },
- { has_xtheadba_p, xthead_opcode_data, decode_xtheadba },
- { has_xtheadbb_p, xthead_opcode_data, decode_xtheadbb },
- { has_xtheadbs_p, xthead_opcode_data, decode_xtheadbs },
- { has_xtheadcmo_p, xthead_opcode_data, decode_xtheadcmo },
- { has_xtheadcondmov_p, xthead_opcode_data, decode_xtheadcondmov },
- { has_xtheadfmemidx_p, xthead_opcode_data, decode_xtheadfmemidx },
- { has_xtheadfmv_p, xthead_opcode_data, decode_xtheadfmv },
- { has_xtheadmac_p, xthead_opcode_data, decode_xtheadmac },
- { has_xtheadmemidx_p, xthead_opcode_data, decode_xtheadmemidx },
- { has_xtheadmempair_p, xthead_opcode_data, decode_xtheadmempair },
- { has_xtheadsync_p, xthead_opcode_data, decode_xtheadsync },
- { has_XVentanaCondOps_p, ventana_opcode_data, decode_xventanacondops },
- { has_xlrbr_p, rv_xlrbr_opcode_data, decode_xlrbr },
- };
-
const rv_opcode_data *op;
- for (size_t i = 0; i < ARRAY_SIZE(decoders); i++) {
- bool (*guard_func)(const RISCVCPUConfig *) = decoders[i].guard_func;
- const rv_opcode_data *opcode_data = decoders[i].opcode_data;
- void (*decode_func)(rv_decode *, rv_isa) = decoders[i].decode_func;
+ dec.opcode_data = rvi_opcode_data;
+ decode_inst_opcode(&dec, isa);
- /* always_true_p don't dereference cfg */
- if (((i == 0) || cfg) && guard_func(cfg)) {
- dec.opcode_data = opcode_data;
- decode_func(&dec, isa);
- if (dec.op != rv_op_illegal)
- break;
+ if (dec.op == rv_op_illegal && cfg) {
+ static const struct {
+ bool (*guard_func)(const RISCVCPUConfig *);
+ const rv_opcode_data *opcode_data;
+ void (*decode_func)(rv_decode *, rv_isa);
+ } decoders[] = {
+ { has_xtheadba_p, xthead_opcode_data, decode_xtheadba },
+ { has_xtheadbb_p, xthead_opcode_data, decode_xtheadbb },
+ { has_xtheadbs_p, xthead_opcode_data, decode_xtheadbs },
+ { has_xtheadcmo_p, xthead_opcode_data, decode_xtheadcmo },
+ { has_xtheadcondmov_p, xthead_opcode_data, decode_xtheadcondmov },
+ { has_xtheadfmemidx_p, xthead_opcode_data, decode_xtheadfmemidx },
+ { has_xtheadfmv_p, xthead_opcode_data, decode_xtheadfmv },
+ { has_xtheadmac_p, xthead_opcode_data, decode_xtheadmac },
+ { has_xtheadmemidx_p, xthead_opcode_data, decode_xtheadmemidx },
+ { has_xtheadmempair_p, xthead_opcode_data, decode_xtheadmempair },
+ { has_xtheadsync_p, xthead_opcode_data, decode_xtheadsync },
+ { has_XVentanaCondOps_p, ventana_opcode_data, decode_xventanacondops },
+ { has_xlrbr_p, rv_xlrbr_opcode_data, decode_xlrbr },
+ };
+
+ for (size_t i = 0; i < ARRAY_SIZE(decoders); i++) {
+ if (decoders[i].guard_func(cfg)) {
+ dec.opcode_data = decoders[i].opcode_data;
+ decoders[i].decode_func(&dec, isa);
+ if (dec.op != rv_op_illegal) {
+ break;
+ }
+ }
}
}
--
2.43.0
^ permalink raw reply related [flat|nested] 119+ messages in thread
* [PATCH 14/56] disas/riscv: Set dec->opcode_data in decode function
2026-08-09 22:34 [RFC PATCH 00/56] disas/riscv: Reorganize the disassembler Richard Henderson
` (12 preceding siblings ...)
2026-08-09 22:35 ` [PATCH 13/56] disas/riscv: Tidy disasm_inst main loop Richard Henderson
@ 2026-08-09 22:35 ` Richard Henderson
2026-08-11 20:09 ` Alistair
2026-08-09 22:35 ` [PATCH 15/56] disas/riscv: Drop explicit zero of rv_opcode_data fields Richard Henderson
` (41 subsequent siblings)
55 siblings, 1 reply; 119+ messages in thread
From: Richard Henderson @ 2026-08-09 22:35 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-riscv
This allows each opcode table to be private to the decode file.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
disas/riscv-xlrbr.h | 2 --
disas/riscv-xthead.h | 2 --
disas/riscv-xventana.h | 2 --
disas/riscv-xlrbr.c | 4 +++-
disas/riscv-xthead.c | 13 ++++++++++++-
disas/riscv-xventana.c | 3 ++-
disas/riscv.c | 34 +++++++++++++++++-----------------
7 files changed, 34 insertions(+), 26 deletions(-)
diff --git a/disas/riscv-xlrbr.h b/disas/riscv-xlrbr.h
index 939a69ea6d..ebf3d4c133 100644
--- a/disas/riscv-xlrbr.h
+++ b/disas/riscv-xlrbr.h
@@ -12,8 +12,6 @@
#include "disas/riscv.h"
-extern const rv_opcode_data rv_xlrbr_opcode_data[];
-
void decode_xlrbr(rv_decode *, rv_isa);
#endif /* DISAS_RISCV_XLRBR_H */
diff --git a/disas/riscv-xthead.h b/disas/riscv-xthead.h
index fcd42746e7..0c65c8e0af 100644
--- a/disas/riscv-xthead.h
+++ b/disas/riscv-xthead.h
@@ -11,8 +11,6 @@
#include "disas/riscv.h"
-extern const rv_opcode_data xthead_opcode_data[];
-
void decode_xtheadba(rv_decode *, rv_isa);
void decode_xtheadbb(rv_decode *, rv_isa);
void decode_xtheadbs(rv_decode *, rv_isa);
diff --git a/disas/riscv-xventana.h b/disas/riscv-xventana.h
index 72be9ffa16..1006c3be00 100644
--- a/disas/riscv-xventana.h
+++ b/disas/riscv-xventana.h
@@ -11,8 +11,6 @@
#include "disas/riscv.h"
-extern const rv_opcode_data ventana_opcode_data[];
-
void decode_xventanacondops(rv_decode*, rv_isa);
#endif /* DISAS_RISCV_XVENTANA_H */
diff --git a/disas/riscv-xlrbr.c b/disas/riscv-xlrbr.c
index 57cb434523..f61028fce9 100644
--- a/disas/riscv-xlrbr.c
+++ b/disas/riscv-xlrbr.c
@@ -24,7 +24,7 @@ typedef enum {
rv_op_crc32c_d = 8,
} rv_xlrbr_op;
-const rv_opcode_data rv_xlrbr_opcode_data[] = {
+static const rv_opcode_data xlrbr_opcode_data[] = {
{ "illegal", rv_codec_illegal, rv_fmt_none, NULL, 0, 0, 0 },
{ "crc32.b", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
{ "crc32.h", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
@@ -75,5 +75,7 @@ void decode_xlrbr(rv_decode *dec, rv_isa isa)
}
break;
}
+
+ dec->opcode_data = xlrbr_opcode_data;
dec->op = op;
}
diff --git a/disas/riscv-xthead.c b/disas/riscv-xthead.c
index 2f2ddb8dd9..96f80bc8e5 100644
--- a/disas/riscv-xthead.c
+++ b/disas/riscv-xthead.c
@@ -127,7 +127,7 @@ typedef enum {
rv_op_th_sync_s,
} rv_xthead_op;
-const rv_opcode_data xthead_opcode_data[] = {
+static const rv_opcode_data xthead_opcode_data[] = {
{ "th.illegal", rv_codec_illegal, rv_fmt_none, NULL, 0, 0, 0 },
/* XTheadBa */
{ "th.addsl", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0, 0 },
@@ -272,6 +272,7 @@ void decode_xtheadba(rv_decode *dec, rv_isa isa)
break;
}
+ dec->opcode_data = xthead_opcode_data;
dec->op = op;
}
@@ -330,6 +331,7 @@ void decode_xtheadbb(rv_decode *dec, rv_isa isa)
break;
}
+ dec->opcode_data = xthead_opcode_data;
dec->op = op;
}
@@ -356,6 +358,7 @@ void decode_xtheadbs(rv_decode *dec, rv_isa isa)
break;
}
+ dec->opcode_data = xthead_opcode_data;
dec->op = op;
}
@@ -434,6 +437,7 @@ void decode_xtheadcmo(rv_decode *dec, rv_isa isa)
break;
}
+ dec->opcode_data = xthead_opcode_data;
dec->op = op;
}
@@ -461,6 +465,7 @@ void decode_xtheadcondmov(rv_decode *dec, rv_isa isa)
break;
}
+ dec->opcode_data = xthead_opcode_data;
dec->op = op;
}
@@ -498,6 +503,7 @@ void decode_xtheadfmemidx(rv_decode *dec, rv_isa isa)
break;
}
+ dec->opcode_data = xthead_opcode_data;
dec->op = op;
}
@@ -533,6 +539,7 @@ void decode_xtheadfmv(rv_decode *dec, rv_isa isa)
break;
}
+ dec->opcode_data = xthead_opcode_data;
dec->op = op;
}
@@ -564,6 +571,7 @@ void decode_xtheadmac(rv_decode *dec, rv_isa isa)
break;
}
+ dec->opcode_data = xthead_opcode_data;
dec->op = op;
}
@@ -638,6 +646,7 @@ void decode_xtheadmemidx(rv_decode *dec, rv_isa isa)
break;
}
+ dec->opcode_data = xthead_opcode_data;
dec->op = op;
}
@@ -672,6 +681,7 @@ void decode_xtheadmempair(rv_decode *dec, rv_isa isa)
break;
}
+ dec->opcode_data = xthead_opcode_data;
dec->op = op;
}
@@ -706,5 +716,6 @@ void decode_xtheadsync(rv_decode *dec, rv_isa isa)
break;
}
+ dec->opcode_data = xthead_opcode_data;
dec->op = op;
}
diff --git a/disas/riscv-xventana.c b/disas/riscv-xventana.c
index cd694f15f3..4539173d95 100644
--- a/disas/riscv-xventana.c
+++ b/disas/riscv-xventana.c
@@ -14,7 +14,7 @@ typedef enum {
ventana_op_vt_maskcn = 2,
} rv_ventana_op;
-const rv_opcode_data ventana_opcode_data[] = {
+static const rv_opcode_data ventana_opcode_data[] = {
{ "vt.illegal", rv_codec_illegal, rv_fmt_none, NULL, 0, 0, 0 },
{ "vt.maskc", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
{ "vt.maskcn", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
@@ -38,5 +38,6 @@ void decode_xventanacondops(rv_decode *dec, rv_isa isa)
break;
}
+ dec->opcode_data = ventana_opcode_data;
dec->op = op;
}
diff --git a/disas/riscv.c b/disas/riscv.c
index 9880b8de20..eb6d132a2c 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -1656,7 +1656,7 @@ static uint32_t operand_lpl(rv_inst inst)
/* instruction metadata */
-const rv_opcode_data rvi_opcode_data[] = {
+static const rv_opcode_data rvi_opcode_data[] = {
{ "illegal", rv_codec_illegal, rv_fmt_none, NULL, 0, 0, 0 },
{ "lui", rv_codec_u, rv_fmt_rd_uimm, NULL, 0, 0, 0 },
{ "auipc", rv_codec_u, rv_fmt_rd_uoffset, NULL, 0, 0, 0 },
@@ -2948,6 +2948,7 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
{
rv_inst inst = dec->inst;
rv_opcode op = rv_op_illegal;
+
switch ((inst >> 0) & 0b11) {
case 0:
switch ((inst >> 13) & 0b111) {
@@ -4590,6 +4591,8 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
}
break;
}
+
+ dec->opcode_data = rvi_opcode_data;
dec->op = op;
}
@@ -5421,33 +5424,30 @@ static GString *disasm_inst(rv_isa isa, uint64_t pc, rv_inst inst,
};
const rv_opcode_data *op;
- dec.opcode_data = rvi_opcode_data;
decode_inst_opcode(&dec, isa);
if (dec.op == rv_op_illegal && cfg) {
static const struct {
bool (*guard_func)(const RISCVCPUConfig *);
- const rv_opcode_data *opcode_data;
void (*decode_func)(rv_decode *, rv_isa);
} decoders[] = {
- { has_xtheadba_p, xthead_opcode_data, decode_xtheadba },
- { has_xtheadbb_p, xthead_opcode_data, decode_xtheadbb },
- { has_xtheadbs_p, xthead_opcode_data, decode_xtheadbs },
- { has_xtheadcmo_p, xthead_opcode_data, decode_xtheadcmo },
- { has_xtheadcondmov_p, xthead_opcode_data, decode_xtheadcondmov },
- { has_xtheadfmemidx_p, xthead_opcode_data, decode_xtheadfmemidx },
- { has_xtheadfmv_p, xthead_opcode_data, decode_xtheadfmv },
- { has_xtheadmac_p, xthead_opcode_data, decode_xtheadmac },
- { has_xtheadmemidx_p, xthead_opcode_data, decode_xtheadmemidx },
- { has_xtheadmempair_p, xthead_opcode_data, decode_xtheadmempair },
- { has_xtheadsync_p, xthead_opcode_data, decode_xtheadsync },
- { has_XVentanaCondOps_p, ventana_opcode_data, decode_xventanacondops },
- { has_xlrbr_p, rv_xlrbr_opcode_data, decode_xlrbr },
+ { has_xtheadba_p, decode_xtheadba },
+ { has_xtheadbb_p, decode_xtheadbb },
+ { has_xtheadbs_p, decode_xtheadbs },
+ { has_xtheadcmo_p, decode_xtheadcmo },
+ { has_xtheadcondmov_p, decode_xtheadcondmov },
+ { has_xtheadfmemidx_p, decode_xtheadfmemidx },
+ { has_xtheadfmv_p, decode_xtheadfmv },
+ { has_xtheadmac_p, decode_xtheadmac },
+ { has_xtheadmemidx_p, decode_xtheadmemidx },
+ { has_xtheadmempair_p, decode_xtheadmempair },
+ { has_xtheadsync_p, decode_xtheadsync },
+ { has_XVentanaCondOps_p, decode_xventanacondops },
+ { has_xlrbr_p, decode_xlrbr },
};
for (size_t i = 0; i < ARRAY_SIZE(decoders); i++) {
if (decoders[i].guard_func(cfg)) {
- dec.opcode_data = decoders[i].opcode_data;
decoders[i].decode_func(&dec, isa);
if (dec.op != rv_op_illegal) {
break;
--
2.43.0
^ permalink raw reply related [flat|nested] 119+ messages in thread
* [PATCH 15/56] disas/riscv: Drop explicit zero of rv_opcode_data fields
2026-08-09 22:34 [RFC PATCH 00/56] disas/riscv: Reorganize the disassembler Richard Henderson
` (13 preceding siblings ...)
2026-08-09 22:35 ` [PATCH 14/56] disas/riscv: Set dec->opcode_data in decode function Richard Henderson
@ 2026-08-09 22:35 ` Richard Henderson
2026-08-11 20:10 ` Alistair
2026-08-09 22:35 ` [PATCH 16/56] disas/riscv: Drop useless const in structures Richard Henderson
` (40 subsequent siblings)
55 siblings, 1 reply; 119+ messages in thread
From: Richard Henderson @ 2026-08-09 22:35 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-riscv
Mechanical
s/, NULL, 0, 0, 0 }/ }/
s/, 0, 0, 0 }/ }/
s/, NULL, 0, 0 }/ }/
s/, NULL, 0 }/ }/
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
disas/riscv-xlrbr.c | 18 +-
disas/riscv-xthead.c | 210 ++---
disas/riscv-xventana.c | 6 +-
disas/riscv.c | 1826 ++++++++++++++++++++--------------------
4 files changed, 1030 insertions(+), 1030 deletions(-)
diff --git a/disas/riscv-xlrbr.c b/disas/riscv-xlrbr.c
index f61028fce9..d0092e9edd 100644
--- a/disas/riscv-xlrbr.c
+++ b/disas/riscv-xlrbr.c
@@ -25,15 +25,15 @@ typedef enum {
} rv_xlrbr_op;
static const rv_opcode_data xlrbr_opcode_data[] = {
- { "illegal", rv_codec_illegal, rv_fmt_none, NULL, 0, 0, 0 },
- { "crc32.b", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
- { "crc32.h", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
- { "crc32.w", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
- { "crc32.d", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
- { "crc32c.b", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
- { "crc32c.h", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
- { "crc32c.w", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
- { "crc32c.d", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
+ { "illegal", rv_codec_illegal, rv_fmt_none },
+ { "crc32.b", rv_codec_r, rv_fmt_rd_rs1 },
+ { "crc32.h", rv_codec_r, rv_fmt_rd_rs1 },
+ { "crc32.w", rv_codec_r, rv_fmt_rd_rs1 },
+ { "crc32.d", rv_codec_r, rv_fmt_rd_rs1 },
+ { "crc32c.b", rv_codec_r, rv_fmt_rd_rs1 },
+ { "crc32c.h", rv_codec_r, rv_fmt_rd_rs1 },
+ { "crc32c.w", rv_codec_r, rv_fmt_rd_rs1 },
+ { "crc32c.d", rv_codec_r, rv_fmt_rd_rs1 },
};
void decode_xlrbr(rv_decode *dec, rv_isa isa)
diff --git a/disas/riscv-xthead.c b/disas/riscv-xthead.c
index 96f80bc8e5..757d6ff39f 100644
--- a/disas/riscv-xthead.c
+++ b/disas/riscv-xthead.c
@@ -128,122 +128,122 @@ typedef enum {
} rv_xthead_op;
static const rv_opcode_data xthead_opcode_data[] = {
- { "th.illegal", rv_codec_illegal, rv_fmt_none, NULL, 0, 0, 0 },
+ { "th.illegal", rv_codec_illegal, rv_fmt_none },
/* XTheadBa */
- { "th.addsl", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0, 0 },
+ { "th.addsl", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm },
/* XTheadBb */
- { "th.srri", rv_codec_r2_imm6, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
- { "th.srriw", rv_codec_r2_imm5, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
- { "th.ext", rv_codec_r2_immhl, rv_fmt_rd_rs1_immh_imml, NULL, 0, 0, 0 },
- { "th.extu", rv_codec_r2_immhl, rv_fmt_rd_rs1_immh_imml, NULL, 0, 0, 0 },
- { "th.ff0", rv_codec_r2, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
- { "th.ff1", rv_codec_r2, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
- { "th.rev", rv_codec_r2, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
- { "th.revw", rv_codec_r2, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
- { "th.tstnbz", rv_codec_r2, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
+ { "th.srri", rv_codec_r2_imm6, rv_fmt_rd_rs1_imm },
+ { "th.srriw", rv_codec_r2_imm5, rv_fmt_rd_rs1_imm },
+ { "th.ext", rv_codec_r2_immhl, rv_fmt_rd_rs1_immh_imml },
+ { "th.extu", rv_codec_r2_immhl, rv_fmt_rd_rs1_immh_imml },
+ { "th.ff0", rv_codec_r2, rv_fmt_rd_rs1 },
+ { "th.ff1", rv_codec_r2, rv_fmt_rd_rs1 },
+ { "th.rev", rv_codec_r2, rv_fmt_rd_rs1 },
+ { "th.revw", rv_codec_r2, rv_fmt_rd_rs1 },
+ { "th.tstnbz", rv_codec_r2, rv_fmt_rd_rs1 },
/* XTheadBs */
- { "th.tst", rv_codec_r2_imm6, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
+ { "th.tst", rv_codec_r2_imm6, rv_fmt_rd_rs1_imm },
/* XTheadCmo */
- { "th.dcache.call", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
- { "th.dcache.ciall", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
- { "th.dcache.iall", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
- { "th.dcache.cpa", rv_codec_r, rv_fmt_rs1, NULL, 0, 0, 0 },
- { "th.dcache.cipa", rv_codec_r, rv_fmt_rs1, NULL, 0, 0, 0 },
- { "th.dcache.ipa", rv_codec_r, rv_fmt_rs1, NULL, 0, 0, 0 },
- { "th.dcache.cva", rv_codec_r, rv_fmt_rs1, NULL, 0, 0, 0 },
- { "th.dcache.civa", rv_codec_r, rv_fmt_rs1, NULL, 0, 0, 0 },
- { "th.dcache.iva", rv_codec_r, rv_fmt_rs1, NULL, 0, 0, 0 },
- { "th.dcache.csw", rv_codec_r, rv_fmt_rs1, NULL, 0, 0, 0 },
- { "th.dcache.cisw", rv_codec_r, rv_fmt_rs1, NULL, 0, 0, 0 },
- { "th.dcache.isw", rv_codec_r, rv_fmt_rs1, NULL, 0, 0, 0 },
- { "th.dcache.cpal1", rv_codec_r, rv_fmt_rs1, NULL, 0, 0, 0 },
- { "th.dcache.cval1", rv_codec_r, rv_fmt_rs1, NULL, 0, 0, 0 },
- { "th.icache.iall", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
- { "th.icache.ialls", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
- { "th.icache.ipa", rv_codec_r, rv_fmt_rs1, NULL, 0, 0, 0 },
- { "th.icache.iva", rv_codec_r, rv_fmt_rs1, NULL, 0, 0, 0 },
- { "th.l2cache.call", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
- { "th.l2cache.ciall", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
- { "th.l2cache.iall", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
+ { "th.dcache.call", rv_codec_none, rv_fmt_none },
+ { "th.dcache.ciall", rv_codec_none, rv_fmt_none },
+ { "th.dcache.iall", rv_codec_none, rv_fmt_none },
+ { "th.dcache.cpa", rv_codec_r, rv_fmt_rs1 },
+ { "th.dcache.cipa", rv_codec_r, rv_fmt_rs1 },
+ { "th.dcache.ipa", rv_codec_r, rv_fmt_rs1 },
+ { "th.dcache.cva", rv_codec_r, rv_fmt_rs1 },
+ { "th.dcache.civa", rv_codec_r, rv_fmt_rs1 },
+ { "th.dcache.iva", rv_codec_r, rv_fmt_rs1 },
+ { "th.dcache.csw", rv_codec_r, rv_fmt_rs1 },
+ { "th.dcache.cisw", rv_codec_r, rv_fmt_rs1 },
+ { "th.dcache.isw", rv_codec_r, rv_fmt_rs1 },
+ { "th.dcache.cpal1", rv_codec_r, rv_fmt_rs1 },
+ { "th.dcache.cval1", rv_codec_r, rv_fmt_rs1 },
+ { "th.icache.iall", rv_codec_none, rv_fmt_none },
+ { "th.icache.ialls", rv_codec_none, rv_fmt_none },
+ { "th.icache.ipa", rv_codec_r, rv_fmt_rs1 },
+ { "th.icache.iva", rv_codec_r, rv_fmt_rs1 },
+ { "th.l2cache.call", rv_codec_none, rv_fmt_none },
+ { "th.l2cache.ciall", rv_codec_none, rv_fmt_none },
+ { "th.l2cache.iall", rv_codec_none, rv_fmt_none },
/* XTheadCondMov */
- { "th.mveqz", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
- { "th.mvnez", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "th.mveqz", rv_codec_r, rv_fmt_rd_rs1_rs2 },
+ { "th.mvnez", rv_codec_r, rv_fmt_rd_rs1_rs2 },
/* XTheadFMemIdx */
- { "th.flrd", rv_codec_r_imm2, rv_fmt_frd_rs1_rs2_imm, NULL, 0, 0, 0 },
- { "th.flrw", rv_codec_r_imm2, rv_fmt_frd_rs1_rs2_imm, NULL, 0, 0, 0 },
- { "th.flurd", rv_codec_r_imm2, rv_fmt_frd_rs1_rs2_imm, NULL, 0, 0, 0 },
- { "th.flurw", rv_codec_r_imm2, rv_fmt_frd_rs1_rs2_imm, NULL, 0, 0, 0 },
- { "th.fsrd", rv_codec_r_imm2, rv_fmt_frd_rs1_rs2_imm, NULL, 0, 0, 0 },
- { "th.fsrw", rv_codec_r_imm2, rv_fmt_frd_rs1_rs2_imm, NULL, 0, 0, 0 },
- { "th.fsurd", rv_codec_r_imm2, rv_fmt_frd_rs1_rs2_imm, NULL, 0, 0, 0 },
- { "th.fsurw", rv_codec_r_imm2, rv_fmt_frd_rs1_rs2_imm, NULL, 0, 0, 0 },
+ { "th.flrd", rv_codec_r_imm2, rv_fmt_frd_rs1_rs2_imm },
+ { "th.flrw", rv_codec_r_imm2, rv_fmt_frd_rs1_rs2_imm },
+ { "th.flurd", rv_codec_r_imm2, rv_fmt_frd_rs1_rs2_imm },
+ { "th.flurw", rv_codec_r_imm2, rv_fmt_frd_rs1_rs2_imm },
+ { "th.fsrd", rv_codec_r_imm2, rv_fmt_frd_rs1_rs2_imm },
+ { "th.fsrw", rv_codec_r_imm2, rv_fmt_frd_rs1_rs2_imm },
+ { "th.fsurd", rv_codec_r_imm2, rv_fmt_frd_rs1_rs2_imm },
+ { "th.fsurw", rv_codec_r_imm2, rv_fmt_frd_rs1_rs2_imm },
/* XTheadFmv */
- { "th.fmv.hw.x", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 },
- { "th.fmv.x.hw", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 },
+ { "th.fmv.hw.x", rv_codec_r, rv_fmt_rd_frs1 },
+ { "th.fmv.x.hw", rv_codec_r, rv_fmt_rd_frs1 },
/* XTheadMac */
- { "th.mula", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
- { "th.mulaw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
- { "th.mulah", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
- { "th.muls", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
- { "th.mulsw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
- { "th.mulsh", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "th.mula", rv_codec_r, rv_fmt_rd_rs1_rs2 },
+ { "th.mulaw", rv_codec_r, rv_fmt_rd_rs1_rs2 },
+ { "th.mulah", rv_codec_r, rv_fmt_rd_rs1_rs2 },
+ { "th.muls", rv_codec_r, rv_fmt_rd_rs1_rs2 },
+ { "th.mulsw", rv_codec_r, rv_fmt_rd_rs1_rs2 },
+ { "th.mulsh", rv_codec_r, rv_fmt_rd_rs1_rs2 },
/* XTheadMemIdx */
- { "th.lbia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr, NULL, 0, 0, 0 },
- { "th.lbib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml, NULL, 0, 0, 0 },
- { "th.lbuia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr, NULL, 0, 0, 0 },
- { "th.lbuib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr, NULL, 0, 0, 0 },
- { "th.lhia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr, NULL, 0, 0, 0 },
- { "th.lhib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr, NULL, 0, 0, 0 },
- { "th.lhuia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr, NULL, 0, 0, 0 },
- { "th.lhuib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr, NULL, 0, 0, 0 },
- { "th.lwia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr, NULL, 0, 0, 0 },
- { "th.lwib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr, NULL, 0, 0, 0 },
- { "th.lwuia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr, NULL, 0, 0, 0 },
- { "th.lwuib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr, NULL, 0, 0, 0 },
- { "th.ldia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr, NULL, 0, 0, 0 },
- { "th.ldib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr, NULL, 0, 0, 0 },
- { "th.sbia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr, NULL, 0, 0, 0 },
- { "th.sbib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr, NULL, 0, 0, 0 },
- { "th.shia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr, NULL, 0, 0, 0 },
- { "th.shib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr, NULL, 0, 0, 0 },
- { "th.swia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr, NULL, 0, 0, 0 },
- { "th.swib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr, NULL, 0, 0, 0 },
- { "th.sdia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr, NULL, 0, 0, 0 },
- { "th.sdib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr, NULL, 0, 0, 0 },
- { "th.lrb", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0, 0 },
- { "th.lrbu", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0, 0 },
- { "th.lrh", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0, 0 },
- { "th.lrhu", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0, 0 },
- { "th.lrw", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0, 0 },
- { "th.lrwu", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0, 0 },
- { "th.lrd", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0, 0 },
- { "th.srb", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0, 0 },
- { "th.srh", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0, 0 },
- { "th.srw", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0, 0 },
- { "th.srd", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0, 0 },
- { "th.lurb", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0, 0 },
- { "th.lurbu", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0, 0 },
- { "th.lurh", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0, 0 },
- { "th.lurhu", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0, 0 },
- { "th.lurw", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0, 0 },
- { "th.lurwu", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0, 0 },
- { "th.lurd", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0, 0 },
- { "th.surb", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0, 0 },
- { "th.surh", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0, 0 },
- { "th.surw", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0, 0 },
- { "th.surd", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0, 0 },
+ { "th.lbia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr },
+ { "th.lbib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml },
+ { "th.lbuia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr },
+ { "th.lbuib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr },
+ { "th.lhia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr },
+ { "th.lhib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr },
+ { "th.lhuia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr },
+ { "th.lhuib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr },
+ { "th.lwia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr },
+ { "th.lwib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr },
+ { "th.lwuia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr },
+ { "th.lwuib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr },
+ { "th.ldia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr },
+ { "th.ldib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr },
+ { "th.sbia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr },
+ { "th.sbib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr },
+ { "th.shia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr },
+ { "th.shib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr },
+ { "th.swia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr },
+ { "th.swib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr },
+ { "th.sdia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr },
+ { "th.sdib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr },
+ { "th.lrb", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm },
+ { "th.lrbu", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm },
+ { "th.lrh", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm },
+ { "th.lrhu", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm },
+ { "th.lrw", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm },
+ { "th.lrwu", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm },
+ { "th.lrd", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm },
+ { "th.srb", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm },
+ { "th.srh", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm },
+ { "th.srw", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm },
+ { "th.srd", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm },
+ { "th.lurb", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm },
+ { "th.lurbu", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm },
+ { "th.lurh", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm },
+ { "th.lurhu", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm },
+ { "th.lurw", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm },
+ { "th.lurwu", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm },
+ { "th.lurd", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm },
+ { "th.surb", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm },
+ { "th.surh", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm },
+ { "th.surw", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm },
+ { "th.surd", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm },
/* XTheadMemPair */
- { "th.ldd", rv_codec_r_imm2, rv_fmt_rd2_imm, NULL, 0, 0, 0 },
- { "th.lwd", rv_codec_r_imm2, rv_fmt_rd2_imm, NULL, 0, 0, 0 },
- { "th.lwud", rv_codec_r_imm2, rv_fmt_rd2_imm, NULL, 0, 0, 0 },
- { "th.sdd", rv_codec_r_imm2, rv_fmt_rd2_imm, NULL, 0, 0, 0 },
- { "th.swd", rv_codec_r_imm2, rv_fmt_rd2_imm, NULL, 0, 0, 0 },
+ { "th.ldd", rv_codec_r_imm2, rv_fmt_rd2_imm },
+ { "th.lwd", rv_codec_r_imm2, rv_fmt_rd2_imm },
+ { "th.lwud", rv_codec_r_imm2, rv_fmt_rd2_imm },
+ { "th.sdd", rv_codec_r_imm2, rv_fmt_rd2_imm },
+ { "th.swd", rv_codec_r_imm2, rv_fmt_rd2_imm },
/* XTheadSync */
- { "th.sfence.vmas", rv_codec_r, rv_fmt_rs1_rs2, NULL, 0, 0, 0 },
- { "th.sync", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
- { "th.sync.i", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
- { "th.sync.is", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
- { "th.sync.s", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
+ { "th.sfence.vmas", rv_codec_r, rv_fmt_rs1_rs2 },
+ { "th.sync", rv_codec_none, rv_fmt_none },
+ { "th.sync.i", rv_codec_none, rv_fmt_none },
+ { "th.sync.is", rv_codec_none, rv_fmt_none },
+ { "th.sync.s", rv_codec_none, rv_fmt_none },
};
void decode_xtheadba(rv_decode *dec, rv_isa isa)
diff --git a/disas/riscv-xventana.c b/disas/riscv-xventana.c
index 4539173d95..4fb9a29d0b 100644
--- a/disas/riscv-xventana.c
+++ b/disas/riscv-xventana.c
@@ -15,9 +15,9 @@ typedef enum {
} rv_ventana_op;
static const rv_opcode_data ventana_opcode_data[] = {
- { "vt.illegal", rv_codec_illegal, rv_fmt_none, NULL, 0, 0, 0 },
- { "vt.maskc", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
- { "vt.maskcn", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "vt.illegal", rv_codec_illegal, rv_fmt_none },
+ { "vt.maskc", rv_codec_r, rv_fmt_rd_rs1_rs2 },
+ { "vt.maskcn", rv_codec_r, rv_fmt_rd_rs1_rs2 },
};
void decode_xventanacondops(rv_decode *dec, rv_isa isa)
diff --git a/disas/riscv.c b/disas/riscv.c
index eb6d132a2c..ec40abb618 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -1657,233 +1657,233 @@ static uint32_t operand_lpl(rv_inst inst)
/* instruction metadata */
static const rv_opcode_data rvi_opcode_data[] = {
- { "illegal", rv_codec_illegal, rv_fmt_none, NULL, 0, 0, 0 },
- { "lui", rv_codec_u, rv_fmt_rd_uimm, NULL, 0, 0, 0 },
- { "auipc", rv_codec_u, rv_fmt_rd_uoffset, NULL, 0, 0, 0 },
- { "jal", rv_codec_uj, rv_fmt_rd_offset, rvcp_jal, 0, 0, 0 },
- { "jalr", rv_codec_i, rv_fmt_rd_rs1_offset, rvcp_jalr, 0, 0, 0 },
- { "beq", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_beq, 0, 0, 0 },
- { "bne", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_bne, 0, 0, 0 },
- { "blt", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_blt, 0, 0, 0 },
- { "bge", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_bge, 0, 0, 0 },
- { "bltu", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_bltu, 0, 0, 0 },
- { "bgeu", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_bgeu, 0, 0, 0 },
- { "lb", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 },
- { "lh", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 },
- { "lw", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 },
- { "lbu", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 },
- { "lhu", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 },
- { "sb", rv_codec_s, rv_fmt_rs2_offset_rs1, NULL, 0, 0, 0 },
- { "sh", rv_codec_s, rv_fmt_rs2_offset_rs1, NULL, 0, 0, 0 },
- { "sw", rv_codec_s, rv_fmt_rs2_offset_rs1, NULL, 0, 0, 0 },
- { "addi", rv_codec_i, rv_fmt_rd_rs1_imm, rvcp_addi, 0, 0, 0 },
- { "slti", rv_codec_i, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
- { "sltiu", rv_codec_i, rv_fmt_rd_rs1_imm, rvcp_sltiu, 0, 0, 0 },
- { "xori", rv_codec_i, rv_fmt_rd_rs1_imm, rvcp_xori, 0, 0, 0 },
- { "ori", rv_codec_i, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
- { "andi", rv_codec_i, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
- { "slli", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
- { "srli", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
- { "srai", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
- { "add", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
- { "sub", rv_codec_r, rv_fmt_rd_rs1_rs2, rvcp_sub, 0, 0, 0 },
- { "sll", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
- { "slt", rv_codec_r, rv_fmt_rd_rs1_rs2, rvcp_slt, 0, 0, 0 },
- { "sltu", rv_codec_r, rv_fmt_rd_rs1_rs2, rvcp_sltu, 0, 0, 0 },
- { "xor", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
- { "srl", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
- { "sra", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
- { "or", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
- { "and", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
- { "fence", rv_codec_r_f, rv_fmt_pred_succ, NULL, 0, 0, 0 },
- { "fence.i", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
- { "lwu", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 },
- { "ld", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 },
- { "sd", rv_codec_s, rv_fmt_rs2_offset_rs1, NULL, 0, 0, 0 },
- { "addiw", rv_codec_i, rv_fmt_rd_rs1_imm, rvcp_addiw, 0, 0, 0 },
- { "slliw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
- { "srliw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
- { "sraiw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
- { "addw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
- { "subw", rv_codec_r, rv_fmt_rd_rs1_rs2, rvcp_subw, 0, 0, 0 },
- { "sllw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
- { "srlw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
- { "sraw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
- { "ldu", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 },
- { "lq", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 },
- { "sq", rv_codec_s, rv_fmt_rs2_offset_rs1, NULL, 0, 0, 0 },
- { "addid", rv_codec_i, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
- { "sllid", rv_codec_i_sh6, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
- { "srlid", rv_codec_i_sh6, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
- { "sraid", rv_codec_i_sh6, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
- { "addd", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
- { "subd", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
- { "slld", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
- { "srld", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
- { "srad", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
- { "mul", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
- { "mulh", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
- { "mulhsu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
- { "mulhu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
- { "div", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
- { "divu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
- { "rem", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
- { "remu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
- { "mulw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
- { "divw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
- { "divuw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
- { "remw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
- { "remuw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
- { "muld", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
- { "divd", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
- { "divud", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
- { "remd", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
- { "remud", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
- { "lr.w", rv_codec_r_l, rv_fmt_aqrl_rd_rs1, NULL, 0, 0, 0 },
- { "sc.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
- { "amoswap.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
- { "amoadd.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
- { "amoxor.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
- { "amoor.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
- { "amoand.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
- { "amomin.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
- { "amomax.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
- { "amominu.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
- { "amomaxu.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
- { "lr.d", rv_codec_r_l, rv_fmt_aqrl_rd_rs1, NULL, 0, 0, 0 },
- { "sc.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
- { "amoswap.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
- { "amoadd.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
- { "amoxor.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
- { "amoor.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
- { "amoand.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
- { "amomin.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
- { "amomax.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
- { "amominu.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
- { "amomaxu.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
- { "lr.q", rv_codec_r_l, rv_fmt_aqrl_rd_rs1, NULL, 0, 0, 0 },
- { "sc.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
- { "amoswap.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
- { "amoadd.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
- { "amoxor.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
- { "amoor.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
- { "amoand.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
- { "amomin.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
- { "amomax.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
- { "amominu.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
- { "amomaxu.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
- { "ecall", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
- { "ebreak", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
- { "uret", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
- { "sret", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
- { "hret", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
- { "mret", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
- { "dret", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
- { "sfence.vm", rv_codec_r, rv_fmt_rs1, NULL, 0, 0, 0 },
- { "sfence.vma", rv_codec_r, rv_fmt_rs1_rs2, NULL, 0, 0, 0 },
- { "wfi", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
- { "csrrw", rv_codec_i_csr, rv_fmt_rd_csr_rs1, rvcp_csrrw, 0, 0, 0 },
- { "csrrs", rv_codec_i_csr, rv_fmt_rd_csr_rs1, rvcp_csrrs, 0, 0, 0 },
- { "csrrc", rv_codec_i_csr, rv_fmt_rd_csr_rs1, NULL, 0, 0, 0 },
- { "csrrwi", rv_codec_i_csr, rv_fmt_rd_csr_zimm, rvcp_csrrwi, 0, 0, 0 },
- { "csrrsi", rv_codec_i_csr, rv_fmt_rd_csr_zimm, NULL, 0, 0, 0 },
- { "csrrci", rv_codec_i_csr, rv_fmt_rd_csr_zimm, NULL, 0, 0, 0 },
- { "flw", rv_codec_i, rv_fmt_frd_offset_rs1, NULL, 0, 0, 0 },
- { "fsw", rv_codec_s, rv_fmt_frs2_offset_rs1, NULL, 0, 0, 0 },
- { "fmadd.s", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 },
- { "fmsub.s", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 },
- { "fnmsub.s", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 },
- { "fnmadd.s", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 },
- { "fadd.s", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 },
- { "fsub.s", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 },
- { "fmul.s", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 },
- { "fdiv.s", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 },
- { "fsgnj.s", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnj_s, 0, 0, 0 },
- { "fsgnjn.s", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjn_s, 0, 0, 0 },
- { "fsgnjx.s", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjx_s, 0, 0, 0 },
- { "fmin.s", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 },
- { "fmax.s", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 },
- { "fsqrt.s", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },
- { "fle.s", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 },
- { "flt.s", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 },
- { "feq.s", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 },
- { "fcvt.w.s", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 },
- { "fcvt.wu.s", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 },
- { "fcvt.s.w", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 },
- { "fcvt.s.wu", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 },
- { "fmv.x.s", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 },
- { "fclass.s", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 },
- { "fmv.s.x", rv_codec_r, rv_fmt_frd_rs1, NULL, 0, 0, 0 },
- { "fcvt.l.s", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 },
- { "fcvt.lu.s", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 },
- { "fcvt.s.l", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 },
- { "fcvt.s.lu", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 },
- { "fld", rv_codec_i, rv_fmt_frd_offset_rs1, NULL, 0, 0, 0 },
- { "fsd", rv_codec_s, rv_fmt_frs2_offset_rs1, NULL, 0, 0, 0 },
- { "fmadd.d", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 },
- { "fmsub.d", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 },
- { "fnmsub.d", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 },
- { "fnmadd.d", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 },
- { "fadd.d", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 },
- { "fsub.d", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 },
- { "fmul.d", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 },
- { "fdiv.d", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 },
- { "fsgnj.d", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnj_d, 0, 0, 0 },
- { "fsgnjn.d", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjn_d, 0, 0, 0 },
- { "fsgnjx.d", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjx_d, 0, 0, 0 },
- { "fmin.d", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 },
- { "fmax.d", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 },
- { "fcvt.s.d", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },
- { "fcvt.d.s", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },
- { "fsqrt.d", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },
- { "fle.d", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 },
- { "flt.d", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 },
- { "feq.d", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 },
- { "fcvt.w.d", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 },
- { "fcvt.wu.d", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 },
- { "fcvt.d.w", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 },
- { "fcvt.d.wu", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 },
- { "fclass.d", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 },
- { "fcvt.l.d", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 },
- { "fcvt.lu.d", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 },
- { "fmv.x.d", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 },
- { "fcvt.d.l", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 },
- { "fcvt.d.lu", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 },
- { "fmv.d.x", rv_codec_r, rv_fmt_frd_rs1, NULL, 0, 0, 0 },
- { "flq", rv_codec_i, rv_fmt_frd_offset_rs1, NULL, 0, 0, 0 },
- { "fsq", rv_codec_s, rv_fmt_frs2_offset_rs1, NULL, 0, 0, 0 },
- { "fmadd.q", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 },
- { "fmsub.q", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 },
- { "fnmsub.q", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 },
- { "fnmadd.q", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 },
- { "fadd.q", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 },
- { "fsub.q", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 },
- { "fmul.q", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 },
- { "fdiv.q", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 },
- { "fsgnj.q", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnj_q, 0, 0, 0 },
- { "fsgnjn.q", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjn_q, 0, 0, 0 },
- { "fsgnjx.q", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjx_q, 0, 0, 0 },
- { "fmin.q", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 },
- { "fmax.q", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 },
- { "fcvt.s.q", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },
- { "fcvt.q.s", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },
- { "fcvt.d.q", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },
- { "fcvt.q.d", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },
- { "fsqrt.q", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },
- { "fle.q", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 },
- { "flt.q", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 },
- { "feq.q", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 },
- { "fcvt.w.q", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 },
- { "fcvt.wu.q", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 },
- { "fcvt.q.w", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 },
- { "fcvt.q.wu", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 },
- { "fclass.q", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 },
- { "fcvt.l.q", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 },
- { "fcvt.lu.q", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 },
- { "fcvt.q.l", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 },
- { "fcvt.q.lu", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 },
- { "fmv.x.q", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 },
- { "fmv.q.x", rv_codec_r, rv_fmt_frd_rs1, NULL, 0, 0, 0 },
+ { "illegal", rv_codec_illegal, rv_fmt_none },
+ { "lui", rv_codec_u, rv_fmt_rd_uimm },
+ { "auipc", rv_codec_u, rv_fmt_rd_uoffset },
+ { "jal", rv_codec_uj, rv_fmt_rd_offset, rvcp_jal },
+ { "jalr", rv_codec_i, rv_fmt_rd_rs1_offset, rvcp_jalr },
+ { "beq", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_beq },
+ { "bne", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_bne },
+ { "blt", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_blt },
+ { "bge", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_bge },
+ { "bltu", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_bltu },
+ { "bgeu", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_bgeu },
+ { "lb", rv_codec_i, rv_fmt_rd_offset_rs1 },
+ { "lh", rv_codec_i, rv_fmt_rd_offset_rs1 },
+ { "lw", rv_codec_i, rv_fmt_rd_offset_rs1 },
+ { "lbu", rv_codec_i, rv_fmt_rd_offset_rs1 },
+ { "lhu", rv_codec_i, rv_fmt_rd_offset_rs1 },
+ { "sb", rv_codec_s, rv_fmt_rs2_offset_rs1 },
+ { "sh", rv_codec_s, rv_fmt_rs2_offset_rs1 },
+ { "sw", rv_codec_s, rv_fmt_rs2_offset_rs1 },
+ { "addi", rv_codec_i, rv_fmt_rd_rs1_imm, rvcp_addi },
+ { "slti", rv_codec_i, rv_fmt_rd_rs1_imm },
+ { "sltiu", rv_codec_i, rv_fmt_rd_rs1_imm, rvcp_sltiu },
+ { "xori", rv_codec_i, rv_fmt_rd_rs1_imm, rvcp_xori },
+ { "ori", rv_codec_i, rv_fmt_rd_rs1_imm },
+ { "andi", rv_codec_i, rv_fmt_rd_rs1_imm },
+ { "slli", rv_codec_i_sh7, rv_fmt_rd_rs1_imm },
+ { "srli", rv_codec_i_sh7, rv_fmt_rd_rs1_imm },
+ { "srai", rv_codec_i_sh7, rv_fmt_rd_rs1_imm },
+ { "add", rv_codec_r, rv_fmt_rd_rs1_rs2 },
+ { "sub", rv_codec_r, rv_fmt_rd_rs1_rs2, rvcp_sub },
+ { "sll", rv_codec_r, rv_fmt_rd_rs1_rs2 },
+ { "slt", rv_codec_r, rv_fmt_rd_rs1_rs2, rvcp_slt },
+ { "sltu", rv_codec_r, rv_fmt_rd_rs1_rs2, rvcp_sltu },
+ { "xor", rv_codec_r, rv_fmt_rd_rs1_rs2 },
+ { "srl", rv_codec_r, rv_fmt_rd_rs1_rs2 },
+ { "sra", rv_codec_r, rv_fmt_rd_rs1_rs2 },
+ { "or", rv_codec_r, rv_fmt_rd_rs1_rs2 },
+ { "and", rv_codec_r, rv_fmt_rd_rs1_rs2 },
+ { "fence", rv_codec_r_f, rv_fmt_pred_succ },
+ { "fence.i", rv_codec_none, rv_fmt_none },
+ { "lwu", rv_codec_i, rv_fmt_rd_offset_rs1 },
+ { "ld", rv_codec_i, rv_fmt_rd_offset_rs1 },
+ { "sd", rv_codec_s, rv_fmt_rs2_offset_rs1 },
+ { "addiw", rv_codec_i, rv_fmt_rd_rs1_imm, rvcp_addiw },
+ { "slliw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm },
+ { "srliw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm },
+ { "sraiw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm },
+ { "addw", rv_codec_r, rv_fmt_rd_rs1_rs2 },
+ { "subw", rv_codec_r, rv_fmt_rd_rs1_rs2, rvcp_subw },
+ { "sllw", rv_codec_r, rv_fmt_rd_rs1_rs2 },
+ { "srlw", rv_codec_r, rv_fmt_rd_rs1_rs2 },
+ { "sraw", rv_codec_r, rv_fmt_rd_rs1_rs2 },
+ { "ldu", rv_codec_i, rv_fmt_rd_offset_rs1 },
+ { "lq", rv_codec_i, rv_fmt_rd_offset_rs1 },
+ { "sq", rv_codec_s, rv_fmt_rs2_offset_rs1 },
+ { "addid", rv_codec_i, rv_fmt_rd_rs1_imm },
+ { "sllid", rv_codec_i_sh6, rv_fmt_rd_rs1_imm },
+ { "srlid", rv_codec_i_sh6, rv_fmt_rd_rs1_imm },
+ { "sraid", rv_codec_i_sh6, rv_fmt_rd_rs1_imm },
+ { "addd", rv_codec_r, rv_fmt_rd_rs1_rs2 },
+ { "subd", rv_codec_r, rv_fmt_rd_rs1_rs2 },
+ { "slld", rv_codec_r, rv_fmt_rd_rs1_rs2 },
+ { "srld", rv_codec_r, rv_fmt_rd_rs1_rs2 },
+ { "srad", rv_codec_r, rv_fmt_rd_rs1_rs2 },
+ { "mul", rv_codec_r, rv_fmt_rd_rs1_rs2 },
+ { "mulh", rv_codec_r, rv_fmt_rd_rs1_rs2 },
+ { "mulhsu", rv_codec_r, rv_fmt_rd_rs1_rs2 },
+ { "mulhu", rv_codec_r, rv_fmt_rd_rs1_rs2 },
+ { "div", rv_codec_r, rv_fmt_rd_rs1_rs2 },
+ { "divu", rv_codec_r, rv_fmt_rd_rs1_rs2 },
+ { "rem", rv_codec_r, rv_fmt_rd_rs1_rs2 },
+ { "remu", rv_codec_r, rv_fmt_rd_rs1_rs2 },
+ { "mulw", rv_codec_r, rv_fmt_rd_rs1_rs2 },
+ { "divw", rv_codec_r, rv_fmt_rd_rs1_rs2 },
+ { "divuw", rv_codec_r, rv_fmt_rd_rs1_rs2 },
+ { "remw", rv_codec_r, rv_fmt_rd_rs1_rs2 },
+ { "remuw", rv_codec_r, rv_fmt_rd_rs1_rs2 },
+ { "muld", rv_codec_r, rv_fmt_rd_rs1_rs2 },
+ { "divd", rv_codec_r, rv_fmt_rd_rs1_rs2 },
+ { "divud", rv_codec_r, rv_fmt_rd_rs1_rs2 },
+ { "remd", rv_codec_r, rv_fmt_rd_rs1_rs2 },
+ { "remud", rv_codec_r, rv_fmt_rd_rs1_rs2 },
+ { "lr.w", rv_codec_r_l, rv_fmt_aqrl_rd_rs1 },
+ { "sc.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
+ { "amoswap.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
+ { "amoadd.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
+ { "amoxor.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
+ { "amoor.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
+ { "amoand.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
+ { "amomin.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
+ { "amomax.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
+ { "amominu.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
+ { "amomaxu.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
+ { "lr.d", rv_codec_r_l, rv_fmt_aqrl_rd_rs1 },
+ { "sc.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
+ { "amoswap.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
+ { "amoadd.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
+ { "amoxor.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
+ { "amoor.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
+ { "amoand.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
+ { "amomin.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
+ { "amomax.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
+ { "amominu.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
+ { "amomaxu.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
+ { "lr.q", rv_codec_r_l, rv_fmt_aqrl_rd_rs1 },
+ { "sc.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
+ { "amoswap.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
+ { "amoadd.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
+ { "amoxor.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
+ { "amoor.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
+ { "amoand.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
+ { "amomin.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
+ { "amomax.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
+ { "amominu.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
+ { "amomaxu.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
+ { "ecall", rv_codec_none, rv_fmt_none },
+ { "ebreak", rv_codec_none, rv_fmt_none },
+ { "uret", rv_codec_none, rv_fmt_none },
+ { "sret", rv_codec_none, rv_fmt_none },
+ { "hret", rv_codec_none, rv_fmt_none },
+ { "mret", rv_codec_none, rv_fmt_none },
+ { "dret", rv_codec_none, rv_fmt_none },
+ { "sfence.vm", rv_codec_r, rv_fmt_rs1 },
+ { "sfence.vma", rv_codec_r, rv_fmt_rs1_rs2 },
+ { "wfi", rv_codec_none, rv_fmt_none },
+ { "csrrw", rv_codec_i_csr, rv_fmt_rd_csr_rs1, rvcp_csrrw },
+ { "csrrs", rv_codec_i_csr, rv_fmt_rd_csr_rs1, rvcp_csrrs },
+ { "csrrc", rv_codec_i_csr, rv_fmt_rd_csr_rs1 },
+ { "csrrwi", rv_codec_i_csr, rv_fmt_rd_csr_zimm, rvcp_csrrwi },
+ { "csrrsi", rv_codec_i_csr, rv_fmt_rd_csr_zimm },
+ { "csrrci", rv_codec_i_csr, rv_fmt_rd_csr_zimm },
+ { "flw", rv_codec_i, rv_fmt_frd_offset_rs1 },
+ { "fsw", rv_codec_s, rv_fmt_frs2_offset_rs1 },
+ { "fmadd.s", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3 },
+ { "fmsub.s", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3 },
+ { "fnmsub.s", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3 },
+ { "fnmadd.s", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3 },
+ { "fadd.s", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2 },
+ { "fsub.s", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2 },
+ { "fmul.s", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2 },
+ { "fdiv.s", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2 },
+ { "fsgnj.s", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnj_s },
+ { "fsgnjn.s", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjn_s },
+ { "fsgnjx.s", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjx_s },
+ { "fmin.s", rv_codec_r, rv_fmt_frd_frs1_frs2 },
+ { "fmax.s", rv_codec_r, rv_fmt_frd_frs1_frs2 },
+ { "fsqrt.s", rv_codec_r_m, rv_fmt_rm_frd_frs1 },
+ { "fle.s", rv_codec_r, rv_fmt_rd_frs1_frs2 },
+ { "flt.s", rv_codec_r, rv_fmt_rd_frs1_frs2 },
+ { "feq.s", rv_codec_r, rv_fmt_rd_frs1_frs2 },
+ { "fcvt.w.s", rv_codec_r_m, rv_fmt_rm_rd_frs1 },
+ { "fcvt.wu.s", rv_codec_r_m, rv_fmt_rm_rd_frs1 },
+ { "fcvt.s.w", rv_codec_r_m, rv_fmt_rm_frd_rs1 },
+ { "fcvt.s.wu", rv_codec_r_m, rv_fmt_rm_frd_rs1 },
+ { "fmv.x.s", rv_codec_r, rv_fmt_rd_frs1 },
+ { "fclass.s", rv_codec_r, rv_fmt_rd_frs1 },
+ { "fmv.s.x", rv_codec_r, rv_fmt_frd_rs1 },
+ { "fcvt.l.s", rv_codec_r_m, rv_fmt_rm_rd_frs1 },
+ { "fcvt.lu.s", rv_codec_r_m, rv_fmt_rm_rd_frs1 },
+ { "fcvt.s.l", rv_codec_r_m, rv_fmt_rm_frd_rs1 },
+ { "fcvt.s.lu", rv_codec_r_m, rv_fmt_rm_frd_rs1 },
+ { "fld", rv_codec_i, rv_fmt_frd_offset_rs1 },
+ { "fsd", rv_codec_s, rv_fmt_frs2_offset_rs1 },
+ { "fmadd.d", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3 },
+ { "fmsub.d", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3 },
+ { "fnmsub.d", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3 },
+ { "fnmadd.d", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3 },
+ { "fadd.d", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2 },
+ { "fsub.d", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2 },
+ { "fmul.d", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2 },
+ { "fdiv.d", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2 },
+ { "fsgnj.d", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnj_d },
+ { "fsgnjn.d", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjn_d },
+ { "fsgnjx.d", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjx_d },
+ { "fmin.d", rv_codec_r, rv_fmt_frd_frs1_frs2 },
+ { "fmax.d", rv_codec_r, rv_fmt_frd_frs1_frs2 },
+ { "fcvt.s.d", rv_codec_r_m, rv_fmt_rm_frd_frs1 },
+ { "fcvt.d.s", rv_codec_r_m, rv_fmt_rm_frd_frs1 },
+ { "fsqrt.d", rv_codec_r_m, rv_fmt_rm_frd_frs1 },
+ { "fle.d", rv_codec_r, rv_fmt_rd_frs1_frs2 },
+ { "flt.d", rv_codec_r, rv_fmt_rd_frs1_frs2 },
+ { "feq.d", rv_codec_r, rv_fmt_rd_frs1_frs2 },
+ { "fcvt.w.d", rv_codec_r_m, rv_fmt_rm_rd_frs1 },
+ { "fcvt.wu.d", rv_codec_r_m, rv_fmt_rm_rd_frs1 },
+ { "fcvt.d.w", rv_codec_r_m, rv_fmt_rm_frd_rs1 },
+ { "fcvt.d.wu", rv_codec_r_m, rv_fmt_rm_frd_rs1 },
+ { "fclass.d", rv_codec_r, rv_fmt_rd_frs1 },
+ { "fcvt.l.d", rv_codec_r_m, rv_fmt_rm_rd_frs1 },
+ { "fcvt.lu.d", rv_codec_r_m, rv_fmt_rm_rd_frs1 },
+ { "fmv.x.d", rv_codec_r, rv_fmt_rd_frs1 },
+ { "fcvt.d.l", rv_codec_r_m, rv_fmt_rm_frd_rs1 },
+ { "fcvt.d.lu", rv_codec_r_m, rv_fmt_rm_frd_rs1 },
+ { "fmv.d.x", rv_codec_r, rv_fmt_frd_rs1 },
+ { "flq", rv_codec_i, rv_fmt_frd_offset_rs1 },
+ { "fsq", rv_codec_s, rv_fmt_frs2_offset_rs1 },
+ { "fmadd.q", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3 },
+ { "fmsub.q", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3 },
+ { "fnmsub.q", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3 },
+ { "fnmadd.q", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3 },
+ { "fadd.q", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2 },
+ { "fsub.q", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2 },
+ { "fmul.q", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2 },
+ { "fdiv.q", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2 },
+ { "fsgnj.q", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnj_q },
+ { "fsgnjn.q", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjn_q },
+ { "fsgnjx.q", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjx_q },
+ { "fmin.q", rv_codec_r, rv_fmt_frd_frs1_frs2 },
+ { "fmax.q", rv_codec_r, rv_fmt_frd_frs1_frs2 },
+ { "fcvt.s.q", rv_codec_r_m, rv_fmt_rm_frd_frs1 },
+ { "fcvt.q.s", rv_codec_r_m, rv_fmt_rm_frd_frs1 },
+ { "fcvt.d.q", rv_codec_r_m, rv_fmt_rm_frd_frs1 },
+ { "fcvt.q.d", rv_codec_r_m, rv_fmt_rm_frd_frs1 },
+ { "fsqrt.q", rv_codec_r_m, rv_fmt_rm_frd_frs1 },
+ { "fle.q", rv_codec_r, rv_fmt_rd_frs1_frs2 },
+ { "flt.q", rv_codec_r, rv_fmt_rd_frs1_frs2 },
+ { "feq.q", rv_codec_r, rv_fmt_rd_frs1_frs2 },
+ { "fcvt.w.q", rv_codec_r_m, rv_fmt_rm_rd_frs1 },
+ { "fcvt.wu.q", rv_codec_r_m, rv_fmt_rm_rd_frs1 },
+ { "fcvt.q.w", rv_codec_r_m, rv_fmt_rm_frd_rs1 },
+ { "fcvt.q.wu", rv_codec_r_m, rv_fmt_rm_frd_rs1 },
+ { "fclass.q", rv_codec_r, rv_fmt_rd_frs1 },
+ { "fcvt.l.q", rv_codec_r_m, rv_fmt_rm_rd_frs1 },
+ { "fcvt.lu.q", rv_codec_r_m, rv_fmt_rm_rd_frs1 },
+ { "fcvt.q.l", rv_codec_r_m, rv_fmt_rm_frd_rs1 },
+ { "fcvt.q.lu", rv_codec_r_m, rv_fmt_rm_frd_rs1 },
+ { "fmv.x.q", rv_codec_r, rv_fmt_rd_frs1 },
+ { "fmv.q.x", rv_codec_r, rv_fmt_frd_rs1 },
{ "c.addi4spn", rv_codec_ciw_4spn, rv_fmt_rd_rs1_imm, NULL, rv_op_addi,
rv_op_addi, rv_op_addi, rvcd_imm_nz },
{ "c.fld", rv_codec_cl_ld, rv_fmt_frd_offset_rs1, NULL, rv_op_fld,
@@ -1970,696 +1970,696 @@ static const rv_opcode_data rvi_opcode_data[] = {
{ "c.lqsp", rv_codec_ci_lqsp, rv_fmt_rd_offset_rs1, NULL, 0, 0, rv_op_lq },
{ "c.sqsp", rv_codec_css_sqsp, rv_fmt_rs2_offset_rs1, NULL, 0, 0,
rv_op_sq },
- { "nop", rv_codec_i, rv_fmt_none, NULL, 0, 0, 0 },
- { "mv", rv_codec_i, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
- { "not", rv_codec_i, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
- { "neg", rv_codec_r, rv_fmt_rd_rs2, NULL, 0, 0, 0 },
- { "negw", rv_codec_r, rv_fmt_rd_rs2, NULL, 0, 0, 0 },
- { "sext.w", rv_codec_i, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
- { "seqz", rv_codec_i, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
- { "snez", rv_codec_r, rv_fmt_rd_rs2, NULL, 0, 0, 0 },
- { "sltz", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
- { "sgtz", rv_codec_r, rv_fmt_rd_rs2, NULL, 0, 0, 0 },
- { "fmv.s", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
- { "fabs.s", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
- { "fneg.s", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
- { "fmv.d", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
- { "fabs.d", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
- { "fneg.d", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
- { "fmv.q", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
- { "fabs.q", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
- { "fneg.q", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
- { "beqz", rv_codec_sb, rv_fmt_rs1_offset, NULL, 0, 0, 0 },
- { "bnez", rv_codec_sb, rv_fmt_rs1_offset, NULL, 0, 0, 0 },
- { "blez", rv_codec_sb, rv_fmt_rs2_offset, NULL, 0, 0, 0 },
- { "bgez", rv_codec_sb, rv_fmt_rs1_offset, NULL, 0, 0, 0 },
- { "bltz", rv_codec_sb, rv_fmt_rs1_offset, NULL, 0, 0, 0 },
- { "bgtz", rv_codec_sb, rv_fmt_rs2_offset, NULL, 0, 0, 0 },
- { "ble", rv_codec_sb, rv_fmt_rs2_rs1_offset, NULL, 0, 0, 0 },
- { "bleu", rv_codec_sb, rv_fmt_rs2_rs1_offset, NULL, 0, 0, 0 },
- { "bgt", rv_codec_sb, rv_fmt_rs2_rs1_offset, NULL, 0, 0, 0 },
- { "bgtu", rv_codec_sb, rv_fmt_rs2_rs1_offset, NULL, 0, 0, 0 },
- { "j", rv_codec_uj, rv_fmt_offset, NULL, 0, 0, 0 },
- { "ret", rv_codec_i, rv_fmt_none, NULL, 0, 0, 0 },
- { "jr", rv_codec_i, rv_fmt_rs1, NULL, 0, 0, 0 },
- { "rdcycle", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 },
- { "rdtime", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 },
- { "rdinstret", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 },
- { "rdcycleh", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 },
- { "rdtimeh", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 },
- { "rdinstreth", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 },
- { "frcsr", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 },
- { "frrm", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 },
- { "frflags", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 },
- { "fscsr", rv_codec_i_csr, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
- { "fsrm", rv_codec_i_csr, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
- { "fsflags", rv_codec_i_csr, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
- { "fsrmi", rv_codec_i_csr, rv_fmt_rd_zimm, NULL, 0, 0, 0 },
- { "fsflagsi", rv_codec_i_csr, rv_fmt_rd_zimm, NULL, 0, 0, 0 },
- { "bseti", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
- { "bclri", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
- { "binvi", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
- { "bexti", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
- { "rori", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
- { "clz", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
- { "ctz", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
- { "cpop", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
- { "sext.h", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
- { "sext.b", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
- { "xnor", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
- { "orn", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
- { "andn", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
- { "rol", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
- { "ror", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
- { "sh1add", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
- { "sh2add", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
- { "sh3add", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
- { "sh1add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
- { "sh2add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
- { "sh3add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
- { "clmul", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
- { "clmulr", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
- { "clmulh", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
- { "min", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
- { "minu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
- { "max", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
- { "maxu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
- { "clzw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
- { "ctzw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
- { "cpopw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
- { "slli.uw", rv_codec_i_sh6, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
- { "add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
- { "rolw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
- { "rorw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
- { "rev8", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
- { "zext.h", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
- { "roriw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
- { "orc.b", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
- { "bset", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
- { "bclr", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
- { "binv", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
- { "bext", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
- { "aes32esmi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 },
- { "aes32esi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 },
- { "aes32dsmi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 },
- { "aes32dsi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 },
- { "aes64ks1i", rv_codec_k_rnum, rv_fmt_rd_rs1_rnum, NULL, 0, 0, 0 },
- { "aes64ks2", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
- { "aes64im", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
- { "aes64esm", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
- { "aes64es", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
- { "aes64dsm", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
- { "aes64ds", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
- { "sha256sig0", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
- { "sha256sig1", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
- { "sha256sum0", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
- { "sha256sum1", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
- { "sha512sig0", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
- { "sha512sig1", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
- { "sha512sum0", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
- { "sha512sum1", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
- { "sha512sum0r", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
- { "sha512sum1r", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
- { "sha512sig0l", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
- { "sha512sig0h", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
- { "sha512sig1l", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
- { "sha512sig1h", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
- { "sm3p0", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
- { "sm3p1", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
- { "sm4ed", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 },
- { "sm4ks", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 },
- { "brev8", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
- { "pack", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
- { "packh", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
- { "packw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
- { "unzip", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
- { "zip", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
- { "xperm4", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
- { "xperm8", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
- { "vle8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
- { "vle16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
- { "vle32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
- { "vle64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
- { "vse8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
- { "vse16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
- { "vse32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
- { "vse64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
- { "vlm.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
- { "vsm.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
- { "vlse8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, 0, 0, 0 },
- { "vlse16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, 0, 0, 0 },
- { "vlse32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, 0, 0, 0 },
- { "vlse64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, 0, 0, 0 },
- { "vsse8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, 0, 0, 0 },
- { "vsse16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, 0, 0, 0 },
- { "vsse32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, 0, 0, 0 },
- { "vsse64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, 0, 0, 0 },
- { "vluxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
- { "vluxei16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
- { "vluxei32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
- { "vluxei64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
- { "vloxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
- { "vloxei16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
- { "vloxei32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
- { "vloxei64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
- { "vsuxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
- { "vsuxei16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
- { "vsuxei32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
- { "vsuxei64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
- { "vsoxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
- { "vsoxei16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
- { "vsoxei32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
- { "vsoxei64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
- { "vle8ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
- { "vle16ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
- { "vle32ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
- { "vle64ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
- { "vl1re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
- { "vl1re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
- { "vl1re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
- { "vl1re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
- { "vl2re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
- { "vl2re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
- { "vl2re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
- { "vl2re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
- { "vl4re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
- { "vl4re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
- { "vl4re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
- { "vl4re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
- { "vl8re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
- { "vl8re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
- { "vl8re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
- { "vl8re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
- { "vs1r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
- { "vs2r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
- { "vs4r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
- { "vs8r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
- { "vadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
- { "vadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
- { "vadd.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 },
- { "vsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
- { "vsub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
- { "vrsub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
- { "vrsub.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 },
- { "vwaddu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
- { "vwaddu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
- { "vwadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
- { "vwadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
- { "vwsubu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
- { "vwsubu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
- { "vwsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
- { "vwsub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
- { "vwaddu.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
- { "vwaddu.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
- { "vwadd.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
- { "vwadd.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
- { "vwsubu.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
- { "vwsubu.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
- { "vwsub.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
- { "vwsub.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
- { "vadc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl, NULL, 0, 0, 0 },
- { "vadc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl, NULL, 0, 0, 0 },
- { "vadc.vim", rv_codec_v_i, rv_fmt_vd_vs2_imm_vl, NULL, 0, 0, 0 },
- { "vmadc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl, NULL, 0, 0, 0 },
- { "vmadc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl, NULL, 0, 0, 0 },
- { "vmadc.vim", rv_codec_v_i, rv_fmt_vd_vs2_imm_vl, NULL, 0, 0, 0 },
- { "vsbc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl, NULL, 0, 0, 0 },
- { "vsbc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl, NULL, 0, 0, 0 },
- { "vmsbc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl, NULL, 0, 0, 0 },
- { "vmsbc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl, NULL, 0, 0, 0 },
- { "vand.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
- { "vand.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
- { "vand.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 },
- { "vor.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
- { "vor.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
- { "vor.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 },
- { "vxor.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
- { "vxor.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
- { "vxor.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 },
- { "vsll.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
- { "vsll.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
- { "vsll.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 },
- { "vsrl.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
- { "vsrl.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
- { "vsrl.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 },
- { "vsra.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
- { "vsra.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
- { "vsra.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 },
- { "vnsrl.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
- { "vnsrl.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
- { "vnsrl.wi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 },
- { "vnsra.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
- { "vnsra.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
- { "vnsra.wi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 },
- { "vmseq.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
- { "vmseq.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
- { "vmseq.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 },
- { "vmsne.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
- { "vmsne.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
- { "vmsne.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 },
- { "vmsltu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
- { "vmsltu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
- { "vmslt.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
- { "vmslt.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
- { "vmsleu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
- { "vmsleu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
- { "vmsleu.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 },
- { "vmsle.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
- { "vmsle.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
- { "vmsle.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 },
- { "vmsgtu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
- { "vmsgtu.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 },
- { "vmsgt.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
- { "vmsgt.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 },
- { "vminu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
- { "vminu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
- { "vmin.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
- { "vmin.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
- { "vmaxu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
- { "vmaxu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
- { "vmax.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
- { "vmax.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
- { "vmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
- { "vmul.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
- { "vmulh.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
- { "vmulh.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
- { "vmulhu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
- { "vmulhu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
- { "vmulhsu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
- { "vmulhsu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
- { "vdivu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
- { "vdivu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
- { "vdiv.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
- { "vdiv.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
- { "vremu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
- { "vremu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
- { "vrem.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
- { "vrem.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
- { "vwmulu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
- { "vwmulu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
- { "vwmulsu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
- { "vwmulsu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
- { "vwmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
- { "vwmul.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
- { "vmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 },
- { "vmacc.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
- { "vnmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 },
- { "vnmsac.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
- { "vmadd.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 },
- { "vmadd.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
- { "vnmsub.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 },
- { "vnmsub.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
- { "vwmaccu.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 },
- { "vwmaccu.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
- { "vwmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 },
- { "vwmacc.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
- { "vwmaccsu.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 },
- { "vwmaccsu.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
- { "vwmaccus.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
- { "vmv.v.v", rv_codec_v_r, rv_fmt_vd_vs1, NULL, 0, 0, 0 },
- { "vmv.v.x", rv_codec_v_r, rv_fmt_vd_rs1, NULL, 0, 0, 0 },
- { "vmv.v.i", rv_codec_v_i, rv_fmt_vd_imm, NULL, 0, 0, 0 },
- { "vmerge.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl, NULL, 0, 0, 0 },
- { "vmerge.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl, NULL, 0, 0, 0 },
- { "vmerge.vim", rv_codec_v_i, rv_fmt_vd_vs2_imm_vl, NULL, 0, 0, 0 },
- { "vsaddu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
- { "vsaddu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
- { "vsaddu.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 },
- { "vsadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
- { "vsadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
- { "vsadd.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 },
- { "vssubu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
- { "vssubu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
- { "vssub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
- { "vssub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
- { "vaadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
- { "vaadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
- { "vaaddu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
- { "vaaddu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
- { "vasub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
- { "vasub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
- { "vasubu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
- { "vasubu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
- { "vsmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
- { "vsmul.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
- { "vssrl.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
- { "vssrl.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
- { "vssrl.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 },
- { "vssra.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
- { "vssra.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
- { "vssra.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 },
- { "vnclipu.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
- { "vnclipu.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
- { "vnclipu.wi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 },
- { "vnclip.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
- { "vnclip.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
- { "vnclip.wi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 },
- { "vfadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
- { "vfadd.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
- { "vfsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
- { "vfsub.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
- { "vfrsub.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
- { "vfwadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
- { "vfwadd.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
- { "vfwadd.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
- { "vfwadd.wf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
- { "vfwsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
- { "vfwsub.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
- { "vfwsub.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
- { "vfwsub.wf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
- { "vfmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
- { "vfmul.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
- { "vfdiv.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
- { "vfdiv.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
- { "vfrdiv.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
- { "vfwmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
- { "vfwmul.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
- { "vfmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 },
- { "vfmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 },
- { "vfnmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 },
- { "vfnmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 },
- { "vfmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 },
- { "vfmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 },
- { "vfnmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 },
- { "vfnmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 },
- { "vfmadd.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 },
- { "vfmadd.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 },
- { "vfnmadd.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 },
- { "vfnmadd.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 },
- { "vfmsub.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 },
- { "vfmsub.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 },
- { "vfnmsub.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 },
- { "vfnmsub.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 },
- { "vfwmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 },
- { "vfwmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 },
- { "vfwnmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 },
- { "vfwnmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 },
- { "vfwmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 },
- { "vfwmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 },
- { "vfwnmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 },
- { "vfwnmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 },
- { "vfsqrt.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
- { "vfrsqrt7.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
- { "vfrec7.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
- { "vfmin.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
- { "vfmin.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
- { "vfmax.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
- { "vfmax.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
- { "vfsgnj.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
- { "vfsgnj.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
- { "vfsgnjn.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
- { "vfsgnjn.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
- { "vfsgnjx.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
- { "vfsgnjx.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
- { "vfslide1up.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
- { "vfslide1down.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
- { "vmfeq.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
- { "vmfeq.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
- { "vmfne.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
- { "vmfne.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
- { "vmflt.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
- { "vmflt.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
- { "vmfle.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
- { "vmfle.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
- { "vmfgt.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
- { "vmfge.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
- { "vfclass.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
- { "vfmerge.vfm", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vl, NULL, 0, 0, 0 },
- { "vfmv.v.f", rv_codec_v_r, rv_fmt_vd_fs1, NULL, 0, 0, 0 },
- { "vfcvt.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
- { "vfcvt.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
- { "vfcvt.f.xu.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
- { "vfcvt.f.x.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
- { "vfcvt.rtz.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
- { "vfcvt.rtz.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
- { "vfwcvt.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
- { "vfwcvt.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
- { "vfwcvt.f.xu.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
- { "vfwcvt.f.x.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
- { "vfwcvt.f.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
- { "vfwcvt.rtz.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
- { "vfwcvt.rtz.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
- { "vfncvt.xu.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
- { "vfncvt.x.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
- { "vfncvt.f.xu.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
- { "vfncvt.f.x.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
- { "vfncvt.f.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
- { "vfncvt.rod.f.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
- { "vfncvt.rtz.xu.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
- { "vfncvt.rtz.x.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
- { "vredsum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
- { "vredand.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
- { "vredor.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
- { "vredxor.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
- { "vredminu.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
- { "vredmin.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
- { "vredmaxu.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
- { "vredmax.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
- { "vwredsumu.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
- { "vwredsum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
- { "vfredusum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
- { "vfredosum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
- { "vfredmin.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
- { "vfredmax.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
- { "vfwredusum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
- { "vfwredosum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
- { "vmand.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
- { "vmnand.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
- { "vmandn.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
- { "vmxor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
- { "vmor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
- { "vmnor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
- { "vmorn.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
- { "vmxnor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
- { "vcpop.m", rv_codec_v_r, rv_fmt_rd_vs2_vm, NULL, 0, 0, 0 },
- { "vfirst.m", rv_codec_v_r, rv_fmt_rd_vs2_vm, NULL, 0, 0, 0 },
- { "vmsbf.m", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
- { "vmsif.m", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
- { "vmsof.m", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
- { "viota.m", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
- { "vid.v", rv_codec_v_r, rv_fmt_vd_vm, NULL, 0, 0, 0 },
- { "vmv.x.s", rv_codec_v_r, rv_fmt_rd_vs2, NULL, 0, 0, 0 },
- { "vmv.s.x", rv_codec_v_r, rv_fmt_vd_rs1, NULL, 0, 0, 0 },
- { "vfmv.f.s", rv_codec_v_r, rv_fmt_fd_vs2, NULL, 0, 0, 0 },
- { "vfmv.s.f", rv_codec_v_r, rv_fmt_vd_fs1, NULL, 0, 0, 0 },
- { "vslideup.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
- { "vslideup.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 },
- { "vslide1up.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
- { "vslidedown.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
- { "vslidedown.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 },
- { "vslide1down.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
- { "vrgather.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
- { "vrgatherei16.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
- { "vrgather.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
- { "vrgather.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 },
- { "vcompress.vm", rv_codec_v_r, rv_fmt_vd_vs2_vs1, NULL, 0, 0, 0 },
- { "vmv1r.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
- { "vmv2r.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
- { "vmv4r.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
- { "vmv8r.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
- { "vzext.vf2", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
- { "vzext.vf4", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
- { "vzext.vf8", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
- { "vsext.vf2", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
- { "vsext.vf4", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
- { "vsext.vf8", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
- { "vsetvli", rv_codec_vsetvli, rv_fmt_vsetvli, NULL, 0, 0, 0 },
- { "vsetivli", rv_codec_vsetivli, rv_fmt_vsetivli, NULL, 0, 0, 0 },
- { "vsetvl", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
- { "c.zext.b", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 },
- { "c.sext.b", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 },
- { "c.zext.h", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 },
- { "c.sext.h", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 },
- { "c.zext.w", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 },
- { "c.not", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 },
- { "c.mul", rv_codec_zcb_mul, rv_fmt_rd_rs2, NULL, 0, 0 },
- { "c.lbu", rv_codec_zcb_lb, rv_fmt_rs1_rs2_zce_ldst, NULL, 0, 0, 0 },
- { "c.lhu", rv_codec_zcb_lh, rv_fmt_rs1_rs2_zce_ldst, NULL, 0, 0, 0 },
- { "c.lh", rv_codec_zcb_lh, rv_fmt_rs1_rs2_zce_ldst, NULL, 0, 0, 0 },
- { "c.sb", rv_codec_zcb_lb, rv_fmt_rs1_rs2_zce_ldst, NULL, 0, 0, 0 },
- { "c.sh", rv_codec_zcb_lh, rv_fmt_rs1_rs2_zce_ldst, NULL, 0, 0, 0 },
- { "cm.push", rv_codec_zcmp_cm_pushpop, rv_fmt_push_rlist, NULL, 0, 0 },
- { "cm.pop", rv_codec_zcmp_cm_pushpop, rv_fmt_pop_rlist, NULL, 0, 0 },
- { "cm.popret", rv_codec_zcmp_cm_pushpop, rv_fmt_pop_rlist, NULL, 0, 0, 0 },
- { "cm.popretz", rv_codec_zcmp_cm_pushpop, rv_fmt_pop_rlist, NULL, 0, 0 },
- { "cm.mva01s", rv_codec_zcmp_cm_mv, rv_fmt_rd_rs2, NULL, 0, 0, 0 },
- { "cm.mvsa01", rv_codec_zcmp_cm_mv, rv_fmt_rd_rs2, NULL, 0, 0, 0 },
- { "cm.jt", rv_codec_zcmt_jt, rv_fmt_zcmt_index, NULL, 0 },
- { "cm.jalt", rv_codec_zcmt_jt, rv_fmt_zcmt_index, NULL, 0 },
- { "czero.eqz", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
- { "czero.nez", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
- { "fcvt.bf16.s", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },
- { "fcvt.s.bf16", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },
- { "vfncvtbf16.f.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
- { "vfwcvtbf16.f.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
- { "vfwmaccbf16.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 },
- { "vfwmaccbf16.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 },
- { "flh", rv_codec_i, rv_fmt_frd_offset_rs1, NULL, 0, 0, 0 },
- { "fsh", rv_codec_s, rv_fmt_frs2_offset_rs1, NULL, 0, 0, 0 },
- { "fmv.h.x", rv_codec_r, rv_fmt_frd_rs1, NULL, 0, 0, 0 },
- { "fmv.x.h", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 },
- { "fli.s", rv_codec_fli, rv_fmt_fli, NULL, 0, 0, 0 },
- { "fli.d", rv_codec_fli, rv_fmt_fli, NULL, 0, 0, 0 },
- { "fli.q", rv_codec_fli, rv_fmt_fli, NULL, 0, 0, 0 },
- { "fli.h", rv_codec_fli, rv_fmt_fli, NULL, 0, 0, 0 },
- { "fminm.s", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 },
- { "fmaxm.s", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 },
- { "fminm.d", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 },
- { "fmaxm.d", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 },
- { "fminm.q", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 },
- { "fmaxm.q", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 },
- { "fminm.h", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 },
- { "fmaxm.h", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 },
- { "fround.s", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },
- { "froundnx.s", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },
- { "fround.d", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },
- { "froundnx.d", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },
- { "fround.q", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },
- { "froundnx.q", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },
- { "fround.h", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },
- { "froundnx.h", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },
- { "fcvtmod.w.d", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 },
- { "fmvh.x.d", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 },
- { "fmvp.d.x", rv_codec_r, rv_fmt_frd_rs1_rs2, NULL, 0, 0, 0 },
- { "fmvh.x.q", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 },
- { "fmvp.q.x", rv_codec_r, rv_fmt_frd_rs1_rs2, NULL, 0, 0, 0 },
- { "fleq.s", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 },
- { "fltq.s", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 },
- { "fleq.d", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 },
- { "fltq.d", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 },
- { "fleq.q", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 },
- { "fltq.q", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 },
- { "fleq.h", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 },
- { "fltq.h", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 },
- { "vaesdf.vv", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
- { "vaesdf.vs", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
- { "vaesdm.vv", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
- { "vaesdm.vs", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
- { "vaesef.vv", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
- { "vaesef.vs", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
- { "vaesem.vv", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
- { "vaesem.vs", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
- { "vaeskf1.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm, NULL, 0, 0, 0 },
- { "vaeskf2.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm, NULL, 0, 0, 0 },
- { "vaesz.vs", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
- { "vandn.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
- { "vandn.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
- { "vbrev.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
- { "vbrev8.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
- { "vclmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
- { "vclmul.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
- { "vclmulh.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
- { "vclmulh.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
- { "vclz.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
- { "vcpop.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
- { "vctz.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
- { "vghsh.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1, NULL, 0, 0, 0 },
- { "vgmul.vv", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
- { "vrev8.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
- { "vrol.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
- { "vrol.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
- { "vror.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
- { "vror.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
- { "vror.vi", rv_codec_vror_vi, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 },
- { "vsha2ch.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1, NULL, 0, 0, 0 },
- { "vsha2cl.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1, NULL, 0, 0, 0 },
- { "vsha2ms.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1, NULL, 0, 0, 0 },
- { "vsm3c.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm, NULL, 0, 0, 0 },
- { "vsm3me.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1, NULL, 0, 0, 0 },
- { "vsm4k.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm, NULL, 0, 0, 0 },
- { "vsm4r.vv", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
- { "vsm4r.vs", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
- { "vwsll.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
- { "vwsll.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
- { "vwsll.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 },
- { "amocas.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
- { "amocas.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
- { "amocas.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
- { "mop.r.0", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
- { "mop.r.1", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
- { "mop.r.2", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
- { "mop.r.3", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
- { "mop.r.4", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
- { "mop.r.5", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
- { "mop.r.6", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
- { "mop.r.7", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
- { "mop.r.8", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
- { "mop.r.9", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
- { "mop.r.10", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
- { "mop.r.11", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
- { "mop.r.12", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
- { "mop.r.13", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
- { "mop.r.14", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
- { "mop.r.15", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
- { "mop.r.16", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
- { "mop.r.17", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
- { "mop.r.18", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
- { "mop.r.19", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
- { "mop.r.20", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
- { "mop.r.21", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
- { "mop.r.22", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
- { "mop.r.23", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
- { "mop.r.24", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
- { "mop.r.25", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
- { "mop.r.26", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
- { "mop.r.27", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
- { "mop.r.28", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
- { "mop.r.29", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
- { "mop.r.30", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
- { "mop.r.31", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
- { "mop.rr.0", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
- { "mop.rr.1", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
- { "mop.rr.2", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
- { "mop.rr.3", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
- { "mop.rr.4", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
- { "mop.rr.5", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
- { "mop.rr.6", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
- { "mop.rr.7", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
- { "c.mop.1", rv_codec_ci_none, rv_fmt_none, NULL, 0, 0, 0 },
- { "c.mop.3", rv_codec_ci_none, rv_fmt_none, NULL, 0, 0, 0 },
- { "c.mop.5", rv_codec_ci_none, rv_fmt_none, NULL, 0, 0, 0 },
- { "c.mop.7", rv_codec_ci_none, rv_fmt_none, NULL, 0, 0, 0 },
- { "c.mop.9", rv_codec_ci_none, rv_fmt_none, NULL, 0, 0, 0 },
- { "c.mop.11", rv_codec_ci_none, rv_fmt_none, NULL, 0, 0, 0 },
- { "c.mop.13", rv_codec_ci_none, rv_fmt_none, NULL, 0, 0, 0 },
- { "c.mop.15", rv_codec_ci_none, rv_fmt_none, NULL, 0, 0, 0 },
- { "amoswap.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
- { "amoadd.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
- { "amoxor.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
- { "amoor.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
- { "amoand.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
- { "amomin.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
- { "amomax.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
- { "amominu.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
- { "amomaxu.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
- { "amoswap.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
- { "amoadd.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
- { "amoxor.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
- { "amoor.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
- { "amoand.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
- { "amomin.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
- { "amomax.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
- { "amominu.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
- { "amomaxu.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
- { "amocas.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
- { "amocas.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
- { "wrs.sto", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
- { "wrs.nto", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
- { "lpad", rv_codec_lp, rv_fmt_imm, NULL, 0, 0, 0 },
- { "sspush", rv_codec_r, rv_fmt_rs2, NULL, 0, 0, 0 },
- { "sspopchk", rv_codec_r, rv_fmt_rs1, NULL, 0, 0, 0 },
- { "ssrdp", rv_codec_r, rv_fmt_rd, NULL, 0, 0, 0 },
- { "ssamoswap.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
- { "ssamoswap.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
+ { "nop", rv_codec_i, rv_fmt_none },
+ { "mv", rv_codec_i, rv_fmt_rd_rs1 },
+ { "not", rv_codec_i, rv_fmt_rd_rs1 },
+ { "neg", rv_codec_r, rv_fmt_rd_rs2 },
+ { "negw", rv_codec_r, rv_fmt_rd_rs2 },
+ { "sext.w", rv_codec_i, rv_fmt_rd_rs1 },
+ { "seqz", rv_codec_i, rv_fmt_rd_rs1 },
+ { "snez", rv_codec_r, rv_fmt_rd_rs2 },
+ { "sltz", rv_codec_r, rv_fmt_rd_rs1 },
+ { "sgtz", rv_codec_r, rv_fmt_rd_rs2 },
+ { "fmv.s", rv_codec_r, rv_fmt_frd_frs1 },
+ { "fabs.s", rv_codec_r, rv_fmt_frd_frs1 },
+ { "fneg.s", rv_codec_r, rv_fmt_frd_frs1 },
+ { "fmv.d", rv_codec_r, rv_fmt_frd_frs1 },
+ { "fabs.d", rv_codec_r, rv_fmt_frd_frs1 },
+ { "fneg.d", rv_codec_r, rv_fmt_frd_frs1 },
+ { "fmv.q", rv_codec_r, rv_fmt_frd_frs1 },
+ { "fabs.q", rv_codec_r, rv_fmt_frd_frs1 },
+ { "fneg.q", rv_codec_r, rv_fmt_frd_frs1 },
+ { "beqz", rv_codec_sb, rv_fmt_rs1_offset },
+ { "bnez", rv_codec_sb, rv_fmt_rs1_offset },
+ { "blez", rv_codec_sb, rv_fmt_rs2_offset },
+ { "bgez", rv_codec_sb, rv_fmt_rs1_offset },
+ { "bltz", rv_codec_sb, rv_fmt_rs1_offset },
+ { "bgtz", rv_codec_sb, rv_fmt_rs2_offset },
+ { "ble", rv_codec_sb, rv_fmt_rs2_rs1_offset },
+ { "bleu", rv_codec_sb, rv_fmt_rs2_rs1_offset },
+ { "bgt", rv_codec_sb, rv_fmt_rs2_rs1_offset },
+ { "bgtu", rv_codec_sb, rv_fmt_rs2_rs1_offset },
+ { "j", rv_codec_uj, rv_fmt_offset },
+ { "ret", rv_codec_i, rv_fmt_none },
+ { "jr", rv_codec_i, rv_fmt_rs1 },
+ { "rdcycle", rv_codec_i_csr, rv_fmt_rd },
+ { "rdtime", rv_codec_i_csr, rv_fmt_rd },
+ { "rdinstret", rv_codec_i_csr, rv_fmt_rd },
+ { "rdcycleh", rv_codec_i_csr, rv_fmt_rd },
+ { "rdtimeh", rv_codec_i_csr, rv_fmt_rd },
+ { "rdinstreth", rv_codec_i_csr, rv_fmt_rd },
+ { "frcsr", rv_codec_i_csr, rv_fmt_rd },
+ { "frrm", rv_codec_i_csr, rv_fmt_rd },
+ { "frflags", rv_codec_i_csr, rv_fmt_rd },
+ { "fscsr", rv_codec_i_csr, rv_fmt_rd_rs1 },
+ { "fsrm", rv_codec_i_csr, rv_fmt_rd_rs1 },
+ { "fsflags", rv_codec_i_csr, rv_fmt_rd_rs1 },
+ { "fsrmi", rv_codec_i_csr, rv_fmt_rd_zimm },
+ { "fsflagsi", rv_codec_i_csr, rv_fmt_rd_zimm },
+ { "bseti", rv_codec_i_sh7, rv_fmt_rd_rs1_imm },
+ { "bclri", rv_codec_i_sh7, rv_fmt_rd_rs1_imm },
+ { "binvi", rv_codec_i_sh7, rv_fmt_rd_rs1_imm },
+ { "bexti", rv_codec_i_sh7, rv_fmt_rd_rs1_imm },
+ { "rori", rv_codec_i_sh7, rv_fmt_rd_rs1_imm },
+ { "clz", rv_codec_r, rv_fmt_rd_rs1 },
+ { "ctz", rv_codec_r, rv_fmt_rd_rs1 },
+ { "cpop", rv_codec_r, rv_fmt_rd_rs1 },
+ { "sext.h", rv_codec_r, rv_fmt_rd_rs1 },
+ { "sext.b", rv_codec_r, rv_fmt_rd_rs1 },
+ { "xnor", rv_codec_r, rv_fmt_rd_rs1_rs2 },
+ { "orn", rv_codec_r, rv_fmt_rd_rs1_rs2 },
+ { "andn", rv_codec_r, rv_fmt_rd_rs1_rs2 },
+ { "rol", rv_codec_r, rv_fmt_rd_rs1_rs2 },
+ { "ror", rv_codec_r, rv_fmt_rd_rs1_rs2 },
+ { "sh1add", rv_codec_r, rv_fmt_rd_rs1_rs2 },
+ { "sh2add", rv_codec_r, rv_fmt_rd_rs1_rs2 },
+ { "sh3add", rv_codec_r, rv_fmt_rd_rs1_rs2 },
+ { "sh1add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2 },
+ { "sh2add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2 },
+ { "sh3add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2 },
+ { "clmul", rv_codec_r, rv_fmt_rd_rs1_rs2 },
+ { "clmulr", rv_codec_r, rv_fmt_rd_rs1_rs2 },
+ { "clmulh", rv_codec_r, rv_fmt_rd_rs1_rs2 },
+ { "min", rv_codec_r, rv_fmt_rd_rs1_rs2 },
+ { "minu", rv_codec_r, rv_fmt_rd_rs1_rs2 },
+ { "max", rv_codec_r, rv_fmt_rd_rs1_rs2 },
+ { "maxu", rv_codec_r, rv_fmt_rd_rs1_rs2 },
+ { "clzw", rv_codec_r, rv_fmt_rd_rs1 },
+ { "ctzw", rv_codec_r, rv_fmt_rd_rs1 },
+ { "cpopw", rv_codec_r, rv_fmt_rd_rs1 },
+ { "slli.uw", rv_codec_i_sh6, rv_fmt_rd_rs1_imm },
+ { "add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2 },
+ { "rolw", rv_codec_r, rv_fmt_rd_rs1_rs2 },
+ { "rorw", rv_codec_r, rv_fmt_rd_rs1_rs2 },
+ { "rev8", rv_codec_r, rv_fmt_rd_rs1 },
+ { "zext.h", rv_codec_r, rv_fmt_rd_rs1 },
+ { "roriw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm },
+ { "orc.b", rv_codec_r, rv_fmt_rd_rs1 },
+ { "bset", rv_codec_r, rv_fmt_rd_rs1_rs2 },
+ { "bclr", rv_codec_r, rv_fmt_rd_rs1_rs2 },
+ { "binv", rv_codec_r, rv_fmt_rd_rs1_rs2 },
+ { "bext", rv_codec_r, rv_fmt_rd_rs1_rs2 },
+ { "aes32esmi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs },
+ { "aes32esi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs },
+ { "aes32dsmi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs },
+ { "aes32dsi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs },
+ { "aes64ks1i", rv_codec_k_rnum, rv_fmt_rd_rs1_rnum },
+ { "aes64ks2", rv_codec_r, rv_fmt_rd_rs1_rs2 },
+ { "aes64im", rv_codec_r, rv_fmt_rd_rs1 },
+ { "aes64esm", rv_codec_r, rv_fmt_rd_rs1_rs2 },
+ { "aes64es", rv_codec_r, rv_fmt_rd_rs1_rs2 },
+ { "aes64dsm", rv_codec_r, rv_fmt_rd_rs1_rs2 },
+ { "aes64ds", rv_codec_r, rv_fmt_rd_rs1_rs2 },
+ { "sha256sig0", rv_codec_r, rv_fmt_rd_rs1 },
+ { "sha256sig1", rv_codec_r, rv_fmt_rd_rs1 },
+ { "sha256sum0", rv_codec_r, rv_fmt_rd_rs1 },
+ { "sha256sum1", rv_codec_r, rv_fmt_rd_rs1 },
+ { "sha512sig0", rv_codec_r, rv_fmt_rd_rs1_rs2 },
+ { "sha512sig1", rv_codec_r, rv_fmt_rd_rs1_rs2 },
+ { "sha512sum0", rv_codec_r, rv_fmt_rd_rs1_rs2 },
+ { "sha512sum1", rv_codec_r, rv_fmt_rd_rs1_rs2 },
+ { "sha512sum0r", rv_codec_r, rv_fmt_rd_rs1_rs2 },
+ { "sha512sum1r", rv_codec_r, rv_fmt_rd_rs1_rs2 },
+ { "sha512sig0l", rv_codec_r, rv_fmt_rd_rs1_rs2 },
+ { "sha512sig0h", rv_codec_r, rv_fmt_rd_rs1_rs2 },
+ { "sha512sig1l", rv_codec_r, rv_fmt_rd_rs1_rs2 },
+ { "sha512sig1h", rv_codec_r, rv_fmt_rd_rs1_rs2 },
+ { "sm3p0", rv_codec_r, rv_fmt_rd_rs1 },
+ { "sm3p1", rv_codec_r, rv_fmt_rd_rs1 },
+ { "sm4ed", rv_codec_k_bs, rv_fmt_rs1_rs2_bs },
+ { "sm4ks", rv_codec_k_bs, rv_fmt_rs1_rs2_bs },
+ { "brev8", rv_codec_r, rv_fmt_rd_rs1 },
+ { "pack", rv_codec_r, rv_fmt_rd_rs1_rs2 },
+ { "packh", rv_codec_r, rv_fmt_rd_rs1_rs2 },
+ { "packw", rv_codec_r, rv_fmt_rd_rs1_rs2 },
+ { "unzip", rv_codec_r, rv_fmt_rd_rs1 },
+ { "zip", rv_codec_r, rv_fmt_rd_rs1 },
+ { "xperm4", rv_codec_r, rv_fmt_rd_rs1_rs2 },
+ { "xperm8", rv_codec_r, rv_fmt_rd_rs1 },
+ { "vle8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
+ { "vle16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
+ { "vle32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
+ { "vle64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
+ { "vse8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
+ { "vse16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
+ { "vse32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
+ { "vse64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
+ { "vlm.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
+ { "vsm.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
+ { "vlse8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm },
+ { "vlse16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm },
+ { "vlse32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm },
+ { "vlse64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm },
+ { "vsse8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm },
+ { "vsse16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm },
+ { "vsse32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm },
+ { "vsse64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm },
+ { "vluxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm },
+ { "vluxei16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm },
+ { "vluxei32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm },
+ { "vluxei64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm },
+ { "vloxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm },
+ { "vloxei16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm },
+ { "vloxei32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm },
+ { "vloxei64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm },
+ { "vsuxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm },
+ { "vsuxei16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm },
+ { "vsuxei32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm },
+ { "vsuxei64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm },
+ { "vsoxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm },
+ { "vsoxei16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm },
+ { "vsoxei32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm },
+ { "vsoxei64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm },
+ { "vle8ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
+ { "vle16ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
+ { "vle32ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
+ { "vle64ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
+ { "vl1re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
+ { "vl1re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
+ { "vl1re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
+ { "vl1re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
+ { "vl2re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
+ { "vl2re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
+ { "vl2re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
+ { "vl2re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
+ { "vl4re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
+ { "vl4re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
+ { "vl4re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
+ { "vl4re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
+ { "vl8re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
+ { "vl8re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
+ { "vl8re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
+ { "vl8re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
+ { "vs1r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
+ { "vs2r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
+ { "vs4r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
+ { "vs8r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
+ { "vadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
+ { "vadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
+ { "vadd.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm },
+ { "vsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
+ { "vsub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
+ { "vrsub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
+ { "vrsub.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm },
+ { "vwaddu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
+ { "vwaddu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
+ { "vwadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
+ { "vwadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
+ { "vwsubu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
+ { "vwsubu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
+ { "vwsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
+ { "vwsub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
+ { "vwaddu.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
+ { "vwaddu.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
+ { "vwadd.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
+ { "vwadd.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
+ { "vwsubu.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
+ { "vwsubu.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
+ { "vwsub.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
+ { "vwsub.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
+ { "vadc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl },
+ { "vadc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl },
+ { "vadc.vim", rv_codec_v_i, rv_fmt_vd_vs2_imm_vl },
+ { "vmadc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl },
+ { "vmadc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl },
+ { "vmadc.vim", rv_codec_v_i, rv_fmt_vd_vs2_imm_vl },
+ { "vsbc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl },
+ { "vsbc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl },
+ { "vmsbc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl },
+ { "vmsbc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl },
+ { "vand.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
+ { "vand.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
+ { "vand.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm },
+ { "vor.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
+ { "vor.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
+ { "vor.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm },
+ { "vxor.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
+ { "vxor.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
+ { "vxor.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm },
+ { "vsll.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
+ { "vsll.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
+ { "vsll.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm },
+ { "vsrl.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
+ { "vsrl.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
+ { "vsrl.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm },
+ { "vsra.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
+ { "vsra.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
+ { "vsra.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm },
+ { "vnsrl.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
+ { "vnsrl.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
+ { "vnsrl.wi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm },
+ { "vnsra.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
+ { "vnsra.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
+ { "vnsra.wi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm },
+ { "vmseq.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
+ { "vmseq.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
+ { "vmseq.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm },
+ { "vmsne.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
+ { "vmsne.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
+ { "vmsne.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm },
+ { "vmsltu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
+ { "vmsltu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
+ { "vmslt.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
+ { "vmslt.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
+ { "vmsleu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
+ { "vmsleu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
+ { "vmsleu.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm },
+ { "vmsle.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
+ { "vmsle.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
+ { "vmsle.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm },
+ { "vmsgtu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
+ { "vmsgtu.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm },
+ { "vmsgt.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
+ { "vmsgt.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm },
+ { "vminu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
+ { "vminu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
+ { "vmin.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
+ { "vmin.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
+ { "vmaxu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
+ { "vmaxu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
+ { "vmax.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
+ { "vmax.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
+ { "vmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
+ { "vmul.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
+ { "vmulh.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
+ { "vmulh.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
+ { "vmulhu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
+ { "vmulhu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
+ { "vmulhsu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
+ { "vmulhsu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
+ { "vdivu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
+ { "vdivu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
+ { "vdiv.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
+ { "vdiv.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
+ { "vremu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
+ { "vremu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
+ { "vrem.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
+ { "vrem.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
+ { "vwmulu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
+ { "vwmulu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
+ { "vwmulsu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
+ { "vwmulsu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
+ { "vwmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
+ { "vwmul.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
+ { "vmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm },
+ { "vmacc.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm },
+ { "vnmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm },
+ { "vnmsac.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm },
+ { "vmadd.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm },
+ { "vmadd.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm },
+ { "vnmsub.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm },
+ { "vnmsub.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm },
+ { "vwmaccu.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm },
+ { "vwmaccu.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm },
+ { "vwmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm },
+ { "vwmacc.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm },
+ { "vwmaccsu.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm },
+ { "vwmaccsu.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm },
+ { "vwmaccus.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm },
+ { "vmv.v.v", rv_codec_v_r, rv_fmt_vd_vs1 },
+ { "vmv.v.x", rv_codec_v_r, rv_fmt_vd_rs1 },
+ { "vmv.v.i", rv_codec_v_i, rv_fmt_vd_imm },
+ { "vmerge.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl },
+ { "vmerge.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl },
+ { "vmerge.vim", rv_codec_v_i, rv_fmt_vd_vs2_imm_vl },
+ { "vsaddu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
+ { "vsaddu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
+ { "vsaddu.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm },
+ { "vsadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
+ { "vsadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
+ { "vsadd.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm },
+ { "vssubu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
+ { "vssubu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
+ { "vssub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
+ { "vssub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
+ { "vaadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
+ { "vaadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
+ { "vaaddu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
+ { "vaaddu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
+ { "vasub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
+ { "vasub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
+ { "vasubu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
+ { "vasubu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
+ { "vsmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
+ { "vsmul.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
+ { "vssrl.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
+ { "vssrl.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
+ { "vssrl.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm },
+ { "vssra.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
+ { "vssra.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
+ { "vssra.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm },
+ { "vnclipu.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
+ { "vnclipu.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
+ { "vnclipu.wi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm },
+ { "vnclip.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
+ { "vnclip.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
+ { "vnclip.wi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm },
+ { "vfadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
+ { "vfadd.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm },
+ { "vfsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
+ { "vfsub.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm },
+ { "vfrsub.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm },
+ { "vfwadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
+ { "vfwadd.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm },
+ { "vfwadd.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
+ { "vfwadd.wf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm },
+ { "vfwsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
+ { "vfwsub.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm },
+ { "vfwsub.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
+ { "vfwsub.wf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm },
+ { "vfmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
+ { "vfmul.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm },
+ { "vfdiv.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
+ { "vfdiv.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm },
+ { "vfrdiv.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm },
+ { "vfwmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
+ { "vfwmul.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm },
+ { "vfmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm },
+ { "vfmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm },
+ { "vfnmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm },
+ { "vfnmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm },
+ { "vfmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm },
+ { "vfmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm },
+ { "vfnmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm },
+ { "vfnmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm },
+ { "vfmadd.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm },
+ { "vfmadd.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm },
+ { "vfnmadd.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm },
+ { "vfnmadd.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm },
+ { "vfmsub.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm },
+ { "vfmsub.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm },
+ { "vfnmsub.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm },
+ { "vfnmsub.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm },
+ { "vfwmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm },
+ { "vfwmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm },
+ { "vfwnmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm },
+ { "vfwnmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm },
+ { "vfwmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm },
+ { "vfwmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm },
+ { "vfwnmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm },
+ { "vfwnmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm },
+ { "vfsqrt.v", rv_codec_v_r, rv_fmt_vd_vs2 },
+ { "vfrsqrt7.v", rv_codec_v_r, rv_fmt_vd_vs2 },
+ { "vfrec7.v", rv_codec_v_r, rv_fmt_vd_vs2 },
+ { "vfmin.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
+ { "vfmin.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm },
+ { "vfmax.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
+ { "vfmax.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm },
+ { "vfsgnj.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
+ { "vfsgnj.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm },
+ { "vfsgnjn.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
+ { "vfsgnjn.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm },
+ { "vfsgnjx.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
+ { "vfsgnjx.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm },
+ { "vfslide1up.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm },
+ { "vfslide1down.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm },
+ { "vmfeq.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
+ { "vmfeq.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm },
+ { "vmfne.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
+ { "vmfne.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm },
+ { "vmflt.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
+ { "vmflt.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm },
+ { "vmfle.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
+ { "vmfle.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm },
+ { "vmfgt.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm },
+ { "vmfge.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm },
+ { "vfclass.v", rv_codec_v_r, rv_fmt_vd_vs2_vm },
+ { "vfmerge.vfm", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vl },
+ { "vfmv.v.f", rv_codec_v_r, rv_fmt_vd_fs1 },
+ { "vfcvt.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm },
+ { "vfcvt.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm },
+ { "vfcvt.f.xu.v", rv_codec_v_r, rv_fmt_vd_vs2_vm },
+ { "vfcvt.f.x.v", rv_codec_v_r, rv_fmt_vd_vs2_vm },
+ { "vfcvt.rtz.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm },
+ { "vfcvt.rtz.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm },
+ { "vfwcvt.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm },
+ { "vfwcvt.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm },
+ { "vfwcvt.f.xu.v", rv_codec_v_r, rv_fmt_vd_vs2_vm },
+ { "vfwcvt.f.x.v", rv_codec_v_r, rv_fmt_vd_vs2_vm },
+ { "vfwcvt.f.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm },
+ { "vfwcvt.rtz.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm },
+ { "vfwcvt.rtz.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm },
+ { "vfncvt.xu.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm },
+ { "vfncvt.x.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm },
+ { "vfncvt.f.xu.w", rv_codec_v_r, rv_fmt_vd_vs2_vm },
+ { "vfncvt.f.x.w", rv_codec_v_r, rv_fmt_vd_vs2_vm },
+ { "vfncvt.f.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm },
+ { "vfncvt.rod.f.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm },
+ { "vfncvt.rtz.xu.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm },
+ { "vfncvt.rtz.x.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm },
+ { "vredsum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
+ { "vredand.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
+ { "vredor.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
+ { "vredxor.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
+ { "vredminu.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
+ { "vredmin.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
+ { "vredmaxu.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
+ { "vredmax.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
+ { "vwredsumu.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
+ { "vwredsum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
+ { "vfredusum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
+ { "vfredosum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
+ { "vfredmin.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
+ { "vfredmax.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
+ { "vfwredusum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
+ { "vfwredosum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
+ { "vmand.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
+ { "vmnand.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
+ { "vmandn.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
+ { "vmxor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
+ { "vmor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
+ { "vmnor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
+ { "vmorn.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
+ { "vmxnor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
+ { "vcpop.m", rv_codec_v_r, rv_fmt_rd_vs2_vm },
+ { "vfirst.m", rv_codec_v_r, rv_fmt_rd_vs2_vm },
+ { "vmsbf.m", rv_codec_v_r, rv_fmt_vd_vs2_vm },
+ { "vmsif.m", rv_codec_v_r, rv_fmt_vd_vs2_vm },
+ { "vmsof.m", rv_codec_v_r, rv_fmt_vd_vs2_vm },
+ { "viota.m", rv_codec_v_r, rv_fmt_vd_vs2_vm },
+ { "vid.v", rv_codec_v_r, rv_fmt_vd_vm },
+ { "vmv.x.s", rv_codec_v_r, rv_fmt_rd_vs2 },
+ { "vmv.s.x", rv_codec_v_r, rv_fmt_vd_rs1 },
+ { "vfmv.f.s", rv_codec_v_r, rv_fmt_fd_vs2 },
+ { "vfmv.s.f", rv_codec_v_r, rv_fmt_vd_fs1 },
+ { "vslideup.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
+ { "vslideup.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm },
+ { "vslide1up.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
+ { "vslidedown.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
+ { "vslidedown.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm },
+ { "vslide1down.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
+ { "vrgather.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
+ { "vrgatherei16.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
+ { "vrgather.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
+ { "vrgather.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm },
+ { "vcompress.vm", rv_codec_v_r, rv_fmt_vd_vs2_vs1 },
+ { "vmv1r.v", rv_codec_v_r, rv_fmt_vd_vs2 },
+ { "vmv2r.v", rv_codec_v_r, rv_fmt_vd_vs2 },
+ { "vmv4r.v", rv_codec_v_r, rv_fmt_vd_vs2 },
+ { "vmv8r.v", rv_codec_v_r, rv_fmt_vd_vs2 },
+ { "vzext.vf2", rv_codec_v_r, rv_fmt_vd_vs2_vm },
+ { "vzext.vf4", rv_codec_v_r, rv_fmt_vd_vs2_vm },
+ { "vzext.vf8", rv_codec_v_r, rv_fmt_vd_vs2_vm },
+ { "vsext.vf2", rv_codec_v_r, rv_fmt_vd_vs2_vm },
+ { "vsext.vf4", rv_codec_v_r, rv_fmt_vd_vs2_vm },
+ { "vsext.vf8", rv_codec_v_r, rv_fmt_vd_vs2_vm },
+ { "vsetvli", rv_codec_vsetvli, rv_fmt_vsetvli },
+ { "vsetivli", rv_codec_vsetivli, rv_fmt_vsetivli },
+ { "vsetvl", rv_codec_r, rv_fmt_rd_rs1_rs2 },
+ { "c.zext.b", rv_codec_zcb_ext, rv_fmt_rd },
+ { "c.sext.b", rv_codec_zcb_ext, rv_fmt_rd },
+ { "c.zext.h", rv_codec_zcb_ext, rv_fmt_rd },
+ { "c.sext.h", rv_codec_zcb_ext, rv_fmt_rd },
+ { "c.zext.w", rv_codec_zcb_ext, rv_fmt_rd },
+ { "c.not", rv_codec_zcb_ext, rv_fmt_rd },
+ { "c.mul", rv_codec_zcb_mul, rv_fmt_rd_rs2 },
+ { "c.lbu", rv_codec_zcb_lb, rv_fmt_rs1_rs2_zce_ldst },
+ { "c.lhu", rv_codec_zcb_lh, rv_fmt_rs1_rs2_zce_ldst },
+ { "c.lh", rv_codec_zcb_lh, rv_fmt_rs1_rs2_zce_ldst },
+ { "c.sb", rv_codec_zcb_lb, rv_fmt_rs1_rs2_zce_ldst },
+ { "c.sh", rv_codec_zcb_lh, rv_fmt_rs1_rs2_zce_ldst },
+ { "cm.push", rv_codec_zcmp_cm_pushpop, rv_fmt_push_rlist },
+ { "cm.pop", rv_codec_zcmp_cm_pushpop, rv_fmt_pop_rlist },
+ { "cm.popret", rv_codec_zcmp_cm_pushpop, rv_fmt_pop_rlist },
+ { "cm.popretz", rv_codec_zcmp_cm_pushpop, rv_fmt_pop_rlist },
+ { "cm.mva01s", rv_codec_zcmp_cm_mv, rv_fmt_rd_rs2 },
+ { "cm.mvsa01", rv_codec_zcmp_cm_mv, rv_fmt_rd_rs2 },
+ { "cm.jt", rv_codec_zcmt_jt, rv_fmt_zcmt_index },
+ { "cm.jalt", rv_codec_zcmt_jt, rv_fmt_zcmt_index },
+ { "czero.eqz", rv_codec_r, rv_fmt_rd_rs1_rs2 },
+ { "czero.nez", rv_codec_r, rv_fmt_rd_rs1_rs2 },
+ { "fcvt.bf16.s", rv_codec_r_m, rv_fmt_rm_frd_frs1 },
+ { "fcvt.s.bf16", rv_codec_r_m, rv_fmt_rm_frd_frs1 },
+ { "vfncvtbf16.f.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm },
+ { "vfwcvtbf16.f.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm },
+ { "vfwmaccbf16.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm },
+ { "vfwmaccbf16.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm },
+ { "flh", rv_codec_i, rv_fmt_frd_offset_rs1 },
+ { "fsh", rv_codec_s, rv_fmt_frs2_offset_rs1 },
+ { "fmv.h.x", rv_codec_r, rv_fmt_frd_rs1 },
+ { "fmv.x.h", rv_codec_r, rv_fmt_rd_frs1 },
+ { "fli.s", rv_codec_fli, rv_fmt_fli },
+ { "fli.d", rv_codec_fli, rv_fmt_fli },
+ { "fli.q", rv_codec_fli, rv_fmt_fli },
+ { "fli.h", rv_codec_fli, rv_fmt_fli },
+ { "fminm.s", rv_codec_r, rv_fmt_frd_frs1_frs2 },
+ { "fmaxm.s", rv_codec_r, rv_fmt_frd_frs1_frs2 },
+ { "fminm.d", rv_codec_r, rv_fmt_frd_frs1_frs2 },
+ { "fmaxm.d", rv_codec_r, rv_fmt_frd_frs1_frs2 },
+ { "fminm.q", rv_codec_r, rv_fmt_frd_frs1_frs2 },
+ { "fmaxm.q", rv_codec_r, rv_fmt_frd_frs1_frs2 },
+ { "fminm.h", rv_codec_r, rv_fmt_frd_frs1_frs2 },
+ { "fmaxm.h", rv_codec_r, rv_fmt_frd_frs1_frs2 },
+ { "fround.s", rv_codec_r_m, rv_fmt_rm_frd_frs1 },
+ { "froundnx.s", rv_codec_r_m, rv_fmt_rm_frd_frs1 },
+ { "fround.d", rv_codec_r_m, rv_fmt_rm_frd_frs1 },
+ { "froundnx.d", rv_codec_r_m, rv_fmt_rm_frd_frs1 },
+ { "fround.q", rv_codec_r_m, rv_fmt_rm_frd_frs1 },
+ { "froundnx.q", rv_codec_r_m, rv_fmt_rm_frd_frs1 },
+ { "fround.h", rv_codec_r_m, rv_fmt_rm_frd_frs1 },
+ { "froundnx.h", rv_codec_r_m, rv_fmt_rm_frd_frs1 },
+ { "fcvtmod.w.d", rv_codec_r_m, rv_fmt_rm_rd_frs1 },
+ { "fmvh.x.d", rv_codec_r, rv_fmt_rd_frs1 },
+ { "fmvp.d.x", rv_codec_r, rv_fmt_frd_rs1_rs2 },
+ { "fmvh.x.q", rv_codec_r, rv_fmt_rd_frs1 },
+ { "fmvp.q.x", rv_codec_r, rv_fmt_frd_rs1_rs2 },
+ { "fleq.s", rv_codec_r, rv_fmt_rd_frs1_frs2 },
+ { "fltq.s", rv_codec_r, rv_fmt_rd_frs1_frs2 },
+ { "fleq.d", rv_codec_r, rv_fmt_rd_frs1_frs2 },
+ { "fltq.d", rv_codec_r, rv_fmt_rd_frs1_frs2 },
+ { "fleq.q", rv_codec_r, rv_fmt_rd_frs1_frs2 },
+ { "fltq.q", rv_codec_r, rv_fmt_rd_frs1_frs2 },
+ { "fleq.h", rv_codec_r, rv_fmt_rd_frs1_frs2 },
+ { "fltq.h", rv_codec_r, rv_fmt_rd_frs1_frs2 },
+ { "vaesdf.vv", rv_codec_v_r, rv_fmt_vd_vs2 },
+ { "vaesdf.vs", rv_codec_v_r, rv_fmt_vd_vs2 },
+ { "vaesdm.vv", rv_codec_v_r, rv_fmt_vd_vs2 },
+ { "vaesdm.vs", rv_codec_v_r, rv_fmt_vd_vs2 },
+ { "vaesef.vv", rv_codec_v_r, rv_fmt_vd_vs2 },
+ { "vaesef.vs", rv_codec_v_r, rv_fmt_vd_vs2 },
+ { "vaesem.vv", rv_codec_v_r, rv_fmt_vd_vs2 },
+ { "vaesem.vs", rv_codec_v_r, rv_fmt_vd_vs2 },
+ { "vaeskf1.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm },
+ { "vaeskf2.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm },
+ { "vaesz.vs", rv_codec_v_r, rv_fmt_vd_vs2 },
+ { "vandn.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
+ { "vandn.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
+ { "vbrev.v", rv_codec_v_r, rv_fmt_vd_vs2_vm },
+ { "vbrev8.v", rv_codec_v_r, rv_fmt_vd_vs2_vm },
+ { "vclmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
+ { "vclmul.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
+ { "vclmulh.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
+ { "vclmulh.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
+ { "vclz.v", rv_codec_v_r, rv_fmt_vd_vs2_vm },
+ { "vcpop.v", rv_codec_v_r, rv_fmt_vd_vs2_vm },
+ { "vctz.v", rv_codec_v_r, rv_fmt_vd_vs2_vm },
+ { "vghsh.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1 },
+ { "vgmul.vv", rv_codec_v_r, rv_fmt_vd_vs2 },
+ { "vrev8.v", rv_codec_v_r, rv_fmt_vd_vs2_vm },
+ { "vrol.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
+ { "vrol.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
+ { "vror.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
+ { "vror.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
+ { "vror.vi", rv_codec_vror_vi, rv_fmt_vd_vs2_uimm_vm },
+ { "vsha2ch.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1 },
+ { "vsha2cl.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1 },
+ { "vsha2ms.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1 },
+ { "vsm3c.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm },
+ { "vsm3me.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1 },
+ { "vsm4k.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm },
+ { "vsm4r.vv", rv_codec_v_r, rv_fmt_vd_vs2 },
+ { "vsm4r.vs", rv_codec_v_r, rv_fmt_vd_vs2 },
+ { "vwsll.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
+ { "vwsll.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
+ { "vwsll.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm },
+ { "amocas.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
+ { "amocas.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
+ { "amocas.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
+ { "mop.r.0", rv_codec_r, rv_fmt_rd_rs1 },
+ { "mop.r.1", rv_codec_r, rv_fmt_rd_rs1 },
+ { "mop.r.2", rv_codec_r, rv_fmt_rd_rs1 },
+ { "mop.r.3", rv_codec_r, rv_fmt_rd_rs1 },
+ { "mop.r.4", rv_codec_r, rv_fmt_rd_rs1 },
+ { "mop.r.5", rv_codec_r, rv_fmt_rd_rs1 },
+ { "mop.r.6", rv_codec_r, rv_fmt_rd_rs1 },
+ { "mop.r.7", rv_codec_r, rv_fmt_rd_rs1 },
+ { "mop.r.8", rv_codec_r, rv_fmt_rd_rs1 },
+ { "mop.r.9", rv_codec_r, rv_fmt_rd_rs1 },
+ { "mop.r.10", rv_codec_r, rv_fmt_rd_rs1 },
+ { "mop.r.11", rv_codec_r, rv_fmt_rd_rs1 },
+ { "mop.r.12", rv_codec_r, rv_fmt_rd_rs1 },
+ { "mop.r.13", rv_codec_r, rv_fmt_rd_rs1 },
+ { "mop.r.14", rv_codec_r, rv_fmt_rd_rs1 },
+ { "mop.r.15", rv_codec_r, rv_fmt_rd_rs1 },
+ { "mop.r.16", rv_codec_r, rv_fmt_rd_rs1 },
+ { "mop.r.17", rv_codec_r, rv_fmt_rd_rs1 },
+ { "mop.r.18", rv_codec_r, rv_fmt_rd_rs1 },
+ { "mop.r.19", rv_codec_r, rv_fmt_rd_rs1 },
+ { "mop.r.20", rv_codec_r, rv_fmt_rd_rs1 },
+ { "mop.r.21", rv_codec_r, rv_fmt_rd_rs1 },
+ { "mop.r.22", rv_codec_r, rv_fmt_rd_rs1 },
+ { "mop.r.23", rv_codec_r, rv_fmt_rd_rs1 },
+ { "mop.r.24", rv_codec_r, rv_fmt_rd_rs1 },
+ { "mop.r.25", rv_codec_r, rv_fmt_rd_rs1 },
+ { "mop.r.26", rv_codec_r, rv_fmt_rd_rs1 },
+ { "mop.r.27", rv_codec_r, rv_fmt_rd_rs1 },
+ { "mop.r.28", rv_codec_r, rv_fmt_rd_rs1 },
+ { "mop.r.29", rv_codec_r, rv_fmt_rd_rs1 },
+ { "mop.r.30", rv_codec_r, rv_fmt_rd_rs1 },
+ { "mop.r.31", rv_codec_r, rv_fmt_rd_rs1 },
+ { "mop.rr.0", rv_codec_r, rv_fmt_rd_rs1_rs2 },
+ { "mop.rr.1", rv_codec_r, rv_fmt_rd_rs1_rs2 },
+ { "mop.rr.2", rv_codec_r, rv_fmt_rd_rs1_rs2 },
+ { "mop.rr.3", rv_codec_r, rv_fmt_rd_rs1_rs2 },
+ { "mop.rr.4", rv_codec_r, rv_fmt_rd_rs1_rs2 },
+ { "mop.rr.5", rv_codec_r, rv_fmt_rd_rs1_rs2 },
+ { "mop.rr.6", rv_codec_r, rv_fmt_rd_rs1_rs2 },
+ { "mop.rr.7", rv_codec_r, rv_fmt_rd_rs1_rs2 },
+ { "c.mop.1", rv_codec_ci_none, rv_fmt_none },
+ { "c.mop.3", rv_codec_ci_none, rv_fmt_none },
+ { "c.mop.5", rv_codec_ci_none, rv_fmt_none },
+ { "c.mop.7", rv_codec_ci_none, rv_fmt_none },
+ { "c.mop.9", rv_codec_ci_none, rv_fmt_none },
+ { "c.mop.11", rv_codec_ci_none, rv_fmt_none },
+ { "c.mop.13", rv_codec_ci_none, rv_fmt_none },
+ { "c.mop.15", rv_codec_ci_none, rv_fmt_none },
+ { "amoswap.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
+ { "amoadd.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
+ { "amoxor.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
+ { "amoor.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
+ { "amoand.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
+ { "amomin.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
+ { "amomax.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
+ { "amominu.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
+ { "amomaxu.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
+ { "amoswap.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
+ { "amoadd.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
+ { "amoxor.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
+ { "amoor.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
+ { "amoand.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
+ { "amomin.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
+ { "amomax.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
+ { "amominu.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
+ { "amomaxu.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
+ { "amocas.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
+ { "amocas.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
+ { "wrs.sto", rv_codec_none, rv_fmt_none },
+ { "wrs.nto", rv_codec_none, rv_fmt_none },
+ { "lpad", rv_codec_lp, rv_fmt_imm },
+ { "sspush", rv_codec_r, rv_fmt_rs2 },
+ { "sspopchk", rv_codec_r, rv_fmt_rs1 },
+ { "ssrdp", rv_codec_r, rv_fmt_rd },
+ { "ssamoswap.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
+ { "ssamoswap.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
{ "c.sspush", rv_codec_cmop_ss, rv_fmt_rs2, NULL, rv_op_sspush,
rv_op_sspush, 0 },
{ "c.sspopchk", rv_codec_cmop_ss, rv_fmt_rs1, NULL, rv_op_sspopchk,
rv_op_sspopchk, 0 },
- { "cbo.inval", rv_codec_r, rv_fmt_rs1, NULL, 0, 0, 0 },
- { "cbo.clean", rv_codec_r, rv_fmt_rs1, NULL, 0, 0, 0 },
- { "cbo.flush", rv_codec_r, rv_fmt_rs1, NULL, 0, 0, 0 },
- { "cbo.zero", rv_codec_r, rv_fmt_rs1, NULL, 0, 0, 0 },
- { "mnret", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
+ { "cbo.inval", rv_codec_r, rv_fmt_rs1 },
+ { "cbo.clean", rv_codec_r, rv_fmt_rs1 },
+ { "cbo.flush", rv_codec_r, rv_fmt_rs1 },
+ { "cbo.zero", rv_codec_r, rv_fmt_rs1 },
+ { "mnret", rv_codec_none, rv_fmt_none },
};
/* CSR names */
--
2.43.0
^ permalink raw reply related [flat|nested] 119+ messages in thread
* [PATCH 16/56] disas/riscv: Drop useless const in structures
2026-08-09 22:34 [RFC PATCH 00/56] disas/riscv: Reorganize the disassembler Richard Henderson
` (14 preceding siblings ...)
2026-08-09 22:35 ` [PATCH 15/56] disas/riscv: Drop explicit zero of rv_opcode_data fields Richard Henderson
@ 2026-08-09 22:35 ` Richard Henderson
2026-08-10 2:55 ` Philippe Mathieu-Daudé
2026-08-11 20:10 ` Alistair
2026-08-09 22:35 ` [PATCH 17/56] disas/riscv: Drop codec from rv_decode Richard Henderson
` (39 subsequent siblings)
55 siblings, 2 replies; 119+ messages in thread
From: Richard Henderson @ 2026-08-09 22:35 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-riscv
Individual fields should not be const, only full structures.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
disas/riscv.h | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/disas/riscv.h b/disas/riscv.h
index eabe193b4f..3325b7b4ef 100644
--- a/disas/riscv.h
+++ b/disas/riscv.h
@@ -174,19 +174,19 @@ typedef enum {
/* structures */
typedef struct {
- const int op;
+ int op;
const rvc_constraint *constraints;
} rv_comp_data;
typedef struct {
- const char * const name;
- const rv_codec codec;
- const char * const format;
+ const char *name;
+ rv_codec codec;
+ const char *format;
const rv_comp_data *pseudo;
- const short decomp_rv32;
- const short decomp_rv64;
- const short decomp_rv128;
- const short decomp_data;
+ short decomp_rv32;
+ short decomp_rv64;
+ short decomp_rv128;
+ short decomp_data;
} rv_opcode_data;
typedef struct {
--
2.43.0
^ permalink raw reply related [flat|nested] 119+ messages in thread
* [PATCH 17/56] disas/riscv: Drop codec from rv_decode
2026-08-09 22:34 [RFC PATCH 00/56] disas/riscv: Reorganize the disassembler Richard Henderson
` (15 preceding siblings ...)
2026-08-09 22:35 ` [PATCH 16/56] disas/riscv: Drop useless const in structures Richard Henderson
@ 2026-08-09 22:35 ` Richard Henderson
2026-08-11 20:11 ` Alistair
2026-08-09 22:35 ` [PATCH 18/56] disas/riscv: Handle c.addi4spn imm != 0 during decode Richard Henderson
` (38 subsequent siblings)
55 siblings, 1 reply; 119+ messages in thread
From: Richard Henderson @ 2026-08-09 22:35 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-riscv
This is mostly write-only, only used in one place;
other updates are ignored.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
disas/riscv.h | 1 -
disas/riscv.c | 7 +++----
2 files changed, 3 insertions(+), 5 deletions(-)
diff --git a/disas/riscv.h b/disas/riscv.h
index 3325b7b4ef..31bb0db86c 100644
--- a/disas/riscv.h
+++ b/disas/riscv.h
@@ -197,7 +197,6 @@ typedef struct {
int32_t imm;
int32_t imm1;
uint16_t op;
- uint8_t codec;
uint8_t rd;
uint8_t rs1;
uint8_t rs2;
diff --git a/disas/riscv.c b/disas/riscv.c
index ec40abb618..9813d75feb 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -4603,8 +4603,9 @@ static void decode_inst_operands(rv_decode *dec, rv_isa isa,
{
rv_inst inst = dec->inst;
- dec->codec = op->codec;
- switch (dec->codec) {
+ switch (op->codec) {
+ case rv_codec_illegal:
+ break;
case rv_codec_none:
dec->rd = dec->rs1 = dec->rs2 = rv_ireg_zero;
dec->imm = 0;
@@ -5369,7 +5370,6 @@ static const rv_opcode_data *decode_inst_lift_pseudo(rv_decode *dec,
if (check_constraints(dec, comp_data->constraints)) {
dec->op = comp_data->op;
op = &dec->opcode_data[dec->op];
- dec->codec = op->codec;
break;
}
comp_data++;
@@ -5407,7 +5407,6 @@ static const rv_opcode_data *decode_inst_decompress(rv_decode *dec, rv_isa isa,
dec->op = decomp_op;
}
op = &dec->opcode_data[decomp_op];
- dec->codec = op->codec;
}
return op;
}
--
2.43.0
^ permalink raw reply related [flat|nested] 119+ messages in thread
* [PATCH 18/56] disas/riscv: Handle c.addi4spn imm != 0 during decode
2026-08-09 22:34 [RFC PATCH 00/56] disas/riscv: Reorganize the disassembler Richard Henderson
` (16 preceding siblings ...)
2026-08-09 22:35 ` [PATCH 17/56] disas/riscv: Drop codec from rv_decode Richard Henderson
@ 2026-08-09 22:35 ` Richard Henderson
2026-08-11 20:12 ` Alistair
2026-08-09 22:35 ` [PATCH 19/56] disas/riscv: Simplify c.addi Richard Henderson
` (37 subsequent siblings)
55 siblings, 1 reply; 119+ messages in thread
From: Richard Henderson @ 2026-08-09 22:35 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-riscv
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
disas/riscv.c | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/disas/riscv.c b/disas/riscv.c
index 9813d75feb..8a957e6a1e 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -1885,7 +1885,7 @@ static const rv_opcode_data rvi_opcode_data[] = {
{ "fmv.x.q", rv_codec_r, rv_fmt_rd_frs1 },
{ "fmv.q.x", rv_codec_r, rv_fmt_frd_rs1 },
{ "c.addi4spn", rv_codec_ciw_4spn, rv_fmt_rd_rs1_imm, NULL, rv_op_addi,
- rv_op_addi, rv_op_addi, rvcd_imm_nz },
+ rv_op_addi, rv_op_addi },
{ "c.fld", rv_codec_cl_ld, rv_fmt_frd_offset_rs1, NULL, rv_op_fld,
rv_op_fld, 0 },
{ "c.lw", rv_codec_cl_lw, rv_fmt_rd_offset_rs1, NULL, rv_op_lw, rv_op_lw,
@@ -2952,7 +2952,11 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
switch ((inst >> 0) & 0b11) {
case 0:
switch ((inst >> 13) & 0b111) {
- case 0: op = rv_op_c_addi4spn; break;
+ case 0:
+ if ((inst >> 5) & 0xff) {
+ op = rv_op_c_addi4spn;
+ }
+ break;
case 1:
if (isa == rv128) {
op = rv_op_c_lq;
--
2.43.0
^ permalink raw reply related [flat|nested] 119+ messages in thread
* [PATCH 19/56] disas/riscv: Simplify c.addi
2026-08-09 22:34 [RFC PATCH 00/56] disas/riscv: Reorganize the disassembler Richard Henderson
` (17 preceding siblings ...)
2026-08-09 22:35 ` [PATCH 18/56] disas/riscv: Handle c.addi4spn imm != 0 during decode Richard Henderson
@ 2026-08-09 22:35 ` Richard Henderson
2026-08-11 20:14 ` Alistair
2026-08-09 22:35 ` [PATCH 20/56] disas/riscv: Handle c.lui imm != 0 during decode Richard Henderson
` (36 subsequent siblings)
55 siblings, 1 reply; 119+ messages in thread
From: Richard Henderson @ 2026-08-09 22:35 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-riscv
While c.addi with imm == 0 and rd == 0 is c.nop,
other c.addi with imm == 0 and rd != 0 are not illegal,
but are reserved as HINTs. Go ahead and disassemble as
c.addi rather than falling back to invalid.
Further, there's no reason to differentiate c.nop, since we have
c.addi -> addi -> nop
vs
c.nop -> addi -> nop
via decompress and pseudo translation steps.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
disas/riscv.c | 11 +++--------
1 file changed, 3 insertions(+), 8 deletions(-)
diff --git a/disas/riscv.c b/disas/riscv.c
index 8a957e6a1e..7978ffb378 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -263,7 +263,6 @@ typedef enum {
rv_op_c_fsd = 231,
rv_op_c_sw = 232,
rv_op_c_fsw = 233,
- rv_op_c_nop = 234,
rv_op_c_addi = 235,
rv_op_c_jal = 236,
rv_op_c_li = 237,
@@ -1896,10 +1895,9 @@ static const rv_opcode_data rvi_opcode_data[] = {
{ "c.sw", rv_codec_cs_sw, rv_fmt_rs2_offset_rs1, NULL, rv_op_sw, rv_op_sw,
rv_op_sw },
{ "c.fsw", rv_codec_cs_sw, rv_fmt_frs2_offset_rs1, NULL, rv_op_fsw, 0, 0 },
- { "c.nop", rv_codec_ci_none, rv_fmt_none, NULL, rv_op_addi, rv_op_addi,
- rv_op_addi },
+ { },
{ "c.addi", rv_codec_ci, rv_fmt_rd_rs1_imm, NULL, rv_op_addi, rv_op_addi,
- rv_op_addi, rvcd_imm_nz },
+ rv_op_addi },
{ "c.jal", rv_codec_cj_jal, rv_fmt_rd_offset, NULL, rv_op_jal, 0, 0 },
{ "c.li", rv_codec_ci_li, rv_fmt_rd_rs1_imm, NULL, rv_op_addi, rv_op_addi,
rv_op_addi },
@@ -3010,10 +3008,7 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
case 1:
switch ((inst >> 13) & 0b111) {
case 0:
- switch ((inst >> 2) & 0b11111111111) {
- case 0: op = rv_op_c_nop; break;
- default: op = rv_op_c_addi; break;
- }
+ op = rv_op_c_addi; /* or unspecified HINT */
break;
case 1:
if (isa == rv32) {
--
2.43.0
^ permalink raw reply related [flat|nested] 119+ messages in thread
* [PATCH 20/56] disas/riscv: Handle c.lui imm != 0 during decode
2026-08-09 22:34 [RFC PATCH 00/56] disas/riscv: Reorganize the disassembler Richard Henderson
` (18 preceding siblings ...)
2026-08-09 22:35 ` [PATCH 19/56] disas/riscv: Simplify c.addi Richard Henderson
@ 2026-08-09 22:35 ` Richard Henderson
2026-08-11 20:14 ` Alistair
2026-08-09 22:35 ` [PATCH 21/56] disas/riscv: Handle c.{srli,srai} imm " Richard Henderson
` (35 subsequent siblings)
55 siblings, 1 reply; 119+ messages in thread
From: Richard Henderson @ 2026-08-09 22:35 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-riscv
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
disas/riscv.c | 12 +++++++-----
1 file changed, 7 insertions(+), 5 deletions(-)
diff --git a/disas/riscv.c b/disas/riscv.c
index 7978ffb378..d6fbb3bca6 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -1902,9 +1902,9 @@ static const rv_opcode_data rvi_opcode_data[] = {
{ "c.li", rv_codec_ci_li, rv_fmt_rd_rs1_imm, NULL, rv_op_addi, rv_op_addi,
rv_op_addi },
{ "c.addi16sp", rv_codec_ci_16sp, rv_fmt_rd_rs1_imm, NULL, rv_op_addi,
- rv_op_addi, rv_op_addi, rvcd_imm_nz },
+ rv_op_addi, rv_op_addi },
{ "c.lui", rv_codec_ci_lui, rv_fmt_rd_uimm, NULL, rv_op_lui, rv_op_lui,
- rv_op_lui, rvcd_imm_nz },
+ rv_op_lui },
{ "c.srli", rv_codec_cb_sh6, rv_fmt_rd_rs1_imm, NULL, rv_op_srli,
rv_op_srli, rv_op_srli, rvcd_imm_nz },
{ "c.srai", rv_codec_cb_sh6, rv_fmt_rd_rs1_imm, NULL, rv_op_srai,
@@ -3032,9 +3032,11 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
break;
}
}
- switch ((inst >> 7) & 0b11111) {
- case 2: op = rv_op_c_addi16sp; break;
- default: op = rv_op_c_lui; break;
+ if (inst & ((1 << 12) | (0x1f << 2))) {
+ switch ((inst >> 7) & 0b11111) {
+ case 2: op = rv_op_c_addi16sp; break;
+ default: op = rv_op_c_lui; break;
+ }
}
break;
case 4:
--
2.43.0
^ permalink raw reply related [flat|nested] 119+ messages in thread
* [PATCH 21/56] disas/riscv: Handle c.{srli,srai} imm during decode
2026-08-09 22:34 [RFC PATCH 00/56] disas/riscv: Reorganize the disassembler Richard Henderson
` (19 preceding siblings ...)
2026-08-09 22:35 ` [PATCH 20/56] disas/riscv: Handle c.lui imm != 0 during decode Richard Henderson
@ 2026-08-09 22:35 ` Richard Henderson
2026-08-11 20:16 ` Alistair
2026-08-09 22:35 ` [PATCH 22/56] disas/riscv: Handle c.slli imm != 0 " Richard Henderson
` (34 subsequent siblings)
55 siblings, 1 reply; 119+ messages in thread
From: Richard Henderson @ 2026-08-09 22:35 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-riscv
Zero shift immediate to c.srli and c.srai are not illegal,
but are reserved as HINTs. Go ahead and disassemble as
shifts rather than falling back to invalid.
On the other hand, shift immediate >= 32 with RV32 is
reserved for custom extensions, and we need to reject those
early so that the extension disassemblers get a look in.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
disas/riscv.c | 14 ++++++++++----
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/disas/riscv.c b/disas/riscv.c
index d6fbb3bca6..a8fbefb9bd 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -1906,9 +1906,9 @@ static const rv_opcode_data rvi_opcode_data[] = {
{ "c.lui", rv_codec_ci_lui, rv_fmt_rd_uimm, NULL, rv_op_lui, rv_op_lui,
rv_op_lui },
{ "c.srli", rv_codec_cb_sh6, rv_fmt_rd_rs1_imm, NULL, rv_op_srli,
- rv_op_srli, rv_op_srli, rvcd_imm_nz },
+ rv_op_srli, rv_op_srli },
{ "c.srai", rv_codec_cb_sh6, rv_fmt_rd_rs1_imm, NULL, rv_op_srai,
- rv_op_srai, rv_op_srai, rvcd_imm_nz },
+ rv_op_srai, rv_op_srai },
{ "c.andi", rv_codec_cb_imm, rv_fmt_rd_rs1_imm, NULL, rv_op_andi,
rv_op_andi, rv_op_andi },
{ "c.sub", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_sub, rv_op_sub,
@@ -3042,10 +3042,16 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
case 4:
switch ((inst >> 10) & 0b11) {
case 0:
- op = rv_op_c_srli;
+ /* For rv32, shamt[5]=1 is designated for custom extensions. */
+ if (isa != rv32 || (inst & 0x1000) == 0) {
+ op = rv_op_c_srli; /* or unspecified HINT */
+ }
break;
case 1:
- op = rv_op_c_srai;
+ /* For rv32, shamt[5]=1 is designated for custom extensions. */
+ if (isa != rv32 || (inst & 0x1000) == 0) {
+ op = rv_op_c_srai; /* or unspecified HINT */
+ }
break;
case 2: op = rv_op_c_andi; break;
case 3:
--
2.43.0
^ permalink raw reply related [flat|nested] 119+ messages in thread
* [PATCH 22/56] disas/riscv: Handle c.slli imm != 0 during decode
2026-08-09 22:34 [RFC PATCH 00/56] disas/riscv: Reorganize the disassembler Richard Henderson
` (20 preceding siblings ...)
2026-08-09 22:35 ` [PATCH 21/56] disas/riscv: Handle c.{srli,srai} imm " Richard Henderson
@ 2026-08-09 22:35 ` Richard Henderson
2026-08-11 20:16 ` Alistair
2026-08-09 22:35 ` [PATCH 23/56] disas/riscv: Do not recognize c.{addw,subw} with rv32 Richard Henderson
` (33 subsequent siblings)
55 siblings, 1 reply; 119+ messages in thread
From: Richard Henderson @ 2026-08-09 22:35 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-riscv
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
disas/riscv.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/disas/riscv.c b/disas/riscv.c
index a8fbefb9bd..77347b557d 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -1930,7 +1930,7 @@ static const rv_opcode_data rvi_opcode_data[] = {
{ "c.bnez", rv_codec_cb, rv_fmt_rs1_rs2_offset, NULL, rv_op_bne, rv_op_bne,
rv_op_bne },
{ "c.slli", rv_codec_ci_sh6, rv_fmt_rd_rs1_imm, NULL, rv_op_slli,
- rv_op_slli, rv_op_slli, rvcd_imm_nz },
+ rv_op_slli, rv_op_slli },
{ "c.fldsp", rv_codec_ci_ldsp, rv_fmt_frd_offset_rs1, NULL, rv_op_fld,
rv_op_fld, rv_op_fld },
{ "c.lwsp", rv_codec_ci_lwsp, rv_fmt_rd_offset_rs1, NULL, rv_op_lw,
@@ -3085,7 +3085,9 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
case 2:
switch ((inst >> 13) & 0b111) {
case 0:
- op = rv_op_c_slli;
+ if (isa != rv32 || (inst & 0x1000) == 0) {
+ op = rv_op_c_slli; /* or unspecified HINT */
+ }
break;
case 1:
if (isa == rv128) {
--
2.43.0
^ permalink raw reply related [flat|nested] 119+ messages in thread
* [PATCH 23/56] disas/riscv: Do not recognize c.{addw,subw} with rv32
2026-08-09 22:34 [RFC PATCH 00/56] disas/riscv: Reorganize the disassembler Richard Henderson
` (21 preceding siblings ...)
2026-08-09 22:35 ` [PATCH 22/56] disas/riscv: Handle c.slli imm != 0 " Richard Henderson
@ 2026-08-09 22:35 ` Richard Henderson
2026-08-11 20:17 ` Alistair
2026-08-09 22:35 ` [PATCH 24/56] disas/riscv: Remove rvcd_imm_nz Richard Henderson
` (32 subsequent siblings)
55 siblings, 1 reply; 119+ messages in thread
From: Richard Henderson @ 2026-08-09 22:35 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-riscv
These code points are reserved with RV32.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
disas/riscv.c | 12 ++++++++++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/disas/riscv.c b/disas/riscv.c
index 77347b557d..ddc2f73eae 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -3060,8 +3060,16 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
case 1: op = rv_op_c_xor; break;
case 2: op = rv_op_c_or; break;
case 3: op = rv_op_c_and; break;
- case 4: op = rv_op_c_subw; break;
- case 5: op = rv_op_c_addw; break;
+ case 4:
+ if (isa != rv32) {
+ op = rv_op_c_subw;
+ }
+ break;
+ case 5:
+ if (isa != rv32) {
+ op = rv_op_c_addw;
+ }
+ break;
case 6: op = rv_op_c_mul; break;
case 7:
switch ((inst >> 2) & 0b111) {
--
2.43.0
^ permalink raw reply related [flat|nested] 119+ messages in thread
* [PATCH 24/56] disas/riscv: Remove rvcd_imm_nz
2026-08-09 22:34 [RFC PATCH 00/56] disas/riscv: Reorganize the disassembler Richard Henderson
` (22 preceding siblings ...)
2026-08-09 22:35 ` [PATCH 23/56] disas/riscv: Do not recognize c.{addw,subw} with rv32 Richard Henderson
@ 2026-08-09 22:35 ` Richard Henderson
2026-08-11 20:17 ` Alistair
2026-08-09 22:35 ` [PATCH 25/56] disas/riscv: Unify decomp_rv{32,64,128} Richard Henderson
` (31 subsequent siblings)
55 siblings, 1 reply; 119+ messages in thread
From: Richard Henderson @ 2026-08-09 22:35 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-riscv
Remove rvcd_imm_nz and rv_opcode_data.decomp_data as unused.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
disas/riscv.h | 5 -----
disas/riscv.c | 7 +------
2 files changed, 1 insertion(+), 11 deletions(-)
diff --git a/disas/riscv.h b/disas/riscv.h
index 31bb0db86c..3909d73dd0 100644
--- a/disas/riscv.h
+++ b/disas/riscv.h
@@ -186,7 +186,6 @@ typedef struct {
short decomp_rv32;
short decomp_rv64;
short decomp_rv128;
- short decomp_data;
} rv_opcode_data;
typedef struct {
@@ -217,10 +216,6 @@ enum {
rv_op_illegal = 0
};
-enum {
- rvcd_imm_nz = 0x1
-};
-
/* instruction formats */
#define rv_fmt_none "O\t"
diff --git a/disas/riscv.c b/disas/riscv.c
index ddc2f73eae..95957506bd 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -5417,12 +5417,7 @@ static const rv_opcode_data *decode_inst_decompress(rv_decode *dec, rv_isa isa,
}
if (decomp_op != rv_op_illegal) {
- if ((op->decomp_data & rvcd_imm_nz) && dec->imm == 0) {
- dec->opcode_data = rvi_opcode_data;
- dec->op = rv_op_illegal;
- } else {
- dec->op = decomp_op;
- }
+ dec->op = decomp_op;
op = &dec->opcode_data[decomp_op];
}
return op;
--
2.43.0
^ permalink raw reply related [flat|nested] 119+ messages in thread
* [PATCH 25/56] disas/riscv: Unify decomp_rv{32,64,128}
2026-08-09 22:34 [RFC PATCH 00/56] disas/riscv: Reorganize the disassembler Richard Henderson
` (23 preceding siblings ...)
2026-08-09 22:35 ` [PATCH 24/56] disas/riscv: Remove rvcd_imm_nz Richard Henderson
@ 2026-08-09 22:35 ` Richard Henderson
2026-08-11 20:18 ` Alistair
2026-08-09 22:35 ` [PATCH 26/56] disas/riscv: Drop always true branch psudeos Richard Henderson
` (30 subsequent siblings)
55 siblings, 1 reply; 119+ messages in thread
From: Richard Henderson @ 2026-08-09 22:35 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-riscv
We now distinguish compressed opcodes by isa during decode.
Therefore we don't need 3 copies of decomp_*.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
disas/riscv.h | 4 +-
disas/riscv.c | 155 ++++++++++++++++----------------------------------
2 files changed, 51 insertions(+), 108 deletions(-)
diff --git a/disas/riscv.h b/disas/riscv.h
index 3909d73dd0..900363c603 100644
--- a/disas/riscv.h
+++ b/disas/riscv.h
@@ -183,9 +183,7 @@ typedef struct {
rv_codec codec;
const char *format;
const rv_comp_data *pseudo;
- short decomp_rv32;
- short decomp_rv64;
- short decomp_rv128;
+ rv_opcode decomp;
} rv_opcode_data;
typedef struct {
diff --git a/disas/riscv.c b/disas/riscv.c
index 95957506bd..2e891f509e 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -1883,91 +1883,52 @@ static const rv_opcode_data rvi_opcode_data[] = {
{ "fcvt.q.lu", rv_codec_r_m, rv_fmt_rm_frd_rs1 },
{ "fmv.x.q", rv_codec_r, rv_fmt_rd_frs1 },
{ "fmv.q.x", rv_codec_r, rv_fmt_frd_rs1 },
- { "c.addi4spn", rv_codec_ciw_4spn, rv_fmt_rd_rs1_imm, NULL, rv_op_addi,
- rv_op_addi, rv_op_addi },
- { "c.fld", rv_codec_cl_ld, rv_fmt_frd_offset_rs1, NULL, rv_op_fld,
- rv_op_fld, 0 },
- { "c.lw", rv_codec_cl_lw, rv_fmt_rd_offset_rs1, NULL, rv_op_lw, rv_op_lw,
- rv_op_lw },
- { "c.flw", rv_codec_cl_lw, rv_fmt_frd_offset_rs1, NULL, rv_op_flw, 0, 0 },
- { "c.fsd", rv_codec_cs_sd, rv_fmt_frs2_offset_rs1, NULL, rv_op_fsd,
- rv_op_fsd, 0 },
- { "c.sw", rv_codec_cs_sw, rv_fmt_rs2_offset_rs1, NULL, rv_op_sw, rv_op_sw,
- rv_op_sw },
- { "c.fsw", rv_codec_cs_sw, rv_fmt_frs2_offset_rs1, NULL, rv_op_fsw, 0, 0 },
+ { "c.addi4spn", rv_codec_ciw_4spn, rv_fmt_rd_rs1_imm, NULL, rv_op_addi },
+ { "c.fld", rv_codec_cl_ld, rv_fmt_frd_offset_rs1, NULL, rv_op_fld },
+ { "c.lw", rv_codec_cl_lw, rv_fmt_rd_offset_rs1, NULL, rv_op_lw },
+ { "c.flw", rv_codec_cl_lw, rv_fmt_frd_offset_rs1, NULL, rv_op_flw },
+ { "c.fsd", rv_codec_cs_sd, rv_fmt_frs2_offset_rs1, NULL, rv_op_fsd },
+ { "c.sw", rv_codec_cs_sw, rv_fmt_rs2_offset_rs1, NULL, rv_op_sw },
+ { "c.fsw", rv_codec_cs_sw, rv_fmt_frs2_offset_rs1, NULL, rv_op_fsw },
{ },
- { "c.addi", rv_codec_ci, rv_fmt_rd_rs1_imm, NULL, rv_op_addi, rv_op_addi,
- rv_op_addi },
- { "c.jal", rv_codec_cj_jal, rv_fmt_rd_offset, NULL, rv_op_jal, 0, 0 },
- { "c.li", rv_codec_ci_li, rv_fmt_rd_rs1_imm, NULL, rv_op_addi, rv_op_addi,
- rv_op_addi },
- { "c.addi16sp", rv_codec_ci_16sp, rv_fmt_rd_rs1_imm, NULL, rv_op_addi,
- rv_op_addi, rv_op_addi },
- { "c.lui", rv_codec_ci_lui, rv_fmt_rd_uimm, NULL, rv_op_lui, rv_op_lui,
- rv_op_lui },
- { "c.srli", rv_codec_cb_sh6, rv_fmt_rd_rs1_imm, NULL, rv_op_srli,
- rv_op_srli, rv_op_srli },
- { "c.srai", rv_codec_cb_sh6, rv_fmt_rd_rs1_imm, NULL, rv_op_srai,
- rv_op_srai, rv_op_srai },
- { "c.andi", rv_codec_cb_imm, rv_fmt_rd_rs1_imm, NULL, rv_op_andi,
- rv_op_andi, rv_op_andi },
- { "c.sub", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_sub, rv_op_sub,
- rv_op_sub },
- { "c.xor", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_xor, rv_op_xor,
- rv_op_xor },
- { "c.or", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_or, rv_op_or,
- rv_op_or },
- { "c.and", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_and, rv_op_and,
- rv_op_and },
- { "c.subw", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_subw, rv_op_subw,
- rv_op_subw },
- { "c.addw", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_addw, rv_op_addw,
- rv_op_addw },
- { "c.j", rv_codec_cj, rv_fmt_rd_offset, NULL, rv_op_jal, rv_op_jal,
- rv_op_jal },
- { "c.beqz", rv_codec_cb, rv_fmt_rs1_rs2_offset, NULL, rv_op_beq, rv_op_beq,
- rv_op_beq },
- { "c.bnez", rv_codec_cb, rv_fmt_rs1_rs2_offset, NULL, rv_op_bne, rv_op_bne,
- rv_op_bne },
- { "c.slli", rv_codec_ci_sh6, rv_fmt_rd_rs1_imm, NULL, rv_op_slli,
- rv_op_slli, rv_op_slli },
- { "c.fldsp", rv_codec_ci_ldsp, rv_fmt_frd_offset_rs1, NULL, rv_op_fld,
- rv_op_fld, rv_op_fld },
- { "c.lwsp", rv_codec_ci_lwsp, rv_fmt_rd_offset_rs1, NULL, rv_op_lw,
- rv_op_lw, rv_op_lw },
- { "c.flwsp", rv_codec_ci_lwsp, rv_fmt_frd_offset_rs1, NULL, rv_op_flw, 0,
- 0 },
- { "c.jr", rv_codec_cr_jr, rv_fmt_rd_rs1_offset, NULL, rv_op_jalr,
- rv_op_jalr, rv_op_jalr },
- { "c.mv", rv_codec_cr_mv, rv_fmt_rd_rs1_rs2, NULL, rv_op_addi, rv_op_addi,
- rv_op_addi },
- { "c.ebreak", rv_codec_ci_none, rv_fmt_none, NULL, rv_op_ebreak,
- rv_op_ebreak, rv_op_ebreak },
- { "c.jalr", rv_codec_cr_jalr, rv_fmt_rd_rs1_offset, NULL, rv_op_jalr,
- rv_op_jalr, rv_op_jalr },
- { "c.add", rv_codec_cr, rv_fmt_rd_rs1_rs2, NULL, rv_op_add, rv_op_add,
- rv_op_add },
- { "c.fsdsp", rv_codec_css_sdsp, rv_fmt_frs2_offset_rs1, NULL, rv_op_fsd,
- rv_op_fsd, rv_op_fsd },
- { "c.swsp", rv_codec_css_swsp, rv_fmt_rs2_offset_rs1, NULL, rv_op_sw,
- rv_op_sw, rv_op_sw },
- { "c.fswsp", rv_codec_css_swsp, rv_fmt_frs2_offset_rs1, NULL, rv_op_fsw, 0,
- 0 },
- { "c.ld", rv_codec_cl_ld, rv_fmt_rd_offset_rs1, NULL, 0, rv_op_ld,
- rv_op_ld },
- { "c.sd", rv_codec_cs_sd, rv_fmt_rs2_offset_rs1, NULL, 0, rv_op_sd,
- rv_op_sd },
- { "c.addiw", rv_codec_ci, rv_fmt_rd_rs1_imm, NULL, 0, rv_op_addiw,
- rv_op_addiw },
- { "c.ldsp", rv_codec_ci_ldsp, rv_fmt_rd_offset_rs1, NULL, 0, rv_op_ld,
- rv_op_ld },
- { "c.sdsp", rv_codec_css_sdsp, rv_fmt_rs2_offset_rs1, NULL, 0, rv_op_sd,
- rv_op_sd },
- { "c.lq", rv_codec_cl_lq, rv_fmt_rd_offset_rs1, NULL, 0, 0, rv_op_lq },
- { "c.sq", rv_codec_cs_sq, rv_fmt_rs2_offset_rs1, NULL, 0, 0, rv_op_sq },
- { "c.lqsp", rv_codec_ci_lqsp, rv_fmt_rd_offset_rs1, NULL, 0, 0, rv_op_lq },
- { "c.sqsp", rv_codec_css_sqsp, rv_fmt_rs2_offset_rs1, NULL, 0, 0,
- rv_op_sq },
+ { "c.addi", rv_codec_ci, rv_fmt_rd_rs1_imm, NULL, rv_op_addi },
+ { "c.jal", rv_codec_cj_jal, rv_fmt_rd_offset, NULL, rv_op_jal },
+ { "c.li", rv_codec_ci_li, rv_fmt_rd_rs1_imm, NULL, rv_op_addi },
+ { "c.addi16sp", rv_codec_ci_16sp, rv_fmt_rd_rs1_imm, NULL, rv_op_addi },
+ { "c.lui", rv_codec_ci_lui, rv_fmt_rd_uimm, NULL, rv_op_lui },
+ { "c.srli", rv_codec_cb_sh6, rv_fmt_rd_rs1_imm, NULL, rv_op_srli },
+ { "c.srai", rv_codec_cb_sh6, rv_fmt_rd_rs1_imm, NULL, rv_op_srai },
+ { "c.andi", rv_codec_cb_imm, rv_fmt_rd_rs1_imm, NULL, rv_op_andi },
+ { "c.sub", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_sub },
+ { "c.xor", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_xor },
+ { "c.or", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_or },
+ { "c.and", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_and },
+ { "c.subw", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_subw },
+ { "c.addw", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_addw },
+ { "c.j", rv_codec_cj, rv_fmt_rd_offset, NULL, rv_op_jal },
+ { "c.beqz", rv_codec_cb, rv_fmt_rs1_rs2_offset, NULL, rv_op_beq },
+ { "c.bnez", rv_codec_cb, rv_fmt_rs1_rs2_offset, NULL, rv_op_bne },
+ { "c.slli", rv_codec_ci_sh6, rv_fmt_rd_rs1_imm, NULL, rv_op_slli },
+ { "c.fldsp", rv_codec_ci_ldsp, rv_fmt_frd_offset_rs1, NULL, rv_op_fld },
+ { "c.lwsp", rv_codec_ci_lwsp, rv_fmt_rd_offset_rs1, NULL, rv_op_lw },
+ { "c.flwsp", rv_codec_ci_lwsp, rv_fmt_frd_offset_rs1, NULL, rv_op_flw },
+ { "c.jr", rv_codec_cr_jr, rv_fmt_rd_rs1_offset, NULL, rv_op_jalr },
+ { "c.mv", rv_codec_cr_mv, rv_fmt_rd_rs1_rs2, NULL, rv_op_addi },
+ { "c.ebreak", rv_codec_ci_none, rv_fmt_none, NULL, rv_op_ebreak },
+ { "c.jalr", rv_codec_cr_jalr, rv_fmt_rd_rs1_offset, NULL, rv_op_jalr },
+ { "c.add", rv_codec_cr, rv_fmt_rd_rs1_rs2, NULL, rv_op_add },
+ { "c.fsdsp", rv_codec_css_sdsp, rv_fmt_frs2_offset_rs1, NULL, rv_op_fsd },
+ { "c.swsp", rv_codec_css_swsp, rv_fmt_rs2_offset_rs1, NULL, rv_op_sw },
+ { "c.fswsp", rv_codec_css_swsp, rv_fmt_frs2_offset_rs1, NULL, rv_op_fsw },
+ { "c.ld", rv_codec_cl_ld, rv_fmt_rd_offset_rs1, NULL, rv_op_ld },
+ { "c.sd", rv_codec_cs_sd, rv_fmt_rs2_offset_rs1, NULL, rv_op_sd },
+ { "c.addiw", rv_codec_ci, rv_fmt_rd_rs1_imm, NULL, rv_op_addiw },
+ { "c.ldsp", rv_codec_ci_ldsp, rv_fmt_rd_offset_rs1, NULL, rv_op_ld },
+ { "c.sdsp", rv_codec_css_sdsp, rv_fmt_rs2_offset_rs1, NULL, rv_op_sd },
+ { "c.lq", rv_codec_cl_lq, rv_fmt_rd_offset_rs1, NULL, rv_op_lq },
+ { "c.sq", rv_codec_cs_sq, rv_fmt_rs2_offset_rs1, NULL, rv_op_sq },
+ { "c.lqsp", rv_codec_ci_lqsp, rv_fmt_rd_offset_rs1, NULL, rv_op_lq },
+ { "c.sqsp", rv_codec_css_sqsp, rv_fmt_rs2_offset_rs1, NULL, rv_op_sq },
{ "nop", rv_codec_i, rv_fmt_none },
{ "mv", rv_codec_i, rv_fmt_rd_rs1 },
{ "not", rv_codec_i, rv_fmt_rd_rs1 },
@@ -2649,10 +2610,8 @@ static const rv_opcode_data rvi_opcode_data[] = {
{ "ssrdp", rv_codec_r, rv_fmt_rd },
{ "ssamoswap.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
{ "ssamoswap.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
- { "c.sspush", rv_codec_cmop_ss, rv_fmt_rs2, NULL, rv_op_sspush,
- rv_op_sspush, 0 },
- { "c.sspopchk", rv_codec_cmop_ss, rv_fmt_rs1, NULL, rv_op_sspopchk,
- rv_op_sspopchk, 0 },
+ { "c.sspush", rv_codec_cmop_ss, rv_fmt_rs2, NULL, rv_op_sspush },
+ { "c.sspopchk", rv_codec_cmop_ss, rv_fmt_rs1, NULL, rv_op_sspopchk },
{ "cbo.inval", rv_codec_r, rv_fmt_rs1 },
{ "cbo.clean", rv_codec_r, rv_fmt_rs1 },
{ "cbo.flush", rv_codec_r, rv_fmt_rs1 },
@@ -5397,24 +5356,10 @@ static const rv_opcode_data *decode_inst_lift_pseudo(rv_decode *dec,
/* decompress instruction */
-static const rv_opcode_data *decode_inst_decompress(rv_decode *dec, rv_isa isa,
+static const rv_opcode_data *decode_inst_decompress(rv_decode *dec,
const rv_opcode_data *op)
{
- int decomp_op;
-
- switch (isa) {
- case rv32:
- decomp_op = op->decomp_rv32;
- break;
- case rv64:
- decomp_op = op->decomp_rv64;
- break;
- case rv128:
- decomp_op = op->decomp_rv128;
- break;
- default:
- g_assert_not_reached();
- }
+ int decomp_op = op->decomp;
if (decomp_op != rv_op_illegal) {
dec->op = decomp_op;
@@ -5473,7 +5418,7 @@ static GString *disasm_inst(rv_isa isa, uint64_t pc, rv_inst inst,
op = &dec.opcode_data[dec.op];
decode_inst_operands(&dec, isa, op);
- op = decode_inst_decompress(&dec, isa, op);
+ op = decode_inst_decompress(&dec, op);
op = decode_inst_lift_pseudo(&dec, op);
return format_inst(24, &dec, op);
}
--
2.43.0
^ permalink raw reply related [flat|nested] 119+ messages in thread
* [PATCH 26/56] disas/riscv: Drop always true branch psudeos
2026-08-09 22:34 [RFC PATCH 00/56] disas/riscv: Reorganize the disassembler Richard Henderson
` (24 preceding siblings ...)
2026-08-09 22:35 ` [PATCH 25/56] disas/riscv: Unify decomp_rv{32,64,128} Richard Henderson
@ 2026-08-09 22:35 ` Richard Henderson
2026-08-10 2:58 ` Philippe Mathieu-Daudé
2026-08-11 20:19 ` Alistair
2026-08-09 22:35 ` [PATCH 27/56] disas/riscv: Handle aliases of csrrw during decode Richard Henderson
` (29 subsequent siblings)
55 siblings, 2 replies; 119+ messages in thread
From: Richard Henderson @ 2026-08-09 22:35 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-riscv
The real insns are blt, bge, bltu, bgeu. Do not include
psuedos that unconditionally swap operands. That's fine
for an assembler but not a disassembler.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
disas/riscv.c | 32 ++++++--------------------------
1 file changed, 6 insertions(+), 26 deletions(-)
diff --git a/disas/riscv.c b/disas/riscv.c
index 2e891f509e..bde1cc6e62 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -326,10 +326,6 @@ typedef enum {
rv_op_bgez = 295,
rv_op_bltz = 296,
rv_op_bgtz = 297,
- rv_op_ble = 298,
- rv_op_bleu = 299,
- rv_op_bgt = 300,
- rv_op_bgtu = 301,
rv_op_j = 302,
rv_op_ret = 303,
rv_op_jr = 304,
@@ -1062,10 +1058,6 @@ static const rvc_constraint rvcc_blez[] = { rvc_rs1_eq_x0, rvc_end };
static const rvc_constraint rvcc_bgez[] = { rvc_rs2_eq_x0, rvc_end };
static const rvc_constraint rvcc_bltz[] = { rvc_rs2_eq_x0, rvc_end };
static const rvc_constraint rvcc_bgtz[] = { rvc_rs1_eq_x0, rvc_end };
-static const rvc_constraint rvcc_ble[] = { rvc_end };
-static const rvc_constraint rvcc_bleu[] = { rvc_end };
-static const rvc_constraint rvcc_bgt[] = { rvc_end };
-static const rvc_constraint rvcc_bgtu[] = { rvc_end };
static const rvc_constraint rvcc_j[] = { rvc_rd_eq_x0, rvc_end };
static const rvc_constraint rvcc_ret[] = { rvc_rd_eq_x0, rvc_rs1_eq_ra,
rvc_end };
@@ -1123,24 +1115,12 @@ static const rv_comp_data rvcp_bne[] = {
static const rv_comp_data rvcp_blt[] = {
{ rv_op_bltz, rvcc_bltz },
{ rv_op_bgtz, rvcc_bgtz },
- { rv_op_bgt, rvcc_bgt },
{ rv_op_illegal, NULL }
};
static const rv_comp_data rvcp_bge[] = {
{ rv_op_blez, rvcc_blez },
{ rv_op_bgez, rvcc_bgez },
- { rv_op_ble, rvcc_ble },
- { rv_op_illegal, NULL }
-};
-
-static const rv_comp_data rvcp_bltu[] = {
- { rv_op_bgtu, rvcc_bgtu },
- { rv_op_illegal, NULL }
-};
-
-static const rv_comp_data rvcp_bgeu[] = {
- { rv_op_bleu, rvcc_bleu },
{ rv_op_illegal, NULL }
};
@@ -1665,8 +1645,8 @@ static const rv_opcode_data rvi_opcode_data[] = {
{ "bne", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_bne },
{ "blt", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_blt },
{ "bge", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_bge },
- { "bltu", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_bltu },
- { "bgeu", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_bgeu },
+ { "bltu", rv_codec_sb, rv_fmt_rs1_rs2_offset },
+ { "bgeu", rv_codec_sb, rv_fmt_rs1_rs2_offset },
{ "lb", rv_codec_i, rv_fmt_rd_offset_rs1 },
{ "lh", rv_codec_i, rv_fmt_rd_offset_rs1 },
{ "lw", rv_codec_i, rv_fmt_rd_offset_rs1 },
@@ -1954,10 +1934,10 @@ static const rv_opcode_data rvi_opcode_data[] = {
{ "bgez", rv_codec_sb, rv_fmt_rs1_offset },
{ "bltz", rv_codec_sb, rv_fmt_rs1_offset },
{ "bgtz", rv_codec_sb, rv_fmt_rs2_offset },
- { "ble", rv_codec_sb, rv_fmt_rs2_rs1_offset },
- { "bleu", rv_codec_sb, rv_fmt_rs2_rs1_offset },
- { "bgt", rv_codec_sb, rv_fmt_rs2_rs1_offset },
- { "bgtu", rv_codec_sb, rv_fmt_rs2_rs1_offset },
+ { },
+ { },
+ { },
+ { },
{ "j", rv_codec_uj, rv_fmt_offset },
{ "ret", rv_codec_i, rv_fmt_none },
{ "jr", rv_codec_i, rv_fmt_rs1 },
--
2.43.0
^ permalink raw reply related [flat|nested] 119+ messages in thread
* [PATCH 27/56] disas/riscv: Handle aliases of csrrw during decode
2026-08-09 22:34 [RFC PATCH 00/56] disas/riscv: Reorganize the disassembler Richard Henderson
` (25 preceding siblings ...)
2026-08-09 22:35 ` [PATCH 26/56] disas/riscv: Drop always true branch psudeos Richard Henderson
@ 2026-08-09 22:35 ` Richard Henderson
2026-08-11 20:20 ` Alistair
2026-08-09 22:35 ` [PATCH 28/56] disas/riscv: Handle aliases of csrrs " Richard Henderson
` (28 subsequent siblings)
55 siblings, 1 reply; 119+ messages in thread
From: Richard Henderson @ 2026-08-09 22:35 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-riscv
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
disas/riscv.c | 22 +++++++++-------------
1 file changed, 9 insertions(+), 13 deletions(-)
diff --git a/disas/riscv.c b/disas/riscv.c
index bde1cc6e62..e464b8b075 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -1081,9 +1081,6 @@ static const rvc_constraint rvcc_frrm[] = { rvc_rs1_eq_x0, rvc_csr_eq_0x002,
rvc_end };
static const rvc_constraint rvcc_frflags[] = { rvc_rs1_eq_x0, rvc_csr_eq_0x001,
rvc_end };
-static const rvc_constraint rvcc_fscsr[] = { rvc_csr_eq_0x003, rvc_end };
-static const rvc_constraint rvcc_fsrm[] = { rvc_csr_eq_0x002, rvc_end };
-static const rvc_constraint rvcc_fsflags[] = { rvc_csr_eq_0x001, rvc_end };
static const rvc_constraint rvcc_fsrmi[] = { rvc_csr_eq_0x002, rvc_end };
static const rvc_constraint rvcc_fsflagsi[] = { rvc_csr_eq_0x001, rvc_end };
@@ -1166,14 +1163,6 @@ static const rv_comp_data rvcp_subw[] = {
{ rv_op_illegal, NULL }
};
-static const rv_comp_data rvcp_csrrw[] = {
- { rv_op_fscsr, rvcc_fscsr },
- { rv_op_fsrm, rvcc_fsrm },
- { rv_op_fsflags, rvcc_fsflags },
- { rv_op_illegal, NULL }
-};
-
-
static const rv_comp_data rvcp_csrrs[] = {
{ rv_op_rdcycle, rvcc_rdcycle },
{ rv_op_rdtime, rvcc_rdtime },
@@ -1761,7 +1750,7 @@ static const rv_opcode_data rvi_opcode_data[] = {
{ "sfence.vm", rv_codec_r, rv_fmt_rs1 },
{ "sfence.vma", rv_codec_r, rv_fmt_rs1_rs2 },
{ "wfi", rv_codec_none, rv_fmt_none },
- { "csrrw", rv_codec_i_csr, rv_fmt_rd_csr_rs1, rvcp_csrrw },
+ { "csrrw", rv_codec_i_csr, rv_fmt_rd_csr_rs1 },
{ "csrrs", rv_codec_i_csr, rv_fmt_rd_csr_rs1, rvcp_csrrs },
{ "csrrc", rv_codec_i_csr, rv_fmt_rd_csr_rs1 },
{ "csrrwi", rv_codec_i_csr, rv_fmt_rd_csr_zimm, rvcp_csrrwi },
@@ -4443,7 +4432,14 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
break;
}
break;
- case 1: op = rv_op_csrrw; break;
+ case 1:
+ switch (operand_csr12(inst)) {
+ case 1: op = rv_op_fsflags; break;
+ case 2: op = rv_op_fsrm; break;
+ case 3: op = rv_op_fscsr; break;
+ default: op = rv_op_csrrw; break;
+ }
+ break;
case 2: op = rv_op_csrrs; break;
case 3: op = rv_op_csrrc; break;
case 4:
--
2.43.0
^ permalink raw reply related [flat|nested] 119+ messages in thread
* [PATCH 28/56] disas/riscv: Handle aliases of csrrs during decode
2026-08-09 22:34 [RFC PATCH 00/56] disas/riscv: Reorganize the disassembler Richard Henderson
` (26 preceding siblings ...)
2026-08-09 22:35 ` [PATCH 27/56] disas/riscv: Handle aliases of csrrw during decode Richard Henderson
@ 2026-08-09 22:35 ` Richard Henderson
2026-08-11 20:21 ` Alistair
2026-08-09 22:35 ` [PATCH 29/56] disas/riscv: Handle aliases of csrrwi " Richard Henderson
` (27 subsequent siblings)
55 siblings, 1 reply; 119+ messages in thread
From: Richard Henderson @ 2026-08-09 22:35 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-riscv
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
disas/riscv.h | 7 -----
disas/riscv.c | 85 +++++++++++----------------------------------------
2 files changed, 17 insertions(+), 75 deletions(-)
diff --git a/disas/riscv.h b/disas/riscv.h
index 900363c603..d8c5acd969 100644
--- a/disas/riscv.h
+++ b/disas/riscv.h
@@ -86,13 +86,6 @@ typedef enum {
rvc_imm_eq_p1,
rvc_csr_eq_0x001,
rvc_csr_eq_0x002,
- rvc_csr_eq_0x003,
- rvc_csr_eq_0xc00,
- rvc_csr_eq_0xc01,
- rvc_csr_eq_0xc02,
- rvc_csr_eq_0xc80,
- rvc_csr_eq_0xc81,
- rvc_csr_eq_0xc82,
} rvc_constraint;
typedef enum {
diff --git a/disas/riscv.c b/disas/riscv.c
index e464b8b075..9ec79baf4d 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -1063,24 +1063,6 @@ static const rvc_constraint rvcc_ret[] = { rvc_rd_eq_x0, rvc_rs1_eq_ra,
rvc_end };
static const rvc_constraint rvcc_jr[] = { rvc_rd_eq_x0, rvc_imm_eq_zero,
rvc_end };
-static const rvc_constraint rvcc_rdcycle[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc00,
- rvc_end };
-static const rvc_constraint rvcc_rdtime[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc01,
- rvc_end };
-static const rvc_constraint rvcc_rdinstret[] = { rvc_rs1_eq_x0,
- rvc_csr_eq_0xc02, rvc_end };
-static const rvc_constraint rvcc_rdcycleh[] = { rvc_rs1_eq_x0,
- rvc_csr_eq_0xc80, rvc_end };
-static const rvc_constraint rvcc_rdtimeh[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc81,
- rvc_end };
-static const rvc_constraint rvcc_rdinstreth[] = { rvc_rs1_eq_x0,
- rvc_csr_eq_0xc82, rvc_end };
-static const rvc_constraint rvcc_frcsr[] = { rvc_rs1_eq_x0, rvc_csr_eq_0x003,
- rvc_end };
-static const rvc_constraint rvcc_frrm[] = { rvc_rs1_eq_x0, rvc_csr_eq_0x002,
- rvc_end };
-static const rvc_constraint rvcc_frflags[] = { rvc_rs1_eq_x0, rvc_csr_eq_0x001,
- rvc_end };
static const rvc_constraint rvcc_fsrmi[] = { rvc_csr_eq_0x002, rvc_end };
static const rvc_constraint rvcc_fsflagsi[] = { rvc_csr_eq_0x001, rvc_end };
@@ -1163,19 +1145,6 @@ static const rv_comp_data rvcp_subw[] = {
{ rv_op_illegal, NULL }
};
-static const rv_comp_data rvcp_csrrs[] = {
- { rv_op_rdcycle, rvcc_rdcycle },
- { rv_op_rdtime, rvcc_rdtime },
- { rv_op_rdinstret, rvcc_rdinstret },
- { rv_op_rdcycleh, rvcc_rdcycleh },
- { rv_op_rdtimeh, rvcc_rdtimeh },
- { rv_op_rdinstreth, rvcc_rdinstreth },
- { rv_op_frcsr, rvcc_frcsr },
- { rv_op_frrm, rvcc_frrm },
- { rv_op_frflags, rvcc_frflags },
- { rv_op_illegal, NULL }
-};
-
static const rv_comp_data rvcp_csrrwi[] = {
{ rv_op_fsrmi, rvcc_fsrmi },
{ rv_op_fsflagsi, rvcc_fsflagsi },
@@ -1751,7 +1720,7 @@ static const rv_opcode_data rvi_opcode_data[] = {
{ "sfence.vma", rv_codec_r, rv_fmt_rs1_rs2 },
{ "wfi", rv_codec_none, rv_fmt_none },
{ "csrrw", rv_codec_i_csr, rv_fmt_rd_csr_rs1 },
- { "csrrs", rv_codec_i_csr, rv_fmt_rd_csr_rs1, rvcp_csrrs },
+ { "csrrs", rv_codec_i_csr, rv_fmt_rd_csr_rs1 },
{ "csrrc", rv_codec_i_csr, rv_fmt_rd_csr_rs1 },
{ "csrrwi", rv_codec_i_csr, rv_fmt_rd_csr_zimm, rvcp_csrrwi },
{ "csrrsi", rv_codec_i_csr, rv_fmt_rd_csr_zimm },
@@ -4440,7 +4409,22 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
default: op = rv_op_csrrw; break;
}
break;
- case 2: op = rv_op_csrrs; break;
+ case 2:
+ op = rv_op_csrrs;
+ if (operand_rs1(inst) == 0) {
+ switch (operand_csr12(inst)) {
+ case 0x001: op = rv_op_frflags; break;
+ case 0x002: op = rv_op_frrm; break;
+ case 0x003: op = rv_op_frcsr; break;
+ case 0xc00: op = rv_op_rdcycle; break;
+ case 0xc01: op = rv_op_rdtime; break;
+ case 0xc02: op = rv_op_rdinstret; break;
+ case 0xc80: op = rv_op_rdcycleh; break;
+ case 0xc81: op = rv_op_rdtimeh; break;
+ case 0xc82: op = rv_op_rdinstreth; break;
+ }
+ }
+ break;
case 3: op = rv_op_csrrc; break;
case 4:
if (dec->cfg && dec->cfg->ext_zimop) {
@@ -5017,41 +5001,6 @@ static bool check_constraints(rv_decode *dec, const rvc_constraint *c)
return false;
}
break;
- case rvc_csr_eq_0x003:
- if (!(imm == 0x003)) {
- return false;
- }
- break;
- case rvc_csr_eq_0xc00:
- if (!(imm == 0xc00)) {
- return false;
- }
- break;
- case rvc_csr_eq_0xc01:
- if (!(imm == 0xc01)) {
- return false;
- }
- break;
- case rvc_csr_eq_0xc02:
- if (!(imm == 0xc02)) {
- return false;
- }
- break;
- case rvc_csr_eq_0xc80:
- if (!(imm == 0xc80)) {
- return false;
- }
- break;
- case rvc_csr_eq_0xc81:
- if (!(imm == 0xc81)) {
- return false;
- }
- break;
- case rvc_csr_eq_0xc82:
- if (!(imm == 0xc82)) {
- return false;
- }
- break;
default: break;
}
c++;
--
2.43.0
^ permalink raw reply related [flat|nested] 119+ messages in thread
* [PATCH 29/56] disas/riscv: Handle aliases of csrrwi during decode
2026-08-09 22:34 [RFC PATCH 00/56] disas/riscv: Reorganize the disassembler Richard Henderson
` (27 preceding siblings ...)
2026-08-09 22:35 ` [PATCH 28/56] disas/riscv: Handle aliases of csrrs " Richard Henderson
@ 2026-08-09 22:35 ` Richard Henderson
2026-08-11 20:22 ` Alistair
2026-08-09 22:35 ` [PATCH 30/56] disas/riscv: Break pseudo loop for jal and jalr Richard Henderson
` (26 subsequent siblings)
55 siblings, 1 reply; 119+ messages in thread
From: Richard Henderson @ 2026-08-09 22:35 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-riscv
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
disas/riscv.h | 2 --
disas/riscv.c | 28 ++++++++--------------------
2 files changed, 8 insertions(+), 22 deletions(-)
diff --git a/disas/riscv.h b/disas/riscv.h
index d8c5acd969..3bbcbf10fb 100644
--- a/disas/riscv.h
+++ b/disas/riscv.h
@@ -84,8 +84,6 @@ typedef enum {
rvc_imm_eq_zero,
rvc_imm_eq_n1,
rvc_imm_eq_p1,
- rvc_csr_eq_0x001,
- rvc_csr_eq_0x002,
} rvc_constraint;
typedef enum {
diff --git a/disas/riscv.c b/disas/riscv.c
index 9ec79baf4d..d3cbfb86ac 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -1063,8 +1063,6 @@ static const rvc_constraint rvcc_ret[] = { rvc_rd_eq_x0, rvc_rs1_eq_ra,
rvc_end };
static const rvc_constraint rvcc_jr[] = { rvc_rd_eq_x0, rvc_imm_eq_zero,
rvc_end };
-static const rvc_constraint rvcc_fsrmi[] = { rvc_csr_eq_0x002, rvc_end };
-static const rvc_constraint rvcc_fsflagsi[] = { rvc_csr_eq_0x001, rvc_end };
/* pseudo-instruction metadata */
@@ -1145,12 +1143,6 @@ static const rv_comp_data rvcp_subw[] = {
{ rv_op_illegal, NULL }
};
-static const rv_comp_data rvcp_csrrwi[] = {
- { rv_op_fsrmi, rvcc_fsrmi },
- { rv_op_fsflagsi, rvcc_fsflagsi },
- { rv_op_illegal, NULL }
-};
-
static const rv_comp_data rvcp_fsgnj_s[] = {
{ rv_op_fmv_s, rvcc_fmv_s },
{ rv_op_illegal, NULL }
@@ -1722,7 +1714,7 @@ static const rv_opcode_data rvi_opcode_data[] = {
{ "csrrw", rv_codec_i_csr, rv_fmt_rd_csr_rs1 },
{ "csrrs", rv_codec_i_csr, rv_fmt_rd_csr_rs1 },
{ "csrrc", rv_codec_i_csr, rv_fmt_rd_csr_rs1 },
- { "csrrwi", rv_codec_i_csr, rv_fmt_rd_csr_zimm, rvcp_csrrwi },
+ { "csrrwi", rv_codec_i_csr, rv_fmt_rd_csr_zimm },
{ "csrrsi", rv_codec_i_csr, rv_fmt_rd_csr_zimm },
{ "csrrci", rv_codec_i_csr, rv_fmt_rd_csr_zimm },
{ "flw", rv_codec_i, rv_fmt_frd_offset_rs1 },
@@ -4469,7 +4461,13 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
}
}
break;
- case 5: op = rv_op_csrrwi; break;
+ case 5:
+ switch (operand_csr12(inst)) {
+ case 1: op = rv_op_fsflagsi; break;
+ case 2: op = rv_op_fsrmi; break;
+ default: op = rv_op_csrrwi; break;
+ }
+ break;
case 6: op = rv_op_csrrsi; break;
case 7: op = rv_op_csrrci; break;
}
@@ -4991,16 +4989,6 @@ static bool check_constraints(rv_decode *dec, const rvc_constraint *c)
return false;
}
break;
- case rvc_csr_eq_0x001:
- if (!(imm == 0x001)) {
- return false;
- }
- break;
- case rvc_csr_eq_0x002:
- if (!(imm == 0x002)) {
- return false;
- }
- break;
default: break;
}
c++;
--
2.43.0
^ permalink raw reply related [flat|nested] 119+ messages in thread
* [PATCH 30/56] disas/riscv: Break pseudo loop for jal and jalr
2026-08-09 22:34 [RFC PATCH 00/56] disas/riscv: Reorganize the disassembler Richard Henderson
` (28 preceding siblings ...)
2026-08-09 22:35 ` [PATCH 29/56] disas/riscv: Handle aliases of csrrwi " Richard Henderson
@ 2026-08-09 22:35 ` Richard Henderson
2026-08-11 20:23 ` Alistair
2026-08-09 22:35 ` [PATCH 31/56] disas/riscv: Allow decode_inst_lift_pseudo to loop Richard Henderson
` (25 subsequent siblings)
55 siblings, 1 reply; 119+ messages in thread
From: Richard Henderson @ 2026-08-09 22:35 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-riscv
These were clearly intending to simplify
jal ra, foo
to
jal foo
and similarly for jalr, but the pseudo expansion looped
back to the original jal/jalr with the full format.
Add new opcode expansions dropping the implied ra.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
disas/riscv.c | 16 +++++++++-------
1 file changed, 9 insertions(+), 7 deletions(-)
diff --git a/disas/riscv.c b/disas/riscv.c
index d3cbfb86ac..fe503b6cae 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -326,6 +326,8 @@ typedef enum {
rv_op_bgez = 295,
rv_op_bltz = 296,
rv_op_bgtz = 297,
+ rv_op_jal_ra = 298,
+ rv_op_jalr_ra = 299,
rv_op_j = 302,
rv_op_ret = 303,
rv_op_jr = 304,
@@ -1029,9 +1031,9 @@ static const char rv_fli_name_const[32][9] =
/* pseudo-instruction constraints */
-static const rvc_constraint rvcc_jal[] = { rvc_rd_eq_ra, rvc_end };
-static const rvc_constraint rvcc_jalr[] = { rvc_rd_eq_ra, rvc_imm_eq_zero,
- rvc_end };
+static const rvc_constraint rvcc_jal_ra[] = { rvc_rd_eq_ra, rvc_end };
+static const rvc_constraint rvcc_jalr_ra[] = { rvc_rd_eq_ra, rvc_imm_eq_zero,
+ rvc_end };
static const rvc_constraint rvcc_nop[] = { rvc_rd_eq_x0, rvc_rs1_eq_x0,
rvc_imm_eq_zero, rvc_end };
static const rvc_constraint rvcc_mv[] = { rvc_imm_eq_zero, rvc_end };
@@ -1068,14 +1070,14 @@ static const rvc_constraint rvcc_jr[] = { rvc_rd_eq_x0, rvc_imm_eq_zero,
static const rv_comp_data rvcp_jal[] = {
{ rv_op_j, rvcc_j },
- { rv_op_jal, rvcc_jal },
+ { rv_op_jal_ra, rvcc_jal_ra },
{ rv_op_illegal, NULL }
};
static const rv_comp_data rvcp_jalr[] = {
{ rv_op_ret, rvcc_ret },
{ rv_op_jr, rvcc_jr },
- { rv_op_jalr, rvcc_jalr },
+ { rv_op_jalr_ra, rvcc_jalr_ra },
{ rv_op_illegal, NULL }
};
@@ -1884,8 +1886,8 @@ static const rv_opcode_data rvi_opcode_data[] = {
{ "bgez", rv_codec_sb, rv_fmt_rs1_offset },
{ "bltz", rv_codec_sb, rv_fmt_rs1_offset },
{ "bgtz", rv_codec_sb, rv_fmt_rs2_offset },
- { },
- { },
+ { "jal", rv_codec_none, rv_fmt_offset }, /* rv_op_jal_ra */
+ { "jalr", rv_codec_none, rv_fmt_rs1 }, /* rv_op_jalr_ra */
{ },
{ },
{ "j", rv_codec_uj, rv_fmt_offset },
--
2.43.0
^ permalink raw reply related [flat|nested] 119+ messages in thread
* [PATCH 31/56] disas/riscv: Allow decode_inst_lift_pseudo to loop
2026-08-09 22:34 [RFC PATCH 00/56] disas/riscv: Reorganize the disassembler Richard Henderson
` (29 preceding siblings ...)
2026-08-09 22:35 ` [PATCH 30/56] disas/riscv: Break pseudo loop for jal and jalr Richard Henderson
@ 2026-08-09 22:35 ` Richard Henderson
2026-08-11 20:23 ` Alistair
2026-08-09 22:35 ` [PATCH 32/56] disas/riscv: Handle decompression via decode_inst_lift_pseudo Richard Henderson
` (24 subsequent siblings)
55 siblings, 1 reply; 119+ messages in thread
From: Richard Henderson @ 2026-08-09 22:35 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-riscv
Allow pseudo expansion to proceed in multiple steps.
Assert that we don't have simple loops.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
disas/riscv.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/disas/riscv.c b/disas/riscv.c
index fe503b6cae..b8e5b124a5 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -5259,9 +5259,9 @@ static const rv_opcode_data *decode_inst_lift_pseudo(rv_decode *dec,
if (comp_data) {
while (comp_data->constraints) {
if (check_constraints(dec, comp_data->constraints)) {
- dec->op = comp_data->op;
- op = &dec->opcode_data[dec->op];
- break;
+ const rv_opcode_data *new_op = &dec->opcode_data[comp_data->op];
+ assert(new_op != op);
+ return decode_inst_lift_pseudo(dec, new_op);
}
comp_data++;
}
--
2.43.0
^ permalink raw reply related [flat|nested] 119+ messages in thread
* [PATCH 32/56] disas/riscv: Handle decompression via decode_inst_lift_pseudo
2026-08-09 22:34 [RFC PATCH 00/56] disas/riscv: Reorganize the disassembler Richard Henderson
` (30 preceding siblings ...)
2026-08-09 22:35 ` [PATCH 31/56] disas/riscv: Allow decode_inst_lift_pseudo to loop Richard Henderson
@ 2026-08-09 22:35 ` Richard Henderson
2026-08-11 20:24 ` Alistair
2026-08-09 22:35 ` [PATCH 33/56] disas/riscv: Drop format from DECOMP insns Richard Henderson
` (23 subsequent siblings)
55 siblings, 1 reply; 119+ messages in thread
From: Richard Henderson @ 2026-08-09 22:35 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-riscv
Introduce a DECOMP macro that expands an rv_comp_data
that always succeeds.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
disas/riscv.h | 1 -
disas/riscv.c | 113 +++++++++++++++++++++++---------------------------
2 files changed, 51 insertions(+), 63 deletions(-)
diff --git a/disas/riscv.h b/disas/riscv.h
index 3bbcbf10fb..ea7141d3b5 100644
--- a/disas/riscv.h
+++ b/disas/riscv.h
@@ -174,7 +174,6 @@ typedef struct {
rv_codec codec;
const char *format;
const rv_comp_data *pseudo;
- rv_opcode decomp;
} rv_opcode_data;
typedef struct {
diff --git a/disas/riscv.c b/disas/riscv.c
index b8e5b124a5..129e545c6e 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -1065,6 +1065,7 @@ static const rvc_constraint rvcc_ret[] = { rvc_rd_eq_x0, rvc_rs1_eq_ra,
rvc_end };
static const rvc_constraint rvcc_jr[] = { rvc_rd_eq_x0, rvc_imm_eq_zero,
rvc_end };
+static const rvc_constraint rvcc_true[] = { rvc_end };
/* pseudo-instruction metadata */
@@ -1190,6 +1191,9 @@ static const rv_comp_data rvcp_fsgnjx_q[] = {
{ rv_op_illegal, NULL }
};
+/* Convert compressed insns into normal insns via pseudo expansion. */
+#define DECOMP(X) (static const rv_comp_data[1]){ { X, rvcc_true } }
+
/* operand extractors */
static uint32_t operand_rd(rv_inst inst)
@@ -1815,52 +1819,52 @@ static const rv_opcode_data rvi_opcode_data[] = {
{ "fcvt.q.lu", rv_codec_r_m, rv_fmt_rm_frd_rs1 },
{ "fmv.x.q", rv_codec_r, rv_fmt_rd_frs1 },
{ "fmv.q.x", rv_codec_r, rv_fmt_frd_rs1 },
- { "c.addi4spn", rv_codec_ciw_4spn, rv_fmt_rd_rs1_imm, NULL, rv_op_addi },
- { "c.fld", rv_codec_cl_ld, rv_fmt_frd_offset_rs1, NULL, rv_op_fld },
- { "c.lw", rv_codec_cl_lw, rv_fmt_rd_offset_rs1, NULL, rv_op_lw },
- { "c.flw", rv_codec_cl_lw, rv_fmt_frd_offset_rs1, NULL, rv_op_flw },
- { "c.fsd", rv_codec_cs_sd, rv_fmt_frs2_offset_rs1, NULL, rv_op_fsd },
- { "c.sw", rv_codec_cs_sw, rv_fmt_rs2_offset_rs1, NULL, rv_op_sw },
- { "c.fsw", rv_codec_cs_sw, rv_fmt_frs2_offset_rs1, NULL, rv_op_fsw },
+ { "c.addi4spn", rv_codec_ciw_4spn, rv_fmt_rd_rs1_imm, DECOMP(rv_op_addi) },
+ { "c.fld", rv_codec_cl_ld, rv_fmt_frd_offset_rs1, DECOMP(rv_op_fld) },
+ { "c.lw", rv_codec_cl_lw, rv_fmt_rd_offset_rs1, DECOMP(rv_op_lw) },
+ { "c.flw", rv_codec_cl_lw, rv_fmt_frd_offset_rs1, DECOMP(rv_op_flw) },
+ { "c.fsd", rv_codec_cs_sd, rv_fmt_frs2_offset_rs1, DECOMP(rv_op_fsd) },
+ { "c.sw", rv_codec_cs_sw, rv_fmt_rs2_offset_rs1, DECOMP(rv_op_sw) },
+ { "c.fsw", rv_codec_cs_sw, rv_fmt_frs2_offset_rs1, DECOMP(rv_op_fsw) },
{ },
- { "c.addi", rv_codec_ci, rv_fmt_rd_rs1_imm, NULL, rv_op_addi },
- { "c.jal", rv_codec_cj_jal, rv_fmt_rd_offset, NULL, rv_op_jal },
- { "c.li", rv_codec_ci_li, rv_fmt_rd_rs1_imm, NULL, rv_op_addi },
- { "c.addi16sp", rv_codec_ci_16sp, rv_fmt_rd_rs1_imm, NULL, rv_op_addi },
- { "c.lui", rv_codec_ci_lui, rv_fmt_rd_uimm, NULL, rv_op_lui },
- { "c.srli", rv_codec_cb_sh6, rv_fmt_rd_rs1_imm, NULL, rv_op_srli },
- { "c.srai", rv_codec_cb_sh6, rv_fmt_rd_rs1_imm, NULL, rv_op_srai },
- { "c.andi", rv_codec_cb_imm, rv_fmt_rd_rs1_imm, NULL, rv_op_andi },
- { "c.sub", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_sub },
- { "c.xor", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_xor },
- { "c.or", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_or },
- { "c.and", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_and },
- { "c.subw", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_subw },
- { "c.addw", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_addw },
- { "c.j", rv_codec_cj, rv_fmt_rd_offset, NULL, rv_op_jal },
- { "c.beqz", rv_codec_cb, rv_fmt_rs1_rs2_offset, NULL, rv_op_beq },
- { "c.bnez", rv_codec_cb, rv_fmt_rs1_rs2_offset, NULL, rv_op_bne },
- { "c.slli", rv_codec_ci_sh6, rv_fmt_rd_rs1_imm, NULL, rv_op_slli },
- { "c.fldsp", rv_codec_ci_ldsp, rv_fmt_frd_offset_rs1, NULL, rv_op_fld },
- { "c.lwsp", rv_codec_ci_lwsp, rv_fmt_rd_offset_rs1, NULL, rv_op_lw },
- { "c.flwsp", rv_codec_ci_lwsp, rv_fmt_frd_offset_rs1, NULL, rv_op_flw },
- { "c.jr", rv_codec_cr_jr, rv_fmt_rd_rs1_offset, NULL, rv_op_jalr },
- { "c.mv", rv_codec_cr_mv, rv_fmt_rd_rs1_rs2, NULL, rv_op_addi },
- { "c.ebreak", rv_codec_ci_none, rv_fmt_none, NULL, rv_op_ebreak },
- { "c.jalr", rv_codec_cr_jalr, rv_fmt_rd_rs1_offset, NULL, rv_op_jalr },
- { "c.add", rv_codec_cr, rv_fmt_rd_rs1_rs2, NULL, rv_op_add },
- { "c.fsdsp", rv_codec_css_sdsp, rv_fmt_frs2_offset_rs1, NULL, rv_op_fsd },
- { "c.swsp", rv_codec_css_swsp, rv_fmt_rs2_offset_rs1, NULL, rv_op_sw },
- { "c.fswsp", rv_codec_css_swsp, rv_fmt_frs2_offset_rs1, NULL, rv_op_fsw },
- { "c.ld", rv_codec_cl_ld, rv_fmt_rd_offset_rs1, NULL, rv_op_ld },
- { "c.sd", rv_codec_cs_sd, rv_fmt_rs2_offset_rs1, NULL, rv_op_sd },
- { "c.addiw", rv_codec_ci, rv_fmt_rd_rs1_imm, NULL, rv_op_addiw },
- { "c.ldsp", rv_codec_ci_ldsp, rv_fmt_rd_offset_rs1, NULL, rv_op_ld },
- { "c.sdsp", rv_codec_css_sdsp, rv_fmt_rs2_offset_rs1, NULL, rv_op_sd },
- { "c.lq", rv_codec_cl_lq, rv_fmt_rd_offset_rs1, NULL, rv_op_lq },
- { "c.sq", rv_codec_cs_sq, rv_fmt_rs2_offset_rs1, NULL, rv_op_sq },
- { "c.lqsp", rv_codec_ci_lqsp, rv_fmt_rd_offset_rs1, NULL, rv_op_lq },
- { "c.sqsp", rv_codec_css_sqsp, rv_fmt_rs2_offset_rs1, NULL, rv_op_sq },
+ { "c.addi", rv_codec_ci, rv_fmt_rd_rs1_imm, DECOMP(rv_op_addi) },
+ { "c.jal", rv_codec_cj_jal, rv_fmt_rd_offset, DECOMP(rv_op_jal) },
+ { "c.li", rv_codec_ci_li, rv_fmt_rd_rs1_imm, DECOMP(rv_op_addi) },
+ { "c.addi16sp", rv_codec_ci_16sp, rv_fmt_rd_rs1_imm, DECOMP(rv_op_addi) },
+ { "c.lui", rv_codec_ci_lui, rv_fmt_rd_uimm, DECOMP(rv_op_lui) },
+ { "c.srli", rv_codec_cb_sh6, rv_fmt_rd_rs1_imm, DECOMP(rv_op_srli) },
+ { "c.srai", rv_codec_cb_sh6, rv_fmt_rd_rs1_imm, DECOMP(rv_op_srai) },
+ { "c.andi", rv_codec_cb_imm, rv_fmt_rd_rs1_imm, DECOMP(rv_op_andi) },
+ { "c.sub", rv_codec_cs, rv_fmt_rd_rs1_rs2, DECOMP(rv_op_sub) },
+ { "c.xor", rv_codec_cs, rv_fmt_rd_rs1_rs2, DECOMP(rv_op_xor) },
+ { "c.or", rv_codec_cs, rv_fmt_rd_rs1_rs2, DECOMP(rv_op_or) },
+ { "c.and", rv_codec_cs, rv_fmt_rd_rs1_rs2, DECOMP(rv_op_and) },
+ { "c.subw", rv_codec_cs, rv_fmt_rd_rs1_rs2, DECOMP(rv_op_subw) },
+ { "c.addw", rv_codec_cs, rv_fmt_rd_rs1_rs2, DECOMP(rv_op_addw) },
+ { "c.j", rv_codec_cj, rv_fmt_rd_offset, DECOMP(rv_op_jal) },
+ { "c.beqz", rv_codec_cb, rv_fmt_rs1_rs2_offset, DECOMP(rv_op_beq) },
+ { "c.bnez", rv_codec_cb, rv_fmt_rs1_rs2_offset, DECOMP(rv_op_bne) },
+ { "c.slli", rv_codec_ci_sh6, rv_fmt_rd_rs1_imm, DECOMP(rv_op_slli) },
+ { "c.fldsp", rv_codec_ci_ldsp, rv_fmt_frd_offset_rs1, DECOMP(rv_op_fld) },
+ { "c.lwsp", rv_codec_ci_lwsp, rv_fmt_rd_offset_rs1, DECOMP(rv_op_lw) },
+ { "c.flwsp", rv_codec_ci_lwsp, rv_fmt_frd_offset_rs1, DECOMP(rv_op_flw) },
+ { "c.jr", rv_codec_cr_jr, rv_fmt_rd_rs1_offset, DECOMP(rv_op_jalr) },
+ { "c.mv", rv_codec_cr_mv, rv_fmt_rd_rs1_rs2, DECOMP(rv_op_addi) },
+ { "c.ebreak", rv_codec_ci_none, rv_fmt_none, DECOMP(rv_op_ebreak) },
+ { "c.jalr", rv_codec_cr_jalr, rv_fmt_rd_rs1_offset, DECOMP(rv_op_jalr) },
+ { "c.add", rv_codec_cr, rv_fmt_rd_rs1_rs2, DECOMP(rv_op_add) },
+ { "c.fsdsp", rv_codec_css_sdsp, rv_fmt_frs2_offset_rs1, DECOMP(rv_op_fsd) },
+ { "c.swsp", rv_codec_css_swsp, rv_fmt_rs2_offset_rs1, DECOMP(rv_op_sw) },
+ { "c.fswsp", rv_codec_css_swsp, rv_fmt_frs2_offset_rs1, DECOMP(rv_op_fsw) },
+ { "c.ld", rv_codec_cl_ld, rv_fmt_rd_offset_rs1, DECOMP(rv_op_ld) },
+ { "c.sd", rv_codec_cs_sd, rv_fmt_rs2_offset_rs1, DECOMP(rv_op_sd) },
+ { "c.addiw", rv_codec_ci, rv_fmt_rd_rs1_imm, DECOMP(rv_op_addiw) },
+ { "c.ldsp", rv_codec_ci_ldsp, rv_fmt_rd_offset_rs1, DECOMP(rv_op_ld) },
+ { "c.sdsp", rv_codec_css_sdsp, rv_fmt_rs2_offset_rs1, DECOMP(rv_op_sd) },
+ { "c.lq", rv_codec_cl_lq, rv_fmt_rd_offset_rs1, DECOMP(rv_op_lq) },
+ { "c.sq", rv_codec_cs_sq, rv_fmt_rs2_offset_rs1, DECOMP(rv_op_sq) },
+ { "c.lqsp", rv_codec_ci_lqsp, rv_fmt_rd_offset_rs1, DECOMP(rv_op_lq) },
+ { "c.sqsp", rv_codec_css_sqsp, rv_fmt_rs2_offset_rs1, DECOMP(rv_op_sq) },
{ "nop", rv_codec_i, rv_fmt_none },
{ "mv", rv_codec_i, rv_fmt_rd_rs1 },
{ "not", rv_codec_i, rv_fmt_rd_rs1 },
@@ -2542,8 +2546,8 @@ static const rv_opcode_data rvi_opcode_data[] = {
{ "ssrdp", rv_codec_r, rv_fmt_rd },
{ "ssamoswap.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
{ "ssamoswap.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
- { "c.sspush", rv_codec_cmop_ss, rv_fmt_rs2, NULL, rv_op_sspush },
- { "c.sspopchk", rv_codec_cmop_ss, rv_fmt_rs1, NULL, rv_op_sspopchk },
+ { "c.sspush", rv_codec_cmop_ss, rv_fmt_rs2, DECOMP(rv_op_sspush) },
+ { "c.sspopchk", rv_codec_cmop_ss, rv_fmt_rs1, DECOMP(rv_op_sspopchk) },
{ "cbo.inval", rv_codec_r, rv_fmt_rs1 },
{ "cbo.clean", rv_codec_r, rv_fmt_rs1 },
{ "cbo.flush", rv_codec_r, rv_fmt_rs1 },
@@ -5269,20 +5273,6 @@ static const rv_opcode_data *decode_inst_lift_pseudo(rv_decode *dec,
return op;
}
-/* decompress instruction */
-
-static const rv_opcode_data *decode_inst_decompress(rv_decode *dec,
- const rv_opcode_data *op)
-{
- int decomp_op = op->decomp;
-
- if (decomp_op != rv_op_illegal) {
- dec->op = decomp_op;
- op = &dec->opcode_data[decomp_op];
- }
- return op;
-}
-
/* disassemble instruction */
static GString *disasm_inst(rv_isa isa, uint64_t pc, rv_inst inst,
@@ -5333,7 +5323,6 @@ static GString *disasm_inst(rv_isa isa, uint64_t pc, rv_inst inst,
op = &dec.opcode_data[dec.op];
decode_inst_operands(&dec, isa, op);
- op = decode_inst_decompress(&dec, op);
op = decode_inst_lift_pseudo(&dec, op);
return format_inst(24, &dec, op);
}
--
2.43.0
^ permalink raw reply related [flat|nested] 119+ messages in thread
* [PATCH 33/56] disas/riscv: Drop format from DECOMP insns
2026-08-09 22:34 [RFC PATCH 00/56] disas/riscv: Reorganize the disassembler Richard Henderson
` (31 preceding siblings ...)
2026-08-09 22:35 ` [PATCH 32/56] disas/riscv: Handle decompression via decode_inst_lift_pseudo Richard Henderson
@ 2026-08-09 22:35 ` Richard Henderson
2026-08-11 20:25 ` Alistair
2026-08-09 22:35 ` [PATCH 34/56] disas/riscv: Tidy rv_comp_data terminators Richard Henderson
` (22 subsequent siblings)
55 siblings, 1 reply; 119+ messages in thread
From: Richard Henderson @ 2026-08-09 22:35 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-riscv
The format for these will never be used -- we will use
the format from the decompressed insn.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
disas/riscv.c | 94 +++++++++++++++++++++++++--------------------------
1 file changed, 47 insertions(+), 47 deletions(-)
diff --git a/disas/riscv.c b/disas/riscv.c
index 129e545c6e..9904b4db03 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -1819,52 +1819,52 @@ static const rv_opcode_data rvi_opcode_data[] = {
{ "fcvt.q.lu", rv_codec_r_m, rv_fmt_rm_frd_rs1 },
{ "fmv.x.q", rv_codec_r, rv_fmt_rd_frs1 },
{ "fmv.q.x", rv_codec_r, rv_fmt_frd_rs1 },
- { "c.addi4spn", rv_codec_ciw_4spn, rv_fmt_rd_rs1_imm, DECOMP(rv_op_addi) },
- { "c.fld", rv_codec_cl_ld, rv_fmt_frd_offset_rs1, DECOMP(rv_op_fld) },
- { "c.lw", rv_codec_cl_lw, rv_fmt_rd_offset_rs1, DECOMP(rv_op_lw) },
- { "c.flw", rv_codec_cl_lw, rv_fmt_frd_offset_rs1, DECOMP(rv_op_flw) },
- { "c.fsd", rv_codec_cs_sd, rv_fmt_frs2_offset_rs1, DECOMP(rv_op_fsd) },
- { "c.sw", rv_codec_cs_sw, rv_fmt_rs2_offset_rs1, DECOMP(rv_op_sw) },
- { "c.fsw", rv_codec_cs_sw, rv_fmt_frs2_offset_rs1, DECOMP(rv_op_fsw) },
+ { "c.addi4spn", rv_codec_ciw_4spn, NULL, DECOMP(rv_op_addi) },
+ { "c.fld", rv_codec_cl_ld, NULL, DECOMP(rv_op_fld) },
+ { "c.lw", rv_codec_cl_lw, NULL, DECOMP(rv_op_lw) },
+ { "c.flw", rv_codec_cl_lw, NULL, DECOMP(rv_op_flw) },
+ { "c.fsd", rv_codec_cs_sd, NULL, DECOMP(rv_op_fsd) },
+ { "c.sw", rv_codec_cs_sw, NULL, DECOMP(rv_op_sw) },
+ { "c.fsw", rv_codec_cs_sw, NULL, DECOMP(rv_op_fsw) },
{ },
- { "c.addi", rv_codec_ci, rv_fmt_rd_rs1_imm, DECOMP(rv_op_addi) },
- { "c.jal", rv_codec_cj_jal, rv_fmt_rd_offset, DECOMP(rv_op_jal) },
- { "c.li", rv_codec_ci_li, rv_fmt_rd_rs1_imm, DECOMP(rv_op_addi) },
- { "c.addi16sp", rv_codec_ci_16sp, rv_fmt_rd_rs1_imm, DECOMP(rv_op_addi) },
- { "c.lui", rv_codec_ci_lui, rv_fmt_rd_uimm, DECOMP(rv_op_lui) },
- { "c.srli", rv_codec_cb_sh6, rv_fmt_rd_rs1_imm, DECOMP(rv_op_srli) },
- { "c.srai", rv_codec_cb_sh6, rv_fmt_rd_rs1_imm, DECOMP(rv_op_srai) },
- { "c.andi", rv_codec_cb_imm, rv_fmt_rd_rs1_imm, DECOMP(rv_op_andi) },
- { "c.sub", rv_codec_cs, rv_fmt_rd_rs1_rs2, DECOMP(rv_op_sub) },
- { "c.xor", rv_codec_cs, rv_fmt_rd_rs1_rs2, DECOMP(rv_op_xor) },
- { "c.or", rv_codec_cs, rv_fmt_rd_rs1_rs2, DECOMP(rv_op_or) },
- { "c.and", rv_codec_cs, rv_fmt_rd_rs1_rs2, DECOMP(rv_op_and) },
- { "c.subw", rv_codec_cs, rv_fmt_rd_rs1_rs2, DECOMP(rv_op_subw) },
- { "c.addw", rv_codec_cs, rv_fmt_rd_rs1_rs2, DECOMP(rv_op_addw) },
- { "c.j", rv_codec_cj, rv_fmt_rd_offset, DECOMP(rv_op_jal) },
- { "c.beqz", rv_codec_cb, rv_fmt_rs1_rs2_offset, DECOMP(rv_op_beq) },
- { "c.bnez", rv_codec_cb, rv_fmt_rs1_rs2_offset, DECOMP(rv_op_bne) },
- { "c.slli", rv_codec_ci_sh6, rv_fmt_rd_rs1_imm, DECOMP(rv_op_slli) },
- { "c.fldsp", rv_codec_ci_ldsp, rv_fmt_frd_offset_rs1, DECOMP(rv_op_fld) },
- { "c.lwsp", rv_codec_ci_lwsp, rv_fmt_rd_offset_rs1, DECOMP(rv_op_lw) },
- { "c.flwsp", rv_codec_ci_lwsp, rv_fmt_frd_offset_rs1, DECOMP(rv_op_flw) },
- { "c.jr", rv_codec_cr_jr, rv_fmt_rd_rs1_offset, DECOMP(rv_op_jalr) },
- { "c.mv", rv_codec_cr_mv, rv_fmt_rd_rs1_rs2, DECOMP(rv_op_addi) },
- { "c.ebreak", rv_codec_ci_none, rv_fmt_none, DECOMP(rv_op_ebreak) },
- { "c.jalr", rv_codec_cr_jalr, rv_fmt_rd_rs1_offset, DECOMP(rv_op_jalr) },
- { "c.add", rv_codec_cr, rv_fmt_rd_rs1_rs2, DECOMP(rv_op_add) },
- { "c.fsdsp", rv_codec_css_sdsp, rv_fmt_frs2_offset_rs1, DECOMP(rv_op_fsd) },
- { "c.swsp", rv_codec_css_swsp, rv_fmt_rs2_offset_rs1, DECOMP(rv_op_sw) },
- { "c.fswsp", rv_codec_css_swsp, rv_fmt_frs2_offset_rs1, DECOMP(rv_op_fsw) },
- { "c.ld", rv_codec_cl_ld, rv_fmt_rd_offset_rs1, DECOMP(rv_op_ld) },
- { "c.sd", rv_codec_cs_sd, rv_fmt_rs2_offset_rs1, DECOMP(rv_op_sd) },
- { "c.addiw", rv_codec_ci, rv_fmt_rd_rs1_imm, DECOMP(rv_op_addiw) },
- { "c.ldsp", rv_codec_ci_ldsp, rv_fmt_rd_offset_rs1, DECOMP(rv_op_ld) },
- { "c.sdsp", rv_codec_css_sdsp, rv_fmt_rs2_offset_rs1, DECOMP(rv_op_sd) },
- { "c.lq", rv_codec_cl_lq, rv_fmt_rd_offset_rs1, DECOMP(rv_op_lq) },
- { "c.sq", rv_codec_cs_sq, rv_fmt_rs2_offset_rs1, DECOMP(rv_op_sq) },
- { "c.lqsp", rv_codec_ci_lqsp, rv_fmt_rd_offset_rs1, DECOMP(rv_op_lq) },
- { "c.sqsp", rv_codec_css_sqsp, rv_fmt_rs2_offset_rs1, DECOMP(rv_op_sq) },
+ { "c.addi", rv_codec_ci, NULL, DECOMP(rv_op_addi) },
+ { "c.jal", rv_codec_cj_jal, NULL, DECOMP(rv_op_jal) },
+ { "c.li", rv_codec_ci_li, NULL, DECOMP(rv_op_addi) },
+ { "c.addi16sp", rv_codec_ci_16sp, NULL, DECOMP(rv_op_addi) },
+ { "c.lui", rv_codec_ci_lui, NULL, DECOMP(rv_op_lui) },
+ { "c.srli", rv_codec_cb_sh6, NULL, DECOMP(rv_op_srli) },
+ { "c.srai", rv_codec_cb_sh6, NULL, DECOMP(rv_op_srai) },
+ { "c.andi", rv_codec_cb_imm, NULL, DECOMP(rv_op_andi) },
+ { "c.sub", rv_codec_cs, NULL, DECOMP(rv_op_sub) },
+ { "c.xor", rv_codec_cs, NULL, DECOMP(rv_op_xor) },
+ { "c.or", rv_codec_cs, NULL, DECOMP(rv_op_or) },
+ { "c.and", rv_codec_cs, NULL, DECOMP(rv_op_and) },
+ { "c.subw", rv_codec_cs, NULL, DECOMP(rv_op_subw) },
+ { "c.addw", rv_codec_cs, NULL, DECOMP(rv_op_addw) },
+ { "c.j", rv_codec_cj, NULL, DECOMP(rv_op_jal) },
+ { "c.beqz", rv_codec_cb, NULL, DECOMP(rv_op_beq) },
+ { "c.bnez", rv_codec_cb, NULL, DECOMP(rv_op_bne) },
+ { "c.slli", rv_codec_ci_sh6, NULL, DECOMP(rv_op_slli) },
+ { "c.fldsp", rv_codec_ci_ldsp, NULL, DECOMP(rv_op_fld) },
+ { "c.lwsp", rv_codec_ci_lwsp, NULL, DECOMP(rv_op_lw) },
+ { "c.flwsp", rv_codec_ci_lwsp, NULL, DECOMP(rv_op_flw) },
+ { "c.jr", rv_codec_cr_jr, NULL, DECOMP(rv_op_jalr) },
+ { "c.mv", rv_codec_cr_mv, NULL, DECOMP(rv_op_addi) },
+ { "c.ebreak", rv_codec_ci_none, NULL, DECOMP(rv_op_ebreak) },
+ { "c.jalr", rv_codec_cr_jalr, NULL, DECOMP(rv_op_jalr) },
+ { "c.add", rv_codec_cr, NULL, DECOMP(rv_op_add) },
+ { "c.fsdsp", rv_codec_css_sdsp, NULL, DECOMP(rv_op_fsd) },
+ { "c.swsp", rv_codec_css_swsp, NULL, DECOMP(rv_op_sw) },
+ { "c.fswsp", rv_codec_css_swsp, NULL, DECOMP(rv_op_fsw) },
+ { "c.ld", rv_codec_cl_ld, NULL, DECOMP(rv_op_ld) },
+ { "c.sd", rv_codec_cs_sd, NULL, DECOMP(rv_op_sd) },
+ { "c.addiw", rv_codec_ci, NULL, DECOMP(rv_op_addiw) },
+ { "c.ldsp", rv_codec_ci_ldsp, NULL, DECOMP(rv_op_ld) },
+ { "c.sdsp", rv_codec_css_sdsp, NULL, DECOMP(rv_op_sd) },
+ { "c.lq", rv_codec_cl_lq, NULL, DECOMP(rv_op_lq) },
+ { "c.sq", rv_codec_cs_sq, NULL, DECOMP(rv_op_sq) },
+ { "c.lqsp", rv_codec_ci_lqsp, NULL, DECOMP(rv_op_lq) },
+ { "c.sqsp", rv_codec_css_sqsp, NULL, DECOMP(rv_op_sq) },
{ "nop", rv_codec_i, rv_fmt_none },
{ "mv", rv_codec_i, rv_fmt_rd_rs1 },
{ "not", rv_codec_i, rv_fmt_rd_rs1 },
@@ -2546,8 +2546,8 @@ static const rv_opcode_data rvi_opcode_data[] = {
{ "ssrdp", rv_codec_r, rv_fmt_rd },
{ "ssamoswap.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
{ "ssamoswap.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
- { "c.sspush", rv_codec_cmop_ss, rv_fmt_rs2, DECOMP(rv_op_sspush) },
- { "c.sspopchk", rv_codec_cmop_ss, rv_fmt_rs1, DECOMP(rv_op_sspopchk) },
+ { "c.sspush", rv_codec_cmop_ss, NULL, DECOMP(rv_op_sspush) },
+ { "c.sspopchk", rv_codec_cmop_ss, NULL, DECOMP(rv_op_sspopchk) },
{ "cbo.inval", rv_codec_r, rv_fmt_rs1 },
{ "cbo.clean", rv_codec_r, rv_fmt_rs1 },
{ "cbo.flush", rv_codec_r, rv_fmt_rs1 },
--
2.43.0
^ permalink raw reply related [flat|nested] 119+ messages in thread
* [PATCH 34/56] disas/riscv: Tidy rv_comp_data terminators
2026-08-09 22:34 [RFC PATCH 00/56] disas/riscv: Reorganize the disassembler Richard Henderson
` (32 preceding siblings ...)
2026-08-09 22:35 ` [PATCH 33/56] disas/riscv: Drop format from DECOMP insns Richard Henderson
@ 2026-08-09 22:35 ` Richard Henderson
2026-08-11 20:25 ` Alistair
2026-08-09 22:35 ` [PATCH 35/56] disas/riscv: Chain "ret" pseudo off "jr" pseudo Richard Henderson
` (21 subsequent siblings)
55 siblings, 1 reply; 119+ messages in thread
From: Richard Henderson @ 2026-08-09 22:35 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-riscv
Use { } instead of two zeros.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
disas/riscv.c | 46 +++++++++++++++++++++++-----------------------
1 file changed, 23 insertions(+), 23 deletions(-)
diff --git a/disas/riscv.c b/disas/riscv.c
index 9904b4db03..bb4779614b 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -1072,123 +1072,123 @@ static const rvc_constraint rvcc_true[] = { rvc_end };
static const rv_comp_data rvcp_jal[] = {
{ rv_op_j, rvcc_j },
{ rv_op_jal_ra, rvcc_jal_ra },
- { rv_op_illegal, NULL }
+ { },
};
static const rv_comp_data rvcp_jalr[] = {
{ rv_op_ret, rvcc_ret },
{ rv_op_jr, rvcc_jr },
{ rv_op_jalr_ra, rvcc_jalr_ra },
- { rv_op_illegal, NULL }
+ { },
};
static const rv_comp_data rvcp_beq[] = {
{ rv_op_beqz, rvcc_beqz },
- { rv_op_illegal, NULL }
+ { },
};
static const rv_comp_data rvcp_bne[] = {
{ rv_op_bnez, rvcc_bnez },
- { rv_op_illegal, NULL }
+ { },
};
static const rv_comp_data rvcp_blt[] = {
{ rv_op_bltz, rvcc_bltz },
{ rv_op_bgtz, rvcc_bgtz },
- { rv_op_illegal, NULL }
+ { },
};
static const rv_comp_data rvcp_bge[] = {
{ rv_op_blez, rvcc_blez },
{ rv_op_bgez, rvcc_bgez },
- { rv_op_illegal, NULL }
+ { },
};
static const rv_comp_data rvcp_addi[] = {
{ rv_op_nop, rvcc_nop },
{ rv_op_mv, rvcc_mv },
- { rv_op_illegal, NULL }
+ { },
};
static const rv_comp_data rvcp_sltiu[] = {
{ rv_op_seqz, rvcc_seqz },
- { rv_op_illegal, NULL }
+ { },
};
static const rv_comp_data rvcp_xori[] = {
{ rv_op_not, rvcc_not },
- { rv_op_illegal, NULL }
+ { },
};
static const rv_comp_data rvcp_sub[] = {
{ rv_op_neg, rvcc_neg },
- { rv_op_illegal, NULL }
+ { },
};
static const rv_comp_data rvcp_slt[] = {
{ rv_op_sltz, rvcc_sltz },
{ rv_op_sgtz, rvcc_sgtz },
- { rv_op_illegal, NULL }
+ { },
};
static const rv_comp_data rvcp_sltu[] = {
{ rv_op_snez, rvcc_snez },
- { rv_op_illegal, NULL }
+ { },
};
static const rv_comp_data rvcp_addiw[] = {
{ rv_op_sext_w, rvcc_sext_w },
- { rv_op_illegal, NULL }
+ { },
};
static const rv_comp_data rvcp_subw[] = {
{ rv_op_negw, rvcc_negw },
- { rv_op_illegal, NULL }
+ { },
};
static const rv_comp_data rvcp_fsgnj_s[] = {
{ rv_op_fmv_s, rvcc_fmv_s },
- { rv_op_illegal, NULL }
+ { },
};
static const rv_comp_data rvcp_fsgnjn_s[] = {
{ rv_op_fneg_s, rvcc_fneg_s },
- { rv_op_illegal, NULL }
+ { },
};
static const rv_comp_data rvcp_fsgnjx_s[] = {
{ rv_op_fabs_s, rvcc_fabs_s },
- { rv_op_illegal, NULL }
+ { },
};
static const rv_comp_data rvcp_fsgnj_d[] = {
{ rv_op_fmv_d, rvcc_fmv_d },
- { rv_op_illegal, NULL }
+ { },
};
static const rv_comp_data rvcp_fsgnjn_d[] = {
{ rv_op_fneg_d, rvcc_fneg_d },
- { rv_op_illegal, NULL }
+ { },
};
static const rv_comp_data rvcp_fsgnjx_d[] = {
{ rv_op_fabs_d, rvcc_fabs_d },
- { rv_op_illegal, NULL }
+ { },
};
static const rv_comp_data rvcp_fsgnj_q[] = {
{ rv_op_fmv_q, rvcc_fmv_q },
- { rv_op_illegal, NULL }
+ { },
};
static const rv_comp_data rvcp_fsgnjn_q[] = {
{ rv_op_fneg_q, rvcc_fneg_q },
- { rv_op_illegal, NULL }
+ { },
};
static const rv_comp_data rvcp_fsgnjx_q[] = {
{ rv_op_fabs_q, rvcc_fabs_q },
- { rv_op_illegal, NULL }
+ { },
};
/* Convert compressed insns into normal insns via pseudo expansion. */
--
2.43.0
^ permalink raw reply related [flat|nested] 119+ messages in thread
* [PATCH 35/56] disas/riscv: Chain "ret" pseudo off "jr" pseudo
2026-08-09 22:34 [RFC PATCH 00/56] disas/riscv: Reorganize the disassembler Richard Henderson
` (33 preceding siblings ...)
2026-08-09 22:35 ` [PATCH 34/56] disas/riscv: Tidy rv_comp_data terminators Richard Henderson
@ 2026-08-09 22:35 ` Richard Henderson
2026-08-11 20:26 ` Alistair
2026-08-09 22:35 ` [PATCH 36/56] disas/riscv: Chain "nop" pseudo off "mv" pseudo Richard Henderson
` (20 subsequent siblings)
55 siblings, 1 reply; 119+ messages in thread
From: Richard Henderson @ 2026-08-09 22:35 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-riscv
"jr" has already checked two conditions that apply to "ret".
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
disas/riscv.c | 11 +++++++----
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/disas/riscv.c b/disas/riscv.c
index bb4779614b..2fec135b5f 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -1061,8 +1061,7 @@ static const rvc_constraint rvcc_bgez[] = { rvc_rs2_eq_x0, rvc_end };
static const rvc_constraint rvcc_bltz[] = { rvc_rs2_eq_x0, rvc_end };
static const rvc_constraint rvcc_bgtz[] = { rvc_rs1_eq_x0, rvc_end };
static const rvc_constraint rvcc_j[] = { rvc_rd_eq_x0, rvc_end };
-static const rvc_constraint rvcc_ret[] = { rvc_rd_eq_x0, rvc_rs1_eq_ra,
- rvc_end };
+static const rvc_constraint rvcc_ret[] = { rvc_rs1_eq_ra, rvc_end };
static const rvc_constraint rvcc_jr[] = { rvc_rd_eq_x0, rvc_imm_eq_zero,
rvc_end };
static const rvc_constraint rvcc_true[] = { rvc_end };
@@ -1076,12 +1075,16 @@ static const rv_comp_data rvcp_jal[] = {
};
static const rv_comp_data rvcp_jalr[] = {
- { rv_op_ret, rvcc_ret },
{ rv_op_jr, rvcc_jr },
{ rv_op_jalr_ra, rvcc_jalr_ra },
{ },
};
+static const rv_comp_data rvcp_jr[] = {
+ { rv_op_ret, rvcc_ret },
+ { },
+};
+
static const rv_comp_data rvcp_beq[] = {
{ rv_op_beqz, rvcc_beqz },
{ },
@@ -1896,7 +1899,7 @@ static const rv_opcode_data rvi_opcode_data[] = {
{ },
{ "j", rv_codec_uj, rv_fmt_offset },
{ "ret", rv_codec_i, rv_fmt_none },
- { "jr", rv_codec_i, rv_fmt_rs1 },
+ { "jr", rv_codec_i, rv_fmt_rs1, rvcp_jr },
{ "rdcycle", rv_codec_i_csr, rv_fmt_rd },
{ "rdtime", rv_codec_i_csr, rv_fmt_rd },
{ "rdinstret", rv_codec_i_csr, rv_fmt_rd },
--
2.43.0
^ permalink raw reply related [flat|nested] 119+ messages in thread
* [PATCH 36/56] disas/riscv: Chain "nop" pseudo off "mv" pseudo
2026-08-09 22:34 [RFC PATCH 00/56] disas/riscv: Reorganize the disassembler Richard Henderson
` (34 preceding siblings ...)
2026-08-09 22:35 ` [PATCH 35/56] disas/riscv: Chain "ret" pseudo off "jr" pseudo Richard Henderson
@ 2026-08-09 22:35 ` Richard Henderson
2026-08-11 20:27 ` Alistair
2026-08-09 22:35 ` [PATCH 37/56] disas/riscv: Use rv_codec_illegal for pseudos Richard Henderson
` (19 subsequent siblings)
55 siblings, 1 reply; 119+ messages in thread
From: Richard Henderson @ 2026-08-09 22:35 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-riscv
"mv" has already checked a condition that applies to "nop".
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
disas/riscv.c | 10 +++++++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/disas/riscv.c b/disas/riscv.c
index 2fec135b5f..37f6440831 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -1035,7 +1035,7 @@ static const rvc_constraint rvcc_jal_ra[] = { rvc_rd_eq_ra, rvc_end };
static const rvc_constraint rvcc_jalr_ra[] = { rvc_rd_eq_ra, rvc_imm_eq_zero,
rvc_end };
static const rvc_constraint rvcc_nop[] = { rvc_rd_eq_x0, rvc_rs1_eq_x0,
- rvc_imm_eq_zero, rvc_end };
+ rvc_end };
static const rvc_constraint rvcc_mv[] = { rvc_imm_eq_zero, rvc_end };
static const rvc_constraint rvcc_not[] = { rvc_imm_eq_n1, rvc_end };
static const rvc_constraint rvcc_neg[] = { rvc_rs1_eq_x0, rvc_end };
@@ -1108,11 +1108,15 @@ static const rv_comp_data rvcp_bge[] = {
};
static const rv_comp_data rvcp_addi[] = {
- { rv_op_nop, rvcc_nop },
{ rv_op_mv, rvcc_mv },
{ },
};
+static const rv_comp_data rvcp_mv[] = {
+ { rv_op_nop, rvcc_nop },
+ { },
+};
+
static const rv_comp_data rvcp_sltiu[] = {
{ rv_op_seqz, rvcc_seqz },
{ },
@@ -1869,7 +1873,7 @@ static const rv_opcode_data rvi_opcode_data[] = {
{ "c.lqsp", rv_codec_ci_lqsp, NULL, DECOMP(rv_op_lq) },
{ "c.sqsp", rv_codec_css_sqsp, NULL, DECOMP(rv_op_sq) },
{ "nop", rv_codec_i, rv_fmt_none },
- { "mv", rv_codec_i, rv_fmt_rd_rs1 },
+ { "mv", rv_codec_i, rv_fmt_rd_rs1, rvcp_mv },
{ "not", rv_codec_i, rv_fmt_rd_rs1 },
{ "neg", rv_codec_r, rv_fmt_rd_rs2 },
{ "negw", rv_codec_r, rv_fmt_rd_rs2 },
--
2.43.0
^ permalink raw reply related [flat|nested] 119+ messages in thread
* [PATCH 37/56] disas/riscv: Use rv_codec_illegal for pseudos
2026-08-09 22:34 [RFC PATCH 00/56] disas/riscv: Reorganize the disassembler Richard Henderson
` (35 preceding siblings ...)
2026-08-09 22:35 ` [PATCH 36/56] disas/riscv: Chain "nop" pseudo off "mv" pseudo Richard Henderson
@ 2026-08-09 22:35 ` Richard Henderson
2026-08-11 20:27 ` Alistair
2026-08-09 22:35 ` [PATCH 38/56] disas/riscv: Simplify some insn decompressions Richard Henderson
` (18 subsequent siblings)
55 siblings, 1 reply; 119+ messages in thread
From: Richard Henderson @ 2026-08-09 22:35 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-riscv
The codec is never used, since we arrive into pseudos
from a decoding of another opcode.
Assert that rv_codec_illegal is never decoded.
Use rv_codec_none for rv_op_illegal.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
disas/riscv.c | 68 +++++++++++++++++++++++++--------------------------
1 file changed, 34 insertions(+), 34 deletions(-)
diff --git a/disas/riscv.c b/disas/riscv.c
index 37f6440831..fc821355fe 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -1599,7 +1599,7 @@ static uint32_t operand_lpl(rv_inst inst)
/* instruction metadata */
static const rv_opcode_data rvi_opcode_data[] = {
- { "illegal", rv_codec_illegal, rv_fmt_none },
+ { "illegal", rv_codec_none, rv_fmt_none },
{ "lui", rv_codec_u, rv_fmt_rd_uimm },
{ "auipc", rv_codec_u, rv_fmt_rd_uoffset },
{ "jal", rv_codec_uj, rv_fmt_rd_offset, rvcp_jal },
@@ -1872,38 +1872,38 @@ static const rv_opcode_data rvi_opcode_data[] = {
{ "c.sq", rv_codec_cs_sq, NULL, DECOMP(rv_op_sq) },
{ "c.lqsp", rv_codec_ci_lqsp, NULL, DECOMP(rv_op_lq) },
{ "c.sqsp", rv_codec_css_sqsp, NULL, DECOMP(rv_op_sq) },
- { "nop", rv_codec_i, rv_fmt_none },
- { "mv", rv_codec_i, rv_fmt_rd_rs1, rvcp_mv },
- { "not", rv_codec_i, rv_fmt_rd_rs1 },
- { "neg", rv_codec_r, rv_fmt_rd_rs2 },
- { "negw", rv_codec_r, rv_fmt_rd_rs2 },
- { "sext.w", rv_codec_i, rv_fmt_rd_rs1 },
- { "seqz", rv_codec_i, rv_fmt_rd_rs1 },
- { "snez", rv_codec_r, rv_fmt_rd_rs2 },
- { "sltz", rv_codec_r, rv_fmt_rd_rs1 },
- { "sgtz", rv_codec_r, rv_fmt_rd_rs2 },
- { "fmv.s", rv_codec_r, rv_fmt_frd_frs1 },
- { "fabs.s", rv_codec_r, rv_fmt_frd_frs1 },
- { "fneg.s", rv_codec_r, rv_fmt_frd_frs1 },
- { "fmv.d", rv_codec_r, rv_fmt_frd_frs1 },
- { "fabs.d", rv_codec_r, rv_fmt_frd_frs1 },
- { "fneg.d", rv_codec_r, rv_fmt_frd_frs1 },
- { "fmv.q", rv_codec_r, rv_fmt_frd_frs1 },
- { "fabs.q", rv_codec_r, rv_fmt_frd_frs1 },
- { "fneg.q", rv_codec_r, rv_fmt_frd_frs1 },
- { "beqz", rv_codec_sb, rv_fmt_rs1_offset },
- { "bnez", rv_codec_sb, rv_fmt_rs1_offset },
- { "blez", rv_codec_sb, rv_fmt_rs2_offset },
- { "bgez", rv_codec_sb, rv_fmt_rs1_offset },
- { "bltz", rv_codec_sb, rv_fmt_rs1_offset },
- { "bgtz", rv_codec_sb, rv_fmt_rs2_offset },
- { "jal", rv_codec_none, rv_fmt_offset }, /* rv_op_jal_ra */
- { "jalr", rv_codec_none, rv_fmt_rs1 }, /* rv_op_jalr_ra */
+ { "nop", rv_codec_illegal, rv_fmt_none },
+ { "mv", rv_codec_illegal, rv_fmt_rd_rs1, rvcp_mv },
+ { "not", rv_codec_illegal, rv_fmt_rd_rs1 },
+ { "neg", rv_codec_illegal, rv_fmt_rd_rs2 },
+ { "negw", rv_codec_illegal, rv_fmt_rd_rs2 },
+ { "sext.w", rv_codec_illegal, rv_fmt_rd_rs1 },
+ { "seqz", rv_codec_illegal, rv_fmt_rd_rs1 },
+ { "snez", rv_codec_illegal, rv_fmt_rd_rs2 },
+ { "sltz", rv_codec_illegal, rv_fmt_rd_rs1 },
+ { "sgtz", rv_codec_illegal, rv_fmt_rd_rs2 },
+ { "fmv.s", rv_codec_illegal, rv_fmt_frd_frs1 },
+ { "fabs.s", rv_codec_illegal, rv_fmt_frd_frs1 },
+ { "fneg.s", rv_codec_illegal, rv_fmt_frd_frs1 },
+ { "fmv.d", rv_codec_illegal, rv_fmt_frd_frs1 },
+ { "fabs.d", rv_codec_illegal, rv_fmt_frd_frs1 },
+ { "fneg.d", rv_codec_illegal, rv_fmt_frd_frs1 },
+ { "fmv.q", rv_codec_illegal, rv_fmt_frd_frs1 },
+ { "fabs.q", rv_codec_illegal, rv_fmt_frd_frs1 },
+ { "fneg.q", rv_codec_illegal, rv_fmt_frd_frs1 },
+ { "beqz", rv_codec_illegal, rv_fmt_rs1_offset },
+ { "bnez", rv_codec_illegal, rv_fmt_rs1_offset },
+ { "blez", rv_codec_illegal, rv_fmt_rs2_offset },
+ { "bgez", rv_codec_illegal, rv_fmt_rs1_offset },
+ { "bltz", rv_codec_illegal, rv_fmt_rs1_offset },
+ { "bgtz", rv_codec_illegal, rv_fmt_rs2_offset },
+ { "jal", rv_codec_illegal, rv_fmt_offset }, /* rv_op_jal_ra */
+ { "jalr", rv_codec_illegal, rv_fmt_rs1 }, /* rv_op_jalr_ra */
{ },
{ },
- { "j", rv_codec_uj, rv_fmt_offset },
- { "ret", rv_codec_i, rv_fmt_none },
- { "jr", rv_codec_i, rv_fmt_rs1, rvcp_jr },
+ { "j", rv_codec_illegal, rv_fmt_offset },
+ { "ret", rv_codec_illegal, rv_fmt_none },
+ { "jr", rv_codec_illegal, rv_fmt_rs1, rvcp_jr },
{ "rdcycle", rv_codec_i_csr, rv_fmt_rd },
{ "rdtime", rv_codec_i_csr, rv_fmt_rd },
{ "rdinstret", rv_codec_i_csr, rv_fmt_rd },
@@ -4551,8 +4551,6 @@ static void decode_inst_operands(rv_decode *dec, rv_isa isa,
rv_inst inst = dec->inst;
switch (op->codec) {
- case rv_codec_illegal:
- break;
case rv_codec_none:
dec->rd = dec->rs1 = dec->rs2 = rv_ireg_zero;
dec->imm = 0;
@@ -4946,7 +4944,9 @@ static void decode_inst_operands(rv_decode *dec, rv_isa isa,
dec->rs1 = dec->rs2 = operand_crs1(inst);
dec->imm = 0;
break;
- };
+ default:
+ g_assert_not_reached();
+ }
}
/* check constraint */
--
2.43.0
^ permalink raw reply related [flat|nested] 119+ messages in thread
* [PATCH 38/56] disas/riscv: Simplify some insn decompressions
2026-08-09 22:34 [RFC PATCH 00/56] disas/riscv: Reorganize the disassembler Richard Henderson
` (36 preceding siblings ...)
2026-08-09 22:35 ` [PATCH 37/56] disas/riscv: Use rv_codec_illegal for pseudos Richard Henderson
@ 2026-08-09 22:35 ` Richard Henderson
2026-08-11 20:29 ` Alistair
2026-08-09 22:35 ` [PATCH 39/56] disas/riscv: Store op pointer in rv_comp_data Richard Henderson
` (17 subsequent siblings)
55 siblings, 1 reply; 119+ messages in thread
From: Richard Henderson @ 2026-08-09 22:35 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-riscv
Route "c.j" to "j" instead of "jal", etc.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
disas/riscv.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/disas/riscv.c b/disas/riscv.c
index fc821355fe..9a528803e8 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -1848,15 +1848,15 @@ static const rv_opcode_data rvi_opcode_data[] = {
{ "c.and", rv_codec_cs, NULL, DECOMP(rv_op_and) },
{ "c.subw", rv_codec_cs, NULL, DECOMP(rv_op_subw) },
{ "c.addw", rv_codec_cs, NULL, DECOMP(rv_op_addw) },
- { "c.j", rv_codec_cj, NULL, DECOMP(rv_op_jal) },
- { "c.beqz", rv_codec_cb, NULL, DECOMP(rv_op_beq) },
- { "c.bnez", rv_codec_cb, NULL, DECOMP(rv_op_bne) },
+ { "c.j", rv_codec_cj, NULL, DECOMP(rv_op_j) },
+ { "c.beqz", rv_codec_cb, NULL, DECOMP(rv_op_beqz) },
+ { "c.bnez", rv_codec_cb, NULL, DECOMP(rv_op_bnez) },
{ "c.slli", rv_codec_ci_sh6, NULL, DECOMP(rv_op_slli) },
{ "c.fldsp", rv_codec_ci_ldsp, NULL, DECOMP(rv_op_fld) },
{ "c.lwsp", rv_codec_ci_lwsp, NULL, DECOMP(rv_op_lw) },
{ "c.flwsp", rv_codec_ci_lwsp, NULL, DECOMP(rv_op_flw) },
- { "c.jr", rv_codec_cr_jr, NULL, DECOMP(rv_op_jalr) },
- { "c.mv", rv_codec_cr_mv, NULL, DECOMP(rv_op_addi) },
+ { "c.jr", rv_codec_cr_jr, NULL, DECOMP(rv_op_jr) },
+ { "c.mv", rv_codec_cr_mv, NULL, DECOMP(rv_op_mv) },
{ "c.ebreak", rv_codec_ci_none, NULL, DECOMP(rv_op_ebreak) },
{ "c.jalr", rv_codec_cr_jalr, NULL, DECOMP(rv_op_jalr) },
{ "c.add", rv_codec_cr, NULL, DECOMP(rv_op_add) },
--
2.43.0
^ permalink raw reply related [flat|nested] 119+ messages in thread
* [PATCH 39/56] disas/riscv: Store op pointer in rv_comp_data
2026-08-09 22:34 [RFC PATCH 00/56] disas/riscv: Reorganize the disassembler Richard Henderson
` (37 preceding siblings ...)
2026-08-09 22:35 ` [PATCH 38/56] disas/riscv: Simplify some insn decompressions Richard Henderson
@ 2026-08-09 22:35 ` Richard Henderson
2026-08-12 12:47 ` Alistair
2026-08-09 22:35 ` [PATCH 40/56] disas/riscv: Return rv_opcode_data pointer from decoders Richard Henderson
` (16 subsequent siblings)
55 siblings, 1 reply; 119+ messages in thread
From: Richard Henderson @ 2026-08-09 22:35 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-riscv
Store a pointer instead of an array index.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
disas/riscv.h | 8 +++---
disas/riscv.c | 69 ++++++++++++++++++++++++++-------------------------
2 files changed, 40 insertions(+), 37 deletions(-)
diff --git a/disas/riscv.h b/disas/riscv.h
index ea7141d3b5..ab62c0db94 100644
--- a/disas/riscv.h
+++ b/disas/riscv.h
@@ -164,17 +164,19 @@ typedef enum {
/* structures */
+typedef struct rv_opcode_data rv_opcode_data;
+
typedef struct {
- int op;
+ const rv_opcode_data *op;
const rvc_constraint *constraints;
} rv_comp_data;
-typedef struct {
+struct rv_opcode_data {
const char *name;
rv_codec codec;
const char *format;
const rv_comp_data *pseudo;
-} rv_opcode_data;
+};
typedef struct {
const RISCVCPUConfig *cfg;
diff --git a/disas/riscv.c b/disas/riscv.c
index 9a528803e8..171c60238f 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -1068,138 +1068,140 @@ static const rvc_constraint rvcc_true[] = { rvc_end };
/* pseudo-instruction metadata */
+static const rv_opcode_data rvi_opcode_data[];
+
static const rv_comp_data rvcp_jal[] = {
- { rv_op_j, rvcc_j },
- { rv_op_jal_ra, rvcc_jal_ra },
+ { &rvi_opcode_data[rv_op_j], rvcc_j },
+ { &rvi_opcode_data[rv_op_jal_ra], rvcc_jal_ra },
{ },
};
static const rv_comp_data rvcp_jalr[] = {
- { rv_op_jr, rvcc_jr },
- { rv_op_jalr_ra, rvcc_jalr_ra },
+ { &rvi_opcode_data[rv_op_jr], rvcc_jr },
+ { &rvi_opcode_data[rv_op_jalr_ra], rvcc_jalr_ra },
{ },
};
static const rv_comp_data rvcp_jr[] = {
- { rv_op_ret, rvcc_ret },
+ { &rvi_opcode_data[rv_op_ret], rvcc_ret },
{ },
};
static const rv_comp_data rvcp_beq[] = {
- { rv_op_beqz, rvcc_beqz },
+ { &rvi_opcode_data[rv_op_beqz], rvcc_beqz },
{ },
};
static const rv_comp_data rvcp_bne[] = {
- { rv_op_bnez, rvcc_bnez },
+ { &rvi_opcode_data[rv_op_bnez], rvcc_bnez },
{ },
};
static const rv_comp_data rvcp_blt[] = {
- { rv_op_bltz, rvcc_bltz },
- { rv_op_bgtz, rvcc_bgtz },
+ { &rvi_opcode_data[rv_op_bltz], rvcc_bltz },
+ { &rvi_opcode_data[rv_op_bgtz], rvcc_bgtz },
{ },
};
static const rv_comp_data rvcp_bge[] = {
- { rv_op_blez, rvcc_blez },
- { rv_op_bgez, rvcc_bgez },
+ { &rvi_opcode_data[rv_op_blez], rvcc_blez },
+ { &rvi_opcode_data[rv_op_bgez], rvcc_bgez },
{ },
};
static const rv_comp_data rvcp_addi[] = {
- { rv_op_mv, rvcc_mv },
+ { &rvi_opcode_data[rv_op_mv], rvcc_mv },
{ },
};
static const rv_comp_data rvcp_mv[] = {
- { rv_op_nop, rvcc_nop },
+ { &rvi_opcode_data[rv_op_nop], rvcc_nop },
{ },
};
static const rv_comp_data rvcp_sltiu[] = {
- { rv_op_seqz, rvcc_seqz },
+ { &rvi_opcode_data[rv_op_seqz], rvcc_seqz },
{ },
};
static const rv_comp_data rvcp_xori[] = {
- { rv_op_not, rvcc_not },
+ { &rvi_opcode_data[rv_op_not], rvcc_not },
{ },
};
static const rv_comp_data rvcp_sub[] = {
- { rv_op_neg, rvcc_neg },
+ { &rvi_opcode_data[rv_op_neg], rvcc_neg },
{ },
};
static const rv_comp_data rvcp_slt[] = {
- { rv_op_sltz, rvcc_sltz },
- { rv_op_sgtz, rvcc_sgtz },
+ { &rvi_opcode_data[rv_op_sltz], rvcc_sltz },
+ { &rvi_opcode_data[rv_op_sgtz], rvcc_sgtz },
{ },
};
static const rv_comp_data rvcp_sltu[] = {
- { rv_op_snez, rvcc_snez },
+ { &rvi_opcode_data[rv_op_snez], rvcc_snez },
{ },
};
static const rv_comp_data rvcp_addiw[] = {
- { rv_op_sext_w, rvcc_sext_w },
+ { &rvi_opcode_data[rv_op_sext_w], rvcc_sext_w },
{ },
};
static const rv_comp_data rvcp_subw[] = {
- { rv_op_negw, rvcc_negw },
+ { &rvi_opcode_data[rv_op_negw], rvcc_negw },
{ },
};
static const rv_comp_data rvcp_fsgnj_s[] = {
- { rv_op_fmv_s, rvcc_fmv_s },
+ { &rvi_opcode_data[rv_op_fmv_s], rvcc_fmv_s },
{ },
};
static const rv_comp_data rvcp_fsgnjn_s[] = {
- { rv_op_fneg_s, rvcc_fneg_s },
+ { &rvi_opcode_data[rv_op_fneg_s], rvcc_fneg_s },
{ },
};
static const rv_comp_data rvcp_fsgnjx_s[] = {
- { rv_op_fabs_s, rvcc_fabs_s },
+ { &rvi_opcode_data[rv_op_fabs_s], rvcc_fabs_s },
{ },
};
static const rv_comp_data rvcp_fsgnj_d[] = {
- { rv_op_fmv_d, rvcc_fmv_d },
+ { &rvi_opcode_data[rv_op_fmv_d], rvcc_fmv_d },
{ },
};
static const rv_comp_data rvcp_fsgnjn_d[] = {
- { rv_op_fneg_d, rvcc_fneg_d },
+ { &rvi_opcode_data[rv_op_fneg_d], rvcc_fneg_d },
{ },
};
static const rv_comp_data rvcp_fsgnjx_d[] = {
- { rv_op_fabs_d, rvcc_fabs_d },
+ { &rvi_opcode_data[rv_op_fabs_d], rvcc_fabs_d },
{ },
};
static const rv_comp_data rvcp_fsgnj_q[] = {
- { rv_op_fmv_q, rvcc_fmv_q },
+ { &rvi_opcode_data[rv_op_fmv_q], rvcc_fmv_q },
{ },
};
static const rv_comp_data rvcp_fsgnjn_q[] = {
- { rv_op_fneg_q, rvcc_fneg_q },
+ { &rvi_opcode_data[rv_op_fneg_q], rvcc_fneg_q },
{ },
};
static const rv_comp_data rvcp_fsgnjx_q[] = {
- { rv_op_fabs_q, rvcc_fabs_q },
+ { &rvi_opcode_data[rv_op_fabs_q], rvcc_fabs_q },
{ },
};
/* Convert compressed insns into normal insns via pseudo expansion. */
-#define DECOMP(X) (static const rv_comp_data[1]){ { X, rvcc_true } }
+#define DECOMP(X) (static const rv_comp_data[1]){ { &rvi_opcode_data[X], rvcc_true } }
/* operand extractors */
@@ -5270,9 +5272,8 @@ static const rv_opcode_data *decode_inst_lift_pseudo(rv_decode *dec,
if (comp_data) {
while (comp_data->constraints) {
if (check_constraints(dec, comp_data->constraints)) {
- const rv_opcode_data *new_op = &dec->opcode_data[comp_data->op];
- assert(new_op != op);
- return decode_inst_lift_pseudo(dec, new_op);
+ assert(op != comp_data->op);
+ return decode_inst_lift_pseudo(dec, comp_data->op);
}
comp_data++;
}
--
2.43.0
^ permalink raw reply related [flat|nested] 119+ messages in thread
* [PATCH 40/56] disas/riscv: Return rv_opcode_data pointer from decoders
2026-08-09 22:34 [RFC PATCH 00/56] disas/riscv: Reorganize the disassembler Richard Henderson
` (38 preceding siblings ...)
2026-08-09 22:35 ` [PATCH 39/56] disas/riscv: Store op pointer in rv_comp_data Richard Henderson
@ 2026-08-09 22:35 ` Richard Henderson
2026-08-12 12:48 ` Alistair
2026-08-09 22:35 ` [PATCH 41/56] disas/riscv: Reject all of OP-32 and OP-IMM-32 for RV32 Richard Henderson
` (15 subsequent siblings)
55 siblings, 1 reply; 119+ messages in thread
From: Richard Henderson @ 2026-08-09 22:35 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-riscv
Rather than putting array + index into rv_decode,
return the pointer to the object directly.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
disas/riscv-xlrbr.h | 2 +-
disas/riscv-xthead.h | 22 ++++++++---------
disas/riscv-xventana.h | 2 +-
disas/riscv.h | 2 --
disas/riscv-xlrbr.c | 5 ++--
disas/riscv-xthead.c | 55 +++++++++++++++++-------------------------
disas/riscv-xventana.c | 5 ++--
disas/riscv.c | 23 +++++++-----------
8 files changed, 48 insertions(+), 68 deletions(-)
diff --git a/disas/riscv-xlrbr.h b/disas/riscv-xlrbr.h
index ebf3d4c133..da14f1b340 100644
--- a/disas/riscv-xlrbr.h
+++ b/disas/riscv-xlrbr.h
@@ -12,6 +12,6 @@
#include "disas/riscv.h"
-void decode_xlrbr(rv_decode *, rv_isa);
+const rv_opcode_data *decode_xlrbr(rv_decode *, rv_isa);
#endif /* DISAS_RISCV_XLRBR_H */
diff --git a/disas/riscv-xthead.h b/disas/riscv-xthead.h
index 0c65c8e0af..f2160be8a4 100644
--- a/disas/riscv-xthead.h
+++ b/disas/riscv-xthead.h
@@ -11,16 +11,16 @@
#include "disas/riscv.h"
-void decode_xtheadba(rv_decode *, rv_isa);
-void decode_xtheadbb(rv_decode *, rv_isa);
-void decode_xtheadbs(rv_decode *, rv_isa);
-void decode_xtheadcmo(rv_decode *, rv_isa);
-void decode_xtheadcondmov(rv_decode *, rv_isa);
-void decode_xtheadfmemidx(rv_decode *, rv_isa);
-void decode_xtheadfmv(rv_decode *, rv_isa);
-void decode_xtheadmac(rv_decode *, rv_isa);
-void decode_xtheadmemidx(rv_decode *, rv_isa);
-void decode_xtheadmempair(rv_decode *, rv_isa);
-void decode_xtheadsync(rv_decode *, rv_isa);
+const rv_opcode_data *decode_xtheadba(rv_decode *, rv_isa);
+const rv_opcode_data *decode_xtheadbb(rv_decode *, rv_isa);
+const rv_opcode_data *decode_xtheadbs(rv_decode *, rv_isa);
+const rv_opcode_data *decode_xtheadcmo(rv_decode *, rv_isa);
+const rv_opcode_data *decode_xtheadcondmov(rv_decode *, rv_isa);
+const rv_opcode_data *decode_xtheadfmemidx(rv_decode *, rv_isa);
+const rv_opcode_data *decode_xtheadfmv(rv_decode *, rv_isa);
+const rv_opcode_data *decode_xtheadmac(rv_decode *, rv_isa);
+const rv_opcode_data *decode_xtheadmemidx(rv_decode *, rv_isa);
+const rv_opcode_data *decode_xtheadmempair(rv_decode *, rv_isa);
+const rv_opcode_data *decode_xtheadsync(rv_decode *, rv_isa);
#endif /* DISAS_RISCV_XTHEAD_H */
diff --git a/disas/riscv-xventana.h b/disas/riscv-xventana.h
index 1006c3be00..d28e84c7e4 100644
--- a/disas/riscv-xventana.h
+++ b/disas/riscv-xventana.h
@@ -11,6 +11,6 @@
#include "disas/riscv.h"
-void decode_xventanacondops(rv_decode*, rv_isa);
+const rv_opcode_data *decode_xventanacondops(rv_decode*, rv_isa);
#endif /* DISAS_RISCV_XVENTANA_H */
diff --git a/disas/riscv.h b/disas/riscv.h
index ab62c0db94..241dd47d7f 100644
--- a/disas/riscv.h
+++ b/disas/riscv.h
@@ -182,10 +182,8 @@ typedef struct {
const RISCVCPUConfig *cfg;
uint64_t pc;
uint64_t inst;
- const rv_opcode_data *opcode_data;
int32_t imm;
int32_t imm1;
- uint16_t op;
uint8_t rd;
uint8_t rs1;
uint8_t rs2;
diff --git a/disas/riscv-xlrbr.c b/disas/riscv-xlrbr.c
index d0092e9edd..b12916c9da 100644
--- a/disas/riscv-xlrbr.c
+++ b/disas/riscv-xlrbr.c
@@ -36,7 +36,7 @@ static const rv_opcode_data xlrbr_opcode_data[] = {
{ "crc32c.d", rv_codec_r, rv_fmt_rd_rs1 },
};
-void decode_xlrbr(rv_decode *dec, rv_isa isa)
+const rv_opcode_data *decode_xlrbr(rv_decode *dec, rv_isa isa)
{
rv_inst inst = dec->inst;
rv_opcode op = rv_op_illegal;
@@ -76,6 +76,5 @@ void decode_xlrbr(rv_decode *dec, rv_isa isa)
break;
}
- dec->opcode_data = xlrbr_opcode_data;
- dec->op = op;
+ return op == rv_op_illegal ? NULL : &xlrbr_opcode_data[op];
}
diff --git a/disas/riscv-xthead.c b/disas/riscv-xthead.c
index 757d6ff39f..428a6380e9 100644
--- a/disas/riscv-xthead.c
+++ b/disas/riscv-xthead.c
@@ -246,7 +246,7 @@ static const rv_opcode_data xthead_opcode_data[] = {
{ "th.sync.s", rv_codec_none, rv_fmt_none },
};
-void decode_xtheadba(rv_decode *dec, rv_isa isa)
+const rv_opcode_data *decode_xtheadba(rv_decode *dec, rv_isa isa)
{
rv_inst inst = dec->inst;
rv_opcode op = rv_op_illegal;
@@ -272,11 +272,10 @@ void decode_xtheadba(rv_decode *dec, rv_isa isa)
break;
}
- dec->opcode_data = xthead_opcode_data;
- dec->op = op;
+ return op == rv_op_illegal ? NULL : &xthead_opcode_data[op];
}
-void decode_xtheadbb(rv_decode *dec, rv_isa isa)
+const rv_opcode_data *decode_xtheadbb(rv_decode *dec, rv_isa isa)
{
rv_inst inst = dec->inst;
rv_opcode op = rv_op_illegal;
@@ -331,11 +330,10 @@ void decode_xtheadbb(rv_decode *dec, rv_isa isa)
break;
}
- dec->opcode_data = xthead_opcode_data;
- dec->op = op;
+ return op == rv_op_illegal ? NULL : &xthead_opcode_data[op];
}
-void decode_xtheadbs(rv_decode *dec, rv_isa isa)
+const rv_opcode_data *decode_xtheadbs(rv_decode *dec, rv_isa isa)
{
rv_inst inst = dec->inst;
rv_opcode op = rv_op_illegal;
@@ -358,11 +356,10 @@ void decode_xtheadbs(rv_decode *dec, rv_isa isa)
break;
}
- dec->opcode_data = xthead_opcode_data;
- dec->op = op;
+ return op == rv_op_illegal ? NULL : &xthead_opcode_data[op];
}
-void decode_xtheadcmo(rv_decode *dec, rv_isa isa)
+const rv_opcode_data *decode_xtheadcmo(rv_decode *dec, rv_isa isa)
{
rv_inst inst = dec->inst;
rv_opcode op = rv_op_illegal;
@@ -437,11 +434,10 @@ void decode_xtheadcmo(rv_decode *dec, rv_isa isa)
break;
}
- dec->opcode_data = xthead_opcode_data;
- dec->op = op;
+ return op == rv_op_illegal ? NULL : &xthead_opcode_data[op];
}
-void decode_xtheadcondmov(rv_decode *dec, rv_isa isa)
+const rv_opcode_data *decode_xtheadcondmov(rv_decode *dec, rv_isa isa)
{
rv_inst inst = dec->inst;
rv_opcode op = rv_op_illegal;
@@ -465,11 +461,10 @@ void decode_xtheadcondmov(rv_decode *dec, rv_isa isa)
break;
}
- dec->opcode_data = xthead_opcode_data;
- dec->op = op;
+ return op == rv_op_illegal ? NULL : &xthead_opcode_data[op];
}
-void decode_xtheadfmemidx(rv_decode *dec, rv_isa isa)
+const rv_opcode_data *decode_xtheadfmemidx(rv_decode *dec, rv_isa isa)
{
rv_inst inst = dec->inst;
rv_opcode op = rv_op_illegal;
@@ -503,11 +498,10 @@ void decode_xtheadfmemidx(rv_decode *dec, rv_isa isa)
break;
}
- dec->opcode_data = xthead_opcode_data;
- dec->op = op;
+ return op == rv_op_illegal ? NULL : &xthead_opcode_data[op];
}
-void decode_xtheadfmv(rv_decode *dec, rv_isa isa)
+const rv_opcode_data *decode_xtheadfmv(rv_decode *dec, rv_isa isa)
{
rv_inst inst = dec->inst;
rv_opcode op = rv_op_illegal;
@@ -539,11 +533,10 @@ void decode_xtheadfmv(rv_decode *dec, rv_isa isa)
break;
}
- dec->opcode_data = xthead_opcode_data;
- dec->op = op;
+ return op == rv_op_illegal ? NULL : &xthead_opcode_data[op];
}
-void decode_xtheadmac(rv_decode *dec, rv_isa isa)
+const rv_opcode_data *decode_xtheadmac(rv_decode *dec, rv_isa isa)
{
rv_inst inst = dec->inst;
rv_opcode op = rv_op_illegal;
@@ -571,11 +564,10 @@ void decode_xtheadmac(rv_decode *dec, rv_isa isa)
break;
}
- dec->opcode_data = xthead_opcode_data;
- dec->op = op;
+ return op == rv_op_illegal ? NULL : &xthead_opcode_data[op];
}
-void decode_xtheadmemidx(rv_decode *dec, rv_isa isa)
+const rv_opcode_data *decode_xtheadmemidx(rv_decode *dec, rv_isa isa)
{
rv_inst inst = dec->inst;
rv_opcode op = rv_op_illegal;
@@ -646,11 +638,10 @@ void decode_xtheadmemidx(rv_decode *dec, rv_isa isa)
break;
}
- dec->opcode_data = xthead_opcode_data;
- dec->op = op;
+ return op == rv_op_illegal ? NULL : &xthead_opcode_data[op];
}
-void decode_xtheadmempair(rv_decode *dec, rv_isa isa)
+const rv_opcode_data *decode_xtheadmempair(rv_decode *dec, rv_isa isa)
{
rv_inst inst = dec->inst;
rv_opcode op = rv_op_illegal;
@@ -681,11 +672,10 @@ void decode_xtheadmempair(rv_decode *dec, rv_isa isa)
break;
}
- dec->opcode_data = xthead_opcode_data;
- dec->op = op;
+ return op == rv_op_illegal ? NULL : &xthead_opcode_data[op];
}
-void decode_xtheadsync(rv_decode *dec, rv_isa isa)
+const rv_opcode_data *decode_xtheadsync(rv_decode *dec, rv_isa isa)
{
rv_inst inst = dec->inst;
rv_opcode op = rv_op_illegal;
@@ -716,6 +706,5 @@ void decode_xtheadsync(rv_decode *dec, rv_isa isa)
break;
}
- dec->opcode_data = xthead_opcode_data;
- dec->op = op;
+ return op == rv_op_illegal ? NULL : &xthead_opcode_data[op];
}
diff --git a/disas/riscv-xventana.c b/disas/riscv-xventana.c
index 4fb9a29d0b..a4e59312d0 100644
--- a/disas/riscv-xventana.c
+++ b/disas/riscv-xventana.c
@@ -20,7 +20,7 @@ static const rv_opcode_data ventana_opcode_data[] = {
{ "vt.maskcn", rv_codec_r, rv_fmt_rd_rs1_rs2 },
};
-void decode_xventanacondops(rv_decode *dec, rv_isa isa)
+const rv_opcode_data *decode_xventanacondops(rv_decode *dec, rv_isa isa)
{
rv_inst inst = dec->inst;
rv_opcode op = rv_op_illegal;
@@ -38,6 +38,5 @@ void decode_xventanacondops(rv_decode *dec, rv_isa isa)
break;
}
- dec->opcode_data = ventana_opcode_data;
- dec->op = op;
+ return op == rv_op_illegal ? NULL : &ventana_opcode_data[op];
}
diff --git a/disas/riscv.c b/disas/riscv.c
index 171c60238f..c4b8ee7d07 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -2846,7 +2846,7 @@ static const char *csr_name(int csrno)
/* decode opcode */
-static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
+static const rv_opcode_data *decode_inst_opcode(rv_decode *dec, rv_isa isa)
{
rv_inst inst = dec->inst;
rv_opcode op = rv_op_illegal;
@@ -4541,8 +4541,7 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
break;
}
- dec->opcode_data = rvi_opcode_data;
- dec->op = op;
+ return op == rv_op_illegal ? NULL : &rvi_opcode_data[op];
}
/* decode operands */
@@ -5291,14 +5290,12 @@ static GString *disasm_inst(rv_isa isa, uint64_t pc, rv_inst inst,
.inst = inst,
.cfg = cfg,
};
- const rv_opcode_data *op;
+ const rv_opcode_data *op = decode_inst_opcode(&dec, isa);
- decode_inst_opcode(&dec, isa);
-
- if (dec.op == rv_op_illegal && cfg) {
+ if (!op && cfg) {
static const struct {
bool (*guard_func)(const RISCVCPUConfig *);
- void (*decode_func)(rv_decode *, rv_isa);
+ const rv_opcode_data *(*decode_func)(rv_decode *, rv_isa);
} decoders[] = {
{ has_xtheadba_p, decode_xtheadba },
{ has_xtheadbb_p, decode_xtheadbb },
@@ -5317,19 +5314,17 @@ static GString *disasm_inst(rv_isa isa, uint64_t pc, rv_inst inst,
for (size_t i = 0; i < ARRAY_SIZE(decoders); i++) {
if (decoders[i].guard_func(cfg)) {
- decoders[i].decode_func(&dec, isa);
- if (dec.op != rv_op_illegal) {
+ op = decoders[i].decode_func(&dec, isa);
+ if (op) {
break;
}
}
}
}
-
- if (dec.op == rv_op_illegal) {
- dec.opcode_data = rvi_opcode_data;
+ if (!op) {
+ op = &rvi_opcode_data[rv_op_illegal];
}
- op = &dec.opcode_data[dec.op];
decode_inst_operands(&dec, isa, op);
op = decode_inst_lift_pseudo(&dec, op);
return format_inst(24, &dec, op);
--
2.43.0
^ permalink raw reply related [flat|nested] 119+ messages in thread
* [PATCH 41/56] disas/riscv: Reject all of OP-32 and OP-IMM-32 for RV32
2026-08-09 22:34 [RFC PATCH 00/56] disas/riscv: Reorganize the disassembler Richard Henderson
` (39 preceding siblings ...)
2026-08-09 22:35 ` [PATCH 40/56] disas/riscv: Return rv_opcode_data pointer from decoders Richard Henderson
@ 2026-08-09 22:35 ` Richard Henderson
2026-08-12 12:49 ` Alistair
2026-08-09 22:35 ` [PATCH 42/56] disas/riscv: Fix rv32 encoding of zext.h Richard Henderson
` (14 subsequent siblings)
55 siblings, 1 reply; 119+ messages in thread
From: Richard Henderson @ 2026-08-09 22:35 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-riscv
These entire base opcodes are RV64. Reject them all at once
rather than one at a time.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
disas/riscv.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/disas/riscv.c b/disas/riscv.c
index c4b8ee7d07..f51d45674e 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -3311,6 +3311,10 @@ static const rv_opcode_data *decode_inst_opcode(rv_decode *dec, rv_isa isa)
}
break;
case 6:
+ /* OP-IMM-32 */
+ if (isa == rv32) {
+ break;
+ }
switch ((inst >> 12) & 0b111) {
case 0: op = rv_op_addiw; break;
case 1:
@@ -3557,6 +3561,10 @@ static const rv_opcode_data *decode_inst_opcode(rv_decode *dec, rv_isa isa)
break;
case 13: op = rv_op_lui; break;
case 14:
+ /* OP-32 */
+ if (isa == rv32) {
+ break;
+ }
switch (((inst >> 22) & 0b1111111000) |
((inst >> 12) & 0b0000000111)) {
case 0: op = rv_op_addw; break;
--
2.43.0
^ permalink raw reply related [flat|nested] 119+ messages in thread
* [PATCH 42/56] disas/riscv: Fix rv32 encoding of zext.h
2026-08-09 22:34 [RFC PATCH 00/56] disas/riscv: Reorganize the disassembler Richard Henderson
` (40 preceding siblings ...)
2026-08-09 22:35 ` [PATCH 41/56] disas/riscv: Reject all of OP-32 and OP-IMM-32 for RV32 Richard Henderson
@ 2026-08-09 22:35 ` Richard Henderson
2026-08-12 12:49 ` Alistair
2026-08-09 22:35 ` [PATCH 43/56] disas/riscv: Fix isa decoding of rev8 Richard Henderson
` (13 subsequent siblings)
55 siblings, 1 reply; 119+ messages in thread
From: Richard Henderson @ 2026-08-09 22:35 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-riscv, qemu-stable
For rv64, pack with rs2 = 0 does not encode zext.h.
Cc: qemu-stable@nongnu.org
Fixes: 02c1b569a15 ("disas/riscv: Add Zb[abcs] instructions")
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
disas/riscv.c | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/disas/riscv.c b/disas/riscv.c
index f51d45674e..9442a6c115 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -3506,9 +3506,10 @@ static const rv_opcode_data *decode_inst_opcode(rv_decode *dec, rv_isa isa)
case 14: op = rv_op_rem; break;
case 15: op = rv_op_remu; break;
case 36:
- switch ((inst >> 20) & 0b11111) {
- case 0: op = rv_op_zext_h; break;
- default: op = rv_op_pack; break;
+ if (isa == rv32 && !((inst >> 20) & 0b11111)) {
+ op = rv_op_zext_h;
+ } else {
+ op = rv_op_pack;
}
break;
case 39: op = rv_op_packh; break;
--
2.43.0
^ permalink raw reply related [flat|nested] 119+ messages in thread
* [PATCH 43/56] disas/riscv: Fix isa decoding of rev8
2026-08-09 22:34 [RFC PATCH 00/56] disas/riscv: Reorganize the disassembler Richard Henderson
` (41 preceding siblings ...)
2026-08-09 22:35 ` [PATCH 42/56] disas/riscv: Fix rv32 encoding of zext.h Richard Henderson
@ 2026-08-09 22:35 ` Richard Henderson
2026-08-12 12:50 ` Alistair
2026-08-09 22:35 ` [PATCH 44/56] disas/riscv: Fix typo in th.lbib format Richard Henderson
` (12 subsequent siblings)
55 siblings, 1 reply; 119+ messages in thread
From: Richard Henderson @ 2026-08-09 22:35 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-riscv, qemu-stable
The encoding of rev8 is different for rv32 and rv64.
Cc: qemu-stable@nongnu.org
Fixes: 02c1b569a15 ("disas/riscv: Add Zb[abcs] instructions")
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
disas/riscv.c | 12 ++++++++++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/disas/riscv.c b/disas/riscv.c
index 9442a6c115..4141741d79 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -3292,8 +3292,16 @@ static const rv_opcode_data *decode_inst_opcode(rv_decode *dec, rv_isa isa)
case 0b01100: op = rv_op_rori; break;
case 0b01101:
switch ((inst >> 20) & 0b1111111) {
- case 0b0011000: op = rv_op_rev8; break;
- case 0b0111000: op = rv_op_rev8; break;
+ case 0b0011000:
+ if (isa == rv32) {
+ op = rv_op_rev8;
+ }
+ break;
+ case 0b0111000:
+ if (isa == rv64) {
+ op = rv_op_rev8;
+ }
+ break;
case 0b0000111: op = rv_op_brev8; break;
}
break;
--
2.43.0
^ permalink raw reply related [flat|nested] 119+ messages in thread
* [PATCH 44/56] disas/riscv: Fix typo in th.lbib format
2026-08-09 22:34 [RFC PATCH 00/56] disas/riscv: Reorganize the disassembler Richard Henderson
` (42 preceding siblings ...)
2026-08-09 22:35 ` [PATCH 43/56] disas/riscv: Fix isa decoding of rev8 Richard Henderson
@ 2026-08-09 22:35 ` Richard Henderson
2026-08-12 12:50 ` Alistair
2026-08-09 22:35 ` [PATCH 45/56] disas/riscv: Split ventana_opcode_data Richard Henderson
` (11 subsequent siblings)
55 siblings, 1 reply; 119+ messages in thread
From: Richard Henderson @ 2026-08-09 22:35 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-riscv, qemu-stable
th.lbib should format the same as th.lbia, and the other
increment insns, with the address register in parenthesis.
Cc: qemu-stable@nongnu.org
Fixes: 318df7238b9 ("disas/riscv: Add support for XThead* instructions")
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
disas/riscv-xthead.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/disas/riscv-xthead.c b/disas/riscv-xthead.c
index 428a6380e9..fbc96631fd 100644
--- a/disas/riscv-xthead.c
+++ b/disas/riscv-xthead.c
@@ -189,7 +189,7 @@ static const rv_opcode_data xthead_opcode_data[] = {
{ "th.mulsh", rv_codec_r, rv_fmt_rd_rs1_rs2 },
/* XTheadMemIdx */
{ "th.lbia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr },
- { "th.lbib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml },
+ { "th.lbib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr },
{ "th.lbuia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr },
{ "th.lbuib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr },
{ "th.lhia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr },
--
2.43.0
^ permalink raw reply related [flat|nested] 119+ messages in thread
* [PATCH 45/56] disas/riscv: Split ventana_opcode_data
2026-08-09 22:34 [RFC PATCH 00/56] disas/riscv: Reorganize the disassembler Richard Henderson
` (43 preceding siblings ...)
2026-08-09 22:35 ` [PATCH 44/56] disas/riscv: Fix typo in th.lbib format Richard Henderson
@ 2026-08-09 22:35 ` Richard Henderson
2026-08-12 12:51 ` Alistair
2026-08-09 22:35 ` [PATCH 46/56] disas/riscv: Split xlrbr_opcode_data Richard Henderson
` (10 subsequent siblings)
55 siblings, 1 reply; 119+ messages in thread
From: Richard Henderson @ 2026-08-09 22:35 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-riscv
Move the table to riscv-xventana-op.c.inc and massage
the lines into OP() form. Drop vt.illegal as unused.
Return pointers to objects directly.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
disas/riscv-xventana.c | 21 ++++++---------------
disas/riscv-xventana-op.c.inc | 2 ++
2 files changed, 8 insertions(+), 15 deletions(-)
create mode 100644 disas/riscv-xventana-op.c.inc
diff --git a/disas/riscv-xventana.c b/disas/riscv-xventana.c
index a4e59312d0..5d2e07865f 100644
--- a/disas/riscv-xventana.c
+++ b/disas/riscv-xventana.c
@@ -8,35 +8,26 @@
#include "disas/riscv.h"
#include "disas/riscv-xventana.h"
-typedef enum {
- /* 0 is reserved for rv_op_illegal. */
- ventana_op_vt_maskc = 1,
- ventana_op_vt_maskcn = 2,
-} rv_ventana_op;
-
-static const rv_opcode_data ventana_opcode_data[] = {
- { "vt.illegal", rv_codec_illegal, rv_fmt_none },
- { "vt.maskc", rv_codec_r, rv_fmt_rd_rs1_rs2 },
- { "vt.maskcn", rv_codec_r, rv_fmt_rd_rs1_rs2 },
-};
+#define OP(N, ...) static const rv_opcode_data op_##N = { __VA_ARGS__ };
+#include "riscv-xventana-op.c.inc"
+#undef OP
const rv_opcode_data *decode_xventanacondops(rv_decode *dec, rv_isa isa)
{
rv_inst inst = dec->inst;
- rv_opcode op = rv_op_illegal;
switch (((inst >> 0) & 0b11)) {
case 3:
switch (((inst >> 2) & 0b11111)) {
case 30:
switch (((inst >> 22) & 0b1111111000) | ((inst >> 12) & 0b0000000111)) {
- case 6: op = ventana_op_vt_maskc; break;
- case 7: op = ventana_op_vt_maskcn; break;
+ case 6: return &op_vt_maskc;
+ case 7: return &op_vt_maskcn;
}
break;
}
break;
}
- return op == rv_op_illegal ? NULL : &ventana_opcode_data[op];
+ return NULL;
}
diff --git a/disas/riscv-xventana-op.c.inc b/disas/riscv-xventana-op.c.inc
new file mode 100644
index 0000000000..0fe4666aee
--- /dev/null
+++ b/disas/riscv-xventana-op.c.inc
@@ -0,0 +1,2 @@
+OP(vt_maskc, "vt.maskc", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(vt_maskcn, "vt.maskcn", rv_codec_r, rv_fmt_rd_rs1_rs2)
--
2.43.0
^ permalink raw reply related [flat|nested] 119+ messages in thread
* [PATCH 46/56] disas/riscv: Split xlrbr_opcode_data
2026-08-09 22:34 [RFC PATCH 00/56] disas/riscv: Reorganize the disassembler Richard Henderson
` (44 preceding siblings ...)
2026-08-09 22:35 ` [PATCH 45/56] disas/riscv: Split ventana_opcode_data Richard Henderson
@ 2026-08-09 22:35 ` Richard Henderson
2026-08-12 12:52 ` Alistair
2026-08-09 22:35 ` [PATCH 47/56] disas/riscv: Split xthead_opcode_data Richard Henderson
` (9 subsequent siblings)
55 siblings, 1 reply; 119+ messages in thread
From: Richard Henderson @ 2026-08-09 22:35 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-riscv
Move the table to riscv-xlrbr-op.c.inc and massage
the lines into OP() form. Drop illegal as unused.
Return pointers to objects directly.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
disas/riscv-xlrbr.c | 54 +++++++++-----------------------------
disas/riscv-xlrbr-op.c.inc | 8 ++++++
2 files changed, 20 insertions(+), 42 deletions(-)
create mode 100644 disas/riscv-xlrbr-op.c.inc
diff --git a/disas/riscv-xlrbr.c b/disas/riscv-xlrbr.c
index b12916c9da..b4229e5c83 100644
--- a/disas/riscv-xlrbr.c
+++ b/disas/riscv-xlrbr.c
@@ -8,38 +8,16 @@
*/
#include "qemu/osdep.h"
-
#include "disas/riscv.h"
#include "disas/riscv-xlrbr.h"
-typedef enum {
- /* 0 is reserved for rv_op_illegal. */
- rv_op_crc32_b = 1,
- rv_op_crc32_h = 2,
- rv_op_crc32_w = 3,
- rv_op_crc32_d = 4,
- rv_op_crc32c_b = 5,
- rv_op_crc32c_h = 6,
- rv_op_crc32c_w = 7,
- rv_op_crc32c_d = 8,
-} rv_xlrbr_op;
-
-static const rv_opcode_data xlrbr_opcode_data[] = {
- { "illegal", rv_codec_illegal, rv_fmt_none },
- { "crc32.b", rv_codec_r, rv_fmt_rd_rs1 },
- { "crc32.h", rv_codec_r, rv_fmt_rd_rs1 },
- { "crc32.w", rv_codec_r, rv_fmt_rd_rs1 },
- { "crc32.d", rv_codec_r, rv_fmt_rd_rs1 },
- { "crc32c.b", rv_codec_r, rv_fmt_rd_rs1 },
- { "crc32c.h", rv_codec_r, rv_fmt_rd_rs1 },
- { "crc32c.w", rv_codec_r, rv_fmt_rd_rs1 },
- { "crc32c.d", rv_codec_r, rv_fmt_rd_rs1 },
-};
+#define OP(N, ...) static const rv_opcode_data op_##N = { __VA_ARGS__ };
+#include "riscv-xlrbr-op.c.inc"
+#undef OP
const rv_opcode_data *decode_xlrbr(rv_decode *dec, rv_isa isa)
{
rv_inst inst = dec->inst;
- rv_opcode op = rv_op_illegal;
switch ((inst >> 0) & 0b1111111) {
case 0b0010011:
@@ -47,34 +25,26 @@ const rv_opcode_data *decode_xlrbr(rv_decode *dec, rv_isa isa)
case 0b001:
switch ((inst >> 20 & 0b111111111111)) {
case 0b011000010000:
- op = rv_op_crc32_b;
- break;
+ return &op_crc32_b;
case 0b011000010001:
- op = rv_op_crc32_h;
- break;
+ return &op_crc32_h;
case 0b011000010010:
- op = rv_op_crc32_w;
- break;
+ return &op_crc32_w;
case 0b011000010011:
- op = rv_op_crc32_d;
- break;
+ return &op_crc32_d;
case 0b011000011000:
- op = rv_op_crc32c_b;
- break;
+ return &op_crc32c_b;
case 0b011000011001:
- op = rv_op_crc32c_h;
- break;
+ return &op_crc32c_h;
case 0b011000011010:
- op = rv_op_crc32c_w;
- break;
+ return &op_crc32c_w;
case 0b011000011011:
- op = rv_op_crc32c_d;
- break;
+ return &op_crc32c_d;
}
break;
}
break;
}
- return op == rv_op_illegal ? NULL : &xlrbr_opcode_data[op];
+ return NULL;
}
diff --git a/disas/riscv-xlrbr-op.c.inc b/disas/riscv-xlrbr-op.c.inc
new file mode 100644
index 0000000000..57add37c24
--- /dev/null
+++ b/disas/riscv-xlrbr-op.c.inc
@@ -0,0 +1,8 @@
+OP(crc32_b, "crc32.b", rv_codec_r, rv_fmt_rd_rs1)
+OP(crc32_h, "crc32.h", rv_codec_r, rv_fmt_rd_rs1)
+OP(crc32_w, "crc32.w", rv_codec_r, rv_fmt_rd_rs1)
+OP(crc32_d, "crc32.d", rv_codec_r, rv_fmt_rd_rs1)
+OP(crc32c_b, "crc32c.b", rv_codec_r, rv_fmt_rd_rs1)
+OP(crc32c_h, "crc32c.h", rv_codec_r, rv_fmt_rd_rs1)
+OP(crc32c_w, "crc32c.w", rv_codec_r, rv_fmt_rd_rs1)
+OP(crc32c_d, "crc32c.d", rv_codec_r, rv_fmt_rd_rs1)
--
2.43.0
^ permalink raw reply related [flat|nested] 119+ messages in thread
* [PATCH 47/56] disas/riscv: Split xthead_opcode_data
2026-08-09 22:34 [RFC PATCH 00/56] disas/riscv: Reorganize the disassembler Richard Henderson
` (45 preceding siblings ...)
2026-08-09 22:35 ` [PATCH 46/56] disas/riscv: Split xlrbr_opcode_data Richard Henderson
@ 2026-08-09 22:35 ` Richard Henderson
2026-08-12 12:53 ` Alistair
2026-08-09 22:35 ` [PATCH 48/56] disas/riscv: Move rv_op_illegal to riscv.c Richard Henderson
` (8 subsequent siblings)
55 siblings, 1 reply; 119+ messages in thread
From: Richard Henderson @ 2026-08-09 22:35 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-riscv
Move the table to riscv-xthead-op.c.inc and massage
the lines into OP() form. Drop th.illegal as unused.
Return pointers to objects directly.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
disas/riscv-xthead.c | 481 +++++++++---------------------------
disas/riscv-xthead-op.c.inc | 125 ++++++++++
2 files changed, 243 insertions(+), 363 deletions(-)
create mode 100644 disas/riscv-xthead-op.c.inc
diff --git a/disas/riscv-xthead.c b/disas/riscv-xthead.c
index fbc96631fd..387c22c869 100644
--- a/disas/riscv-xthead.c
+++ b/disas/riscv-xthead.c
@@ -8,248 +8,13 @@
#include "disas/riscv.h"
#include "disas/riscv-xthead.h"
-typedef enum {
- /* 0 is reserved for rv_op_illegal. */
- /* XTheadBa */
- rv_op_th_addsl = 1,
- /* XTheadBb */
- rv_op_th_srri,
- rv_op_th_srriw,
- rv_op_th_ext,
- rv_op_th_extu,
- rv_op_th_ff0,
- rv_op_th_ff1,
- rv_op_th_rev,
- rv_op_th_revw,
- rv_op_th_tstnbz,
- /* XTheadBs */
- rv_op_th_tst,
- /* XTheadCmo */
- rv_op_th_dcache_call,
- rv_op_th_dcache_ciall,
- rv_op_th_dcache_iall,
- rv_op_th_dcache_cpa,
- rv_op_th_dcache_cipa,
- rv_op_th_dcache_ipa,
- rv_op_th_dcache_cva,
- rv_op_th_dcache_civa,
- rv_op_th_dcache_iva,
- rv_op_th_dcache_csw,
- rv_op_th_dcache_cisw,
- rv_op_th_dcache_isw,
- rv_op_th_dcache_cpal1,
- rv_op_th_dcache_cval1,
- rv_op_th_icache_iall,
- rv_op_th_icache_ialls,
- rv_op_th_icache_ipa,
- rv_op_th_icache_iva,
- rv_op_th_l2cache_call,
- rv_op_th_l2cache_ciall,
- rv_op_th_l2cache_iall,
- /* XTheadCondMov */
- rv_op_th_mveqz,
- rv_op_th_mvnez,
- /* XTheadFMemIdx */
- rv_op_th_flrd,
- rv_op_th_flrw,
- rv_op_th_flurd,
- rv_op_th_flurw,
- rv_op_th_fsrd,
- rv_op_th_fsrw,
- rv_op_th_fsurd,
- rv_op_th_fsurw,
- /* XTheadFmv */
- rv_op_th_fmv_hw_x,
- rv_op_th_fmv_x_hw,
- /* XTheadMac */
- rv_op_th_mula,
- rv_op_th_mulah,
- rv_op_th_mulaw,
- rv_op_th_muls,
- rv_op_th_mulsw,
- rv_op_th_mulsh,
- /* XTheadMemIdx */
- rv_op_th_lbia,
- rv_op_th_lbib,
- rv_op_th_lbuia,
- rv_op_th_lbuib,
- rv_op_th_lhia,
- rv_op_th_lhib,
- rv_op_th_lhuia,
- rv_op_th_lhuib,
- rv_op_th_lwia,
- rv_op_th_lwib,
- rv_op_th_lwuia,
- rv_op_th_lwuib,
- rv_op_th_ldia,
- rv_op_th_ldib,
- rv_op_th_sbia,
- rv_op_th_sbib,
- rv_op_th_shia,
- rv_op_th_shib,
- rv_op_th_swia,
- rv_op_th_swib,
- rv_op_th_sdia,
- rv_op_th_sdib,
- rv_op_th_lrb,
- rv_op_th_lrbu,
- rv_op_th_lrh,
- rv_op_th_lrhu,
- rv_op_th_lrw,
- rv_op_th_lrwu,
- rv_op_th_lrd,
- rv_op_th_srb,
- rv_op_th_srh,
- rv_op_th_srw,
- rv_op_th_srd,
- rv_op_th_lurb,
- rv_op_th_lurbu,
- rv_op_th_lurh,
- rv_op_th_lurhu,
- rv_op_th_lurw,
- rv_op_th_lurwu,
- rv_op_th_lurd,
- rv_op_th_surb,
- rv_op_th_surh,
- rv_op_th_surw,
- rv_op_th_surd,
- /* XTheadMemPair */
- rv_op_th_ldd,
- rv_op_th_lwd,
- rv_op_th_lwud,
- rv_op_th_sdd,
- rv_op_th_swd,
- /* XTheadSync */
- rv_op_th_sfence_vmas,
- rv_op_th_sync,
- rv_op_th_sync_i,
- rv_op_th_sync_is,
- rv_op_th_sync_s,
-} rv_xthead_op;
-
-static const rv_opcode_data xthead_opcode_data[] = {
- { "th.illegal", rv_codec_illegal, rv_fmt_none },
- /* XTheadBa */
- { "th.addsl", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm },
- /* XTheadBb */
- { "th.srri", rv_codec_r2_imm6, rv_fmt_rd_rs1_imm },
- { "th.srriw", rv_codec_r2_imm5, rv_fmt_rd_rs1_imm },
- { "th.ext", rv_codec_r2_immhl, rv_fmt_rd_rs1_immh_imml },
- { "th.extu", rv_codec_r2_immhl, rv_fmt_rd_rs1_immh_imml },
- { "th.ff0", rv_codec_r2, rv_fmt_rd_rs1 },
- { "th.ff1", rv_codec_r2, rv_fmt_rd_rs1 },
- { "th.rev", rv_codec_r2, rv_fmt_rd_rs1 },
- { "th.revw", rv_codec_r2, rv_fmt_rd_rs1 },
- { "th.tstnbz", rv_codec_r2, rv_fmt_rd_rs1 },
- /* XTheadBs */
- { "th.tst", rv_codec_r2_imm6, rv_fmt_rd_rs1_imm },
- /* XTheadCmo */
- { "th.dcache.call", rv_codec_none, rv_fmt_none },
- { "th.dcache.ciall", rv_codec_none, rv_fmt_none },
- { "th.dcache.iall", rv_codec_none, rv_fmt_none },
- { "th.dcache.cpa", rv_codec_r, rv_fmt_rs1 },
- { "th.dcache.cipa", rv_codec_r, rv_fmt_rs1 },
- { "th.dcache.ipa", rv_codec_r, rv_fmt_rs1 },
- { "th.dcache.cva", rv_codec_r, rv_fmt_rs1 },
- { "th.dcache.civa", rv_codec_r, rv_fmt_rs1 },
- { "th.dcache.iva", rv_codec_r, rv_fmt_rs1 },
- { "th.dcache.csw", rv_codec_r, rv_fmt_rs1 },
- { "th.dcache.cisw", rv_codec_r, rv_fmt_rs1 },
- { "th.dcache.isw", rv_codec_r, rv_fmt_rs1 },
- { "th.dcache.cpal1", rv_codec_r, rv_fmt_rs1 },
- { "th.dcache.cval1", rv_codec_r, rv_fmt_rs1 },
- { "th.icache.iall", rv_codec_none, rv_fmt_none },
- { "th.icache.ialls", rv_codec_none, rv_fmt_none },
- { "th.icache.ipa", rv_codec_r, rv_fmt_rs1 },
- { "th.icache.iva", rv_codec_r, rv_fmt_rs1 },
- { "th.l2cache.call", rv_codec_none, rv_fmt_none },
- { "th.l2cache.ciall", rv_codec_none, rv_fmt_none },
- { "th.l2cache.iall", rv_codec_none, rv_fmt_none },
- /* XTheadCondMov */
- { "th.mveqz", rv_codec_r, rv_fmt_rd_rs1_rs2 },
- { "th.mvnez", rv_codec_r, rv_fmt_rd_rs1_rs2 },
- /* XTheadFMemIdx */
- { "th.flrd", rv_codec_r_imm2, rv_fmt_frd_rs1_rs2_imm },
- { "th.flrw", rv_codec_r_imm2, rv_fmt_frd_rs1_rs2_imm },
- { "th.flurd", rv_codec_r_imm2, rv_fmt_frd_rs1_rs2_imm },
- { "th.flurw", rv_codec_r_imm2, rv_fmt_frd_rs1_rs2_imm },
- { "th.fsrd", rv_codec_r_imm2, rv_fmt_frd_rs1_rs2_imm },
- { "th.fsrw", rv_codec_r_imm2, rv_fmt_frd_rs1_rs2_imm },
- { "th.fsurd", rv_codec_r_imm2, rv_fmt_frd_rs1_rs2_imm },
- { "th.fsurw", rv_codec_r_imm2, rv_fmt_frd_rs1_rs2_imm },
- /* XTheadFmv */
- { "th.fmv.hw.x", rv_codec_r, rv_fmt_rd_frs1 },
- { "th.fmv.x.hw", rv_codec_r, rv_fmt_rd_frs1 },
- /* XTheadMac */
- { "th.mula", rv_codec_r, rv_fmt_rd_rs1_rs2 },
- { "th.mulaw", rv_codec_r, rv_fmt_rd_rs1_rs2 },
- { "th.mulah", rv_codec_r, rv_fmt_rd_rs1_rs2 },
- { "th.muls", rv_codec_r, rv_fmt_rd_rs1_rs2 },
- { "th.mulsw", rv_codec_r, rv_fmt_rd_rs1_rs2 },
- { "th.mulsh", rv_codec_r, rv_fmt_rd_rs1_rs2 },
- /* XTheadMemIdx */
- { "th.lbia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr },
- { "th.lbib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr },
- { "th.lbuia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr },
- { "th.lbuib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr },
- { "th.lhia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr },
- { "th.lhib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr },
- { "th.lhuia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr },
- { "th.lhuib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr },
- { "th.lwia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr },
- { "th.lwib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr },
- { "th.lwuia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr },
- { "th.lwuib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr },
- { "th.ldia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr },
- { "th.ldib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr },
- { "th.sbia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr },
- { "th.sbib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr },
- { "th.shia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr },
- { "th.shib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr },
- { "th.swia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr },
- { "th.swib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr },
- { "th.sdia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr },
- { "th.sdib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr },
- { "th.lrb", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm },
- { "th.lrbu", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm },
- { "th.lrh", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm },
- { "th.lrhu", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm },
- { "th.lrw", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm },
- { "th.lrwu", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm },
- { "th.lrd", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm },
- { "th.srb", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm },
- { "th.srh", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm },
- { "th.srw", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm },
- { "th.srd", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm },
- { "th.lurb", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm },
- { "th.lurbu", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm },
- { "th.lurh", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm },
- { "th.lurhu", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm },
- { "th.lurw", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm },
- { "th.lurwu", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm },
- { "th.lurd", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm },
- { "th.surb", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm },
- { "th.surh", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm },
- { "th.surw", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm },
- { "th.surd", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm },
- /* XTheadMemPair */
- { "th.ldd", rv_codec_r_imm2, rv_fmt_rd2_imm },
- { "th.lwd", rv_codec_r_imm2, rv_fmt_rd2_imm },
- { "th.lwud", rv_codec_r_imm2, rv_fmt_rd2_imm },
- { "th.sdd", rv_codec_r_imm2, rv_fmt_rd2_imm },
- { "th.swd", rv_codec_r_imm2, rv_fmt_rd2_imm },
- /* XTheadSync */
- { "th.sfence.vmas", rv_codec_r, rv_fmt_rs1_rs2 },
- { "th.sync", rv_codec_none, rv_fmt_none },
- { "th.sync.i", rv_codec_none, rv_fmt_none },
- { "th.sync.is", rv_codec_none, rv_fmt_none },
- { "th.sync.s", rv_codec_none, rv_fmt_none },
-};
+#define OP(N, ...) static const rv_opcode_data op_##N = { __VA_ARGS__ };
+#include "riscv-xthead-op.c.inc"
+#undef OP
const rv_opcode_data *decode_xtheadba(rv_decode *dec, rv_isa isa)
{
rv_inst inst = dec->inst;
- rv_opcode op = rv_op_illegal;
switch (((inst >> 0) & 0b11)) {
case 3:
@@ -262,7 +27,7 @@ const rv_opcode_data *decode_xtheadba(rv_decode *dec, rv_isa isa)
case 0b0000000:
case 0b0000001:
case 0b0000010:
- case 0b0000011: op = rv_op_th_addsl; break;
+ case 0b0000011: return &op_th_addsl;
}
break;
}
@@ -272,13 +37,12 @@ const rv_opcode_data *decode_xtheadba(rv_decode *dec, rv_isa isa)
break;
}
- return op == rv_op_illegal ? NULL : &xthead_opcode_data[op];
+ return NULL;
}
const rv_opcode_data *decode_xtheadbb(rv_decode *dec, rv_isa isa)
{
rv_inst inst = dec->inst;
- rv_opcode op = rv_op_illegal;
switch (((inst >> 0) & 0b11)) {
case 3:
@@ -288,41 +52,41 @@ const rv_opcode_data *decode_xtheadbb(rv_decode *dec, rv_isa isa)
switch ((inst >> 12) & 0b111) {
case 1:
switch ((inst >> 25) & 0b1111111) {
- case 0b0001010: op = rv_op_th_srriw; break;
+ case 0b0001010: return &op_th_srriw;
case 0b1000000:
if (((inst >> 20) & 0b11111) == 0) {
- op = rv_op_th_tstnbz;
+ return &op_th_tstnbz;
}
break;
case 0b1000001:
if (((inst >> 20) & 0b11111) == 0) {
- op = rv_op_th_rev;
+ return &op_th_rev;
}
break;
case 0b1000010:
if (((inst >> 20) & 0b11111) == 0) {
- op = rv_op_th_ff0;
+ return &op_th_ff0;
}
break;
case 0b1000011:
if (((inst >> 20) & 0b11111) == 0) {
- op = rv_op_th_ff1;
+ return &op_th_ff1;
}
break;
case 0b1000100:
case 0b1001000:
if (((inst >> 20) & 0b11111) == 0) {
- op = rv_op_th_revw;
+ return &op_th_revw;
}
break;
case 0b0001000:
case 0b0001001:
- op = rv_op_th_srri;
+ return &op_th_srri;
break;
}
break;
- case 2: op = rv_op_th_ext; break;
- case 3: op = rv_op_th_extu; break;
+ case 2: return &op_th_ext;
+ case 3: return &op_th_extu;
}
break;
/* custom-0 */
@@ -330,13 +94,12 @@ const rv_opcode_data *decode_xtheadbb(rv_decode *dec, rv_isa isa)
break;
}
- return op == rv_op_illegal ? NULL : &xthead_opcode_data[op];
+ return NULL;
}
const rv_opcode_data *decode_xtheadbs(rv_decode *dec, rv_isa isa)
{
rv_inst inst = dec->inst;
- rv_opcode op = rv_op_illegal;
switch (((inst >> 0) & 0b11)) {
case 3:
@@ -346,7 +109,7 @@ const rv_opcode_data *decode_xtheadbs(rv_decode *dec, rv_isa isa)
switch ((inst >> 12) & 0b111) {
case 1:
switch ((inst >> 26) & 0b111111) {
- case 0b100010: op = rv_op_th_tst; break;
+ case 0b100010: return &op_th_tst;
}
break;
}
@@ -356,13 +119,12 @@ const rv_opcode_data *decode_xtheadbs(rv_decode *dec, rv_isa isa)
break;
}
- return op == rv_op_illegal ? NULL : &xthead_opcode_data[op];
+ return NULL;
}
const rv_opcode_data *decode_xtheadcmo(rv_decode *dec, rv_isa isa)
{
rv_inst inst = dec->inst;
- rv_opcode op = rv_op_illegal;
switch (((inst >> 0) & 0b11)) {
case 3:
@@ -374,55 +136,55 @@ const rv_opcode_data *decode_xtheadcmo(rv_decode *dec, rv_isa isa)
switch ((inst >> 20 & 0b111111111111)) {
case 0b000000000001:
if (((inst >> 20) & 0b11111) == 0) {
- op = rv_op_th_dcache_call;
+ return &op_th_dcache_call;
}
break;
case 0b000000000011:
if (((inst >> 20) & 0b11111) == 0) {
- op = rv_op_th_dcache_ciall;
+ return &op_th_dcache_ciall;
}
break;
case 0b000000000010:
if (((inst >> 20) & 0b11111) == 0) {
- op = rv_op_th_dcache_iall;
+ return &op_th_dcache_iall;
}
break;
- case 0b000000101001: op = rv_op_th_dcache_cpa; break;
- case 0b000000101011: op = rv_op_th_dcache_cipa; break;
- case 0b000000101010: op = rv_op_th_dcache_ipa; break;
- case 0b000000100101: op = rv_op_th_dcache_cva; break;
- case 0b000000100111: op = rv_op_th_dcache_civa; break;
- case 0b000000100110: op = rv_op_th_dcache_iva; break;
- case 0b000000100001: op = rv_op_th_dcache_csw; break;
- case 0b000000100011: op = rv_op_th_dcache_cisw; break;
- case 0b000000100010: op = rv_op_th_dcache_isw; break;
- case 0b000000101000: op = rv_op_th_dcache_cpal1; break;
- case 0b000000100100: op = rv_op_th_dcache_cval1; break;
+ case 0b000000101001: return &op_th_dcache_cpa;
+ case 0b000000101011: return &op_th_dcache_cipa;
+ case 0b000000101010: return &op_th_dcache_ipa;
+ case 0b000000100101: return &op_th_dcache_cva;
+ case 0b000000100111: return &op_th_dcache_civa;
+ case 0b000000100110: return &op_th_dcache_iva;
+ case 0b000000100001: return &op_th_dcache_csw;
+ case 0b000000100011: return &op_th_dcache_cisw;
+ case 0b000000100010: return &op_th_dcache_isw;
+ case 0b000000101000: return &op_th_dcache_cpal1;
+ case 0b000000100100: return &op_th_dcache_cval1;
case 0b000000010000:
if (((inst >> 20) & 0b11111) == 0) {
- op = rv_op_th_icache_iall;
+ return &op_th_icache_iall;
}
break;
case 0b000000010001:
if (((inst >> 20) & 0b11111) == 0) {
- op = rv_op_th_icache_ialls;
+ return &op_th_icache_ialls;
}
break;
- case 0b000000111000: op = rv_op_th_icache_ipa; break;
- case 0b000000110000: op = rv_op_th_icache_iva; break;
+ case 0b000000111000: return &op_th_icache_ipa;
+ case 0b000000110000: return &op_th_icache_iva;
case 0b000000010101:
if (((inst >> 20) & 0b11111) == 0) {
- op = rv_op_th_l2cache_call;
+ return &op_th_l2cache_call;
}
break;
case 0b000000010111:
if (((inst >> 20) & 0b11111) == 0) {
- op = rv_op_th_l2cache_ciall;
+ return &op_th_l2cache_ciall;
}
break;
case 0b000000010110:
if (((inst >> 20) & 0b11111) == 0) {
- op = rv_op_th_l2cache_iall;
+ return &op_th_l2cache_iall;
}
break;
}
@@ -434,13 +196,12 @@ const rv_opcode_data *decode_xtheadcmo(rv_decode *dec, rv_isa isa)
break;
}
- return op == rv_op_illegal ? NULL : &xthead_opcode_data[op];
+ return NULL;
}
const rv_opcode_data *decode_xtheadcondmov(rv_decode *dec, rv_isa isa)
{
rv_inst inst = dec->inst;
- rv_opcode op = rv_op_illegal;
switch (((inst >> 0) & 0b11)) {
case 3:
@@ -450,8 +211,8 @@ const rv_opcode_data *decode_xtheadcondmov(rv_decode *dec, rv_isa isa)
switch ((inst >> 12) & 0b111) {
case 1:
switch ((inst >> 25) & 0b1111111) {
- case 0b0100000: op = rv_op_th_mveqz; break;
- case 0b0100001: op = rv_op_th_mvnez; break;
+ case 0b0100000: return &op_th_mveqz;
+ case 0b0100001: return &op_th_mvnez;
}
break;
}
@@ -461,13 +222,12 @@ const rv_opcode_data *decode_xtheadcondmov(rv_decode *dec, rv_isa isa)
break;
}
- return op == rv_op_illegal ? NULL : &xthead_opcode_data[op];
+ return NULL;
}
const rv_opcode_data *decode_xtheadfmemidx(rv_decode *dec, rv_isa isa)
{
rv_inst inst = dec->inst;
- rv_opcode op = rv_op_illegal;
switch (((inst >> 0) & 0b11)) {
case 3:
@@ -477,18 +237,18 @@ const rv_opcode_data *decode_xtheadfmemidx(rv_decode *dec, rv_isa isa)
switch ((inst >> 12) & 0b111) {
case 6:
switch ((inst >> 27) & 0b11111) {
- case 8: op = rv_op_th_flrw; break;
- case 10: op = rv_op_th_flurw; break;
- case 12: op = rv_op_th_flrd; break;
- case 14: op = rv_op_th_flurd; break;
+ case 8: return &op_th_flrw;
+ case 10: return &op_th_flurw;
+ case 12: return &op_th_flrd;
+ case 14: return &op_th_flurd;
}
break;
case 7:
switch ((inst >> 27) & 0b11111) {
- case 8: op = rv_op_th_fsrw; break;
- case 10: op = rv_op_th_fsurw; break;
- case 12: op = rv_op_th_fsrd; break;
- case 14: op = rv_op_th_fsurd; break;
+ case 8: return &op_th_fsrw;
+ case 10: return &op_th_fsurw;
+ case 12: return &op_th_fsrd;
+ case 14: return &op_th_fsurd;
}
break;
}
@@ -498,13 +258,12 @@ const rv_opcode_data *decode_xtheadfmemidx(rv_decode *dec, rv_isa isa)
break;
}
- return op == rv_op_illegal ? NULL : &xthead_opcode_data[op];
+ return NULL;
}
const rv_opcode_data *decode_xtheadfmv(rv_decode *dec, rv_isa isa)
{
rv_inst inst = dec->inst;
- rv_opcode op = rv_op_illegal;
switch (((inst >> 0) & 0b11)) {
case 3:
@@ -516,12 +275,12 @@ const rv_opcode_data *decode_xtheadfmv(rv_decode *dec, rv_isa isa)
switch ((inst >> 25) & 0b1111111) {
case 0b1010000:
if (((inst >> 20) & 0b11111) == 0) {
- op = rv_op_th_fmv_hw_x;
+ return &op_th_fmv_hw_x;
}
break;
case 0b1100000:
if (((inst >> 20) & 0b11111) == 0) {
- op = rv_op_th_fmv_x_hw;
+ return &op_th_fmv_x_hw;
}
break;
}
@@ -533,13 +292,12 @@ const rv_opcode_data *decode_xtheadfmv(rv_decode *dec, rv_isa isa)
break;
}
- return op == rv_op_illegal ? NULL : &xthead_opcode_data[op];
+ return NULL;
}
const rv_opcode_data *decode_xtheadmac(rv_decode *dec, rv_isa isa)
{
rv_inst inst = dec->inst;
- rv_opcode op = rv_op_illegal;
switch (((inst >> 0) & 0b11)) {
case 3:
@@ -549,12 +307,12 @@ const rv_opcode_data *decode_xtheadmac(rv_decode *dec, rv_isa isa)
switch ((inst >> 12) & 0b111) {
case 1:
switch ((inst >> 25) & 0b1111111) {
- case 0b0010000: op = rv_op_th_mula; break;
- case 0b0010001: op = rv_op_th_muls; break;
- case 0b0010010: op = rv_op_th_mulaw; break;
- case 0b0010011: op = rv_op_th_mulsw; break;
- case 0b0010100: op = rv_op_th_mulah; break;
- case 0b0010101: op = rv_op_th_mulsh; break;
+ case 0b0010000: return &op_th_mula;
+ case 0b0010001: return &op_th_muls;
+ case 0b0010010: return &op_th_mulaw;
+ case 0b0010011: return &op_th_mulsw;
+ case 0b0010100: return &op_th_mulah;
+ case 0b0010101: return &op_th_mulsh;
}
break;
}
@@ -564,13 +322,12 @@ const rv_opcode_data *decode_xtheadmac(rv_decode *dec, rv_isa isa)
break;
}
- return op == rv_op_illegal ? NULL : &xthead_opcode_data[op];
+ return NULL;
}
const rv_opcode_data *decode_xtheadmemidx(rv_decode *dec, rv_isa isa)
{
rv_inst inst = dec->inst;
- rv_opcode op = rv_op_illegal;
switch (((inst >> 0) & 0b11)) {
case 3:
@@ -580,54 +337,54 @@ const rv_opcode_data *decode_xtheadmemidx(rv_decode *dec, rv_isa isa)
switch ((inst >> 12) & 0b111) {
case 4:
switch ((inst >> 27) & 0b11111) {
- case 0: op = rv_op_th_lrb; break;
- case 1: op = rv_op_th_lbib; break;
- case 2: op = rv_op_th_lurb; break;
- case 3: op = rv_op_th_lbia; break;
- case 4: op = rv_op_th_lrh; break;
- case 5: op = rv_op_th_lhib; break;
- case 6: op = rv_op_th_lurh; break;
- case 7: op = rv_op_th_lhia; break;
- case 8: op = rv_op_th_lrw; break;
- case 9: op = rv_op_th_lwib; break;
- case 10: op = rv_op_th_lurw; break;
- case 11: op = rv_op_th_lwia; break;
- case 12: op = rv_op_th_lrd; break;
- case 13: op = rv_op_th_ldib; break;
- case 14: op = rv_op_th_lurd; break;
- case 15: op = rv_op_th_ldia; break;
- case 16: op = rv_op_th_lrbu; break;
- case 17: op = rv_op_th_lbuib; break;
- case 18: op = rv_op_th_lurbu; break;
- case 19: op = rv_op_th_lbuia; break;
- case 20: op = rv_op_th_lrhu; break;
- case 21: op = rv_op_th_lhuib; break;
- case 22: op = rv_op_th_lurhu; break;
- case 23: op = rv_op_th_lhuia; break;
- case 24: op = rv_op_th_lrwu; break;
- case 25: op = rv_op_th_lwuib; break;
- case 26: op = rv_op_th_lurwu; break;
- case 27: op = rv_op_th_lwuia; break;
+ case 0: return &op_th_lrb;
+ case 1: return &op_th_lbib;
+ case 2: return &op_th_lurb;
+ case 3: return &op_th_lbia;
+ case 4: return &op_th_lrh;
+ case 5: return &op_th_lhib;
+ case 6: return &op_th_lurh;
+ case 7: return &op_th_lhia;
+ case 8: return &op_th_lrw;
+ case 9: return &op_th_lwib;
+ case 10: return &op_th_lurw;
+ case 11: return &op_th_lwia;
+ case 12: return &op_th_lrd;
+ case 13: return &op_th_ldib;
+ case 14: return &op_th_lurd;
+ case 15: return &op_th_ldia;
+ case 16: return &op_th_lrbu;
+ case 17: return &op_th_lbuib;
+ case 18: return &op_th_lurbu;
+ case 19: return &op_th_lbuia;
+ case 20: return &op_th_lrhu;
+ case 21: return &op_th_lhuib;
+ case 22: return &op_th_lurhu;
+ case 23: return &op_th_lhuia;
+ case 24: return &op_th_lrwu;
+ case 25: return &op_th_lwuib;
+ case 26: return &op_th_lurwu;
+ case 27: return &op_th_lwuia;
}
break;
case 5:
switch ((inst >> 27) & 0b11111) {
- case 0: op = rv_op_th_srb; break;
- case 1: op = rv_op_th_sbib; break;
- case 2: op = rv_op_th_surb; break;
- case 3: op = rv_op_th_sbia; break;
- case 4: op = rv_op_th_srh; break;
- case 5: op = rv_op_th_shib; break;
- case 6: op = rv_op_th_surh; break;
- case 7: op = rv_op_th_shia; break;
- case 8: op = rv_op_th_srw; break;
- case 9: op = rv_op_th_swib; break;
- case 10: op = rv_op_th_surw; break;
- case 11: op = rv_op_th_swia; break;
- case 12: op = rv_op_th_srd; break;
- case 13: op = rv_op_th_sdib; break;
- case 14: op = rv_op_th_surd; break;
- case 15: op = rv_op_th_sdia; break;
+ case 0: return &op_th_srb;
+ case 1: return &op_th_sbib;
+ case 2: return &op_th_surb;
+ case 3: return &op_th_sbia;
+ case 4: return &op_th_srh;
+ case 5: return &op_th_shib;
+ case 6: return &op_th_surh;
+ case 7: return &op_th_shia;
+ case 8: return &op_th_srw;
+ case 9: return &op_th_swib;
+ case 10: return &op_th_surw;
+ case 11: return &op_th_swia;
+ case 12: return &op_th_srd;
+ case 13: return &op_th_sdib;
+ case 14: return &op_th_surd;
+ case 15: return &op_th_sdia;
}
break;
break;
@@ -638,13 +395,12 @@ const rv_opcode_data *decode_xtheadmemidx(rv_decode *dec, rv_isa isa)
break;
}
- return op == rv_op_illegal ? NULL : &xthead_opcode_data[op];
+ return NULL;
}
const rv_opcode_data *decode_xtheadmempair(rv_decode *dec, rv_isa isa)
{
rv_inst inst = dec->inst;
- rv_opcode op = rv_op_illegal;
switch (((inst >> 0) & 0b11)) {
case 3:
@@ -654,15 +410,15 @@ const rv_opcode_data *decode_xtheadmempair(rv_decode *dec, rv_isa isa)
switch ((inst >> 12) & 0b111) {
case 4:
switch ((inst >> 27) & 0b11111) {
- case 28: op = rv_op_th_lwd; break;
- case 30: op = rv_op_th_lwud; break;
- case 31: op = rv_op_th_ldd; break;
+ case 28: return &op_th_lwd;
+ case 30: return &op_th_lwud;
+ case 31: return &op_th_ldd;
}
break;
case 5:
switch ((inst >> 27) & 0b11111) {
- case 28: op = rv_op_th_swd; break;
- case 31: op = rv_op_th_sdd; break;
+ case 28: return &op_th_swd;
+ case 31: return &op_th_sdd;
}
break;
}
@@ -672,13 +428,12 @@ const rv_opcode_data *decode_xtheadmempair(rv_decode *dec, rv_isa isa)
break;
}
- return op == rv_op_illegal ? NULL : &xthead_opcode_data[op];
+ return NULL;
}
const rv_opcode_data *decode_xtheadsync(rv_decode *dec, rv_isa isa)
{
rv_inst inst = dec->inst;
- rv_opcode op = rv_op_illegal;
switch (((inst >> 0) & 0b11)) {
case 3:
@@ -688,13 +443,13 @@ const rv_opcode_data *decode_xtheadsync(rv_decode *dec, rv_isa isa)
switch ((inst >> 12) & 0b111) {
case 0:
switch ((inst >> 25) & 0b1111111) {
- case 0b0000010: op = rv_op_th_sfence_vmas; break;
+ case 0b0000010: return &op_th_sfence_vmas;
case 0b0000000:
switch ((inst >> 20) & 0b11111) {
- case 0b11000: op = rv_op_th_sync; break;
- case 0b11010: op = rv_op_th_sync_i; break;
- case 0b11011: op = rv_op_th_sync_is; break;
- case 0b11001: op = rv_op_th_sync_s; break;
+ case 0b11000: return &op_th_sync;
+ case 0b11010: return &op_th_sync_i;
+ case 0b11011: return &op_th_sync_is;
+ case 0b11001: return &op_th_sync_s;
}
break;
}
@@ -706,5 +461,5 @@ const rv_opcode_data *decode_xtheadsync(rv_decode *dec, rv_isa isa)
break;
}
- return op == rv_op_illegal ? NULL : &xthead_opcode_data[op];
+ return NULL;
}
diff --git a/disas/riscv-xthead-op.c.inc b/disas/riscv-xthead-op.c.inc
new file mode 100644
index 0000000000..1e4e0557cd
--- /dev/null
+++ b/disas/riscv-xthead-op.c.inc
@@ -0,0 +1,125 @@
+/* XTheadBa */
+OP(th_addsl, "th.addsl", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm)
+
+/* XTheadBb */
+OP(th_srri, "th.srri", rv_codec_r2_imm6, rv_fmt_rd_rs1_imm)
+OP(th_srriw, "th.srriw", rv_codec_r2_imm5, rv_fmt_rd_rs1_imm)
+OP(th_ext, "th.ext", rv_codec_r2_immhl, rv_fmt_rd_rs1_immh_imml)
+OP(th_extu, "th.extu", rv_codec_r2_immhl, rv_fmt_rd_rs1_immh_imml)
+OP(th_ff0, "th.ff0", rv_codec_r2, rv_fmt_rd_rs1)
+OP(th_ff1, "th.ff1", rv_codec_r2, rv_fmt_rd_rs1)
+OP(th_rev, "th.rev", rv_codec_r2, rv_fmt_rd_rs1)
+OP(th_revw, "th.revw", rv_codec_r2, rv_fmt_rd_rs1)
+OP(th_tstnbz, "th.tstnbz", rv_codec_r2, rv_fmt_rd_rs1)
+
+/* XTheadBs */
+OP(th_tst, "th.tst", rv_codec_r2_imm6, rv_fmt_rd_rs1_imm)
+
+/* XTheadCmo */
+OP(th_dcache_call, "th.dcache.call", rv_codec_none, rv_fmt_none)
+OP(th_dcache_ciall, "th.dcache.ciall", rv_codec_none, rv_fmt_none)
+OP(th_dcache_iall, "th.dcache.iall", rv_codec_none, rv_fmt_none)
+OP(th_dcache_cpa, "th.dcache.cpa", rv_codec_r, rv_fmt_rs1)
+OP(th_dcache_cipa, "th.dcache.cipa", rv_codec_r, rv_fmt_rs1)
+OP(th_dcache_ipa, "th.dcache.ipa", rv_codec_r, rv_fmt_rs1)
+OP(th_dcache_cva, "th.dcache.cva", rv_codec_r, rv_fmt_rs1)
+OP(th_dcache_civa, "th.dcache.civa", rv_codec_r, rv_fmt_rs1)
+OP(th_dcache_iva, "th.dcache.iva", rv_codec_r, rv_fmt_rs1)
+OP(th_dcache_csw, "th.dcache.csw", rv_codec_r, rv_fmt_rs1)
+OP(th_dcache_cisw, "th.dcache.cisw", rv_codec_r, rv_fmt_rs1)
+OP(th_dcache_isw, "th.dcache.isw", rv_codec_r, rv_fmt_rs1)
+OP(th_dcache_cpal1, "th.dcache.cpal1", rv_codec_r, rv_fmt_rs1)
+OP(th_dcache_cval1, "th.dcache.cval1", rv_codec_r, rv_fmt_rs1)
+OP(th_icache_iall, "th.icache.iall", rv_codec_none, rv_fmt_none)
+OP(th_icache_ialls, "th.icache.ialls", rv_codec_none, rv_fmt_none)
+OP(th_icache_ipa, "th.icache.ipa", rv_codec_r, rv_fmt_rs1)
+OP(th_icache_iva, "th.icache.iva", rv_codec_r, rv_fmt_rs1)
+OP(th_l2cache_call, "th.l2cache.call", rv_codec_none, rv_fmt_none)
+OP(th_l2cache_ciall, "th.l2cache.ciall", rv_codec_none, rv_fmt_none)
+OP(th_l2cache_iall, "th.l2cache.iall", rv_codec_none, rv_fmt_none)
+
+/* XTheadCondMov */
+OP(th_mveqz, "th.mveqz", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(th_mvnez, "th.mvnez", rv_codec_r, rv_fmt_rd_rs1_rs2)
+
+/* XTheadFMemIdx */
+OP(th_flrd, "th.flrd", rv_codec_r_imm2, rv_fmt_frd_rs1_rs2_imm)
+OP(th_flrw, "th.flrw", rv_codec_r_imm2, rv_fmt_frd_rs1_rs2_imm)
+OP(th_flurd, "th.flurd", rv_codec_r_imm2, rv_fmt_frd_rs1_rs2_imm)
+OP(th_flurw, "th.flurw", rv_codec_r_imm2, rv_fmt_frd_rs1_rs2_imm)
+OP(th_fsrd, "th.fsrd", rv_codec_r_imm2, rv_fmt_frd_rs1_rs2_imm)
+OP(th_fsrw, "th.fsrw", rv_codec_r_imm2, rv_fmt_frd_rs1_rs2_imm)
+OP(th_fsurd, "th.fsurd", rv_codec_r_imm2, rv_fmt_frd_rs1_rs2_imm)
+OP(th_fsurw, "th.fsurw", rv_codec_r_imm2, rv_fmt_frd_rs1_rs2_imm)
+
+/* XTheadFmv */
+OP(th_fmv_hw_x, "th.fmv.hw.x", rv_codec_r, rv_fmt_rd_frs1)
+OP(th_fmv_x_hw, "th.fmv.x.hw", rv_codec_r, rv_fmt_rd_frs1)
+
+/* XTheadMac */
+OP(th_mula, "th.mula", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(th_mulaw, "th.mulaw", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(th_mulah, "th.mulah", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(th_muls, "th.muls", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(th_mulsw, "th.mulsw", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(th_mulsh, "th.mulsh", rv_codec_r, rv_fmt_rd_rs1_rs2)
+
+/* XTheadMemIdx */
+OP(th_lbia, "th.lbia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr)
+OP(th_lbib, "th.lbib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr)
+OP(th_lbuia, "th.lbuia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr)
+OP(th_lbuib, "th.lbuib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr)
+OP(th_lhia, "th.lhia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr)
+OP(th_lhib, "th.lhib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr)
+OP(th_lhuia, "th.lhuia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr)
+OP(th_lhuib, "th.lhuib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr)
+OP(th_lwia, "th.lwia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr)
+OP(th_lwib, "th.lwib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr)
+OP(th_lwuia, "th.lwuia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr)
+OP(th_lwuib, "th.lwuib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr)
+OP(th_ldia, "th.ldia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr)
+OP(th_ldib, "th.ldib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr)
+OP(th_sbia, "th.sbia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr)
+OP(th_sbib, "th.sbib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr)
+OP(th_shia, "th.shia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr)
+OP(th_shib, "th.shib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr)
+OP(th_swia, "th.swia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr)
+OP(th_swib, "th.swib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr)
+OP(th_sdia, "th.sdia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr)
+OP(th_sdib, "th.sdib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr)
+OP(th_lrb, "th.lrb", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm)
+OP(th_lrbu, "th.lrbu", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm)
+OP(th_lrh, "th.lrh", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm)
+OP(th_lrhu, "th.lrhu", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm)
+OP(th_lrw, "th.lrw", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm)
+OP(th_lrwu, "th.lrwu", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm)
+OP(th_lrd, "th.lrd", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm)
+OP(th_srb, "th.srb", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm)
+OP(th_srh, "th.srh", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm)
+OP(th_srw, "th.srw", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm)
+OP(th_srd, "th.srd", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm)
+OP(th_lurb, "th.lurb", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm)
+OP(th_lurbu, "th.lurbu", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm)
+OP(th_lurh, "th.lurh", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm)
+OP(th_lurhu, "th.lurhu", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm)
+OP(th_lurw, "th.lurw", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm)
+OP(th_lurwu, "th.lurwu", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm)
+OP(th_lurd, "th.lurd", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm)
+OP(th_surb, "th.surb", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm)
+OP(th_surh, "th.surh", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm)
+OP(th_surw, "th.surw", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm)
+OP(th_surd, "th.surd", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm)
+
+/* XTheadMemPair */
+OP(th_ldd, "th.ldd", rv_codec_r_imm2, rv_fmt_rd2_imm)
+OP(th_lwd, "th.lwd", rv_codec_r_imm2, rv_fmt_rd2_imm)
+OP(th_lwud, "th.lwud", rv_codec_r_imm2, rv_fmt_rd2_imm)
+OP(th_sdd, "th.sdd", rv_codec_r_imm2, rv_fmt_rd2_imm)
+OP(th_swd, "th.swd", rv_codec_r_imm2, rv_fmt_rd2_imm)
+
+/* XTheadSync */
+OP(th_sfence_vmas, "th.sfence.vmas", rv_codec_r, rv_fmt_rs1_rs2)
+OP(th_sync, "th.sync", rv_codec_none, rv_fmt_none)
+OP(th_sync_i, "th.sync.i", rv_codec_none, rv_fmt_none)
+OP(th_sync_is, "th.sync.is", rv_codec_none, rv_fmt_none)
+OP(th_sync_s, "th.sync.s", rv_codec_none, rv_fmt_none)
--
2.43.0
^ permalink raw reply related [flat|nested] 119+ messages in thread
* [PATCH 48/56] disas/riscv: Move rv_op_illegal to riscv.c
2026-08-09 22:34 [RFC PATCH 00/56] disas/riscv: Reorganize the disassembler Richard Henderson
` (46 preceding siblings ...)
2026-08-09 22:35 ` [PATCH 47/56] disas/riscv: Split xthead_opcode_data Richard Henderson
@ 2026-08-09 22:35 ` Richard Henderson
2026-08-12 12:54 ` Alistair
2026-08-09 22:35 ` [PATCH 49/56] disas/riscv: Split out riscv-op.c.inc Richard Henderson
` (7 subsequent siblings)
55 siblings, 1 reply; 119+ messages in thread
From: Richard Henderson @ 2026-08-09 22:35 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-riscv
illegal is no longer used in other files.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
disas/riscv.h | 4 ----
disas/riscv.c | 2 +-
2 files changed, 1 insertion(+), 5 deletions(-)
diff --git a/disas/riscv.h b/disas/riscv.h
index 241dd47d7f..5ac8c41616 100644
--- a/disas/riscv.h
+++ b/disas/riscv.h
@@ -200,10 +200,6 @@ typedef struct {
uint8_t rlist;
} rv_decode;
-enum {
- rv_op_illegal = 0
-};
-
/* instruction formats */
#define rv_fmt_none "O\t"
diff --git a/disas/riscv.c b/disas/riscv.c
index 4141741d79..f0b3bc6be7 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -29,7 +29,7 @@
#include "disas/riscv-xlrbr.h"
typedef enum {
- /* 0 is reserved for rv_op_illegal. */
+ rv_op_illegal = 0,
rv_op_lui = 1,
rv_op_auipc = 2,
rv_op_jal = 3,
--
2.43.0
^ permalink raw reply related [flat|nested] 119+ messages in thread
* [PATCH 49/56] disas/riscv: Split out riscv-op.c.inc
2026-08-09 22:34 [RFC PATCH 00/56] disas/riscv: Reorganize the disassembler Richard Henderson
` (47 preceding siblings ...)
2026-08-09 22:35 ` [PATCH 48/56] disas/riscv: Move rv_op_illegal to riscv.c Richard Henderson
@ 2026-08-09 22:35 ` Richard Henderson
2026-08-12 12:55 ` Alistair
2026-08-09 22:35 ` [PATCH 50/56] disas/riscv: Merge all mop.r.n to one pattern Richard Henderson
` (6 subsequent siblings)
55 siblings, 1 reply; 119+ messages in thread
From: Richard Henderson @ 2026-08-09 22:35 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-riscv
Move rvi_opcode_data to riscv-op.c.inc and massage
the lines into OP() form. Unlike other files, keep
the enumeration and the table intact for now, but
build them both from the same source.
Adjust the names of rv_*mop to include _op_ to match
the general pattern.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
disas/riscv.c | 1931 +-----------------------------------------
disas/riscv-op.c.inc | 958 +++++++++++++++++++++
2 files changed, 967 insertions(+), 1922 deletions(-)
create mode 100644 disas/riscv-op.c.inc
diff --git a/disas/riscv.c b/disas/riscv.c
index f0b3bc6be7..9dad56b486 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -29,964 +29,9 @@
#include "disas/riscv-xlrbr.h"
typedef enum {
- rv_op_illegal = 0,
- rv_op_lui = 1,
- rv_op_auipc = 2,
- rv_op_jal = 3,
- rv_op_jalr = 4,
- rv_op_beq = 5,
- rv_op_bne = 6,
- rv_op_blt = 7,
- rv_op_bge = 8,
- rv_op_bltu = 9,
- rv_op_bgeu = 10,
- rv_op_lb = 11,
- rv_op_lh = 12,
- rv_op_lw = 13,
- rv_op_lbu = 14,
- rv_op_lhu = 15,
- rv_op_sb = 16,
- rv_op_sh = 17,
- rv_op_sw = 18,
- rv_op_addi = 19,
- rv_op_slti = 20,
- rv_op_sltiu = 21,
- rv_op_xori = 22,
- rv_op_ori = 23,
- rv_op_andi = 24,
- rv_op_slli = 25,
- rv_op_srli = 26,
- rv_op_srai = 27,
- rv_op_add = 28,
- rv_op_sub = 29,
- rv_op_sll = 30,
- rv_op_slt = 31,
- rv_op_sltu = 32,
- rv_op_xor = 33,
- rv_op_srl = 34,
- rv_op_sra = 35,
- rv_op_or = 36,
- rv_op_and = 37,
- rv_op_fence = 38,
- rv_op_fence_i = 39,
- rv_op_lwu = 40,
- rv_op_ld = 41,
- rv_op_sd = 42,
- rv_op_addiw = 43,
- rv_op_slliw = 44,
- rv_op_srliw = 45,
- rv_op_sraiw = 46,
- rv_op_addw = 47,
- rv_op_subw = 48,
- rv_op_sllw = 49,
- rv_op_srlw = 50,
- rv_op_sraw = 51,
- rv_op_ldu = 52,
- rv_op_lq = 53,
- rv_op_sq = 54,
- rv_op_addid = 55,
- rv_op_sllid = 56,
- rv_op_srlid = 57,
- rv_op_sraid = 58,
- rv_op_addd = 59,
- rv_op_subd = 60,
- rv_op_slld = 61,
- rv_op_srld = 62,
- rv_op_srad = 63,
- rv_op_mul = 64,
- rv_op_mulh = 65,
- rv_op_mulhsu = 66,
- rv_op_mulhu = 67,
- rv_op_div = 68,
- rv_op_divu = 69,
- rv_op_rem = 70,
- rv_op_remu = 71,
- rv_op_mulw = 72,
- rv_op_divw = 73,
- rv_op_divuw = 74,
- rv_op_remw = 75,
- rv_op_remuw = 76,
- rv_op_muld = 77,
- rv_op_divd = 78,
- rv_op_divud = 79,
- rv_op_remd = 80,
- rv_op_remud = 81,
- rv_op_lr_w = 82,
- rv_op_sc_w = 83,
- rv_op_amoswap_w = 84,
- rv_op_amoadd_w = 85,
- rv_op_amoxor_w = 86,
- rv_op_amoor_w = 87,
- rv_op_amoand_w = 88,
- rv_op_amomin_w = 89,
- rv_op_amomax_w = 90,
- rv_op_amominu_w = 91,
- rv_op_amomaxu_w = 92,
- rv_op_lr_d = 93,
- rv_op_sc_d = 94,
- rv_op_amoswap_d = 95,
- rv_op_amoadd_d = 96,
- rv_op_amoxor_d = 97,
- rv_op_amoor_d = 98,
- rv_op_amoand_d = 99,
- rv_op_amomin_d = 100,
- rv_op_amomax_d = 101,
- rv_op_amominu_d = 102,
- rv_op_amomaxu_d = 103,
- rv_op_lr_q = 104,
- rv_op_sc_q = 105,
- rv_op_amoswap_q = 106,
- rv_op_amoadd_q = 107,
- rv_op_amoxor_q = 108,
- rv_op_amoor_q = 109,
- rv_op_amoand_q = 110,
- rv_op_amomin_q = 111,
- rv_op_amomax_q = 112,
- rv_op_amominu_q = 113,
- rv_op_amomaxu_q = 114,
- rv_op_ecall = 115,
- rv_op_ebreak = 116,
- rv_op_uret = 117,
- rv_op_sret = 118,
- rv_op_hret = 119,
- rv_op_mret = 120,
- rv_op_dret = 121,
- rv_op_sfence_vm = 122,
- rv_op_sfence_vma = 123,
- rv_op_wfi = 124,
- rv_op_csrrw = 125,
- rv_op_csrrs = 126,
- rv_op_csrrc = 127,
- rv_op_csrrwi = 128,
- rv_op_csrrsi = 129,
- rv_op_csrrci = 130,
- rv_op_flw = 131,
- rv_op_fsw = 132,
- rv_op_fmadd_s = 133,
- rv_op_fmsub_s = 134,
- rv_op_fnmsub_s = 135,
- rv_op_fnmadd_s = 136,
- rv_op_fadd_s = 137,
- rv_op_fsub_s = 138,
- rv_op_fmul_s = 139,
- rv_op_fdiv_s = 140,
- rv_op_fsgnj_s = 141,
- rv_op_fsgnjn_s = 142,
- rv_op_fsgnjx_s = 143,
- rv_op_fmin_s = 144,
- rv_op_fmax_s = 145,
- rv_op_fsqrt_s = 146,
- rv_op_fle_s = 147,
- rv_op_flt_s = 148,
- rv_op_feq_s = 149,
- rv_op_fcvt_w_s = 150,
- rv_op_fcvt_wu_s = 151,
- rv_op_fcvt_s_w = 152,
- rv_op_fcvt_s_wu = 153,
- rv_op_fmv_x_s = 154,
- rv_op_fclass_s = 155,
- rv_op_fmv_s_x = 156,
- rv_op_fcvt_l_s = 157,
- rv_op_fcvt_lu_s = 158,
- rv_op_fcvt_s_l = 159,
- rv_op_fcvt_s_lu = 160,
- rv_op_fld = 161,
- rv_op_fsd = 162,
- rv_op_fmadd_d = 163,
- rv_op_fmsub_d = 164,
- rv_op_fnmsub_d = 165,
- rv_op_fnmadd_d = 166,
- rv_op_fadd_d = 167,
- rv_op_fsub_d = 168,
- rv_op_fmul_d = 169,
- rv_op_fdiv_d = 170,
- rv_op_fsgnj_d = 171,
- rv_op_fsgnjn_d = 172,
- rv_op_fsgnjx_d = 173,
- rv_op_fmin_d = 174,
- rv_op_fmax_d = 175,
- rv_op_fcvt_s_d = 176,
- rv_op_fcvt_d_s = 177,
- rv_op_fsqrt_d = 178,
- rv_op_fle_d = 179,
- rv_op_flt_d = 180,
- rv_op_feq_d = 181,
- rv_op_fcvt_w_d = 182,
- rv_op_fcvt_wu_d = 183,
- rv_op_fcvt_d_w = 184,
- rv_op_fcvt_d_wu = 185,
- rv_op_fclass_d = 186,
- rv_op_fcvt_l_d = 187,
- rv_op_fcvt_lu_d = 188,
- rv_op_fmv_x_d = 189,
- rv_op_fcvt_d_l = 190,
- rv_op_fcvt_d_lu = 191,
- rv_op_fmv_d_x = 192,
- rv_op_flq = 193,
- rv_op_fsq = 194,
- rv_op_fmadd_q = 195,
- rv_op_fmsub_q = 196,
- rv_op_fnmsub_q = 197,
- rv_op_fnmadd_q = 198,
- rv_op_fadd_q = 199,
- rv_op_fsub_q = 200,
- rv_op_fmul_q = 201,
- rv_op_fdiv_q = 202,
- rv_op_fsgnj_q = 203,
- rv_op_fsgnjn_q = 204,
- rv_op_fsgnjx_q = 205,
- rv_op_fmin_q = 206,
- rv_op_fmax_q = 207,
- rv_op_fcvt_s_q = 208,
- rv_op_fcvt_q_s = 209,
- rv_op_fcvt_d_q = 210,
- rv_op_fcvt_q_d = 211,
- rv_op_fsqrt_q = 212,
- rv_op_fle_q = 213,
- rv_op_flt_q = 214,
- rv_op_feq_q = 215,
- rv_op_fcvt_w_q = 216,
- rv_op_fcvt_wu_q = 217,
- rv_op_fcvt_q_w = 218,
- rv_op_fcvt_q_wu = 219,
- rv_op_fclass_q = 220,
- rv_op_fcvt_l_q = 221,
- rv_op_fcvt_lu_q = 222,
- rv_op_fcvt_q_l = 223,
- rv_op_fcvt_q_lu = 224,
- rv_op_fmv_x_q = 225,
- rv_op_fmv_q_x = 226,
- rv_op_c_addi4spn = 227,
- rv_op_c_fld = 228,
- rv_op_c_lw = 229,
- rv_op_c_flw = 230,
- rv_op_c_fsd = 231,
- rv_op_c_sw = 232,
- rv_op_c_fsw = 233,
- rv_op_c_addi = 235,
- rv_op_c_jal = 236,
- rv_op_c_li = 237,
- rv_op_c_addi16sp = 238,
- rv_op_c_lui = 239,
- rv_op_c_srli = 240,
- rv_op_c_srai = 241,
- rv_op_c_andi = 242,
- rv_op_c_sub = 243,
- rv_op_c_xor = 244,
- rv_op_c_or = 245,
- rv_op_c_and = 246,
- rv_op_c_subw = 247,
- rv_op_c_addw = 248,
- rv_op_c_j = 249,
- rv_op_c_beqz = 250,
- rv_op_c_bnez = 251,
- rv_op_c_slli = 252,
- rv_op_c_fldsp = 253,
- rv_op_c_lwsp = 254,
- rv_op_c_flwsp = 255,
- rv_op_c_jr = 256,
- rv_op_c_mv = 257,
- rv_op_c_ebreak = 258,
- rv_op_c_jalr = 259,
- rv_op_c_add = 260,
- rv_op_c_fsdsp = 261,
- rv_op_c_swsp = 262,
- rv_op_c_fswsp = 263,
- rv_op_c_ld = 264,
- rv_op_c_sd = 265,
- rv_op_c_addiw = 266,
- rv_op_c_ldsp = 267,
- rv_op_c_sdsp = 268,
- rv_op_c_lq = 269,
- rv_op_c_sq = 270,
- rv_op_c_lqsp = 271,
- rv_op_c_sqsp = 272,
- rv_op_nop = 273,
- rv_op_mv = 274,
- rv_op_not = 275,
- rv_op_neg = 276,
- rv_op_negw = 277,
- rv_op_sext_w = 278,
- rv_op_seqz = 279,
- rv_op_snez = 280,
- rv_op_sltz = 281,
- rv_op_sgtz = 282,
- rv_op_fmv_s = 283,
- rv_op_fabs_s = 284,
- rv_op_fneg_s = 285,
- rv_op_fmv_d = 286,
- rv_op_fabs_d = 287,
- rv_op_fneg_d = 288,
- rv_op_fmv_q = 289,
- rv_op_fabs_q = 290,
- rv_op_fneg_q = 291,
- rv_op_beqz = 292,
- rv_op_bnez = 293,
- rv_op_blez = 294,
- rv_op_bgez = 295,
- rv_op_bltz = 296,
- rv_op_bgtz = 297,
- rv_op_jal_ra = 298,
- rv_op_jalr_ra = 299,
- rv_op_j = 302,
- rv_op_ret = 303,
- rv_op_jr = 304,
- rv_op_rdcycle = 305,
- rv_op_rdtime = 306,
- rv_op_rdinstret = 307,
- rv_op_rdcycleh = 308,
- rv_op_rdtimeh = 309,
- rv_op_rdinstreth = 310,
- rv_op_frcsr = 311,
- rv_op_frrm = 312,
- rv_op_frflags = 313,
- rv_op_fscsr = 314,
- rv_op_fsrm = 315,
- rv_op_fsflags = 316,
- rv_op_fsrmi = 317,
- rv_op_fsflagsi = 318,
- rv_op_bseti = 319,
- rv_op_bclri = 320,
- rv_op_binvi = 321,
- rv_op_bexti = 322,
- rv_op_rori = 323,
- rv_op_clz = 324,
- rv_op_ctz = 325,
- rv_op_cpop = 326,
- rv_op_sext_h = 327,
- rv_op_sext_b = 328,
- rv_op_xnor = 329,
- rv_op_orn = 330,
- rv_op_andn = 331,
- rv_op_rol = 332,
- rv_op_ror = 333,
- rv_op_sh1add = 334,
- rv_op_sh2add = 335,
- rv_op_sh3add = 336,
- rv_op_sh1add_uw = 337,
- rv_op_sh2add_uw = 338,
- rv_op_sh3add_uw = 339,
- rv_op_clmul = 340,
- rv_op_clmulr = 341,
- rv_op_clmulh = 342,
- rv_op_min = 343,
- rv_op_minu = 344,
- rv_op_max = 345,
- rv_op_maxu = 346,
- rv_op_clzw = 347,
- rv_op_ctzw = 348,
- rv_op_cpopw = 349,
- rv_op_slli_uw = 350,
- rv_op_add_uw = 351,
- rv_op_rolw = 352,
- rv_op_rorw = 353,
- rv_op_rev8 = 354,
- rv_op_zext_h = 355,
- rv_op_roriw = 356,
- rv_op_orc_b = 357,
- rv_op_bset = 358,
- rv_op_bclr = 359,
- rv_op_binv = 360,
- rv_op_bext = 361,
- rv_op_aes32esmi = 362,
- rv_op_aes32esi = 363,
- rv_op_aes32dsmi = 364,
- rv_op_aes32dsi = 365,
- rv_op_aes64ks1i = 366,
- rv_op_aes64ks2 = 367,
- rv_op_aes64im = 368,
- rv_op_aes64esm = 369,
- rv_op_aes64es = 370,
- rv_op_aes64dsm = 371,
- rv_op_aes64ds = 372,
- rv_op_sha256sig0 = 373,
- rv_op_sha256sig1 = 374,
- rv_op_sha256sum0 = 375,
- rv_op_sha256sum1 = 376,
- rv_op_sha512sig0 = 377,
- rv_op_sha512sig1 = 378,
- rv_op_sha512sum0 = 379,
- rv_op_sha512sum1 = 380,
- rv_op_sha512sum0r = 381,
- rv_op_sha512sum1r = 382,
- rv_op_sha512sig0l = 383,
- rv_op_sha512sig0h = 384,
- rv_op_sha512sig1l = 385,
- rv_op_sha512sig1h = 386,
- rv_op_sm3p0 = 387,
- rv_op_sm3p1 = 388,
- rv_op_sm4ed = 389,
- rv_op_sm4ks = 390,
- rv_op_brev8 = 391,
- rv_op_pack = 392,
- rv_op_packh = 393,
- rv_op_packw = 394,
- rv_op_unzip = 395,
- rv_op_zip = 396,
- rv_op_xperm4 = 397,
- rv_op_xperm8 = 398,
- rv_op_vle8_v = 399,
- rv_op_vle16_v = 400,
- rv_op_vle32_v = 401,
- rv_op_vle64_v = 402,
- rv_op_vse8_v = 403,
- rv_op_vse16_v = 404,
- rv_op_vse32_v = 405,
- rv_op_vse64_v = 406,
- rv_op_vlm_v = 407,
- rv_op_vsm_v = 408,
- rv_op_vlse8_v = 409,
- rv_op_vlse16_v = 410,
- rv_op_vlse32_v = 411,
- rv_op_vlse64_v = 412,
- rv_op_vsse8_v = 413,
- rv_op_vsse16_v = 414,
- rv_op_vsse32_v = 415,
- rv_op_vsse64_v = 416,
- rv_op_vluxei8_v = 417,
- rv_op_vluxei16_v = 418,
- rv_op_vluxei32_v = 419,
- rv_op_vluxei64_v = 420,
- rv_op_vloxei8_v = 421,
- rv_op_vloxei16_v = 422,
- rv_op_vloxei32_v = 423,
- rv_op_vloxei64_v = 424,
- rv_op_vsuxei8_v = 425,
- rv_op_vsuxei16_v = 426,
- rv_op_vsuxei32_v = 427,
- rv_op_vsuxei64_v = 428,
- rv_op_vsoxei8_v = 429,
- rv_op_vsoxei16_v = 430,
- rv_op_vsoxei32_v = 431,
- rv_op_vsoxei64_v = 432,
- rv_op_vle8ff_v = 433,
- rv_op_vle16ff_v = 434,
- rv_op_vle32ff_v = 435,
- rv_op_vle64ff_v = 436,
- rv_op_vl1re8_v = 437,
- rv_op_vl1re16_v = 438,
- rv_op_vl1re32_v = 439,
- rv_op_vl1re64_v = 440,
- rv_op_vl2re8_v = 441,
- rv_op_vl2re16_v = 442,
- rv_op_vl2re32_v = 443,
- rv_op_vl2re64_v = 444,
- rv_op_vl4re8_v = 445,
- rv_op_vl4re16_v = 446,
- rv_op_vl4re32_v = 447,
- rv_op_vl4re64_v = 448,
- rv_op_vl8re8_v = 449,
- rv_op_vl8re16_v = 450,
- rv_op_vl8re32_v = 451,
- rv_op_vl8re64_v = 452,
- rv_op_vs1r_v = 453,
- rv_op_vs2r_v = 454,
- rv_op_vs4r_v = 455,
- rv_op_vs8r_v = 456,
- rv_op_vadd_vv = 457,
- rv_op_vadd_vx = 458,
- rv_op_vadd_vi = 459,
- rv_op_vsub_vv = 460,
- rv_op_vsub_vx = 461,
- rv_op_vrsub_vx = 462,
- rv_op_vrsub_vi = 463,
- rv_op_vwaddu_vv = 464,
- rv_op_vwaddu_vx = 465,
- rv_op_vwadd_vv = 466,
- rv_op_vwadd_vx = 467,
- rv_op_vwsubu_vv = 468,
- rv_op_vwsubu_vx = 469,
- rv_op_vwsub_vv = 470,
- rv_op_vwsub_vx = 471,
- rv_op_vwaddu_wv = 472,
- rv_op_vwaddu_wx = 473,
- rv_op_vwadd_wv = 474,
- rv_op_vwadd_wx = 475,
- rv_op_vwsubu_wv = 476,
- rv_op_vwsubu_wx = 477,
- rv_op_vwsub_wv = 478,
- rv_op_vwsub_wx = 479,
- rv_op_vadc_vvm = 480,
- rv_op_vadc_vxm = 481,
- rv_op_vadc_vim = 482,
- rv_op_vmadc_vvm = 483,
- rv_op_vmadc_vxm = 484,
- rv_op_vmadc_vim = 485,
- rv_op_vsbc_vvm = 486,
- rv_op_vsbc_vxm = 487,
- rv_op_vmsbc_vvm = 488,
- rv_op_vmsbc_vxm = 489,
- rv_op_vand_vv = 490,
- rv_op_vand_vx = 491,
- rv_op_vand_vi = 492,
- rv_op_vor_vv = 493,
- rv_op_vor_vx = 494,
- rv_op_vor_vi = 495,
- rv_op_vxor_vv = 496,
- rv_op_vxor_vx = 497,
- rv_op_vxor_vi = 498,
- rv_op_vsll_vv = 499,
- rv_op_vsll_vx = 500,
- rv_op_vsll_vi = 501,
- rv_op_vsrl_vv = 502,
- rv_op_vsrl_vx = 503,
- rv_op_vsrl_vi = 504,
- rv_op_vsra_vv = 505,
- rv_op_vsra_vx = 506,
- rv_op_vsra_vi = 507,
- rv_op_vnsrl_wv = 508,
- rv_op_vnsrl_wx = 509,
- rv_op_vnsrl_wi = 510,
- rv_op_vnsra_wv = 511,
- rv_op_vnsra_wx = 512,
- rv_op_vnsra_wi = 513,
- rv_op_vmseq_vv = 514,
- rv_op_vmseq_vx = 515,
- rv_op_vmseq_vi = 516,
- rv_op_vmsne_vv = 517,
- rv_op_vmsne_vx = 518,
- rv_op_vmsne_vi = 519,
- rv_op_vmsltu_vv = 520,
- rv_op_vmsltu_vx = 521,
- rv_op_vmslt_vv = 522,
- rv_op_vmslt_vx = 523,
- rv_op_vmsleu_vv = 524,
- rv_op_vmsleu_vx = 525,
- rv_op_vmsleu_vi = 526,
- rv_op_vmsle_vv = 527,
- rv_op_vmsle_vx = 528,
- rv_op_vmsle_vi = 529,
- rv_op_vmsgtu_vx = 530,
- rv_op_vmsgtu_vi = 531,
- rv_op_vmsgt_vx = 532,
- rv_op_vmsgt_vi = 533,
- rv_op_vminu_vv = 534,
- rv_op_vminu_vx = 535,
- rv_op_vmin_vv = 536,
- rv_op_vmin_vx = 537,
- rv_op_vmaxu_vv = 538,
- rv_op_vmaxu_vx = 539,
- rv_op_vmax_vv = 540,
- rv_op_vmax_vx = 541,
- rv_op_vmul_vv = 542,
- rv_op_vmul_vx = 543,
- rv_op_vmulh_vv = 544,
- rv_op_vmulh_vx = 545,
- rv_op_vmulhu_vv = 546,
- rv_op_vmulhu_vx = 547,
- rv_op_vmulhsu_vv = 548,
- rv_op_vmulhsu_vx = 549,
- rv_op_vdivu_vv = 550,
- rv_op_vdivu_vx = 551,
- rv_op_vdiv_vv = 552,
- rv_op_vdiv_vx = 553,
- rv_op_vremu_vv = 554,
- rv_op_vremu_vx = 555,
- rv_op_vrem_vv = 556,
- rv_op_vrem_vx = 557,
- rv_op_vwmulu_vv = 558,
- rv_op_vwmulu_vx = 559,
- rv_op_vwmulsu_vv = 560,
- rv_op_vwmulsu_vx = 561,
- rv_op_vwmul_vv = 562,
- rv_op_vwmul_vx = 563,
- rv_op_vmacc_vv = 564,
- rv_op_vmacc_vx = 565,
- rv_op_vnmsac_vv = 566,
- rv_op_vnmsac_vx = 567,
- rv_op_vmadd_vv = 568,
- rv_op_vmadd_vx = 569,
- rv_op_vnmsub_vv = 570,
- rv_op_vnmsub_vx = 571,
- rv_op_vwmaccu_vv = 572,
- rv_op_vwmaccu_vx = 573,
- rv_op_vwmacc_vv = 574,
- rv_op_vwmacc_vx = 575,
- rv_op_vwmaccsu_vv = 576,
- rv_op_vwmaccsu_vx = 577,
- rv_op_vwmaccus_vx = 578,
- rv_op_vmv_v_v = 579,
- rv_op_vmv_v_x = 580,
- rv_op_vmv_v_i = 581,
- rv_op_vmerge_vvm = 582,
- rv_op_vmerge_vxm = 583,
- rv_op_vmerge_vim = 584,
- rv_op_vsaddu_vv = 585,
- rv_op_vsaddu_vx = 586,
- rv_op_vsaddu_vi = 587,
- rv_op_vsadd_vv = 588,
- rv_op_vsadd_vx = 589,
- rv_op_vsadd_vi = 590,
- rv_op_vssubu_vv = 591,
- rv_op_vssubu_vx = 592,
- rv_op_vssub_vv = 593,
- rv_op_vssub_vx = 594,
- rv_op_vaadd_vv = 595,
- rv_op_vaadd_vx = 596,
- rv_op_vaaddu_vv = 597,
- rv_op_vaaddu_vx = 598,
- rv_op_vasub_vv = 599,
- rv_op_vasub_vx = 600,
- rv_op_vasubu_vv = 601,
- rv_op_vasubu_vx = 602,
- rv_op_vsmul_vv = 603,
- rv_op_vsmul_vx = 604,
- rv_op_vssrl_vv = 605,
- rv_op_vssrl_vx = 606,
- rv_op_vssrl_vi = 607,
- rv_op_vssra_vv = 608,
- rv_op_vssra_vx = 609,
- rv_op_vssra_vi = 610,
- rv_op_vnclipu_wv = 611,
- rv_op_vnclipu_wx = 612,
- rv_op_vnclipu_wi = 613,
- rv_op_vnclip_wv = 614,
- rv_op_vnclip_wx = 615,
- rv_op_vnclip_wi = 616,
- rv_op_vfadd_vv = 617,
- rv_op_vfadd_vf = 618,
- rv_op_vfsub_vv = 619,
- rv_op_vfsub_vf = 620,
- rv_op_vfrsub_vf = 621,
- rv_op_vfwadd_vv = 622,
- rv_op_vfwadd_vf = 623,
- rv_op_vfwadd_wv = 624,
- rv_op_vfwadd_wf = 625,
- rv_op_vfwsub_vv = 626,
- rv_op_vfwsub_vf = 627,
- rv_op_vfwsub_wv = 628,
- rv_op_vfwsub_wf = 629,
- rv_op_vfmul_vv = 630,
- rv_op_vfmul_vf = 631,
- rv_op_vfdiv_vv = 632,
- rv_op_vfdiv_vf = 633,
- rv_op_vfrdiv_vf = 634,
- rv_op_vfwmul_vv = 635,
- rv_op_vfwmul_vf = 636,
- rv_op_vfmacc_vv = 637,
- rv_op_vfmacc_vf = 638,
- rv_op_vfnmacc_vv = 639,
- rv_op_vfnmacc_vf = 640,
- rv_op_vfmsac_vv = 641,
- rv_op_vfmsac_vf = 642,
- rv_op_vfnmsac_vv = 643,
- rv_op_vfnmsac_vf = 644,
- rv_op_vfmadd_vv = 645,
- rv_op_vfmadd_vf = 646,
- rv_op_vfnmadd_vv = 647,
- rv_op_vfnmadd_vf = 648,
- rv_op_vfmsub_vv = 649,
- rv_op_vfmsub_vf = 650,
- rv_op_vfnmsub_vv = 651,
- rv_op_vfnmsub_vf = 652,
- rv_op_vfwmacc_vv = 653,
- rv_op_vfwmacc_vf = 654,
- rv_op_vfwnmacc_vv = 655,
- rv_op_vfwnmacc_vf = 656,
- rv_op_vfwmsac_vv = 657,
- rv_op_vfwmsac_vf = 658,
- rv_op_vfwnmsac_vv = 659,
- rv_op_vfwnmsac_vf = 660,
- rv_op_vfsqrt_v = 661,
- rv_op_vfrsqrt7_v = 662,
- rv_op_vfrec7_v = 663,
- rv_op_vfmin_vv = 664,
- rv_op_vfmin_vf = 665,
- rv_op_vfmax_vv = 666,
- rv_op_vfmax_vf = 667,
- rv_op_vfsgnj_vv = 668,
- rv_op_vfsgnj_vf = 669,
- rv_op_vfsgnjn_vv = 670,
- rv_op_vfsgnjn_vf = 671,
- rv_op_vfsgnjx_vv = 672,
- rv_op_vfsgnjx_vf = 673,
- rv_op_vfslide1up_vf = 674,
- rv_op_vfslide1down_vf = 675,
- rv_op_vmfeq_vv = 676,
- rv_op_vmfeq_vf = 677,
- rv_op_vmfne_vv = 678,
- rv_op_vmfne_vf = 679,
- rv_op_vmflt_vv = 680,
- rv_op_vmflt_vf = 681,
- rv_op_vmfle_vv = 682,
- rv_op_vmfle_vf = 683,
- rv_op_vmfgt_vf = 684,
- rv_op_vmfge_vf = 685,
- rv_op_vfclass_v = 686,
- rv_op_vfmerge_vfm = 687,
- rv_op_vfmv_v_f = 688,
- rv_op_vfcvt_xu_f_v = 689,
- rv_op_vfcvt_x_f_v = 690,
- rv_op_vfcvt_f_xu_v = 691,
- rv_op_vfcvt_f_x_v = 692,
- rv_op_vfcvt_rtz_xu_f_v = 693,
- rv_op_vfcvt_rtz_x_f_v = 694,
- rv_op_vfwcvt_xu_f_v = 695,
- rv_op_vfwcvt_x_f_v = 696,
- rv_op_vfwcvt_f_xu_v = 697,
- rv_op_vfwcvt_f_x_v = 698,
- rv_op_vfwcvt_f_f_v = 699,
- rv_op_vfwcvt_rtz_xu_f_v = 700,
- rv_op_vfwcvt_rtz_x_f_v = 701,
- rv_op_vfncvt_xu_f_w = 702,
- rv_op_vfncvt_x_f_w = 703,
- rv_op_vfncvt_f_xu_w = 704,
- rv_op_vfncvt_f_x_w = 705,
- rv_op_vfncvt_f_f_w = 706,
- rv_op_vfncvt_rod_f_f_w = 707,
- rv_op_vfncvt_rtz_xu_f_w = 708,
- rv_op_vfncvt_rtz_x_f_w = 709,
- rv_op_vredsum_vs = 710,
- rv_op_vredand_vs = 711,
- rv_op_vredor_vs = 712,
- rv_op_vredxor_vs = 713,
- rv_op_vredminu_vs = 714,
- rv_op_vredmin_vs = 715,
- rv_op_vredmaxu_vs = 716,
- rv_op_vredmax_vs = 717,
- rv_op_vwredsumu_vs = 718,
- rv_op_vwredsum_vs = 719,
- rv_op_vfredusum_vs = 720,
- rv_op_vfredosum_vs = 721,
- rv_op_vfredmin_vs = 722,
- rv_op_vfredmax_vs = 723,
- rv_op_vfwredusum_vs = 724,
- rv_op_vfwredosum_vs = 725,
- rv_op_vmand_mm = 726,
- rv_op_vmnand_mm = 727,
- rv_op_vmandn_mm = 728,
- rv_op_vmxor_mm = 729,
- rv_op_vmor_mm = 730,
- rv_op_vmnor_mm = 731,
- rv_op_vmorn_mm = 732,
- rv_op_vmxnor_mm = 733,
- rv_op_vcpop_m = 734,
- rv_op_vfirst_m = 735,
- rv_op_vmsbf_m = 736,
- rv_op_vmsif_m = 737,
- rv_op_vmsof_m = 738,
- rv_op_viota_m = 739,
- rv_op_vid_v = 740,
- rv_op_vmv_x_s = 741,
- rv_op_vmv_s_x = 742,
- rv_op_vfmv_f_s = 743,
- rv_op_vfmv_s_f = 744,
- rv_op_vslideup_vx = 745,
- rv_op_vslideup_vi = 746,
- rv_op_vslide1up_vx = 747,
- rv_op_vslidedown_vx = 748,
- rv_op_vslidedown_vi = 749,
- rv_op_vslide1down_vx = 750,
- rv_op_vrgather_vv = 751,
- rv_op_vrgatherei16_vv = 752,
- rv_op_vrgather_vx = 753,
- rv_op_vrgather_vi = 754,
- rv_op_vcompress_vm = 755,
- rv_op_vmv1r_v = 756,
- rv_op_vmv2r_v = 757,
- rv_op_vmv4r_v = 758,
- rv_op_vmv8r_v = 759,
- rv_op_vzext_vf2 = 760,
- rv_op_vzext_vf4 = 761,
- rv_op_vzext_vf8 = 762,
- rv_op_vsext_vf2 = 763,
- rv_op_vsext_vf4 = 764,
- rv_op_vsext_vf8 = 765,
- rv_op_vsetvli = 766,
- rv_op_vsetivli = 767,
- rv_op_vsetvl = 768,
- rv_op_c_zext_b = 769,
- rv_op_c_sext_b = 770,
- rv_op_c_zext_h = 771,
- rv_op_c_sext_h = 772,
- rv_op_c_zext_w = 773,
- rv_op_c_not = 774,
- rv_op_c_mul = 775,
- rv_op_c_lbu = 776,
- rv_op_c_lhu = 777,
- rv_op_c_lh = 778,
- rv_op_c_sb = 779,
- rv_op_c_sh = 780,
- rv_op_cm_push = 781,
- rv_op_cm_pop = 782,
- rv_op_cm_popret = 783,
- rv_op_cm_popretz = 784,
- rv_op_cm_mva01s = 785,
- rv_op_cm_mvsa01 = 786,
- rv_op_cm_jt = 787,
- rv_op_cm_jalt = 788,
- rv_op_czero_eqz = 789,
- rv_op_czero_nez = 790,
- rv_op_fcvt_bf16_s = 791,
- rv_op_fcvt_s_bf16 = 792,
- rv_op_vfncvtbf16_f_f_w = 793,
- rv_op_vfwcvtbf16_f_f_v = 794,
- rv_op_vfwmaccbf16_vv = 795,
- rv_op_vfwmaccbf16_vf = 796,
- rv_op_flh = 797,
- rv_op_fsh = 798,
- rv_op_fmv_h_x = 799,
- rv_op_fmv_x_h = 800,
- rv_op_fli_s = 801,
- rv_op_fli_d = 802,
- rv_op_fli_q = 803,
- rv_op_fli_h = 804,
- rv_op_fminm_s = 805,
- rv_op_fmaxm_s = 806,
- rv_op_fminm_d = 807,
- rv_op_fmaxm_d = 808,
- rv_op_fminm_q = 809,
- rv_op_fmaxm_q = 810,
- rv_op_fminm_h = 811,
- rv_op_fmaxm_h = 812,
- rv_op_fround_s = 813,
- rv_op_froundnx_s = 814,
- rv_op_fround_d = 815,
- rv_op_froundnx_d = 816,
- rv_op_fround_q = 817,
- rv_op_froundnx_q = 818,
- rv_op_fround_h = 819,
- rv_op_froundnx_h = 820,
- rv_op_fcvtmod_w_d = 821,
- rv_op_fmvh_x_d = 822,
- rv_op_fmvp_d_x = 823,
- rv_op_fmvh_x_q = 824,
- rv_op_fmvp_q_x = 825,
- rv_op_fleq_s = 826,
- rv_op_fltq_s = 827,
- rv_op_fleq_d = 828,
- rv_op_fltq_d = 829,
- rv_op_fleq_q = 830,
- rv_op_fltq_q = 831,
- rv_op_fleq_h = 832,
- rv_op_fltq_h = 833,
- rv_op_vaesdf_vv = 834,
- rv_op_vaesdf_vs = 835,
- rv_op_vaesdm_vv = 836,
- rv_op_vaesdm_vs = 837,
- rv_op_vaesef_vv = 838,
- rv_op_vaesef_vs = 839,
- rv_op_vaesem_vv = 840,
- rv_op_vaesem_vs = 841,
- rv_op_vaeskf1_vi = 842,
- rv_op_vaeskf2_vi = 843,
- rv_op_vaesz_vs = 844,
- rv_op_vandn_vv = 845,
- rv_op_vandn_vx = 846,
- rv_op_vbrev_v = 847,
- rv_op_vbrev8_v = 848,
- rv_op_vclmul_vv = 849,
- rv_op_vclmul_vx = 850,
- rv_op_vclmulh_vv = 851,
- rv_op_vclmulh_vx = 852,
- rv_op_vclz_v = 853,
- rv_op_vcpop_v = 854,
- rv_op_vctz_v = 855,
- rv_op_vghsh_vv = 856,
- rv_op_vgmul_vv = 857,
- rv_op_vrev8_v = 858,
- rv_op_vrol_vv = 859,
- rv_op_vrol_vx = 860,
- rv_op_vror_vv = 861,
- rv_op_vror_vx = 862,
- rv_op_vror_vi = 863,
- rv_op_vsha2ch_vv = 864,
- rv_op_vsha2cl_vv = 865,
- rv_op_vsha2ms_vv = 866,
- rv_op_vsm3c_vi = 867,
- rv_op_vsm3me_vv = 868,
- rv_op_vsm4k_vi = 869,
- rv_op_vsm4r_vv = 870,
- rv_op_vsm4r_vs = 871,
- rv_op_vwsll_vv = 872,
- rv_op_vwsll_vx = 873,
- rv_op_vwsll_vi = 874,
- rv_op_amocas_w = 875,
- rv_op_amocas_d = 876,
- rv_op_amocas_q = 877,
- rv_mop_r_0 = 878,
- rv_mop_r_1 = 879,
- rv_mop_r_2 = 880,
- rv_mop_r_3 = 881,
- rv_mop_r_4 = 882,
- rv_mop_r_5 = 883,
- rv_mop_r_6 = 884,
- rv_mop_r_7 = 885,
- rv_mop_r_8 = 886,
- rv_mop_r_9 = 887,
- rv_mop_r_10 = 888,
- rv_mop_r_11 = 889,
- rv_mop_r_12 = 890,
- rv_mop_r_13 = 891,
- rv_mop_r_14 = 892,
- rv_mop_r_15 = 893,
- rv_mop_r_16 = 894,
- rv_mop_r_17 = 895,
- rv_mop_r_18 = 896,
- rv_mop_r_19 = 897,
- rv_mop_r_20 = 898,
- rv_mop_r_21 = 899,
- rv_mop_r_22 = 900,
- rv_mop_r_23 = 901,
- rv_mop_r_24 = 902,
- rv_mop_r_25 = 903,
- rv_mop_r_26 = 904,
- rv_mop_r_27 = 905,
- rv_mop_r_28 = 906,
- rv_mop_r_29 = 907,
- rv_mop_r_30 = 908,
- rv_mop_r_31 = 909,
- rv_mop_rr_0 = 910,
- rv_mop_rr_1 = 911,
- rv_mop_rr_2 = 912,
- rv_mop_rr_3 = 913,
- rv_mop_rr_4 = 914,
- rv_mop_rr_5 = 915,
- rv_mop_rr_6 = 916,
- rv_mop_rr_7 = 917,
- rv_c_mop_1 = 918,
- rv_c_mop_3 = 919,
- rv_c_mop_5 = 920,
- rv_c_mop_7 = 921,
- rv_c_mop_9 = 922,
- rv_c_mop_11 = 923,
- rv_c_mop_13 = 924,
- rv_c_mop_15 = 925,
- rv_op_amoswap_b = 926,
- rv_op_amoadd_b = 927,
- rv_op_amoxor_b = 928,
- rv_op_amoor_b = 929,
- rv_op_amoand_b = 930,
- rv_op_amomin_b = 931,
- rv_op_amomax_b = 932,
- rv_op_amominu_b = 933,
- rv_op_amomaxu_b = 934,
- rv_op_amoswap_h = 935,
- rv_op_amoadd_h = 936,
- rv_op_amoxor_h = 937,
- rv_op_amoor_h = 938,
- rv_op_amoand_h = 939,
- rv_op_amomin_h = 940,
- rv_op_amomax_h = 941,
- rv_op_amominu_h = 942,
- rv_op_amomaxu_h = 943,
- rv_op_amocas_b = 944,
- rv_op_amocas_h = 945,
- rv_op_wrs_sto = 946,
- rv_op_wrs_nto = 947,
- rv_op_lpad = 948,
- rv_op_sspush = 949,
- rv_op_sspopchk = 950,
- rv_op_ssrdp = 951,
- rv_op_ssamoswap_w = 952,
- rv_op_ssamoswap_d = 953,
- rv_op_c_sspush = 954,
- rv_op_c_sspopchk = 955,
- rv_op_cbo_inval = 956,
- rv_op_cbo_clean = 957,
- rv_op_cbo_flush = 958,
- rv_op_cbo_zero = 959,
- rv_op_mnret = 960,
+#define OP(N, ...) rv_op_##N,
+#include "riscv-op.c.inc"
+#undef OP
} rv_op;
/* register names */
@@ -1601,967 +646,9 @@ static uint32_t operand_lpl(rv_inst inst)
/* instruction metadata */
static const rv_opcode_data rvi_opcode_data[] = {
- { "illegal", rv_codec_none, rv_fmt_none },
- { "lui", rv_codec_u, rv_fmt_rd_uimm },
- { "auipc", rv_codec_u, rv_fmt_rd_uoffset },
- { "jal", rv_codec_uj, rv_fmt_rd_offset, rvcp_jal },
- { "jalr", rv_codec_i, rv_fmt_rd_rs1_offset, rvcp_jalr },
- { "beq", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_beq },
- { "bne", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_bne },
- { "blt", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_blt },
- { "bge", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_bge },
- { "bltu", rv_codec_sb, rv_fmt_rs1_rs2_offset },
- { "bgeu", rv_codec_sb, rv_fmt_rs1_rs2_offset },
- { "lb", rv_codec_i, rv_fmt_rd_offset_rs1 },
- { "lh", rv_codec_i, rv_fmt_rd_offset_rs1 },
- { "lw", rv_codec_i, rv_fmt_rd_offset_rs1 },
- { "lbu", rv_codec_i, rv_fmt_rd_offset_rs1 },
- { "lhu", rv_codec_i, rv_fmt_rd_offset_rs1 },
- { "sb", rv_codec_s, rv_fmt_rs2_offset_rs1 },
- { "sh", rv_codec_s, rv_fmt_rs2_offset_rs1 },
- { "sw", rv_codec_s, rv_fmt_rs2_offset_rs1 },
- { "addi", rv_codec_i, rv_fmt_rd_rs1_imm, rvcp_addi },
- { "slti", rv_codec_i, rv_fmt_rd_rs1_imm },
- { "sltiu", rv_codec_i, rv_fmt_rd_rs1_imm, rvcp_sltiu },
- { "xori", rv_codec_i, rv_fmt_rd_rs1_imm, rvcp_xori },
- { "ori", rv_codec_i, rv_fmt_rd_rs1_imm },
- { "andi", rv_codec_i, rv_fmt_rd_rs1_imm },
- { "slli", rv_codec_i_sh7, rv_fmt_rd_rs1_imm },
- { "srli", rv_codec_i_sh7, rv_fmt_rd_rs1_imm },
- { "srai", rv_codec_i_sh7, rv_fmt_rd_rs1_imm },
- { "add", rv_codec_r, rv_fmt_rd_rs1_rs2 },
- { "sub", rv_codec_r, rv_fmt_rd_rs1_rs2, rvcp_sub },
- { "sll", rv_codec_r, rv_fmt_rd_rs1_rs2 },
- { "slt", rv_codec_r, rv_fmt_rd_rs1_rs2, rvcp_slt },
- { "sltu", rv_codec_r, rv_fmt_rd_rs1_rs2, rvcp_sltu },
- { "xor", rv_codec_r, rv_fmt_rd_rs1_rs2 },
- { "srl", rv_codec_r, rv_fmt_rd_rs1_rs2 },
- { "sra", rv_codec_r, rv_fmt_rd_rs1_rs2 },
- { "or", rv_codec_r, rv_fmt_rd_rs1_rs2 },
- { "and", rv_codec_r, rv_fmt_rd_rs1_rs2 },
- { "fence", rv_codec_r_f, rv_fmt_pred_succ },
- { "fence.i", rv_codec_none, rv_fmt_none },
- { "lwu", rv_codec_i, rv_fmt_rd_offset_rs1 },
- { "ld", rv_codec_i, rv_fmt_rd_offset_rs1 },
- { "sd", rv_codec_s, rv_fmt_rs2_offset_rs1 },
- { "addiw", rv_codec_i, rv_fmt_rd_rs1_imm, rvcp_addiw },
- { "slliw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm },
- { "srliw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm },
- { "sraiw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm },
- { "addw", rv_codec_r, rv_fmt_rd_rs1_rs2 },
- { "subw", rv_codec_r, rv_fmt_rd_rs1_rs2, rvcp_subw },
- { "sllw", rv_codec_r, rv_fmt_rd_rs1_rs2 },
- { "srlw", rv_codec_r, rv_fmt_rd_rs1_rs2 },
- { "sraw", rv_codec_r, rv_fmt_rd_rs1_rs2 },
- { "ldu", rv_codec_i, rv_fmt_rd_offset_rs1 },
- { "lq", rv_codec_i, rv_fmt_rd_offset_rs1 },
- { "sq", rv_codec_s, rv_fmt_rs2_offset_rs1 },
- { "addid", rv_codec_i, rv_fmt_rd_rs1_imm },
- { "sllid", rv_codec_i_sh6, rv_fmt_rd_rs1_imm },
- { "srlid", rv_codec_i_sh6, rv_fmt_rd_rs1_imm },
- { "sraid", rv_codec_i_sh6, rv_fmt_rd_rs1_imm },
- { "addd", rv_codec_r, rv_fmt_rd_rs1_rs2 },
- { "subd", rv_codec_r, rv_fmt_rd_rs1_rs2 },
- { "slld", rv_codec_r, rv_fmt_rd_rs1_rs2 },
- { "srld", rv_codec_r, rv_fmt_rd_rs1_rs2 },
- { "srad", rv_codec_r, rv_fmt_rd_rs1_rs2 },
- { "mul", rv_codec_r, rv_fmt_rd_rs1_rs2 },
- { "mulh", rv_codec_r, rv_fmt_rd_rs1_rs2 },
- { "mulhsu", rv_codec_r, rv_fmt_rd_rs1_rs2 },
- { "mulhu", rv_codec_r, rv_fmt_rd_rs1_rs2 },
- { "div", rv_codec_r, rv_fmt_rd_rs1_rs2 },
- { "divu", rv_codec_r, rv_fmt_rd_rs1_rs2 },
- { "rem", rv_codec_r, rv_fmt_rd_rs1_rs2 },
- { "remu", rv_codec_r, rv_fmt_rd_rs1_rs2 },
- { "mulw", rv_codec_r, rv_fmt_rd_rs1_rs2 },
- { "divw", rv_codec_r, rv_fmt_rd_rs1_rs2 },
- { "divuw", rv_codec_r, rv_fmt_rd_rs1_rs2 },
- { "remw", rv_codec_r, rv_fmt_rd_rs1_rs2 },
- { "remuw", rv_codec_r, rv_fmt_rd_rs1_rs2 },
- { "muld", rv_codec_r, rv_fmt_rd_rs1_rs2 },
- { "divd", rv_codec_r, rv_fmt_rd_rs1_rs2 },
- { "divud", rv_codec_r, rv_fmt_rd_rs1_rs2 },
- { "remd", rv_codec_r, rv_fmt_rd_rs1_rs2 },
- { "remud", rv_codec_r, rv_fmt_rd_rs1_rs2 },
- { "lr.w", rv_codec_r_l, rv_fmt_aqrl_rd_rs1 },
- { "sc.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
- { "amoswap.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
- { "amoadd.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
- { "amoxor.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
- { "amoor.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
- { "amoand.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
- { "amomin.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
- { "amomax.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
- { "amominu.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
- { "amomaxu.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
- { "lr.d", rv_codec_r_l, rv_fmt_aqrl_rd_rs1 },
- { "sc.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
- { "amoswap.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
- { "amoadd.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
- { "amoxor.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
- { "amoor.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
- { "amoand.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
- { "amomin.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
- { "amomax.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
- { "amominu.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
- { "amomaxu.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
- { "lr.q", rv_codec_r_l, rv_fmt_aqrl_rd_rs1 },
- { "sc.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
- { "amoswap.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
- { "amoadd.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
- { "amoxor.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
- { "amoor.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
- { "amoand.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
- { "amomin.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
- { "amomax.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
- { "amominu.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
- { "amomaxu.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
- { "ecall", rv_codec_none, rv_fmt_none },
- { "ebreak", rv_codec_none, rv_fmt_none },
- { "uret", rv_codec_none, rv_fmt_none },
- { "sret", rv_codec_none, rv_fmt_none },
- { "hret", rv_codec_none, rv_fmt_none },
- { "mret", rv_codec_none, rv_fmt_none },
- { "dret", rv_codec_none, rv_fmt_none },
- { "sfence.vm", rv_codec_r, rv_fmt_rs1 },
- { "sfence.vma", rv_codec_r, rv_fmt_rs1_rs2 },
- { "wfi", rv_codec_none, rv_fmt_none },
- { "csrrw", rv_codec_i_csr, rv_fmt_rd_csr_rs1 },
- { "csrrs", rv_codec_i_csr, rv_fmt_rd_csr_rs1 },
- { "csrrc", rv_codec_i_csr, rv_fmt_rd_csr_rs1 },
- { "csrrwi", rv_codec_i_csr, rv_fmt_rd_csr_zimm },
- { "csrrsi", rv_codec_i_csr, rv_fmt_rd_csr_zimm },
- { "csrrci", rv_codec_i_csr, rv_fmt_rd_csr_zimm },
- { "flw", rv_codec_i, rv_fmt_frd_offset_rs1 },
- { "fsw", rv_codec_s, rv_fmt_frs2_offset_rs1 },
- { "fmadd.s", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3 },
- { "fmsub.s", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3 },
- { "fnmsub.s", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3 },
- { "fnmadd.s", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3 },
- { "fadd.s", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2 },
- { "fsub.s", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2 },
- { "fmul.s", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2 },
- { "fdiv.s", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2 },
- { "fsgnj.s", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnj_s },
- { "fsgnjn.s", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjn_s },
- { "fsgnjx.s", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjx_s },
- { "fmin.s", rv_codec_r, rv_fmt_frd_frs1_frs2 },
- { "fmax.s", rv_codec_r, rv_fmt_frd_frs1_frs2 },
- { "fsqrt.s", rv_codec_r_m, rv_fmt_rm_frd_frs1 },
- { "fle.s", rv_codec_r, rv_fmt_rd_frs1_frs2 },
- { "flt.s", rv_codec_r, rv_fmt_rd_frs1_frs2 },
- { "feq.s", rv_codec_r, rv_fmt_rd_frs1_frs2 },
- { "fcvt.w.s", rv_codec_r_m, rv_fmt_rm_rd_frs1 },
- { "fcvt.wu.s", rv_codec_r_m, rv_fmt_rm_rd_frs1 },
- { "fcvt.s.w", rv_codec_r_m, rv_fmt_rm_frd_rs1 },
- { "fcvt.s.wu", rv_codec_r_m, rv_fmt_rm_frd_rs1 },
- { "fmv.x.s", rv_codec_r, rv_fmt_rd_frs1 },
- { "fclass.s", rv_codec_r, rv_fmt_rd_frs1 },
- { "fmv.s.x", rv_codec_r, rv_fmt_frd_rs1 },
- { "fcvt.l.s", rv_codec_r_m, rv_fmt_rm_rd_frs1 },
- { "fcvt.lu.s", rv_codec_r_m, rv_fmt_rm_rd_frs1 },
- { "fcvt.s.l", rv_codec_r_m, rv_fmt_rm_frd_rs1 },
- { "fcvt.s.lu", rv_codec_r_m, rv_fmt_rm_frd_rs1 },
- { "fld", rv_codec_i, rv_fmt_frd_offset_rs1 },
- { "fsd", rv_codec_s, rv_fmt_frs2_offset_rs1 },
- { "fmadd.d", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3 },
- { "fmsub.d", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3 },
- { "fnmsub.d", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3 },
- { "fnmadd.d", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3 },
- { "fadd.d", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2 },
- { "fsub.d", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2 },
- { "fmul.d", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2 },
- { "fdiv.d", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2 },
- { "fsgnj.d", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnj_d },
- { "fsgnjn.d", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjn_d },
- { "fsgnjx.d", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjx_d },
- { "fmin.d", rv_codec_r, rv_fmt_frd_frs1_frs2 },
- { "fmax.d", rv_codec_r, rv_fmt_frd_frs1_frs2 },
- { "fcvt.s.d", rv_codec_r_m, rv_fmt_rm_frd_frs1 },
- { "fcvt.d.s", rv_codec_r_m, rv_fmt_rm_frd_frs1 },
- { "fsqrt.d", rv_codec_r_m, rv_fmt_rm_frd_frs1 },
- { "fle.d", rv_codec_r, rv_fmt_rd_frs1_frs2 },
- { "flt.d", rv_codec_r, rv_fmt_rd_frs1_frs2 },
- { "feq.d", rv_codec_r, rv_fmt_rd_frs1_frs2 },
- { "fcvt.w.d", rv_codec_r_m, rv_fmt_rm_rd_frs1 },
- { "fcvt.wu.d", rv_codec_r_m, rv_fmt_rm_rd_frs1 },
- { "fcvt.d.w", rv_codec_r_m, rv_fmt_rm_frd_rs1 },
- { "fcvt.d.wu", rv_codec_r_m, rv_fmt_rm_frd_rs1 },
- { "fclass.d", rv_codec_r, rv_fmt_rd_frs1 },
- { "fcvt.l.d", rv_codec_r_m, rv_fmt_rm_rd_frs1 },
- { "fcvt.lu.d", rv_codec_r_m, rv_fmt_rm_rd_frs1 },
- { "fmv.x.d", rv_codec_r, rv_fmt_rd_frs1 },
- { "fcvt.d.l", rv_codec_r_m, rv_fmt_rm_frd_rs1 },
- { "fcvt.d.lu", rv_codec_r_m, rv_fmt_rm_frd_rs1 },
- { "fmv.d.x", rv_codec_r, rv_fmt_frd_rs1 },
- { "flq", rv_codec_i, rv_fmt_frd_offset_rs1 },
- { "fsq", rv_codec_s, rv_fmt_frs2_offset_rs1 },
- { "fmadd.q", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3 },
- { "fmsub.q", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3 },
- { "fnmsub.q", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3 },
- { "fnmadd.q", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3 },
- { "fadd.q", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2 },
- { "fsub.q", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2 },
- { "fmul.q", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2 },
- { "fdiv.q", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2 },
- { "fsgnj.q", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnj_q },
- { "fsgnjn.q", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjn_q },
- { "fsgnjx.q", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjx_q },
- { "fmin.q", rv_codec_r, rv_fmt_frd_frs1_frs2 },
- { "fmax.q", rv_codec_r, rv_fmt_frd_frs1_frs2 },
- { "fcvt.s.q", rv_codec_r_m, rv_fmt_rm_frd_frs1 },
- { "fcvt.q.s", rv_codec_r_m, rv_fmt_rm_frd_frs1 },
- { "fcvt.d.q", rv_codec_r_m, rv_fmt_rm_frd_frs1 },
- { "fcvt.q.d", rv_codec_r_m, rv_fmt_rm_frd_frs1 },
- { "fsqrt.q", rv_codec_r_m, rv_fmt_rm_frd_frs1 },
- { "fle.q", rv_codec_r, rv_fmt_rd_frs1_frs2 },
- { "flt.q", rv_codec_r, rv_fmt_rd_frs1_frs2 },
- { "feq.q", rv_codec_r, rv_fmt_rd_frs1_frs2 },
- { "fcvt.w.q", rv_codec_r_m, rv_fmt_rm_rd_frs1 },
- { "fcvt.wu.q", rv_codec_r_m, rv_fmt_rm_rd_frs1 },
- { "fcvt.q.w", rv_codec_r_m, rv_fmt_rm_frd_rs1 },
- { "fcvt.q.wu", rv_codec_r_m, rv_fmt_rm_frd_rs1 },
- { "fclass.q", rv_codec_r, rv_fmt_rd_frs1 },
- { "fcvt.l.q", rv_codec_r_m, rv_fmt_rm_rd_frs1 },
- { "fcvt.lu.q", rv_codec_r_m, rv_fmt_rm_rd_frs1 },
- { "fcvt.q.l", rv_codec_r_m, rv_fmt_rm_frd_rs1 },
- { "fcvt.q.lu", rv_codec_r_m, rv_fmt_rm_frd_rs1 },
- { "fmv.x.q", rv_codec_r, rv_fmt_rd_frs1 },
- { "fmv.q.x", rv_codec_r, rv_fmt_frd_rs1 },
- { "c.addi4spn", rv_codec_ciw_4spn, NULL, DECOMP(rv_op_addi) },
- { "c.fld", rv_codec_cl_ld, NULL, DECOMP(rv_op_fld) },
- { "c.lw", rv_codec_cl_lw, NULL, DECOMP(rv_op_lw) },
- { "c.flw", rv_codec_cl_lw, NULL, DECOMP(rv_op_flw) },
- { "c.fsd", rv_codec_cs_sd, NULL, DECOMP(rv_op_fsd) },
- { "c.sw", rv_codec_cs_sw, NULL, DECOMP(rv_op_sw) },
- { "c.fsw", rv_codec_cs_sw, NULL, DECOMP(rv_op_fsw) },
- { },
- { "c.addi", rv_codec_ci, NULL, DECOMP(rv_op_addi) },
- { "c.jal", rv_codec_cj_jal, NULL, DECOMP(rv_op_jal) },
- { "c.li", rv_codec_ci_li, NULL, DECOMP(rv_op_addi) },
- { "c.addi16sp", rv_codec_ci_16sp, NULL, DECOMP(rv_op_addi) },
- { "c.lui", rv_codec_ci_lui, NULL, DECOMP(rv_op_lui) },
- { "c.srli", rv_codec_cb_sh6, NULL, DECOMP(rv_op_srli) },
- { "c.srai", rv_codec_cb_sh6, NULL, DECOMP(rv_op_srai) },
- { "c.andi", rv_codec_cb_imm, NULL, DECOMP(rv_op_andi) },
- { "c.sub", rv_codec_cs, NULL, DECOMP(rv_op_sub) },
- { "c.xor", rv_codec_cs, NULL, DECOMP(rv_op_xor) },
- { "c.or", rv_codec_cs, NULL, DECOMP(rv_op_or) },
- { "c.and", rv_codec_cs, NULL, DECOMP(rv_op_and) },
- { "c.subw", rv_codec_cs, NULL, DECOMP(rv_op_subw) },
- { "c.addw", rv_codec_cs, NULL, DECOMP(rv_op_addw) },
- { "c.j", rv_codec_cj, NULL, DECOMP(rv_op_j) },
- { "c.beqz", rv_codec_cb, NULL, DECOMP(rv_op_beqz) },
- { "c.bnez", rv_codec_cb, NULL, DECOMP(rv_op_bnez) },
- { "c.slli", rv_codec_ci_sh6, NULL, DECOMP(rv_op_slli) },
- { "c.fldsp", rv_codec_ci_ldsp, NULL, DECOMP(rv_op_fld) },
- { "c.lwsp", rv_codec_ci_lwsp, NULL, DECOMP(rv_op_lw) },
- { "c.flwsp", rv_codec_ci_lwsp, NULL, DECOMP(rv_op_flw) },
- { "c.jr", rv_codec_cr_jr, NULL, DECOMP(rv_op_jr) },
- { "c.mv", rv_codec_cr_mv, NULL, DECOMP(rv_op_mv) },
- { "c.ebreak", rv_codec_ci_none, NULL, DECOMP(rv_op_ebreak) },
- { "c.jalr", rv_codec_cr_jalr, NULL, DECOMP(rv_op_jalr) },
- { "c.add", rv_codec_cr, NULL, DECOMP(rv_op_add) },
- { "c.fsdsp", rv_codec_css_sdsp, NULL, DECOMP(rv_op_fsd) },
- { "c.swsp", rv_codec_css_swsp, NULL, DECOMP(rv_op_sw) },
- { "c.fswsp", rv_codec_css_swsp, NULL, DECOMP(rv_op_fsw) },
- { "c.ld", rv_codec_cl_ld, NULL, DECOMP(rv_op_ld) },
- { "c.sd", rv_codec_cs_sd, NULL, DECOMP(rv_op_sd) },
- { "c.addiw", rv_codec_ci, NULL, DECOMP(rv_op_addiw) },
- { "c.ldsp", rv_codec_ci_ldsp, NULL, DECOMP(rv_op_ld) },
- { "c.sdsp", rv_codec_css_sdsp, NULL, DECOMP(rv_op_sd) },
- { "c.lq", rv_codec_cl_lq, NULL, DECOMP(rv_op_lq) },
- { "c.sq", rv_codec_cs_sq, NULL, DECOMP(rv_op_sq) },
- { "c.lqsp", rv_codec_ci_lqsp, NULL, DECOMP(rv_op_lq) },
- { "c.sqsp", rv_codec_css_sqsp, NULL, DECOMP(rv_op_sq) },
- { "nop", rv_codec_illegal, rv_fmt_none },
- { "mv", rv_codec_illegal, rv_fmt_rd_rs1, rvcp_mv },
- { "not", rv_codec_illegal, rv_fmt_rd_rs1 },
- { "neg", rv_codec_illegal, rv_fmt_rd_rs2 },
- { "negw", rv_codec_illegal, rv_fmt_rd_rs2 },
- { "sext.w", rv_codec_illegal, rv_fmt_rd_rs1 },
- { "seqz", rv_codec_illegal, rv_fmt_rd_rs1 },
- { "snez", rv_codec_illegal, rv_fmt_rd_rs2 },
- { "sltz", rv_codec_illegal, rv_fmt_rd_rs1 },
- { "sgtz", rv_codec_illegal, rv_fmt_rd_rs2 },
- { "fmv.s", rv_codec_illegal, rv_fmt_frd_frs1 },
- { "fabs.s", rv_codec_illegal, rv_fmt_frd_frs1 },
- { "fneg.s", rv_codec_illegal, rv_fmt_frd_frs1 },
- { "fmv.d", rv_codec_illegal, rv_fmt_frd_frs1 },
- { "fabs.d", rv_codec_illegal, rv_fmt_frd_frs1 },
- { "fneg.d", rv_codec_illegal, rv_fmt_frd_frs1 },
- { "fmv.q", rv_codec_illegal, rv_fmt_frd_frs1 },
- { "fabs.q", rv_codec_illegal, rv_fmt_frd_frs1 },
- { "fneg.q", rv_codec_illegal, rv_fmt_frd_frs1 },
- { "beqz", rv_codec_illegal, rv_fmt_rs1_offset },
- { "bnez", rv_codec_illegal, rv_fmt_rs1_offset },
- { "blez", rv_codec_illegal, rv_fmt_rs2_offset },
- { "bgez", rv_codec_illegal, rv_fmt_rs1_offset },
- { "bltz", rv_codec_illegal, rv_fmt_rs1_offset },
- { "bgtz", rv_codec_illegal, rv_fmt_rs2_offset },
- { "jal", rv_codec_illegal, rv_fmt_offset }, /* rv_op_jal_ra */
- { "jalr", rv_codec_illegal, rv_fmt_rs1 }, /* rv_op_jalr_ra */
- { },
- { },
- { "j", rv_codec_illegal, rv_fmt_offset },
- { "ret", rv_codec_illegal, rv_fmt_none },
- { "jr", rv_codec_illegal, rv_fmt_rs1, rvcp_jr },
- { "rdcycle", rv_codec_i_csr, rv_fmt_rd },
- { "rdtime", rv_codec_i_csr, rv_fmt_rd },
- { "rdinstret", rv_codec_i_csr, rv_fmt_rd },
- { "rdcycleh", rv_codec_i_csr, rv_fmt_rd },
- { "rdtimeh", rv_codec_i_csr, rv_fmt_rd },
- { "rdinstreth", rv_codec_i_csr, rv_fmt_rd },
- { "frcsr", rv_codec_i_csr, rv_fmt_rd },
- { "frrm", rv_codec_i_csr, rv_fmt_rd },
- { "frflags", rv_codec_i_csr, rv_fmt_rd },
- { "fscsr", rv_codec_i_csr, rv_fmt_rd_rs1 },
- { "fsrm", rv_codec_i_csr, rv_fmt_rd_rs1 },
- { "fsflags", rv_codec_i_csr, rv_fmt_rd_rs1 },
- { "fsrmi", rv_codec_i_csr, rv_fmt_rd_zimm },
- { "fsflagsi", rv_codec_i_csr, rv_fmt_rd_zimm },
- { "bseti", rv_codec_i_sh7, rv_fmt_rd_rs1_imm },
- { "bclri", rv_codec_i_sh7, rv_fmt_rd_rs1_imm },
- { "binvi", rv_codec_i_sh7, rv_fmt_rd_rs1_imm },
- { "bexti", rv_codec_i_sh7, rv_fmt_rd_rs1_imm },
- { "rori", rv_codec_i_sh7, rv_fmt_rd_rs1_imm },
- { "clz", rv_codec_r, rv_fmt_rd_rs1 },
- { "ctz", rv_codec_r, rv_fmt_rd_rs1 },
- { "cpop", rv_codec_r, rv_fmt_rd_rs1 },
- { "sext.h", rv_codec_r, rv_fmt_rd_rs1 },
- { "sext.b", rv_codec_r, rv_fmt_rd_rs1 },
- { "xnor", rv_codec_r, rv_fmt_rd_rs1_rs2 },
- { "orn", rv_codec_r, rv_fmt_rd_rs1_rs2 },
- { "andn", rv_codec_r, rv_fmt_rd_rs1_rs2 },
- { "rol", rv_codec_r, rv_fmt_rd_rs1_rs2 },
- { "ror", rv_codec_r, rv_fmt_rd_rs1_rs2 },
- { "sh1add", rv_codec_r, rv_fmt_rd_rs1_rs2 },
- { "sh2add", rv_codec_r, rv_fmt_rd_rs1_rs2 },
- { "sh3add", rv_codec_r, rv_fmt_rd_rs1_rs2 },
- { "sh1add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2 },
- { "sh2add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2 },
- { "sh3add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2 },
- { "clmul", rv_codec_r, rv_fmt_rd_rs1_rs2 },
- { "clmulr", rv_codec_r, rv_fmt_rd_rs1_rs2 },
- { "clmulh", rv_codec_r, rv_fmt_rd_rs1_rs2 },
- { "min", rv_codec_r, rv_fmt_rd_rs1_rs2 },
- { "minu", rv_codec_r, rv_fmt_rd_rs1_rs2 },
- { "max", rv_codec_r, rv_fmt_rd_rs1_rs2 },
- { "maxu", rv_codec_r, rv_fmt_rd_rs1_rs2 },
- { "clzw", rv_codec_r, rv_fmt_rd_rs1 },
- { "ctzw", rv_codec_r, rv_fmt_rd_rs1 },
- { "cpopw", rv_codec_r, rv_fmt_rd_rs1 },
- { "slli.uw", rv_codec_i_sh6, rv_fmt_rd_rs1_imm },
- { "add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2 },
- { "rolw", rv_codec_r, rv_fmt_rd_rs1_rs2 },
- { "rorw", rv_codec_r, rv_fmt_rd_rs1_rs2 },
- { "rev8", rv_codec_r, rv_fmt_rd_rs1 },
- { "zext.h", rv_codec_r, rv_fmt_rd_rs1 },
- { "roriw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm },
- { "orc.b", rv_codec_r, rv_fmt_rd_rs1 },
- { "bset", rv_codec_r, rv_fmt_rd_rs1_rs2 },
- { "bclr", rv_codec_r, rv_fmt_rd_rs1_rs2 },
- { "binv", rv_codec_r, rv_fmt_rd_rs1_rs2 },
- { "bext", rv_codec_r, rv_fmt_rd_rs1_rs2 },
- { "aes32esmi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs },
- { "aes32esi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs },
- { "aes32dsmi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs },
- { "aes32dsi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs },
- { "aes64ks1i", rv_codec_k_rnum, rv_fmt_rd_rs1_rnum },
- { "aes64ks2", rv_codec_r, rv_fmt_rd_rs1_rs2 },
- { "aes64im", rv_codec_r, rv_fmt_rd_rs1 },
- { "aes64esm", rv_codec_r, rv_fmt_rd_rs1_rs2 },
- { "aes64es", rv_codec_r, rv_fmt_rd_rs1_rs2 },
- { "aes64dsm", rv_codec_r, rv_fmt_rd_rs1_rs2 },
- { "aes64ds", rv_codec_r, rv_fmt_rd_rs1_rs2 },
- { "sha256sig0", rv_codec_r, rv_fmt_rd_rs1 },
- { "sha256sig1", rv_codec_r, rv_fmt_rd_rs1 },
- { "sha256sum0", rv_codec_r, rv_fmt_rd_rs1 },
- { "sha256sum1", rv_codec_r, rv_fmt_rd_rs1 },
- { "sha512sig0", rv_codec_r, rv_fmt_rd_rs1_rs2 },
- { "sha512sig1", rv_codec_r, rv_fmt_rd_rs1_rs2 },
- { "sha512sum0", rv_codec_r, rv_fmt_rd_rs1_rs2 },
- { "sha512sum1", rv_codec_r, rv_fmt_rd_rs1_rs2 },
- { "sha512sum0r", rv_codec_r, rv_fmt_rd_rs1_rs2 },
- { "sha512sum1r", rv_codec_r, rv_fmt_rd_rs1_rs2 },
- { "sha512sig0l", rv_codec_r, rv_fmt_rd_rs1_rs2 },
- { "sha512sig0h", rv_codec_r, rv_fmt_rd_rs1_rs2 },
- { "sha512sig1l", rv_codec_r, rv_fmt_rd_rs1_rs2 },
- { "sha512sig1h", rv_codec_r, rv_fmt_rd_rs1_rs2 },
- { "sm3p0", rv_codec_r, rv_fmt_rd_rs1 },
- { "sm3p1", rv_codec_r, rv_fmt_rd_rs1 },
- { "sm4ed", rv_codec_k_bs, rv_fmt_rs1_rs2_bs },
- { "sm4ks", rv_codec_k_bs, rv_fmt_rs1_rs2_bs },
- { "brev8", rv_codec_r, rv_fmt_rd_rs1 },
- { "pack", rv_codec_r, rv_fmt_rd_rs1_rs2 },
- { "packh", rv_codec_r, rv_fmt_rd_rs1_rs2 },
- { "packw", rv_codec_r, rv_fmt_rd_rs1_rs2 },
- { "unzip", rv_codec_r, rv_fmt_rd_rs1 },
- { "zip", rv_codec_r, rv_fmt_rd_rs1 },
- { "xperm4", rv_codec_r, rv_fmt_rd_rs1_rs2 },
- { "xperm8", rv_codec_r, rv_fmt_rd_rs1 },
- { "vle8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
- { "vle16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
- { "vle32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
- { "vle64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
- { "vse8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
- { "vse16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
- { "vse32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
- { "vse64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
- { "vlm.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
- { "vsm.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
- { "vlse8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm },
- { "vlse16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm },
- { "vlse32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm },
- { "vlse64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm },
- { "vsse8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm },
- { "vsse16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm },
- { "vsse32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm },
- { "vsse64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm },
- { "vluxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm },
- { "vluxei16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm },
- { "vluxei32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm },
- { "vluxei64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm },
- { "vloxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm },
- { "vloxei16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm },
- { "vloxei32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm },
- { "vloxei64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm },
- { "vsuxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm },
- { "vsuxei16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm },
- { "vsuxei32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm },
- { "vsuxei64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm },
- { "vsoxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm },
- { "vsoxei16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm },
- { "vsoxei32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm },
- { "vsoxei64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm },
- { "vle8ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
- { "vle16ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
- { "vle32ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
- { "vle64ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
- { "vl1re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
- { "vl1re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
- { "vl1re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
- { "vl1re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
- { "vl2re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
- { "vl2re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
- { "vl2re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
- { "vl2re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
- { "vl4re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
- { "vl4re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
- { "vl4re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
- { "vl4re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
- { "vl8re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
- { "vl8re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
- { "vl8re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
- { "vl8re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
- { "vs1r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
- { "vs2r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
- { "vs4r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
- { "vs8r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
- { "vadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
- { "vadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
- { "vadd.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm },
- { "vsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
- { "vsub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
- { "vrsub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
- { "vrsub.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm },
- { "vwaddu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
- { "vwaddu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
- { "vwadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
- { "vwadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
- { "vwsubu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
- { "vwsubu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
- { "vwsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
- { "vwsub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
- { "vwaddu.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
- { "vwaddu.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
- { "vwadd.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
- { "vwadd.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
- { "vwsubu.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
- { "vwsubu.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
- { "vwsub.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
- { "vwsub.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
- { "vadc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl },
- { "vadc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl },
- { "vadc.vim", rv_codec_v_i, rv_fmt_vd_vs2_imm_vl },
- { "vmadc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl },
- { "vmadc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl },
- { "vmadc.vim", rv_codec_v_i, rv_fmt_vd_vs2_imm_vl },
- { "vsbc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl },
- { "vsbc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl },
- { "vmsbc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl },
- { "vmsbc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl },
- { "vand.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
- { "vand.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
- { "vand.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm },
- { "vor.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
- { "vor.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
- { "vor.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm },
- { "vxor.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
- { "vxor.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
- { "vxor.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm },
- { "vsll.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
- { "vsll.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
- { "vsll.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm },
- { "vsrl.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
- { "vsrl.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
- { "vsrl.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm },
- { "vsra.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
- { "vsra.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
- { "vsra.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm },
- { "vnsrl.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
- { "vnsrl.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
- { "vnsrl.wi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm },
- { "vnsra.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
- { "vnsra.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
- { "vnsra.wi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm },
- { "vmseq.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
- { "vmseq.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
- { "vmseq.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm },
- { "vmsne.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
- { "vmsne.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
- { "vmsne.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm },
- { "vmsltu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
- { "vmsltu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
- { "vmslt.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
- { "vmslt.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
- { "vmsleu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
- { "vmsleu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
- { "vmsleu.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm },
- { "vmsle.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
- { "vmsle.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
- { "vmsle.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm },
- { "vmsgtu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
- { "vmsgtu.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm },
- { "vmsgt.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
- { "vmsgt.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm },
- { "vminu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
- { "vminu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
- { "vmin.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
- { "vmin.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
- { "vmaxu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
- { "vmaxu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
- { "vmax.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
- { "vmax.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
- { "vmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
- { "vmul.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
- { "vmulh.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
- { "vmulh.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
- { "vmulhu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
- { "vmulhu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
- { "vmulhsu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
- { "vmulhsu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
- { "vdivu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
- { "vdivu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
- { "vdiv.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
- { "vdiv.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
- { "vremu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
- { "vremu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
- { "vrem.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
- { "vrem.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
- { "vwmulu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
- { "vwmulu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
- { "vwmulsu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
- { "vwmulsu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
- { "vwmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
- { "vwmul.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
- { "vmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm },
- { "vmacc.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm },
- { "vnmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm },
- { "vnmsac.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm },
- { "vmadd.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm },
- { "vmadd.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm },
- { "vnmsub.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm },
- { "vnmsub.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm },
- { "vwmaccu.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm },
- { "vwmaccu.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm },
- { "vwmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm },
- { "vwmacc.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm },
- { "vwmaccsu.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm },
- { "vwmaccsu.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm },
- { "vwmaccus.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm },
- { "vmv.v.v", rv_codec_v_r, rv_fmt_vd_vs1 },
- { "vmv.v.x", rv_codec_v_r, rv_fmt_vd_rs1 },
- { "vmv.v.i", rv_codec_v_i, rv_fmt_vd_imm },
- { "vmerge.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl },
- { "vmerge.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl },
- { "vmerge.vim", rv_codec_v_i, rv_fmt_vd_vs2_imm_vl },
- { "vsaddu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
- { "vsaddu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
- { "vsaddu.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm },
- { "vsadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
- { "vsadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
- { "vsadd.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm },
- { "vssubu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
- { "vssubu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
- { "vssub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
- { "vssub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
- { "vaadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
- { "vaadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
- { "vaaddu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
- { "vaaddu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
- { "vasub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
- { "vasub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
- { "vasubu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
- { "vasubu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
- { "vsmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
- { "vsmul.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
- { "vssrl.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
- { "vssrl.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
- { "vssrl.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm },
- { "vssra.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
- { "vssra.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
- { "vssra.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm },
- { "vnclipu.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
- { "vnclipu.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
- { "vnclipu.wi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm },
- { "vnclip.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
- { "vnclip.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
- { "vnclip.wi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm },
- { "vfadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
- { "vfadd.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm },
- { "vfsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
- { "vfsub.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm },
- { "vfrsub.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm },
- { "vfwadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
- { "vfwadd.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm },
- { "vfwadd.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
- { "vfwadd.wf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm },
- { "vfwsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
- { "vfwsub.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm },
- { "vfwsub.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
- { "vfwsub.wf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm },
- { "vfmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
- { "vfmul.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm },
- { "vfdiv.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
- { "vfdiv.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm },
- { "vfrdiv.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm },
- { "vfwmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
- { "vfwmul.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm },
- { "vfmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm },
- { "vfmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm },
- { "vfnmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm },
- { "vfnmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm },
- { "vfmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm },
- { "vfmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm },
- { "vfnmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm },
- { "vfnmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm },
- { "vfmadd.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm },
- { "vfmadd.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm },
- { "vfnmadd.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm },
- { "vfnmadd.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm },
- { "vfmsub.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm },
- { "vfmsub.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm },
- { "vfnmsub.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm },
- { "vfnmsub.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm },
- { "vfwmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm },
- { "vfwmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm },
- { "vfwnmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm },
- { "vfwnmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm },
- { "vfwmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm },
- { "vfwmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm },
- { "vfwnmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm },
- { "vfwnmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm },
- { "vfsqrt.v", rv_codec_v_r, rv_fmt_vd_vs2 },
- { "vfrsqrt7.v", rv_codec_v_r, rv_fmt_vd_vs2 },
- { "vfrec7.v", rv_codec_v_r, rv_fmt_vd_vs2 },
- { "vfmin.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
- { "vfmin.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm },
- { "vfmax.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
- { "vfmax.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm },
- { "vfsgnj.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
- { "vfsgnj.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm },
- { "vfsgnjn.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
- { "vfsgnjn.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm },
- { "vfsgnjx.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
- { "vfsgnjx.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm },
- { "vfslide1up.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm },
- { "vfslide1down.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm },
- { "vmfeq.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
- { "vmfeq.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm },
- { "vmfne.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
- { "vmfne.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm },
- { "vmflt.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
- { "vmflt.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm },
- { "vmfle.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
- { "vmfle.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm },
- { "vmfgt.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm },
- { "vmfge.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm },
- { "vfclass.v", rv_codec_v_r, rv_fmt_vd_vs2_vm },
- { "vfmerge.vfm", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vl },
- { "vfmv.v.f", rv_codec_v_r, rv_fmt_vd_fs1 },
- { "vfcvt.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm },
- { "vfcvt.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm },
- { "vfcvt.f.xu.v", rv_codec_v_r, rv_fmt_vd_vs2_vm },
- { "vfcvt.f.x.v", rv_codec_v_r, rv_fmt_vd_vs2_vm },
- { "vfcvt.rtz.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm },
- { "vfcvt.rtz.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm },
- { "vfwcvt.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm },
- { "vfwcvt.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm },
- { "vfwcvt.f.xu.v", rv_codec_v_r, rv_fmt_vd_vs2_vm },
- { "vfwcvt.f.x.v", rv_codec_v_r, rv_fmt_vd_vs2_vm },
- { "vfwcvt.f.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm },
- { "vfwcvt.rtz.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm },
- { "vfwcvt.rtz.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm },
- { "vfncvt.xu.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm },
- { "vfncvt.x.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm },
- { "vfncvt.f.xu.w", rv_codec_v_r, rv_fmt_vd_vs2_vm },
- { "vfncvt.f.x.w", rv_codec_v_r, rv_fmt_vd_vs2_vm },
- { "vfncvt.f.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm },
- { "vfncvt.rod.f.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm },
- { "vfncvt.rtz.xu.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm },
- { "vfncvt.rtz.x.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm },
- { "vredsum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
- { "vredand.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
- { "vredor.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
- { "vredxor.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
- { "vredminu.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
- { "vredmin.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
- { "vredmaxu.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
- { "vredmax.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
- { "vwredsumu.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
- { "vwredsum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
- { "vfredusum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
- { "vfredosum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
- { "vfredmin.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
- { "vfredmax.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
- { "vfwredusum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
- { "vfwredosum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
- { "vmand.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
- { "vmnand.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
- { "vmandn.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
- { "vmxor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
- { "vmor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
- { "vmnor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
- { "vmorn.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
- { "vmxnor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
- { "vcpop.m", rv_codec_v_r, rv_fmt_rd_vs2_vm },
- { "vfirst.m", rv_codec_v_r, rv_fmt_rd_vs2_vm },
- { "vmsbf.m", rv_codec_v_r, rv_fmt_vd_vs2_vm },
- { "vmsif.m", rv_codec_v_r, rv_fmt_vd_vs2_vm },
- { "vmsof.m", rv_codec_v_r, rv_fmt_vd_vs2_vm },
- { "viota.m", rv_codec_v_r, rv_fmt_vd_vs2_vm },
- { "vid.v", rv_codec_v_r, rv_fmt_vd_vm },
- { "vmv.x.s", rv_codec_v_r, rv_fmt_rd_vs2 },
- { "vmv.s.x", rv_codec_v_r, rv_fmt_vd_rs1 },
- { "vfmv.f.s", rv_codec_v_r, rv_fmt_fd_vs2 },
- { "vfmv.s.f", rv_codec_v_r, rv_fmt_vd_fs1 },
- { "vslideup.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
- { "vslideup.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm },
- { "vslide1up.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
- { "vslidedown.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
- { "vslidedown.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm },
- { "vslide1down.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
- { "vrgather.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
- { "vrgatherei16.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
- { "vrgather.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
- { "vrgather.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm },
- { "vcompress.vm", rv_codec_v_r, rv_fmt_vd_vs2_vs1 },
- { "vmv1r.v", rv_codec_v_r, rv_fmt_vd_vs2 },
- { "vmv2r.v", rv_codec_v_r, rv_fmt_vd_vs2 },
- { "vmv4r.v", rv_codec_v_r, rv_fmt_vd_vs2 },
- { "vmv8r.v", rv_codec_v_r, rv_fmt_vd_vs2 },
- { "vzext.vf2", rv_codec_v_r, rv_fmt_vd_vs2_vm },
- { "vzext.vf4", rv_codec_v_r, rv_fmt_vd_vs2_vm },
- { "vzext.vf8", rv_codec_v_r, rv_fmt_vd_vs2_vm },
- { "vsext.vf2", rv_codec_v_r, rv_fmt_vd_vs2_vm },
- { "vsext.vf4", rv_codec_v_r, rv_fmt_vd_vs2_vm },
- { "vsext.vf8", rv_codec_v_r, rv_fmt_vd_vs2_vm },
- { "vsetvli", rv_codec_vsetvli, rv_fmt_vsetvli },
- { "vsetivli", rv_codec_vsetivli, rv_fmt_vsetivli },
- { "vsetvl", rv_codec_r, rv_fmt_rd_rs1_rs2 },
- { "c.zext.b", rv_codec_zcb_ext, rv_fmt_rd },
- { "c.sext.b", rv_codec_zcb_ext, rv_fmt_rd },
- { "c.zext.h", rv_codec_zcb_ext, rv_fmt_rd },
- { "c.sext.h", rv_codec_zcb_ext, rv_fmt_rd },
- { "c.zext.w", rv_codec_zcb_ext, rv_fmt_rd },
- { "c.not", rv_codec_zcb_ext, rv_fmt_rd },
- { "c.mul", rv_codec_zcb_mul, rv_fmt_rd_rs2 },
- { "c.lbu", rv_codec_zcb_lb, rv_fmt_rs1_rs2_zce_ldst },
- { "c.lhu", rv_codec_zcb_lh, rv_fmt_rs1_rs2_zce_ldst },
- { "c.lh", rv_codec_zcb_lh, rv_fmt_rs1_rs2_zce_ldst },
- { "c.sb", rv_codec_zcb_lb, rv_fmt_rs1_rs2_zce_ldst },
- { "c.sh", rv_codec_zcb_lh, rv_fmt_rs1_rs2_zce_ldst },
- { "cm.push", rv_codec_zcmp_cm_pushpop, rv_fmt_push_rlist },
- { "cm.pop", rv_codec_zcmp_cm_pushpop, rv_fmt_pop_rlist },
- { "cm.popret", rv_codec_zcmp_cm_pushpop, rv_fmt_pop_rlist },
- { "cm.popretz", rv_codec_zcmp_cm_pushpop, rv_fmt_pop_rlist },
- { "cm.mva01s", rv_codec_zcmp_cm_mv, rv_fmt_rd_rs2 },
- { "cm.mvsa01", rv_codec_zcmp_cm_mv, rv_fmt_rd_rs2 },
- { "cm.jt", rv_codec_zcmt_jt, rv_fmt_zcmt_index },
- { "cm.jalt", rv_codec_zcmt_jt, rv_fmt_zcmt_index },
- { "czero.eqz", rv_codec_r, rv_fmt_rd_rs1_rs2 },
- { "czero.nez", rv_codec_r, rv_fmt_rd_rs1_rs2 },
- { "fcvt.bf16.s", rv_codec_r_m, rv_fmt_rm_frd_frs1 },
- { "fcvt.s.bf16", rv_codec_r_m, rv_fmt_rm_frd_frs1 },
- { "vfncvtbf16.f.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm },
- { "vfwcvtbf16.f.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm },
- { "vfwmaccbf16.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm },
- { "vfwmaccbf16.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm },
- { "flh", rv_codec_i, rv_fmt_frd_offset_rs1 },
- { "fsh", rv_codec_s, rv_fmt_frs2_offset_rs1 },
- { "fmv.h.x", rv_codec_r, rv_fmt_frd_rs1 },
- { "fmv.x.h", rv_codec_r, rv_fmt_rd_frs1 },
- { "fli.s", rv_codec_fli, rv_fmt_fli },
- { "fli.d", rv_codec_fli, rv_fmt_fli },
- { "fli.q", rv_codec_fli, rv_fmt_fli },
- { "fli.h", rv_codec_fli, rv_fmt_fli },
- { "fminm.s", rv_codec_r, rv_fmt_frd_frs1_frs2 },
- { "fmaxm.s", rv_codec_r, rv_fmt_frd_frs1_frs2 },
- { "fminm.d", rv_codec_r, rv_fmt_frd_frs1_frs2 },
- { "fmaxm.d", rv_codec_r, rv_fmt_frd_frs1_frs2 },
- { "fminm.q", rv_codec_r, rv_fmt_frd_frs1_frs2 },
- { "fmaxm.q", rv_codec_r, rv_fmt_frd_frs1_frs2 },
- { "fminm.h", rv_codec_r, rv_fmt_frd_frs1_frs2 },
- { "fmaxm.h", rv_codec_r, rv_fmt_frd_frs1_frs2 },
- { "fround.s", rv_codec_r_m, rv_fmt_rm_frd_frs1 },
- { "froundnx.s", rv_codec_r_m, rv_fmt_rm_frd_frs1 },
- { "fround.d", rv_codec_r_m, rv_fmt_rm_frd_frs1 },
- { "froundnx.d", rv_codec_r_m, rv_fmt_rm_frd_frs1 },
- { "fround.q", rv_codec_r_m, rv_fmt_rm_frd_frs1 },
- { "froundnx.q", rv_codec_r_m, rv_fmt_rm_frd_frs1 },
- { "fround.h", rv_codec_r_m, rv_fmt_rm_frd_frs1 },
- { "froundnx.h", rv_codec_r_m, rv_fmt_rm_frd_frs1 },
- { "fcvtmod.w.d", rv_codec_r_m, rv_fmt_rm_rd_frs1 },
- { "fmvh.x.d", rv_codec_r, rv_fmt_rd_frs1 },
- { "fmvp.d.x", rv_codec_r, rv_fmt_frd_rs1_rs2 },
- { "fmvh.x.q", rv_codec_r, rv_fmt_rd_frs1 },
- { "fmvp.q.x", rv_codec_r, rv_fmt_frd_rs1_rs2 },
- { "fleq.s", rv_codec_r, rv_fmt_rd_frs1_frs2 },
- { "fltq.s", rv_codec_r, rv_fmt_rd_frs1_frs2 },
- { "fleq.d", rv_codec_r, rv_fmt_rd_frs1_frs2 },
- { "fltq.d", rv_codec_r, rv_fmt_rd_frs1_frs2 },
- { "fleq.q", rv_codec_r, rv_fmt_rd_frs1_frs2 },
- { "fltq.q", rv_codec_r, rv_fmt_rd_frs1_frs2 },
- { "fleq.h", rv_codec_r, rv_fmt_rd_frs1_frs2 },
- { "fltq.h", rv_codec_r, rv_fmt_rd_frs1_frs2 },
- { "vaesdf.vv", rv_codec_v_r, rv_fmt_vd_vs2 },
- { "vaesdf.vs", rv_codec_v_r, rv_fmt_vd_vs2 },
- { "vaesdm.vv", rv_codec_v_r, rv_fmt_vd_vs2 },
- { "vaesdm.vs", rv_codec_v_r, rv_fmt_vd_vs2 },
- { "vaesef.vv", rv_codec_v_r, rv_fmt_vd_vs2 },
- { "vaesef.vs", rv_codec_v_r, rv_fmt_vd_vs2 },
- { "vaesem.vv", rv_codec_v_r, rv_fmt_vd_vs2 },
- { "vaesem.vs", rv_codec_v_r, rv_fmt_vd_vs2 },
- { "vaeskf1.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm },
- { "vaeskf2.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm },
- { "vaesz.vs", rv_codec_v_r, rv_fmt_vd_vs2 },
- { "vandn.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
- { "vandn.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
- { "vbrev.v", rv_codec_v_r, rv_fmt_vd_vs2_vm },
- { "vbrev8.v", rv_codec_v_r, rv_fmt_vd_vs2_vm },
- { "vclmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
- { "vclmul.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
- { "vclmulh.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
- { "vclmulh.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
- { "vclz.v", rv_codec_v_r, rv_fmt_vd_vs2_vm },
- { "vcpop.v", rv_codec_v_r, rv_fmt_vd_vs2_vm },
- { "vctz.v", rv_codec_v_r, rv_fmt_vd_vs2_vm },
- { "vghsh.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1 },
- { "vgmul.vv", rv_codec_v_r, rv_fmt_vd_vs2 },
- { "vrev8.v", rv_codec_v_r, rv_fmt_vd_vs2_vm },
- { "vrol.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
- { "vrol.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
- { "vror.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
- { "vror.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
- { "vror.vi", rv_codec_vror_vi, rv_fmt_vd_vs2_uimm_vm },
- { "vsha2ch.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1 },
- { "vsha2cl.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1 },
- { "vsha2ms.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1 },
- { "vsm3c.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm },
- { "vsm3me.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1 },
- { "vsm4k.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm },
- { "vsm4r.vv", rv_codec_v_r, rv_fmt_vd_vs2 },
- { "vsm4r.vs", rv_codec_v_r, rv_fmt_vd_vs2 },
- { "vwsll.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
- { "vwsll.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
- { "vwsll.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm },
- { "amocas.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
- { "amocas.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
- { "amocas.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
- { "mop.r.0", rv_codec_r, rv_fmt_rd_rs1 },
- { "mop.r.1", rv_codec_r, rv_fmt_rd_rs1 },
- { "mop.r.2", rv_codec_r, rv_fmt_rd_rs1 },
- { "mop.r.3", rv_codec_r, rv_fmt_rd_rs1 },
- { "mop.r.4", rv_codec_r, rv_fmt_rd_rs1 },
- { "mop.r.5", rv_codec_r, rv_fmt_rd_rs1 },
- { "mop.r.6", rv_codec_r, rv_fmt_rd_rs1 },
- { "mop.r.7", rv_codec_r, rv_fmt_rd_rs1 },
- { "mop.r.8", rv_codec_r, rv_fmt_rd_rs1 },
- { "mop.r.9", rv_codec_r, rv_fmt_rd_rs1 },
- { "mop.r.10", rv_codec_r, rv_fmt_rd_rs1 },
- { "mop.r.11", rv_codec_r, rv_fmt_rd_rs1 },
- { "mop.r.12", rv_codec_r, rv_fmt_rd_rs1 },
- { "mop.r.13", rv_codec_r, rv_fmt_rd_rs1 },
- { "mop.r.14", rv_codec_r, rv_fmt_rd_rs1 },
- { "mop.r.15", rv_codec_r, rv_fmt_rd_rs1 },
- { "mop.r.16", rv_codec_r, rv_fmt_rd_rs1 },
- { "mop.r.17", rv_codec_r, rv_fmt_rd_rs1 },
- { "mop.r.18", rv_codec_r, rv_fmt_rd_rs1 },
- { "mop.r.19", rv_codec_r, rv_fmt_rd_rs1 },
- { "mop.r.20", rv_codec_r, rv_fmt_rd_rs1 },
- { "mop.r.21", rv_codec_r, rv_fmt_rd_rs1 },
- { "mop.r.22", rv_codec_r, rv_fmt_rd_rs1 },
- { "mop.r.23", rv_codec_r, rv_fmt_rd_rs1 },
- { "mop.r.24", rv_codec_r, rv_fmt_rd_rs1 },
- { "mop.r.25", rv_codec_r, rv_fmt_rd_rs1 },
- { "mop.r.26", rv_codec_r, rv_fmt_rd_rs1 },
- { "mop.r.27", rv_codec_r, rv_fmt_rd_rs1 },
- { "mop.r.28", rv_codec_r, rv_fmt_rd_rs1 },
- { "mop.r.29", rv_codec_r, rv_fmt_rd_rs1 },
- { "mop.r.30", rv_codec_r, rv_fmt_rd_rs1 },
- { "mop.r.31", rv_codec_r, rv_fmt_rd_rs1 },
- { "mop.rr.0", rv_codec_r, rv_fmt_rd_rs1_rs2 },
- { "mop.rr.1", rv_codec_r, rv_fmt_rd_rs1_rs2 },
- { "mop.rr.2", rv_codec_r, rv_fmt_rd_rs1_rs2 },
- { "mop.rr.3", rv_codec_r, rv_fmt_rd_rs1_rs2 },
- { "mop.rr.4", rv_codec_r, rv_fmt_rd_rs1_rs2 },
- { "mop.rr.5", rv_codec_r, rv_fmt_rd_rs1_rs2 },
- { "mop.rr.6", rv_codec_r, rv_fmt_rd_rs1_rs2 },
- { "mop.rr.7", rv_codec_r, rv_fmt_rd_rs1_rs2 },
- { "c.mop.1", rv_codec_ci_none, rv_fmt_none },
- { "c.mop.3", rv_codec_ci_none, rv_fmt_none },
- { "c.mop.5", rv_codec_ci_none, rv_fmt_none },
- { "c.mop.7", rv_codec_ci_none, rv_fmt_none },
- { "c.mop.9", rv_codec_ci_none, rv_fmt_none },
- { "c.mop.11", rv_codec_ci_none, rv_fmt_none },
- { "c.mop.13", rv_codec_ci_none, rv_fmt_none },
- { "c.mop.15", rv_codec_ci_none, rv_fmt_none },
- { "amoswap.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
- { "amoadd.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
- { "amoxor.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
- { "amoor.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
- { "amoand.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
- { "amomin.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
- { "amomax.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
- { "amominu.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
- { "amomaxu.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
- { "amoswap.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
- { "amoadd.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
- { "amoxor.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
- { "amoor.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
- { "amoand.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
- { "amomin.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
- { "amomax.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
- { "amominu.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
- { "amomaxu.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
- { "amocas.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
- { "amocas.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
- { "wrs.sto", rv_codec_none, rv_fmt_none },
- { "wrs.nto", rv_codec_none, rv_fmt_none },
- { "lpad", rv_codec_lp, rv_fmt_imm },
- { "sspush", rv_codec_r, rv_fmt_rs2 },
- { "sspopchk", rv_codec_r, rv_fmt_rs1 },
- { "ssrdp", rv_codec_r, rv_fmt_rd },
- { "ssamoswap.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
- { "ssamoswap.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
- { "c.sspush", rv_codec_cmop_ss, NULL, DECOMP(rv_op_sspush) },
- { "c.sspopchk", rv_codec_cmop_ss, NULL, DECOMP(rv_op_sspopchk) },
- { "cbo.inval", rv_codec_r, rv_fmt_rs1 },
- { "cbo.clean", rv_codec_r, rv_fmt_rs1 },
- { "cbo.flush", rv_codec_r, rv_fmt_rs1 },
- { "cbo.zero", rv_codec_r, rv_fmt_rs1 },
- { "mnret", rv_codec_none, rv_fmt_none },
+#define OP(N, ...) { __VA_ARGS__ },
+#include "riscv-op.c.inc"
+#undef OP
};
/* CSR names */
@@ -2928,7 +1015,7 @@ static const rv_opcode_data *decode_inst_opcode(rv_decode *dec, rv_isa isa)
(((inst >> 11) & 0b11) == 0b0)) {
unsigned int cmop_code = 0;
cmop_code = ((inst >> 8) & 0b111);
- op = rv_c_mop_1 + cmop_code;
+ op = rv_op_c_mop_1 + cmop_code;
if (dec->cfg->ext_zicfiss) {
op = (cmop_code == 0) ? rv_op_c_sspush : op;
op = (cmop_code == 2) ? rv_op_c_sspopchk : op;
@@ -4459,7 +2546,7 @@ static const rv_opcode_data *decode_inst_opcode(rv_decode *dec, rv_isa isa)
2, 2,
extract32(inst, 26, 2)),
4, 1, extract32(inst, 30, 1));
- op = rv_mop_r_0 + imm_mop5;
+ op = rv_op_mop_r_0 + imm_mop5;
/* if zicfiss enabled and mop5 is shadow stack */
if (dec->cfg->ext_zicfiss &&
((imm_mop5 & 0b11100) == 0b11100)) {
@@ -4478,7 +2565,7 @@ static const rv_opcode_data *decode_inst_opcode(rv_decode *dec, rv_isa isa)
== 0b1000001) {
imm_mop3 = deposit32(extract32(inst, 26, 2),
2, 1, extract32(inst, 30, 1));
- op = rv_mop_rr_0 + imm_mop3;
+ op = rv_op_mop_rr_0 + imm_mop3;
/* if zicfiss enabled and mop3 is shadow stack */
if (dec->cfg->ext_zicfiss &&
((imm_mop3 & 0b111) == 0b111)) {
diff --git a/disas/riscv-op.c.inc b/disas/riscv-op.c.inc
new file mode 100644
index 0000000000..3fe934688e
--- /dev/null
+++ b/disas/riscv-op.c.inc
@@ -0,0 +1,958 @@
+OP(illegal, "illegal", rv_codec_none, rv_fmt_none)
+OP(lui, "lui", rv_codec_u, rv_fmt_rd_uimm)
+OP(auipc, "auipc", rv_codec_u, rv_fmt_rd_uoffset)
+OP(jal, "jal", rv_codec_uj, rv_fmt_rd_offset, rvcp_jal)
+OP(jalr, "jalr", rv_codec_i, rv_fmt_rd_rs1_offset, rvcp_jalr)
+OP(beq, "beq", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_beq)
+OP(bne, "bne", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_bne)
+OP(blt, "blt", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_blt)
+OP(bge, "bge", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_bge)
+OP(bltu, "bltu", rv_codec_sb, rv_fmt_rs1_rs2_offset)
+OP(bgeu, "bgeu", rv_codec_sb, rv_fmt_rs1_rs2_offset)
+OP(lb, "lb", rv_codec_i, rv_fmt_rd_offset_rs1)
+OP(lh, "lh", rv_codec_i, rv_fmt_rd_offset_rs1)
+OP(lw, "lw", rv_codec_i, rv_fmt_rd_offset_rs1)
+OP(lbu, "lbu", rv_codec_i, rv_fmt_rd_offset_rs1)
+OP(lhu, "lhu", rv_codec_i, rv_fmt_rd_offset_rs1)
+OP(sb, "sb", rv_codec_s, rv_fmt_rs2_offset_rs1)
+OP(sh, "sh", rv_codec_s, rv_fmt_rs2_offset_rs1)
+OP(sw, "sw", rv_codec_s, rv_fmt_rs2_offset_rs1)
+OP(addi, "addi", rv_codec_i, rv_fmt_rd_rs1_imm, rvcp_addi)
+OP(slti, "slti", rv_codec_i, rv_fmt_rd_rs1_imm)
+OP(sltiu, "sltiu", rv_codec_i, rv_fmt_rd_rs1_imm, rvcp_sltiu)
+OP(xori, "xori", rv_codec_i, rv_fmt_rd_rs1_imm, rvcp_xori)
+OP(ori, "ori", rv_codec_i, rv_fmt_rd_rs1_imm)
+OP(andi, "andi", rv_codec_i, rv_fmt_rd_rs1_imm)
+OP(slli, "slli", rv_codec_i_sh7, rv_fmt_rd_rs1_imm)
+OP(srli, "srli", rv_codec_i_sh7, rv_fmt_rd_rs1_imm)
+OP(srai, "srai", rv_codec_i_sh7, rv_fmt_rd_rs1_imm)
+OP(add, "add", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(sub, "sub", rv_codec_r, rv_fmt_rd_rs1_rs2, rvcp_sub)
+OP(sll, "sll", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(slt, "slt", rv_codec_r, rv_fmt_rd_rs1_rs2, rvcp_slt)
+OP(sltu, "sltu", rv_codec_r, rv_fmt_rd_rs1_rs2, rvcp_sltu)
+OP(xor, "xor", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(srl, "srl", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(sra, "sra", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(or, "or", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(and, "and", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(fence, "fence", rv_codec_r_f, rv_fmt_pred_succ)
+OP(fence_i, "fence.i", rv_codec_none, rv_fmt_none)
+OP(lwu, "lwu", rv_codec_i, rv_fmt_rd_offset_rs1)
+OP(ld, "ld", rv_codec_i, rv_fmt_rd_offset_rs1)
+OP(sd, "sd", rv_codec_s, rv_fmt_rs2_offset_rs1)
+OP(addiw, "addiw", rv_codec_i, rv_fmt_rd_rs1_imm, rvcp_addiw)
+OP(slliw, "slliw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm)
+OP(srliw, "srliw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm)
+OP(sraiw, "sraiw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm)
+OP(addw, "addw", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(subw, "subw", rv_codec_r, rv_fmt_rd_rs1_rs2, rvcp_subw)
+OP(sllw, "sllw", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(srlw, "srlw", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(sraw, "sraw", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(ldu, "ldu", rv_codec_i, rv_fmt_rd_offset_rs1)
+OP(lq, "lq", rv_codec_i, rv_fmt_rd_offset_rs1)
+OP(sq, "sq", rv_codec_s, rv_fmt_rs2_offset_rs1)
+OP(addid, "addid", rv_codec_i, rv_fmt_rd_rs1_imm)
+OP(sllid, "sllid", rv_codec_i_sh6, rv_fmt_rd_rs1_imm)
+OP(srlid, "srlid", rv_codec_i_sh6, rv_fmt_rd_rs1_imm)
+OP(sraid, "sraid", rv_codec_i_sh6, rv_fmt_rd_rs1_imm)
+OP(addd, "addd", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(subd, "subd", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(slld, "slld", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(srld, "srld", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(srad, "srad", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(mul, "mul", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(mulh, "mulh", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(mulhsu, "mulhsu", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(mulhu, "mulhu", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(div, "div", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(divu, "divu", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(rem, "rem", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(remu, "remu", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(mulw, "mulw", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(divw, "divw", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(divuw, "divuw", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(remw, "remw", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(remuw, "remuw", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(muld, "muld", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(divd, "divd", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(divud, "divud", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(remd, "remd", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(remud, "remud", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(lr_w, "lr.w", rv_codec_r_l, rv_fmt_aqrl_rd_rs1)
+OP(sc_w, "sc.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
+OP(amoswap_w, "amoswap.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
+OP(amoadd_w, "amoadd.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
+OP(amoxor_w, "amoxor.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
+OP(amoor_w, "amoor.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
+OP(amoand_w, "amoand.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
+OP(amomin_w, "amomin.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
+OP(amomax_w, "amomax.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
+OP(amominu_w, "amominu.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
+OP(amomaxu_w, "amomaxu.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
+OP(lr_d, "lr.d", rv_codec_r_l, rv_fmt_aqrl_rd_rs1)
+OP(sc_d, "sc.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
+OP(amoswap_d, "amoswap.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
+OP(amoadd_d, "amoadd.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
+OP(amoxor_d, "amoxor.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
+OP(amoor_d, "amoor.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
+OP(amoand_d, "amoand.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
+OP(amomin_d, "amomin.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
+OP(amomax_d, "amomax.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
+OP(amominu_d, "amominu.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
+OP(amomaxu_d, "amomaxu.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
+OP(lr_q, "lr.q", rv_codec_r_l, rv_fmt_aqrl_rd_rs1)
+OP(sc_q, "sc.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
+OP(amoswap_q, "amoswap.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
+OP(amoadd_q, "amoadd.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
+OP(amoxor_q, "amoxor.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
+OP(amoor_q, "amoor.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
+OP(amoand_q, "amoand.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
+OP(amomin_q, "amomin.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
+OP(amomax_q, "amomax.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
+OP(amominu_q, "amominu.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
+OP(amomaxu_q, "amomaxu.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
+OP(ecall, "ecall", rv_codec_none, rv_fmt_none)
+OP(ebreak, "ebreak", rv_codec_none, rv_fmt_none)
+OP(uret, "uret", rv_codec_none, rv_fmt_none)
+OP(sret, "sret", rv_codec_none, rv_fmt_none)
+OP(hret, "hret", rv_codec_none, rv_fmt_none)
+OP(mret, "mret", rv_codec_none, rv_fmt_none)
+OP(dret, "dret", rv_codec_none, rv_fmt_none)
+OP(sfence_vm, "sfence.vm", rv_codec_r, rv_fmt_rs1)
+OP(sfence_vma, "sfence.vma", rv_codec_r, rv_fmt_rs1_rs2)
+OP(wfi, "wfi", rv_codec_none, rv_fmt_none)
+OP(csrrw, "csrrw", rv_codec_i_csr, rv_fmt_rd_csr_rs1)
+OP(csrrs, "csrrs", rv_codec_i_csr, rv_fmt_rd_csr_rs1)
+OP(csrrc, "csrrc", rv_codec_i_csr, rv_fmt_rd_csr_rs1)
+OP(csrrwi, "csrrwi", rv_codec_i_csr, rv_fmt_rd_csr_zimm)
+OP(csrrsi, "csrrsi", rv_codec_i_csr, rv_fmt_rd_csr_zimm)
+OP(csrrci, "csrrci", rv_codec_i_csr, rv_fmt_rd_csr_zimm)
+OP(flw, "flw", rv_codec_i, rv_fmt_frd_offset_rs1)
+OP(fsw, "fsw", rv_codec_s, rv_fmt_frs2_offset_rs1)
+OP(fmadd_s, "fmadd.s", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3)
+OP(fmsub_s, "fmsub.s", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3)
+OP(fnmsub_s, "fnmsub.s", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3)
+OP(fnmadd_s, "fnmadd.s", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3)
+OP(fadd_s, "fadd.s", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2)
+OP(fsub_s, "fsub.s", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2)
+OP(fmul_s, "fmul.s", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2)
+OP(fdiv_s, "fdiv.s", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2)
+OP(fsgnj_s, "fsgnj.s", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnj_s)
+OP(fsgnjn_s, "fsgnjn.s", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjn_s)
+OP(fsgnjx_s, "fsgnjx.s", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjx_s)
+OP(fmin_s, "fmin.s", rv_codec_r, rv_fmt_frd_frs1_frs2)
+OP(fmax_s, "fmax.s", rv_codec_r, rv_fmt_frd_frs1_frs2)
+OP(fsqrt_s, "fsqrt.s", rv_codec_r_m, rv_fmt_rm_frd_frs1)
+OP(fle_s, "fle.s", rv_codec_r, rv_fmt_rd_frs1_frs2)
+OP(flt_s, "flt.s", rv_codec_r, rv_fmt_rd_frs1_frs2)
+OP(feq_s, "feq.s", rv_codec_r, rv_fmt_rd_frs1_frs2)
+OP(fcvt_w_s, "fcvt.w.s", rv_codec_r_m, rv_fmt_rm_rd_frs1)
+OP(fcvt_wu_s, "fcvt.wu.s", rv_codec_r_m, rv_fmt_rm_rd_frs1)
+OP(fcvt_s_w, "fcvt.s.w", rv_codec_r_m, rv_fmt_rm_frd_rs1)
+OP(fcvt_s_wu, "fcvt.s.wu", rv_codec_r_m, rv_fmt_rm_frd_rs1)
+OP(fmv_x_s, "fmv.x.s", rv_codec_r, rv_fmt_rd_frs1)
+OP(fclass_s, "fclass.s", rv_codec_r, rv_fmt_rd_frs1)
+OP(fmv_s_x, "fmv.s.x", rv_codec_r, rv_fmt_frd_rs1)
+OP(fcvt_l_s, "fcvt.l.s", rv_codec_r_m, rv_fmt_rm_rd_frs1)
+OP(fcvt_lu_s, "fcvt.lu.s", rv_codec_r_m, rv_fmt_rm_rd_frs1)
+OP(fcvt_s_l, "fcvt.s.l", rv_codec_r_m, rv_fmt_rm_frd_rs1)
+OP(fcvt_s_lu, "fcvt.s.lu", rv_codec_r_m, rv_fmt_rm_frd_rs1)
+OP(fld, "fld", rv_codec_i, rv_fmt_frd_offset_rs1)
+OP(fsd, "fsd", rv_codec_s, rv_fmt_frs2_offset_rs1)
+OP(fmadd_d, "fmadd.d", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3)
+OP(fmsub_d, "fmsub.d", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3)
+OP(fnmsub_d, "fnmsub.d", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3)
+OP(fnmadd_d, "fnmadd.d", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3)
+OP(fadd_d, "fadd.d", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2)
+OP(fsub_d, "fsub.d", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2)
+OP(fmul_d, "fmul.d", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2)
+OP(fdiv_d, "fdiv.d", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2)
+OP(fsgnj_d, "fsgnj.d", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnj_d)
+OP(fsgnjn_d, "fsgnjn.d", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjn_d)
+OP(fsgnjx_d, "fsgnjx.d", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjx_d)
+OP(fmin_d, "fmin.d", rv_codec_r, rv_fmt_frd_frs1_frs2)
+OP(fmax_d, "fmax.d", rv_codec_r, rv_fmt_frd_frs1_frs2)
+OP(fcvt_s_d, "fcvt.s.d", rv_codec_r_m, rv_fmt_rm_frd_frs1)
+OP(fcvt_d_s, "fcvt.d.s", rv_codec_r_m, rv_fmt_rm_frd_frs1)
+OP(fsqrt_d, "fsqrt.d", rv_codec_r_m, rv_fmt_rm_frd_frs1)
+OP(fle_d, "fle.d", rv_codec_r, rv_fmt_rd_frs1_frs2)
+OP(flt_d, "flt.d", rv_codec_r, rv_fmt_rd_frs1_frs2)
+OP(feq_d, "feq.d", rv_codec_r, rv_fmt_rd_frs1_frs2)
+OP(fcvt_w_d, "fcvt.w.d", rv_codec_r_m, rv_fmt_rm_rd_frs1)
+OP(fcvt_wu_d, "fcvt.wu.d", rv_codec_r_m, rv_fmt_rm_rd_frs1)
+OP(fcvt_d_w, "fcvt.d.w", rv_codec_r_m, rv_fmt_rm_frd_rs1)
+OP(fcvt_d_wu, "fcvt.d.wu", rv_codec_r_m, rv_fmt_rm_frd_rs1)
+OP(fclass_d, "fclass.d", rv_codec_r, rv_fmt_rd_frs1)
+OP(fcvt_l_d, "fcvt.l.d", rv_codec_r_m, rv_fmt_rm_rd_frs1)
+OP(fcvt_lu_d, "fcvt.lu.d", rv_codec_r_m, rv_fmt_rm_rd_frs1)
+OP(fmv_x_d, "fmv.x.d", rv_codec_r, rv_fmt_rd_frs1)
+OP(fcvt_d_l, "fcvt.d.l", rv_codec_r_m, rv_fmt_rm_frd_rs1)
+OP(fcvt_d_lu, "fcvt.d.lu", rv_codec_r_m, rv_fmt_rm_frd_rs1)
+OP(fmv_d_x, "fmv.d.x", rv_codec_r, rv_fmt_frd_rs1)
+OP(flq, "flq", rv_codec_i, rv_fmt_frd_offset_rs1)
+OP(fsq, "fsq", rv_codec_s, rv_fmt_frs2_offset_rs1)
+OP(fmadd_q, "fmadd.q", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3)
+OP(fmsub_q, "fmsub.q", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3)
+OP(fnmsub_q, "fnmsub.q", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3)
+OP(fnmadd_q, "fnmadd.q", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3)
+OP(fadd_q, "fadd.q", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2)
+OP(fsub_q, "fsub.q", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2)
+OP(fmul_q, "fmul.q", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2)
+OP(fdiv_q, "fdiv.q", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2)
+OP(fsgnj_q, "fsgnj.q", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnj_q)
+OP(fsgnjn_q, "fsgnjn.q", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjn_q)
+OP(fsgnjx_q, "fsgnjx.q", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjx_q)
+OP(fmin_q, "fmin.q", rv_codec_r, rv_fmt_frd_frs1_frs2)
+OP(fmax_q, "fmax.q", rv_codec_r, rv_fmt_frd_frs1_frs2)
+OP(fcvt_s_q, "fcvt.s.q", rv_codec_r_m, rv_fmt_rm_frd_frs1)
+OP(fcvt_q_s, "fcvt.q.s", rv_codec_r_m, rv_fmt_rm_frd_frs1)
+OP(fcvt_d_q, "fcvt.d.q", rv_codec_r_m, rv_fmt_rm_frd_frs1)
+OP(fcvt_q_d, "fcvt.q.d", rv_codec_r_m, rv_fmt_rm_frd_frs1)
+OP(fsqrt_q, "fsqrt.q", rv_codec_r_m, rv_fmt_rm_frd_frs1)
+OP(fle_q, "fle.q", rv_codec_r, rv_fmt_rd_frs1_frs2)
+OP(flt_q, "flt.q", rv_codec_r, rv_fmt_rd_frs1_frs2)
+OP(feq_q, "feq.q", rv_codec_r, rv_fmt_rd_frs1_frs2)
+OP(fcvt_w_q, "fcvt.w.q", rv_codec_r_m, rv_fmt_rm_rd_frs1)
+OP(fcvt_wu_q, "fcvt.wu.q", rv_codec_r_m, rv_fmt_rm_rd_frs1)
+OP(fcvt_q_w, "fcvt.q.w", rv_codec_r_m, rv_fmt_rm_frd_rs1)
+OP(fcvt_q_wu, "fcvt.q.wu", rv_codec_r_m, rv_fmt_rm_frd_rs1)
+OP(fclass_q, "fclass.q", rv_codec_r, rv_fmt_rd_frs1)
+OP(fcvt_l_q, "fcvt.l.q", rv_codec_r_m, rv_fmt_rm_rd_frs1)
+OP(fcvt_lu_q, "fcvt.lu.q", rv_codec_r_m, rv_fmt_rm_rd_frs1)
+OP(fcvt_q_l, "fcvt.q.l", rv_codec_r_m, rv_fmt_rm_frd_rs1)
+OP(fcvt_q_lu, "fcvt.q.lu", rv_codec_r_m, rv_fmt_rm_frd_rs1)
+OP(fmv_x_q, "fmv.x.q", rv_codec_r, rv_fmt_rd_frs1)
+OP(fmv_q_x, "fmv.q.x", rv_codec_r, rv_fmt_frd_rs1)
+OP(c_addi4spn, "c.addi4spn", rv_codec_ciw_4spn, NULL, DECOMP(rv_op_addi))
+OP(c_fld, "c.fld", rv_codec_cl_ld, NULL, DECOMP(rv_op_fld))
+OP(c_lw, "c.lw", rv_codec_cl_lw, NULL, DECOMP(rv_op_lw))
+OP(c_flw, "c.flw", rv_codec_cl_lw, NULL, DECOMP(rv_op_flw))
+OP(c_fsd, "c.fsd", rv_codec_cs_sd, NULL, DECOMP(rv_op_fsd))
+OP(c_sw, "c.sw", rv_codec_cs_sw, NULL, DECOMP(rv_op_sw))
+OP(c_fsw, "c.fsw", rv_codec_cs_sw, NULL, DECOMP(rv_op_fsw))
+OP(c_addi, "c.addi", rv_codec_ci, NULL, DECOMP(rv_op_addi))
+OP(c_jal, "c.jal", rv_codec_cj_jal, NULL, DECOMP(rv_op_jal))
+OP(c_li, "c.li", rv_codec_ci_li, NULL, DECOMP(rv_op_addi))
+OP(c_addi16sp, "c.addi16sp", rv_codec_ci_16sp, NULL, DECOMP(rv_op_addi))
+OP(c_lui, "c.lui", rv_codec_ci_lui, NULL, DECOMP(rv_op_lui))
+OP(c_srli, "c.srli", rv_codec_cb_sh6, NULL, DECOMP(rv_op_srli))
+OP(c_srai, "c.srai", rv_codec_cb_sh6, NULL, DECOMP(rv_op_srai))
+OP(c_andi, "c.andi", rv_codec_cb_imm, NULL, DECOMP(rv_op_andi))
+OP(c_sub, "c.sub", rv_codec_cs, NULL, DECOMP(rv_op_sub))
+OP(c_xor, "c.xor", rv_codec_cs, NULL, DECOMP(rv_op_xor))
+OP(c_or, "c.or", rv_codec_cs, NULL, DECOMP(rv_op_or))
+OP(c_and, "c.and", rv_codec_cs, NULL, DECOMP(rv_op_and))
+OP(c_subw, "c.subw", rv_codec_cs, NULL, DECOMP(rv_op_subw))
+OP(c_addw, "c.addw", rv_codec_cs, NULL, DECOMP(rv_op_addw))
+OP(c_j, "c.j", rv_codec_cj, NULL, DECOMP(rv_op_j))
+OP(c_beqz, "c.beqz", rv_codec_cb, NULL, DECOMP(rv_op_beqz))
+OP(c_bnez, "c.bnez", rv_codec_cb, NULL, DECOMP(rv_op_bnez))
+OP(c_slli, "c.slli", rv_codec_ci_sh6, NULL, DECOMP(rv_op_slli))
+OP(c_fldsp, "c.fldsp", rv_codec_ci_ldsp, NULL, DECOMP(rv_op_fld))
+OP(c_lwsp, "c.lwsp", rv_codec_ci_lwsp, NULL, DECOMP(rv_op_lw))
+OP(c_flwsp, "c.flwsp", rv_codec_ci_lwsp, NULL, DECOMP(rv_op_flw))
+OP(c_jr, "c.jr", rv_codec_cr_jr, NULL, DECOMP(rv_op_jr))
+OP(c_mv, "c.mv", rv_codec_cr_mv, NULL, DECOMP(rv_op_mv))
+OP(c_ebreak, "c.ebreak", rv_codec_ci_none, NULL, DECOMP(rv_op_ebreak))
+OP(c_jalr, "c.jalr", rv_codec_cr_jalr, NULL, DECOMP(rv_op_jalr))
+OP(c_add, "c.add", rv_codec_cr, NULL, DECOMP(rv_op_add))
+OP(c_fsdsp, "c.fsdsp", rv_codec_css_sdsp, NULL, DECOMP(rv_op_fsd))
+OP(c_swsp, "c.swsp", rv_codec_css_swsp, NULL, DECOMP(rv_op_sw))
+OP(c_fswsp, "c.fswsp", rv_codec_css_swsp, NULL, DECOMP(rv_op_fsw))
+OP(c_ld, "c.ld", rv_codec_cl_ld, NULL, DECOMP(rv_op_ld))
+OP(c_sd, "c.sd", rv_codec_cs_sd, NULL, DECOMP(rv_op_sd))
+OP(c_addiw, "c.addiw", rv_codec_ci, NULL, DECOMP(rv_op_addiw))
+OP(c_ldsp, "c.ldsp", rv_codec_ci_ldsp, NULL, DECOMP(rv_op_ld))
+OP(c_sdsp, "c.sdsp", rv_codec_css_sdsp, NULL, DECOMP(rv_op_sd))
+OP(c_lq, "c.lq", rv_codec_cl_lq, NULL, DECOMP(rv_op_lq))
+OP(c_sq, "c.sq", rv_codec_cs_sq, NULL, DECOMP(rv_op_sq))
+OP(c_lqsp, "c.lqsp", rv_codec_ci_lqsp, NULL, DECOMP(rv_op_lq))
+OP(c_sqsp, "c.sqsp", rv_codec_css_sqsp, NULL, DECOMP(rv_op_sq))
+OP(nop, "nop", rv_codec_illegal, rv_fmt_none)
+OP(mv, "mv", rv_codec_illegal, rv_fmt_rd_rs1, rvcp_mv)
+OP(not, "not", rv_codec_illegal, rv_fmt_rd_rs1)
+OP(neg, "neg", rv_codec_illegal, rv_fmt_rd_rs2)
+OP(negw, "negw", rv_codec_illegal, rv_fmt_rd_rs2)
+OP(sext_w, "sext.w", rv_codec_illegal, rv_fmt_rd_rs1)
+OP(seqz, "seqz", rv_codec_illegal, rv_fmt_rd_rs1)
+OP(snez, "snez", rv_codec_illegal, rv_fmt_rd_rs2)
+OP(sltz, "sltz", rv_codec_illegal, rv_fmt_rd_rs1)
+OP(sgtz, "sgtz", rv_codec_illegal, rv_fmt_rd_rs2)
+OP(fmv_s, "fmv.s", rv_codec_illegal, rv_fmt_frd_frs1)
+OP(fabs_s, "fabs.s", rv_codec_illegal, rv_fmt_frd_frs1)
+OP(fneg_s, "fneg.s", rv_codec_illegal, rv_fmt_frd_frs1)
+OP(fmv_d, "fmv.d", rv_codec_illegal, rv_fmt_frd_frs1)
+OP(fabs_d, "fabs.d", rv_codec_illegal, rv_fmt_frd_frs1)
+OP(fneg_d, "fneg.d", rv_codec_illegal, rv_fmt_frd_frs1)
+OP(fmv_q, "fmv.q", rv_codec_illegal, rv_fmt_frd_frs1)
+OP(fabs_q, "fabs.q", rv_codec_illegal, rv_fmt_frd_frs1)
+OP(fneg_q, "fneg.q", rv_codec_illegal, rv_fmt_frd_frs1)
+OP(beqz, "beqz", rv_codec_illegal, rv_fmt_rs1_offset)
+OP(bnez, "bnez", rv_codec_illegal, rv_fmt_rs1_offset)
+OP(blez, "blez", rv_codec_illegal, rv_fmt_rs2_offset)
+OP(bgez, "bgez", rv_codec_illegal, rv_fmt_rs1_offset)
+OP(bltz, "bltz", rv_codec_illegal, rv_fmt_rs1_offset)
+OP(bgtz, "bgtz", rv_codec_illegal, rv_fmt_rs2_offset)
+OP(jal_ra, "jal", rv_codec_illegal, rv_fmt_offset)
+OP(jalr_ra, "jalr", rv_codec_illegal, rv_fmt_rs1)
+OP(j, "j", rv_codec_illegal, rv_fmt_offset)
+OP(ret, "ret", rv_codec_illegal, rv_fmt_none)
+OP(jr, "jr", rv_codec_illegal, rv_fmt_rs1, rvcp_jr)
+OP(rdcycle, "rdcycle", rv_codec_i_csr, rv_fmt_rd)
+OP(rdtime, "rdtime", rv_codec_i_csr, rv_fmt_rd)
+OP(rdinstret, "rdinstret", rv_codec_i_csr, rv_fmt_rd)
+OP(rdcycleh, "rdcycleh", rv_codec_i_csr, rv_fmt_rd)
+OP(rdtimeh, "rdtimeh", rv_codec_i_csr, rv_fmt_rd)
+OP(rdinstreth, "rdinstreth", rv_codec_i_csr, rv_fmt_rd)
+OP(frcsr, "frcsr", rv_codec_i_csr, rv_fmt_rd)
+OP(frrm, "frrm", rv_codec_i_csr, rv_fmt_rd)
+OP(frflags, "frflags", rv_codec_i_csr, rv_fmt_rd)
+OP(fscsr, "fscsr", rv_codec_i_csr, rv_fmt_rd_rs1)
+OP(fsrm, "fsrm", rv_codec_i_csr, rv_fmt_rd_rs1)
+OP(fsflags, "fsflags", rv_codec_i_csr, rv_fmt_rd_rs1)
+OP(fsrmi, "fsrmi", rv_codec_i_csr, rv_fmt_rd_zimm)
+OP(fsflagsi, "fsflagsi", rv_codec_i_csr, rv_fmt_rd_zimm)
+OP(bseti, "bseti", rv_codec_i_sh7, rv_fmt_rd_rs1_imm)
+OP(bclri, "bclri", rv_codec_i_sh7, rv_fmt_rd_rs1_imm)
+OP(binvi, "binvi", rv_codec_i_sh7, rv_fmt_rd_rs1_imm)
+OP(bexti, "bexti", rv_codec_i_sh7, rv_fmt_rd_rs1_imm)
+OP(rori, "rori", rv_codec_i_sh7, rv_fmt_rd_rs1_imm)
+OP(clz, "clz", rv_codec_r, rv_fmt_rd_rs1)
+OP(ctz, "ctz", rv_codec_r, rv_fmt_rd_rs1)
+OP(cpop, "cpop", rv_codec_r, rv_fmt_rd_rs1)
+OP(sext_h, "sext.h", rv_codec_r, rv_fmt_rd_rs1)
+OP(sext_b, "sext.b", rv_codec_r, rv_fmt_rd_rs1)
+OP(xnor, "xnor", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(orn, "orn", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(andn, "andn", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(rol, "rol", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(ror, "ror", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(sh1add, "sh1add", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(sh2add, "sh2add", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(sh3add, "sh3add", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(sh1add_uw, "sh1add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(sh2add_uw, "sh2add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(sh3add_uw, "sh3add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(clmul, "clmul", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(clmulr, "clmulr", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(clmulh, "clmulh", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(min, "min", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(minu, "minu", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(max, "max", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(maxu, "maxu", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(clzw, "clzw", rv_codec_r, rv_fmt_rd_rs1)
+OP(ctzw, "ctzw", rv_codec_r, rv_fmt_rd_rs1)
+OP(cpopw, "cpopw", rv_codec_r, rv_fmt_rd_rs1)
+OP(slli_uw, "slli.uw", rv_codec_i_sh6, rv_fmt_rd_rs1_imm)
+OP(add_uw, "add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(rolw, "rolw", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(rorw, "rorw", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(rev8, "rev8", rv_codec_r, rv_fmt_rd_rs1)
+OP(zext_h, "zext.h", rv_codec_r, rv_fmt_rd_rs1)
+OP(roriw, "roriw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm)
+OP(orc_b, "orc.b", rv_codec_r, rv_fmt_rd_rs1)
+OP(bset, "bset", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(bclr, "bclr", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(binv, "binv", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(bext, "bext", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(aes32esmi, "aes32esmi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs)
+OP(aes32esi, "aes32esi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs)
+OP(aes32dsmi, "aes32dsmi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs)
+OP(aes32dsi, "aes32dsi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs)
+OP(aes64ks1i, "aes64ks1i", rv_codec_k_rnum, rv_fmt_rd_rs1_rnum)
+OP(aes64ks2, "aes64ks2", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(aes64im, "aes64im", rv_codec_r, rv_fmt_rd_rs1)
+OP(aes64esm, "aes64esm", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(aes64es, "aes64es", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(aes64dsm, "aes64dsm", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(aes64ds, "aes64ds", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(sha256sig0, "sha256sig0", rv_codec_r, rv_fmt_rd_rs1)
+OP(sha256sig1, "sha256sig1", rv_codec_r, rv_fmt_rd_rs1)
+OP(sha256sum0, "sha256sum0", rv_codec_r, rv_fmt_rd_rs1)
+OP(sha256sum1, "sha256sum1", rv_codec_r, rv_fmt_rd_rs1)
+OP(sha512sig0, "sha512sig0", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(sha512sig1, "sha512sig1", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(sha512sum0, "sha512sum0", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(sha512sum1, "sha512sum1", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(sha512sum0r, "sha512sum0r", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(sha512sum1r, "sha512sum1r", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(sha512sig0l, "sha512sig0l", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(sha512sig0h, "sha512sig0h", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(sha512sig1l, "sha512sig1l", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(sha512sig1h, "sha512sig1h", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(sm3p0, "sm3p0", rv_codec_r, rv_fmt_rd_rs1)
+OP(sm3p1, "sm3p1", rv_codec_r, rv_fmt_rd_rs1)
+OP(sm4ed, "sm4ed", rv_codec_k_bs, rv_fmt_rs1_rs2_bs)
+OP(sm4ks, "sm4ks", rv_codec_k_bs, rv_fmt_rs1_rs2_bs)
+OP(brev8, "brev8", rv_codec_r, rv_fmt_rd_rs1)
+OP(pack, "pack", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(packh, "packh", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(packw, "packw", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(unzip, "unzip", rv_codec_r, rv_fmt_rd_rs1)
+OP(zip, "zip", rv_codec_r, rv_fmt_rd_rs1)
+OP(xperm4, "xperm4", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(xperm8, "xperm8", rv_codec_r, rv_fmt_rd_rs1)
+OP(vle8_v, "vle8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
+OP(vle16_v, "vle16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
+OP(vle32_v, "vle32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
+OP(vle64_v, "vle64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
+OP(vse8_v, "vse8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
+OP(vse16_v, "vse16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
+OP(vse32_v, "vse32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
+OP(vse64_v, "vse64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
+OP(vlm_v, "vlm.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
+OP(vsm_v, "vsm.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
+OP(vlse8_v, "vlse8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm)
+OP(vlse16_v, "vlse16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm)
+OP(vlse32_v, "vlse32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm)
+OP(vlse64_v, "vlse64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm)
+OP(vsse8_v, "vsse8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm)
+OP(vsse16_v, "vsse16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm)
+OP(vsse32_v, "vsse32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm)
+OP(vsse64_v, "vsse64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm)
+OP(vluxei8_v, "vluxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm)
+OP(vluxei16_v, "vluxei16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm)
+OP(vluxei32_v, "vluxei32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm)
+OP(vluxei64_v, "vluxei64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm)
+OP(vloxei8_v, "vloxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm)
+OP(vloxei16_v, "vloxei16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm)
+OP(vloxei32_v, "vloxei32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm)
+OP(vloxei64_v, "vloxei64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm)
+OP(vsuxei8_v, "vsuxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm)
+OP(vsuxei16_v, "vsuxei16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm)
+OP(vsuxei32_v, "vsuxei32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm)
+OP(vsuxei64_v, "vsuxei64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm)
+OP(vsoxei8_v, "vsoxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm)
+OP(vsoxei16_v, "vsoxei16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm)
+OP(vsoxei32_v, "vsoxei32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm)
+OP(vsoxei64_v, "vsoxei64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm)
+OP(vle8ff_v, "vle8ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
+OP(vle16ff_v, "vle16ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
+OP(vle32ff_v, "vle32ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
+OP(vle64ff_v, "vle64ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
+OP(vl1re8_v, "vl1re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
+OP(vl1re16_v, "vl1re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
+OP(vl1re32_v, "vl1re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
+OP(vl1re64_v, "vl1re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
+OP(vl2re8_v, "vl2re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
+OP(vl2re16_v, "vl2re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
+OP(vl2re32_v, "vl2re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
+OP(vl2re64_v, "vl2re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
+OP(vl4re8_v, "vl4re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
+OP(vl4re16_v, "vl4re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
+OP(vl4re32_v, "vl4re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
+OP(vl4re64_v, "vl4re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
+OP(vl8re8_v, "vl8re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
+OP(vl8re16_v, "vl8re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
+OP(vl8re32_v, "vl8re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
+OP(vl8re64_v, "vl8re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
+OP(vs1r_v, "vs1r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
+OP(vs2r_v, "vs2r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
+OP(vs4r_v, "vs4r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
+OP(vs8r_v, "vs8r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
+OP(vadd_vv, "vadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vadd_vx, "vadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
+OP(vadd_vi, "vadd.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm)
+OP(vsub_vv, "vsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vsub_vx, "vsub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
+OP(vrsub_vx, "vrsub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
+OP(vrsub_vi, "vrsub.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm)
+OP(vwaddu_vv, "vwaddu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vwaddu_vx, "vwaddu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
+OP(vwadd_vv, "vwadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vwadd_vx, "vwadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
+OP(vwsubu_vv, "vwsubu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vwsubu_vx, "vwsubu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
+OP(vwsub_vv, "vwsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vwsub_vx, "vwsub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
+OP(vwaddu_wv, "vwaddu.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vwaddu_wx, "vwaddu.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
+OP(vwadd_wv, "vwadd.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vwadd_wx, "vwadd.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
+OP(vwsubu_wv, "vwsubu.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vwsubu_wx, "vwsubu.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
+OP(vwsub_wv, "vwsub.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vwsub_wx, "vwsub.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
+OP(vadc_vvm, "vadc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl)
+OP(vadc_vxm, "vadc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl)
+OP(vadc_vim, "vadc.vim", rv_codec_v_i, rv_fmt_vd_vs2_imm_vl)
+OP(vmadc_vvm, "vmadc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl)
+OP(vmadc_vxm, "vmadc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl)
+OP(vmadc_vim, "vmadc.vim", rv_codec_v_i, rv_fmt_vd_vs2_imm_vl)
+OP(vsbc_vvm, "vsbc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl)
+OP(vsbc_vxm, "vsbc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl)
+OP(vmsbc_vvm, "vmsbc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl)
+OP(vmsbc_vxm, "vmsbc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl)
+OP(vand_vv, "vand.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vand_vx, "vand.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
+OP(vand_vi, "vand.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm)
+OP(vor_vv, "vor.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vor_vx, "vor.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
+OP(vor_vi, "vor.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm)
+OP(vxor_vv, "vxor.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vxor_vx, "vxor.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
+OP(vxor_vi, "vxor.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm)
+OP(vsll_vv, "vsll.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vsll_vx, "vsll.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
+OP(vsll_vi, "vsll.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm)
+OP(vsrl_vv, "vsrl.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vsrl_vx, "vsrl.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
+OP(vsrl_vi, "vsrl.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm)
+OP(vsra_vv, "vsra.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vsra_vx, "vsra.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
+OP(vsra_vi, "vsra.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm)
+OP(vnsrl_wv, "vnsrl.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vnsrl_wx, "vnsrl.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
+OP(vnsrl_wi, "vnsrl.wi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm)
+OP(vnsra_wv, "vnsra.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vnsra_wx, "vnsra.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
+OP(vnsra_wi, "vnsra.wi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm)
+OP(vmseq_vv, "vmseq.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vmseq_vx, "vmseq.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
+OP(vmseq_vi, "vmseq.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm)
+OP(vmsne_vv, "vmsne.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vmsne_vx, "vmsne.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
+OP(vmsne_vi, "vmsne.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm)
+OP(vmsltu_vv, "vmsltu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vmsltu_vx, "vmsltu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
+OP(vmslt_vv, "vmslt.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vmslt_vx, "vmslt.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
+OP(vmsleu_vv, "vmsleu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vmsleu_vx, "vmsleu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
+OP(vmsleu_vi, "vmsleu.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm)
+OP(vmsle_vv, "vmsle.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vmsle_vx, "vmsle.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
+OP(vmsle_vi, "vmsle.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm)
+OP(vmsgtu_vx, "vmsgtu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
+OP(vmsgtu_vi, "vmsgtu.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm)
+OP(vmsgt_vx, "vmsgt.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
+OP(vmsgt_vi, "vmsgt.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm)
+OP(vminu_vv, "vminu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vminu_vx, "vminu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
+OP(vmin_vv, "vmin.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vmin_vx, "vmin.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
+OP(vmaxu_vv, "vmaxu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vmaxu_vx, "vmaxu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
+OP(vmax_vv, "vmax.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vmax_vx, "vmax.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
+OP(vmul_vv, "vmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vmul_vx, "vmul.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
+OP(vmulh_vv, "vmulh.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vmulh_vx, "vmulh.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
+OP(vmulhu_vv, "vmulhu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vmulhu_vx, "vmulhu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
+OP(vmulhsu_vv, "vmulhsu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vmulhsu_vx, "vmulhsu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
+OP(vdivu_vv, "vdivu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vdivu_vx, "vdivu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
+OP(vdiv_vv, "vdiv.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vdiv_vx, "vdiv.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
+OP(vremu_vv, "vremu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vremu_vx, "vremu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
+OP(vrem_vv, "vrem.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vrem_vx, "vrem.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
+OP(vwmulu_vv, "vwmulu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vwmulu_vx, "vwmulu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
+OP(vwmulsu_vv, "vwmulsu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vwmulsu_vx, "vwmulsu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
+OP(vwmul_vv, "vwmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vwmul_vx, "vwmul.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
+OP(vmacc_vv, "vmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
+OP(vmacc_vx, "vmacc.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm)
+OP(vnmsac_vv, "vnmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
+OP(vnmsac_vx, "vnmsac.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm)
+OP(vmadd_vv, "vmadd.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
+OP(vmadd_vx, "vmadd.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm)
+OP(vnmsub_vv, "vnmsub.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
+OP(vnmsub_vx, "vnmsub.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm)
+OP(vwmaccu_vv, "vwmaccu.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
+OP(vwmaccu_vx, "vwmaccu.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm)
+OP(vwmacc_vv, "vwmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
+OP(vwmacc_vx, "vwmacc.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm)
+OP(vwmaccsu_vv, "vwmaccsu.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
+OP(vwmaccsu_vx, "vwmaccsu.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm)
+OP(vwmaccus_vx, "vwmaccus.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm)
+OP(vmv_v_v, "vmv.v.v", rv_codec_v_r, rv_fmt_vd_vs1)
+OP(vmv_v_x, "vmv.v.x", rv_codec_v_r, rv_fmt_vd_rs1)
+OP(vmv_v_i, "vmv.v.i", rv_codec_v_i, rv_fmt_vd_imm)
+OP(vmerge_vvm, "vmerge.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl)
+OP(vmerge_vxm, "vmerge.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl)
+OP(vmerge_vim, "vmerge.vim", rv_codec_v_i, rv_fmt_vd_vs2_imm_vl)
+OP(vsaddu_vv, "vsaddu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vsaddu_vx, "vsaddu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
+OP(vsaddu_vi, "vsaddu.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm)
+OP(vsadd_vv, "vsadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vsadd_vx, "vsadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
+OP(vsadd_vi, "vsadd.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm)
+OP(vssubu_vv, "vssubu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vssubu_vx, "vssubu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
+OP(vssub_vv, "vssub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vssub_vx, "vssub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
+OP(vaadd_vv, "vaadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vaadd_vx, "vaadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
+OP(vaaddu_vv, "vaaddu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vaaddu_vx, "vaaddu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
+OP(vasub_vv, "vasub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vasub_vx, "vasub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
+OP(vasubu_vv, "vasubu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vasubu_vx, "vasubu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
+OP(vsmul_vv, "vsmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vsmul_vx, "vsmul.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
+OP(vssrl_vv, "vssrl.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vssrl_vx, "vssrl.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
+OP(vssrl_vi, "vssrl.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm)
+OP(vssra_vv, "vssra.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vssra_vx, "vssra.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
+OP(vssra_vi, "vssra.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm)
+OP(vnclipu_wv, "vnclipu.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vnclipu_wx, "vnclipu.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
+OP(vnclipu_wi, "vnclipu.wi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm)
+OP(vnclip_wv, "vnclip.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vnclip_wx, "vnclip.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
+OP(vnclip_wi, "vnclip.wi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm)
+OP(vfadd_vv, "vfadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vfadd_vf, "vfadd.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
+OP(vfsub_vv, "vfsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vfsub_vf, "vfsub.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
+OP(vfrsub_vf, "vfrsub.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
+OP(vfwadd_vv, "vfwadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vfwadd_vf, "vfwadd.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
+OP(vfwadd_wv, "vfwadd.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vfwadd_wf, "vfwadd.wf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
+OP(vfwsub_vv, "vfwsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vfwsub_vf, "vfwsub.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
+OP(vfwsub_wv, "vfwsub.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vfwsub_wf, "vfwsub.wf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
+OP(vfmul_vv, "vfmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vfmul_vf, "vfmul.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
+OP(vfdiv_vv, "vfdiv.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vfdiv_vf, "vfdiv.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
+OP(vfrdiv_vf, "vfrdiv.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
+OP(vfwmul_vv, "vfwmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vfwmul_vf, "vfwmul.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
+OP(vfmacc_vv, "vfmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
+OP(vfmacc_vf, "vfmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm)
+OP(vfnmacc_vv, "vfnmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
+OP(vfnmacc_vf, "vfnmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm)
+OP(vfmsac_vv, "vfmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
+OP(vfmsac_vf, "vfmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm)
+OP(vfnmsac_vv, "vfnmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
+OP(vfnmsac_vf, "vfnmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm)
+OP(vfmadd_vv, "vfmadd.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
+OP(vfmadd_vf, "vfmadd.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm)
+OP(vfnmadd_vv, "vfnmadd.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
+OP(vfnmadd_vf, "vfnmadd.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm)
+OP(vfmsub_vv, "vfmsub.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
+OP(vfmsub_vf, "vfmsub.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm)
+OP(vfnmsub_vv, "vfnmsub.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
+OP(vfnmsub_vf, "vfnmsub.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm)
+OP(vfwmacc_vv, "vfwmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
+OP(vfwmacc_vf, "vfwmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm)
+OP(vfwnmacc_vv, "vfwnmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
+OP(vfwnmacc_vf, "vfwnmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm)
+OP(vfwmsac_vv, "vfwmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
+OP(vfwmsac_vf, "vfwmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm)
+OP(vfwnmsac_vv, "vfwnmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
+OP(vfwnmsac_vf, "vfwnmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm)
+OP(vfsqrt_v, "vfsqrt.v", rv_codec_v_r, rv_fmt_vd_vs2)
+OP(vfrsqrt7_v, "vfrsqrt7.v", rv_codec_v_r, rv_fmt_vd_vs2)
+OP(vfrec7_v, "vfrec7.v", rv_codec_v_r, rv_fmt_vd_vs2)
+OP(vfmin_vv, "vfmin.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vfmin_vf, "vfmin.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
+OP(vfmax_vv, "vfmax.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vfmax_vf, "vfmax.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
+OP(vfsgnj_vv, "vfsgnj.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vfsgnj_vf, "vfsgnj.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
+OP(vfsgnjn_vv, "vfsgnjn.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vfsgnjn_vf, "vfsgnjn.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
+OP(vfsgnjx_vv, "vfsgnjx.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vfsgnjx_vf, "vfsgnjx.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
+OP(vfslide1up_vf, "vfslide1up.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
+OP(vfslide1down_vf, "vfslide1down.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
+OP(vmfeq_vv, "vmfeq.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vmfeq_vf, "vmfeq.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
+OP(vmfne_vv, "vmfne.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vmfne_vf, "vmfne.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
+OP(vmflt_vv, "vmflt.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vmflt_vf, "vmflt.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
+OP(vmfle_vv, "vmfle.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vmfle_vf, "vmfle.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
+OP(vmfgt_vf, "vmfgt.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
+OP(vmfge_vf, "vmfge.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
+OP(vfclass_v, "vfclass.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
+OP(vfmerge_vfm, "vfmerge.vfm", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vl)
+OP(vfmv_v_f, "vfmv.v.f", rv_codec_v_r, rv_fmt_vd_fs1)
+OP(vfcvt_xu_f_v, "vfcvt.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
+OP(vfcvt_x_f_v, "vfcvt.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
+OP(vfcvt_f_xu_v, "vfcvt.f.xu.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
+OP(vfcvt_f_x_v, "vfcvt.f.x.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
+OP(vfcvt_rtz_xu_f_v, "vfcvt.rtz.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
+OP(vfcvt_rtz_x_f_v, "vfcvt.rtz.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
+OP(vfwcvt_xu_f_v, "vfwcvt.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
+OP(vfwcvt_x_f_v, "vfwcvt.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
+OP(vfwcvt_f_xu_v, "vfwcvt.f.xu.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
+OP(vfwcvt_f_x_v, "vfwcvt.f.x.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
+OP(vfwcvt_f_f_v, "vfwcvt.f.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
+OP(vfwcvt_rtz_xu_f_v, "vfwcvt.rtz.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
+OP(vfwcvt_rtz_x_f_v, "vfwcvt.rtz.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
+OP(vfncvt_xu_f_w, "vfncvt.xu.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm)
+OP(vfncvt_x_f_w, "vfncvt.x.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm)
+OP(vfncvt_f_xu_w, "vfncvt.f.xu.w", rv_codec_v_r, rv_fmt_vd_vs2_vm)
+OP(vfncvt_f_x_w, "vfncvt.f.x.w", rv_codec_v_r, rv_fmt_vd_vs2_vm)
+OP(vfncvt_f_f_w, "vfncvt.f.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm)
+OP(vfncvt_rod_f_f_w, "vfncvt.rod.f.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm)
+OP(vfncvt_rtz_xu_f_w, "vfncvt.rtz.xu.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm)
+OP(vfncvt_rtz_x_f_w, "vfncvt.rtz.x.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm)
+OP(vredsum_vs, "vredsum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vredand_vs, "vredand.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vredor_vs, "vredor.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vredxor_vs, "vredxor.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vredminu_vs, "vredminu.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vredmin_vs, "vredmin.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vredmaxu_vs, "vredmaxu.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vredmax_vs, "vredmax.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vwredsumu_vs, "vwredsumu.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vwredsum_vs, "vwredsum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vfredusum_vs, "vfredusum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vfredosum_vs, "vfredosum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vfredmin_vs, "vfredmin.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vfredmax_vs, "vfredmax.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vfwredusum_vs, "vfwredusum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vfwredosum_vs, "vfwredosum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vmand_mm, "vmand.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vmnand_mm, "vmnand.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vmandn_mm, "vmandn.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vmxor_mm, "vmxor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vmor_mm, "vmor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vmnor_mm, "vmnor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vmorn_mm, "vmorn.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vmxnor_mm, "vmxnor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vcpop_m, "vcpop.m", rv_codec_v_r, rv_fmt_rd_vs2_vm)
+OP(vfirst_m, "vfirst.m", rv_codec_v_r, rv_fmt_rd_vs2_vm)
+OP(vmsbf_m, "vmsbf.m", rv_codec_v_r, rv_fmt_vd_vs2_vm)
+OP(vmsif_m, "vmsif.m", rv_codec_v_r, rv_fmt_vd_vs2_vm)
+OP(vmsof_m, "vmsof.m", rv_codec_v_r, rv_fmt_vd_vs2_vm)
+OP(viota_m, "viota.m", rv_codec_v_r, rv_fmt_vd_vs2_vm)
+OP(vid_v, "vid.v", rv_codec_v_r, rv_fmt_vd_vm)
+OP(vmv_x_s, "vmv.x.s", rv_codec_v_r, rv_fmt_rd_vs2)
+OP(vmv_s_x, "vmv.s.x", rv_codec_v_r, rv_fmt_vd_rs1)
+OP(vfmv_f_s, "vfmv.f.s", rv_codec_v_r, rv_fmt_fd_vs2)
+OP(vfmv_s_f, "vfmv.s.f", rv_codec_v_r, rv_fmt_vd_fs1)
+OP(vslideup_vx, "vslideup.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
+OP(vslideup_vi, "vslideup.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm)
+OP(vslide1up_vx, "vslide1up.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
+OP(vslidedown_vx, "vslidedown.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
+OP(vslidedown_vi, "vslidedown.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm)
+OP(vslide1down_vx, "vslide1down.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
+OP(vrgather_vv, "vrgather.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vrgatherei16_vv, "vrgatherei16.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vrgather_vx, "vrgather.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
+OP(vrgather_vi, "vrgather.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm)
+OP(vcompress_vm, "vcompress.vm", rv_codec_v_r, rv_fmt_vd_vs2_vs1)
+OP(vmv1r_v, "vmv1r.v", rv_codec_v_r, rv_fmt_vd_vs2)
+OP(vmv2r_v, "vmv2r.v", rv_codec_v_r, rv_fmt_vd_vs2)
+OP(vmv4r_v, "vmv4r.v", rv_codec_v_r, rv_fmt_vd_vs2)
+OP(vmv8r_v, "vmv8r.v", rv_codec_v_r, rv_fmt_vd_vs2)
+OP(vzext_vf2, "vzext.vf2", rv_codec_v_r, rv_fmt_vd_vs2_vm)
+OP(vzext_vf4, "vzext.vf4", rv_codec_v_r, rv_fmt_vd_vs2_vm)
+OP(vzext_vf8, "vzext.vf8", rv_codec_v_r, rv_fmt_vd_vs2_vm)
+OP(vsext_vf2, "vsext.vf2", rv_codec_v_r, rv_fmt_vd_vs2_vm)
+OP(vsext_vf4, "vsext.vf4", rv_codec_v_r, rv_fmt_vd_vs2_vm)
+OP(vsext_vf8, "vsext.vf8", rv_codec_v_r, rv_fmt_vd_vs2_vm)
+OP(vsetvli, "vsetvli", rv_codec_vsetvli, rv_fmt_vsetvli)
+OP(vsetivli, "vsetivli", rv_codec_vsetivli, rv_fmt_vsetivli)
+OP(vsetvl, "vsetvl", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(c_zext_b, "c.zext.b", rv_codec_zcb_ext, rv_fmt_rd)
+OP(c_sext_b, "c.sext.b", rv_codec_zcb_ext, rv_fmt_rd)
+OP(c_zext_h, "c.zext.h", rv_codec_zcb_ext, rv_fmt_rd)
+OP(c_sext_h, "c.sext.h", rv_codec_zcb_ext, rv_fmt_rd)
+OP(c_zext_w, "c.zext.w", rv_codec_zcb_ext, rv_fmt_rd)
+OP(c_not, "c.not", rv_codec_zcb_ext, rv_fmt_rd)
+OP(c_mul, "c.mul", rv_codec_zcb_mul, rv_fmt_rd_rs2)
+OP(c_lbu, "c.lbu", rv_codec_zcb_lb, rv_fmt_rs1_rs2_zce_ldst)
+OP(c_lhu, "c.lhu", rv_codec_zcb_lh, rv_fmt_rs1_rs2_zce_ldst)
+OP(c_lh, "c.lh", rv_codec_zcb_lh, rv_fmt_rs1_rs2_zce_ldst)
+OP(c_sb, "c.sb", rv_codec_zcb_lb, rv_fmt_rs1_rs2_zce_ldst)
+OP(c_sh, "c.sh", rv_codec_zcb_lh, rv_fmt_rs1_rs2_zce_ldst)
+OP(cm_push, "cm.push", rv_codec_zcmp_cm_pushpop, rv_fmt_push_rlist)
+OP(cm_pop, "cm.pop", rv_codec_zcmp_cm_pushpop, rv_fmt_pop_rlist)
+OP(cm_popret, "cm.popret", rv_codec_zcmp_cm_pushpop, rv_fmt_pop_rlist)
+OP(cm_popretz, "cm.popretz", rv_codec_zcmp_cm_pushpop, rv_fmt_pop_rlist)
+OP(cm_mva01s, "cm.mva01s", rv_codec_zcmp_cm_mv, rv_fmt_rd_rs2)
+OP(cm_mvsa01, "cm.mvsa01", rv_codec_zcmp_cm_mv, rv_fmt_rd_rs2)
+OP(cm_jt, "cm.jt", rv_codec_zcmt_jt, rv_fmt_zcmt_index)
+OP(cm_jalt, "cm.jalt", rv_codec_zcmt_jt, rv_fmt_zcmt_index)
+OP(czero_eqz, "czero.eqz", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(czero_nez, "czero.nez", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(fcvt_bf16_s, "fcvt.bf16.s", rv_codec_r_m, rv_fmt_rm_frd_frs1)
+OP(fcvt_s_bf16, "fcvt.s.bf16", rv_codec_r_m, rv_fmt_rm_frd_frs1)
+OP(vfncvtbf16_f_f_w, "vfncvtbf16.f.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm)
+OP(vfwcvtbf16_f_f_v, "vfwcvtbf16.f.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
+OP(vfwmaccbf16_vv, "vfwmaccbf16.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
+OP(vfwmaccbf16_vf, "vfwmaccbf16.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm)
+OP(flh, "flh", rv_codec_i, rv_fmt_frd_offset_rs1)
+OP(fsh, "fsh", rv_codec_s, rv_fmt_frs2_offset_rs1)
+OP(fmv_h_x, "fmv.h.x", rv_codec_r, rv_fmt_frd_rs1)
+OP(fmv_x_h, "fmv.x.h", rv_codec_r, rv_fmt_rd_frs1)
+OP(fli_s, "fli.s", rv_codec_fli, rv_fmt_fli)
+OP(fli_d, "fli.d", rv_codec_fli, rv_fmt_fli)
+OP(fli_q, "fli.q", rv_codec_fli, rv_fmt_fli)
+OP(fli_h, "fli.h", rv_codec_fli, rv_fmt_fli)
+OP(fminm_s, "fminm.s", rv_codec_r, rv_fmt_frd_frs1_frs2)
+OP(fmaxm_s, "fmaxm.s", rv_codec_r, rv_fmt_frd_frs1_frs2)
+OP(fminm_d, "fminm.d", rv_codec_r, rv_fmt_frd_frs1_frs2)
+OP(fmaxm_d, "fmaxm.d", rv_codec_r, rv_fmt_frd_frs1_frs2)
+OP(fminm_q, "fminm.q", rv_codec_r, rv_fmt_frd_frs1_frs2)
+OP(fmaxm_q, "fmaxm.q", rv_codec_r, rv_fmt_frd_frs1_frs2)
+OP(fminm_h, "fminm.h", rv_codec_r, rv_fmt_frd_frs1_frs2)
+OP(fmaxm_h, "fmaxm.h", rv_codec_r, rv_fmt_frd_frs1_frs2)
+OP(fround_s, "fround.s", rv_codec_r_m, rv_fmt_rm_frd_frs1)
+OP(froundnx_s, "froundnx.s", rv_codec_r_m, rv_fmt_rm_frd_frs1)
+OP(fround_d, "fround.d", rv_codec_r_m, rv_fmt_rm_frd_frs1)
+OP(froundnx_d, "froundnx.d", rv_codec_r_m, rv_fmt_rm_frd_frs1)
+OP(fround_q, "fround.q", rv_codec_r_m, rv_fmt_rm_frd_frs1)
+OP(froundnx_q, "froundnx.q", rv_codec_r_m, rv_fmt_rm_frd_frs1)
+OP(fround_h, "fround.h", rv_codec_r_m, rv_fmt_rm_frd_frs1)
+OP(froundnx_h, "froundnx.h", rv_codec_r_m, rv_fmt_rm_frd_frs1)
+OP(fcvtmod_w_d, "fcvtmod.w.d", rv_codec_r_m, rv_fmt_rm_rd_frs1)
+OP(fmvh_x_d, "fmvh.x.d", rv_codec_r, rv_fmt_rd_frs1)
+OP(fmvp_d_x, "fmvp.d.x", rv_codec_r, rv_fmt_frd_rs1_rs2)
+OP(fmvh_x_q, "fmvh.x.q", rv_codec_r, rv_fmt_rd_frs1)
+OP(fmvp_q_x, "fmvp.q.x", rv_codec_r, rv_fmt_frd_rs1_rs2)
+OP(fleq_s, "fleq.s", rv_codec_r, rv_fmt_rd_frs1_frs2)
+OP(fltq_s, "fltq.s", rv_codec_r, rv_fmt_rd_frs1_frs2)
+OP(fleq_d, "fleq.d", rv_codec_r, rv_fmt_rd_frs1_frs2)
+OP(fltq_d, "fltq.d", rv_codec_r, rv_fmt_rd_frs1_frs2)
+OP(fleq_q, "fleq.q", rv_codec_r, rv_fmt_rd_frs1_frs2)
+OP(fltq_q, "fltq.q", rv_codec_r, rv_fmt_rd_frs1_frs2)
+OP(fleq_h, "fleq.h", rv_codec_r, rv_fmt_rd_frs1_frs2)
+OP(fltq_h, "fltq.h", rv_codec_r, rv_fmt_rd_frs1_frs2)
+OP(vaesdf_vv, "vaesdf.vv", rv_codec_v_r, rv_fmt_vd_vs2)
+OP(vaesdf_vs, "vaesdf.vs", rv_codec_v_r, rv_fmt_vd_vs2)
+OP(vaesdm_vv, "vaesdm.vv", rv_codec_v_r, rv_fmt_vd_vs2)
+OP(vaesdm_vs, "vaesdm.vs", rv_codec_v_r, rv_fmt_vd_vs2)
+OP(vaesef_vv, "vaesef.vv", rv_codec_v_r, rv_fmt_vd_vs2)
+OP(vaesef_vs, "vaesef.vs", rv_codec_v_r, rv_fmt_vd_vs2)
+OP(vaesem_vv, "vaesem.vv", rv_codec_v_r, rv_fmt_vd_vs2)
+OP(vaesem_vs, "vaesem.vs", rv_codec_v_r, rv_fmt_vd_vs2)
+OP(vaeskf1_vi, "vaeskf1.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm)
+OP(vaeskf2_vi, "vaeskf2.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm)
+OP(vaesz_vs, "vaesz.vs", rv_codec_v_r, rv_fmt_vd_vs2)
+OP(vandn_vv, "vandn.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vandn_vx, "vandn.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
+OP(vbrev_v, "vbrev.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
+OP(vbrev8_v, "vbrev8.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
+OP(vclmul_vv, "vclmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vclmul_vx, "vclmul.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
+OP(vclmulh_vv, "vclmulh.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vclmulh_vx, "vclmulh.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
+OP(vclz_v, "vclz.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
+OP(vcpop_v, "vcpop.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
+OP(vctz_v, "vctz.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
+OP(vghsh_vv, "vghsh.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1)
+OP(vgmul_vv, "vgmul.vv", rv_codec_v_r, rv_fmt_vd_vs2)
+OP(vrev8_v, "vrev8.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
+OP(vrol_vv, "vrol.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vrol_vx, "vrol.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
+OP(vror_vv, "vror.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vror_vx, "vror.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
+OP(vror_vi, "vror.vi", rv_codec_vror_vi, rv_fmt_vd_vs2_uimm_vm)
+OP(vsha2ch_vv, "vsha2ch.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1)
+OP(vsha2cl_vv, "vsha2cl.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1)
+OP(vsha2ms_vv, "vsha2ms.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1)
+OP(vsm3c_vi, "vsm3c.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm)
+OP(vsm3me_vv, "vsm3me.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1)
+OP(vsm4k_vi, "vsm4k.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm)
+OP(vsm4r_vv, "vsm4r.vv", rv_codec_v_r, rv_fmt_vd_vs2)
+OP(vsm4r_vs, "vsm4r.vs", rv_codec_v_r, rv_fmt_vd_vs2)
+OP(vwsll_vv, "vwsll.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vwsll_vx, "vwsll.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
+OP(vwsll_vi, "vwsll.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm)
+OP(amocas_w, "amocas.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
+OP(amocas_d, "amocas.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
+OP(amocas_q, "amocas.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
+OP(mop_r_0, "mop.r.0", rv_codec_r, rv_fmt_rd_rs1)
+OP(mop_r_1, "mop.r.1", rv_codec_r, rv_fmt_rd_rs1)
+OP(mop_r_2, "mop.r.2", rv_codec_r, rv_fmt_rd_rs1)
+OP(mop_r_3, "mop.r.3", rv_codec_r, rv_fmt_rd_rs1)
+OP(mop_r_4, "mop.r.4", rv_codec_r, rv_fmt_rd_rs1)
+OP(mop_r_5, "mop.r.5", rv_codec_r, rv_fmt_rd_rs1)
+OP(mop_r_6, "mop.r.6", rv_codec_r, rv_fmt_rd_rs1)
+OP(mop_r_7, "mop.r.7", rv_codec_r, rv_fmt_rd_rs1)
+OP(mop_r_8, "mop.r.8", rv_codec_r, rv_fmt_rd_rs1)
+OP(mop_r_9, "mop.r.9", rv_codec_r, rv_fmt_rd_rs1)
+OP(mop_r_10, "mop.r.10", rv_codec_r, rv_fmt_rd_rs1)
+OP(mop_r_11, "mop.r.11", rv_codec_r, rv_fmt_rd_rs1)
+OP(mop_r_12, "mop.r.12", rv_codec_r, rv_fmt_rd_rs1)
+OP(mop_r_13, "mop.r.13", rv_codec_r, rv_fmt_rd_rs1)
+OP(mop_r_14, "mop.r.14", rv_codec_r, rv_fmt_rd_rs1)
+OP(mop_r_15, "mop.r.15", rv_codec_r, rv_fmt_rd_rs1)
+OP(mop_r_16, "mop.r.16", rv_codec_r, rv_fmt_rd_rs1)
+OP(mop_r_17, "mop.r.17", rv_codec_r, rv_fmt_rd_rs1)
+OP(mop_r_18, "mop.r.18", rv_codec_r, rv_fmt_rd_rs1)
+OP(mop_r_19, "mop.r.19", rv_codec_r, rv_fmt_rd_rs1)
+OP(mop_r_20, "mop.r.20", rv_codec_r, rv_fmt_rd_rs1)
+OP(mop_r_21, "mop.r.21", rv_codec_r, rv_fmt_rd_rs1)
+OP(mop_r_22, "mop.r.22", rv_codec_r, rv_fmt_rd_rs1)
+OP(mop_r_23, "mop.r.23", rv_codec_r, rv_fmt_rd_rs1)
+OP(mop_r_24, "mop.r.24", rv_codec_r, rv_fmt_rd_rs1)
+OP(mop_r_25, "mop.r.25", rv_codec_r, rv_fmt_rd_rs1)
+OP(mop_r_26, "mop.r.26", rv_codec_r, rv_fmt_rd_rs1)
+OP(mop_r_27, "mop.r.27", rv_codec_r, rv_fmt_rd_rs1)
+OP(mop_r_28, "mop.r.28", rv_codec_r, rv_fmt_rd_rs1)
+OP(mop_r_29, "mop.r.29", rv_codec_r, rv_fmt_rd_rs1)
+OP(mop_r_30, "mop.r.30", rv_codec_r, rv_fmt_rd_rs1)
+OP(mop_r_31, "mop.r.31", rv_codec_r, rv_fmt_rd_rs1)
+OP(mop_rr_0, "mop.rr.0", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(mop_rr_1, "mop.rr.1", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(mop_rr_2, "mop.rr.2", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(mop_rr_3, "mop.rr.3", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(mop_rr_4, "mop.rr.4", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(mop_rr_5, "mop.rr.5", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(mop_rr_6, "mop.rr.6", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(mop_rr_7, "mop.rr.7", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(c_mop_1, "c.mop.1", rv_codec_ci_none, rv_fmt_none)
+OP(c_mop_3, "c.mop.3", rv_codec_ci_none, rv_fmt_none)
+OP(c_mop_5, "c.mop.5", rv_codec_ci_none, rv_fmt_none)
+OP(c_mop_7, "c.mop.7", rv_codec_ci_none, rv_fmt_none)
+OP(c_mop_9, "c.mop.9", rv_codec_ci_none, rv_fmt_none)
+OP(c_mop_11, "c.mop.11", rv_codec_ci_none, rv_fmt_none)
+OP(c_mop_13, "c.mop.13", rv_codec_ci_none, rv_fmt_none)
+OP(c_mop_15, "c.mop.15", rv_codec_ci_none, rv_fmt_none)
+OP(amoswap_b, "amoswap.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
+OP(amoadd_b, "amoadd.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
+OP(amoxor_b, "amoxor.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
+OP(amoor_b, "amoor.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
+OP(amoand_b, "amoand.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
+OP(amomin_b, "amomin.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
+OP(amomax_b, "amomax.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
+OP(amominu_b, "amominu.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
+OP(amomaxu_b, "amomaxu.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
+OP(amoswap_h, "amoswap.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
+OP(amoadd_h, "amoadd.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
+OP(amoxor_h, "amoxor.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
+OP(amoor_h, "amoor.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
+OP(amoand_h, "amoand.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
+OP(amomin_h, "amomin.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
+OP(amomax_h, "amomax.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
+OP(amominu_h, "amominu.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
+OP(amomaxu_h, "amomaxu.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
+OP(amocas_b, "amocas.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
+OP(amocas_h, "amocas.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
+OP(wrs_sto, "wrs.sto", rv_codec_none, rv_fmt_none)
+OP(wrs_nto, "wrs.nto", rv_codec_none, rv_fmt_none)
+OP(lpad, "lpad", rv_codec_lp, rv_fmt_imm)
+OP(sspush, "sspush", rv_codec_r, rv_fmt_rs2)
+OP(sspopchk, "sspopchk", rv_codec_r, rv_fmt_rs1)
+OP(ssrdp, "ssrdp", rv_codec_r, rv_fmt_rd)
+OP(ssamoswap_w, "ssamoswap.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
+OP(ssamoswap_d, "ssamoswap.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
+OP(c_sspush, "c.sspush", rv_codec_cmop_ss, NULL, DECOMP(rv_op_sspush))
+OP(c_sspopchk, "c.sspopchk", rv_codec_cmop_ss, NULL, DECOMP(rv_op_sspopchk))
+OP(cbo_inval, "cbo.inval", rv_codec_r, rv_fmt_rs1)
+OP(cbo_clean, "cbo.clean", rv_codec_r, rv_fmt_rs1)
+OP(cbo_flush, "cbo.flush", rv_codec_r, rv_fmt_rs1)
+OP(cbo_zero, "cbo.zero", rv_codec_r, rv_fmt_rs1)
+OP(mnret, "mnret", rv_codec_none, rv_fmt_none)
--
2.43.0
^ permalink raw reply related [flat|nested] 119+ messages in thread
* [PATCH 50/56] disas/riscv: Merge all mop.r.n to one pattern
2026-08-09 22:34 [RFC PATCH 00/56] disas/riscv: Reorganize the disassembler Richard Henderson
` (48 preceding siblings ...)
2026-08-09 22:35 ` [PATCH 49/56] disas/riscv: Split out riscv-op.c.inc Richard Henderson
@ 2026-08-09 22:35 ` Richard Henderson
2026-08-12 12:57 ` Alistair
2026-08-09 22:35 ` [PATCH 51/56] disas/riscv: Merge all mop.rr.n " Richard Henderson
` (5 subsequent siblings)
55 siblings, 1 reply; 119+ messages in thread
From: Richard Henderson @ 2026-08-09 22:35 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-riscv
Avoid performing arithmetic on rv_op_mop_r_0.
Treat the 'n' as an immediate.
Create a codec and format to match.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
disas/riscv.h | 2 ++
disas/riscv.c | 15 ++++++++++++++-
disas/riscv-op.c.inc | 33 +--------------------------------
3 files changed, 17 insertions(+), 33 deletions(-)
diff --git a/disas/riscv.h b/disas/riscv.h
index 5ac8c41616..b47a7f0150 100644
--- a/disas/riscv.h
+++ b/disas/riscv.h
@@ -160,6 +160,7 @@ typedef enum {
rv_codec_fli,
rv_codec_lp,
rv_codec_cmop_ss,
+ rv_codec_mop_r,
} rv_codec;
/* structures */
@@ -284,5 +285,6 @@ typedef struct {
#define rv_fmt_rd_rs1_immh_imml_addr "O\t0,(1),i,j"
#define rv_fmt_rd2_imm "O\t0,2,(1),i"
#define rv_fmt_fli "O\t3,h"
+#define rv_fmt_mop_r "O.i\t0,1"
#endif /* DISAS_RISCV_H */
diff --git a/disas/riscv.c b/disas/riscv.c
index 9dad56b486..450a5c8142 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -643,6 +643,13 @@ static uint32_t operand_lpl(rv_inst inst)
return extract32(inst, 12, 20);
}
+static uint32_t operand_mop_r_imm(rv_inst inst)
+{
+ return (extract32(inst, 30, 1) << 4) |
+ (extract32(inst, 26, 2) << 2) |
+ extract32(inst, 20, 2);
+}
+
/* instruction metadata */
static const rv_opcode_data rvi_opcode_data[] = {
@@ -2546,7 +2553,7 @@ static const rv_opcode_data *decode_inst_opcode(rv_decode *dec, rv_isa isa)
2, 2,
extract32(inst, 26, 2)),
4, 1, extract32(inst, 30, 1));
- op = rv_op_mop_r_0 + imm_mop5;
+ op = rv_op_mop_r;
/* if zicfiss enabled and mop5 is shadow stack */
if (dec->cfg->ext_zicfiss &&
((imm_mop5 & 0b11100) == 0b11100)) {
@@ -3049,6 +3056,11 @@ static void decode_inst_operands(rv_decode *dec, rv_isa isa,
dec->rs1 = dec->rs2 = operand_crs1(inst);
dec->imm = 0;
break;
+ case rv_codec_mop_r:
+ dec->rd = operand_rd(inst);
+ dec->rs1 = operand_rs1(inst);
+ dec->imm = operand_mop_r_imm(inst);
+ break;
default:
g_assert_not_reached();
}
@@ -3134,6 +3146,7 @@ static GString *format_inst(size_t tab, rv_decode *dec,
g_string_append(buf, op->name);
break;
case '(':
+ case '.':
case ',':
case ')':
case '-':
diff --git a/disas/riscv-op.c.inc b/disas/riscv-op.c.inc
index 3fe934688e..222d249a70 100644
--- a/disas/riscv-op.c.inc
+++ b/disas/riscv-op.c.inc
@@ -873,38 +873,7 @@ OP(vwsll_vi, "vwsll.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm)
OP(amocas_w, "amocas.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
OP(amocas_d, "amocas.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
OP(amocas_q, "amocas.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
-OP(mop_r_0, "mop.r.0", rv_codec_r, rv_fmt_rd_rs1)
-OP(mop_r_1, "mop.r.1", rv_codec_r, rv_fmt_rd_rs1)
-OP(mop_r_2, "mop.r.2", rv_codec_r, rv_fmt_rd_rs1)
-OP(mop_r_3, "mop.r.3", rv_codec_r, rv_fmt_rd_rs1)
-OP(mop_r_4, "mop.r.4", rv_codec_r, rv_fmt_rd_rs1)
-OP(mop_r_5, "mop.r.5", rv_codec_r, rv_fmt_rd_rs1)
-OP(mop_r_6, "mop.r.6", rv_codec_r, rv_fmt_rd_rs1)
-OP(mop_r_7, "mop.r.7", rv_codec_r, rv_fmt_rd_rs1)
-OP(mop_r_8, "mop.r.8", rv_codec_r, rv_fmt_rd_rs1)
-OP(mop_r_9, "mop.r.9", rv_codec_r, rv_fmt_rd_rs1)
-OP(mop_r_10, "mop.r.10", rv_codec_r, rv_fmt_rd_rs1)
-OP(mop_r_11, "mop.r.11", rv_codec_r, rv_fmt_rd_rs1)
-OP(mop_r_12, "mop.r.12", rv_codec_r, rv_fmt_rd_rs1)
-OP(mop_r_13, "mop.r.13", rv_codec_r, rv_fmt_rd_rs1)
-OP(mop_r_14, "mop.r.14", rv_codec_r, rv_fmt_rd_rs1)
-OP(mop_r_15, "mop.r.15", rv_codec_r, rv_fmt_rd_rs1)
-OP(mop_r_16, "mop.r.16", rv_codec_r, rv_fmt_rd_rs1)
-OP(mop_r_17, "mop.r.17", rv_codec_r, rv_fmt_rd_rs1)
-OP(mop_r_18, "mop.r.18", rv_codec_r, rv_fmt_rd_rs1)
-OP(mop_r_19, "mop.r.19", rv_codec_r, rv_fmt_rd_rs1)
-OP(mop_r_20, "mop.r.20", rv_codec_r, rv_fmt_rd_rs1)
-OP(mop_r_21, "mop.r.21", rv_codec_r, rv_fmt_rd_rs1)
-OP(mop_r_22, "mop.r.22", rv_codec_r, rv_fmt_rd_rs1)
-OP(mop_r_23, "mop.r.23", rv_codec_r, rv_fmt_rd_rs1)
-OP(mop_r_24, "mop.r.24", rv_codec_r, rv_fmt_rd_rs1)
-OP(mop_r_25, "mop.r.25", rv_codec_r, rv_fmt_rd_rs1)
-OP(mop_r_26, "mop.r.26", rv_codec_r, rv_fmt_rd_rs1)
-OP(mop_r_27, "mop.r.27", rv_codec_r, rv_fmt_rd_rs1)
-OP(mop_r_28, "mop.r.28", rv_codec_r, rv_fmt_rd_rs1)
-OP(mop_r_29, "mop.r.29", rv_codec_r, rv_fmt_rd_rs1)
-OP(mop_r_30, "mop.r.30", rv_codec_r, rv_fmt_rd_rs1)
-OP(mop_r_31, "mop.r.31", rv_codec_r, rv_fmt_rd_rs1)
+OP(mop_r, "mop.r", rv_codec_mop_r, rv_fmt_mop_r)
OP(mop_rr_0, "mop.rr.0", rv_codec_r, rv_fmt_rd_rs1_rs2)
OP(mop_rr_1, "mop.rr.1", rv_codec_r, rv_fmt_rd_rs1_rs2)
OP(mop_rr_2, "mop.rr.2", rv_codec_r, rv_fmt_rd_rs1_rs2)
--
2.43.0
^ permalink raw reply related [flat|nested] 119+ messages in thread
* [PATCH 51/56] disas/riscv: Merge all mop.rr.n to one pattern
2026-08-09 22:34 [RFC PATCH 00/56] disas/riscv: Reorganize the disassembler Richard Henderson
` (49 preceding siblings ...)
2026-08-09 22:35 ` [PATCH 50/56] disas/riscv: Merge all mop.r.n to one pattern Richard Henderson
@ 2026-08-09 22:35 ` Richard Henderson
2026-08-12 12:57 ` Alistair
2026-08-09 22:35 ` [PATCH 52/56] disas/riscv: Merge all c.mop.n " Richard Henderson
` (4 subsequent siblings)
55 siblings, 1 reply; 119+ messages in thread
From: Richard Henderson @ 2026-08-09 22:35 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-riscv
Avoid performing arithmetic on rv_op_mop_rr_0.
Treat the 'n' as an immediate.
Create a codec and format to match.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
disas/riscv.h | 2 ++
disas/riscv.c | 13 ++++++++++++-
disas/riscv-op.c.inc | 9 +--------
3 files changed, 15 insertions(+), 9 deletions(-)
diff --git a/disas/riscv.h b/disas/riscv.h
index b47a7f0150..47647f750f 100644
--- a/disas/riscv.h
+++ b/disas/riscv.h
@@ -161,6 +161,7 @@ typedef enum {
rv_codec_lp,
rv_codec_cmop_ss,
rv_codec_mop_r,
+ rv_codec_mop_rr,
} rv_codec;
/* structures */
@@ -286,5 +287,6 @@ typedef struct {
#define rv_fmt_rd2_imm "O\t0,2,(1),i"
#define rv_fmt_fli "O\t3,h"
#define rv_fmt_mop_r "O.i\t0,1"
+#define rv_fmt_mop_rr "O.i\t0,1,2"
#endif /* DISAS_RISCV_H */
diff --git a/disas/riscv.c b/disas/riscv.c
index 450a5c8142..6ec62a5830 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -650,6 +650,11 @@ static uint32_t operand_mop_r_imm(rv_inst inst)
extract32(inst, 20, 2);
}
+static uint32_t operand_mop_rr_imm(rv_inst inst)
+{
+ return (extract32(inst, 30, 1) << 2) | extract32(inst, 26, 2);
+}
+
/* instruction metadata */
static const rv_opcode_data rvi_opcode_data[] = {
@@ -2572,7 +2577,7 @@ static const rv_opcode_data *decode_inst_opcode(rv_decode *dec, rv_isa isa)
== 0b1000001) {
imm_mop3 = deposit32(extract32(inst, 26, 2),
2, 1, extract32(inst, 30, 1));
- op = rv_op_mop_rr_0 + imm_mop3;
+ op = rv_op_mop_rr;
/* if zicfiss enabled and mop3 is shadow stack */
if (dec->cfg->ext_zicfiss &&
((imm_mop3 & 0b111) == 0b111)) {
@@ -3061,6 +3066,12 @@ static void decode_inst_operands(rv_decode *dec, rv_isa isa,
dec->rs1 = operand_rs1(inst);
dec->imm = operand_mop_r_imm(inst);
break;
+ case rv_codec_mop_rr:
+ dec->rd = operand_rd(inst);
+ dec->rs1 = operand_rs1(inst);
+ dec->rs2 = operand_rs2(inst);
+ dec->imm = operand_mop_rr_imm(inst);
+ break;
default:
g_assert_not_reached();
}
diff --git a/disas/riscv-op.c.inc b/disas/riscv-op.c.inc
index 222d249a70..2100e54475 100644
--- a/disas/riscv-op.c.inc
+++ b/disas/riscv-op.c.inc
@@ -874,14 +874,7 @@ OP(amocas_w, "amocas.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
OP(amocas_d, "amocas.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
OP(amocas_q, "amocas.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
OP(mop_r, "mop.r", rv_codec_mop_r, rv_fmt_mop_r)
-OP(mop_rr_0, "mop.rr.0", rv_codec_r, rv_fmt_rd_rs1_rs2)
-OP(mop_rr_1, "mop.rr.1", rv_codec_r, rv_fmt_rd_rs1_rs2)
-OP(mop_rr_2, "mop.rr.2", rv_codec_r, rv_fmt_rd_rs1_rs2)
-OP(mop_rr_3, "mop.rr.3", rv_codec_r, rv_fmt_rd_rs1_rs2)
-OP(mop_rr_4, "mop.rr.4", rv_codec_r, rv_fmt_rd_rs1_rs2)
-OP(mop_rr_5, "mop.rr.5", rv_codec_r, rv_fmt_rd_rs1_rs2)
-OP(mop_rr_6, "mop.rr.6", rv_codec_r, rv_fmt_rd_rs1_rs2)
-OP(mop_rr_7, "mop.rr.7", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(mop_rr, "mop.rr", rv_codec_mop_rr, rv_fmt_mop_rr)
OP(c_mop_1, "c.mop.1", rv_codec_ci_none, rv_fmt_none)
OP(c_mop_3, "c.mop.3", rv_codec_ci_none, rv_fmt_none)
OP(c_mop_5, "c.mop.5", rv_codec_ci_none, rv_fmt_none)
--
2.43.0
^ permalink raw reply related [flat|nested] 119+ messages in thread
* [PATCH 52/56] disas/riscv: Merge all c.mop.n to one pattern
2026-08-09 22:34 [RFC PATCH 00/56] disas/riscv: Reorganize the disassembler Richard Henderson
` (50 preceding siblings ...)
2026-08-09 22:35 ` [PATCH 51/56] disas/riscv: Merge all mop.rr.n " Richard Henderson
@ 2026-08-09 22:35 ` Richard Henderson
2026-08-12 12:58 ` Alistair
2026-08-09 22:35 ` [PATCH 53/56] disas/riscv: Tidy decode of c.mop.n Richard Henderson
` (3 subsequent siblings)
55 siblings, 1 reply; 119+ messages in thread
From: Richard Henderson @ 2026-08-09 22:35 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-riscv
Avoid performing arithmetic on rv_op_c_mop_1.
Treat the 'n' as an immediate.
Create a codec and format to match.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
disas/riscv.h | 2 ++
disas/riscv.c | 10 +++++++++-
disas/riscv-op.c.inc | 9 +--------
3 files changed, 12 insertions(+), 9 deletions(-)
diff --git a/disas/riscv.h b/disas/riscv.h
index 47647f750f..b0269bb709 100644
--- a/disas/riscv.h
+++ b/disas/riscv.h
@@ -159,6 +159,7 @@ typedef enum {
rv_codec_r2_imm2_imm5,
rv_codec_fli,
rv_codec_lp,
+ rv_codec_cmop,
rv_codec_cmop_ss,
rv_codec_mop_r,
rv_codec_mop_rr,
@@ -286,6 +287,7 @@ typedef struct {
#define rv_fmt_rd_rs1_immh_imml_addr "O\t0,(1),i,j"
#define rv_fmt_rd2_imm "O\t0,2,(1),i"
#define rv_fmt_fli "O\t3,h"
+#define rv_fmt_cmop "O.i"
#define rv_fmt_mop_r "O.i\t0,1"
#define rv_fmt_mop_rr "O.i\t0,1,2"
diff --git a/disas/riscv.c b/disas/riscv.c
index 6ec62a5830..89c2e63941 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -643,6 +643,11 @@ static uint32_t operand_lpl(rv_inst inst)
return extract32(inst, 12, 20);
}
+static uint32_t operand_cmop_imm(rv_inst inst)
+{
+ return extract32(inst, 8, 3) * 2 + 1;
+}
+
static uint32_t operand_mop_r_imm(rv_inst inst)
{
return (extract32(inst, 30, 1) << 4) |
@@ -1027,7 +1032,7 @@ static const rv_opcode_data *decode_inst_opcode(rv_decode *dec, rv_isa isa)
(((inst >> 11) & 0b11) == 0b0)) {
unsigned int cmop_code = 0;
cmop_code = ((inst >> 8) & 0b111);
- op = rv_op_c_mop_1 + cmop_code;
+ op = rv_op_c_mop;
if (dec->cfg->ext_zicfiss) {
op = (cmop_code == 0) ? rv_op_c_sspush : op;
op = (cmop_code == 2) ? rv_op_c_sspopchk : op;
@@ -3056,6 +3061,9 @@ static void decode_inst_operands(rv_decode *dec, rv_isa isa,
case rv_codec_lp:
dec->imm = operand_lpl(inst);
break;
+ case rv_codec_cmop:
+ dec->imm = operand_cmop_imm(inst);
+ break;
case rv_codec_cmop_ss:
dec->rd = rv_ireg_zero;
dec->rs1 = dec->rs2 = operand_crs1(inst);
diff --git a/disas/riscv-op.c.inc b/disas/riscv-op.c.inc
index 2100e54475..802a521bca 100644
--- a/disas/riscv-op.c.inc
+++ b/disas/riscv-op.c.inc
@@ -875,14 +875,7 @@ OP(amocas_d, "amocas.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
OP(amocas_q, "amocas.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
OP(mop_r, "mop.r", rv_codec_mop_r, rv_fmt_mop_r)
OP(mop_rr, "mop.rr", rv_codec_mop_rr, rv_fmt_mop_rr)
-OP(c_mop_1, "c.mop.1", rv_codec_ci_none, rv_fmt_none)
-OP(c_mop_3, "c.mop.3", rv_codec_ci_none, rv_fmt_none)
-OP(c_mop_5, "c.mop.5", rv_codec_ci_none, rv_fmt_none)
-OP(c_mop_7, "c.mop.7", rv_codec_ci_none, rv_fmt_none)
-OP(c_mop_9, "c.mop.9", rv_codec_ci_none, rv_fmt_none)
-OP(c_mop_11, "c.mop.11", rv_codec_ci_none, rv_fmt_none)
-OP(c_mop_13, "c.mop.13", rv_codec_ci_none, rv_fmt_none)
-OP(c_mop_15, "c.mop.15", rv_codec_ci_none, rv_fmt_none)
+OP(c_mop, "c.mop", rv_codec_cmop, rv_fmt_cmop)
OP(amoswap_b, "amoswap.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
OP(amoadd_b, "amoadd.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
OP(amoxor_b, "amoxor.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
--
2.43.0
^ permalink raw reply related [flat|nested] 119+ messages in thread
* [PATCH 53/56] disas/riscv: Tidy decode of c.mop.n
2026-08-09 22:34 [RFC PATCH 00/56] disas/riscv: Reorganize the disassembler Richard Henderson
` (51 preceding siblings ...)
2026-08-09 22:35 ` [PATCH 52/56] disas/riscv: Merge all c.mop.n " Richard Henderson
@ 2026-08-09 22:35 ` Richard Henderson
2026-08-12 12:59 ` Alistair
2026-08-09 22:35 ` [PATCH 54/56] disas/riscv: Tidy decode of mop.r.n and mop.rr.n Richard Henderson
` (2 subsequent siblings)
55 siblings, 1 reply; 119+ messages in thread
From: Richard Henderson @ 2026-08-09 22:35 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-riscv
Merge nested if's.
Reuse operand_cmop_imm for zicfiss decode.
Return pointers directly.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
disas/riscv.c | 19 +++++++++----------
1 file changed, 9 insertions(+), 10 deletions(-)
diff --git a/disas/riscv.c b/disas/riscv.c
index 89c2e63941..9682e6f5a5 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -1027,18 +1027,17 @@ static const rv_opcode_data *decode_inst_opcode(rv_decode *dec, rv_isa isa)
break;
case 2: op = rv_op_c_li; break;
case 3:
- if (dec->cfg && dec->cfg->ext_zcmop) {
- if ((((inst >> 2) & 0b111111) == 0b100000) &&
- (((inst >> 11) & 0b11) == 0b0)) {
- unsigned int cmop_code = 0;
- cmop_code = ((inst >> 8) & 0b111);
- op = rv_op_c_mop;
- if (dec->cfg->ext_zicfiss) {
- op = (cmop_code == 0) ? rv_op_c_sspush : op;
- op = (cmop_code == 2) ? rv_op_c_sspopchk : op;
+ if (dec->cfg
+ && dec->cfg->ext_zcmop
+ && ((inst >> 2) & 0b111111) == 0b100000
+ && ((inst >> 11) & 0b11) == 0) {
+ if (dec->cfg->ext_zicfiss) {
+ switch (operand_cmop_imm(inst)) {
+ case 1: return &rvi_opcode_data[rv_op_c_sspush];
+ case 5: return &rvi_opcode_data[rv_op_c_sspopchk];
}
- break;
}
+ return &rvi_opcode_data[rv_op_c_mop];
}
if (inst & ((1 << 12) | (0x1f << 2))) {
switch ((inst >> 7) & 0b11111) {
--
2.43.0
^ permalink raw reply related [flat|nested] 119+ messages in thread
* [PATCH 54/56] disas/riscv: Tidy decode of mop.r.n and mop.rr.n
2026-08-09 22:34 [RFC PATCH 00/56] disas/riscv: Reorganize the disassembler Richard Henderson
` (52 preceding siblings ...)
2026-08-09 22:35 ` [PATCH 53/56] disas/riscv: Tidy decode of c.mop.n Richard Henderson
@ 2026-08-09 22:35 ` Richard Henderson
2026-08-12 13:00 ` Alistair
2026-08-09 22:35 ` [PATCH 55/56] disas/riscv: Split rvi_opcode_data Richard Henderson
2026-08-09 22:35 ` [PATCH 56/56] disas/riscv: Sort riscv-op.c.inc Richard Henderson
55 siblings, 1 reply; 119+ messages in thread
From: Richard Henderson @ 2026-08-09 22:35 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-riscv
Merge nested if's.
Reuse operand_mop_{r,rr}_imm for zicfiss decode.
Return pointers directly.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
disas/riscv.c | 59 +++++++++++++++++++++------------------------------
1 file changed, 24 insertions(+), 35 deletions(-)
diff --git a/disas/riscv.c b/disas/riscv.c
index 9682e6f5a5..94d1ed1e20 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -2555,44 +2555,33 @@ static const rv_opcode_data *decode_inst_opcode(rv_decode *dec, rv_isa isa)
case 3: op = rv_op_csrrc; break;
case 4:
if (dec->cfg && dec->cfg->ext_zimop) {
- int imm_mop5, imm_mop3, reg_num;
- if ((extract32(inst, 22, 10) & 0b1011001111)
- == 0b1000000111) {
- imm_mop5 = deposit32(deposit32(extract32(inst, 20, 2),
- 2, 2,
- extract32(inst, 26, 2)),
- 4, 1, extract32(inst, 30, 1));
- op = rv_op_mop_r;
- /* if zicfiss enabled and mop5 is shadow stack */
- if (dec->cfg->ext_zicfiss &&
- ((imm_mop5 & 0b11100) == 0b11100)) {
- /* rs1=0 means ssrdp */
- if ((inst & (0b011111 << 15)) == 0) {
- op = rv_op_ssrdp;
- }
- /* rd=0 means sspopchk */
- reg_num = (inst >> 15) & 0b011111;
- if (((inst & (0b011111 << 7)) == 0) &&
- ((reg_num == 1) || (reg_num == 5))) {
- op = rv_op_sspopchk;
+ if (((inst >> 22) & 0b1011001111) == 0b1000000111) {
+ if (dec->cfg->ext_zicfiss
+ && operand_mop_r_imm(inst) == 28) {
+ switch (operand_rs1(inst)) {
+ case 0:
+ return &rvi_opcode_data[rv_op_ssrdp];
+ case 1:
+ case 5:
+ if (operand_rd(inst) == 0) {
+ return &rvi_opcode_data[rv_op_sspopchk];
}
+ }
}
- } else if ((extract32(inst, 25, 7) & 0b1011001)
- == 0b1000001) {
- imm_mop3 = deposit32(extract32(inst, 26, 2),
- 2, 1, extract32(inst, 30, 1));
- op = rv_op_mop_rr;
- /* if zicfiss enabled and mop3 is shadow stack */
- if (dec->cfg->ext_zicfiss &&
- ((imm_mop3 & 0b111) == 0b111)) {
- /* rs1=0 and rd=0 means sspush */
- reg_num = (inst >> 20) & 0b011111;
- if (((inst & (0b011111 << 15)) == 0) &&
- ((inst & (0b011111 << 7)) == 0) &&
- ((reg_num == 1) || (reg_num == 5))) {
- op = rv_op_sspush;
- }
+ return &rvi_opcode_data[rv_op_mop_r];
+ }
+ if (((inst >> 25) & 0b1011001) == 0b1000001) {
+ if (dec->cfg->ext_zicfiss
+ && operand_mop_rr_imm(inst) == 7
+ && operand_rd(inst) == 0
+ && operand_rs1(inst) == 0) {
+ switch (operand_rs2(inst)) {
+ case 1:
+ case 5:
+ return &rvi_opcode_data[rv_op_sspush];
+ }
}
+ return &rvi_opcode_data[rv_op_mop_rr];
}
}
break;
--
2.43.0
^ permalink raw reply related [flat|nested] 119+ messages in thread
* [PATCH 55/56] disas/riscv: Split rvi_opcode_data
2026-08-09 22:34 [RFC PATCH 00/56] disas/riscv: Reorganize the disassembler Richard Henderson
` (53 preceding siblings ...)
2026-08-09 22:35 ` [PATCH 54/56] disas/riscv: Tidy decode of mop.r.n and mop.rr.n Richard Henderson
@ 2026-08-09 22:35 ` Richard Henderson
2026-08-12 13:02 ` Alistair
2026-08-09 22:35 ` [PATCH 56/56] disas/riscv: Sort riscv-op.c.inc Richard Henderson
55 siblings, 1 reply; 119+ messages in thread
From: Richard Henderson @ 2026-08-09 22:35 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-riscv
Generate separate objects for OP() instead of collecting in a table.
Return pointers to objects directly.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
disas/riscv.c | 1981 +++++++++++++++++++++---------------------
disas/riscv-op.c.inc | 94 +-
2 files changed, 1048 insertions(+), 1027 deletions(-)
diff --git a/disas/riscv.c b/disas/riscv.c
index 94d1ed1e20..586857502a 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -28,12 +28,6 @@
#include "disas/riscv-xventana.h"
#include "disas/riscv-xlrbr.h"
-typedef enum {
-#define OP(N, ...) rv_op_##N,
-#include "riscv-op.c.inc"
-#undef OP
-} rv_op;
-
/* register names */
static const char rv_ireg_name_sym[32][5] = {
@@ -113,140 +107,143 @@ static const rvc_constraint rvcc_true[] = { rvc_end };
/* pseudo-instruction metadata */
-static const rv_opcode_data rvi_opcode_data[];
+/* Forward declare the all the opcodes so that we may link them. */
+#define OP(N, ...) static const rv_opcode_data op_##N;
+#include "riscv-op.c.inc"
+#undef OP
static const rv_comp_data rvcp_jal[] = {
- { &rvi_opcode_data[rv_op_j], rvcc_j },
- { &rvi_opcode_data[rv_op_jal_ra], rvcc_jal_ra },
+ { &op_j, rvcc_j },
+ { &op_jal_ra, rvcc_jal_ra },
{ },
};
static const rv_comp_data rvcp_jalr[] = {
- { &rvi_opcode_data[rv_op_jr], rvcc_jr },
- { &rvi_opcode_data[rv_op_jalr_ra], rvcc_jalr_ra },
+ { &op_jr, rvcc_jr },
+ { &op_jalr_ra, rvcc_jalr_ra },
{ },
};
static const rv_comp_data rvcp_jr[] = {
- { &rvi_opcode_data[rv_op_ret], rvcc_ret },
+ { &op_ret, rvcc_ret },
{ },
};
static const rv_comp_data rvcp_beq[] = {
- { &rvi_opcode_data[rv_op_beqz], rvcc_beqz },
+ { &op_beqz, rvcc_beqz },
{ },
};
static const rv_comp_data rvcp_bne[] = {
- { &rvi_opcode_data[rv_op_bnez], rvcc_bnez },
+ { &op_bnez, rvcc_bnez },
{ },
};
static const rv_comp_data rvcp_blt[] = {
- { &rvi_opcode_data[rv_op_bltz], rvcc_bltz },
- { &rvi_opcode_data[rv_op_bgtz], rvcc_bgtz },
+ { &op_bltz, rvcc_bltz },
+ { &op_bgtz, rvcc_bgtz },
{ },
};
static const rv_comp_data rvcp_bge[] = {
- { &rvi_opcode_data[rv_op_blez], rvcc_blez },
- { &rvi_opcode_data[rv_op_bgez], rvcc_bgez },
+ { &op_blez, rvcc_blez },
+ { &op_bgez, rvcc_bgez },
{ },
};
static const rv_comp_data rvcp_addi[] = {
- { &rvi_opcode_data[rv_op_mv], rvcc_mv },
+ { &op_mv, rvcc_mv },
{ },
};
static const rv_comp_data rvcp_mv[] = {
- { &rvi_opcode_data[rv_op_nop], rvcc_nop },
+ { &op_nop, rvcc_nop },
{ },
};
static const rv_comp_data rvcp_sltiu[] = {
- { &rvi_opcode_data[rv_op_seqz], rvcc_seqz },
+ { &op_seqz, rvcc_seqz },
{ },
};
static const rv_comp_data rvcp_xori[] = {
- { &rvi_opcode_data[rv_op_not], rvcc_not },
+ { &op_not, rvcc_not },
{ },
};
static const rv_comp_data rvcp_sub[] = {
- { &rvi_opcode_data[rv_op_neg], rvcc_neg },
+ { &op_neg, rvcc_neg },
{ },
};
static const rv_comp_data rvcp_slt[] = {
- { &rvi_opcode_data[rv_op_sltz], rvcc_sltz },
- { &rvi_opcode_data[rv_op_sgtz], rvcc_sgtz },
+ { &op_sltz, rvcc_sltz },
+ { &op_sgtz, rvcc_sgtz },
{ },
};
static const rv_comp_data rvcp_sltu[] = {
- { &rvi_opcode_data[rv_op_snez], rvcc_snez },
+ { &op_snez, rvcc_snez },
{ },
};
static const rv_comp_data rvcp_addiw[] = {
- { &rvi_opcode_data[rv_op_sext_w], rvcc_sext_w },
+ { &op_sext_w, rvcc_sext_w },
{ },
};
static const rv_comp_data rvcp_subw[] = {
- { &rvi_opcode_data[rv_op_negw], rvcc_negw },
+ { &op_negw, rvcc_negw },
{ },
};
static const rv_comp_data rvcp_fsgnj_s[] = {
- { &rvi_opcode_data[rv_op_fmv_s], rvcc_fmv_s },
+ { &op_fmv_s, rvcc_fmv_s },
{ },
};
static const rv_comp_data rvcp_fsgnjn_s[] = {
- { &rvi_opcode_data[rv_op_fneg_s], rvcc_fneg_s },
+ { &op_fneg_s, rvcc_fneg_s },
{ },
};
static const rv_comp_data rvcp_fsgnjx_s[] = {
- { &rvi_opcode_data[rv_op_fabs_s], rvcc_fabs_s },
+ { &op_fabs_s, rvcc_fabs_s },
{ },
};
static const rv_comp_data rvcp_fsgnj_d[] = {
- { &rvi_opcode_data[rv_op_fmv_d], rvcc_fmv_d },
+ { &op_fmv_d, rvcc_fmv_d },
{ },
};
static const rv_comp_data rvcp_fsgnjn_d[] = {
- { &rvi_opcode_data[rv_op_fneg_d], rvcc_fneg_d },
+ { &op_fneg_d, rvcc_fneg_d },
{ },
};
static const rv_comp_data rvcp_fsgnjx_d[] = {
- { &rvi_opcode_data[rv_op_fabs_d], rvcc_fabs_d },
+ { &op_fabs_d, rvcc_fabs_d },
{ },
};
static const rv_comp_data rvcp_fsgnj_q[] = {
- { &rvi_opcode_data[rv_op_fmv_q], rvcc_fmv_q },
+ { &op_fmv_q, rvcc_fmv_q },
{ },
};
static const rv_comp_data rvcp_fsgnjn_q[] = {
- { &rvi_opcode_data[rv_op_fneg_q], rvcc_fneg_q },
+ { &op_fneg_q, rvcc_fneg_q },
{ },
};
static const rv_comp_data rvcp_fsgnjx_q[] = {
- { &rvi_opcode_data[rv_op_fabs_q], rvcc_fabs_q },
+ { &op_fabs_q, rvcc_fabs_q },
{ },
};
/* Convert compressed insns into normal insns via pseudo expansion. */
-#define DECOMP(X) (static const rv_comp_data[1]){ { &rvi_opcode_data[X], rvcc_true } }
+#define DECOMP(X) (static const rv_comp_data[1]){ { &X, rvcc_true } }
/* operand extractors */
@@ -662,11 +659,9 @@ static uint32_t operand_mop_rr_imm(rv_inst inst)
/* instruction metadata */
-static const rv_opcode_data rvi_opcode_data[] = {
-#define OP(N, ...) { __VA_ARGS__ },
+#define OP(N, ...) static const rv_opcode_data op_##N = { __VA_ARGS__ };
#include "riscv-op.c.inc"
#undef OP
-};
/* CSR names */
@@ -953,79 +948,65 @@ static const char *csr_name(int csrno)
static const rv_opcode_data *decode_inst_opcode(rv_decode *dec, rv_isa isa)
{
rv_inst inst = dec->inst;
- rv_opcode op = rv_op_illegal;
switch ((inst >> 0) & 0b11) {
case 0:
switch ((inst >> 13) & 0b111) {
case 0:
if ((inst >> 5) & 0xff) {
- op = rv_op_c_addi4spn;
+ return &op_c_addi4spn;
}
break;
case 1:
if (isa == rv128) {
- op = rv_op_c_lq;
- } else {
- op = rv_op_c_fld;
+ return &op_c_lq;
}
- break;
- case 2: op = rv_op_c_lw; break;
+ return &op_c_fld;
+ case 2: return &op_c_lw;
case 3:
if (isa == rv32) {
- op = rv_op_c_flw;
- } else {
- op = rv_op_c_ld;
+ return &op_c_flw;
}
- break;
+ return &op_c_ld;
case 4:
switch ((inst >> 10) & 0b111) {
- case 0: op = rv_op_c_lbu; break;
+ case 0: return &op_c_lbu;
case 1:
if (((inst >> 6) & 1) == 0) {
- op = rv_op_c_lhu;
- } else {
- op = rv_op_c_lh;
+ return &op_c_lhu;
}
- break;
- case 2: op = rv_op_c_sb; break;
+ return &op_c_lh;
+ case 2: return &op_c_sb;
case 3:
if (((inst >> 6) & 1) == 0) {
- op = rv_op_c_sh;
+ return &op_c_sh;
}
break;
}
break;
case 5:
if (isa == rv128) {
- op = rv_op_c_sq;
- } else {
- op = rv_op_c_fsd;
+ return &op_c_sq;
}
- break;
- case 6: op = rv_op_c_sw; break;
+ return &op_c_fsd;
+ case 6: return &op_c_sw;
case 7:
if (isa == rv32) {
- op = rv_op_c_fsw;
- } else {
- op = rv_op_c_sd;
+ return &op_c_fsw;
}
- break;
+ return &op_c_sd;
}
break;
case 1:
switch ((inst >> 13) & 0b111) {
case 0:
- op = rv_op_c_addi; /* or unspecified HINT */
- break;
+ return &op_c_addi; /* or unspecified HINT */
case 1:
if (isa == rv32) {
- op = rv_op_c_jal;
- } else {
- op = rv_op_c_addiw;
+ return &op_c_jal;
}
- break;
- case 2: op = rv_op_c_li; break;
+ return &op_c_addiw;
+ case 2: return &op_c_li;
case 3:
if (dec->cfg
&& dec->cfg->ext_zcmop
@@ -1033,16 +1014,16 @@ static const rv_opcode_data *decode_inst_opcode(rv_decode *dec, rv_isa isa)
&& ((inst >> 11) & 0b11) == 0) {
if (dec->cfg->ext_zicfiss) {
switch (operand_cmop_imm(inst)) {
- case 1: return &rvi_opcode_data[rv_op_c_sspush];
- case 5: return &rvi_opcode_data[rv_op_c_sspopchk];
+ case 1: return &op_c_sspush;
+ case 5: return &op_c_sspopchk;
}
}
- return &rvi_opcode_data[rv_op_c_mop];
+ return &op_c_mop;
}
if (inst & ((1 << 12) | (0x1f << 2))) {
switch ((inst >> 7) & 0b11111) {
- case 2: op = rv_op_c_addi16sp; break;
- default: op = rv_op_c_lui; break;
+ case 2: return &op_c_addi16sp;
+ default: return &op_c_lui;
}
}
break;
@@ -1051,261 +1032,252 @@ static const rv_opcode_data *decode_inst_opcode(rv_decode *dec, rv_isa isa)
case 0:
/* For rv32, shamt[5]=1 is designated for custom extensions. */
if (isa != rv32 || (inst & 0x1000) == 0) {
- op = rv_op_c_srli; /* or unspecified HINT */
+ return &op_c_srli; /* or unspecified HINT */
}
break;
case 1:
/* For rv32, shamt[5]=1 is designated for custom extensions. */
if (isa != rv32 || (inst & 0x1000) == 0) {
- op = rv_op_c_srai; /* or unspecified HINT */
+ return &op_c_srai; /* or unspecified HINT */
}
break;
- case 2: op = rv_op_c_andi; break;
+ case 2: return &op_c_andi;
case 3:
switch (((inst >> 10) & 0b100) | ((inst >> 5) & 0b011)) {
- case 0: op = rv_op_c_sub; break;
- case 1: op = rv_op_c_xor; break;
- case 2: op = rv_op_c_or; break;
- case 3: op = rv_op_c_and; break;
+ case 0: return &op_c_sub;
+ case 1: return &op_c_xor;
+ case 2: return &op_c_or;
+ case 3: return &op_c_and;
case 4:
if (isa != rv32) {
- op = rv_op_c_subw;
+ return &op_c_subw;
}
break;
case 5:
if (isa != rv32) {
- op = rv_op_c_addw;
+ return &op_c_addw;
}
break;
- case 6: op = rv_op_c_mul; break;
+ case 6: return &op_c_mul;
case 7:
switch ((inst >> 2) & 0b111) {
- case 0: op = rv_op_c_zext_b; break;
- case 1: op = rv_op_c_sext_b; break;
- case 2: op = rv_op_c_zext_h; break;
- case 3: op = rv_op_c_sext_h; break;
- case 4: op = rv_op_c_zext_w; break;
- case 5: op = rv_op_c_not; break;
+ case 0: return &op_c_zext_b;
+ case 1: return &op_c_sext_b;
+ case 2: return &op_c_zext_h;
+ case 3: return &op_c_sext_h;
+ case 4: return &op_c_zext_w;
+ case 5: return &op_c_not;
}
break;
}
break;
}
break;
- case 5: op = rv_op_c_j; break;
- case 6: op = rv_op_c_beqz; break;
- case 7: op = rv_op_c_bnez; break;
+ case 5: return &op_c_j;
+ case 6: return &op_c_beqz;
+ case 7: return &op_c_bnez;
}
break;
case 2:
switch ((inst >> 13) & 0b111) {
case 0:
if (isa != rv32 || (inst & 0x1000) == 0) {
- op = rv_op_c_slli; /* or unspecified HINT */
+ return &op_c_slli; /* or unspecified HINT */
}
break;
case 1:
if (isa == rv128) {
- op = rv_op_c_lqsp;
- } else {
- op = rv_op_c_fldsp;
+ return &op_c_lqsp;
}
- break;
- case 2: op = rv_op_c_lwsp; break;
+ return &op_c_fldsp;
+ case 2: return &op_c_lwsp;
case 3:
if (isa == rv32) {
- op = rv_op_c_flwsp;
- } else {
- op = rv_op_c_ldsp;
+ return &op_c_flwsp;
}
- break;
+ return &op_c_ldsp;
case 4:
switch ((inst >> 12) & 0b1) {
case 0:
switch ((inst >> 2) & 0b11111) {
- case 0: op = rv_op_c_jr; break;
- default: op = rv_op_c_mv; break;
+ case 0: return &op_c_jr;
+ default: return &op_c_mv;
}
break;
case 1:
switch ((inst >> 2) & 0b11111) {
case 0:
switch ((inst >> 7) & 0b11111) {
- case 0: op = rv_op_c_ebreak; break;
- default: op = rv_op_c_jalr; break;
+ case 0: return &op_c_ebreak;
+ default: return &op_c_jalr;
}
break;
- default: op = rv_op_c_add; break;
+ default: return &op_c_add;
}
break;
}
break;
case 5:
if (isa == rv128) {
- op = rv_op_c_sqsp;
- } else {
- op = rv_op_c_fsdsp;
- if (dec->cfg && dec->cfg->ext_zcmp && ((inst >> 12) & 0b01)) {
+ return &op_c_sqsp;
+ }
+ if (dec->cfg) {
+ if (dec->cfg->ext_zcmp && ((inst >> 12) & 0b01)) {
switch ((inst >> 8) & 0b01111) {
case 8:
if (((inst >> 4) & 0b01111) >= 4) {
- op = rv_op_cm_push;
+ return &op_cm_push;
}
break;
case 10:
if (((inst >> 4) & 0b01111) >= 4) {
- op = rv_op_cm_pop;
+ return &op_cm_pop;
}
break;
case 12:
if (((inst >> 4) & 0b01111) >= 4) {
- op = rv_op_cm_popretz;
+ return &op_cm_popretz;
}
break;
case 14:
if (((inst >> 4) & 0b01111) >= 4) {
- op = rv_op_cm_popret;
- }
- break;
- }
- } else {
- switch ((inst >> 10) & 0b011) {
- case 0:
- if (dec->cfg && !dec->cfg->ext_zcmt) {
- break;
- }
- if (((inst >> 2) & 0xFF) >= 32) {
- op = rv_op_cm_jalt;
- } else {
- op = rv_op_cm_jt;
- }
- break;
- case 3:
- if (dec->cfg && !dec->cfg->ext_zcmp) {
- break;
- }
- switch ((inst >> 5) & 0b011) {
- case 1: op = rv_op_cm_mvsa01; break;
- case 3: op = rv_op_cm_mva01s; break;
+ return &op_cm_popret;
}
break;
}
}
+ switch ((inst >> 10) & 0b011) {
+ case 0:
+ if (!dec->cfg->ext_zcmt) {
+ break;
+ }
+ if (((inst >> 2) & 0xFF) >= 32) {
+ return &op_cm_jalt;
+ }
+ return &op_cm_jt;
+ case 3:
+ if (!dec->cfg->ext_zcmp) {
+ break;
+ }
+ switch ((inst >> 5) & 0b011) {
+ case 1: return &op_cm_mvsa01;
+ case 3: return &op_cm_mva01s;
+ }
+ break;
+ }
}
- break;
- case 6: op = rv_op_c_swsp; break;
+ return &op_c_fsdsp;
+ case 6: return &op_c_swsp;
case 7:
if (isa == rv32) {
- op = rv_op_c_fswsp;
- } else {
- op = rv_op_c_sdsp;
+ return &op_c_fswsp;
}
- break;
+ return &op_c_sdsp;
}
break;
case 3:
switch ((inst >> 2) & 0b11111) {
case 0:
switch ((inst >> 12) & 0b111) {
- case 0: op = rv_op_lb; break;
- case 1: op = rv_op_lh; break;
- case 2: op = rv_op_lw; break;
- case 3: op = rv_op_ld; break;
- case 4: op = rv_op_lbu; break;
- case 5: op = rv_op_lhu; break;
- case 6: op = rv_op_lwu; break;
- case 7: op = rv_op_ldu; break;
+ case 0: return &op_lb;
+ case 1: return &op_lh;
+ case 2: return &op_lw;
+ case 3: return &op_ld;
+ case 4: return &op_lbu;
+ case 5: return &op_lhu;
+ case 6: return &op_lwu;
+ case 7: return &op_ldu;
}
break;
case 1:
switch ((inst >> 12) & 0b111) {
case 0:
switch ((inst >> 20) & 0b111111111111) {
- case 40: op = rv_op_vl1re8_v; break;
- case 552: op = rv_op_vl2re8_v; break;
- case 1576: op = rv_op_vl4re8_v; break;
- case 3624: op = rv_op_vl8re8_v; break;
+ case 40: return &op_vl1re8_v;
+ case 552: return &op_vl2re8_v;
+ case 1576: return &op_vl4re8_v;
+ case 3624: return &op_vl8re8_v;
}
switch ((inst >> 26) & 0b111) {
case 0:
switch ((inst >> 20) & 0b11111) {
- case 0: op = rv_op_vle8_v; break;
- case 11: op = rv_op_vlm_v; break;
- case 16: op = rv_op_vle8ff_v; break;
+ case 0: return &op_vle8_v;
+ case 11: return &op_vlm_v;
+ case 16: return &op_vle8ff_v;
}
break;
- case 1: op = rv_op_vluxei8_v; break;
- case 2: op = rv_op_vlse8_v; break;
- case 3: op = rv_op_vloxei8_v; break;
+ case 1: return &op_vluxei8_v;
+ case 2: return &op_vlse8_v;
+ case 3: return &op_vloxei8_v;
}
break;
- case 1: op = rv_op_flh; break;
- case 2: op = rv_op_flw; break;
- case 3: op = rv_op_fld; break;
- case 4: op = rv_op_flq; break;
+ case 1: return &op_flh;
+ case 2: return &op_flw;
+ case 3: return &op_fld;
+ case 4: return &op_flq;
case 5:
switch ((inst >> 20) & 0b111111111111) {
- case 40: op = rv_op_vl1re16_v; break;
- case 552: op = rv_op_vl2re16_v; break;
- case 1576: op = rv_op_vl4re16_v; break;
- case 3624: op = rv_op_vl8re16_v; break;
+ case 40: return &op_vl1re16_v;
+ case 552: return &op_vl2re16_v;
+ case 1576: return &op_vl4re16_v;
+ case 3624: return &op_vl8re16_v;
}
switch ((inst >> 26) & 0b111) {
case 0:
switch ((inst >> 20) & 0b11111) {
- case 0: op = rv_op_vle16_v; break;
- case 16: op = rv_op_vle16ff_v; break;
+ case 0: return &op_vle16_v;
+ case 16: return &op_vle16ff_v;
}
break;
- case 1: op = rv_op_vluxei16_v; break;
- case 2: op = rv_op_vlse16_v; break;
- case 3: op = rv_op_vloxei16_v; break;
+ case 1: return &op_vluxei16_v;
+ case 2: return &op_vlse16_v;
+ case 3: return &op_vloxei16_v;
}
break;
case 6:
switch ((inst >> 20) & 0b111111111111) {
- case 40: op = rv_op_vl1re32_v; break;
- case 552: op = rv_op_vl2re32_v; break;
- case 1576: op = rv_op_vl4re32_v; break;
- case 3624: op = rv_op_vl8re32_v; break;
+ case 40: return &op_vl1re32_v;
+ case 552: return &op_vl2re32_v;
+ case 1576: return &op_vl4re32_v;
+ case 3624: return &op_vl8re32_v;
}
switch ((inst >> 26) & 0b111) {
case 0:
switch ((inst >> 20) & 0b11111) {
- case 0: op = rv_op_vle32_v; break;
- case 16: op = rv_op_vle32ff_v; break;
+ case 0: return &op_vle32_v;
+ case 16: return &op_vle32ff_v;
}
break;
- case 1: op = rv_op_vluxei32_v; break;
- case 2: op = rv_op_vlse32_v; break;
- case 3: op = rv_op_vloxei32_v; break;
+ case 1: return &op_vluxei32_v;
+ case 2: return &op_vlse32_v;
+ case 3: return &op_vloxei32_v;
}
break;
case 7:
switch ((inst >> 20) & 0b111111111111) {
- case 40: op = rv_op_vl1re64_v; break;
- case 552: op = rv_op_vl2re64_v; break;
- case 1576: op = rv_op_vl4re64_v; break;
- case 3624: op = rv_op_vl8re64_v; break;
+ case 40: return &op_vl1re64_v;
+ case 552: return &op_vl2re64_v;
+ case 1576: return &op_vl4re64_v;
+ case 3624: return &op_vl8re64_v;
}
switch ((inst >> 26) & 0b111) {
case 0:
switch ((inst >> 20) & 0b11111) {
- case 0: op = rv_op_vle64_v; break;
- case 16: op = rv_op_vle64ff_v; break;
+ case 0: return &op_vle64_v;
+ case 16: return &op_vle64ff_v;
}
break;
- case 1: op = rv_op_vluxei64_v; break;
- case 2: op = rv_op_vlse64_v; break;
- case 3: op = rv_op_vloxei64_v; break;
+ case 1: return &op_vluxei64_v;
+ case 2: return &op_vlse64_v;
+ case 3: return &op_vloxei64_v;
}
break;
}
break;
case 3:
switch ((inst >> 12) & 0b111) {
- case 0: op = rv_op_fence; break;
- case 1: op = rv_op_fence_i; break;
+ case 0: return &op_fence;
+ case 1: return &op_fence_i;
case 2:
/*
* 'lq' shares the "(...) 010 ..... 0001111" opcode space
@@ -1320,204 +1292,203 @@ static const rv_opcode_data *decode_inst_opcode(rv_decode *dec, rv_isa isa)
* Anything that doesn't match these will default to 'lq'.
*/
switch ((inst >> 17) & 0b11111) {
- case 0: op = rv_op_cbo_inval; break;
- case 1: op = rv_op_cbo_clean; break;
- case 2: op = rv_op_cbo_flush; break;
- case 4: op = rv_op_cbo_zero; break;
- default: op = rv_op_lq; break;
+ case 0: return &op_cbo_inval;
+ case 1: return &op_cbo_clean;
+ case 2: return &op_cbo_flush;
+ case 4: return &op_cbo_zero;
+ default: return &op_lq;
}
}
break;
case 4:
switch ((inst >> 12) & 0b111) {
- case 0: op = rv_op_addi; break;
+ case 0: return &op_addi;
case 1:
switch ((inst >> 27) & 0b11111) {
- case 0b00000: op = rv_op_slli; break;
+ case 0b00000: return &op_slli;
case 0b00001:
switch ((inst >> 20) & 0b1111111) {
- case 0b0001111: op = rv_op_zip; break;
+ case 0b0001111: return &op_zip;
}
break;
case 0b00010:
switch ((inst >> 20) & 0b1111111) {
- case 0b0000000: op = rv_op_sha256sum0; break;
- case 0b0000001: op = rv_op_sha256sum1; break;
- case 0b0000010: op = rv_op_sha256sig0; break;
- case 0b0000011: op = rv_op_sha256sig1; break;
- case 0b0000100: op = rv_op_sha512sum0; break;
- case 0b0000101: op = rv_op_sha512sum1; break;
- case 0b0000110: op = rv_op_sha512sig0; break;
- case 0b0000111: op = rv_op_sha512sig1; break;
- case 0b0001000: op = rv_op_sm3p0; break;
- case 0b0001001: op = rv_op_sm3p1; break;
+ case 0b0000000: return &op_sha256sum0;
+ case 0b0000001: return &op_sha256sum1;
+ case 0b0000010: return &op_sha256sig0;
+ case 0b0000011: return &op_sha256sig1;
+ case 0b0000100: return &op_sha512sum0;
+ case 0b0000101: return &op_sha512sum1;
+ case 0b0000110: return &op_sha512sig0;
+ case 0b0000111: return &op_sha512sig1;
+ case 0b0001000: return &op_sm3p0;
+ case 0b0001001: return &op_sm3p1;
}
break;
- case 0b00101: op = rv_op_bseti; break;
+ case 0b00101: return &op_bseti;
case 0b00110:
switch ((inst >> 20) & 0b1111111) {
- case 0b0000000: op = rv_op_aes64im; break;
+ case 0b0000000: return &op_aes64im;
default:
if (((inst >> 24) & 0b0111) == 0b001) {
- op = rv_op_aes64ks1i;
+ return &op_aes64ks1i;
}
break;
}
break;
- case 0b01001: op = rv_op_bclri; break;
- case 0b01101: op = rv_op_binvi; break;
+ case 0b01001: return &op_bclri;
+ case 0b01101: return &op_binvi;
case 0b01100:
switch ((inst >> 20) & 0b1111111) {
- case 0b0000000: op = rv_op_clz; break;
- case 0b0000001: op = rv_op_ctz; break;
- case 0b0000010: op = rv_op_cpop; break;
+ case 0b0000000: return &op_clz;
+ case 0b0000001: return &op_ctz;
+ case 0b0000010: return &op_cpop;
/* 0b0000011 */
- case 0b0000100: op = rv_op_sext_b; break;
- case 0b0000101: op = rv_op_sext_h; break;
+ case 0b0000100: return &op_sext_b;
+ case 0b0000101: return &op_sext_h;
}
break;
}
break;
- case 2: op = rv_op_slti; break;
- case 3: op = rv_op_sltiu; break;
- case 4: op = rv_op_xori; break;
+ case 2: return &op_slti;
+ case 3: return &op_sltiu;
+ case 4: return &op_xori;
case 5:
switch ((inst >> 27) & 0b11111) {
- case 0b00000: op = rv_op_srli; break;
+ case 0b00000: return &op_srli;
case 0b00001:
switch ((inst >> 20) & 0b1111111) {
- case 0b0001111: op = rv_op_unzip; break;
+ case 0b0001111: return &op_unzip;
}
break;
- case 0b00101: op = rv_op_orc_b; break;
- case 0b01000: op = rv_op_srai; break;
- case 0b01001: op = rv_op_bexti; break;
- case 0b01100: op = rv_op_rori; break;
+ case 0b00101: return &op_orc_b;
+ case 0b01000: return &op_srai;
+ case 0b01001: return &op_bexti;
+ case 0b01100: return &op_rori;
case 0b01101:
switch ((inst >> 20) & 0b1111111) {
case 0b0011000:
if (isa == rv32) {
- op = rv_op_rev8;
+ return &op_rev8;
}
break;
case 0b0111000:
if (isa == rv64) {
- op = rv_op_rev8;
+ return &op_rev8;
}
break;
- case 0b0000111: op = rv_op_brev8; break;
+ case 0b0000111: return &op_brev8;
}
break;
}
break;
- case 6: op = rv_op_ori; break;
- case 7: op = rv_op_andi; break;
+ case 6: return &op_ori;
+ case 7: return &op_andi;
}
break;
case 5:
- op = rv_op_auipc;
if (dec->cfg && dec->cfg->ext_zicfilp &&
(((inst >> 7) & 0b11111) == 0b00000)) {
- op = rv_op_lpad;
+ return &op_lpad;
}
- break;
+ return &op_auipc;
case 6:
/* OP-IMM-32 */
if (isa == rv32) {
break;
}
switch ((inst >> 12) & 0b111) {
- case 0: op = rv_op_addiw; break;
+ case 0: return &op_addiw;
case 1:
switch ((inst >> 26) & 0b111111) {
- case 0: op = rv_op_slliw; break;
- case 2: op = rv_op_slli_uw; break;
+ case 0: return &op_slliw;
+ case 2: return &op_slli_uw;
case 24:
switch ((inst >> 20) & 0b11111) {
- case 0b00000: op = rv_op_clzw; break;
- case 0b00001: op = rv_op_ctzw; break;
- case 0b00010: op = rv_op_cpopw; break;
+ case 0b00000: return &op_clzw;
+ case 0b00001: return &op_ctzw;
+ case 0b00010: return &op_cpopw;
}
break;
}
break;
case 5:
switch ((inst >> 25) & 0b1111111) {
- case 0: op = rv_op_srliw; break;
- case 32: op = rv_op_sraiw; break;
- case 48: op = rv_op_roriw; break;
+ case 0: return &op_srliw;
+ case 32: return &op_sraiw;
+ case 48: return &op_roriw;
}
break;
}
break;
case 8:
switch ((inst >> 12) & 0b111) {
- case 0: op = rv_op_sb; break;
- case 1: op = rv_op_sh; break;
- case 2: op = rv_op_sw; break;
- case 3: op = rv_op_sd; break;
- case 4: op = rv_op_sq; break;
+ case 0: return &op_sb;
+ case 1: return &op_sh;
+ case 2: return &op_sw;
+ case 3: return &op_sd;
+ case 4: return &op_sq;
}
break;
case 9:
switch ((inst >> 12) & 0b111) {
case 0:
switch ((inst >> 20) & 0b111111111111) {
- case 40: op = rv_op_vs1r_v; break;
- case 552: op = rv_op_vs2r_v; break;
- case 1576: op = rv_op_vs4r_v; break;
- case 3624: op = rv_op_vs8r_v; break;
+ case 40: return &op_vs1r_v;
+ case 552: return &op_vs2r_v;
+ case 1576: return &op_vs4r_v;
+ case 3624: return &op_vs8r_v;
}
switch ((inst >> 26) & 0b111) {
case 0:
switch ((inst >> 20) & 0b11111) {
- case 0: op = rv_op_vse8_v; break;
- case 11: op = rv_op_vsm_v; break;
+ case 0: return &op_vse8_v;
+ case 11: return &op_vsm_v;
}
break;
- case 1: op = rv_op_vsuxei8_v; break;
- case 2: op = rv_op_vsse8_v; break;
- case 3: op = rv_op_vsoxei8_v; break;
+ case 1: return &op_vsuxei8_v;
+ case 2: return &op_vsse8_v;
+ case 3: return &op_vsoxei8_v;
}
break;
- case 1: op = rv_op_fsh; break;
- case 2: op = rv_op_fsw; break;
- case 3: op = rv_op_fsd; break;
- case 4: op = rv_op_fsq; break;
+ case 1: return &op_fsh;
+ case 2: return &op_fsw;
+ case 3: return &op_fsd;
+ case 4: return &op_fsq;
case 5:
switch ((inst >> 26) & 0b111) {
case 0:
switch ((inst >> 20) & 0b11111) {
- case 0: op = rv_op_vse16_v; break;
+ case 0: return &op_vse16_v;
}
break;
- case 1: op = rv_op_vsuxei16_v; break;
- case 2: op = rv_op_vsse16_v; break;
- case 3: op = rv_op_vsoxei16_v; break;
+ case 1: return &op_vsuxei16_v;
+ case 2: return &op_vsse16_v;
+ case 3: return &op_vsoxei16_v;
}
break;
case 6:
switch ((inst >> 26) & 0b111) {
case 0:
switch ((inst >> 20) & 0b11111) {
- case 0: op = rv_op_vse32_v; break;
+ case 0: return &op_vse32_v;
}
break;
- case 1: op = rv_op_vsuxei32_v; break;
- case 2: op = rv_op_vsse32_v; break;
- case 3: op = rv_op_vsoxei32_v; break;
+ case 1: return &op_vsuxei32_v;
+ case 2: return &op_vsse32_v;
+ case 3: return &op_vsoxei32_v;
}
break;
case 7:
switch ((inst >> 26) & 0b111) {
case 0:
switch ((inst >> 20) & 0b11111) {
- case 0: op = rv_op_vse64_v; break;
+ case 0: return &op_vse64_v;
}
break;
- case 1: op = rv_op_vsuxei64_v; break;
- case 2: op = rv_op_vsse64_v; break;
- case 3: op = rv_op_vsoxei64_v; break;
+ case 1: return &op_vsuxei64_v;
+ case 2: return &op_vsse64_v;
+ case 3: return &op_vsoxei64_v;
}
break;
}
@@ -1525,153 +1496,150 @@ static const rv_opcode_data *decode_inst_opcode(rv_decode *dec, rv_isa isa)
case 11:
switch (((inst >> 24) & 0b11111000) |
((inst >> 12) & 0b00000111)) {
- case 0: op = rv_op_amoadd_b; break;
- case 1: op = rv_op_amoadd_h; break;
- case 2: op = rv_op_amoadd_w; break;
- case 3: op = rv_op_amoadd_d; break;
- case 4: op = rv_op_amoadd_q; break;
- case 8: op = rv_op_amoswap_b; break;
- case 9: op = rv_op_amoswap_h; break;
- case 10: op = rv_op_amoswap_w; break;
- case 11: op = rv_op_amoswap_d; break;
- case 12: op = rv_op_amoswap_q; break;
+ case 0: return &op_amoadd_b;
+ case 1: return &op_amoadd_h;
+ case 2: return &op_amoadd_w;
+ case 3: return &op_amoadd_d;
+ case 4: return &op_amoadd_q;
+ case 8: return &op_amoswap_b;
+ case 9: return &op_amoswap_h;
+ case 10: return &op_amoswap_w;
+ case 11: return &op_amoswap_d;
+ case 12: return &op_amoswap_q;
case 18:
switch ((inst >> 20) & 0b11111) {
- case 0: op = rv_op_lr_w; break;
+ case 0: return &op_lr_w;
}
break;
case 19:
switch ((inst >> 20) & 0b11111) {
- case 0: op = rv_op_lr_d; break;
+ case 0: return &op_lr_d;
}
break;
case 20:
switch ((inst >> 20) & 0b11111) {
- case 0: op = rv_op_lr_q; break;
+ case 0: return &op_lr_q;
}
break;
- case 26: op = rv_op_sc_w; break;
- case 27: op = rv_op_sc_d; break;
- case 28: op = rv_op_sc_q; break;
- case 32: op = rv_op_amoxor_b; break;
- case 33: op = rv_op_amoxor_h; break;
- case 34: op = rv_op_amoxor_w; break;
- case 35: op = rv_op_amoxor_d; break;
- case 36: op = rv_op_amoxor_q; break;
- case 40: op = rv_op_amocas_b; break;
- case 41: op = rv_op_amocas_h; break;
- case 42: op = rv_op_amocas_w; break;
- case 43: op = rv_op_amocas_d; break;
- case 44: op = rv_op_amocas_q; break;
- case 64: op = rv_op_amoor_b; break;
- case 65: op = rv_op_amoor_h; break;
- case 66: op = rv_op_amoor_w; break;
- case 67: op = rv_op_amoor_d; break;
- case 68: op = rv_op_amoor_q; break;
- case 74: op = rv_op_ssamoswap_w; break;
- case 75: op = rv_op_ssamoswap_d; break;
- case 96: op = rv_op_amoand_b; break;
- case 97: op = rv_op_amoand_h; break;
- case 98: op = rv_op_amoand_w; break;
- case 99: op = rv_op_amoand_d; break;
- case 100: op = rv_op_amoand_q; break;
- case 128: op = rv_op_amomin_b; break;
- case 129: op = rv_op_amomin_h; break;
- case 130: op = rv_op_amomin_w; break;
- case 131: op = rv_op_amomin_d; break;
- case 132: op = rv_op_amomin_q; break;
- case 160: op = rv_op_amomax_b; break;
- case 161: op = rv_op_amomax_h; break;
- case 162: op = rv_op_amomax_w; break;
- case 163: op = rv_op_amomax_d; break;
- case 164: op = rv_op_amomax_q; break;
- case 192: op = rv_op_amominu_b; break;
- case 193: op = rv_op_amominu_h; break;
- case 194: op = rv_op_amominu_w; break;
- case 195: op = rv_op_amominu_d; break;
- case 196: op = rv_op_amominu_q; break;
- case 224: op = rv_op_amomaxu_b; break;
- case 225: op = rv_op_amomaxu_h; break;
- case 226: op = rv_op_amomaxu_w; break;
- case 227: op = rv_op_amomaxu_d; break;
- case 228: op = rv_op_amomaxu_q; break;
+ case 26: return &op_sc_w;
+ case 27: return &op_sc_d;
+ case 28: return &op_sc_q;
+ case 32: return &op_amoxor_b;
+ case 33: return &op_amoxor_h;
+ case 34: return &op_amoxor_w;
+ case 35: return &op_amoxor_d;
+ case 36: return &op_amoxor_q;
+ case 40: return &op_amocas_b;
+ case 41: return &op_amocas_h;
+ case 42: return &op_amocas_w;
+ case 43: return &op_amocas_d;
+ case 44: return &op_amocas_q;
+ case 64: return &op_amoor_b;
+ case 65: return &op_amoor_h;
+ case 66: return &op_amoor_w;
+ case 67: return &op_amoor_d;
+ case 68: return &op_amoor_q;
+ case 74: return &op_ssamoswap_w;
+ case 75: return &op_ssamoswap_d;
+ case 96: return &op_amoand_b;
+ case 97: return &op_amoand_h;
+ case 98: return &op_amoand_w;
+ case 99: return &op_amoand_d;
+ case 100: return &op_amoand_q;
+ case 128: return &op_amomin_b;
+ case 129: return &op_amomin_h;
+ case 130: return &op_amomin_w;
+ case 131: return &op_amomin_d;
+ case 132: return &op_amomin_q;
+ case 160: return &op_amomax_b;
+ case 161: return &op_amomax_h;
+ case 162: return &op_amomax_w;
+ case 163: return &op_amomax_d;
+ case 164: return &op_amomax_q;
+ case 192: return &op_amominu_b;
+ case 193: return &op_amominu_h;
+ case 194: return &op_amominu_w;
+ case 195: return &op_amominu_d;
+ case 196: return &op_amominu_q;
+ case 224: return &op_amomaxu_b;
+ case 225: return &op_amomaxu_h;
+ case 226: return &op_amomaxu_w;
+ case 227: return &op_amomaxu_d;
+ case 228: return &op_amomaxu_q;
}
break;
case 12:
switch (((inst >> 22) & 0b1111111000) |
((inst >> 12) & 0b0000000111)) {
- case 0: op = rv_op_add; break;
- case 1: op = rv_op_sll; break;
- case 2: op = rv_op_slt; break;
- case 3: op = rv_op_sltu; break;
- case 4: op = rv_op_xor; break;
- case 5: op = rv_op_srl; break;
- case 6: op = rv_op_or; break;
- case 7: op = rv_op_and; break;
- case 8: op = rv_op_mul; break;
- case 9: op = rv_op_mulh; break;
- case 10: op = rv_op_mulhsu; break;
- case 11: op = rv_op_mulhu; break;
- case 12: op = rv_op_div; break;
- case 13: op = rv_op_divu; break;
- case 14: op = rv_op_rem; break;
- case 15: op = rv_op_remu; break;
+ case 0: return &op_add;
+ case 1: return &op_sll;
+ case 2: return &op_slt;
+ case 3: return &op_sltu;
+ case 4: return &op_xor;
+ case 5: return &op_srl;
+ case 6: return &op_or;
+ case 7: return &op_and;
+ case 8: return &op_mul;
+ case 9: return &op_mulh;
+ case 10: return &op_mulhsu;
+ case 11: return &op_mulhu;
+ case 12: return &op_div;
+ case 13: return &op_divu;
+ case 14: return &op_rem;
+ case 15: return &op_remu;
case 36:
if (isa == rv32 && !((inst >> 20) & 0b11111)) {
- op = rv_op_zext_h;
- } else {
- op = rv_op_pack;
+ return &op_zext_h;
}
- break;
- case 39: op = rv_op_packh; break;
-
- case 41: op = rv_op_clmul; break;
- case 42: op = rv_op_clmulr; break;
- case 43: op = rv_op_clmulh; break;
- case 44: op = rv_op_min; break;
- case 45: op = rv_op_minu; break;
- case 46: op = rv_op_max; break;
- case 47: op = rv_op_maxu; break;
- case 075: op = rv_op_czero_eqz; break;
- case 077: op = rv_op_czero_nez; break;
- case 130: op = rv_op_sh1add; break;
- case 132: op = rv_op_sh2add; break;
- case 134: op = rv_op_sh3add; break;
- case 161: op = rv_op_bset; break;
- case 162: op = rv_op_xperm4; break;
- case 164: op = rv_op_xperm8; break;
- case 200: op = rv_op_aes64es; break;
- case 216: op = rv_op_aes64esm; break;
- case 232: op = rv_op_aes64ds; break;
- case 248: op = rv_op_aes64dsm; break;
- case 256: op = rv_op_sub; break;
- case 260: op = rv_op_xnor; break;
- case 261: op = rv_op_sra; break;
- case 262: op = rv_op_orn; break;
- case 263: op = rv_op_andn; break;
- case 289: op = rv_op_bclr; break;
- case 293: op = rv_op_bext; break;
- case 320: op = rv_op_sha512sum0r; break;
- case 328: op = rv_op_sha512sum1r; break;
- case 336: op = rv_op_sha512sig0l; break;
- case 344: op = rv_op_sha512sig1l; break;
- case 368: op = rv_op_sha512sig0h; break;
- case 376: op = rv_op_sha512sig1h; break;
- case 385: op = rv_op_rol; break;
- case 389: op = rv_op_ror; break;
- case 417: op = rv_op_binv; break;
- case 504: op = rv_op_aes64ks2; break;
+ return &op_pack;
+ case 39: return &op_packh;
+ case 41: return &op_clmul;
+ case 42: return &op_clmulr;
+ case 43: return &op_clmulh;
+ case 44: return &op_min;
+ case 45: return &op_minu;
+ case 46: return &op_max;
+ case 47: return &op_maxu;
+ case 075: return &op_czero_eqz;
+ case 077: return &op_czero_nez;
+ case 130: return &op_sh1add;
+ case 132: return &op_sh2add;
+ case 134: return &op_sh3add;
+ case 161: return &op_bset;
+ case 162: return &op_xperm4;
+ case 164: return &op_xperm8;
+ case 200: return &op_aes64es;
+ case 216: return &op_aes64esm;
+ case 232: return &op_aes64ds;
+ case 248: return &op_aes64dsm;
+ case 256: return &op_sub;
+ case 260: return &op_xnor;
+ case 261: return &op_sra;
+ case 262: return &op_orn;
+ case 263: return &op_andn;
+ case 289: return &op_bclr;
+ case 293: return &op_bext;
+ case 320: return &op_sha512sum0r;
+ case 328: return &op_sha512sum1r;
+ case 336: return &op_sha512sig0l;
+ case 344: return &op_sha512sig1l;
+ case 368: return &op_sha512sig0h;
+ case 376: return &op_sha512sig1h;
+ case 385: return &op_rol;
+ case 389: return &op_ror;
+ case 417: return &op_binv;
+ case 504: return &op_aes64ks2;
}
switch ((inst >> 25) & 0b0011111) {
- case 17: op = rv_op_aes32esi; break;
- case 19: op = rv_op_aes32esmi; break;
- case 21: op = rv_op_aes32dsi; break;
- case 23: op = rv_op_aes32dsmi; break;
- case 24: op = rv_op_sm4ed; break;
- case 26: op = rv_op_sm4ks; break;
+ case 17: return &op_aes32esi;
+ case 19: return &op_aes32esmi;
+ case 21: return &op_aes32dsi;
+ case 23: return &op_aes32dsmi;
+ case 24: return &op_sm4ed;
+ case 26: return &op_sm4ks;
}
break;
- case 13: op = rv_op_lui; break;
+ case 13: return &op_lui;
case 14:
/* OP-32 */
if (isa == rv32) {
@@ -1679,317 +1647,317 @@ static const rv_opcode_data *decode_inst_opcode(rv_decode *dec, rv_isa isa)
}
switch (((inst >> 22) & 0b1111111000) |
((inst >> 12) & 0b0000000111)) {
- case 0: op = rv_op_addw; break;
- case 1: op = rv_op_sllw; break;
- case 5: op = rv_op_srlw; break;
- case 8: op = rv_op_mulw; break;
- case 12: op = rv_op_divw; break;
- case 13: op = rv_op_divuw; break;
- case 14: op = rv_op_remw; break;
- case 15: op = rv_op_remuw; break;
- case 32: op = rv_op_add_uw; break;
+ case 0: return &op_addw;
+ case 1: return &op_sllw;
+ case 5: return &op_srlw;
+ case 8: return &op_mulw;
+ case 12: return &op_divw;
+ case 13: return &op_divuw;
+ case 14: return &op_remw;
+ case 15: return &op_remuw;
+ case 32: return &op_add_uw;
case 36:
switch ((inst >> 20) & 0b11111) {
- case 0: op = rv_op_zext_h; break;
- default: op = rv_op_packw; break;
+ case 0: return &op_zext_h;
+ default: return &op_packw;
}
break;
- case 130: op = rv_op_sh1add_uw; break;
- case 132: op = rv_op_sh2add_uw; break;
- case 134: op = rv_op_sh3add_uw; break;
- case 256: op = rv_op_subw; break;
- case 261: op = rv_op_sraw; break;
- case 385: op = rv_op_rolw; break;
- case 389: op = rv_op_rorw; break;
+ case 130: return &op_sh1add_uw;
+ case 132: return &op_sh2add_uw;
+ case 134: return &op_sh3add_uw;
+ case 256: return &op_subw;
+ case 261: return &op_sraw;
+ case 385: return &op_rolw;
+ case 389: return &op_rorw;
}
break;
case 16:
switch ((inst >> 25) & 0b11) {
- case 0: op = rv_op_fmadd_s; break;
- case 1: op = rv_op_fmadd_d; break;
- case 3: op = rv_op_fmadd_q; break;
+ case 0: return &op_fmadd_s;
+ case 1: return &op_fmadd_d;
+ case 3: return &op_fmadd_q;
}
break;
case 17:
switch ((inst >> 25) & 0b11) {
- case 0: op = rv_op_fmsub_s; break;
- case 1: op = rv_op_fmsub_d; break;
- case 3: op = rv_op_fmsub_q; break;
+ case 0: return &op_fmsub_s;
+ case 1: return &op_fmsub_d;
+ case 3: return &op_fmsub_q;
}
break;
case 18:
switch ((inst >> 25) & 0b11) {
- case 0: op = rv_op_fnmsub_s; break;
- case 1: op = rv_op_fnmsub_d; break;
- case 3: op = rv_op_fnmsub_q; break;
+ case 0: return &op_fnmsub_s;
+ case 1: return &op_fnmsub_d;
+ case 3: return &op_fnmsub_q;
}
break;
case 19:
switch ((inst >> 25) & 0b11) {
- case 0: op = rv_op_fnmadd_s; break;
- case 1: op = rv_op_fnmadd_d; break;
- case 3: op = rv_op_fnmadd_q; break;
+ case 0: return &op_fnmadd_s;
+ case 1: return &op_fnmadd_d;
+ case 3: return &op_fnmadd_q;
}
break;
case 20:
switch ((inst >> 25) & 0b1111111) {
- case 0: op = rv_op_fadd_s; break;
- case 1: op = rv_op_fadd_d; break;
- case 3: op = rv_op_fadd_q; break;
- case 4: op = rv_op_fsub_s; break;
- case 5: op = rv_op_fsub_d; break;
- case 7: op = rv_op_fsub_q; break;
- case 8: op = rv_op_fmul_s; break;
- case 9: op = rv_op_fmul_d; break;
- case 11: op = rv_op_fmul_q; break;
- case 12: op = rv_op_fdiv_s; break;
- case 13: op = rv_op_fdiv_d; break;
- case 15: op = rv_op_fdiv_q; break;
+ case 0: return &op_fadd_s;
+ case 1: return &op_fadd_d;
+ case 3: return &op_fadd_q;
+ case 4: return &op_fsub_s;
+ case 5: return &op_fsub_d;
+ case 7: return &op_fsub_q;
+ case 8: return &op_fmul_s;
+ case 9: return &op_fmul_d;
+ case 11: return &op_fmul_q;
+ case 12: return &op_fdiv_s;
+ case 13: return &op_fdiv_d;
+ case 15: return &op_fdiv_q;
case 16:
switch ((inst >> 12) & 0b111) {
- case 0: op = rv_op_fsgnj_s; break;
- case 1: op = rv_op_fsgnjn_s; break;
- case 2: op = rv_op_fsgnjx_s; break;
+ case 0: return &op_fsgnj_s;
+ case 1: return &op_fsgnjn_s;
+ case 2: return &op_fsgnjx_s;
}
break;
case 17:
switch ((inst >> 12) & 0b111) {
- case 0: op = rv_op_fsgnj_d; break;
- case 1: op = rv_op_fsgnjn_d; break;
- case 2: op = rv_op_fsgnjx_d; break;
+ case 0: return &op_fsgnj_d;
+ case 1: return &op_fsgnjn_d;
+ case 2: return &op_fsgnjx_d;
}
break;
case 19:
switch ((inst >> 12) & 0b111) {
- case 0: op = rv_op_fsgnj_q; break;
- case 1: op = rv_op_fsgnjn_q; break;
- case 2: op = rv_op_fsgnjx_q; break;
+ case 0: return &op_fsgnj_q;
+ case 1: return &op_fsgnjn_q;
+ case 2: return &op_fsgnjx_q;
}
break;
case 20:
switch ((inst >> 12) & 0b111) {
- case 0: op = rv_op_fmin_s; break;
- case 1: op = rv_op_fmax_s; break;
- case 2: op = rv_op_fminm_s; break;
- case 3: op = rv_op_fmaxm_s; break;
+ case 0: return &op_fmin_s;
+ case 1: return &op_fmax_s;
+ case 2: return &op_fminm_s;
+ case 3: return &op_fmaxm_s;
}
break;
case 21:
switch ((inst >> 12) & 0b111) {
- case 0: op = rv_op_fmin_d; break;
- case 1: op = rv_op_fmax_d; break;
- case 2: op = rv_op_fminm_d; break;
- case 3: op = rv_op_fmaxm_d; break;
+ case 0: return &op_fmin_d;
+ case 1: return &op_fmax_d;
+ case 2: return &op_fminm_d;
+ case 3: return &op_fmaxm_d;
}
break;
case 22:
switch (((inst >> 12) & 0b111)) {
- case 2: op = rv_op_fminm_h; break;
- case 3: op = rv_op_fmaxm_h; break;
+ case 2: return &op_fminm_h;
+ case 3: return &op_fmaxm_h;
}
break;
case 23:
switch ((inst >> 12) & 0b111) {
- case 0: op = rv_op_fmin_q; break;
- case 1: op = rv_op_fmax_q; break;
- case 2: op = rv_op_fminm_q; break;
- case 3: op = rv_op_fmaxm_q; break;
+ case 0: return &op_fmin_q;
+ case 1: return &op_fmax_q;
+ case 2: return &op_fminm_q;
+ case 3: return &op_fmaxm_q;
}
break;
case 32:
switch ((inst >> 20) & 0b11111) {
- case 1: op = rv_op_fcvt_s_d; break;
- case 3: op = rv_op_fcvt_s_q; break;
- case 4: op = rv_op_fround_s; break;
- case 5: op = rv_op_froundnx_s; break;
- case 6: op = rv_op_fcvt_s_bf16; break;
+ case 1: return &op_fcvt_s_d;
+ case 3: return &op_fcvt_s_q;
+ case 4: return &op_fround_s;
+ case 5: return &op_froundnx_s;
+ case 6: return &op_fcvt_s_bf16;
}
break;
case 33:
switch ((inst >> 20) & 0b11111) {
- case 0: op = rv_op_fcvt_d_s; break;
- case 3: op = rv_op_fcvt_d_q; break;
- case 4: op = rv_op_fround_d; break;
- case 5: op = rv_op_froundnx_d; break;
+ case 0: return &op_fcvt_d_s;
+ case 3: return &op_fcvt_d_q;
+ case 4: return &op_fround_d;
+ case 5: return &op_froundnx_d;
}
break;
case 34:
switch (((inst >> 20) & 0b11111)) {
- case 4: op = rv_op_fround_h; break;
- case 5: op = rv_op_froundnx_h; break;
- case 8: op = rv_op_fcvt_bf16_s; break;
+ case 4: return &op_fround_h;
+ case 5: return &op_froundnx_h;
+ case 8: return &op_fcvt_bf16_s;
}
break;
case 35:
switch ((inst >> 20) & 0b11111) {
- case 0: op = rv_op_fcvt_q_s; break;
- case 1: op = rv_op_fcvt_q_d; break;
- case 4: op = rv_op_fround_q; break;
- case 5: op = rv_op_froundnx_q; break;
+ case 0: return &op_fcvt_q_s;
+ case 1: return &op_fcvt_q_d;
+ case 4: return &op_fround_q;
+ case 5: return &op_froundnx_q;
}
break;
case 44:
switch ((inst >> 20) & 0b11111) {
- case 0: op = rv_op_fsqrt_s; break;
+ case 0: return &op_fsqrt_s;
}
break;
case 45:
switch ((inst >> 20) & 0b11111) {
- case 0: op = rv_op_fsqrt_d; break;
+ case 0: return &op_fsqrt_d;
}
break;
case 47:
switch ((inst >> 20) & 0b11111) {
- case 0: op = rv_op_fsqrt_q; break;
+ case 0: return &op_fsqrt_q;
}
break;
case 80:
switch ((inst >> 12) & 0b111) {
- case 0: op = rv_op_fle_s; break;
- case 1: op = rv_op_flt_s; break;
- case 2: op = rv_op_feq_s; break;
- case 4: op = rv_op_fleq_s; break;
- case 5: op = rv_op_fltq_s; break;
+ case 0: return &op_fle_s;
+ case 1: return &op_flt_s;
+ case 2: return &op_feq_s;
+ case 4: return &op_fleq_s;
+ case 5: return &op_fltq_s;
}
break;
case 81:
switch ((inst >> 12) & 0b111) {
- case 0: op = rv_op_fle_d; break;
- case 1: op = rv_op_flt_d; break;
- case 2: op = rv_op_feq_d; break;
- case 4: op = rv_op_fleq_d; break;
- case 5: op = rv_op_fltq_d; break;
+ case 0: return &op_fle_d;
+ case 1: return &op_flt_d;
+ case 2: return &op_feq_d;
+ case 4: return &op_fleq_d;
+ case 5: return &op_fltq_d;
}
break;
case 82:
switch (((inst >> 12) & 0b111)) {
- case 4: op = rv_op_fleq_h; break;
- case 5: op = rv_op_fltq_h; break;
+ case 4: return &op_fleq_h;
+ case 5: return &op_fltq_h;
}
break;
case 83:
switch ((inst >> 12) & 0b111) {
- case 0: op = rv_op_fle_q; break;
- case 1: op = rv_op_flt_q; break;
- case 2: op = rv_op_feq_q; break;
- case 4: op = rv_op_fleq_q; break;
- case 5: op = rv_op_fltq_q; break;
+ case 0: return &op_fle_q;
+ case 1: return &op_flt_q;
+ case 2: return &op_feq_q;
+ case 4: return &op_fleq_q;
+ case 5: return &op_fltq_q;
}
break;
case 89:
switch (((inst >> 12) & 0b111)) {
- case 0: op = rv_op_fmvp_d_x; break;
+ case 0: return &op_fmvp_d_x;
}
break;
case 91:
switch (((inst >> 12) & 0b111)) {
- case 0: op = rv_op_fmvp_q_x; break;
+ case 0: return &op_fmvp_q_x;
}
break;
case 96:
switch ((inst >> 20) & 0b11111) {
- case 0: op = rv_op_fcvt_w_s; break;
- case 1: op = rv_op_fcvt_wu_s; break;
- case 2: op = rv_op_fcvt_l_s; break;
- case 3: op = rv_op_fcvt_lu_s; break;
+ case 0: return &op_fcvt_w_s;
+ case 1: return &op_fcvt_wu_s;
+ case 2: return &op_fcvt_l_s;
+ case 3: return &op_fcvt_lu_s;
}
break;
case 97:
switch ((inst >> 20) & 0b11111) {
- case 0: op = rv_op_fcvt_w_d; break;
- case 1: op = rv_op_fcvt_wu_d; break;
- case 2: op = rv_op_fcvt_l_d; break;
- case 3: op = rv_op_fcvt_lu_d; break;
- case 8: op = rv_op_fcvtmod_w_d; break;
+ case 0: return &op_fcvt_w_d;
+ case 1: return &op_fcvt_wu_d;
+ case 2: return &op_fcvt_l_d;
+ case 3: return &op_fcvt_lu_d;
+ case 8: return &op_fcvtmod_w_d;
}
break;
case 99:
switch ((inst >> 20) & 0b11111) {
- case 0: op = rv_op_fcvt_w_q; break;
- case 1: op = rv_op_fcvt_wu_q; break;
- case 2: op = rv_op_fcvt_l_q; break;
- case 3: op = rv_op_fcvt_lu_q; break;
+ case 0: return &op_fcvt_w_q;
+ case 1: return &op_fcvt_wu_q;
+ case 2: return &op_fcvt_l_q;
+ case 3: return &op_fcvt_lu_q;
}
break;
case 104:
switch ((inst >> 20) & 0b11111) {
- case 0: op = rv_op_fcvt_s_w; break;
- case 1: op = rv_op_fcvt_s_wu; break;
- case 2: op = rv_op_fcvt_s_l; break;
- case 3: op = rv_op_fcvt_s_lu; break;
+ case 0: return &op_fcvt_s_w;
+ case 1: return &op_fcvt_s_wu;
+ case 2: return &op_fcvt_s_l;
+ case 3: return &op_fcvt_s_lu;
}
break;
case 105:
switch ((inst >> 20) & 0b11111) {
- case 0: op = rv_op_fcvt_d_w; break;
- case 1: op = rv_op_fcvt_d_wu; break;
- case 2: op = rv_op_fcvt_d_l; break;
- case 3: op = rv_op_fcvt_d_lu; break;
+ case 0: return &op_fcvt_d_w;
+ case 1: return &op_fcvt_d_wu;
+ case 2: return &op_fcvt_d_l;
+ case 3: return &op_fcvt_d_lu;
}
break;
case 107:
switch ((inst >> 20) & 0b11111) {
- case 0: op = rv_op_fcvt_q_w; break;
- case 1: op = rv_op_fcvt_q_wu; break;
- case 2: op = rv_op_fcvt_q_l; break;
- case 3: op = rv_op_fcvt_q_lu; break;
+ case 0: return &op_fcvt_q_w;
+ case 1: return &op_fcvt_q_wu;
+ case 2: return &op_fcvt_q_l;
+ case 3: return &op_fcvt_q_lu;
}
break;
case 112:
switch (((inst >> 17) & 0b11111000) |
((inst >> 12) & 0b00000111)) {
- case 0: op = rv_op_fmv_x_s; break;
- case 1: op = rv_op_fclass_s; break;
+ case 0: return &op_fmv_x_s;
+ case 1: return &op_fclass_s;
}
break;
case 113:
switch (((inst >> 17) & 0b11111000) |
((inst >> 12) & 0b00000111)) {
- case 0: op = rv_op_fmv_x_d; break;
- case 1: op = rv_op_fclass_d; break;
- case 8: op = rv_op_fmvh_x_d; break;
+ case 0: return &op_fmv_x_d;
+ case 1: return &op_fclass_d;
+ case 8: return &op_fmvh_x_d;
}
break;
case 114:
switch (((inst >> 17) & 0b11111000) |
((inst >> 12) & 0b00000111)) {
- case 0: op = rv_op_fmv_x_h; break;
+ case 0: return &op_fmv_x_h;
}
break;
case 115:
switch (((inst >> 17) & 0b11111000) |
((inst >> 12) & 0b00000111)) {
- case 0: op = rv_op_fmv_x_q; break;
- case 1: op = rv_op_fclass_q; break;
- case 8: op = rv_op_fmvh_x_q; break;
+ case 0: return &op_fmv_x_q;
+ case 1: return &op_fclass_q;
+ case 8: return &op_fmvh_x_q;
}
break;
case 120:
switch (((inst >> 17) & 0b11111000) |
((inst >> 12) & 0b00000111)) {
- case 0: op = rv_op_fmv_s_x; break;
- case 8: op = rv_op_fli_s; break;
+ case 0: return &op_fmv_s_x;
+ case 8: return &op_fli_s;
}
break;
case 121:
switch (((inst >> 17) & 0b11111000) |
((inst >> 12) & 0b00000111)) {
- case 0: op = rv_op_fmv_d_x; break;
- case 8: op = rv_op_fli_d; break;
+ case 0: return &op_fmv_d_x;
+ case 8: return &op_fli_d;
}
break;
case 122:
switch (((inst >> 17) & 0b11111000) |
((inst >> 12) & 0b00000111)) {
- case 0: op = rv_op_fmv_h_x; break;
- case 8: op = rv_op_fli_h; break;
+ case 0: return &op_fmv_h_x;
+ case 8: return &op_fli_h;
}
break;
case 123:
switch (((inst >> 17) & 0b11111000) |
((inst >> 12) & 0b00000111)) {
- case 0: op = rv_op_fmv_q_x; break;
- case 8: op = rv_op_fli_q; break;
+ case 0: return &op_fmv_q_x;
+ case 8: return &op_fli_q;
}
break;
}
@@ -1998,484 +1966,537 @@ static const rv_opcode_data *decode_inst_opcode(rv_decode *dec, rv_isa isa)
switch ((inst >> 12) & 0b111) {
case 0:
switch ((inst >> 26) & 0b111111) {
- case 0: op = rv_op_vadd_vv; break;
- case 1: op = rv_op_vandn_vv; break;
- case 2: op = rv_op_vsub_vv; break;
- case 4: op = rv_op_vminu_vv; break;
- case 5: op = rv_op_vmin_vv; break;
- case 6: op = rv_op_vmaxu_vv; break;
- case 7: op = rv_op_vmax_vv; break;
- case 9: op = rv_op_vand_vv; break;
- case 10: op = rv_op_vor_vv; break;
- case 11: op = rv_op_vxor_vv; break;
- case 12: op = rv_op_vrgather_vv; break;
- case 14: op = rv_op_vrgatherei16_vv; break;
+ case 0: return &op_vadd_vv;
+ case 1: return &op_vandn_vv;
+ case 2: return &op_vsub_vv;
+ case 4: return &op_vminu_vv;
+ case 5: return &op_vmin_vv;
+ case 6: return &op_vmaxu_vv;
+ case 7: return &op_vmax_vv;
+ case 9: return &op_vand_vv;
+ case 10: return &op_vor_vv;
+ case 11: return &op_vxor_vv;
+ case 12: return &op_vrgather_vv;
+ case 14: return &op_vrgatherei16_vv;
case 16:
if (((inst >> 25) & 1) == 0) {
- op = rv_op_vadc_vvm;
+ return &op_vadc_vvm;
}
break;
- case 17: op = rv_op_vmadc_vvm; break;
+ case 17: return &op_vmadc_vvm;
case 18:
if (((inst >> 25) & 1) == 0) {
- op = rv_op_vsbc_vvm;
+ return &op_vsbc_vvm;
}
break;
- case 19: op = rv_op_vmsbc_vvm; break;
- case 20: op = rv_op_vror_vv; break;
- case 21: op = rv_op_vrol_vv; break;
+ case 19: return &op_vmsbc_vvm;
+ case 20: return &op_vror_vv;
+ case 21: return &op_vrol_vv;
case 23:
- if (((inst >> 20) & 0b111111) == 32)
- op = rv_op_vmv_v_v;
- else if (((inst >> 25) & 1) == 0)
- op = rv_op_vmerge_vvm;
+ if (((inst >> 20) & 0b111111) == 32) {
+ return &op_vmv_v_v;
+ } else if (((inst >> 25) & 1) == 0) {
+ return &op_vmerge_vvm;
+ }
break;
- case 24: op = rv_op_vmseq_vv; break;
- case 25: op = rv_op_vmsne_vv; break;
- case 26: op = rv_op_vmsltu_vv; break;
- case 27: op = rv_op_vmslt_vv; break;
- case 28: op = rv_op_vmsleu_vv; break;
- case 29: op = rv_op_vmsle_vv; break;
- case 32: op = rv_op_vsaddu_vv; break;
- case 33: op = rv_op_vsadd_vv; break;
- case 34: op = rv_op_vssubu_vv; break;
- case 35: op = rv_op_vssub_vv; break;
- case 37: op = rv_op_vsll_vv; break;
- case 39: op = rv_op_vsmul_vv; break;
- case 40: op = rv_op_vsrl_vv; break;
- case 41: op = rv_op_vsra_vv; break;
- case 42: op = rv_op_vssrl_vv; break;
- case 43: op = rv_op_vssra_vv; break;
- case 44: op = rv_op_vnsrl_wv; break;
- case 45: op = rv_op_vnsra_wv; break;
- case 46: op = rv_op_vnclipu_wv; break;
- case 47: op = rv_op_vnclip_wv; break;
- case 48: op = rv_op_vwredsumu_vs; break;
- case 49: op = rv_op_vwredsum_vs; break;
- case 53: op = rv_op_vwsll_vv; break;
+ case 24: return &op_vmseq_vv;
+ case 25: return &op_vmsne_vv;
+ case 26: return &op_vmsltu_vv;
+ case 27: return &op_vmslt_vv;
+ case 28: return &op_vmsleu_vv;
+ case 29: return &op_vmsle_vv;
+ case 32: return &op_vsaddu_vv;
+ case 33: return &op_vsadd_vv;
+ case 34: return &op_vssubu_vv;
+ case 35: return &op_vssub_vv;
+ case 37: return &op_vsll_vv;
+ case 39: return &op_vsmul_vv;
+ case 40: return &op_vsrl_vv;
+ case 41: return &op_vsra_vv;
+ case 42: return &op_vssrl_vv;
+ case 43: return &op_vssra_vv;
+ case 44: return &op_vnsrl_wv;
+ case 45: return &op_vnsra_wv;
+ case 46: return &op_vnclipu_wv;
+ case 47: return &op_vnclip_wv;
+ case 48: return &op_vwredsumu_vs;
+ case 49: return &op_vwredsum_vs;
+ case 53: return &op_vwsll_vv;
}
break;
case 1:
switch ((inst >> 26) & 0b111111) {
- case 0: op = rv_op_vfadd_vv; break;
- case 1: op = rv_op_vfredusum_vs; break;
- case 2: op = rv_op_vfsub_vv; break;
- case 3: op = rv_op_vfredosum_vs; break;
- case 4: op = rv_op_vfmin_vv; break;
- case 5: op = rv_op_vfredmin_vs; break;
- case 6: op = rv_op_vfmax_vv; break;
- case 7: op = rv_op_vfredmax_vs; break;
- case 8: op = rv_op_vfsgnj_vv; break;
- case 9: op = rv_op_vfsgnjn_vv; break;
- case 10: op = rv_op_vfsgnjx_vv; break;
+ case 0: return &op_vfadd_vv;
+ case 1: return &op_vfredusum_vs;
+ case 2: return &op_vfsub_vv;
+ case 3: return &op_vfredosum_vs;
+ case 4: return &op_vfmin_vv;
+ case 5: return &op_vfredmin_vs;
+ case 6: return &op_vfmax_vv;
+ case 7: return &op_vfredmax_vs;
+ case 8: return &op_vfsgnj_vv;
+ case 9: return &op_vfsgnjn_vv;
+ case 10: return &op_vfsgnjx_vv;
case 16:
switch ((inst >> 15) & 0b11111) {
- case 0: if ((inst >> 25) & 1) op = rv_op_vfmv_f_s; break;
+ case 0:
+ if ((inst >> 25) & 1) {
+ return &op_vfmv_f_s;
+ }
}
break;
case 18:
switch ((inst >> 15) & 0b11111) {
- case 0: op = rv_op_vfcvt_xu_f_v; break;
- case 1: op = rv_op_vfcvt_x_f_v; break;
- case 2: op = rv_op_vfcvt_f_xu_v; break;
- case 3: op = rv_op_vfcvt_f_x_v; break;
- case 6: op = rv_op_vfcvt_rtz_xu_f_v; break;
- case 7: op = rv_op_vfcvt_rtz_x_f_v; break;
- case 8: op = rv_op_vfwcvt_xu_f_v; break;
- case 9: op = rv_op_vfwcvt_x_f_v; break;
- case 10: op = rv_op_vfwcvt_f_xu_v; break;
- case 11: op = rv_op_vfwcvt_f_x_v; break;
- case 12: op = rv_op_vfwcvt_f_f_v; break;
- case 13: op = rv_op_vfwcvtbf16_f_f_v; break;
- case 14: op = rv_op_vfwcvt_rtz_xu_f_v; break;
- case 15: op = rv_op_vfwcvt_rtz_x_f_v; break;
- case 16: op = rv_op_vfncvt_xu_f_w; break;
- case 17: op = rv_op_vfncvt_x_f_w; break;
- case 18: op = rv_op_vfncvt_f_xu_w; break;
- case 19: op = rv_op_vfncvt_f_x_w; break;
- case 20: op = rv_op_vfncvt_f_f_w; break;
- case 21: op = rv_op_vfncvt_rod_f_f_w; break;
- case 22: op = rv_op_vfncvt_rtz_xu_f_w; break;
- case 23: op = rv_op_vfncvt_rtz_x_f_w; break;
- case 29: op = rv_op_vfncvtbf16_f_f_w; break;
+ case 0: return &op_vfcvt_xu_f_v;
+ case 1: return &op_vfcvt_x_f_v;
+ case 2: return &op_vfcvt_f_xu_v;
+ case 3: return &op_vfcvt_f_x_v;
+ case 6: return &op_vfcvt_rtz_xu_f_v;
+ case 7: return &op_vfcvt_rtz_x_f_v;
+ case 8: return &op_vfwcvt_xu_f_v;
+ case 9: return &op_vfwcvt_x_f_v;
+ case 10: return &op_vfwcvt_f_xu_v;
+ case 11: return &op_vfwcvt_f_x_v;
+ case 12: return &op_vfwcvt_f_f_v;
+ case 13: return &op_vfwcvtbf16_f_f_v;
+ case 14: return &op_vfwcvt_rtz_xu_f_v;
+ case 15: return &op_vfwcvt_rtz_x_f_v;
+ case 16: return &op_vfncvt_xu_f_w;
+ case 17: return &op_vfncvt_x_f_w;
+ case 18: return &op_vfncvt_f_xu_w;
+ case 19: return &op_vfncvt_f_x_w;
+ case 20: return &op_vfncvt_f_f_w;
+ case 21: return &op_vfncvt_rod_f_f_w;
+ case 22: return &op_vfncvt_rtz_xu_f_w;
+ case 23: return &op_vfncvt_rtz_x_f_w;
+ case 29: return &op_vfncvtbf16_f_f_w;
}
break;
case 19:
switch ((inst >> 15) & 0b11111) {
- case 0: op = rv_op_vfsqrt_v; break;
- case 4: op = rv_op_vfrsqrt7_v; break;
- case 5: op = rv_op_vfrec7_v; break;
- case 16: op = rv_op_vfclass_v; break;
+ case 0: return &op_vfsqrt_v;
+ case 4: return &op_vfrsqrt7_v;
+ case 5: return &op_vfrec7_v;
+ case 16: return &op_vfclass_v;
}
break;
- case 24: op = rv_op_vmfeq_vv; break;
- case 25: op = rv_op_vmfle_vv; break;
- case 27: op = rv_op_vmflt_vv; break;
- case 28: op = rv_op_vmfne_vv; break;
- case 32: op = rv_op_vfdiv_vv; break;
- case 36: op = rv_op_vfmul_vv; break;
- case 40: op = rv_op_vfmadd_vv; break;
- case 41: op = rv_op_vfnmadd_vv; break;
- case 42: op = rv_op_vfmsub_vv; break;
- case 43: op = rv_op_vfnmsub_vv; break;
- case 44: op = rv_op_vfmacc_vv; break;
- case 45: op = rv_op_vfnmacc_vv; break;
- case 46: op = rv_op_vfmsac_vv; break;
- case 47: op = rv_op_vfnmsac_vv; break;
- case 48: op = rv_op_vfwadd_vv; break;
- case 49: op = rv_op_vfwredusum_vs; break;
- case 50: op = rv_op_vfwsub_vv; break;
- case 51: op = rv_op_vfwredosum_vs; break;
- case 52: op = rv_op_vfwadd_wv; break;
- case 54: op = rv_op_vfwsub_wv; break;
- case 56: op = rv_op_vfwmul_vv; break;
- case 59: op = rv_op_vfwmaccbf16_vv; break;
- case 60: op = rv_op_vfwmacc_vv; break;
- case 61: op = rv_op_vfwnmacc_vv; break;
- case 62: op = rv_op_vfwmsac_vv; break;
- case 63: op = rv_op_vfwnmsac_vv; break;
+ case 24: return &op_vmfeq_vv;
+ case 25: return &op_vmfle_vv;
+ case 27: return &op_vmflt_vv;
+ case 28: return &op_vmfne_vv;
+ case 32: return &op_vfdiv_vv;
+ case 36: return &op_vfmul_vv;
+ case 40: return &op_vfmadd_vv;
+ case 41: return &op_vfnmadd_vv;
+ case 42: return &op_vfmsub_vv;
+ case 43: return &op_vfnmsub_vv;
+ case 44: return &op_vfmacc_vv;
+ case 45: return &op_vfnmacc_vv;
+ case 46: return &op_vfmsac_vv;
+ case 47: return &op_vfnmsac_vv;
+ case 48: return &op_vfwadd_vv;
+ case 49: return &op_vfwredusum_vs;
+ case 50: return &op_vfwsub_vv;
+ case 51: return &op_vfwredosum_vs;
+ case 52: return &op_vfwadd_wv;
+ case 54: return &op_vfwsub_wv;
+ case 56: return &op_vfwmul_vv;
+ case 59: return &op_vfwmaccbf16_vv;
+ case 60: return &op_vfwmacc_vv;
+ case 61: return &op_vfwnmacc_vv;
+ case 62: return &op_vfwmsac_vv;
+ case 63: return &op_vfwnmsac_vv;
}
break;
case 2:
switch ((inst >> 26) & 0b111111) {
- case 0: op = rv_op_vredsum_vs; break;
- case 1: op = rv_op_vredand_vs; break;
- case 2: op = rv_op_vredor_vs; break;
- case 3: op = rv_op_vredxor_vs; break;
- case 4: op = rv_op_vredminu_vs; break;
- case 5: op = rv_op_vredmin_vs; break;
- case 6: op = rv_op_vredmaxu_vs; break;
- case 7: op = rv_op_vredmax_vs; break;
- case 8: op = rv_op_vaaddu_vv; break;
- case 9: op = rv_op_vaadd_vv; break;
- case 10: op = rv_op_vasubu_vv; break;
- case 11: op = rv_op_vasub_vv; break;
- case 12: op = rv_op_vclmul_vv; break;
- case 13: op = rv_op_vclmulh_vv; break;
+ case 0: return &op_vredsum_vs;
+ case 1: return &op_vredand_vs;
+ case 2: return &op_vredor_vs;
+ case 3: return &op_vredxor_vs;
+ case 4: return &op_vredminu_vs;
+ case 5: return &op_vredmin_vs;
+ case 6: return &op_vredmaxu_vs;
+ case 7: return &op_vredmax_vs;
+ case 8: return &op_vaaddu_vv;
+ case 9: return &op_vaadd_vv;
+ case 10: return &op_vasubu_vv;
+ case 11: return &op_vasub_vv;
+ case 12: return &op_vclmul_vv;
+ case 13: return &op_vclmulh_vv;
case 16:
switch ((inst >> 15) & 0b11111) {
- case 0: if ((inst >> 25) & 1) op = rv_op_vmv_x_s; break;
- case 16: op = rv_op_vcpop_m; break;
- case 17: op = rv_op_vfirst_m; break;
+ case 0:
+ if ((inst >> 25) & 1) {
+ return &op_vmv_x_s;
+ }
+ break;
+ case 16: return &op_vcpop_m;
+ case 17: return &op_vfirst_m;
}
break;
case 18:
switch ((inst >> 15) & 0b11111) {
- case 2: op = rv_op_vzext_vf8; break;
- case 3: op = rv_op_vsext_vf8; break;
- case 4: op = rv_op_vzext_vf4; break;
- case 5: op = rv_op_vsext_vf4; break;
- case 6: op = rv_op_vzext_vf2; break;
- case 7: op = rv_op_vsext_vf2; break;
- case 8: op = rv_op_vbrev8_v; break;
- case 9: op = rv_op_vrev8_v; break;
- case 10: op = rv_op_vbrev_v; break;
- case 12: op = rv_op_vclz_v; break;
- case 13: op = rv_op_vctz_v; break;
- case 14: op = rv_op_vcpop_v; break;
+ case 2: return &op_vzext_vf8;
+ case 3: return &op_vsext_vf8;
+ case 4: return &op_vzext_vf4;
+ case 5: return &op_vsext_vf4;
+ case 6: return &op_vzext_vf2;
+ case 7: return &op_vsext_vf2;
+ case 8: return &op_vbrev8_v;
+ case 9: return &op_vrev8_v;
+ case 10: return &op_vbrev_v;
+ case 12: return &op_vclz_v;
+ case 13: return &op_vctz_v;
+ case 14: return &op_vcpop_v;
}
break;
case 20:
switch ((inst >> 15) & 0b11111) {
- case 1: op = rv_op_vmsbf_m; break;
- case 2: op = rv_op_vmsof_m; break;
- case 3: op = rv_op_vmsif_m; break;
- case 16: op = rv_op_viota_m; break;
+ case 1: return &op_vmsbf_m; break;
+ case 2: return &op_vmsof_m;
+ case 3: return &op_vmsif_m;
+ case 16: return &op_viota_m;
case 17:
if (((inst >> 20) & 0b11111) == 0) {
- op = rv_op_vid_v;
+ return &op_vid_v;
}
break;
}
break;
- case 23: if ((inst >> 25) & 1) op = rv_op_vcompress_vm; break;
- case 24: if ((inst >> 25) & 1) op = rv_op_vmandn_mm; break;
- case 25: if ((inst >> 25) & 1) op = rv_op_vmand_mm; break;
- case 26: if ((inst >> 25) & 1) op = rv_op_vmor_mm; break;
- case 27: if ((inst >> 25) & 1) op = rv_op_vmxor_mm; break;
- case 28: if ((inst >> 25) & 1) op = rv_op_vmorn_mm; break;
- case 29: if ((inst >> 25) & 1) op = rv_op_vmnand_mm; break;
- case 30: if ((inst >> 25) & 1) op = rv_op_vmnor_mm; break;
- case 31: if ((inst >> 25) & 1) op = rv_op_vmxnor_mm; break;
- case 32: op = rv_op_vdivu_vv; break;
- case 33: op = rv_op_vdiv_vv; break;
- case 34: op = rv_op_vremu_vv; break;
- case 35: op = rv_op_vrem_vv; break;
- case 36: op = rv_op_vmulhu_vv; break;
- case 37: op = rv_op_vmul_vv; break;
- case 38: op = rv_op_vmulhsu_vv; break;
- case 39: op = rv_op_vmulh_vv; break;
- case 41: op = rv_op_vmadd_vv; break;
- case 43: op = rv_op_vnmsub_vv; break;
- case 45: op = rv_op_vmacc_vv; break;
- case 47: op = rv_op_vnmsac_vv; break;
- case 48: op = rv_op_vwaddu_vv; break;
- case 49: op = rv_op_vwadd_vv; break;
- case 50: op = rv_op_vwsubu_vv; break;
- case 51: op = rv_op_vwsub_vv; break;
- case 52: op = rv_op_vwaddu_wv; break;
- case 53: op = rv_op_vwadd_wv; break;
- case 54: op = rv_op_vwsubu_wv; break;
- case 55: op = rv_op_vwsub_wv; break;
- case 56: op = rv_op_vwmulu_vv; break;
- case 58: op = rv_op_vwmulsu_vv; break;
- case 59: op = rv_op_vwmul_vv; break;
- case 60: op = rv_op_vwmaccu_vv; break;
- case 61: op = rv_op_vwmacc_vv; break;
- case 63: op = rv_op_vwmaccsu_vv; break;
+ case 23:
+ if ((inst >> 25) & 1) {
+ return &op_vcompress_vm;
+ }
+ break;
+ case 24:
+ if ((inst >> 25) & 1) {
+ return &op_vmandn_mm;
+ }
+ break;
+ case 25:
+ if ((inst >> 25) & 1) {
+ return &op_vmand_mm;
+ }
+ break;
+ case 26:
+ if ((inst >> 25) & 1) {
+ return &op_vmor_mm;
+ }
+ break;
+ case 27:
+ if ((inst >> 25) & 1) {
+ return &op_vmxor_mm;
+ }
+ break;
+ case 28:
+ if ((inst >> 25) & 1) {
+ return &op_vmorn_mm;
+ }
+ break;
+ case 29:
+ if ((inst >> 25) & 1) {
+ return &op_vmnand_mm;
+ }
+ break;
+ case 30:
+ if ((inst >> 25) & 1) {
+ return &op_vmnor_mm;
+ }
+ break;
+ case 31:
+ if ((inst >> 25) & 1) {
+ return &op_vmxnor_mm;
+ }
+ break;
+ case 32: return &op_vdivu_vv;
+ case 33: return &op_vdiv_vv;
+ case 34: return &op_vremu_vv;
+ case 35: return &op_vrem_vv;
+ case 36: return &op_vmulhu_vv;
+ case 37: return &op_vmul_vv;
+ case 38: return &op_vmulhsu_vv;
+ case 39: return &op_vmulh_vv;
+ case 41: return &op_vmadd_vv;
+ case 43: return &op_vnmsub_vv;
+ case 45: return &op_vmacc_vv;
+ case 47: return &op_vnmsac_vv;
+ case 48: return &op_vwaddu_vv;
+ case 49: return &op_vwadd_vv;
+ case 50: return &op_vwsubu_vv;
+ case 51: return &op_vwsub_vv;
+ case 52: return &op_vwaddu_wv;
+ case 53: return &op_vwadd_wv;
+ case 54: return &op_vwsubu_wv;
+ case 55: return &op_vwsub_wv;
+ case 56: return &op_vwmulu_vv;
+ case 58: return &op_vwmulsu_vv;
+ case 59: return &op_vwmul_vv;
+ case 60: return &op_vwmaccu_vv;
+ case 61: return &op_vwmacc_vv;
+ case 63: return &op_vwmaccsu_vv;
}
break;
case 3:
switch ((inst >> 26) & 0b111111) {
- case 0: op = rv_op_vadd_vi; break;
- case 3: op = rv_op_vrsub_vi; break;
- case 9: op = rv_op_vand_vi; break;
- case 10: op = rv_op_vor_vi; break;
- case 11: op = rv_op_vxor_vi; break;
- case 12: op = rv_op_vrgather_vi; break;
- case 14: op = rv_op_vslideup_vi; break;
- case 15: op = rv_op_vslidedown_vi; break;
+ case 0: return &op_vadd_vi;
+ case 3: return &op_vrsub_vi;
+ case 9: return &op_vand_vi;
+ case 10: return &op_vor_vi;
+ case 11: return &op_vxor_vi;
+ case 12: return &op_vrgather_vi;
+ case 14: return &op_vslideup_vi;
+ case 15: return &op_vslidedown_vi;
case 16:
if (((inst >> 25) & 1) == 0) {
- op = rv_op_vadc_vim;
+ return &op_vadc_vim;
}
break;
- case 17: op = rv_op_vmadc_vim; break;
- case 20: case 21: op = rv_op_vror_vi; break;
+ case 17: return &op_vmadc_vim;
+ case 20: case 21: return &op_vror_vi;
case 23:
- if (((inst >> 20) & 0b111111) == 32)
- op = rv_op_vmv_v_i;
- else if (((inst >> 25) & 1) == 0)
- op = rv_op_vmerge_vim;
+ if (((inst >> 20) & 0b111111) == 32) {
+ return &op_vmv_v_i;
+ } else if (((inst >> 25) & 1) == 0) {
+ return &op_vmerge_vim;
+ }
break;
- case 24: op = rv_op_vmseq_vi; break;
- case 25: op = rv_op_vmsne_vi; break;
- case 28: op = rv_op_vmsleu_vi; break;
- case 29: op = rv_op_vmsle_vi; break;
- case 30: op = rv_op_vmsgtu_vi; break;
- case 31: op = rv_op_vmsgt_vi; break;
- case 32: op = rv_op_vsaddu_vi; break;
- case 33: op = rv_op_vsadd_vi; break;
- case 37: op = rv_op_vsll_vi; break;
+ case 24: return &op_vmseq_vi;
+ case 25: return &op_vmsne_vi;
+ case 28: return &op_vmsleu_vi;
+ case 29: return &op_vmsle_vi;
+ case 30: return &op_vmsgtu_vi;
+ case 31: return &op_vmsgt_vi;
+ case 32: return &op_vsaddu_vi;
+ case 33: return &op_vsadd_vi;
+ case 37: return &op_vsll_vi;
case 39:
switch ((inst >> 15) & 0b11111) {
- case 0: op = rv_op_vmv1r_v; break;
- case 1: op = rv_op_vmv2r_v; break;
- case 3: op = rv_op_vmv4r_v; break;
- case 7: op = rv_op_vmv8r_v; break;
+ case 0: return &op_vmv1r_v;
+ case 1: return &op_vmv2r_v;
+ case 3: return &op_vmv4r_v;
+ case 7: return &op_vmv8r_v;
}
break;
- case 40: op = rv_op_vsrl_vi; break;
- case 41: op = rv_op_vsra_vi; break;
- case 42: op = rv_op_vssrl_vi; break;
- case 43: op = rv_op_vssra_vi; break;
- case 44: op = rv_op_vnsrl_wi; break;
- case 45: op = rv_op_vnsra_wi; break;
- case 46: op = rv_op_vnclipu_wi; break;
- case 47: op = rv_op_vnclip_wi; break;
- case 53: op = rv_op_vwsll_vi; break;
+ case 40: return &op_vsrl_vi;
+ case 41: return &op_vsra_vi;
+ case 42: return &op_vssrl_vi;
+ case 43: return &op_vssra_vi;
+ case 44: return &op_vnsrl_wi;
+ case 45: return &op_vnsra_wi;
+ case 46: return &op_vnclipu_wi;
+ case 47: return &op_vnclip_wi;
+ case 53: return &op_vwsll_vi;
}
break;
case 4:
switch ((inst >> 26) & 0b111111) {
- case 0: op = rv_op_vadd_vx; break;
- case 1: op = rv_op_vandn_vx; break;
- case 2: op = rv_op_vsub_vx; break;
- case 3: op = rv_op_vrsub_vx; break;
- case 4: op = rv_op_vminu_vx; break;
- case 5: op = rv_op_vmin_vx; break;
- case 6: op = rv_op_vmaxu_vx; break;
- case 7: op = rv_op_vmax_vx; break;
- case 9: op = rv_op_vand_vx; break;
- case 10: op = rv_op_vor_vx; break;
- case 11: op = rv_op_vxor_vx; break;
- case 12: op = rv_op_vrgather_vx; break;
- case 14: op = rv_op_vslideup_vx; break;
- case 15: op = rv_op_vslidedown_vx; break;
+ case 0: return &op_vadd_vx;
+ case 1: return &op_vandn_vx;
+ case 2: return &op_vsub_vx;
+ case 3: return &op_vrsub_vx;
+ case 4: return &op_vminu_vx;
+ case 5: return &op_vmin_vx;
+ case 6: return &op_vmaxu_vx;
+ case 7: return &op_vmax_vx;
+ case 9: return &op_vand_vx;
+ case 10: return &op_vor_vx;
+ case 11: return &op_vxor_vx;
+ case 12: return &op_vrgather_vx;
+ case 14: return &op_vslideup_vx;
+ case 15: return &op_vslidedown_vx;
case 16:
if (((inst >> 25) & 1) == 0) {
- op = rv_op_vadc_vxm;
+ return &op_vadc_vxm;
}
break;
- case 17: op = rv_op_vmadc_vxm; break;
+ case 17: return &op_vmadc_vxm;
case 18:
if (((inst >> 25) & 1) == 0) {
- op = rv_op_vsbc_vxm;
+ return &op_vsbc_vxm;
}
break;
- case 19: op = rv_op_vmsbc_vxm; break;
- case 20: op = rv_op_vror_vx; break;
- case 21: op = rv_op_vrol_vx; break;
+ case 19: return &op_vmsbc_vxm;
+ case 20: return &op_vror_vx;
+ case 21: return &op_vrol_vx;
case 23:
- if (((inst >> 20) & 0b111111) == 32)
- op = rv_op_vmv_v_x;
- else if (((inst >> 25) & 1) == 0)
- op = rv_op_vmerge_vxm;
+ if (((inst >> 20) & 0b111111) == 32) {
+ return &op_vmv_v_x;
+ } else if (((inst >> 25) & 1) == 0) {
+ return &op_vmerge_vxm;
+ }
break;
- case 24: op = rv_op_vmseq_vx; break;
- case 25: op = rv_op_vmsne_vx; break;
- case 26: op = rv_op_vmsltu_vx; break;
- case 27: op = rv_op_vmslt_vx; break;
- case 28: op = rv_op_vmsleu_vx; break;
- case 29: op = rv_op_vmsle_vx; break;
- case 30: op = rv_op_vmsgtu_vx; break;
- case 31: op = rv_op_vmsgt_vx; break;
- case 32: op = rv_op_vsaddu_vx; break;
- case 33: op = rv_op_vsadd_vx; break;
- case 34: op = rv_op_vssubu_vx; break;
- case 35: op = rv_op_vssub_vx; break;
- case 37: op = rv_op_vsll_vx; break;
- case 39: op = rv_op_vsmul_vx; break;
- case 40: op = rv_op_vsrl_vx; break;
- case 41: op = rv_op_vsra_vx; break;
- case 42: op = rv_op_vssrl_vx; break;
- case 43: op = rv_op_vssra_vx; break;
- case 44: op = rv_op_vnsrl_wx; break;
- case 45: op = rv_op_vnsra_wx; break;
- case 46: op = rv_op_vnclipu_wx; break;
- case 47: op = rv_op_vnclip_wx; break;
- case 53: op = rv_op_vwsll_vx; break;
+ case 24: return &op_vmseq_vx;
+ case 25: return &op_vmsne_vx;
+ case 26: return &op_vmsltu_vx;
+ case 27: return &op_vmslt_vx;
+ case 28: return &op_vmsleu_vx;
+ case 29: return &op_vmsle_vx;
+ case 30: return &op_vmsgtu_vx;
+ case 31: return &op_vmsgt_vx;
+ case 32: return &op_vsaddu_vx;
+ case 33: return &op_vsadd_vx;
+ case 34: return &op_vssubu_vx;
+ case 35: return &op_vssub_vx;
+ case 37: return &op_vsll_vx;
+ case 39: return &op_vsmul_vx;
+ case 40: return &op_vsrl_vx;
+ case 41: return &op_vsra_vx;
+ case 42: return &op_vssrl_vx;
+ case 43: return &op_vssra_vx;
+ case 44: return &op_vnsrl_wx;
+ case 45: return &op_vnsra_wx;
+ case 46: return &op_vnclipu_wx;
+ case 47: return &op_vnclip_wx;
+ case 53: return &op_vwsll_vx;
}
break;
case 5:
switch ((inst >> 26) & 0b111111) {
- case 0: op = rv_op_vfadd_vf; break;
- case 2: op = rv_op_vfsub_vf; break;
- case 4: op = rv_op_vfmin_vf; break;
- case 6: op = rv_op_vfmax_vf; break;
- case 8: op = rv_op_vfsgnj_vf; break;
- case 9: op = rv_op_vfsgnjn_vf; break;
- case 10: op = rv_op_vfsgnjx_vf; break;
- case 14: op = rv_op_vfslide1up_vf; break;
- case 15: op = rv_op_vfslide1down_vf; break;
+ case 0: return &op_vfadd_vf;
+ case 2: return &op_vfsub_vf;
+ case 4: return &op_vfmin_vf;
+ case 6: return &op_vfmax_vf;
+ case 8: return &op_vfsgnj_vf;
+ case 9: return &op_vfsgnjn_vf;
+ case 10: return &op_vfsgnjx_vf;
+ case 14: return &op_vfslide1up_vf;
+ case 15: return &op_vfslide1down_vf;
case 16:
switch ((inst >> 20) & 0b11111) {
- case 0: if ((inst >> 25) & 1) op = rv_op_vfmv_s_f; break;
+ case 0:
+ if ((inst >> 25) & 1) {
+ return &op_vfmv_s_f;
+ }
}
break;
case 23:
- if (((inst >> 25) & 1) == 0)
- op = rv_op_vfmerge_vfm;
- else if (((inst >> 20) & 0b111111) == 32)
- op = rv_op_vfmv_v_f;
+ if (((inst >> 25) & 1) == 0) {
+ return &op_vfmerge_vfm;
+ } else if (((inst >> 20) & 0b111111) == 32) {
+ return &op_vfmv_v_f;
+ }
break;
- case 24: op = rv_op_vmfeq_vf; break;
- case 25: op = rv_op_vmfle_vf; break;
- case 27: op = rv_op_vmflt_vf; break;
- case 28: op = rv_op_vmfne_vf; break;
- case 29: op = rv_op_vmfgt_vf; break;
- case 31: op = rv_op_vmfge_vf; break;
- case 32: op = rv_op_vfdiv_vf; break;
- case 33: op = rv_op_vfrdiv_vf; break;
- case 36: op = rv_op_vfmul_vf; break;
- case 39: op = rv_op_vfrsub_vf; break;
- case 40: op = rv_op_vfmadd_vf; break;
- case 41: op = rv_op_vfnmadd_vf; break;
- case 42: op = rv_op_vfmsub_vf; break;
- case 43: op = rv_op_vfnmsub_vf; break;
- case 44: op = rv_op_vfmacc_vf; break;
- case 45: op = rv_op_vfnmacc_vf; break;
- case 46: op = rv_op_vfmsac_vf; break;
- case 47: op = rv_op_vfnmsac_vf; break;
- case 48: op = rv_op_vfwadd_vf; break;
- case 50: op = rv_op_vfwsub_vf; break;
- case 52: op = rv_op_vfwadd_wf; break;
- case 54: op = rv_op_vfwsub_wf; break;
- case 56: op = rv_op_vfwmul_vf; break;
- case 59: op = rv_op_vfwmaccbf16_vf; break;
- case 60: op = rv_op_vfwmacc_vf; break;
- case 61: op = rv_op_vfwnmacc_vf; break;
- case 62: op = rv_op_vfwmsac_vf; break;
- case 63: op = rv_op_vfwnmsac_vf; break;
+ case 24: return &op_vmfeq_vf;
+ case 25: return &op_vmfle_vf;
+ case 27: return &op_vmflt_vf;
+ case 28: return &op_vmfne_vf;
+ case 29: return &op_vmfgt_vf;
+ case 31: return &op_vmfge_vf;
+ case 32: return &op_vfdiv_vf;
+ case 33: return &op_vfrdiv_vf;
+ case 36: return &op_vfmul_vf;
+ case 39: return &op_vfrsub_vf;
+ case 40: return &op_vfmadd_vf;
+ case 41: return &op_vfnmadd_vf;
+ case 42: return &op_vfmsub_vf;
+ case 43: return &op_vfnmsub_vf;
+ case 44: return &op_vfmacc_vf;
+ case 45: return &op_vfnmacc_vf;
+ case 46: return &op_vfmsac_vf;
+ case 47: return &op_vfnmsac_vf;
+ case 48: return &op_vfwadd_vf;
+ case 50: return &op_vfwsub_vf;
+ case 52: return &op_vfwadd_wf;
+ case 54: return &op_vfwsub_wf;
+ case 56: return &op_vfwmul_vf;
+ case 59: return &op_vfwmaccbf16_vf;
+ case 60: return &op_vfwmacc_vf;
+ case 61: return &op_vfwnmacc_vf;
+ case 62: return &op_vfwmsac_vf;
+ case 63: return &op_vfwnmsac_vf;
}
break;
case 6:
switch ((inst >> 26) & 0b111111) {
- case 8: op = rv_op_vaaddu_vx; break;
- case 9: op = rv_op_vaadd_vx; break;
- case 10: op = rv_op_vasubu_vx; break;
- case 11: op = rv_op_vasub_vx; break;
- case 12: op = rv_op_vclmul_vx; break;
- case 13: op = rv_op_vclmulh_vx; break;
- case 14: op = rv_op_vslide1up_vx; break;
- case 15: op = rv_op_vslide1down_vx; break;
+ case 8: return &op_vaaddu_vx;
+ case 9: return &op_vaadd_vx;
+ case 10: return &op_vasubu_vx;
+ case 11: return &op_vasub_vx;
+ case 12: return &op_vclmul_vx;
+ case 13: return &op_vclmulh_vx;
+ case 14: return &op_vslide1up_vx;
+ case 15: return &op_vslide1down_vx;
case 16:
switch ((inst >> 20) & 0b11111) {
- case 0: if ((inst >> 25) & 1) op = rv_op_vmv_s_x; break;
+ case 0:
+ if ((inst >> 25) & 1) {
+ return &op_vmv_s_x;
+ }
}
break;
- case 32: op = rv_op_vdivu_vx; break;
- case 33: op = rv_op_vdiv_vx; break;
- case 34: op = rv_op_vremu_vx; break;
- case 35: op = rv_op_vrem_vx; break;
- case 36: op = rv_op_vmulhu_vx; break;
- case 37: op = rv_op_vmul_vx; break;
- case 38: op = rv_op_vmulhsu_vx; break;
- case 39: op = rv_op_vmulh_vx; break;
- case 41: op = rv_op_vmadd_vx; break;
- case 43: op = rv_op_vnmsub_vx; break;
- case 45: op = rv_op_vmacc_vx; break;
- case 47: op = rv_op_vnmsac_vx; break;
- case 48: op = rv_op_vwaddu_vx; break;
- case 49: op = rv_op_vwadd_vx; break;
- case 50: op = rv_op_vwsubu_vx; break;
- case 51: op = rv_op_vwsub_vx; break;
- case 52: op = rv_op_vwaddu_wx; break;
- case 53: op = rv_op_vwadd_wx; break;
- case 54: op = rv_op_vwsubu_wx; break;
- case 55: op = rv_op_vwsub_wx; break;
- case 56: op = rv_op_vwmulu_vx; break;
- case 58: op = rv_op_vwmulsu_vx; break;
- case 59: op = rv_op_vwmul_vx; break;
- case 60: op = rv_op_vwmaccu_vx; break;
- case 61: op = rv_op_vwmacc_vx; break;
- case 62: op = rv_op_vwmaccus_vx; break;
- case 63: op = rv_op_vwmaccsu_vx; break;
+ case 32: return &op_vdivu_vx;
+ case 33: return &op_vdiv_vx;
+ case 34: return &op_vremu_vx;
+ case 35: return &op_vrem_vx;
+ case 36: return &op_vmulhu_vx;
+ case 37: return &op_vmul_vx;
+ case 38: return &op_vmulhsu_vx;
+ case 39: return &op_vmulh_vx;
+ case 41: return &op_vmadd_vx;
+ case 43: return &op_vnmsub_vx;
+ case 45: return &op_vmacc_vx;
+ case 47: return &op_vnmsac_vx;
+ case 48: return &op_vwaddu_vx;
+ case 49: return &op_vwadd_vx;
+ case 50: return &op_vwsubu_vx;
+ case 51: return &op_vwsub_vx;
+ case 52: return &op_vwaddu_wx;
+ case 53: return &op_vwadd_wx;
+ case 54: return &op_vwsubu_wx;
+ case 55: return &op_vwsub_wx;
+ case 56: return &op_vwmulu_vx;
+ case 58: return &op_vwmulsu_vx;
+ case 59: return &op_vwmul_vx;
+ case 60: return &op_vwmaccu_vx;
+ case 61: return &op_vwmacc_vx;
+ case 62: return &op_vwmaccus_vx;
+ case 63: return &op_vwmaccsu_vx;
}
break;
case 7:
if (((inst >> 31) & 1) == 0) {
- op = rv_op_vsetvli;
+ return &op_vsetvli;
} else if ((inst >> 30) & 1) {
- op = rv_op_vsetivli;
+ return &op_vsetivli;
} else if (((inst >> 25) & 0b11111) == 0) {
- op = rv_op_vsetvl;
+ return &op_vsetvl;
}
break;
}
break;
case 22:
switch ((inst >> 12) & 0b111) {
- case 0: op = rv_op_addid; break;
+ case 0: return &op_addid;
case 1:
switch ((inst >> 26) & 0b111111) {
- case 0: op = rv_op_sllid; break;
+ case 0: return &op_sllid;
}
break;
case 5:
switch ((inst >> 26) & 0b111111) {
- case 0: op = rv_op_srlid; break;
- case 16: op = rv_op_sraid; break;
+ case 0: return &op_srlid;
+ case 16: return &op_sraid;
}
break;
}
break;
case 24:
switch ((inst >> 12) & 0b111) {
- case 0: op = rv_op_beq; break;
- case 1: op = rv_op_bne; break;
- case 4: op = rv_op_blt; break;
- case 5: op = rv_op_bge; break;
- case 6: op = rv_op_bltu; break;
- case 7: op = rv_op_bgeu; break;
+ case 0: return &op_beq;
+ case 1: return &op_bne;
+ case 4: return &op_blt;
+ case 5: return &op_bge;
+ case 6: return &op_bltu;
+ case 7: return &op_bgeu;
}
break;
case 25:
switch ((inst >> 12) & 0b111) {
- case 0: op = rv_op_jalr; break;
+ case 0: return &op_jalr;
}
break;
- case 27: op = rv_op_jal; break;
+ case 27: return &op_jal;
case 28:
switch ((inst >> 12) & 0b111) {
case 0:
@@ -2483,76 +2504,76 @@ static const rv_opcode_data *decode_inst_opcode(rv_decode *dec, rv_isa isa)
((inst >> 7) & 0b000000011111)) {
case 0:
switch ((inst >> 15) & 0b1111111111) {
- case 0: op = rv_op_ecall; break;
- case 32: op = rv_op_ebreak; break;
- case 64: op = rv_op_uret; break;
- case 416: op = rv_op_wrs_nto; break;
- case 928: op = rv_op_wrs_sto; break;
+ case 0: return &op_ecall;
+ case 32: return &op_ebreak;
+ case 64: return &op_uret;
+ case 416: return &op_wrs_nto;
+ case 928: return &op_wrs_sto;
}
break;
case 256:
switch ((inst >> 20) & 0b11111) {
case 2:
switch ((inst >> 15) & 0b11111) {
- case 0: op = rv_op_sret; break;
+ case 0: return &op_sret;
}
break;
- case 4: op = rv_op_sfence_vm; break;
+ case 4: return &op_sfence_vm;
case 5:
switch ((inst >> 15) & 0b11111) {
- case 0: op = rv_op_wfi; break;
+ case 0: return &op_wfi;
}
break;
}
break;
- case 288: op = rv_op_sfence_vma; break;
+ case 288: return &op_sfence_vma;
case 512:
switch ((inst >> 15) & 0b1111111111) {
- case 64: op = rv_op_hret; break;
+ case 64: return &op_hret;
}
break;
case 768:
switch ((inst >> 15) & 0b1111111111) {
- case 64: op = rv_op_mret; break;
+ case 64: return &op_mret;
}
break;
case 1792:
switch ((inst >> 15) & 0b1111111111) {
- case 64: op = rv_op_mnret; break;
+ case 64: return &op_mnret;
}
break;
case 1952:
switch ((inst >> 15) & 0b1111111111) {
- case 576: op = rv_op_dret; break;
+ case 576: return &op_dret;
}
break;
}
break;
case 1:
switch (operand_csr12(inst)) {
- case 1: op = rv_op_fsflags; break;
- case 2: op = rv_op_fsrm; break;
- case 3: op = rv_op_fscsr; break;
- default: op = rv_op_csrrw; break;
+ case 1: return &op_fsflags;
+ case 2: return &op_fsrm;
+ case 3: return &op_fscsr;
+ default: return &op_csrrw;
}
break;
case 2:
- op = rv_op_csrrs;
+ return &op_csrrs;
if (operand_rs1(inst) == 0) {
switch (operand_csr12(inst)) {
- case 0x001: op = rv_op_frflags; break;
- case 0x002: op = rv_op_frrm; break;
- case 0x003: op = rv_op_frcsr; break;
- case 0xc00: op = rv_op_rdcycle; break;
- case 0xc01: op = rv_op_rdtime; break;
- case 0xc02: op = rv_op_rdinstret; break;
- case 0xc80: op = rv_op_rdcycleh; break;
- case 0xc81: op = rv_op_rdtimeh; break;
- case 0xc82: op = rv_op_rdinstreth; break;
+ case 0x001: return &op_frflags;
+ case 0x002: return &op_frrm;
+ case 0x003: return &op_frcsr;
+ case 0xc00: return &op_rdcycle;
+ case 0xc01: return &op_rdtime;
+ case 0xc02: return &op_rdinstret;
+ case 0xc80: return &op_rdcycleh;
+ case 0xc81: return &op_rdtimeh;
+ case 0xc82: return &op_rdinstreth;
}
}
break;
- case 3: op = rv_op_csrrc; break;
+ case 3: return &op_csrrc;
case 4:
if (dec->cfg && dec->cfg->ext_zimop) {
if (((inst >> 22) & 0b1011001111) == 0b1000000111) {
@@ -2560,15 +2581,15 @@ static const rv_opcode_data *decode_inst_opcode(rv_decode *dec, rv_isa isa)
&& operand_mop_r_imm(inst) == 28) {
switch (operand_rs1(inst)) {
case 0:
- return &rvi_opcode_data[rv_op_ssrdp];
+ return &op_ssrdp;
case 1:
case 5:
if (operand_rd(inst) == 0) {
- return &rvi_opcode_data[rv_op_sspopchk];
+ return &op_sspopchk;
}
}
}
- return &rvi_opcode_data[rv_op_mop_r];
+ return &op_mop_r;
}
if (((inst >> 25) & 0b1011001) == 0b1000001) {
if (dec->cfg->ext_zicfiss
@@ -2578,79 +2599,79 @@ static const rv_opcode_data *decode_inst_opcode(rv_decode *dec, rv_isa isa)
switch (operand_rs2(inst)) {
case 1:
case 5:
- return &rvi_opcode_data[rv_op_sspush];
+ return &op_sspush;
}
}
- return &rvi_opcode_data[rv_op_mop_rr];
+ return &op_mop_rr;
}
}
break;
case 5:
switch (operand_csr12(inst)) {
- case 1: op = rv_op_fsflagsi; break;
- case 2: op = rv_op_fsrmi; break;
- default: op = rv_op_csrrwi; break;
+ case 1: return &op_fsflagsi;
+ case 2: return &op_fsrmi;
+ default: return &op_csrrwi;
}
break;
- case 6: op = rv_op_csrrsi; break;
- case 7: op = rv_op_csrrci; break;
+ case 6: return &op_csrrsi;
+ case 7: return &op_csrrci;
}
break;
case 29:
if (((inst >> 25) & 1) == 1 && ((inst >> 12) & 0b111) == 2) {
switch ((inst >> 26) & 0b111111) {
- case 32: op = rv_op_vsm3me_vv; break;
- case 33: op = rv_op_vsm4k_vi; break;
- case 34: op = rv_op_vaeskf1_vi; break;
+ case 32: return &op_vsm3me_vv;
+ case 33: return &op_vsm4k_vi;
+ case 34: return &op_vaeskf1_vi;
case 40:
switch ((inst >> 15) & 0b11111) {
- case 0: op = rv_op_vaesdm_vv; break;
- case 1: op = rv_op_vaesdf_vv; break;
- case 2: op = rv_op_vaesem_vv; break;
- case 3: op = rv_op_vaesef_vv; break;
- case 16: op = rv_op_vsm4r_vv; break;
- case 17: op = rv_op_vgmul_vv; break;
+ case 0: return &op_vaesdm_vv;
+ case 1: return &op_vaesdf_vv;
+ case 2: return &op_vaesem_vv;
+ case 3: return &op_vaesef_vv;
+ case 16: return &op_vsm4r_vv;
+ case 17: return &op_vgmul_vv;
}
break;
case 41:
switch ((inst >> 15) & 0b11111) {
- case 0: op = rv_op_vaesdm_vs; break;
- case 1: op = rv_op_vaesdf_vs; break;
- case 2: op = rv_op_vaesem_vs; break;
- case 3: op = rv_op_vaesef_vs; break;
- case 7: op = rv_op_vaesz_vs; break;
- case 16: op = rv_op_vsm4r_vs; break;
+ case 0: return &op_vaesdm_vs;
+ case 1: return &op_vaesdf_vs;
+ case 2: return &op_vaesem_vs;
+ case 3: return &op_vaesef_vs;
+ case 7: return &op_vaesz_vs;
+ case 16: return &op_vsm4r_vs;
}
break;
- case 42: op = rv_op_vaeskf2_vi; break;
- case 43: op = rv_op_vsm3c_vi; break;
- case 44: op = rv_op_vghsh_vv; break;
- case 45: op = rv_op_vsha2ms_vv; break;
- case 46: op = rv_op_vsha2ch_vv; break;
- case 47: op = rv_op_vsha2cl_vv; break;
+ case 42: return &op_vaeskf2_vi;
+ case 43: return &op_vsm3c_vi;
+ case 44: return &op_vghsh_vv;
+ case 45: return &op_vsha2ms_vv;
+ case 46: return &op_vsha2ch_vv;
+ case 47: return &op_vsha2cl_vv;
}
}
break;
case 30:
switch (((inst >> 22) & 0b1111111000) |
((inst >> 12) & 0b0000000111)) {
- case 0: op = rv_op_addd; break;
- case 1: op = rv_op_slld; break;
- case 5: op = rv_op_srld; break;
- case 8: op = rv_op_muld; break;
- case 12: op = rv_op_divd; break;
- case 13: op = rv_op_divud; break;
- case 14: op = rv_op_remd; break;
- case 15: op = rv_op_remud; break;
- case 256: op = rv_op_subd; break;
- case 261: op = rv_op_srad; break;
+ case 0: return &op_addd;
+ case 1: return &op_slld;
+ case 5: return &op_srld;
+ case 8: return &op_muld;
+ case 12: return &op_divd;
+ case 13: return &op_divud;
+ case 14: return &op_remd;
+ case 15: return &op_remud;
+ case 256: return &op_subd;
+ case 261: return &op_srad;
}
break;
}
break;
}
- return op == rv_op_illegal ? NULL : &rvi_opcode_data[op];
+ return NULL;
}
/* decode operands */
@@ -3446,7 +3467,7 @@ static GString *disasm_inst(rv_isa isa, uint64_t pc, rv_inst inst,
}
}
if (!op) {
- op = &rvi_opcode_data[rv_op_illegal];
+ op = &op_illegal;
}
decode_inst_operands(&dec, isa, op);
diff --git a/disas/riscv-op.c.inc b/disas/riscv-op.c.inc
index 802a521bca..cc939f557f 100644
--- a/disas/riscv-op.c.inc
+++ b/disas/riscv-op.c.inc
@@ -225,51 +225,51 @@ OP(fcvt_q_l, "fcvt.q.l", rv_codec_r_m, rv_fmt_rm_frd_rs1)
OP(fcvt_q_lu, "fcvt.q.lu", rv_codec_r_m, rv_fmt_rm_frd_rs1)
OP(fmv_x_q, "fmv.x.q", rv_codec_r, rv_fmt_rd_frs1)
OP(fmv_q_x, "fmv.q.x", rv_codec_r, rv_fmt_frd_rs1)
-OP(c_addi4spn, "c.addi4spn", rv_codec_ciw_4spn, NULL, DECOMP(rv_op_addi))
-OP(c_fld, "c.fld", rv_codec_cl_ld, NULL, DECOMP(rv_op_fld))
-OP(c_lw, "c.lw", rv_codec_cl_lw, NULL, DECOMP(rv_op_lw))
-OP(c_flw, "c.flw", rv_codec_cl_lw, NULL, DECOMP(rv_op_flw))
-OP(c_fsd, "c.fsd", rv_codec_cs_sd, NULL, DECOMP(rv_op_fsd))
-OP(c_sw, "c.sw", rv_codec_cs_sw, NULL, DECOMP(rv_op_sw))
-OP(c_fsw, "c.fsw", rv_codec_cs_sw, NULL, DECOMP(rv_op_fsw))
-OP(c_addi, "c.addi", rv_codec_ci, NULL, DECOMP(rv_op_addi))
-OP(c_jal, "c.jal", rv_codec_cj_jal, NULL, DECOMP(rv_op_jal))
-OP(c_li, "c.li", rv_codec_ci_li, NULL, DECOMP(rv_op_addi))
-OP(c_addi16sp, "c.addi16sp", rv_codec_ci_16sp, NULL, DECOMP(rv_op_addi))
-OP(c_lui, "c.lui", rv_codec_ci_lui, NULL, DECOMP(rv_op_lui))
-OP(c_srli, "c.srli", rv_codec_cb_sh6, NULL, DECOMP(rv_op_srli))
-OP(c_srai, "c.srai", rv_codec_cb_sh6, NULL, DECOMP(rv_op_srai))
-OP(c_andi, "c.andi", rv_codec_cb_imm, NULL, DECOMP(rv_op_andi))
-OP(c_sub, "c.sub", rv_codec_cs, NULL, DECOMP(rv_op_sub))
-OP(c_xor, "c.xor", rv_codec_cs, NULL, DECOMP(rv_op_xor))
-OP(c_or, "c.or", rv_codec_cs, NULL, DECOMP(rv_op_or))
-OP(c_and, "c.and", rv_codec_cs, NULL, DECOMP(rv_op_and))
-OP(c_subw, "c.subw", rv_codec_cs, NULL, DECOMP(rv_op_subw))
-OP(c_addw, "c.addw", rv_codec_cs, NULL, DECOMP(rv_op_addw))
-OP(c_j, "c.j", rv_codec_cj, NULL, DECOMP(rv_op_j))
-OP(c_beqz, "c.beqz", rv_codec_cb, NULL, DECOMP(rv_op_beqz))
-OP(c_bnez, "c.bnez", rv_codec_cb, NULL, DECOMP(rv_op_bnez))
-OP(c_slli, "c.slli", rv_codec_ci_sh6, NULL, DECOMP(rv_op_slli))
-OP(c_fldsp, "c.fldsp", rv_codec_ci_ldsp, NULL, DECOMP(rv_op_fld))
-OP(c_lwsp, "c.lwsp", rv_codec_ci_lwsp, NULL, DECOMP(rv_op_lw))
-OP(c_flwsp, "c.flwsp", rv_codec_ci_lwsp, NULL, DECOMP(rv_op_flw))
-OP(c_jr, "c.jr", rv_codec_cr_jr, NULL, DECOMP(rv_op_jr))
-OP(c_mv, "c.mv", rv_codec_cr_mv, NULL, DECOMP(rv_op_mv))
-OP(c_ebreak, "c.ebreak", rv_codec_ci_none, NULL, DECOMP(rv_op_ebreak))
-OP(c_jalr, "c.jalr", rv_codec_cr_jalr, NULL, DECOMP(rv_op_jalr))
-OP(c_add, "c.add", rv_codec_cr, NULL, DECOMP(rv_op_add))
-OP(c_fsdsp, "c.fsdsp", rv_codec_css_sdsp, NULL, DECOMP(rv_op_fsd))
-OP(c_swsp, "c.swsp", rv_codec_css_swsp, NULL, DECOMP(rv_op_sw))
-OP(c_fswsp, "c.fswsp", rv_codec_css_swsp, NULL, DECOMP(rv_op_fsw))
-OP(c_ld, "c.ld", rv_codec_cl_ld, NULL, DECOMP(rv_op_ld))
-OP(c_sd, "c.sd", rv_codec_cs_sd, NULL, DECOMP(rv_op_sd))
-OP(c_addiw, "c.addiw", rv_codec_ci, NULL, DECOMP(rv_op_addiw))
-OP(c_ldsp, "c.ldsp", rv_codec_ci_ldsp, NULL, DECOMP(rv_op_ld))
-OP(c_sdsp, "c.sdsp", rv_codec_css_sdsp, NULL, DECOMP(rv_op_sd))
-OP(c_lq, "c.lq", rv_codec_cl_lq, NULL, DECOMP(rv_op_lq))
-OP(c_sq, "c.sq", rv_codec_cs_sq, NULL, DECOMP(rv_op_sq))
-OP(c_lqsp, "c.lqsp", rv_codec_ci_lqsp, NULL, DECOMP(rv_op_lq))
-OP(c_sqsp, "c.sqsp", rv_codec_css_sqsp, NULL, DECOMP(rv_op_sq))
+OP(c_addi4spn, "c.addi4spn", rv_codec_ciw_4spn, NULL, DECOMP(op_addi))
+OP(c_fld, "c.fld", rv_codec_cl_ld, NULL, DECOMP(op_fld))
+OP(c_lw, "c.lw", rv_codec_cl_lw, NULL, DECOMP(op_lw))
+OP(c_flw, "c.flw", rv_codec_cl_lw, NULL, DECOMP(op_flw))
+OP(c_fsd, "c.fsd", rv_codec_cs_sd, NULL, DECOMP(op_fsd))
+OP(c_sw, "c.sw", rv_codec_cs_sw, NULL, DECOMP(op_sw))
+OP(c_fsw, "c.fsw", rv_codec_cs_sw, NULL, DECOMP(op_fsw))
+OP(c_addi, "c.addi", rv_codec_ci, NULL, DECOMP(op_addi))
+OP(c_jal, "c.jal", rv_codec_cj_jal, NULL, DECOMP(op_jal))
+OP(c_li, "c.li", rv_codec_ci_li, NULL, DECOMP(op_addi))
+OP(c_addi16sp, "c.addi16sp", rv_codec_ci_16sp, NULL, DECOMP(op_addi))
+OP(c_lui, "c.lui", rv_codec_ci_lui, NULL, DECOMP(op_lui))
+OP(c_srli, "c.srli", rv_codec_cb_sh6, NULL, DECOMP(op_srli))
+OP(c_srai, "c.srai", rv_codec_cb_sh6, NULL, DECOMP(op_srai))
+OP(c_andi, "c.andi", rv_codec_cb_imm, NULL, DECOMP(op_andi))
+OP(c_sub, "c.sub", rv_codec_cs, NULL, DECOMP(op_sub))
+OP(c_xor, "c.xor", rv_codec_cs, NULL, DECOMP(op_xor))
+OP(c_or, "c.or", rv_codec_cs, NULL, DECOMP(op_or))
+OP(c_and, "c.and", rv_codec_cs, NULL, DECOMP(op_and))
+OP(c_subw, "c.subw", rv_codec_cs, NULL, DECOMP(op_subw))
+OP(c_addw, "c.addw", rv_codec_cs, NULL, DECOMP(op_addw))
+OP(c_j, "c.j", rv_codec_cj, NULL, DECOMP(op_j))
+OP(c_beqz, "c.beqz", rv_codec_cb, NULL, DECOMP(op_beqz))
+OP(c_bnez, "c.bnez", rv_codec_cb, NULL, DECOMP(op_bnez))
+OP(c_slli, "c.slli", rv_codec_ci_sh6, NULL, DECOMP(op_slli))
+OP(c_fldsp, "c.fldsp", rv_codec_ci_ldsp, NULL, DECOMP(op_fld))
+OP(c_lwsp, "c.lwsp", rv_codec_ci_lwsp, NULL, DECOMP(op_lw))
+OP(c_flwsp, "c.flwsp", rv_codec_ci_lwsp, NULL, DECOMP(op_flw))
+OP(c_jr, "c.jr", rv_codec_cr_jr, NULL, DECOMP(op_jr))
+OP(c_mv, "c.mv", rv_codec_cr_mv, NULL, DECOMP(op_mv))
+OP(c_ebreak, "c.ebreak", rv_codec_ci_none, NULL, DECOMP(op_ebreak))
+OP(c_jalr, "c.jalr", rv_codec_cr_jalr, NULL, DECOMP(op_jalr))
+OP(c_add, "c.add", rv_codec_cr, NULL, DECOMP(op_add))
+OP(c_fsdsp, "c.fsdsp", rv_codec_css_sdsp, NULL, DECOMP(op_fsd))
+OP(c_swsp, "c.swsp", rv_codec_css_swsp, NULL, DECOMP(op_sw))
+OP(c_fswsp, "c.fswsp", rv_codec_css_swsp, NULL, DECOMP(op_fsw))
+OP(c_ld, "c.ld", rv_codec_cl_ld, NULL, DECOMP(op_ld))
+OP(c_sd, "c.sd", rv_codec_cs_sd, NULL, DECOMP(op_sd))
+OP(c_addiw, "c.addiw", rv_codec_ci, NULL, DECOMP(op_addiw))
+OP(c_ldsp, "c.ldsp", rv_codec_ci_ldsp, NULL, DECOMP(op_ld))
+OP(c_sdsp, "c.sdsp", rv_codec_css_sdsp, NULL, DECOMP(op_sd))
+OP(c_lq, "c.lq", rv_codec_cl_lq, NULL, DECOMP(op_lq))
+OP(c_sq, "c.sq", rv_codec_cs_sq, NULL, DECOMP(op_sq))
+OP(c_lqsp, "c.lqsp", rv_codec_ci_lqsp, NULL, DECOMP(op_lq))
+OP(c_sqsp, "c.sqsp", rv_codec_css_sqsp, NULL, DECOMP(op_sq))
OP(nop, "nop", rv_codec_illegal, rv_fmt_none)
OP(mv, "mv", rv_codec_illegal, rv_fmt_rd_rs1, rvcp_mv)
OP(not, "not", rv_codec_illegal, rv_fmt_rd_rs1)
@@ -904,8 +904,8 @@ OP(sspopchk, "sspopchk", rv_codec_r, rv_fmt_rs1)
OP(ssrdp, "ssrdp", rv_codec_r, rv_fmt_rd)
OP(ssamoswap_w, "ssamoswap.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
OP(ssamoswap_d, "ssamoswap.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
-OP(c_sspush, "c.sspush", rv_codec_cmop_ss, NULL, DECOMP(rv_op_sspush))
-OP(c_sspopchk, "c.sspopchk", rv_codec_cmop_ss, NULL, DECOMP(rv_op_sspopchk))
+OP(c_sspush, "c.sspush", rv_codec_cmop_ss, NULL, DECOMP(op_sspush))
+OP(c_sspopchk, "c.sspopchk", rv_codec_cmop_ss, NULL, DECOMP(op_sspopchk))
OP(cbo_inval, "cbo.inval", rv_codec_r, rv_fmt_rs1)
OP(cbo_clean, "cbo.clean", rv_codec_r, rv_fmt_rs1)
OP(cbo_flush, "cbo.flush", rv_codec_r, rv_fmt_rs1)
--
2.43.0
^ permalink raw reply related [flat|nested] 119+ messages in thread
* [PATCH 56/56] disas/riscv: Sort riscv-op.c.inc
2026-08-09 22:34 [RFC PATCH 00/56] disas/riscv: Reorganize the disassembler Richard Henderson
` (54 preceding siblings ...)
2026-08-09 22:35 ` [PATCH 55/56] disas/riscv: Split rvi_opcode_data Richard Henderson
@ 2026-08-09 22:35 ` Richard Henderson
2026-08-10 2:59 ` Philippe Mathieu-Daudé
2026-08-12 13:03 ` Alistair
55 siblings, 2 replies; 119+ messages in thread
From: Richard Henderson @ 2026-08-09 22:35 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-riscv
To date, opcodes had to be added to the end of the list,
resulting in quite the disorder. Sort via 'LANG=C sort'.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
disas/riscv-op.c.inc | 1704 +++++++++++++++++++++---------------------
1 file changed, 852 insertions(+), 852 deletions(-)
diff --git a/disas/riscv-op.c.inc b/disas/riscv-op.c.inc
index cc939f557f..1d334e4857 100644
--- a/disas/riscv-op.c.inc
+++ b/disas/riscv-op.c.inc
@@ -1,913 +1,913 @@
-OP(illegal, "illegal", rv_codec_none, rv_fmt_none)
-OP(lui, "lui", rv_codec_u, rv_fmt_rd_uimm)
-OP(auipc, "auipc", rv_codec_u, rv_fmt_rd_uoffset)
-OP(jal, "jal", rv_codec_uj, rv_fmt_rd_offset, rvcp_jal)
-OP(jalr, "jalr", rv_codec_i, rv_fmt_rd_rs1_offset, rvcp_jalr)
-OP(beq, "beq", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_beq)
-OP(bne, "bne", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_bne)
-OP(blt, "blt", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_blt)
-OP(bge, "bge", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_bge)
-OP(bltu, "bltu", rv_codec_sb, rv_fmt_rs1_rs2_offset)
-OP(bgeu, "bgeu", rv_codec_sb, rv_fmt_rs1_rs2_offset)
-OP(lb, "lb", rv_codec_i, rv_fmt_rd_offset_rs1)
-OP(lh, "lh", rv_codec_i, rv_fmt_rd_offset_rs1)
-OP(lw, "lw", rv_codec_i, rv_fmt_rd_offset_rs1)
-OP(lbu, "lbu", rv_codec_i, rv_fmt_rd_offset_rs1)
-OP(lhu, "lhu", rv_codec_i, rv_fmt_rd_offset_rs1)
-OP(sb, "sb", rv_codec_s, rv_fmt_rs2_offset_rs1)
-OP(sh, "sh", rv_codec_s, rv_fmt_rs2_offset_rs1)
-OP(sw, "sw", rv_codec_s, rv_fmt_rs2_offset_rs1)
-OP(addi, "addi", rv_codec_i, rv_fmt_rd_rs1_imm, rvcp_addi)
-OP(slti, "slti", rv_codec_i, rv_fmt_rd_rs1_imm)
-OP(sltiu, "sltiu", rv_codec_i, rv_fmt_rd_rs1_imm, rvcp_sltiu)
-OP(xori, "xori", rv_codec_i, rv_fmt_rd_rs1_imm, rvcp_xori)
-OP(ori, "ori", rv_codec_i, rv_fmt_rd_rs1_imm)
-OP(andi, "andi", rv_codec_i, rv_fmt_rd_rs1_imm)
-OP(slli, "slli", rv_codec_i_sh7, rv_fmt_rd_rs1_imm)
-OP(srli, "srli", rv_codec_i_sh7, rv_fmt_rd_rs1_imm)
-OP(srai, "srai", rv_codec_i_sh7, rv_fmt_rd_rs1_imm)
OP(add, "add", rv_codec_r, rv_fmt_rd_rs1_rs2)
-OP(sub, "sub", rv_codec_r, rv_fmt_rd_rs1_rs2, rvcp_sub)
-OP(sll, "sll", rv_codec_r, rv_fmt_rd_rs1_rs2)
-OP(slt, "slt", rv_codec_r, rv_fmt_rd_rs1_rs2, rvcp_slt)
-OP(sltu, "sltu", rv_codec_r, rv_fmt_rd_rs1_rs2, rvcp_sltu)
-OP(xor, "xor", rv_codec_r, rv_fmt_rd_rs1_rs2)
-OP(srl, "srl", rv_codec_r, rv_fmt_rd_rs1_rs2)
-OP(sra, "sra", rv_codec_r, rv_fmt_rd_rs1_rs2)
-OP(or, "or", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(add_uw, "add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(addd, "addd", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(addi, "addi", rv_codec_i, rv_fmt_rd_rs1_imm, rvcp_addi)
+OP(addid, "addid", rv_codec_i, rv_fmt_rd_rs1_imm)
+OP(addiw, "addiw", rv_codec_i, rv_fmt_rd_rs1_imm, rvcp_addiw)
+OP(addw, "addw", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(aes32dsi, "aes32dsi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs)
+OP(aes32dsmi, "aes32dsmi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs)
+OP(aes32esi, "aes32esi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs)
+OP(aes32esmi, "aes32esmi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs)
+OP(aes64ds, "aes64ds", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(aes64dsm, "aes64dsm", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(aes64es, "aes64es", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(aes64esm, "aes64esm", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(aes64im, "aes64im", rv_codec_r, rv_fmt_rd_rs1)
+OP(aes64ks1i, "aes64ks1i", rv_codec_k_rnum, rv_fmt_rd_rs1_rnum)
+OP(aes64ks2, "aes64ks2", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(amoadd_b, "amoadd.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
+OP(amoadd_d, "amoadd.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
+OP(amoadd_h, "amoadd.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
+OP(amoadd_q, "amoadd.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
+OP(amoadd_w, "amoadd.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
+OP(amoand_b, "amoand.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
+OP(amoand_d, "amoand.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
+OP(amoand_h, "amoand.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
+OP(amoand_q, "amoand.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
+OP(amoand_w, "amoand.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
+OP(amocas_b, "amocas.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
+OP(amocas_d, "amocas.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
+OP(amocas_h, "amocas.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
+OP(amocas_q, "amocas.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
+OP(amocas_w, "amocas.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
+OP(amomax_b, "amomax.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
+OP(amomax_d, "amomax.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
+OP(amomax_h, "amomax.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
+OP(amomax_q, "amomax.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
+OP(amomax_w, "amomax.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
+OP(amomaxu_b, "amomaxu.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
+OP(amomaxu_d, "amomaxu.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
+OP(amomaxu_h, "amomaxu.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
+OP(amomaxu_q, "amomaxu.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
+OP(amomaxu_w, "amomaxu.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
+OP(amomin_b, "amomin.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
+OP(amomin_d, "amomin.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
+OP(amomin_h, "amomin.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
+OP(amomin_q, "amomin.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
+OP(amomin_w, "amomin.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
+OP(amominu_b, "amominu.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
+OP(amominu_d, "amominu.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
+OP(amominu_h, "amominu.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
+OP(amominu_q, "amominu.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
+OP(amominu_w, "amominu.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
+OP(amoor_b, "amoor.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
+OP(amoor_d, "amoor.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
+OP(amoor_h, "amoor.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
+OP(amoor_q, "amoor.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
+OP(amoor_w, "amoor.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
+OP(amoswap_b, "amoswap.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
+OP(amoswap_d, "amoswap.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
+OP(amoswap_h, "amoswap.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
+OP(amoswap_q, "amoswap.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
+OP(amoswap_w, "amoswap.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
+OP(amoxor_b, "amoxor.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
+OP(amoxor_d, "amoxor.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
+OP(amoxor_h, "amoxor.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
+OP(amoxor_q, "amoxor.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
+OP(amoxor_w, "amoxor.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
OP(and, "and", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(andi, "andi", rv_codec_i, rv_fmt_rd_rs1_imm)
+OP(andn, "andn", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(auipc, "auipc", rv_codec_u, rv_fmt_rd_uoffset)
+OP(bclr, "bclr", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(bclri, "bclri", rv_codec_i_sh7, rv_fmt_rd_rs1_imm)
+OP(beq, "beq", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_beq)
+OP(beqz, "beqz", rv_codec_illegal, rv_fmt_rs1_offset)
+OP(bext, "bext", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(bexti, "bexti", rv_codec_i_sh7, rv_fmt_rd_rs1_imm)
+OP(bge, "bge", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_bge)
+OP(bgeu, "bgeu", rv_codec_sb, rv_fmt_rs1_rs2_offset)
+OP(bgez, "bgez", rv_codec_illegal, rv_fmt_rs1_offset)
+OP(bgtz, "bgtz", rv_codec_illegal, rv_fmt_rs2_offset)
+OP(binv, "binv", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(binvi, "binvi", rv_codec_i_sh7, rv_fmt_rd_rs1_imm)
+OP(blez, "blez", rv_codec_illegal, rv_fmt_rs2_offset)
+OP(blt, "blt", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_blt)
+OP(bltu, "bltu", rv_codec_sb, rv_fmt_rs1_rs2_offset)
+OP(bltz, "bltz", rv_codec_illegal, rv_fmt_rs1_offset)
+OP(bne, "bne", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_bne)
+OP(bnez, "bnez", rv_codec_illegal, rv_fmt_rs1_offset)
+OP(brev8, "brev8", rv_codec_r, rv_fmt_rd_rs1)
+OP(bset, "bset", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(bseti, "bseti", rv_codec_i_sh7, rv_fmt_rd_rs1_imm)
+OP(c_add, "c.add", rv_codec_cr, NULL, DECOMP(op_add))
+OP(c_addi, "c.addi", rv_codec_ci, NULL, DECOMP(op_addi))
+OP(c_addi16sp, "c.addi16sp", rv_codec_ci_16sp, NULL, DECOMP(op_addi))
+OP(c_addi4spn, "c.addi4spn", rv_codec_ciw_4spn, NULL, DECOMP(op_addi))
+OP(c_addiw, "c.addiw", rv_codec_ci, NULL, DECOMP(op_addiw))
+OP(c_addw, "c.addw", rv_codec_cs, NULL, DECOMP(op_addw))
+OP(c_and, "c.and", rv_codec_cs, NULL, DECOMP(op_and))
+OP(c_andi, "c.andi", rv_codec_cb_imm, NULL, DECOMP(op_andi))
+OP(c_beqz, "c.beqz", rv_codec_cb, NULL, DECOMP(op_beqz))
+OP(c_bnez, "c.bnez", rv_codec_cb, NULL, DECOMP(op_bnez))
+OP(c_ebreak, "c.ebreak", rv_codec_ci_none, NULL, DECOMP(op_ebreak))
+OP(c_fld, "c.fld", rv_codec_cl_ld, NULL, DECOMP(op_fld))
+OP(c_fldsp, "c.fldsp", rv_codec_ci_ldsp, NULL, DECOMP(op_fld))
+OP(c_flw, "c.flw", rv_codec_cl_lw, NULL, DECOMP(op_flw))
+OP(c_flwsp, "c.flwsp", rv_codec_ci_lwsp, NULL, DECOMP(op_flw))
+OP(c_fsd, "c.fsd", rv_codec_cs_sd, NULL, DECOMP(op_fsd))
+OP(c_fsdsp, "c.fsdsp", rv_codec_css_sdsp, NULL, DECOMP(op_fsd))
+OP(c_fsw, "c.fsw", rv_codec_cs_sw, NULL, DECOMP(op_fsw))
+OP(c_fswsp, "c.fswsp", rv_codec_css_swsp, NULL, DECOMP(op_fsw))
+OP(c_j, "c.j", rv_codec_cj, NULL, DECOMP(op_j))
+OP(c_jal, "c.jal", rv_codec_cj_jal, NULL, DECOMP(op_jal))
+OP(c_jalr, "c.jalr", rv_codec_cr_jalr, NULL, DECOMP(op_jalr))
+OP(c_jr, "c.jr", rv_codec_cr_jr, NULL, DECOMP(op_jr))
+OP(c_lbu, "c.lbu", rv_codec_zcb_lb, rv_fmt_rs1_rs2_zce_ldst)
+OP(c_ld, "c.ld", rv_codec_cl_ld, NULL, DECOMP(op_ld))
+OP(c_ldsp, "c.ldsp", rv_codec_ci_ldsp, NULL, DECOMP(op_ld))
+OP(c_lh, "c.lh", rv_codec_zcb_lh, rv_fmt_rs1_rs2_zce_ldst)
+OP(c_lhu, "c.lhu", rv_codec_zcb_lh, rv_fmt_rs1_rs2_zce_ldst)
+OP(c_li, "c.li", rv_codec_ci_li, NULL, DECOMP(op_addi))
+OP(c_lq, "c.lq", rv_codec_cl_lq, NULL, DECOMP(op_lq))
+OP(c_lqsp, "c.lqsp", rv_codec_ci_lqsp, NULL, DECOMP(op_lq))
+OP(c_lui, "c.lui", rv_codec_ci_lui, NULL, DECOMP(op_lui))
+OP(c_lw, "c.lw", rv_codec_cl_lw, NULL, DECOMP(op_lw))
+OP(c_lwsp, "c.lwsp", rv_codec_ci_lwsp, NULL, DECOMP(op_lw))
+OP(c_mop, "c.mop", rv_codec_cmop, rv_fmt_cmop)
+OP(c_mul, "c.mul", rv_codec_zcb_mul, rv_fmt_rd_rs2)
+OP(c_mv, "c.mv", rv_codec_cr_mv, NULL, DECOMP(op_mv))
+OP(c_not, "c.not", rv_codec_zcb_ext, rv_fmt_rd)
+OP(c_or, "c.or", rv_codec_cs, NULL, DECOMP(op_or))
+OP(c_sb, "c.sb", rv_codec_zcb_lb, rv_fmt_rs1_rs2_zce_ldst)
+OP(c_sd, "c.sd", rv_codec_cs_sd, NULL, DECOMP(op_sd))
+OP(c_sdsp, "c.sdsp", rv_codec_css_sdsp, NULL, DECOMP(op_sd))
+OP(c_sext_b, "c.sext.b", rv_codec_zcb_ext, rv_fmt_rd)
+OP(c_sext_h, "c.sext.h", rv_codec_zcb_ext, rv_fmt_rd)
+OP(c_sh, "c.sh", rv_codec_zcb_lh, rv_fmt_rs1_rs2_zce_ldst)
+OP(c_slli, "c.slli", rv_codec_ci_sh6, NULL, DECOMP(op_slli))
+OP(c_sq, "c.sq", rv_codec_cs_sq, NULL, DECOMP(op_sq))
+OP(c_sqsp, "c.sqsp", rv_codec_css_sqsp, NULL, DECOMP(op_sq))
+OP(c_srai, "c.srai", rv_codec_cb_sh6, NULL, DECOMP(op_srai))
+OP(c_srli, "c.srli", rv_codec_cb_sh6, NULL, DECOMP(op_srli))
+OP(c_sspopchk, "c.sspopchk", rv_codec_cmop_ss, NULL, DECOMP(op_sspopchk))
+OP(c_sspush, "c.sspush", rv_codec_cmop_ss, NULL, DECOMP(op_sspush))
+OP(c_sub, "c.sub", rv_codec_cs, NULL, DECOMP(op_sub))
+OP(c_subw, "c.subw", rv_codec_cs, NULL, DECOMP(op_subw))
+OP(c_sw, "c.sw", rv_codec_cs_sw, NULL, DECOMP(op_sw))
+OP(c_swsp, "c.swsp", rv_codec_css_swsp, NULL, DECOMP(op_sw))
+OP(c_xor, "c.xor", rv_codec_cs, NULL, DECOMP(op_xor))
+OP(c_zext_b, "c.zext.b", rv_codec_zcb_ext, rv_fmt_rd)
+OP(c_zext_h, "c.zext.h", rv_codec_zcb_ext, rv_fmt_rd)
+OP(c_zext_w, "c.zext.w", rv_codec_zcb_ext, rv_fmt_rd)
+OP(cbo_clean, "cbo.clean", rv_codec_r, rv_fmt_rs1)
+OP(cbo_flush, "cbo.flush", rv_codec_r, rv_fmt_rs1)
+OP(cbo_inval, "cbo.inval", rv_codec_r, rv_fmt_rs1)
+OP(cbo_zero, "cbo.zero", rv_codec_r, rv_fmt_rs1)
+OP(clmul, "clmul", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(clmulh, "clmulh", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(clmulr, "clmulr", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(clz, "clz", rv_codec_r, rv_fmt_rd_rs1)
+OP(clzw, "clzw", rv_codec_r, rv_fmt_rd_rs1)
+OP(cm_jalt, "cm.jalt", rv_codec_zcmt_jt, rv_fmt_zcmt_index)
+OP(cm_jt, "cm.jt", rv_codec_zcmt_jt, rv_fmt_zcmt_index)
+OP(cm_mva01s, "cm.mva01s", rv_codec_zcmp_cm_mv, rv_fmt_rd_rs2)
+OP(cm_mvsa01, "cm.mvsa01", rv_codec_zcmp_cm_mv, rv_fmt_rd_rs2)
+OP(cm_pop, "cm.pop", rv_codec_zcmp_cm_pushpop, rv_fmt_pop_rlist)
+OP(cm_popret, "cm.popret", rv_codec_zcmp_cm_pushpop, rv_fmt_pop_rlist)
+OP(cm_popretz, "cm.popretz", rv_codec_zcmp_cm_pushpop, rv_fmt_pop_rlist)
+OP(cm_push, "cm.push", rv_codec_zcmp_cm_pushpop, rv_fmt_push_rlist)
+OP(cpop, "cpop", rv_codec_r, rv_fmt_rd_rs1)
+OP(cpopw, "cpopw", rv_codec_r, rv_fmt_rd_rs1)
+OP(csrrc, "csrrc", rv_codec_i_csr, rv_fmt_rd_csr_rs1)
+OP(csrrci, "csrrci", rv_codec_i_csr, rv_fmt_rd_csr_zimm)
+OP(csrrs, "csrrs", rv_codec_i_csr, rv_fmt_rd_csr_rs1)
+OP(csrrsi, "csrrsi", rv_codec_i_csr, rv_fmt_rd_csr_zimm)
+OP(csrrw, "csrrw", rv_codec_i_csr, rv_fmt_rd_csr_rs1)
+OP(csrrwi, "csrrwi", rv_codec_i_csr, rv_fmt_rd_csr_zimm)
+OP(ctz, "ctz", rv_codec_r, rv_fmt_rd_rs1)
+OP(ctzw, "ctzw", rv_codec_r, rv_fmt_rd_rs1)
+OP(czero_eqz, "czero.eqz", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(czero_nez, "czero.nez", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(div, "div", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(divd, "divd", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(divu, "divu", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(divud, "divud", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(divuw, "divuw", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(divw, "divw", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(dret, "dret", rv_codec_none, rv_fmt_none)
+OP(ebreak, "ebreak", rv_codec_none, rv_fmt_none)
+OP(ecall, "ecall", rv_codec_none, rv_fmt_none)
+OP(fabs_d, "fabs.d", rv_codec_illegal, rv_fmt_frd_frs1)
+OP(fabs_q, "fabs.q", rv_codec_illegal, rv_fmt_frd_frs1)
+OP(fabs_s, "fabs.s", rv_codec_illegal, rv_fmt_frd_frs1)
+OP(fadd_d, "fadd.d", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2)
+OP(fadd_q, "fadd.q", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2)
+OP(fadd_s, "fadd.s", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2)
+OP(fclass_d, "fclass.d", rv_codec_r, rv_fmt_rd_frs1)
+OP(fclass_q, "fclass.q", rv_codec_r, rv_fmt_rd_frs1)
+OP(fclass_s, "fclass.s", rv_codec_r, rv_fmt_rd_frs1)
+OP(fcvt_bf16_s, "fcvt.bf16.s", rv_codec_r_m, rv_fmt_rm_frd_frs1)
+OP(fcvt_d_l, "fcvt.d.l", rv_codec_r_m, rv_fmt_rm_frd_rs1)
+OP(fcvt_d_lu, "fcvt.d.lu", rv_codec_r_m, rv_fmt_rm_frd_rs1)
+OP(fcvt_d_q, "fcvt.d.q", rv_codec_r_m, rv_fmt_rm_frd_frs1)
+OP(fcvt_d_s, "fcvt.d.s", rv_codec_r_m, rv_fmt_rm_frd_frs1)
+OP(fcvt_d_w, "fcvt.d.w", rv_codec_r_m, rv_fmt_rm_frd_rs1)
+OP(fcvt_d_wu, "fcvt.d.wu", rv_codec_r_m, rv_fmt_rm_frd_rs1)
+OP(fcvt_l_d, "fcvt.l.d", rv_codec_r_m, rv_fmt_rm_rd_frs1)
+OP(fcvt_l_q, "fcvt.l.q", rv_codec_r_m, rv_fmt_rm_rd_frs1)
+OP(fcvt_l_s, "fcvt.l.s", rv_codec_r_m, rv_fmt_rm_rd_frs1)
+OP(fcvt_lu_d, "fcvt.lu.d", rv_codec_r_m, rv_fmt_rm_rd_frs1)
+OP(fcvt_lu_q, "fcvt.lu.q", rv_codec_r_m, rv_fmt_rm_rd_frs1)
+OP(fcvt_lu_s, "fcvt.lu.s", rv_codec_r_m, rv_fmt_rm_rd_frs1)
+OP(fcvt_q_d, "fcvt.q.d", rv_codec_r_m, rv_fmt_rm_frd_frs1)
+OP(fcvt_q_l, "fcvt.q.l", rv_codec_r_m, rv_fmt_rm_frd_rs1)
+OP(fcvt_q_lu, "fcvt.q.lu", rv_codec_r_m, rv_fmt_rm_frd_rs1)
+OP(fcvt_q_s, "fcvt.q.s", rv_codec_r_m, rv_fmt_rm_frd_frs1)
+OP(fcvt_q_w, "fcvt.q.w", rv_codec_r_m, rv_fmt_rm_frd_rs1)
+OP(fcvt_q_wu, "fcvt.q.wu", rv_codec_r_m, rv_fmt_rm_frd_rs1)
+OP(fcvt_s_bf16, "fcvt.s.bf16", rv_codec_r_m, rv_fmt_rm_frd_frs1)
+OP(fcvt_s_d, "fcvt.s.d", rv_codec_r_m, rv_fmt_rm_frd_frs1)
+OP(fcvt_s_l, "fcvt.s.l", rv_codec_r_m, rv_fmt_rm_frd_rs1)
+OP(fcvt_s_lu, "fcvt.s.lu", rv_codec_r_m, rv_fmt_rm_frd_rs1)
+OP(fcvt_s_q, "fcvt.s.q", rv_codec_r_m, rv_fmt_rm_frd_frs1)
+OP(fcvt_s_w, "fcvt.s.w", rv_codec_r_m, rv_fmt_rm_frd_rs1)
+OP(fcvt_s_wu, "fcvt.s.wu", rv_codec_r_m, rv_fmt_rm_frd_rs1)
+OP(fcvt_w_d, "fcvt.w.d", rv_codec_r_m, rv_fmt_rm_rd_frs1)
+OP(fcvt_w_q, "fcvt.w.q", rv_codec_r_m, rv_fmt_rm_rd_frs1)
+OP(fcvt_w_s, "fcvt.w.s", rv_codec_r_m, rv_fmt_rm_rd_frs1)
+OP(fcvt_wu_d, "fcvt.wu.d", rv_codec_r_m, rv_fmt_rm_rd_frs1)
+OP(fcvt_wu_q, "fcvt.wu.q", rv_codec_r_m, rv_fmt_rm_rd_frs1)
+OP(fcvt_wu_s, "fcvt.wu.s", rv_codec_r_m, rv_fmt_rm_rd_frs1)
+OP(fcvtmod_w_d, "fcvtmod.w.d", rv_codec_r_m, rv_fmt_rm_rd_frs1)
+OP(fdiv_d, "fdiv.d", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2)
+OP(fdiv_q, "fdiv.q", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2)
+OP(fdiv_s, "fdiv.s", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2)
OP(fence, "fence", rv_codec_r_f, rv_fmt_pred_succ)
OP(fence_i, "fence.i", rv_codec_none, rv_fmt_none)
-OP(lwu, "lwu", rv_codec_i, rv_fmt_rd_offset_rs1)
+OP(feq_d, "feq.d", rv_codec_r, rv_fmt_rd_frs1_frs2)
+OP(feq_q, "feq.q", rv_codec_r, rv_fmt_rd_frs1_frs2)
+OP(feq_s, "feq.s", rv_codec_r, rv_fmt_rd_frs1_frs2)
+OP(fld, "fld", rv_codec_i, rv_fmt_frd_offset_rs1)
+OP(fle_d, "fle.d", rv_codec_r, rv_fmt_rd_frs1_frs2)
+OP(fle_q, "fle.q", rv_codec_r, rv_fmt_rd_frs1_frs2)
+OP(fle_s, "fle.s", rv_codec_r, rv_fmt_rd_frs1_frs2)
+OP(fleq_d, "fleq.d", rv_codec_r, rv_fmt_rd_frs1_frs2)
+OP(fleq_h, "fleq.h", rv_codec_r, rv_fmt_rd_frs1_frs2)
+OP(fleq_q, "fleq.q", rv_codec_r, rv_fmt_rd_frs1_frs2)
+OP(fleq_s, "fleq.s", rv_codec_r, rv_fmt_rd_frs1_frs2)
+OP(flh, "flh", rv_codec_i, rv_fmt_frd_offset_rs1)
+OP(fli_d, "fli.d", rv_codec_fli, rv_fmt_fli)
+OP(fli_h, "fli.h", rv_codec_fli, rv_fmt_fli)
+OP(fli_q, "fli.q", rv_codec_fli, rv_fmt_fli)
+OP(fli_s, "fli.s", rv_codec_fli, rv_fmt_fli)
+OP(flq, "flq", rv_codec_i, rv_fmt_frd_offset_rs1)
+OP(flt_d, "flt.d", rv_codec_r, rv_fmt_rd_frs1_frs2)
+OP(flt_q, "flt.q", rv_codec_r, rv_fmt_rd_frs1_frs2)
+OP(flt_s, "flt.s", rv_codec_r, rv_fmt_rd_frs1_frs2)
+OP(fltq_d, "fltq.d", rv_codec_r, rv_fmt_rd_frs1_frs2)
+OP(fltq_h, "fltq.h", rv_codec_r, rv_fmt_rd_frs1_frs2)
+OP(fltq_q, "fltq.q", rv_codec_r, rv_fmt_rd_frs1_frs2)
+OP(fltq_s, "fltq.s", rv_codec_r, rv_fmt_rd_frs1_frs2)
+OP(flw, "flw", rv_codec_i, rv_fmt_frd_offset_rs1)
+OP(fmadd_d, "fmadd.d", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3)
+OP(fmadd_q, "fmadd.q", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3)
+OP(fmadd_s, "fmadd.s", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3)
+OP(fmax_d, "fmax.d", rv_codec_r, rv_fmt_frd_frs1_frs2)
+OP(fmax_q, "fmax.q", rv_codec_r, rv_fmt_frd_frs1_frs2)
+OP(fmax_s, "fmax.s", rv_codec_r, rv_fmt_frd_frs1_frs2)
+OP(fmaxm_d, "fmaxm.d", rv_codec_r, rv_fmt_frd_frs1_frs2)
+OP(fmaxm_h, "fmaxm.h", rv_codec_r, rv_fmt_frd_frs1_frs2)
+OP(fmaxm_q, "fmaxm.q", rv_codec_r, rv_fmt_frd_frs1_frs2)
+OP(fmaxm_s, "fmaxm.s", rv_codec_r, rv_fmt_frd_frs1_frs2)
+OP(fmin_d, "fmin.d", rv_codec_r, rv_fmt_frd_frs1_frs2)
+OP(fmin_q, "fmin.q", rv_codec_r, rv_fmt_frd_frs1_frs2)
+OP(fmin_s, "fmin.s", rv_codec_r, rv_fmt_frd_frs1_frs2)
+OP(fminm_d, "fminm.d", rv_codec_r, rv_fmt_frd_frs1_frs2)
+OP(fminm_h, "fminm.h", rv_codec_r, rv_fmt_frd_frs1_frs2)
+OP(fminm_q, "fminm.q", rv_codec_r, rv_fmt_frd_frs1_frs2)
+OP(fminm_s, "fminm.s", rv_codec_r, rv_fmt_frd_frs1_frs2)
+OP(fmsub_d, "fmsub.d", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3)
+OP(fmsub_q, "fmsub.q", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3)
+OP(fmsub_s, "fmsub.s", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3)
+OP(fmul_d, "fmul.d", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2)
+OP(fmul_q, "fmul.q", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2)
+OP(fmul_s, "fmul.s", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2)
+OP(fmv_d, "fmv.d", rv_codec_illegal, rv_fmt_frd_frs1)
+OP(fmv_d_x, "fmv.d.x", rv_codec_r, rv_fmt_frd_rs1)
+OP(fmv_h_x, "fmv.h.x", rv_codec_r, rv_fmt_frd_rs1)
+OP(fmv_q, "fmv.q", rv_codec_illegal, rv_fmt_frd_frs1)
+OP(fmv_q_x, "fmv.q.x", rv_codec_r, rv_fmt_frd_rs1)
+OP(fmv_s, "fmv.s", rv_codec_illegal, rv_fmt_frd_frs1)
+OP(fmv_s_x, "fmv.s.x", rv_codec_r, rv_fmt_frd_rs1)
+OP(fmv_x_d, "fmv.x.d", rv_codec_r, rv_fmt_rd_frs1)
+OP(fmv_x_h, "fmv.x.h", rv_codec_r, rv_fmt_rd_frs1)
+OP(fmv_x_q, "fmv.x.q", rv_codec_r, rv_fmt_rd_frs1)
+OP(fmv_x_s, "fmv.x.s", rv_codec_r, rv_fmt_rd_frs1)
+OP(fmvh_x_d, "fmvh.x.d", rv_codec_r, rv_fmt_rd_frs1)
+OP(fmvh_x_q, "fmvh.x.q", rv_codec_r, rv_fmt_rd_frs1)
+OP(fmvp_d_x, "fmvp.d.x", rv_codec_r, rv_fmt_frd_rs1_rs2)
+OP(fmvp_q_x, "fmvp.q.x", rv_codec_r, rv_fmt_frd_rs1_rs2)
+OP(fneg_d, "fneg.d", rv_codec_illegal, rv_fmt_frd_frs1)
+OP(fneg_q, "fneg.q", rv_codec_illegal, rv_fmt_frd_frs1)
+OP(fneg_s, "fneg.s", rv_codec_illegal, rv_fmt_frd_frs1)
+OP(fnmadd_d, "fnmadd.d", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3)
+OP(fnmadd_q, "fnmadd.q", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3)
+OP(fnmadd_s, "fnmadd.s", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3)
+OP(fnmsub_d, "fnmsub.d", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3)
+OP(fnmsub_q, "fnmsub.q", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3)
+OP(fnmsub_s, "fnmsub.s", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3)
+OP(frcsr, "frcsr", rv_codec_i_csr, rv_fmt_rd)
+OP(frflags, "frflags", rv_codec_i_csr, rv_fmt_rd)
+OP(fround_d, "fround.d", rv_codec_r_m, rv_fmt_rm_frd_frs1)
+OP(fround_h, "fround.h", rv_codec_r_m, rv_fmt_rm_frd_frs1)
+OP(fround_q, "fround.q", rv_codec_r_m, rv_fmt_rm_frd_frs1)
+OP(fround_s, "fround.s", rv_codec_r_m, rv_fmt_rm_frd_frs1)
+OP(froundnx_d, "froundnx.d", rv_codec_r_m, rv_fmt_rm_frd_frs1)
+OP(froundnx_h, "froundnx.h", rv_codec_r_m, rv_fmt_rm_frd_frs1)
+OP(froundnx_q, "froundnx.q", rv_codec_r_m, rv_fmt_rm_frd_frs1)
+OP(froundnx_s, "froundnx.s", rv_codec_r_m, rv_fmt_rm_frd_frs1)
+OP(frrm, "frrm", rv_codec_i_csr, rv_fmt_rd)
+OP(fscsr, "fscsr", rv_codec_i_csr, rv_fmt_rd_rs1)
+OP(fsd, "fsd", rv_codec_s, rv_fmt_frs2_offset_rs1)
+OP(fsflags, "fsflags", rv_codec_i_csr, rv_fmt_rd_rs1)
+OP(fsflagsi, "fsflagsi", rv_codec_i_csr, rv_fmt_rd_zimm)
+OP(fsgnj_d, "fsgnj.d", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnj_d)
+OP(fsgnj_q, "fsgnj.q", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnj_q)
+OP(fsgnj_s, "fsgnj.s", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnj_s)
+OP(fsgnjn_d, "fsgnjn.d", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjn_d)
+OP(fsgnjn_q, "fsgnjn.q", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjn_q)
+OP(fsgnjn_s, "fsgnjn.s", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjn_s)
+OP(fsgnjx_d, "fsgnjx.d", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjx_d)
+OP(fsgnjx_q, "fsgnjx.q", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjx_q)
+OP(fsgnjx_s, "fsgnjx.s", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjx_s)
+OP(fsh, "fsh", rv_codec_s, rv_fmt_frs2_offset_rs1)
+OP(fsq, "fsq", rv_codec_s, rv_fmt_frs2_offset_rs1)
+OP(fsqrt_d, "fsqrt.d", rv_codec_r_m, rv_fmt_rm_frd_frs1)
+OP(fsqrt_q, "fsqrt.q", rv_codec_r_m, rv_fmt_rm_frd_frs1)
+OP(fsqrt_s, "fsqrt.s", rv_codec_r_m, rv_fmt_rm_frd_frs1)
+OP(fsrm, "fsrm", rv_codec_i_csr, rv_fmt_rd_rs1)
+OP(fsrmi, "fsrmi", rv_codec_i_csr, rv_fmt_rd_zimm)
+OP(fsub_d, "fsub.d", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2)
+OP(fsub_q, "fsub.q", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2)
+OP(fsub_s, "fsub.s", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2)
+OP(fsw, "fsw", rv_codec_s, rv_fmt_frs2_offset_rs1)
+OP(hret, "hret", rv_codec_none, rv_fmt_none)
+OP(illegal, "illegal", rv_codec_none, rv_fmt_none)
+OP(j, "j", rv_codec_illegal, rv_fmt_offset)
+OP(jal, "jal", rv_codec_uj, rv_fmt_rd_offset, rvcp_jal)
+OP(jal_ra, "jal", rv_codec_illegal, rv_fmt_offset)
+OP(jalr, "jalr", rv_codec_i, rv_fmt_rd_rs1_offset, rvcp_jalr)
+OP(jalr_ra, "jalr", rv_codec_illegal, rv_fmt_rs1)
+OP(jr, "jr", rv_codec_illegal, rv_fmt_rs1, rvcp_jr)
+OP(lb, "lb", rv_codec_i, rv_fmt_rd_offset_rs1)
+OP(lbu, "lbu", rv_codec_i, rv_fmt_rd_offset_rs1)
OP(ld, "ld", rv_codec_i, rv_fmt_rd_offset_rs1)
-OP(sd, "sd", rv_codec_s, rv_fmt_rs2_offset_rs1)
-OP(addiw, "addiw", rv_codec_i, rv_fmt_rd_rs1_imm, rvcp_addiw)
-OP(slliw, "slliw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm)
-OP(srliw, "srliw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm)
-OP(sraiw, "sraiw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm)
-OP(addw, "addw", rv_codec_r, rv_fmt_rd_rs1_rs2)
-OP(subw, "subw", rv_codec_r, rv_fmt_rd_rs1_rs2, rvcp_subw)
-OP(sllw, "sllw", rv_codec_r, rv_fmt_rd_rs1_rs2)
-OP(srlw, "srlw", rv_codec_r, rv_fmt_rd_rs1_rs2)
-OP(sraw, "sraw", rv_codec_r, rv_fmt_rd_rs1_rs2)
OP(ldu, "ldu", rv_codec_i, rv_fmt_rd_offset_rs1)
+OP(lh, "lh", rv_codec_i, rv_fmt_rd_offset_rs1)
+OP(lhu, "lhu", rv_codec_i, rv_fmt_rd_offset_rs1)
+OP(lpad, "lpad", rv_codec_lp, rv_fmt_imm)
OP(lq, "lq", rv_codec_i, rv_fmt_rd_offset_rs1)
-OP(sq, "sq", rv_codec_s, rv_fmt_rs2_offset_rs1)
-OP(addid, "addid", rv_codec_i, rv_fmt_rd_rs1_imm)
-OP(sllid, "sllid", rv_codec_i_sh6, rv_fmt_rd_rs1_imm)
-OP(srlid, "srlid", rv_codec_i_sh6, rv_fmt_rd_rs1_imm)
-OP(sraid, "sraid", rv_codec_i_sh6, rv_fmt_rd_rs1_imm)
-OP(addd, "addd", rv_codec_r, rv_fmt_rd_rs1_rs2)
-OP(subd, "subd", rv_codec_r, rv_fmt_rd_rs1_rs2)
-OP(slld, "slld", rv_codec_r, rv_fmt_rd_rs1_rs2)
-OP(srld, "srld", rv_codec_r, rv_fmt_rd_rs1_rs2)
-OP(srad, "srad", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(lr_d, "lr.d", rv_codec_r_l, rv_fmt_aqrl_rd_rs1)
+OP(lr_q, "lr.q", rv_codec_r_l, rv_fmt_aqrl_rd_rs1)
+OP(lr_w, "lr.w", rv_codec_r_l, rv_fmt_aqrl_rd_rs1)
+OP(lui, "lui", rv_codec_u, rv_fmt_rd_uimm)
+OP(lw, "lw", rv_codec_i, rv_fmt_rd_offset_rs1)
+OP(lwu, "lwu", rv_codec_i, rv_fmt_rd_offset_rs1)
+OP(max, "max", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(maxu, "maxu", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(min, "min", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(minu, "minu", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(mnret, "mnret", rv_codec_none, rv_fmt_none)
+OP(mop_r, "mop.r", rv_codec_mop_r, rv_fmt_mop_r)
+OP(mop_rr, "mop.rr", rv_codec_mop_rr, rv_fmt_mop_rr)
+OP(mret, "mret", rv_codec_none, rv_fmt_none)
OP(mul, "mul", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(muld, "muld", rv_codec_r, rv_fmt_rd_rs1_rs2)
OP(mulh, "mulh", rv_codec_r, rv_fmt_rd_rs1_rs2)
OP(mulhsu, "mulhsu", rv_codec_r, rv_fmt_rd_rs1_rs2)
OP(mulhu, "mulhu", rv_codec_r, rv_fmt_rd_rs1_rs2)
-OP(div, "div", rv_codec_r, rv_fmt_rd_rs1_rs2)
-OP(divu, "divu", rv_codec_r, rv_fmt_rd_rs1_rs2)
-OP(rem, "rem", rv_codec_r, rv_fmt_rd_rs1_rs2)
-OP(remu, "remu", rv_codec_r, rv_fmt_rd_rs1_rs2)
OP(mulw, "mulw", rv_codec_r, rv_fmt_rd_rs1_rs2)
-OP(divw, "divw", rv_codec_r, rv_fmt_rd_rs1_rs2)
-OP(divuw, "divuw", rv_codec_r, rv_fmt_rd_rs1_rs2)
-OP(remw, "remw", rv_codec_r, rv_fmt_rd_rs1_rs2)
-OP(remuw, "remuw", rv_codec_r, rv_fmt_rd_rs1_rs2)
-OP(muld, "muld", rv_codec_r, rv_fmt_rd_rs1_rs2)
-OP(divd, "divd", rv_codec_r, rv_fmt_rd_rs1_rs2)
-OP(divud, "divud", rv_codec_r, rv_fmt_rd_rs1_rs2)
-OP(remd, "remd", rv_codec_r, rv_fmt_rd_rs1_rs2)
-OP(remud, "remud", rv_codec_r, rv_fmt_rd_rs1_rs2)
-OP(lr_w, "lr.w", rv_codec_r_l, rv_fmt_aqrl_rd_rs1)
-OP(sc_w, "sc.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
-OP(amoswap_w, "amoswap.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
-OP(amoadd_w, "amoadd.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
-OP(amoxor_w, "amoxor.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
-OP(amoor_w, "amoor.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
-OP(amoand_w, "amoand.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
-OP(amomin_w, "amomin.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
-OP(amomax_w, "amomax.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
-OP(amominu_w, "amominu.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
-OP(amomaxu_w, "amomaxu.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
-OP(lr_d, "lr.d", rv_codec_r_l, rv_fmt_aqrl_rd_rs1)
-OP(sc_d, "sc.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
-OP(amoswap_d, "amoswap.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
-OP(amoadd_d, "amoadd.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
-OP(amoxor_d, "amoxor.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
-OP(amoor_d, "amoor.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
-OP(amoand_d, "amoand.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
-OP(amomin_d, "amomin.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
-OP(amomax_d, "amomax.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
-OP(amominu_d, "amominu.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
-OP(amomaxu_d, "amomaxu.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
-OP(lr_q, "lr.q", rv_codec_r_l, rv_fmt_aqrl_rd_rs1)
-OP(sc_q, "sc.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
-OP(amoswap_q, "amoswap.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
-OP(amoadd_q, "amoadd.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
-OP(amoxor_q, "amoxor.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
-OP(amoor_q, "amoor.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
-OP(amoand_q, "amoand.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
-OP(amomin_q, "amomin.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
-OP(amomax_q, "amomax.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
-OP(amominu_q, "amominu.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
-OP(amomaxu_q, "amomaxu.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
-OP(ecall, "ecall", rv_codec_none, rv_fmt_none)
-OP(ebreak, "ebreak", rv_codec_none, rv_fmt_none)
-OP(uret, "uret", rv_codec_none, rv_fmt_none)
-OP(sret, "sret", rv_codec_none, rv_fmt_none)
-OP(hret, "hret", rv_codec_none, rv_fmt_none)
-OP(mret, "mret", rv_codec_none, rv_fmt_none)
-OP(dret, "dret", rv_codec_none, rv_fmt_none)
-OP(sfence_vm, "sfence.vm", rv_codec_r, rv_fmt_rs1)
-OP(sfence_vma, "sfence.vma", rv_codec_r, rv_fmt_rs1_rs2)
-OP(wfi, "wfi", rv_codec_none, rv_fmt_none)
-OP(csrrw, "csrrw", rv_codec_i_csr, rv_fmt_rd_csr_rs1)
-OP(csrrs, "csrrs", rv_codec_i_csr, rv_fmt_rd_csr_rs1)
-OP(csrrc, "csrrc", rv_codec_i_csr, rv_fmt_rd_csr_rs1)
-OP(csrrwi, "csrrwi", rv_codec_i_csr, rv_fmt_rd_csr_zimm)
-OP(csrrsi, "csrrsi", rv_codec_i_csr, rv_fmt_rd_csr_zimm)
-OP(csrrci, "csrrci", rv_codec_i_csr, rv_fmt_rd_csr_zimm)
-OP(flw, "flw", rv_codec_i, rv_fmt_frd_offset_rs1)
-OP(fsw, "fsw", rv_codec_s, rv_fmt_frs2_offset_rs1)
-OP(fmadd_s, "fmadd.s", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3)
-OP(fmsub_s, "fmsub.s", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3)
-OP(fnmsub_s, "fnmsub.s", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3)
-OP(fnmadd_s, "fnmadd.s", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3)
-OP(fadd_s, "fadd.s", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2)
-OP(fsub_s, "fsub.s", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2)
-OP(fmul_s, "fmul.s", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2)
-OP(fdiv_s, "fdiv.s", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2)
-OP(fsgnj_s, "fsgnj.s", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnj_s)
-OP(fsgnjn_s, "fsgnjn.s", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjn_s)
-OP(fsgnjx_s, "fsgnjx.s", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjx_s)
-OP(fmin_s, "fmin.s", rv_codec_r, rv_fmt_frd_frs1_frs2)
-OP(fmax_s, "fmax.s", rv_codec_r, rv_fmt_frd_frs1_frs2)
-OP(fsqrt_s, "fsqrt.s", rv_codec_r_m, rv_fmt_rm_frd_frs1)
-OP(fle_s, "fle.s", rv_codec_r, rv_fmt_rd_frs1_frs2)
-OP(flt_s, "flt.s", rv_codec_r, rv_fmt_rd_frs1_frs2)
-OP(feq_s, "feq.s", rv_codec_r, rv_fmt_rd_frs1_frs2)
-OP(fcvt_w_s, "fcvt.w.s", rv_codec_r_m, rv_fmt_rm_rd_frs1)
-OP(fcvt_wu_s, "fcvt.wu.s", rv_codec_r_m, rv_fmt_rm_rd_frs1)
-OP(fcvt_s_w, "fcvt.s.w", rv_codec_r_m, rv_fmt_rm_frd_rs1)
-OP(fcvt_s_wu, "fcvt.s.wu", rv_codec_r_m, rv_fmt_rm_frd_rs1)
-OP(fmv_x_s, "fmv.x.s", rv_codec_r, rv_fmt_rd_frs1)
-OP(fclass_s, "fclass.s", rv_codec_r, rv_fmt_rd_frs1)
-OP(fmv_s_x, "fmv.s.x", rv_codec_r, rv_fmt_frd_rs1)
-OP(fcvt_l_s, "fcvt.l.s", rv_codec_r_m, rv_fmt_rm_rd_frs1)
-OP(fcvt_lu_s, "fcvt.lu.s", rv_codec_r_m, rv_fmt_rm_rd_frs1)
-OP(fcvt_s_l, "fcvt.s.l", rv_codec_r_m, rv_fmt_rm_frd_rs1)
-OP(fcvt_s_lu, "fcvt.s.lu", rv_codec_r_m, rv_fmt_rm_frd_rs1)
-OP(fld, "fld", rv_codec_i, rv_fmt_frd_offset_rs1)
-OP(fsd, "fsd", rv_codec_s, rv_fmt_frs2_offset_rs1)
-OP(fmadd_d, "fmadd.d", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3)
-OP(fmsub_d, "fmsub.d", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3)
-OP(fnmsub_d, "fnmsub.d", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3)
-OP(fnmadd_d, "fnmadd.d", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3)
-OP(fadd_d, "fadd.d", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2)
-OP(fsub_d, "fsub.d", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2)
-OP(fmul_d, "fmul.d", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2)
-OP(fdiv_d, "fdiv.d", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2)
-OP(fsgnj_d, "fsgnj.d", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnj_d)
-OP(fsgnjn_d, "fsgnjn.d", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjn_d)
-OP(fsgnjx_d, "fsgnjx.d", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjx_d)
-OP(fmin_d, "fmin.d", rv_codec_r, rv_fmt_frd_frs1_frs2)
-OP(fmax_d, "fmax.d", rv_codec_r, rv_fmt_frd_frs1_frs2)
-OP(fcvt_s_d, "fcvt.s.d", rv_codec_r_m, rv_fmt_rm_frd_frs1)
-OP(fcvt_d_s, "fcvt.d.s", rv_codec_r_m, rv_fmt_rm_frd_frs1)
-OP(fsqrt_d, "fsqrt.d", rv_codec_r_m, rv_fmt_rm_frd_frs1)
-OP(fle_d, "fle.d", rv_codec_r, rv_fmt_rd_frs1_frs2)
-OP(flt_d, "flt.d", rv_codec_r, rv_fmt_rd_frs1_frs2)
-OP(feq_d, "feq.d", rv_codec_r, rv_fmt_rd_frs1_frs2)
-OP(fcvt_w_d, "fcvt.w.d", rv_codec_r_m, rv_fmt_rm_rd_frs1)
-OP(fcvt_wu_d, "fcvt.wu.d", rv_codec_r_m, rv_fmt_rm_rd_frs1)
-OP(fcvt_d_w, "fcvt.d.w", rv_codec_r_m, rv_fmt_rm_frd_rs1)
-OP(fcvt_d_wu, "fcvt.d.wu", rv_codec_r_m, rv_fmt_rm_frd_rs1)
-OP(fclass_d, "fclass.d", rv_codec_r, rv_fmt_rd_frs1)
-OP(fcvt_l_d, "fcvt.l.d", rv_codec_r_m, rv_fmt_rm_rd_frs1)
-OP(fcvt_lu_d, "fcvt.lu.d", rv_codec_r_m, rv_fmt_rm_rd_frs1)
-OP(fmv_x_d, "fmv.x.d", rv_codec_r, rv_fmt_rd_frs1)
-OP(fcvt_d_l, "fcvt.d.l", rv_codec_r_m, rv_fmt_rm_frd_rs1)
-OP(fcvt_d_lu, "fcvt.d.lu", rv_codec_r_m, rv_fmt_rm_frd_rs1)
-OP(fmv_d_x, "fmv.d.x", rv_codec_r, rv_fmt_frd_rs1)
-OP(flq, "flq", rv_codec_i, rv_fmt_frd_offset_rs1)
-OP(fsq, "fsq", rv_codec_s, rv_fmt_frs2_offset_rs1)
-OP(fmadd_q, "fmadd.q", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3)
-OP(fmsub_q, "fmsub.q", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3)
-OP(fnmsub_q, "fnmsub.q", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3)
-OP(fnmadd_q, "fnmadd.q", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3)
-OP(fadd_q, "fadd.q", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2)
-OP(fsub_q, "fsub.q", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2)
-OP(fmul_q, "fmul.q", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2)
-OP(fdiv_q, "fdiv.q", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2)
-OP(fsgnj_q, "fsgnj.q", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnj_q)
-OP(fsgnjn_q, "fsgnjn.q", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjn_q)
-OP(fsgnjx_q, "fsgnjx.q", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjx_q)
-OP(fmin_q, "fmin.q", rv_codec_r, rv_fmt_frd_frs1_frs2)
-OP(fmax_q, "fmax.q", rv_codec_r, rv_fmt_frd_frs1_frs2)
-OP(fcvt_s_q, "fcvt.s.q", rv_codec_r_m, rv_fmt_rm_frd_frs1)
-OP(fcvt_q_s, "fcvt.q.s", rv_codec_r_m, rv_fmt_rm_frd_frs1)
-OP(fcvt_d_q, "fcvt.d.q", rv_codec_r_m, rv_fmt_rm_frd_frs1)
-OP(fcvt_q_d, "fcvt.q.d", rv_codec_r_m, rv_fmt_rm_frd_frs1)
-OP(fsqrt_q, "fsqrt.q", rv_codec_r_m, rv_fmt_rm_frd_frs1)
-OP(fle_q, "fle.q", rv_codec_r, rv_fmt_rd_frs1_frs2)
-OP(flt_q, "flt.q", rv_codec_r, rv_fmt_rd_frs1_frs2)
-OP(feq_q, "feq.q", rv_codec_r, rv_fmt_rd_frs1_frs2)
-OP(fcvt_w_q, "fcvt.w.q", rv_codec_r_m, rv_fmt_rm_rd_frs1)
-OP(fcvt_wu_q, "fcvt.wu.q", rv_codec_r_m, rv_fmt_rm_rd_frs1)
-OP(fcvt_q_w, "fcvt.q.w", rv_codec_r_m, rv_fmt_rm_frd_rs1)
-OP(fcvt_q_wu, "fcvt.q.wu", rv_codec_r_m, rv_fmt_rm_frd_rs1)
-OP(fclass_q, "fclass.q", rv_codec_r, rv_fmt_rd_frs1)
-OP(fcvt_l_q, "fcvt.l.q", rv_codec_r_m, rv_fmt_rm_rd_frs1)
-OP(fcvt_lu_q, "fcvt.lu.q", rv_codec_r_m, rv_fmt_rm_rd_frs1)
-OP(fcvt_q_l, "fcvt.q.l", rv_codec_r_m, rv_fmt_rm_frd_rs1)
-OP(fcvt_q_lu, "fcvt.q.lu", rv_codec_r_m, rv_fmt_rm_frd_rs1)
-OP(fmv_x_q, "fmv.x.q", rv_codec_r, rv_fmt_rd_frs1)
-OP(fmv_q_x, "fmv.q.x", rv_codec_r, rv_fmt_frd_rs1)
-OP(c_addi4spn, "c.addi4spn", rv_codec_ciw_4spn, NULL, DECOMP(op_addi))
-OP(c_fld, "c.fld", rv_codec_cl_ld, NULL, DECOMP(op_fld))
-OP(c_lw, "c.lw", rv_codec_cl_lw, NULL, DECOMP(op_lw))
-OP(c_flw, "c.flw", rv_codec_cl_lw, NULL, DECOMP(op_flw))
-OP(c_fsd, "c.fsd", rv_codec_cs_sd, NULL, DECOMP(op_fsd))
-OP(c_sw, "c.sw", rv_codec_cs_sw, NULL, DECOMP(op_sw))
-OP(c_fsw, "c.fsw", rv_codec_cs_sw, NULL, DECOMP(op_fsw))
-OP(c_addi, "c.addi", rv_codec_ci, NULL, DECOMP(op_addi))
-OP(c_jal, "c.jal", rv_codec_cj_jal, NULL, DECOMP(op_jal))
-OP(c_li, "c.li", rv_codec_ci_li, NULL, DECOMP(op_addi))
-OP(c_addi16sp, "c.addi16sp", rv_codec_ci_16sp, NULL, DECOMP(op_addi))
-OP(c_lui, "c.lui", rv_codec_ci_lui, NULL, DECOMP(op_lui))
-OP(c_srli, "c.srli", rv_codec_cb_sh6, NULL, DECOMP(op_srli))
-OP(c_srai, "c.srai", rv_codec_cb_sh6, NULL, DECOMP(op_srai))
-OP(c_andi, "c.andi", rv_codec_cb_imm, NULL, DECOMP(op_andi))
-OP(c_sub, "c.sub", rv_codec_cs, NULL, DECOMP(op_sub))
-OP(c_xor, "c.xor", rv_codec_cs, NULL, DECOMP(op_xor))
-OP(c_or, "c.or", rv_codec_cs, NULL, DECOMP(op_or))
-OP(c_and, "c.and", rv_codec_cs, NULL, DECOMP(op_and))
-OP(c_subw, "c.subw", rv_codec_cs, NULL, DECOMP(op_subw))
-OP(c_addw, "c.addw", rv_codec_cs, NULL, DECOMP(op_addw))
-OP(c_j, "c.j", rv_codec_cj, NULL, DECOMP(op_j))
-OP(c_beqz, "c.beqz", rv_codec_cb, NULL, DECOMP(op_beqz))
-OP(c_bnez, "c.bnez", rv_codec_cb, NULL, DECOMP(op_bnez))
-OP(c_slli, "c.slli", rv_codec_ci_sh6, NULL, DECOMP(op_slli))
-OP(c_fldsp, "c.fldsp", rv_codec_ci_ldsp, NULL, DECOMP(op_fld))
-OP(c_lwsp, "c.lwsp", rv_codec_ci_lwsp, NULL, DECOMP(op_lw))
-OP(c_flwsp, "c.flwsp", rv_codec_ci_lwsp, NULL, DECOMP(op_flw))
-OP(c_jr, "c.jr", rv_codec_cr_jr, NULL, DECOMP(op_jr))
-OP(c_mv, "c.mv", rv_codec_cr_mv, NULL, DECOMP(op_mv))
-OP(c_ebreak, "c.ebreak", rv_codec_ci_none, NULL, DECOMP(op_ebreak))
-OP(c_jalr, "c.jalr", rv_codec_cr_jalr, NULL, DECOMP(op_jalr))
-OP(c_add, "c.add", rv_codec_cr, NULL, DECOMP(op_add))
-OP(c_fsdsp, "c.fsdsp", rv_codec_css_sdsp, NULL, DECOMP(op_fsd))
-OP(c_swsp, "c.swsp", rv_codec_css_swsp, NULL, DECOMP(op_sw))
-OP(c_fswsp, "c.fswsp", rv_codec_css_swsp, NULL, DECOMP(op_fsw))
-OP(c_ld, "c.ld", rv_codec_cl_ld, NULL, DECOMP(op_ld))
-OP(c_sd, "c.sd", rv_codec_cs_sd, NULL, DECOMP(op_sd))
-OP(c_addiw, "c.addiw", rv_codec_ci, NULL, DECOMP(op_addiw))
-OP(c_ldsp, "c.ldsp", rv_codec_ci_ldsp, NULL, DECOMP(op_ld))
-OP(c_sdsp, "c.sdsp", rv_codec_css_sdsp, NULL, DECOMP(op_sd))
-OP(c_lq, "c.lq", rv_codec_cl_lq, NULL, DECOMP(op_lq))
-OP(c_sq, "c.sq", rv_codec_cs_sq, NULL, DECOMP(op_sq))
-OP(c_lqsp, "c.lqsp", rv_codec_ci_lqsp, NULL, DECOMP(op_lq))
-OP(c_sqsp, "c.sqsp", rv_codec_css_sqsp, NULL, DECOMP(op_sq))
-OP(nop, "nop", rv_codec_illegal, rv_fmt_none)
OP(mv, "mv", rv_codec_illegal, rv_fmt_rd_rs1, rvcp_mv)
-OP(not, "not", rv_codec_illegal, rv_fmt_rd_rs1)
OP(neg, "neg", rv_codec_illegal, rv_fmt_rd_rs2)
OP(negw, "negw", rv_codec_illegal, rv_fmt_rd_rs2)
-OP(sext_w, "sext.w", rv_codec_illegal, rv_fmt_rd_rs1)
-OP(seqz, "seqz", rv_codec_illegal, rv_fmt_rd_rs1)
-OP(snez, "snez", rv_codec_illegal, rv_fmt_rd_rs2)
-OP(sltz, "sltz", rv_codec_illegal, rv_fmt_rd_rs1)
-OP(sgtz, "sgtz", rv_codec_illegal, rv_fmt_rd_rs2)
-OP(fmv_s, "fmv.s", rv_codec_illegal, rv_fmt_frd_frs1)
-OP(fabs_s, "fabs.s", rv_codec_illegal, rv_fmt_frd_frs1)
-OP(fneg_s, "fneg.s", rv_codec_illegal, rv_fmt_frd_frs1)
-OP(fmv_d, "fmv.d", rv_codec_illegal, rv_fmt_frd_frs1)
-OP(fabs_d, "fabs.d", rv_codec_illegal, rv_fmt_frd_frs1)
-OP(fneg_d, "fneg.d", rv_codec_illegal, rv_fmt_frd_frs1)
-OP(fmv_q, "fmv.q", rv_codec_illegal, rv_fmt_frd_frs1)
-OP(fabs_q, "fabs.q", rv_codec_illegal, rv_fmt_frd_frs1)
-OP(fneg_q, "fneg.q", rv_codec_illegal, rv_fmt_frd_frs1)
-OP(beqz, "beqz", rv_codec_illegal, rv_fmt_rs1_offset)
-OP(bnez, "bnez", rv_codec_illegal, rv_fmt_rs1_offset)
-OP(blez, "blez", rv_codec_illegal, rv_fmt_rs2_offset)
-OP(bgez, "bgez", rv_codec_illegal, rv_fmt_rs1_offset)
-OP(bltz, "bltz", rv_codec_illegal, rv_fmt_rs1_offset)
-OP(bgtz, "bgtz", rv_codec_illegal, rv_fmt_rs2_offset)
-OP(jal_ra, "jal", rv_codec_illegal, rv_fmt_offset)
-OP(jalr_ra, "jalr", rv_codec_illegal, rv_fmt_rs1)
-OP(j, "j", rv_codec_illegal, rv_fmt_offset)
-OP(ret, "ret", rv_codec_illegal, rv_fmt_none)
-OP(jr, "jr", rv_codec_illegal, rv_fmt_rs1, rvcp_jr)
-OP(rdcycle, "rdcycle", rv_codec_i_csr, rv_fmt_rd)
-OP(rdtime, "rdtime", rv_codec_i_csr, rv_fmt_rd)
-OP(rdinstret, "rdinstret", rv_codec_i_csr, rv_fmt_rd)
-OP(rdcycleh, "rdcycleh", rv_codec_i_csr, rv_fmt_rd)
-OP(rdtimeh, "rdtimeh", rv_codec_i_csr, rv_fmt_rd)
-OP(rdinstreth, "rdinstreth", rv_codec_i_csr, rv_fmt_rd)
-OP(frcsr, "frcsr", rv_codec_i_csr, rv_fmt_rd)
-OP(frrm, "frrm", rv_codec_i_csr, rv_fmt_rd)
-OP(frflags, "frflags", rv_codec_i_csr, rv_fmt_rd)
-OP(fscsr, "fscsr", rv_codec_i_csr, rv_fmt_rd_rs1)
-OP(fsrm, "fsrm", rv_codec_i_csr, rv_fmt_rd_rs1)
-OP(fsflags, "fsflags", rv_codec_i_csr, rv_fmt_rd_rs1)
-OP(fsrmi, "fsrmi", rv_codec_i_csr, rv_fmt_rd_zimm)
-OP(fsflagsi, "fsflagsi", rv_codec_i_csr, rv_fmt_rd_zimm)
-OP(bseti, "bseti", rv_codec_i_sh7, rv_fmt_rd_rs1_imm)
-OP(bclri, "bclri", rv_codec_i_sh7, rv_fmt_rd_rs1_imm)
-OP(binvi, "binvi", rv_codec_i_sh7, rv_fmt_rd_rs1_imm)
-OP(bexti, "bexti", rv_codec_i_sh7, rv_fmt_rd_rs1_imm)
-OP(rori, "rori", rv_codec_i_sh7, rv_fmt_rd_rs1_imm)
-OP(clz, "clz", rv_codec_r, rv_fmt_rd_rs1)
-OP(ctz, "ctz", rv_codec_r, rv_fmt_rd_rs1)
-OP(cpop, "cpop", rv_codec_r, rv_fmt_rd_rs1)
-OP(sext_h, "sext.h", rv_codec_r, rv_fmt_rd_rs1)
-OP(sext_b, "sext.b", rv_codec_r, rv_fmt_rd_rs1)
-OP(xnor, "xnor", rv_codec_r, rv_fmt_rd_rs1_rs2)
-OP(orn, "orn", rv_codec_r, rv_fmt_rd_rs1_rs2)
-OP(andn, "andn", rv_codec_r, rv_fmt_rd_rs1_rs2)
-OP(rol, "rol", rv_codec_r, rv_fmt_rd_rs1_rs2)
-OP(ror, "ror", rv_codec_r, rv_fmt_rd_rs1_rs2)
-OP(sh1add, "sh1add", rv_codec_r, rv_fmt_rd_rs1_rs2)
-OP(sh2add, "sh2add", rv_codec_r, rv_fmt_rd_rs1_rs2)
-OP(sh3add, "sh3add", rv_codec_r, rv_fmt_rd_rs1_rs2)
-OP(sh1add_uw, "sh1add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2)
-OP(sh2add_uw, "sh2add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2)
-OP(sh3add_uw, "sh3add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2)
-OP(clmul, "clmul", rv_codec_r, rv_fmt_rd_rs1_rs2)
-OP(clmulr, "clmulr", rv_codec_r, rv_fmt_rd_rs1_rs2)
-OP(clmulh, "clmulh", rv_codec_r, rv_fmt_rd_rs1_rs2)
-OP(min, "min", rv_codec_r, rv_fmt_rd_rs1_rs2)
-OP(minu, "minu", rv_codec_r, rv_fmt_rd_rs1_rs2)
-OP(max, "max", rv_codec_r, rv_fmt_rd_rs1_rs2)
-OP(maxu, "maxu", rv_codec_r, rv_fmt_rd_rs1_rs2)
-OP(clzw, "clzw", rv_codec_r, rv_fmt_rd_rs1)
-OP(ctzw, "ctzw", rv_codec_r, rv_fmt_rd_rs1)
-OP(cpopw, "cpopw", rv_codec_r, rv_fmt_rd_rs1)
-OP(slli_uw, "slli.uw", rv_codec_i_sh6, rv_fmt_rd_rs1_imm)
-OP(add_uw, "add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2)
-OP(rolw, "rolw", rv_codec_r, rv_fmt_rd_rs1_rs2)
-OP(rorw, "rorw", rv_codec_r, rv_fmt_rd_rs1_rs2)
-OP(rev8, "rev8", rv_codec_r, rv_fmt_rd_rs1)
-OP(zext_h, "zext.h", rv_codec_r, rv_fmt_rd_rs1)
-OP(roriw, "roriw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm)
+OP(nop, "nop", rv_codec_illegal, rv_fmt_none)
+OP(not, "not", rv_codec_illegal, rv_fmt_rd_rs1)
+OP(or, "or", rv_codec_r, rv_fmt_rd_rs1_rs2)
OP(orc_b, "orc.b", rv_codec_r, rv_fmt_rd_rs1)
-OP(bset, "bset", rv_codec_r, rv_fmt_rd_rs1_rs2)
-OP(bclr, "bclr", rv_codec_r, rv_fmt_rd_rs1_rs2)
-OP(binv, "binv", rv_codec_r, rv_fmt_rd_rs1_rs2)
-OP(bext, "bext", rv_codec_r, rv_fmt_rd_rs1_rs2)
-OP(aes32esmi, "aes32esmi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs)
-OP(aes32esi, "aes32esi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs)
-OP(aes32dsmi, "aes32dsmi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs)
-OP(aes32dsi, "aes32dsi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs)
-OP(aes64ks1i, "aes64ks1i", rv_codec_k_rnum, rv_fmt_rd_rs1_rnum)
-OP(aes64ks2, "aes64ks2", rv_codec_r, rv_fmt_rd_rs1_rs2)
-OP(aes64im, "aes64im", rv_codec_r, rv_fmt_rd_rs1)
-OP(aes64esm, "aes64esm", rv_codec_r, rv_fmt_rd_rs1_rs2)
-OP(aes64es, "aes64es", rv_codec_r, rv_fmt_rd_rs1_rs2)
-OP(aes64dsm, "aes64dsm", rv_codec_r, rv_fmt_rd_rs1_rs2)
-OP(aes64ds, "aes64ds", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(ori, "ori", rv_codec_i, rv_fmt_rd_rs1_imm)
+OP(orn, "orn", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(pack, "pack", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(packh, "packh", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(packw, "packw", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(rdcycle, "rdcycle", rv_codec_i_csr, rv_fmt_rd)
+OP(rdcycleh, "rdcycleh", rv_codec_i_csr, rv_fmt_rd)
+OP(rdinstret, "rdinstret", rv_codec_i_csr, rv_fmt_rd)
+OP(rdinstreth, "rdinstreth", rv_codec_i_csr, rv_fmt_rd)
+OP(rdtime, "rdtime", rv_codec_i_csr, rv_fmt_rd)
+OP(rdtimeh, "rdtimeh", rv_codec_i_csr, rv_fmt_rd)
+OP(rem, "rem", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(remd, "remd", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(remu, "remu", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(remud, "remud", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(remuw, "remuw", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(remw, "remw", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(ret, "ret", rv_codec_illegal, rv_fmt_none)
+OP(rev8, "rev8", rv_codec_r, rv_fmt_rd_rs1)
+OP(rol, "rol", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(rolw, "rolw", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(ror, "ror", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(rori, "rori", rv_codec_i_sh7, rv_fmt_rd_rs1_imm)
+OP(roriw, "roriw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm)
+OP(rorw, "rorw", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(sb, "sb", rv_codec_s, rv_fmt_rs2_offset_rs1)
+OP(sc_d, "sc.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
+OP(sc_q, "sc.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
+OP(sc_w, "sc.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
+OP(sd, "sd", rv_codec_s, rv_fmt_rs2_offset_rs1)
+OP(seqz, "seqz", rv_codec_illegal, rv_fmt_rd_rs1)
+OP(sext_b, "sext.b", rv_codec_r, rv_fmt_rd_rs1)
+OP(sext_h, "sext.h", rv_codec_r, rv_fmt_rd_rs1)
+OP(sext_w, "sext.w", rv_codec_illegal, rv_fmt_rd_rs1)
+OP(sfence_vm, "sfence.vm", rv_codec_r, rv_fmt_rs1)
+OP(sfence_vma, "sfence.vma", rv_codec_r, rv_fmt_rs1_rs2)
+OP(sgtz, "sgtz", rv_codec_illegal, rv_fmt_rd_rs2)
+OP(sh, "sh", rv_codec_s, rv_fmt_rs2_offset_rs1)
+OP(sh1add, "sh1add", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(sh1add_uw, "sh1add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(sh2add, "sh2add", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(sh2add_uw, "sh2add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(sh3add, "sh3add", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(sh3add_uw, "sh3add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2)
OP(sha256sig0, "sha256sig0", rv_codec_r, rv_fmt_rd_rs1)
OP(sha256sig1, "sha256sig1", rv_codec_r, rv_fmt_rd_rs1)
OP(sha256sum0, "sha256sum0", rv_codec_r, rv_fmt_rd_rs1)
OP(sha256sum1, "sha256sum1", rv_codec_r, rv_fmt_rd_rs1)
OP(sha512sig0, "sha512sig0", rv_codec_r, rv_fmt_rd_rs1_rs2)
-OP(sha512sig1, "sha512sig1", rv_codec_r, rv_fmt_rd_rs1_rs2)
-OP(sha512sum0, "sha512sum0", rv_codec_r, rv_fmt_rd_rs1_rs2)
-OP(sha512sum1, "sha512sum1", rv_codec_r, rv_fmt_rd_rs1_rs2)
-OP(sha512sum0r, "sha512sum0r", rv_codec_r, rv_fmt_rd_rs1_rs2)
-OP(sha512sum1r, "sha512sum1r", rv_codec_r, rv_fmt_rd_rs1_rs2)
-OP(sha512sig0l, "sha512sig0l", rv_codec_r, rv_fmt_rd_rs1_rs2)
OP(sha512sig0h, "sha512sig0h", rv_codec_r, rv_fmt_rd_rs1_rs2)
-OP(sha512sig1l, "sha512sig1l", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(sha512sig0l, "sha512sig0l", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(sha512sig1, "sha512sig1", rv_codec_r, rv_fmt_rd_rs1_rs2)
OP(sha512sig1h, "sha512sig1h", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(sha512sig1l, "sha512sig1l", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(sha512sum0, "sha512sum0", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(sha512sum0r, "sha512sum0r", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(sha512sum1, "sha512sum1", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(sha512sum1r, "sha512sum1r", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(sll, "sll", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(slld, "slld", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(slli, "slli", rv_codec_i_sh7, rv_fmt_rd_rs1_imm)
+OP(slli_uw, "slli.uw", rv_codec_i_sh6, rv_fmt_rd_rs1_imm)
+OP(sllid, "sllid", rv_codec_i_sh6, rv_fmt_rd_rs1_imm)
+OP(slliw, "slliw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm)
+OP(sllw, "sllw", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(slt, "slt", rv_codec_r, rv_fmt_rd_rs1_rs2, rvcp_slt)
+OP(slti, "slti", rv_codec_i, rv_fmt_rd_rs1_imm)
+OP(sltiu, "sltiu", rv_codec_i, rv_fmt_rd_rs1_imm, rvcp_sltiu)
+OP(sltu, "sltu", rv_codec_r, rv_fmt_rd_rs1_rs2, rvcp_sltu)
+OP(sltz, "sltz", rv_codec_illegal, rv_fmt_rd_rs1)
OP(sm3p0, "sm3p0", rv_codec_r, rv_fmt_rd_rs1)
OP(sm3p1, "sm3p1", rv_codec_r, rv_fmt_rd_rs1)
OP(sm4ed, "sm4ed", rv_codec_k_bs, rv_fmt_rs1_rs2_bs)
OP(sm4ks, "sm4ks", rv_codec_k_bs, rv_fmt_rs1_rs2_bs)
-OP(brev8, "brev8", rv_codec_r, rv_fmt_rd_rs1)
-OP(pack, "pack", rv_codec_r, rv_fmt_rd_rs1_rs2)
-OP(packh, "packh", rv_codec_r, rv_fmt_rd_rs1_rs2)
-OP(packw, "packw", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(snez, "snez", rv_codec_illegal, rv_fmt_rd_rs2)
+OP(sq, "sq", rv_codec_s, rv_fmt_rs2_offset_rs1)
+OP(sra, "sra", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(srad, "srad", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(srai, "srai", rv_codec_i_sh7, rv_fmt_rd_rs1_imm)
+OP(sraid, "sraid", rv_codec_i_sh6, rv_fmt_rd_rs1_imm)
+OP(sraiw, "sraiw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm)
+OP(sraw, "sraw", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(sret, "sret", rv_codec_none, rv_fmt_none)
+OP(srl, "srl", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(srld, "srld", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(srli, "srli", rv_codec_i_sh7, rv_fmt_rd_rs1_imm)
+OP(srlid, "srlid", rv_codec_i_sh6, rv_fmt_rd_rs1_imm)
+OP(srliw, "srliw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm)
+OP(srlw, "srlw", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(ssamoswap_d, "ssamoswap.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
+OP(ssamoswap_w, "ssamoswap.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
+OP(sspopchk, "sspopchk", rv_codec_r, rv_fmt_rs1)
+OP(sspush, "sspush", rv_codec_r, rv_fmt_rs2)
+OP(ssrdp, "ssrdp", rv_codec_r, rv_fmt_rd)
+OP(sub, "sub", rv_codec_r, rv_fmt_rd_rs1_rs2, rvcp_sub)
+OP(subd, "subd", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(subw, "subw", rv_codec_r, rv_fmt_rd_rs1_rs2, rvcp_subw)
+OP(sw, "sw", rv_codec_s, rv_fmt_rs2_offset_rs1)
OP(unzip, "unzip", rv_codec_r, rv_fmt_rd_rs1)
-OP(zip, "zip", rv_codec_r, rv_fmt_rd_rs1)
-OP(xperm4, "xperm4", rv_codec_r, rv_fmt_rd_rs1_rs2)
-OP(xperm8, "xperm8", rv_codec_r, rv_fmt_rd_rs1)
-OP(vle8_v, "vle8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
-OP(vle16_v, "vle16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
-OP(vle32_v, "vle32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
-OP(vle64_v, "vle64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
-OP(vse8_v, "vse8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
-OP(vse16_v, "vse16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
-OP(vse32_v, "vse32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
-OP(vse64_v, "vse64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
-OP(vlm_v, "vlm.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
-OP(vsm_v, "vsm.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
-OP(vlse8_v, "vlse8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm)
-OP(vlse16_v, "vlse16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm)
-OP(vlse32_v, "vlse32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm)
-OP(vlse64_v, "vlse64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm)
-OP(vsse8_v, "vsse8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm)
-OP(vsse16_v, "vsse16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm)
-OP(vsse32_v, "vsse32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm)
-OP(vsse64_v, "vsse64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm)
-OP(vluxei8_v, "vluxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm)
-OP(vluxei16_v, "vluxei16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm)
-OP(vluxei32_v, "vluxei32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm)
-OP(vluxei64_v, "vluxei64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm)
-OP(vloxei8_v, "vloxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm)
-OP(vloxei16_v, "vloxei16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm)
-OP(vloxei32_v, "vloxei32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm)
-OP(vloxei64_v, "vloxei64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm)
-OP(vsuxei8_v, "vsuxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm)
-OP(vsuxei16_v, "vsuxei16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm)
-OP(vsuxei32_v, "vsuxei32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm)
-OP(vsuxei64_v, "vsuxei64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm)
-OP(vsoxei8_v, "vsoxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm)
-OP(vsoxei16_v, "vsoxei16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm)
-OP(vsoxei32_v, "vsoxei32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm)
-OP(vsoxei64_v, "vsoxei64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm)
-OP(vle8ff_v, "vle8ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
-OP(vle16ff_v, "vle16ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
-OP(vle32ff_v, "vle32ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
-OP(vle64ff_v, "vle64ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
-OP(vl1re8_v, "vl1re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
-OP(vl1re16_v, "vl1re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
-OP(vl1re32_v, "vl1re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
-OP(vl1re64_v, "vl1re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
-OP(vl2re8_v, "vl2re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
-OP(vl2re16_v, "vl2re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
-OP(vl2re32_v, "vl2re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
-OP(vl2re64_v, "vl2re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
-OP(vl4re8_v, "vl4re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
-OP(vl4re16_v, "vl4re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
-OP(vl4re32_v, "vl4re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
-OP(vl4re64_v, "vl4re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
-OP(vl8re8_v, "vl8re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
-OP(vl8re16_v, "vl8re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
-OP(vl8re32_v, "vl8re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
-OP(vl8re64_v, "vl8re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
-OP(vs1r_v, "vs1r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
-OP(vs2r_v, "vs2r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
-OP(vs4r_v, "vs4r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
-OP(vs8r_v, "vs8r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
-OP(vadd_vv, "vadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
-OP(vadd_vx, "vadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
-OP(vadd_vi, "vadd.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm)
-OP(vsub_vv, "vsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
-OP(vsub_vx, "vsub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
-OP(vrsub_vx, "vrsub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
-OP(vrsub_vi, "vrsub.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm)
-OP(vwaddu_vv, "vwaddu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
-OP(vwaddu_vx, "vwaddu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
-OP(vwadd_vv, "vwadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
-OP(vwadd_vx, "vwadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
-OP(vwsubu_vv, "vwsubu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
-OP(vwsubu_vx, "vwsubu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
-OP(vwsub_vv, "vwsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
-OP(vwsub_vx, "vwsub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
-OP(vwaddu_wv, "vwaddu.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
-OP(vwaddu_wx, "vwaddu.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
-OP(vwadd_wv, "vwadd.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
-OP(vwadd_wx, "vwadd.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
-OP(vwsubu_wv, "vwsubu.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
-OP(vwsubu_wx, "vwsubu.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
-OP(vwsub_wv, "vwsub.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
-OP(vwsub_wx, "vwsub.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
-OP(vadc_vvm, "vadc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl)
-OP(vadc_vxm, "vadc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl)
-OP(vadc_vim, "vadc.vim", rv_codec_v_i, rv_fmt_vd_vs2_imm_vl)
-OP(vmadc_vvm, "vmadc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl)
-OP(vmadc_vxm, "vmadc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl)
-OP(vmadc_vim, "vmadc.vim", rv_codec_v_i, rv_fmt_vd_vs2_imm_vl)
-OP(vsbc_vvm, "vsbc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl)
-OP(vsbc_vxm, "vsbc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl)
-OP(vmsbc_vvm, "vmsbc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl)
-OP(vmsbc_vxm, "vmsbc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl)
-OP(vand_vv, "vand.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
-OP(vand_vx, "vand.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
-OP(vand_vi, "vand.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm)
-OP(vor_vv, "vor.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
-OP(vor_vx, "vor.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
-OP(vor_vi, "vor.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm)
-OP(vxor_vv, "vxor.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
-OP(vxor_vx, "vxor.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
-OP(vxor_vi, "vxor.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm)
-OP(vsll_vv, "vsll.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
-OP(vsll_vx, "vsll.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
-OP(vsll_vi, "vsll.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm)
-OP(vsrl_vv, "vsrl.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
-OP(vsrl_vx, "vsrl.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
-OP(vsrl_vi, "vsrl.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm)
-OP(vsra_vv, "vsra.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
-OP(vsra_vx, "vsra.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
-OP(vsra_vi, "vsra.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm)
-OP(vnsrl_wv, "vnsrl.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
-OP(vnsrl_wx, "vnsrl.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
-OP(vnsrl_wi, "vnsrl.wi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm)
-OP(vnsra_wv, "vnsra.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
-OP(vnsra_wx, "vnsra.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
-OP(vnsra_wi, "vnsra.wi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm)
-OP(vmseq_vv, "vmseq.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
-OP(vmseq_vx, "vmseq.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
-OP(vmseq_vi, "vmseq.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm)
-OP(vmsne_vv, "vmsne.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
-OP(vmsne_vx, "vmsne.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
-OP(vmsne_vi, "vmsne.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm)
-OP(vmsltu_vv, "vmsltu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
-OP(vmsltu_vx, "vmsltu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
-OP(vmslt_vv, "vmslt.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
-OP(vmslt_vx, "vmslt.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
-OP(vmsleu_vv, "vmsleu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
-OP(vmsleu_vx, "vmsleu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
-OP(vmsleu_vi, "vmsleu.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm)
-OP(vmsle_vv, "vmsle.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
-OP(vmsle_vx, "vmsle.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
-OP(vmsle_vi, "vmsle.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm)
-OP(vmsgtu_vx, "vmsgtu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
-OP(vmsgtu_vi, "vmsgtu.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm)
-OP(vmsgt_vx, "vmsgt.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
-OP(vmsgt_vi, "vmsgt.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm)
-OP(vminu_vv, "vminu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
-OP(vminu_vx, "vminu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
-OP(vmin_vv, "vmin.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
-OP(vmin_vx, "vmin.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
-OP(vmaxu_vv, "vmaxu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
-OP(vmaxu_vx, "vmaxu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
-OP(vmax_vv, "vmax.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
-OP(vmax_vx, "vmax.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
-OP(vmul_vv, "vmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
-OP(vmul_vx, "vmul.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
-OP(vmulh_vv, "vmulh.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
-OP(vmulh_vx, "vmulh.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
-OP(vmulhu_vv, "vmulhu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
-OP(vmulhu_vx, "vmulhu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
-OP(vmulhsu_vv, "vmulhsu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
-OP(vmulhsu_vx, "vmulhsu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
-OP(vdivu_vv, "vdivu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
-OP(vdivu_vx, "vdivu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
-OP(vdiv_vv, "vdiv.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
-OP(vdiv_vx, "vdiv.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
-OP(vremu_vv, "vremu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
-OP(vremu_vx, "vremu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
-OP(vrem_vv, "vrem.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
-OP(vrem_vx, "vrem.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
-OP(vwmulu_vv, "vwmulu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
-OP(vwmulu_vx, "vwmulu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
-OP(vwmulsu_vv, "vwmulsu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
-OP(vwmulsu_vx, "vwmulsu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
-OP(vwmul_vv, "vwmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
-OP(vwmul_vx, "vwmul.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
-OP(vmacc_vv, "vmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
-OP(vmacc_vx, "vmacc.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm)
-OP(vnmsac_vv, "vnmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
-OP(vnmsac_vx, "vnmsac.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm)
-OP(vmadd_vv, "vmadd.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
-OP(vmadd_vx, "vmadd.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm)
-OP(vnmsub_vv, "vnmsub.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
-OP(vnmsub_vx, "vnmsub.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm)
-OP(vwmaccu_vv, "vwmaccu.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
-OP(vwmaccu_vx, "vwmaccu.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm)
-OP(vwmacc_vv, "vwmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
-OP(vwmacc_vx, "vwmacc.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm)
-OP(vwmaccsu_vv, "vwmaccsu.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
-OP(vwmaccsu_vx, "vwmaccsu.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm)
-OP(vwmaccus_vx, "vwmaccus.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm)
-OP(vmv_v_v, "vmv.v.v", rv_codec_v_r, rv_fmt_vd_vs1)
-OP(vmv_v_x, "vmv.v.x", rv_codec_v_r, rv_fmt_vd_rs1)
-OP(vmv_v_i, "vmv.v.i", rv_codec_v_i, rv_fmt_vd_imm)
-OP(vmerge_vvm, "vmerge.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl)
-OP(vmerge_vxm, "vmerge.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl)
-OP(vmerge_vim, "vmerge.vim", rv_codec_v_i, rv_fmt_vd_vs2_imm_vl)
-OP(vsaddu_vv, "vsaddu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
-OP(vsaddu_vx, "vsaddu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
-OP(vsaddu_vi, "vsaddu.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm)
-OP(vsadd_vv, "vsadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
-OP(vsadd_vx, "vsadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
-OP(vsadd_vi, "vsadd.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm)
-OP(vssubu_vv, "vssubu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
-OP(vssubu_vx, "vssubu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
-OP(vssub_vv, "vssub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
-OP(vssub_vx, "vssub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
+OP(uret, "uret", rv_codec_none, rv_fmt_none)
OP(vaadd_vv, "vaadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
OP(vaadd_vx, "vaadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
OP(vaaddu_vv, "vaaddu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
OP(vaaddu_vx, "vaaddu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
+OP(vadc_vim, "vadc.vim", rv_codec_v_i, rv_fmt_vd_vs2_imm_vl)
+OP(vadc_vvm, "vadc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl)
+OP(vadc_vxm, "vadc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl)
+OP(vadd_vi, "vadd.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm)
+OP(vadd_vv, "vadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vadd_vx, "vadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
+OP(vaesdf_vs, "vaesdf.vs", rv_codec_v_r, rv_fmt_vd_vs2)
+OP(vaesdf_vv, "vaesdf.vv", rv_codec_v_r, rv_fmt_vd_vs2)
+OP(vaesdm_vs, "vaesdm.vs", rv_codec_v_r, rv_fmt_vd_vs2)
+OP(vaesdm_vv, "vaesdm.vv", rv_codec_v_r, rv_fmt_vd_vs2)
+OP(vaesef_vs, "vaesef.vs", rv_codec_v_r, rv_fmt_vd_vs2)
+OP(vaesef_vv, "vaesef.vv", rv_codec_v_r, rv_fmt_vd_vs2)
+OP(vaesem_vs, "vaesem.vs", rv_codec_v_r, rv_fmt_vd_vs2)
+OP(vaesem_vv, "vaesem.vv", rv_codec_v_r, rv_fmt_vd_vs2)
+OP(vaeskf1_vi, "vaeskf1.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm)
+OP(vaeskf2_vi, "vaeskf2.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm)
+OP(vaesz_vs, "vaesz.vs", rv_codec_v_r, rv_fmt_vd_vs2)
+OP(vand_vi, "vand.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm)
+OP(vand_vv, "vand.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vand_vx, "vand.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
+OP(vandn_vv, "vandn.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vandn_vx, "vandn.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
OP(vasub_vv, "vasub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
OP(vasub_vx, "vasub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
OP(vasubu_vv, "vasubu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
OP(vasubu_vx, "vasubu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
-OP(vsmul_vv, "vsmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
-OP(vsmul_vx, "vsmul.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
-OP(vssrl_vv, "vssrl.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
-OP(vssrl_vx, "vssrl.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
-OP(vssrl_vi, "vssrl.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm)
-OP(vssra_vv, "vssra.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
-OP(vssra_vx, "vssra.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
-OP(vssra_vi, "vssra.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm)
-OP(vnclipu_wv, "vnclipu.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
-OP(vnclipu_wx, "vnclipu.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
-OP(vnclipu_wi, "vnclipu.wi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm)
-OP(vnclip_wv, "vnclip.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
-OP(vnclip_wx, "vnclip.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
-OP(vnclip_wi, "vnclip.wi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm)
-OP(vfadd_vv, "vfadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
-OP(vfadd_vf, "vfadd.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
-OP(vfsub_vv, "vfsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
-OP(vfsub_vf, "vfsub.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
-OP(vfrsub_vf, "vfrsub.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
-OP(vfwadd_vv, "vfwadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
-OP(vfwadd_vf, "vfwadd.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
-OP(vfwadd_wv, "vfwadd.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
-OP(vfwadd_wf, "vfwadd.wf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
-OP(vfwsub_vv, "vfwsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
-OP(vfwsub_vf, "vfwsub.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
-OP(vfwsub_wv, "vfwsub.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
-OP(vfwsub_wf, "vfwsub.wf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
-OP(vfmul_vv, "vfmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
-OP(vfmul_vf, "vfmul.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
-OP(vfdiv_vv, "vfdiv.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
-OP(vfdiv_vf, "vfdiv.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
-OP(vfrdiv_vf, "vfrdiv.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
-OP(vfwmul_vv, "vfwmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
-OP(vfwmul_vf, "vfwmul.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
-OP(vfmacc_vv, "vfmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
-OP(vfmacc_vf, "vfmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm)
-OP(vfnmacc_vv, "vfnmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
-OP(vfnmacc_vf, "vfnmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm)
-OP(vfmsac_vv, "vfmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
-OP(vfmsac_vf, "vfmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm)
-OP(vfnmsac_vv, "vfnmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
-OP(vfnmsac_vf, "vfnmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm)
-OP(vfmadd_vv, "vfmadd.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
-OP(vfmadd_vf, "vfmadd.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm)
-OP(vfnmadd_vv, "vfnmadd.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
-OP(vfnmadd_vf, "vfnmadd.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm)
-OP(vfmsub_vv, "vfmsub.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
-OP(vfmsub_vf, "vfmsub.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm)
-OP(vfnmsub_vv, "vfnmsub.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
-OP(vfnmsub_vf, "vfnmsub.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm)
-OP(vfwmacc_vv, "vfwmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
-OP(vfwmacc_vf, "vfwmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm)
-OP(vfwnmacc_vv, "vfwnmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
-OP(vfwnmacc_vf, "vfwnmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm)
-OP(vfwmsac_vv, "vfwmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
-OP(vfwmsac_vf, "vfwmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm)
-OP(vfwnmsac_vv, "vfwnmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
-OP(vfwnmsac_vf, "vfwnmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm)
-OP(vfsqrt_v, "vfsqrt.v", rv_codec_v_r, rv_fmt_vd_vs2)
-OP(vfrsqrt7_v, "vfrsqrt7.v", rv_codec_v_r, rv_fmt_vd_vs2)
-OP(vfrec7_v, "vfrec7.v", rv_codec_v_r, rv_fmt_vd_vs2)
-OP(vfmin_vv, "vfmin.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
-OP(vfmin_vf, "vfmin.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
-OP(vfmax_vv, "vfmax.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
-OP(vfmax_vf, "vfmax.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
-OP(vfsgnj_vv, "vfsgnj.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
-OP(vfsgnj_vf, "vfsgnj.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
-OP(vfsgnjn_vv, "vfsgnjn.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
-OP(vfsgnjn_vf, "vfsgnjn.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
-OP(vfsgnjx_vv, "vfsgnjx.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
-OP(vfsgnjx_vf, "vfsgnjx.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
-OP(vfslide1up_vf, "vfslide1up.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
-OP(vfslide1down_vf, "vfslide1down.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
-OP(vmfeq_vv, "vmfeq.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
-OP(vmfeq_vf, "vmfeq.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
-OP(vmfne_vv, "vmfne.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
-OP(vmfne_vf, "vmfne.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
-OP(vmflt_vv, "vmflt.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
-OP(vmflt_vf, "vmflt.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
-OP(vmfle_vv, "vmfle.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
-OP(vmfle_vf, "vmfle.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
-OP(vmfgt_vf, "vmfgt.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
-OP(vmfge_vf, "vmfge.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
-OP(vfclass_v, "vfclass.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
-OP(vfmerge_vfm, "vfmerge.vfm", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vl)
-OP(vfmv_v_f, "vfmv.v.f", rv_codec_v_r, rv_fmt_vd_fs1)
-OP(vfcvt_xu_f_v, "vfcvt.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
-OP(vfcvt_x_f_v, "vfcvt.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
-OP(vfcvt_f_xu_v, "vfcvt.f.xu.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
-OP(vfcvt_f_x_v, "vfcvt.f.x.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
-OP(vfcvt_rtz_xu_f_v, "vfcvt.rtz.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
-OP(vfcvt_rtz_x_f_v, "vfcvt.rtz.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
-OP(vfwcvt_xu_f_v, "vfwcvt.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
-OP(vfwcvt_x_f_v, "vfwcvt.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
-OP(vfwcvt_f_xu_v, "vfwcvt.f.xu.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
-OP(vfwcvt_f_x_v, "vfwcvt.f.x.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
-OP(vfwcvt_f_f_v, "vfwcvt.f.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
-OP(vfwcvt_rtz_xu_f_v, "vfwcvt.rtz.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
-OP(vfwcvt_rtz_x_f_v, "vfwcvt.rtz.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
-OP(vfncvt_xu_f_w, "vfncvt.xu.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm)
-OP(vfncvt_x_f_w, "vfncvt.x.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm)
-OP(vfncvt_f_xu_w, "vfncvt.f.xu.w", rv_codec_v_r, rv_fmt_vd_vs2_vm)
-OP(vfncvt_f_x_w, "vfncvt.f.x.w", rv_codec_v_r, rv_fmt_vd_vs2_vm)
-OP(vfncvt_f_f_w, "vfncvt.f.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm)
-OP(vfncvt_rod_f_f_w, "vfncvt.rod.f.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm)
-OP(vfncvt_rtz_xu_f_w, "vfncvt.rtz.xu.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm)
-OP(vfncvt_rtz_x_f_w, "vfncvt.rtz.x.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm)
-OP(vredsum_vs, "vredsum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
-OP(vredand_vs, "vredand.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
-OP(vredor_vs, "vredor.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
-OP(vredxor_vs, "vredxor.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
-OP(vredminu_vs, "vredminu.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
-OP(vredmin_vs, "vredmin.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
-OP(vredmaxu_vs, "vredmaxu.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
-OP(vredmax_vs, "vredmax.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
-OP(vwredsumu_vs, "vwredsumu.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
-OP(vwredsum_vs, "vwredsum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
-OP(vfredusum_vs, "vfredusum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
-OP(vfredosum_vs, "vfredosum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
-OP(vfredmin_vs, "vfredmin.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
-OP(vfredmax_vs, "vfredmax.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
-OP(vfwredusum_vs, "vfwredusum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
-OP(vfwredosum_vs, "vfwredosum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
-OP(vmand_mm, "vmand.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
-OP(vmnand_mm, "vmnand.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
-OP(vmandn_mm, "vmandn.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
-OP(vmxor_mm, "vmxor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
-OP(vmor_mm, "vmor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
-OP(vmnor_mm, "vmnor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
-OP(vmorn_mm, "vmorn.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
-OP(vmxnor_mm, "vmxnor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
-OP(vcpop_m, "vcpop.m", rv_codec_v_r, rv_fmt_rd_vs2_vm)
-OP(vfirst_m, "vfirst.m", rv_codec_v_r, rv_fmt_rd_vs2_vm)
-OP(vmsbf_m, "vmsbf.m", rv_codec_v_r, rv_fmt_vd_vs2_vm)
-OP(vmsif_m, "vmsif.m", rv_codec_v_r, rv_fmt_vd_vs2_vm)
-OP(vmsof_m, "vmsof.m", rv_codec_v_r, rv_fmt_vd_vs2_vm)
-OP(viota_m, "viota.m", rv_codec_v_r, rv_fmt_vd_vs2_vm)
-OP(vid_v, "vid.v", rv_codec_v_r, rv_fmt_vd_vm)
-OP(vmv_x_s, "vmv.x.s", rv_codec_v_r, rv_fmt_rd_vs2)
-OP(vmv_s_x, "vmv.s.x", rv_codec_v_r, rv_fmt_vd_rs1)
-OP(vfmv_f_s, "vfmv.f.s", rv_codec_v_r, rv_fmt_fd_vs2)
-OP(vfmv_s_f, "vfmv.s.f", rv_codec_v_r, rv_fmt_vd_fs1)
-OP(vslideup_vx, "vslideup.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
-OP(vslideup_vi, "vslideup.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm)
-OP(vslide1up_vx, "vslide1up.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
-OP(vslidedown_vx, "vslidedown.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
-OP(vslidedown_vi, "vslidedown.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm)
-OP(vslide1down_vx, "vslide1down.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
-OP(vrgather_vv, "vrgather.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
-OP(vrgatherei16_vv, "vrgatherei16.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
-OP(vrgather_vx, "vrgather.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
-OP(vrgather_vi, "vrgather.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm)
-OP(vcompress_vm, "vcompress.vm", rv_codec_v_r, rv_fmt_vd_vs2_vs1)
-OP(vmv1r_v, "vmv1r.v", rv_codec_v_r, rv_fmt_vd_vs2)
-OP(vmv2r_v, "vmv2r.v", rv_codec_v_r, rv_fmt_vd_vs2)
-OP(vmv4r_v, "vmv4r.v", rv_codec_v_r, rv_fmt_vd_vs2)
-OP(vmv8r_v, "vmv8r.v", rv_codec_v_r, rv_fmt_vd_vs2)
-OP(vzext_vf2, "vzext.vf2", rv_codec_v_r, rv_fmt_vd_vs2_vm)
-OP(vzext_vf4, "vzext.vf4", rv_codec_v_r, rv_fmt_vd_vs2_vm)
-OP(vzext_vf8, "vzext.vf8", rv_codec_v_r, rv_fmt_vd_vs2_vm)
-OP(vsext_vf2, "vsext.vf2", rv_codec_v_r, rv_fmt_vd_vs2_vm)
-OP(vsext_vf4, "vsext.vf4", rv_codec_v_r, rv_fmt_vd_vs2_vm)
-OP(vsext_vf8, "vsext.vf8", rv_codec_v_r, rv_fmt_vd_vs2_vm)
-OP(vsetvli, "vsetvli", rv_codec_vsetvli, rv_fmt_vsetvli)
-OP(vsetivli, "vsetivli", rv_codec_vsetivli, rv_fmt_vsetivli)
-OP(vsetvl, "vsetvl", rv_codec_r, rv_fmt_rd_rs1_rs2)
-OP(c_zext_b, "c.zext.b", rv_codec_zcb_ext, rv_fmt_rd)
-OP(c_sext_b, "c.sext.b", rv_codec_zcb_ext, rv_fmt_rd)
-OP(c_zext_h, "c.zext.h", rv_codec_zcb_ext, rv_fmt_rd)
-OP(c_sext_h, "c.sext.h", rv_codec_zcb_ext, rv_fmt_rd)
-OP(c_zext_w, "c.zext.w", rv_codec_zcb_ext, rv_fmt_rd)
-OP(c_not, "c.not", rv_codec_zcb_ext, rv_fmt_rd)
-OP(c_mul, "c.mul", rv_codec_zcb_mul, rv_fmt_rd_rs2)
-OP(c_lbu, "c.lbu", rv_codec_zcb_lb, rv_fmt_rs1_rs2_zce_ldst)
-OP(c_lhu, "c.lhu", rv_codec_zcb_lh, rv_fmt_rs1_rs2_zce_ldst)
-OP(c_lh, "c.lh", rv_codec_zcb_lh, rv_fmt_rs1_rs2_zce_ldst)
-OP(c_sb, "c.sb", rv_codec_zcb_lb, rv_fmt_rs1_rs2_zce_ldst)
-OP(c_sh, "c.sh", rv_codec_zcb_lh, rv_fmt_rs1_rs2_zce_ldst)
-OP(cm_push, "cm.push", rv_codec_zcmp_cm_pushpop, rv_fmt_push_rlist)
-OP(cm_pop, "cm.pop", rv_codec_zcmp_cm_pushpop, rv_fmt_pop_rlist)
-OP(cm_popret, "cm.popret", rv_codec_zcmp_cm_pushpop, rv_fmt_pop_rlist)
-OP(cm_popretz, "cm.popretz", rv_codec_zcmp_cm_pushpop, rv_fmt_pop_rlist)
-OP(cm_mva01s, "cm.mva01s", rv_codec_zcmp_cm_mv, rv_fmt_rd_rs2)
-OP(cm_mvsa01, "cm.mvsa01", rv_codec_zcmp_cm_mv, rv_fmt_rd_rs2)
-OP(cm_jt, "cm.jt", rv_codec_zcmt_jt, rv_fmt_zcmt_index)
-OP(cm_jalt, "cm.jalt", rv_codec_zcmt_jt, rv_fmt_zcmt_index)
-OP(czero_eqz, "czero.eqz", rv_codec_r, rv_fmt_rd_rs1_rs2)
-OP(czero_nez, "czero.nez", rv_codec_r, rv_fmt_rd_rs1_rs2)
-OP(fcvt_bf16_s, "fcvt.bf16.s", rv_codec_r_m, rv_fmt_rm_frd_frs1)
-OP(fcvt_s_bf16, "fcvt.s.bf16", rv_codec_r_m, rv_fmt_rm_frd_frs1)
-OP(vfncvtbf16_f_f_w, "vfncvtbf16.f.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm)
-OP(vfwcvtbf16_f_f_v, "vfwcvtbf16.f.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
-OP(vfwmaccbf16_vv, "vfwmaccbf16.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
-OP(vfwmaccbf16_vf, "vfwmaccbf16.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm)
-OP(flh, "flh", rv_codec_i, rv_fmt_frd_offset_rs1)
-OP(fsh, "fsh", rv_codec_s, rv_fmt_frs2_offset_rs1)
-OP(fmv_h_x, "fmv.h.x", rv_codec_r, rv_fmt_frd_rs1)
-OP(fmv_x_h, "fmv.x.h", rv_codec_r, rv_fmt_rd_frs1)
-OP(fli_s, "fli.s", rv_codec_fli, rv_fmt_fli)
-OP(fli_d, "fli.d", rv_codec_fli, rv_fmt_fli)
-OP(fli_q, "fli.q", rv_codec_fli, rv_fmt_fli)
-OP(fli_h, "fli.h", rv_codec_fli, rv_fmt_fli)
-OP(fminm_s, "fminm.s", rv_codec_r, rv_fmt_frd_frs1_frs2)
-OP(fmaxm_s, "fmaxm.s", rv_codec_r, rv_fmt_frd_frs1_frs2)
-OP(fminm_d, "fminm.d", rv_codec_r, rv_fmt_frd_frs1_frs2)
-OP(fmaxm_d, "fmaxm.d", rv_codec_r, rv_fmt_frd_frs1_frs2)
-OP(fminm_q, "fminm.q", rv_codec_r, rv_fmt_frd_frs1_frs2)
-OP(fmaxm_q, "fmaxm.q", rv_codec_r, rv_fmt_frd_frs1_frs2)
-OP(fminm_h, "fminm.h", rv_codec_r, rv_fmt_frd_frs1_frs2)
-OP(fmaxm_h, "fmaxm.h", rv_codec_r, rv_fmt_frd_frs1_frs2)
-OP(fround_s, "fround.s", rv_codec_r_m, rv_fmt_rm_frd_frs1)
-OP(froundnx_s, "froundnx.s", rv_codec_r_m, rv_fmt_rm_frd_frs1)
-OP(fround_d, "fround.d", rv_codec_r_m, rv_fmt_rm_frd_frs1)
-OP(froundnx_d, "froundnx.d", rv_codec_r_m, rv_fmt_rm_frd_frs1)
-OP(fround_q, "fround.q", rv_codec_r_m, rv_fmt_rm_frd_frs1)
-OP(froundnx_q, "froundnx.q", rv_codec_r_m, rv_fmt_rm_frd_frs1)
-OP(fround_h, "fround.h", rv_codec_r_m, rv_fmt_rm_frd_frs1)
-OP(froundnx_h, "froundnx.h", rv_codec_r_m, rv_fmt_rm_frd_frs1)
-OP(fcvtmod_w_d, "fcvtmod.w.d", rv_codec_r_m, rv_fmt_rm_rd_frs1)
-OP(fmvh_x_d, "fmvh.x.d", rv_codec_r, rv_fmt_rd_frs1)
-OP(fmvp_d_x, "fmvp.d.x", rv_codec_r, rv_fmt_frd_rs1_rs2)
-OP(fmvh_x_q, "fmvh.x.q", rv_codec_r, rv_fmt_rd_frs1)
-OP(fmvp_q_x, "fmvp.q.x", rv_codec_r, rv_fmt_frd_rs1_rs2)
-OP(fleq_s, "fleq.s", rv_codec_r, rv_fmt_rd_frs1_frs2)
-OP(fltq_s, "fltq.s", rv_codec_r, rv_fmt_rd_frs1_frs2)
-OP(fleq_d, "fleq.d", rv_codec_r, rv_fmt_rd_frs1_frs2)
-OP(fltq_d, "fltq.d", rv_codec_r, rv_fmt_rd_frs1_frs2)
-OP(fleq_q, "fleq.q", rv_codec_r, rv_fmt_rd_frs1_frs2)
-OP(fltq_q, "fltq.q", rv_codec_r, rv_fmt_rd_frs1_frs2)
-OP(fleq_h, "fleq.h", rv_codec_r, rv_fmt_rd_frs1_frs2)
-OP(fltq_h, "fltq.h", rv_codec_r, rv_fmt_rd_frs1_frs2)
-OP(vaesdf_vv, "vaesdf.vv", rv_codec_v_r, rv_fmt_vd_vs2)
-OP(vaesdf_vs, "vaesdf.vs", rv_codec_v_r, rv_fmt_vd_vs2)
-OP(vaesdm_vv, "vaesdm.vv", rv_codec_v_r, rv_fmt_vd_vs2)
-OP(vaesdm_vs, "vaesdm.vs", rv_codec_v_r, rv_fmt_vd_vs2)
-OP(vaesef_vv, "vaesef.vv", rv_codec_v_r, rv_fmt_vd_vs2)
-OP(vaesef_vs, "vaesef.vs", rv_codec_v_r, rv_fmt_vd_vs2)
-OP(vaesem_vv, "vaesem.vv", rv_codec_v_r, rv_fmt_vd_vs2)
-OP(vaesem_vs, "vaesem.vs", rv_codec_v_r, rv_fmt_vd_vs2)
-OP(vaeskf1_vi, "vaeskf1.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm)
-OP(vaeskf2_vi, "vaeskf2.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm)
-OP(vaesz_vs, "vaesz.vs", rv_codec_v_r, rv_fmt_vd_vs2)
-OP(vandn_vv, "vandn.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
-OP(vandn_vx, "vandn.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
-OP(vbrev_v, "vbrev.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
OP(vbrev8_v, "vbrev8.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
+OP(vbrev_v, "vbrev.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
OP(vclmul_vv, "vclmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
OP(vclmul_vx, "vclmul.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
OP(vclmulh_vv, "vclmulh.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
OP(vclmulh_vx, "vclmulh.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
OP(vclz_v, "vclz.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
+OP(vcompress_vm, "vcompress.vm", rv_codec_v_r, rv_fmt_vd_vs2_vs1)
+OP(vcpop_m, "vcpop.m", rv_codec_v_r, rv_fmt_rd_vs2_vm)
OP(vcpop_v, "vcpop.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
OP(vctz_v, "vctz.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
+OP(vdiv_vv, "vdiv.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vdiv_vx, "vdiv.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
+OP(vdivu_vv, "vdivu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vdivu_vx, "vdivu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
+OP(vfadd_vf, "vfadd.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
+OP(vfadd_vv, "vfadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vfclass_v, "vfclass.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
+OP(vfcvt_f_x_v, "vfcvt.f.x.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
+OP(vfcvt_f_xu_v, "vfcvt.f.xu.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
+OP(vfcvt_rtz_x_f_v, "vfcvt.rtz.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
+OP(vfcvt_rtz_xu_f_v, "vfcvt.rtz.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
+OP(vfcvt_x_f_v, "vfcvt.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
+OP(vfcvt_xu_f_v, "vfcvt.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
+OP(vfdiv_vf, "vfdiv.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
+OP(vfdiv_vv, "vfdiv.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vfirst_m, "vfirst.m", rv_codec_v_r, rv_fmt_rd_vs2_vm)
+OP(vfmacc_vf, "vfmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm)
+OP(vfmacc_vv, "vfmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
+OP(vfmadd_vf, "vfmadd.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm)
+OP(vfmadd_vv, "vfmadd.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
+OP(vfmax_vf, "vfmax.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
+OP(vfmax_vv, "vfmax.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vfmerge_vfm, "vfmerge.vfm", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vl)
+OP(vfmin_vf, "vfmin.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
+OP(vfmin_vv, "vfmin.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vfmsac_vf, "vfmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm)
+OP(vfmsac_vv, "vfmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
+OP(vfmsub_vf, "vfmsub.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm)
+OP(vfmsub_vv, "vfmsub.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
+OP(vfmul_vf, "vfmul.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
+OP(vfmul_vv, "vfmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vfmv_f_s, "vfmv.f.s", rv_codec_v_r, rv_fmt_fd_vs2)
+OP(vfmv_s_f, "vfmv.s.f", rv_codec_v_r, rv_fmt_vd_fs1)
+OP(vfmv_v_f, "vfmv.v.f", rv_codec_v_r, rv_fmt_vd_fs1)
+OP(vfncvt_f_f_w, "vfncvt.f.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm)
+OP(vfncvt_f_x_w, "vfncvt.f.x.w", rv_codec_v_r, rv_fmt_vd_vs2_vm)
+OP(vfncvt_f_xu_w, "vfncvt.f.xu.w", rv_codec_v_r, rv_fmt_vd_vs2_vm)
+OP(vfncvt_rod_f_f_w, "vfncvt.rod.f.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm)
+OP(vfncvt_rtz_x_f_w, "vfncvt.rtz.x.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm)
+OP(vfncvt_rtz_xu_f_w, "vfncvt.rtz.xu.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm)
+OP(vfncvt_x_f_w, "vfncvt.x.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm)
+OP(vfncvt_xu_f_w, "vfncvt.xu.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm)
+OP(vfncvtbf16_f_f_w, "vfncvtbf16.f.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm)
+OP(vfnmacc_vf, "vfnmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm)
+OP(vfnmacc_vv, "vfnmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
+OP(vfnmadd_vf, "vfnmadd.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm)
+OP(vfnmadd_vv, "vfnmadd.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
+OP(vfnmsac_vf, "vfnmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm)
+OP(vfnmsac_vv, "vfnmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
+OP(vfnmsub_vf, "vfnmsub.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm)
+OP(vfnmsub_vv, "vfnmsub.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
+OP(vfrdiv_vf, "vfrdiv.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
+OP(vfrec7_v, "vfrec7.v", rv_codec_v_r, rv_fmt_vd_vs2)
+OP(vfredmax_vs, "vfredmax.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vfredmin_vs, "vfredmin.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vfredosum_vs, "vfredosum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vfredusum_vs, "vfredusum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vfrsqrt7_v, "vfrsqrt7.v", rv_codec_v_r, rv_fmt_vd_vs2)
+OP(vfrsub_vf, "vfrsub.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
+OP(vfsgnj_vf, "vfsgnj.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
+OP(vfsgnj_vv, "vfsgnj.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vfsgnjn_vf, "vfsgnjn.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
+OP(vfsgnjn_vv, "vfsgnjn.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vfsgnjx_vf, "vfsgnjx.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
+OP(vfsgnjx_vv, "vfsgnjx.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vfslide1down_vf, "vfslide1down.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
+OP(vfslide1up_vf, "vfslide1up.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
+OP(vfsqrt_v, "vfsqrt.v", rv_codec_v_r, rv_fmt_vd_vs2)
+OP(vfsub_vf, "vfsub.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
+OP(vfsub_vv, "vfsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vfwadd_vf, "vfwadd.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
+OP(vfwadd_vv, "vfwadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vfwadd_wf, "vfwadd.wf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
+OP(vfwadd_wv, "vfwadd.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vfwcvt_f_f_v, "vfwcvt.f.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
+OP(vfwcvt_f_x_v, "vfwcvt.f.x.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
+OP(vfwcvt_f_xu_v, "vfwcvt.f.xu.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
+OP(vfwcvt_rtz_x_f_v, "vfwcvt.rtz.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
+OP(vfwcvt_rtz_xu_f_v, "vfwcvt.rtz.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
+OP(vfwcvt_x_f_v, "vfwcvt.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
+OP(vfwcvt_xu_f_v, "vfwcvt.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
+OP(vfwcvtbf16_f_f_v, "vfwcvtbf16.f.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
+OP(vfwmacc_vf, "vfwmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm)
+OP(vfwmacc_vv, "vfwmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
+OP(vfwmaccbf16_vf, "vfwmaccbf16.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm)
+OP(vfwmaccbf16_vv, "vfwmaccbf16.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
+OP(vfwmsac_vf, "vfwmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm)
+OP(vfwmsac_vv, "vfwmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
+OP(vfwmul_vf, "vfwmul.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
+OP(vfwmul_vv, "vfwmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vfwnmacc_vf, "vfwnmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm)
+OP(vfwnmacc_vv, "vfwnmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
+OP(vfwnmsac_vf, "vfwnmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm)
+OP(vfwnmsac_vv, "vfwnmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
+OP(vfwredosum_vs, "vfwredosum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vfwredusum_vs, "vfwredusum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vfwsub_vf, "vfwsub.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
+OP(vfwsub_vv, "vfwsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vfwsub_wf, "vfwsub.wf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
+OP(vfwsub_wv, "vfwsub.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
OP(vghsh_vv, "vghsh.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1)
OP(vgmul_vv, "vgmul.vv", rv_codec_v_r, rv_fmt_vd_vs2)
+OP(vid_v, "vid.v", rv_codec_v_r, rv_fmt_vd_vm)
+OP(viota_m, "viota.m", rv_codec_v_r, rv_fmt_vd_vs2_vm)
+OP(vl1re16_v, "vl1re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
+OP(vl1re32_v, "vl1re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
+OP(vl1re64_v, "vl1re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
+OP(vl1re8_v, "vl1re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
+OP(vl2re16_v, "vl2re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
+OP(vl2re32_v, "vl2re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
+OP(vl2re64_v, "vl2re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
+OP(vl2re8_v, "vl2re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
+OP(vl4re16_v, "vl4re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
+OP(vl4re32_v, "vl4re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
+OP(vl4re64_v, "vl4re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
+OP(vl4re8_v, "vl4re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
+OP(vl8re16_v, "vl8re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
+OP(vl8re32_v, "vl8re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
+OP(vl8re64_v, "vl8re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
+OP(vl8re8_v, "vl8re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
+OP(vle16_v, "vle16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
+OP(vle16ff_v, "vle16ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
+OP(vle32_v, "vle32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
+OP(vle32ff_v, "vle32ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
+OP(vle64_v, "vle64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
+OP(vle64ff_v, "vle64ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
+OP(vle8_v, "vle8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
+OP(vle8ff_v, "vle8ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
+OP(vlm_v, "vlm.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
+OP(vloxei16_v, "vloxei16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm)
+OP(vloxei32_v, "vloxei32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm)
+OP(vloxei64_v, "vloxei64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm)
+OP(vloxei8_v, "vloxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm)
+OP(vlse16_v, "vlse16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm)
+OP(vlse32_v, "vlse32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm)
+OP(vlse64_v, "vlse64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm)
+OP(vlse8_v, "vlse8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm)
+OP(vluxei16_v, "vluxei16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm)
+OP(vluxei32_v, "vluxei32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm)
+OP(vluxei64_v, "vluxei64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm)
+OP(vluxei8_v, "vluxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm)
+OP(vmacc_vv, "vmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
+OP(vmacc_vx, "vmacc.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm)
+OP(vmadc_vim, "vmadc.vim", rv_codec_v_i, rv_fmt_vd_vs2_imm_vl)
+OP(vmadc_vvm, "vmadc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl)
+OP(vmadc_vxm, "vmadc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl)
+OP(vmadd_vv, "vmadd.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
+OP(vmadd_vx, "vmadd.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm)
+OP(vmand_mm, "vmand.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vmandn_mm, "vmandn.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vmax_vv, "vmax.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vmax_vx, "vmax.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
+OP(vmaxu_vv, "vmaxu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vmaxu_vx, "vmaxu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
+OP(vmerge_vim, "vmerge.vim", rv_codec_v_i, rv_fmt_vd_vs2_imm_vl)
+OP(vmerge_vvm, "vmerge.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl)
+OP(vmerge_vxm, "vmerge.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl)
+OP(vmfeq_vf, "vmfeq.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
+OP(vmfeq_vv, "vmfeq.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vmfge_vf, "vmfge.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
+OP(vmfgt_vf, "vmfgt.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
+OP(vmfle_vf, "vmfle.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
+OP(vmfle_vv, "vmfle.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vmflt_vf, "vmflt.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
+OP(vmflt_vv, "vmflt.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vmfne_vf, "vmfne.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
+OP(vmfne_vv, "vmfne.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vmin_vv, "vmin.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vmin_vx, "vmin.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
+OP(vminu_vv, "vminu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vminu_vx, "vminu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
+OP(vmnand_mm, "vmnand.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vmnor_mm, "vmnor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vmor_mm, "vmor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vmorn_mm, "vmorn.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vmsbc_vvm, "vmsbc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl)
+OP(vmsbc_vxm, "vmsbc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl)
+OP(vmsbf_m, "vmsbf.m", rv_codec_v_r, rv_fmt_vd_vs2_vm)
+OP(vmseq_vi, "vmseq.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm)
+OP(vmseq_vv, "vmseq.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vmseq_vx, "vmseq.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
+OP(vmsgt_vi, "vmsgt.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm)
+OP(vmsgt_vx, "vmsgt.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
+OP(vmsgtu_vi, "vmsgtu.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm)
+OP(vmsgtu_vx, "vmsgtu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
+OP(vmsif_m, "vmsif.m", rv_codec_v_r, rv_fmt_vd_vs2_vm)
+OP(vmsle_vi, "vmsle.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm)
+OP(vmsle_vv, "vmsle.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vmsle_vx, "vmsle.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
+OP(vmsleu_vi, "vmsleu.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm)
+OP(vmsleu_vv, "vmsleu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vmsleu_vx, "vmsleu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
+OP(vmslt_vv, "vmslt.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vmslt_vx, "vmslt.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
+OP(vmsltu_vv, "vmsltu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vmsltu_vx, "vmsltu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
+OP(vmsne_vi, "vmsne.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm)
+OP(vmsne_vv, "vmsne.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vmsne_vx, "vmsne.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
+OP(vmsof_m, "vmsof.m", rv_codec_v_r, rv_fmt_vd_vs2_vm)
+OP(vmul_vv, "vmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vmul_vx, "vmul.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
+OP(vmulh_vv, "vmulh.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vmulh_vx, "vmulh.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
+OP(vmulhsu_vv, "vmulhsu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vmulhsu_vx, "vmulhsu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
+OP(vmulhu_vv, "vmulhu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vmulhu_vx, "vmulhu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
+OP(vmv1r_v, "vmv1r.v", rv_codec_v_r, rv_fmt_vd_vs2)
+OP(vmv2r_v, "vmv2r.v", rv_codec_v_r, rv_fmt_vd_vs2)
+OP(vmv4r_v, "vmv4r.v", rv_codec_v_r, rv_fmt_vd_vs2)
+OP(vmv8r_v, "vmv8r.v", rv_codec_v_r, rv_fmt_vd_vs2)
+OP(vmv_s_x, "vmv.s.x", rv_codec_v_r, rv_fmt_vd_rs1)
+OP(vmv_v_i, "vmv.v.i", rv_codec_v_i, rv_fmt_vd_imm)
+OP(vmv_v_v, "vmv.v.v", rv_codec_v_r, rv_fmt_vd_vs1)
+OP(vmv_v_x, "vmv.v.x", rv_codec_v_r, rv_fmt_vd_rs1)
+OP(vmv_x_s, "vmv.x.s", rv_codec_v_r, rv_fmt_rd_vs2)
+OP(vmxnor_mm, "vmxnor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vmxor_mm, "vmxor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vnclip_wi, "vnclip.wi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm)
+OP(vnclip_wv, "vnclip.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vnclip_wx, "vnclip.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
+OP(vnclipu_wi, "vnclipu.wi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm)
+OP(vnclipu_wv, "vnclipu.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vnclipu_wx, "vnclipu.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
+OP(vnmsac_vv, "vnmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
+OP(vnmsac_vx, "vnmsac.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm)
+OP(vnmsub_vv, "vnmsub.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
+OP(vnmsub_vx, "vnmsub.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm)
+OP(vnsra_wi, "vnsra.wi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm)
+OP(vnsra_wv, "vnsra.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vnsra_wx, "vnsra.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
+OP(vnsrl_wi, "vnsrl.wi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm)
+OP(vnsrl_wv, "vnsrl.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vnsrl_wx, "vnsrl.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
+OP(vor_vi, "vor.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm)
+OP(vor_vv, "vor.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vor_vx, "vor.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
+OP(vredand_vs, "vredand.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vredmax_vs, "vredmax.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vredmaxu_vs, "vredmaxu.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vredmin_vs, "vredmin.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vredminu_vs, "vredminu.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vredor_vs, "vredor.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vredsum_vs, "vredsum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vredxor_vs, "vredxor.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vrem_vv, "vrem.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vrem_vx, "vrem.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
+OP(vremu_vv, "vremu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vremu_vx, "vremu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
OP(vrev8_v, "vrev8.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
+OP(vrgather_vi, "vrgather.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm)
+OP(vrgather_vv, "vrgather.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vrgather_vx, "vrgather.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
+OP(vrgatherei16_vv, "vrgatherei16.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
OP(vrol_vv, "vrol.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
OP(vrol_vx, "vrol.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
+OP(vror_vi, "vror.vi", rv_codec_vror_vi, rv_fmt_vd_vs2_uimm_vm)
OP(vror_vv, "vror.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
OP(vror_vx, "vror.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
-OP(vror_vi, "vror.vi", rv_codec_vror_vi, rv_fmt_vd_vs2_uimm_vm)
+OP(vrsub_vi, "vrsub.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm)
+OP(vrsub_vx, "vrsub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
+OP(vs1r_v, "vs1r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
+OP(vs2r_v, "vs2r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
+OP(vs4r_v, "vs4r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
+OP(vs8r_v, "vs8r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
+OP(vsadd_vi, "vsadd.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm)
+OP(vsadd_vv, "vsadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vsadd_vx, "vsadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
+OP(vsaddu_vi, "vsaddu.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm)
+OP(vsaddu_vv, "vsaddu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vsaddu_vx, "vsaddu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
+OP(vsbc_vvm, "vsbc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl)
+OP(vsbc_vxm, "vsbc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl)
+OP(vse16_v, "vse16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
+OP(vse32_v, "vse32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
+OP(vse64_v, "vse64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
+OP(vse8_v, "vse8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
+OP(vsetivli, "vsetivli", rv_codec_vsetivli, rv_fmt_vsetivli)
+OP(vsetvl, "vsetvl", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(vsetvli, "vsetvli", rv_codec_vsetvli, rv_fmt_vsetvli)
+OP(vsext_vf2, "vsext.vf2", rv_codec_v_r, rv_fmt_vd_vs2_vm)
+OP(vsext_vf4, "vsext.vf4", rv_codec_v_r, rv_fmt_vd_vs2_vm)
+OP(vsext_vf8, "vsext.vf8", rv_codec_v_r, rv_fmt_vd_vs2_vm)
OP(vsha2ch_vv, "vsha2ch.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1)
OP(vsha2cl_vv, "vsha2cl.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1)
OP(vsha2ms_vv, "vsha2ms.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1)
+OP(vslide1down_vx, "vslide1down.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
+OP(vslide1up_vx, "vslide1up.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
+OP(vslidedown_vi, "vslidedown.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm)
+OP(vslidedown_vx, "vslidedown.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
+OP(vslideup_vi, "vslideup.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm)
+OP(vslideup_vx, "vslideup.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
+OP(vsll_vi, "vsll.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm)
+OP(vsll_vv, "vsll.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vsll_vx, "vsll.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
OP(vsm3c_vi, "vsm3c.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm)
OP(vsm3me_vv, "vsm3me.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1)
OP(vsm4k_vi, "vsm4k.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm)
-OP(vsm4r_vv, "vsm4r.vv", rv_codec_v_r, rv_fmt_vd_vs2)
OP(vsm4r_vs, "vsm4r.vs", rv_codec_v_r, rv_fmt_vd_vs2)
+OP(vsm4r_vv, "vsm4r.vv", rv_codec_v_r, rv_fmt_vd_vs2)
+OP(vsm_v, "vsm.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
+OP(vsmul_vv, "vsmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vsmul_vx, "vsmul.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
+OP(vsoxei16_v, "vsoxei16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm)
+OP(vsoxei32_v, "vsoxei32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm)
+OP(vsoxei64_v, "vsoxei64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm)
+OP(vsoxei8_v, "vsoxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm)
+OP(vsra_vi, "vsra.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm)
+OP(vsra_vv, "vsra.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vsra_vx, "vsra.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
+OP(vsrl_vi, "vsrl.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm)
+OP(vsrl_vv, "vsrl.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vsrl_vx, "vsrl.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
+OP(vsse16_v, "vsse16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm)
+OP(vsse32_v, "vsse32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm)
+OP(vsse64_v, "vsse64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm)
+OP(vsse8_v, "vsse8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm)
+OP(vssra_vi, "vssra.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm)
+OP(vssra_vv, "vssra.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vssra_vx, "vssra.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
+OP(vssrl_vi, "vssrl.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm)
+OP(vssrl_vv, "vssrl.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vssrl_vx, "vssrl.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
+OP(vssub_vv, "vssub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vssub_vx, "vssub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
+OP(vssubu_vv, "vssubu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vssubu_vx, "vssubu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
+OP(vsub_vv, "vsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vsub_vx, "vsub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
+OP(vsuxei16_v, "vsuxei16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm)
+OP(vsuxei32_v, "vsuxei32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm)
+OP(vsuxei64_v, "vsuxei64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm)
+OP(vsuxei8_v, "vsuxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm)
+OP(vwadd_vv, "vwadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vwadd_vx, "vwadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
+OP(vwadd_wv, "vwadd.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vwadd_wx, "vwadd.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
+OP(vwaddu_vv, "vwaddu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vwaddu_vx, "vwaddu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
+OP(vwaddu_wv, "vwaddu.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vwaddu_wx, "vwaddu.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
+OP(vwmacc_vv, "vwmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
+OP(vwmacc_vx, "vwmacc.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm)
+OP(vwmaccsu_vv, "vwmaccsu.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
+OP(vwmaccsu_vx, "vwmaccsu.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm)
+OP(vwmaccu_vv, "vwmaccu.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
+OP(vwmaccu_vx, "vwmaccu.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm)
+OP(vwmaccus_vx, "vwmaccus.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm)
+OP(vwmul_vv, "vwmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vwmul_vx, "vwmul.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
+OP(vwmulsu_vv, "vwmulsu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vwmulsu_vx, "vwmulsu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
+OP(vwmulu_vv, "vwmulu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vwmulu_vx, "vwmulu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
+OP(vwredsum_vs, "vwredsum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vwredsumu_vs, "vwredsumu.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vwsll_vi, "vwsll.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm)
OP(vwsll_vv, "vwsll.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
OP(vwsll_vx, "vwsll.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
-OP(vwsll_vi, "vwsll.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm)
-OP(amocas_w, "amocas.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
-OP(amocas_d, "amocas.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
-OP(amocas_q, "amocas.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
-OP(mop_r, "mop.r", rv_codec_mop_r, rv_fmt_mop_r)
-OP(mop_rr, "mop.rr", rv_codec_mop_rr, rv_fmt_mop_rr)
-OP(c_mop, "c.mop", rv_codec_cmop, rv_fmt_cmop)
-OP(amoswap_b, "amoswap.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
-OP(amoadd_b, "amoadd.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
-OP(amoxor_b, "amoxor.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
-OP(amoor_b, "amoor.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
-OP(amoand_b, "amoand.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
-OP(amomin_b, "amomin.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
-OP(amomax_b, "amomax.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
-OP(amominu_b, "amominu.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
-OP(amomaxu_b, "amomaxu.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
-OP(amoswap_h, "amoswap.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
-OP(amoadd_h, "amoadd.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
-OP(amoxor_h, "amoxor.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
-OP(amoor_h, "amoor.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
-OP(amoand_h, "amoand.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
-OP(amomin_h, "amomin.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
-OP(amomax_h, "amomax.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
-OP(amominu_h, "amominu.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
-OP(amomaxu_h, "amomaxu.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
-OP(amocas_b, "amocas.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
-OP(amocas_h, "amocas.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
-OP(wrs_sto, "wrs.sto", rv_codec_none, rv_fmt_none)
+OP(vwsub_vv, "vwsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vwsub_vx, "vwsub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
+OP(vwsub_wv, "vwsub.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vwsub_wx, "vwsub.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
+OP(vwsubu_vv, "vwsubu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vwsubu_vx, "vwsubu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
+OP(vwsubu_wv, "vwsubu.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vwsubu_wx, "vwsubu.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
+OP(vxor_vi, "vxor.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm)
+OP(vxor_vv, "vxor.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
+OP(vxor_vx, "vxor.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
+OP(vzext_vf2, "vzext.vf2", rv_codec_v_r, rv_fmt_vd_vs2_vm)
+OP(vzext_vf4, "vzext.vf4", rv_codec_v_r, rv_fmt_vd_vs2_vm)
+OP(vzext_vf8, "vzext.vf8", rv_codec_v_r, rv_fmt_vd_vs2_vm)
+OP(wfi, "wfi", rv_codec_none, rv_fmt_none)
OP(wrs_nto, "wrs.nto", rv_codec_none, rv_fmt_none)
-OP(lpad, "lpad", rv_codec_lp, rv_fmt_imm)
-OP(sspush, "sspush", rv_codec_r, rv_fmt_rs2)
-OP(sspopchk, "sspopchk", rv_codec_r, rv_fmt_rs1)
-OP(ssrdp, "ssrdp", rv_codec_r, rv_fmt_rd)
-OP(ssamoswap_w, "ssamoswap.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
-OP(ssamoswap_d, "ssamoswap.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
-OP(c_sspush, "c.sspush", rv_codec_cmop_ss, NULL, DECOMP(op_sspush))
-OP(c_sspopchk, "c.sspopchk", rv_codec_cmop_ss, NULL, DECOMP(op_sspopchk))
-OP(cbo_inval, "cbo.inval", rv_codec_r, rv_fmt_rs1)
-OP(cbo_clean, "cbo.clean", rv_codec_r, rv_fmt_rs1)
-OP(cbo_flush, "cbo.flush", rv_codec_r, rv_fmt_rs1)
-OP(cbo_zero, "cbo.zero", rv_codec_r, rv_fmt_rs1)
-OP(mnret, "mnret", rv_codec_none, rv_fmt_none)
+OP(wrs_sto, "wrs.sto", rv_codec_none, rv_fmt_none)
+OP(xnor, "xnor", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(xor, "xor", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(xori, "xori", rv_codec_i, rv_fmt_rd_rs1_imm, rvcp_xori)
+OP(xperm4, "xperm4", rv_codec_r, rv_fmt_rd_rs1_rs2)
+OP(xperm8, "xperm8", rv_codec_r, rv_fmt_rd_rs1)
+OP(zext_h, "zext.h", rv_codec_r, rv_fmt_rd_rs1)
+OP(zip, "zip", rv_codec_r, rv_fmt_rd_rs1)
--
2.43.0
^ permalink raw reply related [flat|nested] 119+ messages in thread
* Re: [PATCH 03/56] disas/riscv: Use signed type for vector immediates
2026-08-09 22:34 ` [PATCH 03/56] disas/riscv: Use signed type for vector immediates Richard Henderson
@ 2026-08-10 2:53 ` Philippe Mathieu-Daudé
2026-08-11 19:56 ` Alistair
1 sibling, 0 replies; 119+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-08-10 2:53 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: qemu-riscv, TANG Tiancheng, LIU Zhiwei
On 10/8/26 00:34, Richard Henderson wrote:
> From: TANG Tiancheng <lyndra@linux.alibaba.com>
>
> operand_vimm() sign-extends the 5-bit vector immediate field in bits
> 19:15, but returns uint32_t. This sends negative immediates through an
> unsigned type before they are assigned to rv_decode.imm.
>
> Return int32_t to match the signed value extracted by the helper.
>
> Signed-off-by: TANG Tiancheng <lyndra@linux.alibaba.com>
> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
(Missing your S-o-b)
Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
> Message-Id: <20260703-b4-disas-xthead-fix-riscv-next-v4-3-84c566330bc7@linux.alibaba.com>
> ---
> disas/riscv.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
^ permalink raw reply [flat|nested] 119+ messages in thread
* Re: [PATCH 07/56] disas/riscv: Reduce rv_insn to uint32_t
2026-08-09 22:34 ` [PATCH 07/56] disas/riscv: Reduce rv_insn to uint32_t Richard Henderson
@ 2026-08-10 2:54 ` Philippe Mathieu-Daudé
2026-08-11 19:59 ` Alistair
1 sibling, 0 replies; 119+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-08-10 2:54 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: qemu-riscv
On 10/8/26 00:34, Richard Henderson wrote:
> Since 758dce9c98a, the only possible values for
> instruction length are 2 and 4.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> disas/riscv.h | 2 +-
> disas/riscv.c | 12 +++---------
> 2 files changed, 4 insertions(+), 10 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
^ permalink raw reply [flat|nested] 119+ messages in thread
* Re: [PATCH 08/56] disas/riscv: Tidy dec initialization in disasm_inst
2026-08-09 22:34 ` [PATCH 08/56] disas/riscv: Tidy dec initialization in disasm_inst Richard Henderson
@ 2026-08-10 2:54 ` Philippe Mathieu-Daudé
2026-08-11 20:00 ` Alistair
1 sibling, 0 replies; 119+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-08-10 2:54 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: qemu-riscv
On 10/8/26 00:34, Richard Henderson wrote:
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> disas/riscv.c | 9 +++++----
> 1 file changed, 5 insertions(+), 4 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
^ permalink raw reply [flat|nested] 119+ messages in thread
* Re: [PATCH 16/56] disas/riscv: Drop useless const in structures
2026-08-09 22:35 ` [PATCH 16/56] disas/riscv: Drop useless const in structures Richard Henderson
@ 2026-08-10 2:55 ` Philippe Mathieu-Daudé
2026-08-11 20:10 ` Alistair
1 sibling, 0 replies; 119+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-08-10 2:55 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: qemu-riscv
On 10/8/26 00:35, Richard Henderson wrote:
> Individual fields should not be const, only full structures.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> disas/riscv.h | 16 ++++++++--------
> 1 file changed, 8 insertions(+), 8 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
^ permalink raw reply [flat|nested] 119+ messages in thread
* Re: [PATCH 26/56] disas/riscv: Drop always true branch psudeos
2026-08-09 22:35 ` [PATCH 26/56] disas/riscv: Drop always true branch psudeos Richard Henderson
@ 2026-08-10 2:58 ` Philippe Mathieu-Daudé
2026-08-11 20:19 ` Alistair
1 sibling, 0 replies; 119+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-08-10 2:58 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: qemu-riscv
On 10/8/26 00:35, Richard Henderson wrote:
> The real insns are blt, bge, bltu, bgeu. Do not include
> psuedos that unconditionally swap operands. That's fine
Typo "pseudos" (also in $subject), otherwise:
Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
> for an assembler but not a disassembler.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> disas/riscv.c | 32 ++++++--------------------------
> 1 file changed, 6 insertions(+), 26 deletions(-)
^ permalink raw reply [flat|nested] 119+ messages in thread
* Re: [PATCH 56/56] disas/riscv: Sort riscv-op.c.inc
2026-08-09 22:35 ` [PATCH 56/56] disas/riscv: Sort riscv-op.c.inc Richard Henderson
@ 2026-08-10 2:59 ` Philippe Mathieu-Daudé
2026-08-12 13:03 ` Alistair
1 sibling, 0 replies; 119+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-08-10 2:59 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: qemu-riscv
On 10/8/26 00:35, Richard Henderson wrote:
> To date, opcodes had to be added to the end of the list,
> resulting in quite the disorder. Sort via 'LANG=C sort'.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> disas/riscv-op.c.inc | 1704 +++++++++++++++++++++---------------------
> 1 file changed, 852 insertions(+), 852 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
^ permalink raw reply [flat|nested] 119+ messages in thread
* Re: [PATCH 01/56] disas/riscv: Fix th.srri decoding
2026-08-09 22:34 ` [PATCH 01/56] disas/riscv: Fix th.srri decoding Richard Henderson
@ 2026-08-11 19:54 ` Alistair
0 siblings, 0 replies; 119+ messages in thread
From: Alistair @ 2026-08-11 19:54 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
Cc: qemu-riscv, TANG Tiancheng, LIU Zhiwei, Daniel Henrique Barboza
On Sun, 2026-08-09 at 15:34 -0700, Richard Henderson wrote:
> From: TANG Tiancheng <lyndra@linux.alibaba.com>
>
> target/riscv/xthead.decode defines th.srri as funct6=000100 in
> bits 31:26, with the 6-bit immediate in bits 25:20.
>
> decode_xtheadbb() switches on bits 31:25, i.e. funct6 plus imm[5].
> Therefore valid th.srri encodings are 0001000 and 0001001. The
> current 0000100 and 0000101 cases use the wrong funct6 value and
> decode valid th.srri instructions as illegal.
>
> Fix the cases to match funct6=000100 with both imm[5] values.
>
> Fixes: 318df7238b9f ("disas/riscv: Add support for XThead*
> instructions")
> Signed-off-by: TANG Tiancheng <lyndra@linux.alibaba.com>
> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
> Reviewed-by: Daniel Henrique Barboza
> <daniel.barboza@oss.qualcomm.com>
> Message-Id:
> <20260703-b4-disas-xthead-fix-riscv-next-v4-1-84c566330bc7@linux.alib
> aba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> disas/riscv-xthead.c | 6 ++++--
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/disas/riscv-xthead.c b/disas/riscv-xthead.c
> index fcca326d1c..2f2ddb8dd9 100644
> --- a/disas/riscv-xthead.c
> +++ b/disas/riscv-xthead.c
> @@ -315,8 +315,10 @@ void decode_xtheadbb(rv_decode *dec, rv_isa isa)
> op = rv_op_th_revw;
> }
> break;
> - case 0b0000100:
> - case 0b0000101: op = rv_op_th_srri; break;
> + case 0b0001000:
> + case 0b0001001:
> + op = rv_op_th_srri;
> + break;
> }
> break;
> case 2: op = rv_op_th_ext; break;
^ permalink raw reply [flat|nested] 119+ messages in thread
* Re: [PATCH 02/56] disas/riscv: Fix 6-bit immediate extraction
2026-08-09 22:34 ` [PATCH 02/56] disas/riscv: Fix 6-bit immediate extraction Richard Henderson
@ 2026-08-11 19:55 ` Alistair
0 siblings, 0 replies; 119+ messages in thread
From: Alistair @ 2026-08-11 19:55 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
Cc: qemu-riscv, TANG Tiancheng, Alex Bennée, LIU Zhiwei,
Daniel Henrique Barboza
On Sun, 2026-08-09 at 15:34 -0700, Richard Henderson wrote:
> From: TANG Tiancheng <lyndra@linux.alibaba.com>
>
> rv_codec_r2_imm6 is used for XThead instructions whose 6-bit
> immediate field is encoded in bits 25:20. The old expression
> left-shifted by 38 and then right-shifted by 60, so it kept only
> bits 25:22.
>
> Use extract32() to decode bits 25:20 directly. This fixes the
> immediate printed for th.srri and th.tst.
>
> Fixes: 318df7238b9f ("disas/riscv: Add support for XThead*
> instructions")
> Suggested-by: Alex Bennée <alex.bennee@linaro.org>
> Signed-off-by: TANG Tiancheng <lyndra@linux.alibaba.com>
> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
> Reviewed-by: Daniel Henrique Barboza
> <daniel.barboza@oss.qualcomm.com>
> Message-Id:
> <20260703-b4-disas-xthead-fix-riscv-next-v4-2-84c566330bc7@linux.alib
> aba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> disas/riscv.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/disas/riscv.c b/disas/riscv.c
> index 7f1b262773..fdf75a12ef 100644
> --- a/disas/riscv.c
> +++ b/disas/riscv.c
> @@ -4546,7 +4546,7 @@ static uint32_t operand_zcmp_rlist(rv_inst
> inst)
>
> static uint32_t operand_imm6(rv_inst inst)
> {
> - return (inst << 38) >> 60;
> + return extract32(inst, 20, 6);
> }
>
> static uint32_t operand_imm2(rv_inst inst)
^ permalink raw reply [flat|nested] 119+ messages in thread
* Re: [PATCH 03/56] disas/riscv: Use signed type for vector immediates
2026-08-09 22:34 ` [PATCH 03/56] disas/riscv: Use signed type for vector immediates Richard Henderson
2026-08-10 2:53 ` Philippe Mathieu-Daudé
@ 2026-08-11 19:56 ` Alistair
1 sibling, 0 replies; 119+ messages in thread
From: Alistair @ 2026-08-11 19:56 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: qemu-riscv, TANG Tiancheng, LIU Zhiwei
On Sun, 2026-08-09 at 15:34 -0700, Richard Henderson wrote:
> From: TANG Tiancheng <lyndra@linux.alibaba.com>
>
> operand_vimm() sign-extends the 5-bit vector immediate field in bits
> 19:15, but returns uint32_t. This sends negative immediates through
> an
> unsigned type before they are assigned to rv_decode.imm.
>
> Return int32_t to match the signed value extracted by the helper.
>
> Signed-off-by: TANG Tiancheng <lyndra@linux.alibaba.com>
> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
> Message-Id:
> <20260703-b4-disas-xthead-fix-riscv-next-v4-3-84c566330bc7@linux.alib
> aba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> disas/riscv.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/disas/riscv.c b/disas/riscv.c
> index fdf75a12ef..967739bdbb 100644
> --- a/disas/riscv.c
> +++ b/disas/riscv.c
> @@ -4487,7 +4487,7 @@ static uint32_t operand_cimmq(rv_inst inst)
> ((inst << 57) >> 62) << 6;
> }
>
> -static uint32_t operand_vimm(rv_inst inst)
> +static int32_t operand_vimm(rv_inst inst)
> {
> return (int64_t)(inst << 44) >> 59;
> }
^ permalink raw reply [flat|nested] 119+ messages in thread
* Re: [PATCH 04/56] disas/riscv: Decode unsigned vector immediates as unsigned
2026-08-09 22:34 ` [PATCH 04/56] disas/riscv: Decode unsigned vector immediates as unsigned Richard Henderson
@ 2026-08-11 19:57 ` Alistair
0 siblings, 0 replies; 119+ messages in thread
From: Alistair @ 2026-08-11 19:57 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: qemu-riscv, TANG Tiancheng, LIU Zhiwei
On Sun, 2026-08-09 at 15:34 -0700, Richard Henderson wrote:
> From: TANG Tiancheng <lyndra@linux.alibaba.com>
>
> rv_codec_v_i decodes all .vi operands with operand_vimm(), which
> sign-extends bits 19:15. That matches spec operands named imm, but
> not the
> .vi forms whose operand is uimm; uimm=31 is decoded as -1 and printed
> by
> the shared 6-bit 'u' formatter as 63.
>
> Add rv_codec_v_i_u/operand_vuimm() for the 5-bit uimm forms: vsll.vi,
> vsrl.vi, vsra.vi, vnsrl.wi, vnsra.wi, vssrl.vi, vssra.vi, vnclipu.wi,
> vnclip.wi, vslideup.vi, vslidedown.vi, vrgather.vi, vaeskf1.vi,
> vaeskf2.vi, vsm3c.vi, vsm4k.vi and vwsll.vi. The remaining
> rv_codec_v_i
> entries are the signed imm forms.
>
> Fixes: 07f4964d1785 ("disas/riscv.c: rvv: Add disas support for
> vector instructions")
> Fixes: 9d92f56d4a44 ("disas/riscv: Add support for vector crypto
> extensions")
> Signed-off-by: TANG Tiancheng <lyndra@linux.alibaba.com>
> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
> Message-Id:
> <20260703-b4-disas-xthead-fix-riscv-next-v4-4-84c566330bc7@linux.alib
> aba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> disas/riscv.h | 1 +
> disas/riscv.c | 45 ++++++++++++++++++++++++++++-----------------
> 2 files changed, 29 insertions(+), 17 deletions(-)
>
> diff --git a/disas/riscv.h b/disas/riscv.h
> index 379e642ec8..91ada8b531 100644
> --- a/disas/riscv.h
> +++ b/disas/riscv.h
> @@ -149,6 +149,7 @@ typedef enum {
> rv_codec_v_r,
> rv_codec_v_ldst,
> rv_codec_v_i,
> + rv_codec_v_i_u,
> rv_codec_vsetvli,
> rv_codec_vsetivli,
> rv_codec_vror_vi,
> diff --git a/disas/riscv.c b/disas/riscv.c
> index 967739bdbb..82b962dc71 100644
> --- a/disas/riscv.c
> +++ b/disas/riscv.c
> @@ -1803,19 +1803,19 @@ const rv_opcode_data rvi_opcode_data[] = {
> { "vxor.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0
> },
> { "vsll.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0
> },
> { "vsll.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0
> },
> - { "vsll.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0
> },
> + { "vsll.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0,
> 0 },
> { "vsrl.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0
> },
> { "vsrl.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0
> },
> - { "vsrl.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0
> },
> + { "vsrl.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0,
> 0 },
> { "vsra.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0
> },
> { "vsra.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0
> },
> - { "vsra.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0
> },
> + { "vsra.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0,
> 0 },
> { "vnsrl.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0
> },
> { "vnsrl.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0
> },
> - { "vnsrl.wi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0
> },
> + { "vnsrl.wi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0,
> 0 },
> { "vnsra.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0
> },
> { "vnsra.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0
> },
> - { "vnsra.wi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0
> },
> + { "vnsra.wi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0,
> 0 },
> { "vmseq.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0
> },
> { "vmseq.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0
> },
> { "vmseq.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0
> },
> @@ -1909,16 +1909,16 @@ const rv_opcode_data rvi_opcode_data[] = {
> { "vsmul.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0
> },
> { "vssrl.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0
> },
> { "vssrl.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0
> },
> - { "vssrl.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0
> },
> + { "vssrl.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0,
> 0 },
> { "vssra.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0
> },
> { "vssra.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0
> },
> - { "vssra.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0
> },
> + { "vssra.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0,
> 0 },
> { "vnclipu.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0,
> 0 },
> { "vnclipu.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0,
> 0 },
> - { "vnclipu.wi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0,
> 0 },
> + { "vnclipu.wi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm, NULL, 0,
> 0, 0 },
> { "vnclip.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0
> },
> { "vnclip.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0
> },
> - { "vnclip.wi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0,
> 0 },
> + { "vnclip.wi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm, NULL, 0,
> 0, 0 },
> { "vfadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0
> },
> { "vfadd.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0
> },
> { "vfsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0
> },
> @@ -2048,15 +2048,15 @@ const rv_opcode_data rvi_opcode_data[] = {
> { "vfmv.f.s", rv_codec_v_r, rv_fmt_fd_vs2, NULL, 0, 0, 0 },
> { "vfmv.s.f", rv_codec_v_r, rv_fmt_vd_fs1, NULL, 0, 0, 0 },
> { "vslideup.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0,
> 0 },
> - { "vslideup.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0,
> 0, 0 },
> + { "vslideup.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm, NULL, 0,
> 0, 0 },
> { "vslide1up.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0,
> 0, 0 },
> { "vslidedown.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0,
> 0, 0 },
> - { "vslidedown.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0,
> 0, 0 },
> + { "vslidedown.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm, NULL,
> 0, 0, 0 },
> { "vslide1down.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0,
> 0, 0 },
> { "vrgather.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0,
> 0 },
> { "vrgatherei16.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL,
> 0, 0, 0 },
> { "vrgather.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0,
> 0 },
> - { "vrgather.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0,
> 0, 0 },
> + { "vrgather.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm, NULL, 0,
> 0, 0 },
> { "vcompress.vm", rv_codec_v_r, rv_fmt_vd_vs2_vs1, NULL, 0, 0, 0
> },
> { "vmv1r.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
> { "vmv2r.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
> @@ -2144,8 +2144,8 @@ const rv_opcode_data rvi_opcode_data[] = {
> { "vaesef.vs", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
> { "vaesem.vv", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
> { "vaesem.vs", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
> - { "vaeskf1.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm, NULL, 0, 0, 0
> },
> - { "vaeskf2.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm, NULL, 0, 0, 0
> },
> + { "vaeskf1.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm, NULL, 0, 0,
> 0 },
> + { "vaeskf2.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm, NULL, 0, 0,
> 0 },
> { "vaesz.vs", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
> { "vandn.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0
> },
> { "vandn.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0
> },
> @@ -2169,14 +2169,14 @@ const rv_opcode_data rvi_opcode_data[] = {
> { "vsha2ch.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1, NULL, 0, 0, 0
> },
> { "vsha2cl.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1, NULL, 0, 0, 0
> },
> { "vsha2ms.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1, NULL, 0, 0, 0
> },
> - { "vsm3c.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm, NULL, 0, 0, 0 },
> + { "vsm3c.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm, NULL, 0, 0, 0
> },
> { "vsm3me.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1, NULL, 0, 0, 0 },
> - { "vsm4k.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm, NULL, 0, 0, 0 },
> + { "vsm4k.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm, NULL, 0, 0, 0
> },
> { "vsm4r.vv", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
> { "vsm4r.vs", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
> { "vwsll.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0
> },
> { "vwsll.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0
> },
> - { "vwsll.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0
> },
> + { "vwsll.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0,
> 0 },
> { "amocas.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0,
> 0 },
> { "amocas.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0,
> 0 },
> { "amocas.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0,
> 0 },
> @@ -4492,6 +4492,11 @@ static int32_t operand_vimm(rv_inst inst)
> return (int64_t)(inst << 44) >> 59;
> }
>
> +static uint32_t operand_vuimm(rv_inst inst)
> +{
> + return extract32(inst, 15, 5);
> +}
> +
> static uint32_t operand_vzimm11(rv_inst inst)
> {
> return (inst << 33) >> 53;
> @@ -4895,6 +4900,12 @@ static void decode_inst_operands(rv_decode
> *dec, rv_isa isa)
> dec->imm = operand_vimm(inst);
> dec->vm = operand_vm(inst);
> break;
> + case rv_codec_v_i_u:
> + dec->rd = operand_rd(inst);
> + dec->rs2 = operand_rs2(inst);
> + dec->imm = operand_vuimm(inst);
> + dec->vm = operand_vm(inst);
> + break;
> case rv_codec_vror_vi:
> dec->rd = operand_rd(inst);
> dec->rs2 = operand_rs2(inst);
^ permalink raw reply [flat|nested] 119+ messages in thread
* Re: [PATCH 05/56] disas/riscv: Use extract helpers for operand fields
2026-08-09 22:34 ` [PATCH 05/56] disas/riscv: Use extract helpers for operand fields Richard Henderson
@ 2026-08-11 19:58 ` Alistair
0 siblings, 0 replies; 119+ messages in thread
From: Alistair @ 2026-08-11 19:58 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: qemu-riscv, TANG Tiancheng, LIU Zhiwei
On Sun, 2026-08-09 at 15:34 -0700, Richard Henderson wrote:
> From: TANG Tiancheng <lyndra@linux.alibaba.com>
>
> Replace shift-based operand extraction with extract32() and
> sextract32().
> For signed immediates, use sextract32() on the field that carries the
> sign
> bit and combine it with the remaining extract32() fields.
>
> The RISC-V disassembler currently follows target/riscv/internals.h:
> insn_len() and decodes only 16-bit or 32-bit instruction lengths, so
> the
> converted fields are all in the low 32 bits of rv_inst.
>
> Suggested-by: Richard Henderson <richard.henderson@linaro.org>
> Signed-off-by: TANG Tiancheng <lyndra@linux.alibaba.com>
> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
> Message-Id:
> <20260703-b4-disas-xthead-fix-riscv-next-v4-5-84c566330bc7@linux.alib
> aba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> disas/riscv.c | 214 +++++++++++++++++++++++++-----------------------
> --
> 1 file changed, 107 insertions(+), 107 deletions(-)
>
> diff --git a/disas/riscv.c b/disas/riscv.c
> index 82b962dc71..2ba0a6a73a 100644
> --- a/disas/riscv.c
> +++ b/disas/riscv.c
> @@ -4202,82 +4202,82 @@ static void decode_inst_opcode(rv_decode
> *dec, rv_isa isa)
>
> static uint32_t operand_rd(rv_inst inst)
> {
> - return (inst << 52) >> 59;
> + return extract32(inst, 7, 5);
> }
>
> static uint32_t operand_rs1(rv_inst inst)
> {
> - return (inst << 44) >> 59;
> + return extract32(inst, 15, 5);
> }
>
> static uint32_t operand_rs2(rv_inst inst)
> {
> - return (inst << 39) >> 59;
> + return extract32(inst, 20, 5);
> }
>
> static uint32_t operand_rs3(rv_inst inst)
> {
> - return (inst << 32) >> 59;
> + return extract32(inst, 27, 5);
> }
>
> static uint32_t operand_aq(rv_inst inst)
> {
> - return (inst << 37) >> 63;
> + return extract32(inst, 26, 1);
> }
>
> static uint32_t operand_rl(rv_inst inst)
> {
> - return (inst << 38) >> 63;
> + return extract32(inst, 25, 1);
> }
>
> static uint32_t operand_pred(rv_inst inst)
> {
> - return (inst << 36) >> 60;
> + return extract32(inst, 24, 4);
> }
>
> static uint32_t operand_succ(rv_inst inst)
> {
> - return (inst << 40) >> 60;
> + return extract32(inst, 20, 4);
> }
>
> static uint32_t operand_rm(rv_inst inst)
> {
> - return (inst << 49) >> 61;
> + return extract32(inst, 12, 3);
> }
>
> static uint32_t operand_shamt5(rv_inst inst)
> {
> - return (inst << 39) >> 59;
> + return extract32(inst, 20, 5);
> }
>
> static uint32_t operand_shamt6(rv_inst inst)
> {
> - return (inst << 38) >> 58;
> + return extract32(inst, 20, 6);
> }
>
> static uint32_t operand_shamt7(rv_inst inst)
> {
> - return (inst << 37) >> 57;
> + return extract32(inst, 20, 7);
> }
>
> static uint32_t operand_crdq(rv_inst inst)
> {
> - return (inst << 59) >> 61;
> + return extract32(inst, 2, 3);
> }
>
> static uint32_t operand_crs1q(rv_inst inst)
> {
> - return (inst << 54) >> 61;
> + return extract32(inst, 7, 3);
> }
>
> static uint32_t operand_crs1rdq(rv_inst inst)
> {
> - return (inst << 54) >> 61;
> + return extract32(inst, 7, 3);
> }
>
> static uint32_t operand_crs2q(rv_inst inst)
> {
> - return (inst << 59) >> 61;
> + return extract32(inst, 2, 3);
> }
>
> static uint32_t calculate_xreg(uint32_t sreg)
> @@ -4287,80 +4287,80 @@ static uint32_t calculate_xreg(uint32_t sreg)
>
> static uint32_t operand_sreg1(rv_inst inst)
> {
> - return calculate_xreg((inst << 54) >> 61);
> + return calculate_xreg(extract32(inst, 7, 3));
> }
>
> static uint32_t operand_sreg2(rv_inst inst)
> {
> - return calculate_xreg((inst << 59) >> 61);
> + return calculate_xreg(extract32(inst, 2, 3));
> }
>
> static uint32_t operand_crd(rv_inst inst)
> {
> - return (inst << 52) >> 59;
> + return extract32(inst, 7, 5);
> }
>
> static uint32_t operand_crs1(rv_inst inst)
> {
> - return (inst << 52) >> 59;
> + return extract32(inst, 7, 5);
> }
>
> static uint32_t operand_crs1rd(rv_inst inst)
> {
> - return (inst << 52) >> 59;
> + return extract32(inst, 7, 5);
> }
>
> static uint32_t operand_crs2(rv_inst inst)
> {
> - return (inst << 57) >> 59;
> + return extract32(inst, 2, 5);
> }
>
> static uint32_t operand_cimmsh5(rv_inst inst)
> {
> - return (inst << 57) >> 59;
> + return extract32(inst, 2, 5);
> }
>
> static uint32_t operand_csr12(rv_inst inst)
> {
> - return (inst << 32) >> 52;
> + return extract32(inst, 20, 12);
> }
>
> static int32_t operand_imm12(rv_inst inst)
> {
> - return ((int64_t)inst << 32) >> 52;
> + return sextract32(inst, 20, 12);
> }
>
> static int32_t operand_imm20(rv_inst inst)
> {
> - return (((int64_t)inst << 32) >> 44) << 12;
> + return sextract32(inst, 12, 20) << 12;
> }
>
> static int32_t operand_jimm20(rv_inst inst)
> {
> - return (((int64_t)inst << 32) >> 63) << 20 |
> - ((inst << 33) >> 54) << 1 |
> - ((inst << 43) >> 63) << 11 |
> - ((inst << 44) >> 56) << 12;
> + return sextract32(inst, 31, 1) << 20 |
> + extract32(inst, 21, 10) << 1 |
> + extract32(inst, 20, 1) << 11 |
> + extract32(inst, 12, 8) << 12;
> }
>
> static int32_t operand_simm12(rv_inst inst)
> {
> - return (((int64_t)inst << 32) >> 57) << 5 |
> - (inst << 52) >> 59;
> + return sextract32(inst, 25, 7) << 5 |
> + extract32(inst, 7, 5);
> }
>
> static int32_t operand_sbimm12(rv_inst inst)
> {
> - return (((int64_t)inst << 32) >> 63) << 12 |
> - ((inst << 33) >> 58) << 5 |
> - ((inst << 52) >> 60) << 1 |
> - ((inst << 56) >> 63) << 11;
> + return sextract32(inst, 31, 1) << 12 |
> + extract32(inst, 25, 6) << 5 |
> + extract32(inst, 8, 4) << 1 |
> + extract32(inst, 7, 1) << 11;
> }
>
> static uint32_t operand_cimmshl6(rv_inst inst, rv_isa isa)
> {
> - int imm = ((inst << 51) >> 63) << 5 |
> - (inst << 57) >> 59;
> + int imm = extract32(inst, 12, 1) << 5 |
> + extract32(inst, 2, 5);
> if (isa == rv128) {
> imm = imm ? imm : 64;
> }
> @@ -4369,8 +4369,8 @@ static uint32_t operand_cimmshl6(rv_inst inst,
> rv_isa isa)
>
> static uint32_t operand_cimmshr6(rv_inst inst, rv_isa isa)
> {
> - int imm = ((inst << 51) >> 63) << 5 |
> - (inst << 57) >> 59;
> + int imm = extract32(inst, 12, 1) << 5 |
> + extract32(inst, 2, 5);
> if (isa == rv128) {
> imm = imm | (imm & 32) << 1;
> imm = imm ? imm : 64;
> @@ -4380,116 +4380,116 @@ static uint32_t operand_cimmshr6(rv_inst
> inst, rv_isa isa)
>
> static int32_t operand_cimmi(rv_inst inst)
> {
> - return (((int64_t)inst << 51) >> 63) << 5 |
> - (inst << 57) >> 59;
> + return sextract32(inst, 12, 1) << 5 |
> + extract32(inst, 2, 5);
> }
>
> static int32_t operand_cimmui(rv_inst inst)
> {
> - return (((int64_t)inst << 51) >> 63) << 17 |
> - ((inst << 57) >> 59) << 12;
> + return sextract32(inst, 12, 1) << 17 |
> + extract32(inst, 2, 5) << 12;
> }
>
> static uint32_t operand_cimmlwsp(rv_inst inst)
> {
> - return ((inst << 51) >> 63) << 5 |
> - ((inst << 57) >> 61) << 2 |
> - ((inst << 60) >> 62) << 6;
> + return extract32(inst, 12, 1) << 5 |
> + extract32(inst, 4, 3) << 2 |
> + extract32(inst, 2, 2) << 6;
> }
>
> static uint32_t operand_cimmldsp(rv_inst inst)
> {
> - return ((inst << 51) >> 63) << 5 |
> - ((inst << 57) >> 62) << 3 |
> - ((inst << 59) >> 61) << 6;
> + return extract32(inst, 12, 1) << 5 |
> + extract32(inst, 5, 2) << 3 |
> + extract32(inst, 2, 3) << 6;
> }
>
> static uint32_t operand_cimmlqsp(rv_inst inst)
> {
> - return ((inst << 51) >> 63) << 5 |
> - ((inst << 57) >> 63) << 4 |
> - ((inst << 58) >> 60) << 6;
> + return extract32(inst, 12, 1) << 5 |
> + extract32(inst, 6, 1) << 4 |
> + extract32(inst, 2, 4) << 6;
> }
>
> static int32_t operand_cimm16sp(rv_inst inst)
> {
> - return (((int64_t)inst << 51) >> 63) << 9 |
> - ((inst << 57) >> 63) << 4 |
> - ((inst << 58) >> 63) << 6 |
> - ((inst << 59) >> 62) << 7 |
> - ((inst << 61) >> 63) << 5;
> + return sextract32(inst, 12, 1) << 9 |
> + extract32(inst, 6, 1) << 4 |
> + extract32(inst, 5, 1) << 6 |
> + extract32(inst, 3, 2) << 7 |
> + extract32(inst, 2, 1) << 5;
> }
>
> static int32_t operand_cimmj(rv_inst inst)
> {
> - return (((int64_t)inst << 51) >> 63) << 11 |
> - ((inst << 52) >> 63) << 4 |
> - ((inst << 53) >> 62) << 8 |
> - ((inst << 55) >> 63) << 10 |
> - ((inst << 56) >> 63) << 6 |
> - ((inst << 57) >> 63) << 7 |
> - ((inst << 58) >> 61) << 1 |
> - ((inst << 61) >> 63) << 5;
> + return sextract32(inst, 12, 1) << 11 |
> + extract32(inst, 11, 1) << 4 |
> + extract32(inst, 9, 2) << 8 |
> + extract32(inst, 8, 1) << 10 |
> + extract32(inst, 7, 1) << 6 |
> + extract32(inst, 6, 1) << 7 |
> + extract32(inst, 3, 3) << 1 |
> + extract32(inst, 2, 1) << 5;
> }
>
> static int32_t operand_cimmb(rv_inst inst)
> {
> - return (((int64_t)inst << 51) >> 63) << 8 |
> - ((inst << 52) >> 62) << 3 |
> - ((inst << 57) >> 62) << 6 |
> - ((inst << 59) >> 62) << 1 |
> - ((inst << 61) >> 63) << 5;
> + return sextract32(inst, 12, 1) << 8 |
> + extract32(inst, 10, 2) << 3 |
> + extract32(inst, 5, 2) << 6 |
> + extract32(inst, 3, 2) << 1 |
> + extract32(inst, 2, 1) << 5;
> }
>
> static uint32_t operand_cimmswsp(rv_inst inst)
> {
> - return ((inst << 51) >> 60) << 2 |
> - ((inst << 55) >> 62) << 6;
> + return extract32(inst, 9, 4) << 2 |
> + extract32(inst, 7, 2) << 6;
> }
>
> static uint32_t operand_cimmsdsp(rv_inst inst)
> {
> - return ((inst << 51) >> 61) << 3 |
> - ((inst << 54) >> 61) << 6;
> + return extract32(inst, 10, 3) << 3 |
> + extract32(inst, 7, 3) << 6;
> }
>
> static uint32_t operand_cimmsqsp(rv_inst inst)
> {
> - return ((inst << 51) >> 62) << 4 |
> - ((inst << 53) >> 60) << 6;
> + return extract32(inst, 11, 2) << 4 |
> + extract32(inst, 7, 4) << 6;
> }
>
> static uint32_t operand_cimm4spn(rv_inst inst)
> {
> - return ((inst << 51) >> 62) << 4 |
> - ((inst << 53) >> 60) << 6 |
> - ((inst << 57) >> 63) << 2 |
> - ((inst << 58) >> 63) << 3;
> + return extract32(inst, 11, 2) << 4 |
> + extract32(inst, 7, 4) << 6 |
> + extract32(inst, 6, 1) << 2 |
> + extract32(inst, 5, 1) << 3;
> }
>
> static uint32_t operand_cimmw(rv_inst inst)
> {
> - return ((inst << 51) >> 61) << 3 |
> - ((inst << 57) >> 63) << 2 |
> - ((inst << 58) >> 63) << 6;
> + return extract32(inst, 10, 3) << 3 |
> + extract32(inst, 6, 1) << 2 |
> + extract32(inst, 5, 1) << 6;
> }
>
> static uint32_t operand_cimmd(rv_inst inst)
> {
> - return ((inst << 51) >> 61) << 3 |
> - ((inst << 57) >> 62) << 6;
> + return extract32(inst, 10, 3) << 3 |
> + extract32(inst, 5, 2) << 6;
> }
>
> static uint32_t operand_cimmq(rv_inst inst)
> {
> - return ((inst << 51) >> 62) << 4 |
> - ((inst << 53) >> 63) << 8 |
> - ((inst << 57) >> 62) << 6;
> + return extract32(inst, 11, 2) << 4 |
> + extract32(inst, 10, 1) << 8 |
> + extract32(inst, 5, 2) << 6;
> }
>
> static int32_t operand_vimm(rv_inst inst)
> {
> - return (int64_t)(inst << 44) >> 59;
> + return sextract32(inst, 15, 5);
> }
>
> static uint32_t operand_vuimm(rv_inst inst)
> @@ -4499,54 +4499,54 @@ static uint32_t operand_vuimm(rv_inst inst)
>
> static uint32_t operand_vzimm11(rv_inst inst)
> {
> - return (inst << 33) >> 53;
> + return extract32(inst, 20, 11);
> }
>
> static uint32_t operand_vzimm10(rv_inst inst)
> {
> - return (inst << 34) >> 54;
> + return extract32(inst, 20, 10);
> }
>
> static uint32_t operand_vzimm6(rv_inst inst)
> {
> - return ((inst << 37) >> 63) << 5 |
> - ((inst << 44) >> 59);
> + return extract32(inst, 26, 1) << 5 |
> + extract32(inst, 15, 5);
> }
>
> static uint32_t operand_bs(rv_inst inst)
> {
> - return (inst << 32) >> 62;
> + return extract32(inst, 30, 2);
> }
>
> static uint32_t operand_rnum(rv_inst inst)
> {
> - return (inst << 40) >> 60;
> + return extract32(inst, 20, 4);
> }
>
> static uint32_t operand_vm(rv_inst inst)
> {
> - return (inst << 38) >> 63;
> + return extract32(inst, 25, 1);
> }
>
> static uint32_t operand_uimm_c_lb(rv_inst inst)
> {
> - return (((inst << 58) >> 63) << 1) |
> - ((inst << 57) >> 63);
> + return extract32(inst, 5, 1) << 1 |
> + extract32(inst, 6, 1);
> }
>
> static uint32_t operand_uimm_c_lh(rv_inst inst)
> {
> - return (((inst << 58) >> 63) << 1);
> + return extract32(inst, 5, 1) << 1;
> }
>
> static uint32_t operand_zcmp_spimm(rv_inst inst)
> {
> - return ((inst << 60) >> 62) << 4;
> + return extract32(inst, 2, 2) << 4;
> }
>
> static uint32_t operand_zcmp_rlist(rv_inst inst)
> {
> - return ((inst << 56) >> 60);
> + return extract32(inst, 4, 4);
> }
>
> static uint32_t operand_imm6(rv_inst inst)
> @@ -4556,17 +4556,17 @@ static uint32_t operand_imm6(rv_inst inst)
>
> static uint32_t operand_imm2(rv_inst inst)
> {
> - return (inst << 37) >> 62;
> + return extract32(inst, 25, 2);
> }
>
> static uint32_t operand_immh(rv_inst inst)
> {
> - return (inst << 32) >> 58;
> + return extract32(inst, 26, 6);
> }
>
> static uint32_t operand_imml(rv_inst inst)
> {
> - return (inst << 38) >> 58;
> + return extract32(inst, 20, 6);
> }
>
> static uint32_t calculate_stack_adj(rv_isa isa, uint32_t rlist,
> uint32_t spimm)
> @@ -4585,12 +4585,12 @@ static uint32_t
> operand_zcmp_stack_adj(rv_inst inst, rv_isa isa)
>
> static uint32_t operand_tbl_index(rv_inst inst)
> {
> - return ((inst << 54) >> 56);
> + return extract32(inst, 2, 8);
> }
>
> static uint32_t operand_lpl(rv_inst inst)
> {
> - return inst >> 12;
> + return extract32(inst, 12, 20);
> }
>
> /* decode operands */
^ permalink raw reply [flat|nested] 119+ messages in thread
* Re: [PATCH 06/56] disas/riscv: Move operand extractors earlier in file
2026-08-09 22:34 ` [PATCH 06/56] disas/riscv: Move operand extractors earlier in file Richard Henderson
@ 2026-08-11 19:59 ` Alistair
0 siblings, 0 replies; 119+ messages in thread
From: Alistair @ 2026-08-11 19:59 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: qemu-riscv
On Sun, 2026-08-09 at 15:34 -0700, Richard Henderson wrote:
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> disas/riscv.c | 790 +++++++++++++++++++++++++-----------------------
> --
> 1 file changed, 395 insertions(+), 395 deletions(-)
>
> diff --git a/disas/riscv.c b/disas/riscv.c
> index 2ba0a6a73a..e3fbc26626 100644
> --- a/disas/riscv.c
> +++ b/disas/riscv.c
> @@ -1259,6 +1259,401 @@ static const rv_comp_data rvcp_fsgnjx_q[] = {
> { rv_op_illegal, NULL }
> };
>
> +/* operand extractors */
> +
> +static uint32_t operand_rd(rv_inst inst)
> +{
> + return extract32(inst, 7, 5);
> +}
> +
> +static uint32_t operand_rs1(rv_inst inst)
> +{
> + return extract32(inst, 15, 5);
> +}
> +
> +static uint32_t operand_rs2(rv_inst inst)
> +{
> + return extract32(inst, 20, 5);
> +}
> +
> +static uint32_t operand_rs3(rv_inst inst)
> +{
> + return extract32(inst, 27, 5);
> +}
> +
> +static uint32_t operand_aq(rv_inst inst)
> +{
> + return extract32(inst, 26, 1);
> +}
> +
> +static uint32_t operand_rl(rv_inst inst)
> +{
> + return extract32(inst, 25, 1);
> +}
> +
> +static uint32_t operand_pred(rv_inst inst)
> +{
> + return extract32(inst, 24, 4);
> +}
> +
> +static uint32_t operand_succ(rv_inst inst)
> +{
> + return extract32(inst, 20, 4);
> +}
> +
> +static uint32_t operand_rm(rv_inst inst)
> +{
> + return extract32(inst, 12, 3);
> +}
> +
> +static uint32_t operand_shamt5(rv_inst inst)
> +{
> + return extract32(inst, 20, 5);
> +}
> +
> +static uint32_t operand_shamt6(rv_inst inst)
> +{
> + return extract32(inst, 20, 6);
> +}
> +
> +static uint32_t operand_shamt7(rv_inst inst)
> +{
> + return extract32(inst, 20, 7);
> +}
> +
> +static uint32_t operand_crdq(rv_inst inst)
> +{
> + return extract32(inst, 2, 3);
> +}
> +
> +static uint32_t operand_crs1q(rv_inst inst)
> +{
> + return extract32(inst, 7, 3);
> +}
> +
> +static uint32_t operand_crs1rdq(rv_inst inst)
> +{
> + return extract32(inst, 7, 3);
> +}
> +
> +static uint32_t operand_crs2q(rv_inst inst)
> +{
> + return extract32(inst, 2, 3);
> +}
> +
> +static uint32_t calculate_xreg(uint32_t sreg)
> +{
> + return sreg < 2 ? sreg + 8 : sreg + 16;
> +}
> +
> +static uint32_t operand_sreg1(rv_inst inst)
> +{
> + return calculate_xreg(extract32(inst, 7, 3));
> +}
> +
> +static uint32_t operand_sreg2(rv_inst inst)
> +{
> + return calculate_xreg(extract32(inst, 2, 3));
> +}
> +
> +static uint32_t operand_crd(rv_inst inst)
> +{
> + return extract32(inst, 7, 5);
> +}
> +
> +static uint32_t operand_crs1(rv_inst inst)
> +{
> + return extract32(inst, 7, 5);
> +}
> +
> +static uint32_t operand_crs1rd(rv_inst inst)
> +{
> + return extract32(inst, 7, 5);
> +}
> +
> +static uint32_t operand_crs2(rv_inst inst)
> +{
> + return extract32(inst, 2, 5);
> +}
> +
> +static uint32_t operand_cimmsh5(rv_inst inst)
> +{
> + return extract32(inst, 2, 5);
> +}
> +
> +static uint32_t operand_csr12(rv_inst inst)
> +{
> + return extract32(inst, 20, 12);
> +}
> +
> +static int32_t operand_imm12(rv_inst inst)
> +{
> + return sextract32(inst, 20, 12);
> +}
> +
> +static int32_t operand_imm20(rv_inst inst)
> +{
> + return sextract32(inst, 12, 20) << 12;
> +}
> +
> +static int32_t operand_jimm20(rv_inst inst)
> +{
> + return sextract32(inst, 31, 1) << 20 |
> + extract32(inst, 21, 10) << 1 |
> + extract32(inst, 20, 1) << 11 |
> + extract32(inst, 12, 8) << 12;
> +}
> +
> +static int32_t operand_simm12(rv_inst inst)
> +{
> + return sextract32(inst, 25, 7) << 5 |
> + extract32(inst, 7, 5);
> +}
> +
> +static int32_t operand_sbimm12(rv_inst inst)
> +{
> + return sextract32(inst, 31, 1) << 12 |
> + extract32(inst, 25, 6) << 5 |
> + extract32(inst, 8, 4) << 1 |
> + extract32(inst, 7, 1) << 11;
> +}
> +
> +static uint32_t operand_cimmshl6(rv_inst inst, rv_isa isa)
> +{
> + int imm = extract32(inst, 12, 1) << 5 |
> + extract32(inst, 2, 5);
> + if (isa == rv128) {
> + imm = imm ? imm : 64;
> + }
> + return imm;
> +}
> +
> +static uint32_t operand_cimmshr6(rv_inst inst, rv_isa isa)
> +{
> + int imm = extract32(inst, 12, 1) << 5 |
> + extract32(inst, 2, 5);
> + if (isa == rv128) {
> + imm = imm | (imm & 32) << 1;
> + imm = imm ? imm : 64;
> + }
> + return imm;
> +}
> +
> +static int32_t operand_cimmi(rv_inst inst)
> +{
> + return sextract32(inst, 12, 1) << 5 |
> + extract32(inst, 2, 5);
> +}
> +
> +static int32_t operand_cimmui(rv_inst inst)
> +{
> + return sextract32(inst, 12, 1) << 17 |
> + extract32(inst, 2, 5) << 12;
> +}
> +
> +static uint32_t operand_cimmlwsp(rv_inst inst)
> +{
> + return extract32(inst, 12, 1) << 5 |
> + extract32(inst, 4, 3) << 2 |
> + extract32(inst, 2, 2) << 6;
> +}
> +
> +static uint32_t operand_cimmldsp(rv_inst inst)
> +{
> + return extract32(inst, 12, 1) << 5 |
> + extract32(inst, 5, 2) << 3 |
> + extract32(inst, 2, 3) << 6;
> +}
> +
> +static uint32_t operand_cimmlqsp(rv_inst inst)
> +{
> + return extract32(inst, 12, 1) << 5 |
> + extract32(inst, 6, 1) << 4 |
> + extract32(inst, 2, 4) << 6;
> +}
> +
> +static int32_t operand_cimm16sp(rv_inst inst)
> +{
> + return sextract32(inst, 12, 1) << 9 |
> + extract32(inst, 6, 1) << 4 |
> + extract32(inst, 5, 1) << 6 |
> + extract32(inst, 3, 2) << 7 |
> + extract32(inst, 2, 1) << 5;
> +}
> +
> +static int32_t operand_cimmj(rv_inst inst)
> +{
> + return sextract32(inst, 12, 1) << 11 |
> + extract32(inst, 11, 1) << 4 |
> + extract32(inst, 9, 2) << 8 |
> + extract32(inst, 8, 1) << 10 |
> + extract32(inst, 7, 1) << 6 |
> + extract32(inst, 6, 1) << 7 |
> + extract32(inst, 3, 3) << 1 |
> + extract32(inst, 2, 1) << 5;
> +}
> +
> +static int32_t operand_cimmb(rv_inst inst)
> +{
> + return sextract32(inst, 12, 1) << 8 |
> + extract32(inst, 10, 2) << 3 |
> + extract32(inst, 5, 2) << 6 |
> + extract32(inst, 3, 2) << 1 |
> + extract32(inst, 2, 1) << 5;
> +}
> +
> +static uint32_t operand_cimmswsp(rv_inst inst)
> +{
> + return extract32(inst, 9, 4) << 2 |
> + extract32(inst, 7, 2) << 6;
> +}
> +
> +static uint32_t operand_cimmsdsp(rv_inst inst)
> +{
> + return extract32(inst, 10, 3) << 3 |
> + extract32(inst, 7, 3) << 6;
> +}
> +
> +static uint32_t operand_cimmsqsp(rv_inst inst)
> +{
> + return extract32(inst, 11, 2) << 4 |
> + extract32(inst, 7, 4) << 6;
> +}
> +
> +static uint32_t operand_cimm4spn(rv_inst inst)
> +{
> + return extract32(inst, 11, 2) << 4 |
> + extract32(inst, 7, 4) << 6 |
> + extract32(inst, 6, 1) << 2 |
> + extract32(inst, 5, 1) << 3;
> +}
> +
> +static uint32_t operand_cimmw(rv_inst inst)
> +{
> + return extract32(inst, 10, 3) << 3 |
> + extract32(inst, 6, 1) << 2 |
> + extract32(inst, 5, 1) << 6;
> +}
> +
> +static uint32_t operand_cimmd(rv_inst inst)
> +{
> + return extract32(inst, 10, 3) << 3 |
> + extract32(inst, 5, 2) << 6;
> +}
> +
> +static uint32_t operand_cimmq(rv_inst inst)
> +{
> + return extract32(inst, 11, 2) << 4 |
> + extract32(inst, 10, 1) << 8 |
> + extract32(inst, 5, 2) << 6;
> +}
> +
> +static int32_t operand_vimm(rv_inst inst)
> +{
> + return sextract32(inst, 15, 5);
> +}
> +
> +static uint32_t operand_vuimm(rv_inst inst)
> +{
> + return extract32(inst, 15, 5);
> +}
> +
> +static uint32_t operand_vzimm11(rv_inst inst)
> +{
> + return extract32(inst, 20, 11);
> +}
> +
> +static uint32_t operand_vzimm10(rv_inst inst)
> +{
> + return extract32(inst, 20, 10);
> +}
> +
> +static uint32_t operand_vzimm6(rv_inst inst)
> +{
> + return extract32(inst, 26, 1) << 5 |
> + extract32(inst, 15, 5);
> +}
> +
> +static uint32_t operand_bs(rv_inst inst)
> +{
> + return extract32(inst, 30, 2);
> +}
> +
> +static uint32_t operand_rnum(rv_inst inst)
> +{
> + return extract32(inst, 20, 4);
> +}
> +
> +static uint32_t operand_vm(rv_inst inst)
> +{
> + return extract32(inst, 25, 1);
> +}
> +
> +static uint32_t operand_uimm_c_lb(rv_inst inst)
> +{
> + return extract32(inst, 5, 1) << 1 |
> + extract32(inst, 6, 1);
> +}
> +
> +static uint32_t operand_uimm_c_lh(rv_inst inst)
> +{
> + return extract32(inst, 5, 1) << 1;
> +}
> +
> +static uint32_t operand_zcmp_spimm(rv_inst inst)
> +{
> + return extract32(inst, 2, 2) << 4;
> +}
> +
> +static uint32_t operand_zcmp_rlist(rv_inst inst)
> +{
> + return extract32(inst, 4, 4);
> +}
> +
> +static uint32_t operand_imm6(rv_inst inst)
> +{
> + return extract32(inst, 20, 6);
> +}
> +
> +static uint32_t operand_imm2(rv_inst inst)
> +{
> + return extract32(inst, 25, 2);
> +}
> +
> +static uint32_t operand_immh(rv_inst inst)
> +{
> + return extract32(inst, 26, 6);
> +}
> +
> +static uint32_t operand_imml(rv_inst inst)
> +{
> + return extract32(inst, 20, 6);
> +}
> +
> +static uint32_t calculate_stack_adj(rv_isa isa, uint32_t rlist,
> uint32_t spimm)
> +{
> + int xlen_bytes_log2 = isa == rv64 ? 3 : 2;
> + int regs = rlist == 15 ? 13 : rlist - 3;
> + uint32_t stack_adj_base = ROUND_UP(regs << xlen_bytes_log2, 16);
> + return stack_adj_base + spimm;
> +}
> +
> +static uint32_t operand_zcmp_stack_adj(rv_inst inst, rv_isa isa)
> +{
> + return calculate_stack_adj(isa, operand_zcmp_rlist(inst),
> + operand_zcmp_spimm(inst));
> +}
> +
> +static uint32_t operand_tbl_index(rv_inst inst)
> +{
> + return extract32(inst, 2, 8);
> +}
> +
> +static uint32_t operand_lpl(rv_inst inst)
> +{
> + return extract32(inst, 12, 20);
> +}
> +
> /* instruction metadata */
>
> const rv_opcode_data rvi_opcode_data[] = {
> @@ -4198,401 +4593,6 @@ static void decode_inst_opcode(rv_decode
> *dec, rv_isa isa)
> dec->op = op;
> }
>
> -/* operand extractors */
> -
> -static uint32_t operand_rd(rv_inst inst)
> -{
> - return extract32(inst, 7, 5);
> -}
> -
> -static uint32_t operand_rs1(rv_inst inst)
> -{
> - return extract32(inst, 15, 5);
> -}
> -
> -static uint32_t operand_rs2(rv_inst inst)
> -{
> - return extract32(inst, 20, 5);
> -}
> -
> -static uint32_t operand_rs3(rv_inst inst)
> -{
> - return extract32(inst, 27, 5);
> -}
> -
> -static uint32_t operand_aq(rv_inst inst)
> -{
> - return extract32(inst, 26, 1);
> -}
> -
> -static uint32_t operand_rl(rv_inst inst)
> -{
> - return extract32(inst, 25, 1);
> -}
> -
> -static uint32_t operand_pred(rv_inst inst)
> -{
> - return extract32(inst, 24, 4);
> -}
> -
> -static uint32_t operand_succ(rv_inst inst)
> -{
> - return extract32(inst, 20, 4);
> -}
> -
> -static uint32_t operand_rm(rv_inst inst)
> -{
> - return extract32(inst, 12, 3);
> -}
> -
> -static uint32_t operand_shamt5(rv_inst inst)
> -{
> - return extract32(inst, 20, 5);
> -}
> -
> -static uint32_t operand_shamt6(rv_inst inst)
> -{
> - return extract32(inst, 20, 6);
> -}
> -
> -static uint32_t operand_shamt7(rv_inst inst)
> -{
> - return extract32(inst, 20, 7);
> -}
> -
> -static uint32_t operand_crdq(rv_inst inst)
> -{
> - return extract32(inst, 2, 3);
> -}
> -
> -static uint32_t operand_crs1q(rv_inst inst)
> -{
> - return extract32(inst, 7, 3);
> -}
> -
> -static uint32_t operand_crs1rdq(rv_inst inst)
> -{
> - return extract32(inst, 7, 3);
> -}
> -
> -static uint32_t operand_crs2q(rv_inst inst)
> -{
> - return extract32(inst, 2, 3);
> -}
> -
> -static uint32_t calculate_xreg(uint32_t sreg)
> -{
> - return sreg < 2 ? sreg + 8 : sreg + 16;
> -}
> -
> -static uint32_t operand_sreg1(rv_inst inst)
> -{
> - return calculate_xreg(extract32(inst, 7, 3));
> -}
> -
> -static uint32_t operand_sreg2(rv_inst inst)
> -{
> - return calculate_xreg(extract32(inst, 2, 3));
> -}
> -
> -static uint32_t operand_crd(rv_inst inst)
> -{
> - return extract32(inst, 7, 5);
> -}
> -
> -static uint32_t operand_crs1(rv_inst inst)
> -{
> - return extract32(inst, 7, 5);
> -}
> -
> -static uint32_t operand_crs1rd(rv_inst inst)
> -{
> - return extract32(inst, 7, 5);
> -}
> -
> -static uint32_t operand_crs2(rv_inst inst)
> -{
> - return extract32(inst, 2, 5);
> -}
> -
> -static uint32_t operand_cimmsh5(rv_inst inst)
> -{
> - return extract32(inst, 2, 5);
> -}
> -
> -static uint32_t operand_csr12(rv_inst inst)
> -{
> - return extract32(inst, 20, 12);
> -}
> -
> -static int32_t operand_imm12(rv_inst inst)
> -{
> - return sextract32(inst, 20, 12);
> -}
> -
> -static int32_t operand_imm20(rv_inst inst)
> -{
> - return sextract32(inst, 12, 20) << 12;
> -}
> -
> -static int32_t operand_jimm20(rv_inst inst)
> -{
> - return sextract32(inst, 31, 1) << 20 |
> - extract32(inst, 21, 10) << 1 |
> - extract32(inst, 20, 1) << 11 |
> - extract32(inst, 12, 8) << 12;
> -}
> -
> -static int32_t operand_simm12(rv_inst inst)
> -{
> - return sextract32(inst, 25, 7) << 5 |
> - extract32(inst, 7, 5);
> -}
> -
> -static int32_t operand_sbimm12(rv_inst inst)
> -{
> - return sextract32(inst, 31, 1) << 12 |
> - extract32(inst, 25, 6) << 5 |
> - extract32(inst, 8, 4) << 1 |
> - extract32(inst, 7, 1) << 11;
> -}
> -
> -static uint32_t operand_cimmshl6(rv_inst inst, rv_isa isa)
> -{
> - int imm = extract32(inst, 12, 1) << 5 |
> - extract32(inst, 2, 5);
> - if (isa == rv128) {
> - imm = imm ? imm : 64;
> - }
> - return imm;
> -}
> -
> -static uint32_t operand_cimmshr6(rv_inst inst, rv_isa isa)
> -{
> - int imm = extract32(inst, 12, 1) << 5 |
> - extract32(inst, 2, 5);
> - if (isa == rv128) {
> - imm = imm | (imm & 32) << 1;
> - imm = imm ? imm : 64;
> - }
> - return imm;
> -}
> -
> -static int32_t operand_cimmi(rv_inst inst)
> -{
> - return sextract32(inst, 12, 1) << 5 |
> - extract32(inst, 2, 5);
> -}
> -
> -static int32_t operand_cimmui(rv_inst inst)
> -{
> - return sextract32(inst, 12, 1) << 17 |
> - extract32(inst, 2, 5) << 12;
> -}
> -
> -static uint32_t operand_cimmlwsp(rv_inst inst)
> -{
> - return extract32(inst, 12, 1) << 5 |
> - extract32(inst, 4, 3) << 2 |
> - extract32(inst, 2, 2) << 6;
> -}
> -
> -static uint32_t operand_cimmldsp(rv_inst inst)
> -{
> - return extract32(inst, 12, 1) << 5 |
> - extract32(inst, 5, 2) << 3 |
> - extract32(inst, 2, 3) << 6;
> -}
> -
> -static uint32_t operand_cimmlqsp(rv_inst inst)
> -{
> - return extract32(inst, 12, 1) << 5 |
> - extract32(inst, 6, 1) << 4 |
> - extract32(inst, 2, 4) << 6;
> -}
> -
> -static int32_t operand_cimm16sp(rv_inst inst)
> -{
> - return sextract32(inst, 12, 1) << 9 |
> - extract32(inst, 6, 1) << 4 |
> - extract32(inst, 5, 1) << 6 |
> - extract32(inst, 3, 2) << 7 |
> - extract32(inst, 2, 1) << 5;
> -}
> -
> -static int32_t operand_cimmj(rv_inst inst)
> -{
> - return sextract32(inst, 12, 1) << 11 |
> - extract32(inst, 11, 1) << 4 |
> - extract32(inst, 9, 2) << 8 |
> - extract32(inst, 8, 1) << 10 |
> - extract32(inst, 7, 1) << 6 |
> - extract32(inst, 6, 1) << 7 |
> - extract32(inst, 3, 3) << 1 |
> - extract32(inst, 2, 1) << 5;
> -}
> -
> -static int32_t operand_cimmb(rv_inst inst)
> -{
> - return sextract32(inst, 12, 1) << 8 |
> - extract32(inst, 10, 2) << 3 |
> - extract32(inst, 5, 2) << 6 |
> - extract32(inst, 3, 2) << 1 |
> - extract32(inst, 2, 1) << 5;
> -}
> -
> -static uint32_t operand_cimmswsp(rv_inst inst)
> -{
> - return extract32(inst, 9, 4) << 2 |
> - extract32(inst, 7, 2) << 6;
> -}
> -
> -static uint32_t operand_cimmsdsp(rv_inst inst)
> -{
> - return extract32(inst, 10, 3) << 3 |
> - extract32(inst, 7, 3) << 6;
> -}
> -
> -static uint32_t operand_cimmsqsp(rv_inst inst)
> -{
> - return extract32(inst, 11, 2) << 4 |
> - extract32(inst, 7, 4) << 6;
> -}
> -
> -static uint32_t operand_cimm4spn(rv_inst inst)
> -{
> - return extract32(inst, 11, 2) << 4 |
> - extract32(inst, 7, 4) << 6 |
> - extract32(inst, 6, 1) << 2 |
> - extract32(inst, 5, 1) << 3;
> -}
> -
> -static uint32_t operand_cimmw(rv_inst inst)
> -{
> - return extract32(inst, 10, 3) << 3 |
> - extract32(inst, 6, 1) << 2 |
> - extract32(inst, 5, 1) << 6;
> -}
> -
> -static uint32_t operand_cimmd(rv_inst inst)
> -{
> - return extract32(inst, 10, 3) << 3 |
> - extract32(inst, 5, 2) << 6;
> -}
> -
> -static uint32_t operand_cimmq(rv_inst inst)
> -{
> - return extract32(inst, 11, 2) << 4 |
> - extract32(inst, 10, 1) << 8 |
> - extract32(inst, 5, 2) << 6;
> -}
> -
> -static int32_t operand_vimm(rv_inst inst)
> -{
> - return sextract32(inst, 15, 5);
> -}
> -
> -static uint32_t operand_vuimm(rv_inst inst)
> -{
> - return extract32(inst, 15, 5);
> -}
> -
> -static uint32_t operand_vzimm11(rv_inst inst)
> -{
> - return extract32(inst, 20, 11);
> -}
> -
> -static uint32_t operand_vzimm10(rv_inst inst)
> -{
> - return extract32(inst, 20, 10);
> -}
> -
> -static uint32_t operand_vzimm6(rv_inst inst)
> -{
> - return extract32(inst, 26, 1) << 5 |
> - extract32(inst, 15, 5);
> -}
> -
> -static uint32_t operand_bs(rv_inst inst)
> -{
> - return extract32(inst, 30, 2);
> -}
> -
> -static uint32_t operand_rnum(rv_inst inst)
> -{
> - return extract32(inst, 20, 4);
> -}
> -
> -static uint32_t operand_vm(rv_inst inst)
> -{
> - return extract32(inst, 25, 1);
> -}
> -
> -static uint32_t operand_uimm_c_lb(rv_inst inst)
> -{
> - return extract32(inst, 5, 1) << 1 |
> - extract32(inst, 6, 1);
> -}
> -
> -static uint32_t operand_uimm_c_lh(rv_inst inst)
> -{
> - return extract32(inst, 5, 1) << 1;
> -}
> -
> -static uint32_t operand_zcmp_spimm(rv_inst inst)
> -{
> - return extract32(inst, 2, 2) << 4;
> -}
> -
> -static uint32_t operand_zcmp_rlist(rv_inst inst)
> -{
> - return extract32(inst, 4, 4);
> -}
> -
> -static uint32_t operand_imm6(rv_inst inst)
> -{
> - return extract32(inst, 20, 6);
> -}
> -
> -static uint32_t operand_imm2(rv_inst inst)
> -{
> - return extract32(inst, 25, 2);
> -}
> -
> -static uint32_t operand_immh(rv_inst inst)
> -{
> - return extract32(inst, 26, 6);
> -}
> -
> -static uint32_t operand_imml(rv_inst inst)
> -{
> - return extract32(inst, 20, 6);
> -}
> -
> -static uint32_t calculate_stack_adj(rv_isa isa, uint32_t rlist,
> uint32_t spimm)
> -{
> - int xlen_bytes_log2 = isa == rv64 ? 3 : 2;
> - int regs = rlist == 15 ? 13 : rlist - 3;
> - uint32_t stack_adj_base = ROUND_UP(regs << xlen_bytes_log2, 16);
> - return stack_adj_base + spimm;
> -}
> -
> -static uint32_t operand_zcmp_stack_adj(rv_inst inst, rv_isa isa)
> -{
> - return calculate_stack_adj(isa, operand_zcmp_rlist(inst),
> - operand_zcmp_spimm(inst));
> -}
> -
> -static uint32_t operand_tbl_index(rv_inst inst)
> -{
> - return extract32(inst, 2, 8);
> -}
> -
> -static uint32_t operand_lpl(rv_inst inst)
> -{
> - return extract32(inst, 12, 20);
> -}
> -
> /* decode operands */
>
> static void decode_inst_operands(rv_decode *dec, rv_isa isa)
^ permalink raw reply [flat|nested] 119+ messages in thread
* Re: [PATCH 07/56] disas/riscv: Reduce rv_insn to uint32_t
2026-08-09 22:34 ` [PATCH 07/56] disas/riscv: Reduce rv_insn to uint32_t Richard Henderson
2026-08-10 2:54 ` Philippe Mathieu-Daudé
@ 2026-08-11 19:59 ` Alistair
1 sibling, 0 replies; 119+ messages in thread
From: Alistair @ 2026-08-11 19:59 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: qemu-riscv
On Sun, 2026-08-09 at 15:34 -0700, Richard Henderson wrote:
> Since 758dce9c98a, the only possible values for
> instruction length are 2 and 4.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> disas/riscv.h | 2 +-
> disas/riscv.c | 12 +++---------
> 2 files changed, 4 insertions(+), 10 deletions(-)
>
> diff --git a/disas/riscv.h b/disas/riscv.h
> index 91ada8b531..eabe193b4f 100644
> --- a/disas/riscv.h
> +++ b/disas/riscv.h
> @@ -11,7 +11,7 @@
>
> /* types */
>
> -typedef uint64_t rv_inst;
> +typedef uint32_t rv_inst;
> typedef uint16_t rv_opcode;
>
> /* enums */
> diff --git a/disas/riscv.c b/disas/riscv.c
> index e3fbc26626..012f90fce6 100644
> --- a/disas/riscv.c
> +++ b/disas/riscv.c
> @@ -5491,10 +5491,8 @@ static GString *disasm_inst(rv_isa isa,
> uint64_t pc, rv_inst inst,
> return format_inst(24, &dec);
> }
>
> -#define INST_FMT_2 "%04" PRIx64 " "
> -#define INST_FMT_4 "%08" PRIx64 " "
> -#define INST_FMT_6 "%012" PRIx64 " "
> -#define INST_FMT_8 "%016" PRIx64 " "
> +#define INST_FMT_2 "%04x "
> +#define INST_FMT_4 "%08x "
>
> static int
> print_insn_riscv(bfd_vma memaddr, struct disassemble_info *info,
> rv_isa isa)
> @@ -5530,12 +5528,8 @@ print_insn_riscv(bfd_vma memaddr, struct
> disassemble_info *info, rv_isa isa)
> case 4:
> (*info->fprintf_func)(info->stream, INST_FMT_4, inst);
> break;
> - case 6:
> - (*info->fprintf_func)(info->stream, INST_FMT_6, inst);
> - break;
> default:
> - (*info->fprintf_func)(info->stream, INST_FMT_8, inst);
> - break;
> + g_assert_not_reached();
> }
> }
>
^ permalink raw reply [flat|nested] 119+ messages in thread
* Re: [PATCH 08/56] disas/riscv: Tidy dec initialization in disasm_inst
2026-08-09 22:34 ` [PATCH 08/56] disas/riscv: Tidy dec initialization in disasm_inst Richard Henderson
2026-08-10 2:54 ` Philippe Mathieu-Daudé
@ 2026-08-11 20:00 ` Alistair
1 sibling, 0 replies; 119+ messages in thread
From: Alistair @ 2026-08-11 20:00 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: qemu-riscv
On Sun, 2026-08-09 at 15:34 -0700, Richard Henderson wrote:
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> disas/riscv.c | 9 +++++----
> 1 file changed, 5 insertions(+), 4 deletions(-)
>
> diff --git a/disas/riscv.c b/disas/riscv.c
> index 012f90fce6..986dc6b752 100644
> --- a/disas/riscv.c
> +++ b/disas/riscv.c
> @@ -5441,10 +5441,11 @@ static void decode_inst_decompress(rv_decode
> *dec, rv_isa isa)
> static GString *disasm_inst(rv_isa isa, uint64_t pc, rv_inst inst,
> const RISCVCPUConfig *cfg)
> {
> - rv_decode dec = { 0 };
> - dec.pc = pc;
> - dec.inst = inst;
> - dec.cfg = cfg;
> + rv_decode dec = {
> + .pc = pc,
> + .inst = inst,
> + .cfg = cfg,
> + };
>
> static const struct {
> bool (*guard_func)(const RISCVCPUConfig *);
^ permalink raw reply [flat|nested] 119+ messages in thread
* Re: [PATCH 09/56] disas/riscv: Pass rv_opcode_data pointer to decode_inst_operands
2026-08-09 22:34 ` [PATCH 09/56] disas/riscv: Pass rv_opcode_data pointer to decode_inst_operands Richard Henderson
@ 2026-08-11 20:02 ` Alistair
0 siblings, 0 replies; 119+ messages in thread
From: Alistair @ 2026-08-11 20:02 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: qemu-riscv
On Sun, 2026-08-09 at 15:34 -0700, Richard Henderson wrote:
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> disas/riscv.c | 12 ++++++++----
> 1 file changed, 8 insertions(+), 4 deletions(-)
>
> diff --git a/disas/riscv.c b/disas/riscv.c
> index 986dc6b752..af43940732 100644
> --- a/disas/riscv.c
> +++ b/disas/riscv.c
> @@ -4595,11 +4595,12 @@ static void decode_inst_opcode(rv_decode
> *dec, rv_isa isa)
>
> /* decode operands */
>
> -static void decode_inst_operands(rv_decode *dec, rv_isa isa)
> +static void decode_inst_operands(rv_decode *dec, rv_isa isa,
> + const rv_opcode_data *op)
> {
> - const rv_opcode_data *opcode_data = dec->opcode_data;
> rv_inst inst = dec->inst;
> - dec->codec = opcode_data[dec->op].codec;
> +
> + dec->codec = op->codec;
> switch (dec->codec) {
> case rv_codec_none:
> dec->rd = dec->rs1 = dec->rs2 = rv_ireg_zero;
> @@ -5468,6 +5469,8 @@ static GString *disasm_inst(rv_isa isa,
> uint64_t pc, rv_inst inst,
> { has_xlrbr_p, rv_xlrbr_opcode_data, decode_xlrbr },
> };
>
> + const rv_opcode_data *op;
> +
> for (size_t i = 0; i < ARRAY_SIZE(decoders); i++) {
> bool (*guard_func)(const RISCVCPUConfig *) =
> decoders[i].guard_func;
> const rv_opcode_data *opcode_data = decoders[i].opcode_data;
> @@ -5486,7 +5489,8 @@ static GString *disasm_inst(rv_isa isa,
> uint64_t pc, rv_inst inst,
> dec.opcode_data = rvi_opcode_data;
> }
>
> - decode_inst_operands(&dec, isa);
> + op = &dec.opcode_data[dec.op];
> + decode_inst_operands(&dec, isa, op);
> decode_inst_decompress(&dec, isa);
> decode_inst_lift_pseudo(&dec);
> return format_inst(24, &dec);
^ permalink raw reply [flat|nested] 119+ messages in thread
* Re: [PATCH 10/56] disas/riscv: Pass rv_opcode_data pointer to/from decode_inst_decompress
2026-08-09 22:34 ` [PATCH 10/56] disas/riscv: Pass rv_opcode_data pointer to/from decode_inst_decompress Richard Henderson
@ 2026-08-11 20:04 ` Alistair
0 siblings, 0 replies; 119+ messages in thread
From: Alistair @ 2026-08-11 20:04 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: qemu-riscv
On Sun, 2026-08-09 at 15:34 -0700, Richard Henderson wrote:
> Unify 4 functions, sharing code.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> disas/riscv.c | 70 ++++++++++++++++---------------------------------
> --
> 1 file changed, 21 insertions(+), 49 deletions(-)
>
> diff --git a/disas/riscv.c b/disas/riscv.c
> index af43940732..47fae7316c 100644
> --- a/disas/riscv.c
> +++ b/disas/riscv.c
> @@ -5377,64 +5377,36 @@ static void decode_inst_lift_pseudo(rv_decode
> *dec)
>
> /* decompress instruction */
>
> -static void decode_inst_decompress_rv32(rv_decode *dec)
> +static const rv_opcode_data *decode_inst_decompress(rv_decode *dec,
> rv_isa isa,
> + const
> rv_opcode_data *op)
> {
> - const rv_opcode_data *opcode_data = dec->opcode_data;
> - int decomp_op = opcode_data[dec->op].decomp_rv32;
> - if (decomp_op != rv_op_illegal) {
> - if ((opcode_data[dec->op].decomp_data & rvcd_imm_nz)
> - && dec->imm == 0) {
> - dec->op = rv_op_illegal;
> - } else {
> - dec->op = decomp_op;
> - dec->codec = opcode_data[decomp_op].codec;
> - }
> - }
> -}
> + int decomp_op;
>
> -static void decode_inst_decompress_rv64(rv_decode *dec)
> -{
> - const rv_opcode_data *opcode_data = dec->opcode_data;
> - int decomp_op = opcode_data[dec->op].decomp_rv64;
> - if (decomp_op != rv_op_illegal) {
> - if ((opcode_data[dec->op].decomp_data & rvcd_imm_nz)
> - && dec->imm == 0) {
> - dec->op = rv_op_illegal;
> - } else {
> - dec->op = decomp_op;
> - dec->codec = opcode_data[decomp_op].codec;
> - }
> - }
> -}
> -
> -static void decode_inst_decompress_rv128(rv_decode *dec)
> -{
> - const rv_opcode_data *opcode_data = dec->opcode_data;
> - int decomp_op = opcode_data[dec->op].decomp_rv128;
> - if (decomp_op != rv_op_illegal) {
> - if ((opcode_data[dec->op].decomp_data & rvcd_imm_nz)
> - && dec->imm == 0) {
> - dec->op = rv_op_illegal;
> - } else {
> - dec->op = decomp_op;
> - dec->codec = opcode_data[decomp_op].codec;
> - }
> - }
> -}
> -
> -static void decode_inst_decompress(rv_decode *dec, rv_isa isa)
> -{
> switch (isa) {
> case rv32:
> - decode_inst_decompress_rv32(dec);
> + decomp_op = op->decomp_rv32;
> break;
> case rv64:
> - decode_inst_decompress_rv64(dec);
> + decomp_op = op->decomp_rv64;
> break;
> case rv128:
> - decode_inst_decompress_rv128(dec);
> + decomp_op = op->decomp_rv128;
> break;
> + default:
> + g_assert_not_reached();
> }
> +
> + if (decomp_op != rv_op_illegal) {
> + if ((op->decomp_data & rvcd_imm_nz) && dec->imm == 0) {
> + dec->opcode_data = rvi_opcode_data;
> + dec->op = rv_op_illegal;
> + } else {
> + dec->op = decomp_op;
> + }
> + op = &dec->opcode_data[decomp_op];
> + dec->codec = op->codec;
> + }
> + return op;
> }
>
> /* disassemble instruction */
> @@ -5491,7 +5463,7 @@ static GString *disasm_inst(rv_isa isa,
> uint64_t pc, rv_inst inst,
>
> op = &dec.opcode_data[dec.op];
> decode_inst_operands(&dec, isa, op);
> - decode_inst_decompress(&dec, isa);
> + op = decode_inst_decompress(&dec, isa, op);
> decode_inst_lift_pseudo(&dec);
> return format_inst(24, &dec);
> }
^ permalink raw reply [flat|nested] 119+ messages in thread
* Re: [PATCH 11/56] disas/riscv: Pass rv_opcode_data pointer to/from decode_inst_lift_pseudo
2026-08-09 22:35 ` [PATCH 11/56] disas/riscv: Pass rv_opcode_data pointer to/from decode_inst_lift_pseudo Richard Henderson
@ 2026-08-11 20:05 ` Alistair
0 siblings, 0 replies; 119+ messages in thread
From: Alistair @ 2026-08-11 20:05 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: qemu-riscv
On Sun, 2026-08-09 at 15:35 -0700, Richard Henderson wrote:
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> disas/riscv.c | 27 ++++++++++++++-------------
> 1 file changed, 14 insertions(+), 13 deletions(-)
>
> diff --git a/disas/riscv.c b/disas/riscv.c
> index 47fae7316c..0be2f07612 100644
> --- a/disas/riscv.c
> +++ b/disas/riscv.c
> @@ -5358,21 +5358,22 @@ static GString *format_inst(size_t tab,
> rv_decode *dec)
>
> /* lift instruction to pseudo-instruction */
>
> -static void decode_inst_lift_pseudo(rv_decode *dec)
> +static const rv_opcode_data *decode_inst_lift_pseudo(rv_decode *dec,
> + const
> rv_opcode_data *op)
> {
> - const rv_opcode_data *opcode_data = dec->opcode_data;
> - const rv_comp_data *comp_data = opcode_data[dec->op].pseudo;
> - if (!comp_data) {
> - return;
> - }
> - while (comp_data->constraints) {
> - if (check_constraints(dec, comp_data->constraints)) {
> - dec->op = comp_data->op;
> - dec->codec = opcode_data[dec->op].codec;
> - return;
> + const rv_comp_data *comp_data = op->pseudo;
> + if (comp_data) {
> + while (comp_data->constraints) {
> + if (check_constraints(dec, comp_data->constraints)) {
> + dec->op = comp_data->op;
> + op = &dec->opcode_data[dec->op];
> + dec->codec = op->codec;
> + break;
> + }
> + comp_data++;
> }
> - comp_data++;
> }
> + return op;
> }
>
> /* decompress instruction */
> @@ -5464,7 +5465,7 @@ static GString *disasm_inst(rv_isa isa,
> uint64_t pc, rv_inst inst,
> op = &dec.opcode_data[dec.op];
> decode_inst_operands(&dec, isa, op);
> op = decode_inst_decompress(&dec, isa, op);
> - decode_inst_lift_pseudo(&dec);
> + op = decode_inst_lift_pseudo(&dec, op);
> return format_inst(24, &dec);
> }
>
^ permalink raw reply [flat|nested] 119+ messages in thread
* Re: [PATCH 12/56] disas/riscv: Pass rv_opcode_data pointer to format_inst
2026-08-09 22:35 ` [PATCH 12/56] disas/riscv: Pass rv_opcode_data pointer to format_inst Richard Henderson
@ 2026-08-11 20:06 ` Alistair
0 siblings, 0 replies; 119+ messages in thread
From: Alistair @ 2026-08-11 20:06 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: qemu-riscv
On Sun, 2026-08-09 at 15:35 -0700, Richard Henderson wrote:
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> disas/riscv.c | 11 +++++------
> 1 file changed, 5 insertions(+), 6 deletions(-)
>
> diff --git a/disas/riscv.c b/disas/riscv.c
> index 0be2f07612..70ea41f125 100644
> --- a/disas/riscv.c
> +++ b/disas/riscv.c
> @@ -5111,17 +5111,16 @@ static size_t inst_length(rv_inst inst)
>
> /* format instruction */
>
> -static GString *format_inst(size_t tab, rv_decode *dec)
> +static GString *format_inst(size_t tab, rv_decode *dec,
> + const rv_opcode_data *op)
> {
> - const rv_opcode_data *opcode_data = dec->opcode_data;
> GString *buf = g_string_sized_new(64);
> - const char *fmt;
> + const char *fmt = op->format;
>
> - fmt = opcode_data[dec->op].format;
> while (*fmt) {
> switch (*fmt) {
> case 'O':
> - g_string_append(buf, opcode_data[dec->op].name);
> + g_string_append(buf, op->name);
> break;
> case '(':
> case ',':
> @@ -5466,7 +5465,7 @@ static GString *disasm_inst(rv_isa isa,
> uint64_t pc, rv_inst inst,
> decode_inst_operands(&dec, isa, op);
> op = decode_inst_decompress(&dec, isa, op);
> op = decode_inst_lift_pseudo(&dec, op);
> - return format_inst(24, &dec);
> + return format_inst(24, &dec, op);
> }
>
> #define INST_FMT_2 "%04x "
^ permalink raw reply [flat|nested] 119+ messages in thread
* Re: [PATCH 13/56] disas/riscv: Tidy disasm_inst main loop
2026-08-09 22:35 ` [PATCH 13/56] disas/riscv: Tidy disasm_inst main loop Richard Henderson
@ 2026-08-11 20:08 ` Alistair
0 siblings, 0 replies; 119+ messages in thread
From: Alistair @ 2026-08-11 20:08 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: qemu-riscv
On Sun, 2026-08-09 at 15:35 -0700, Richard Henderson wrote:
> Unroll first iteration, so that always_true_p is not used,
> Drop some local variables and use 'decoders' directly.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> disas/riscv.c | 63 +++++++++++++++++++++++++------------------------
> --
> 1 file changed, 31 insertions(+), 32 deletions(-)
>
> diff --git a/disas/riscv.c b/disas/riscv.c
> index 70ea41f125..9880b8de20 100644
> --- a/disas/riscv.c
> +++ b/disas/riscv.c
> @@ -5419,41 +5419,40 @@ static GString *disasm_inst(rv_isa isa,
> uint64_t pc, rv_inst inst,
> .inst = inst,
> .cfg = cfg,
> };
> -
> - static const struct {
> - bool (*guard_func)(const RISCVCPUConfig *);
> - const rv_opcode_data *opcode_data;
> - void (*decode_func)(rv_decode *, rv_isa);
> - } decoders[] = {
> - { always_true_p, rvi_opcode_data, decode_inst_opcode },
> - { has_xtheadba_p, xthead_opcode_data, decode_xtheadba },
> - { has_xtheadbb_p, xthead_opcode_data, decode_xtheadbb },
> - { has_xtheadbs_p, xthead_opcode_data, decode_xtheadbs },
> - { has_xtheadcmo_p, xthead_opcode_data, decode_xtheadcmo },
> - { has_xtheadcondmov_p, xthead_opcode_data,
> decode_xtheadcondmov },
> - { has_xtheadfmemidx_p, xthead_opcode_data,
> decode_xtheadfmemidx },
> - { has_xtheadfmv_p, xthead_opcode_data, decode_xtheadfmv },
> - { has_xtheadmac_p, xthead_opcode_data, decode_xtheadmac },
> - { has_xtheadmemidx_p, xthead_opcode_data,
> decode_xtheadmemidx },
> - { has_xtheadmempair_p, xthead_opcode_data,
> decode_xtheadmempair },
> - { has_xtheadsync_p, xthead_opcode_data, decode_xtheadsync },
> - { has_XVentanaCondOps_p, ventana_opcode_data,
> decode_xventanacondops },
> - { has_xlrbr_p, rv_xlrbr_opcode_data, decode_xlrbr },
> - };
> -
> const rv_opcode_data *op;
>
> - for (size_t i = 0; i < ARRAY_SIZE(decoders); i++) {
> - bool (*guard_func)(const RISCVCPUConfig *) =
> decoders[i].guard_func;
> - const rv_opcode_data *opcode_data = decoders[i].opcode_data;
> - void (*decode_func)(rv_decode *, rv_isa) =
> decoders[i].decode_func;
> + dec.opcode_data = rvi_opcode_data;
> + decode_inst_opcode(&dec, isa);
>
> - /* always_true_p don't dereference cfg */
> - if (((i == 0) || cfg) && guard_func(cfg)) {
> - dec.opcode_data = opcode_data;
> - decode_func(&dec, isa);
> - if (dec.op != rv_op_illegal)
> - break;
> + if (dec.op == rv_op_illegal && cfg) {
> + static const struct {
> + bool (*guard_func)(const RISCVCPUConfig *);
> + const rv_opcode_data *opcode_data;
> + void (*decode_func)(rv_decode *, rv_isa);
> + } decoders[] = {
> + { has_xtheadba_p, xthead_opcode_data, decode_xtheadba },
> + { has_xtheadbb_p, xthead_opcode_data, decode_xtheadbb },
> + { has_xtheadbs_p, xthead_opcode_data, decode_xtheadbs },
> + { has_xtheadcmo_p, xthead_opcode_data, decode_xtheadcmo
> },
> + { has_xtheadcondmov_p, xthead_opcode_data,
> decode_xtheadcondmov },
> + { has_xtheadfmemidx_p, xthead_opcode_data,
> decode_xtheadfmemidx },
> + { has_xtheadfmv_p, xthead_opcode_data, decode_xtheadfmv
> },
> + { has_xtheadmac_p, xthead_opcode_data, decode_xtheadmac
> },
> + { has_xtheadmemidx_p, xthead_opcode_data,
> decode_xtheadmemidx },
> + { has_xtheadmempair_p, xthead_opcode_data,
> decode_xtheadmempair },
> + { has_xtheadsync_p, xthead_opcode_data,
> decode_xtheadsync },
> + { has_XVentanaCondOps_p, ventana_opcode_data,
> decode_xventanacondops },
> + { has_xlrbr_p, rv_xlrbr_opcode_data, decode_xlrbr },
> + };
> +
> + for (size_t i = 0; i < ARRAY_SIZE(decoders); i++) {
> + if (decoders[i].guard_func(cfg)) {
> + dec.opcode_data = decoders[i].opcode_data;
> + decoders[i].decode_func(&dec, isa);
> + if (dec.op != rv_op_illegal) {
> + break;
> + }
> + }
> }
> }
>
^ permalink raw reply [flat|nested] 119+ messages in thread
* Re: [PATCH 14/56] disas/riscv: Set dec->opcode_data in decode function
2026-08-09 22:35 ` [PATCH 14/56] disas/riscv: Set dec->opcode_data in decode function Richard Henderson
@ 2026-08-11 20:09 ` Alistair
0 siblings, 0 replies; 119+ messages in thread
From: Alistair @ 2026-08-11 20:09 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: qemu-riscv
On Sun, 2026-08-09 at 15:35 -0700, Richard Henderson wrote:
> This allows each opcode table to be private to the decode file.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> disas/riscv-xlrbr.h | 2 --
> disas/riscv-xthead.h | 2 --
> disas/riscv-xventana.h | 2 --
> disas/riscv-xlrbr.c | 4 +++-
> disas/riscv-xthead.c | 13 ++++++++++++-
> disas/riscv-xventana.c | 3 ++-
> disas/riscv.c | 34 +++++++++++++++++-----------------
> 7 files changed, 34 insertions(+), 26 deletions(-)
>
> diff --git a/disas/riscv-xlrbr.h b/disas/riscv-xlrbr.h
> index 939a69ea6d..ebf3d4c133 100644
> --- a/disas/riscv-xlrbr.h
> +++ b/disas/riscv-xlrbr.h
> @@ -12,8 +12,6 @@
>
> #include "disas/riscv.h"
>
> -extern const rv_opcode_data rv_xlrbr_opcode_data[];
> -
> void decode_xlrbr(rv_decode *, rv_isa);
>
> #endif /* DISAS_RISCV_XLRBR_H */
> diff --git a/disas/riscv-xthead.h b/disas/riscv-xthead.h
> index fcd42746e7..0c65c8e0af 100644
> --- a/disas/riscv-xthead.h
> +++ b/disas/riscv-xthead.h
> @@ -11,8 +11,6 @@
>
> #include "disas/riscv.h"
>
> -extern const rv_opcode_data xthead_opcode_data[];
> -
> void decode_xtheadba(rv_decode *, rv_isa);
> void decode_xtheadbb(rv_decode *, rv_isa);
> void decode_xtheadbs(rv_decode *, rv_isa);
> diff --git a/disas/riscv-xventana.h b/disas/riscv-xventana.h
> index 72be9ffa16..1006c3be00 100644
> --- a/disas/riscv-xventana.h
> +++ b/disas/riscv-xventana.h
> @@ -11,8 +11,6 @@
>
> #include "disas/riscv.h"
>
> -extern const rv_opcode_data ventana_opcode_data[];
> -
> void decode_xventanacondops(rv_decode*, rv_isa);
>
> #endif /* DISAS_RISCV_XVENTANA_H */
> diff --git a/disas/riscv-xlrbr.c b/disas/riscv-xlrbr.c
> index 57cb434523..f61028fce9 100644
> --- a/disas/riscv-xlrbr.c
> +++ b/disas/riscv-xlrbr.c
> @@ -24,7 +24,7 @@ typedef enum {
> rv_op_crc32c_d = 8,
> } rv_xlrbr_op;
>
> -const rv_opcode_data rv_xlrbr_opcode_data[] = {
> +static const rv_opcode_data xlrbr_opcode_data[] = {
> { "illegal", rv_codec_illegal, rv_fmt_none, NULL, 0, 0, 0 },
> { "crc32.b", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
> { "crc32.h", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
> @@ -75,5 +75,7 @@ void decode_xlrbr(rv_decode *dec, rv_isa isa)
> }
> break;
> }
> +
> + dec->opcode_data = xlrbr_opcode_data;
> dec->op = op;
> }
> diff --git a/disas/riscv-xthead.c b/disas/riscv-xthead.c
> index 2f2ddb8dd9..96f80bc8e5 100644
> --- a/disas/riscv-xthead.c
> +++ b/disas/riscv-xthead.c
> @@ -127,7 +127,7 @@ typedef enum {
> rv_op_th_sync_s,
> } rv_xthead_op;
>
> -const rv_opcode_data xthead_opcode_data[] = {
> +static const rv_opcode_data xthead_opcode_data[] = {
> { "th.illegal", rv_codec_illegal, rv_fmt_none, NULL, 0, 0, 0 },
> /* XTheadBa */
> { "th.addsl", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0,
> 0, 0 },
> @@ -272,6 +272,7 @@ void decode_xtheadba(rv_decode *dec, rv_isa isa)
> break;
> }
>
> + dec->opcode_data = xthead_opcode_data;
> dec->op = op;
> }
>
> @@ -330,6 +331,7 @@ void decode_xtheadbb(rv_decode *dec, rv_isa isa)
> break;
> }
>
> + dec->opcode_data = xthead_opcode_data;
> dec->op = op;
> }
>
> @@ -356,6 +358,7 @@ void decode_xtheadbs(rv_decode *dec, rv_isa isa)
> break;
> }
>
> + dec->opcode_data = xthead_opcode_data;
> dec->op = op;
> }
>
> @@ -434,6 +437,7 @@ void decode_xtheadcmo(rv_decode *dec, rv_isa isa)
> break;
> }
>
> + dec->opcode_data = xthead_opcode_data;
> dec->op = op;
> }
>
> @@ -461,6 +465,7 @@ void decode_xtheadcondmov(rv_decode *dec, rv_isa
> isa)
> break;
> }
>
> + dec->opcode_data = xthead_opcode_data;
> dec->op = op;
> }
>
> @@ -498,6 +503,7 @@ void decode_xtheadfmemidx(rv_decode *dec, rv_isa
> isa)
> break;
> }
>
> + dec->opcode_data = xthead_opcode_data;
> dec->op = op;
> }
>
> @@ -533,6 +539,7 @@ void decode_xtheadfmv(rv_decode *dec, rv_isa isa)
> break;
> }
>
> + dec->opcode_data = xthead_opcode_data;
> dec->op = op;
> }
>
> @@ -564,6 +571,7 @@ void decode_xtheadmac(rv_decode *dec, rv_isa isa)
> break;
> }
>
> + dec->opcode_data = xthead_opcode_data;
> dec->op = op;
> }
>
> @@ -638,6 +646,7 @@ void decode_xtheadmemidx(rv_decode *dec, rv_isa
> isa)
> break;
> }
>
> + dec->opcode_data = xthead_opcode_data;
> dec->op = op;
> }
>
> @@ -672,6 +681,7 @@ void decode_xtheadmempair(rv_decode *dec, rv_isa
> isa)
> break;
> }
>
> + dec->opcode_data = xthead_opcode_data;
> dec->op = op;
> }
>
> @@ -706,5 +716,6 @@ void decode_xtheadsync(rv_decode *dec, rv_isa
> isa)
> break;
> }
>
> + dec->opcode_data = xthead_opcode_data;
> dec->op = op;
> }
> diff --git a/disas/riscv-xventana.c b/disas/riscv-xventana.c
> index cd694f15f3..4539173d95 100644
> --- a/disas/riscv-xventana.c
> +++ b/disas/riscv-xventana.c
> @@ -14,7 +14,7 @@ typedef enum {
> ventana_op_vt_maskcn = 2,
> } rv_ventana_op;
>
> -const rv_opcode_data ventana_opcode_data[] = {
> +static const rv_opcode_data ventana_opcode_data[] = {
> { "vt.illegal", rv_codec_illegal, rv_fmt_none, NULL, 0, 0, 0 },
> { "vt.maskc", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
> { "vt.maskcn", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
> @@ -38,5 +38,6 @@ void decode_xventanacondops(rv_decode *dec, rv_isa
> isa)
> break;
> }
>
> + dec->opcode_data = ventana_opcode_data;
> dec->op = op;
> }
> diff --git a/disas/riscv.c b/disas/riscv.c
> index 9880b8de20..eb6d132a2c 100644
> --- a/disas/riscv.c
> +++ b/disas/riscv.c
> @@ -1656,7 +1656,7 @@ static uint32_t operand_lpl(rv_inst inst)
>
> /* instruction metadata */
>
> -const rv_opcode_data rvi_opcode_data[] = {
> +static const rv_opcode_data rvi_opcode_data[] = {
> { "illegal", rv_codec_illegal, rv_fmt_none, NULL, 0, 0, 0 },
> { "lui", rv_codec_u, rv_fmt_rd_uimm, NULL, 0, 0, 0 },
> { "auipc", rv_codec_u, rv_fmt_rd_uoffset, NULL, 0, 0, 0 },
> @@ -2948,6 +2948,7 @@ static void decode_inst_opcode(rv_decode *dec,
> rv_isa isa)
> {
> rv_inst inst = dec->inst;
> rv_opcode op = rv_op_illegal;
> +
> switch ((inst >> 0) & 0b11) {
> case 0:
> switch ((inst >> 13) & 0b111) {
> @@ -4590,6 +4591,8 @@ static void decode_inst_opcode(rv_decode *dec,
> rv_isa isa)
> }
> break;
> }
> +
> + dec->opcode_data = rvi_opcode_data;
> dec->op = op;
> }
>
> @@ -5421,33 +5424,30 @@ static GString *disasm_inst(rv_isa isa,
> uint64_t pc, rv_inst inst,
> };
> const rv_opcode_data *op;
>
> - dec.opcode_data = rvi_opcode_data;
> decode_inst_opcode(&dec, isa);
>
> if (dec.op == rv_op_illegal && cfg) {
> static const struct {
> bool (*guard_func)(const RISCVCPUConfig *);
> - const rv_opcode_data *opcode_data;
> void (*decode_func)(rv_decode *, rv_isa);
> } decoders[] = {
> - { has_xtheadba_p, xthead_opcode_data, decode_xtheadba },
> - { has_xtheadbb_p, xthead_opcode_data, decode_xtheadbb },
> - { has_xtheadbs_p, xthead_opcode_data, decode_xtheadbs },
> - { has_xtheadcmo_p, xthead_opcode_data, decode_xtheadcmo
> },
> - { has_xtheadcondmov_p, xthead_opcode_data,
> decode_xtheadcondmov },
> - { has_xtheadfmemidx_p, xthead_opcode_data,
> decode_xtheadfmemidx },
> - { has_xtheadfmv_p, xthead_opcode_data, decode_xtheadfmv
> },
> - { has_xtheadmac_p, xthead_opcode_data, decode_xtheadmac
> },
> - { has_xtheadmemidx_p, xthead_opcode_data,
> decode_xtheadmemidx },
> - { has_xtheadmempair_p, xthead_opcode_data,
> decode_xtheadmempair },
> - { has_xtheadsync_p, xthead_opcode_data,
> decode_xtheadsync },
> - { has_XVentanaCondOps_p, ventana_opcode_data,
> decode_xventanacondops },
> - { has_xlrbr_p, rv_xlrbr_opcode_data, decode_xlrbr },
> + { has_xtheadba_p, decode_xtheadba },
> + { has_xtheadbb_p, decode_xtheadbb },
> + { has_xtheadbs_p, decode_xtheadbs },
> + { has_xtheadcmo_p, decode_xtheadcmo },
> + { has_xtheadcondmov_p, decode_xtheadcondmov },
> + { has_xtheadfmemidx_p, decode_xtheadfmemidx },
> + { has_xtheadfmv_p, decode_xtheadfmv },
> + { has_xtheadmac_p, decode_xtheadmac },
> + { has_xtheadmemidx_p, decode_xtheadmemidx },
> + { has_xtheadmempair_p, decode_xtheadmempair },
> + { has_xtheadsync_p, decode_xtheadsync },
> + { has_XVentanaCondOps_p, decode_xventanacondops },
> + { has_xlrbr_p, decode_xlrbr },
> };
>
> for (size_t i = 0; i < ARRAY_SIZE(decoders); i++) {
> if (decoders[i].guard_func(cfg)) {
> - dec.opcode_data = decoders[i].opcode_data;
> decoders[i].decode_func(&dec, isa);
> if (dec.op != rv_op_illegal) {
> break;
^ permalink raw reply [flat|nested] 119+ messages in thread
* Re: [PATCH 15/56] disas/riscv: Drop explicit zero of rv_opcode_data fields
2026-08-09 22:35 ` [PATCH 15/56] disas/riscv: Drop explicit zero of rv_opcode_data fields Richard Henderson
@ 2026-08-11 20:10 ` Alistair
0 siblings, 0 replies; 119+ messages in thread
From: Alistair @ 2026-08-11 20:10 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: qemu-riscv
On Sun, 2026-08-09 at 15:35 -0700, Richard Henderson wrote:
> Mechanical
>
> s/, NULL, 0, 0, 0 }/ }/
> s/, 0, 0, 0 }/ }/
> s/, NULL, 0, 0 }/ }/
> s/, NULL, 0 }/ }/
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> disas/riscv-xlrbr.c | 18 +-
> disas/riscv-xthead.c | 210 ++---
> disas/riscv-xventana.c | 6 +-
> disas/riscv.c | 1826 ++++++++++++++++++++------------------
> --
> 4 files changed, 1030 insertions(+), 1030 deletions(-)
>
> diff --git a/disas/riscv-xlrbr.c b/disas/riscv-xlrbr.c
> index f61028fce9..d0092e9edd 100644
> --- a/disas/riscv-xlrbr.c
> +++ b/disas/riscv-xlrbr.c
> @@ -25,15 +25,15 @@ typedef enum {
> } rv_xlrbr_op;
>
> static const rv_opcode_data xlrbr_opcode_data[] = {
> - { "illegal", rv_codec_illegal, rv_fmt_none, NULL, 0, 0, 0 },
> - { "crc32.b", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
> - { "crc32.h", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
> - { "crc32.w", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
> - { "crc32.d", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
> - { "crc32c.b", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
> - { "crc32c.h", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
> - { "crc32c.w", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
> - { "crc32c.d", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
> + { "illegal", rv_codec_illegal, rv_fmt_none },
> + { "crc32.b", rv_codec_r, rv_fmt_rd_rs1 },
> + { "crc32.h", rv_codec_r, rv_fmt_rd_rs1 },
> + { "crc32.w", rv_codec_r, rv_fmt_rd_rs1 },
> + { "crc32.d", rv_codec_r, rv_fmt_rd_rs1 },
> + { "crc32c.b", rv_codec_r, rv_fmt_rd_rs1 },
> + { "crc32c.h", rv_codec_r, rv_fmt_rd_rs1 },
> + { "crc32c.w", rv_codec_r, rv_fmt_rd_rs1 },
> + { "crc32c.d", rv_codec_r, rv_fmt_rd_rs1 },
> };
>
> void decode_xlrbr(rv_decode *dec, rv_isa isa)
> diff --git a/disas/riscv-xthead.c b/disas/riscv-xthead.c
> index 96f80bc8e5..757d6ff39f 100644
> --- a/disas/riscv-xthead.c
> +++ b/disas/riscv-xthead.c
> @@ -128,122 +128,122 @@ typedef enum {
> } rv_xthead_op;
>
> static const rv_opcode_data xthead_opcode_data[] = {
> - { "th.illegal", rv_codec_illegal, rv_fmt_none, NULL, 0, 0, 0 },
> + { "th.illegal", rv_codec_illegal, rv_fmt_none },
> /* XTheadBa */
> - { "th.addsl", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0,
> 0, 0 },
> + { "th.addsl", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm },
> /* XTheadBb */
> - { "th.srri", rv_codec_r2_imm6, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0
> },
> - { "th.srriw", rv_codec_r2_imm5, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0
> },
> - { "th.ext", rv_codec_r2_immhl, rv_fmt_rd_rs1_immh_imml, NULL, 0,
> 0, 0 },
> - { "th.extu", rv_codec_r2_immhl, rv_fmt_rd_rs1_immh_imml, NULL,
> 0, 0, 0 },
> - { "th.ff0", rv_codec_r2, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
> - { "th.ff1", rv_codec_r2, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
> - { "th.rev", rv_codec_r2, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
> - { "th.revw", rv_codec_r2, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
> - { "th.tstnbz", rv_codec_r2, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
> + { "th.srri", rv_codec_r2_imm6, rv_fmt_rd_rs1_imm },
> + { "th.srriw", rv_codec_r2_imm5, rv_fmt_rd_rs1_imm },
> + { "th.ext", rv_codec_r2_immhl, rv_fmt_rd_rs1_immh_imml },
> + { "th.extu", rv_codec_r2_immhl, rv_fmt_rd_rs1_immh_imml },
> + { "th.ff0", rv_codec_r2, rv_fmt_rd_rs1 },
> + { "th.ff1", rv_codec_r2, rv_fmt_rd_rs1 },
> + { "th.rev", rv_codec_r2, rv_fmt_rd_rs1 },
> + { "th.revw", rv_codec_r2, rv_fmt_rd_rs1 },
> + { "th.tstnbz", rv_codec_r2, rv_fmt_rd_rs1 },
> /* XTheadBs */
> - { "th.tst", rv_codec_r2_imm6, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0
> },
> + { "th.tst", rv_codec_r2_imm6, rv_fmt_rd_rs1_imm },
> /* XTheadCmo */
> - { "th.dcache.call", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
> - { "th.dcache.ciall", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0
> },
> - { "th.dcache.iall", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
> - { "th.dcache.cpa", rv_codec_r, rv_fmt_rs1, NULL, 0, 0, 0 },
> - { "th.dcache.cipa", rv_codec_r, rv_fmt_rs1, NULL, 0, 0, 0 },
> - { "th.dcache.ipa", rv_codec_r, rv_fmt_rs1, NULL, 0, 0, 0 },
> - { "th.dcache.cva", rv_codec_r, rv_fmt_rs1, NULL, 0, 0, 0 },
> - { "th.dcache.civa", rv_codec_r, rv_fmt_rs1, NULL, 0, 0, 0 },
> - { "th.dcache.iva", rv_codec_r, rv_fmt_rs1, NULL, 0, 0, 0 },
> - { "th.dcache.csw", rv_codec_r, rv_fmt_rs1, NULL, 0, 0, 0 },
> - { "th.dcache.cisw", rv_codec_r, rv_fmt_rs1, NULL, 0, 0, 0 },
> - { "th.dcache.isw", rv_codec_r, rv_fmt_rs1, NULL, 0, 0, 0 },
> - { "th.dcache.cpal1", rv_codec_r, rv_fmt_rs1, NULL, 0, 0, 0 },
> - { "th.dcache.cval1", rv_codec_r, rv_fmt_rs1, NULL, 0, 0, 0 },
> - { "th.icache.iall", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
> - { "th.icache.ialls", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0
> },
> - { "th.icache.ipa", rv_codec_r, rv_fmt_rs1, NULL, 0, 0, 0 },
> - { "th.icache.iva", rv_codec_r, rv_fmt_rs1, NULL, 0, 0, 0 },
> - { "th.l2cache.call", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0
> },
> - { "th.l2cache.ciall", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0
> },
> - { "th.l2cache.iall", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0
> },
> + { "th.dcache.call", rv_codec_none, rv_fmt_none },
> + { "th.dcache.ciall", rv_codec_none, rv_fmt_none },
> + { "th.dcache.iall", rv_codec_none, rv_fmt_none },
> + { "th.dcache.cpa", rv_codec_r, rv_fmt_rs1 },
> + { "th.dcache.cipa", rv_codec_r, rv_fmt_rs1 },
> + { "th.dcache.ipa", rv_codec_r, rv_fmt_rs1 },
> + { "th.dcache.cva", rv_codec_r, rv_fmt_rs1 },
> + { "th.dcache.civa", rv_codec_r, rv_fmt_rs1 },
> + { "th.dcache.iva", rv_codec_r, rv_fmt_rs1 },
> + { "th.dcache.csw", rv_codec_r, rv_fmt_rs1 },
> + { "th.dcache.cisw", rv_codec_r, rv_fmt_rs1 },
> + { "th.dcache.isw", rv_codec_r, rv_fmt_rs1 },
> + { "th.dcache.cpal1", rv_codec_r, rv_fmt_rs1 },
> + { "th.dcache.cval1", rv_codec_r, rv_fmt_rs1 },
> + { "th.icache.iall", rv_codec_none, rv_fmt_none },
> + { "th.icache.ialls", rv_codec_none, rv_fmt_none },
> + { "th.icache.ipa", rv_codec_r, rv_fmt_rs1 },
> + { "th.icache.iva", rv_codec_r, rv_fmt_rs1 },
> + { "th.l2cache.call", rv_codec_none, rv_fmt_none },
> + { "th.l2cache.ciall", rv_codec_none, rv_fmt_none },
> + { "th.l2cache.iall", rv_codec_none, rv_fmt_none },
> /* XTheadCondMov */
> - { "th.mveqz", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
> - { "th.mvnez", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
> + { "th.mveqz", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> + { "th.mvnez", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> /* XTheadFMemIdx */
> - { "th.flrd", rv_codec_r_imm2, rv_fmt_frd_rs1_rs2_imm, NULL, 0,
> 0, 0 },
> - { "th.flrw", rv_codec_r_imm2, rv_fmt_frd_rs1_rs2_imm, NULL, 0,
> 0, 0 },
> - { "th.flurd", rv_codec_r_imm2, rv_fmt_frd_rs1_rs2_imm, NULL, 0,
> 0, 0 },
> - { "th.flurw", rv_codec_r_imm2, rv_fmt_frd_rs1_rs2_imm, NULL, 0,
> 0, 0 },
> - { "th.fsrd", rv_codec_r_imm2, rv_fmt_frd_rs1_rs2_imm, NULL, 0,
> 0, 0 },
> - { "th.fsrw", rv_codec_r_imm2, rv_fmt_frd_rs1_rs2_imm, NULL, 0,
> 0, 0 },
> - { "th.fsurd", rv_codec_r_imm2, rv_fmt_frd_rs1_rs2_imm, NULL, 0,
> 0, 0 },
> - { "th.fsurw", rv_codec_r_imm2, rv_fmt_frd_rs1_rs2_imm, NULL, 0,
> 0, 0 },
> + { "th.flrd", rv_codec_r_imm2, rv_fmt_frd_rs1_rs2_imm },
> + { "th.flrw", rv_codec_r_imm2, rv_fmt_frd_rs1_rs2_imm },
> + { "th.flurd", rv_codec_r_imm2, rv_fmt_frd_rs1_rs2_imm },
> + { "th.flurw", rv_codec_r_imm2, rv_fmt_frd_rs1_rs2_imm },
> + { "th.fsrd", rv_codec_r_imm2, rv_fmt_frd_rs1_rs2_imm },
> + { "th.fsrw", rv_codec_r_imm2, rv_fmt_frd_rs1_rs2_imm },
> + { "th.fsurd", rv_codec_r_imm2, rv_fmt_frd_rs1_rs2_imm },
> + { "th.fsurw", rv_codec_r_imm2, rv_fmt_frd_rs1_rs2_imm },
> /* XTheadFmv */
> - { "th.fmv.hw.x", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 },
> - { "th.fmv.x.hw", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 },
> + { "th.fmv.hw.x", rv_codec_r, rv_fmt_rd_frs1 },
> + { "th.fmv.x.hw", rv_codec_r, rv_fmt_rd_frs1 },
> /* XTheadMac */
> - { "th.mula", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
> - { "th.mulaw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
> - { "th.mulah", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
> - { "th.muls", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
> - { "th.mulsw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
> - { "th.mulsh", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
> + { "th.mula", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> + { "th.mulaw", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> + { "th.mulah", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> + { "th.muls", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> + { "th.mulsw", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> + { "th.mulsh", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> /* XTheadMemIdx */
> - { "th.lbia", rv_codec_r2_imm2_imm5,
> rv_fmt_rd_rs1_immh_imml_addr, NULL, 0, 0, 0 },
> - { "th.lbib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml,
> NULL, 0, 0, 0 },
> - { "th.lbuia", rv_codec_r2_imm2_imm5,
> rv_fmt_rd_rs1_immh_imml_addr, NULL, 0, 0, 0 },
> - { "th.lbuib", rv_codec_r2_imm2_imm5,
> rv_fmt_rd_rs1_immh_imml_addr, NULL, 0, 0, 0 },
> - { "th.lhia", rv_codec_r2_imm2_imm5,
> rv_fmt_rd_rs1_immh_imml_addr, NULL, 0, 0, 0 },
> - { "th.lhib", rv_codec_r2_imm2_imm5,
> rv_fmt_rd_rs1_immh_imml_addr, NULL, 0, 0, 0 },
> - { "th.lhuia", rv_codec_r2_imm2_imm5,
> rv_fmt_rd_rs1_immh_imml_addr, NULL, 0, 0, 0 },
> - { "th.lhuib", rv_codec_r2_imm2_imm5,
> rv_fmt_rd_rs1_immh_imml_addr, NULL, 0, 0, 0 },
> - { "th.lwia", rv_codec_r2_imm2_imm5,
> rv_fmt_rd_rs1_immh_imml_addr, NULL, 0, 0, 0 },
> - { "th.lwib", rv_codec_r2_imm2_imm5,
> rv_fmt_rd_rs1_immh_imml_addr, NULL, 0, 0, 0 },
> - { "th.lwuia", rv_codec_r2_imm2_imm5,
> rv_fmt_rd_rs1_immh_imml_addr, NULL, 0, 0, 0 },
> - { "th.lwuib", rv_codec_r2_imm2_imm5,
> rv_fmt_rd_rs1_immh_imml_addr, NULL, 0, 0, 0 },
> - { "th.ldia", rv_codec_r2_imm2_imm5,
> rv_fmt_rd_rs1_immh_imml_addr, NULL, 0, 0, 0 },
> - { "th.ldib", rv_codec_r2_imm2_imm5,
> rv_fmt_rd_rs1_immh_imml_addr, NULL, 0, 0, 0 },
> - { "th.sbia", rv_codec_r2_imm2_imm5,
> rv_fmt_rd_rs1_immh_imml_addr, NULL, 0, 0, 0 },
> - { "th.sbib", rv_codec_r2_imm2_imm5,
> rv_fmt_rd_rs1_immh_imml_addr, NULL, 0, 0, 0 },
> - { "th.shia", rv_codec_r2_imm2_imm5,
> rv_fmt_rd_rs1_immh_imml_addr, NULL, 0, 0, 0 },
> - { "th.shib", rv_codec_r2_imm2_imm5,
> rv_fmt_rd_rs1_immh_imml_addr, NULL, 0, 0, 0 },
> - { "th.swia", rv_codec_r2_imm2_imm5,
> rv_fmt_rd_rs1_immh_imml_addr, NULL, 0, 0, 0 },
> - { "th.swib", rv_codec_r2_imm2_imm5,
> rv_fmt_rd_rs1_immh_imml_addr, NULL, 0, 0, 0 },
> - { "th.sdia", rv_codec_r2_imm2_imm5,
> rv_fmt_rd_rs1_immh_imml_addr, NULL, 0, 0, 0 },
> - { "th.sdib", rv_codec_r2_imm2_imm5,
> rv_fmt_rd_rs1_immh_imml_addr, NULL, 0, 0, 0 },
> - { "th.lrb", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0,
> 0 },
> - { "th.lrbu", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0,
> 0 },
> - { "th.lrh", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0,
> 0 },
> - { "th.lrhu", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0,
> 0 },
> - { "th.lrw", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0,
> 0 },
> - { "th.lrwu", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0,
> 0 },
> - { "th.lrd", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0,
> 0 },
> - { "th.srb", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0,
> 0 },
> - { "th.srh", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0,
> 0 },
> - { "th.srw", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0,
> 0 },
> - { "th.srd", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0,
> 0 },
> - { "th.lurb", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0,
> 0 },
> - { "th.lurbu", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0,
> 0, 0 },
> - { "th.lurh", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0,
> 0 },
> - { "th.lurhu", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0,
> 0, 0 },
> - { "th.lurw", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0,
> 0 },
> - { "th.lurwu", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0,
> 0, 0 },
> - { "th.lurd", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0,
> 0 },
> - { "th.surb", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0,
> 0 },
> - { "th.surh", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0,
> 0 },
> - { "th.surw", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0,
> 0 },
> - { "th.surd", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0,
> 0 },
> + { "th.lbia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr
> },
> + { "th.lbib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml },
> + { "th.lbuia", rv_codec_r2_imm2_imm5,
> rv_fmt_rd_rs1_immh_imml_addr },
> + { "th.lbuib", rv_codec_r2_imm2_imm5,
> rv_fmt_rd_rs1_immh_imml_addr },
> + { "th.lhia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr
> },
> + { "th.lhib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr
> },
> + { "th.lhuia", rv_codec_r2_imm2_imm5,
> rv_fmt_rd_rs1_immh_imml_addr },
> + { "th.lhuib", rv_codec_r2_imm2_imm5,
> rv_fmt_rd_rs1_immh_imml_addr },
> + { "th.lwia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr
> },
> + { "th.lwib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr
> },
> + { "th.lwuia", rv_codec_r2_imm2_imm5,
> rv_fmt_rd_rs1_immh_imml_addr },
> + { "th.lwuib", rv_codec_r2_imm2_imm5,
> rv_fmt_rd_rs1_immh_imml_addr },
> + { "th.ldia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr
> },
> + { "th.ldib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr
> },
> + { "th.sbia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr
> },
> + { "th.sbib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr
> },
> + { "th.shia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr
> },
> + { "th.shib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr
> },
> + { "th.swia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr
> },
> + { "th.swib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr
> },
> + { "th.sdia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr
> },
> + { "th.sdib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr
> },
> + { "th.lrb", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm },
> + { "th.lrbu", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm },
> + { "th.lrh", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm },
> + { "th.lrhu", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm },
> + { "th.lrw", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm },
> + { "th.lrwu", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm },
> + { "th.lrd", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm },
> + { "th.srb", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm },
> + { "th.srh", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm },
> + { "th.srw", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm },
> + { "th.srd", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm },
> + { "th.lurb", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm },
> + { "th.lurbu", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm },
> + { "th.lurh", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm },
> + { "th.lurhu", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm },
> + { "th.lurw", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm },
> + { "th.lurwu", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm },
> + { "th.lurd", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm },
> + { "th.surb", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm },
> + { "th.surh", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm },
> + { "th.surw", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm },
> + { "th.surd", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm },
> /* XTheadMemPair */
> - { "th.ldd", rv_codec_r_imm2, rv_fmt_rd2_imm, NULL, 0, 0, 0 },
> - { "th.lwd", rv_codec_r_imm2, rv_fmt_rd2_imm, NULL, 0, 0, 0 },
> - { "th.lwud", rv_codec_r_imm2, rv_fmt_rd2_imm, NULL, 0, 0, 0 },
> - { "th.sdd", rv_codec_r_imm2, rv_fmt_rd2_imm, NULL, 0, 0, 0 },
> - { "th.swd", rv_codec_r_imm2, rv_fmt_rd2_imm, NULL, 0, 0, 0 },
> + { "th.ldd", rv_codec_r_imm2, rv_fmt_rd2_imm },
> + { "th.lwd", rv_codec_r_imm2, rv_fmt_rd2_imm },
> + { "th.lwud", rv_codec_r_imm2, rv_fmt_rd2_imm },
> + { "th.sdd", rv_codec_r_imm2, rv_fmt_rd2_imm },
> + { "th.swd", rv_codec_r_imm2, rv_fmt_rd2_imm },
> /* XTheadSync */
> - { "th.sfence.vmas", rv_codec_r, rv_fmt_rs1_rs2, NULL, 0, 0, 0 },
> - { "th.sync", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
> - { "th.sync.i", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
> - { "th.sync.is", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
> - { "th.sync.s", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
> + { "th.sfence.vmas", rv_codec_r, rv_fmt_rs1_rs2 },
> + { "th.sync", rv_codec_none, rv_fmt_none },
> + { "th.sync.i", rv_codec_none, rv_fmt_none },
> + { "th.sync.is", rv_codec_none, rv_fmt_none },
> + { "th.sync.s", rv_codec_none, rv_fmt_none },
> };
>
> void decode_xtheadba(rv_decode *dec, rv_isa isa)
> diff --git a/disas/riscv-xventana.c b/disas/riscv-xventana.c
> index 4539173d95..4fb9a29d0b 100644
> --- a/disas/riscv-xventana.c
> +++ b/disas/riscv-xventana.c
> @@ -15,9 +15,9 @@ typedef enum {
> } rv_ventana_op;
>
> static const rv_opcode_data ventana_opcode_data[] = {
> - { "vt.illegal", rv_codec_illegal, rv_fmt_none, NULL, 0, 0, 0 },
> - { "vt.maskc", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
> - { "vt.maskcn", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
> + { "vt.illegal", rv_codec_illegal, rv_fmt_none },
> + { "vt.maskc", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> + { "vt.maskcn", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> };
>
> void decode_xventanacondops(rv_decode *dec, rv_isa isa)
> diff --git a/disas/riscv.c b/disas/riscv.c
> index eb6d132a2c..ec40abb618 100644
> --- a/disas/riscv.c
> +++ b/disas/riscv.c
> @@ -1657,233 +1657,233 @@ static uint32_t operand_lpl(rv_inst inst)
> /* instruction metadata */
>
> static const rv_opcode_data rvi_opcode_data[] = {
> - { "illegal", rv_codec_illegal, rv_fmt_none, NULL, 0, 0, 0 },
> - { "lui", rv_codec_u, rv_fmt_rd_uimm, NULL, 0, 0, 0 },
> - { "auipc", rv_codec_u, rv_fmt_rd_uoffset, NULL, 0, 0, 0 },
> - { "jal", rv_codec_uj, rv_fmt_rd_offset, rvcp_jal, 0, 0, 0 },
> - { "jalr", rv_codec_i, rv_fmt_rd_rs1_offset, rvcp_jalr, 0, 0, 0
> },
> - { "beq", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_beq, 0, 0, 0
> },
> - { "bne", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_bne, 0, 0, 0
> },
> - { "blt", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_blt, 0, 0, 0
> },
> - { "bge", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_bge, 0, 0, 0
> },
> - { "bltu", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_bltu, 0, 0, 0
> },
> - { "bgeu", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_bgeu, 0, 0, 0
> },
> - { "lb", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 },
> - { "lh", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 },
> - { "lw", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 },
> - { "lbu", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 },
> - { "lhu", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 },
> - { "sb", rv_codec_s, rv_fmt_rs2_offset_rs1, NULL, 0, 0, 0 },
> - { "sh", rv_codec_s, rv_fmt_rs2_offset_rs1, NULL, 0, 0, 0 },
> - { "sw", rv_codec_s, rv_fmt_rs2_offset_rs1, NULL, 0, 0, 0 },
> - { "addi", rv_codec_i, rv_fmt_rd_rs1_imm, rvcp_addi, 0, 0, 0 },
> - { "slti", rv_codec_i, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
> - { "sltiu", rv_codec_i, rv_fmt_rd_rs1_imm, rvcp_sltiu, 0, 0, 0 },
> - { "xori", rv_codec_i, rv_fmt_rd_rs1_imm, rvcp_xori, 0, 0, 0 },
> - { "ori", rv_codec_i, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
> - { "andi", rv_codec_i, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
> - { "slli", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
> - { "srli", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
> - { "srai", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
> - { "add", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
> - { "sub", rv_codec_r, rv_fmt_rd_rs1_rs2, rvcp_sub, 0, 0, 0 },
> - { "sll", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
> - { "slt", rv_codec_r, rv_fmt_rd_rs1_rs2, rvcp_slt, 0, 0, 0 },
> - { "sltu", rv_codec_r, rv_fmt_rd_rs1_rs2, rvcp_sltu, 0, 0, 0 },
> - { "xor", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
> - { "srl", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
> - { "sra", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
> - { "or", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
> - { "and", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
> - { "fence", rv_codec_r_f, rv_fmt_pred_succ, NULL, 0, 0, 0 },
> - { "fence.i", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
> - { "lwu", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 },
> - { "ld", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 },
> - { "sd", rv_codec_s, rv_fmt_rs2_offset_rs1, NULL, 0, 0, 0 },
> - { "addiw", rv_codec_i, rv_fmt_rd_rs1_imm, rvcp_addiw, 0, 0, 0 },
> - { "slliw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
> - { "srliw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
> - { "sraiw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
> - { "addw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
> - { "subw", rv_codec_r, rv_fmt_rd_rs1_rs2, rvcp_subw, 0, 0, 0 },
> - { "sllw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
> - { "srlw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
> - { "sraw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
> - { "ldu", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 },
> - { "lq", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 },
> - { "sq", rv_codec_s, rv_fmt_rs2_offset_rs1, NULL, 0, 0, 0 },
> - { "addid", rv_codec_i, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
> - { "sllid", rv_codec_i_sh6, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
> - { "srlid", rv_codec_i_sh6, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
> - { "sraid", rv_codec_i_sh6, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
> - { "addd", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
> - { "subd", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
> - { "slld", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
> - { "srld", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
> - { "srad", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
> - { "mul", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
> - { "mulh", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
> - { "mulhsu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
> - { "mulhu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
> - { "div", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
> - { "divu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
> - { "rem", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
> - { "remu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
> - { "mulw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
> - { "divw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
> - { "divuw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
> - { "remw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
> - { "remuw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
> - { "muld", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
> - { "divd", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
> - { "divud", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
> - { "remd", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
> - { "remud", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
> - { "lr.w", rv_codec_r_l, rv_fmt_aqrl_rd_rs1, NULL, 0, 0, 0 },
> - { "sc.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
> - { "amoswap.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0,
> 0 },
> - { "amoadd.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0,
> 0 },
> - { "amoxor.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0,
> 0 },
> - { "amoor.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0
> },
> - { "amoand.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0,
> 0 },
> - { "amomin.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0,
> 0 },
> - { "amomax.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0,
> 0 },
> - { "amominu.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0,
> 0 },
> - { "amomaxu.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0,
> 0 },
> - { "lr.d", rv_codec_r_l, rv_fmt_aqrl_rd_rs1, NULL, 0, 0, 0 },
> - { "sc.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
> - { "amoswap.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0,
> 0 },
> - { "amoadd.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0,
> 0 },
> - { "amoxor.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0,
> 0 },
> - { "amoor.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0
> },
> - { "amoand.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0,
> 0 },
> - { "amomin.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0,
> 0 },
> - { "amomax.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0,
> 0 },
> - { "amominu.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0,
> 0 },
> - { "amomaxu.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0,
> 0 },
> - { "lr.q", rv_codec_r_l, rv_fmt_aqrl_rd_rs1, NULL, 0, 0, 0 },
> - { "sc.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
> - { "amoswap.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0,
> 0 },
> - { "amoadd.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0,
> 0 },
> - { "amoxor.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0,
> 0 },
> - { "amoor.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0
> },
> - { "amoand.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0,
> 0 },
> - { "amomin.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0,
> 0 },
> - { "amomax.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0,
> 0 },
> - { "amominu.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0,
> 0 },
> - { "amomaxu.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0,
> 0 },
> - { "ecall", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
> - { "ebreak", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
> - { "uret", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
> - { "sret", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
> - { "hret", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
> - { "mret", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
> - { "dret", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
> - { "sfence.vm", rv_codec_r, rv_fmt_rs1, NULL, 0, 0, 0 },
> - { "sfence.vma", rv_codec_r, rv_fmt_rs1_rs2, NULL, 0, 0, 0 },
> - { "wfi", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
> - { "csrrw", rv_codec_i_csr, rv_fmt_rd_csr_rs1, rvcp_csrrw, 0, 0,
> 0 },
> - { "csrrs", rv_codec_i_csr, rv_fmt_rd_csr_rs1, rvcp_csrrs, 0, 0,
> 0 },
> - { "csrrc", rv_codec_i_csr, rv_fmt_rd_csr_rs1, NULL, 0, 0, 0 },
> - { "csrrwi", rv_codec_i_csr, rv_fmt_rd_csr_zimm, rvcp_csrrwi, 0,
> 0, 0 },
> - { "csrrsi", rv_codec_i_csr, rv_fmt_rd_csr_zimm, NULL, 0, 0, 0 },
> - { "csrrci", rv_codec_i_csr, rv_fmt_rd_csr_zimm, NULL, 0, 0, 0 },
> - { "flw", rv_codec_i, rv_fmt_frd_offset_rs1, NULL, 0, 0, 0 },
> - { "fsw", rv_codec_s, rv_fmt_frs2_offset_rs1, NULL, 0, 0, 0 },
> - { "fmadd.s", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL,
> 0, 0, 0 },
> - { "fmsub.s", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL,
> 0, 0, 0 },
> - { "fnmsub.s", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL,
> 0, 0, 0 },
> - { "fnmadd.s", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL,
> 0, 0, 0 },
> - { "fadd.s", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0
> },
> - { "fsub.s", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0
> },
> - { "fmul.s", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0
> },
> - { "fdiv.s", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0
> },
> - { "fsgnj.s", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnj_s, 0,
> 0, 0 },
> - { "fsgnjn.s", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjn_s,
> 0, 0, 0 },
> - { "fsgnjx.s", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjx_s,
> 0, 0, 0 },
> - { "fmin.s", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 },
> - { "fmax.s", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 },
> - { "fsqrt.s", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },
> - { "fle.s", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 },
> - { "flt.s", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 },
> - { "feq.s", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 },
> - { "fcvt.w.s", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 },
> - { "fcvt.wu.s", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 },
> - { "fcvt.s.w", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 },
> - { "fcvt.s.wu", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 },
> - { "fmv.x.s", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 },
> - { "fclass.s", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 },
> - { "fmv.s.x", rv_codec_r, rv_fmt_frd_rs1, NULL, 0, 0, 0 },
> - { "fcvt.l.s", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 },
> - { "fcvt.lu.s", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 },
> - { "fcvt.s.l", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 },
> - { "fcvt.s.lu", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 },
> - { "fld", rv_codec_i, rv_fmt_frd_offset_rs1, NULL, 0, 0, 0 },
> - { "fsd", rv_codec_s, rv_fmt_frs2_offset_rs1, NULL, 0, 0, 0 },
> - { "fmadd.d", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL,
> 0, 0, 0 },
> - { "fmsub.d", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL,
> 0, 0, 0 },
> - { "fnmsub.d", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL,
> 0, 0, 0 },
> - { "fnmadd.d", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL,
> 0, 0, 0 },
> - { "fadd.d", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0
> },
> - { "fsub.d", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0
> },
> - { "fmul.d", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0
> },
> - { "fdiv.d", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0
> },
> - { "fsgnj.d", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnj_d, 0,
> 0, 0 },
> - { "fsgnjn.d", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjn_d,
> 0, 0, 0 },
> - { "fsgnjx.d", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjx_d,
> 0, 0, 0 },
> - { "fmin.d", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 },
> - { "fmax.d", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 },
> - { "fcvt.s.d", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },
> - { "fcvt.d.s", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },
> - { "fsqrt.d", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },
> - { "fle.d", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 },
> - { "flt.d", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 },
> - { "feq.d", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 },
> - { "fcvt.w.d", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 },
> - { "fcvt.wu.d", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 },
> - { "fcvt.d.w", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 },
> - { "fcvt.d.wu", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 },
> - { "fclass.d", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 },
> - { "fcvt.l.d", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 },
> - { "fcvt.lu.d", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 },
> - { "fmv.x.d", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 },
> - { "fcvt.d.l", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 },
> - { "fcvt.d.lu", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 },
> - { "fmv.d.x", rv_codec_r, rv_fmt_frd_rs1, NULL, 0, 0, 0 },
> - { "flq", rv_codec_i, rv_fmt_frd_offset_rs1, NULL, 0, 0, 0 },
> - { "fsq", rv_codec_s, rv_fmt_frs2_offset_rs1, NULL, 0, 0, 0 },
> - { "fmadd.q", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL,
> 0, 0, 0 },
> - { "fmsub.q", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL,
> 0, 0, 0 },
> - { "fnmsub.q", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL,
> 0, 0, 0 },
> - { "fnmadd.q", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL,
> 0, 0, 0 },
> - { "fadd.q", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0
> },
> - { "fsub.q", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0
> },
> - { "fmul.q", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0
> },
> - { "fdiv.q", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0
> },
> - { "fsgnj.q", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnj_q, 0,
> 0, 0 },
> - { "fsgnjn.q", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjn_q,
> 0, 0, 0 },
> - { "fsgnjx.q", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjx_q,
> 0, 0, 0 },
> - { "fmin.q", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 },
> - { "fmax.q", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 },
> - { "fcvt.s.q", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },
> - { "fcvt.q.s", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },
> - { "fcvt.d.q", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },
> - { "fcvt.q.d", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },
> - { "fsqrt.q", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },
> - { "fle.q", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 },
> - { "flt.q", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 },
> - { "feq.q", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 },
> - { "fcvt.w.q", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 },
> - { "fcvt.wu.q", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 },
> - { "fcvt.q.w", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 },
> - { "fcvt.q.wu", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 },
> - { "fclass.q", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 },
> - { "fcvt.l.q", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 },
> - { "fcvt.lu.q", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 },
> - { "fcvt.q.l", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 },
> - { "fcvt.q.lu", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 },
> - { "fmv.x.q", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 },
> - { "fmv.q.x", rv_codec_r, rv_fmt_frd_rs1, NULL, 0, 0, 0 },
> + { "illegal", rv_codec_illegal, rv_fmt_none },
> + { "lui", rv_codec_u, rv_fmt_rd_uimm },
> + { "auipc", rv_codec_u, rv_fmt_rd_uoffset },
> + { "jal", rv_codec_uj, rv_fmt_rd_offset, rvcp_jal },
> + { "jalr", rv_codec_i, rv_fmt_rd_rs1_offset, rvcp_jalr },
> + { "beq", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_beq },
> + { "bne", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_bne },
> + { "blt", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_blt },
> + { "bge", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_bge },
> + { "bltu", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_bltu },
> + { "bgeu", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_bgeu },
> + { "lb", rv_codec_i, rv_fmt_rd_offset_rs1 },
> + { "lh", rv_codec_i, rv_fmt_rd_offset_rs1 },
> + { "lw", rv_codec_i, rv_fmt_rd_offset_rs1 },
> + { "lbu", rv_codec_i, rv_fmt_rd_offset_rs1 },
> + { "lhu", rv_codec_i, rv_fmt_rd_offset_rs1 },
> + { "sb", rv_codec_s, rv_fmt_rs2_offset_rs1 },
> + { "sh", rv_codec_s, rv_fmt_rs2_offset_rs1 },
> + { "sw", rv_codec_s, rv_fmt_rs2_offset_rs1 },
> + { "addi", rv_codec_i, rv_fmt_rd_rs1_imm, rvcp_addi },
> + { "slti", rv_codec_i, rv_fmt_rd_rs1_imm },
> + { "sltiu", rv_codec_i, rv_fmt_rd_rs1_imm, rvcp_sltiu },
> + { "xori", rv_codec_i, rv_fmt_rd_rs1_imm, rvcp_xori },
> + { "ori", rv_codec_i, rv_fmt_rd_rs1_imm },
> + { "andi", rv_codec_i, rv_fmt_rd_rs1_imm },
> + { "slli", rv_codec_i_sh7, rv_fmt_rd_rs1_imm },
> + { "srli", rv_codec_i_sh7, rv_fmt_rd_rs1_imm },
> + { "srai", rv_codec_i_sh7, rv_fmt_rd_rs1_imm },
> + { "add", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> + { "sub", rv_codec_r, rv_fmt_rd_rs1_rs2, rvcp_sub },
> + { "sll", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> + { "slt", rv_codec_r, rv_fmt_rd_rs1_rs2, rvcp_slt },
> + { "sltu", rv_codec_r, rv_fmt_rd_rs1_rs2, rvcp_sltu },
> + { "xor", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> + { "srl", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> + { "sra", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> + { "or", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> + { "and", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> + { "fence", rv_codec_r_f, rv_fmt_pred_succ },
> + { "fence.i", rv_codec_none, rv_fmt_none },
> + { "lwu", rv_codec_i, rv_fmt_rd_offset_rs1 },
> + { "ld", rv_codec_i, rv_fmt_rd_offset_rs1 },
> + { "sd", rv_codec_s, rv_fmt_rs2_offset_rs1 },
> + { "addiw", rv_codec_i, rv_fmt_rd_rs1_imm, rvcp_addiw },
> + { "slliw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm },
> + { "srliw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm },
> + { "sraiw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm },
> + { "addw", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> + { "subw", rv_codec_r, rv_fmt_rd_rs1_rs2, rvcp_subw },
> + { "sllw", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> + { "srlw", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> + { "sraw", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> + { "ldu", rv_codec_i, rv_fmt_rd_offset_rs1 },
> + { "lq", rv_codec_i, rv_fmt_rd_offset_rs1 },
> + { "sq", rv_codec_s, rv_fmt_rs2_offset_rs1 },
> + { "addid", rv_codec_i, rv_fmt_rd_rs1_imm },
> + { "sllid", rv_codec_i_sh6, rv_fmt_rd_rs1_imm },
> + { "srlid", rv_codec_i_sh6, rv_fmt_rd_rs1_imm },
> + { "sraid", rv_codec_i_sh6, rv_fmt_rd_rs1_imm },
> + { "addd", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> + { "subd", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> + { "slld", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> + { "srld", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> + { "srad", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> + { "mul", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> + { "mulh", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> + { "mulhsu", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> + { "mulhu", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> + { "div", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> + { "divu", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> + { "rem", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> + { "remu", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> + { "mulw", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> + { "divw", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> + { "divuw", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> + { "remw", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> + { "remuw", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> + { "muld", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> + { "divd", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> + { "divud", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> + { "remd", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> + { "remud", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> + { "lr.w", rv_codec_r_l, rv_fmt_aqrl_rd_rs1 },
> + { "sc.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
> + { "amoswap.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
> + { "amoadd.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
> + { "amoxor.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
> + { "amoor.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
> + { "amoand.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
> + { "amomin.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
> + { "amomax.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
> + { "amominu.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
> + { "amomaxu.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
> + { "lr.d", rv_codec_r_l, rv_fmt_aqrl_rd_rs1 },
> + { "sc.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
> + { "amoswap.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
> + { "amoadd.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
> + { "amoxor.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
> + { "amoor.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
> + { "amoand.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
> + { "amomin.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
> + { "amomax.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
> + { "amominu.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
> + { "amomaxu.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
> + { "lr.q", rv_codec_r_l, rv_fmt_aqrl_rd_rs1 },
> + { "sc.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
> + { "amoswap.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
> + { "amoadd.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
> + { "amoxor.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
> + { "amoor.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
> + { "amoand.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
> + { "amomin.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
> + { "amomax.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
> + { "amominu.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
> + { "amomaxu.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
> + { "ecall", rv_codec_none, rv_fmt_none },
> + { "ebreak", rv_codec_none, rv_fmt_none },
> + { "uret", rv_codec_none, rv_fmt_none },
> + { "sret", rv_codec_none, rv_fmt_none },
> + { "hret", rv_codec_none, rv_fmt_none },
> + { "mret", rv_codec_none, rv_fmt_none },
> + { "dret", rv_codec_none, rv_fmt_none },
> + { "sfence.vm", rv_codec_r, rv_fmt_rs1 },
> + { "sfence.vma", rv_codec_r, rv_fmt_rs1_rs2 },
> + { "wfi", rv_codec_none, rv_fmt_none },
> + { "csrrw", rv_codec_i_csr, rv_fmt_rd_csr_rs1, rvcp_csrrw },
> + { "csrrs", rv_codec_i_csr, rv_fmt_rd_csr_rs1, rvcp_csrrs },
> + { "csrrc", rv_codec_i_csr, rv_fmt_rd_csr_rs1 },
> + { "csrrwi", rv_codec_i_csr, rv_fmt_rd_csr_zimm, rvcp_csrrwi },
> + { "csrrsi", rv_codec_i_csr, rv_fmt_rd_csr_zimm },
> + { "csrrci", rv_codec_i_csr, rv_fmt_rd_csr_zimm },
> + { "flw", rv_codec_i, rv_fmt_frd_offset_rs1 },
> + { "fsw", rv_codec_s, rv_fmt_frs2_offset_rs1 },
> + { "fmadd.s", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3 },
> + { "fmsub.s", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3 },
> + { "fnmsub.s", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3 },
> + { "fnmadd.s", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3 },
> + { "fadd.s", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2 },
> + { "fsub.s", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2 },
> + { "fmul.s", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2 },
> + { "fdiv.s", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2 },
> + { "fsgnj.s", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnj_s },
> + { "fsgnjn.s", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjn_s },
> + { "fsgnjx.s", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjx_s },
> + { "fmin.s", rv_codec_r, rv_fmt_frd_frs1_frs2 },
> + { "fmax.s", rv_codec_r, rv_fmt_frd_frs1_frs2 },
> + { "fsqrt.s", rv_codec_r_m, rv_fmt_rm_frd_frs1 },
> + { "fle.s", rv_codec_r, rv_fmt_rd_frs1_frs2 },
> + { "flt.s", rv_codec_r, rv_fmt_rd_frs1_frs2 },
> + { "feq.s", rv_codec_r, rv_fmt_rd_frs1_frs2 },
> + { "fcvt.w.s", rv_codec_r_m, rv_fmt_rm_rd_frs1 },
> + { "fcvt.wu.s", rv_codec_r_m, rv_fmt_rm_rd_frs1 },
> + { "fcvt.s.w", rv_codec_r_m, rv_fmt_rm_frd_rs1 },
> + { "fcvt.s.wu", rv_codec_r_m, rv_fmt_rm_frd_rs1 },
> + { "fmv.x.s", rv_codec_r, rv_fmt_rd_frs1 },
> + { "fclass.s", rv_codec_r, rv_fmt_rd_frs1 },
> + { "fmv.s.x", rv_codec_r, rv_fmt_frd_rs1 },
> + { "fcvt.l.s", rv_codec_r_m, rv_fmt_rm_rd_frs1 },
> + { "fcvt.lu.s", rv_codec_r_m, rv_fmt_rm_rd_frs1 },
> + { "fcvt.s.l", rv_codec_r_m, rv_fmt_rm_frd_rs1 },
> + { "fcvt.s.lu", rv_codec_r_m, rv_fmt_rm_frd_rs1 },
> + { "fld", rv_codec_i, rv_fmt_frd_offset_rs1 },
> + { "fsd", rv_codec_s, rv_fmt_frs2_offset_rs1 },
> + { "fmadd.d", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3 },
> + { "fmsub.d", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3 },
> + { "fnmsub.d", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3 },
> + { "fnmadd.d", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3 },
> + { "fadd.d", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2 },
> + { "fsub.d", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2 },
> + { "fmul.d", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2 },
> + { "fdiv.d", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2 },
> + { "fsgnj.d", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnj_d },
> + { "fsgnjn.d", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjn_d },
> + { "fsgnjx.d", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjx_d },
> + { "fmin.d", rv_codec_r, rv_fmt_frd_frs1_frs2 },
> + { "fmax.d", rv_codec_r, rv_fmt_frd_frs1_frs2 },
> + { "fcvt.s.d", rv_codec_r_m, rv_fmt_rm_frd_frs1 },
> + { "fcvt.d.s", rv_codec_r_m, rv_fmt_rm_frd_frs1 },
> + { "fsqrt.d", rv_codec_r_m, rv_fmt_rm_frd_frs1 },
> + { "fle.d", rv_codec_r, rv_fmt_rd_frs1_frs2 },
> + { "flt.d", rv_codec_r, rv_fmt_rd_frs1_frs2 },
> + { "feq.d", rv_codec_r, rv_fmt_rd_frs1_frs2 },
> + { "fcvt.w.d", rv_codec_r_m, rv_fmt_rm_rd_frs1 },
> + { "fcvt.wu.d", rv_codec_r_m, rv_fmt_rm_rd_frs1 },
> + { "fcvt.d.w", rv_codec_r_m, rv_fmt_rm_frd_rs1 },
> + { "fcvt.d.wu", rv_codec_r_m, rv_fmt_rm_frd_rs1 },
> + { "fclass.d", rv_codec_r, rv_fmt_rd_frs1 },
> + { "fcvt.l.d", rv_codec_r_m, rv_fmt_rm_rd_frs1 },
> + { "fcvt.lu.d", rv_codec_r_m, rv_fmt_rm_rd_frs1 },
> + { "fmv.x.d", rv_codec_r, rv_fmt_rd_frs1 },
> + { "fcvt.d.l", rv_codec_r_m, rv_fmt_rm_frd_rs1 },
> + { "fcvt.d.lu", rv_codec_r_m, rv_fmt_rm_frd_rs1 },
> + { "fmv.d.x", rv_codec_r, rv_fmt_frd_rs1 },
> + { "flq", rv_codec_i, rv_fmt_frd_offset_rs1 },
> + { "fsq", rv_codec_s, rv_fmt_frs2_offset_rs1 },
> + { "fmadd.q", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3 },
> + { "fmsub.q", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3 },
> + { "fnmsub.q", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3 },
> + { "fnmadd.q", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3 },
> + { "fadd.q", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2 },
> + { "fsub.q", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2 },
> + { "fmul.q", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2 },
> + { "fdiv.q", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2 },
> + { "fsgnj.q", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnj_q },
> + { "fsgnjn.q", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjn_q },
> + { "fsgnjx.q", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjx_q },
> + { "fmin.q", rv_codec_r, rv_fmt_frd_frs1_frs2 },
> + { "fmax.q", rv_codec_r, rv_fmt_frd_frs1_frs2 },
> + { "fcvt.s.q", rv_codec_r_m, rv_fmt_rm_frd_frs1 },
> + { "fcvt.q.s", rv_codec_r_m, rv_fmt_rm_frd_frs1 },
> + { "fcvt.d.q", rv_codec_r_m, rv_fmt_rm_frd_frs1 },
> + { "fcvt.q.d", rv_codec_r_m, rv_fmt_rm_frd_frs1 },
> + { "fsqrt.q", rv_codec_r_m, rv_fmt_rm_frd_frs1 },
> + { "fle.q", rv_codec_r, rv_fmt_rd_frs1_frs2 },
> + { "flt.q", rv_codec_r, rv_fmt_rd_frs1_frs2 },
> + { "feq.q", rv_codec_r, rv_fmt_rd_frs1_frs2 },
> + { "fcvt.w.q", rv_codec_r_m, rv_fmt_rm_rd_frs1 },
> + { "fcvt.wu.q", rv_codec_r_m, rv_fmt_rm_rd_frs1 },
> + { "fcvt.q.w", rv_codec_r_m, rv_fmt_rm_frd_rs1 },
> + { "fcvt.q.wu", rv_codec_r_m, rv_fmt_rm_frd_rs1 },
> + { "fclass.q", rv_codec_r, rv_fmt_rd_frs1 },
> + { "fcvt.l.q", rv_codec_r_m, rv_fmt_rm_rd_frs1 },
> + { "fcvt.lu.q", rv_codec_r_m, rv_fmt_rm_rd_frs1 },
> + { "fcvt.q.l", rv_codec_r_m, rv_fmt_rm_frd_rs1 },
> + { "fcvt.q.lu", rv_codec_r_m, rv_fmt_rm_frd_rs1 },
> + { "fmv.x.q", rv_codec_r, rv_fmt_rd_frs1 },
> + { "fmv.q.x", rv_codec_r, rv_fmt_frd_rs1 },
> { "c.addi4spn", rv_codec_ciw_4spn, rv_fmt_rd_rs1_imm, NULL,
> rv_op_addi,
> rv_op_addi, rv_op_addi, rvcd_imm_nz },
> { "c.fld", rv_codec_cl_ld, rv_fmt_frd_offset_rs1, NULL,
> rv_op_fld,
> @@ -1970,696 +1970,696 @@ static const rv_opcode_data
> rvi_opcode_data[] = {
> { "c.lqsp", rv_codec_ci_lqsp, rv_fmt_rd_offset_rs1, NULL, 0, 0,
> rv_op_lq },
> { "c.sqsp", rv_codec_css_sqsp, rv_fmt_rs2_offset_rs1, NULL, 0,
> 0,
> rv_op_sq },
> - { "nop", rv_codec_i, rv_fmt_none, NULL, 0, 0, 0 },
> - { "mv", rv_codec_i, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
> - { "not", rv_codec_i, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
> - { "neg", rv_codec_r, rv_fmt_rd_rs2, NULL, 0, 0, 0 },
> - { "negw", rv_codec_r, rv_fmt_rd_rs2, NULL, 0, 0, 0 },
> - { "sext.w", rv_codec_i, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
> - { "seqz", rv_codec_i, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
> - { "snez", rv_codec_r, rv_fmt_rd_rs2, NULL, 0, 0, 0 },
> - { "sltz", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
> - { "sgtz", rv_codec_r, rv_fmt_rd_rs2, NULL, 0, 0, 0 },
> - { "fmv.s", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
> - { "fabs.s", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
> - { "fneg.s", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
> - { "fmv.d", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
> - { "fabs.d", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
> - { "fneg.d", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
> - { "fmv.q", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
> - { "fabs.q", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
> - { "fneg.q", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
> - { "beqz", rv_codec_sb, rv_fmt_rs1_offset, NULL, 0, 0, 0 },
> - { "bnez", rv_codec_sb, rv_fmt_rs1_offset, NULL, 0, 0, 0 },
> - { "blez", rv_codec_sb, rv_fmt_rs2_offset, NULL, 0, 0, 0 },
> - { "bgez", rv_codec_sb, rv_fmt_rs1_offset, NULL, 0, 0, 0 },
> - { "bltz", rv_codec_sb, rv_fmt_rs1_offset, NULL, 0, 0, 0 },
> - { "bgtz", rv_codec_sb, rv_fmt_rs2_offset, NULL, 0, 0, 0 },
> - { "ble", rv_codec_sb, rv_fmt_rs2_rs1_offset, NULL, 0, 0, 0 },
> - { "bleu", rv_codec_sb, rv_fmt_rs2_rs1_offset, NULL, 0, 0, 0 },
> - { "bgt", rv_codec_sb, rv_fmt_rs2_rs1_offset, NULL, 0, 0, 0 },
> - { "bgtu", rv_codec_sb, rv_fmt_rs2_rs1_offset, NULL, 0, 0, 0 },
> - { "j", rv_codec_uj, rv_fmt_offset, NULL, 0, 0, 0 },
> - { "ret", rv_codec_i, rv_fmt_none, NULL, 0, 0, 0 },
> - { "jr", rv_codec_i, rv_fmt_rs1, NULL, 0, 0, 0 },
> - { "rdcycle", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 },
> - { "rdtime", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 },
> - { "rdinstret", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 },
> - { "rdcycleh", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 },
> - { "rdtimeh", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 },
> - { "rdinstreth", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 },
> - { "frcsr", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 },
> - { "frrm", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 },
> - { "frflags", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 },
> - { "fscsr", rv_codec_i_csr, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
> - { "fsrm", rv_codec_i_csr, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
> - { "fsflags", rv_codec_i_csr, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
> - { "fsrmi", rv_codec_i_csr, rv_fmt_rd_zimm, NULL, 0, 0, 0 },
> - { "fsflagsi", rv_codec_i_csr, rv_fmt_rd_zimm, NULL, 0, 0, 0 },
> - { "bseti", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
> - { "bclri", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
> - { "binvi", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
> - { "bexti", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
> - { "rori", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
> - { "clz", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
> - { "ctz", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
> - { "cpop", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
> - { "sext.h", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
> - { "sext.b", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
> - { "xnor", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
> - { "orn", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
> - { "andn", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
> - { "rol", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
> - { "ror", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
> - { "sh1add", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
> - { "sh2add", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
> - { "sh3add", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
> - { "sh1add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
> - { "sh2add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
> - { "sh3add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
> - { "clmul", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
> - { "clmulr", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
> - { "clmulh", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
> - { "min", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
> - { "minu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
> - { "max", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
> - { "maxu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
> - { "clzw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
> - { "ctzw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
> - { "cpopw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
> - { "slli.uw", rv_codec_i_sh6, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
> - { "add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
> - { "rolw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
> - { "rorw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
> - { "rev8", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
> - { "zext.h", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
> - { "roriw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
> - { "orc.b", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
> - { "bset", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
> - { "bclr", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
> - { "binv", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
> - { "bext", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
> - { "aes32esmi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0
> },
> - { "aes32esi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 },
> - { "aes32dsmi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0
> },
> - { "aes32dsi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 },
> - { "aes64ks1i", rv_codec_k_rnum, rv_fmt_rd_rs1_rnum, NULL, 0, 0,
> 0 },
> - { "aes64ks2", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
> - { "aes64im", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
> - { "aes64esm", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
> - { "aes64es", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
> - { "aes64dsm", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
> - { "aes64ds", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
> - { "sha256sig0", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
> - { "sha256sig1", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
> - { "sha256sum0", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
> - { "sha256sum1", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
> - { "sha512sig0", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
> - { "sha512sig1", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
> - { "sha512sum0", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
> - { "sha512sum1", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
> - { "sha512sum0r", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
> - { "sha512sum1r", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
> - { "sha512sig0l", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
> - { "sha512sig0h", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
> - { "sha512sig1l", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
> - { "sha512sig1h", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
> - { "sm3p0", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
> - { "sm3p1", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
> - { "sm4ed", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 },
> - { "sm4ks", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 },
> - { "brev8", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
> - { "pack", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
> - { "packh", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
> - { "packw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
> - { "unzip", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
> - { "zip", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
> - { "xperm4", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
> - { "xperm8", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
> - { "vle8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0,
> 0 },
> - { "vle16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0,
> 0 },
> - { "vle32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0,
> 0 },
> - { "vle64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0,
> 0 },
> - { "vse8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0,
> 0 },
> - { "vse16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0,
> 0 },
> - { "vse32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0,
> 0 },
> - { "vse64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0,
> 0 },
> - { "vlm.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0
> },
> - { "vsm.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0
> },
> - { "vlse8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, 0,
> 0, 0 },
> - { "vlse16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, 0,
> 0, 0 },
> - { "vlse32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, 0,
> 0, 0 },
> - { "vlse64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, 0,
> 0, 0 },
> - { "vsse8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, 0,
> 0, 0 },
> - { "vsse16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, 0,
> 0, 0 },
> - { "vsse32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, 0,
> 0, 0 },
> - { "vsse64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, 0,
> 0, 0 },
> - { "vluxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0,
> 0, 0 },
> - { "vluxei16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL,
> 0, 0, 0 },
> - { "vluxei32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL,
> 0, 0, 0 },
> - { "vluxei64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL,
> 0, 0, 0 },
> - { "vloxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0,
> 0, 0 },
> - { "vloxei16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL,
> 0, 0, 0 },
> - { "vloxei32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL,
> 0, 0, 0 },
> - { "vloxei64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL,
> 0, 0, 0 },
> - { "vsuxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0,
> 0, 0 },
> - { "vsuxei16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL,
> 0, 0, 0 },
> - { "vsuxei32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL,
> 0, 0, 0 },
> - { "vsuxei64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL,
> 0, 0, 0 },
> - { "vsoxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0,
> 0, 0 },
> - { "vsoxei16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL,
> 0, 0, 0 },
> - { "vsoxei32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL,
> 0, 0, 0 },
> - { "vsoxei64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL,
> 0, 0, 0 },
> - { "vle8ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0,
> 0, 0 },
> - { "vle16ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0,
> 0, 0 },
> - { "vle32ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0,
> 0, 0 },
> - { "vle64ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0,
> 0, 0 },
> - { "vl1re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0,
> 0, 0 },
> - { "vl1re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0,
> 0, 0 },
> - { "vl1re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0,
> 0, 0 },
> - { "vl1re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0,
> 0, 0 },
> - { "vl2re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0,
> 0, 0 },
> - { "vl2re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0,
> 0, 0 },
> - { "vl2re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0,
> 0, 0 },
> - { "vl2re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0,
> 0, 0 },
> - { "vl4re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0,
> 0, 0 },
> - { "vl4re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0,
> 0, 0 },
> - { "vl4re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0,
> 0, 0 },
> - { "vl4re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0,
> 0, 0 },
> - { "vl8re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0,
> 0, 0 },
> - { "vl8re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0,
> 0, 0 },
> - { "vl8re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0,
> 0, 0 },
> - { "vl8re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0,
> 0, 0 },
> - { "vs1r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0,
> 0 },
> - { "vs2r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0,
> 0 },
> - { "vs4r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0,
> 0 },
> - { "vs8r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0,
> 0 },
> - { "vadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0
> },
> - { "vadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0
> },
> - { "vadd.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0
> },
> - { "vsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0
> },
> - { "vsub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0
> },
> - { "vrsub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0
> },
> - { "vrsub.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0
> },
> - { "vwaddu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0
> },
> - { "vwaddu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0
> },
> - { "vwadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0
> },
> - { "vwadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0
> },
> - { "vwsubu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0
> },
> - { "vwsubu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0
> },
> - { "vwsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0
> },
> - { "vwsub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0
> },
> - { "vwaddu.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0
> },
> - { "vwaddu.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0
> },
> - { "vwadd.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0
> },
> - { "vwadd.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0
> },
> - { "vwsubu.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0
> },
> - { "vwsubu.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0
> },
> - { "vwsub.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0
> },
> - { "vwsub.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0
> },
> - { "vadc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl, NULL, 0, 0, 0
> },
> - { "vadc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl, NULL, 0, 0, 0
> },
> - { "vadc.vim", rv_codec_v_i, rv_fmt_vd_vs2_imm_vl, NULL, 0, 0, 0
> },
> - { "vmadc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl, NULL, 0, 0, 0
> },
> - { "vmadc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl, NULL, 0, 0, 0
> },
> - { "vmadc.vim", rv_codec_v_i, rv_fmt_vd_vs2_imm_vl, NULL, 0, 0, 0
> },
> - { "vsbc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl, NULL, 0, 0, 0
> },
> - { "vsbc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl, NULL, 0, 0, 0
> },
> - { "vmsbc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl, NULL, 0, 0, 0
> },
> - { "vmsbc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl, NULL, 0, 0, 0
> },
> - { "vand.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0
> },
> - { "vand.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0
> },
> - { "vand.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0
> },
> - { "vor.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
> - { "vor.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
> - { "vor.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 },
> - { "vxor.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0
> },
> - { "vxor.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0
> },
> - { "vxor.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0
> },
> - { "vsll.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0
> },
> - { "vsll.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0
> },
> - { "vsll.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0,
> 0 },
> - { "vsrl.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0
> },
> - { "vsrl.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0
> },
> - { "vsrl.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0,
> 0 },
> - { "vsra.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0
> },
> - { "vsra.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0
> },
> - { "vsra.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0,
> 0 },
> - { "vnsrl.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0
> },
> - { "vnsrl.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0
> },
> - { "vnsrl.wi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0,
> 0 },
> - { "vnsra.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0
> },
> - { "vnsra.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0
> },
> - { "vnsra.wi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0,
> 0 },
> - { "vmseq.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0
> },
> - { "vmseq.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0
> },
> - { "vmseq.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0
> },
> - { "vmsne.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0
> },
> - { "vmsne.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0
> },
> - { "vmsne.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0
> },
> - { "vmsltu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0
> },
> - { "vmsltu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0
> },
> - { "vmslt.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0
> },
> - { "vmslt.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0
> },
> - { "vmsleu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0
> },
> - { "vmsleu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0
> },
> - { "vmsleu.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0
> },
> - { "vmsle.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0
> },
> - { "vmsle.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0
> },
> - { "vmsle.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0
> },
> - { "vmsgtu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0
> },
> - { "vmsgtu.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0
> },
> - { "vmsgt.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0
> },
> - { "vmsgt.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0
> },
> - { "vminu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0
> },
> - { "vminu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0
> },
> - { "vmin.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0
> },
> - { "vmin.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0
> },
> - { "vmaxu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0
> },
> - { "vmaxu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0
> },
> - { "vmax.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0
> },
> - { "vmax.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0
> },
> - { "vmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0
> },
> - { "vmul.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0
> },
> - { "vmulh.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0
> },
> - { "vmulh.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0
> },
> - { "vmulhu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0
> },
> - { "vmulhu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0
> },
> - { "vmulhsu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0,
> 0 },
> - { "vmulhsu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0,
> 0 },
> - { "vdivu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0
> },
> - { "vdivu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0
> },
> - { "vdiv.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0
> },
> - { "vdiv.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0
> },
> - { "vremu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0
> },
> - { "vremu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0
> },
> - { "vrem.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0
> },
> - { "vrem.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0
> },
> - { "vwmulu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0
> },
> - { "vwmulu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0
> },
> - { "vwmulsu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0,
> 0 },
> - { "vwmulsu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0,
> 0 },
> - { "vwmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0
> },
> - { "vwmul.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0
> },
> - { "vmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0
> },
> - { "vmacc.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, 0, 0, 0
> },
> - { "vnmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0
> },
> - { "vnmsac.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, 0, 0, 0
> },
> - { "vmadd.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0
> },
> - { "vmadd.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, 0, 0, 0
> },
> - { "vnmsub.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0
> },
> - { "vnmsub.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, 0, 0, 0
> },
> - { "vwmaccu.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0,
> 0 },
> - { "vwmaccu.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, 0, 0,
> 0 },
> - { "vwmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0
> },
> - { "vwmacc.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, 0, 0, 0
> },
> - { "vwmaccsu.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0,
> 0 },
> - { "vwmaccsu.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, 0, 0,
> 0 },
> - { "vwmaccus.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, 0, 0,
> 0 },
> - { "vmv.v.v", rv_codec_v_r, rv_fmt_vd_vs1, NULL, 0, 0, 0 },
> - { "vmv.v.x", rv_codec_v_r, rv_fmt_vd_rs1, NULL, 0, 0, 0 },
> - { "vmv.v.i", rv_codec_v_i, rv_fmt_vd_imm, NULL, 0, 0, 0 },
> - { "vmerge.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl, NULL, 0, 0,
> 0 },
> - { "vmerge.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl, NULL, 0, 0,
> 0 },
> - { "vmerge.vim", rv_codec_v_i, rv_fmt_vd_vs2_imm_vl, NULL, 0, 0,
> 0 },
> - { "vsaddu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0
> },
> - { "vsaddu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0
> },
> - { "vsaddu.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0
> },
> - { "vsadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0
> },
> - { "vsadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0
> },
> - { "vsadd.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0
> },
> - { "vssubu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0
> },
> - { "vssubu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0
> },
> - { "vssub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0
> },
> - { "vssub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0
> },
> - { "vaadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0
> },
> - { "vaadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0
> },
> - { "vaaddu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0
> },
> - { "vaaddu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0
> },
> - { "vasub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0
> },
> - { "vasub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0
> },
> - { "vasubu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0
> },
> - { "vasubu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0
> },
> - { "vsmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0
> },
> - { "vsmul.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0
> },
> - { "vssrl.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0
> },
> - { "vssrl.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0
> },
> - { "vssrl.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0,
> 0 },
> - { "vssra.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0
> },
> - { "vssra.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0
> },
> - { "vssra.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0,
> 0 },
> - { "vnclipu.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0,
> 0 },
> - { "vnclipu.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0,
> 0 },
> - { "vnclipu.wi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm, NULL, 0,
> 0, 0 },
> - { "vnclip.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0
> },
> - { "vnclip.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0
> },
> - { "vnclip.wi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm, NULL, 0,
> 0, 0 },
> - { "vfadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0
> },
> - { "vfadd.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0
> },
> - { "vfsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0
> },
> - { "vfsub.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0
> },
> - { "vfrsub.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0
> },
> - { "vfwadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0
> },
> - { "vfwadd.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0
> },
> - { "vfwadd.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0
> },
> - { "vfwadd.wf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0
> },
> - { "vfwsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0
> },
> - { "vfwsub.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0
> },
> - { "vfwsub.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0
> },
> - { "vfwsub.wf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0
> },
> - { "vfmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0
> },
> - { "vfmul.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0
> },
> - { "vfdiv.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0
> },
> - { "vfdiv.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0
> },
> - { "vfrdiv.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0
> },
> - { "vfwmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0
> },
> - { "vfwmul.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0
> },
> - { "vfmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0
> },
> - { "vfmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0
> },
> - { "vfnmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0,
> 0 },
> - { "vfnmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0,
> 0 },
> - { "vfmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0
> },
> - { "vfmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0
> },
> - { "vfnmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0,
> 0 },
> - { "vfnmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0,
> 0 },
> - { "vfmadd.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0
> },
> - { "vfmadd.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0
> },
> - { "vfnmadd.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0,
> 0 },
> - { "vfnmadd.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0,
> 0 },
> - { "vfmsub.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0
> },
> - { "vfmsub.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0
> },
> - { "vfnmsub.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0,
> 0 },
> - { "vfnmsub.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0,
> 0 },
> - { "vfwmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0,
> 0 },
> - { "vfwmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0,
> 0 },
> - { "vfwnmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0,
> 0 },
> - { "vfwnmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0,
> 0 },
> - { "vfwmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0,
> 0 },
> - { "vfwmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0,
> 0 },
> - { "vfwnmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0,
> 0 },
> - { "vfwnmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0,
> 0 },
> - { "vfsqrt.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
> - { "vfrsqrt7.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
> - { "vfrec7.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
> - { "vfmin.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0
> },
> - { "vfmin.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0
> },
> - { "vfmax.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0
> },
> - { "vfmax.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0
> },
> - { "vfsgnj.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0
> },
> - { "vfsgnj.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0
> },
> - { "vfsgnjn.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0,
> 0 },
> - { "vfsgnjn.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0,
> 0 },
> - { "vfsgnjx.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0,
> 0 },
> - { "vfsgnjx.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0,
> 0 },
> - { "vfslide1up.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0,
> 0, 0 },
> - { "vfslide1down.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL,
> 0, 0, 0 },
> - { "vmfeq.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0
> },
> - { "vmfeq.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0
> },
> - { "vmfne.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0
> },
> - { "vmfne.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0
> },
> - { "vmflt.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0
> },
> - { "vmflt.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0
> },
> - { "vmfle.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0
> },
> - { "vmfle.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0
> },
> - { "vmfgt.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0
> },
> - { "vmfge.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0
> },
> - { "vfclass.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
> - { "vfmerge.vfm", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vl, NULL, 0, 0,
> 0 },
> - { "vfmv.v.f", rv_codec_v_r, rv_fmt_vd_fs1, NULL, 0, 0, 0 },
> - { "vfcvt.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0
> },
> - { "vfcvt.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0
> },
> - { "vfcvt.f.xu.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0
> },
> - { "vfcvt.f.x.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0
> },
> - { "vfcvt.rtz.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0,
> 0, 0 },
> - { "vfcvt.rtz.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0,
> 0 },
> - { "vfwcvt.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0
> },
> - { "vfwcvt.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0
> },
> - { "vfwcvt.f.xu.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0
> },
> - { "vfwcvt.f.x.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0
> },
> - { "vfwcvt.f.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0
> },
> - { "vfwcvt.rtz.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0,
> 0, 0 },
> - { "vfwcvt.rtz.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0,
> 0, 0 },
> - { "vfncvt.xu.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0
> },
> - { "vfncvt.x.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0
> },
> - { "vfncvt.f.xu.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0
> },
> - { "vfncvt.f.x.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0
> },
> - { "vfncvt.f.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0
> },
> - { "vfncvt.rod.f.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0,
> 0, 0 },
> - { "vfncvt.rtz.xu.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0,
> 0, 0 },
> - { "vfncvt.rtz.x.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0,
> 0, 0 },
> - { "vredsum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0,
> 0 },
> - { "vredand.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0,
> 0 },
> - { "vredor.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0
> },
> - { "vredxor.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0,
> 0 },
> - { "vredminu.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0,
> 0 },
> - { "vredmin.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0,
> 0 },
> - { "vredmaxu.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0,
> 0 },
> - { "vredmax.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0,
> 0 },
> - { "vwredsumu.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0,
> 0, 0 },
> - { "vwredsum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0,
> 0 },
> - { "vfredusum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0,
> 0, 0 },
> - { "vfredosum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0,
> 0, 0 },
> - { "vfredmin.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0,
> 0 },
> - { "vfredmax.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0,
> 0 },
> - { "vfwredusum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0,
> 0, 0 },
> - { "vfwredosum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0,
> 0, 0 },
> - { "vmand.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0
> },
> - { "vmnand.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0
> },
> - { "vmandn.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0
> },
> - { "vmxor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0
> },
> - { "vmor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0
> },
> - { "vmnor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0
> },
> - { "vmorn.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0
> },
> - { "vmxnor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0
> },
> - { "vcpop.m", rv_codec_v_r, rv_fmt_rd_vs2_vm, NULL, 0, 0, 0 },
> - { "vfirst.m", rv_codec_v_r, rv_fmt_rd_vs2_vm, NULL, 0, 0, 0 },
> - { "vmsbf.m", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
> - { "vmsif.m", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
> - { "vmsof.m", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
> - { "viota.m", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
> - { "vid.v", rv_codec_v_r, rv_fmt_vd_vm, NULL, 0, 0, 0 },
> - { "vmv.x.s", rv_codec_v_r, rv_fmt_rd_vs2, NULL, 0, 0, 0 },
> - { "vmv.s.x", rv_codec_v_r, rv_fmt_vd_rs1, NULL, 0, 0, 0 },
> - { "vfmv.f.s", rv_codec_v_r, rv_fmt_fd_vs2, NULL, 0, 0, 0 },
> - { "vfmv.s.f", rv_codec_v_r, rv_fmt_vd_fs1, NULL, 0, 0, 0 },
> - { "vslideup.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0,
> 0 },
> - { "vslideup.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm, NULL, 0,
> 0, 0 },
> - { "vslide1up.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0,
> 0, 0 },
> - { "vslidedown.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0,
> 0, 0 },
> - { "vslidedown.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm, NULL,
> 0, 0, 0 },
> - { "vslide1down.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0,
> 0, 0 },
> - { "vrgather.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0,
> 0 },
> - { "vrgatherei16.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL,
> 0, 0, 0 },
> - { "vrgather.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0,
> 0 },
> - { "vrgather.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm, NULL, 0,
> 0, 0 },
> - { "vcompress.vm", rv_codec_v_r, rv_fmt_vd_vs2_vs1, NULL, 0, 0, 0
> },
> - { "vmv1r.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
> - { "vmv2r.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
> - { "vmv4r.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
> - { "vmv8r.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
> - { "vzext.vf2", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
> - { "vzext.vf4", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
> - { "vzext.vf8", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
> - { "vsext.vf2", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
> - { "vsext.vf4", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
> - { "vsext.vf8", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
> - { "vsetvli", rv_codec_vsetvli, rv_fmt_vsetvli, NULL, 0, 0, 0 },
> - { "vsetivli", rv_codec_vsetivli, rv_fmt_vsetivli, NULL, 0, 0, 0
> },
> - { "vsetvl", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
> - { "c.zext.b", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 },
> - { "c.sext.b", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 },
> - { "c.zext.h", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 },
> - { "c.sext.h", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 },
> - { "c.zext.w", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 },
> - { "c.not", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 },
> - { "c.mul", rv_codec_zcb_mul, rv_fmt_rd_rs2, NULL, 0, 0 },
> - { "c.lbu", rv_codec_zcb_lb, rv_fmt_rs1_rs2_zce_ldst, NULL, 0, 0,
> 0 },
> - { "c.lhu", rv_codec_zcb_lh, rv_fmt_rs1_rs2_zce_ldst, NULL, 0, 0,
> 0 },
> - { "c.lh", rv_codec_zcb_lh, rv_fmt_rs1_rs2_zce_ldst, NULL, 0, 0,
> 0 },
> - { "c.sb", rv_codec_zcb_lb, rv_fmt_rs1_rs2_zce_ldst, NULL, 0, 0,
> 0 },
> - { "c.sh", rv_codec_zcb_lh, rv_fmt_rs1_rs2_zce_ldst, NULL, 0, 0,
> 0 },
> - { "cm.push", rv_codec_zcmp_cm_pushpop, rv_fmt_push_rlist, NULL,
> 0, 0 },
> - { "cm.pop", rv_codec_zcmp_cm_pushpop, rv_fmt_pop_rlist, NULL, 0,
> 0 },
> - { "cm.popret", rv_codec_zcmp_cm_pushpop, rv_fmt_pop_rlist, NULL,
> 0, 0, 0 },
> - { "cm.popretz", rv_codec_zcmp_cm_pushpop, rv_fmt_pop_rlist,
> NULL, 0, 0 },
> - { "cm.mva01s", rv_codec_zcmp_cm_mv, rv_fmt_rd_rs2, NULL, 0, 0, 0
> },
> - { "cm.mvsa01", rv_codec_zcmp_cm_mv, rv_fmt_rd_rs2, NULL, 0, 0, 0
> },
> - { "cm.jt", rv_codec_zcmt_jt, rv_fmt_zcmt_index, NULL, 0 },
> - { "cm.jalt", rv_codec_zcmt_jt, rv_fmt_zcmt_index, NULL, 0 },
> - { "czero.eqz", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
> - { "czero.nez", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
> - { "fcvt.bf16.s", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0
> },
> - { "fcvt.s.bf16", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0
> },
> - { "vfncvtbf16.f.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0,
> 0, 0 },
> - { "vfwcvtbf16.f.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0,
> 0, 0 },
> - { "vfwmaccbf16.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0,
> 0, 0 },
> - { "vfwmaccbf16.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0,
> 0, 0 },
> - { "flh", rv_codec_i, rv_fmt_frd_offset_rs1, NULL, 0, 0, 0 },
> - { "fsh", rv_codec_s, rv_fmt_frs2_offset_rs1, NULL, 0, 0, 0 },
> - { "fmv.h.x", rv_codec_r, rv_fmt_frd_rs1, NULL, 0, 0, 0 },
> - { "fmv.x.h", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 },
> - { "fli.s", rv_codec_fli, rv_fmt_fli, NULL, 0, 0, 0 },
> - { "fli.d", rv_codec_fli, rv_fmt_fli, NULL, 0, 0, 0 },
> - { "fli.q", rv_codec_fli, rv_fmt_fli, NULL, 0, 0, 0 },
> - { "fli.h", rv_codec_fli, rv_fmt_fli, NULL, 0, 0, 0 },
> - { "fminm.s", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 },
> - { "fmaxm.s", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 },
> - { "fminm.d", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 },
> - { "fmaxm.d", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 },
> - { "fminm.q", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 },
> - { "fmaxm.q", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 },
> - { "fminm.h", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 },
> - { "fmaxm.h", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 },
> - { "fround.s", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },
> - { "froundnx.s", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0
> },
> - { "fround.d", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },
> - { "froundnx.d", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0
> },
> - { "fround.q", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },
> - { "froundnx.q", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0
> },
> - { "fround.h", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },
> - { "froundnx.h", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0
> },
> - { "fcvtmod.w.d", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0
> },
> - { "fmvh.x.d", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 },
> - { "fmvp.d.x", rv_codec_r, rv_fmt_frd_rs1_rs2, NULL, 0, 0, 0 },
> - { "fmvh.x.q", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 },
> - { "fmvp.q.x", rv_codec_r, rv_fmt_frd_rs1_rs2, NULL, 0, 0, 0 },
> - { "fleq.s", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 },
> - { "fltq.s", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 },
> - { "fleq.d", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 },
> - { "fltq.d", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 },
> - { "fleq.q", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 },
> - { "fltq.q", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 },
> - { "fleq.h", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 },
> - { "fltq.h", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 },
> - { "vaesdf.vv", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
> - { "vaesdf.vs", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
> - { "vaesdm.vv", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
> - { "vaesdm.vs", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
> - { "vaesef.vv", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
> - { "vaesef.vs", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
> - { "vaesem.vv", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
> - { "vaesem.vs", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
> - { "vaeskf1.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm, NULL, 0, 0,
> 0 },
> - { "vaeskf2.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm, NULL, 0, 0,
> 0 },
> - { "vaesz.vs", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
> - { "vandn.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0
> },
> - { "vandn.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0
> },
> - { "vbrev.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
> - { "vbrev8.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
> - { "vclmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0
> },
> - { "vclmul.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0
> },
> - { "vclmulh.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0,
> 0 },
> - { "vclmulh.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0,
> 0 },
> - { "vclz.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
> - { "vcpop.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
> - { "vctz.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
> - { "vghsh.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1, NULL, 0, 0, 0 },
> - { "vgmul.vv", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
> - { "vrev8.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
> - { "vrol.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0
> },
> - { "vrol.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0
> },
> - { "vror.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0
> },
> - { "vror.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0
> },
> - { "vror.vi", rv_codec_vror_vi, rv_fmt_vd_vs2_uimm_vm, NULL, 0,
> 0, 0 },
> - { "vsha2ch.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1, NULL, 0, 0, 0
> },
> - { "vsha2cl.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1, NULL, 0, 0, 0
> },
> - { "vsha2ms.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1, NULL, 0, 0, 0
> },
> - { "vsm3c.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm, NULL, 0, 0, 0
> },
> - { "vsm3me.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1, NULL, 0, 0, 0 },
> - { "vsm4k.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm, NULL, 0, 0, 0
> },
> - { "vsm4r.vv", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
> - { "vsm4r.vs", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
> - { "vwsll.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0
> },
> - { "vwsll.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0
> },
> - { "vwsll.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0,
> 0 },
> - { "amocas.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0,
> 0 },
> - { "amocas.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0,
> 0 },
> - { "amocas.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0,
> 0 },
> - { "mop.r.0", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
> - { "mop.r.1", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
> - { "mop.r.2", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
> - { "mop.r.3", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
> - { "mop.r.4", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
> - { "mop.r.5", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
> - { "mop.r.6", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
> - { "mop.r.7", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
> - { "mop.r.8", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
> - { "mop.r.9", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
> - { "mop.r.10", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
> - { "mop.r.11", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
> - { "mop.r.12", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
> - { "mop.r.13", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
> - { "mop.r.14", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
> - { "mop.r.15", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
> - { "mop.r.16", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
> - { "mop.r.17", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
> - { "mop.r.18", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
> - { "mop.r.19", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
> - { "mop.r.20", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
> - { "mop.r.21", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
> - { "mop.r.22", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
> - { "mop.r.23", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
> - { "mop.r.24", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
> - { "mop.r.25", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
> - { "mop.r.26", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
> - { "mop.r.27", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
> - { "mop.r.28", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
> - { "mop.r.29", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
> - { "mop.r.30", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
> - { "mop.r.31", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
> - { "mop.rr.0", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
> - { "mop.rr.1", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
> - { "mop.rr.2", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
> - { "mop.rr.3", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
> - { "mop.rr.4", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
> - { "mop.rr.5", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
> - { "mop.rr.6", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
> - { "mop.rr.7", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
> - { "c.mop.1", rv_codec_ci_none, rv_fmt_none, NULL, 0, 0, 0 },
> - { "c.mop.3", rv_codec_ci_none, rv_fmt_none, NULL, 0, 0, 0 },
> - { "c.mop.5", rv_codec_ci_none, rv_fmt_none, NULL, 0, 0, 0 },
> - { "c.mop.7", rv_codec_ci_none, rv_fmt_none, NULL, 0, 0, 0 },
> - { "c.mop.9", rv_codec_ci_none, rv_fmt_none, NULL, 0, 0, 0 },
> - { "c.mop.11", rv_codec_ci_none, rv_fmt_none, NULL, 0, 0, 0 },
> - { "c.mop.13", rv_codec_ci_none, rv_fmt_none, NULL, 0, 0, 0 },
> - { "c.mop.15", rv_codec_ci_none, rv_fmt_none, NULL, 0, 0, 0 },
> - { "amoswap.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0,
> 0 },
> - { "amoadd.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0,
> 0 },
> - { "amoxor.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0,
> 0 },
> - { "amoor.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0
> },
> - { "amoand.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0,
> 0 },
> - { "amomin.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0,
> 0 },
> - { "amomax.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0,
> 0 },
> - { "amominu.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0,
> 0 },
> - { "amomaxu.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0,
> 0 },
> - { "amoswap.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0,
> 0 },
> - { "amoadd.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0,
> 0 },
> - { "amoxor.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0,
> 0 },
> - { "amoor.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0
> },
> - { "amoand.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0,
> 0 },
> - { "amomin.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0,
> 0 },
> - { "amomax.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0,
> 0 },
> - { "amominu.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0,
> 0 },
> - { "amomaxu.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0,
> 0 },
> - { "amocas.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0,
> 0 },
> - { "amocas.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0,
> 0 },
> - { "wrs.sto", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
> - { "wrs.nto", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
> - { "lpad", rv_codec_lp, rv_fmt_imm, NULL, 0, 0, 0 },
> - { "sspush", rv_codec_r, rv_fmt_rs2, NULL, 0, 0, 0 },
> - { "sspopchk", rv_codec_r, rv_fmt_rs1, NULL, 0, 0, 0 },
> - { "ssrdp", rv_codec_r, rv_fmt_rd, NULL, 0, 0, 0 },
> - { "ssamoswap.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0,
> 0, 0 },
> - { "ssamoswap.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0,
> 0, 0 },
> + { "nop", rv_codec_i, rv_fmt_none },
> + { "mv", rv_codec_i, rv_fmt_rd_rs1 },
> + { "not", rv_codec_i, rv_fmt_rd_rs1 },
> + { "neg", rv_codec_r, rv_fmt_rd_rs2 },
> + { "negw", rv_codec_r, rv_fmt_rd_rs2 },
> + { "sext.w", rv_codec_i, rv_fmt_rd_rs1 },
> + { "seqz", rv_codec_i, rv_fmt_rd_rs1 },
> + { "snez", rv_codec_r, rv_fmt_rd_rs2 },
> + { "sltz", rv_codec_r, rv_fmt_rd_rs1 },
> + { "sgtz", rv_codec_r, rv_fmt_rd_rs2 },
> + { "fmv.s", rv_codec_r, rv_fmt_frd_frs1 },
> + { "fabs.s", rv_codec_r, rv_fmt_frd_frs1 },
> + { "fneg.s", rv_codec_r, rv_fmt_frd_frs1 },
> + { "fmv.d", rv_codec_r, rv_fmt_frd_frs1 },
> + { "fabs.d", rv_codec_r, rv_fmt_frd_frs1 },
> + { "fneg.d", rv_codec_r, rv_fmt_frd_frs1 },
> + { "fmv.q", rv_codec_r, rv_fmt_frd_frs1 },
> + { "fabs.q", rv_codec_r, rv_fmt_frd_frs1 },
> + { "fneg.q", rv_codec_r, rv_fmt_frd_frs1 },
> + { "beqz", rv_codec_sb, rv_fmt_rs1_offset },
> + { "bnez", rv_codec_sb, rv_fmt_rs1_offset },
> + { "blez", rv_codec_sb, rv_fmt_rs2_offset },
> + { "bgez", rv_codec_sb, rv_fmt_rs1_offset },
> + { "bltz", rv_codec_sb, rv_fmt_rs1_offset },
> + { "bgtz", rv_codec_sb, rv_fmt_rs2_offset },
> + { "ble", rv_codec_sb, rv_fmt_rs2_rs1_offset },
> + { "bleu", rv_codec_sb, rv_fmt_rs2_rs1_offset },
> + { "bgt", rv_codec_sb, rv_fmt_rs2_rs1_offset },
> + { "bgtu", rv_codec_sb, rv_fmt_rs2_rs1_offset },
> + { "j", rv_codec_uj, rv_fmt_offset },
> + { "ret", rv_codec_i, rv_fmt_none },
> + { "jr", rv_codec_i, rv_fmt_rs1 },
> + { "rdcycle", rv_codec_i_csr, rv_fmt_rd },
> + { "rdtime", rv_codec_i_csr, rv_fmt_rd },
> + { "rdinstret", rv_codec_i_csr, rv_fmt_rd },
> + { "rdcycleh", rv_codec_i_csr, rv_fmt_rd },
> + { "rdtimeh", rv_codec_i_csr, rv_fmt_rd },
> + { "rdinstreth", rv_codec_i_csr, rv_fmt_rd },
> + { "frcsr", rv_codec_i_csr, rv_fmt_rd },
> + { "frrm", rv_codec_i_csr, rv_fmt_rd },
> + { "frflags", rv_codec_i_csr, rv_fmt_rd },
> + { "fscsr", rv_codec_i_csr, rv_fmt_rd_rs1 },
> + { "fsrm", rv_codec_i_csr, rv_fmt_rd_rs1 },
> + { "fsflags", rv_codec_i_csr, rv_fmt_rd_rs1 },
> + { "fsrmi", rv_codec_i_csr, rv_fmt_rd_zimm },
> + { "fsflagsi", rv_codec_i_csr, rv_fmt_rd_zimm },
> + { "bseti", rv_codec_i_sh7, rv_fmt_rd_rs1_imm },
> + { "bclri", rv_codec_i_sh7, rv_fmt_rd_rs1_imm },
> + { "binvi", rv_codec_i_sh7, rv_fmt_rd_rs1_imm },
> + { "bexti", rv_codec_i_sh7, rv_fmt_rd_rs1_imm },
> + { "rori", rv_codec_i_sh7, rv_fmt_rd_rs1_imm },
> + { "clz", rv_codec_r, rv_fmt_rd_rs1 },
> + { "ctz", rv_codec_r, rv_fmt_rd_rs1 },
> + { "cpop", rv_codec_r, rv_fmt_rd_rs1 },
> + { "sext.h", rv_codec_r, rv_fmt_rd_rs1 },
> + { "sext.b", rv_codec_r, rv_fmt_rd_rs1 },
> + { "xnor", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> + { "orn", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> + { "andn", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> + { "rol", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> + { "ror", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> + { "sh1add", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> + { "sh2add", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> + { "sh3add", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> + { "sh1add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> + { "sh2add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> + { "sh3add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> + { "clmul", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> + { "clmulr", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> + { "clmulh", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> + { "min", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> + { "minu", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> + { "max", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> + { "maxu", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> + { "clzw", rv_codec_r, rv_fmt_rd_rs1 },
> + { "ctzw", rv_codec_r, rv_fmt_rd_rs1 },
> + { "cpopw", rv_codec_r, rv_fmt_rd_rs1 },
> + { "slli.uw", rv_codec_i_sh6, rv_fmt_rd_rs1_imm },
> + { "add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> + { "rolw", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> + { "rorw", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> + { "rev8", rv_codec_r, rv_fmt_rd_rs1 },
> + { "zext.h", rv_codec_r, rv_fmt_rd_rs1 },
> + { "roriw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm },
> + { "orc.b", rv_codec_r, rv_fmt_rd_rs1 },
> + { "bset", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> + { "bclr", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> + { "binv", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> + { "bext", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> + { "aes32esmi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs },
> + { "aes32esi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs },
> + { "aes32dsmi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs },
> + { "aes32dsi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs },
> + { "aes64ks1i", rv_codec_k_rnum, rv_fmt_rd_rs1_rnum },
> + { "aes64ks2", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> + { "aes64im", rv_codec_r, rv_fmt_rd_rs1 },
> + { "aes64esm", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> + { "aes64es", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> + { "aes64dsm", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> + { "aes64ds", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> + { "sha256sig0", rv_codec_r, rv_fmt_rd_rs1 },
> + { "sha256sig1", rv_codec_r, rv_fmt_rd_rs1 },
> + { "sha256sum0", rv_codec_r, rv_fmt_rd_rs1 },
> + { "sha256sum1", rv_codec_r, rv_fmt_rd_rs1 },
> + { "sha512sig0", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> + { "sha512sig1", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> + { "sha512sum0", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> + { "sha512sum1", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> + { "sha512sum0r", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> + { "sha512sum1r", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> + { "sha512sig0l", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> + { "sha512sig0h", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> + { "sha512sig1l", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> + { "sha512sig1h", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> + { "sm3p0", rv_codec_r, rv_fmt_rd_rs1 },
> + { "sm3p1", rv_codec_r, rv_fmt_rd_rs1 },
> + { "sm4ed", rv_codec_k_bs, rv_fmt_rs1_rs2_bs },
> + { "sm4ks", rv_codec_k_bs, rv_fmt_rs1_rs2_bs },
> + { "brev8", rv_codec_r, rv_fmt_rd_rs1 },
> + { "pack", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> + { "packh", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> + { "packw", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> + { "unzip", rv_codec_r, rv_fmt_rd_rs1 },
> + { "zip", rv_codec_r, rv_fmt_rd_rs1 },
> + { "xperm4", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> + { "xperm8", rv_codec_r, rv_fmt_rd_rs1 },
> + { "vle8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
> + { "vle16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
> + { "vle32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
> + { "vle64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
> + { "vse8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
> + { "vse16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
> + { "vse32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
> + { "vse64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
> + { "vlm.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
> + { "vsm.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
> + { "vlse8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm },
> + { "vlse16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm },
> + { "vlse32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm },
> + { "vlse64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm },
> + { "vsse8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm },
> + { "vsse16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm },
> + { "vsse32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm },
> + { "vsse64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm },
> + { "vluxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm },
> + { "vluxei16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm },
> + { "vluxei32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm },
> + { "vluxei64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm },
> + { "vloxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm },
> + { "vloxei16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm },
> + { "vloxei32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm },
> + { "vloxei64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm },
> + { "vsuxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm },
> + { "vsuxei16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm },
> + { "vsuxei32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm },
> + { "vsuxei64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm },
> + { "vsoxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm },
> + { "vsoxei16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm },
> + { "vsoxei32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm },
> + { "vsoxei64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm },
> + { "vle8ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
> + { "vle16ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
> + { "vle32ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
> + { "vle64ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
> + { "vl1re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
> + { "vl1re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
> + { "vl1re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
> + { "vl1re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
> + { "vl2re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
> + { "vl2re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
> + { "vl2re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
> + { "vl2re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
> + { "vl4re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
> + { "vl4re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
> + { "vl4re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
> + { "vl4re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
> + { "vl8re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
> + { "vl8re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
> + { "vl8re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
> + { "vl8re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
> + { "vs1r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
> + { "vs2r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
> + { "vs4r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
> + { "vs8r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
> + { "vadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> + { "vadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
> + { "vadd.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm },
> + { "vsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> + { "vsub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
> + { "vrsub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
> + { "vrsub.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm },
> + { "vwaddu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> + { "vwaddu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
> + { "vwadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> + { "vwadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
> + { "vwsubu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> + { "vwsubu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
> + { "vwsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> + { "vwsub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
> + { "vwaddu.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> + { "vwaddu.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
> + { "vwadd.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> + { "vwadd.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
> + { "vwsubu.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> + { "vwsubu.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
> + { "vwsub.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> + { "vwsub.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
> + { "vadc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl },
> + { "vadc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl },
> + { "vadc.vim", rv_codec_v_i, rv_fmt_vd_vs2_imm_vl },
> + { "vmadc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl },
> + { "vmadc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl },
> + { "vmadc.vim", rv_codec_v_i, rv_fmt_vd_vs2_imm_vl },
> + { "vsbc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl },
> + { "vsbc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl },
> + { "vmsbc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl },
> + { "vmsbc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl },
> + { "vand.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> + { "vand.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
> + { "vand.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm },
> + { "vor.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> + { "vor.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
> + { "vor.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm },
> + { "vxor.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> + { "vxor.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
> + { "vxor.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm },
> + { "vsll.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> + { "vsll.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
> + { "vsll.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm },
> + { "vsrl.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> + { "vsrl.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
> + { "vsrl.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm },
> + { "vsra.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> + { "vsra.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
> + { "vsra.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm },
> + { "vnsrl.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> + { "vnsrl.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
> + { "vnsrl.wi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm },
> + { "vnsra.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> + { "vnsra.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
> + { "vnsra.wi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm },
> + { "vmseq.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> + { "vmseq.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
> + { "vmseq.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm },
> + { "vmsne.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> + { "vmsne.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
> + { "vmsne.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm },
> + { "vmsltu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> + { "vmsltu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
> + { "vmslt.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> + { "vmslt.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
> + { "vmsleu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> + { "vmsleu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
> + { "vmsleu.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm },
> + { "vmsle.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> + { "vmsle.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
> + { "vmsle.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm },
> + { "vmsgtu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
> + { "vmsgtu.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm },
> + { "vmsgt.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
> + { "vmsgt.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm },
> + { "vminu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> + { "vminu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
> + { "vmin.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> + { "vmin.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
> + { "vmaxu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> + { "vmaxu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
> + { "vmax.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> + { "vmax.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
> + { "vmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> + { "vmul.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
> + { "vmulh.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> + { "vmulh.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
> + { "vmulhu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> + { "vmulhu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
> + { "vmulhsu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> + { "vmulhsu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
> + { "vdivu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> + { "vdivu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
> + { "vdiv.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> + { "vdiv.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
> + { "vremu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> + { "vremu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
> + { "vrem.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> + { "vrem.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
> + { "vwmulu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> + { "vwmulu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
> + { "vwmulsu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> + { "vwmulsu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
> + { "vwmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> + { "vwmul.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
> + { "vmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm },
> + { "vmacc.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm },
> + { "vnmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm },
> + { "vnmsac.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm },
> + { "vmadd.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm },
> + { "vmadd.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm },
> + { "vnmsub.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm },
> + { "vnmsub.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm },
> + { "vwmaccu.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm },
> + { "vwmaccu.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm },
> + { "vwmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm },
> + { "vwmacc.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm },
> + { "vwmaccsu.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm },
> + { "vwmaccsu.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm },
> + { "vwmaccus.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm },
> + { "vmv.v.v", rv_codec_v_r, rv_fmt_vd_vs1 },
> + { "vmv.v.x", rv_codec_v_r, rv_fmt_vd_rs1 },
> + { "vmv.v.i", rv_codec_v_i, rv_fmt_vd_imm },
> + { "vmerge.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl },
> + { "vmerge.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl },
> + { "vmerge.vim", rv_codec_v_i, rv_fmt_vd_vs2_imm_vl },
> + { "vsaddu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> + { "vsaddu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
> + { "vsaddu.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm },
> + { "vsadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> + { "vsadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
> + { "vsadd.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm },
> + { "vssubu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> + { "vssubu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
> + { "vssub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> + { "vssub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
> + { "vaadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> + { "vaadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
> + { "vaaddu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> + { "vaaddu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
> + { "vasub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> + { "vasub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
> + { "vasubu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> + { "vasubu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
> + { "vsmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> + { "vsmul.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
> + { "vssrl.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> + { "vssrl.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
> + { "vssrl.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm },
> + { "vssra.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> + { "vssra.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
> + { "vssra.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm },
> + { "vnclipu.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> + { "vnclipu.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
> + { "vnclipu.wi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm },
> + { "vnclip.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> + { "vnclip.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
> + { "vnclip.wi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm },
> + { "vfadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> + { "vfadd.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm },
> + { "vfsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> + { "vfsub.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm },
> + { "vfrsub.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm },
> + { "vfwadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> + { "vfwadd.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm },
> + { "vfwadd.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> + { "vfwadd.wf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm },
> + { "vfwsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> + { "vfwsub.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm },
> + { "vfwsub.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> + { "vfwsub.wf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm },
> + { "vfmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> + { "vfmul.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm },
> + { "vfdiv.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> + { "vfdiv.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm },
> + { "vfrdiv.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm },
> + { "vfwmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> + { "vfwmul.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm },
> + { "vfmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm },
> + { "vfmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm },
> + { "vfnmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm },
> + { "vfnmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm },
> + { "vfmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm },
> + { "vfmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm },
> + { "vfnmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm },
> + { "vfnmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm },
> + { "vfmadd.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm },
> + { "vfmadd.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm },
> + { "vfnmadd.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm },
> + { "vfnmadd.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm },
> + { "vfmsub.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm },
> + { "vfmsub.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm },
> + { "vfnmsub.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm },
> + { "vfnmsub.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm },
> + { "vfwmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm },
> + { "vfwmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm },
> + { "vfwnmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm },
> + { "vfwnmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm },
> + { "vfwmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm },
> + { "vfwmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm },
> + { "vfwnmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm },
> + { "vfwnmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm },
> + { "vfsqrt.v", rv_codec_v_r, rv_fmt_vd_vs2 },
> + { "vfrsqrt7.v", rv_codec_v_r, rv_fmt_vd_vs2 },
> + { "vfrec7.v", rv_codec_v_r, rv_fmt_vd_vs2 },
> + { "vfmin.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> + { "vfmin.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm },
> + { "vfmax.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> + { "vfmax.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm },
> + { "vfsgnj.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> + { "vfsgnj.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm },
> + { "vfsgnjn.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> + { "vfsgnjn.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm },
> + { "vfsgnjx.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> + { "vfsgnjx.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm },
> + { "vfslide1up.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm },
> + { "vfslide1down.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm },
> + { "vmfeq.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> + { "vmfeq.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm },
> + { "vmfne.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> + { "vmfne.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm },
> + { "vmflt.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> + { "vmflt.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm },
> + { "vmfle.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> + { "vmfle.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm },
> + { "vmfgt.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm },
> + { "vmfge.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm },
> + { "vfclass.v", rv_codec_v_r, rv_fmt_vd_vs2_vm },
> + { "vfmerge.vfm", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vl },
> + { "vfmv.v.f", rv_codec_v_r, rv_fmt_vd_fs1 },
> + { "vfcvt.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm },
> + { "vfcvt.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm },
> + { "vfcvt.f.xu.v", rv_codec_v_r, rv_fmt_vd_vs2_vm },
> + { "vfcvt.f.x.v", rv_codec_v_r, rv_fmt_vd_vs2_vm },
> + { "vfcvt.rtz.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm },
> + { "vfcvt.rtz.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm },
> + { "vfwcvt.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm },
> + { "vfwcvt.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm },
> + { "vfwcvt.f.xu.v", rv_codec_v_r, rv_fmt_vd_vs2_vm },
> + { "vfwcvt.f.x.v", rv_codec_v_r, rv_fmt_vd_vs2_vm },
> + { "vfwcvt.f.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm },
> + { "vfwcvt.rtz.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm },
> + { "vfwcvt.rtz.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm },
> + { "vfncvt.xu.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm },
> + { "vfncvt.x.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm },
> + { "vfncvt.f.xu.w", rv_codec_v_r, rv_fmt_vd_vs2_vm },
> + { "vfncvt.f.x.w", rv_codec_v_r, rv_fmt_vd_vs2_vm },
> + { "vfncvt.f.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm },
> + { "vfncvt.rod.f.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm },
> + { "vfncvt.rtz.xu.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm },
> + { "vfncvt.rtz.x.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm },
> + { "vredsum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> + { "vredand.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> + { "vredor.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> + { "vredxor.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> + { "vredminu.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> + { "vredmin.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> + { "vredmaxu.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> + { "vredmax.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> + { "vwredsumu.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> + { "vwredsum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> + { "vfredusum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> + { "vfredosum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> + { "vfredmin.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> + { "vfredmax.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> + { "vfwredusum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> + { "vfwredosum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> + { "vmand.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> + { "vmnand.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> + { "vmandn.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> + { "vmxor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> + { "vmor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> + { "vmnor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> + { "vmorn.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> + { "vmxnor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> + { "vcpop.m", rv_codec_v_r, rv_fmt_rd_vs2_vm },
> + { "vfirst.m", rv_codec_v_r, rv_fmt_rd_vs2_vm },
> + { "vmsbf.m", rv_codec_v_r, rv_fmt_vd_vs2_vm },
> + { "vmsif.m", rv_codec_v_r, rv_fmt_vd_vs2_vm },
> + { "vmsof.m", rv_codec_v_r, rv_fmt_vd_vs2_vm },
> + { "viota.m", rv_codec_v_r, rv_fmt_vd_vs2_vm },
> + { "vid.v", rv_codec_v_r, rv_fmt_vd_vm },
> + { "vmv.x.s", rv_codec_v_r, rv_fmt_rd_vs2 },
> + { "vmv.s.x", rv_codec_v_r, rv_fmt_vd_rs1 },
> + { "vfmv.f.s", rv_codec_v_r, rv_fmt_fd_vs2 },
> + { "vfmv.s.f", rv_codec_v_r, rv_fmt_vd_fs1 },
> + { "vslideup.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
> + { "vslideup.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm },
> + { "vslide1up.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
> + { "vslidedown.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
> + { "vslidedown.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm },
> + { "vslide1down.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
> + { "vrgather.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> + { "vrgatherei16.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> + { "vrgather.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
> + { "vrgather.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm },
> + { "vcompress.vm", rv_codec_v_r, rv_fmt_vd_vs2_vs1 },
> + { "vmv1r.v", rv_codec_v_r, rv_fmt_vd_vs2 },
> + { "vmv2r.v", rv_codec_v_r, rv_fmt_vd_vs2 },
> + { "vmv4r.v", rv_codec_v_r, rv_fmt_vd_vs2 },
> + { "vmv8r.v", rv_codec_v_r, rv_fmt_vd_vs2 },
> + { "vzext.vf2", rv_codec_v_r, rv_fmt_vd_vs2_vm },
> + { "vzext.vf4", rv_codec_v_r, rv_fmt_vd_vs2_vm },
> + { "vzext.vf8", rv_codec_v_r, rv_fmt_vd_vs2_vm },
> + { "vsext.vf2", rv_codec_v_r, rv_fmt_vd_vs2_vm },
> + { "vsext.vf4", rv_codec_v_r, rv_fmt_vd_vs2_vm },
> + { "vsext.vf8", rv_codec_v_r, rv_fmt_vd_vs2_vm },
> + { "vsetvli", rv_codec_vsetvli, rv_fmt_vsetvli },
> + { "vsetivli", rv_codec_vsetivli, rv_fmt_vsetivli },
> + { "vsetvl", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> + { "c.zext.b", rv_codec_zcb_ext, rv_fmt_rd },
> + { "c.sext.b", rv_codec_zcb_ext, rv_fmt_rd },
> + { "c.zext.h", rv_codec_zcb_ext, rv_fmt_rd },
> + { "c.sext.h", rv_codec_zcb_ext, rv_fmt_rd },
> + { "c.zext.w", rv_codec_zcb_ext, rv_fmt_rd },
> + { "c.not", rv_codec_zcb_ext, rv_fmt_rd },
> + { "c.mul", rv_codec_zcb_mul, rv_fmt_rd_rs2 },
> + { "c.lbu", rv_codec_zcb_lb, rv_fmt_rs1_rs2_zce_ldst },
> + { "c.lhu", rv_codec_zcb_lh, rv_fmt_rs1_rs2_zce_ldst },
> + { "c.lh", rv_codec_zcb_lh, rv_fmt_rs1_rs2_zce_ldst },
> + { "c.sb", rv_codec_zcb_lb, rv_fmt_rs1_rs2_zce_ldst },
> + { "c.sh", rv_codec_zcb_lh, rv_fmt_rs1_rs2_zce_ldst },
> + { "cm.push", rv_codec_zcmp_cm_pushpop, rv_fmt_push_rlist },
> + { "cm.pop", rv_codec_zcmp_cm_pushpop, rv_fmt_pop_rlist },
> + { "cm.popret", rv_codec_zcmp_cm_pushpop, rv_fmt_pop_rlist },
> + { "cm.popretz", rv_codec_zcmp_cm_pushpop, rv_fmt_pop_rlist },
> + { "cm.mva01s", rv_codec_zcmp_cm_mv, rv_fmt_rd_rs2 },
> + { "cm.mvsa01", rv_codec_zcmp_cm_mv, rv_fmt_rd_rs2 },
> + { "cm.jt", rv_codec_zcmt_jt, rv_fmt_zcmt_index },
> + { "cm.jalt", rv_codec_zcmt_jt, rv_fmt_zcmt_index },
> + { "czero.eqz", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> + { "czero.nez", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> + { "fcvt.bf16.s", rv_codec_r_m, rv_fmt_rm_frd_frs1 },
> + { "fcvt.s.bf16", rv_codec_r_m, rv_fmt_rm_frd_frs1 },
> + { "vfncvtbf16.f.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm },
> + { "vfwcvtbf16.f.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm },
> + { "vfwmaccbf16.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm },
> + { "vfwmaccbf16.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm },
> + { "flh", rv_codec_i, rv_fmt_frd_offset_rs1 },
> + { "fsh", rv_codec_s, rv_fmt_frs2_offset_rs1 },
> + { "fmv.h.x", rv_codec_r, rv_fmt_frd_rs1 },
> + { "fmv.x.h", rv_codec_r, rv_fmt_rd_frs1 },
> + { "fli.s", rv_codec_fli, rv_fmt_fli },
> + { "fli.d", rv_codec_fli, rv_fmt_fli },
> + { "fli.q", rv_codec_fli, rv_fmt_fli },
> + { "fli.h", rv_codec_fli, rv_fmt_fli },
> + { "fminm.s", rv_codec_r, rv_fmt_frd_frs1_frs2 },
> + { "fmaxm.s", rv_codec_r, rv_fmt_frd_frs1_frs2 },
> + { "fminm.d", rv_codec_r, rv_fmt_frd_frs1_frs2 },
> + { "fmaxm.d", rv_codec_r, rv_fmt_frd_frs1_frs2 },
> + { "fminm.q", rv_codec_r, rv_fmt_frd_frs1_frs2 },
> + { "fmaxm.q", rv_codec_r, rv_fmt_frd_frs1_frs2 },
> + { "fminm.h", rv_codec_r, rv_fmt_frd_frs1_frs2 },
> + { "fmaxm.h", rv_codec_r, rv_fmt_frd_frs1_frs2 },
> + { "fround.s", rv_codec_r_m, rv_fmt_rm_frd_frs1 },
> + { "froundnx.s", rv_codec_r_m, rv_fmt_rm_frd_frs1 },
> + { "fround.d", rv_codec_r_m, rv_fmt_rm_frd_frs1 },
> + { "froundnx.d", rv_codec_r_m, rv_fmt_rm_frd_frs1 },
> + { "fround.q", rv_codec_r_m, rv_fmt_rm_frd_frs1 },
> + { "froundnx.q", rv_codec_r_m, rv_fmt_rm_frd_frs1 },
> + { "fround.h", rv_codec_r_m, rv_fmt_rm_frd_frs1 },
> + { "froundnx.h", rv_codec_r_m, rv_fmt_rm_frd_frs1 },
> + { "fcvtmod.w.d", rv_codec_r_m, rv_fmt_rm_rd_frs1 },
> + { "fmvh.x.d", rv_codec_r, rv_fmt_rd_frs1 },
> + { "fmvp.d.x", rv_codec_r, rv_fmt_frd_rs1_rs2 },
> + { "fmvh.x.q", rv_codec_r, rv_fmt_rd_frs1 },
> + { "fmvp.q.x", rv_codec_r, rv_fmt_frd_rs1_rs2 },
> + { "fleq.s", rv_codec_r, rv_fmt_rd_frs1_frs2 },
> + { "fltq.s", rv_codec_r, rv_fmt_rd_frs1_frs2 },
> + { "fleq.d", rv_codec_r, rv_fmt_rd_frs1_frs2 },
> + { "fltq.d", rv_codec_r, rv_fmt_rd_frs1_frs2 },
> + { "fleq.q", rv_codec_r, rv_fmt_rd_frs1_frs2 },
> + { "fltq.q", rv_codec_r, rv_fmt_rd_frs1_frs2 },
> + { "fleq.h", rv_codec_r, rv_fmt_rd_frs1_frs2 },
> + { "fltq.h", rv_codec_r, rv_fmt_rd_frs1_frs2 },
> + { "vaesdf.vv", rv_codec_v_r, rv_fmt_vd_vs2 },
> + { "vaesdf.vs", rv_codec_v_r, rv_fmt_vd_vs2 },
> + { "vaesdm.vv", rv_codec_v_r, rv_fmt_vd_vs2 },
> + { "vaesdm.vs", rv_codec_v_r, rv_fmt_vd_vs2 },
> + { "vaesef.vv", rv_codec_v_r, rv_fmt_vd_vs2 },
> + { "vaesef.vs", rv_codec_v_r, rv_fmt_vd_vs2 },
> + { "vaesem.vv", rv_codec_v_r, rv_fmt_vd_vs2 },
> + { "vaesem.vs", rv_codec_v_r, rv_fmt_vd_vs2 },
> + { "vaeskf1.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm },
> + { "vaeskf2.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm },
> + { "vaesz.vs", rv_codec_v_r, rv_fmt_vd_vs2 },
> + { "vandn.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> + { "vandn.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
> + { "vbrev.v", rv_codec_v_r, rv_fmt_vd_vs2_vm },
> + { "vbrev8.v", rv_codec_v_r, rv_fmt_vd_vs2_vm },
> + { "vclmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> + { "vclmul.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
> + { "vclmulh.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> + { "vclmulh.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
> + { "vclz.v", rv_codec_v_r, rv_fmt_vd_vs2_vm },
> + { "vcpop.v", rv_codec_v_r, rv_fmt_vd_vs2_vm },
> + { "vctz.v", rv_codec_v_r, rv_fmt_vd_vs2_vm },
> + { "vghsh.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1 },
> + { "vgmul.vv", rv_codec_v_r, rv_fmt_vd_vs2 },
> + { "vrev8.v", rv_codec_v_r, rv_fmt_vd_vs2_vm },
> + { "vrol.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> + { "vrol.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
> + { "vror.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> + { "vror.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
> + { "vror.vi", rv_codec_vror_vi, rv_fmt_vd_vs2_uimm_vm },
> + { "vsha2ch.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1 },
> + { "vsha2cl.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1 },
> + { "vsha2ms.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1 },
> + { "vsm3c.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm },
> + { "vsm3me.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1 },
> + { "vsm4k.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm },
> + { "vsm4r.vv", rv_codec_v_r, rv_fmt_vd_vs2 },
> + { "vsm4r.vs", rv_codec_v_r, rv_fmt_vd_vs2 },
> + { "vwsll.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> + { "vwsll.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
> + { "vwsll.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm },
> + { "amocas.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
> + { "amocas.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
> + { "amocas.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
> + { "mop.r.0", rv_codec_r, rv_fmt_rd_rs1 },
> + { "mop.r.1", rv_codec_r, rv_fmt_rd_rs1 },
> + { "mop.r.2", rv_codec_r, rv_fmt_rd_rs1 },
> + { "mop.r.3", rv_codec_r, rv_fmt_rd_rs1 },
> + { "mop.r.4", rv_codec_r, rv_fmt_rd_rs1 },
> + { "mop.r.5", rv_codec_r, rv_fmt_rd_rs1 },
> + { "mop.r.6", rv_codec_r, rv_fmt_rd_rs1 },
> + { "mop.r.7", rv_codec_r, rv_fmt_rd_rs1 },
> + { "mop.r.8", rv_codec_r, rv_fmt_rd_rs1 },
> + { "mop.r.9", rv_codec_r, rv_fmt_rd_rs1 },
> + { "mop.r.10", rv_codec_r, rv_fmt_rd_rs1 },
> + { "mop.r.11", rv_codec_r, rv_fmt_rd_rs1 },
> + { "mop.r.12", rv_codec_r, rv_fmt_rd_rs1 },
> + { "mop.r.13", rv_codec_r, rv_fmt_rd_rs1 },
> + { "mop.r.14", rv_codec_r, rv_fmt_rd_rs1 },
> + { "mop.r.15", rv_codec_r, rv_fmt_rd_rs1 },
> + { "mop.r.16", rv_codec_r, rv_fmt_rd_rs1 },
> + { "mop.r.17", rv_codec_r, rv_fmt_rd_rs1 },
> + { "mop.r.18", rv_codec_r, rv_fmt_rd_rs1 },
> + { "mop.r.19", rv_codec_r, rv_fmt_rd_rs1 },
> + { "mop.r.20", rv_codec_r, rv_fmt_rd_rs1 },
> + { "mop.r.21", rv_codec_r, rv_fmt_rd_rs1 },
> + { "mop.r.22", rv_codec_r, rv_fmt_rd_rs1 },
> + { "mop.r.23", rv_codec_r, rv_fmt_rd_rs1 },
> + { "mop.r.24", rv_codec_r, rv_fmt_rd_rs1 },
> + { "mop.r.25", rv_codec_r, rv_fmt_rd_rs1 },
> + { "mop.r.26", rv_codec_r, rv_fmt_rd_rs1 },
> + { "mop.r.27", rv_codec_r, rv_fmt_rd_rs1 },
> + { "mop.r.28", rv_codec_r, rv_fmt_rd_rs1 },
> + { "mop.r.29", rv_codec_r, rv_fmt_rd_rs1 },
> + { "mop.r.30", rv_codec_r, rv_fmt_rd_rs1 },
> + { "mop.r.31", rv_codec_r, rv_fmt_rd_rs1 },
> + { "mop.rr.0", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> + { "mop.rr.1", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> + { "mop.rr.2", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> + { "mop.rr.3", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> + { "mop.rr.4", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> + { "mop.rr.5", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> + { "mop.rr.6", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> + { "mop.rr.7", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> + { "c.mop.1", rv_codec_ci_none, rv_fmt_none },
> + { "c.mop.3", rv_codec_ci_none, rv_fmt_none },
> + { "c.mop.5", rv_codec_ci_none, rv_fmt_none },
> + { "c.mop.7", rv_codec_ci_none, rv_fmt_none },
> + { "c.mop.9", rv_codec_ci_none, rv_fmt_none },
> + { "c.mop.11", rv_codec_ci_none, rv_fmt_none },
> + { "c.mop.13", rv_codec_ci_none, rv_fmt_none },
> + { "c.mop.15", rv_codec_ci_none, rv_fmt_none },
> + { "amoswap.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
> + { "amoadd.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
> + { "amoxor.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
> + { "amoor.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
> + { "amoand.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
> + { "amomin.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
> + { "amomax.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
> + { "amominu.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
> + { "amomaxu.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
> + { "amoswap.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
> + { "amoadd.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
> + { "amoxor.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
> + { "amoor.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
> + { "amoand.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
> + { "amomin.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
> + { "amomax.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
> + { "amominu.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
> + { "amomaxu.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
> + { "amocas.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
> + { "amocas.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
> + { "wrs.sto", rv_codec_none, rv_fmt_none },
> + { "wrs.nto", rv_codec_none, rv_fmt_none },
> + { "lpad", rv_codec_lp, rv_fmt_imm },
> + { "sspush", rv_codec_r, rv_fmt_rs2 },
> + { "sspopchk", rv_codec_r, rv_fmt_rs1 },
> + { "ssrdp", rv_codec_r, rv_fmt_rd },
> + { "ssamoswap.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
> + { "ssamoswap.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
> { "c.sspush", rv_codec_cmop_ss, rv_fmt_rs2, NULL, rv_op_sspush,
> rv_op_sspush, 0 },
> { "c.sspopchk", rv_codec_cmop_ss, rv_fmt_rs1, NULL,
> rv_op_sspopchk,
> rv_op_sspopchk, 0 },
> - { "cbo.inval", rv_codec_r, rv_fmt_rs1, NULL, 0, 0, 0 },
> - { "cbo.clean", rv_codec_r, rv_fmt_rs1, NULL, 0, 0, 0 },
> - { "cbo.flush", rv_codec_r, rv_fmt_rs1, NULL, 0, 0, 0 },
> - { "cbo.zero", rv_codec_r, rv_fmt_rs1, NULL, 0, 0, 0 },
> - { "mnret", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
> + { "cbo.inval", rv_codec_r, rv_fmt_rs1 },
> + { "cbo.clean", rv_codec_r, rv_fmt_rs1 },
> + { "cbo.flush", rv_codec_r, rv_fmt_rs1 },
> + { "cbo.zero", rv_codec_r, rv_fmt_rs1 },
> + { "mnret", rv_codec_none, rv_fmt_none },
> };
>
> /* CSR names */
^ permalink raw reply [flat|nested] 119+ messages in thread
* Re: [PATCH 16/56] disas/riscv: Drop useless const in structures
2026-08-09 22:35 ` [PATCH 16/56] disas/riscv: Drop useless const in structures Richard Henderson
2026-08-10 2:55 ` Philippe Mathieu-Daudé
@ 2026-08-11 20:10 ` Alistair
1 sibling, 0 replies; 119+ messages in thread
From: Alistair @ 2026-08-11 20:10 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: qemu-riscv
On Sun, 2026-08-09 at 15:35 -0700, Richard Henderson wrote:
> Individual fields should not be const, only full structures.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> disas/riscv.h | 16 ++++++++--------
> 1 file changed, 8 insertions(+), 8 deletions(-)
>
> diff --git a/disas/riscv.h b/disas/riscv.h
> index eabe193b4f..3325b7b4ef 100644
> --- a/disas/riscv.h
> +++ b/disas/riscv.h
> @@ -174,19 +174,19 @@ typedef enum {
> /* structures */
>
> typedef struct {
> - const int op;
> + int op;
> const rvc_constraint *constraints;
> } rv_comp_data;
>
> typedef struct {
> - const char * const name;
> - const rv_codec codec;
> - const char * const format;
> + const char *name;
> + rv_codec codec;
> + const char *format;
> const rv_comp_data *pseudo;
> - const short decomp_rv32;
> - const short decomp_rv64;
> - const short decomp_rv128;
> - const short decomp_data;
> + short decomp_rv32;
> + short decomp_rv64;
> + short decomp_rv128;
> + short decomp_data;
> } rv_opcode_data;
>
> typedef struct {
^ permalink raw reply [flat|nested] 119+ messages in thread
* Re: [PATCH 17/56] disas/riscv: Drop codec from rv_decode
2026-08-09 22:35 ` [PATCH 17/56] disas/riscv: Drop codec from rv_decode Richard Henderson
@ 2026-08-11 20:11 ` Alistair
0 siblings, 0 replies; 119+ messages in thread
From: Alistair @ 2026-08-11 20:11 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: qemu-riscv
On Sun, 2026-08-09 at 15:35 -0700, Richard Henderson wrote:
> This is mostly write-only, only used in one place;
> other updates are ignored.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> disas/riscv.h | 1 -
> disas/riscv.c | 7 +++----
> 2 files changed, 3 insertions(+), 5 deletions(-)
>
> diff --git a/disas/riscv.h b/disas/riscv.h
> index 3325b7b4ef..31bb0db86c 100644
> --- a/disas/riscv.h
> +++ b/disas/riscv.h
> @@ -197,7 +197,6 @@ typedef struct {
> int32_t imm;
> int32_t imm1;
> uint16_t op;
> - uint8_t codec;
> uint8_t rd;
> uint8_t rs1;
> uint8_t rs2;
> diff --git a/disas/riscv.c b/disas/riscv.c
> index ec40abb618..9813d75feb 100644
> --- a/disas/riscv.c
> +++ b/disas/riscv.c
> @@ -4603,8 +4603,9 @@ static void decode_inst_operands(rv_decode
> *dec, rv_isa isa,
> {
> rv_inst inst = dec->inst;
>
> - dec->codec = op->codec;
> - switch (dec->codec) {
> + switch (op->codec) {
> + case rv_codec_illegal:
> + break;
> case rv_codec_none:
> dec->rd = dec->rs1 = dec->rs2 = rv_ireg_zero;
> dec->imm = 0;
> @@ -5369,7 +5370,6 @@ static const rv_opcode_data
> *decode_inst_lift_pseudo(rv_decode *dec,
> if (check_constraints(dec, comp_data->constraints)) {
> dec->op = comp_data->op;
> op = &dec->opcode_data[dec->op];
> - dec->codec = op->codec;
> break;
> }
> comp_data++;
> @@ -5407,7 +5407,6 @@ static const rv_opcode_data
> *decode_inst_decompress(rv_decode *dec, rv_isa isa,
> dec->op = decomp_op;
> }
> op = &dec->opcode_data[decomp_op];
> - dec->codec = op->codec;
> }
> return op;
> }
^ permalink raw reply [flat|nested] 119+ messages in thread
* Re: [PATCH 18/56] disas/riscv: Handle c.addi4spn imm != 0 during decode
2026-08-09 22:35 ` [PATCH 18/56] disas/riscv: Handle c.addi4spn imm != 0 during decode Richard Henderson
@ 2026-08-11 20:12 ` Alistair
0 siblings, 0 replies; 119+ messages in thread
From: Alistair @ 2026-08-11 20:12 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: qemu-riscv
On Sun, 2026-08-09 at 15:35 -0700, Richard Henderson wrote:
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> disas/riscv.c | 8 ++++++--
> 1 file changed, 6 insertions(+), 2 deletions(-)
>
> diff --git a/disas/riscv.c b/disas/riscv.c
> index 9813d75feb..8a957e6a1e 100644
> --- a/disas/riscv.c
> +++ b/disas/riscv.c
> @@ -1885,7 +1885,7 @@ static const rv_opcode_data rvi_opcode_data[] =
> {
> { "fmv.x.q", rv_codec_r, rv_fmt_rd_frs1 },
> { "fmv.q.x", rv_codec_r, rv_fmt_frd_rs1 },
> { "c.addi4spn", rv_codec_ciw_4spn, rv_fmt_rd_rs1_imm, NULL,
> rv_op_addi,
> - rv_op_addi, rv_op_addi, rvcd_imm_nz },
> + rv_op_addi, rv_op_addi },
> { "c.fld", rv_codec_cl_ld, rv_fmt_frd_offset_rs1, NULL,
> rv_op_fld,
> rv_op_fld, 0 },
> { "c.lw", rv_codec_cl_lw, rv_fmt_rd_offset_rs1, NULL, rv_op_lw,
> rv_op_lw,
> @@ -2952,7 +2952,11 @@ static void decode_inst_opcode(rv_decode *dec,
> rv_isa isa)
> switch ((inst >> 0) & 0b11) {
> case 0:
> switch ((inst >> 13) & 0b111) {
> - case 0: op = rv_op_c_addi4spn; break;
> + case 0:
> + if ((inst >> 5) & 0xff) {
> + op = rv_op_c_addi4spn;
> + }
> + break;
> case 1:
> if (isa == rv128) {
> op = rv_op_c_lq;
^ permalink raw reply [flat|nested] 119+ messages in thread
* Re: [PATCH 19/56] disas/riscv: Simplify c.addi
2026-08-09 22:35 ` [PATCH 19/56] disas/riscv: Simplify c.addi Richard Henderson
@ 2026-08-11 20:14 ` Alistair
0 siblings, 0 replies; 119+ messages in thread
From: Alistair @ 2026-08-11 20:14 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: qemu-riscv
On Sun, 2026-08-09 at 15:35 -0700, Richard Henderson wrote:
> While c.addi with imm == 0 and rd == 0 is c.nop,
> other c.addi with imm == 0 and rd != 0 are not illegal,
> but are reserved as HINTs. Go ahead and disassemble as
> c.addi rather than falling back to invalid.
>
> Further, there's no reason to differentiate c.nop, since we have
> c.addi -> addi -> nop
> vs
> c.nop -> addi -> nop
> via decompress and pseudo translation steps.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> disas/riscv.c | 11 +++--------
> 1 file changed, 3 insertions(+), 8 deletions(-)
>
> diff --git a/disas/riscv.c b/disas/riscv.c
> index 8a957e6a1e..7978ffb378 100644
> --- a/disas/riscv.c
> +++ b/disas/riscv.c
> @@ -263,7 +263,6 @@ typedef enum {
> rv_op_c_fsd = 231,
> rv_op_c_sw = 232,
> rv_op_c_fsw = 233,
> - rv_op_c_nop = 234,
> rv_op_c_addi = 235,
> rv_op_c_jal = 236,
> rv_op_c_li = 237,
> @@ -1896,10 +1895,9 @@ static const rv_opcode_data rvi_opcode_data[]
> = {
> { "c.sw", rv_codec_cs_sw, rv_fmt_rs2_offset_rs1, NULL, rv_op_sw,
> rv_op_sw,
> rv_op_sw },
> { "c.fsw", rv_codec_cs_sw, rv_fmt_frs2_offset_rs1, NULL,
> rv_op_fsw, 0, 0 },
> - { "c.nop", rv_codec_ci_none, rv_fmt_none, NULL, rv_op_addi,
> rv_op_addi,
> - rv_op_addi },
> + { },
> { "c.addi", rv_codec_ci, rv_fmt_rd_rs1_imm, NULL, rv_op_addi,
> rv_op_addi,
> - rv_op_addi, rvcd_imm_nz },
> + rv_op_addi },
> { "c.jal", rv_codec_cj_jal, rv_fmt_rd_offset, NULL, rv_op_jal,
> 0, 0 },
> { "c.li", rv_codec_ci_li, rv_fmt_rd_rs1_imm, NULL, rv_op_addi,
> rv_op_addi,
> rv_op_addi },
> @@ -3010,10 +3008,7 @@ static void decode_inst_opcode(rv_decode *dec,
> rv_isa isa)
> case 1:
> switch ((inst >> 13) & 0b111) {
> case 0:
> - switch ((inst >> 2) & 0b11111111111) {
> - case 0: op = rv_op_c_nop; break;
> - default: op = rv_op_c_addi; break;
> - }
> + op = rv_op_c_addi; /* or unspecified HINT */
> break;
> case 1:
> if (isa == rv32) {
^ permalink raw reply [flat|nested] 119+ messages in thread
* Re: [PATCH 20/56] disas/riscv: Handle c.lui imm != 0 during decode
2026-08-09 22:35 ` [PATCH 20/56] disas/riscv: Handle c.lui imm != 0 during decode Richard Henderson
@ 2026-08-11 20:14 ` Alistair
0 siblings, 0 replies; 119+ messages in thread
From: Alistair @ 2026-08-11 20:14 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: qemu-riscv
On Sun, 2026-08-09 at 15:35 -0700, Richard Henderson wrote:
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> disas/riscv.c | 12 +++++++-----
> 1 file changed, 7 insertions(+), 5 deletions(-)
>
> diff --git a/disas/riscv.c b/disas/riscv.c
> index 7978ffb378..d6fbb3bca6 100644
> --- a/disas/riscv.c
> +++ b/disas/riscv.c
> @@ -1902,9 +1902,9 @@ static const rv_opcode_data rvi_opcode_data[] =
> {
> { "c.li", rv_codec_ci_li, rv_fmt_rd_rs1_imm, NULL, rv_op_addi,
> rv_op_addi,
> rv_op_addi },
> { "c.addi16sp", rv_codec_ci_16sp, rv_fmt_rd_rs1_imm, NULL,
> rv_op_addi,
> - rv_op_addi, rv_op_addi, rvcd_imm_nz },
> + rv_op_addi, rv_op_addi },
> { "c.lui", rv_codec_ci_lui, rv_fmt_rd_uimm, NULL, rv_op_lui,
> rv_op_lui,
> - rv_op_lui, rvcd_imm_nz },
> + rv_op_lui },
> { "c.srli", rv_codec_cb_sh6, rv_fmt_rd_rs1_imm, NULL,
> rv_op_srli,
> rv_op_srli, rv_op_srli, rvcd_imm_nz },
> { "c.srai", rv_codec_cb_sh6, rv_fmt_rd_rs1_imm, NULL,
> rv_op_srai,
> @@ -3032,9 +3032,11 @@ static void decode_inst_opcode(rv_decode *dec,
> rv_isa isa)
> break;
> }
> }
> - switch ((inst >> 7) & 0b11111) {
> - case 2: op = rv_op_c_addi16sp; break;
> - default: op = rv_op_c_lui; break;
> + if (inst & ((1 << 12) | (0x1f << 2))) {
> + switch ((inst >> 7) & 0b11111) {
> + case 2: op = rv_op_c_addi16sp; break;
> + default: op = rv_op_c_lui; break;
> + }
> }
> break;
> case 4:
^ permalink raw reply [flat|nested] 119+ messages in thread
* Re: [PATCH 21/56] disas/riscv: Handle c.{srli,srai} imm during decode
2026-08-09 22:35 ` [PATCH 21/56] disas/riscv: Handle c.{srli,srai} imm " Richard Henderson
@ 2026-08-11 20:16 ` Alistair
0 siblings, 0 replies; 119+ messages in thread
From: Alistair @ 2026-08-11 20:16 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: qemu-riscv
On Sun, 2026-08-09 at 15:35 -0700, Richard Henderson wrote:
> Zero shift immediate to c.srli and c.srai are not illegal,
> but are reserved as HINTs. Go ahead and disassemble as
> shifts rather than falling back to invalid.
>
> On the other hand, shift immediate >= 32 with RV32 is
> reserved for custom extensions, and we need to reject those
> early so that the extension disassemblers get a look in.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> disas/riscv.c | 14 ++++++++++----
> 1 file changed, 10 insertions(+), 4 deletions(-)
>
> diff --git a/disas/riscv.c b/disas/riscv.c
> index d6fbb3bca6..a8fbefb9bd 100644
> --- a/disas/riscv.c
> +++ b/disas/riscv.c
> @@ -1906,9 +1906,9 @@ static const rv_opcode_data rvi_opcode_data[] =
> {
> { "c.lui", rv_codec_ci_lui, rv_fmt_rd_uimm, NULL, rv_op_lui,
> rv_op_lui,
> rv_op_lui },
> { "c.srli", rv_codec_cb_sh6, rv_fmt_rd_rs1_imm, NULL,
> rv_op_srli,
> - rv_op_srli, rv_op_srli, rvcd_imm_nz },
> + rv_op_srli, rv_op_srli },
> { "c.srai", rv_codec_cb_sh6, rv_fmt_rd_rs1_imm, NULL,
> rv_op_srai,
> - rv_op_srai, rv_op_srai, rvcd_imm_nz },
> + rv_op_srai, rv_op_srai },
> { "c.andi", rv_codec_cb_imm, rv_fmt_rd_rs1_imm, NULL,
> rv_op_andi,
> rv_op_andi, rv_op_andi },
> { "c.sub", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_sub,
> rv_op_sub,
> @@ -3042,10 +3042,16 @@ static void decode_inst_opcode(rv_decode
> *dec, rv_isa isa)
> case 4:
> switch ((inst >> 10) & 0b11) {
> case 0:
> - op = rv_op_c_srli;
> + /* For rv32, shamt[5]=1 is designated for custom
> extensions. */
> + if (isa != rv32 || (inst & 0x1000) == 0) {
> + op = rv_op_c_srli; /* or unspecified HINT */
> + }
> break;
> case 1:
> - op = rv_op_c_srai;
> + /* For rv32, shamt[5]=1 is designated for custom
> extensions. */
> + if (isa != rv32 || (inst & 0x1000) == 0) {
> + op = rv_op_c_srai; /* or unspecified HINT */
> + }
> break;
> case 2: op = rv_op_c_andi; break;
> case 3:
^ permalink raw reply [flat|nested] 119+ messages in thread
* Re: [PATCH 22/56] disas/riscv: Handle c.slli imm != 0 during decode
2026-08-09 22:35 ` [PATCH 22/56] disas/riscv: Handle c.slli imm != 0 " Richard Henderson
@ 2026-08-11 20:16 ` Alistair
0 siblings, 0 replies; 119+ messages in thread
From: Alistair @ 2026-08-11 20:16 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: qemu-riscv
On Sun, 2026-08-09 at 15:35 -0700, Richard Henderson wrote:
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> disas/riscv.c | 6 ++++--
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/disas/riscv.c b/disas/riscv.c
> index a8fbefb9bd..77347b557d 100644
> --- a/disas/riscv.c
> +++ b/disas/riscv.c
> @@ -1930,7 +1930,7 @@ static const rv_opcode_data rvi_opcode_data[] =
> {
> { "c.bnez", rv_codec_cb, rv_fmt_rs1_rs2_offset, NULL, rv_op_bne,
> rv_op_bne,
> rv_op_bne },
> { "c.slli", rv_codec_ci_sh6, rv_fmt_rd_rs1_imm, NULL,
> rv_op_slli,
> - rv_op_slli, rv_op_slli, rvcd_imm_nz },
> + rv_op_slli, rv_op_slli },
> { "c.fldsp", rv_codec_ci_ldsp, rv_fmt_frd_offset_rs1, NULL,
> rv_op_fld,
> rv_op_fld, rv_op_fld },
> { "c.lwsp", rv_codec_ci_lwsp, rv_fmt_rd_offset_rs1, NULL,
> rv_op_lw,
> @@ -3085,7 +3085,9 @@ static void decode_inst_opcode(rv_decode *dec,
> rv_isa isa)
> case 2:
> switch ((inst >> 13) & 0b111) {
> case 0:
> - op = rv_op_c_slli;
> + if (isa != rv32 || (inst & 0x1000) == 0) {
> + op = rv_op_c_slli; /* or unspecified HINT */
> + }
> break;
> case 1:
> if (isa == rv128) {
^ permalink raw reply [flat|nested] 119+ messages in thread
* Re: [PATCH 23/56] disas/riscv: Do not recognize c.{addw,subw} with rv32
2026-08-09 22:35 ` [PATCH 23/56] disas/riscv: Do not recognize c.{addw,subw} with rv32 Richard Henderson
@ 2026-08-11 20:17 ` Alistair
0 siblings, 0 replies; 119+ messages in thread
From: Alistair @ 2026-08-11 20:17 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: qemu-riscv
On Sun, 2026-08-09 at 15:35 -0700, Richard Henderson wrote:
> These code points are reserved with RV32.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> disas/riscv.c | 12 ++++++++++--
> 1 file changed, 10 insertions(+), 2 deletions(-)
>
> diff --git a/disas/riscv.c b/disas/riscv.c
> index 77347b557d..ddc2f73eae 100644
> --- a/disas/riscv.c
> +++ b/disas/riscv.c
> @@ -3060,8 +3060,16 @@ static void decode_inst_opcode(rv_decode *dec,
> rv_isa isa)
> case 1: op = rv_op_c_xor; break;
> case 2: op = rv_op_c_or; break;
> case 3: op = rv_op_c_and; break;
> - case 4: op = rv_op_c_subw; break;
> - case 5: op = rv_op_c_addw; break;
> + case 4:
> + if (isa != rv32) {
> + op = rv_op_c_subw;
> + }
> + break;
> + case 5:
> + if (isa != rv32) {
> + op = rv_op_c_addw;
> + }
> + break;
> case 6: op = rv_op_c_mul; break;
> case 7:
> switch ((inst >> 2) & 0b111) {
^ permalink raw reply [flat|nested] 119+ messages in thread
* Re: [PATCH 24/56] disas/riscv: Remove rvcd_imm_nz
2026-08-09 22:35 ` [PATCH 24/56] disas/riscv: Remove rvcd_imm_nz Richard Henderson
@ 2026-08-11 20:17 ` Alistair
0 siblings, 0 replies; 119+ messages in thread
From: Alistair @ 2026-08-11 20:17 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: qemu-riscv
On Sun, 2026-08-09 at 15:35 -0700, Richard Henderson wrote:
> Remove rvcd_imm_nz and rv_opcode_data.decomp_data as unused.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> disas/riscv.h | 5 -----
> disas/riscv.c | 7 +------
> 2 files changed, 1 insertion(+), 11 deletions(-)
>
> diff --git a/disas/riscv.h b/disas/riscv.h
> index 31bb0db86c..3909d73dd0 100644
> --- a/disas/riscv.h
> +++ b/disas/riscv.h
> @@ -186,7 +186,6 @@ typedef struct {
> short decomp_rv32;
> short decomp_rv64;
> short decomp_rv128;
> - short decomp_data;
> } rv_opcode_data;
>
> typedef struct {
> @@ -217,10 +216,6 @@ enum {
> rv_op_illegal = 0
> };
>
> -enum {
> - rvcd_imm_nz = 0x1
> -};
> -
> /* instruction formats */
>
> #define rv_fmt_none "O\t"
> diff --git a/disas/riscv.c b/disas/riscv.c
> index ddc2f73eae..95957506bd 100644
> --- a/disas/riscv.c
> +++ b/disas/riscv.c
> @@ -5417,12 +5417,7 @@ static const rv_opcode_data
> *decode_inst_decompress(rv_decode *dec, rv_isa isa,
> }
>
> if (decomp_op != rv_op_illegal) {
> - if ((op->decomp_data & rvcd_imm_nz) && dec->imm == 0) {
> - dec->opcode_data = rvi_opcode_data;
> - dec->op = rv_op_illegal;
> - } else {
> - dec->op = decomp_op;
> - }
> + dec->op = decomp_op;
> op = &dec->opcode_data[decomp_op];
> }
> return op;
^ permalink raw reply [flat|nested] 119+ messages in thread
* Re: [PATCH 25/56] disas/riscv: Unify decomp_rv{32,64,128}
2026-08-09 22:35 ` [PATCH 25/56] disas/riscv: Unify decomp_rv{32,64,128} Richard Henderson
@ 2026-08-11 20:18 ` Alistair
0 siblings, 0 replies; 119+ messages in thread
From: Alistair @ 2026-08-11 20:18 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: qemu-riscv
On Sun, 2026-08-09 at 15:35 -0700, Richard Henderson wrote:
> We now distinguish compressed opcodes by isa during decode.
> Therefore we don't need 3 copies of decomp_*.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> disas/riscv.h | 4 +-
> disas/riscv.c | 155 ++++++++++++++++--------------------------------
> --
> 2 files changed, 51 insertions(+), 108 deletions(-)
>
> diff --git a/disas/riscv.h b/disas/riscv.h
> index 3909d73dd0..900363c603 100644
> --- a/disas/riscv.h
> +++ b/disas/riscv.h
> @@ -183,9 +183,7 @@ typedef struct {
> rv_codec codec;
> const char *format;
> const rv_comp_data *pseudo;
> - short decomp_rv32;
> - short decomp_rv64;
> - short decomp_rv128;
> + rv_opcode decomp;
> } rv_opcode_data;
>
> typedef struct {
> diff --git a/disas/riscv.c b/disas/riscv.c
> index 95957506bd..2e891f509e 100644
> --- a/disas/riscv.c
> +++ b/disas/riscv.c
> @@ -1883,91 +1883,52 @@ static const rv_opcode_data rvi_opcode_data[]
> = {
> { "fcvt.q.lu", rv_codec_r_m, rv_fmt_rm_frd_rs1 },
> { "fmv.x.q", rv_codec_r, rv_fmt_rd_frs1 },
> { "fmv.q.x", rv_codec_r, rv_fmt_frd_rs1 },
> - { "c.addi4spn", rv_codec_ciw_4spn, rv_fmt_rd_rs1_imm, NULL,
> rv_op_addi,
> - rv_op_addi, rv_op_addi },
> - { "c.fld", rv_codec_cl_ld, rv_fmt_frd_offset_rs1, NULL,
> rv_op_fld,
> - rv_op_fld, 0 },
> - { "c.lw", rv_codec_cl_lw, rv_fmt_rd_offset_rs1, NULL, rv_op_lw,
> rv_op_lw,
> - rv_op_lw },
> - { "c.flw", rv_codec_cl_lw, rv_fmt_frd_offset_rs1, NULL,
> rv_op_flw, 0, 0 },
> - { "c.fsd", rv_codec_cs_sd, rv_fmt_frs2_offset_rs1, NULL,
> rv_op_fsd,
> - rv_op_fsd, 0 },
> - { "c.sw", rv_codec_cs_sw, rv_fmt_rs2_offset_rs1, NULL, rv_op_sw,
> rv_op_sw,
> - rv_op_sw },
> - { "c.fsw", rv_codec_cs_sw, rv_fmt_frs2_offset_rs1, NULL,
> rv_op_fsw, 0, 0 },
> + { "c.addi4spn", rv_codec_ciw_4spn, rv_fmt_rd_rs1_imm, NULL,
> rv_op_addi },
> + { "c.fld", rv_codec_cl_ld, rv_fmt_frd_offset_rs1, NULL,
> rv_op_fld },
> + { "c.lw", rv_codec_cl_lw, rv_fmt_rd_offset_rs1, NULL, rv_op_lw
> },
> + { "c.flw", rv_codec_cl_lw, rv_fmt_frd_offset_rs1, NULL,
> rv_op_flw },
> + { "c.fsd", rv_codec_cs_sd, rv_fmt_frs2_offset_rs1, NULL,
> rv_op_fsd },
> + { "c.sw", rv_codec_cs_sw, rv_fmt_rs2_offset_rs1, NULL, rv_op_sw
> },
> + { "c.fsw", rv_codec_cs_sw, rv_fmt_frs2_offset_rs1, NULL,
> rv_op_fsw },
> { },
> - { "c.addi", rv_codec_ci, rv_fmt_rd_rs1_imm, NULL, rv_op_addi,
> rv_op_addi,
> - rv_op_addi },
> - { "c.jal", rv_codec_cj_jal, rv_fmt_rd_offset, NULL, rv_op_jal,
> 0, 0 },
> - { "c.li", rv_codec_ci_li, rv_fmt_rd_rs1_imm, NULL, rv_op_addi,
> rv_op_addi,
> - rv_op_addi },
> - { "c.addi16sp", rv_codec_ci_16sp, rv_fmt_rd_rs1_imm, NULL,
> rv_op_addi,
> - rv_op_addi, rv_op_addi },
> - { "c.lui", rv_codec_ci_lui, rv_fmt_rd_uimm, NULL, rv_op_lui,
> rv_op_lui,
> - rv_op_lui },
> - { "c.srli", rv_codec_cb_sh6, rv_fmt_rd_rs1_imm, NULL,
> rv_op_srli,
> - rv_op_srli, rv_op_srli },
> - { "c.srai", rv_codec_cb_sh6, rv_fmt_rd_rs1_imm, NULL,
> rv_op_srai,
> - rv_op_srai, rv_op_srai },
> - { "c.andi", rv_codec_cb_imm, rv_fmt_rd_rs1_imm, NULL,
> rv_op_andi,
> - rv_op_andi, rv_op_andi },
> - { "c.sub", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_sub,
> rv_op_sub,
> - rv_op_sub },
> - { "c.xor", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_xor,
> rv_op_xor,
> - rv_op_xor },
> - { "c.or", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_or,
> rv_op_or,
> - rv_op_or },
> - { "c.and", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_and,
> rv_op_and,
> - rv_op_and },
> - { "c.subw", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_subw,
> rv_op_subw,
> - rv_op_subw },
> - { "c.addw", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_addw,
> rv_op_addw,
> - rv_op_addw },
> - { "c.j", rv_codec_cj, rv_fmt_rd_offset, NULL, rv_op_jal,
> rv_op_jal,
> - rv_op_jal },
> - { "c.beqz", rv_codec_cb, rv_fmt_rs1_rs2_offset, NULL, rv_op_beq,
> rv_op_beq,
> - rv_op_beq },
> - { "c.bnez", rv_codec_cb, rv_fmt_rs1_rs2_offset, NULL, rv_op_bne,
> rv_op_bne,
> - rv_op_bne },
> - { "c.slli", rv_codec_ci_sh6, rv_fmt_rd_rs1_imm, NULL,
> rv_op_slli,
> - rv_op_slli, rv_op_slli },
> - { "c.fldsp", rv_codec_ci_ldsp, rv_fmt_frd_offset_rs1, NULL,
> rv_op_fld,
> - rv_op_fld, rv_op_fld },
> - { "c.lwsp", rv_codec_ci_lwsp, rv_fmt_rd_offset_rs1, NULL,
> rv_op_lw,
> - rv_op_lw, rv_op_lw },
> - { "c.flwsp", rv_codec_ci_lwsp, rv_fmt_frd_offset_rs1, NULL,
> rv_op_flw, 0,
> - 0 },
> - { "c.jr", rv_codec_cr_jr, rv_fmt_rd_rs1_offset, NULL,
> rv_op_jalr,
> - rv_op_jalr, rv_op_jalr },
> - { "c.mv", rv_codec_cr_mv, rv_fmt_rd_rs1_rs2, NULL, rv_op_addi,
> rv_op_addi,
> - rv_op_addi },
> - { "c.ebreak", rv_codec_ci_none, rv_fmt_none, NULL, rv_op_ebreak,
> - rv_op_ebreak, rv_op_ebreak },
> - { "c.jalr", rv_codec_cr_jalr, rv_fmt_rd_rs1_offset, NULL,
> rv_op_jalr,
> - rv_op_jalr, rv_op_jalr },
> - { "c.add", rv_codec_cr, rv_fmt_rd_rs1_rs2, NULL, rv_op_add,
> rv_op_add,
> - rv_op_add },
> - { "c.fsdsp", rv_codec_css_sdsp, rv_fmt_frs2_offset_rs1, NULL,
> rv_op_fsd,
> - rv_op_fsd, rv_op_fsd },
> - { "c.swsp", rv_codec_css_swsp, rv_fmt_rs2_offset_rs1, NULL,
> rv_op_sw,
> - rv_op_sw, rv_op_sw },
> - { "c.fswsp", rv_codec_css_swsp, rv_fmt_frs2_offset_rs1, NULL,
> rv_op_fsw, 0,
> - 0 },
> - { "c.ld", rv_codec_cl_ld, rv_fmt_rd_offset_rs1, NULL, 0,
> rv_op_ld,
> - rv_op_ld },
> - { "c.sd", rv_codec_cs_sd, rv_fmt_rs2_offset_rs1, NULL, 0,
> rv_op_sd,
> - rv_op_sd },
> - { "c.addiw", rv_codec_ci, rv_fmt_rd_rs1_imm, NULL, 0,
> rv_op_addiw,
> - rv_op_addiw },
> - { "c.ldsp", rv_codec_ci_ldsp, rv_fmt_rd_offset_rs1, NULL, 0,
> rv_op_ld,
> - rv_op_ld },
> - { "c.sdsp", rv_codec_css_sdsp, rv_fmt_rs2_offset_rs1, NULL, 0,
> rv_op_sd,
> - rv_op_sd },
> - { "c.lq", rv_codec_cl_lq, rv_fmt_rd_offset_rs1, NULL, 0, 0,
> rv_op_lq },
> - { "c.sq", rv_codec_cs_sq, rv_fmt_rs2_offset_rs1, NULL, 0, 0,
> rv_op_sq },
> - { "c.lqsp", rv_codec_ci_lqsp, rv_fmt_rd_offset_rs1, NULL, 0, 0,
> rv_op_lq },
> - { "c.sqsp", rv_codec_css_sqsp, rv_fmt_rs2_offset_rs1, NULL, 0,
> 0,
> - rv_op_sq },
> + { "c.addi", rv_codec_ci, rv_fmt_rd_rs1_imm, NULL, rv_op_addi },
> + { "c.jal", rv_codec_cj_jal, rv_fmt_rd_offset, NULL, rv_op_jal },
> + { "c.li", rv_codec_ci_li, rv_fmt_rd_rs1_imm, NULL, rv_op_addi },
> + { "c.addi16sp", rv_codec_ci_16sp, rv_fmt_rd_rs1_imm, NULL,
> rv_op_addi },
> + { "c.lui", rv_codec_ci_lui, rv_fmt_rd_uimm, NULL, rv_op_lui },
> + { "c.srli", rv_codec_cb_sh6, rv_fmt_rd_rs1_imm, NULL, rv_op_srli
> },
> + { "c.srai", rv_codec_cb_sh6, rv_fmt_rd_rs1_imm, NULL, rv_op_srai
> },
> + { "c.andi", rv_codec_cb_imm, rv_fmt_rd_rs1_imm, NULL, rv_op_andi
> },
> + { "c.sub", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_sub },
> + { "c.xor", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_xor },
> + { "c.or", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_or },
> + { "c.and", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_and },
> + { "c.subw", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_subw },
> + { "c.addw", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_addw },
> + { "c.j", rv_codec_cj, rv_fmt_rd_offset, NULL, rv_op_jal },
> + { "c.beqz", rv_codec_cb, rv_fmt_rs1_rs2_offset, NULL, rv_op_beq
> },
> + { "c.bnez", rv_codec_cb, rv_fmt_rs1_rs2_offset, NULL, rv_op_bne
> },
> + { "c.slli", rv_codec_ci_sh6, rv_fmt_rd_rs1_imm, NULL, rv_op_slli
> },
> + { "c.fldsp", rv_codec_ci_ldsp, rv_fmt_frd_offset_rs1, NULL,
> rv_op_fld },
> + { "c.lwsp", rv_codec_ci_lwsp, rv_fmt_rd_offset_rs1, NULL,
> rv_op_lw },
> + { "c.flwsp", rv_codec_ci_lwsp, rv_fmt_frd_offset_rs1, NULL,
> rv_op_flw },
> + { "c.jr", rv_codec_cr_jr, rv_fmt_rd_rs1_offset, NULL, rv_op_jalr
> },
> + { "c.mv", rv_codec_cr_mv, rv_fmt_rd_rs1_rs2, NULL, rv_op_addi },
> + { "c.ebreak", rv_codec_ci_none, rv_fmt_none, NULL, rv_op_ebreak
> },
> + { "c.jalr", rv_codec_cr_jalr, rv_fmt_rd_rs1_offset, NULL,
> rv_op_jalr },
> + { "c.add", rv_codec_cr, rv_fmt_rd_rs1_rs2, NULL, rv_op_add },
> + { "c.fsdsp", rv_codec_css_sdsp, rv_fmt_frs2_offset_rs1, NULL,
> rv_op_fsd },
> + { "c.swsp", rv_codec_css_swsp, rv_fmt_rs2_offset_rs1, NULL,
> rv_op_sw },
> + { "c.fswsp", rv_codec_css_swsp, rv_fmt_frs2_offset_rs1, NULL,
> rv_op_fsw },
> + { "c.ld", rv_codec_cl_ld, rv_fmt_rd_offset_rs1, NULL, rv_op_ld
> },
> + { "c.sd", rv_codec_cs_sd, rv_fmt_rs2_offset_rs1, NULL, rv_op_sd
> },
> + { "c.addiw", rv_codec_ci, rv_fmt_rd_rs1_imm, NULL, rv_op_addiw
> },
> + { "c.ldsp", rv_codec_ci_ldsp, rv_fmt_rd_offset_rs1, NULL,
> rv_op_ld },
> + { "c.sdsp", rv_codec_css_sdsp, rv_fmt_rs2_offset_rs1, NULL,
> rv_op_sd },
> + { "c.lq", rv_codec_cl_lq, rv_fmt_rd_offset_rs1, NULL, rv_op_lq
> },
> + { "c.sq", rv_codec_cs_sq, rv_fmt_rs2_offset_rs1, NULL, rv_op_sq
> },
> + { "c.lqsp", rv_codec_ci_lqsp, rv_fmt_rd_offset_rs1, NULL,
> rv_op_lq },
> + { "c.sqsp", rv_codec_css_sqsp, rv_fmt_rs2_offset_rs1, NULL,
> rv_op_sq },
> { "nop", rv_codec_i, rv_fmt_none },
> { "mv", rv_codec_i, rv_fmt_rd_rs1 },
> { "not", rv_codec_i, rv_fmt_rd_rs1 },
> @@ -2649,10 +2610,8 @@ static const rv_opcode_data rvi_opcode_data[]
> = {
> { "ssrdp", rv_codec_r, rv_fmt_rd },
> { "ssamoswap.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
> { "ssamoswap.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
> - { "c.sspush", rv_codec_cmop_ss, rv_fmt_rs2, NULL, rv_op_sspush,
> - rv_op_sspush, 0 },
> - { "c.sspopchk", rv_codec_cmop_ss, rv_fmt_rs1, NULL,
> rv_op_sspopchk,
> - rv_op_sspopchk, 0 },
> + { "c.sspush", rv_codec_cmop_ss, rv_fmt_rs2, NULL, rv_op_sspush
> },
> + { "c.sspopchk", rv_codec_cmop_ss, rv_fmt_rs1, NULL,
> rv_op_sspopchk },
> { "cbo.inval", rv_codec_r, rv_fmt_rs1 },
> { "cbo.clean", rv_codec_r, rv_fmt_rs1 },
> { "cbo.flush", rv_codec_r, rv_fmt_rs1 },
> @@ -5397,24 +5356,10 @@ static const rv_opcode_data
> *decode_inst_lift_pseudo(rv_decode *dec,
>
> /* decompress instruction */
>
> -static const rv_opcode_data *decode_inst_decompress(rv_decode *dec,
> rv_isa isa,
> +static const rv_opcode_data *decode_inst_decompress(rv_decode *dec,
> const
> rv_opcode_data *op)
> {
> - int decomp_op;
> -
> - switch (isa) {
> - case rv32:
> - decomp_op = op->decomp_rv32;
> - break;
> - case rv64:
> - decomp_op = op->decomp_rv64;
> - break;
> - case rv128:
> - decomp_op = op->decomp_rv128;
> - break;
> - default:
> - g_assert_not_reached();
> - }
> + int decomp_op = op->decomp;
>
> if (decomp_op != rv_op_illegal) {
> dec->op = decomp_op;
> @@ -5473,7 +5418,7 @@ static GString *disasm_inst(rv_isa isa,
> uint64_t pc, rv_inst inst,
>
> op = &dec.opcode_data[dec.op];
> decode_inst_operands(&dec, isa, op);
> - op = decode_inst_decompress(&dec, isa, op);
> + op = decode_inst_decompress(&dec, op);
> op = decode_inst_lift_pseudo(&dec, op);
> return format_inst(24, &dec, op);
> }
^ permalink raw reply [flat|nested] 119+ messages in thread
* Re: [PATCH 26/56] disas/riscv: Drop always true branch psudeos
2026-08-09 22:35 ` [PATCH 26/56] disas/riscv: Drop always true branch psudeos Richard Henderson
2026-08-10 2:58 ` Philippe Mathieu-Daudé
@ 2026-08-11 20:19 ` Alistair
1 sibling, 0 replies; 119+ messages in thread
From: Alistair @ 2026-08-11 20:19 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: qemu-riscv
On Sun, 2026-08-09 at 15:35 -0700, Richard Henderson wrote:
> The real insns are blt, bge, bltu, bgeu. Do not include
> psuedos that unconditionally swap operands. That's fine
> for an assembler but not a disassembler.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> disas/riscv.c | 32 ++++++--------------------------
> 1 file changed, 6 insertions(+), 26 deletions(-)
>
> diff --git a/disas/riscv.c b/disas/riscv.c
> index 2e891f509e..bde1cc6e62 100644
> --- a/disas/riscv.c
> +++ b/disas/riscv.c
> @@ -326,10 +326,6 @@ typedef enum {
> rv_op_bgez = 295,
> rv_op_bltz = 296,
> rv_op_bgtz = 297,
> - rv_op_ble = 298,
> - rv_op_bleu = 299,
> - rv_op_bgt = 300,
> - rv_op_bgtu = 301,
> rv_op_j = 302,
> rv_op_ret = 303,
> rv_op_jr = 304,
> @@ -1062,10 +1058,6 @@ static const rvc_constraint rvcc_blez[] = {
> rvc_rs1_eq_x0, rvc_end };
> static const rvc_constraint rvcc_bgez[] = { rvc_rs2_eq_x0, rvc_end
> };
> static const rvc_constraint rvcc_bltz[] = { rvc_rs2_eq_x0, rvc_end
> };
> static const rvc_constraint rvcc_bgtz[] = { rvc_rs1_eq_x0, rvc_end
> };
> -static const rvc_constraint rvcc_ble[] = { rvc_end };
> -static const rvc_constraint rvcc_bleu[] = { rvc_end };
> -static const rvc_constraint rvcc_bgt[] = { rvc_end };
> -static const rvc_constraint rvcc_bgtu[] = { rvc_end };
> static const rvc_constraint rvcc_j[] = { rvc_rd_eq_x0, rvc_end };
> static const rvc_constraint rvcc_ret[] = { rvc_rd_eq_x0,
> rvc_rs1_eq_ra,
> rvc_end };
> @@ -1123,24 +1115,12 @@ static const rv_comp_data rvcp_bne[] = {
> static const rv_comp_data rvcp_blt[] = {
> { rv_op_bltz, rvcc_bltz },
> { rv_op_bgtz, rvcc_bgtz },
> - { rv_op_bgt, rvcc_bgt },
> { rv_op_illegal, NULL }
> };
>
> static const rv_comp_data rvcp_bge[] = {
> { rv_op_blez, rvcc_blez },
> { rv_op_bgez, rvcc_bgez },
> - { rv_op_ble, rvcc_ble },
> - { rv_op_illegal, NULL }
> -};
> -
> -static const rv_comp_data rvcp_bltu[] = {
> - { rv_op_bgtu, rvcc_bgtu },
> - { rv_op_illegal, NULL }
> -};
> -
> -static const rv_comp_data rvcp_bgeu[] = {
> - { rv_op_bleu, rvcc_bleu },
> { rv_op_illegal, NULL }
> };
>
> @@ -1665,8 +1645,8 @@ static const rv_opcode_data rvi_opcode_data[] =
> {
> { "bne", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_bne },
> { "blt", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_blt },
> { "bge", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_bge },
> - { "bltu", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_bltu },
> - { "bgeu", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_bgeu },
> + { "bltu", rv_codec_sb, rv_fmt_rs1_rs2_offset },
> + { "bgeu", rv_codec_sb, rv_fmt_rs1_rs2_offset },
> { "lb", rv_codec_i, rv_fmt_rd_offset_rs1 },
> { "lh", rv_codec_i, rv_fmt_rd_offset_rs1 },
> { "lw", rv_codec_i, rv_fmt_rd_offset_rs1 },
> @@ -1954,10 +1934,10 @@ static const rv_opcode_data rvi_opcode_data[]
> = {
> { "bgez", rv_codec_sb, rv_fmt_rs1_offset },
> { "bltz", rv_codec_sb, rv_fmt_rs1_offset },
> { "bgtz", rv_codec_sb, rv_fmt_rs2_offset },
> - { "ble", rv_codec_sb, rv_fmt_rs2_rs1_offset },
> - { "bleu", rv_codec_sb, rv_fmt_rs2_rs1_offset },
> - { "bgt", rv_codec_sb, rv_fmt_rs2_rs1_offset },
> - { "bgtu", rv_codec_sb, rv_fmt_rs2_rs1_offset },
> + { },
> + { },
> + { },
> + { },
> { "j", rv_codec_uj, rv_fmt_offset },
> { "ret", rv_codec_i, rv_fmt_none },
> { "jr", rv_codec_i, rv_fmt_rs1 },
^ permalink raw reply [flat|nested] 119+ messages in thread
* Re: [PATCH 27/56] disas/riscv: Handle aliases of csrrw during decode
2026-08-09 22:35 ` [PATCH 27/56] disas/riscv: Handle aliases of csrrw during decode Richard Henderson
@ 2026-08-11 20:20 ` Alistair
0 siblings, 0 replies; 119+ messages in thread
From: Alistair @ 2026-08-11 20:20 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: qemu-riscv
On Sun, 2026-08-09 at 15:35 -0700, Richard Henderson wrote:
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> disas/riscv.c | 22 +++++++++-------------
> 1 file changed, 9 insertions(+), 13 deletions(-)
>
> diff --git a/disas/riscv.c b/disas/riscv.c
> index bde1cc6e62..e464b8b075 100644
> --- a/disas/riscv.c
> +++ b/disas/riscv.c
> @@ -1081,9 +1081,6 @@ static const rvc_constraint rvcc_frrm[] = {
> rvc_rs1_eq_x0, rvc_csr_eq_0x002,
> rvc_end };
> static const rvc_constraint rvcc_frflags[] = { rvc_rs1_eq_x0,
> rvc_csr_eq_0x001,
> rvc_end };
> -static const rvc_constraint rvcc_fscsr[] = { rvc_csr_eq_0x003,
> rvc_end };
> -static const rvc_constraint rvcc_fsrm[] = { rvc_csr_eq_0x002,
> rvc_end };
> -static const rvc_constraint rvcc_fsflags[] = { rvc_csr_eq_0x001,
> rvc_end };
> static const rvc_constraint rvcc_fsrmi[] = { rvc_csr_eq_0x002,
> rvc_end };
> static const rvc_constraint rvcc_fsflagsi[] = { rvc_csr_eq_0x001,
> rvc_end };
>
> @@ -1166,14 +1163,6 @@ static const rv_comp_data rvcp_subw[] = {
> { rv_op_illegal, NULL }
> };
>
> -static const rv_comp_data rvcp_csrrw[] = {
> - { rv_op_fscsr, rvcc_fscsr },
> - { rv_op_fsrm, rvcc_fsrm },
> - { rv_op_fsflags, rvcc_fsflags },
> - { rv_op_illegal, NULL }
> -};
> -
> -
> static const rv_comp_data rvcp_csrrs[] = {
> { rv_op_rdcycle, rvcc_rdcycle },
> { rv_op_rdtime, rvcc_rdtime },
> @@ -1761,7 +1750,7 @@ static const rv_opcode_data rvi_opcode_data[] =
> {
> { "sfence.vm", rv_codec_r, rv_fmt_rs1 },
> { "sfence.vma", rv_codec_r, rv_fmt_rs1_rs2 },
> { "wfi", rv_codec_none, rv_fmt_none },
> - { "csrrw", rv_codec_i_csr, rv_fmt_rd_csr_rs1, rvcp_csrrw },
> + { "csrrw", rv_codec_i_csr, rv_fmt_rd_csr_rs1 },
> { "csrrs", rv_codec_i_csr, rv_fmt_rd_csr_rs1, rvcp_csrrs },
> { "csrrc", rv_codec_i_csr, rv_fmt_rd_csr_rs1 },
> { "csrrwi", rv_codec_i_csr, rv_fmt_rd_csr_zimm, rvcp_csrrwi },
> @@ -4443,7 +4432,14 @@ static void decode_inst_opcode(rv_decode *dec,
> rv_isa isa)
> break;
> }
> break;
> - case 1: op = rv_op_csrrw; break;
> + case 1:
> + switch (operand_csr12(inst)) {
> + case 1: op = rv_op_fsflags; break;
> + case 2: op = rv_op_fsrm; break;
> + case 3: op = rv_op_fscsr; break;
> + default: op = rv_op_csrrw; break;
> + }
> + break;
> case 2: op = rv_op_csrrs; break;
> case 3: op = rv_op_csrrc; break;
> case 4:
^ permalink raw reply [flat|nested] 119+ messages in thread
* Re: [PATCH 28/56] disas/riscv: Handle aliases of csrrs during decode
2026-08-09 22:35 ` [PATCH 28/56] disas/riscv: Handle aliases of csrrs " Richard Henderson
@ 2026-08-11 20:21 ` Alistair
0 siblings, 0 replies; 119+ messages in thread
From: Alistair @ 2026-08-11 20:21 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: qemu-riscv
On Sun, 2026-08-09 at 15:35 -0700, Richard Henderson wrote:
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> disas/riscv.h | 7 -----
> disas/riscv.c | 85 +++++++++++--------------------------------------
> --
> 2 files changed, 17 insertions(+), 75 deletions(-)
>
> diff --git a/disas/riscv.h b/disas/riscv.h
> index 900363c603..d8c5acd969 100644
> --- a/disas/riscv.h
> +++ b/disas/riscv.h
> @@ -86,13 +86,6 @@ typedef enum {
> rvc_imm_eq_p1,
> rvc_csr_eq_0x001,
> rvc_csr_eq_0x002,
> - rvc_csr_eq_0x003,
> - rvc_csr_eq_0xc00,
> - rvc_csr_eq_0xc01,
> - rvc_csr_eq_0xc02,
> - rvc_csr_eq_0xc80,
> - rvc_csr_eq_0xc81,
> - rvc_csr_eq_0xc82,
> } rvc_constraint;
>
> typedef enum {
> diff --git a/disas/riscv.c b/disas/riscv.c
> index e464b8b075..9ec79baf4d 100644
> --- a/disas/riscv.c
> +++ b/disas/riscv.c
> @@ -1063,24 +1063,6 @@ static const rvc_constraint rvcc_ret[] = {
> rvc_rd_eq_x0, rvc_rs1_eq_ra,
> rvc_end };
> static const rvc_constraint rvcc_jr[] = { rvc_rd_eq_x0,
> rvc_imm_eq_zero,
> rvc_end };
> -static const rvc_constraint rvcc_rdcycle[] = { rvc_rs1_eq_x0,
> rvc_csr_eq_0xc00,
> - rvc_end };
> -static const rvc_constraint rvcc_rdtime[] = { rvc_rs1_eq_x0,
> rvc_csr_eq_0xc01,
> - rvc_end };
> -static const rvc_constraint rvcc_rdinstret[] = { rvc_rs1_eq_x0,
> - rvc_csr_eq_0xc02,
> rvc_end };
> -static const rvc_constraint rvcc_rdcycleh[] = { rvc_rs1_eq_x0,
> - rvc_csr_eq_0xc80,
> rvc_end };
> -static const rvc_constraint rvcc_rdtimeh[] = { rvc_rs1_eq_x0,
> rvc_csr_eq_0xc81,
> - rvc_end };
> -static const rvc_constraint rvcc_rdinstreth[] = { rvc_rs1_eq_x0,
> - rvc_csr_eq_0xc82,
> rvc_end };
> -static const rvc_constraint rvcc_frcsr[] = { rvc_rs1_eq_x0,
> rvc_csr_eq_0x003,
> - rvc_end };
> -static const rvc_constraint rvcc_frrm[] = { rvc_rs1_eq_x0,
> rvc_csr_eq_0x002,
> - rvc_end };
> -static const rvc_constraint rvcc_frflags[] = { rvc_rs1_eq_x0,
> rvc_csr_eq_0x001,
> - rvc_end };
> static const rvc_constraint rvcc_fsrmi[] = { rvc_csr_eq_0x002,
> rvc_end };
> static const rvc_constraint rvcc_fsflagsi[] = { rvc_csr_eq_0x001,
> rvc_end };
>
> @@ -1163,19 +1145,6 @@ static const rv_comp_data rvcp_subw[] = {
> { rv_op_illegal, NULL }
> };
>
> -static const rv_comp_data rvcp_csrrs[] = {
> - { rv_op_rdcycle, rvcc_rdcycle },
> - { rv_op_rdtime, rvcc_rdtime },
> - { rv_op_rdinstret, rvcc_rdinstret },
> - { rv_op_rdcycleh, rvcc_rdcycleh },
> - { rv_op_rdtimeh, rvcc_rdtimeh },
> - { rv_op_rdinstreth, rvcc_rdinstreth },
> - { rv_op_frcsr, rvcc_frcsr },
> - { rv_op_frrm, rvcc_frrm },
> - { rv_op_frflags, rvcc_frflags },
> - { rv_op_illegal, NULL }
> -};
> -
> static const rv_comp_data rvcp_csrrwi[] = {
> { rv_op_fsrmi, rvcc_fsrmi },
> { rv_op_fsflagsi, rvcc_fsflagsi },
> @@ -1751,7 +1720,7 @@ static const rv_opcode_data rvi_opcode_data[] =
> {
> { "sfence.vma", rv_codec_r, rv_fmt_rs1_rs2 },
> { "wfi", rv_codec_none, rv_fmt_none },
> { "csrrw", rv_codec_i_csr, rv_fmt_rd_csr_rs1 },
> - { "csrrs", rv_codec_i_csr, rv_fmt_rd_csr_rs1, rvcp_csrrs },
> + { "csrrs", rv_codec_i_csr, rv_fmt_rd_csr_rs1 },
> { "csrrc", rv_codec_i_csr, rv_fmt_rd_csr_rs1 },
> { "csrrwi", rv_codec_i_csr, rv_fmt_rd_csr_zimm, rvcp_csrrwi },
> { "csrrsi", rv_codec_i_csr, rv_fmt_rd_csr_zimm },
> @@ -4440,7 +4409,22 @@ static void decode_inst_opcode(rv_decode *dec,
> rv_isa isa)
> default: op = rv_op_csrrw; break;
> }
> break;
> - case 2: op = rv_op_csrrs; break;
> + case 2:
> + op = rv_op_csrrs;
> + if (operand_rs1(inst) == 0) {
> + switch (operand_csr12(inst)) {
> + case 0x001: op = rv_op_frflags; break;
> + case 0x002: op = rv_op_frrm; break;
> + case 0x003: op = rv_op_frcsr; break;
> + case 0xc00: op = rv_op_rdcycle; break;
> + case 0xc01: op = rv_op_rdtime; break;
> + case 0xc02: op = rv_op_rdinstret; break;
> + case 0xc80: op = rv_op_rdcycleh; break;
> + case 0xc81: op = rv_op_rdtimeh; break;
> + case 0xc82: op = rv_op_rdinstreth; break;
> + }
> + }
> + break;
> case 3: op = rv_op_csrrc; break;
> case 4:
> if (dec->cfg && dec->cfg->ext_zimop) {
> @@ -5017,41 +5001,6 @@ static bool check_constraints(rv_decode *dec,
> const rvc_constraint *c)
> return false;
> }
> break;
> - case rvc_csr_eq_0x003:
> - if (!(imm == 0x003)) {
> - return false;
> - }
> - break;
> - case rvc_csr_eq_0xc00:
> - if (!(imm == 0xc00)) {
> - return false;
> - }
> - break;
> - case rvc_csr_eq_0xc01:
> - if (!(imm == 0xc01)) {
> - return false;
> - }
> - break;
> - case rvc_csr_eq_0xc02:
> - if (!(imm == 0xc02)) {
> - return false;
> - }
> - break;
> - case rvc_csr_eq_0xc80:
> - if (!(imm == 0xc80)) {
> - return false;
> - }
> - break;
> - case rvc_csr_eq_0xc81:
> - if (!(imm == 0xc81)) {
> - return false;
> - }
> - break;
> - case rvc_csr_eq_0xc82:
> - if (!(imm == 0xc82)) {
> - return false;
> - }
> - break;
> default: break;
> }
> c++;
^ permalink raw reply [flat|nested] 119+ messages in thread
* Re: [PATCH 29/56] disas/riscv: Handle aliases of csrrwi during decode
2026-08-09 22:35 ` [PATCH 29/56] disas/riscv: Handle aliases of csrrwi " Richard Henderson
@ 2026-08-11 20:22 ` Alistair
0 siblings, 0 replies; 119+ messages in thread
From: Alistair @ 2026-08-11 20:22 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: qemu-riscv
On Sun, 2026-08-09 at 15:35 -0700, Richard Henderson wrote:
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> disas/riscv.h | 2 --
> disas/riscv.c | 28 ++++++++--------------------
> 2 files changed, 8 insertions(+), 22 deletions(-)
>
> diff --git a/disas/riscv.h b/disas/riscv.h
> index d8c5acd969..3bbcbf10fb 100644
> --- a/disas/riscv.h
> +++ b/disas/riscv.h
> @@ -84,8 +84,6 @@ typedef enum {
> rvc_imm_eq_zero,
> rvc_imm_eq_n1,
> rvc_imm_eq_p1,
> - rvc_csr_eq_0x001,
> - rvc_csr_eq_0x002,
> } rvc_constraint;
>
> typedef enum {
> diff --git a/disas/riscv.c b/disas/riscv.c
> index 9ec79baf4d..d3cbfb86ac 100644
> --- a/disas/riscv.c
> +++ b/disas/riscv.c
> @@ -1063,8 +1063,6 @@ static const rvc_constraint rvcc_ret[] = {
> rvc_rd_eq_x0, rvc_rs1_eq_ra,
> rvc_end };
> static const rvc_constraint rvcc_jr[] = { rvc_rd_eq_x0,
> rvc_imm_eq_zero,
> rvc_end };
> -static const rvc_constraint rvcc_fsrmi[] = { rvc_csr_eq_0x002,
> rvc_end };
> -static const rvc_constraint rvcc_fsflagsi[] = { rvc_csr_eq_0x001,
> rvc_end };
>
> /* pseudo-instruction metadata */
>
> @@ -1145,12 +1143,6 @@ static const rv_comp_data rvcp_subw[] = {
> { rv_op_illegal, NULL }
> };
>
> -static const rv_comp_data rvcp_csrrwi[] = {
> - { rv_op_fsrmi, rvcc_fsrmi },
> - { rv_op_fsflagsi, rvcc_fsflagsi },
> - { rv_op_illegal, NULL }
> -};
> -
> static const rv_comp_data rvcp_fsgnj_s[] = {
> { rv_op_fmv_s, rvcc_fmv_s },
> { rv_op_illegal, NULL }
> @@ -1722,7 +1714,7 @@ static const rv_opcode_data rvi_opcode_data[] =
> {
> { "csrrw", rv_codec_i_csr, rv_fmt_rd_csr_rs1 },
> { "csrrs", rv_codec_i_csr, rv_fmt_rd_csr_rs1 },
> { "csrrc", rv_codec_i_csr, rv_fmt_rd_csr_rs1 },
> - { "csrrwi", rv_codec_i_csr, rv_fmt_rd_csr_zimm, rvcp_csrrwi },
> + { "csrrwi", rv_codec_i_csr, rv_fmt_rd_csr_zimm },
> { "csrrsi", rv_codec_i_csr, rv_fmt_rd_csr_zimm },
> { "csrrci", rv_codec_i_csr, rv_fmt_rd_csr_zimm },
> { "flw", rv_codec_i, rv_fmt_frd_offset_rs1 },
> @@ -4469,7 +4461,13 @@ static void decode_inst_opcode(rv_decode *dec,
> rv_isa isa)
> }
> }
> break;
> - case 5: op = rv_op_csrrwi; break;
> + case 5:
> + switch (operand_csr12(inst)) {
> + case 1: op = rv_op_fsflagsi; break;
> + case 2: op = rv_op_fsrmi; break;
> + default: op = rv_op_csrrwi; break;
> + }
> + break;
> case 6: op = rv_op_csrrsi; break;
> case 7: op = rv_op_csrrci; break;
> }
> @@ -4991,16 +4989,6 @@ static bool check_constraints(rv_decode *dec,
> const rvc_constraint *c)
> return false;
> }
> break;
> - case rvc_csr_eq_0x001:
> - if (!(imm == 0x001)) {
> - return false;
> - }
> - break;
> - case rvc_csr_eq_0x002:
> - if (!(imm == 0x002)) {
> - return false;
> - }
> - break;
> default: break;
> }
> c++;
^ permalink raw reply [flat|nested] 119+ messages in thread
* Re: [PATCH 30/56] disas/riscv: Break pseudo loop for jal and jalr
2026-08-09 22:35 ` [PATCH 30/56] disas/riscv: Break pseudo loop for jal and jalr Richard Henderson
@ 2026-08-11 20:23 ` Alistair
0 siblings, 0 replies; 119+ messages in thread
From: Alistair @ 2026-08-11 20:23 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: qemu-riscv
On Sun, 2026-08-09 at 15:35 -0700, Richard Henderson wrote:
> These were clearly intending to simplify
> jal ra, foo
> to
> jal foo
> and similarly for jalr, but the pseudo expansion looped
> back to the original jal/jalr with the full format.
>
> Add new opcode expansions dropping the implied ra.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> disas/riscv.c | 16 +++++++++-------
> 1 file changed, 9 insertions(+), 7 deletions(-)
>
> diff --git a/disas/riscv.c b/disas/riscv.c
> index d3cbfb86ac..fe503b6cae 100644
> --- a/disas/riscv.c
> +++ b/disas/riscv.c
> @@ -326,6 +326,8 @@ typedef enum {
> rv_op_bgez = 295,
> rv_op_bltz = 296,
> rv_op_bgtz = 297,
> + rv_op_jal_ra = 298,
> + rv_op_jalr_ra = 299,
> rv_op_j = 302,
> rv_op_ret = 303,
> rv_op_jr = 304,
> @@ -1029,9 +1031,9 @@ static const char rv_fli_name_const[32][9] =
>
> /* pseudo-instruction constraints */
>
> -static const rvc_constraint rvcc_jal[] = { rvc_rd_eq_ra, rvc_end };
> -static const rvc_constraint rvcc_jalr[] = { rvc_rd_eq_ra,
> rvc_imm_eq_zero,
> - rvc_end };
> +static const rvc_constraint rvcc_jal_ra[] = { rvc_rd_eq_ra, rvc_end
> };
> +static const rvc_constraint rvcc_jalr_ra[] = { rvc_rd_eq_ra,
> rvc_imm_eq_zero,
> + rvc_end };
> static const rvc_constraint rvcc_nop[] = { rvc_rd_eq_x0,
> rvc_rs1_eq_x0,
> rvc_imm_eq_zero, rvc_end
> };
> static const rvc_constraint rvcc_mv[] = { rvc_imm_eq_zero, rvc_end
> };
> @@ -1068,14 +1070,14 @@ static const rvc_constraint rvcc_jr[] = {
> rvc_rd_eq_x0, rvc_imm_eq_zero,
>
> static const rv_comp_data rvcp_jal[] = {
> { rv_op_j, rvcc_j },
> - { rv_op_jal, rvcc_jal },
> + { rv_op_jal_ra, rvcc_jal_ra },
> { rv_op_illegal, NULL }
> };
>
> static const rv_comp_data rvcp_jalr[] = {
> { rv_op_ret, rvcc_ret },
> { rv_op_jr, rvcc_jr },
> - { rv_op_jalr, rvcc_jalr },
> + { rv_op_jalr_ra, rvcc_jalr_ra },
> { rv_op_illegal, NULL }
> };
>
> @@ -1884,8 +1886,8 @@ static const rv_opcode_data rvi_opcode_data[] =
> {
> { "bgez", rv_codec_sb, rv_fmt_rs1_offset },
> { "bltz", rv_codec_sb, rv_fmt_rs1_offset },
> { "bgtz", rv_codec_sb, rv_fmt_rs2_offset },
> - { },
> - { },
> + { "jal", rv_codec_none, rv_fmt_offset }, /* rv_op_jal_ra */
> + { "jalr", rv_codec_none, rv_fmt_rs1 }, /* rv_op_jalr_ra */
> { },
> { },
> { "j", rv_codec_uj, rv_fmt_offset },
^ permalink raw reply [flat|nested] 119+ messages in thread
* Re: [PATCH 31/56] disas/riscv: Allow decode_inst_lift_pseudo to loop
2026-08-09 22:35 ` [PATCH 31/56] disas/riscv: Allow decode_inst_lift_pseudo to loop Richard Henderson
@ 2026-08-11 20:23 ` Alistair
0 siblings, 0 replies; 119+ messages in thread
From: Alistair @ 2026-08-11 20:23 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: qemu-riscv
On Sun, 2026-08-09 at 15:35 -0700, Richard Henderson wrote:
> Allow pseudo expansion to proceed in multiple steps.
> Assert that we don't have simple loops.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> disas/riscv.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/disas/riscv.c b/disas/riscv.c
> index fe503b6cae..b8e5b124a5 100644
> --- a/disas/riscv.c
> +++ b/disas/riscv.c
> @@ -5259,9 +5259,9 @@ static const rv_opcode_data
> *decode_inst_lift_pseudo(rv_decode *dec,
> if (comp_data) {
> while (comp_data->constraints) {
> if (check_constraints(dec, comp_data->constraints)) {
> - dec->op = comp_data->op;
> - op = &dec->opcode_data[dec->op];
> - break;
> + const rv_opcode_data *new_op = &dec-
> >opcode_data[comp_data->op];
> + assert(new_op != op);
> + return decode_inst_lift_pseudo(dec, new_op);
> }
> comp_data++;
> }
^ permalink raw reply [flat|nested] 119+ messages in thread
* Re: [PATCH 32/56] disas/riscv: Handle decompression via decode_inst_lift_pseudo
2026-08-09 22:35 ` [PATCH 32/56] disas/riscv: Handle decompression via decode_inst_lift_pseudo Richard Henderson
@ 2026-08-11 20:24 ` Alistair
0 siblings, 0 replies; 119+ messages in thread
From: Alistair @ 2026-08-11 20:24 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: qemu-riscv
On Sun, 2026-08-09 at 15:35 -0700, Richard Henderson wrote:
> Introduce a DECOMP macro that expands an rv_comp_data
> that always succeeds.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> disas/riscv.h | 1 -
> disas/riscv.c | 113 +++++++++++++++++++++++-------------------------
> --
> 2 files changed, 51 insertions(+), 63 deletions(-)
>
> diff --git a/disas/riscv.h b/disas/riscv.h
> index 3bbcbf10fb..ea7141d3b5 100644
> --- a/disas/riscv.h
> +++ b/disas/riscv.h
> @@ -174,7 +174,6 @@ typedef struct {
> rv_codec codec;
> const char *format;
> const rv_comp_data *pseudo;
> - rv_opcode decomp;
> } rv_opcode_data;
>
> typedef struct {
> diff --git a/disas/riscv.c b/disas/riscv.c
> index b8e5b124a5..129e545c6e 100644
> --- a/disas/riscv.c
> +++ b/disas/riscv.c
> @@ -1065,6 +1065,7 @@ static const rvc_constraint rvcc_ret[] = {
> rvc_rd_eq_x0, rvc_rs1_eq_ra,
> rvc_end };
> static const rvc_constraint rvcc_jr[] = { rvc_rd_eq_x0,
> rvc_imm_eq_zero,
> rvc_end };
> +static const rvc_constraint rvcc_true[] = { rvc_end };
>
> /* pseudo-instruction metadata */
>
> @@ -1190,6 +1191,9 @@ static const rv_comp_data rvcp_fsgnjx_q[] = {
> { rv_op_illegal, NULL }
> };
>
> +/* Convert compressed insns into normal insns via pseudo expansion.
> */
> +#define DECOMP(X) (static const rv_comp_data[1]){ { X, rvcc_true } }
> +
> /* operand extractors */
>
> static uint32_t operand_rd(rv_inst inst)
> @@ -1815,52 +1819,52 @@ static const rv_opcode_data rvi_opcode_data[]
> = {
> { "fcvt.q.lu", rv_codec_r_m, rv_fmt_rm_frd_rs1 },
> { "fmv.x.q", rv_codec_r, rv_fmt_rd_frs1 },
> { "fmv.q.x", rv_codec_r, rv_fmt_frd_rs1 },
> - { "c.addi4spn", rv_codec_ciw_4spn, rv_fmt_rd_rs1_imm, NULL,
> rv_op_addi },
> - { "c.fld", rv_codec_cl_ld, rv_fmt_frd_offset_rs1, NULL,
> rv_op_fld },
> - { "c.lw", rv_codec_cl_lw, rv_fmt_rd_offset_rs1, NULL, rv_op_lw
> },
> - { "c.flw", rv_codec_cl_lw, rv_fmt_frd_offset_rs1, NULL,
> rv_op_flw },
> - { "c.fsd", rv_codec_cs_sd, rv_fmt_frs2_offset_rs1, NULL,
> rv_op_fsd },
> - { "c.sw", rv_codec_cs_sw, rv_fmt_rs2_offset_rs1, NULL, rv_op_sw
> },
> - { "c.fsw", rv_codec_cs_sw, rv_fmt_frs2_offset_rs1, NULL,
> rv_op_fsw },
> + { "c.addi4spn", rv_codec_ciw_4spn, rv_fmt_rd_rs1_imm,
> DECOMP(rv_op_addi) },
> + { "c.fld", rv_codec_cl_ld, rv_fmt_frd_offset_rs1,
> DECOMP(rv_op_fld) },
> + { "c.lw", rv_codec_cl_lw, rv_fmt_rd_offset_rs1, DECOMP(rv_op_lw)
> },
> + { "c.flw", rv_codec_cl_lw, rv_fmt_frd_offset_rs1,
> DECOMP(rv_op_flw) },
> + { "c.fsd", rv_codec_cs_sd, rv_fmt_frs2_offset_rs1,
> DECOMP(rv_op_fsd) },
> + { "c.sw", rv_codec_cs_sw, rv_fmt_rs2_offset_rs1,
> DECOMP(rv_op_sw) },
> + { "c.fsw", rv_codec_cs_sw, rv_fmt_frs2_offset_rs1,
> DECOMP(rv_op_fsw) },
> { },
> - { "c.addi", rv_codec_ci, rv_fmt_rd_rs1_imm, NULL, rv_op_addi },
> - { "c.jal", rv_codec_cj_jal, rv_fmt_rd_offset, NULL, rv_op_jal },
> - { "c.li", rv_codec_ci_li, rv_fmt_rd_rs1_imm, NULL, rv_op_addi },
> - { "c.addi16sp", rv_codec_ci_16sp, rv_fmt_rd_rs1_imm, NULL,
> rv_op_addi },
> - { "c.lui", rv_codec_ci_lui, rv_fmt_rd_uimm, NULL, rv_op_lui },
> - { "c.srli", rv_codec_cb_sh6, rv_fmt_rd_rs1_imm, NULL, rv_op_srli
> },
> - { "c.srai", rv_codec_cb_sh6, rv_fmt_rd_rs1_imm, NULL, rv_op_srai
> },
> - { "c.andi", rv_codec_cb_imm, rv_fmt_rd_rs1_imm, NULL, rv_op_andi
> },
> - { "c.sub", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_sub },
> - { "c.xor", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_xor },
> - { "c.or", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_or },
> - { "c.and", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_and },
> - { "c.subw", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_subw },
> - { "c.addw", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_addw },
> - { "c.j", rv_codec_cj, rv_fmt_rd_offset, NULL, rv_op_jal },
> - { "c.beqz", rv_codec_cb, rv_fmt_rs1_rs2_offset, NULL, rv_op_beq
> },
> - { "c.bnez", rv_codec_cb, rv_fmt_rs1_rs2_offset, NULL, rv_op_bne
> },
> - { "c.slli", rv_codec_ci_sh6, rv_fmt_rd_rs1_imm, NULL, rv_op_slli
> },
> - { "c.fldsp", rv_codec_ci_ldsp, rv_fmt_frd_offset_rs1, NULL,
> rv_op_fld },
> - { "c.lwsp", rv_codec_ci_lwsp, rv_fmt_rd_offset_rs1, NULL,
> rv_op_lw },
> - { "c.flwsp", rv_codec_ci_lwsp, rv_fmt_frd_offset_rs1, NULL,
> rv_op_flw },
> - { "c.jr", rv_codec_cr_jr, rv_fmt_rd_rs1_offset, NULL, rv_op_jalr
> },
> - { "c.mv", rv_codec_cr_mv, rv_fmt_rd_rs1_rs2, NULL, rv_op_addi },
> - { "c.ebreak", rv_codec_ci_none, rv_fmt_none, NULL, rv_op_ebreak
> },
> - { "c.jalr", rv_codec_cr_jalr, rv_fmt_rd_rs1_offset, NULL,
> rv_op_jalr },
> - { "c.add", rv_codec_cr, rv_fmt_rd_rs1_rs2, NULL, rv_op_add },
> - { "c.fsdsp", rv_codec_css_sdsp, rv_fmt_frs2_offset_rs1, NULL,
> rv_op_fsd },
> - { "c.swsp", rv_codec_css_swsp, rv_fmt_rs2_offset_rs1, NULL,
> rv_op_sw },
> - { "c.fswsp", rv_codec_css_swsp, rv_fmt_frs2_offset_rs1, NULL,
> rv_op_fsw },
> - { "c.ld", rv_codec_cl_ld, rv_fmt_rd_offset_rs1, NULL, rv_op_ld
> },
> - { "c.sd", rv_codec_cs_sd, rv_fmt_rs2_offset_rs1, NULL, rv_op_sd
> },
> - { "c.addiw", rv_codec_ci, rv_fmt_rd_rs1_imm, NULL, rv_op_addiw
> },
> - { "c.ldsp", rv_codec_ci_ldsp, rv_fmt_rd_offset_rs1, NULL,
> rv_op_ld },
> - { "c.sdsp", rv_codec_css_sdsp, rv_fmt_rs2_offset_rs1, NULL,
> rv_op_sd },
> - { "c.lq", rv_codec_cl_lq, rv_fmt_rd_offset_rs1, NULL, rv_op_lq
> },
> - { "c.sq", rv_codec_cs_sq, rv_fmt_rs2_offset_rs1, NULL, rv_op_sq
> },
> - { "c.lqsp", rv_codec_ci_lqsp, rv_fmt_rd_offset_rs1, NULL,
> rv_op_lq },
> - { "c.sqsp", rv_codec_css_sqsp, rv_fmt_rs2_offset_rs1, NULL,
> rv_op_sq },
> + { "c.addi", rv_codec_ci, rv_fmt_rd_rs1_imm, DECOMP(rv_op_addi)
> },
> + { "c.jal", rv_codec_cj_jal, rv_fmt_rd_offset, DECOMP(rv_op_jal)
> },
> + { "c.li", rv_codec_ci_li, rv_fmt_rd_rs1_imm, DECOMP(rv_op_addi)
> },
> + { "c.addi16sp", rv_codec_ci_16sp, rv_fmt_rd_rs1_imm,
> DECOMP(rv_op_addi) },
> + { "c.lui", rv_codec_ci_lui, rv_fmt_rd_uimm, DECOMP(rv_op_lui) },
> + { "c.srli", rv_codec_cb_sh6, rv_fmt_rd_rs1_imm,
> DECOMP(rv_op_srli) },
> + { "c.srai", rv_codec_cb_sh6, rv_fmt_rd_rs1_imm,
> DECOMP(rv_op_srai) },
> + { "c.andi", rv_codec_cb_imm, rv_fmt_rd_rs1_imm,
> DECOMP(rv_op_andi) },
> + { "c.sub", rv_codec_cs, rv_fmt_rd_rs1_rs2, DECOMP(rv_op_sub) },
> + { "c.xor", rv_codec_cs, rv_fmt_rd_rs1_rs2, DECOMP(rv_op_xor) },
> + { "c.or", rv_codec_cs, rv_fmt_rd_rs1_rs2, DECOMP(rv_op_or) },
> + { "c.and", rv_codec_cs, rv_fmt_rd_rs1_rs2, DECOMP(rv_op_and) },
> + { "c.subw", rv_codec_cs, rv_fmt_rd_rs1_rs2, DECOMP(rv_op_subw)
> },
> + { "c.addw", rv_codec_cs, rv_fmt_rd_rs1_rs2, DECOMP(rv_op_addw)
> },
> + { "c.j", rv_codec_cj, rv_fmt_rd_offset, DECOMP(rv_op_jal) },
> + { "c.beqz", rv_codec_cb, rv_fmt_rs1_rs2_offset,
> DECOMP(rv_op_beq) },
> + { "c.bnez", rv_codec_cb, rv_fmt_rs1_rs2_offset,
> DECOMP(rv_op_bne) },
> + { "c.slli", rv_codec_ci_sh6, rv_fmt_rd_rs1_imm,
> DECOMP(rv_op_slli) },
> + { "c.fldsp", rv_codec_ci_ldsp, rv_fmt_frd_offset_rs1,
> DECOMP(rv_op_fld) },
> + { "c.lwsp", rv_codec_ci_lwsp, rv_fmt_rd_offset_rs1,
> DECOMP(rv_op_lw) },
> + { "c.flwsp", rv_codec_ci_lwsp, rv_fmt_frd_offset_rs1,
> DECOMP(rv_op_flw) },
> + { "c.jr", rv_codec_cr_jr, rv_fmt_rd_rs1_offset,
> DECOMP(rv_op_jalr) },
> + { "c.mv", rv_codec_cr_mv, rv_fmt_rd_rs1_rs2, DECOMP(rv_op_addi)
> },
> + { "c.ebreak", rv_codec_ci_none, rv_fmt_none,
> DECOMP(rv_op_ebreak) },
> + { "c.jalr", rv_codec_cr_jalr, rv_fmt_rd_rs1_offset,
> DECOMP(rv_op_jalr) },
> + { "c.add", rv_codec_cr, rv_fmt_rd_rs1_rs2, DECOMP(rv_op_add) },
> + { "c.fsdsp", rv_codec_css_sdsp, rv_fmt_frs2_offset_rs1,
> DECOMP(rv_op_fsd) },
> + { "c.swsp", rv_codec_css_swsp, rv_fmt_rs2_offset_rs1,
> DECOMP(rv_op_sw) },
> + { "c.fswsp", rv_codec_css_swsp, rv_fmt_frs2_offset_rs1,
> DECOMP(rv_op_fsw) },
> + { "c.ld", rv_codec_cl_ld, rv_fmt_rd_offset_rs1, DECOMP(rv_op_ld)
> },
> + { "c.sd", rv_codec_cs_sd, rv_fmt_rs2_offset_rs1,
> DECOMP(rv_op_sd) },
> + { "c.addiw", rv_codec_ci, rv_fmt_rd_rs1_imm, DECOMP(rv_op_addiw)
> },
> + { "c.ldsp", rv_codec_ci_ldsp, rv_fmt_rd_offset_rs1,
> DECOMP(rv_op_ld) },
> + { "c.sdsp", rv_codec_css_sdsp, rv_fmt_rs2_offset_rs1,
> DECOMP(rv_op_sd) },
> + { "c.lq", rv_codec_cl_lq, rv_fmt_rd_offset_rs1, DECOMP(rv_op_lq)
> },
> + { "c.sq", rv_codec_cs_sq, rv_fmt_rs2_offset_rs1,
> DECOMP(rv_op_sq) },
> + { "c.lqsp", rv_codec_ci_lqsp, rv_fmt_rd_offset_rs1,
> DECOMP(rv_op_lq) },
> + { "c.sqsp", rv_codec_css_sqsp, rv_fmt_rs2_offset_rs1,
> DECOMP(rv_op_sq) },
> { "nop", rv_codec_i, rv_fmt_none },
> { "mv", rv_codec_i, rv_fmt_rd_rs1 },
> { "not", rv_codec_i, rv_fmt_rd_rs1 },
> @@ -2542,8 +2546,8 @@ static const rv_opcode_data rvi_opcode_data[] =
> {
> { "ssrdp", rv_codec_r, rv_fmt_rd },
> { "ssamoswap.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
> { "ssamoswap.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
> - { "c.sspush", rv_codec_cmop_ss, rv_fmt_rs2, NULL, rv_op_sspush
> },
> - { "c.sspopchk", rv_codec_cmop_ss, rv_fmt_rs1, NULL,
> rv_op_sspopchk },
> + { "c.sspush", rv_codec_cmop_ss, rv_fmt_rs2, DECOMP(rv_op_sspush)
> },
> + { "c.sspopchk", rv_codec_cmop_ss, rv_fmt_rs1,
> DECOMP(rv_op_sspopchk) },
> { "cbo.inval", rv_codec_r, rv_fmt_rs1 },
> { "cbo.clean", rv_codec_r, rv_fmt_rs1 },
> { "cbo.flush", rv_codec_r, rv_fmt_rs1 },
> @@ -5269,20 +5273,6 @@ static const rv_opcode_data
> *decode_inst_lift_pseudo(rv_decode *dec,
> return op;
> }
>
> -/* decompress instruction */
> -
> -static const rv_opcode_data *decode_inst_decompress(rv_decode *dec,
> - const
> rv_opcode_data *op)
> -{
> - int decomp_op = op->decomp;
> -
> - if (decomp_op != rv_op_illegal) {
> - dec->op = decomp_op;
> - op = &dec->opcode_data[decomp_op];
> - }
> - return op;
> -}
> -
> /* disassemble instruction */
>
> static GString *disasm_inst(rv_isa isa, uint64_t pc, rv_inst inst,
> @@ -5333,7 +5323,6 @@ static GString *disasm_inst(rv_isa isa,
> uint64_t pc, rv_inst inst,
>
> op = &dec.opcode_data[dec.op];
> decode_inst_operands(&dec, isa, op);
> - op = decode_inst_decompress(&dec, op);
> op = decode_inst_lift_pseudo(&dec, op);
> return format_inst(24, &dec, op);
> }
^ permalink raw reply [flat|nested] 119+ messages in thread
* Re: [PATCH 33/56] disas/riscv: Drop format from DECOMP insns
2026-08-09 22:35 ` [PATCH 33/56] disas/riscv: Drop format from DECOMP insns Richard Henderson
@ 2026-08-11 20:25 ` Alistair
0 siblings, 0 replies; 119+ messages in thread
From: Alistair @ 2026-08-11 20:25 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: qemu-riscv
On Sun, 2026-08-09 at 15:35 -0700, Richard Henderson wrote:
> The format for these will never be used -- we will use
> the format from the decompressed insn.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> disas/riscv.c | 94 +++++++++++++++++++++++++------------------------
> --
> 1 file changed, 47 insertions(+), 47 deletions(-)
>
> diff --git a/disas/riscv.c b/disas/riscv.c
> index 129e545c6e..9904b4db03 100644
> --- a/disas/riscv.c
> +++ b/disas/riscv.c
> @@ -1819,52 +1819,52 @@ static const rv_opcode_data rvi_opcode_data[]
> = {
> { "fcvt.q.lu", rv_codec_r_m, rv_fmt_rm_frd_rs1 },
> { "fmv.x.q", rv_codec_r, rv_fmt_rd_frs1 },
> { "fmv.q.x", rv_codec_r, rv_fmt_frd_rs1 },
> - { "c.addi4spn", rv_codec_ciw_4spn, rv_fmt_rd_rs1_imm,
> DECOMP(rv_op_addi) },
> - { "c.fld", rv_codec_cl_ld, rv_fmt_frd_offset_rs1,
> DECOMP(rv_op_fld) },
> - { "c.lw", rv_codec_cl_lw, rv_fmt_rd_offset_rs1, DECOMP(rv_op_lw)
> },
> - { "c.flw", rv_codec_cl_lw, rv_fmt_frd_offset_rs1,
> DECOMP(rv_op_flw) },
> - { "c.fsd", rv_codec_cs_sd, rv_fmt_frs2_offset_rs1,
> DECOMP(rv_op_fsd) },
> - { "c.sw", rv_codec_cs_sw, rv_fmt_rs2_offset_rs1,
> DECOMP(rv_op_sw) },
> - { "c.fsw", rv_codec_cs_sw, rv_fmt_frs2_offset_rs1,
> DECOMP(rv_op_fsw) },
> + { "c.addi4spn", rv_codec_ciw_4spn, NULL, DECOMP(rv_op_addi) },
> + { "c.fld", rv_codec_cl_ld, NULL, DECOMP(rv_op_fld) },
> + { "c.lw", rv_codec_cl_lw, NULL, DECOMP(rv_op_lw) },
> + { "c.flw", rv_codec_cl_lw, NULL, DECOMP(rv_op_flw) },
> + { "c.fsd", rv_codec_cs_sd, NULL, DECOMP(rv_op_fsd) },
> + { "c.sw", rv_codec_cs_sw, NULL, DECOMP(rv_op_sw) },
> + { "c.fsw", rv_codec_cs_sw, NULL, DECOMP(rv_op_fsw) },
> { },
> - { "c.addi", rv_codec_ci, rv_fmt_rd_rs1_imm, DECOMP(rv_op_addi)
> },
> - { "c.jal", rv_codec_cj_jal, rv_fmt_rd_offset, DECOMP(rv_op_jal)
> },
> - { "c.li", rv_codec_ci_li, rv_fmt_rd_rs1_imm, DECOMP(rv_op_addi)
> },
> - { "c.addi16sp", rv_codec_ci_16sp, rv_fmt_rd_rs1_imm,
> DECOMP(rv_op_addi) },
> - { "c.lui", rv_codec_ci_lui, rv_fmt_rd_uimm, DECOMP(rv_op_lui) },
> - { "c.srli", rv_codec_cb_sh6, rv_fmt_rd_rs1_imm,
> DECOMP(rv_op_srli) },
> - { "c.srai", rv_codec_cb_sh6, rv_fmt_rd_rs1_imm,
> DECOMP(rv_op_srai) },
> - { "c.andi", rv_codec_cb_imm, rv_fmt_rd_rs1_imm,
> DECOMP(rv_op_andi) },
> - { "c.sub", rv_codec_cs, rv_fmt_rd_rs1_rs2, DECOMP(rv_op_sub) },
> - { "c.xor", rv_codec_cs, rv_fmt_rd_rs1_rs2, DECOMP(rv_op_xor) },
> - { "c.or", rv_codec_cs, rv_fmt_rd_rs1_rs2, DECOMP(rv_op_or) },
> - { "c.and", rv_codec_cs, rv_fmt_rd_rs1_rs2, DECOMP(rv_op_and) },
> - { "c.subw", rv_codec_cs, rv_fmt_rd_rs1_rs2, DECOMP(rv_op_subw)
> },
> - { "c.addw", rv_codec_cs, rv_fmt_rd_rs1_rs2, DECOMP(rv_op_addw)
> },
> - { "c.j", rv_codec_cj, rv_fmt_rd_offset, DECOMP(rv_op_jal) },
> - { "c.beqz", rv_codec_cb, rv_fmt_rs1_rs2_offset,
> DECOMP(rv_op_beq) },
> - { "c.bnez", rv_codec_cb, rv_fmt_rs1_rs2_offset,
> DECOMP(rv_op_bne) },
> - { "c.slli", rv_codec_ci_sh6, rv_fmt_rd_rs1_imm,
> DECOMP(rv_op_slli) },
> - { "c.fldsp", rv_codec_ci_ldsp, rv_fmt_frd_offset_rs1,
> DECOMP(rv_op_fld) },
> - { "c.lwsp", rv_codec_ci_lwsp, rv_fmt_rd_offset_rs1,
> DECOMP(rv_op_lw) },
> - { "c.flwsp", rv_codec_ci_lwsp, rv_fmt_frd_offset_rs1,
> DECOMP(rv_op_flw) },
> - { "c.jr", rv_codec_cr_jr, rv_fmt_rd_rs1_offset,
> DECOMP(rv_op_jalr) },
> - { "c.mv", rv_codec_cr_mv, rv_fmt_rd_rs1_rs2, DECOMP(rv_op_addi)
> },
> - { "c.ebreak", rv_codec_ci_none, rv_fmt_none,
> DECOMP(rv_op_ebreak) },
> - { "c.jalr", rv_codec_cr_jalr, rv_fmt_rd_rs1_offset,
> DECOMP(rv_op_jalr) },
> - { "c.add", rv_codec_cr, rv_fmt_rd_rs1_rs2, DECOMP(rv_op_add) },
> - { "c.fsdsp", rv_codec_css_sdsp, rv_fmt_frs2_offset_rs1,
> DECOMP(rv_op_fsd) },
> - { "c.swsp", rv_codec_css_swsp, rv_fmt_rs2_offset_rs1,
> DECOMP(rv_op_sw) },
> - { "c.fswsp", rv_codec_css_swsp, rv_fmt_frs2_offset_rs1,
> DECOMP(rv_op_fsw) },
> - { "c.ld", rv_codec_cl_ld, rv_fmt_rd_offset_rs1, DECOMP(rv_op_ld)
> },
> - { "c.sd", rv_codec_cs_sd, rv_fmt_rs2_offset_rs1,
> DECOMP(rv_op_sd) },
> - { "c.addiw", rv_codec_ci, rv_fmt_rd_rs1_imm, DECOMP(rv_op_addiw)
> },
> - { "c.ldsp", rv_codec_ci_ldsp, rv_fmt_rd_offset_rs1,
> DECOMP(rv_op_ld) },
> - { "c.sdsp", rv_codec_css_sdsp, rv_fmt_rs2_offset_rs1,
> DECOMP(rv_op_sd) },
> - { "c.lq", rv_codec_cl_lq, rv_fmt_rd_offset_rs1, DECOMP(rv_op_lq)
> },
> - { "c.sq", rv_codec_cs_sq, rv_fmt_rs2_offset_rs1,
> DECOMP(rv_op_sq) },
> - { "c.lqsp", rv_codec_ci_lqsp, rv_fmt_rd_offset_rs1,
> DECOMP(rv_op_lq) },
> - { "c.sqsp", rv_codec_css_sqsp, rv_fmt_rs2_offset_rs1,
> DECOMP(rv_op_sq) },
> + { "c.addi", rv_codec_ci, NULL, DECOMP(rv_op_addi) },
> + { "c.jal", rv_codec_cj_jal, NULL, DECOMP(rv_op_jal) },
> + { "c.li", rv_codec_ci_li, NULL, DECOMP(rv_op_addi) },
> + { "c.addi16sp", rv_codec_ci_16sp, NULL, DECOMP(rv_op_addi) },
> + { "c.lui", rv_codec_ci_lui, NULL, DECOMP(rv_op_lui) },
> + { "c.srli", rv_codec_cb_sh6, NULL, DECOMP(rv_op_srli) },
> + { "c.srai", rv_codec_cb_sh6, NULL, DECOMP(rv_op_srai) },
> + { "c.andi", rv_codec_cb_imm, NULL, DECOMP(rv_op_andi) },
> + { "c.sub", rv_codec_cs, NULL, DECOMP(rv_op_sub) },
> + { "c.xor", rv_codec_cs, NULL, DECOMP(rv_op_xor) },
> + { "c.or", rv_codec_cs, NULL, DECOMP(rv_op_or) },
> + { "c.and", rv_codec_cs, NULL, DECOMP(rv_op_and) },
> + { "c.subw", rv_codec_cs, NULL, DECOMP(rv_op_subw) },
> + { "c.addw", rv_codec_cs, NULL, DECOMP(rv_op_addw) },
> + { "c.j", rv_codec_cj, NULL, DECOMP(rv_op_jal) },
> + { "c.beqz", rv_codec_cb, NULL, DECOMP(rv_op_beq) },
> + { "c.bnez", rv_codec_cb, NULL, DECOMP(rv_op_bne) },
> + { "c.slli", rv_codec_ci_sh6, NULL, DECOMP(rv_op_slli) },
> + { "c.fldsp", rv_codec_ci_ldsp, NULL, DECOMP(rv_op_fld) },
> + { "c.lwsp", rv_codec_ci_lwsp, NULL, DECOMP(rv_op_lw) },
> + { "c.flwsp", rv_codec_ci_lwsp, NULL, DECOMP(rv_op_flw) },
> + { "c.jr", rv_codec_cr_jr, NULL, DECOMP(rv_op_jalr) },
> + { "c.mv", rv_codec_cr_mv, NULL, DECOMP(rv_op_addi) },
> + { "c.ebreak", rv_codec_ci_none, NULL, DECOMP(rv_op_ebreak) },
> + { "c.jalr", rv_codec_cr_jalr, NULL, DECOMP(rv_op_jalr) },
> + { "c.add", rv_codec_cr, NULL, DECOMP(rv_op_add) },
> + { "c.fsdsp", rv_codec_css_sdsp, NULL, DECOMP(rv_op_fsd) },
> + { "c.swsp", rv_codec_css_swsp, NULL, DECOMP(rv_op_sw) },
> + { "c.fswsp", rv_codec_css_swsp, NULL, DECOMP(rv_op_fsw) },
> + { "c.ld", rv_codec_cl_ld, NULL, DECOMP(rv_op_ld) },
> + { "c.sd", rv_codec_cs_sd, NULL, DECOMP(rv_op_sd) },
> + { "c.addiw", rv_codec_ci, NULL, DECOMP(rv_op_addiw) },
> + { "c.ldsp", rv_codec_ci_ldsp, NULL, DECOMP(rv_op_ld) },
> + { "c.sdsp", rv_codec_css_sdsp, NULL, DECOMP(rv_op_sd) },
> + { "c.lq", rv_codec_cl_lq, NULL, DECOMP(rv_op_lq) },
> + { "c.sq", rv_codec_cs_sq, NULL, DECOMP(rv_op_sq) },
> + { "c.lqsp", rv_codec_ci_lqsp, NULL, DECOMP(rv_op_lq) },
> + { "c.sqsp", rv_codec_css_sqsp, NULL, DECOMP(rv_op_sq) },
> { "nop", rv_codec_i, rv_fmt_none },
> { "mv", rv_codec_i, rv_fmt_rd_rs1 },
> { "not", rv_codec_i, rv_fmt_rd_rs1 },
> @@ -2546,8 +2546,8 @@ static const rv_opcode_data rvi_opcode_data[] =
> {
> { "ssrdp", rv_codec_r, rv_fmt_rd },
> { "ssamoswap.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
> { "ssamoswap.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
> - { "c.sspush", rv_codec_cmop_ss, rv_fmt_rs2, DECOMP(rv_op_sspush)
> },
> - { "c.sspopchk", rv_codec_cmop_ss, rv_fmt_rs1,
> DECOMP(rv_op_sspopchk) },
> + { "c.sspush", rv_codec_cmop_ss, NULL, DECOMP(rv_op_sspush) },
> + { "c.sspopchk", rv_codec_cmop_ss, NULL, DECOMP(rv_op_sspopchk)
> },
> { "cbo.inval", rv_codec_r, rv_fmt_rs1 },
> { "cbo.clean", rv_codec_r, rv_fmt_rs1 },
> { "cbo.flush", rv_codec_r, rv_fmt_rs1 },
^ permalink raw reply [flat|nested] 119+ messages in thread
* Re: [PATCH 34/56] disas/riscv: Tidy rv_comp_data terminators
2026-08-09 22:35 ` [PATCH 34/56] disas/riscv: Tidy rv_comp_data terminators Richard Henderson
@ 2026-08-11 20:25 ` Alistair
0 siblings, 0 replies; 119+ messages in thread
From: Alistair @ 2026-08-11 20:25 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: qemu-riscv
On Sun, 2026-08-09 at 15:35 -0700, Richard Henderson wrote:
> Use { } instead of two zeros.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> disas/riscv.c | 46 +++++++++++++++++++++++-----------------------
> 1 file changed, 23 insertions(+), 23 deletions(-)
>
> diff --git a/disas/riscv.c b/disas/riscv.c
> index 9904b4db03..bb4779614b 100644
> --- a/disas/riscv.c
> +++ b/disas/riscv.c
> @@ -1072,123 +1072,123 @@ static const rvc_constraint rvcc_true[] = {
> rvc_end };
> static const rv_comp_data rvcp_jal[] = {
> { rv_op_j, rvcc_j },
> { rv_op_jal_ra, rvcc_jal_ra },
> - { rv_op_illegal, NULL }
> + { },
> };
>
> static const rv_comp_data rvcp_jalr[] = {
> { rv_op_ret, rvcc_ret },
> { rv_op_jr, rvcc_jr },
> { rv_op_jalr_ra, rvcc_jalr_ra },
> - { rv_op_illegal, NULL }
> + { },
> };
>
> static const rv_comp_data rvcp_beq[] = {
> { rv_op_beqz, rvcc_beqz },
> - { rv_op_illegal, NULL }
> + { },
> };
>
> static const rv_comp_data rvcp_bne[] = {
> { rv_op_bnez, rvcc_bnez },
> - { rv_op_illegal, NULL }
> + { },
> };
>
> static const rv_comp_data rvcp_blt[] = {
> { rv_op_bltz, rvcc_bltz },
> { rv_op_bgtz, rvcc_bgtz },
> - { rv_op_illegal, NULL }
> + { },
> };
>
> static const rv_comp_data rvcp_bge[] = {
> { rv_op_blez, rvcc_blez },
> { rv_op_bgez, rvcc_bgez },
> - { rv_op_illegal, NULL }
> + { },
> };
>
> static const rv_comp_data rvcp_addi[] = {
> { rv_op_nop, rvcc_nop },
> { rv_op_mv, rvcc_mv },
> - { rv_op_illegal, NULL }
> + { },
> };
>
> static const rv_comp_data rvcp_sltiu[] = {
> { rv_op_seqz, rvcc_seqz },
> - { rv_op_illegal, NULL }
> + { },
> };
>
> static const rv_comp_data rvcp_xori[] = {
> { rv_op_not, rvcc_not },
> - { rv_op_illegal, NULL }
> + { },
> };
>
> static const rv_comp_data rvcp_sub[] = {
> { rv_op_neg, rvcc_neg },
> - { rv_op_illegal, NULL }
> + { },
> };
>
> static const rv_comp_data rvcp_slt[] = {
> { rv_op_sltz, rvcc_sltz },
> { rv_op_sgtz, rvcc_sgtz },
> - { rv_op_illegal, NULL }
> + { },
> };
>
> static const rv_comp_data rvcp_sltu[] = {
> { rv_op_snez, rvcc_snez },
> - { rv_op_illegal, NULL }
> + { },
> };
>
> static const rv_comp_data rvcp_addiw[] = {
> { rv_op_sext_w, rvcc_sext_w },
> - { rv_op_illegal, NULL }
> + { },
> };
>
> static const rv_comp_data rvcp_subw[] = {
> { rv_op_negw, rvcc_negw },
> - { rv_op_illegal, NULL }
> + { },
> };
>
> static const rv_comp_data rvcp_fsgnj_s[] = {
> { rv_op_fmv_s, rvcc_fmv_s },
> - { rv_op_illegal, NULL }
> + { },
> };
>
> static const rv_comp_data rvcp_fsgnjn_s[] = {
> { rv_op_fneg_s, rvcc_fneg_s },
> - { rv_op_illegal, NULL }
> + { },
> };
>
> static const rv_comp_data rvcp_fsgnjx_s[] = {
> { rv_op_fabs_s, rvcc_fabs_s },
> - { rv_op_illegal, NULL }
> + { },
> };
>
> static const rv_comp_data rvcp_fsgnj_d[] = {
> { rv_op_fmv_d, rvcc_fmv_d },
> - { rv_op_illegal, NULL }
> + { },
> };
>
> static const rv_comp_data rvcp_fsgnjn_d[] = {
> { rv_op_fneg_d, rvcc_fneg_d },
> - { rv_op_illegal, NULL }
> + { },
> };
>
> static const rv_comp_data rvcp_fsgnjx_d[] = {
> { rv_op_fabs_d, rvcc_fabs_d },
> - { rv_op_illegal, NULL }
> + { },
> };
>
> static const rv_comp_data rvcp_fsgnj_q[] = {
> { rv_op_fmv_q, rvcc_fmv_q },
> - { rv_op_illegal, NULL }
> + { },
> };
>
> static const rv_comp_data rvcp_fsgnjn_q[] = {
> { rv_op_fneg_q, rvcc_fneg_q },
> - { rv_op_illegal, NULL }
> + { },
> };
>
> static const rv_comp_data rvcp_fsgnjx_q[] = {
> { rv_op_fabs_q, rvcc_fabs_q },
> - { rv_op_illegal, NULL }
> + { },
> };
>
> /* Convert compressed insns into normal insns via pseudo expansion.
> */
^ permalink raw reply [flat|nested] 119+ messages in thread
* Re: [PATCH 35/56] disas/riscv: Chain "ret" pseudo off "jr" pseudo
2026-08-09 22:35 ` [PATCH 35/56] disas/riscv: Chain "ret" pseudo off "jr" pseudo Richard Henderson
@ 2026-08-11 20:26 ` Alistair
0 siblings, 0 replies; 119+ messages in thread
From: Alistair @ 2026-08-11 20:26 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: qemu-riscv
On Sun, 2026-08-09 at 15:35 -0700, Richard Henderson wrote:
> "jr" has already checked two conditions that apply to "ret".
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> disas/riscv.c | 11 +++++++----
> 1 file changed, 7 insertions(+), 4 deletions(-)
>
> diff --git a/disas/riscv.c b/disas/riscv.c
> index bb4779614b..2fec135b5f 100644
> --- a/disas/riscv.c
> +++ b/disas/riscv.c
> @@ -1061,8 +1061,7 @@ static const rvc_constraint rvcc_bgez[] = {
> rvc_rs2_eq_x0, rvc_end };
> static const rvc_constraint rvcc_bltz[] = { rvc_rs2_eq_x0, rvc_end
> };
> static const rvc_constraint rvcc_bgtz[] = { rvc_rs1_eq_x0, rvc_end
> };
> static const rvc_constraint rvcc_j[] = { rvc_rd_eq_x0, rvc_end };
> -static const rvc_constraint rvcc_ret[] = { rvc_rd_eq_x0,
> rvc_rs1_eq_ra,
> - rvc_end };
> +static const rvc_constraint rvcc_ret[] = { rvc_rs1_eq_ra, rvc_end };
> static const rvc_constraint rvcc_jr[] = { rvc_rd_eq_x0,
> rvc_imm_eq_zero,
> rvc_end };
> static const rvc_constraint rvcc_true[] = { rvc_end };
> @@ -1076,12 +1075,16 @@ static const rv_comp_data rvcp_jal[] = {
> };
>
> static const rv_comp_data rvcp_jalr[] = {
> - { rv_op_ret, rvcc_ret },
> { rv_op_jr, rvcc_jr },
> { rv_op_jalr_ra, rvcc_jalr_ra },
> { },
> };
>
> +static const rv_comp_data rvcp_jr[] = {
> + { rv_op_ret, rvcc_ret },
> + { },
> +};
> +
> static const rv_comp_data rvcp_beq[] = {
> { rv_op_beqz, rvcc_beqz },
> { },
> @@ -1896,7 +1899,7 @@ static const rv_opcode_data rvi_opcode_data[] =
> {
> { },
> { "j", rv_codec_uj, rv_fmt_offset },
> { "ret", rv_codec_i, rv_fmt_none },
> - { "jr", rv_codec_i, rv_fmt_rs1 },
> + { "jr", rv_codec_i, rv_fmt_rs1, rvcp_jr },
> { "rdcycle", rv_codec_i_csr, rv_fmt_rd },
> { "rdtime", rv_codec_i_csr, rv_fmt_rd },
> { "rdinstret", rv_codec_i_csr, rv_fmt_rd },
^ permalink raw reply [flat|nested] 119+ messages in thread
* Re: [PATCH 36/56] disas/riscv: Chain "nop" pseudo off "mv" pseudo
2026-08-09 22:35 ` [PATCH 36/56] disas/riscv: Chain "nop" pseudo off "mv" pseudo Richard Henderson
@ 2026-08-11 20:27 ` Alistair
0 siblings, 0 replies; 119+ messages in thread
From: Alistair @ 2026-08-11 20:27 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: qemu-riscv
On Sun, 2026-08-09 at 15:35 -0700, Richard Henderson wrote:
> "mv" has already checked a condition that applies to "nop".
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> disas/riscv.c | 10 +++++++---
> 1 file changed, 7 insertions(+), 3 deletions(-)
>
> diff --git a/disas/riscv.c b/disas/riscv.c
> index 2fec135b5f..37f6440831 100644
> --- a/disas/riscv.c
> +++ b/disas/riscv.c
> @@ -1035,7 +1035,7 @@ static const rvc_constraint rvcc_jal_ra[] = {
> rvc_rd_eq_ra, rvc_end };
> static const rvc_constraint rvcc_jalr_ra[] = { rvc_rd_eq_ra,
> rvc_imm_eq_zero,
> rvc_end };
> static const rvc_constraint rvcc_nop[] = { rvc_rd_eq_x0,
> rvc_rs1_eq_x0,
> - rvc_imm_eq_zero, rvc_end
> };
> + rvc_end };
> static const rvc_constraint rvcc_mv[] = { rvc_imm_eq_zero, rvc_end
> };
> static const rvc_constraint rvcc_not[] = { rvc_imm_eq_n1, rvc_end };
> static const rvc_constraint rvcc_neg[] = { rvc_rs1_eq_x0, rvc_end };
> @@ -1108,11 +1108,15 @@ static const rv_comp_data rvcp_bge[] = {
> };
>
> static const rv_comp_data rvcp_addi[] = {
> - { rv_op_nop, rvcc_nop },
> { rv_op_mv, rvcc_mv },
> { },
> };
>
> +static const rv_comp_data rvcp_mv[] = {
> + { rv_op_nop, rvcc_nop },
> + { },
> +};
> +
> static const rv_comp_data rvcp_sltiu[] = {
> { rv_op_seqz, rvcc_seqz },
> { },
> @@ -1869,7 +1873,7 @@ static const rv_opcode_data rvi_opcode_data[] =
> {
> { "c.lqsp", rv_codec_ci_lqsp, NULL, DECOMP(rv_op_lq) },
> { "c.sqsp", rv_codec_css_sqsp, NULL, DECOMP(rv_op_sq) },
> { "nop", rv_codec_i, rv_fmt_none },
> - { "mv", rv_codec_i, rv_fmt_rd_rs1 },
> + { "mv", rv_codec_i, rv_fmt_rd_rs1, rvcp_mv },
> { "not", rv_codec_i, rv_fmt_rd_rs1 },
> { "neg", rv_codec_r, rv_fmt_rd_rs2 },
> { "negw", rv_codec_r, rv_fmt_rd_rs2 },
^ permalink raw reply [flat|nested] 119+ messages in thread
* Re: [PATCH 37/56] disas/riscv: Use rv_codec_illegal for pseudos
2026-08-09 22:35 ` [PATCH 37/56] disas/riscv: Use rv_codec_illegal for pseudos Richard Henderson
@ 2026-08-11 20:27 ` Alistair
0 siblings, 0 replies; 119+ messages in thread
From: Alistair @ 2026-08-11 20:27 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: qemu-riscv
On Sun, 2026-08-09 at 15:35 -0700, Richard Henderson wrote:
> The codec is never used, since we arrive into pseudos
> from a decoding of another opcode.
> Assert that rv_codec_illegal is never decoded.
> Use rv_codec_none for rv_op_illegal.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> disas/riscv.c | 68 +++++++++++++++++++++++++------------------------
> --
> 1 file changed, 34 insertions(+), 34 deletions(-)
>
> diff --git a/disas/riscv.c b/disas/riscv.c
> index 37f6440831..fc821355fe 100644
> --- a/disas/riscv.c
> +++ b/disas/riscv.c
> @@ -1599,7 +1599,7 @@ static uint32_t operand_lpl(rv_inst inst)
> /* instruction metadata */
>
> static const rv_opcode_data rvi_opcode_data[] = {
> - { "illegal", rv_codec_illegal, rv_fmt_none },
> + { "illegal", rv_codec_none, rv_fmt_none },
> { "lui", rv_codec_u, rv_fmt_rd_uimm },
> { "auipc", rv_codec_u, rv_fmt_rd_uoffset },
> { "jal", rv_codec_uj, rv_fmt_rd_offset, rvcp_jal },
> @@ -1872,38 +1872,38 @@ static const rv_opcode_data rvi_opcode_data[]
> = {
> { "c.sq", rv_codec_cs_sq, NULL, DECOMP(rv_op_sq) },
> { "c.lqsp", rv_codec_ci_lqsp, NULL, DECOMP(rv_op_lq) },
> { "c.sqsp", rv_codec_css_sqsp, NULL, DECOMP(rv_op_sq) },
> - { "nop", rv_codec_i, rv_fmt_none },
> - { "mv", rv_codec_i, rv_fmt_rd_rs1, rvcp_mv },
> - { "not", rv_codec_i, rv_fmt_rd_rs1 },
> - { "neg", rv_codec_r, rv_fmt_rd_rs2 },
> - { "negw", rv_codec_r, rv_fmt_rd_rs2 },
> - { "sext.w", rv_codec_i, rv_fmt_rd_rs1 },
> - { "seqz", rv_codec_i, rv_fmt_rd_rs1 },
> - { "snez", rv_codec_r, rv_fmt_rd_rs2 },
> - { "sltz", rv_codec_r, rv_fmt_rd_rs1 },
> - { "sgtz", rv_codec_r, rv_fmt_rd_rs2 },
> - { "fmv.s", rv_codec_r, rv_fmt_frd_frs1 },
> - { "fabs.s", rv_codec_r, rv_fmt_frd_frs1 },
> - { "fneg.s", rv_codec_r, rv_fmt_frd_frs1 },
> - { "fmv.d", rv_codec_r, rv_fmt_frd_frs1 },
> - { "fabs.d", rv_codec_r, rv_fmt_frd_frs1 },
> - { "fneg.d", rv_codec_r, rv_fmt_frd_frs1 },
> - { "fmv.q", rv_codec_r, rv_fmt_frd_frs1 },
> - { "fabs.q", rv_codec_r, rv_fmt_frd_frs1 },
> - { "fneg.q", rv_codec_r, rv_fmt_frd_frs1 },
> - { "beqz", rv_codec_sb, rv_fmt_rs1_offset },
> - { "bnez", rv_codec_sb, rv_fmt_rs1_offset },
> - { "blez", rv_codec_sb, rv_fmt_rs2_offset },
> - { "bgez", rv_codec_sb, rv_fmt_rs1_offset },
> - { "bltz", rv_codec_sb, rv_fmt_rs1_offset },
> - { "bgtz", rv_codec_sb, rv_fmt_rs2_offset },
> - { "jal", rv_codec_none, rv_fmt_offset }, /* rv_op_jal_ra */
> - { "jalr", rv_codec_none, rv_fmt_rs1 }, /* rv_op_jalr_ra */
> + { "nop", rv_codec_illegal, rv_fmt_none },
> + { "mv", rv_codec_illegal, rv_fmt_rd_rs1, rvcp_mv },
> + { "not", rv_codec_illegal, rv_fmt_rd_rs1 },
> + { "neg", rv_codec_illegal, rv_fmt_rd_rs2 },
> + { "negw", rv_codec_illegal, rv_fmt_rd_rs2 },
> + { "sext.w", rv_codec_illegal, rv_fmt_rd_rs1 },
> + { "seqz", rv_codec_illegal, rv_fmt_rd_rs1 },
> + { "snez", rv_codec_illegal, rv_fmt_rd_rs2 },
> + { "sltz", rv_codec_illegal, rv_fmt_rd_rs1 },
> + { "sgtz", rv_codec_illegal, rv_fmt_rd_rs2 },
> + { "fmv.s", rv_codec_illegal, rv_fmt_frd_frs1 },
> + { "fabs.s", rv_codec_illegal, rv_fmt_frd_frs1 },
> + { "fneg.s", rv_codec_illegal, rv_fmt_frd_frs1 },
> + { "fmv.d", rv_codec_illegal, rv_fmt_frd_frs1 },
> + { "fabs.d", rv_codec_illegal, rv_fmt_frd_frs1 },
> + { "fneg.d", rv_codec_illegal, rv_fmt_frd_frs1 },
> + { "fmv.q", rv_codec_illegal, rv_fmt_frd_frs1 },
> + { "fabs.q", rv_codec_illegal, rv_fmt_frd_frs1 },
> + { "fneg.q", rv_codec_illegal, rv_fmt_frd_frs1 },
> + { "beqz", rv_codec_illegal, rv_fmt_rs1_offset },
> + { "bnez", rv_codec_illegal, rv_fmt_rs1_offset },
> + { "blez", rv_codec_illegal, rv_fmt_rs2_offset },
> + { "bgez", rv_codec_illegal, rv_fmt_rs1_offset },
> + { "bltz", rv_codec_illegal, rv_fmt_rs1_offset },
> + { "bgtz", rv_codec_illegal, rv_fmt_rs2_offset },
> + { "jal", rv_codec_illegal, rv_fmt_offset }, /* rv_op_jal_ra */
> + { "jalr", rv_codec_illegal, rv_fmt_rs1 }, /* rv_op_jalr_ra */
> { },
> { },
> - { "j", rv_codec_uj, rv_fmt_offset },
> - { "ret", rv_codec_i, rv_fmt_none },
> - { "jr", rv_codec_i, rv_fmt_rs1, rvcp_jr },
> + { "j", rv_codec_illegal, rv_fmt_offset },
> + { "ret", rv_codec_illegal, rv_fmt_none },
> + { "jr", rv_codec_illegal, rv_fmt_rs1, rvcp_jr },
> { "rdcycle", rv_codec_i_csr, rv_fmt_rd },
> { "rdtime", rv_codec_i_csr, rv_fmt_rd },
> { "rdinstret", rv_codec_i_csr, rv_fmt_rd },
> @@ -4551,8 +4551,6 @@ static void decode_inst_operands(rv_decode
> *dec, rv_isa isa,
> rv_inst inst = dec->inst;
>
> switch (op->codec) {
> - case rv_codec_illegal:
> - break;
> case rv_codec_none:
> dec->rd = dec->rs1 = dec->rs2 = rv_ireg_zero;
> dec->imm = 0;
> @@ -4946,7 +4944,9 @@ static void decode_inst_operands(rv_decode
> *dec, rv_isa isa,
> dec->rs1 = dec->rs2 = operand_crs1(inst);
> dec->imm = 0;
> break;
> - };
> + default:
> + g_assert_not_reached();
> + }
> }
>
> /* check constraint */
^ permalink raw reply [flat|nested] 119+ messages in thread
* Re: [PATCH 38/56] disas/riscv: Simplify some insn decompressions
2026-08-09 22:35 ` [PATCH 38/56] disas/riscv: Simplify some insn decompressions Richard Henderson
@ 2026-08-11 20:29 ` Alistair
0 siblings, 0 replies; 119+ messages in thread
From: Alistair @ 2026-08-11 20:29 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: qemu-riscv
On Sun, 2026-08-09 at 15:35 -0700, Richard Henderson wrote:
> Route "c.j" to "j" instead of "jal", etc.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> disas/riscv.c | 10 +++++-----
> 1 file changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/disas/riscv.c b/disas/riscv.c
> index fc821355fe..9a528803e8 100644
> --- a/disas/riscv.c
> +++ b/disas/riscv.c
> @@ -1848,15 +1848,15 @@ static const rv_opcode_data rvi_opcode_data[]
> = {
> { "c.and", rv_codec_cs, NULL, DECOMP(rv_op_and) },
> { "c.subw", rv_codec_cs, NULL, DECOMP(rv_op_subw) },
> { "c.addw", rv_codec_cs, NULL, DECOMP(rv_op_addw) },
> - { "c.j", rv_codec_cj, NULL, DECOMP(rv_op_jal) },
> - { "c.beqz", rv_codec_cb, NULL, DECOMP(rv_op_beq) },
> - { "c.bnez", rv_codec_cb, NULL, DECOMP(rv_op_bne) },
> + { "c.j", rv_codec_cj, NULL, DECOMP(rv_op_j) },
> + { "c.beqz", rv_codec_cb, NULL, DECOMP(rv_op_beqz) },
> + { "c.bnez", rv_codec_cb, NULL, DECOMP(rv_op_bnez) },
> { "c.slli", rv_codec_ci_sh6, NULL, DECOMP(rv_op_slli) },
> { "c.fldsp", rv_codec_ci_ldsp, NULL, DECOMP(rv_op_fld) },
> { "c.lwsp", rv_codec_ci_lwsp, NULL, DECOMP(rv_op_lw) },
> { "c.flwsp", rv_codec_ci_lwsp, NULL, DECOMP(rv_op_flw) },
> - { "c.jr", rv_codec_cr_jr, NULL, DECOMP(rv_op_jalr) },
> - { "c.mv", rv_codec_cr_mv, NULL, DECOMP(rv_op_addi) },
> + { "c.jr", rv_codec_cr_jr, NULL, DECOMP(rv_op_jr) },
> + { "c.mv", rv_codec_cr_mv, NULL, DECOMP(rv_op_mv) },
> { "c.ebreak", rv_codec_ci_none, NULL, DECOMP(rv_op_ebreak) },
> { "c.jalr", rv_codec_cr_jalr, NULL, DECOMP(rv_op_jalr) },
> { "c.add", rv_codec_cr, NULL, DECOMP(rv_op_add) },
^ permalink raw reply [flat|nested] 119+ messages in thread
* Re: [PATCH 39/56] disas/riscv: Store op pointer in rv_comp_data
2026-08-09 22:35 ` [PATCH 39/56] disas/riscv: Store op pointer in rv_comp_data Richard Henderson
@ 2026-08-12 12:47 ` Alistair
0 siblings, 0 replies; 119+ messages in thread
From: Alistair @ 2026-08-12 12:47 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: qemu-riscv
On Sun, 2026-08-09 at 15:35 -0700, Richard Henderson wrote:
> Store a pointer instead of an array index.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> disas/riscv.h | 8 +++---
> disas/riscv.c | 69 ++++++++++++++++++++++++++-----------------------
> --
> 2 files changed, 40 insertions(+), 37 deletions(-)
>
> diff --git a/disas/riscv.h b/disas/riscv.h
> index ea7141d3b5..ab62c0db94 100644
> --- a/disas/riscv.h
> +++ b/disas/riscv.h
> @@ -164,17 +164,19 @@ typedef enum {
>
> /* structures */
>
> +typedef struct rv_opcode_data rv_opcode_data;
> +
> typedef struct {
> - int op;
> + const rv_opcode_data *op;
> const rvc_constraint *constraints;
> } rv_comp_data;
>
> -typedef struct {
> +struct rv_opcode_data {
> const char *name;
> rv_codec codec;
> const char *format;
> const rv_comp_data *pseudo;
> -} rv_opcode_data;
> +};
>
> typedef struct {
> const RISCVCPUConfig *cfg;
> diff --git a/disas/riscv.c b/disas/riscv.c
> index 9a528803e8..171c60238f 100644
> --- a/disas/riscv.c
> +++ b/disas/riscv.c
> @@ -1068,138 +1068,140 @@ static const rvc_constraint rvcc_true[] = {
> rvc_end };
>
> /* pseudo-instruction metadata */
>
> +static const rv_opcode_data rvi_opcode_data[];
> +
> static const rv_comp_data rvcp_jal[] = {
> - { rv_op_j, rvcc_j },
> - { rv_op_jal_ra, rvcc_jal_ra },
> + { &rvi_opcode_data[rv_op_j], rvcc_j },
> + { &rvi_opcode_data[rv_op_jal_ra], rvcc_jal_ra },
> { },
> };
>
> static const rv_comp_data rvcp_jalr[] = {
> - { rv_op_jr, rvcc_jr },
> - { rv_op_jalr_ra, rvcc_jalr_ra },
> + { &rvi_opcode_data[rv_op_jr], rvcc_jr },
> + { &rvi_opcode_data[rv_op_jalr_ra], rvcc_jalr_ra },
> { },
> };
>
> static const rv_comp_data rvcp_jr[] = {
> - { rv_op_ret, rvcc_ret },
> + { &rvi_opcode_data[rv_op_ret], rvcc_ret },
> { },
> };
>
> static const rv_comp_data rvcp_beq[] = {
> - { rv_op_beqz, rvcc_beqz },
> + { &rvi_opcode_data[rv_op_beqz], rvcc_beqz },
> { },
> };
>
> static const rv_comp_data rvcp_bne[] = {
> - { rv_op_bnez, rvcc_bnez },
> + { &rvi_opcode_data[rv_op_bnez], rvcc_bnez },
> { },
> };
>
> static const rv_comp_data rvcp_blt[] = {
> - { rv_op_bltz, rvcc_bltz },
> - { rv_op_bgtz, rvcc_bgtz },
> + { &rvi_opcode_data[rv_op_bltz], rvcc_bltz },
> + { &rvi_opcode_data[rv_op_bgtz], rvcc_bgtz },
> { },
> };
>
> static const rv_comp_data rvcp_bge[] = {
> - { rv_op_blez, rvcc_blez },
> - { rv_op_bgez, rvcc_bgez },
> + { &rvi_opcode_data[rv_op_blez], rvcc_blez },
> + { &rvi_opcode_data[rv_op_bgez], rvcc_bgez },
> { },
> };
>
> static const rv_comp_data rvcp_addi[] = {
> - { rv_op_mv, rvcc_mv },
> + { &rvi_opcode_data[rv_op_mv], rvcc_mv },
> { },
> };
>
> static const rv_comp_data rvcp_mv[] = {
> - { rv_op_nop, rvcc_nop },
> + { &rvi_opcode_data[rv_op_nop], rvcc_nop },
> { },
> };
>
> static const rv_comp_data rvcp_sltiu[] = {
> - { rv_op_seqz, rvcc_seqz },
> + { &rvi_opcode_data[rv_op_seqz], rvcc_seqz },
> { },
> };
>
> static const rv_comp_data rvcp_xori[] = {
> - { rv_op_not, rvcc_not },
> + { &rvi_opcode_data[rv_op_not], rvcc_not },
> { },
> };
>
> static const rv_comp_data rvcp_sub[] = {
> - { rv_op_neg, rvcc_neg },
> + { &rvi_opcode_data[rv_op_neg], rvcc_neg },
> { },
> };
>
> static const rv_comp_data rvcp_slt[] = {
> - { rv_op_sltz, rvcc_sltz },
> - { rv_op_sgtz, rvcc_sgtz },
> + { &rvi_opcode_data[rv_op_sltz], rvcc_sltz },
> + { &rvi_opcode_data[rv_op_sgtz], rvcc_sgtz },
> { },
> };
>
> static const rv_comp_data rvcp_sltu[] = {
> - { rv_op_snez, rvcc_snez },
> + { &rvi_opcode_data[rv_op_snez], rvcc_snez },
> { },
> };
>
> static const rv_comp_data rvcp_addiw[] = {
> - { rv_op_sext_w, rvcc_sext_w },
> + { &rvi_opcode_data[rv_op_sext_w], rvcc_sext_w },
> { },
> };
>
> static const rv_comp_data rvcp_subw[] = {
> - { rv_op_negw, rvcc_negw },
> + { &rvi_opcode_data[rv_op_negw], rvcc_negw },
> { },
> };
>
> static const rv_comp_data rvcp_fsgnj_s[] = {
> - { rv_op_fmv_s, rvcc_fmv_s },
> + { &rvi_opcode_data[rv_op_fmv_s], rvcc_fmv_s },
> { },
> };
>
> static const rv_comp_data rvcp_fsgnjn_s[] = {
> - { rv_op_fneg_s, rvcc_fneg_s },
> + { &rvi_opcode_data[rv_op_fneg_s], rvcc_fneg_s },
> { },
> };
>
> static const rv_comp_data rvcp_fsgnjx_s[] = {
> - { rv_op_fabs_s, rvcc_fabs_s },
> + { &rvi_opcode_data[rv_op_fabs_s], rvcc_fabs_s },
> { },
> };
>
> static const rv_comp_data rvcp_fsgnj_d[] = {
> - { rv_op_fmv_d, rvcc_fmv_d },
> + { &rvi_opcode_data[rv_op_fmv_d], rvcc_fmv_d },
> { },
> };
>
> static const rv_comp_data rvcp_fsgnjn_d[] = {
> - { rv_op_fneg_d, rvcc_fneg_d },
> + { &rvi_opcode_data[rv_op_fneg_d], rvcc_fneg_d },
> { },
> };
>
> static const rv_comp_data rvcp_fsgnjx_d[] = {
> - { rv_op_fabs_d, rvcc_fabs_d },
> + { &rvi_opcode_data[rv_op_fabs_d], rvcc_fabs_d },
> { },
> };
>
> static const rv_comp_data rvcp_fsgnj_q[] = {
> - { rv_op_fmv_q, rvcc_fmv_q },
> + { &rvi_opcode_data[rv_op_fmv_q], rvcc_fmv_q },
> { },
> };
>
> static const rv_comp_data rvcp_fsgnjn_q[] = {
> - { rv_op_fneg_q, rvcc_fneg_q },
> + { &rvi_opcode_data[rv_op_fneg_q], rvcc_fneg_q },
> { },
> };
>
> static const rv_comp_data rvcp_fsgnjx_q[] = {
> - { rv_op_fabs_q, rvcc_fabs_q },
> + { &rvi_opcode_data[rv_op_fabs_q], rvcc_fabs_q },
> { },
> };
>
> /* Convert compressed insns into normal insns via pseudo expansion.
> */
> -#define DECOMP(X) (static const rv_comp_data[1]){ { X, rvcc_true } }
> +#define DECOMP(X) (static const rv_comp_data[1]){ {
> &rvi_opcode_data[X], rvcc_true } }
>
> /* operand extractors */
>
> @@ -5270,9 +5272,8 @@ static const rv_opcode_data
> *decode_inst_lift_pseudo(rv_decode *dec,
> if (comp_data) {
> while (comp_data->constraints) {
> if (check_constraints(dec, comp_data->constraints)) {
> - const rv_opcode_data *new_op = &dec-
> >opcode_data[comp_data->op];
> - assert(new_op != op);
> - return decode_inst_lift_pseudo(dec, new_op);
> + assert(op != comp_data->op);
> + return decode_inst_lift_pseudo(dec, comp_data->op);
> }
> comp_data++;
> }
^ permalink raw reply [flat|nested] 119+ messages in thread
* Re: [PATCH 40/56] disas/riscv: Return rv_opcode_data pointer from decoders
2026-08-09 22:35 ` [PATCH 40/56] disas/riscv: Return rv_opcode_data pointer from decoders Richard Henderson
@ 2026-08-12 12:48 ` Alistair
0 siblings, 0 replies; 119+ messages in thread
From: Alistair @ 2026-08-12 12:48 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: qemu-riscv
On Sun, 2026-08-09 at 15:35 -0700, Richard Henderson wrote:
> Rather than putting array + index into rv_decode,
> return the pointer to the object directly.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> disas/riscv-xlrbr.h | 2 +-
> disas/riscv-xthead.h | 22 ++++++++---------
> disas/riscv-xventana.h | 2 +-
> disas/riscv.h | 2 --
> disas/riscv-xlrbr.c | 5 ++--
> disas/riscv-xthead.c | 55 +++++++++++++++++-----------------------
> --
> disas/riscv-xventana.c | 5 ++--
> disas/riscv.c | 23 +++++++-----------
> 8 files changed, 48 insertions(+), 68 deletions(-)
>
> diff --git a/disas/riscv-xlrbr.h b/disas/riscv-xlrbr.h
> index ebf3d4c133..da14f1b340 100644
> --- a/disas/riscv-xlrbr.h
> +++ b/disas/riscv-xlrbr.h
> @@ -12,6 +12,6 @@
>
> #include "disas/riscv.h"
>
> -void decode_xlrbr(rv_decode *, rv_isa);
> +const rv_opcode_data *decode_xlrbr(rv_decode *, rv_isa);
>
> #endif /* DISAS_RISCV_XLRBR_H */
> diff --git a/disas/riscv-xthead.h b/disas/riscv-xthead.h
> index 0c65c8e0af..f2160be8a4 100644
> --- a/disas/riscv-xthead.h
> +++ b/disas/riscv-xthead.h
> @@ -11,16 +11,16 @@
>
> #include "disas/riscv.h"
>
> -void decode_xtheadba(rv_decode *, rv_isa);
> -void decode_xtheadbb(rv_decode *, rv_isa);
> -void decode_xtheadbs(rv_decode *, rv_isa);
> -void decode_xtheadcmo(rv_decode *, rv_isa);
> -void decode_xtheadcondmov(rv_decode *, rv_isa);
> -void decode_xtheadfmemidx(rv_decode *, rv_isa);
> -void decode_xtheadfmv(rv_decode *, rv_isa);
> -void decode_xtheadmac(rv_decode *, rv_isa);
> -void decode_xtheadmemidx(rv_decode *, rv_isa);
> -void decode_xtheadmempair(rv_decode *, rv_isa);
> -void decode_xtheadsync(rv_decode *, rv_isa);
> +const rv_opcode_data *decode_xtheadba(rv_decode *, rv_isa);
> +const rv_opcode_data *decode_xtheadbb(rv_decode *, rv_isa);
> +const rv_opcode_data *decode_xtheadbs(rv_decode *, rv_isa);
> +const rv_opcode_data *decode_xtheadcmo(rv_decode *, rv_isa);
> +const rv_opcode_data *decode_xtheadcondmov(rv_decode *, rv_isa);
> +const rv_opcode_data *decode_xtheadfmemidx(rv_decode *, rv_isa);
> +const rv_opcode_data *decode_xtheadfmv(rv_decode *, rv_isa);
> +const rv_opcode_data *decode_xtheadmac(rv_decode *, rv_isa);
> +const rv_opcode_data *decode_xtheadmemidx(rv_decode *, rv_isa);
> +const rv_opcode_data *decode_xtheadmempair(rv_decode *, rv_isa);
> +const rv_opcode_data *decode_xtheadsync(rv_decode *, rv_isa);
>
> #endif /* DISAS_RISCV_XTHEAD_H */
> diff --git a/disas/riscv-xventana.h b/disas/riscv-xventana.h
> index 1006c3be00..d28e84c7e4 100644
> --- a/disas/riscv-xventana.h
> +++ b/disas/riscv-xventana.h
> @@ -11,6 +11,6 @@
>
> #include "disas/riscv.h"
>
> -void decode_xventanacondops(rv_decode*, rv_isa);
> +const rv_opcode_data *decode_xventanacondops(rv_decode*, rv_isa);
>
> #endif /* DISAS_RISCV_XVENTANA_H */
> diff --git a/disas/riscv.h b/disas/riscv.h
> index ab62c0db94..241dd47d7f 100644
> --- a/disas/riscv.h
> +++ b/disas/riscv.h
> @@ -182,10 +182,8 @@ typedef struct {
> const RISCVCPUConfig *cfg;
> uint64_t pc;
> uint64_t inst;
> - const rv_opcode_data *opcode_data;
> int32_t imm;
> int32_t imm1;
> - uint16_t op;
> uint8_t rd;
> uint8_t rs1;
> uint8_t rs2;
> diff --git a/disas/riscv-xlrbr.c b/disas/riscv-xlrbr.c
> index d0092e9edd..b12916c9da 100644
> --- a/disas/riscv-xlrbr.c
> +++ b/disas/riscv-xlrbr.c
> @@ -36,7 +36,7 @@ static const rv_opcode_data xlrbr_opcode_data[] = {
> { "crc32c.d", rv_codec_r, rv_fmt_rd_rs1 },
> };
>
> -void decode_xlrbr(rv_decode *dec, rv_isa isa)
> +const rv_opcode_data *decode_xlrbr(rv_decode *dec, rv_isa isa)
> {
> rv_inst inst = dec->inst;
> rv_opcode op = rv_op_illegal;
> @@ -76,6 +76,5 @@ void decode_xlrbr(rv_decode *dec, rv_isa isa)
> break;
> }
>
> - dec->opcode_data = xlrbr_opcode_data;
> - dec->op = op;
> + return op == rv_op_illegal ? NULL : &xlrbr_opcode_data[op];
> }
> diff --git a/disas/riscv-xthead.c b/disas/riscv-xthead.c
> index 757d6ff39f..428a6380e9 100644
> --- a/disas/riscv-xthead.c
> +++ b/disas/riscv-xthead.c
> @@ -246,7 +246,7 @@ static const rv_opcode_data xthead_opcode_data[]
> = {
> { "th.sync.s", rv_codec_none, rv_fmt_none },
> };
>
> -void decode_xtheadba(rv_decode *dec, rv_isa isa)
> +const rv_opcode_data *decode_xtheadba(rv_decode *dec, rv_isa isa)
> {
> rv_inst inst = dec->inst;
> rv_opcode op = rv_op_illegal;
> @@ -272,11 +272,10 @@ void decode_xtheadba(rv_decode *dec, rv_isa
> isa)
> break;
> }
>
> - dec->opcode_data = xthead_opcode_data;
> - dec->op = op;
> + return op == rv_op_illegal ? NULL : &xthead_opcode_data[op];
> }
>
> -void decode_xtheadbb(rv_decode *dec, rv_isa isa)
> +const rv_opcode_data *decode_xtheadbb(rv_decode *dec, rv_isa isa)
> {
> rv_inst inst = dec->inst;
> rv_opcode op = rv_op_illegal;
> @@ -331,11 +330,10 @@ void decode_xtheadbb(rv_decode *dec, rv_isa
> isa)
> break;
> }
>
> - dec->opcode_data = xthead_opcode_data;
> - dec->op = op;
> + return op == rv_op_illegal ? NULL : &xthead_opcode_data[op];
> }
>
> -void decode_xtheadbs(rv_decode *dec, rv_isa isa)
> +const rv_opcode_data *decode_xtheadbs(rv_decode *dec, rv_isa isa)
> {
> rv_inst inst = dec->inst;
> rv_opcode op = rv_op_illegal;
> @@ -358,11 +356,10 @@ void decode_xtheadbs(rv_decode *dec, rv_isa
> isa)
> break;
> }
>
> - dec->opcode_data = xthead_opcode_data;
> - dec->op = op;
> + return op == rv_op_illegal ? NULL : &xthead_opcode_data[op];
> }
>
> -void decode_xtheadcmo(rv_decode *dec, rv_isa isa)
> +const rv_opcode_data *decode_xtheadcmo(rv_decode *dec, rv_isa isa)
> {
> rv_inst inst = dec->inst;
> rv_opcode op = rv_op_illegal;
> @@ -437,11 +434,10 @@ void decode_xtheadcmo(rv_decode *dec, rv_isa
> isa)
> break;
> }
>
> - dec->opcode_data = xthead_opcode_data;
> - dec->op = op;
> + return op == rv_op_illegal ? NULL : &xthead_opcode_data[op];
> }
>
> -void decode_xtheadcondmov(rv_decode *dec, rv_isa isa)
> +const rv_opcode_data *decode_xtheadcondmov(rv_decode *dec, rv_isa
> isa)
> {
> rv_inst inst = dec->inst;
> rv_opcode op = rv_op_illegal;
> @@ -465,11 +461,10 @@ void decode_xtheadcondmov(rv_decode *dec,
> rv_isa isa)
> break;
> }
>
> - dec->opcode_data = xthead_opcode_data;
> - dec->op = op;
> + return op == rv_op_illegal ? NULL : &xthead_opcode_data[op];
> }
>
> -void decode_xtheadfmemidx(rv_decode *dec, rv_isa isa)
> +const rv_opcode_data *decode_xtheadfmemidx(rv_decode *dec, rv_isa
> isa)
> {
> rv_inst inst = dec->inst;
> rv_opcode op = rv_op_illegal;
> @@ -503,11 +498,10 @@ void decode_xtheadfmemidx(rv_decode *dec,
> rv_isa isa)
> break;
> }
>
> - dec->opcode_data = xthead_opcode_data;
> - dec->op = op;
> + return op == rv_op_illegal ? NULL : &xthead_opcode_data[op];
> }
>
> -void decode_xtheadfmv(rv_decode *dec, rv_isa isa)
> +const rv_opcode_data *decode_xtheadfmv(rv_decode *dec, rv_isa isa)
> {
> rv_inst inst = dec->inst;
> rv_opcode op = rv_op_illegal;
> @@ -539,11 +533,10 @@ void decode_xtheadfmv(rv_decode *dec, rv_isa
> isa)
> break;
> }
>
> - dec->opcode_data = xthead_opcode_data;
> - dec->op = op;
> + return op == rv_op_illegal ? NULL : &xthead_opcode_data[op];
> }
>
> -void decode_xtheadmac(rv_decode *dec, rv_isa isa)
> +const rv_opcode_data *decode_xtheadmac(rv_decode *dec, rv_isa isa)
> {
> rv_inst inst = dec->inst;
> rv_opcode op = rv_op_illegal;
> @@ -571,11 +564,10 @@ void decode_xtheadmac(rv_decode *dec, rv_isa
> isa)
> break;
> }
>
> - dec->opcode_data = xthead_opcode_data;
> - dec->op = op;
> + return op == rv_op_illegal ? NULL : &xthead_opcode_data[op];
> }
>
> -void decode_xtheadmemidx(rv_decode *dec, rv_isa isa)
> +const rv_opcode_data *decode_xtheadmemidx(rv_decode *dec, rv_isa
> isa)
> {
> rv_inst inst = dec->inst;
> rv_opcode op = rv_op_illegal;
> @@ -646,11 +638,10 @@ void decode_xtheadmemidx(rv_decode *dec, rv_isa
> isa)
> break;
> }
>
> - dec->opcode_data = xthead_opcode_data;
> - dec->op = op;
> + return op == rv_op_illegal ? NULL : &xthead_opcode_data[op];
> }
>
> -void decode_xtheadmempair(rv_decode *dec, rv_isa isa)
> +const rv_opcode_data *decode_xtheadmempair(rv_decode *dec, rv_isa
> isa)
> {
> rv_inst inst = dec->inst;
> rv_opcode op = rv_op_illegal;
> @@ -681,11 +672,10 @@ void decode_xtheadmempair(rv_decode *dec,
> rv_isa isa)
> break;
> }
>
> - dec->opcode_data = xthead_opcode_data;
> - dec->op = op;
> + return op == rv_op_illegal ? NULL : &xthead_opcode_data[op];
> }
>
> -void decode_xtheadsync(rv_decode *dec, rv_isa isa)
> +const rv_opcode_data *decode_xtheadsync(rv_decode *dec, rv_isa isa)
> {
> rv_inst inst = dec->inst;
> rv_opcode op = rv_op_illegal;
> @@ -716,6 +706,5 @@ void decode_xtheadsync(rv_decode *dec, rv_isa
> isa)
> break;
> }
>
> - dec->opcode_data = xthead_opcode_data;
> - dec->op = op;
> + return op == rv_op_illegal ? NULL : &xthead_opcode_data[op];
> }
> diff --git a/disas/riscv-xventana.c b/disas/riscv-xventana.c
> index 4fb9a29d0b..a4e59312d0 100644
> --- a/disas/riscv-xventana.c
> +++ b/disas/riscv-xventana.c
> @@ -20,7 +20,7 @@ static const rv_opcode_data ventana_opcode_data[] =
> {
> { "vt.maskcn", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> };
>
> -void decode_xventanacondops(rv_decode *dec, rv_isa isa)
> +const rv_opcode_data *decode_xventanacondops(rv_decode *dec, rv_isa
> isa)
> {
> rv_inst inst = dec->inst;
> rv_opcode op = rv_op_illegal;
> @@ -38,6 +38,5 @@ void decode_xventanacondops(rv_decode *dec, rv_isa
> isa)
> break;
> }
>
> - dec->opcode_data = ventana_opcode_data;
> - dec->op = op;
> + return op == rv_op_illegal ? NULL : &ventana_opcode_data[op];
> }
> diff --git a/disas/riscv.c b/disas/riscv.c
> index 171c60238f..c4b8ee7d07 100644
> --- a/disas/riscv.c
> +++ b/disas/riscv.c
> @@ -2846,7 +2846,7 @@ static const char *csr_name(int csrno)
>
> /* decode opcode */
>
> -static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
> +static const rv_opcode_data *decode_inst_opcode(rv_decode *dec,
> rv_isa isa)
> {
> rv_inst inst = dec->inst;
> rv_opcode op = rv_op_illegal;
> @@ -4541,8 +4541,7 @@ static void decode_inst_opcode(rv_decode *dec,
> rv_isa isa)
> break;
> }
>
> - dec->opcode_data = rvi_opcode_data;
> - dec->op = op;
> + return op == rv_op_illegal ? NULL : &rvi_opcode_data[op];
> }
>
> /* decode operands */
> @@ -5291,14 +5290,12 @@ static GString *disasm_inst(rv_isa isa,
> uint64_t pc, rv_inst inst,
> .inst = inst,
> .cfg = cfg,
> };
> - const rv_opcode_data *op;
> + const rv_opcode_data *op = decode_inst_opcode(&dec, isa);
>
> - decode_inst_opcode(&dec, isa);
> -
> - if (dec.op == rv_op_illegal && cfg) {
> + if (!op && cfg) {
> static const struct {
> bool (*guard_func)(const RISCVCPUConfig *);
> - void (*decode_func)(rv_decode *, rv_isa);
> + const rv_opcode_data *(*decode_func)(rv_decode *,
> rv_isa);
> } decoders[] = {
> { has_xtheadba_p, decode_xtheadba },
> { has_xtheadbb_p, decode_xtheadbb },
> @@ -5317,19 +5314,17 @@ static GString *disasm_inst(rv_isa isa,
> uint64_t pc, rv_inst inst,
>
> for (size_t i = 0; i < ARRAY_SIZE(decoders); i++) {
> if (decoders[i].guard_func(cfg)) {
> - decoders[i].decode_func(&dec, isa);
> - if (dec.op != rv_op_illegal) {
> + op = decoders[i].decode_func(&dec, isa);
> + if (op) {
> break;
> }
> }
> }
> }
> -
> - if (dec.op == rv_op_illegal) {
> - dec.opcode_data = rvi_opcode_data;
> + if (!op) {
> + op = &rvi_opcode_data[rv_op_illegal];
> }
>
> - op = &dec.opcode_data[dec.op];
> decode_inst_operands(&dec, isa, op);
> op = decode_inst_lift_pseudo(&dec, op);
> return format_inst(24, &dec, op);
^ permalink raw reply [flat|nested] 119+ messages in thread
* Re: [PATCH 41/56] disas/riscv: Reject all of OP-32 and OP-IMM-32 for RV32
2026-08-09 22:35 ` [PATCH 41/56] disas/riscv: Reject all of OP-32 and OP-IMM-32 for RV32 Richard Henderson
@ 2026-08-12 12:49 ` Alistair
0 siblings, 0 replies; 119+ messages in thread
From: Alistair @ 2026-08-12 12:49 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: qemu-riscv
On Sun, 2026-08-09 at 15:35 -0700, Richard Henderson wrote:
> These entire base opcodes are RV64. Reject them all at once
> rather than one at a time.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> disas/riscv.c | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/disas/riscv.c b/disas/riscv.c
> index c4b8ee7d07..f51d45674e 100644
> --- a/disas/riscv.c
> +++ b/disas/riscv.c
> @@ -3311,6 +3311,10 @@ static const rv_opcode_data
> *decode_inst_opcode(rv_decode *dec, rv_isa isa)
> }
> break;
> case 6:
> + /* OP-IMM-32 */
> + if (isa == rv32) {
> + break;
> + }
> switch ((inst >> 12) & 0b111) {
> case 0: op = rv_op_addiw; break;
> case 1:
> @@ -3557,6 +3561,10 @@ static const rv_opcode_data
> *decode_inst_opcode(rv_decode *dec, rv_isa isa)
> break;
> case 13: op = rv_op_lui; break;
> case 14:
> + /* OP-32 */
> + if (isa == rv32) {
> + break;
> + }
> switch (((inst >> 22) & 0b1111111000) |
> ((inst >> 12) & 0b0000000111)) {
> case 0: op = rv_op_addw; break;
^ permalink raw reply [flat|nested] 119+ messages in thread
* Re: [PATCH 42/56] disas/riscv: Fix rv32 encoding of zext.h
2026-08-09 22:35 ` [PATCH 42/56] disas/riscv: Fix rv32 encoding of zext.h Richard Henderson
@ 2026-08-12 12:49 ` Alistair
0 siblings, 0 replies; 119+ messages in thread
From: Alistair @ 2026-08-12 12:49 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: qemu-riscv, qemu-stable
On Sun, 2026-08-09 at 15:35 -0700, Richard Henderson wrote:
> For rv64, pack with rs2 = 0 does not encode zext.h.
>
> Cc: qemu-stable@nongnu.org
> Fixes: 02c1b569a15 ("disas/riscv: Add Zb[abcs] instructions")
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> disas/riscv.c | 7 ++++---
> 1 file changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/disas/riscv.c b/disas/riscv.c
> index f51d45674e..9442a6c115 100644
> --- a/disas/riscv.c
> +++ b/disas/riscv.c
> @@ -3506,9 +3506,10 @@ static const rv_opcode_data
> *decode_inst_opcode(rv_decode *dec, rv_isa isa)
> case 14: op = rv_op_rem; break;
> case 15: op = rv_op_remu; break;
> case 36:
> - switch ((inst >> 20) & 0b11111) {
> - case 0: op = rv_op_zext_h; break;
> - default: op = rv_op_pack; break;
> + if (isa == rv32 && !((inst >> 20) & 0b11111)) {
> + op = rv_op_zext_h;
> + } else {
> + op = rv_op_pack;
> }
> break;
> case 39: op = rv_op_packh; break;
^ permalink raw reply [flat|nested] 119+ messages in thread
* Re: [PATCH 43/56] disas/riscv: Fix isa decoding of rev8
2026-08-09 22:35 ` [PATCH 43/56] disas/riscv: Fix isa decoding of rev8 Richard Henderson
@ 2026-08-12 12:50 ` Alistair
0 siblings, 0 replies; 119+ messages in thread
From: Alistair @ 2026-08-12 12:50 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: qemu-riscv, qemu-stable
On Sun, 2026-08-09 at 15:35 -0700, Richard Henderson wrote:
> The encoding of rev8 is different for rv32 and rv64.
>
> Cc: qemu-stable@nongnu.org
> Fixes: 02c1b569a15 ("disas/riscv: Add Zb[abcs] instructions")
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> disas/riscv.c | 12 ++++++++++--
> 1 file changed, 10 insertions(+), 2 deletions(-)
>
> diff --git a/disas/riscv.c b/disas/riscv.c
> index 9442a6c115..4141741d79 100644
> --- a/disas/riscv.c
> +++ b/disas/riscv.c
> @@ -3292,8 +3292,16 @@ static const rv_opcode_data
> *decode_inst_opcode(rv_decode *dec, rv_isa isa)
> case 0b01100: op = rv_op_rori; break;
> case 0b01101:
> switch ((inst >> 20) & 0b1111111) {
> - case 0b0011000: op = rv_op_rev8; break;
> - case 0b0111000: op = rv_op_rev8; break;
> + case 0b0011000:
> + if (isa == rv32) {
> + op = rv_op_rev8;
> + }
> + break;
> + case 0b0111000:
> + if (isa == rv64) {
> + op = rv_op_rev8;
> + }
> + break;
> case 0b0000111: op = rv_op_brev8; break;
> }
> break;
^ permalink raw reply [flat|nested] 119+ messages in thread
* Re: [PATCH 44/56] disas/riscv: Fix typo in th.lbib format
2026-08-09 22:35 ` [PATCH 44/56] disas/riscv: Fix typo in th.lbib format Richard Henderson
@ 2026-08-12 12:50 ` Alistair
0 siblings, 0 replies; 119+ messages in thread
From: Alistair @ 2026-08-12 12:50 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: qemu-riscv, qemu-stable
On Sun, 2026-08-09 at 15:35 -0700, Richard Henderson wrote:
> th.lbib should format the same as th.lbia, and the other
> increment insns, with the address register in parenthesis.
>
> Cc: qemu-stable@nongnu.org
> Fixes: 318df7238b9 ("disas/riscv: Add support for XThead*
> instructions")
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> disas/riscv-xthead.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/disas/riscv-xthead.c b/disas/riscv-xthead.c
> index 428a6380e9..fbc96631fd 100644
> --- a/disas/riscv-xthead.c
> +++ b/disas/riscv-xthead.c
> @@ -189,7 +189,7 @@ static const rv_opcode_data xthead_opcode_data[]
> = {
> { "th.mulsh", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> /* XTheadMemIdx */
> { "th.lbia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr
> },
> - { "th.lbib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml },
> + { "th.lbib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr
> },
> { "th.lbuia", rv_codec_r2_imm2_imm5,
> rv_fmt_rd_rs1_immh_imml_addr },
> { "th.lbuib", rv_codec_r2_imm2_imm5,
> rv_fmt_rd_rs1_immh_imml_addr },
> { "th.lhia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr
> },
^ permalink raw reply [flat|nested] 119+ messages in thread
* Re: [PATCH 45/56] disas/riscv: Split ventana_opcode_data
2026-08-09 22:35 ` [PATCH 45/56] disas/riscv: Split ventana_opcode_data Richard Henderson
@ 2026-08-12 12:51 ` Alistair
0 siblings, 0 replies; 119+ messages in thread
From: Alistair @ 2026-08-12 12:51 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: qemu-riscv
On Sun, 2026-08-09 at 15:35 -0700, Richard Henderson wrote:
> Move the table to riscv-xventana-op.c.inc and massage
> the lines into OP() form. Drop vt.illegal as unused.
> Return pointers to objects directly.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> disas/riscv-xventana.c | 21 ++++++---------------
> disas/riscv-xventana-op.c.inc | 2 ++
> 2 files changed, 8 insertions(+), 15 deletions(-)
> create mode 100644 disas/riscv-xventana-op.c.inc
>
> diff --git a/disas/riscv-xventana.c b/disas/riscv-xventana.c
> index a4e59312d0..5d2e07865f 100644
> --- a/disas/riscv-xventana.c
> +++ b/disas/riscv-xventana.c
> @@ -8,35 +8,26 @@
> #include "disas/riscv.h"
> #include "disas/riscv-xventana.h"
>
> -typedef enum {
> - /* 0 is reserved for rv_op_illegal. */
> - ventana_op_vt_maskc = 1,
> - ventana_op_vt_maskcn = 2,
> -} rv_ventana_op;
> -
> -static const rv_opcode_data ventana_opcode_data[] = {
> - { "vt.illegal", rv_codec_illegal, rv_fmt_none },
> - { "vt.maskc", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> - { "vt.maskcn", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> -};
> +#define OP(N, ...) static const rv_opcode_data op_##N = {
> __VA_ARGS__ };
> +#include "riscv-xventana-op.c.inc"
> +#undef OP
>
> const rv_opcode_data *decode_xventanacondops(rv_decode *dec, rv_isa
> isa)
> {
> rv_inst inst = dec->inst;
> - rv_opcode op = rv_op_illegal;
>
> switch (((inst >> 0) & 0b11)) {
> case 3:
> switch (((inst >> 2) & 0b11111)) {
> case 30:
> switch (((inst >> 22) & 0b1111111000) | ((inst >> 12) &
> 0b0000000111)) {
> - case 6: op = ventana_op_vt_maskc; break;
> - case 7: op = ventana_op_vt_maskcn; break;
> + case 6: return &op_vt_maskc;
> + case 7: return &op_vt_maskcn;
> }
> break;
> }
> break;
> }
>
> - return op == rv_op_illegal ? NULL : &ventana_opcode_data[op];
> + return NULL;
> }
> diff --git a/disas/riscv-xventana-op.c.inc b/disas/riscv-xventana-
> op.c.inc
> new file mode 100644
> index 0000000000..0fe4666aee
> --- /dev/null
> +++ b/disas/riscv-xventana-op.c.inc
> @@ -0,0 +1,2 @@
> +OP(vt_maskc, "vt.maskc", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(vt_maskcn, "vt.maskcn", rv_codec_r, rv_fmt_rd_rs1_rs2)
^ permalink raw reply [flat|nested] 119+ messages in thread
* Re: [PATCH 46/56] disas/riscv: Split xlrbr_opcode_data
2026-08-09 22:35 ` [PATCH 46/56] disas/riscv: Split xlrbr_opcode_data Richard Henderson
@ 2026-08-12 12:52 ` Alistair
0 siblings, 0 replies; 119+ messages in thread
From: Alistair @ 2026-08-12 12:52 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: qemu-riscv
On Sun, 2026-08-09 at 15:35 -0700, Richard Henderson wrote:
> Move the table to riscv-xlrbr-op.c.inc and massage
> the lines into OP() form. Drop illegal as unused.
> Return pointers to objects directly.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> disas/riscv-xlrbr.c | 54 +++++++++---------------------------
> --
> disas/riscv-xlrbr-op.c.inc | 8 ++++++
> 2 files changed, 20 insertions(+), 42 deletions(-)
> create mode 100644 disas/riscv-xlrbr-op.c.inc
>
> diff --git a/disas/riscv-xlrbr.c b/disas/riscv-xlrbr.c
> index b12916c9da..b4229e5c83 100644
> --- a/disas/riscv-xlrbr.c
> +++ b/disas/riscv-xlrbr.c
> @@ -8,38 +8,16 @@
> */
>
> #include "qemu/osdep.h"
> -
> #include "disas/riscv.h"
> #include "disas/riscv-xlrbr.h"
>
> -typedef enum {
> - /* 0 is reserved for rv_op_illegal. */
> - rv_op_crc32_b = 1,
> - rv_op_crc32_h = 2,
> - rv_op_crc32_w = 3,
> - rv_op_crc32_d = 4,
> - rv_op_crc32c_b = 5,
> - rv_op_crc32c_h = 6,
> - rv_op_crc32c_w = 7,
> - rv_op_crc32c_d = 8,
> -} rv_xlrbr_op;
> -
> -static const rv_opcode_data xlrbr_opcode_data[] = {
> - { "illegal", rv_codec_illegal, rv_fmt_none },
> - { "crc32.b", rv_codec_r, rv_fmt_rd_rs1 },
> - { "crc32.h", rv_codec_r, rv_fmt_rd_rs1 },
> - { "crc32.w", rv_codec_r, rv_fmt_rd_rs1 },
> - { "crc32.d", rv_codec_r, rv_fmt_rd_rs1 },
> - { "crc32c.b", rv_codec_r, rv_fmt_rd_rs1 },
> - { "crc32c.h", rv_codec_r, rv_fmt_rd_rs1 },
> - { "crc32c.w", rv_codec_r, rv_fmt_rd_rs1 },
> - { "crc32c.d", rv_codec_r, rv_fmt_rd_rs1 },
> -};
> +#define OP(N, ...) static const rv_opcode_data op_##N = {
> __VA_ARGS__ };
> +#include "riscv-xlrbr-op.c.inc"
> +#undef OP
>
> const rv_opcode_data *decode_xlrbr(rv_decode *dec, rv_isa isa)
> {
> rv_inst inst = dec->inst;
> - rv_opcode op = rv_op_illegal;
>
> switch ((inst >> 0) & 0b1111111) {
> case 0b0010011:
> @@ -47,34 +25,26 @@ const rv_opcode_data *decode_xlrbr(rv_decode
> *dec, rv_isa isa)
> case 0b001:
> switch ((inst >> 20 & 0b111111111111)) {
> case 0b011000010000:
> - op = rv_op_crc32_b;
> - break;
> + return &op_crc32_b;
> case 0b011000010001:
> - op = rv_op_crc32_h;
> - break;
> + return &op_crc32_h;
> case 0b011000010010:
> - op = rv_op_crc32_w;
> - break;
> + return &op_crc32_w;
> case 0b011000010011:
> - op = rv_op_crc32_d;
> - break;
> + return &op_crc32_d;
> case 0b011000011000:
> - op = rv_op_crc32c_b;
> - break;
> + return &op_crc32c_b;
> case 0b011000011001:
> - op = rv_op_crc32c_h;
> - break;
> + return &op_crc32c_h;
> case 0b011000011010:
> - op = rv_op_crc32c_w;
> - break;
> + return &op_crc32c_w;
> case 0b011000011011:
> - op = rv_op_crc32c_d;
> - break;
> + return &op_crc32c_d;
> }
> break;
> }
> break;
> }
>
> - return op == rv_op_illegal ? NULL : &xlrbr_opcode_data[op];
> + return NULL;
> }
> diff --git a/disas/riscv-xlrbr-op.c.inc b/disas/riscv-xlrbr-op.c.inc
> new file mode 100644
> index 0000000000..57add37c24
> --- /dev/null
> +++ b/disas/riscv-xlrbr-op.c.inc
> @@ -0,0 +1,8 @@
> +OP(crc32_b, "crc32.b", rv_codec_r, rv_fmt_rd_rs1)
> +OP(crc32_h, "crc32.h", rv_codec_r, rv_fmt_rd_rs1)
> +OP(crc32_w, "crc32.w", rv_codec_r, rv_fmt_rd_rs1)
> +OP(crc32_d, "crc32.d", rv_codec_r, rv_fmt_rd_rs1)
> +OP(crc32c_b, "crc32c.b", rv_codec_r, rv_fmt_rd_rs1)
> +OP(crc32c_h, "crc32c.h", rv_codec_r, rv_fmt_rd_rs1)
> +OP(crc32c_w, "crc32c.w", rv_codec_r, rv_fmt_rd_rs1)
> +OP(crc32c_d, "crc32c.d", rv_codec_r, rv_fmt_rd_rs1)
^ permalink raw reply [flat|nested] 119+ messages in thread
* Re: [PATCH 47/56] disas/riscv: Split xthead_opcode_data
2026-08-09 22:35 ` [PATCH 47/56] disas/riscv: Split xthead_opcode_data Richard Henderson
@ 2026-08-12 12:53 ` Alistair
0 siblings, 0 replies; 119+ messages in thread
From: Alistair @ 2026-08-12 12:53 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: qemu-riscv
On Sun, 2026-08-09 at 15:35 -0700, Richard Henderson wrote:
> Move the table to riscv-xthead-op.c.inc and massage
> the lines into OP() form. Drop th.illegal as unused.
> Return pointers to objects directly.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> disas/riscv-xthead.c | 481 +++++++++-------------------------
> --
> disas/riscv-xthead-op.c.inc | 125 ++++++++++
> 2 files changed, 243 insertions(+), 363 deletions(-)
> create mode 100644 disas/riscv-xthead-op.c.inc
>
> diff --git a/disas/riscv-xthead.c b/disas/riscv-xthead.c
> index fbc96631fd..387c22c869 100644
> --- a/disas/riscv-xthead.c
> +++ b/disas/riscv-xthead.c
> @@ -8,248 +8,13 @@
> #include "disas/riscv.h"
> #include "disas/riscv-xthead.h"
>
> -typedef enum {
> - /* 0 is reserved for rv_op_illegal. */
> - /* XTheadBa */
> - rv_op_th_addsl = 1,
> - /* XTheadBb */
> - rv_op_th_srri,
> - rv_op_th_srriw,
> - rv_op_th_ext,
> - rv_op_th_extu,
> - rv_op_th_ff0,
> - rv_op_th_ff1,
> - rv_op_th_rev,
> - rv_op_th_revw,
> - rv_op_th_tstnbz,
> - /* XTheadBs */
> - rv_op_th_tst,
> - /* XTheadCmo */
> - rv_op_th_dcache_call,
> - rv_op_th_dcache_ciall,
> - rv_op_th_dcache_iall,
> - rv_op_th_dcache_cpa,
> - rv_op_th_dcache_cipa,
> - rv_op_th_dcache_ipa,
> - rv_op_th_dcache_cva,
> - rv_op_th_dcache_civa,
> - rv_op_th_dcache_iva,
> - rv_op_th_dcache_csw,
> - rv_op_th_dcache_cisw,
> - rv_op_th_dcache_isw,
> - rv_op_th_dcache_cpal1,
> - rv_op_th_dcache_cval1,
> - rv_op_th_icache_iall,
> - rv_op_th_icache_ialls,
> - rv_op_th_icache_ipa,
> - rv_op_th_icache_iva,
> - rv_op_th_l2cache_call,
> - rv_op_th_l2cache_ciall,
> - rv_op_th_l2cache_iall,
> - /* XTheadCondMov */
> - rv_op_th_mveqz,
> - rv_op_th_mvnez,
> - /* XTheadFMemIdx */
> - rv_op_th_flrd,
> - rv_op_th_flrw,
> - rv_op_th_flurd,
> - rv_op_th_flurw,
> - rv_op_th_fsrd,
> - rv_op_th_fsrw,
> - rv_op_th_fsurd,
> - rv_op_th_fsurw,
> - /* XTheadFmv */
> - rv_op_th_fmv_hw_x,
> - rv_op_th_fmv_x_hw,
> - /* XTheadMac */
> - rv_op_th_mula,
> - rv_op_th_mulah,
> - rv_op_th_mulaw,
> - rv_op_th_muls,
> - rv_op_th_mulsw,
> - rv_op_th_mulsh,
> - /* XTheadMemIdx */
> - rv_op_th_lbia,
> - rv_op_th_lbib,
> - rv_op_th_lbuia,
> - rv_op_th_lbuib,
> - rv_op_th_lhia,
> - rv_op_th_lhib,
> - rv_op_th_lhuia,
> - rv_op_th_lhuib,
> - rv_op_th_lwia,
> - rv_op_th_lwib,
> - rv_op_th_lwuia,
> - rv_op_th_lwuib,
> - rv_op_th_ldia,
> - rv_op_th_ldib,
> - rv_op_th_sbia,
> - rv_op_th_sbib,
> - rv_op_th_shia,
> - rv_op_th_shib,
> - rv_op_th_swia,
> - rv_op_th_swib,
> - rv_op_th_sdia,
> - rv_op_th_sdib,
> - rv_op_th_lrb,
> - rv_op_th_lrbu,
> - rv_op_th_lrh,
> - rv_op_th_lrhu,
> - rv_op_th_lrw,
> - rv_op_th_lrwu,
> - rv_op_th_lrd,
> - rv_op_th_srb,
> - rv_op_th_srh,
> - rv_op_th_srw,
> - rv_op_th_srd,
> - rv_op_th_lurb,
> - rv_op_th_lurbu,
> - rv_op_th_lurh,
> - rv_op_th_lurhu,
> - rv_op_th_lurw,
> - rv_op_th_lurwu,
> - rv_op_th_lurd,
> - rv_op_th_surb,
> - rv_op_th_surh,
> - rv_op_th_surw,
> - rv_op_th_surd,
> - /* XTheadMemPair */
> - rv_op_th_ldd,
> - rv_op_th_lwd,
> - rv_op_th_lwud,
> - rv_op_th_sdd,
> - rv_op_th_swd,
> - /* XTheadSync */
> - rv_op_th_sfence_vmas,
> - rv_op_th_sync,
> - rv_op_th_sync_i,
> - rv_op_th_sync_is,
> - rv_op_th_sync_s,
> -} rv_xthead_op;
> -
> -static const rv_opcode_data xthead_opcode_data[] = {
> - { "th.illegal", rv_codec_illegal, rv_fmt_none },
> - /* XTheadBa */
> - { "th.addsl", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm },
> - /* XTheadBb */
> - { "th.srri", rv_codec_r2_imm6, rv_fmt_rd_rs1_imm },
> - { "th.srriw", rv_codec_r2_imm5, rv_fmt_rd_rs1_imm },
> - { "th.ext", rv_codec_r2_immhl, rv_fmt_rd_rs1_immh_imml },
> - { "th.extu", rv_codec_r2_immhl, rv_fmt_rd_rs1_immh_imml },
> - { "th.ff0", rv_codec_r2, rv_fmt_rd_rs1 },
> - { "th.ff1", rv_codec_r2, rv_fmt_rd_rs1 },
> - { "th.rev", rv_codec_r2, rv_fmt_rd_rs1 },
> - { "th.revw", rv_codec_r2, rv_fmt_rd_rs1 },
> - { "th.tstnbz", rv_codec_r2, rv_fmt_rd_rs1 },
> - /* XTheadBs */
> - { "th.tst", rv_codec_r2_imm6, rv_fmt_rd_rs1_imm },
> - /* XTheadCmo */
> - { "th.dcache.call", rv_codec_none, rv_fmt_none },
> - { "th.dcache.ciall", rv_codec_none, rv_fmt_none },
> - { "th.dcache.iall", rv_codec_none, rv_fmt_none },
> - { "th.dcache.cpa", rv_codec_r, rv_fmt_rs1 },
> - { "th.dcache.cipa", rv_codec_r, rv_fmt_rs1 },
> - { "th.dcache.ipa", rv_codec_r, rv_fmt_rs1 },
> - { "th.dcache.cva", rv_codec_r, rv_fmt_rs1 },
> - { "th.dcache.civa", rv_codec_r, rv_fmt_rs1 },
> - { "th.dcache.iva", rv_codec_r, rv_fmt_rs1 },
> - { "th.dcache.csw", rv_codec_r, rv_fmt_rs1 },
> - { "th.dcache.cisw", rv_codec_r, rv_fmt_rs1 },
> - { "th.dcache.isw", rv_codec_r, rv_fmt_rs1 },
> - { "th.dcache.cpal1", rv_codec_r, rv_fmt_rs1 },
> - { "th.dcache.cval1", rv_codec_r, rv_fmt_rs1 },
> - { "th.icache.iall", rv_codec_none, rv_fmt_none },
> - { "th.icache.ialls", rv_codec_none, rv_fmt_none },
> - { "th.icache.ipa", rv_codec_r, rv_fmt_rs1 },
> - { "th.icache.iva", rv_codec_r, rv_fmt_rs1 },
> - { "th.l2cache.call", rv_codec_none, rv_fmt_none },
> - { "th.l2cache.ciall", rv_codec_none, rv_fmt_none },
> - { "th.l2cache.iall", rv_codec_none, rv_fmt_none },
> - /* XTheadCondMov */
> - { "th.mveqz", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> - { "th.mvnez", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> - /* XTheadFMemIdx */
> - { "th.flrd", rv_codec_r_imm2, rv_fmt_frd_rs1_rs2_imm },
> - { "th.flrw", rv_codec_r_imm2, rv_fmt_frd_rs1_rs2_imm },
> - { "th.flurd", rv_codec_r_imm2, rv_fmt_frd_rs1_rs2_imm },
> - { "th.flurw", rv_codec_r_imm2, rv_fmt_frd_rs1_rs2_imm },
> - { "th.fsrd", rv_codec_r_imm2, rv_fmt_frd_rs1_rs2_imm },
> - { "th.fsrw", rv_codec_r_imm2, rv_fmt_frd_rs1_rs2_imm },
> - { "th.fsurd", rv_codec_r_imm2, rv_fmt_frd_rs1_rs2_imm },
> - { "th.fsurw", rv_codec_r_imm2, rv_fmt_frd_rs1_rs2_imm },
> - /* XTheadFmv */
> - { "th.fmv.hw.x", rv_codec_r, rv_fmt_rd_frs1 },
> - { "th.fmv.x.hw", rv_codec_r, rv_fmt_rd_frs1 },
> - /* XTheadMac */
> - { "th.mula", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> - { "th.mulaw", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> - { "th.mulah", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> - { "th.muls", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> - { "th.mulsw", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> - { "th.mulsh", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> - /* XTheadMemIdx */
> - { "th.lbia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr
> },
> - { "th.lbib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr
> },
> - { "th.lbuia", rv_codec_r2_imm2_imm5,
> rv_fmt_rd_rs1_immh_imml_addr },
> - { "th.lbuib", rv_codec_r2_imm2_imm5,
> rv_fmt_rd_rs1_immh_imml_addr },
> - { "th.lhia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr
> },
> - { "th.lhib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr
> },
> - { "th.lhuia", rv_codec_r2_imm2_imm5,
> rv_fmt_rd_rs1_immh_imml_addr },
> - { "th.lhuib", rv_codec_r2_imm2_imm5,
> rv_fmt_rd_rs1_immh_imml_addr },
> - { "th.lwia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr
> },
> - { "th.lwib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr
> },
> - { "th.lwuia", rv_codec_r2_imm2_imm5,
> rv_fmt_rd_rs1_immh_imml_addr },
> - { "th.lwuib", rv_codec_r2_imm2_imm5,
> rv_fmt_rd_rs1_immh_imml_addr },
> - { "th.ldia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr
> },
> - { "th.ldib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr
> },
> - { "th.sbia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr
> },
> - { "th.sbib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr
> },
> - { "th.shia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr
> },
> - { "th.shib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr
> },
> - { "th.swia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr
> },
> - { "th.swib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr
> },
> - { "th.sdia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr
> },
> - { "th.sdib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr
> },
> - { "th.lrb", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm },
> - { "th.lrbu", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm },
> - { "th.lrh", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm },
> - { "th.lrhu", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm },
> - { "th.lrw", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm },
> - { "th.lrwu", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm },
> - { "th.lrd", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm },
> - { "th.srb", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm },
> - { "th.srh", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm },
> - { "th.srw", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm },
> - { "th.srd", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm },
> - { "th.lurb", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm },
> - { "th.lurbu", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm },
> - { "th.lurh", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm },
> - { "th.lurhu", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm },
> - { "th.lurw", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm },
> - { "th.lurwu", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm },
> - { "th.lurd", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm },
> - { "th.surb", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm },
> - { "th.surh", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm },
> - { "th.surw", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm },
> - { "th.surd", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm },
> - /* XTheadMemPair */
> - { "th.ldd", rv_codec_r_imm2, rv_fmt_rd2_imm },
> - { "th.lwd", rv_codec_r_imm2, rv_fmt_rd2_imm },
> - { "th.lwud", rv_codec_r_imm2, rv_fmt_rd2_imm },
> - { "th.sdd", rv_codec_r_imm2, rv_fmt_rd2_imm },
> - { "th.swd", rv_codec_r_imm2, rv_fmt_rd2_imm },
> - /* XTheadSync */
> - { "th.sfence.vmas", rv_codec_r, rv_fmt_rs1_rs2 },
> - { "th.sync", rv_codec_none, rv_fmt_none },
> - { "th.sync.i", rv_codec_none, rv_fmt_none },
> - { "th.sync.is", rv_codec_none, rv_fmt_none },
> - { "th.sync.s", rv_codec_none, rv_fmt_none },
> -};
> +#define OP(N, ...) static const rv_opcode_data op_##N = {
> __VA_ARGS__ };
> +#include "riscv-xthead-op.c.inc"
> +#undef OP
>
> const rv_opcode_data *decode_xtheadba(rv_decode *dec, rv_isa isa)
> {
> rv_inst inst = dec->inst;
> - rv_opcode op = rv_op_illegal;
>
> switch (((inst >> 0) & 0b11)) {
> case 3:
> @@ -262,7 +27,7 @@ const rv_opcode_data *decode_xtheadba(rv_decode
> *dec, rv_isa isa)
> case 0b0000000:
> case 0b0000001:
> case 0b0000010:
> - case 0b0000011: op = rv_op_th_addsl; break;
> + case 0b0000011: return &op_th_addsl;
> }
> break;
> }
> @@ -272,13 +37,12 @@ const rv_opcode_data *decode_xtheadba(rv_decode
> *dec, rv_isa isa)
> break;
> }
>
> - return op == rv_op_illegal ? NULL : &xthead_opcode_data[op];
> + return NULL;
> }
>
> const rv_opcode_data *decode_xtheadbb(rv_decode *dec, rv_isa isa)
> {
> rv_inst inst = dec->inst;
> - rv_opcode op = rv_op_illegal;
>
> switch (((inst >> 0) & 0b11)) {
> case 3:
> @@ -288,41 +52,41 @@ const rv_opcode_data *decode_xtheadbb(rv_decode
> *dec, rv_isa isa)
> switch ((inst >> 12) & 0b111) {
> case 1:
> switch ((inst >> 25) & 0b1111111) {
> - case 0b0001010: op = rv_op_th_srriw; break;
> + case 0b0001010: return &op_th_srriw;
> case 0b1000000:
> if (((inst >> 20) & 0b11111) == 0) {
> - op = rv_op_th_tstnbz;
> + return &op_th_tstnbz;
> }
> break;
> case 0b1000001:
> if (((inst >> 20) & 0b11111) == 0) {
> - op = rv_op_th_rev;
> + return &op_th_rev;
> }
> break;
> case 0b1000010:
> if (((inst >> 20) & 0b11111) == 0) {
> - op = rv_op_th_ff0;
> + return &op_th_ff0;
> }
> break;
> case 0b1000011:
> if (((inst >> 20) & 0b11111) == 0) {
> - op = rv_op_th_ff1;
> + return &op_th_ff1;
> }
> break;
> case 0b1000100:
> case 0b1001000:
> if (((inst >> 20) & 0b11111) == 0) {
> - op = rv_op_th_revw;
> + return &op_th_revw;
> }
> break;
> case 0b0001000:
> case 0b0001001:
> - op = rv_op_th_srri;
> + return &op_th_srri;
> break;
> }
> break;
> - case 2: op = rv_op_th_ext; break;
> - case 3: op = rv_op_th_extu; break;
> + case 2: return &op_th_ext;
> + case 3: return &op_th_extu;
> }
> break;
> /* custom-0 */
> @@ -330,13 +94,12 @@ const rv_opcode_data *decode_xtheadbb(rv_decode
> *dec, rv_isa isa)
> break;
> }
>
> - return op == rv_op_illegal ? NULL : &xthead_opcode_data[op];
> + return NULL;
> }
>
> const rv_opcode_data *decode_xtheadbs(rv_decode *dec, rv_isa isa)
> {
> rv_inst inst = dec->inst;
> - rv_opcode op = rv_op_illegal;
>
> switch (((inst >> 0) & 0b11)) {
> case 3:
> @@ -346,7 +109,7 @@ const rv_opcode_data *decode_xtheadbs(rv_decode
> *dec, rv_isa isa)
> switch ((inst >> 12) & 0b111) {
> case 1:
> switch ((inst >> 26) & 0b111111) {
> - case 0b100010: op = rv_op_th_tst; break;
> + case 0b100010: return &op_th_tst;
> }
> break;
> }
> @@ -356,13 +119,12 @@ const rv_opcode_data *decode_xtheadbs(rv_decode
> *dec, rv_isa isa)
> break;
> }
>
> - return op == rv_op_illegal ? NULL : &xthead_opcode_data[op];
> + return NULL;
> }
>
> const rv_opcode_data *decode_xtheadcmo(rv_decode *dec, rv_isa isa)
> {
> rv_inst inst = dec->inst;
> - rv_opcode op = rv_op_illegal;
>
> switch (((inst >> 0) & 0b11)) {
> case 3:
> @@ -374,55 +136,55 @@ const rv_opcode_data
> *decode_xtheadcmo(rv_decode *dec, rv_isa isa)
> switch ((inst >> 20 & 0b111111111111)) {
> case 0b000000000001:
> if (((inst >> 20) & 0b11111) == 0) {
> - op = rv_op_th_dcache_call;
> + return &op_th_dcache_call;
> }
> break;
> case 0b000000000011:
> if (((inst >> 20) & 0b11111) == 0) {
> - op = rv_op_th_dcache_ciall;
> + return &op_th_dcache_ciall;
> }
> break;
> case 0b000000000010:
> if (((inst >> 20) & 0b11111) == 0) {
> - op = rv_op_th_dcache_iall;
> + return &op_th_dcache_iall;
> }
> break;
> - case 0b000000101001: op = rv_op_th_dcache_cpa;
> break;
> - case 0b000000101011: op = rv_op_th_dcache_cipa;
> break;
> - case 0b000000101010: op = rv_op_th_dcache_ipa;
> break;
> - case 0b000000100101: op = rv_op_th_dcache_cva;
> break;
> - case 0b000000100111: op = rv_op_th_dcache_civa;
> break;
> - case 0b000000100110: op = rv_op_th_dcache_iva;
> break;
> - case 0b000000100001: op = rv_op_th_dcache_csw;
> break;
> - case 0b000000100011: op = rv_op_th_dcache_cisw;
> break;
> - case 0b000000100010: op = rv_op_th_dcache_isw;
> break;
> - case 0b000000101000: op = rv_op_th_dcache_cpal1;
> break;
> - case 0b000000100100: op = rv_op_th_dcache_cval1;
> break;
> + case 0b000000101001: return &op_th_dcache_cpa;
> + case 0b000000101011: return &op_th_dcache_cipa;
> + case 0b000000101010: return &op_th_dcache_ipa;
> + case 0b000000100101: return &op_th_dcache_cva;
> + case 0b000000100111: return &op_th_dcache_civa;
> + case 0b000000100110: return &op_th_dcache_iva;
> + case 0b000000100001: return &op_th_dcache_csw;
> + case 0b000000100011: return &op_th_dcache_cisw;
> + case 0b000000100010: return &op_th_dcache_isw;
> + case 0b000000101000: return &op_th_dcache_cpal1;
> + case 0b000000100100: return &op_th_dcache_cval1;
> case 0b000000010000:
> if (((inst >> 20) & 0b11111) == 0) {
> - op = rv_op_th_icache_iall;
> + return &op_th_icache_iall;
> }
> break;
> case 0b000000010001:
> if (((inst >> 20) & 0b11111) == 0) {
> - op = rv_op_th_icache_ialls;
> + return &op_th_icache_ialls;
> }
> break;
> - case 0b000000111000: op = rv_op_th_icache_ipa;
> break;
> - case 0b000000110000: op = rv_op_th_icache_iva;
> break;
> + case 0b000000111000: return &op_th_icache_ipa;
> + case 0b000000110000: return &op_th_icache_iva;
> case 0b000000010101:
> if (((inst >> 20) & 0b11111) == 0) {
> - op = rv_op_th_l2cache_call;
> + return &op_th_l2cache_call;
> }
> break;
> case 0b000000010111:
> if (((inst >> 20) & 0b11111) == 0) {
> - op = rv_op_th_l2cache_ciall;
> + return &op_th_l2cache_ciall;
> }
> break;
> case 0b000000010110:
> if (((inst >> 20) & 0b11111) == 0) {
> - op = rv_op_th_l2cache_iall;
> + return &op_th_l2cache_iall;
> }
> break;
> }
> @@ -434,13 +196,12 @@ const rv_opcode_data
> *decode_xtheadcmo(rv_decode *dec, rv_isa isa)
> break;
> }
>
> - return op == rv_op_illegal ? NULL : &xthead_opcode_data[op];
> + return NULL;
> }
>
> const rv_opcode_data *decode_xtheadcondmov(rv_decode *dec, rv_isa
> isa)
> {
> rv_inst inst = dec->inst;
> - rv_opcode op = rv_op_illegal;
>
> switch (((inst >> 0) & 0b11)) {
> case 3:
> @@ -450,8 +211,8 @@ const rv_opcode_data
> *decode_xtheadcondmov(rv_decode *dec, rv_isa isa)
> switch ((inst >> 12) & 0b111) {
> case 1:
> switch ((inst >> 25) & 0b1111111) {
> - case 0b0100000: op = rv_op_th_mveqz; break;
> - case 0b0100001: op = rv_op_th_mvnez; break;
> + case 0b0100000: return &op_th_mveqz;
> + case 0b0100001: return &op_th_mvnez;
> }
> break;
> }
> @@ -461,13 +222,12 @@ const rv_opcode_data
> *decode_xtheadcondmov(rv_decode *dec, rv_isa isa)
> break;
> }
>
> - return op == rv_op_illegal ? NULL : &xthead_opcode_data[op];
> + return NULL;
> }
>
> const rv_opcode_data *decode_xtheadfmemidx(rv_decode *dec, rv_isa
> isa)
> {
> rv_inst inst = dec->inst;
> - rv_opcode op = rv_op_illegal;
>
> switch (((inst >> 0) & 0b11)) {
> case 3:
> @@ -477,18 +237,18 @@ const rv_opcode_data
> *decode_xtheadfmemidx(rv_decode *dec, rv_isa isa)
> switch ((inst >> 12) & 0b111) {
> case 6:
> switch ((inst >> 27) & 0b11111) {
> - case 8: op = rv_op_th_flrw; break;
> - case 10: op = rv_op_th_flurw; break;
> - case 12: op = rv_op_th_flrd; break;
> - case 14: op = rv_op_th_flurd; break;
> + case 8: return &op_th_flrw;
> + case 10: return &op_th_flurw;
> + case 12: return &op_th_flrd;
> + case 14: return &op_th_flurd;
> }
> break;
> case 7:
> switch ((inst >> 27) & 0b11111) {
> - case 8: op = rv_op_th_fsrw; break;
> - case 10: op = rv_op_th_fsurw; break;
> - case 12: op = rv_op_th_fsrd; break;
> - case 14: op = rv_op_th_fsurd; break;
> + case 8: return &op_th_fsrw;
> + case 10: return &op_th_fsurw;
> + case 12: return &op_th_fsrd;
> + case 14: return &op_th_fsurd;
> }
> break;
> }
> @@ -498,13 +258,12 @@ const rv_opcode_data
> *decode_xtheadfmemidx(rv_decode *dec, rv_isa isa)
> break;
> }
>
> - return op == rv_op_illegal ? NULL : &xthead_opcode_data[op];
> + return NULL;
> }
>
> const rv_opcode_data *decode_xtheadfmv(rv_decode *dec, rv_isa isa)
> {
> rv_inst inst = dec->inst;
> - rv_opcode op = rv_op_illegal;
>
> switch (((inst >> 0) & 0b11)) {
> case 3:
> @@ -516,12 +275,12 @@ const rv_opcode_data
> *decode_xtheadfmv(rv_decode *dec, rv_isa isa)
> switch ((inst >> 25) & 0b1111111) {
> case 0b1010000:
> if (((inst >> 20) & 0b11111) == 0) {
> - op = rv_op_th_fmv_hw_x;
> + return &op_th_fmv_hw_x;
> }
> break;
> case 0b1100000:
> if (((inst >> 20) & 0b11111) == 0) {
> - op = rv_op_th_fmv_x_hw;
> + return &op_th_fmv_x_hw;
> }
> break;
> }
> @@ -533,13 +292,12 @@ const rv_opcode_data
> *decode_xtheadfmv(rv_decode *dec, rv_isa isa)
> break;
> }
>
> - return op == rv_op_illegal ? NULL : &xthead_opcode_data[op];
> + return NULL;
> }
>
> const rv_opcode_data *decode_xtheadmac(rv_decode *dec, rv_isa isa)
> {
> rv_inst inst = dec->inst;
> - rv_opcode op = rv_op_illegal;
>
> switch (((inst >> 0) & 0b11)) {
> case 3:
> @@ -549,12 +307,12 @@ const rv_opcode_data
> *decode_xtheadmac(rv_decode *dec, rv_isa isa)
> switch ((inst >> 12) & 0b111) {
> case 1:
> switch ((inst >> 25) & 0b1111111) {
> - case 0b0010000: op = rv_op_th_mula; break;
> - case 0b0010001: op = rv_op_th_muls; break;
> - case 0b0010010: op = rv_op_th_mulaw; break;
> - case 0b0010011: op = rv_op_th_mulsw; break;
> - case 0b0010100: op = rv_op_th_mulah; break;
> - case 0b0010101: op = rv_op_th_mulsh; break;
> + case 0b0010000: return &op_th_mula;
> + case 0b0010001: return &op_th_muls;
> + case 0b0010010: return &op_th_mulaw;
> + case 0b0010011: return &op_th_mulsw;
> + case 0b0010100: return &op_th_mulah;
> + case 0b0010101: return &op_th_mulsh;
> }
> break;
> }
> @@ -564,13 +322,12 @@ const rv_opcode_data
> *decode_xtheadmac(rv_decode *dec, rv_isa isa)
> break;
> }
>
> - return op == rv_op_illegal ? NULL : &xthead_opcode_data[op];
> + return NULL;
> }
>
> const rv_opcode_data *decode_xtheadmemidx(rv_decode *dec, rv_isa
> isa)
> {
> rv_inst inst = dec->inst;
> - rv_opcode op = rv_op_illegal;
>
> switch (((inst >> 0) & 0b11)) {
> case 3:
> @@ -580,54 +337,54 @@ const rv_opcode_data
> *decode_xtheadmemidx(rv_decode *dec, rv_isa isa)
> switch ((inst >> 12) & 0b111) {
> case 4:
> switch ((inst >> 27) & 0b11111) {
> - case 0: op = rv_op_th_lrb; break;
> - case 1: op = rv_op_th_lbib; break;
> - case 2: op = rv_op_th_lurb; break;
> - case 3: op = rv_op_th_lbia; break;
> - case 4: op = rv_op_th_lrh; break;
> - case 5: op = rv_op_th_lhib; break;
> - case 6: op = rv_op_th_lurh; break;
> - case 7: op = rv_op_th_lhia; break;
> - case 8: op = rv_op_th_lrw; break;
> - case 9: op = rv_op_th_lwib; break;
> - case 10: op = rv_op_th_lurw; break;
> - case 11: op = rv_op_th_lwia; break;
> - case 12: op = rv_op_th_lrd; break;
> - case 13: op = rv_op_th_ldib; break;
> - case 14: op = rv_op_th_lurd; break;
> - case 15: op = rv_op_th_ldia; break;
> - case 16: op = rv_op_th_lrbu; break;
> - case 17: op = rv_op_th_lbuib; break;
> - case 18: op = rv_op_th_lurbu; break;
> - case 19: op = rv_op_th_lbuia; break;
> - case 20: op = rv_op_th_lrhu; break;
> - case 21: op = rv_op_th_lhuib; break;
> - case 22: op = rv_op_th_lurhu; break;
> - case 23: op = rv_op_th_lhuia; break;
> - case 24: op = rv_op_th_lrwu; break;
> - case 25: op = rv_op_th_lwuib; break;
> - case 26: op = rv_op_th_lurwu; break;
> - case 27: op = rv_op_th_lwuia; break;
> + case 0: return &op_th_lrb;
> + case 1: return &op_th_lbib;
> + case 2: return &op_th_lurb;
> + case 3: return &op_th_lbia;
> + case 4: return &op_th_lrh;
> + case 5: return &op_th_lhib;
> + case 6: return &op_th_lurh;
> + case 7: return &op_th_lhia;
> + case 8: return &op_th_lrw;
> + case 9: return &op_th_lwib;
> + case 10: return &op_th_lurw;
> + case 11: return &op_th_lwia;
> + case 12: return &op_th_lrd;
> + case 13: return &op_th_ldib;
> + case 14: return &op_th_lurd;
> + case 15: return &op_th_ldia;
> + case 16: return &op_th_lrbu;
> + case 17: return &op_th_lbuib;
> + case 18: return &op_th_lurbu;
> + case 19: return &op_th_lbuia;
> + case 20: return &op_th_lrhu;
> + case 21: return &op_th_lhuib;
> + case 22: return &op_th_lurhu;
> + case 23: return &op_th_lhuia;
> + case 24: return &op_th_lrwu;
> + case 25: return &op_th_lwuib;
> + case 26: return &op_th_lurwu;
> + case 27: return &op_th_lwuia;
> }
> break;
> case 5:
> switch ((inst >> 27) & 0b11111) {
> - case 0: op = rv_op_th_srb; break;
> - case 1: op = rv_op_th_sbib; break;
> - case 2: op = rv_op_th_surb; break;
> - case 3: op = rv_op_th_sbia; break;
> - case 4: op = rv_op_th_srh; break;
> - case 5: op = rv_op_th_shib; break;
> - case 6: op = rv_op_th_surh; break;
> - case 7: op = rv_op_th_shia; break;
> - case 8: op = rv_op_th_srw; break;
> - case 9: op = rv_op_th_swib; break;
> - case 10: op = rv_op_th_surw; break;
> - case 11: op = rv_op_th_swia; break;
> - case 12: op = rv_op_th_srd; break;
> - case 13: op = rv_op_th_sdib; break;
> - case 14: op = rv_op_th_surd; break;
> - case 15: op = rv_op_th_sdia; break;
> + case 0: return &op_th_srb;
> + case 1: return &op_th_sbib;
> + case 2: return &op_th_surb;
> + case 3: return &op_th_sbia;
> + case 4: return &op_th_srh;
> + case 5: return &op_th_shib;
> + case 6: return &op_th_surh;
> + case 7: return &op_th_shia;
> + case 8: return &op_th_srw;
> + case 9: return &op_th_swib;
> + case 10: return &op_th_surw;
> + case 11: return &op_th_swia;
> + case 12: return &op_th_srd;
> + case 13: return &op_th_sdib;
> + case 14: return &op_th_surd;
> + case 15: return &op_th_sdia;
> }
> break;
> break;
> @@ -638,13 +395,12 @@ const rv_opcode_data
> *decode_xtheadmemidx(rv_decode *dec, rv_isa isa)
> break;
> }
>
> - return op == rv_op_illegal ? NULL : &xthead_opcode_data[op];
> + return NULL;
> }
>
> const rv_opcode_data *decode_xtheadmempair(rv_decode *dec, rv_isa
> isa)
> {
> rv_inst inst = dec->inst;
> - rv_opcode op = rv_op_illegal;
>
> switch (((inst >> 0) & 0b11)) {
> case 3:
> @@ -654,15 +410,15 @@ const rv_opcode_data
> *decode_xtheadmempair(rv_decode *dec, rv_isa isa)
> switch ((inst >> 12) & 0b111) {
> case 4:
> switch ((inst >> 27) & 0b11111) {
> - case 28: op = rv_op_th_lwd; break;
> - case 30: op = rv_op_th_lwud; break;
> - case 31: op = rv_op_th_ldd; break;
> + case 28: return &op_th_lwd;
> + case 30: return &op_th_lwud;
> + case 31: return &op_th_ldd;
> }
> break;
> case 5:
> switch ((inst >> 27) & 0b11111) {
> - case 28: op = rv_op_th_swd; break;
> - case 31: op = rv_op_th_sdd; break;
> + case 28: return &op_th_swd;
> + case 31: return &op_th_sdd;
> }
> break;
> }
> @@ -672,13 +428,12 @@ const rv_opcode_data
> *decode_xtheadmempair(rv_decode *dec, rv_isa isa)
> break;
> }
>
> - return op == rv_op_illegal ? NULL : &xthead_opcode_data[op];
> + return NULL;
> }
>
> const rv_opcode_data *decode_xtheadsync(rv_decode *dec, rv_isa isa)
> {
> rv_inst inst = dec->inst;
> - rv_opcode op = rv_op_illegal;
>
> switch (((inst >> 0) & 0b11)) {
> case 3:
> @@ -688,13 +443,13 @@ const rv_opcode_data
> *decode_xtheadsync(rv_decode *dec, rv_isa isa)
> switch ((inst >> 12) & 0b111) {
> case 0:
> switch ((inst >> 25) & 0b1111111) {
> - case 0b0000010: op = rv_op_th_sfence_vmas; break;
> + case 0b0000010: return &op_th_sfence_vmas;
> case 0b0000000:
> switch ((inst >> 20) & 0b11111) {
> - case 0b11000: op = rv_op_th_sync; break;
> - case 0b11010: op = rv_op_th_sync_i; break;
> - case 0b11011: op = rv_op_th_sync_is; break;
> - case 0b11001: op = rv_op_th_sync_s; break;
> + case 0b11000: return &op_th_sync;
> + case 0b11010: return &op_th_sync_i;
> + case 0b11011: return &op_th_sync_is;
> + case 0b11001: return &op_th_sync_s;
> }
> break;
> }
> @@ -706,5 +461,5 @@ const rv_opcode_data *decode_xtheadsync(rv_decode
> *dec, rv_isa isa)
> break;
> }
>
> - return op == rv_op_illegal ? NULL : &xthead_opcode_data[op];
> + return NULL;
> }
> diff --git a/disas/riscv-xthead-op.c.inc b/disas/riscv-xthead-
> op.c.inc
> new file mode 100644
> index 0000000000..1e4e0557cd
> --- /dev/null
> +++ b/disas/riscv-xthead-op.c.inc
> @@ -0,0 +1,125 @@
> +/* XTheadBa */
> +OP(th_addsl, "th.addsl", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm)
> +
> +/* XTheadBb */
> +OP(th_srri, "th.srri", rv_codec_r2_imm6, rv_fmt_rd_rs1_imm)
> +OP(th_srriw, "th.srriw", rv_codec_r2_imm5, rv_fmt_rd_rs1_imm)
> +OP(th_ext, "th.ext", rv_codec_r2_immhl, rv_fmt_rd_rs1_immh_imml)
> +OP(th_extu, "th.extu", rv_codec_r2_immhl, rv_fmt_rd_rs1_immh_imml)
> +OP(th_ff0, "th.ff0", rv_codec_r2, rv_fmt_rd_rs1)
> +OP(th_ff1, "th.ff1", rv_codec_r2, rv_fmt_rd_rs1)
> +OP(th_rev, "th.rev", rv_codec_r2, rv_fmt_rd_rs1)
> +OP(th_revw, "th.revw", rv_codec_r2, rv_fmt_rd_rs1)
> +OP(th_tstnbz, "th.tstnbz", rv_codec_r2, rv_fmt_rd_rs1)
> +
> +/* XTheadBs */
> +OP(th_tst, "th.tst", rv_codec_r2_imm6, rv_fmt_rd_rs1_imm)
> +
> +/* XTheadCmo */
> +OP(th_dcache_call, "th.dcache.call", rv_codec_none, rv_fmt_none)
> +OP(th_dcache_ciall, "th.dcache.ciall", rv_codec_none, rv_fmt_none)
> +OP(th_dcache_iall, "th.dcache.iall", rv_codec_none, rv_fmt_none)
> +OP(th_dcache_cpa, "th.dcache.cpa", rv_codec_r, rv_fmt_rs1)
> +OP(th_dcache_cipa, "th.dcache.cipa", rv_codec_r, rv_fmt_rs1)
> +OP(th_dcache_ipa, "th.dcache.ipa", rv_codec_r, rv_fmt_rs1)
> +OP(th_dcache_cva, "th.dcache.cva", rv_codec_r, rv_fmt_rs1)
> +OP(th_dcache_civa, "th.dcache.civa", rv_codec_r, rv_fmt_rs1)
> +OP(th_dcache_iva, "th.dcache.iva", rv_codec_r, rv_fmt_rs1)
> +OP(th_dcache_csw, "th.dcache.csw", rv_codec_r, rv_fmt_rs1)
> +OP(th_dcache_cisw, "th.dcache.cisw", rv_codec_r, rv_fmt_rs1)
> +OP(th_dcache_isw, "th.dcache.isw", rv_codec_r, rv_fmt_rs1)
> +OP(th_dcache_cpal1, "th.dcache.cpal1", rv_codec_r, rv_fmt_rs1)
> +OP(th_dcache_cval1, "th.dcache.cval1", rv_codec_r, rv_fmt_rs1)
> +OP(th_icache_iall, "th.icache.iall", rv_codec_none, rv_fmt_none)
> +OP(th_icache_ialls, "th.icache.ialls", rv_codec_none, rv_fmt_none)
> +OP(th_icache_ipa, "th.icache.ipa", rv_codec_r, rv_fmt_rs1)
> +OP(th_icache_iva, "th.icache.iva", rv_codec_r, rv_fmt_rs1)
> +OP(th_l2cache_call, "th.l2cache.call", rv_codec_none, rv_fmt_none)
> +OP(th_l2cache_ciall, "th.l2cache.ciall", rv_codec_none, rv_fmt_none)
> +OP(th_l2cache_iall, "th.l2cache.iall", rv_codec_none, rv_fmt_none)
> +
> +/* XTheadCondMov */
> +OP(th_mveqz, "th.mveqz", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(th_mvnez, "th.mvnez", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +
> +/* XTheadFMemIdx */
> +OP(th_flrd, "th.flrd", rv_codec_r_imm2, rv_fmt_frd_rs1_rs2_imm)
> +OP(th_flrw, "th.flrw", rv_codec_r_imm2, rv_fmt_frd_rs1_rs2_imm)
> +OP(th_flurd, "th.flurd", rv_codec_r_imm2, rv_fmt_frd_rs1_rs2_imm)
> +OP(th_flurw, "th.flurw", rv_codec_r_imm2, rv_fmt_frd_rs1_rs2_imm)
> +OP(th_fsrd, "th.fsrd", rv_codec_r_imm2, rv_fmt_frd_rs1_rs2_imm)
> +OP(th_fsrw, "th.fsrw", rv_codec_r_imm2, rv_fmt_frd_rs1_rs2_imm)
> +OP(th_fsurd, "th.fsurd", rv_codec_r_imm2, rv_fmt_frd_rs1_rs2_imm)
> +OP(th_fsurw, "th.fsurw", rv_codec_r_imm2, rv_fmt_frd_rs1_rs2_imm)
> +
> +/* XTheadFmv */
> +OP(th_fmv_hw_x, "th.fmv.hw.x", rv_codec_r, rv_fmt_rd_frs1)
> +OP(th_fmv_x_hw, "th.fmv.x.hw", rv_codec_r, rv_fmt_rd_frs1)
> +
> +/* XTheadMac */
> +OP(th_mula, "th.mula", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(th_mulaw, "th.mulaw", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(th_mulah, "th.mulah", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(th_muls, "th.muls", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(th_mulsw, "th.mulsw", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(th_mulsh, "th.mulsh", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +
> +/* XTheadMemIdx */
> +OP(th_lbia, "th.lbia", rv_codec_r2_imm2_imm5,
> rv_fmt_rd_rs1_immh_imml_addr)
> +OP(th_lbib, "th.lbib", rv_codec_r2_imm2_imm5,
> rv_fmt_rd_rs1_immh_imml_addr)
> +OP(th_lbuia, "th.lbuia", rv_codec_r2_imm2_imm5,
> rv_fmt_rd_rs1_immh_imml_addr)
> +OP(th_lbuib, "th.lbuib", rv_codec_r2_imm2_imm5,
> rv_fmt_rd_rs1_immh_imml_addr)
> +OP(th_lhia, "th.lhia", rv_codec_r2_imm2_imm5,
> rv_fmt_rd_rs1_immh_imml_addr)
> +OP(th_lhib, "th.lhib", rv_codec_r2_imm2_imm5,
> rv_fmt_rd_rs1_immh_imml_addr)
> +OP(th_lhuia, "th.lhuia", rv_codec_r2_imm2_imm5,
> rv_fmt_rd_rs1_immh_imml_addr)
> +OP(th_lhuib, "th.lhuib", rv_codec_r2_imm2_imm5,
> rv_fmt_rd_rs1_immh_imml_addr)
> +OP(th_lwia, "th.lwia", rv_codec_r2_imm2_imm5,
> rv_fmt_rd_rs1_immh_imml_addr)
> +OP(th_lwib, "th.lwib", rv_codec_r2_imm2_imm5,
> rv_fmt_rd_rs1_immh_imml_addr)
> +OP(th_lwuia, "th.lwuia", rv_codec_r2_imm2_imm5,
> rv_fmt_rd_rs1_immh_imml_addr)
> +OP(th_lwuib, "th.lwuib", rv_codec_r2_imm2_imm5,
> rv_fmt_rd_rs1_immh_imml_addr)
> +OP(th_ldia, "th.ldia", rv_codec_r2_imm2_imm5,
> rv_fmt_rd_rs1_immh_imml_addr)
> +OP(th_ldib, "th.ldib", rv_codec_r2_imm2_imm5,
> rv_fmt_rd_rs1_immh_imml_addr)
> +OP(th_sbia, "th.sbia", rv_codec_r2_imm2_imm5,
> rv_fmt_rd_rs1_immh_imml_addr)
> +OP(th_sbib, "th.sbib", rv_codec_r2_imm2_imm5,
> rv_fmt_rd_rs1_immh_imml_addr)
> +OP(th_shia, "th.shia", rv_codec_r2_imm2_imm5,
> rv_fmt_rd_rs1_immh_imml_addr)
> +OP(th_shib, "th.shib", rv_codec_r2_imm2_imm5,
> rv_fmt_rd_rs1_immh_imml_addr)
> +OP(th_swia, "th.swia", rv_codec_r2_imm2_imm5,
> rv_fmt_rd_rs1_immh_imml_addr)
> +OP(th_swib, "th.swib", rv_codec_r2_imm2_imm5,
> rv_fmt_rd_rs1_immh_imml_addr)
> +OP(th_sdia, "th.sdia", rv_codec_r2_imm2_imm5,
> rv_fmt_rd_rs1_immh_imml_addr)
> +OP(th_sdib, "th.sdib", rv_codec_r2_imm2_imm5,
> rv_fmt_rd_rs1_immh_imml_addr)
> +OP(th_lrb, "th.lrb", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm)
> +OP(th_lrbu, "th.lrbu", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm)
> +OP(th_lrh, "th.lrh", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm)
> +OP(th_lrhu, "th.lrhu", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm)
> +OP(th_lrw, "th.lrw", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm)
> +OP(th_lrwu, "th.lrwu", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm)
> +OP(th_lrd, "th.lrd", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm)
> +OP(th_srb, "th.srb", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm)
> +OP(th_srh, "th.srh", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm)
> +OP(th_srw, "th.srw", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm)
> +OP(th_srd, "th.srd", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm)
> +OP(th_lurb, "th.lurb", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm)
> +OP(th_lurbu, "th.lurbu", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm)
> +OP(th_lurh, "th.lurh", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm)
> +OP(th_lurhu, "th.lurhu", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm)
> +OP(th_lurw, "th.lurw", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm)
> +OP(th_lurwu, "th.lurwu", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm)
> +OP(th_lurd, "th.lurd", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm)
> +OP(th_surb, "th.surb", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm)
> +OP(th_surh, "th.surh", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm)
> +OP(th_surw, "th.surw", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm)
> +OP(th_surd, "th.surd", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm)
> +
> +/* XTheadMemPair */
> +OP(th_ldd, "th.ldd", rv_codec_r_imm2, rv_fmt_rd2_imm)
> +OP(th_lwd, "th.lwd", rv_codec_r_imm2, rv_fmt_rd2_imm)
> +OP(th_lwud, "th.lwud", rv_codec_r_imm2, rv_fmt_rd2_imm)
> +OP(th_sdd, "th.sdd", rv_codec_r_imm2, rv_fmt_rd2_imm)
> +OP(th_swd, "th.swd", rv_codec_r_imm2, rv_fmt_rd2_imm)
> +
> +/* XTheadSync */
> +OP(th_sfence_vmas, "th.sfence.vmas", rv_codec_r, rv_fmt_rs1_rs2)
> +OP(th_sync, "th.sync", rv_codec_none, rv_fmt_none)
> +OP(th_sync_i, "th.sync.i", rv_codec_none, rv_fmt_none)
> +OP(th_sync_is, "th.sync.is", rv_codec_none, rv_fmt_none)
> +OP(th_sync_s, "th.sync.s", rv_codec_none, rv_fmt_none)
^ permalink raw reply [flat|nested] 119+ messages in thread
* Re: [PATCH 48/56] disas/riscv: Move rv_op_illegal to riscv.c
2026-08-09 22:35 ` [PATCH 48/56] disas/riscv: Move rv_op_illegal to riscv.c Richard Henderson
@ 2026-08-12 12:54 ` Alistair
0 siblings, 0 replies; 119+ messages in thread
From: Alistair @ 2026-08-12 12:54 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: qemu-riscv
On Sun, 2026-08-09 at 15:35 -0700, Richard Henderson wrote:
> illegal is no longer used in other files.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> disas/riscv.h | 4 ----
> disas/riscv.c | 2 +-
> 2 files changed, 1 insertion(+), 5 deletions(-)
>
> diff --git a/disas/riscv.h b/disas/riscv.h
> index 241dd47d7f..5ac8c41616 100644
> --- a/disas/riscv.h
> +++ b/disas/riscv.h
> @@ -200,10 +200,6 @@ typedef struct {
> uint8_t rlist;
> } rv_decode;
>
> -enum {
> - rv_op_illegal = 0
> -};
> -
> /* instruction formats */
>
> #define rv_fmt_none "O\t"
> diff --git a/disas/riscv.c b/disas/riscv.c
> index 4141741d79..f0b3bc6be7 100644
> --- a/disas/riscv.c
> +++ b/disas/riscv.c
> @@ -29,7 +29,7 @@
> #include "disas/riscv-xlrbr.h"
>
> typedef enum {
> - /* 0 is reserved for rv_op_illegal. */
> + rv_op_illegal = 0,
> rv_op_lui = 1,
> rv_op_auipc = 2,
> rv_op_jal = 3,
^ permalink raw reply [flat|nested] 119+ messages in thread
* Re: [PATCH 49/56] disas/riscv: Split out riscv-op.c.inc
2026-08-09 22:35 ` [PATCH 49/56] disas/riscv: Split out riscv-op.c.inc Richard Henderson
@ 2026-08-12 12:55 ` Alistair
0 siblings, 0 replies; 119+ messages in thread
From: Alistair @ 2026-08-12 12:55 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: qemu-riscv
On Sun, 2026-08-09 at 15:35 -0700, Richard Henderson wrote:
> Move rvi_opcode_data to riscv-op.c.inc and massage
> the lines into OP() form. Unlike other files, keep
> the enumeration and the table intact for now, but
> build them both from the same source.
>
> Adjust the names of rv_*mop to include _op_ to match
> the general pattern.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> disas/riscv.c | 1931 +---------------------------------------
> --
> disas/riscv-op.c.inc | 958 +++++++++++++++++++++
> 2 files changed, 967 insertions(+), 1922 deletions(-)
> create mode 100644 disas/riscv-op.c.inc
>
> diff --git a/disas/riscv.c b/disas/riscv.c
> index f0b3bc6be7..9dad56b486 100644
> --- a/disas/riscv.c
> +++ b/disas/riscv.c
> @@ -29,964 +29,9 @@
> #include "disas/riscv-xlrbr.h"
>
> typedef enum {
> - rv_op_illegal = 0,
> - rv_op_lui = 1,
> - rv_op_auipc = 2,
> - rv_op_jal = 3,
> - rv_op_jalr = 4,
> - rv_op_beq = 5,
> - rv_op_bne = 6,
> - rv_op_blt = 7,
> - rv_op_bge = 8,
> - rv_op_bltu = 9,
> - rv_op_bgeu = 10,
> - rv_op_lb = 11,
> - rv_op_lh = 12,
> - rv_op_lw = 13,
> - rv_op_lbu = 14,
> - rv_op_lhu = 15,
> - rv_op_sb = 16,
> - rv_op_sh = 17,
> - rv_op_sw = 18,
> - rv_op_addi = 19,
> - rv_op_slti = 20,
> - rv_op_sltiu = 21,
> - rv_op_xori = 22,
> - rv_op_ori = 23,
> - rv_op_andi = 24,
> - rv_op_slli = 25,
> - rv_op_srli = 26,
> - rv_op_srai = 27,
> - rv_op_add = 28,
> - rv_op_sub = 29,
> - rv_op_sll = 30,
> - rv_op_slt = 31,
> - rv_op_sltu = 32,
> - rv_op_xor = 33,
> - rv_op_srl = 34,
> - rv_op_sra = 35,
> - rv_op_or = 36,
> - rv_op_and = 37,
> - rv_op_fence = 38,
> - rv_op_fence_i = 39,
> - rv_op_lwu = 40,
> - rv_op_ld = 41,
> - rv_op_sd = 42,
> - rv_op_addiw = 43,
> - rv_op_slliw = 44,
> - rv_op_srliw = 45,
> - rv_op_sraiw = 46,
> - rv_op_addw = 47,
> - rv_op_subw = 48,
> - rv_op_sllw = 49,
> - rv_op_srlw = 50,
> - rv_op_sraw = 51,
> - rv_op_ldu = 52,
> - rv_op_lq = 53,
> - rv_op_sq = 54,
> - rv_op_addid = 55,
> - rv_op_sllid = 56,
> - rv_op_srlid = 57,
> - rv_op_sraid = 58,
> - rv_op_addd = 59,
> - rv_op_subd = 60,
> - rv_op_slld = 61,
> - rv_op_srld = 62,
> - rv_op_srad = 63,
> - rv_op_mul = 64,
> - rv_op_mulh = 65,
> - rv_op_mulhsu = 66,
> - rv_op_mulhu = 67,
> - rv_op_div = 68,
> - rv_op_divu = 69,
> - rv_op_rem = 70,
> - rv_op_remu = 71,
> - rv_op_mulw = 72,
> - rv_op_divw = 73,
> - rv_op_divuw = 74,
> - rv_op_remw = 75,
> - rv_op_remuw = 76,
> - rv_op_muld = 77,
> - rv_op_divd = 78,
> - rv_op_divud = 79,
> - rv_op_remd = 80,
> - rv_op_remud = 81,
> - rv_op_lr_w = 82,
> - rv_op_sc_w = 83,
> - rv_op_amoswap_w = 84,
> - rv_op_amoadd_w = 85,
> - rv_op_amoxor_w = 86,
> - rv_op_amoor_w = 87,
> - rv_op_amoand_w = 88,
> - rv_op_amomin_w = 89,
> - rv_op_amomax_w = 90,
> - rv_op_amominu_w = 91,
> - rv_op_amomaxu_w = 92,
> - rv_op_lr_d = 93,
> - rv_op_sc_d = 94,
> - rv_op_amoswap_d = 95,
> - rv_op_amoadd_d = 96,
> - rv_op_amoxor_d = 97,
> - rv_op_amoor_d = 98,
> - rv_op_amoand_d = 99,
> - rv_op_amomin_d = 100,
> - rv_op_amomax_d = 101,
> - rv_op_amominu_d = 102,
> - rv_op_amomaxu_d = 103,
> - rv_op_lr_q = 104,
> - rv_op_sc_q = 105,
> - rv_op_amoswap_q = 106,
> - rv_op_amoadd_q = 107,
> - rv_op_amoxor_q = 108,
> - rv_op_amoor_q = 109,
> - rv_op_amoand_q = 110,
> - rv_op_amomin_q = 111,
> - rv_op_amomax_q = 112,
> - rv_op_amominu_q = 113,
> - rv_op_amomaxu_q = 114,
> - rv_op_ecall = 115,
> - rv_op_ebreak = 116,
> - rv_op_uret = 117,
> - rv_op_sret = 118,
> - rv_op_hret = 119,
> - rv_op_mret = 120,
> - rv_op_dret = 121,
> - rv_op_sfence_vm = 122,
> - rv_op_sfence_vma = 123,
> - rv_op_wfi = 124,
> - rv_op_csrrw = 125,
> - rv_op_csrrs = 126,
> - rv_op_csrrc = 127,
> - rv_op_csrrwi = 128,
> - rv_op_csrrsi = 129,
> - rv_op_csrrci = 130,
> - rv_op_flw = 131,
> - rv_op_fsw = 132,
> - rv_op_fmadd_s = 133,
> - rv_op_fmsub_s = 134,
> - rv_op_fnmsub_s = 135,
> - rv_op_fnmadd_s = 136,
> - rv_op_fadd_s = 137,
> - rv_op_fsub_s = 138,
> - rv_op_fmul_s = 139,
> - rv_op_fdiv_s = 140,
> - rv_op_fsgnj_s = 141,
> - rv_op_fsgnjn_s = 142,
> - rv_op_fsgnjx_s = 143,
> - rv_op_fmin_s = 144,
> - rv_op_fmax_s = 145,
> - rv_op_fsqrt_s = 146,
> - rv_op_fle_s = 147,
> - rv_op_flt_s = 148,
> - rv_op_feq_s = 149,
> - rv_op_fcvt_w_s = 150,
> - rv_op_fcvt_wu_s = 151,
> - rv_op_fcvt_s_w = 152,
> - rv_op_fcvt_s_wu = 153,
> - rv_op_fmv_x_s = 154,
> - rv_op_fclass_s = 155,
> - rv_op_fmv_s_x = 156,
> - rv_op_fcvt_l_s = 157,
> - rv_op_fcvt_lu_s = 158,
> - rv_op_fcvt_s_l = 159,
> - rv_op_fcvt_s_lu = 160,
> - rv_op_fld = 161,
> - rv_op_fsd = 162,
> - rv_op_fmadd_d = 163,
> - rv_op_fmsub_d = 164,
> - rv_op_fnmsub_d = 165,
> - rv_op_fnmadd_d = 166,
> - rv_op_fadd_d = 167,
> - rv_op_fsub_d = 168,
> - rv_op_fmul_d = 169,
> - rv_op_fdiv_d = 170,
> - rv_op_fsgnj_d = 171,
> - rv_op_fsgnjn_d = 172,
> - rv_op_fsgnjx_d = 173,
> - rv_op_fmin_d = 174,
> - rv_op_fmax_d = 175,
> - rv_op_fcvt_s_d = 176,
> - rv_op_fcvt_d_s = 177,
> - rv_op_fsqrt_d = 178,
> - rv_op_fle_d = 179,
> - rv_op_flt_d = 180,
> - rv_op_feq_d = 181,
> - rv_op_fcvt_w_d = 182,
> - rv_op_fcvt_wu_d = 183,
> - rv_op_fcvt_d_w = 184,
> - rv_op_fcvt_d_wu = 185,
> - rv_op_fclass_d = 186,
> - rv_op_fcvt_l_d = 187,
> - rv_op_fcvt_lu_d = 188,
> - rv_op_fmv_x_d = 189,
> - rv_op_fcvt_d_l = 190,
> - rv_op_fcvt_d_lu = 191,
> - rv_op_fmv_d_x = 192,
> - rv_op_flq = 193,
> - rv_op_fsq = 194,
> - rv_op_fmadd_q = 195,
> - rv_op_fmsub_q = 196,
> - rv_op_fnmsub_q = 197,
> - rv_op_fnmadd_q = 198,
> - rv_op_fadd_q = 199,
> - rv_op_fsub_q = 200,
> - rv_op_fmul_q = 201,
> - rv_op_fdiv_q = 202,
> - rv_op_fsgnj_q = 203,
> - rv_op_fsgnjn_q = 204,
> - rv_op_fsgnjx_q = 205,
> - rv_op_fmin_q = 206,
> - rv_op_fmax_q = 207,
> - rv_op_fcvt_s_q = 208,
> - rv_op_fcvt_q_s = 209,
> - rv_op_fcvt_d_q = 210,
> - rv_op_fcvt_q_d = 211,
> - rv_op_fsqrt_q = 212,
> - rv_op_fle_q = 213,
> - rv_op_flt_q = 214,
> - rv_op_feq_q = 215,
> - rv_op_fcvt_w_q = 216,
> - rv_op_fcvt_wu_q = 217,
> - rv_op_fcvt_q_w = 218,
> - rv_op_fcvt_q_wu = 219,
> - rv_op_fclass_q = 220,
> - rv_op_fcvt_l_q = 221,
> - rv_op_fcvt_lu_q = 222,
> - rv_op_fcvt_q_l = 223,
> - rv_op_fcvt_q_lu = 224,
> - rv_op_fmv_x_q = 225,
> - rv_op_fmv_q_x = 226,
> - rv_op_c_addi4spn = 227,
> - rv_op_c_fld = 228,
> - rv_op_c_lw = 229,
> - rv_op_c_flw = 230,
> - rv_op_c_fsd = 231,
> - rv_op_c_sw = 232,
> - rv_op_c_fsw = 233,
> - rv_op_c_addi = 235,
> - rv_op_c_jal = 236,
> - rv_op_c_li = 237,
> - rv_op_c_addi16sp = 238,
> - rv_op_c_lui = 239,
> - rv_op_c_srli = 240,
> - rv_op_c_srai = 241,
> - rv_op_c_andi = 242,
> - rv_op_c_sub = 243,
> - rv_op_c_xor = 244,
> - rv_op_c_or = 245,
> - rv_op_c_and = 246,
> - rv_op_c_subw = 247,
> - rv_op_c_addw = 248,
> - rv_op_c_j = 249,
> - rv_op_c_beqz = 250,
> - rv_op_c_bnez = 251,
> - rv_op_c_slli = 252,
> - rv_op_c_fldsp = 253,
> - rv_op_c_lwsp = 254,
> - rv_op_c_flwsp = 255,
> - rv_op_c_jr = 256,
> - rv_op_c_mv = 257,
> - rv_op_c_ebreak = 258,
> - rv_op_c_jalr = 259,
> - rv_op_c_add = 260,
> - rv_op_c_fsdsp = 261,
> - rv_op_c_swsp = 262,
> - rv_op_c_fswsp = 263,
> - rv_op_c_ld = 264,
> - rv_op_c_sd = 265,
> - rv_op_c_addiw = 266,
> - rv_op_c_ldsp = 267,
> - rv_op_c_sdsp = 268,
> - rv_op_c_lq = 269,
> - rv_op_c_sq = 270,
> - rv_op_c_lqsp = 271,
> - rv_op_c_sqsp = 272,
> - rv_op_nop = 273,
> - rv_op_mv = 274,
> - rv_op_not = 275,
> - rv_op_neg = 276,
> - rv_op_negw = 277,
> - rv_op_sext_w = 278,
> - rv_op_seqz = 279,
> - rv_op_snez = 280,
> - rv_op_sltz = 281,
> - rv_op_sgtz = 282,
> - rv_op_fmv_s = 283,
> - rv_op_fabs_s = 284,
> - rv_op_fneg_s = 285,
> - rv_op_fmv_d = 286,
> - rv_op_fabs_d = 287,
> - rv_op_fneg_d = 288,
> - rv_op_fmv_q = 289,
> - rv_op_fabs_q = 290,
> - rv_op_fneg_q = 291,
> - rv_op_beqz = 292,
> - rv_op_bnez = 293,
> - rv_op_blez = 294,
> - rv_op_bgez = 295,
> - rv_op_bltz = 296,
> - rv_op_bgtz = 297,
> - rv_op_jal_ra = 298,
> - rv_op_jalr_ra = 299,
> - rv_op_j = 302,
> - rv_op_ret = 303,
> - rv_op_jr = 304,
> - rv_op_rdcycle = 305,
> - rv_op_rdtime = 306,
> - rv_op_rdinstret = 307,
> - rv_op_rdcycleh = 308,
> - rv_op_rdtimeh = 309,
> - rv_op_rdinstreth = 310,
> - rv_op_frcsr = 311,
> - rv_op_frrm = 312,
> - rv_op_frflags = 313,
> - rv_op_fscsr = 314,
> - rv_op_fsrm = 315,
> - rv_op_fsflags = 316,
> - rv_op_fsrmi = 317,
> - rv_op_fsflagsi = 318,
> - rv_op_bseti = 319,
> - rv_op_bclri = 320,
> - rv_op_binvi = 321,
> - rv_op_bexti = 322,
> - rv_op_rori = 323,
> - rv_op_clz = 324,
> - rv_op_ctz = 325,
> - rv_op_cpop = 326,
> - rv_op_sext_h = 327,
> - rv_op_sext_b = 328,
> - rv_op_xnor = 329,
> - rv_op_orn = 330,
> - rv_op_andn = 331,
> - rv_op_rol = 332,
> - rv_op_ror = 333,
> - rv_op_sh1add = 334,
> - rv_op_sh2add = 335,
> - rv_op_sh3add = 336,
> - rv_op_sh1add_uw = 337,
> - rv_op_sh2add_uw = 338,
> - rv_op_sh3add_uw = 339,
> - rv_op_clmul = 340,
> - rv_op_clmulr = 341,
> - rv_op_clmulh = 342,
> - rv_op_min = 343,
> - rv_op_minu = 344,
> - rv_op_max = 345,
> - rv_op_maxu = 346,
> - rv_op_clzw = 347,
> - rv_op_ctzw = 348,
> - rv_op_cpopw = 349,
> - rv_op_slli_uw = 350,
> - rv_op_add_uw = 351,
> - rv_op_rolw = 352,
> - rv_op_rorw = 353,
> - rv_op_rev8 = 354,
> - rv_op_zext_h = 355,
> - rv_op_roriw = 356,
> - rv_op_orc_b = 357,
> - rv_op_bset = 358,
> - rv_op_bclr = 359,
> - rv_op_binv = 360,
> - rv_op_bext = 361,
> - rv_op_aes32esmi = 362,
> - rv_op_aes32esi = 363,
> - rv_op_aes32dsmi = 364,
> - rv_op_aes32dsi = 365,
> - rv_op_aes64ks1i = 366,
> - rv_op_aes64ks2 = 367,
> - rv_op_aes64im = 368,
> - rv_op_aes64esm = 369,
> - rv_op_aes64es = 370,
> - rv_op_aes64dsm = 371,
> - rv_op_aes64ds = 372,
> - rv_op_sha256sig0 = 373,
> - rv_op_sha256sig1 = 374,
> - rv_op_sha256sum0 = 375,
> - rv_op_sha256sum1 = 376,
> - rv_op_sha512sig0 = 377,
> - rv_op_sha512sig1 = 378,
> - rv_op_sha512sum0 = 379,
> - rv_op_sha512sum1 = 380,
> - rv_op_sha512sum0r = 381,
> - rv_op_sha512sum1r = 382,
> - rv_op_sha512sig0l = 383,
> - rv_op_sha512sig0h = 384,
> - rv_op_sha512sig1l = 385,
> - rv_op_sha512sig1h = 386,
> - rv_op_sm3p0 = 387,
> - rv_op_sm3p1 = 388,
> - rv_op_sm4ed = 389,
> - rv_op_sm4ks = 390,
> - rv_op_brev8 = 391,
> - rv_op_pack = 392,
> - rv_op_packh = 393,
> - rv_op_packw = 394,
> - rv_op_unzip = 395,
> - rv_op_zip = 396,
> - rv_op_xperm4 = 397,
> - rv_op_xperm8 = 398,
> - rv_op_vle8_v = 399,
> - rv_op_vle16_v = 400,
> - rv_op_vle32_v = 401,
> - rv_op_vle64_v = 402,
> - rv_op_vse8_v = 403,
> - rv_op_vse16_v = 404,
> - rv_op_vse32_v = 405,
> - rv_op_vse64_v = 406,
> - rv_op_vlm_v = 407,
> - rv_op_vsm_v = 408,
> - rv_op_vlse8_v = 409,
> - rv_op_vlse16_v = 410,
> - rv_op_vlse32_v = 411,
> - rv_op_vlse64_v = 412,
> - rv_op_vsse8_v = 413,
> - rv_op_vsse16_v = 414,
> - rv_op_vsse32_v = 415,
> - rv_op_vsse64_v = 416,
> - rv_op_vluxei8_v = 417,
> - rv_op_vluxei16_v = 418,
> - rv_op_vluxei32_v = 419,
> - rv_op_vluxei64_v = 420,
> - rv_op_vloxei8_v = 421,
> - rv_op_vloxei16_v = 422,
> - rv_op_vloxei32_v = 423,
> - rv_op_vloxei64_v = 424,
> - rv_op_vsuxei8_v = 425,
> - rv_op_vsuxei16_v = 426,
> - rv_op_vsuxei32_v = 427,
> - rv_op_vsuxei64_v = 428,
> - rv_op_vsoxei8_v = 429,
> - rv_op_vsoxei16_v = 430,
> - rv_op_vsoxei32_v = 431,
> - rv_op_vsoxei64_v = 432,
> - rv_op_vle8ff_v = 433,
> - rv_op_vle16ff_v = 434,
> - rv_op_vle32ff_v = 435,
> - rv_op_vle64ff_v = 436,
> - rv_op_vl1re8_v = 437,
> - rv_op_vl1re16_v = 438,
> - rv_op_vl1re32_v = 439,
> - rv_op_vl1re64_v = 440,
> - rv_op_vl2re8_v = 441,
> - rv_op_vl2re16_v = 442,
> - rv_op_vl2re32_v = 443,
> - rv_op_vl2re64_v = 444,
> - rv_op_vl4re8_v = 445,
> - rv_op_vl4re16_v = 446,
> - rv_op_vl4re32_v = 447,
> - rv_op_vl4re64_v = 448,
> - rv_op_vl8re8_v = 449,
> - rv_op_vl8re16_v = 450,
> - rv_op_vl8re32_v = 451,
> - rv_op_vl8re64_v = 452,
> - rv_op_vs1r_v = 453,
> - rv_op_vs2r_v = 454,
> - rv_op_vs4r_v = 455,
> - rv_op_vs8r_v = 456,
> - rv_op_vadd_vv = 457,
> - rv_op_vadd_vx = 458,
> - rv_op_vadd_vi = 459,
> - rv_op_vsub_vv = 460,
> - rv_op_vsub_vx = 461,
> - rv_op_vrsub_vx = 462,
> - rv_op_vrsub_vi = 463,
> - rv_op_vwaddu_vv = 464,
> - rv_op_vwaddu_vx = 465,
> - rv_op_vwadd_vv = 466,
> - rv_op_vwadd_vx = 467,
> - rv_op_vwsubu_vv = 468,
> - rv_op_vwsubu_vx = 469,
> - rv_op_vwsub_vv = 470,
> - rv_op_vwsub_vx = 471,
> - rv_op_vwaddu_wv = 472,
> - rv_op_vwaddu_wx = 473,
> - rv_op_vwadd_wv = 474,
> - rv_op_vwadd_wx = 475,
> - rv_op_vwsubu_wv = 476,
> - rv_op_vwsubu_wx = 477,
> - rv_op_vwsub_wv = 478,
> - rv_op_vwsub_wx = 479,
> - rv_op_vadc_vvm = 480,
> - rv_op_vadc_vxm = 481,
> - rv_op_vadc_vim = 482,
> - rv_op_vmadc_vvm = 483,
> - rv_op_vmadc_vxm = 484,
> - rv_op_vmadc_vim = 485,
> - rv_op_vsbc_vvm = 486,
> - rv_op_vsbc_vxm = 487,
> - rv_op_vmsbc_vvm = 488,
> - rv_op_vmsbc_vxm = 489,
> - rv_op_vand_vv = 490,
> - rv_op_vand_vx = 491,
> - rv_op_vand_vi = 492,
> - rv_op_vor_vv = 493,
> - rv_op_vor_vx = 494,
> - rv_op_vor_vi = 495,
> - rv_op_vxor_vv = 496,
> - rv_op_vxor_vx = 497,
> - rv_op_vxor_vi = 498,
> - rv_op_vsll_vv = 499,
> - rv_op_vsll_vx = 500,
> - rv_op_vsll_vi = 501,
> - rv_op_vsrl_vv = 502,
> - rv_op_vsrl_vx = 503,
> - rv_op_vsrl_vi = 504,
> - rv_op_vsra_vv = 505,
> - rv_op_vsra_vx = 506,
> - rv_op_vsra_vi = 507,
> - rv_op_vnsrl_wv = 508,
> - rv_op_vnsrl_wx = 509,
> - rv_op_vnsrl_wi = 510,
> - rv_op_vnsra_wv = 511,
> - rv_op_vnsra_wx = 512,
> - rv_op_vnsra_wi = 513,
> - rv_op_vmseq_vv = 514,
> - rv_op_vmseq_vx = 515,
> - rv_op_vmseq_vi = 516,
> - rv_op_vmsne_vv = 517,
> - rv_op_vmsne_vx = 518,
> - rv_op_vmsne_vi = 519,
> - rv_op_vmsltu_vv = 520,
> - rv_op_vmsltu_vx = 521,
> - rv_op_vmslt_vv = 522,
> - rv_op_vmslt_vx = 523,
> - rv_op_vmsleu_vv = 524,
> - rv_op_vmsleu_vx = 525,
> - rv_op_vmsleu_vi = 526,
> - rv_op_vmsle_vv = 527,
> - rv_op_vmsle_vx = 528,
> - rv_op_vmsle_vi = 529,
> - rv_op_vmsgtu_vx = 530,
> - rv_op_vmsgtu_vi = 531,
> - rv_op_vmsgt_vx = 532,
> - rv_op_vmsgt_vi = 533,
> - rv_op_vminu_vv = 534,
> - rv_op_vminu_vx = 535,
> - rv_op_vmin_vv = 536,
> - rv_op_vmin_vx = 537,
> - rv_op_vmaxu_vv = 538,
> - rv_op_vmaxu_vx = 539,
> - rv_op_vmax_vv = 540,
> - rv_op_vmax_vx = 541,
> - rv_op_vmul_vv = 542,
> - rv_op_vmul_vx = 543,
> - rv_op_vmulh_vv = 544,
> - rv_op_vmulh_vx = 545,
> - rv_op_vmulhu_vv = 546,
> - rv_op_vmulhu_vx = 547,
> - rv_op_vmulhsu_vv = 548,
> - rv_op_vmulhsu_vx = 549,
> - rv_op_vdivu_vv = 550,
> - rv_op_vdivu_vx = 551,
> - rv_op_vdiv_vv = 552,
> - rv_op_vdiv_vx = 553,
> - rv_op_vremu_vv = 554,
> - rv_op_vremu_vx = 555,
> - rv_op_vrem_vv = 556,
> - rv_op_vrem_vx = 557,
> - rv_op_vwmulu_vv = 558,
> - rv_op_vwmulu_vx = 559,
> - rv_op_vwmulsu_vv = 560,
> - rv_op_vwmulsu_vx = 561,
> - rv_op_vwmul_vv = 562,
> - rv_op_vwmul_vx = 563,
> - rv_op_vmacc_vv = 564,
> - rv_op_vmacc_vx = 565,
> - rv_op_vnmsac_vv = 566,
> - rv_op_vnmsac_vx = 567,
> - rv_op_vmadd_vv = 568,
> - rv_op_vmadd_vx = 569,
> - rv_op_vnmsub_vv = 570,
> - rv_op_vnmsub_vx = 571,
> - rv_op_vwmaccu_vv = 572,
> - rv_op_vwmaccu_vx = 573,
> - rv_op_vwmacc_vv = 574,
> - rv_op_vwmacc_vx = 575,
> - rv_op_vwmaccsu_vv = 576,
> - rv_op_vwmaccsu_vx = 577,
> - rv_op_vwmaccus_vx = 578,
> - rv_op_vmv_v_v = 579,
> - rv_op_vmv_v_x = 580,
> - rv_op_vmv_v_i = 581,
> - rv_op_vmerge_vvm = 582,
> - rv_op_vmerge_vxm = 583,
> - rv_op_vmerge_vim = 584,
> - rv_op_vsaddu_vv = 585,
> - rv_op_vsaddu_vx = 586,
> - rv_op_vsaddu_vi = 587,
> - rv_op_vsadd_vv = 588,
> - rv_op_vsadd_vx = 589,
> - rv_op_vsadd_vi = 590,
> - rv_op_vssubu_vv = 591,
> - rv_op_vssubu_vx = 592,
> - rv_op_vssub_vv = 593,
> - rv_op_vssub_vx = 594,
> - rv_op_vaadd_vv = 595,
> - rv_op_vaadd_vx = 596,
> - rv_op_vaaddu_vv = 597,
> - rv_op_vaaddu_vx = 598,
> - rv_op_vasub_vv = 599,
> - rv_op_vasub_vx = 600,
> - rv_op_vasubu_vv = 601,
> - rv_op_vasubu_vx = 602,
> - rv_op_vsmul_vv = 603,
> - rv_op_vsmul_vx = 604,
> - rv_op_vssrl_vv = 605,
> - rv_op_vssrl_vx = 606,
> - rv_op_vssrl_vi = 607,
> - rv_op_vssra_vv = 608,
> - rv_op_vssra_vx = 609,
> - rv_op_vssra_vi = 610,
> - rv_op_vnclipu_wv = 611,
> - rv_op_vnclipu_wx = 612,
> - rv_op_vnclipu_wi = 613,
> - rv_op_vnclip_wv = 614,
> - rv_op_vnclip_wx = 615,
> - rv_op_vnclip_wi = 616,
> - rv_op_vfadd_vv = 617,
> - rv_op_vfadd_vf = 618,
> - rv_op_vfsub_vv = 619,
> - rv_op_vfsub_vf = 620,
> - rv_op_vfrsub_vf = 621,
> - rv_op_vfwadd_vv = 622,
> - rv_op_vfwadd_vf = 623,
> - rv_op_vfwadd_wv = 624,
> - rv_op_vfwadd_wf = 625,
> - rv_op_vfwsub_vv = 626,
> - rv_op_vfwsub_vf = 627,
> - rv_op_vfwsub_wv = 628,
> - rv_op_vfwsub_wf = 629,
> - rv_op_vfmul_vv = 630,
> - rv_op_vfmul_vf = 631,
> - rv_op_vfdiv_vv = 632,
> - rv_op_vfdiv_vf = 633,
> - rv_op_vfrdiv_vf = 634,
> - rv_op_vfwmul_vv = 635,
> - rv_op_vfwmul_vf = 636,
> - rv_op_vfmacc_vv = 637,
> - rv_op_vfmacc_vf = 638,
> - rv_op_vfnmacc_vv = 639,
> - rv_op_vfnmacc_vf = 640,
> - rv_op_vfmsac_vv = 641,
> - rv_op_vfmsac_vf = 642,
> - rv_op_vfnmsac_vv = 643,
> - rv_op_vfnmsac_vf = 644,
> - rv_op_vfmadd_vv = 645,
> - rv_op_vfmadd_vf = 646,
> - rv_op_vfnmadd_vv = 647,
> - rv_op_vfnmadd_vf = 648,
> - rv_op_vfmsub_vv = 649,
> - rv_op_vfmsub_vf = 650,
> - rv_op_vfnmsub_vv = 651,
> - rv_op_vfnmsub_vf = 652,
> - rv_op_vfwmacc_vv = 653,
> - rv_op_vfwmacc_vf = 654,
> - rv_op_vfwnmacc_vv = 655,
> - rv_op_vfwnmacc_vf = 656,
> - rv_op_vfwmsac_vv = 657,
> - rv_op_vfwmsac_vf = 658,
> - rv_op_vfwnmsac_vv = 659,
> - rv_op_vfwnmsac_vf = 660,
> - rv_op_vfsqrt_v = 661,
> - rv_op_vfrsqrt7_v = 662,
> - rv_op_vfrec7_v = 663,
> - rv_op_vfmin_vv = 664,
> - rv_op_vfmin_vf = 665,
> - rv_op_vfmax_vv = 666,
> - rv_op_vfmax_vf = 667,
> - rv_op_vfsgnj_vv = 668,
> - rv_op_vfsgnj_vf = 669,
> - rv_op_vfsgnjn_vv = 670,
> - rv_op_vfsgnjn_vf = 671,
> - rv_op_vfsgnjx_vv = 672,
> - rv_op_vfsgnjx_vf = 673,
> - rv_op_vfslide1up_vf = 674,
> - rv_op_vfslide1down_vf = 675,
> - rv_op_vmfeq_vv = 676,
> - rv_op_vmfeq_vf = 677,
> - rv_op_vmfne_vv = 678,
> - rv_op_vmfne_vf = 679,
> - rv_op_vmflt_vv = 680,
> - rv_op_vmflt_vf = 681,
> - rv_op_vmfle_vv = 682,
> - rv_op_vmfle_vf = 683,
> - rv_op_vmfgt_vf = 684,
> - rv_op_vmfge_vf = 685,
> - rv_op_vfclass_v = 686,
> - rv_op_vfmerge_vfm = 687,
> - rv_op_vfmv_v_f = 688,
> - rv_op_vfcvt_xu_f_v = 689,
> - rv_op_vfcvt_x_f_v = 690,
> - rv_op_vfcvt_f_xu_v = 691,
> - rv_op_vfcvt_f_x_v = 692,
> - rv_op_vfcvt_rtz_xu_f_v = 693,
> - rv_op_vfcvt_rtz_x_f_v = 694,
> - rv_op_vfwcvt_xu_f_v = 695,
> - rv_op_vfwcvt_x_f_v = 696,
> - rv_op_vfwcvt_f_xu_v = 697,
> - rv_op_vfwcvt_f_x_v = 698,
> - rv_op_vfwcvt_f_f_v = 699,
> - rv_op_vfwcvt_rtz_xu_f_v = 700,
> - rv_op_vfwcvt_rtz_x_f_v = 701,
> - rv_op_vfncvt_xu_f_w = 702,
> - rv_op_vfncvt_x_f_w = 703,
> - rv_op_vfncvt_f_xu_w = 704,
> - rv_op_vfncvt_f_x_w = 705,
> - rv_op_vfncvt_f_f_w = 706,
> - rv_op_vfncvt_rod_f_f_w = 707,
> - rv_op_vfncvt_rtz_xu_f_w = 708,
> - rv_op_vfncvt_rtz_x_f_w = 709,
> - rv_op_vredsum_vs = 710,
> - rv_op_vredand_vs = 711,
> - rv_op_vredor_vs = 712,
> - rv_op_vredxor_vs = 713,
> - rv_op_vredminu_vs = 714,
> - rv_op_vredmin_vs = 715,
> - rv_op_vredmaxu_vs = 716,
> - rv_op_vredmax_vs = 717,
> - rv_op_vwredsumu_vs = 718,
> - rv_op_vwredsum_vs = 719,
> - rv_op_vfredusum_vs = 720,
> - rv_op_vfredosum_vs = 721,
> - rv_op_vfredmin_vs = 722,
> - rv_op_vfredmax_vs = 723,
> - rv_op_vfwredusum_vs = 724,
> - rv_op_vfwredosum_vs = 725,
> - rv_op_vmand_mm = 726,
> - rv_op_vmnand_mm = 727,
> - rv_op_vmandn_mm = 728,
> - rv_op_vmxor_mm = 729,
> - rv_op_vmor_mm = 730,
> - rv_op_vmnor_mm = 731,
> - rv_op_vmorn_mm = 732,
> - rv_op_vmxnor_mm = 733,
> - rv_op_vcpop_m = 734,
> - rv_op_vfirst_m = 735,
> - rv_op_vmsbf_m = 736,
> - rv_op_vmsif_m = 737,
> - rv_op_vmsof_m = 738,
> - rv_op_viota_m = 739,
> - rv_op_vid_v = 740,
> - rv_op_vmv_x_s = 741,
> - rv_op_vmv_s_x = 742,
> - rv_op_vfmv_f_s = 743,
> - rv_op_vfmv_s_f = 744,
> - rv_op_vslideup_vx = 745,
> - rv_op_vslideup_vi = 746,
> - rv_op_vslide1up_vx = 747,
> - rv_op_vslidedown_vx = 748,
> - rv_op_vslidedown_vi = 749,
> - rv_op_vslide1down_vx = 750,
> - rv_op_vrgather_vv = 751,
> - rv_op_vrgatherei16_vv = 752,
> - rv_op_vrgather_vx = 753,
> - rv_op_vrgather_vi = 754,
> - rv_op_vcompress_vm = 755,
> - rv_op_vmv1r_v = 756,
> - rv_op_vmv2r_v = 757,
> - rv_op_vmv4r_v = 758,
> - rv_op_vmv8r_v = 759,
> - rv_op_vzext_vf2 = 760,
> - rv_op_vzext_vf4 = 761,
> - rv_op_vzext_vf8 = 762,
> - rv_op_vsext_vf2 = 763,
> - rv_op_vsext_vf4 = 764,
> - rv_op_vsext_vf8 = 765,
> - rv_op_vsetvli = 766,
> - rv_op_vsetivli = 767,
> - rv_op_vsetvl = 768,
> - rv_op_c_zext_b = 769,
> - rv_op_c_sext_b = 770,
> - rv_op_c_zext_h = 771,
> - rv_op_c_sext_h = 772,
> - rv_op_c_zext_w = 773,
> - rv_op_c_not = 774,
> - rv_op_c_mul = 775,
> - rv_op_c_lbu = 776,
> - rv_op_c_lhu = 777,
> - rv_op_c_lh = 778,
> - rv_op_c_sb = 779,
> - rv_op_c_sh = 780,
> - rv_op_cm_push = 781,
> - rv_op_cm_pop = 782,
> - rv_op_cm_popret = 783,
> - rv_op_cm_popretz = 784,
> - rv_op_cm_mva01s = 785,
> - rv_op_cm_mvsa01 = 786,
> - rv_op_cm_jt = 787,
> - rv_op_cm_jalt = 788,
> - rv_op_czero_eqz = 789,
> - rv_op_czero_nez = 790,
> - rv_op_fcvt_bf16_s = 791,
> - rv_op_fcvt_s_bf16 = 792,
> - rv_op_vfncvtbf16_f_f_w = 793,
> - rv_op_vfwcvtbf16_f_f_v = 794,
> - rv_op_vfwmaccbf16_vv = 795,
> - rv_op_vfwmaccbf16_vf = 796,
> - rv_op_flh = 797,
> - rv_op_fsh = 798,
> - rv_op_fmv_h_x = 799,
> - rv_op_fmv_x_h = 800,
> - rv_op_fli_s = 801,
> - rv_op_fli_d = 802,
> - rv_op_fli_q = 803,
> - rv_op_fli_h = 804,
> - rv_op_fminm_s = 805,
> - rv_op_fmaxm_s = 806,
> - rv_op_fminm_d = 807,
> - rv_op_fmaxm_d = 808,
> - rv_op_fminm_q = 809,
> - rv_op_fmaxm_q = 810,
> - rv_op_fminm_h = 811,
> - rv_op_fmaxm_h = 812,
> - rv_op_fround_s = 813,
> - rv_op_froundnx_s = 814,
> - rv_op_fround_d = 815,
> - rv_op_froundnx_d = 816,
> - rv_op_fround_q = 817,
> - rv_op_froundnx_q = 818,
> - rv_op_fround_h = 819,
> - rv_op_froundnx_h = 820,
> - rv_op_fcvtmod_w_d = 821,
> - rv_op_fmvh_x_d = 822,
> - rv_op_fmvp_d_x = 823,
> - rv_op_fmvh_x_q = 824,
> - rv_op_fmvp_q_x = 825,
> - rv_op_fleq_s = 826,
> - rv_op_fltq_s = 827,
> - rv_op_fleq_d = 828,
> - rv_op_fltq_d = 829,
> - rv_op_fleq_q = 830,
> - rv_op_fltq_q = 831,
> - rv_op_fleq_h = 832,
> - rv_op_fltq_h = 833,
> - rv_op_vaesdf_vv = 834,
> - rv_op_vaesdf_vs = 835,
> - rv_op_vaesdm_vv = 836,
> - rv_op_vaesdm_vs = 837,
> - rv_op_vaesef_vv = 838,
> - rv_op_vaesef_vs = 839,
> - rv_op_vaesem_vv = 840,
> - rv_op_vaesem_vs = 841,
> - rv_op_vaeskf1_vi = 842,
> - rv_op_vaeskf2_vi = 843,
> - rv_op_vaesz_vs = 844,
> - rv_op_vandn_vv = 845,
> - rv_op_vandn_vx = 846,
> - rv_op_vbrev_v = 847,
> - rv_op_vbrev8_v = 848,
> - rv_op_vclmul_vv = 849,
> - rv_op_vclmul_vx = 850,
> - rv_op_vclmulh_vv = 851,
> - rv_op_vclmulh_vx = 852,
> - rv_op_vclz_v = 853,
> - rv_op_vcpop_v = 854,
> - rv_op_vctz_v = 855,
> - rv_op_vghsh_vv = 856,
> - rv_op_vgmul_vv = 857,
> - rv_op_vrev8_v = 858,
> - rv_op_vrol_vv = 859,
> - rv_op_vrol_vx = 860,
> - rv_op_vror_vv = 861,
> - rv_op_vror_vx = 862,
> - rv_op_vror_vi = 863,
> - rv_op_vsha2ch_vv = 864,
> - rv_op_vsha2cl_vv = 865,
> - rv_op_vsha2ms_vv = 866,
> - rv_op_vsm3c_vi = 867,
> - rv_op_vsm3me_vv = 868,
> - rv_op_vsm4k_vi = 869,
> - rv_op_vsm4r_vv = 870,
> - rv_op_vsm4r_vs = 871,
> - rv_op_vwsll_vv = 872,
> - rv_op_vwsll_vx = 873,
> - rv_op_vwsll_vi = 874,
> - rv_op_amocas_w = 875,
> - rv_op_amocas_d = 876,
> - rv_op_amocas_q = 877,
> - rv_mop_r_0 = 878,
> - rv_mop_r_1 = 879,
> - rv_mop_r_2 = 880,
> - rv_mop_r_3 = 881,
> - rv_mop_r_4 = 882,
> - rv_mop_r_5 = 883,
> - rv_mop_r_6 = 884,
> - rv_mop_r_7 = 885,
> - rv_mop_r_8 = 886,
> - rv_mop_r_9 = 887,
> - rv_mop_r_10 = 888,
> - rv_mop_r_11 = 889,
> - rv_mop_r_12 = 890,
> - rv_mop_r_13 = 891,
> - rv_mop_r_14 = 892,
> - rv_mop_r_15 = 893,
> - rv_mop_r_16 = 894,
> - rv_mop_r_17 = 895,
> - rv_mop_r_18 = 896,
> - rv_mop_r_19 = 897,
> - rv_mop_r_20 = 898,
> - rv_mop_r_21 = 899,
> - rv_mop_r_22 = 900,
> - rv_mop_r_23 = 901,
> - rv_mop_r_24 = 902,
> - rv_mop_r_25 = 903,
> - rv_mop_r_26 = 904,
> - rv_mop_r_27 = 905,
> - rv_mop_r_28 = 906,
> - rv_mop_r_29 = 907,
> - rv_mop_r_30 = 908,
> - rv_mop_r_31 = 909,
> - rv_mop_rr_0 = 910,
> - rv_mop_rr_1 = 911,
> - rv_mop_rr_2 = 912,
> - rv_mop_rr_3 = 913,
> - rv_mop_rr_4 = 914,
> - rv_mop_rr_5 = 915,
> - rv_mop_rr_6 = 916,
> - rv_mop_rr_7 = 917,
> - rv_c_mop_1 = 918,
> - rv_c_mop_3 = 919,
> - rv_c_mop_5 = 920,
> - rv_c_mop_7 = 921,
> - rv_c_mop_9 = 922,
> - rv_c_mop_11 = 923,
> - rv_c_mop_13 = 924,
> - rv_c_mop_15 = 925,
> - rv_op_amoswap_b = 926,
> - rv_op_amoadd_b = 927,
> - rv_op_amoxor_b = 928,
> - rv_op_amoor_b = 929,
> - rv_op_amoand_b = 930,
> - rv_op_amomin_b = 931,
> - rv_op_amomax_b = 932,
> - rv_op_amominu_b = 933,
> - rv_op_amomaxu_b = 934,
> - rv_op_amoswap_h = 935,
> - rv_op_amoadd_h = 936,
> - rv_op_amoxor_h = 937,
> - rv_op_amoor_h = 938,
> - rv_op_amoand_h = 939,
> - rv_op_amomin_h = 940,
> - rv_op_amomax_h = 941,
> - rv_op_amominu_h = 942,
> - rv_op_amomaxu_h = 943,
> - rv_op_amocas_b = 944,
> - rv_op_amocas_h = 945,
> - rv_op_wrs_sto = 946,
> - rv_op_wrs_nto = 947,
> - rv_op_lpad = 948,
> - rv_op_sspush = 949,
> - rv_op_sspopchk = 950,
> - rv_op_ssrdp = 951,
> - rv_op_ssamoswap_w = 952,
> - rv_op_ssamoswap_d = 953,
> - rv_op_c_sspush = 954,
> - rv_op_c_sspopchk = 955,
> - rv_op_cbo_inval = 956,
> - rv_op_cbo_clean = 957,
> - rv_op_cbo_flush = 958,
> - rv_op_cbo_zero = 959,
> - rv_op_mnret = 960,
> +#define OP(N, ...) rv_op_##N,
> +#include "riscv-op.c.inc"
> +#undef OP
> } rv_op;
>
> /* register names */
> @@ -1601,967 +646,9 @@ static uint32_t operand_lpl(rv_inst inst)
> /* instruction metadata */
>
> static const rv_opcode_data rvi_opcode_data[] = {
> - { "illegal", rv_codec_none, rv_fmt_none },
> - { "lui", rv_codec_u, rv_fmt_rd_uimm },
> - { "auipc", rv_codec_u, rv_fmt_rd_uoffset },
> - { "jal", rv_codec_uj, rv_fmt_rd_offset, rvcp_jal },
> - { "jalr", rv_codec_i, rv_fmt_rd_rs1_offset, rvcp_jalr },
> - { "beq", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_beq },
> - { "bne", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_bne },
> - { "blt", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_blt },
> - { "bge", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_bge },
> - { "bltu", rv_codec_sb, rv_fmt_rs1_rs2_offset },
> - { "bgeu", rv_codec_sb, rv_fmt_rs1_rs2_offset },
> - { "lb", rv_codec_i, rv_fmt_rd_offset_rs1 },
> - { "lh", rv_codec_i, rv_fmt_rd_offset_rs1 },
> - { "lw", rv_codec_i, rv_fmt_rd_offset_rs1 },
> - { "lbu", rv_codec_i, rv_fmt_rd_offset_rs1 },
> - { "lhu", rv_codec_i, rv_fmt_rd_offset_rs1 },
> - { "sb", rv_codec_s, rv_fmt_rs2_offset_rs1 },
> - { "sh", rv_codec_s, rv_fmt_rs2_offset_rs1 },
> - { "sw", rv_codec_s, rv_fmt_rs2_offset_rs1 },
> - { "addi", rv_codec_i, rv_fmt_rd_rs1_imm, rvcp_addi },
> - { "slti", rv_codec_i, rv_fmt_rd_rs1_imm },
> - { "sltiu", rv_codec_i, rv_fmt_rd_rs1_imm, rvcp_sltiu },
> - { "xori", rv_codec_i, rv_fmt_rd_rs1_imm, rvcp_xori },
> - { "ori", rv_codec_i, rv_fmt_rd_rs1_imm },
> - { "andi", rv_codec_i, rv_fmt_rd_rs1_imm },
> - { "slli", rv_codec_i_sh7, rv_fmt_rd_rs1_imm },
> - { "srli", rv_codec_i_sh7, rv_fmt_rd_rs1_imm },
> - { "srai", rv_codec_i_sh7, rv_fmt_rd_rs1_imm },
> - { "add", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> - { "sub", rv_codec_r, rv_fmt_rd_rs1_rs2, rvcp_sub },
> - { "sll", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> - { "slt", rv_codec_r, rv_fmt_rd_rs1_rs2, rvcp_slt },
> - { "sltu", rv_codec_r, rv_fmt_rd_rs1_rs2, rvcp_sltu },
> - { "xor", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> - { "srl", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> - { "sra", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> - { "or", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> - { "and", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> - { "fence", rv_codec_r_f, rv_fmt_pred_succ },
> - { "fence.i", rv_codec_none, rv_fmt_none },
> - { "lwu", rv_codec_i, rv_fmt_rd_offset_rs1 },
> - { "ld", rv_codec_i, rv_fmt_rd_offset_rs1 },
> - { "sd", rv_codec_s, rv_fmt_rs2_offset_rs1 },
> - { "addiw", rv_codec_i, rv_fmt_rd_rs1_imm, rvcp_addiw },
> - { "slliw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm },
> - { "srliw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm },
> - { "sraiw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm },
> - { "addw", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> - { "subw", rv_codec_r, rv_fmt_rd_rs1_rs2, rvcp_subw },
> - { "sllw", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> - { "srlw", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> - { "sraw", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> - { "ldu", rv_codec_i, rv_fmt_rd_offset_rs1 },
> - { "lq", rv_codec_i, rv_fmt_rd_offset_rs1 },
> - { "sq", rv_codec_s, rv_fmt_rs2_offset_rs1 },
> - { "addid", rv_codec_i, rv_fmt_rd_rs1_imm },
> - { "sllid", rv_codec_i_sh6, rv_fmt_rd_rs1_imm },
> - { "srlid", rv_codec_i_sh6, rv_fmt_rd_rs1_imm },
> - { "sraid", rv_codec_i_sh6, rv_fmt_rd_rs1_imm },
> - { "addd", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> - { "subd", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> - { "slld", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> - { "srld", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> - { "srad", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> - { "mul", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> - { "mulh", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> - { "mulhsu", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> - { "mulhu", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> - { "div", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> - { "divu", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> - { "rem", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> - { "remu", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> - { "mulw", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> - { "divw", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> - { "divuw", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> - { "remw", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> - { "remuw", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> - { "muld", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> - { "divd", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> - { "divud", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> - { "remd", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> - { "remud", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> - { "lr.w", rv_codec_r_l, rv_fmt_aqrl_rd_rs1 },
> - { "sc.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
> - { "amoswap.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
> - { "amoadd.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
> - { "amoxor.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
> - { "amoor.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
> - { "amoand.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
> - { "amomin.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
> - { "amomax.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
> - { "amominu.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
> - { "amomaxu.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
> - { "lr.d", rv_codec_r_l, rv_fmt_aqrl_rd_rs1 },
> - { "sc.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
> - { "amoswap.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
> - { "amoadd.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
> - { "amoxor.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
> - { "amoor.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
> - { "amoand.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
> - { "amomin.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
> - { "amomax.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
> - { "amominu.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
> - { "amomaxu.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
> - { "lr.q", rv_codec_r_l, rv_fmt_aqrl_rd_rs1 },
> - { "sc.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
> - { "amoswap.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
> - { "amoadd.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
> - { "amoxor.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
> - { "amoor.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
> - { "amoand.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
> - { "amomin.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
> - { "amomax.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
> - { "amominu.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
> - { "amomaxu.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
> - { "ecall", rv_codec_none, rv_fmt_none },
> - { "ebreak", rv_codec_none, rv_fmt_none },
> - { "uret", rv_codec_none, rv_fmt_none },
> - { "sret", rv_codec_none, rv_fmt_none },
> - { "hret", rv_codec_none, rv_fmt_none },
> - { "mret", rv_codec_none, rv_fmt_none },
> - { "dret", rv_codec_none, rv_fmt_none },
> - { "sfence.vm", rv_codec_r, rv_fmt_rs1 },
> - { "sfence.vma", rv_codec_r, rv_fmt_rs1_rs2 },
> - { "wfi", rv_codec_none, rv_fmt_none },
> - { "csrrw", rv_codec_i_csr, rv_fmt_rd_csr_rs1 },
> - { "csrrs", rv_codec_i_csr, rv_fmt_rd_csr_rs1 },
> - { "csrrc", rv_codec_i_csr, rv_fmt_rd_csr_rs1 },
> - { "csrrwi", rv_codec_i_csr, rv_fmt_rd_csr_zimm },
> - { "csrrsi", rv_codec_i_csr, rv_fmt_rd_csr_zimm },
> - { "csrrci", rv_codec_i_csr, rv_fmt_rd_csr_zimm },
> - { "flw", rv_codec_i, rv_fmt_frd_offset_rs1 },
> - { "fsw", rv_codec_s, rv_fmt_frs2_offset_rs1 },
> - { "fmadd.s", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3 },
> - { "fmsub.s", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3 },
> - { "fnmsub.s", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3 },
> - { "fnmadd.s", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3 },
> - { "fadd.s", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2 },
> - { "fsub.s", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2 },
> - { "fmul.s", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2 },
> - { "fdiv.s", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2 },
> - { "fsgnj.s", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnj_s },
> - { "fsgnjn.s", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjn_s },
> - { "fsgnjx.s", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjx_s },
> - { "fmin.s", rv_codec_r, rv_fmt_frd_frs1_frs2 },
> - { "fmax.s", rv_codec_r, rv_fmt_frd_frs1_frs2 },
> - { "fsqrt.s", rv_codec_r_m, rv_fmt_rm_frd_frs1 },
> - { "fle.s", rv_codec_r, rv_fmt_rd_frs1_frs2 },
> - { "flt.s", rv_codec_r, rv_fmt_rd_frs1_frs2 },
> - { "feq.s", rv_codec_r, rv_fmt_rd_frs1_frs2 },
> - { "fcvt.w.s", rv_codec_r_m, rv_fmt_rm_rd_frs1 },
> - { "fcvt.wu.s", rv_codec_r_m, rv_fmt_rm_rd_frs1 },
> - { "fcvt.s.w", rv_codec_r_m, rv_fmt_rm_frd_rs1 },
> - { "fcvt.s.wu", rv_codec_r_m, rv_fmt_rm_frd_rs1 },
> - { "fmv.x.s", rv_codec_r, rv_fmt_rd_frs1 },
> - { "fclass.s", rv_codec_r, rv_fmt_rd_frs1 },
> - { "fmv.s.x", rv_codec_r, rv_fmt_frd_rs1 },
> - { "fcvt.l.s", rv_codec_r_m, rv_fmt_rm_rd_frs1 },
> - { "fcvt.lu.s", rv_codec_r_m, rv_fmt_rm_rd_frs1 },
> - { "fcvt.s.l", rv_codec_r_m, rv_fmt_rm_frd_rs1 },
> - { "fcvt.s.lu", rv_codec_r_m, rv_fmt_rm_frd_rs1 },
> - { "fld", rv_codec_i, rv_fmt_frd_offset_rs1 },
> - { "fsd", rv_codec_s, rv_fmt_frs2_offset_rs1 },
> - { "fmadd.d", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3 },
> - { "fmsub.d", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3 },
> - { "fnmsub.d", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3 },
> - { "fnmadd.d", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3 },
> - { "fadd.d", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2 },
> - { "fsub.d", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2 },
> - { "fmul.d", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2 },
> - { "fdiv.d", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2 },
> - { "fsgnj.d", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnj_d },
> - { "fsgnjn.d", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjn_d },
> - { "fsgnjx.d", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjx_d },
> - { "fmin.d", rv_codec_r, rv_fmt_frd_frs1_frs2 },
> - { "fmax.d", rv_codec_r, rv_fmt_frd_frs1_frs2 },
> - { "fcvt.s.d", rv_codec_r_m, rv_fmt_rm_frd_frs1 },
> - { "fcvt.d.s", rv_codec_r_m, rv_fmt_rm_frd_frs1 },
> - { "fsqrt.d", rv_codec_r_m, rv_fmt_rm_frd_frs1 },
> - { "fle.d", rv_codec_r, rv_fmt_rd_frs1_frs2 },
> - { "flt.d", rv_codec_r, rv_fmt_rd_frs1_frs2 },
> - { "feq.d", rv_codec_r, rv_fmt_rd_frs1_frs2 },
> - { "fcvt.w.d", rv_codec_r_m, rv_fmt_rm_rd_frs1 },
> - { "fcvt.wu.d", rv_codec_r_m, rv_fmt_rm_rd_frs1 },
> - { "fcvt.d.w", rv_codec_r_m, rv_fmt_rm_frd_rs1 },
> - { "fcvt.d.wu", rv_codec_r_m, rv_fmt_rm_frd_rs1 },
> - { "fclass.d", rv_codec_r, rv_fmt_rd_frs1 },
> - { "fcvt.l.d", rv_codec_r_m, rv_fmt_rm_rd_frs1 },
> - { "fcvt.lu.d", rv_codec_r_m, rv_fmt_rm_rd_frs1 },
> - { "fmv.x.d", rv_codec_r, rv_fmt_rd_frs1 },
> - { "fcvt.d.l", rv_codec_r_m, rv_fmt_rm_frd_rs1 },
> - { "fcvt.d.lu", rv_codec_r_m, rv_fmt_rm_frd_rs1 },
> - { "fmv.d.x", rv_codec_r, rv_fmt_frd_rs1 },
> - { "flq", rv_codec_i, rv_fmt_frd_offset_rs1 },
> - { "fsq", rv_codec_s, rv_fmt_frs2_offset_rs1 },
> - { "fmadd.q", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3 },
> - { "fmsub.q", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3 },
> - { "fnmsub.q", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3 },
> - { "fnmadd.q", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3 },
> - { "fadd.q", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2 },
> - { "fsub.q", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2 },
> - { "fmul.q", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2 },
> - { "fdiv.q", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2 },
> - { "fsgnj.q", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnj_q },
> - { "fsgnjn.q", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjn_q },
> - { "fsgnjx.q", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjx_q },
> - { "fmin.q", rv_codec_r, rv_fmt_frd_frs1_frs2 },
> - { "fmax.q", rv_codec_r, rv_fmt_frd_frs1_frs2 },
> - { "fcvt.s.q", rv_codec_r_m, rv_fmt_rm_frd_frs1 },
> - { "fcvt.q.s", rv_codec_r_m, rv_fmt_rm_frd_frs1 },
> - { "fcvt.d.q", rv_codec_r_m, rv_fmt_rm_frd_frs1 },
> - { "fcvt.q.d", rv_codec_r_m, rv_fmt_rm_frd_frs1 },
> - { "fsqrt.q", rv_codec_r_m, rv_fmt_rm_frd_frs1 },
> - { "fle.q", rv_codec_r, rv_fmt_rd_frs1_frs2 },
> - { "flt.q", rv_codec_r, rv_fmt_rd_frs1_frs2 },
> - { "feq.q", rv_codec_r, rv_fmt_rd_frs1_frs2 },
> - { "fcvt.w.q", rv_codec_r_m, rv_fmt_rm_rd_frs1 },
> - { "fcvt.wu.q", rv_codec_r_m, rv_fmt_rm_rd_frs1 },
> - { "fcvt.q.w", rv_codec_r_m, rv_fmt_rm_frd_rs1 },
> - { "fcvt.q.wu", rv_codec_r_m, rv_fmt_rm_frd_rs1 },
> - { "fclass.q", rv_codec_r, rv_fmt_rd_frs1 },
> - { "fcvt.l.q", rv_codec_r_m, rv_fmt_rm_rd_frs1 },
> - { "fcvt.lu.q", rv_codec_r_m, rv_fmt_rm_rd_frs1 },
> - { "fcvt.q.l", rv_codec_r_m, rv_fmt_rm_frd_rs1 },
> - { "fcvt.q.lu", rv_codec_r_m, rv_fmt_rm_frd_rs1 },
> - { "fmv.x.q", rv_codec_r, rv_fmt_rd_frs1 },
> - { "fmv.q.x", rv_codec_r, rv_fmt_frd_rs1 },
> - { "c.addi4spn", rv_codec_ciw_4spn, NULL, DECOMP(rv_op_addi) },
> - { "c.fld", rv_codec_cl_ld, NULL, DECOMP(rv_op_fld) },
> - { "c.lw", rv_codec_cl_lw, NULL, DECOMP(rv_op_lw) },
> - { "c.flw", rv_codec_cl_lw, NULL, DECOMP(rv_op_flw) },
> - { "c.fsd", rv_codec_cs_sd, NULL, DECOMP(rv_op_fsd) },
> - { "c.sw", rv_codec_cs_sw, NULL, DECOMP(rv_op_sw) },
> - { "c.fsw", rv_codec_cs_sw, NULL, DECOMP(rv_op_fsw) },
> - { },
> - { "c.addi", rv_codec_ci, NULL, DECOMP(rv_op_addi) },
> - { "c.jal", rv_codec_cj_jal, NULL, DECOMP(rv_op_jal) },
> - { "c.li", rv_codec_ci_li, NULL, DECOMP(rv_op_addi) },
> - { "c.addi16sp", rv_codec_ci_16sp, NULL, DECOMP(rv_op_addi) },
> - { "c.lui", rv_codec_ci_lui, NULL, DECOMP(rv_op_lui) },
> - { "c.srli", rv_codec_cb_sh6, NULL, DECOMP(rv_op_srli) },
> - { "c.srai", rv_codec_cb_sh6, NULL, DECOMP(rv_op_srai) },
> - { "c.andi", rv_codec_cb_imm, NULL, DECOMP(rv_op_andi) },
> - { "c.sub", rv_codec_cs, NULL, DECOMP(rv_op_sub) },
> - { "c.xor", rv_codec_cs, NULL, DECOMP(rv_op_xor) },
> - { "c.or", rv_codec_cs, NULL, DECOMP(rv_op_or) },
> - { "c.and", rv_codec_cs, NULL, DECOMP(rv_op_and) },
> - { "c.subw", rv_codec_cs, NULL, DECOMP(rv_op_subw) },
> - { "c.addw", rv_codec_cs, NULL, DECOMP(rv_op_addw) },
> - { "c.j", rv_codec_cj, NULL, DECOMP(rv_op_j) },
> - { "c.beqz", rv_codec_cb, NULL, DECOMP(rv_op_beqz) },
> - { "c.bnez", rv_codec_cb, NULL, DECOMP(rv_op_bnez) },
> - { "c.slli", rv_codec_ci_sh6, NULL, DECOMP(rv_op_slli) },
> - { "c.fldsp", rv_codec_ci_ldsp, NULL, DECOMP(rv_op_fld) },
> - { "c.lwsp", rv_codec_ci_lwsp, NULL, DECOMP(rv_op_lw) },
> - { "c.flwsp", rv_codec_ci_lwsp, NULL, DECOMP(rv_op_flw) },
> - { "c.jr", rv_codec_cr_jr, NULL, DECOMP(rv_op_jr) },
> - { "c.mv", rv_codec_cr_mv, NULL, DECOMP(rv_op_mv) },
> - { "c.ebreak", rv_codec_ci_none, NULL, DECOMP(rv_op_ebreak) },
> - { "c.jalr", rv_codec_cr_jalr, NULL, DECOMP(rv_op_jalr) },
> - { "c.add", rv_codec_cr, NULL, DECOMP(rv_op_add) },
> - { "c.fsdsp", rv_codec_css_sdsp, NULL, DECOMP(rv_op_fsd) },
> - { "c.swsp", rv_codec_css_swsp, NULL, DECOMP(rv_op_sw) },
> - { "c.fswsp", rv_codec_css_swsp, NULL, DECOMP(rv_op_fsw) },
> - { "c.ld", rv_codec_cl_ld, NULL, DECOMP(rv_op_ld) },
> - { "c.sd", rv_codec_cs_sd, NULL, DECOMP(rv_op_sd) },
> - { "c.addiw", rv_codec_ci, NULL, DECOMP(rv_op_addiw) },
> - { "c.ldsp", rv_codec_ci_ldsp, NULL, DECOMP(rv_op_ld) },
> - { "c.sdsp", rv_codec_css_sdsp, NULL, DECOMP(rv_op_sd) },
> - { "c.lq", rv_codec_cl_lq, NULL, DECOMP(rv_op_lq) },
> - { "c.sq", rv_codec_cs_sq, NULL, DECOMP(rv_op_sq) },
> - { "c.lqsp", rv_codec_ci_lqsp, NULL, DECOMP(rv_op_lq) },
> - { "c.sqsp", rv_codec_css_sqsp, NULL, DECOMP(rv_op_sq) },
> - { "nop", rv_codec_illegal, rv_fmt_none },
> - { "mv", rv_codec_illegal, rv_fmt_rd_rs1, rvcp_mv },
> - { "not", rv_codec_illegal, rv_fmt_rd_rs1 },
> - { "neg", rv_codec_illegal, rv_fmt_rd_rs2 },
> - { "negw", rv_codec_illegal, rv_fmt_rd_rs2 },
> - { "sext.w", rv_codec_illegal, rv_fmt_rd_rs1 },
> - { "seqz", rv_codec_illegal, rv_fmt_rd_rs1 },
> - { "snez", rv_codec_illegal, rv_fmt_rd_rs2 },
> - { "sltz", rv_codec_illegal, rv_fmt_rd_rs1 },
> - { "sgtz", rv_codec_illegal, rv_fmt_rd_rs2 },
> - { "fmv.s", rv_codec_illegal, rv_fmt_frd_frs1 },
> - { "fabs.s", rv_codec_illegal, rv_fmt_frd_frs1 },
> - { "fneg.s", rv_codec_illegal, rv_fmt_frd_frs1 },
> - { "fmv.d", rv_codec_illegal, rv_fmt_frd_frs1 },
> - { "fabs.d", rv_codec_illegal, rv_fmt_frd_frs1 },
> - { "fneg.d", rv_codec_illegal, rv_fmt_frd_frs1 },
> - { "fmv.q", rv_codec_illegal, rv_fmt_frd_frs1 },
> - { "fabs.q", rv_codec_illegal, rv_fmt_frd_frs1 },
> - { "fneg.q", rv_codec_illegal, rv_fmt_frd_frs1 },
> - { "beqz", rv_codec_illegal, rv_fmt_rs1_offset },
> - { "bnez", rv_codec_illegal, rv_fmt_rs1_offset },
> - { "blez", rv_codec_illegal, rv_fmt_rs2_offset },
> - { "bgez", rv_codec_illegal, rv_fmt_rs1_offset },
> - { "bltz", rv_codec_illegal, rv_fmt_rs1_offset },
> - { "bgtz", rv_codec_illegal, rv_fmt_rs2_offset },
> - { "jal", rv_codec_illegal, rv_fmt_offset }, /* rv_op_jal_ra */
> - { "jalr", rv_codec_illegal, rv_fmt_rs1 }, /* rv_op_jalr_ra */
> - { },
> - { },
> - { "j", rv_codec_illegal, rv_fmt_offset },
> - { "ret", rv_codec_illegal, rv_fmt_none },
> - { "jr", rv_codec_illegal, rv_fmt_rs1, rvcp_jr },
> - { "rdcycle", rv_codec_i_csr, rv_fmt_rd },
> - { "rdtime", rv_codec_i_csr, rv_fmt_rd },
> - { "rdinstret", rv_codec_i_csr, rv_fmt_rd },
> - { "rdcycleh", rv_codec_i_csr, rv_fmt_rd },
> - { "rdtimeh", rv_codec_i_csr, rv_fmt_rd },
> - { "rdinstreth", rv_codec_i_csr, rv_fmt_rd },
> - { "frcsr", rv_codec_i_csr, rv_fmt_rd },
> - { "frrm", rv_codec_i_csr, rv_fmt_rd },
> - { "frflags", rv_codec_i_csr, rv_fmt_rd },
> - { "fscsr", rv_codec_i_csr, rv_fmt_rd_rs1 },
> - { "fsrm", rv_codec_i_csr, rv_fmt_rd_rs1 },
> - { "fsflags", rv_codec_i_csr, rv_fmt_rd_rs1 },
> - { "fsrmi", rv_codec_i_csr, rv_fmt_rd_zimm },
> - { "fsflagsi", rv_codec_i_csr, rv_fmt_rd_zimm },
> - { "bseti", rv_codec_i_sh7, rv_fmt_rd_rs1_imm },
> - { "bclri", rv_codec_i_sh7, rv_fmt_rd_rs1_imm },
> - { "binvi", rv_codec_i_sh7, rv_fmt_rd_rs1_imm },
> - { "bexti", rv_codec_i_sh7, rv_fmt_rd_rs1_imm },
> - { "rori", rv_codec_i_sh7, rv_fmt_rd_rs1_imm },
> - { "clz", rv_codec_r, rv_fmt_rd_rs1 },
> - { "ctz", rv_codec_r, rv_fmt_rd_rs1 },
> - { "cpop", rv_codec_r, rv_fmt_rd_rs1 },
> - { "sext.h", rv_codec_r, rv_fmt_rd_rs1 },
> - { "sext.b", rv_codec_r, rv_fmt_rd_rs1 },
> - { "xnor", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> - { "orn", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> - { "andn", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> - { "rol", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> - { "ror", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> - { "sh1add", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> - { "sh2add", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> - { "sh3add", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> - { "sh1add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> - { "sh2add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> - { "sh3add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> - { "clmul", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> - { "clmulr", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> - { "clmulh", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> - { "min", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> - { "minu", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> - { "max", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> - { "maxu", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> - { "clzw", rv_codec_r, rv_fmt_rd_rs1 },
> - { "ctzw", rv_codec_r, rv_fmt_rd_rs1 },
> - { "cpopw", rv_codec_r, rv_fmt_rd_rs1 },
> - { "slli.uw", rv_codec_i_sh6, rv_fmt_rd_rs1_imm },
> - { "add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> - { "rolw", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> - { "rorw", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> - { "rev8", rv_codec_r, rv_fmt_rd_rs1 },
> - { "zext.h", rv_codec_r, rv_fmt_rd_rs1 },
> - { "roriw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm },
> - { "orc.b", rv_codec_r, rv_fmt_rd_rs1 },
> - { "bset", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> - { "bclr", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> - { "binv", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> - { "bext", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> - { "aes32esmi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs },
> - { "aes32esi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs },
> - { "aes32dsmi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs },
> - { "aes32dsi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs },
> - { "aes64ks1i", rv_codec_k_rnum, rv_fmt_rd_rs1_rnum },
> - { "aes64ks2", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> - { "aes64im", rv_codec_r, rv_fmt_rd_rs1 },
> - { "aes64esm", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> - { "aes64es", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> - { "aes64dsm", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> - { "aes64ds", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> - { "sha256sig0", rv_codec_r, rv_fmt_rd_rs1 },
> - { "sha256sig1", rv_codec_r, rv_fmt_rd_rs1 },
> - { "sha256sum0", rv_codec_r, rv_fmt_rd_rs1 },
> - { "sha256sum1", rv_codec_r, rv_fmt_rd_rs1 },
> - { "sha512sig0", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> - { "sha512sig1", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> - { "sha512sum0", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> - { "sha512sum1", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> - { "sha512sum0r", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> - { "sha512sum1r", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> - { "sha512sig0l", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> - { "sha512sig0h", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> - { "sha512sig1l", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> - { "sha512sig1h", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> - { "sm3p0", rv_codec_r, rv_fmt_rd_rs1 },
> - { "sm3p1", rv_codec_r, rv_fmt_rd_rs1 },
> - { "sm4ed", rv_codec_k_bs, rv_fmt_rs1_rs2_bs },
> - { "sm4ks", rv_codec_k_bs, rv_fmt_rs1_rs2_bs },
> - { "brev8", rv_codec_r, rv_fmt_rd_rs1 },
> - { "pack", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> - { "packh", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> - { "packw", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> - { "unzip", rv_codec_r, rv_fmt_rd_rs1 },
> - { "zip", rv_codec_r, rv_fmt_rd_rs1 },
> - { "xperm4", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> - { "xperm8", rv_codec_r, rv_fmt_rd_rs1 },
> - { "vle8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
> - { "vle16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
> - { "vle32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
> - { "vle64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
> - { "vse8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
> - { "vse16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
> - { "vse32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
> - { "vse64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
> - { "vlm.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
> - { "vsm.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
> - { "vlse8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm },
> - { "vlse16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm },
> - { "vlse32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm },
> - { "vlse64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm },
> - { "vsse8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm },
> - { "vsse16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm },
> - { "vsse32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm },
> - { "vsse64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm },
> - { "vluxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm },
> - { "vluxei16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm },
> - { "vluxei32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm },
> - { "vluxei64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm },
> - { "vloxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm },
> - { "vloxei16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm },
> - { "vloxei32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm },
> - { "vloxei64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm },
> - { "vsuxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm },
> - { "vsuxei16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm },
> - { "vsuxei32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm },
> - { "vsuxei64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm },
> - { "vsoxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm },
> - { "vsoxei16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm },
> - { "vsoxei32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm },
> - { "vsoxei64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm },
> - { "vle8ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
> - { "vle16ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
> - { "vle32ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
> - { "vle64ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
> - { "vl1re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
> - { "vl1re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
> - { "vl1re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
> - { "vl1re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
> - { "vl2re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
> - { "vl2re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
> - { "vl2re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
> - { "vl2re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
> - { "vl4re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
> - { "vl4re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
> - { "vl4re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
> - { "vl4re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
> - { "vl8re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
> - { "vl8re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
> - { "vl8re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
> - { "vl8re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
> - { "vs1r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
> - { "vs2r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
> - { "vs4r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
> - { "vs8r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm },
> - { "vadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> - { "vadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
> - { "vadd.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm },
> - { "vsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> - { "vsub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
> - { "vrsub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
> - { "vrsub.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm },
> - { "vwaddu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> - { "vwaddu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
> - { "vwadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> - { "vwadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
> - { "vwsubu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> - { "vwsubu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
> - { "vwsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> - { "vwsub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
> - { "vwaddu.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> - { "vwaddu.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
> - { "vwadd.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> - { "vwadd.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
> - { "vwsubu.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> - { "vwsubu.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
> - { "vwsub.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> - { "vwsub.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
> - { "vadc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl },
> - { "vadc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl },
> - { "vadc.vim", rv_codec_v_i, rv_fmt_vd_vs2_imm_vl },
> - { "vmadc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl },
> - { "vmadc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl },
> - { "vmadc.vim", rv_codec_v_i, rv_fmt_vd_vs2_imm_vl },
> - { "vsbc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl },
> - { "vsbc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl },
> - { "vmsbc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl },
> - { "vmsbc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl },
> - { "vand.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> - { "vand.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
> - { "vand.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm },
> - { "vor.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> - { "vor.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
> - { "vor.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm },
> - { "vxor.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> - { "vxor.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
> - { "vxor.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm },
> - { "vsll.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> - { "vsll.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
> - { "vsll.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm },
> - { "vsrl.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> - { "vsrl.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
> - { "vsrl.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm },
> - { "vsra.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> - { "vsra.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
> - { "vsra.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm },
> - { "vnsrl.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> - { "vnsrl.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
> - { "vnsrl.wi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm },
> - { "vnsra.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> - { "vnsra.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
> - { "vnsra.wi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm },
> - { "vmseq.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> - { "vmseq.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
> - { "vmseq.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm },
> - { "vmsne.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> - { "vmsne.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
> - { "vmsne.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm },
> - { "vmsltu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> - { "vmsltu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
> - { "vmslt.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> - { "vmslt.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
> - { "vmsleu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> - { "vmsleu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
> - { "vmsleu.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm },
> - { "vmsle.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> - { "vmsle.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
> - { "vmsle.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm },
> - { "vmsgtu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
> - { "vmsgtu.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm },
> - { "vmsgt.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
> - { "vmsgt.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm },
> - { "vminu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> - { "vminu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
> - { "vmin.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> - { "vmin.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
> - { "vmaxu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> - { "vmaxu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
> - { "vmax.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> - { "vmax.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
> - { "vmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> - { "vmul.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
> - { "vmulh.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> - { "vmulh.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
> - { "vmulhu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> - { "vmulhu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
> - { "vmulhsu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> - { "vmulhsu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
> - { "vdivu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> - { "vdivu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
> - { "vdiv.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> - { "vdiv.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
> - { "vremu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> - { "vremu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
> - { "vrem.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> - { "vrem.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
> - { "vwmulu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> - { "vwmulu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
> - { "vwmulsu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> - { "vwmulsu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
> - { "vwmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> - { "vwmul.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
> - { "vmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm },
> - { "vmacc.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm },
> - { "vnmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm },
> - { "vnmsac.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm },
> - { "vmadd.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm },
> - { "vmadd.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm },
> - { "vnmsub.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm },
> - { "vnmsub.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm },
> - { "vwmaccu.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm },
> - { "vwmaccu.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm },
> - { "vwmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm },
> - { "vwmacc.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm },
> - { "vwmaccsu.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm },
> - { "vwmaccsu.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm },
> - { "vwmaccus.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm },
> - { "vmv.v.v", rv_codec_v_r, rv_fmt_vd_vs1 },
> - { "vmv.v.x", rv_codec_v_r, rv_fmt_vd_rs1 },
> - { "vmv.v.i", rv_codec_v_i, rv_fmt_vd_imm },
> - { "vmerge.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl },
> - { "vmerge.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl },
> - { "vmerge.vim", rv_codec_v_i, rv_fmt_vd_vs2_imm_vl },
> - { "vsaddu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> - { "vsaddu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
> - { "vsaddu.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm },
> - { "vsadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> - { "vsadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
> - { "vsadd.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm },
> - { "vssubu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> - { "vssubu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
> - { "vssub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> - { "vssub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
> - { "vaadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> - { "vaadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
> - { "vaaddu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> - { "vaaddu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
> - { "vasub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> - { "vasub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
> - { "vasubu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> - { "vasubu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
> - { "vsmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> - { "vsmul.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
> - { "vssrl.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> - { "vssrl.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
> - { "vssrl.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm },
> - { "vssra.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> - { "vssra.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
> - { "vssra.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm },
> - { "vnclipu.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> - { "vnclipu.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
> - { "vnclipu.wi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm },
> - { "vnclip.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> - { "vnclip.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
> - { "vnclip.wi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm },
> - { "vfadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> - { "vfadd.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm },
> - { "vfsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> - { "vfsub.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm },
> - { "vfrsub.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm },
> - { "vfwadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> - { "vfwadd.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm },
> - { "vfwadd.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> - { "vfwadd.wf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm },
> - { "vfwsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> - { "vfwsub.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm },
> - { "vfwsub.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> - { "vfwsub.wf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm },
> - { "vfmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> - { "vfmul.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm },
> - { "vfdiv.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> - { "vfdiv.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm },
> - { "vfrdiv.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm },
> - { "vfwmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> - { "vfwmul.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm },
> - { "vfmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm },
> - { "vfmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm },
> - { "vfnmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm },
> - { "vfnmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm },
> - { "vfmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm },
> - { "vfmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm },
> - { "vfnmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm },
> - { "vfnmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm },
> - { "vfmadd.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm },
> - { "vfmadd.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm },
> - { "vfnmadd.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm },
> - { "vfnmadd.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm },
> - { "vfmsub.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm },
> - { "vfmsub.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm },
> - { "vfnmsub.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm },
> - { "vfnmsub.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm },
> - { "vfwmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm },
> - { "vfwmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm },
> - { "vfwnmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm },
> - { "vfwnmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm },
> - { "vfwmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm },
> - { "vfwmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm },
> - { "vfwnmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm },
> - { "vfwnmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm },
> - { "vfsqrt.v", rv_codec_v_r, rv_fmt_vd_vs2 },
> - { "vfrsqrt7.v", rv_codec_v_r, rv_fmt_vd_vs2 },
> - { "vfrec7.v", rv_codec_v_r, rv_fmt_vd_vs2 },
> - { "vfmin.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> - { "vfmin.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm },
> - { "vfmax.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> - { "vfmax.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm },
> - { "vfsgnj.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> - { "vfsgnj.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm },
> - { "vfsgnjn.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> - { "vfsgnjn.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm },
> - { "vfsgnjx.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> - { "vfsgnjx.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm },
> - { "vfslide1up.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm },
> - { "vfslide1down.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm },
> - { "vmfeq.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> - { "vmfeq.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm },
> - { "vmfne.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> - { "vmfne.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm },
> - { "vmflt.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> - { "vmflt.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm },
> - { "vmfle.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> - { "vmfle.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm },
> - { "vmfgt.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm },
> - { "vmfge.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm },
> - { "vfclass.v", rv_codec_v_r, rv_fmt_vd_vs2_vm },
> - { "vfmerge.vfm", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vl },
> - { "vfmv.v.f", rv_codec_v_r, rv_fmt_vd_fs1 },
> - { "vfcvt.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm },
> - { "vfcvt.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm },
> - { "vfcvt.f.xu.v", rv_codec_v_r, rv_fmt_vd_vs2_vm },
> - { "vfcvt.f.x.v", rv_codec_v_r, rv_fmt_vd_vs2_vm },
> - { "vfcvt.rtz.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm },
> - { "vfcvt.rtz.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm },
> - { "vfwcvt.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm },
> - { "vfwcvt.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm },
> - { "vfwcvt.f.xu.v", rv_codec_v_r, rv_fmt_vd_vs2_vm },
> - { "vfwcvt.f.x.v", rv_codec_v_r, rv_fmt_vd_vs2_vm },
> - { "vfwcvt.f.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm },
> - { "vfwcvt.rtz.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm },
> - { "vfwcvt.rtz.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm },
> - { "vfncvt.xu.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm },
> - { "vfncvt.x.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm },
> - { "vfncvt.f.xu.w", rv_codec_v_r, rv_fmt_vd_vs2_vm },
> - { "vfncvt.f.x.w", rv_codec_v_r, rv_fmt_vd_vs2_vm },
> - { "vfncvt.f.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm },
> - { "vfncvt.rod.f.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm },
> - { "vfncvt.rtz.xu.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm },
> - { "vfncvt.rtz.x.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm },
> - { "vredsum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> - { "vredand.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> - { "vredor.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> - { "vredxor.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> - { "vredminu.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> - { "vredmin.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> - { "vredmaxu.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> - { "vredmax.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> - { "vwredsumu.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> - { "vwredsum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> - { "vfredusum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> - { "vfredosum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> - { "vfredmin.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> - { "vfredmax.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> - { "vfwredusum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> - { "vfwredosum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> - { "vmand.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> - { "vmnand.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> - { "vmandn.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> - { "vmxor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> - { "vmor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> - { "vmnor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> - { "vmorn.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> - { "vmxnor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> - { "vcpop.m", rv_codec_v_r, rv_fmt_rd_vs2_vm },
> - { "vfirst.m", rv_codec_v_r, rv_fmt_rd_vs2_vm },
> - { "vmsbf.m", rv_codec_v_r, rv_fmt_vd_vs2_vm },
> - { "vmsif.m", rv_codec_v_r, rv_fmt_vd_vs2_vm },
> - { "vmsof.m", rv_codec_v_r, rv_fmt_vd_vs2_vm },
> - { "viota.m", rv_codec_v_r, rv_fmt_vd_vs2_vm },
> - { "vid.v", rv_codec_v_r, rv_fmt_vd_vm },
> - { "vmv.x.s", rv_codec_v_r, rv_fmt_rd_vs2 },
> - { "vmv.s.x", rv_codec_v_r, rv_fmt_vd_rs1 },
> - { "vfmv.f.s", rv_codec_v_r, rv_fmt_fd_vs2 },
> - { "vfmv.s.f", rv_codec_v_r, rv_fmt_vd_fs1 },
> - { "vslideup.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
> - { "vslideup.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm },
> - { "vslide1up.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
> - { "vslidedown.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
> - { "vslidedown.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm },
> - { "vslide1down.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
> - { "vrgather.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> - { "vrgatherei16.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> - { "vrgather.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
> - { "vrgather.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm },
> - { "vcompress.vm", rv_codec_v_r, rv_fmt_vd_vs2_vs1 },
> - { "vmv1r.v", rv_codec_v_r, rv_fmt_vd_vs2 },
> - { "vmv2r.v", rv_codec_v_r, rv_fmt_vd_vs2 },
> - { "vmv4r.v", rv_codec_v_r, rv_fmt_vd_vs2 },
> - { "vmv8r.v", rv_codec_v_r, rv_fmt_vd_vs2 },
> - { "vzext.vf2", rv_codec_v_r, rv_fmt_vd_vs2_vm },
> - { "vzext.vf4", rv_codec_v_r, rv_fmt_vd_vs2_vm },
> - { "vzext.vf8", rv_codec_v_r, rv_fmt_vd_vs2_vm },
> - { "vsext.vf2", rv_codec_v_r, rv_fmt_vd_vs2_vm },
> - { "vsext.vf4", rv_codec_v_r, rv_fmt_vd_vs2_vm },
> - { "vsext.vf8", rv_codec_v_r, rv_fmt_vd_vs2_vm },
> - { "vsetvli", rv_codec_vsetvli, rv_fmt_vsetvli },
> - { "vsetivli", rv_codec_vsetivli, rv_fmt_vsetivli },
> - { "vsetvl", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> - { "c.zext.b", rv_codec_zcb_ext, rv_fmt_rd },
> - { "c.sext.b", rv_codec_zcb_ext, rv_fmt_rd },
> - { "c.zext.h", rv_codec_zcb_ext, rv_fmt_rd },
> - { "c.sext.h", rv_codec_zcb_ext, rv_fmt_rd },
> - { "c.zext.w", rv_codec_zcb_ext, rv_fmt_rd },
> - { "c.not", rv_codec_zcb_ext, rv_fmt_rd },
> - { "c.mul", rv_codec_zcb_mul, rv_fmt_rd_rs2 },
> - { "c.lbu", rv_codec_zcb_lb, rv_fmt_rs1_rs2_zce_ldst },
> - { "c.lhu", rv_codec_zcb_lh, rv_fmt_rs1_rs2_zce_ldst },
> - { "c.lh", rv_codec_zcb_lh, rv_fmt_rs1_rs2_zce_ldst },
> - { "c.sb", rv_codec_zcb_lb, rv_fmt_rs1_rs2_zce_ldst },
> - { "c.sh", rv_codec_zcb_lh, rv_fmt_rs1_rs2_zce_ldst },
> - { "cm.push", rv_codec_zcmp_cm_pushpop, rv_fmt_push_rlist },
> - { "cm.pop", rv_codec_zcmp_cm_pushpop, rv_fmt_pop_rlist },
> - { "cm.popret", rv_codec_zcmp_cm_pushpop, rv_fmt_pop_rlist },
> - { "cm.popretz", rv_codec_zcmp_cm_pushpop, rv_fmt_pop_rlist },
> - { "cm.mva01s", rv_codec_zcmp_cm_mv, rv_fmt_rd_rs2 },
> - { "cm.mvsa01", rv_codec_zcmp_cm_mv, rv_fmt_rd_rs2 },
> - { "cm.jt", rv_codec_zcmt_jt, rv_fmt_zcmt_index },
> - { "cm.jalt", rv_codec_zcmt_jt, rv_fmt_zcmt_index },
> - { "czero.eqz", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> - { "czero.nez", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> - { "fcvt.bf16.s", rv_codec_r_m, rv_fmt_rm_frd_frs1 },
> - { "fcvt.s.bf16", rv_codec_r_m, rv_fmt_rm_frd_frs1 },
> - { "vfncvtbf16.f.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm },
> - { "vfwcvtbf16.f.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm },
> - { "vfwmaccbf16.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm },
> - { "vfwmaccbf16.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm },
> - { "flh", rv_codec_i, rv_fmt_frd_offset_rs1 },
> - { "fsh", rv_codec_s, rv_fmt_frs2_offset_rs1 },
> - { "fmv.h.x", rv_codec_r, rv_fmt_frd_rs1 },
> - { "fmv.x.h", rv_codec_r, rv_fmt_rd_frs1 },
> - { "fli.s", rv_codec_fli, rv_fmt_fli },
> - { "fli.d", rv_codec_fli, rv_fmt_fli },
> - { "fli.q", rv_codec_fli, rv_fmt_fli },
> - { "fli.h", rv_codec_fli, rv_fmt_fli },
> - { "fminm.s", rv_codec_r, rv_fmt_frd_frs1_frs2 },
> - { "fmaxm.s", rv_codec_r, rv_fmt_frd_frs1_frs2 },
> - { "fminm.d", rv_codec_r, rv_fmt_frd_frs1_frs2 },
> - { "fmaxm.d", rv_codec_r, rv_fmt_frd_frs1_frs2 },
> - { "fminm.q", rv_codec_r, rv_fmt_frd_frs1_frs2 },
> - { "fmaxm.q", rv_codec_r, rv_fmt_frd_frs1_frs2 },
> - { "fminm.h", rv_codec_r, rv_fmt_frd_frs1_frs2 },
> - { "fmaxm.h", rv_codec_r, rv_fmt_frd_frs1_frs2 },
> - { "fround.s", rv_codec_r_m, rv_fmt_rm_frd_frs1 },
> - { "froundnx.s", rv_codec_r_m, rv_fmt_rm_frd_frs1 },
> - { "fround.d", rv_codec_r_m, rv_fmt_rm_frd_frs1 },
> - { "froundnx.d", rv_codec_r_m, rv_fmt_rm_frd_frs1 },
> - { "fround.q", rv_codec_r_m, rv_fmt_rm_frd_frs1 },
> - { "froundnx.q", rv_codec_r_m, rv_fmt_rm_frd_frs1 },
> - { "fround.h", rv_codec_r_m, rv_fmt_rm_frd_frs1 },
> - { "froundnx.h", rv_codec_r_m, rv_fmt_rm_frd_frs1 },
> - { "fcvtmod.w.d", rv_codec_r_m, rv_fmt_rm_rd_frs1 },
> - { "fmvh.x.d", rv_codec_r, rv_fmt_rd_frs1 },
> - { "fmvp.d.x", rv_codec_r, rv_fmt_frd_rs1_rs2 },
> - { "fmvh.x.q", rv_codec_r, rv_fmt_rd_frs1 },
> - { "fmvp.q.x", rv_codec_r, rv_fmt_frd_rs1_rs2 },
> - { "fleq.s", rv_codec_r, rv_fmt_rd_frs1_frs2 },
> - { "fltq.s", rv_codec_r, rv_fmt_rd_frs1_frs2 },
> - { "fleq.d", rv_codec_r, rv_fmt_rd_frs1_frs2 },
> - { "fltq.d", rv_codec_r, rv_fmt_rd_frs1_frs2 },
> - { "fleq.q", rv_codec_r, rv_fmt_rd_frs1_frs2 },
> - { "fltq.q", rv_codec_r, rv_fmt_rd_frs1_frs2 },
> - { "fleq.h", rv_codec_r, rv_fmt_rd_frs1_frs2 },
> - { "fltq.h", rv_codec_r, rv_fmt_rd_frs1_frs2 },
> - { "vaesdf.vv", rv_codec_v_r, rv_fmt_vd_vs2 },
> - { "vaesdf.vs", rv_codec_v_r, rv_fmt_vd_vs2 },
> - { "vaesdm.vv", rv_codec_v_r, rv_fmt_vd_vs2 },
> - { "vaesdm.vs", rv_codec_v_r, rv_fmt_vd_vs2 },
> - { "vaesef.vv", rv_codec_v_r, rv_fmt_vd_vs2 },
> - { "vaesef.vs", rv_codec_v_r, rv_fmt_vd_vs2 },
> - { "vaesem.vv", rv_codec_v_r, rv_fmt_vd_vs2 },
> - { "vaesem.vs", rv_codec_v_r, rv_fmt_vd_vs2 },
> - { "vaeskf1.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm },
> - { "vaeskf2.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm },
> - { "vaesz.vs", rv_codec_v_r, rv_fmt_vd_vs2 },
> - { "vandn.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> - { "vandn.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
> - { "vbrev.v", rv_codec_v_r, rv_fmt_vd_vs2_vm },
> - { "vbrev8.v", rv_codec_v_r, rv_fmt_vd_vs2_vm },
> - { "vclmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> - { "vclmul.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
> - { "vclmulh.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> - { "vclmulh.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
> - { "vclz.v", rv_codec_v_r, rv_fmt_vd_vs2_vm },
> - { "vcpop.v", rv_codec_v_r, rv_fmt_vd_vs2_vm },
> - { "vctz.v", rv_codec_v_r, rv_fmt_vd_vs2_vm },
> - { "vghsh.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1 },
> - { "vgmul.vv", rv_codec_v_r, rv_fmt_vd_vs2 },
> - { "vrev8.v", rv_codec_v_r, rv_fmt_vd_vs2_vm },
> - { "vrol.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> - { "vrol.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
> - { "vror.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> - { "vror.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
> - { "vror.vi", rv_codec_vror_vi, rv_fmt_vd_vs2_uimm_vm },
> - { "vsha2ch.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1 },
> - { "vsha2cl.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1 },
> - { "vsha2ms.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1 },
> - { "vsm3c.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm },
> - { "vsm3me.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1 },
> - { "vsm4k.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm },
> - { "vsm4r.vv", rv_codec_v_r, rv_fmt_vd_vs2 },
> - { "vsm4r.vs", rv_codec_v_r, rv_fmt_vd_vs2 },
> - { "vwsll.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm },
> - { "vwsll.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm },
> - { "vwsll.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm },
> - { "amocas.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
> - { "amocas.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
> - { "amocas.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
> - { "mop.r.0", rv_codec_r, rv_fmt_rd_rs1 },
> - { "mop.r.1", rv_codec_r, rv_fmt_rd_rs1 },
> - { "mop.r.2", rv_codec_r, rv_fmt_rd_rs1 },
> - { "mop.r.3", rv_codec_r, rv_fmt_rd_rs1 },
> - { "mop.r.4", rv_codec_r, rv_fmt_rd_rs1 },
> - { "mop.r.5", rv_codec_r, rv_fmt_rd_rs1 },
> - { "mop.r.6", rv_codec_r, rv_fmt_rd_rs1 },
> - { "mop.r.7", rv_codec_r, rv_fmt_rd_rs1 },
> - { "mop.r.8", rv_codec_r, rv_fmt_rd_rs1 },
> - { "mop.r.9", rv_codec_r, rv_fmt_rd_rs1 },
> - { "mop.r.10", rv_codec_r, rv_fmt_rd_rs1 },
> - { "mop.r.11", rv_codec_r, rv_fmt_rd_rs1 },
> - { "mop.r.12", rv_codec_r, rv_fmt_rd_rs1 },
> - { "mop.r.13", rv_codec_r, rv_fmt_rd_rs1 },
> - { "mop.r.14", rv_codec_r, rv_fmt_rd_rs1 },
> - { "mop.r.15", rv_codec_r, rv_fmt_rd_rs1 },
> - { "mop.r.16", rv_codec_r, rv_fmt_rd_rs1 },
> - { "mop.r.17", rv_codec_r, rv_fmt_rd_rs1 },
> - { "mop.r.18", rv_codec_r, rv_fmt_rd_rs1 },
> - { "mop.r.19", rv_codec_r, rv_fmt_rd_rs1 },
> - { "mop.r.20", rv_codec_r, rv_fmt_rd_rs1 },
> - { "mop.r.21", rv_codec_r, rv_fmt_rd_rs1 },
> - { "mop.r.22", rv_codec_r, rv_fmt_rd_rs1 },
> - { "mop.r.23", rv_codec_r, rv_fmt_rd_rs1 },
> - { "mop.r.24", rv_codec_r, rv_fmt_rd_rs1 },
> - { "mop.r.25", rv_codec_r, rv_fmt_rd_rs1 },
> - { "mop.r.26", rv_codec_r, rv_fmt_rd_rs1 },
> - { "mop.r.27", rv_codec_r, rv_fmt_rd_rs1 },
> - { "mop.r.28", rv_codec_r, rv_fmt_rd_rs1 },
> - { "mop.r.29", rv_codec_r, rv_fmt_rd_rs1 },
> - { "mop.r.30", rv_codec_r, rv_fmt_rd_rs1 },
> - { "mop.r.31", rv_codec_r, rv_fmt_rd_rs1 },
> - { "mop.rr.0", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> - { "mop.rr.1", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> - { "mop.rr.2", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> - { "mop.rr.3", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> - { "mop.rr.4", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> - { "mop.rr.5", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> - { "mop.rr.6", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> - { "mop.rr.7", rv_codec_r, rv_fmt_rd_rs1_rs2 },
> - { "c.mop.1", rv_codec_ci_none, rv_fmt_none },
> - { "c.mop.3", rv_codec_ci_none, rv_fmt_none },
> - { "c.mop.5", rv_codec_ci_none, rv_fmt_none },
> - { "c.mop.7", rv_codec_ci_none, rv_fmt_none },
> - { "c.mop.9", rv_codec_ci_none, rv_fmt_none },
> - { "c.mop.11", rv_codec_ci_none, rv_fmt_none },
> - { "c.mop.13", rv_codec_ci_none, rv_fmt_none },
> - { "c.mop.15", rv_codec_ci_none, rv_fmt_none },
> - { "amoswap.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
> - { "amoadd.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
> - { "amoxor.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
> - { "amoor.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
> - { "amoand.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
> - { "amomin.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
> - { "amomax.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
> - { "amominu.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
> - { "amomaxu.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
> - { "amoswap.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
> - { "amoadd.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
> - { "amoxor.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
> - { "amoor.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
> - { "amoand.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
> - { "amomin.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
> - { "amomax.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
> - { "amominu.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
> - { "amomaxu.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
> - { "amocas.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
> - { "amocas.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
> - { "wrs.sto", rv_codec_none, rv_fmt_none },
> - { "wrs.nto", rv_codec_none, rv_fmt_none },
> - { "lpad", rv_codec_lp, rv_fmt_imm },
> - { "sspush", rv_codec_r, rv_fmt_rs2 },
> - { "sspopchk", rv_codec_r, rv_fmt_rs1 },
> - { "ssrdp", rv_codec_r, rv_fmt_rd },
> - { "ssamoswap.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
> - { "ssamoswap.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
> - { "c.sspush", rv_codec_cmop_ss, NULL, DECOMP(rv_op_sspush) },
> - { "c.sspopchk", rv_codec_cmop_ss, NULL, DECOMP(rv_op_sspopchk)
> },
> - { "cbo.inval", rv_codec_r, rv_fmt_rs1 },
> - { "cbo.clean", rv_codec_r, rv_fmt_rs1 },
> - { "cbo.flush", rv_codec_r, rv_fmt_rs1 },
> - { "cbo.zero", rv_codec_r, rv_fmt_rs1 },
> - { "mnret", rv_codec_none, rv_fmt_none },
> +#define OP(N, ...) { __VA_ARGS__ },
> +#include "riscv-op.c.inc"
> +#undef OP
> };
>
> /* CSR names */
> @@ -2928,7 +1015,7 @@ static const rv_opcode_data
> *decode_inst_opcode(rv_decode *dec, rv_isa isa)
> (((inst >> 11) & 0b11) == 0b0)) {
> unsigned int cmop_code = 0;
> cmop_code = ((inst >> 8) & 0b111);
> - op = rv_c_mop_1 + cmop_code;
> + op = rv_op_c_mop_1 + cmop_code;
> if (dec->cfg->ext_zicfiss) {
> op = (cmop_code == 0) ? rv_op_c_sspush : op;
> op = (cmop_code == 2) ? rv_op_c_sspopchk :
> op;
> @@ -4459,7 +2546,7 @@ static const rv_opcode_data
> *decode_inst_opcode(rv_decode *dec, rv_isa isa)
> 2, 2,
>
> extract32(inst, 26, 2)),
> 4, 1, extract32(inst,
> 30, 1));
> - op = rv_mop_r_0 + imm_mop5;
> + op = rv_op_mop_r_0 + imm_mop5;
> /* if zicfiss enabled and mop5 is shadow
> stack */
> if (dec->cfg->ext_zicfiss &&
> ((imm_mop5 & 0b11100) == 0b11100)) {
> @@ -4478,7 +2565,7 @@ static const rv_opcode_data
> *decode_inst_opcode(rv_decode *dec, rv_isa isa)
> == 0b1000001) {
> imm_mop3 = deposit32(extract32(inst, 26, 2),
> 2, 1, extract32(inst,
> 30, 1));
> - op = rv_mop_rr_0 + imm_mop3;
> + op = rv_op_mop_rr_0 + imm_mop3;
> /* if zicfiss enabled and mop3 is shadow
> stack */
> if (dec->cfg->ext_zicfiss &&
> ((imm_mop3 & 0b111) == 0b111)) {
> diff --git a/disas/riscv-op.c.inc b/disas/riscv-op.c.inc
> new file mode 100644
> index 0000000000..3fe934688e
> --- /dev/null
> +++ b/disas/riscv-op.c.inc
> @@ -0,0 +1,958 @@
> +OP(illegal, "illegal", rv_codec_none, rv_fmt_none)
> +OP(lui, "lui", rv_codec_u, rv_fmt_rd_uimm)
> +OP(auipc, "auipc", rv_codec_u, rv_fmt_rd_uoffset)
> +OP(jal, "jal", rv_codec_uj, rv_fmt_rd_offset, rvcp_jal)
> +OP(jalr, "jalr", rv_codec_i, rv_fmt_rd_rs1_offset, rvcp_jalr)
> +OP(beq, "beq", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_beq)
> +OP(bne, "bne", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_bne)
> +OP(blt, "blt", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_blt)
> +OP(bge, "bge", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_bge)
> +OP(bltu, "bltu", rv_codec_sb, rv_fmt_rs1_rs2_offset)
> +OP(bgeu, "bgeu", rv_codec_sb, rv_fmt_rs1_rs2_offset)
> +OP(lb, "lb", rv_codec_i, rv_fmt_rd_offset_rs1)
> +OP(lh, "lh", rv_codec_i, rv_fmt_rd_offset_rs1)
> +OP(lw, "lw", rv_codec_i, rv_fmt_rd_offset_rs1)
> +OP(lbu, "lbu", rv_codec_i, rv_fmt_rd_offset_rs1)
> +OP(lhu, "lhu", rv_codec_i, rv_fmt_rd_offset_rs1)
> +OP(sb, "sb", rv_codec_s, rv_fmt_rs2_offset_rs1)
> +OP(sh, "sh", rv_codec_s, rv_fmt_rs2_offset_rs1)
> +OP(sw, "sw", rv_codec_s, rv_fmt_rs2_offset_rs1)
> +OP(addi, "addi", rv_codec_i, rv_fmt_rd_rs1_imm, rvcp_addi)
> +OP(slti, "slti", rv_codec_i, rv_fmt_rd_rs1_imm)
> +OP(sltiu, "sltiu", rv_codec_i, rv_fmt_rd_rs1_imm, rvcp_sltiu)
> +OP(xori, "xori", rv_codec_i, rv_fmt_rd_rs1_imm, rvcp_xori)
> +OP(ori, "ori", rv_codec_i, rv_fmt_rd_rs1_imm)
> +OP(andi, "andi", rv_codec_i, rv_fmt_rd_rs1_imm)
> +OP(slli, "slli", rv_codec_i_sh7, rv_fmt_rd_rs1_imm)
> +OP(srli, "srli", rv_codec_i_sh7, rv_fmt_rd_rs1_imm)
> +OP(srai, "srai", rv_codec_i_sh7, rv_fmt_rd_rs1_imm)
> +OP(add, "add", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(sub, "sub", rv_codec_r, rv_fmt_rd_rs1_rs2, rvcp_sub)
> +OP(sll, "sll", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(slt, "slt", rv_codec_r, rv_fmt_rd_rs1_rs2, rvcp_slt)
> +OP(sltu, "sltu", rv_codec_r, rv_fmt_rd_rs1_rs2, rvcp_sltu)
> +OP(xor, "xor", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(srl, "srl", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(sra, "sra", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(or, "or", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(and, "and", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(fence, "fence", rv_codec_r_f, rv_fmt_pred_succ)
> +OP(fence_i, "fence.i", rv_codec_none, rv_fmt_none)
> +OP(lwu, "lwu", rv_codec_i, rv_fmt_rd_offset_rs1)
> +OP(ld, "ld", rv_codec_i, rv_fmt_rd_offset_rs1)
> +OP(sd, "sd", rv_codec_s, rv_fmt_rs2_offset_rs1)
> +OP(addiw, "addiw", rv_codec_i, rv_fmt_rd_rs1_imm, rvcp_addiw)
> +OP(slliw, "slliw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm)
> +OP(srliw, "srliw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm)
> +OP(sraiw, "sraiw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm)
> +OP(addw, "addw", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(subw, "subw", rv_codec_r, rv_fmt_rd_rs1_rs2, rvcp_subw)
> +OP(sllw, "sllw", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(srlw, "srlw", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(sraw, "sraw", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(ldu, "ldu", rv_codec_i, rv_fmt_rd_offset_rs1)
> +OP(lq, "lq", rv_codec_i, rv_fmt_rd_offset_rs1)
> +OP(sq, "sq", rv_codec_s, rv_fmt_rs2_offset_rs1)
> +OP(addid, "addid", rv_codec_i, rv_fmt_rd_rs1_imm)
> +OP(sllid, "sllid", rv_codec_i_sh6, rv_fmt_rd_rs1_imm)
> +OP(srlid, "srlid", rv_codec_i_sh6, rv_fmt_rd_rs1_imm)
> +OP(sraid, "sraid", rv_codec_i_sh6, rv_fmt_rd_rs1_imm)
> +OP(addd, "addd", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(subd, "subd", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(slld, "slld", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(srld, "srld", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(srad, "srad", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(mul, "mul", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(mulh, "mulh", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(mulhsu, "mulhsu", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(mulhu, "mulhu", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(div, "div", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(divu, "divu", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(rem, "rem", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(remu, "remu", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(mulw, "mulw", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(divw, "divw", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(divuw, "divuw", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(remw, "remw", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(remuw, "remuw", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(muld, "muld", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(divd, "divd", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(divud, "divud", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(remd, "remd", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(remud, "remud", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(lr_w, "lr.w", rv_codec_r_l, rv_fmt_aqrl_rd_rs1)
> +OP(sc_w, "sc.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> +OP(amoswap_w, "amoswap.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> +OP(amoadd_w, "amoadd.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> +OP(amoxor_w, "amoxor.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> +OP(amoor_w, "amoor.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> +OP(amoand_w, "amoand.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> +OP(amomin_w, "amomin.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> +OP(amomax_w, "amomax.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> +OP(amominu_w, "amominu.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> +OP(amomaxu_w, "amomaxu.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> +OP(lr_d, "lr.d", rv_codec_r_l, rv_fmt_aqrl_rd_rs1)
> +OP(sc_d, "sc.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> +OP(amoswap_d, "amoswap.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> +OP(amoadd_d, "amoadd.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> +OP(amoxor_d, "amoxor.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> +OP(amoor_d, "amoor.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> +OP(amoand_d, "amoand.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> +OP(amomin_d, "amomin.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> +OP(amomax_d, "amomax.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> +OP(amominu_d, "amominu.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> +OP(amomaxu_d, "amomaxu.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> +OP(lr_q, "lr.q", rv_codec_r_l, rv_fmt_aqrl_rd_rs1)
> +OP(sc_q, "sc.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> +OP(amoswap_q, "amoswap.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> +OP(amoadd_q, "amoadd.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> +OP(amoxor_q, "amoxor.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> +OP(amoor_q, "amoor.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> +OP(amoand_q, "amoand.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> +OP(amomin_q, "amomin.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> +OP(amomax_q, "amomax.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> +OP(amominu_q, "amominu.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> +OP(amomaxu_q, "amomaxu.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> +OP(ecall, "ecall", rv_codec_none, rv_fmt_none)
> +OP(ebreak, "ebreak", rv_codec_none, rv_fmt_none)
> +OP(uret, "uret", rv_codec_none, rv_fmt_none)
> +OP(sret, "sret", rv_codec_none, rv_fmt_none)
> +OP(hret, "hret", rv_codec_none, rv_fmt_none)
> +OP(mret, "mret", rv_codec_none, rv_fmt_none)
> +OP(dret, "dret", rv_codec_none, rv_fmt_none)
> +OP(sfence_vm, "sfence.vm", rv_codec_r, rv_fmt_rs1)
> +OP(sfence_vma, "sfence.vma", rv_codec_r, rv_fmt_rs1_rs2)
> +OP(wfi, "wfi", rv_codec_none, rv_fmt_none)
> +OP(csrrw, "csrrw", rv_codec_i_csr, rv_fmt_rd_csr_rs1)
> +OP(csrrs, "csrrs", rv_codec_i_csr, rv_fmt_rd_csr_rs1)
> +OP(csrrc, "csrrc", rv_codec_i_csr, rv_fmt_rd_csr_rs1)
> +OP(csrrwi, "csrrwi", rv_codec_i_csr, rv_fmt_rd_csr_zimm)
> +OP(csrrsi, "csrrsi", rv_codec_i_csr, rv_fmt_rd_csr_zimm)
> +OP(csrrci, "csrrci", rv_codec_i_csr, rv_fmt_rd_csr_zimm)
> +OP(flw, "flw", rv_codec_i, rv_fmt_frd_offset_rs1)
> +OP(fsw, "fsw", rv_codec_s, rv_fmt_frs2_offset_rs1)
> +OP(fmadd_s, "fmadd.s", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3)
> +OP(fmsub_s, "fmsub.s", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3)
> +OP(fnmsub_s, "fnmsub.s", rv_codec_r4_m,
> rv_fmt_rm_frd_frs1_frs2_frs3)
> +OP(fnmadd_s, "fnmadd.s", rv_codec_r4_m,
> rv_fmt_rm_frd_frs1_frs2_frs3)
> +OP(fadd_s, "fadd.s", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2)
> +OP(fsub_s, "fsub.s", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2)
> +OP(fmul_s, "fmul.s", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2)
> +OP(fdiv_s, "fdiv.s", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2)
> +OP(fsgnj_s, "fsgnj.s", rv_codec_r, rv_fmt_frd_frs1_frs2,
> rvcp_fsgnj_s)
> +OP(fsgnjn_s, "fsgnjn.s", rv_codec_r, rv_fmt_frd_frs1_frs2,
> rvcp_fsgnjn_s)
> +OP(fsgnjx_s, "fsgnjx.s", rv_codec_r, rv_fmt_frd_frs1_frs2,
> rvcp_fsgnjx_s)
> +OP(fmin_s, "fmin.s", rv_codec_r, rv_fmt_frd_frs1_frs2)
> +OP(fmax_s, "fmax.s", rv_codec_r, rv_fmt_frd_frs1_frs2)
> +OP(fsqrt_s, "fsqrt.s", rv_codec_r_m, rv_fmt_rm_frd_frs1)
> +OP(fle_s, "fle.s", rv_codec_r, rv_fmt_rd_frs1_frs2)
> +OP(flt_s, "flt.s", rv_codec_r, rv_fmt_rd_frs1_frs2)
> +OP(feq_s, "feq.s", rv_codec_r, rv_fmt_rd_frs1_frs2)
> +OP(fcvt_w_s, "fcvt.w.s", rv_codec_r_m, rv_fmt_rm_rd_frs1)
> +OP(fcvt_wu_s, "fcvt.wu.s", rv_codec_r_m, rv_fmt_rm_rd_frs1)
> +OP(fcvt_s_w, "fcvt.s.w", rv_codec_r_m, rv_fmt_rm_frd_rs1)
> +OP(fcvt_s_wu, "fcvt.s.wu", rv_codec_r_m, rv_fmt_rm_frd_rs1)
> +OP(fmv_x_s, "fmv.x.s", rv_codec_r, rv_fmt_rd_frs1)
> +OP(fclass_s, "fclass.s", rv_codec_r, rv_fmt_rd_frs1)
> +OP(fmv_s_x, "fmv.s.x", rv_codec_r, rv_fmt_frd_rs1)
> +OP(fcvt_l_s, "fcvt.l.s", rv_codec_r_m, rv_fmt_rm_rd_frs1)
> +OP(fcvt_lu_s, "fcvt.lu.s", rv_codec_r_m, rv_fmt_rm_rd_frs1)
> +OP(fcvt_s_l, "fcvt.s.l", rv_codec_r_m, rv_fmt_rm_frd_rs1)
> +OP(fcvt_s_lu, "fcvt.s.lu", rv_codec_r_m, rv_fmt_rm_frd_rs1)
> +OP(fld, "fld", rv_codec_i, rv_fmt_frd_offset_rs1)
> +OP(fsd, "fsd", rv_codec_s, rv_fmt_frs2_offset_rs1)
> +OP(fmadd_d, "fmadd.d", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3)
> +OP(fmsub_d, "fmsub.d", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3)
> +OP(fnmsub_d, "fnmsub.d", rv_codec_r4_m,
> rv_fmt_rm_frd_frs1_frs2_frs3)
> +OP(fnmadd_d, "fnmadd.d", rv_codec_r4_m,
> rv_fmt_rm_frd_frs1_frs2_frs3)
> +OP(fadd_d, "fadd.d", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2)
> +OP(fsub_d, "fsub.d", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2)
> +OP(fmul_d, "fmul.d", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2)
> +OP(fdiv_d, "fdiv.d", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2)
> +OP(fsgnj_d, "fsgnj.d", rv_codec_r, rv_fmt_frd_frs1_frs2,
> rvcp_fsgnj_d)
> +OP(fsgnjn_d, "fsgnjn.d", rv_codec_r, rv_fmt_frd_frs1_frs2,
> rvcp_fsgnjn_d)
> +OP(fsgnjx_d, "fsgnjx.d", rv_codec_r, rv_fmt_frd_frs1_frs2,
> rvcp_fsgnjx_d)
> +OP(fmin_d, "fmin.d", rv_codec_r, rv_fmt_frd_frs1_frs2)
> +OP(fmax_d, "fmax.d", rv_codec_r, rv_fmt_frd_frs1_frs2)
> +OP(fcvt_s_d, "fcvt.s.d", rv_codec_r_m, rv_fmt_rm_frd_frs1)
> +OP(fcvt_d_s, "fcvt.d.s", rv_codec_r_m, rv_fmt_rm_frd_frs1)
> +OP(fsqrt_d, "fsqrt.d", rv_codec_r_m, rv_fmt_rm_frd_frs1)
> +OP(fle_d, "fle.d", rv_codec_r, rv_fmt_rd_frs1_frs2)
> +OP(flt_d, "flt.d", rv_codec_r, rv_fmt_rd_frs1_frs2)
> +OP(feq_d, "feq.d", rv_codec_r, rv_fmt_rd_frs1_frs2)
> +OP(fcvt_w_d, "fcvt.w.d", rv_codec_r_m, rv_fmt_rm_rd_frs1)
> +OP(fcvt_wu_d, "fcvt.wu.d", rv_codec_r_m, rv_fmt_rm_rd_frs1)
> +OP(fcvt_d_w, "fcvt.d.w", rv_codec_r_m, rv_fmt_rm_frd_rs1)
> +OP(fcvt_d_wu, "fcvt.d.wu", rv_codec_r_m, rv_fmt_rm_frd_rs1)
> +OP(fclass_d, "fclass.d", rv_codec_r, rv_fmt_rd_frs1)
> +OP(fcvt_l_d, "fcvt.l.d", rv_codec_r_m, rv_fmt_rm_rd_frs1)
> +OP(fcvt_lu_d, "fcvt.lu.d", rv_codec_r_m, rv_fmt_rm_rd_frs1)
> +OP(fmv_x_d, "fmv.x.d", rv_codec_r, rv_fmt_rd_frs1)
> +OP(fcvt_d_l, "fcvt.d.l", rv_codec_r_m, rv_fmt_rm_frd_rs1)
> +OP(fcvt_d_lu, "fcvt.d.lu", rv_codec_r_m, rv_fmt_rm_frd_rs1)
> +OP(fmv_d_x, "fmv.d.x", rv_codec_r, rv_fmt_frd_rs1)
> +OP(flq, "flq", rv_codec_i, rv_fmt_frd_offset_rs1)
> +OP(fsq, "fsq", rv_codec_s, rv_fmt_frs2_offset_rs1)
> +OP(fmadd_q, "fmadd.q", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3)
> +OP(fmsub_q, "fmsub.q", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3)
> +OP(fnmsub_q, "fnmsub.q", rv_codec_r4_m,
> rv_fmt_rm_frd_frs1_frs2_frs3)
> +OP(fnmadd_q, "fnmadd.q", rv_codec_r4_m,
> rv_fmt_rm_frd_frs1_frs2_frs3)
> +OP(fadd_q, "fadd.q", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2)
> +OP(fsub_q, "fsub.q", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2)
> +OP(fmul_q, "fmul.q", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2)
> +OP(fdiv_q, "fdiv.q", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2)
> +OP(fsgnj_q, "fsgnj.q", rv_codec_r, rv_fmt_frd_frs1_frs2,
> rvcp_fsgnj_q)
> +OP(fsgnjn_q, "fsgnjn.q", rv_codec_r, rv_fmt_frd_frs1_frs2,
> rvcp_fsgnjn_q)
> +OP(fsgnjx_q, "fsgnjx.q", rv_codec_r, rv_fmt_frd_frs1_frs2,
> rvcp_fsgnjx_q)
> +OP(fmin_q, "fmin.q", rv_codec_r, rv_fmt_frd_frs1_frs2)
> +OP(fmax_q, "fmax.q", rv_codec_r, rv_fmt_frd_frs1_frs2)
> +OP(fcvt_s_q, "fcvt.s.q", rv_codec_r_m, rv_fmt_rm_frd_frs1)
> +OP(fcvt_q_s, "fcvt.q.s", rv_codec_r_m, rv_fmt_rm_frd_frs1)
> +OP(fcvt_d_q, "fcvt.d.q", rv_codec_r_m, rv_fmt_rm_frd_frs1)
> +OP(fcvt_q_d, "fcvt.q.d", rv_codec_r_m, rv_fmt_rm_frd_frs1)
> +OP(fsqrt_q, "fsqrt.q", rv_codec_r_m, rv_fmt_rm_frd_frs1)
> +OP(fle_q, "fle.q", rv_codec_r, rv_fmt_rd_frs1_frs2)
> +OP(flt_q, "flt.q", rv_codec_r, rv_fmt_rd_frs1_frs2)
> +OP(feq_q, "feq.q", rv_codec_r, rv_fmt_rd_frs1_frs2)
> +OP(fcvt_w_q, "fcvt.w.q", rv_codec_r_m, rv_fmt_rm_rd_frs1)
> +OP(fcvt_wu_q, "fcvt.wu.q", rv_codec_r_m, rv_fmt_rm_rd_frs1)
> +OP(fcvt_q_w, "fcvt.q.w", rv_codec_r_m, rv_fmt_rm_frd_rs1)
> +OP(fcvt_q_wu, "fcvt.q.wu", rv_codec_r_m, rv_fmt_rm_frd_rs1)
> +OP(fclass_q, "fclass.q", rv_codec_r, rv_fmt_rd_frs1)
> +OP(fcvt_l_q, "fcvt.l.q", rv_codec_r_m, rv_fmt_rm_rd_frs1)
> +OP(fcvt_lu_q, "fcvt.lu.q", rv_codec_r_m, rv_fmt_rm_rd_frs1)
> +OP(fcvt_q_l, "fcvt.q.l", rv_codec_r_m, rv_fmt_rm_frd_rs1)
> +OP(fcvt_q_lu, "fcvt.q.lu", rv_codec_r_m, rv_fmt_rm_frd_rs1)
> +OP(fmv_x_q, "fmv.x.q", rv_codec_r, rv_fmt_rd_frs1)
> +OP(fmv_q_x, "fmv.q.x", rv_codec_r, rv_fmt_frd_rs1)
> +OP(c_addi4spn, "c.addi4spn", rv_codec_ciw_4spn, NULL,
> DECOMP(rv_op_addi))
> +OP(c_fld, "c.fld", rv_codec_cl_ld, NULL, DECOMP(rv_op_fld))
> +OP(c_lw, "c.lw", rv_codec_cl_lw, NULL, DECOMP(rv_op_lw))
> +OP(c_flw, "c.flw", rv_codec_cl_lw, NULL, DECOMP(rv_op_flw))
> +OP(c_fsd, "c.fsd", rv_codec_cs_sd, NULL, DECOMP(rv_op_fsd))
> +OP(c_sw, "c.sw", rv_codec_cs_sw, NULL, DECOMP(rv_op_sw))
> +OP(c_fsw, "c.fsw", rv_codec_cs_sw, NULL, DECOMP(rv_op_fsw))
> +OP(c_addi, "c.addi", rv_codec_ci, NULL, DECOMP(rv_op_addi))
> +OP(c_jal, "c.jal", rv_codec_cj_jal, NULL, DECOMP(rv_op_jal))
> +OP(c_li, "c.li", rv_codec_ci_li, NULL, DECOMP(rv_op_addi))
> +OP(c_addi16sp, "c.addi16sp", rv_codec_ci_16sp, NULL,
> DECOMP(rv_op_addi))
> +OP(c_lui, "c.lui", rv_codec_ci_lui, NULL, DECOMP(rv_op_lui))
> +OP(c_srli, "c.srli", rv_codec_cb_sh6, NULL, DECOMP(rv_op_srli))
> +OP(c_srai, "c.srai", rv_codec_cb_sh6, NULL, DECOMP(rv_op_srai))
> +OP(c_andi, "c.andi", rv_codec_cb_imm, NULL, DECOMP(rv_op_andi))
> +OP(c_sub, "c.sub", rv_codec_cs, NULL, DECOMP(rv_op_sub))
> +OP(c_xor, "c.xor", rv_codec_cs, NULL, DECOMP(rv_op_xor))
> +OP(c_or, "c.or", rv_codec_cs, NULL, DECOMP(rv_op_or))
> +OP(c_and, "c.and", rv_codec_cs, NULL, DECOMP(rv_op_and))
> +OP(c_subw, "c.subw", rv_codec_cs, NULL, DECOMP(rv_op_subw))
> +OP(c_addw, "c.addw", rv_codec_cs, NULL, DECOMP(rv_op_addw))
> +OP(c_j, "c.j", rv_codec_cj, NULL, DECOMP(rv_op_j))
> +OP(c_beqz, "c.beqz", rv_codec_cb, NULL, DECOMP(rv_op_beqz))
> +OP(c_bnez, "c.bnez", rv_codec_cb, NULL, DECOMP(rv_op_bnez))
> +OP(c_slli, "c.slli", rv_codec_ci_sh6, NULL, DECOMP(rv_op_slli))
> +OP(c_fldsp, "c.fldsp", rv_codec_ci_ldsp, NULL, DECOMP(rv_op_fld))
> +OP(c_lwsp, "c.lwsp", rv_codec_ci_lwsp, NULL, DECOMP(rv_op_lw))
> +OP(c_flwsp, "c.flwsp", rv_codec_ci_lwsp, NULL, DECOMP(rv_op_flw))
> +OP(c_jr, "c.jr", rv_codec_cr_jr, NULL, DECOMP(rv_op_jr))
> +OP(c_mv, "c.mv", rv_codec_cr_mv, NULL, DECOMP(rv_op_mv))
> +OP(c_ebreak, "c.ebreak", rv_codec_ci_none, NULL,
> DECOMP(rv_op_ebreak))
> +OP(c_jalr, "c.jalr", rv_codec_cr_jalr, NULL, DECOMP(rv_op_jalr))
> +OP(c_add, "c.add", rv_codec_cr, NULL, DECOMP(rv_op_add))
> +OP(c_fsdsp, "c.fsdsp", rv_codec_css_sdsp, NULL, DECOMP(rv_op_fsd))
> +OP(c_swsp, "c.swsp", rv_codec_css_swsp, NULL, DECOMP(rv_op_sw))
> +OP(c_fswsp, "c.fswsp", rv_codec_css_swsp, NULL, DECOMP(rv_op_fsw))
> +OP(c_ld, "c.ld", rv_codec_cl_ld, NULL, DECOMP(rv_op_ld))
> +OP(c_sd, "c.sd", rv_codec_cs_sd, NULL, DECOMP(rv_op_sd))
> +OP(c_addiw, "c.addiw", rv_codec_ci, NULL, DECOMP(rv_op_addiw))
> +OP(c_ldsp, "c.ldsp", rv_codec_ci_ldsp, NULL, DECOMP(rv_op_ld))
> +OP(c_sdsp, "c.sdsp", rv_codec_css_sdsp, NULL, DECOMP(rv_op_sd))
> +OP(c_lq, "c.lq", rv_codec_cl_lq, NULL, DECOMP(rv_op_lq))
> +OP(c_sq, "c.sq", rv_codec_cs_sq, NULL, DECOMP(rv_op_sq))
> +OP(c_lqsp, "c.lqsp", rv_codec_ci_lqsp, NULL, DECOMP(rv_op_lq))
> +OP(c_sqsp, "c.sqsp", rv_codec_css_sqsp, NULL, DECOMP(rv_op_sq))
> +OP(nop, "nop", rv_codec_illegal, rv_fmt_none)
> +OP(mv, "mv", rv_codec_illegal, rv_fmt_rd_rs1, rvcp_mv)
> +OP(not, "not", rv_codec_illegal, rv_fmt_rd_rs1)
> +OP(neg, "neg", rv_codec_illegal, rv_fmt_rd_rs2)
> +OP(negw, "negw", rv_codec_illegal, rv_fmt_rd_rs2)
> +OP(sext_w, "sext.w", rv_codec_illegal, rv_fmt_rd_rs1)
> +OP(seqz, "seqz", rv_codec_illegal, rv_fmt_rd_rs1)
> +OP(snez, "snez", rv_codec_illegal, rv_fmt_rd_rs2)
> +OP(sltz, "sltz", rv_codec_illegal, rv_fmt_rd_rs1)
> +OP(sgtz, "sgtz", rv_codec_illegal, rv_fmt_rd_rs2)
> +OP(fmv_s, "fmv.s", rv_codec_illegal, rv_fmt_frd_frs1)
> +OP(fabs_s, "fabs.s", rv_codec_illegal, rv_fmt_frd_frs1)
> +OP(fneg_s, "fneg.s", rv_codec_illegal, rv_fmt_frd_frs1)
> +OP(fmv_d, "fmv.d", rv_codec_illegal, rv_fmt_frd_frs1)
> +OP(fabs_d, "fabs.d", rv_codec_illegal, rv_fmt_frd_frs1)
> +OP(fneg_d, "fneg.d", rv_codec_illegal, rv_fmt_frd_frs1)
> +OP(fmv_q, "fmv.q", rv_codec_illegal, rv_fmt_frd_frs1)
> +OP(fabs_q, "fabs.q", rv_codec_illegal, rv_fmt_frd_frs1)
> +OP(fneg_q, "fneg.q", rv_codec_illegal, rv_fmt_frd_frs1)
> +OP(beqz, "beqz", rv_codec_illegal, rv_fmt_rs1_offset)
> +OP(bnez, "bnez", rv_codec_illegal, rv_fmt_rs1_offset)
> +OP(blez, "blez", rv_codec_illegal, rv_fmt_rs2_offset)
> +OP(bgez, "bgez", rv_codec_illegal, rv_fmt_rs1_offset)
> +OP(bltz, "bltz", rv_codec_illegal, rv_fmt_rs1_offset)
> +OP(bgtz, "bgtz", rv_codec_illegal, rv_fmt_rs2_offset)
> +OP(jal_ra, "jal", rv_codec_illegal, rv_fmt_offset)
> +OP(jalr_ra, "jalr", rv_codec_illegal, rv_fmt_rs1)
> +OP(j, "j", rv_codec_illegal, rv_fmt_offset)
> +OP(ret, "ret", rv_codec_illegal, rv_fmt_none)
> +OP(jr, "jr", rv_codec_illegal, rv_fmt_rs1, rvcp_jr)
> +OP(rdcycle, "rdcycle", rv_codec_i_csr, rv_fmt_rd)
> +OP(rdtime, "rdtime", rv_codec_i_csr, rv_fmt_rd)
> +OP(rdinstret, "rdinstret", rv_codec_i_csr, rv_fmt_rd)
> +OP(rdcycleh, "rdcycleh", rv_codec_i_csr, rv_fmt_rd)
> +OP(rdtimeh, "rdtimeh", rv_codec_i_csr, rv_fmt_rd)
> +OP(rdinstreth, "rdinstreth", rv_codec_i_csr, rv_fmt_rd)
> +OP(frcsr, "frcsr", rv_codec_i_csr, rv_fmt_rd)
> +OP(frrm, "frrm", rv_codec_i_csr, rv_fmt_rd)
> +OP(frflags, "frflags", rv_codec_i_csr, rv_fmt_rd)
> +OP(fscsr, "fscsr", rv_codec_i_csr, rv_fmt_rd_rs1)
> +OP(fsrm, "fsrm", rv_codec_i_csr, rv_fmt_rd_rs1)
> +OP(fsflags, "fsflags", rv_codec_i_csr, rv_fmt_rd_rs1)
> +OP(fsrmi, "fsrmi", rv_codec_i_csr, rv_fmt_rd_zimm)
> +OP(fsflagsi, "fsflagsi", rv_codec_i_csr, rv_fmt_rd_zimm)
> +OP(bseti, "bseti", rv_codec_i_sh7, rv_fmt_rd_rs1_imm)
> +OP(bclri, "bclri", rv_codec_i_sh7, rv_fmt_rd_rs1_imm)
> +OP(binvi, "binvi", rv_codec_i_sh7, rv_fmt_rd_rs1_imm)
> +OP(bexti, "bexti", rv_codec_i_sh7, rv_fmt_rd_rs1_imm)
> +OP(rori, "rori", rv_codec_i_sh7, rv_fmt_rd_rs1_imm)
> +OP(clz, "clz", rv_codec_r, rv_fmt_rd_rs1)
> +OP(ctz, "ctz", rv_codec_r, rv_fmt_rd_rs1)
> +OP(cpop, "cpop", rv_codec_r, rv_fmt_rd_rs1)
> +OP(sext_h, "sext.h", rv_codec_r, rv_fmt_rd_rs1)
> +OP(sext_b, "sext.b", rv_codec_r, rv_fmt_rd_rs1)
> +OP(xnor, "xnor", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(orn, "orn", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(andn, "andn", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(rol, "rol", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(ror, "ror", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(sh1add, "sh1add", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(sh2add, "sh2add", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(sh3add, "sh3add", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(sh1add_uw, "sh1add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(sh2add_uw, "sh2add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(sh3add_uw, "sh3add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(clmul, "clmul", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(clmulr, "clmulr", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(clmulh, "clmulh", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(min, "min", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(minu, "minu", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(max, "max", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(maxu, "maxu", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(clzw, "clzw", rv_codec_r, rv_fmt_rd_rs1)
> +OP(ctzw, "ctzw", rv_codec_r, rv_fmt_rd_rs1)
> +OP(cpopw, "cpopw", rv_codec_r, rv_fmt_rd_rs1)
> +OP(slli_uw, "slli.uw", rv_codec_i_sh6, rv_fmt_rd_rs1_imm)
> +OP(add_uw, "add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(rolw, "rolw", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(rorw, "rorw", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(rev8, "rev8", rv_codec_r, rv_fmt_rd_rs1)
> +OP(zext_h, "zext.h", rv_codec_r, rv_fmt_rd_rs1)
> +OP(roriw, "roriw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm)
> +OP(orc_b, "orc.b", rv_codec_r, rv_fmt_rd_rs1)
> +OP(bset, "bset", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(bclr, "bclr", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(binv, "binv", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(bext, "bext", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(aes32esmi, "aes32esmi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs)
> +OP(aes32esi, "aes32esi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs)
> +OP(aes32dsmi, "aes32dsmi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs)
> +OP(aes32dsi, "aes32dsi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs)
> +OP(aes64ks1i, "aes64ks1i", rv_codec_k_rnum, rv_fmt_rd_rs1_rnum)
> +OP(aes64ks2, "aes64ks2", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(aes64im, "aes64im", rv_codec_r, rv_fmt_rd_rs1)
> +OP(aes64esm, "aes64esm", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(aes64es, "aes64es", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(aes64dsm, "aes64dsm", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(aes64ds, "aes64ds", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(sha256sig0, "sha256sig0", rv_codec_r, rv_fmt_rd_rs1)
> +OP(sha256sig1, "sha256sig1", rv_codec_r, rv_fmt_rd_rs1)
> +OP(sha256sum0, "sha256sum0", rv_codec_r, rv_fmt_rd_rs1)
> +OP(sha256sum1, "sha256sum1", rv_codec_r, rv_fmt_rd_rs1)
> +OP(sha512sig0, "sha512sig0", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(sha512sig1, "sha512sig1", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(sha512sum0, "sha512sum0", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(sha512sum1, "sha512sum1", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(sha512sum0r, "sha512sum0r", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(sha512sum1r, "sha512sum1r", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(sha512sig0l, "sha512sig0l", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(sha512sig0h, "sha512sig0h", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(sha512sig1l, "sha512sig1l", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(sha512sig1h, "sha512sig1h", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(sm3p0, "sm3p0", rv_codec_r, rv_fmt_rd_rs1)
> +OP(sm3p1, "sm3p1", rv_codec_r, rv_fmt_rd_rs1)
> +OP(sm4ed, "sm4ed", rv_codec_k_bs, rv_fmt_rs1_rs2_bs)
> +OP(sm4ks, "sm4ks", rv_codec_k_bs, rv_fmt_rs1_rs2_bs)
> +OP(brev8, "brev8", rv_codec_r, rv_fmt_rd_rs1)
> +OP(pack, "pack", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(packh, "packh", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(packw, "packw", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(unzip, "unzip", rv_codec_r, rv_fmt_rd_rs1)
> +OP(zip, "zip", rv_codec_r, rv_fmt_rd_rs1)
> +OP(xperm4, "xperm4", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(xperm8, "xperm8", rv_codec_r, rv_fmt_rd_rs1)
> +OP(vle8_v, "vle8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
> +OP(vle16_v, "vle16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
> +OP(vle32_v, "vle32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
> +OP(vle64_v, "vle64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
> +OP(vse8_v, "vse8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
> +OP(vse16_v, "vse16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
> +OP(vse32_v, "vse32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
> +OP(vse64_v, "vse64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
> +OP(vlm_v, "vlm.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
> +OP(vsm_v, "vsm.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
> +OP(vlse8_v, "vlse8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm)
> +OP(vlse16_v, "vlse16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm)
> +OP(vlse32_v, "vlse32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm)
> +OP(vlse64_v, "vlse64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm)
> +OP(vsse8_v, "vsse8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm)
> +OP(vsse16_v, "vsse16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm)
> +OP(vsse32_v, "vsse32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm)
> +OP(vsse64_v, "vsse64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm)
> +OP(vluxei8_v, "vluxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm)
> +OP(vluxei16_v, "vluxei16.v", rv_codec_v_r,
> rv_fmt_ldst_vd_rs1_vs2_vm)
> +OP(vluxei32_v, "vluxei32.v", rv_codec_v_r,
> rv_fmt_ldst_vd_rs1_vs2_vm)
> +OP(vluxei64_v, "vluxei64.v", rv_codec_v_r,
> rv_fmt_ldst_vd_rs1_vs2_vm)
> +OP(vloxei8_v, "vloxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm)
> +OP(vloxei16_v, "vloxei16.v", rv_codec_v_r,
> rv_fmt_ldst_vd_rs1_vs2_vm)
> +OP(vloxei32_v, "vloxei32.v", rv_codec_v_r,
> rv_fmt_ldst_vd_rs1_vs2_vm)
> +OP(vloxei64_v, "vloxei64.v", rv_codec_v_r,
> rv_fmt_ldst_vd_rs1_vs2_vm)
> +OP(vsuxei8_v, "vsuxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm)
> +OP(vsuxei16_v, "vsuxei16.v", rv_codec_v_r,
> rv_fmt_ldst_vd_rs1_vs2_vm)
> +OP(vsuxei32_v, "vsuxei32.v", rv_codec_v_r,
> rv_fmt_ldst_vd_rs1_vs2_vm)
> +OP(vsuxei64_v, "vsuxei64.v", rv_codec_v_r,
> rv_fmt_ldst_vd_rs1_vs2_vm)
> +OP(vsoxei8_v, "vsoxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm)
> +OP(vsoxei16_v, "vsoxei16.v", rv_codec_v_r,
> rv_fmt_ldst_vd_rs1_vs2_vm)
> +OP(vsoxei32_v, "vsoxei32.v", rv_codec_v_r,
> rv_fmt_ldst_vd_rs1_vs2_vm)
> +OP(vsoxei64_v, "vsoxei64.v", rv_codec_v_r,
> rv_fmt_ldst_vd_rs1_vs2_vm)
> +OP(vle8ff_v, "vle8ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
> +OP(vle16ff_v, "vle16ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
> +OP(vle32ff_v, "vle32ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
> +OP(vle64ff_v, "vle64ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
> +OP(vl1re8_v, "vl1re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
> +OP(vl1re16_v, "vl1re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
> +OP(vl1re32_v, "vl1re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
> +OP(vl1re64_v, "vl1re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
> +OP(vl2re8_v, "vl2re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
> +OP(vl2re16_v, "vl2re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
> +OP(vl2re32_v, "vl2re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
> +OP(vl2re64_v, "vl2re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
> +OP(vl4re8_v, "vl4re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
> +OP(vl4re16_v, "vl4re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
> +OP(vl4re32_v, "vl4re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
> +OP(vl4re64_v, "vl4re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
> +OP(vl8re8_v, "vl8re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
> +OP(vl8re16_v, "vl8re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
> +OP(vl8re32_v, "vl8re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
> +OP(vl8re64_v, "vl8re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
> +OP(vs1r_v, "vs1r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
> +OP(vs2r_v, "vs2r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
> +OP(vs4r_v, "vs4r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
> +OP(vs8r_v, "vs8r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
> +OP(vadd_vv, "vadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vadd_vx, "vadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> +OP(vadd_vi, "vadd.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm)
> +OP(vsub_vv, "vsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vsub_vx, "vsub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> +OP(vrsub_vx, "vrsub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> +OP(vrsub_vi, "vrsub.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm)
> +OP(vwaddu_vv, "vwaddu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vwaddu_vx, "vwaddu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> +OP(vwadd_vv, "vwadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vwadd_vx, "vwadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> +OP(vwsubu_vv, "vwsubu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vwsubu_vx, "vwsubu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> +OP(vwsub_vv, "vwsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vwsub_vx, "vwsub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> +OP(vwaddu_wv, "vwaddu.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vwaddu_wx, "vwaddu.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> +OP(vwadd_wv, "vwadd.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vwadd_wx, "vwadd.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> +OP(vwsubu_wv, "vwsubu.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vwsubu_wx, "vwsubu.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> +OP(vwsub_wv, "vwsub.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vwsub_wx, "vwsub.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> +OP(vadc_vvm, "vadc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl)
> +OP(vadc_vxm, "vadc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl)
> +OP(vadc_vim, "vadc.vim", rv_codec_v_i, rv_fmt_vd_vs2_imm_vl)
> +OP(vmadc_vvm, "vmadc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl)
> +OP(vmadc_vxm, "vmadc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl)
> +OP(vmadc_vim, "vmadc.vim", rv_codec_v_i, rv_fmt_vd_vs2_imm_vl)
> +OP(vsbc_vvm, "vsbc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl)
> +OP(vsbc_vxm, "vsbc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl)
> +OP(vmsbc_vvm, "vmsbc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl)
> +OP(vmsbc_vxm, "vmsbc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl)
> +OP(vand_vv, "vand.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vand_vx, "vand.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> +OP(vand_vi, "vand.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm)
> +OP(vor_vv, "vor.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vor_vx, "vor.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> +OP(vor_vi, "vor.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm)
> +OP(vxor_vv, "vxor.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vxor_vx, "vxor.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> +OP(vxor_vi, "vxor.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm)
> +OP(vsll_vv, "vsll.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vsll_vx, "vsll.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> +OP(vsll_vi, "vsll.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm)
> +OP(vsrl_vv, "vsrl.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vsrl_vx, "vsrl.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> +OP(vsrl_vi, "vsrl.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm)
> +OP(vsra_vv, "vsra.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vsra_vx, "vsra.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> +OP(vsra_vi, "vsra.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm)
> +OP(vnsrl_wv, "vnsrl.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vnsrl_wx, "vnsrl.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> +OP(vnsrl_wi, "vnsrl.wi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm)
> +OP(vnsra_wv, "vnsra.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vnsra_wx, "vnsra.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> +OP(vnsra_wi, "vnsra.wi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm)
> +OP(vmseq_vv, "vmseq.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vmseq_vx, "vmseq.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> +OP(vmseq_vi, "vmseq.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm)
> +OP(vmsne_vv, "vmsne.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vmsne_vx, "vmsne.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> +OP(vmsne_vi, "vmsne.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm)
> +OP(vmsltu_vv, "vmsltu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vmsltu_vx, "vmsltu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> +OP(vmslt_vv, "vmslt.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vmslt_vx, "vmslt.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> +OP(vmsleu_vv, "vmsleu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vmsleu_vx, "vmsleu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> +OP(vmsleu_vi, "vmsleu.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm)
> +OP(vmsle_vv, "vmsle.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vmsle_vx, "vmsle.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> +OP(vmsle_vi, "vmsle.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm)
> +OP(vmsgtu_vx, "vmsgtu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> +OP(vmsgtu_vi, "vmsgtu.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm)
> +OP(vmsgt_vx, "vmsgt.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> +OP(vmsgt_vi, "vmsgt.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm)
> +OP(vminu_vv, "vminu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vminu_vx, "vminu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> +OP(vmin_vv, "vmin.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vmin_vx, "vmin.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> +OP(vmaxu_vv, "vmaxu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vmaxu_vx, "vmaxu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> +OP(vmax_vv, "vmax.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vmax_vx, "vmax.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> +OP(vmul_vv, "vmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vmul_vx, "vmul.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> +OP(vmulh_vv, "vmulh.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vmulh_vx, "vmulh.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> +OP(vmulhu_vv, "vmulhu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vmulhu_vx, "vmulhu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> +OP(vmulhsu_vv, "vmulhsu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vmulhsu_vx, "vmulhsu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> +OP(vdivu_vv, "vdivu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vdivu_vx, "vdivu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> +OP(vdiv_vv, "vdiv.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vdiv_vx, "vdiv.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> +OP(vremu_vv, "vremu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vremu_vx, "vremu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> +OP(vrem_vv, "vrem.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vrem_vx, "vrem.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> +OP(vwmulu_vv, "vwmulu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vwmulu_vx, "vwmulu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> +OP(vwmulsu_vv, "vwmulsu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vwmulsu_vx, "vwmulsu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> +OP(vwmul_vv, "vwmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vwmul_vx, "vwmul.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> +OP(vmacc_vv, "vmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
> +OP(vmacc_vx, "vmacc.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm)
> +OP(vnmsac_vv, "vnmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
> +OP(vnmsac_vx, "vnmsac.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm)
> +OP(vmadd_vv, "vmadd.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
> +OP(vmadd_vx, "vmadd.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm)
> +OP(vnmsub_vv, "vnmsub.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
> +OP(vnmsub_vx, "vnmsub.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm)
> +OP(vwmaccu_vv, "vwmaccu.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
> +OP(vwmaccu_vx, "vwmaccu.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm)
> +OP(vwmacc_vv, "vwmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
> +OP(vwmacc_vx, "vwmacc.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm)
> +OP(vwmaccsu_vv, "vwmaccsu.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
> +OP(vwmaccsu_vx, "vwmaccsu.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm)
> +OP(vwmaccus_vx, "vwmaccus.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm)
> +OP(vmv_v_v, "vmv.v.v", rv_codec_v_r, rv_fmt_vd_vs1)
> +OP(vmv_v_x, "vmv.v.x", rv_codec_v_r, rv_fmt_vd_rs1)
> +OP(vmv_v_i, "vmv.v.i", rv_codec_v_i, rv_fmt_vd_imm)
> +OP(vmerge_vvm, "vmerge.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl)
> +OP(vmerge_vxm, "vmerge.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl)
> +OP(vmerge_vim, "vmerge.vim", rv_codec_v_i, rv_fmt_vd_vs2_imm_vl)
> +OP(vsaddu_vv, "vsaddu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vsaddu_vx, "vsaddu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> +OP(vsaddu_vi, "vsaddu.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm)
> +OP(vsadd_vv, "vsadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vsadd_vx, "vsadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> +OP(vsadd_vi, "vsadd.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm)
> +OP(vssubu_vv, "vssubu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vssubu_vx, "vssubu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> +OP(vssub_vv, "vssub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vssub_vx, "vssub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> +OP(vaadd_vv, "vaadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vaadd_vx, "vaadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> +OP(vaaddu_vv, "vaaddu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vaaddu_vx, "vaaddu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> +OP(vasub_vv, "vasub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vasub_vx, "vasub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> +OP(vasubu_vv, "vasubu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vasubu_vx, "vasubu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> +OP(vsmul_vv, "vsmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vsmul_vx, "vsmul.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> +OP(vssrl_vv, "vssrl.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vssrl_vx, "vssrl.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> +OP(vssrl_vi, "vssrl.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm)
> +OP(vssra_vv, "vssra.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vssra_vx, "vssra.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> +OP(vssra_vi, "vssra.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm)
> +OP(vnclipu_wv, "vnclipu.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vnclipu_wx, "vnclipu.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> +OP(vnclipu_wi, "vnclipu.wi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm)
> +OP(vnclip_wv, "vnclip.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vnclip_wx, "vnclip.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> +OP(vnclip_wi, "vnclip.wi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm)
> +OP(vfadd_vv, "vfadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vfadd_vf, "vfadd.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
> +OP(vfsub_vv, "vfsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vfsub_vf, "vfsub.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
> +OP(vfrsub_vf, "vfrsub.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
> +OP(vfwadd_vv, "vfwadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vfwadd_vf, "vfwadd.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
> +OP(vfwadd_wv, "vfwadd.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vfwadd_wf, "vfwadd.wf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
> +OP(vfwsub_vv, "vfwsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vfwsub_vf, "vfwsub.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
> +OP(vfwsub_wv, "vfwsub.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vfwsub_wf, "vfwsub.wf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
> +OP(vfmul_vv, "vfmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vfmul_vf, "vfmul.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
> +OP(vfdiv_vv, "vfdiv.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vfdiv_vf, "vfdiv.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
> +OP(vfrdiv_vf, "vfrdiv.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
> +OP(vfwmul_vv, "vfwmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vfwmul_vf, "vfwmul.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
> +OP(vfmacc_vv, "vfmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
> +OP(vfmacc_vf, "vfmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm)
> +OP(vfnmacc_vv, "vfnmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
> +OP(vfnmacc_vf, "vfnmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm)
> +OP(vfmsac_vv, "vfmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
> +OP(vfmsac_vf, "vfmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm)
> +OP(vfnmsac_vv, "vfnmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
> +OP(vfnmsac_vf, "vfnmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm)
> +OP(vfmadd_vv, "vfmadd.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
> +OP(vfmadd_vf, "vfmadd.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm)
> +OP(vfnmadd_vv, "vfnmadd.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
> +OP(vfnmadd_vf, "vfnmadd.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm)
> +OP(vfmsub_vv, "vfmsub.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
> +OP(vfmsub_vf, "vfmsub.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm)
> +OP(vfnmsub_vv, "vfnmsub.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
> +OP(vfnmsub_vf, "vfnmsub.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm)
> +OP(vfwmacc_vv, "vfwmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
> +OP(vfwmacc_vf, "vfwmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm)
> +OP(vfwnmacc_vv, "vfwnmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
> +OP(vfwnmacc_vf, "vfwnmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm)
> +OP(vfwmsac_vv, "vfwmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
> +OP(vfwmsac_vf, "vfwmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm)
> +OP(vfwnmsac_vv, "vfwnmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
> +OP(vfwnmsac_vf, "vfwnmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm)
> +OP(vfsqrt_v, "vfsqrt.v", rv_codec_v_r, rv_fmt_vd_vs2)
> +OP(vfrsqrt7_v, "vfrsqrt7.v", rv_codec_v_r, rv_fmt_vd_vs2)
> +OP(vfrec7_v, "vfrec7.v", rv_codec_v_r, rv_fmt_vd_vs2)
> +OP(vfmin_vv, "vfmin.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vfmin_vf, "vfmin.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
> +OP(vfmax_vv, "vfmax.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vfmax_vf, "vfmax.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
> +OP(vfsgnj_vv, "vfsgnj.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vfsgnj_vf, "vfsgnj.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
> +OP(vfsgnjn_vv, "vfsgnjn.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vfsgnjn_vf, "vfsgnjn.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
> +OP(vfsgnjx_vv, "vfsgnjx.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vfsgnjx_vf, "vfsgnjx.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
> +OP(vfslide1up_vf, "vfslide1up.vf", rv_codec_v_r,
> rv_fmt_vd_vs2_fs1_vm)
> +OP(vfslide1down_vf, "vfslide1down.vf", rv_codec_v_r,
> rv_fmt_vd_vs2_fs1_vm)
> +OP(vmfeq_vv, "vmfeq.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vmfeq_vf, "vmfeq.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
> +OP(vmfne_vv, "vmfne.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vmfne_vf, "vmfne.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
> +OP(vmflt_vv, "vmflt.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vmflt_vf, "vmflt.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
> +OP(vmfle_vv, "vmfle.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vmfle_vf, "vmfle.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
> +OP(vmfgt_vf, "vmfgt.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
> +OP(vmfge_vf, "vmfge.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
> +OP(vfclass_v, "vfclass.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
> +OP(vfmerge_vfm, "vfmerge.vfm", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vl)
> +OP(vfmv_v_f, "vfmv.v.f", rv_codec_v_r, rv_fmt_vd_fs1)
> +OP(vfcvt_xu_f_v, "vfcvt.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
> +OP(vfcvt_x_f_v, "vfcvt.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
> +OP(vfcvt_f_xu_v, "vfcvt.f.xu.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
> +OP(vfcvt_f_x_v, "vfcvt.f.x.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
> +OP(vfcvt_rtz_xu_f_v, "vfcvt.rtz.xu.f.v", rv_codec_v_r,
> rv_fmt_vd_vs2_vm)
> +OP(vfcvt_rtz_x_f_v, "vfcvt.rtz.x.f.v", rv_codec_v_r,
> rv_fmt_vd_vs2_vm)
> +OP(vfwcvt_xu_f_v, "vfwcvt.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
> +OP(vfwcvt_x_f_v, "vfwcvt.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
> +OP(vfwcvt_f_xu_v, "vfwcvt.f.xu.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
> +OP(vfwcvt_f_x_v, "vfwcvt.f.x.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
> +OP(vfwcvt_f_f_v, "vfwcvt.f.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
> +OP(vfwcvt_rtz_xu_f_v, "vfwcvt.rtz.xu.f.v", rv_codec_v_r,
> rv_fmt_vd_vs2_vm)
> +OP(vfwcvt_rtz_x_f_v, "vfwcvt.rtz.x.f.v", rv_codec_v_r,
> rv_fmt_vd_vs2_vm)
> +OP(vfncvt_xu_f_w, "vfncvt.xu.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm)
> +OP(vfncvt_x_f_w, "vfncvt.x.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm)
> +OP(vfncvt_f_xu_w, "vfncvt.f.xu.w", rv_codec_v_r, rv_fmt_vd_vs2_vm)
> +OP(vfncvt_f_x_w, "vfncvt.f.x.w", rv_codec_v_r, rv_fmt_vd_vs2_vm)
> +OP(vfncvt_f_f_w, "vfncvt.f.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm)
> +OP(vfncvt_rod_f_f_w, "vfncvt.rod.f.f.w", rv_codec_v_r,
> rv_fmt_vd_vs2_vm)
> +OP(vfncvt_rtz_xu_f_w, "vfncvt.rtz.xu.f.w", rv_codec_v_r,
> rv_fmt_vd_vs2_vm)
> +OP(vfncvt_rtz_x_f_w, "vfncvt.rtz.x.f.w", rv_codec_v_r,
> rv_fmt_vd_vs2_vm)
> +OP(vredsum_vs, "vredsum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vredand_vs, "vredand.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vredor_vs, "vredor.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vredxor_vs, "vredxor.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vredminu_vs, "vredminu.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vredmin_vs, "vredmin.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vredmaxu_vs, "vredmaxu.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vredmax_vs, "vredmax.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vwredsumu_vs, "vwredsumu.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vwredsum_vs, "vwredsum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vfredusum_vs, "vfredusum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vfredosum_vs, "vfredosum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vfredmin_vs, "vfredmin.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vfredmax_vs, "vfredmax.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vfwredusum_vs, "vfwredusum.vs", rv_codec_v_r,
> rv_fmt_vd_vs2_vs1_vm)
> +OP(vfwredosum_vs, "vfwredosum.vs", rv_codec_v_r,
> rv_fmt_vd_vs2_vs1_vm)
> +OP(vmand_mm, "vmand.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vmnand_mm, "vmnand.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vmandn_mm, "vmandn.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vmxor_mm, "vmxor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vmor_mm, "vmor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vmnor_mm, "vmnor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vmorn_mm, "vmorn.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vmxnor_mm, "vmxnor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vcpop_m, "vcpop.m", rv_codec_v_r, rv_fmt_rd_vs2_vm)
> +OP(vfirst_m, "vfirst.m", rv_codec_v_r, rv_fmt_rd_vs2_vm)
> +OP(vmsbf_m, "vmsbf.m", rv_codec_v_r, rv_fmt_vd_vs2_vm)
> +OP(vmsif_m, "vmsif.m", rv_codec_v_r, rv_fmt_vd_vs2_vm)
> +OP(vmsof_m, "vmsof.m", rv_codec_v_r, rv_fmt_vd_vs2_vm)
> +OP(viota_m, "viota.m", rv_codec_v_r, rv_fmt_vd_vs2_vm)
> +OP(vid_v, "vid.v", rv_codec_v_r, rv_fmt_vd_vm)
> +OP(vmv_x_s, "vmv.x.s", rv_codec_v_r, rv_fmt_rd_vs2)
> +OP(vmv_s_x, "vmv.s.x", rv_codec_v_r, rv_fmt_vd_rs1)
> +OP(vfmv_f_s, "vfmv.f.s", rv_codec_v_r, rv_fmt_fd_vs2)
> +OP(vfmv_s_f, "vfmv.s.f", rv_codec_v_r, rv_fmt_vd_fs1)
> +OP(vslideup_vx, "vslideup.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> +OP(vslideup_vi, "vslideup.vi", rv_codec_v_i_u,
> rv_fmt_vd_vs2_uimm_vm)
> +OP(vslide1up_vx, "vslide1up.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> +OP(vslidedown_vx, "vslidedown.vx", rv_codec_v_r,
> rv_fmt_vd_vs2_rs1_vm)
> +OP(vslidedown_vi, "vslidedown.vi", rv_codec_v_i_u,
> rv_fmt_vd_vs2_uimm_vm)
> +OP(vslide1down_vx, "vslide1down.vx", rv_codec_v_r,
> rv_fmt_vd_vs2_rs1_vm)
> +OP(vrgather_vv, "vrgather.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vrgatherei16_vv, "vrgatherei16.vv", rv_codec_v_r,
> rv_fmt_vd_vs2_vs1_vm)
> +OP(vrgather_vx, "vrgather.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> +OP(vrgather_vi, "vrgather.vi", rv_codec_v_i_u,
> rv_fmt_vd_vs2_uimm_vm)
> +OP(vcompress_vm, "vcompress.vm", rv_codec_v_r, rv_fmt_vd_vs2_vs1)
> +OP(vmv1r_v, "vmv1r.v", rv_codec_v_r, rv_fmt_vd_vs2)
> +OP(vmv2r_v, "vmv2r.v", rv_codec_v_r, rv_fmt_vd_vs2)
> +OP(vmv4r_v, "vmv4r.v", rv_codec_v_r, rv_fmt_vd_vs2)
> +OP(vmv8r_v, "vmv8r.v", rv_codec_v_r, rv_fmt_vd_vs2)
> +OP(vzext_vf2, "vzext.vf2", rv_codec_v_r, rv_fmt_vd_vs2_vm)
> +OP(vzext_vf4, "vzext.vf4", rv_codec_v_r, rv_fmt_vd_vs2_vm)
> +OP(vzext_vf8, "vzext.vf8", rv_codec_v_r, rv_fmt_vd_vs2_vm)
> +OP(vsext_vf2, "vsext.vf2", rv_codec_v_r, rv_fmt_vd_vs2_vm)
> +OP(vsext_vf4, "vsext.vf4", rv_codec_v_r, rv_fmt_vd_vs2_vm)
> +OP(vsext_vf8, "vsext.vf8", rv_codec_v_r, rv_fmt_vd_vs2_vm)
> +OP(vsetvli, "vsetvli", rv_codec_vsetvli, rv_fmt_vsetvli)
> +OP(vsetivli, "vsetivli", rv_codec_vsetivli, rv_fmt_vsetivli)
> +OP(vsetvl, "vsetvl", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(c_zext_b, "c.zext.b", rv_codec_zcb_ext, rv_fmt_rd)
> +OP(c_sext_b, "c.sext.b", rv_codec_zcb_ext, rv_fmt_rd)
> +OP(c_zext_h, "c.zext.h", rv_codec_zcb_ext, rv_fmt_rd)
> +OP(c_sext_h, "c.sext.h", rv_codec_zcb_ext, rv_fmt_rd)
> +OP(c_zext_w, "c.zext.w", rv_codec_zcb_ext, rv_fmt_rd)
> +OP(c_not, "c.not", rv_codec_zcb_ext, rv_fmt_rd)
> +OP(c_mul, "c.mul", rv_codec_zcb_mul, rv_fmt_rd_rs2)
> +OP(c_lbu, "c.lbu", rv_codec_zcb_lb, rv_fmt_rs1_rs2_zce_ldst)
> +OP(c_lhu, "c.lhu", rv_codec_zcb_lh, rv_fmt_rs1_rs2_zce_ldst)
> +OP(c_lh, "c.lh", rv_codec_zcb_lh, rv_fmt_rs1_rs2_zce_ldst)
> +OP(c_sb, "c.sb", rv_codec_zcb_lb, rv_fmt_rs1_rs2_zce_ldst)
> +OP(c_sh, "c.sh", rv_codec_zcb_lh, rv_fmt_rs1_rs2_zce_ldst)
> +OP(cm_push, "cm.push", rv_codec_zcmp_cm_pushpop, rv_fmt_push_rlist)
> +OP(cm_pop, "cm.pop", rv_codec_zcmp_cm_pushpop, rv_fmt_pop_rlist)
> +OP(cm_popret, "cm.popret", rv_codec_zcmp_cm_pushpop,
> rv_fmt_pop_rlist)
> +OP(cm_popretz, "cm.popretz", rv_codec_zcmp_cm_pushpop,
> rv_fmt_pop_rlist)
> +OP(cm_mva01s, "cm.mva01s", rv_codec_zcmp_cm_mv, rv_fmt_rd_rs2)
> +OP(cm_mvsa01, "cm.mvsa01", rv_codec_zcmp_cm_mv, rv_fmt_rd_rs2)
> +OP(cm_jt, "cm.jt", rv_codec_zcmt_jt, rv_fmt_zcmt_index)
> +OP(cm_jalt, "cm.jalt", rv_codec_zcmt_jt, rv_fmt_zcmt_index)
> +OP(czero_eqz, "czero.eqz", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(czero_nez, "czero.nez", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(fcvt_bf16_s, "fcvt.bf16.s", rv_codec_r_m, rv_fmt_rm_frd_frs1)
> +OP(fcvt_s_bf16, "fcvt.s.bf16", rv_codec_r_m, rv_fmt_rm_frd_frs1)
> +OP(vfncvtbf16_f_f_w, "vfncvtbf16.f.f.w", rv_codec_v_r,
> rv_fmt_vd_vs2_vm)
> +OP(vfwcvtbf16_f_f_v, "vfwcvtbf16.f.f.v", rv_codec_v_r,
> rv_fmt_vd_vs2_vm)
> +OP(vfwmaccbf16_vv, "vfwmaccbf16.vv", rv_codec_v_r,
> rv_fmt_vd_vs1_vs2_vm)
> +OP(vfwmaccbf16_vf, "vfwmaccbf16.vf", rv_codec_v_r,
> rv_fmt_vd_fs1_vs2_vm)
> +OP(flh, "flh", rv_codec_i, rv_fmt_frd_offset_rs1)
> +OP(fsh, "fsh", rv_codec_s, rv_fmt_frs2_offset_rs1)
> +OP(fmv_h_x, "fmv.h.x", rv_codec_r, rv_fmt_frd_rs1)
> +OP(fmv_x_h, "fmv.x.h", rv_codec_r, rv_fmt_rd_frs1)
> +OP(fli_s, "fli.s", rv_codec_fli, rv_fmt_fli)
> +OP(fli_d, "fli.d", rv_codec_fli, rv_fmt_fli)
> +OP(fli_q, "fli.q", rv_codec_fli, rv_fmt_fli)
> +OP(fli_h, "fli.h", rv_codec_fli, rv_fmt_fli)
> +OP(fminm_s, "fminm.s", rv_codec_r, rv_fmt_frd_frs1_frs2)
> +OP(fmaxm_s, "fmaxm.s", rv_codec_r, rv_fmt_frd_frs1_frs2)
> +OP(fminm_d, "fminm.d", rv_codec_r, rv_fmt_frd_frs1_frs2)
> +OP(fmaxm_d, "fmaxm.d", rv_codec_r, rv_fmt_frd_frs1_frs2)
> +OP(fminm_q, "fminm.q", rv_codec_r, rv_fmt_frd_frs1_frs2)
> +OP(fmaxm_q, "fmaxm.q", rv_codec_r, rv_fmt_frd_frs1_frs2)
> +OP(fminm_h, "fminm.h", rv_codec_r, rv_fmt_frd_frs1_frs2)
> +OP(fmaxm_h, "fmaxm.h", rv_codec_r, rv_fmt_frd_frs1_frs2)
> +OP(fround_s, "fround.s", rv_codec_r_m, rv_fmt_rm_frd_frs1)
> +OP(froundnx_s, "froundnx.s", rv_codec_r_m, rv_fmt_rm_frd_frs1)
> +OP(fround_d, "fround.d", rv_codec_r_m, rv_fmt_rm_frd_frs1)
> +OP(froundnx_d, "froundnx.d", rv_codec_r_m, rv_fmt_rm_frd_frs1)
> +OP(fround_q, "fround.q", rv_codec_r_m, rv_fmt_rm_frd_frs1)
> +OP(froundnx_q, "froundnx.q", rv_codec_r_m, rv_fmt_rm_frd_frs1)
> +OP(fround_h, "fround.h", rv_codec_r_m, rv_fmt_rm_frd_frs1)
> +OP(froundnx_h, "froundnx.h", rv_codec_r_m, rv_fmt_rm_frd_frs1)
> +OP(fcvtmod_w_d, "fcvtmod.w.d", rv_codec_r_m, rv_fmt_rm_rd_frs1)
> +OP(fmvh_x_d, "fmvh.x.d", rv_codec_r, rv_fmt_rd_frs1)
> +OP(fmvp_d_x, "fmvp.d.x", rv_codec_r, rv_fmt_frd_rs1_rs2)
> +OP(fmvh_x_q, "fmvh.x.q", rv_codec_r, rv_fmt_rd_frs1)
> +OP(fmvp_q_x, "fmvp.q.x", rv_codec_r, rv_fmt_frd_rs1_rs2)
> +OP(fleq_s, "fleq.s", rv_codec_r, rv_fmt_rd_frs1_frs2)
> +OP(fltq_s, "fltq.s", rv_codec_r, rv_fmt_rd_frs1_frs2)
> +OP(fleq_d, "fleq.d", rv_codec_r, rv_fmt_rd_frs1_frs2)
> +OP(fltq_d, "fltq.d", rv_codec_r, rv_fmt_rd_frs1_frs2)
> +OP(fleq_q, "fleq.q", rv_codec_r, rv_fmt_rd_frs1_frs2)
> +OP(fltq_q, "fltq.q", rv_codec_r, rv_fmt_rd_frs1_frs2)
> +OP(fleq_h, "fleq.h", rv_codec_r, rv_fmt_rd_frs1_frs2)
> +OP(fltq_h, "fltq.h", rv_codec_r, rv_fmt_rd_frs1_frs2)
> +OP(vaesdf_vv, "vaesdf.vv", rv_codec_v_r, rv_fmt_vd_vs2)
> +OP(vaesdf_vs, "vaesdf.vs", rv_codec_v_r, rv_fmt_vd_vs2)
> +OP(vaesdm_vv, "vaesdm.vv", rv_codec_v_r, rv_fmt_vd_vs2)
> +OP(vaesdm_vs, "vaesdm.vs", rv_codec_v_r, rv_fmt_vd_vs2)
> +OP(vaesef_vv, "vaesef.vv", rv_codec_v_r, rv_fmt_vd_vs2)
> +OP(vaesef_vs, "vaesef.vs", rv_codec_v_r, rv_fmt_vd_vs2)
> +OP(vaesem_vv, "vaesem.vv", rv_codec_v_r, rv_fmt_vd_vs2)
> +OP(vaesem_vs, "vaesem.vs", rv_codec_v_r, rv_fmt_vd_vs2)
> +OP(vaeskf1_vi, "vaeskf1.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm)
> +OP(vaeskf2_vi, "vaeskf2.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm)
> +OP(vaesz_vs, "vaesz.vs", rv_codec_v_r, rv_fmt_vd_vs2)
> +OP(vandn_vv, "vandn.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vandn_vx, "vandn.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> +OP(vbrev_v, "vbrev.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
> +OP(vbrev8_v, "vbrev8.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
> +OP(vclmul_vv, "vclmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vclmul_vx, "vclmul.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> +OP(vclmulh_vv, "vclmulh.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vclmulh_vx, "vclmulh.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> +OP(vclz_v, "vclz.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
> +OP(vcpop_v, "vcpop.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
> +OP(vctz_v, "vctz.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
> +OP(vghsh_vv, "vghsh.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1)
> +OP(vgmul_vv, "vgmul.vv", rv_codec_v_r, rv_fmt_vd_vs2)
> +OP(vrev8_v, "vrev8.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
> +OP(vrol_vv, "vrol.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vrol_vx, "vrol.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> +OP(vror_vv, "vror.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vror_vx, "vror.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> +OP(vror_vi, "vror.vi", rv_codec_vror_vi, rv_fmt_vd_vs2_uimm_vm)
> +OP(vsha2ch_vv, "vsha2ch.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1)
> +OP(vsha2cl_vv, "vsha2cl.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1)
> +OP(vsha2ms_vv, "vsha2ms.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1)
> +OP(vsm3c_vi, "vsm3c.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm)
> +OP(vsm3me_vv, "vsm3me.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1)
> +OP(vsm4k_vi, "vsm4k.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm)
> +OP(vsm4r_vv, "vsm4r.vv", rv_codec_v_r, rv_fmt_vd_vs2)
> +OP(vsm4r_vs, "vsm4r.vs", rv_codec_v_r, rv_fmt_vd_vs2)
> +OP(vwsll_vv, "vwsll.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vwsll_vx, "vwsll.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> +OP(vwsll_vi, "vwsll.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm)
> +OP(amocas_w, "amocas.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> +OP(amocas_d, "amocas.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> +OP(amocas_q, "amocas.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> +OP(mop_r_0, "mop.r.0", rv_codec_r, rv_fmt_rd_rs1)
> +OP(mop_r_1, "mop.r.1", rv_codec_r, rv_fmt_rd_rs1)
> +OP(mop_r_2, "mop.r.2", rv_codec_r, rv_fmt_rd_rs1)
> +OP(mop_r_3, "mop.r.3", rv_codec_r, rv_fmt_rd_rs1)
> +OP(mop_r_4, "mop.r.4", rv_codec_r, rv_fmt_rd_rs1)
> +OP(mop_r_5, "mop.r.5", rv_codec_r, rv_fmt_rd_rs1)
> +OP(mop_r_6, "mop.r.6", rv_codec_r, rv_fmt_rd_rs1)
> +OP(mop_r_7, "mop.r.7", rv_codec_r, rv_fmt_rd_rs1)
> +OP(mop_r_8, "mop.r.8", rv_codec_r, rv_fmt_rd_rs1)
> +OP(mop_r_9, "mop.r.9", rv_codec_r, rv_fmt_rd_rs1)
> +OP(mop_r_10, "mop.r.10", rv_codec_r, rv_fmt_rd_rs1)
> +OP(mop_r_11, "mop.r.11", rv_codec_r, rv_fmt_rd_rs1)
> +OP(mop_r_12, "mop.r.12", rv_codec_r, rv_fmt_rd_rs1)
> +OP(mop_r_13, "mop.r.13", rv_codec_r, rv_fmt_rd_rs1)
> +OP(mop_r_14, "mop.r.14", rv_codec_r, rv_fmt_rd_rs1)
> +OP(mop_r_15, "mop.r.15", rv_codec_r, rv_fmt_rd_rs1)
> +OP(mop_r_16, "mop.r.16", rv_codec_r, rv_fmt_rd_rs1)
> +OP(mop_r_17, "mop.r.17", rv_codec_r, rv_fmt_rd_rs1)
> +OP(mop_r_18, "mop.r.18", rv_codec_r, rv_fmt_rd_rs1)
> +OP(mop_r_19, "mop.r.19", rv_codec_r, rv_fmt_rd_rs1)
> +OP(mop_r_20, "mop.r.20", rv_codec_r, rv_fmt_rd_rs1)
> +OP(mop_r_21, "mop.r.21", rv_codec_r, rv_fmt_rd_rs1)
> +OP(mop_r_22, "mop.r.22", rv_codec_r, rv_fmt_rd_rs1)
> +OP(mop_r_23, "mop.r.23", rv_codec_r, rv_fmt_rd_rs1)
> +OP(mop_r_24, "mop.r.24", rv_codec_r, rv_fmt_rd_rs1)
> +OP(mop_r_25, "mop.r.25", rv_codec_r, rv_fmt_rd_rs1)
> +OP(mop_r_26, "mop.r.26", rv_codec_r, rv_fmt_rd_rs1)
> +OP(mop_r_27, "mop.r.27", rv_codec_r, rv_fmt_rd_rs1)
> +OP(mop_r_28, "mop.r.28", rv_codec_r, rv_fmt_rd_rs1)
> +OP(mop_r_29, "mop.r.29", rv_codec_r, rv_fmt_rd_rs1)
> +OP(mop_r_30, "mop.r.30", rv_codec_r, rv_fmt_rd_rs1)
> +OP(mop_r_31, "mop.r.31", rv_codec_r, rv_fmt_rd_rs1)
> +OP(mop_rr_0, "mop.rr.0", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(mop_rr_1, "mop.rr.1", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(mop_rr_2, "mop.rr.2", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(mop_rr_3, "mop.rr.3", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(mop_rr_4, "mop.rr.4", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(mop_rr_5, "mop.rr.5", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(mop_rr_6, "mop.rr.6", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(mop_rr_7, "mop.rr.7", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(c_mop_1, "c.mop.1", rv_codec_ci_none, rv_fmt_none)
> +OP(c_mop_3, "c.mop.3", rv_codec_ci_none, rv_fmt_none)
> +OP(c_mop_5, "c.mop.5", rv_codec_ci_none, rv_fmt_none)
> +OP(c_mop_7, "c.mop.7", rv_codec_ci_none, rv_fmt_none)
> +OP(c_mop_9, "c.mop.9", rv_codec_ci_none, rv_fmt_none)
> +OP(c_mop_11, "c.mop.11", rv_codec_ci_none, rv_fmt_none)
> +OP(c_mop_13, "c.mop.13", rv_codec_ci_none, rv_fmt_none)
> +OP(c_mop_15, "c.mop.15", rv_codec_ci_none, rv_fmt_none)
> +OP(amoswap_b, "amoswap.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> +OP(amoadd_b, "amoadd.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> +OP(amoxor_b, "amoxor.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> +OP(amoor_b, "amoor.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> +OP(amoand_b, "amoand.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> +OP(amomin_b, "amomin.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> +OP(amomax_b, "amomax.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> +OP(amominu_b, "amominu.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> +OP(amomaxu_b, "amomaxu.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> +OP(amoswap_h, "amoswap.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> +OP(amoadd_h, "amoadd.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> +OP(amoxor_h, "amoxor.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> +OP(amoor_h, "amoor.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> +OP(amoand_h, "amoand.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> +OP(amomin_h, "amomin.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> +OP(amomax_h, "amomax.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> +OP(amominu_h, "amominu.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> +OP(amomaxu_h, "amomaxu.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> +OP(amocas_b, "amocas.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> +OP(amocas_h, "amocas.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> +OP(wrs_sto, "wrs.sto", rv_codec_none, rv_fmt_none)
> +OP(wrs_nto, "wrs.nto", rv_codec_none, rv_fmt_none)
> +OP(lpad, "lpad", rv_codec_lp, rv_fmt_imm)
> +OP(sspush, "sspush", rv_codec_r, rv_fmt_rs2)
> +OP(sspopchk, "sspopchk", rv_codec_r, rv_fmt_rs1)
> +OP(ssrdp, "ssrdp", rv_codec_r, rv_fmt_rd)
> +OP(ssamoswap_w, "ssamoswap.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> +OP(ssamoswap_d, "ssamoswap.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> +OP(c_sspush, "c.sspush", rv_codec_cmop_ss, NULL,
> DECOMP(rv_op_sspush))
> +OP(c_sspopchk, "c.sspopchk", rv_codec_cmop_ss, NULL,
> DECOMP(rv_op_sspopchk))
> +OP(cbo_inval, "cbo.inval", rv_codec_r, rv_fmt_rs1)
> +OP(cbo_clean, "cbo.clean", rv_codec_r, rv_fmt_rs1)
> +OP(cbo_flush, "cbo.flush", rv_codec_r, rv_fmt_rs1)
> +OP(cbo_zero, "cbo.zero", rv_codec_r, rv_fmt_rs1)
> +OP(mnret, "mnret", rv_codec_none, rv_fmt_none)
^ permalink raw reply [flat|nested] 119+ messages in thread
* Re: [PATCH 50/56] disas/riscv: Merge all mop.r.n to one pattern
2026-08-09 22:35 ` [PATCH 50/56] disas/riscv: Merge all mop.r.n to one pattern Richard Henderson
@ 2026-08-12 12:57 ` Alistair
0 siblings, 0 replies; 119+ messages in thread
From: Alistair @ 2026-08-12 12:57 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: qemu-riscv
On Sun, 2026-08-09 at 15:35 -0700, Richard Henderson wrote:
> Avoid performing arithmetic on rv_op_mop_r_0.
> Treat the 'n' as an immediate.
> Create a codec and format to match.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> disas/riscv.h | 2 ++
> disas/riscv.c | 15 ++++++++++++++-
> disas/riscv-op.c.inc | 33 +--------------------------------
> 3 files changed, 17 insertions(+), 33 deletions(-)
>
> diff --git a/disas/riscv.h b/disas/riscv.h
> index 5ac8c41616..b47a7f0150 100644
> --- a/disas/riscv.h
> +++ b/disas/riscv.h
> @@ -160,6 +160,7 @@ typedef enum {
> rv_codec_fli,
> rv_codec_lp,
> rv_codec_cmop_ss,
> + rv_codec_mop_r,
> } rv_codec;
>
> /* structures */
> @@ -284,5 +285,6 @@ typedef struct {
> #define rv_fmt_rd_rs1_immh_imml_addr "O\t0,(1),i,j"
> #define rv_fmt_rd2_imm "O\t0,2,(1),i"
> #define rv_fmt_fli "O\t3,h"
> +#define rv_fmt_mop_r "O.i\t0,1"
>
> #endif /* DISAS_RISCV_H */
> diff --git a/disas/riscv.c b/disas/riscv.c
> index 9dad56b486..450a5c8142 100644
> --- a/disas/riscv.c
> +++ b/disas/riscv.c
> @@ -643,6 +643,13 @@ static uint32_t operand_lpl(rv_inst inst)
> return extract32(inst, 12, 20);
> }
>
> +static uint32_t operand_mop_r_imm(rv_inst inst)
> +{
> + return (extract32(inst, 30, 1) << 4) |
> + (extract32(inst, 26, 2) << 2) |
> + extract32(inst, 20, 2);
> +}
> +
> /* instruction metadata */
>
> static const rv_opcode_data rvi_opcode_data[] = {
> @@ -2546,7 +2553,7 @@ static const rv_opcode_data
> *decode_inst_opcode(rv_decode *dec, rv_isa isa)
> 2, 2,
>
> extract32(inst, 26, 2)),
> 4, 1, extract32(inst,
> 30, 1));
> - op = rv_op_mop_r_0 + imm_mop5;
> + op = rv_op_mop_r;
> /* if zicfiss enabled and mop5 is shadow
> stack */
> if (dec->cfg->ext_zicfiss &&
> ((imm_mop5 & 0b11100) == 0b11100)) {
> @@ -3049,6 +3056,11 @@ static void decode_inst_operands(rv_decode
> *dec, rv_isa isa,
> dec->rs1 = dec->rs2 = operand_crs1(inst);
> dec->imm = 0;
> break;
> + case rv_codec_mop_r:
> + dec->rd = operand_rd(inst);
> + dec->rs1 = operand_rs1(inst);
> + dec->imm = operand_mop_r_imm(inst);
> + break;
> default:
> g_assert_not_reached();
> }
> @@ -3134,6 +3146,7 @@ static GString *format_inst(size_t tab,
> rv_decode *dec,
> g_string_append(buf, op->name);
> break;
> case '(':
> + case '.':
> case ',':
> case ')':
> case '-':
> diff --git a/disas/riscv-op.c.inc b/disas/riscv-op.c.inc
> index 3fe934688e..222d249a70 100644
> --- a/disas/riscv-op.c.inc
> +++ b/disas/riscv-op.c.inc
> @@ -873,38 +873,7 @@ OP(vwsll_vi, "vwsll.vi", rv_codec_v_i_u,
> rv_fmt_vd_vs2_uimm_vm)
> OP(amocas_w, "amocas.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> OP(amocas_d, "amocas.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> OP(amocas_q, "amocas.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> -OP(mop_r_0, "mop.r.0", rv_codec_r, rv_fmt_rd_rs1)
> -OP(mop_r_1, "mop.r.1", rv_codec_r, rv_fmt_rd_rs1)
> -OP(mop_r_2, "mop.r.2", rv_codec_r, rv_fmt_rd_rs1)
> -OP(mop_r_3, "mop.r.3", rv_codec_r, rv_fmt_rd_rs1)
> -OP(mop_r_4, "mop.r.4", rv_codec_r, rv_fmt_rd_rs1)
> -OP(mop_r_5, "mop.r.5", rv_codec_r, rv_fmt_rd_rs1)
> -OP(mop_r_6, "mop.r.6", rv_codec_r, rv_fmt_rd_rs1)
> -OP(mop_r_7, "mop.r.7", rv_codec_r, rv_fmt_rd_rs1)
> -OP(mop_r_8, "mop.r.8", rv_codec_r, rv_fmt_rd_rs1)
> -OP(mop_r_9, "mop.r.9", rv_codec_r, rv_fmt_rd_rs1)
> -OP(mop_r_10, "mop.r.10", rv_codec_r, rv_fmt_rd_rs1)
> -OP(mop_r_11, "mop.r.11", rv_codec_r, rv_fmt_rd_rs1)
> -OP(mop_r_12, "mop.r.12", rv_codec_r, rv_fmt_rd_rs1)
> -OP(mop_r_13, "mop.r.13", rv_codec_r, rv_fmt_rd_rs1)
> -OP(mop_r_14, "mop.r.14", rv_codec_r, rv_fmt_rd_rs1)
> -OP(mop_r_15, "mop.r.15", rv_codec_r, rv_fmt_rd_rs1)
> -OP(mop_r_16, "mop.r.16", rv_codec_r, rv_fmt_rd_rs1)
> -OP(mop_r_17, "mop.r.17", rv_codec_r, rv_fmt_rd_rs1)
> -OP(mop_r_18, "mop.r.18", rv_codec_r, rv_fmt_rd_rs1)
> -OP(mop_r_19, "mop.r.19", rv_codec_r, rv_fmt_rd_rs1)
> -OP(mop_r_20, "mop.r.20", rv_codec_r, rv_fmt_rd_rs1)
> -OP(mop_r_21, "mop.r.21", rv_codec_r, rv_fmt_rd_rs1)
> -OP(mop_r_22, "mop.r.22", rv_codec_r, rv_fmt_rd_rs1)
> -OP(mop_r_23, "mop.r.23", rv_codec_r, rv_fmt_rd_rs1)
> -OP(mop_r_24, "mop.r.24", rv_codec_r, rv_fmt_rd_rs1)
> -OP(mop_r_25, "mop.r.25", rv_codec_r, rv_fmt_rd_rs1)
> -OP(mop_r_26, "mop.r.26", rv_codec_r, rv_fmt_rd_rs1)
> -OP(mop_r_27, "mop.r.27", rv_codec_r, rv_fmt_rd_rs1)
> -OP(mop_r_28, "mop.r.28", rv_codec_r, rv_fmt_rd_rs1)
> -OP(mop_r_29, "mop.r.29", rv_codec_r, rv_fmt_rd_rs1)
> -OP(mop_r_30, "mop.r.30", rv_codec_r, rv_fmt_rd_rs1)
> -OP(mop_r_31, "mop.r.31", rv_codec_r, rv_fmt_rd_rs1)
> +OP(mop_r, "mop.r", rv_codec_mop_r, rv_fmt_mop_r)
> OP(mop_rr_0, "mop.rr.0", rv_codec_r, rv_fmt_rd_rs1_rs2)
> OP(mop_rr_1, "mop.rr.1", rv_codec_r, rv_fmt_rd_rs1_rs2)
> OP(mop_rr_2, "mop.rr.2", rv_codec_r, rv_fmt_rd_rs1_rs2)
^ permalink raw reply [flat|nested] 119+ messages in thread
* Re: [PATCH 51/56] disas/riscv: Merge all mop.rr.n to one pattern
2026-08-09 22:35 ` [PATCH 51/56] disas/riscv: Merge all mop.rr.n " Richard Henderson
@ 2026-08-12 12:57 ` Alistair
0 siblings, 0 replies; 119+ messages in thread
From: Alistair @ 2026-08-12 12:57 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: qemu-riscv
On Sun, 2026-08-09 at 15:35 -0700, Richard Henderson wrote:
> Avoid performing arithmetic on rv_op_mop_rr_0.
> Treat the 'n' as an immediate.
> Create a codec and format to match.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> disas/riscv.h | 2 ++
> disas/riscv.c | 13 ++++++++++++-
> disas/riscv-op.c.inc | 9 +--------
> 3 files changed, 15 insertions(+), 9 deletions(-)
>
> diff --git a/disas/riscv.h b/disas/riscv.h
> index b47a7f0150..47647f750f 100644
> --- a/disas/riscv.h
> +++ b/disas/riscv.h
> @@ -161,6 +161,7 @@ typedef enum {
> rv_codec_lp,
> rv_codec_cmop_ss,
> rv_codec_mop_r,
> + rv_codec_mop_rr,
> } rv_codec;
>
> /* structures */
> @@ -286,5 +287,6 @@ typedef struct {
> #define rv_fmt_rd2_imm "O\t0,2,(1),i"
> #define rv_fmt_fli "O\t3,h"
> #define rv_fmt_mop_r "O.i\t0,1"
> +#define rv_fmt_mop_rr "O.i\t0,1,2"
>
> #endif /* DISAS_RISCV_H */
> diff --git a/disas/riscv.c b/disas/riscv.c
> index 450a5c8142..6ec62a5830 100644
> --- a/disas/riscv.c
> +++ b/disas/riscv.c
> @@ -650,6 +650,11 @@ static uint32_t operand_mop_r_imm(rv_inst inst)
> extract32(inst, 20, 2);
> }
>
> +static uint32_t operand_mop_rr_imm(rv_inst inst)
> +{
> + return (extract32(inst, 30, 1) << 2) | extract32(inst, 26, 2);
> +}
> +
> /* instruction metadata */
>
> static const rv_opcode_data rvi_opcode_data[] = {
> @@ -2572,7 +2577,7 @@ static const rv_opcode_data
> *decode_inst_opcode(rv_decode *dec, rv_isa isa)
> == 0b1000001) {
> imm_mop3 = deposit32(extract32(inst, 26, 2),
> 2, 1, extract32(inst,
> 30, 1));
> - op = rv_op_mop_rr_0 + imm_mop3;
> + op = rv_op_mop_rr;
> /* if zicfiss enabled and mop3 is shadow
> stack */
> if (dec->cfg->ext_zicfiss &&
> ((imm_mop3 & 0b111) == 0b111)) {
> @@ -3061,6 +3066,12 @@ static void decode_inst_operands(rv_decode
> *dec, rv_isa isa,
> dec->rs1 = operand_rs1(inst);
> dec->imm = operand_mop_r_imm(inst);
> break;
> + case rv_codec_mop_rr:
> + dec->rd = operand_rd(inst);
> + dec->rs1 = operand_rs1(inst);
> + dec->rs2 = operand_rs2(inst);
> + dec->imm = operand_mop_rr_imm(inst);
> + break;
> default:
> g_assert_not_reached();
> }
> diff --git a/disas/riscv-op.c.inc b/disas/riscv-op.c.inc
> index 222d249a70..2100e54475 100644
> --- a/disas/riscv-op.c.inc
> +++ b/disas/riscv-op.c.inc
> @@ -874,14 +874,7 @@ OP(amocas_w, "amocas.w", rv_codec_r_a,
> rv_fmt_aqrl_rd_rs2_rs1)
> OP(amocas_d, "amocas.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> OP(amocas_q, "amocas.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> OP(mop_r, "mop.r", rv_codec_mop_r, rv_fmt_mop_r)
> -OP(mop_rr_0, "mop.rr.0", rv_codec_r, rv_fmt_rd_rs1_rs2)
> -OP(mop_rr_1, "mop.rr.1", rv_codec_r, rv_fmt_rd_rs1_rs2)
> -OP(mop_rr_2, "mop.rr.2", rv_codec_r, rv_fmt_rd_rs1_rs2)
> -OP(mop_rr_3, "mop.rr.3", rv_codec_r, rv_fmt_rd_rs1_rs2)
> -OP(mop_rr_4, "mop.rr.4", rv_codec_r, rv_fmt_rd_rs1_rs2)
> -OP(mop_rr_5, "mop.rr.5", rv_codec_r, rv_fmt_rd_rs1_rs2)
> -OP(mop_rr_6, "mop.rr.6", rv_codec_r, rv_fmt_rd_rs1_rs2)
> -OP(mop_rr_7, "mop.rr.7", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(mop_rr, "mop.rr", rv_codec_mop_rr, rv_fmt_mop_rr)
> OP(c_mop_1, "c.mop.1", rv_codec_ci_none, rv_fmt_none)
> OP(c_mop_3, "c.mop.3", rv_codec_ci_none, rv_fmt_none)
> OP(c_mop_5, "c.mop.5", rv_codec_ci_none, rv_fmt_none)
^ permalink raw reply [flat|nested] 119+ messages in thread
* Re: [PATCH 52/56] disas/riscv: Merge all c.mop.n to one pattern
2026-08-09 22:35 ` [PATCH 52/56] disas/riscv: Merge all c.mop.n " Richard Henderson
@ 2026-08-12 12:58 ` Alistair
0 siblings, 0 replies; 119+ messages in thread
From: Alistair @ 2026-08-12 12:58 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: qemu-riscv
On Sun, 2026-08-09 at 15:35 -0700, Richard Henderson wrote:
> Avoid performing arithmetic on rv_op_c_mop_1.
> Treat the 'n' as an immediate.
> Create a codec and format to match.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> disas/riscv.h | 2 ++
> disas/riscv.c | 10 +++++++++-
> disas/riscv-op.c.inc | 9 +--------
> 3 files changed, 12 insertions(+), 9 deletions(-)
>
> diff --git a/disas/riscv.h b/disas/riscv.h
> index 47647f750f..b0269bb709 100644
> --- a/disas/riscv.h
> +++ b/disas/riscv.h
> @@ -159,6 +159,7 @@ typedef enum {
> rv_codec_r2_imm2_imm5,
> rv_codec_fli,
> rv_codec_lp,
> + rv_codec_cmop,
> rv_codec_cmop_ss,
> rv_codec_mop_r,
> rv_codec_mop_rr,
> @@ -286,6 +287,7 @@ typedef struct {
> #define rv_fmt_rd_rs1_immh_imml_addr "O\t0,(1),i,j"
> #define rv_fmt_rd2_imm "O\t0,2,(1),i"
> #define rv_fmt_fli "O\t3,h"
> +#define rv_fmt_cmop "O.i"
> #define rv_fmt_mop_r "O.i\t0,1"
> #define rv_fmt_mop_rr "O.i\t0,1,2"
>
> diff --git a/disas/riscv.c b/disas/riscv.c
> index 6ec62a5830..89c2e63941 100644
> --- a/disas/riscv.c
> +++ b/disas/riscv.c
> @@ -643,6 +643,11 @@ static uint32_t operand_lpl(rv_inst inst)
> return extract32(inst, 12, 20);
> }
>
> +static uint32_t operand_cmop_imm(rv_inst inst)
> +{
> + return extract32(inst, 8, 3) * 2 + 1;
> +}
> +
> static uint32_t operand_mop_r_imm(rv_inst inst)
> {
> return (extract32(inst, 30, 1) << 4) |
> @@ -1027,7 +1032,7 @@ static const rv_opcode_data
> *decode_inst_opcode(rv_decode *dec, rv_isa isa)
> (((inst >> 11) & 0b11) == 0b0)) {
> unsigned int cmop_code = 0;
> cmop_code = ((inst >> 8) & 0b111);
> - op = rv_op_c_mop_1 + cmop_code;
> + op = rv_op_c_mop;
> if (dec->cfg->ext_zicfiss) {
> op = (cmop_code == 0) ? rv_op_c_sspush : op;
> op = (cmop_code == 2) ? rv_op_c_sspopchk :
> op;
> @@ -3056,6 +3061,9 @@ static void decode_inst_operands(rv_decode
> *dec, rv_isa isa,
> case rv_codec_lp:
> dec->imm = operand_lpl(inst);
> break;
> + case rv_codec_cmop:
> + dec->imm = operand_cmop_imm(inst);
> + break;
> case rv_codec_cmop_ss:
> dec->rd = rv_ireg_zero;
> dec->rs1 = dec->rs2 = operand_crs1(inst);
> diff --git a/disas/riscv-op.c.inc b/disas/riscv-op.c.inc
> index 2100e54475..802a521bca 100644
> --- a/disas/riscv-op.c.inc
> +++ b/disas/riscv-op.c.inc
> @@ -875,14 +875,7 @@ OP(amocas_d, "amocas.d", rv_codec_r_a,
> rv_fmt_aqrl_rd_rs2_rs1)
> OP(amocas_q, "amocas.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> OP(mop_r, "mop.r", rv_codec_mop_r, rv_fmt_mop_r)
> OP(mop_rr, "mop.rr", rv_codec_mop_rr, rv_fmt_mop_rr)
> -OP(c_mop_1, "c.mop.1", rv_codec_ci_none, rv_fmt_none)
> -OP(c_mop_3, "c.mop.3", rv_codec_ci_none, rv_fmt_none)
> -OP(c_mop_5, "c.mop.5", rv_codec_ci_none, rv_fmt_none)
> -OP(c_mop_7, "c.mop.7", rv_codec_ci_none, rv_fmt_none)
> -OP(c_mop_9, "c.mop.9", rv_codec_ci_none, rv_fmt_none)
> -OP(c_mop_11, "c.mop.11", rv_codec_ci_none, rv_fmt_none)
> -OP(c_mop_13, "c.mop.13", rv_codec_ci_none, rv_fmt_none)
> -OP(c_mop_15, "c.mop.15", rv_codec_ci_none, rv_fmt_none)
> +OP(c_mop, "c.mop", rv_codec_cmop, rv_fmt_cmop)
> OP(amoswap_b, "amoswap.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> OP(amoadd_b, "amoadd.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> OP(amoxor_b, "amoxor.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
^ permalink raw reply [flat|nested] 119+ messages in thread
* Re: [PATCH 53/56] disas/riscv: Tidy decode of c.mop.n
2026-08-09 22:35 ` [PATCH 53/56] disas/riscv: Tidy decode of c.mop.n Richard Henderson
@ 2026-08-12 12:59 ` Alistair
0 siblings, 0 replies; 119+ messages in thread
From: Alistair @ 2026-08-12 12:59 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: qemu-riscv
On Sun, 2026-08-09 at 15:35 -0700, Richard Henderson wrote:
> Merge nested if's.
> Reuse operand_cmop_imm for zicfiss decode.
> Return pointers directly.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> disas/riscv.c | 19 +++++++++----------
> 1 file changed, 9 insertions(+), 10 deletions(-)
>
> diff --git a/disas/riscv.c b/disas/riscv.c
> index 89c2e63941..9682e6f5a5 100644
> --- a/disas/riscv.c
> +++ b/disas/riscv.c
> @@ -1027,18 +1027,17 @@ static const rv_opcode_data
> *decode_inst_opcode(rv_decode *dec, rv_isa isa)
> break;
> case 2: op = rv_op_c_li; break;
> case 3:
> - if (dec->cfg && dec->cfg->ext_zcmop) {
> - if ((((inst >> 2) & 0b111111) == 0b100000) &&
> - (((inst >> 11) & 0b11) == 0b0)) {
> - unsigned int cmop_code = 0;
> - cmop_code = ((inst >> 8) & 0b111);
> - op = rv_op_c_mop;
> - if (dec->cfg->ext_zicfiss) {
> - op = (cmop_code == 0) ? rv_op_c_sspush : op;
> - op = (cmop_code == 2) ? rv_op_c_sspopchk :
> op;
> + if (dec->cfg
> + && dec->cfg->ext_zcmop
> + && ((inst >> 2) & 0b111111) == 0b100000
> + && ((inst >> 11) & 0b11) == 0) {
> + if (dec->cfg->ext_zicfiss) {
> + switch (operand_cmop_imm(inst)) {
> + case 1: return &rvi_opcode_data[rv_op_c_sspush];
> + case 5: return
> &rvi_opcode_data[rv_op_c_sspopchk];
> }
> - break;
> }
> + return &rvi_opcode_data[rv_op_c_mop];
> }
> if (inst & ((1 << 12) | (0x1f << 2))) {
> switch ((inst >> 7) & 0b11111) {
^ permalink raw reply [flat|nested] 119+ messages in thread
* Re: [PATCH 54/56] disas/riscv: Tidy decode of mop.r.n and mop.rr.n
2026-08-09 22:35 ` [PATCH 54/56] disas/riscv: Tidy decode of mop.r.n and mop.rr.n Richard Henderson
@ 2026-08-12 13:00 ` Alistair
0 siblings, 0 replies; 119+ messages in thread
From: Alistair @ 2026-08-12 13:00 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: qemu-riscv
On Sun, 2026-08-09 at 15:35 -0700, Richard Henderson wrote:
> Merge nested if's.
> Reuse operand_mop_{r,rr}_imm for zicfiss decode.
> Return pointers directly.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> disas/riscv.c | 59 +++++++++++++++++++++----------------------------
> --
> 1 file changed, 24 insertions(+), 35 deletions(-)
>
> diff --git a/disas/riscv.c b/disas/riscv.c
> index 9682e6f5a5..94d1ed1e20 100644
> --- a/disas/riscv.c
> +++ b/disas/riscv.c
> @@ -2555,44 +2555,33 @@ static const rv_opcode_data
> *decode_inst_opcode(rv_decode *dec, rv_isa isa)
> case 3: op = rv_op_csrrc; break;
> case 4:
> if (dec->cfg && dec->cfg->ext_zimop) {
> - int imm_mop5, imm_mop3, reg_num;
> - if ((extract32(inst, 22, 10) & 0b1011001111)
> - == 0b1000000111) {
> - imm_mop5 =
> deposit32(deposit32(extract32(inst, 20, 2),
> - 2, 2,
> -
> extract32(inst, 26, 2)),
> - 4, 1, extract32(inst,
> 30, 1));
> - op = rv_op_mop_r;
> - /* if zicfiss enabled and mop5 is shadow
> stack */
> - if (dec->cfg->ext_zicfiss &&
> - ((imm_mop5 & 0b11100) == 0b11100)) {
> - /* rs1=0 means ssrdp */
> - if ((inst & (0b011111 << 15)) == 0)
> {
> - op = rv_op_ssrdp;
> - }
> - /* rd=0 means sspopchk */
> - reg_num = (inst >> 15) & 0b011111;
> - if (((inst & (0b011111 << 7)) == 0)
> &&
> - ((reg_num == 1) || (reg_num ==
> 5))) {
> - op = rv_op_sspopchk;
> + if (((inst >> 22) & 0b1011001111) ==
> 0b1000000111) {
> + if (dec->cfg->ext_zicfiss
> + && operand_mop_r_imm(inst) == 28) {
> + switch (operand_rs1(inst)) {
> + case 0:
> + return
> &rvi_opcode_data[rv_op_ssrdp];
> + case 1:
> + case 5:
> + if (operand_rd(inst) == 0) {
> + return
> &rvi_opcode_data[rv_op_sspopchk];
> }
> + }
> }
> - } else if ((extract32(inst, 25, 7) & 0b1011001)
> - == 0b1000001) {
> - imm_mop3 = deposit32(extract32(inst, 26, 2),
> - 2, 1, extract32(inst,
> 30, 1));
> - op = rv_op_mop_rr;
> - /* if zicfiss enabled and mop3 is shadow
> stack */
> - if (dec->cfg->ext_zicfiss &&
> - ((imm_mop3 & 0b111) == 0b111)) {
> - /* rs1=0 and rd=0 means sspush */
> - reg_num = (inst >> 20) & 0b011111;
> - if (((inst & (0b011111 << 15)) == 0)
> &&
> - ((inst & (0b011111 << 7)) == 0)
> &&
> - ((reg_num == 1) || (reg_num ==
> 5))) {
> - op = rv_op_sspush;
> - }
> + return &rvi_opcode_data[rv_op_mop_r];
> + }
> + if (((inst >> 25) & 0b1011001) == 0b1000001) {
> + if (dec->cfg->ext_zicfiss
> + && operand_mop_rr_imm(inst) == 7
> + && operand_rd(inst) == 0
> + && operand_rs1(inst) == 0) {
> + switch (operand_rs2(inst)) {
> + case 1:
> + case 5:
> + return
> &rvi_opcode_data[rv_op_sspush];
> + }
> }
> + return &rvi_opcode_data[rv_op_mop_rr];
> }
> }
> break;
^ permalink raw reply [flat|nested] 119+ messages in thread
* Re: [PATCH 55/56] disas/riscv: Split rvi_opcode_data
2026-08-09 22:35 ` [PATCH 55/56] disas/riscv: Split rvi_opcode_data Richard Henderson
@ 2026-08-12 13:02 ` Alistair
0 siblings, 0 replies; 119+ messages in thread
From: Alistair @ 2026-08-12 13:02 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: qemu-riscv
On Sun, 2026-08-09 at 15:35 -0700, Richard Henderson wrote:
> Generate separate objects for OP() instead of collecting in a table.
> Return pointers to objects directly.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> disas/riscv.c | 1981 +++++++++++++++++++++-------------------
> --
> disas/riscv-op.c.inc | 94 +-
> 2 files changed, 1048 insertions(+), 1027 deletions(-)
>
> diff --git a/disas/riscv.c b/disas/riscv.c
> index 94d1ed1e20..586857502a 100644
> --- a/disas/riscv.c
> +++ b/disas/riscv.c
> @@ -28,12 +28,6 @@
> #include "disas/riscv-xventana.h"
> #include "disas/riscv-xlrbr.h"
>
> -typedef enum {
> -#define OP(N, ...) rv_op_##N,
> -#include "riscv-op.c.inc"
> -#undef OP
> -} rv_op;
> -
> /* register names */
>
> static const char rv_ireg_name_sym[32][5] = {
> @@ -113,140 +107,143 @@ static const rvc_constraint rvcc_true[] = {
> rvc_end };
>
> /* pseudo-instruction metadata */
>
> -static const rv_opcode_data rvi_opcode_data[];
> +/* Forward declare the all the opcodes so that we may link them. */
> +#define OP(N, ...) static const rv_opcode_data op_##N;
> +#include "riscv-op.c.inc"
> +#undef OP
>
> static const rv_comp_data rvcp_jal[] = {
> - { &rvi_opcode_data[rv_op_j], rvcc_j },
> - { &rvi_opcode_data[rv_op_jal_ra], rvcc_jal_ra },
> + { &op_j, rvcc_j },
> + { &op_jal_ra, rvcc_jal_ra },
> { },
> };
>
> static const rv_comp_data rvcp_jalr[] = {
> - { &rvi_opcode_data[rv_op_jr], rvcc_jr },
> - { &rvi_opcode_data[rv_op_jalr_ra], rvcc_jalr_ra },
> + { &op_jr, rvcc_jr },
> + { &op_jalr_ra, rvcc_jalr_ra },
> { },
> };
>
> static const rv_comp_data rvcp_jr[] = {
> - { &rvi_opcode_data[rv_op_ret], rvcc_ret },
> + { &op_ret, rvcc_ret },
> { },
> };
>
> static const rv_comp_data rvcp_beq[] = {
> - { &rvi_opcode_data[rv_op_beqz], rvcc_beqz },
> + { &op_beqz, rvcc_beqz },
> { },
> };
>
> static const rv_comp_data rvcp_bne[] = {
> - { &rvi_opcode_data[rv_op_bnez], rvcc_bnez },
> + { &op_bnez, rvcc_bnez },
> { },
> };
>
> static const rv_comp_data rvcp_blt[] = {
> - { &rvi_opcode_data[rv_op_bltz], rvcc_bltz },
> - { &rvi_opcode_data[rv_op_bgtz], rvcc_bgtz },
> + { &op_bltz, rvcc_bltz },
> + { &op_bgtz, rvcc_bgtz },
> { },
> };
>
> static const rv_comp_data rvcp_bge[] = {
> - { &rvi_opcode_data[rv_op_blez], rvcc_blez },
> - { &rvi_opcode_data[rv_op_bgez], rvcc_bgez },
> + { &op_blez, rvcc_blez },
> + { &op_bgez, rvcc_bgez },
> { },
> };
>
> static const rv_comp_data rvcp_addi[] = {
> - { &rvi_opcode_data[rv_op_mv], rvcc_mv },
> + { &op_mv, rvcc_mv },
> { },
> };
>
> static const rv_comp_data rvcp_mv[] = {
> - { &rvi_opcode_data[rv_op_nop], rvcc_nop },
> + { &op_nop, rvcc_nop },
> { },
> };
>
> static const rv_comp_data rvcp_sltiu[] = {
> - { &rvi_opcode_data[rv_op_seqz], rvcc_seqz },
> + { &op_seqz, rvcc_seqz },
> { },
> };
>
> static const rv_comp_data rvcp_xori[] = {
> - { &rvi_opcode_data[rv_op_not], rvcc_not },
> + { &op_not, rvcc_not },
> { },
> };
>
> static const rv_comp_data rvcp_sub[] = {
> - { &rvi_opcode_data[rv_op_neg], rvcc_neg },
> + { &op_neg, rvcc_neg },
> { },
> };
>
> static const rv_comp_data rvcp_slt[] = {
> - { &rvi_opcode_data[rv_op_sltz], rvcc_sltz },
> - { &rvi_opcode_data[rv_op_sgtz], rvcc_sgtz },
> + { &op_sltz, rvcc_sltz },
> + { &op_sgtz, rvcc_sgtz },
> { },
> };
>
> static const rv_comp_data rvcp_sltu[] = {
> - { &rvi_opcode_data[rv_op_snez], rvcc_snez },
> + { &op_snez, rvcc_snez },
> { },
> };
>
> static const rv_comp_data rvcp_addiw[] = {
> - { &rvi_opcode_data[rv_op_sext_w], rvcc_sext_w },
> + { &op_sext_w, rvcc_sext_w },
> { },
> };
>
> static const rv_comp_data rvcp_subw[] = {
> - { &rvi_opcode_data[rv_op_negw], rvcc_negw },
> + { &op_negw, rvcc_negw },
> { },
> };
>
> static const rv_comp_data rvcp_fsgnj_s[] = {
> - { &rvi_opcode_data[rv_op_fmv_s], rvcc_fmv_s },
> + { &op_fmv_s, rvcc_fmv_s },
> { },
> };
>
> static const rv_comp_data rvcp_fsgnjn_s[] = {
> - { &rvi_opcode_data[rv_op_fneg_s], rvcc_fneg_s },
> + { &op_fneg_s, rvcc_fneg_s },
> { },
> };
>
> static const rv_comp_data rvcp_fsgnjx_s[] = {
> - { &rvi_opcode_data[rv_op_fabs_s], rvcc_fabs_s },
> + { &op_fabs_s, rvcc_fabs_s },
> { },
> };
>
> static const rv_comp_data rvcp_fsgnj_d[] = {
> - { &rvi_opcode_data[rv_op_fmv_d], rvcc_fmv_d },
> + { &op_fmv_d, rvcc_fmv_d },
> { },
> };
>
> static const rv_comp_data rvcp_fsgnjn_d[] = {
> - { &rvi_opcode_data[rv_op_fneg_d], rvcc_fneg_d },
> + { &op_fneg_d, rvcc_fneg_d },
> { },
> };
>
> static const rv_comp_data rvcp_fsgnjx_d[] = {
> - { &rvi_opcode_data[rv_op_fabs_d], rvcc_fabs_d },
> + { &op_fabs_d, rvcc_fabs_d },
> { },
> };
>
> static const rv_comp_data rvcp_fsgnj_q[] = {
> - { &rvi_opcode_data[rv_op_fmv_q], rvcc_fmv_q },
> + { &op_fmv_q, rvcc_fmv_q },
> { },
> };
>
> static const rv_comp_data rvcp_fsgnjn_q[] = {
> - { &rvi_opcode_data[rv_op_fneg_q], rvcc_fneg_q },
> + { &op_fneg_q, rvcc_fneg_q },
> { },
> };
>
> static const rv_comp_data rvcp_fsgnjx_q[] = {
> - { &rvi_opcode_data[rv_op_fabs_q], rvcc_fabs_q },
> + { &op_fabs_q, rvcc_fabs_q },
> { },
> };
>
> /* Convert compressed insns into normal insns via pseudo expansion.
> */
> -#define DECOMP(X) (static const rv_comp_data[1]){ {
> &rvi_opcode_data[X], rvcc_true } }
> +#define DECOMP(X) (static const rv_comp_data[1]){ { &X, rvcc_true }
> }
>
> /* operand extractors */
>
> @@ -662,11 +659,9 @@ static uint32_t operand_mop_rr_imm(rv_inst inst)
>
> /* instruction metadata */
>
> -static const rv_opcode_data rvi_opcode_data[] = {
> -#define OP(N, ...) { __VA_ARGS__ },
> +#define OP(N, ...) static const rv_opcode_data op_##N = {
> __VA_ARGS__ };
> #include "riscv-op.c.inc"
> #undef OP
> -};
>
> /* CSR names */
>
> @@ -953,79 +948,65 @@ static const char *csr_name(int csrno)
> static const rv_opcode_data *decode_inst_opcode(rv_decode *dec,
> rv_isa isa)
> {
> rv_inst inst = dec->inst;
> - rv_opcode op = rv_op_illegal;
>
> switch ((inst >> 0) & 0b11) {
> case 0:
> switch ((inst >> 13) & 0b111) {
> case 0:
> if ((inst >> 5) & 0xff) {
> - op = rv_op_c_addi4spn;
> + return &op_c_addi4spn;
> }
> break;
> case 1:
> if (isa == rv128) {
> - op = rv_op_c_lq;
> - } else {
> - op = rv_op_c_fld;
> + return &op_c_lq;
> }
> - break;
> - case 2: op = rv_op_c_lw; break;
> + return &op_c_fld;
> + case 2: return &op_c_lw;
> case 3:
> if (isa == rv32) {
> - op = rv_op_c_flw;
> - } else {
> - op = rv_op_c_ld;
> + return &op_c_flw;
> }
> - break;
> + return &op_c_ld;
> case 4:
> switch ((inst >> 10) & 0b111) {
> - case 0: op = rv_op_c_lbu; break;
> + case 0: return &op_c_lbu;
> case 1:
> if (((inst >> 6) & 1) == 0) {
> - op = rv_op_c_lhu;
> - } else {
> - op = rv_op_c_lh;
> + return &op_c_lhu;
> }
> - break;
> - case 2: op = rv_op_c_sb; break;
> + return &op_c_lh;
> + case 2: return &op_c_sb;
> case 3:
> if (((inst >> 6) & 1) == 0) {
> - op = rv_op_c_sh;
> + return &op_c_sh;
> }
> break;
> }
> break;
> case 5:
> if (isa == rv128) {
> - op = rv_op_c_sq;
> - } else {
> - op = rv_op_c_fsd;
> + return &op_c_sq;
> }
> - break;
> - case 6: op = rv_op_c_sw; break;
> + return &op_c_fsd;
> + case 6: return &op_c_sw;
> case 7:
> if (isa == rv32) {
> - op = rv_op_c_fsw;
> - } else {
> - op = rv_op_c_sd;
> + return &op_c_fsw;
> }
> - break;
> + return &op_c_sd;
> }
> break;
> case 1:
> switch ((inst >> 13) & 0b111) {
> case 0:
> - op = rv_op_c_addi; /* or unspecified HINT */
> - break;
> + return &op_c_addi; /* or unspecified HINT */
> case 1:
> if (isa == rv32) {
> - op = rv_op_c_jal;
> - } else {
> - op = rv_op_c_addiw;
> + return &op_c_jal;
> }
> - break;
> - case 2: op = rv_op_c_li; break;
> + return &op_c_addiw;
> + case 2: return &op_c_li;
> case 3:
> if (dec->cfg
> && dec->cfg->ext_zcmop
> @@ -1033,16 +1014,16 @@ static const rv_opcode_data
> *decode_inst_opcode(rv_decode *dec, rv_isa isa)
> && ((inst >> 11) & 0b11) == 0) {
> if (dec->cfg->ext_zicfiss) {
> switch (operand_cmop_imm(inst)) {
> - case 1: return &rvi_opcode_data[rv_op_c_sspush];
> - case 5: return
> &rvi_opcode_data[rv_op_c_sspopchk];
> + case 1: return &op_c_sspush;
> + case 5: return &op_c_sspopchk;
> }
> }
> - return &rvi_opcode_data[rv_op_c_mop];
> + return &op_c_mop;
> }
> if (inst & ((1 << 12) | (0x1f << 2))) {
> switch ((inst >> 7) & 0b11111) {
> - case 2: op = rv_op_c_addi16sp; break;
> - default: op = rv_op_c_lui; break;
> + case 2: return &op_c_addi16sp;
> + default: return &op_c_lui;
> }
> }
> break;
> @@ -1051,261 +1032,252 @@ static const rv_opcode_data
> *decode_inst_opcode(rv_decode *dec, rv_isa isa)
> case 0:
> /* For rv32, shamt[5]=1 is designated for custom
> extensions. */
> if (isa != rv32 || (inst & 0x1000) == 0) {
> - op = rv_op_c_srli; /* or unspecified HINT */
> + return &op_c_srli; /* or unspecified HINT */
> }
> break;
> case 1:
> /* For rv32, shamt[5]=1 is designated for custom
> extensions. */
> if (isa != rv32 || (inst & 0x1000) == 0) {
> - op = rv_op_c_srai; /* or unspecified HINT */
> + return &op_c_srai; /* or unspecified HINT */
> }
> break;
> - case 2: op = rv_op_c_andi; break;
> + case 2: return &op_c_andi;
> case 3:
> switch (((inst >> 10) & 0b100) | ((inst >> 5) &
> 0b011)) {
> - case 0: op = rv_op_c_sub; break;
> - case 1: op = rv_op_c_xor; break;
> - case 2: op = rv_op_c_or; break;
> - case 3: op = rv_op_c_and; break;
> + case 0: return &op_c_sub;
> + case 1: return &op_c_xor;
> + case 2: return &op_c_or;
> + case 3: return &op_c_and;
> case 4:
> if (isa != rv32) {
> - op = rv_op_c_subw;
> + return &op_c_subw;
> }
> break;
> case 5:
> if (isa != rv32) {
> - op = rv_op_c_addw;
> + return &op_c_addw;
> }
> break;
> - case 6: op = rv_op_c_mul; break;
> + case 6: return &op_c_mul;
> case 7:
> switch ((inst >> 2) & 0b111) {
> - case 0: op = rv_op_c_zext_b; break;
> - case 1: op = rv_op_c_sext_b; break;
> - case 2: op = rv_op_c_zext_h; break;
> - case 3: op = rv_op_c_sext_h; break;
> - case 4: op = rv_op_c_zext_w; break;
> - case 5: op = rv_op_c_not; break;
> + case 0: return &op_c_zext_b;
> + case 1: return &op_c_sext_b;
> + case 2: return &op_c_zext_h;
> + case 3: return &op_c_sext_h;
> + case 4: return &op_c_zext_w;
> + case 5: return &op_c_not;
> }
> break;
> }
> break;
> }
> break;
> - case 5: op = rv_op_c_j; break;
> - case 6: op = rv_op_c_beqz; break;
> - case 7: op = rv_op_c_bnez; break;
> + case 5: return &op_c_j;
> + case 6: return &op_c_beqz;
> + case 7: return &op_c_bnez;
> }
> break;
> case 2:
> switch ((inst >> 13) & 0b111) {
> case 0:
> if (isa != rv32 || (inst & 0x1000) == 0) {
> - op = rv_op_c_slli; /* or unspecified HINT */
> + return &op_c_slli; /* or unspecified HINT */
> }
> break;
> case 1:
> if (isa == rv128) {
> - op = rv_op_c_lqsp;
> - } else {
> - op = rv_op_c_fldsp;
> + return &op_c_lqsp;
> }
> - break;
> - case 2: op = rv_op_c_lwsp; break;
> + return &op_c_fldsp;
> + case 2: return &op_c_lwsp;
> case 3:
> if (isa == rv32) {
> - op = rv_op_c_flwsp;
> - } else {
> - op = rv_op_c_ldsp;
> + return &op_c_flwsp;
> }
> - break;
> + return &op_c_ldsp;
> case 4:
> switch ((inst >> 12) & 0b1) {
> case 0:
> switch ((inst >> 2) & 0b11111) {
> - case 0: op = rv_op_c_jr; break;
> - default: op = rv_op_c_mv; break;
> + case 0: return &op_c_jr;
> + default: return &op_c_mv;
> }
> break;
> case 1:
> switch ((inst >> 2) & 0b11111) {
> case 0:
> switch ((inst >> 7) & 0b11111) {
> - case 0: op = rv_op_c_ebreak; break;
> - default: op = rv_op_c_jalr; break;
> + case 0: return &op_c_ebreak;
> + default: return &op_c_jalr;
> }
> break;
> - default: op = rv_op_c_add; break;
> + default: return &op_c_add;
> }
> break;
> }
> break;
> case 5:
> if (isa == rv128) {
> - op = rv_op_c_sqsp;
> - } else {
> - op = rv_op_c_fsdsp;
> - if (dec->cfg && dec->cfg->ext_zcmp && ((inst >> 12)
> & 0b01)) {
> + return &op_c_sqsp;
> + }
> + if (dec->cfg) {
> + if (dec->cfg->ext_zcmp && ((inst >> 12) & 0b01)) {
> switch ((inst >> 8) & 0b01111) {
> case 8:
> if (((inst >> 4) & 0b01111) >= 4) {
> - op = rv_op_cm_push;
> + return &op_cm_push;
> }
> break;
> case 10:
> if (((inst >> 4) & 0b01111) >= 4) {
> - op = rv_op_cm_pop;
> + return &op_cm_pop;
> }
> break;
> case 12:
> if (((inst >> 4) & 0b01111) >= 4) {
> - op = rv_op_cm_popretz;
> + return &op_cm_popretz;
> }
> break;
> case 14:
> if (((inst >> 4) & 0b01111) >= 4) {
> - op = rv_op_cm_popret;
> - }
> - break;
> - }
> - } else {
> - switch ((inst >> 10) & 0b011) {
> - case 0:
> - if (dec->cfg && !dec->cfg->ext_zcmt) {
> - break;
> - }
> - if (((inst >> 2) & 0xFF) >= 32) {
> - op = rv_op_cm_jalt;
> - } else {
> - op = rv_op_cm_jt;
> - }
> - break;
> - case 3:
> - if (dec->cfg && !dec->cfg->ext_zcmp) {
> - break;
> - }
> - switch ((inst >> 5) & 0b011) {
> - case 1: op = rv_op_cm_mvsa01; break;
> - case 3: op = rv_op_cm_mva01s; break;
> + return &op_cm_popret;
> }
> break;
> }
> }
> + switch ((inst >> 10) & 0b011) {
> + case 0:
> + if (!dec->cfg->ext_zcmt) {
> + break;
> + }
> + if (((inst >> 2) & 0xFF) >= 32) {
> + return &op_cm_jalt;
> + }
> + return &op_cm_jt;
> + case 3:
> + if (!dec->cfg->ext_zcmp) {
> + break;
> + }
> + switch ((inst >> 5) & 0b011) {
> + case 1: return &op_cm_mvsa01;
> + case 3: return &op_cm_mva01s;
> + }
> + break;
> + }
> }
> - break;
> - case 6: op = rv_op_c_swsp; break;
> + return &op_c_fsdsp;
> + case 6: return &op_c_swsp;
> case 7:
> if (isa == rv32) {
> - op = rv_op_c_fswsp;
> - } else {
> - op = rv_op_c_sdsp;
> + return &op_c_fswsp;
> }
> - break;
> + return &op_c_sdsp;
> }
> break;
> case 3:
> switch ((inst >> 2) & 0b11111) {
> case 0:
> switch ((inst >> 12) & 0b111) {
> - case 0: op = rv_op_lb; break;
> - case 1: op = rv_op_lh; break;
> - case 2: op = rv_op_lw; break;
> - case 3: op = rv_op_ld; break;
> - case 4: op = rv_op_lbu; break;
> - case 5: op = rv_op_lhu; break;
> - case 6: op = rv_op_lwu; break;
> - case 7: op = rv_op_ldu; break;
> + case 0: return &op_lb;
> + case 1: return &op_lh;
> + case 2: return &op_lw;
> + case 3: return &op_ld;
> + case 4: return &op_lbu;
> + case 5: return &op_lhu;
> + case 6: return &op_lwu;
> + case 7: return &op_ldu;
> }
> break;
> case 1:
> switch ((inst >> 12) & 0b111) {
> case 0:
> switch ((inst >> 20) & 0b111111111111) {
> - case 40: op = rv_op_vl1re8_v; break;
> - case 552: op = rv_op_vl2re8_v; break;
> - case 1576: op = rv_op_vl4re8_v; break;
> - case 3624: op = rv_op_vl8re8_v; break;
> + case 40: return &op_vl1re8_v;
> + case 552: return &op_vl2re8_v;
> + case 1576: return &op_vl4re8_v;
> + case 3624: return &op_vl8re8_v;
> }
> switch ((inst >> 26) & 0b111) {
> case 0:
> switch ((inst >> 20) & 0b11111) {
> - case 0: op = rv_op_vle8_v; break;
> - case 11: op = rv_op_vlm_v; break;
> - case 16: op = rv_op_vle8ff_v; break;
> + case 0: return &op_vle8_v;
> + case 11: return &op_vlm_v;
> + case 16: return &op_vle8ff_v;
> }
> break;
> - case 1: op = rv_op_vluxei8_v; break;
> - case 2: op = rv_op_vlse8_v; break;
> - case 3: op = rv_op_vloxei8_v; break;
> + case 1: return &op_vluxei8_v;
> + case 2: return &op_vlse8_v;
> + case 3: return &op_vloxei8_v;
> }
> break;
> - case 1: op = rv_op_flh; break;
> - case 2: op = rv_op_flw; break;
> - case 3: op = rv_op_fld; break;
> - case 4: op = rv_op_flq; break;
> + case 1: return &op_flh;
> + case 2: return &op_flw;
> + case 3: return &op_fld;
> + case 4: return &op_flq;
> case 5:
> switch ((inst >> 20) & 0b111111111111) {
> - case 40: op = rv_op_vl1re16_v; break;
> - case 552: op = rv_op_vl2re16_v; break;
> - case 1576: op = rv_op_vl4re16_v; break;
> - case 3624: op = rv_op_vl8re16_v; break;
> + case 40: return &op_vl1re16_v;
> + case 552: return &op_vl2re16_v;
> + case 1576: return &op_vl4re16_v;
> + case 3624: return &op_vl8re16_v;
> }
> switch ((inst >> 26) & 0b111) {
> case 0:
> switch ((inst >> 20) & 0b11111) {
> - case 0: op = rv_op_vle16_v; break;
> - case 16: op = rv_op_vle16ff_v; break;
> + case 0: return &op_vle16_v;
> + case 16: return &op_vle16ff_v;
> }
> break;
> - case 1: op = rv_op_vluxei16_v; break;
> - case 2: op = rv_op_vlse16_v; break;
> - case 3: op = rv_op_vloxei16_v; break;
> + case 1: return &op_vluxei16_v;
> + case 2: return &op_vlse16_v;
> + case 3: return &op_vloxei16_v;
> }
> break;
> case 6:
> switch ((inst >> 20) & 0b111111111111) {
> - case 40: op = rv_op_vl1re32_v; break;
> - case 552: op = rv_op_vl2re32_v; break;
> - case 1576: op = rv_op_vl4re32_v; break;
> - case 3624: op = rv_op_vl8re32_v; break;
> + case 40: return &op_vl1re32_v;
> + case 552: return &op_vl2re32_v;
> + case 1576: return &op_vl4re32_v;
> + case 3624: return &op_vl8re32_v;
> }
> switch ((inst >> 26) & 0b111) {
> case 0:
> switch ((inst >> 20) & 0b11111) {
> - case 0: op = rv_op_vle32_v; break;
> - case 16: op = rv_op_vle32ff_v; break;
> + case 0: return &op_vle32_v;
> + case 16: return &op_vle32ff_v;
> }
> break;
> - case 1: op = rv_op_vluxei32_v; break;
> - case 2: op = rv_op_vlse32_v; break;
> - case 3: op = rv_op_vloxei32_v; break;
> + case 1: return &op_vluxei32_v;
> + case 2: return &op_vlse32_v;
> + case 3: return &op_vloxei32_v;
> }
> break;
> case 7:
> switch ((inst >> 20) & 0b111111111111) {
> - case 40: op = rv_op_vl1re64_v; break;
> - case 552: op = rv_op_vl2re64_v; break;
> - case 1576: op = rv_op_vl4re64_v; break;
> - case 3624: op = rv_op_vl8re64_v; break;
> + case 40: return &op_vl1re64_v;
> + case 552: return &op_vl2re64_v;
> + case 1576: return &op_vl4re64_v;
> + case 3624: return &op_vl8re64_v;
> }
> switch ((inst >> 26) & 0b111) {
> case 0:
> switch ((inst >> 20) & 0b11111) {
> - case 0: op = rv_op_vle64_v; break;
> - case 16: op = rv_op_vle64ff_v; break;
> + case 0: return &op_vle64_v;
> + case 16: return &op_vle64ff_v;
> }
> break;
> - case 1: op = rv_op_vluxei64_v; break;
> - case 2: op = rv_op_vlse64_v; break;
> - case 3: op = rv_op_vloxei64_v; break;
> + case 1: return &op_vluxei64_v;
> + case 2: return &op_vlse64_v;
> + case 3: return &op_vloxei64_v;
> }
> break;
> }
> break;
> case 3:
> switch ((inst >> 12) & 0b111) {
> - case 0: op = rv_op_fence; break;
> - case 1: op = rv_op_fence_i; break;
> + case 0: return &op_fence;
> + case 1: return &op_fence_i;
> case 2:
> /*
> * 'lq' shares the "(...) 010 ..... 0001111" opcode
> space
> @@ -1320,204 +1292,203 @@ static const rv_opcode_data
> *decode_inst_opcode(rv_decode *dec, rv_isa isa)
> * Anything that doesn't match these will default to
> 'lq'.
> */
> switch ((inst >> 17) & 0b11111) {
> - case 0: op = rv_op_cbo_inval; break;
> - case 1: op = rv_op_cbo_clean; break;
> - case 2: op = rv_op_cbo_flush; break;
> - case 4: op = rv_op_cbo_zero; break;
> - default: op = rv_op_lq; break;
> + case 0: return &op_cbo_inval;
> + case 1: return &op_cbo_clean;
> + case 2: return &op_cbo_flush;
> + case 4: return &op_cbo_zero;
> + default: return &op_lq;
> }
> }
> break;
> case 4:
> switch ((inst >> 12) & 0b111) {
> - case 0: op = rv_op_addi; break;
> + case 0: return &op_addi;
> case 1:
> switch ((inst >> 27) & 0b11111) {
> - case 0b00000: op = rv_op_slli; break;
> + case 0b00000: return &op_slli;
> case 0b00001:
> switch ((inst >> 20) & 0b1111111) {
> - case 0b0001111: op = rv_op_zip; break;
> + case 0b0001111: return &op_zip;
> }
> break;
> case 0b00010:
> switch ((inst >> 20) & 0b1111111) {
> - case 0b0000000: op = rv_op_sha256sum0; break;
> - case 0b0000001: op = rv_op_sha256sum1; break;
> - case 0b0000010: op = rv_op_sha256sig0; break;
> - case 0b0000011: op = rv_op_sha256sig1; break;
> - case 0b0000100: op = rv_op_sha512sum0; break;
> - case 0b0000101: op = rv_op_sha512sum1; break;
> - case 0b0000110: op = rv_op_sha512sig0; break;
> - case 0b0000111: op = rv_op_sha512sig1; break;
> - case 0b0001000: op = rv_op_sm3p0; break;
> - case 0b0001001: op = rv_op_sm3p1; break;
> + case 0b0000000: return &op_sha256sum0;
> + case 0b0000001: return &op_sha256sum1;
> + case 0b0000010: return &op_sha256sig0;
> + case 0b0000011: return &op_sha256sig1;
> + case 0b0000100: return &op_sha512sum0;
> + case 0b0000101: return &op_sha512sum1;
> + case 0b0000110: return &op_sha512sig0;
> + case 0b0000111: return &op_sha512sig1;
> + case 0b0001000: return &op_sm3p0;
> + case 0b0001001: return &op_sm3p1;
> }
> break;
> - case 0b00101: op = rv_op_bseti; break;
> + case 0b00101: return &op_bseti;
> case 0b00110:
> switch ((inst >> 20) & 0b1111111) {
> - case 0b0000000: op = rv_op_aes64im; break;
> + case 0b0000000: return &op_aes64im;
> default:
> if (((inst >> 24) & 0b0111) == 0b001) {
> - op = rv_op_aes64ks1i;
> + return &op_aes64ks1i;
> }
> break;
> }
> break;
> - case 0b01001: op = rv_op_bclri; break;
> - case 0b01101: op = rv_op_binvi; break;
> + case 0b01001: return &op_bclri;
> + case 0b01101: return &op_binvi;
> case 0b01100:
> switch ((inst >> 20) & 0b1111111) {
> - case 0b0000000: op = rv_op_clz; break;
> - case 0b0000001: op = rv_op_ctz; break;
> - case 0b0000010: op = rv_op_cpop; break;
> + case 0b0000000: return &op_clz;
> + case 0b0000001: return &op_ctz;
> + case 0b0000010: return &op_cpop;
> /* 0b0000011 */
> - case 0b0000100: op = rv_op_sext_b; break;
> - case 0b0000101: op = rv_op_sext_h; break;
> + case 0b0000100: return &op_sext_b;
> + case 0b0000101: return &op_sext_h;
> }
> break;
> }
> break;
> - case 2: op = rv_op_slti; break;
> - case 3: op = rv_op_sltiu; break;
> - case 4: op = rv_op_xori; break;
> + case 2: return &op_slti;
> + case 3: return &op_sltiu;
> + case 4: return &op_xori;
> case 5:
> switch ((inst >> 27) & 0b11111) {
> - case 0b00000: op = rv_op_srli; break;
> + case 0b00000: return &op_srli;
> case 0b00001:
> switch ((inst >> 20) & 0b1111111) {
> - case 0b0001111: op = rv_op_unzip; break;
> + case 0b0001111: return &op_unzip;
> }
> break;
> - case 0b00101: op = rv_op_orc_b; break;
> - case 0b01000: op = rv_op_srai; break;
> - case 0b01001: op = rv_op_bexti; break;
> - case 0b01100: op = rv_op_rori; break;
> + case 0b00101: return &op_orc_b;
> + case 0b01000: return &op_srai;
> + case 0b01001: return &op_bexti;
> + case 0b01100: return &op_rori;
> case 0b01101:
> switch ((inst >> 20) & 0b1111111) {
> case 0b0011000:
> if (isa == rv32) {
> - op = rv_op_rev8;
> + return &op_rev8;
> }
> break;
> case 0b0111000:
> if (isa == rv64) {
> - op = rv_op_rev8;
> + return &op_rev8;
> }
> break;
> - case 0b0000111: op = rv_op_brev8; break;
> + case 0b0000111: return &op_brev8;
> }
> break;
> }
> break;
> - case 6: op = rv_op_ori; break;
> - case 7: op = rv_op_andi; break;
> + case 6: return &op_ori;
> + case 7: return &op_andi;
> }
> break;
> case 5:
> - op = rv_op_auipc;
> if (dec->cfg && dec->cfg->ext_zicfilp &&
> (((inst >> 7) & 0b11111) == 0b00000)) {
> - op = rv_op_lpad;
> + return &op_lpad;
> }
> - break;
> + return &op_auipc;
> case 6:
> /* OP-IMM-32 */
> if (isa == rv32) {
> break;
> }
> switch ((inst >> 12) & 0b111) {
> - case 0: op = rv_op_addiw; break;
> + case 0: return &op_addiw;
> case 1:
> switch ((inst >> 26) & 0b111111) {
> - case 0: op = rv_op_slliw; break;
> - case 2: op = rv_op_slli_uw; break;
> + case 0: return &op_slliw;
> + case 2: return &op_slli_uw;
> case 24:
> switch ((inst >> 20) & 0b11111) {
> - case 0b00000: op = rv_op_clzw; break;
> - case 0b00001: op = rv_op_ctzw; break;
> - case 0b00010: op = rv_op_cpopw; break;
> + case 0b00000: return &op_clzw;
> + case 0b00001: return &op_ctzw;
> + case 0b00010: return &op_cpopw;
> }
> break;
> }
> break;
> case 5:
> switch ((inst >> 25) & 0b1111111) {
> - case 0: op = rv_op_srliw; break;
> - case 32: op = rv_op_sraiw; break;
> - case 48: op = rv_op_roriw; break;
> + case 0: return &op_srliw;
> + case 32: return &op_sraiw;
> + case 48: return &op_roriw;
> }
> break;
> }
> break;
> case 8:
> switch ((inst >> 12) & 0b111) {
> - case 0: op = rv_op_sb; break;
> - case 1: op = rv_op_sh; break;
> - case 2: op = rv_op_sw; break;
> - case 3: op = rv_op_sd; break;
> - case 4: op = rv_op_sq; break;
> + case 0: return &op_sb;
> + case 1: return &op_sh;
> + case 2: return &op_sw;
> + case 3: return &op_sd;
> + case 4: return &op_sq;
> }
> break;
> case 9:
> switch ((inst >> 12) & 0b111) {
> case 0:
> switch ((inst >> 20) & 0b111111111111) {
> - case 40: op = rv_op_vs1r_v; break;
> - case 552: op = rv_op_vs2r_v; break;
> - case 1576: op = rv_op_vs4r_v; break;
> - case 3624: op = rv_op_vs8r_v; break;
> + case 40: return &op_vs1r_v;
> + case 552: return &op_vs2r_v;
> + case 1576: return &op_vs4r_v;
> + case 3624: return &op_vs8r_v;
> }
> switch ((inst >> 26) & 0b111) {
> case 0:
> switch ((inst >> 20) & 0b11111) {
> - case 0: op = rv_op_vse8_v; break;
> - case 11: op = rv_op_vsm_v; break;
> + case 0: return &op_vse8_v;
> + case 11: return &op_vsm_v;
> }
> break;
> - case 1: op = rv_op_vsuxei8_v; break;
> - case 2: op = rv_op_vsse8_v; break;
> - case 3: op = rv_op_vsoxei8_v; break;
> + case 1: return &op_vsuxei8_v;
> + case 2: return &op_vsse8_v;
> + case 3: return &op_vsoxei8_v;
> }
> break;
> - case 1: op = rv_op_fsh; break;
> - case 2: op = rv_op_fsw; break;
> - case 3: op = rv_op_fsd; break;
> - case 4: op = rv_op_fsq; break;
> + case 1: return &op_fsh;
> + case 2: return &op_fsw;
> + case 3: return &op_fsd;
> + case 4: return &op_fsq;
> case 5:
> switch ((inst >> 26) & 0b111) {
> case 0:
> switch ((inst >> 20) & 0b11111) {
> - case 0: op = rv_op_vse16_v; break;
> + case 0: return &op_vse16_v;
> }
> break;
> - case 1: op = rv_op_vsuxei16_v; break;
> - case 2: op = rv_op_vsse16_v; break;
> - case 3: op = rv_op_vsoxei16_v; break;
> + case 1: return &op_vsuxei16_v;
> + case 2: return &op_vsse16_v;
> + case 3: return &op_vsoxei16_v;
> }
> break;
> case 6:
> switch ((inst >> 26) & 0b111) {
> case 0:
> switch ((inst >> 20) & 0b11111) {
> - case 0: op = rv_op_vse32_v; break;
> + case 0: return &op_vse32_v;
> }
> break;
> - case 1: op = rv_op_vsuxei32_v; break;
> - case 2: op = rv_op_vsse32_v; break;
> - case 3: op = rv_op_vsoxei32_v; break;
> + case 1: return &op_vsuxei32_v;
> + case 2: return &op_vsse32_v;
> + case 3: return &op_vsoxei32_v;
> }
> break;
> case 7:
> switch ((inst >> 26) & 0b111) {
> case 0:
> switch ((inst >> 20) & 0b11111) {
> - case 0: op = rv_op_vse64_v; break;
> + case 0: return &op_vse64_v;
> }
> break;
> - case 1: op = rv_op_vsuxei64_v; break;
> - case 2: op = rv_op_vsse64_v; break;
> - case 3: op = rv_op_vsoxei64_v; break;
> + case 1: return &op_vsuxei64_v;
> + case 2: return &op_vsse64_v;
> + case 3: return &op_vsoxei64_v;
> }
> break;
> }
> @@ -1525,153 +1496,150 @@ static const rv_opcode_data
> *decode_inst_opcode(rv_decode *dec, rv_isa isa)
> case 11:
> switch (((inst >> 24) & 0b11111000) |
> ((inst >> 12) & 0b00000111)) {
> - case 0: op = rv_op_amoadd_b; break;
> - case 1: op = rv_op_amoadd_h; break;
> - case 2: op = rv_op_amoadd_w; break;
> - case 3: op = rv_op_amoadd_d; break;
> - case 4: op = rv_op_amoadd_q; break;
> - case 8: op = rv_op_amoswap_b; break;
> - case 9: op = rv_op_amoswap_h; break;
> - case 10: op = rv_op_amoswap_w; break;
> - case 11: op = rv_op_amoswap_d; break;
> - case 12: op = rv_op_amoswap_q; break;
> + case 0: return &op_amoadd_b;
> + case 1: return &op_amoadd_h;
> + case 2: return &op_amoadd_w;
> + case 3: return &op_amoadd_d;
> + case 4: return &op_amoadd_q;
> + case 8: return &op_amoswap_b;
> + case 9: return &op_amoswap_h;
> + case 10: return &op_amoswap_w;
> + case 11: return &op_amoswap_d;
> + case 12: return &op_amoswap_q;
> case 18:
> switch ((inst >> 20) & 0b11111) {
> - case 0: op = rv_op_lr_w; break;
> + case 0: return &op_lr_w;
> }
> break;
> case 19:
> switch ((inst >> 20) & 0b11111) {
> - case 0: op = rv_op_lr_d; break;
> + case 0: return &op_lr_d;
> }
> break;
> case 20:
> switch ((inst >> 20) & 0b11111) {
> - case 0: op = rv_op_lr_q; break;
> + case 0: return &op_lr_q;
> }
> break;
> - case 26: op = rv_op_sc_w; break;
> - case 27: op = rv_op_sc_d; break;
> - case 28: op = rv_op_sc_q; break;
> - case 32: op = rv_op_amoxor_b; break;
> - case 33: op = rv_op_amoxor_h; break;
> - case 34: op = rv_op_amoxor_w; break;
> - case 35: op = rv_op_amoxor_d; break;
> - case 36: op = rv_op_amoxor_q; break;
> - case 40: op = rv_op_amocas_b; break;
> - case 41: op = rv_op_amocas_h; break;
> - case 42: op = rv_op_amocas_w; break;
> - case 43: op = rv_op_amocas_d; break;
> - case 44: op = rv_op_amocas_q; break;
> - case 64: op = rv_op_amoor_b; break;
> - case 65: op = rv_op_amoor_h; break;
> - case 66: op = rv_op_amoor_w; break;
> - case 67: op = rv_op_amoor_d; break;
> - case 68: op = rv_op_amoor_q; break;
> - case 74: op = rv_op_ssamoswap_w; break;
> - case 75: op = rv_op_ssamoswap_d; break;
> - case 96: op = rv_op_amoand_b; break;
> - case 97: op = rv_op_amoand_h; break;
> - case 98: op = rv_op_amoand_w; break;
> - case 99: op = rv_op_amoand_d; break;
> - case 100: op = rv_op_amoand_q; break;
> - case 128: op = rv_op_amomin_b; break;
> - case 129: op = rv_op_amomin_h; break;
> - case 130: op = rv_op_amomin_w; break;
> - case 131: op = rv_op_amomin_d; break;
> - case 132: op = rv_op_amomin_q; break;
> - case 160: op = rv_op_amomax_b; break;
> - case 161: op = rv_op_amomax_h; break;
> - case 162: op = rv_op_amomax_w; break;
> - case 163: op = rv_op_amomax_d; break;
> - case 164: op = rv_op_amomax_q; break;
> - case 192: op = rv_op_amominu_b; break;
> - case 193: op = rv_op_amominu_h; break;
> - case 194: op = rv_op_amominu_w; break;
> - case 195: op = rv_op_amominu_d; break;
> - case 196: op = rv_op_amominu_q; break;
> - case 224: op = rv_op_amomaxu_b; break;
> - case 225: op = rv_op_amomaxu_h; break;
> - case 226: op = rv_op_amomaxu_w; break;
> - case 227: op = rv_op_amomaxu_d; break;
> - case 228: op = rv_op_amomaxu_q; break;
> + case 26: return &op_sc_w;
> + case 27: return &op_sc_d;
> + case 28: return &op_sc_q;
> + case 32: return &op_amoxor_b;
> + case 33: return &op_amoxor_h;
> + case 34: return &op_amoxor_w;
> + case 35: return &op_amoxor_d;
> + case 36: return &op_amoxor_q;
> + case 40: return &op_amocas_b;
> + case 41: return &op_amocas_h;
> + case 42: return &op_amocas_w;
> + case 43: return &op_amocas_d;
> + case 44: return &op_amocas_q;
> + case 64: return &op_amoor_b;
> + case 65: return &op_amoor_h;
> + case 66: return &op_amoor_w;
> + case 67: return &op_amoor_d;
> + case 68: return &op_amoor_q;
> + case 74: return &op_ssamoswap_w;
> + case 75: return &op_ssamoswap_d;
> + case 96: return &op_amoand_b;
> + case 97: return &op_amoand_h;
> + case 98: return &op_amoand_w;
> + case 99: return &op_amoand_d;
> + case 100: return &op_amoand_q;
> + case 128: return &op_amomin_b;
> + case 129: return &op_amomin_h;
> + case 130: return &op_amomin_w;
> + case 131: return &op_amomin_d;
> + case 132: return &op_amomin_q;
> + case 160: return &op_amomax_b;
> + case 161: return &op_amomax_h;
> + case 162: return &op_amomax_w;
> + case 163: return &op_amomax_d;
> + case 164: return &op_amomax_q;
> + case 192: return &op_amominu_b;
> + case 193: return &op_amominu_h;
> + case 194: return &op_amominu_w;
> + case 195: return &op_amominu_d;
> + case 196: return &op_amominu_q;
> + case 224: return &op_amomaxu_b;
> + case 225: return &op_amomaxu_h;
> + case 226: return &op_amomaxu_w;
> + case 227: return &op_amomaxu_d;
> + case 228: return &op_amomaxu_q;
> }
> break;
> case 12:
> switch (((inst >> 22) & 0b1111111000) |
> ((inst >> 12) & 0b0000000111)) {
> - case 0: op = rv_op_add; break;
> - case 1: op = rv_op_sll; break;
> - case 2: op = rv_op_slt; break;
> - case 3: op = rv_op_sltu; break;
> - case 4: op = rv_op_xor; break;
> - case 5: op = rv_op_srl; break;
> - case 6: op = rv_op_or; break;
> - case 7: op = rv_op_and; break;
> - case 8: op = rv_op_mul; break;
> - case 9: op = rv_op_mulh; break;
> - case 10: op = rv_op_mulhsu; break;
> - case 11: op = rv_op_mulhu; break;
> - case 12: op = rv_op_div; break;
> - case 13: op = rv_op_divu; break;
> - case 14: op = rv_op_rem; break;
> - case 15: op = rv_op_remu; break;
> + case 0: return &op_add;
> + case 1: return &op_sll;
> + case 2: return &op_slt;
> + case 3: return &op_sltu;
> + case 4: return &op_xor;
> + case 5: return &op_srl;
> + case 6: return &op_or;
> + case 7: return &op_and;
> + case 8: return &op_mul;
> + case 9: return &op_mulh;
> + case 10: return &op_mulhsu;
> + case 11: return &op_mulhu;
> + case 12: return &op_div;
> + case 13: return &op_divu;
> + case 14: return &op_rem;
> + case 15: return &op_remu;
> case 36:
> if (isa == rv32 && !((inst >> 20) & 0b11111)) {
> - op = rv_op_zext_h;
> - } else {
> - op = rv_op_pack;
> + return &op_zext_h;
> }
> - break;
> - case 39: op = rv_op_packh; break;
> -
> - case 41: op = rv_op_clmul; break;
> - case 42: op = rv_op_clmulr; break;
> - case 43: op = rv_op_clmulh; break;
> - case 44: op = rv_op_min; break;
> - case 45: op = rv_op_minu; break;
> - case 46: op = rv_op_max; break;
> - case 47: op = rv_op_maxu; break;
> - case 075: op = rv_op_czero_eqz; break;
> - case 077: op = rv_op_czero_nez; break;
> - case 130: op = rv_op_sh1add; break;
> - case 132: op = rv_op_sh2add; break;
> - case 134: op = rv_op_sh3add; break;
> - case 161: op = rv_op_bset; break;
> - case 162: op = rv_op_xperm4; break;
> - case 164: op = rv_op_xperm8; break;
> - case 200: op = rv_op_aes64es; break;
> - case 216: op = rv_op_aes64esm; break;
> - case 232: op = rv_op_aes64ds; break;
> - case 248: op = rv_op_aes64dsm; break;
> - case 256: op = rv_op_sub; break;
> - case 260: op = rv_op_xnor; break;
> - case 261: op = rv_op_sra; break;
> - case 262: op = rv_op_orn; break;
> - case 263: op = rv_op_andn; break;
> - case 289: op = rv_op_bclr; break;
> - case 293: op = rv_op_bext; break;
> - case 320: op = rv_op_sha512sum0r; break;
> - case 328: op = rv_op_sha512sum1r; break;
> - case 336: op = rv_op_sha512sig0l; break;
> - case 344: op = rv_op_sha512sig1l; break;
> - case 368: op = rv_op_sha512sig0h; break;
> - case 376: op = rv_op_sha512sig1h; break;
> - case 385: op = rv_op_rol; break;
> - case 389: op = rv_op_ror; break;
> - case 417: op = rv_op_binv; break;
> - case 504: op = rv_op_aes64ks2; break;
> + return &op_pack;
> + case 39: return &op_packh;
> + case 41: return &op_clmul;
> + case 42: return &op_clmulr;
> + case 43: return &op_clmulh;
> + case 44: return &op_min;
> + case 45: return &op_minu;
> + case 46: return &op_max;
> + case 47: return &op_maxu;
> + case 075: return &op_czero_eqz;
> + case 077: return &op_czero_nez;
> + case 130: return &op_sh1add;
> + case 132: return &op_sh2add;
> + case 134: return &op_sh3add;
> + case 161: return &op_bset;
> + case 162: return &op_xperm4;
> + case 164: return &op_xperm8;
> + case 200: return &op_aes64es;
> + case 216: return &op_aes64esm;
> + case 232: return &op_aes64ds;
> + case 248: return &op_aes64dsm;
> + case 256: return &op_sub;
> + case 260: return &op_xnor;
> + case 261: return &op_sra;
> + case 262: return &op_orn;
> + case 263: return &op_andn;
> + case 289: return &op_bclr;
> + case 293: return &op_bext;
> + case 320: return &op_sha512sum0r;
> + case 328: return &op_sha512sum1r;
> + case 336: return &op_sha512sig0l;
> + case 344: return &op_sha512sig1l;
> + case 368: return &op_sha512sig0h;
> + case 376: return &op_sha512sig1h;
> + case 385: return &op_rol;
> + case 389: return &op_ror;
> + case 417: return &op_binv;
> + case 504: return &op_aes64ks2;
> }
> switch ((inst >> 25) & 0b0011111) {
> - case 17: op = rv_op_aes32esi; break;
> - case 19: op = rv_op_aes32esmi; break;
> - case 21: op = rv_op_aes32dsi; break;
> - case 23: op = rv_op_aes32dsmi; break;
> - case 24: op = rv_op_sm4ed; break;
> - case 26: op = rv_op_sm4ks; break;
> + case 17: return &op_aes32esi;
> + case 19: return &op_aes32esmi;
> + case 21: return &op_aes32dsi;
> + case 23: return &op_aes32dsmi;
> + case 24: return &op_sm4ed;
> + case 26: return &op_sm4ks;
> }
> break;
> - case 13: op = rv_op_lui; break;
> + case 13: return &op_lui;
> case 14:
> /* OP-32 */
> if (isa == rv32) {
> @@ -1679,317 +1647,317 @@ static const rv_opcode_data
> *decode_inst_opcode(rv_decode *dec, rv_isa isa)
> }
> switch (((inst >> 22) & 0b1111111000) |
> ((inst >> 12) & 0b0000000111)) {
> - case 0: op = rv_op_addw; break;
> - case 1: op = rv_op_sllw; break;
> - case 5: op = rv_op_srlw; break;
> - case 8: op = rv_op_mulw; break;
> - case 12: op = rv_op_divw; break;
> - case 13: op = rv_op_divuw; break;
> - case 14: op = rv_op_remw; break;
> - case 15: op = rv_op_remuw; break;
> - case 32: op = rv_op_add_uw; break;
> + case 0: return &op_addw;
> + case 1: return &op_sllw;
> + case 5: return &op_srlw;
> + case 8: return &op_mulw;
> + case 12: return &op_divw;
> + case 13: return &op_divuw;
> + case 14: return &op_remw;
> + case 15: return &op_remuw;
> + case 32: return &op_add_uw;
> case 36:
> switch ((inst >> 20) & 0b11111) {
> - case 0: op = rv_op_zext_h; break;
> - default: op = rv_op_packw; break;
> + case 0: return &op_zext_h;
> + default: return &op_packw;
> }
> break;
> - case 130: op = rv_op_sh1add_uw; break;
> - case 132: op = rv_op_sh2add_uw; break;
> - case 134: op = rv_op_sh3add_uw; break;
> - case 256: op = rv_op_subw; break;
> - case 261: op = rv_op_sraw; break;
> - case 385: op = rv_op_rolw; break;
> - case 389: op = rv_op_rorw; break;
> + case 130: return &op_sh1add_uw;
> + case 132: return &op_sh2add_uw;
> + case 134: return &op_sh3add_uw;
> + case 256: return &op_subw;
> + case 261: return &op_sraw;
> + case 385: return &op_rolw;
> + case 389: return &op_rorw;
> }
> break;
> case 16:
> switch ((inst >> 25) & 0b11) {
> - case 0: op = rv_op_fmadd_s; break;
> - case 1: op = rv_op_fmadd_d; break;
> - case 3: op = rv_op_fmadd_q; break;
> + case 0: return &op_fmadd_s;
> + case 1: return &op_fmadd_d;
> + case 3: return &op_fmadd_q;
> }
> break;
> case 17:
> switch ((inst >> 25) & 0b11) {
> - case 0: op = rv_op_fmsub_s; break;
> - case 1: op = rv_op_fmsub_d; break;
> - case 3: op = rv_op_fmsub_q; break;
> + case 0: return &op_fmsub_s;
> + case 1: return &op_fmsub_d;
> + case 3: return &op_fmsub_q;
> }
> break;
> case 18:
> switch ((inst >> 25) & 0b11) {
> - case 0: op = rv_op_fnmsub_s; break;
> - case 1: op = rv_op_fnmsub_d; break;
> - case 3: op = rv_op_fnmsub_q; break;
> + case 0: return &op_fnmsub_s;
> + case 1: return &op_fnmsub_d;
> + case 3: return &op_fnmsub_q;
> }
> break;
> case 19:
> switch ((inst >> 25) & 0b11) {
> - case 0: op = rv_op_fnmadd_s; break;
> - case 1: op = rv_op_fnmadd_d; break;
> - case 3: op = rv_op_fnmadd_q; break;
> + case 0: return &op_fnmadd_s;
> + case 1: return &op_fnmadd_d;
> + case 3: return &op_fnmadd_q;
> }
> break;
> case 20:
> switch ((inst >> 25) & 0b1111111) {
> - case 0: op = rv_op_fadd_s; break;
> - case 1: op = rv_op_fadd_d; break;
> - case 3: op = rv_op_fadd_q; break;
> - case 4: op = rv_op_fsub_s; break;
> - case 5: op = rv_op_fsub_d; break;
> - case 7: op = rv_op_fsub_q; break;
> - case 8: op = rv_op_fmul_s; break;
> - case 9: op = rv_op_fmul_d; break;
> - case 11: op = rv_op_fmul_q; break;
> - case 12: op = rv_op_fdiv_s; break;
> - case 13: op = rv_op_fdiv_d; break;
> - case 15: op = rv_op_fdiv_q; break;
> + case 0: return &op_fadd_s;
> + case 1: return &op_fadd_d;
> + case 3: return &op_fadd_q;
> + case 4: return &op_fsub_s;
> + case 5: return &op_fsub_d;
> + case 7: return &op_fsub_q;
> + case 8: return &op_fmul_s;
> + case 9: return &op_fmul_d;
> + case 11: return &op_fmul_q;
> + case 12: return &op_fdiv_s;
> + case 13: return &op_fdiv_d;
> + case 15: return &op_fdiv_q;
> case 16:
> switch ((inst >> 12) & 0b111) {
> - case 0: op = rv_op_fsgnj_s; break;
> - case 1: op = rv_op_fsgnjn_s; break;
> - case 2: op = rv_op_fsgnjx_s; break;
> + case 0: return &op_fsgnj_s;
> + case 1: return &op_fsgnjn_s;
> + case 2: return &op_fsgnjx_s;
> }
> break;
> case 17:
> switch ((inst >> 12) & 0b111) {
> - case 0: op = rv_op_fsgnj_d; break;
> - case 1: op = rv_op_fsgnjn_d; break;
> - case 2: op = rv_op_fsgnjx_d; break;
> + case 0: return &op_fsgnj_d;
> + case 1: return &op_fsgnjn_d;
> + case 2: return &op_fsgnjx_d;
> }
> break;
> case 19:
> switch ((inst >> 12) & 0b111) {
> - case 0: op = rv_op_fsgnj_q; break;
> - case 1: op = rv_op_fsgnjn_q; break;
> - case 2: op = rv_op_fsgnjx_q; break;
> + case 0: return &op_fsgnj_q;
> + case 1: return &op_fsgnjn_q;
> + case 2: return &op_fsgnjx_q;
> }
> break;
> case 20:
> switch ((inst >> 12) & 0b111) {
> - case 0: op = rv_op_fmin_s; break;
> - case 1: op = rv_op_fmax_s; break;
> - case 2: op = rv_op_fminm_s; break;
> - case 3: op = rv_op_fmaxm_s; break;
> + case 0: return &op_fmin_s;
> + case 1: return &op_fmax_s;
> + case 2: return &op_fminm_s;
> + case 3: return &op_fmaxm_s;
> }
> break;
> case 21:
> switch ((inst >> 12) & 0b111) {
> - case 0: op = rv_op_fmin_d; break;
> - case 1: op = rv_op_fmax_d; break;
> - case 2: op = rv_op_fminm_d; break;
> - case 3: op = rv_op_fmaxm_d; break;
> + case 0: return &op_fmin_d;
> + case 1: return &op_fmax_d;
> + case 2: return &op_fminm_d;
> + case 3: return &op_fmaxm_d;
> }
> break;
> case 22:
> switch (((inst >> 12) & 0b111)) {
> - case 2: op = rv_op_fminm_h; break;
> - case 3: op = rv_op_fmaxm_h; break;
> + case 2: return &op_fminm_h;
> + case 3: return &op_fmaxm_h;
> }
> break;
> case 23:
> switch ((inst >> 12) & 0b111) {
> - case 0: op = rv_op_fmin_q; break;
> - case 1: op = rv_op_fmax_q; break;
> - case 2: op = rv_op_fminm_q; break;
> - case 3: op = rv_op_fmaxm_q; break;
> + case 0: return &op_fmin_q;
> + case 1: return &op_fmax_q;
> + case 2: return &op_fminm_q;
> + case 3: return &op_fmaxm_q;
> }
> break;
> case 32:
> switch ((inst >> 20) & 0b11111) {
> - case 1: op = rv_op_fcvt_s_d; break;
> - case 3: op = rv_op_fcvt_s_q; break;
> - case 4: op = rv_op_fround_s; break;
> - case 5: op = rv_op_froundnx_s; break;
> - case 6: op = rv_op_fcvt_s_bf16; break;
> + case 1: return &op_fcvt_s_d;
> + case 3: return &op_fcvt_s_q;
> + case 4: return &op_fround_s;
> + case 5: return &op_froundnx_s;
> + case 6: return &op_fcvt_s_bf16;
> }
> break;
> case 33:
> switch ((inst >> 20) & 0b11111) {
> - case 0: op = rv_op_fcvt_d_s; break;
> - case 3: op = rv_op_fcvt_d_q; break;
> - case 4: op = rv_op_fround_d; break;
> - case 5: op = rv_op_froundnx_d; break;
> + case 0: return &op_fcvt_d_s;
> + case 3: return &op_fcvt_d_q;
> + case 4: return &op_fround_d;
> + case 5: return &op_froundnx_d;
> }
> break;
> case 34:
> switch (((inst >> 20) & 0b11111)) {
> - case 4: op = rv_op_fround_h; break;
> - case 5: op = rv_op_froundnx_h; break;
> - case 8: op = rv_op_fcvt_bf16_s; break;
> + case 4: return &op_fround_h;
> + case 5: return &op_froundnx_h;
> + case 8: return &op_fcvt_bf16_s;
> }
> break;
> case 35:
> switch ((inst >> 20) & 0b11111) {
> - case 0: op = rv_op_fcvt_q_s; break;
> - case 1: op = rv_op_fcvt_q_d; break;
> - case 4: op = rv_op_fround_q; break;
> - case 5: op = rv_op_froundnx_q; break;
> + case 0: return &op_fcvt_q_s;
> + case 1: return &op_fcvt_q_d;
> + case 4: return &op_fround_q;
> + case 5: return &op_froundnx_q;
> }
> break;
> case 44:
> switch ((inst >> 20) & 0b11111) {
> - case 0: op = rv_op_fsqrt_s; break;
> + case 0: return &op_fsqrt_s;
> }
> break;
> case 45:
> switch ((inst >> 20) & 0b11111) {
> - case 0: op = rv_op_fsqrt_d; break;
> + case 0: return &op_fsqrt_d;
> }
> break;
> case 47:
> switch ((inst >> 20) & 0b11111) {
> - case 0: op = rv_op_fsqrt_q; break;
> + case 0: return &op_fsqrt_q;
> }
> break;
> case 80:
> switch ((inst >> 12) & 0b111) {
> - case 0: op = rv_op_fle_s; break;
> - case 1: op = rv_op_flt_s; break;
> - case 2: op = rv_op_feq_s; break;
> - case 4: op = rv_op_fleq_s; break;
> - case 5: op = rv_op_fltq_s; break;
> + case 0: return &op_fle_s;
> + case 1: return &op_flt_s;
> + case 2: return &op_feq_s;
> + case 4: return &op_fleq_s;
> + case 5: return &op_fltq_s;
> }
> break;
> case 81:
> switch ((inst >> 12) & 0b111) {
> - case 0: op = rv_op_fle_d; break;
> - case 1: op = rv_op_flt_d; break;
> - case 2: op = rv_op_feq_d; break;
> - case 4: op = rv_op_fleq_d; break;
> - case 5: op = rv_op_fltq_d; break;
> + case 0: return &op_fle_d;
> + case 1: return &op_flt_d;
> + case 2: return &op_feq_d;
> + case 4: return &op_fleq_d;
> + case 5: return &op_fltq_d;
> }
> break;
> case 82:
> switch (((inst >> 12) & 0b111)) {
> - case 4: op = rv_op_fleq_h; break;
> - case 5: op = rv_op_fltq_h; break;
> + case 4: return &op_fleq_h;
> + case 5: return &op_fltq_h;
> }
> break;
> case 83:
> switch ((inst >> 12) & 0b111) {
> - case 0: op = rv_op_fle_q; break;
> - case 1: op = rv_op_flt_q; break;
> - case 2: op = rv_op_feq_q; break;
> - case 4: op = rv_op_fleq_q; break;
> - case 5: op = rv_op_fltq_q; break;
> + case 0: return &op_fle_q;
> + case 1: return &op_flt_q;
> + case 2: return &op_feq_q;
> + case 4: return &op_fleq_q;
> + case 5: return &op_fltq_q;
> }
> break;
> case 89:
> switch (((inst >> 12) & 0b111)) {
> - case 0: op = rv_op_fmvp_d_x; break;
> + case 0: return &op_fmvp_d_x;
> }
> break;
> case 91:
> switch (((inst >> 12) & 0b111)) {
> - case 0: op = rv_op_fmvp_q_x; break;
> + case 0: return &op_fmvp_q_x;
> }
> break;
> case 96:
> switch ((inst >> 20) & 0b11111) {
> - case 0: op = rv_op_fcvt_w_s; break;
> - case 1: op = rv_op_fcvt_wu_s; break;
> - case 2: op = rv_op_fcvt_l_s; break;
> - case 3: op = rv_op_fcvt_lu_s; break;
> + case 0: return &op_fcvt_w_s;
> + case 1: return &op_fcvt_wu_s;
> + case 2: return &op_fcvt_l_s;
> + case 3: return &op_fcvt_lu_s;
> }
> break;
> case 97:
> switch ((inst >> 20) & 0b11111) {
> - case 0: op = rv_op_fcvt_w_d; break;
> - case 1: op = rv_op_fcvt_wu_d; break;
> - case 2: op = rv_op_fcvt_l_d; break;
> - case 3: op = rv_op_fcvt_lu_d; break;
> - case 8: op = rv_op_fcvtmod_w_d; break;
> + case 0: return &op_fcvt_w_d;
> + case 1: return &op_fcvt_wu_d;
> + case 2: return &op_fcvt_l_d;
> + case 3: return &op_fcvt_lu_d;
> + case 8: return &op_fcvtmod_w_d;
> }
> break;
> case 99:
> switch ((inst >> 20) & 0b11111) {
> - case 0: op = rv_op_fcvt_w_q; break;
> - case 1: op = rv_op_fcvt_wu_q; break;
> - case 2: op = rv_op_fcvt_l_q; break;
> - case 3: op = rv_op_fcvt_lu_q; break;
> + case 0: return &op_fcvt_w_q;
> + case 1: return &op_fcvt_wu_q;
> + case 2: return &op_fcvt_l_q;
> + case 3: return &op_fcvt_lu_q;
> }
> break;
> case 104:
> switch ((inst >> 20) & 0b11111) {
> - case 0: op = rv_op_fcvt_s_w; break;
> - case 1: op = rv_op_fcvt_s_wu; break;
> - case 2: op = rv_op_fcvt_s_l; break;
> - case 3: op = rv_op_fcvt_s_lu; break;
> + case 0: return &op_fcvt_s_w;
> + case 1: return &op_fcvt_s_wu;
> + case 2: return &op_fcvt_s_l;
> + case 3: return &op_fcvt_s_lu;
> }
> break;
> case 105:
> switch ((inst >> 20) & 0b11111) {
> - case 0: op = rv_op_fcvt_d_w; break;
> - case 1: op = rv_op_fcvt_d_wu; break;
> - case 2: op = rv_op_fcvt_d_l; break;
> - case 3: op = rv_op_fcvt_d_lu; break;
> + case 0: return &op_fcvt_d_w;
> + case 1: return &op_fcvt_d_wu;
> + case 2: return &op_fcvt_d_l;
> + case 3: return &op_fcvt_d_lu;
> }
> break;
> case 107:
> switch ((inst >> 20) & 0b11111) {
> - case 0: op = rv_op_fcvt_q_w; break;
> - case 1: op = rv_op_fcvt_q_wu; break;
> - case 2: op = rv_op_fcvt_q_l; break;
> - case 3: op = rv_op_fcvt_q_lu; break;
> + case 0: return &op_fcvt_q_w;
> + case 1: return &op_fcvt_q_wu;
> + case 2: return &op_fcvt_q_l;
> + case 3: return &op_fcvt_q_lu;
> }
> break;
> case 112:
> switch (((inst >> 17) & 0b11111000) |
> ((inst >> 12) & 0b00000111)) {
> - case 0: op = rv_op_fmv_x_s; break;
> - case 1: op = rv_op_fclass_s; break;
> + case 0: return &op_fmv_x_s;
> + case 1: return &op_fclass_s;
> }
> break;
> case 113:
> switch (((inst >> 17) & 0b11111000) |
> ((inst >> 12) & 0b00000111)) {
> - case 0: op = rv_op_fmv_x_d; break;
> - case 1: op = rv_op_fclass_d; break;
> - case 8: op = rv_op_fmvh_x_d; break;
> + case 0: return &op_fmv_x_d;
> + case 1: return &op_fclass_d;
> + case 8: return &op_fmvh_x_d;
> }
> break;
> case 114:
> switch (((inst >> 17) & 0b11111000) |
> ((inst >> 12) & 0b00000111)) {
> - case 0: op = rv_op_fmv_x_h; break;
> + case 0: return &op_fmv_x_h;
> }
> break;
> case 115:
> switch (((inst >> 17) & 0b11111000) |
> ((inst >> 12) & 0b00000111)) {
> - case 0: op = rv_op_fmv_x_q; break;
> - case 1: op = rv_op_fclass_q; break;
> - case 8: op = rv_op_fmvh_x_q; break;
> + case 0: return &op_fmv_x_q;
> + case 1: return &op_fclass_q;
> + case 8: return &op_fmvh_x_q;
> }
> break;
> case 120:
> switch (((inst >> 17) & 0b11111000) |
> ((inst >> 12) & 0b00000111)) {
> - case 0: op = rv_op_fmv_s_x; break;
> - case 8: op = rv_op_fli_s; break;
> + case 0: return &op_fmv_s_x;
> + case 8: return &op_fli_s;
> }
> break;
> case 121:
> switch (((inst >> 17) & 0b11111000) |
> ((inst >> 12) & 0b00000111)) {
> - case 0: op = rv_op_fmv_d_x; break;
> - case 8: op = rv_op_fli_d; break;
> + case 0: return &op_fmv_d_x;
> + case 8: return &op_fli_d;
> }
> break;
> case 122:
> switch (((inst >> 17) & 0b11111000) |
> ((inst >> 12) & 0b00000111)) {
> - case 0: op = rv_op_fmv_h_x; break;
> - case 8: op = rv_op_fli_h; break;
> + case 0: return &op_fmv_h_x;
> + case 8: return &op_fli_h;
> }
> break;
> case 123:
> switch (((inst >> 17) & 0b11111000) |
> ((inst >> 12) & 0b00000111)) {
> - case 0: op = rv_op_fmv_q_x; break;
> - case 8: op = rv_op_fli_q; break;
> + case 0: return &op_fmv_q_x;
> + case 8: return &op_fli_q;
> }
> break;
> }
> @@ -1998,484 +1966,537 @@ static const rv_opcode_data
> *decode_inst_opcode(rv_decode *dec, rv_isa isa)
> switch ((inst >> 12) & 0b111) {
> case 0:
> switch ((inst >> 26) & 0b111111) {
> - case 0: op = rv_op_vadd_vv; break;
> - case 1: op = rv_op_vandn_vv; break;
> - case 2: op = rv_op_vsub_vv; break;
> - case 4: op = rv_op_vminu_vv; break;
> - case 5: op = rv_op_vmin_vv; break;
> - case 6: op = rv_op_vmaxu_vv; break;
> - case 7: op = rv_op_vmax_vv; break;
> - case 9: op = rv_op_vand_vv; break;
> - case 10: op = rv_op_vor_vv; break;
> - case 11: op = rv_op_vxor_vv; break;
> - case 12: op = rv_op_vrgather_vv; break;
> - case 14: op = rv_op_vrgatherei16_vv; break;
> + case 0: return &op_vadd_vv;
> + case 1: return &op_vandn_vv;
> + case 2: return &op_vsub_vv;
> + case 4: return &op_vminu_vv;
> + case 5: return &op_vmin_vv;
> + case 6: return &op_vmaxu_vv;
> + case 7: return &op_vmax_vv;
> + case 9: return &op_vand_vv;
> + case 10: return &op_vor_vv;
> + case 11: return &op_vxor_vv;
> + case 12: return &op_vrgather_vv;
> + case 14: return &op_vrgatherei16_vv;
> case 16:
> if (((inst >> 25) & 1) == 0) {
> - op = rv_op_vadc_vvm;
> + return &op_vadc_vvm;
> }
> break;
> - case 17: op = rv_op_vmadc_vvm; break;
> + case 17: return &op_vmadc_vvm;
> case 18:
> if (((inst >> 25) & 1) == 0) {
> - op = rv_op_vsbc_vvm;
> + return &op_vsbc_vvm;
> }
> break;
> - case 19: op = rv_op_vmsbc_vvm; break;
> - case 20: op = rv_op_vror_vv; break;
> - case 21: op = rv_op_vrol_vv; break;
> + case 19: return &op_vmsbc_vvm;
> + case 20: return &op_vror_vv;
> + case 21: return &op_vrol_vv;
> case 23:
> - if (((inst >> 20) & 0b111111) == 32)
> - op = rv_op_vmv_v_v;
> - else if (((inst >> 25) & 1) == 0)
> - op = rv_op_vmerge_vvm;
> + if (((inst >> 20) & 0b111111) == 32) {
> + return &op_vmv_v_v;
> + } else if (((inst >> 25) & 1) == 0) {
> + return &op_vmerge_vvm;
> + }
> break;
> - case 24: op = rv_op_vmseq_vv; break;
> - case 25: op = rv_op_vmsne_vv; break;
> - case 26: op = rv_op_vmsltu_vv; break;
> - case 27: op = rv_op_vmslt_vv; break;
> - case 28: op = rv_op_vmsleu_vv; break;
> - case 29: op = rv_op_vmsle_vv; break;
> - case 32: op = rv_op_vsaddu_vv; break;
> - case 33: op = rv_op_vsadd_vv; break;
> - case 34: op = rv_op_vssubu_vv; break;
> - case 35: op = rv_op_vssub_vv; break;
> - case 37: op = rv_op_vsll_vv; break;
> - case 39: op = rv_op_vsmul_vv; break;
> - case 40: op = rv_op_vsrl_vv; break;
> - case 41: op = rv_op_vsra_vv; break;
> - case 42: op = rv_op_vssrl_vv; break;
> - case 43: op = rv_op_vssra_vv; break;
> - case 44: op = rv_op_vnsrl_wv; break;
> - case 45: op = rv_op_vnsra_wv; break;
> - case 46: op = rv_op_vnclipu_wv; break;
> - case 47: op = rv_op_vnclip_wv; break;
> - case 48: op = rv_op_vwredsumu_vs; break;
> - case 49: op = rv_op_vwredsum_vs; break;
> - case 53: op = rv_op_vwsll_vv; break;
> + case 24: return &op_vmseq_vv;
> + case 25: return &op_vmsne_vv;
> + case 26: return &op_vmsltu_vv;
> + case 27: return &op_vmslt_vv;
> + case 28: return &op_vmsleu_vv;
> + case 29: return &op_vmsle_vv;
> + case 32: return &op_vsaddu_vv;
> + case 33: return &op_vsadd_vv;
> + case 34: return &op_vssubu_vv;
> + case 35: return &op_vssub_vv;
> + case 37: return &op_vsll_vv;
> + case 39: return &op_vsmul_vv;
> + case 40: return &op_vsrl_vv;
> + case 41: return &op_vsra_vv;
> + case 42: return &op_vssrl_vv;
> + case 43: return &op_vssra_vv;
> + case 44: return &op_vnsrl_wv;
> + case 45: return &op_vnsra_wv;
> + case 46: return &op_vnclipu_wv;
> + case 47: return &op_vnclip_wv;
> + case 48: return &op_vwredsumu_vs;
> + case 49: return &op_vwredsum_vs;
> + case 53: return &op_vwsll_vv;
> }
> break;
> case 1:
> switch ((inst >> 26) & 0b111111) {
> - case 0: op = rv_op_vfadd_vv; break;
> - case 1: op = rv_op_vfredusum_vs; break;
> - case 2: op = rv_op_vfsub_vv; break;
> - case 3: op = rv_op_vfredosum_vs; break;
> - case 4: op = rv_op_vfmin_vv; break;
> - case 5: op = rv_op_vfredmin_vs; break;
> - case 6: op = rv_op_vfmax_vv; break;
> - case 7: op = rv_op_vfredmax_vs; break;
> - case 8: op = rv_op_vfsgnj_vv; break;
> - case 9: op = rv_op_vfsgnjn_vv; break;
> - case 10: op = rv_op_vfsgnjx_vv; break;
> + case 0: return &op_vfadd_vv;
> + case 1: return &op_vfredusum_vs;
> + case 2: return &op_vfsub_vv;
> + case 3: return &op_vfredosum_vs;
> + case 4: return &op_vfmin_vv;
> + case 5: return &op_vfredmin_vs;
> + case 6: return &op_vfmax_vv;
> + case 7: return &op_vfredmax_vs;
> + case 8: return &op_vfsgnj_vv;
> + case 9: return &op_vfsgnjn_vv;
> + case 10: return &op_vfsgnjx_vv;
> case 16:
> switch ((inst >> 15) & 0b11111) {
> - case 0: if ((inst >> 25) & 1) op =
> rv_op_vfmv_f_s; break;
> + case 0:
> + if ((inst >> 25) & 1) {
> + return &op_vfmv_f_s;
> + }
> }
> break;
> case 18:
> switch ((inst >> 15) & 0b11111) {
> - case 0: op = rv_op_vfcvt_xu_f_v; break;
> - case 1: op = rv_op_vfcvt_x_f_v; break;
> - case 2: op = rv_op_vfcvt_f_xu_v; break;
> - case 3: op = rv_op_vfcvt_f_x_v; break;
> - case 6: op = rv_op_vfcvt_rtz_xu_f_v; break;
> - case 7: op = rv_op_vfcvt_rtz_x_f_v; break;
> - case 8: op = rv_op_vfwcvt_xu_f_v; break;
> - case 9: op = rv_op_vfwcvt_x_f_v; break;
> - case 10: op = rv_op_vfwcvt_f_xu_v; break;
> - case 11: op = rv_op_vfwcvt_f_x_v; break;
> - case 12: op = rv_op_vfwcvt_f_f_v; break;
> - case 13: op = rv_op_vfwcvtbf16_f_f_v; break;
> - case 14: op = rv_op_vfwcvt_rtz_xu_f_v; break;
> - case 15: op = rv_op_vfwcvt_rtz_x_f_v; break;
> - case 16: op = rv_op_vfncvt_xu_f_w; break;
> - case 17: op = rv_op_vfncvt_x_f_w; break;
> - case 18: op = rv_op_vfncvt_f_xu_w; break;
> - case 19: op = rv_op_vfncvt_f_x_w; break;
> - case 20: op = rv_op_vfncvt_f_f_w; break;
> - case 21: op = rv_op_vfncvt_rod_f_f_w; break;
> - case 22: op = rv_op_vfncvt_rtz_xu_f_w; break;
> - case 23: op = rv_op_vfncvt_rtz_x_f_w; break;
> - case 29: op = rv_op_vfncvtbf16_f_f_w; break;
> + case 0: return &op_vfcvt_xu_f_v;
> + case 1: return &op_vfcvt_x_f_v;
> + case 2: return &op_vfcvt_f_xu_v;
> + case 3: return &op_vfcvt_f_x_v;
> + case 6: return &op_vfcvt_rtz_xu_f_v;
> + case 7: return &op_vfcvt_rtz_x_f_v;
> + case 8: return &op_vfwcvt_xu_f_v;
> + case 9: return &op_vfwcvt_x_f_v;
> + case 10: return &op_vfwcvt_f_xu_v;
> + case 11: return &op_vfwcvt_f_x_v;
> + case 12: return &op_vfwcvt_f_f_v;
> + case 13: return &op_vfwcvtbf16_f_f_v;
> + case 14: return &op_vfwcvt_rtz_xu_f_v;
> + case 15: return &op_vfwcvt_rtz_x_f_v;
> + case 16: return &op_vfncvt_xu_f_w;
> + case 17: return &op_vfncvt_x_f_w;
> + case 18: return &op_vfncvt_f_xu_w;
> + case 19: return &op_vfncvt_f_x_w;
> + case 20: return &op_vfncvt_f_f_w;
> + case 21: return &op_vfncvt_rod_f_f_w;
> + case 22: return &op_vfncvt_rtz_xu_f_w;
> + case 23: return &op_vfncvt_rtz_x_f_w;
> + case 29: return &op_vfncvtbf16_f_f_w;
> }
> break;
> case 19:
> switch ((inst >> 15) & 0b11111) {
> - case 0: op = rv_op_vfsqrt_v; break;
> - case 4: op = rv_op_vfrsqrt7_v; break;
> - case 5: op = rv_op_vfrec7_v; break;
> - case 16: op = rv_op_vfclass_v; break;
> + case 0: return &op_vfsqrt_v;
> + case 4: return &op_vfrsqrt7_v;
> + case 5: return &op_vfrec7_v;
> + case 16: return &op_vfclass_v;
> }
> break;
> - case 24: op = rv_op_vmfeq_vv; break;
> - case 25: op = rv_op_vmfle_vv; break;
> - case 27: op = rv_op_vmflt_vv; break;
> - case 28: op = rv_op_vmfne_vv; break;
> - case 32: op = rv_op_vfdiv_vv; break;
> - case 36: op = rv_op_vfmul_vv; break;
> - case 40: op = rv_op_vfmadd_vv; break;
> - case 41: op = rv_op_vfnmadd_vv; break;
> - case 42: op = rv_op_vfmsub_vv; break;
> - case 43: op = rv_op_vfnmsub_vv; break;
> - case 44: op = rv_op_vfmacc_vv; break;
> - case 45: op = rv_op_vfnmacc_vv; break;
> - case 46: op = rv_op_vfmsac_vv; break;
> - case 47: op = rv_op_vfnmsac_vv; break;
> - case 48: op = rv_op_vfwadd_vv; break;
> - case 49: op = rv_op_vfwredusum_vs; break;
> - case 50: op = rv_op_vfwsub_vv; break;
> - case 51: op = rv_op_vfwredosum_vs; break;
> - case 52: op = rv_op_vfwadd_wv; break;
> - case 54: op = rv_op_vfwsub_wv; break;
> - case 56: op = rv_op_vfwmul_vv; break;
> - case 59: op = rv_op_vfwmaccbf16_vv; break;
> - case 60: op = rv_op_vfwmacc_vv; break;
> - case 61: op = rv_op_vfwnmacc_vv; break;
> - case 62: op = rv_op_vfwmsac_vv; break;
> - case 63: op = rv_op_vfwnmsac_vv; break;
> + case 24: return &op_vmfeq_vv;
> + case 25: return &op_vmfle_vv;
> + case 27: return &op_vmflt_vv;
> + case 28: return &op_vmfne_vv;
> + case 32: return &op_vfdiv_vv;
> + case 36: return &op_vfmul_vv;
> + case 40: return &op_vfmadd_vv;
> + case 41: return &op_vfnmadd_vv;
> + case 42: return &op_vfmsub_vv;
> + case 43: return &op_vfnmsub_vv;
> + case 44: return &op_vfmacc_vv;
> + case 45: return &op_vfnmacc_vv;
> + case 46: return &op_vfmsac_vv;
> + case 47: return &op_vfnmsac_vv;
> + case 48: return &op_vfwadd_vv;
> + case 49: return &op_vfwredusum_vs;
> + case 50: return &op_vfwsub_vv;
> + case 51: return &op_vfwredosum_vs;
> + case 52: return &op_vfwadd_wv;
> + case 54: return &op_vfwsub_wv;
> + case 56: return &op_vfwmul_vv;
> + case 59: return &op_vfwmaccbf16_vv;
> + case 60: return &op_vfwmacc_vv;
> + case 61: return &op_vfwnmacc_vv;
> + case 62: return &op_vfwmsac_vv;
> + case 63: return &op_vfwnmsac_vv;
> }
> break;
> case 2:
> switch ((inst >> 26) & 0b111111) {
> - case 0: op = rv_op_vredsum_vs; break;
> - case 1: op = rv_op_vredand_vs; break;
> - case 2: op = rv_op_vredor_vs; break;
> - case 3: op = rv_op_vredxor_vs; break;
> - case 4: op = rv_op_vredminu_vs; break;
> - case 5: op = rv_op_vredmin_vs; break;
> - case 6: op = rv_op_vredmaxu_vs; break;
> - case 7: op = rv_op_vredmax_vs; break;
> - case 8: op = rv_op_vaaddu_vv; break;
> - case 9: op = rv_op_vaadd_vv; break;
> - case 10: op = rv_op_vasubu_vv; break;
> - case 11: op = rv_op_vasub_vv; break;
> - case 12: op = rv_op_vclmul_vv; break;
> - case 13: op = rv_op_vclmulh_vv; break;
> + case 0: return &op_vredsum_vs;
> + case 1: return &op_vredand_vs;
> + case 2: return &op_vredor_vs;
> + case 3: return &op_vredxor_vs;
> + case 4: return &op_vredminu_vs;
> + case 5: return &op_vredmin_vs;
> + case 6: return &op_vredmaxu_vs;
> + case 7: return &op_vredmax_vs;
> + case 8: return &op_vaaddu_vv;
> + case 9: return &op_vaadd_vv;
> + case 10: return &op_vasubu_vv;
> + case 11: return &op_vasub_vv;
> + case 12: return &op_vclmul_vv;
> + case 13: return &op_vclmulh_vv;
> case 16:
> switch ((inst >> 15) & 0b11111) {
> - case 0: if ((inst >> 25) & 1) op =
> rv_op_vmv_x_s; break;
> - case 16: op = rv_op_vcpop_m; break;
> - case 17: op = rv_op_vfirst_m; break;
> + case 0:
> + if ((inst >> 25) & 1) {
> + return &op_vmv_x_s;
> + }
> + break;
> + case 16: return &op_vcpop_m;
> + case 17: return &op_vfirst_m;
> }
> break;
> case 18:
> switch ((inst >> 15) & 0b11111) {
> - case 2: op = rv_op_vzext_vf8; break;
> - case 3: op = rv_op_vsext_vf8; break;
> - case 4: op = rv_op_vzext_vf4; break;
> - case 5: op = rv_op_vsext_vf4; break;
> - case 6: op = rv_op_vzext_vf2; break;
> - case 7: op = rv_op_vsext_vf2; break;
> - case 8: op = rv_op_vbrev8_v; break;
> - case 9: op = rv_op_vrev8_v; break;
> - case 10: op = rv_op_vbrev_v; break;
> - case 12: op = rv_op_vclz_v; break;
> - case 13: op = rv_op_vctz_v; break;
> - case 14: op = rv_op_vcpop_v; break;
> + case 2: return &op_vzext_vf8;
> + case 3: return &op_vsext_vf8;
> + case 4: return &op_vzext_vf4;
> + case 5: return &op_vsext_vf4;
> + case 6: return &op_vzext_vf2;
> + case 7: return &op_vsext_vf2;
> + case 8: return &op_vbrev8_v;
> + case 9: return &op_vrev8_v;
> + case 10: return &op_vbrev_v;
> + case 12: return &op_vclz_v;
> + case 13: return &op_vctz_v;
> + case 14: return &op_vcpop_v;
> }
> break;
> case 20:
> switch ((inst >> 15) & 0b11111) {
> - case 1: op = rv_op_vmsbf_m; break;
> - case 2: op = rv_op_vmsof_m; break;
> - case 3: op = rv_op_vmsif_m; break;
> - case 16: op = rv_op_viota_m; break;
> + case 1: return &op_vmsbf_m; break;
> + case 2: return &op_vmsof_m;
> + case 3: return &op_vmsif_m;
> + case 16: return &op_viota_m;
> case 17:
> if (((inst >> 20) & 0b11111) == 0) {
> - op = rv_op_vid_v;
> + return &op_vid_v;
> }
> break;
> }
> break;
> - case 23: if ((inst >> 25) & 1) op =
> rv_op_vcompress_vm; break;
> - case 24: if ((inst >> 25) & 1) op = rv_op_vmandn_mm;
> break;
> - case 25: if ((inst >> 25) & 1) op = rv_op_vmand_mm;
> break;
> - case 26: if ((inst >> 25) & 1) op = rv_op_vmor_mm;
> break;
> - case 27: if ((inst >> 25) & 1) op = rv_op_vmxor_mm;
> break;
> - case 28: if ((inst >> 25) & 1) op = rv_op_vmorn_mm;
> break;
> - case 29: if ((inst >> 25) & 1) op = rv_op_vmnand_mm;
> break;
> - case 30: if ((inst >> 25) & 1) op = rv_op_vmnor_mm;
> break;
> - case 31: if ((inst >> 25) & 1) op = rv_op_vmxnor_mm;
> break;
> - case 32: op = rv_op_vdivu_vv; break;
> - case 33: op = rv_op_vdiv_vv; break;
> - case 34: op = rv_op_vremu_vv; break;
> - case 35: op = rv_op_vrem_vv; break;
> - case 36: op = rv_op_vmulhu_vv; break;
> - case 37: op = rv_op_vmul_vv; break;
> - case 38: op = rv_op_vmulhsu_vv; break;
> - case 39: op = rv_op_vmulh_vv; break;
> - case 41: op = rv_op_vmadd_vv; break;
> - case 43: op = rv_op_vnmsub_vv; break;
> - case 45: op = rv_op_vmacc_vv; break;
> - case 47: op = rv_op_vnmsac_vv; break;
> - case 48: op = rv_op_vwaddu_vv; break;
> - case 49: op = rv_op_vwadd_vv; break;
> - case 50: op = rv_op_vwsubu_vv; break;
> - case 51: op = rv_op_vwsub_vv; break;
> - case 52: op = rv_op_vwaddu_wv; break;
> - case 53: op = rv_op_vwadd_wv; break;
> - case 54: op = rv_op_vwsubu_wv; break;
> - case 55: op = rv_op_vwsub_wv; break;
> - case 56: op = rv_op_vwmulu_vv; break;
> - case 58: op = rv_op_vwmulsu_vv; break;
> - case 59: op = rv_op_vwmul_vv; break;
> - case 60: op = rv_op_vwmaccu_vv; break;
> - case 61: op = rv_op_vwmacc_vv; break;
> - case 63: op = rv_op_vwmaccsu_vv; break;
> + case 23:
> + if ((inst >> 25) & 1) {
> + return &op_vcompress_vm;
> + }
> + break;
> + case 24:
> + if ((inst >> 25) & 1) {
> + return &op_vmandn_mm;
> + }
> + break;
> + case 25:
> + if ((inst >> 25) & 1) {
> + return &op_vmand_mm;
> + }
> + break;
> + case 26:
> + if ((inst >> 25) & 1) {
> + return &op_vmor_mm;
> + }
> + break;
> + case 27:
> + if ((inst >> 25) & 1) {
> + return &op_vmxor_mm;
> + }
> + break;
> + case 28:
> + if ((inst >> 25) & 1) {
> + return &op_vmorn_mm;
> + }
> + break;
> + case 29:
> + if ((inst >> 25) & 1) {
> + return &op_vmnand_mm;
> + }
> + break;
> + case 30:
> + if ((inst >> 25) & 1) {
> + return &op_vmnor_mm;
> + }
> + break;
> + case 31:
> + if ((inst >> 25) & 1) {
> + return &op_vmxnor_mm;
> + }
> + break;
> + case 32: return &op_vdivu_vv;
> + case 33: return &op_vdiv_vv;
> + case 34: return &op_vremu_vv;
> + case 35: return &op_vrem_vv;
> + case 36: return &op_vmulhu_vv;
> + case 37: return &op_vmul_vv;
> + case 38: return &op_vmulhsu_vv;
> + case 39: return &op_vmulh_vv;
> + case 41: return &op_vmadd_vv;
> + case 43: return &op_vnmsub_vv;
> + case 45: return &op_vmacc_vv;
> + case 47: return &op_vnmsac_vv;
> + case 48: return &op_vwaddu_vv;
> + case 49: return &op_vwadd_vv;
> + case 50: return &op_vwsubu_vv;
> + case 51: return &op_vwsub_vv;
> + case 52: return &op_vwaddu_wv;
> + case 53: return &op_vwadd_wv;
> + case 54: return &op_vwsubu_wv;
> + case 55: return &op_vwsub_wv;
> + case 56: return &op_vwmulu_vv;
> + case 58: return &op_vwmulsu_vv;
> + case 59: return &op_vwmul_vv;
> + case 60: return &op_vwmaccu_vv;
> + case 61: return &op_vwmacc_vv;
> + case 63: return &op_vwmaccsu_vv;
> }
> break;
> case 3:
> switch ((inst >> 26) & 0b111111) {
> - case 0: op = rv_op_vadd_vi; break;
> - case 3: op = rv_op_vrsub_vi; break;
> - case 9: op = rv_op_vand_vi; break;
> - case 10: op = rv_op_vor_vi; break;
> - case 11: op = rv_op_vxor_vi; break;
> - case 12: op = rv_op_vrgather_vi; break;
> - case 14: op = rv_op_vslideup_vi; break;
> - case 15: op = rv_op_vslidedown_vi; break;
> + case 0: return &op_vadd_vi;
> + case 3: return &op_vrsub_vi;
> + case 9: return &op_vand_vi;
> + case 10: return &op_vor_vi;
> + case 11: return &op_vxor_vi;
> + case 12: return &op_vrgather_vi;
> + case 14: return &op_vslideup_vi;
> + case 15: return &op_vslidedown_vi;
> case 16:
> if (((inst >> 25) & 1) == 0) {
> - op = rv_op_vadc_vim;
> + return &op_vadc_vim;
> }
> break;
> - case 17: op = rv_op_vmadc_vim; break;
> - case 20: case 21: op = rv_op_vror_vi; break;
> + case 17: return &op_vmadc_vim;
> + case 20: case 21: return &op_vror_vi;
> case 23:
> - if (((inst >> 20) & 0b111111) == 32)
> - op = rv_op_vmv_v_i;
> - else if (((inst >> 25) & 1) == 0)
> - op = rv_op_vmerge_vim;
> + if (((inst >> 20) & 0b111111) == 32) {
> + return &op_vmv_v_i;
> + } else if (((inst >> 25) & 1) == 0) {
> + return &op_vmerge_vim;
> + }
> break;
> - case 24: op = rv_op_vmseq_vi; break;
> - case 25: op = rv_op_vmsne_vi; break;
> - case 28: op = rv_op_vmsleu_vi; break;
> - case 29: op = rv_op_vmsle_vi; break;
> - case 30: op = rv_op_vmsgtu_vi; break;
> - case 31: op = rv_op_vmsgt_vi; break;
> - case 32: op = rv_op_vsaddu_vi; break;
> - case 33: op = rv_op_vsadd_vi; break;
> - case 37: op = rv_op_vsll_vi; break;
> + case 24: return &op_vmseq_vi;
> + case 25: return &op_vmsne_vi;
> + case 28: return &op_vmsleu_vi;
> + case 29: return &op_vmsle_vi;
> + case 30: return &op_vmsgtu_vi;
> + case 31: return &op_vmsgt_vi;
> + case 32: return &op_vsaddu_vi;
> + case 33: return &op_vsadd_vi;
> + case 37: return &op_vsll_vi;
> case 39:
> switch ((inst >> 15) & 0b11111) {
> - case 0: op = rv_op_vmv1r_v; break;
> - case 1: op = rv_op_vmv2r_v; break;
> - case 3: op = rv_op_vmv4r_v; break;
> - case 7: op = rv_op_vmv8r_v; break;
> + case 0: return &op_vmv1r_v;
> + case 1: return &op_vmv2r_v;
> + case 3: return &op_vmv4r_v;
> + case 7: return &op_vmv8r_v;
> }
> break;
> - case 40: op = rv_op_vsrl_vi; break;
> - case 41: op = rv_op_vsra_vi; break;
> - case 42: op = rv_op_vssrl_vi; break;
> - case 43: op = rv_op_vssra_vi; break;
> - case 44: op = rv_op_vnsrl_wi; break;
> - case 45: op = rv_op_vnsra_wi; break;
> - case 46: op = rv_op_vnclipu_wi; break;
> - case 47: op = rv_op_vnclip_wi; break;
> - case 53: op = rv_op_vwsll_vi; break;
> + case 40: return &op_vsrl_vi;
> + case 41: return &op_vsra_vi;
> + case 42: return &op_vssrl_vi;
> + case 43: return &op_vssra_vi;
> + case 44: return &op_vnsrl_wi;
> + case 45: return &op_vnsra_wi;
> + case 46: return &op_vnclipu_wi;
> + case 47: return &op_vnclip_wi;
> + case 53: return &op_vwsll_vi;
> }
> break;
> case 4:
> switch ((inst >> 26) & 0b111111) {
> - case 0: op = rv_op_vadd_vx; break;
> - case 1: op = rv_op_vandn_vx; break;
> - case 2: op = rv_op_vsub_vx; break;
> - case 3: op = rv_op_vrsub_vx; break;
> - case 4: op = rv_op_vminu_vx; break;
> - case 5: op = rv_op_vmin_vx; break;
> - case 6: op = rv_op_vmaxu_vx; break;
> - case 7: op = rv_op_vmax_vx; break;
> - case 9: op = rv_op_vand_vx; break;
> - case 10: op = rv_op_vor_vx; break;
> - case 11: op = rv_op_vxor_vx; break;
> - case 12: op = rv_op_vrgather_vx; break;
> - case 14: op = rv_op_vslideup_vx; break;
> - case 15: op = rv_op_vslidedown_vx; break;
> + case 0: return &op_vadd_vx;
> + case 1: return &op_vandn_vx;
> + case 2: return &op_vsub_vx;
> + case 3: return &op_vrsub_vx;
> + case 4: return &op_vminu_vx;
> + case 5: return &op_vmin_vx;
> + case 6: return &op_vmaxu_vx;
> + case 7: return &op_vmax_vx;
> + case 9: return &op_vand_vx;
> + case 10: return &op_vor_vx;
> + case 11: return &op_vxor_vx;
> + case 12: return &op_vrgather_vx;
> + case 14: return &op_vslideup_vx;
> + case 15: return &op_vslidedown_vx;
> case 16:
> if (((inst >> 25) & 1) == 0) {
> - op = rv_op_vadc_vxm;
> + return &op_vadc_vxm;
> }
> break;
> - case 17: op = rv_op_vmadc_vxm; break;
> + case 17: return &op_vmadc_vxm;
> case 18:
> if (((inst >> 25) & 1) == 0) {
> - op = rv_op_vsbc_vxm;
> + return &op_vsbc_vxm;
> }
> break;
> - case 19: op = rv_op_vmsbc_vxm; break;
> - case 20: op = rv_op_vror_vx; break;
> - case 21: op = rv_op_vrol_vx; break;
> + case 19: return &op_vmsbc_vxm;
> + case 20: return &op_vror_vx;
> + case 21: return &op_vrol_vx;
> case 23:
> - if (((inst >> 20) & 0b111111) == 32)
> - op = rv_op_vmv_v_x;
> - else if (((inst >> 25) & 1) == 0)
> - op = rv_op_vmerge_vxm;
> + if (((inst >> 20) & 0b111111) == 32) {
> + return &op_vmv_v_x;
> + } else if (((inst >> 25) & 1) == 0) {
> + return &op_vmerge_vxm;
> + }
> break;
> - case 24: op = rv_op_vmseq_vx; break;
> - case 25: op = rv_op_vmsne_vx; break;
> - case 26: op = rv_op_vmsltu_vx; break;
> - case 27: op = rv_op_vmslt_vx; break;
> - case 28: op = rv_op_vmsleu_vx; break;
> - case 29: op = rv_op_vmsle_vx; break;
> - case 30: op = rv_op_vmsgtu_vx; break;
> - case 31: op = rv_op_vmsgt_vx; break;
> - case 32: op = rv_op_vsaddu_vx; break;
> - case 33: op = rv_op_vsadd_vx; break;
> - case 34: op = rv_op_vssubu_vx; break;
> - case 35: op = rv_op_vssub_vx; break;
> - case 37: op = rv_op_vsll_vx; break;
> - case 39: op = rv_op_vsmul_vx; break;
> - case 40: op = rv_op_vsrl_vx; break;
> - case 41: op = rv_op_vsra_vx; break;
> - case 42: op = rv_op_vssrl_vx; break;
> - case 43: op = rv_op_vssra_vx; break;
> - case 44: op = rv_op_vnsrl_wx; break;
> - case 45: op = rv_op_vnsra_wx; break;
> - case 46: op = rv_op_vnclipu_wx; break;
> - case 47: op = rv_op_vnclip_wx; break;
> - case 53: op = rv_op_vwsll_vx; break;
> + case 24: return &op_vmseq_vx;
> + case 25: return &op_vmsne_vx;
> + case 26: return &op_vmsltu_vx;
> + case 27: return &op_vmslt_vx;
> + case 28: return &op_vmsleu_vx;
> + case 29: return &op_vmsle_vx;
> + case 30: return &op_vmsgtu_vx;
> + case 31: return &op_vmsgt_vx;
> + case 32: return &op_vsaddu_vx;
> + case 33: return &op_vsadd_vx;
> + case 34: return &op_vssubu_vx;
> + case 35: return &op_vssub_vx;
> + case 37: return &op_vsll_vx;
> + case 39: return &op_vsmul_vx;
> + case 40: return &op_vsrl_vx;
> + case 41: return &op_vsra_vx;
> + case 42: return &op_vssrl_vx;
> + case 43: return &op_vssra_vx;
> + case 44: return &op_vnsrl_wx;
> + case 45: return &op_vnsra_wx;
> + case 46: return &op_vnclipu_wx;
> + case 47: return &op_vnclip_wx;
> + case 53: return &op_vwsll_vx;
> }
> break;
> case 5:
> switch ((inst >> 26) & 0b111111) {
> - case 0: op = rv_op_vfadd_vf; break;
> - case 2: op = rv_op_vfsub_vf; break;
> - case 4: op = rv_op_vfmin_vf; break;
> - case 6: op = rv_op_vfmax_vf; break;
> - case 8: op = rv_op_vfsgnj_vf; break;
> - case 9: op = rv_op_vfsgnjn_vf; break;
> - case 10: op = rv_op_vfsgnjx_vf; break;
> - case 14: op = rv_op_vfslide1up_vf; break;
> - case 15: op = rv_op_vfslide1down_vf; break;
> + case 0: return &op_vfadd_vf;
> + case 2: return &op_vfsub_vf;
> + case 4: return &op_vfmin_vf;
> + case 6: return &op_vfmax_vf;
> + case 8: return &op_vfsgnj_vf;
> + case 9: return &op_vfsgnjn_vf;
> + case 10: return &op_vfsgnjx_vf;
> + case 14: return &op_vfslide1up_vf;
> + case 15: return &op_vfslide1down_vf;
> case 16:
> switch ((inst >> 20) & 0b11111) {
> - case 0: if ((inst >> 25) & 1) op =
> rv_op_vfmv_s_f; break;
> + case 0:
> + if ((inst >> 25) & 1) {
> + return &op_vfmv_s_f;
> + }
> }
> break;
> case 23:
> - if (((inst >> 25) & 1) == 0)
> - op = rv_op_vfmerge_vfm;
> - else if (((inst >> 20) & 0b111111) == 32)
> - op = rv_op_vfmv_v_f;
> + if (((inst >> 25) & 1) == 0) {
> + return &op_vfmerge_vfm;
> + } else if (((inst >> 20) & 0b111111) == 32) {
> + return &op_vfmv_v_f;
> + }
> break;
> - case 24: op = rv_op_vmfeq_vf; break;
> - case 25: op = rv_op_vmfle_vf; break;
> - case 27: op = rv_op_vmflt_vf; break;
> - case 28: op = rv_op_vmfne_vf; break;
> - case 29: op = rv_op_vmfgt_vf; break;
> - case 31: op = rv_op_vmfge_vf; break;
> - case 32: op = rv_op_vfdiv_vf; break;
> - case 33: op = rv_op_vfrdiv_vf; break;
> - case 36: op = rv_op_vfmul_vf; break;
> - case 39: op = rv_op_vfrsub_vf; break;
> - case 40: op = rv_op_vfmadd_vf; break;
> - case 41: op = rv_op_vfnmadd_vf; break;
> - case 42: op = rv_op_vfmsub_vf; break;
> - case 43: op = rv_op_vfnmsub_vf; break;
> - case 44: op = rv_op_vfmacc_vf; break;
> - case 45: op = rv_op_vfnmacc_vf; break;
> - case 46: op = rv_op_vfmsac_vf; break;
> - case 47: op = rv_op_vfnmsac_vf; break;
> - case 48: op = rv_op_vfwadd_vf; break;
> - case 50: op = rv_op_vfwsub_vf; break;
> - case 52: op = rv_op_vfwadd_wf; break;
> - case 54: op = rv_op_vfwsub_wf; break;
> - case 56: op = rv_op_vfwmul_vf; break;
> - case 59: op = rv_op_vfwmaccbf16_vf; break;
> - case 60: op = rv_op_vfwmacc_vf; break;
> - case 61: op = rv_op_vfwnmacc_vf; break;
> - case 62: op = rv_op_vfwmsac_vf; break;
> - case 63: op = rv_op_vfwnmsac_vf; break;
> + case 24: return &op_vmfeq_vf;
> + case 25: return &op_vmfle_vf;
> + case 27: return &op_vmflt_vf;
> + case 28: return &op_vmfne_vf;
> + case 29: return &op_vmfgt_vf;
> + case 31: return &op_vmfge_vf;
> + case 32: return &op_vfdiv_vf;
> + case 33: return &op_vfrdiv_vf;
> + case 36: return &op_vfmul_vf;
> + case 39: return &op_vfrsub_vf;
> + case 40: return &op_vfmadd_vf;
> + case 41: return &op_vfnmadd_vf;
> + case 42: return &op_vfmsub_vf;
> + case 43: return &op_vfnmsub_vf;
> + case 44: return &op_vfmacc_vf;
> + case 45: return &op_vfnmacc_vf;
> + case 46: return &op_vfmsac_vf;
> + case 47: return &op_vfnmsac_vf;
> + case 48: return &op_vfwadd_vf;
> + case 50: return &op_vfwsub_vf;
> + case 52: return &op_vfwadd_wf;
> + case 54: return &op_vfwsub_wf;
> + case 56: return &op_vfwmul_vf;
> + case 59: return &op_vfwmaccbf16_vf;
> + case 60: return &op_vfwmacc_vf;
> + case 61: return &op_vfwnmacc_vf;
> + case 62: return &op_vfwmsac_vf;
> + case 63: return &op_vfwnmsac_vf;
> }
> break;
> case 6:
> switch ((inst >> 26) & 0b111111) {
> - case 8: op = rv_op_vaaddu_vx; break;
> - case 9: op = rv_op_vaadd_vx; break;
> - case 10: op = rv_op_vasubu_vx; break;
> - case 11: op = rv_op_vasub_vx; break;
> - case 12: op = rv_op_vclmul_vx; break;
> - case 13: op = rv_op_vclmulh_vx; break;
> - case 14: op = rv_op_vslide1up_vx; break;
> - case 15: op = rv_op_vslide1down_vx; break;
> + case 8: return &op_vaaddu_vx;
> + case 9: return &op_vaadd_vx;
> + case 10: return &op_vasubu_vx;
> + case 11: return &op_vasub_vx;
> + case 12: return &op_vclmul_vx;
> + case 13: return &op_vclmulh_vx;
> + case 14: return &op_vslide1up_vx;
> + case 15: return &op_vslide1down_vx;
> case 16:
> switch ((inst >> 20) & 0b11111) {
> - case 0: if ((inst >> 25) & 1) op =
> rv_op_vmv_s_x; break;
> + case 0:
> + if ((inst >> 25) & 1) {
> + return &op_vmv_s_x;
> + }
> }
> break;
> - case 32: op = rv_op_vdivu_vx; break;
> - case 33: op = rv_op_vdiv_vx; break;
> - case 34: op = rv_op_vremu_vx; break;
> - case 35: op = rv_op_vrem_vx; break;
> - case 36: op = rv_op_vmulhu_vx; break;
> - case 37: op = rv_op_vmul_vx; break;
> - case 38: op = rv_op_vmulhsu_vx; break;
> - case 39: op = rv_op_vmulh_vx; break;
> - case 41: op = rv_op_vmadd_vx; break;
> - case 43: op = rv_op_vnmsub_vx; break;
> - case 45: op = rv_op_vmacc_vx; break;
> - case 47: op = rv_op_vnmsac_vx; break;
> - case 48: op = rv_op_vwaddu_vx; break;
> - case 49: op = rv_op_vwadd_vx; break;
> - case 50: op = rv_op_vwsubu_vx; break;
> - case 51: op = rv_op_vwsub_vx; break;
> - case 52: op = rv_op_vwaddu_wx; break;
> - case 53: op = rv_op_vwadd_wx; break;
> - case 54: op = rv_op_vwsubu_wx; break;
> - case 55: op = rv_op_vwsub_wx; break;
> - case 56: op = rv_op_vwmulu_vx; break;
> - case 58: op = rv_op_vwmulsu_vx; break;
> - case 59: op = rv_op_vwmul_vx; break;
> - case 60: op = rv_op_vwmaccu_vx; break;
> - case 61: op = rv_op_vwmacc_vx; break;
> - case 62: op = rv_op_vwmaccus_vx; break;
> - case 63: op = rv_op_vwmaccsu_vx; break;
> + case 32: return &op_vdivu_vx;
> + case 33: return &op_vdiv_vx;
> + case 34: return &op_vremu_vx;
> + case 35: return &op_vrem_vx;
> + case 36: return &op_vmulhu_vx;
> + case 37: return &op_vmul_vx;
> + case 38: return &op_vmulhsu_vx;
> + case 39: return &op_vmulh_vx;
> + case 41: return &op_vmadd_vx;
> + case 43: return &op_vnmsub_vx;
> + case 45: return &op_vmacc_vx;
> + case 47: return &op_vnmsac_vx;
> + case 48: return &op_vwaddu_vx;
> + case 49: return &op_vwadd_vx;
> + case 50: return &op_vwsubu_vx;
> + case 51: return &op_vwsub_vx;
> + case 52: return &op_vwaddu_wx;
> + case 53: return &op_vwadd_wx;
> + case 54: return &op_vwsubu_wx;
> + case 55: return &op_vwsub_wx;
> + case 56: return &op_vwmulu_vx;
> + case 58: return &op_vwmulsu_vx;
> + case 59: return &op_vwmul_vx;
> + case 60: return &op_vwmaccu_vx;
> + case 61: return &op_vwmacc_vx;
> + case 62: return &op_vwmaccus_vx;
> + case 63: return &op_vwmaccsu_vx;
> }
> break;
> case 7:
> if (((inst >> 31) & 1) == 0) {
> - op = rv_op_vsetvli;
> + return &op_vsetvli;
> } else if ((inst >> 30) & 1) {
> - op = rv_op_vsetivli;
> + return &op_vsetivli;
> } else if (((inst >> 25) & 0b11111) == 0) {
> - op = rv_op_vsetvl;
> + return &op_vsetvl;
> }
> break;
> }
> break;
> case 22:
> switch ((inst >> 12) & 0b111) {
> - case 0: op = rv_op_addid; break;
> + case 0: return &op_addid;
> case 1:
> switch ((inst >> 26) & 0b111111) {
> - case 0: op = rv_op_sllid; break;
> + case 0: return &op_sllid;
> }
> break;
> case 5:
> switch ((inst >> 26) & 0b111111) {
> - case 0: op = rv_op_srlid; break;
> - case 16: op = rv_op_sraid; break;
> + case 0: return &op_srlid;
> + case 16: return &op_sraid;
> }
> break;
> }
> break;
> case 24:
> switch ((inst >> 12) & 0b111) {
> - case 0: op = rv_op_beq; break;
> - case 1: op = rv_op_bne; break;
> - case 4: op = rv_op_blt; break;
> - case 5: op = rv_op_bge; break;
> - case 6: op = rv_op_bltu; break;
> - case 7: op = rv_op_bgeu; break;
> + case 0: return &op_beq;
> + case 1: return &op_bne;
> + case 4: return &op_blt;
> + case 5: return &op_bge;
> + case 6: return &op_bltu;
> + case 7: return &op_bgeu;
> }
> break;
> case 25:
> switch ((inst >> 12) & 0b111) {
> - case 0: op = rv_op_jalr; break;
> + case 0: return &op_jalr;
> }
> break;
> - case 27: op = rv_op_jal; break;
> + case 27: return &op_jal;
> case 28:
> switch ((inst >> 12) & 0b111) {
> case 0:
> @@ -2483,76 +2504,76 @@ static const rv_opcode_data
> *decode_inst_opcode(rv_decode *dec, rv_isa isa)
> ((inst >> 7) & 0b000000011111)) {
> case 0:
> switch ((inst >> 15) & 0b1111111111) {
> - case 0: op = rv_op_ecall; break;
> - case 32: op = rv_op_ebreak; break;
> - case 64: op = rv_op_uret; break;
> - case 416: op = rv_op_wrs_nto; break;
> - case 928: op = rv_op_wrs_sto; break;
> + case 0: return &op_ecall;
> + case 32: return &op_ebreak;
> + case 64: return &op_uret;
> + case 416: return &op_wrs_nto;
> + case 928: return &op_wrs_sto;
> }
> break;
> case 256:
> switch ((inst >> 20) & 0b11111) {
> case 2:
> switch ((inst >> 15) & 0b11111) {
> - case 0: op = rv_op_sret; break;
> + case 0: return &op_sret;
> }
> break;
> - case 4: op = rv_op_sfence_vm; break;
> + case 4: return &op_sfence_vm;
> case 5:
> switch ((inst >> 15) & 0b11111) {
> - case 0: op = rv_op_wfi; break;
> + case 0: return &op_wfi;
> }
> break;
> }
> break;
> - case 288: op = rv_op_sfence_vma; break;
> + case 288: return &op_sfence_vma;
> case 512:
> switch ((inst >> 15) & 0b1111111111) {
> - case 64: op = rv_op_hret; break;
> + case 64: return &op_hret;
> }
> break;
> case 768:
> switch ((inst >> 15) & 0b1111111111) {
> - case 64: op = rv_op_mret; break;
> + case 64: return &op_mret;
> }
> break;
> case 1792:
> switch ((inst >> 15) & 0b1111111111) {
> - case 64: op = rv_op_mnret; break;
> + case 64: return &op_mnret;
> }
> break;
> case 1952:
> switch ((inst >> 15) & 0b1111111111) {
> - case 576: op = rv_op_dret; break;
> + case 576: return &op_dret;
> }
> break;
> }
> break;
> case 1:
> switch (operand_csr12(inst)) {
> - case 1: op = rv_op_fsflags; break;
> - case 2: op = rv_op_fsrm; break;
> - case 3: op = rv_op_fscsr; break;
> - default: op = rv_op_csrrw; break;
> + case 1: return &op_fsflags;
> + case 2: return &op_fsrm;
> + case 3: return &op_fscsr;
> + default: return &op_csrrw;
> }
> break;
> case 2:
> - op = rv_op_csrrs;
> + return &op_csrrs;
> if (operand_rs1(inst) == 0) {
> switch (operand_csr12(inst)) {
> - case 0x001: op = rv_op_frflags; break;
> - case 0x002: op = rv_op_frrm; break;
> - case 0x003: op = rv_op_frcsr; break;
> - case 0xc00: op = rv_op_rdcycle; break;
> - case 0xc01: op = rv_op_rdtime; break;
> - case 0xc02: op = rv_op_rdinstret; break;
> - case 0xc80: op = rv_op_rdcycleh; break;
> - case 0xc81: op = rv_op_rdtimeh; break;
> - case 0xc82: op = rv_op_rdinstreth; break;
> + case 0x001: return &op_frflags;
> + case 0x002: return &op_frrm;
> + case 0x003: return &op_frcsr;
> + case 0xc00: return &op_rdcycle;
> + case 0xc01: return &op_rdtime;
> + case 0xc02: return &op_rdinstret;
> + case 0xc80: return &op_rdcycleh;
> + case 0xc81: return &op_rdtimeh;
> + case 0xc82: return &op_rdinstreth;
> }
> }
> break;
> - case 3: op = rv_op_csrrc; break;
> + case 3: return &op_csrrc;
> case 4:
> if (dec->cfg && dec->cfg->ext_zimop) {
> if (((inst >> 22) & 0b1011001111) ==
> 0b1000000111) {
> @@ -2560,15 +2581,15 @@ static const rv_opcode_data
> *decode_inst_opcode(rv_decode *dec, rv_isa isa)
> && operand_mop_r_imm(inst) == 28) {
> switch (operand_rs1(inst)) {
> case 0:
> - return
> &rvi_opcode_data[rv_op_ssrdp];
> + return &op_ssrdp;
> case 1:
> case 5:
> if (operand_rd(inst) == 0) {
> - return
> &rvi_opcode_data[rv_op_sspopchk];
> + return &op_sspopchk;
> }
> }
> }
> - return &rvi_opcode_data[rv_op_mop_r];
> + return &op_mop_r;
> }
> if (((inst >> 25) & 0b1011001) == 0b1000001) {
> if (dec->cfg->ext_zicfiss
> @@ -2578,79 +2599,79 @@ static const rv_opcode_data
> *decode_inst_opcode(rv_decode *dec, rv_isa isa)
> switch (operand_rs2(inst)) {
> case 1:
> case 5:
> - return
> &rvi_opcode_data[rv_op_sspush];
> + return &op_sspush;
> }
> }
> - return &rvi_opcode_data[rv_op_mop_rr];
> + return &op_mop_rr;
> }
> }
> break;
> case 5:
> switch (operand_csr12(inst)) {
> - case 1: op = rv_op_fsflagsi; break;
> - case 2: op = rv_op_fsrmi; break;
> - default: op = rv_op_csrrwi; break;
> + case 1: return &op_fsflagsi;
> + case 2: return &op_fsrmi;
> + default: return &op_csrrwi;
> }
> break;
> - case 6: op = rv_op_csrrsi; break;
> - case 7: op = rv_op_csrrci; break;
> + case 6: return &op_csrrsi;
> + case 7: return &op_csrrci;
> }
> break;
> case 29:
> if (((inst >> 25) & 1) == 1 && ((inst >> 12) & 0b111) ==
> 2) {
> switch ((inst >> 26) & 0b111111) {
> - case 32: op = rv_op_vsm3me_vv; break;
> - case 33: op = rv_op_vsm4k_vi; break;
> - case 34: op = rv_op_vaeskf1_vi; break;
> + case 32: return &op_vsm3me_vv;
> + case 33: return &op_vsm4k_vi;
> + case 34: return &op_vaeskf1_vi;
> case 40:
> switch ((inst >> 15) & 0b11111) {
> - case 0: op = rv_op_vaesdm_vv; break;
> - case 1: op = rv_op_vaesdf_vv; break;
> - case 2: op = rv_op_vaesem_vv; break;
> - case 3: op = rv_op_vaesef_vv; break;
> - case 16: op = rv_op_vsm4r_vv; break;
> - case 17: op = rv_op_vgmul_vv; break;
> + case 0: return &op_vaesdm_vv;
> + case 1: return &op_vaesdf_vv;
> + case 2: return &op_vaesem_vv;
> + case 3: return &op_vaesef_vv;
> + case 16: return &op_vsm4r_vv;
> + case 17: return &op_vgmul_vv;
> }
> break;
> case 41:
> switch ((inst >> 15) & 0b11111) {
> - case 0: op = rv_op_vaesdm_vs; break;
> - case 1: op = rv_op_vaesdf_vs; break;
> - case 2: op = rv_op_vaesem_vs; break;
> - case 3: op = rv_op_vaesef_vs; break;
> - case 7: op = rv_op_vaesz_vs; break;
> - case 16: op = rv_op_vsm4r_vs; break;
> + case 0: return &op_vaesdm_vs;
> + case 1: return &op_vaesdf_vs;
> + case 2: return &op_vaesem_vs;
> + case 3: return &op_vaesef_vs;
> + case 7: return &op_vaesz_vs;
> + case 16: return &op_vsm4r_vs;
> }
> break;
> - case 42: op = rv_op_vaeskf2_vi; break;
> - case 43: op = rv_op_vsm3c_vi; break;
> - case 44: op = rv_op_vghsh_vv; break;
> - case 45: op = rv_op_vsha2ms_vv; break;
> - case 46: op = rv_op_vsha2ch_vv; break;
> - case 47: op = rv_op_vsha2cl_vv; break;
> + case 42: return &op_vaeskf2_vi;
> + case 43: return &op_vsm3c_vi;
> + case 44: return &op_vghsh_vv;
> + case 45: return &op_vsha2ms_vv;
> + case 46: return &op_vsha2ch_vv;
> + case 47: return &op_vsha2cl_vv;
> }
> }
> break;
> case 30:
> switch (((inst >> 22) & 0b1111111000) |
> ((inst >> 12) & 0b0000000111)) {
> - case 0: op = rv_op_addd; break;
> - case 1: op = rv_op_slld; break;
> - case 5: op = rv_op_srld; break;
> - case 8: op = rv_op_muld; break;
> - case 12: op = rv_op_divd; break;
> - case 13: op = rv_op_divud; break;
> - case 14: op = rv_op_remd; break;
> - case 15: op = rv_op_remud; break;
> - case 256: op = rv_op_subd; break;
> - case 261: op = rv_op_srad; break;
> + case 0: return &op_addd;
> + case 1: return &op_slld;
> + case 5: return &op_srld;
> + case 8: return &op_muld;
> + case 12: return &op_divd;
> + case 13: return &op_divud;
> + case 14: return &op_remd;
> + case 15: return &op_remud;
> + case 256: return &op_subd;
> + case 261: return &op_srad;
> }
> break;
> }
> break;
> }
>
> - return op == rv_op_illegal ? NULL : &rvi_opcode_data[op];
> + return NULL;
> }
>
> /* decode operands */
> @@ -3446,7 +3467,7 @@ static GString *disasm_inst(rv_isa isa,
> uint64_t pc, rv_inst inst,
> }
> }
> if (!op) {
> - op = &rvi_opcode_data[rv_op_illegal];
> + op = &op_illegal;
> }
>
> decode_inst_operands(&dec, isa, op);
> diff --git a/disas/riscv-op.c.inc b/disas/riscv-op.c.inc
> index 802a521bca..cc939f557f 100644
> --- a/disas/riscv-op.c.inc
> +++ b/disas/riscv-op.c.inc
> @@ -225,51 +225,51 @@ OP(fcvt_q_l, "fcvt.q.l", rv_codec_r_m,
> rv_fmt_rm_frd_rs1)
> OP(fcvt_q_lu, "fcvt.q.lu", rv_codec_r_m, rv_fmt_rm_frd_rs1)
> OP(fmv_x_q, "fmv.x.q", rv_codec_r, rv_fmt_rd_frs1)
> OP(fmv_q_x, "fmv.q.x", rv_codec_r, rv_fmt_frd_rs1)
> -OP(c_addi4spn, "c.addi4spn", rv_codec_ciw_4spn, NULL,
> DECOMP(rv_op_addi))
> -OP(c_fld, "c.fld", rv_codec_cl_ld, NULL, DECOMP(rv_op_fld))
> -OP(c_lw, "c.lw", rv_codec_cl_lw, NULL, DECOMP(rv_op_lw))
> -OP(c_flw, "c.flw", rv_codec_cl_lw, NULL, DECOMP(rv_op_flw))
> -OP(c_fsd, "c.fsd", rv_codec_cs_sd, NULL, DECOMP(rv_op_fsd))
> -OP(c_sw, "c.sw", rv_codec_cs_sw, NULL, DECOMP(rv_op_sw))
> -OP(c_fsw, "c.fsw", rv_codec_cs_sw, NULL, DECOMP(rv_op_fsw))
> -OP(c_addi, "c.addi", rv_codec_ci, NULL, DECOMP(rv_op_addi))
> -OP(c_jal, "c.jal", rv_codec_cj_jal, NULL, DECOMP(rv_op_jal))
> -OP(c_li, "c.li", rv_codec_ci_li, NULL, DECOMP(rv_op_addi))
> -OP(c_addi16sp, "c.addi16sp", rv_codec_ci_16sp, NULL,
> DECOMP(rv_op_addi))
> -OP(c_lui, "c.lui", rv_codec_ci_lui, NULL, DECOMP(rv_op_lui))
> -OP(c_srli, "c.srli", rv_codec_cb_sh6, NULL, DECOMP(rv_op_srli))
> -OP(c_srai, "c.srai", rv_codec_cb_sh6, NULL, DECOMP(rv_op_srai))
> -OP(c_andi, "c.andi", rv_codec_cb_imm, NULL, DECOMP(rv_op_andi))
> -OP(c_sub, "c.sub", rv_codec_cs, NULL, DECOMP(rv_op_sub))
> -OP(c_xor, "c.xor", rv_codec_cs, NULL, DECOMP(rv_op_xor))
> -OP(c_or, "c.or", rv_codec_cs, NULL, DECOMP(rv_op_or))
> -OP(c_and, "c.and", rv_codec_cs, NULL, DECOMP(rv_op_and))
> -OP(c_subw, "c.subw", rv_codec_cs, NULL, DECOMP(rv_op_subw))
> -OP(c_addw, "c.addw", rv_codec_cs, NULL, DECOMP(rv_op_addw))
> -OP(c_j, "c.j", rv_codec_cj, NULL, DECOMP(rv_op_j))
> -OP(c_beqz, "c.beqz", rv_codec_cb, NULL, DECOMP(rv_op_beqz))
> -OP(c_bnez, "c.bnez", rv_codec_cb, NULL, DECOMP(rv_op_bnez))
> -OP(c_slli, "c.slli", rv_codec_ci_sh6, NULL, DECOMP(rv_op_slli))
> -OP(c_fldsp, "c.fldsp", rv_codec_ci_ldsp, NULL, DECOMP(rv_op_fld))
> -OP(c_lwsp, "c.lwsp", rv_codec_ci_lwsp, NULL, DECOMP(rv_op_lw))
> -OP(c_flwsp, "c.flwsp", rv_codec_ci_lwsp, NULL, DECOMP(rv_op_flw))
> -OP(c_jr, "c.jr", rv_codec_cr_jr, NULL, DECOMP(rv_op_jr))
> -OP(c_mv, "c.mv", rv_codec_cr_mv, NULL, DECOMP(rv_op_mv))
> -OP(c_ebreak, "c.ebreak", rv_codec_ci_none, NULL,
> DECOMP(rv_op_ebreak))
> -OP(c_jalr, "c.jalr", rv_codec_cr_jalr, NULL, DECOMP(rv_op_jalr))
> -OP(c_add, "c.add", rv_codec_cr, NULL, DECOMP(rv_op_add))
> -OP(c_fsdsp, "c.fsdsp", rv_codec_css_sdsp, NULL, DECOMP(rv_op_fsd))
> -OP(c_swsp, "c.swsp", rv_codec_css_swsp, NULL, DECOMP(rv_op_sw))
> -OP(c_fswsp, "c.fswsp", rv_codec_css_swsp, NULL, DECOMP(rv_op_fsw))
> -OP(c_ld, "c.ld", rv_codec_cl_ld, NULL, DECOMP(rv_op_ld))
> -OP(c_sd, "c.sd", rv_codec_cs_sd, NULL, DECOMP(rv_op_sd))
> -OP(c_addiw, "c.addiw", rv_codec_ci, NULL, DECOMP(rv_op_addiw))
> -OP(c_ldsp, "c.ldsp", rv_codec_ci_ldsp, NULL, DECOMP(rv_op_ld))
> -OP(c_sdsp, "c.sdsp", rv_codec_css_sdsp, NULL, DECOMP(rv_op_sd))
> -OP(c_lq, "c.lq", rv_codec_cl_lq, NULL, DECOMP(rv_op_lq))
> -OP(c_sq, "c.sq", rv_codec_cs_sq, NULL, DECOMP(rv_op_sq))
> -OP(c_lqsp, "c.lqsp", rv_codec_ci_lqsp, NULL, DECOMP(rv_op_lq))
> -OP(c_sqsp, "c.sqsp", rv_codec_css_sqsp, NULL, DECOMP(rv_op_sq))
> +OP(c_addi4spn, "c.addi4spn", rv_codec_ciw_4spn, NULL,
> DECOMP(op_addi))
> +OP(c_fld, "c.fld", rv_codec_cl_ld, NULL, DECOMP(op_fld))
> +OP(c_lw, "c.lw", rv_codec_cl_lw, NULL, DECOMP(op_lw))
> +OP(c_flw, "c.flw", rv_codec_cl_lw, NULL, DECOMP(op_flw))
> +OP(c_fsd, "c.fsd", rv_codec_cs_sd, NULL, DECOMP(op_fsd))
> +OP(c_sw, "c.sw", rv_codec_cs_sw, NULL, DECOMP(op_sw))
> +OP(c_fsw, "c.fsw", rv_codec_cs_sw, NULL, DECOMP(op_fsw))
> +OP(c_addi, "c.addi", rv_codec_ci, NULL, DECOMP(op_addi))
> +OP(c_jal, "c.jal", rv_codec_cj_jal, NULL, DECOMP(op_jal))
> +OP(c_li, "c.li", rv_codec_ci_li, NULL, DECOMP(op_addi))
> +OP(c_addi16sp, "c.addi16sp", rv_codec_ci_16sp, NULL,
> DECOMP(op_addi))
> +OP(c_lui, "c.lui", rv_codec_ci_lui, NULL, DECOMP(op_lui))
> +OP(c_srli, "c.srli", rv_codec_cb_sh6, NULL, DECOMP(op_srli))
> +OP(c_srai, "c.srai", rv_codec_cb_sh6, NULL, DECOMP(op_srai))
> +OP(c_andi, "c.andi", rv_codec_cb_imm, NULL, DECOMP(op_andi))
> +OP(c_sub, "c.sub", rv_codec_cs, NULL, DECOMP(op_sub))
> +OP(c_xor, "c.xor", rv_codec_cs, NULL, DECOMP(op_xor))
> +OP(c_or, "c.or", rv_codec_cs, NULL, DECOMP(op_or))
> +OP(c_and, "c.and", rv_codec_cs, NULL, DECOMP(op_and))
> +OP(c_subw, "c.subw", rv_codec_cs, NULL, DECOMP(op_subw))
> +OP(c_addw, "c.addw", rv_codec_cs, NULL, DECOMP(op_addw))
> +OP(c_j, "c.j", rv_codec_cj, NULL, DECOMP(op_j))
> +OP(c_beqz, "c.beqz", rv_codec_cb, NULL, DECOMP(op_beqz))
> +OP(c_bnez, "c.bnez", rv_codec_cb, NULL, DECOMP(op_bnez))
> +OP(c_slli, "c.slli", rv_codec_ci_sh6, NULL, DECOMP(op_slli))
> +OP(c_fldsp, "c.fldsp", rv_codec_ci_ldsp, NULL, DECOMP(op_fld))
> +OP(c_lwsp, "c.lwsp", rv_codec_ci_lwsp, NULL, DECOMP(op_lw))
> +OP(c_flwsp, "c.flwsp", rv_codec_ci_lwsp, NULL, DECOMP(op_flw))
> +OP(c_jr, "c.jr", rv_codec_cr_jr, NULL, DECOMP(op_jr))
> +OP(c_mv, "c.mv", rv_codec_cr_mv, NULL, DECOMP(op_mv))
> +OP(c_ebreak, "c.ebreak", rv_codec_ci_none, NULL, DECOMP(op_ebreak))
> +OP(c_jalr, "c.jalr", rv_codec_cr_jalr, NULL, DECOMP(op_jalr))
> +OP(c_add, "c.add", rv_codec_cr, NULL, DECOMP(op_add))
> +OP(c_fsdsp, "c.fsdsp", rv_codec_css_sdsp, NULL, DECOMP(op_fsd))
> +OP(c_swsp, "c.swsp", rv_codec_css_swsp, NULL, DECOMP(op_sw))
> +OP(c_fswsp, "c.fswsp", rv_codec_css_swsp, NULL, DECOMP(op_fsw))
> +OP(c_ld, "c.ld", rv_codec_cl_ld, NULL, DECOMP(op_ld))
> +OP(c_sd, "c.sd", rv_codec_cs_sd, NULL, DECOMP(op_sd))
> +OP(c_addiw, "c.addiw", rv_codec_ci, NULL, DECOMP(op_addiw))
> +OP(c_ldsp, "c.ldsp", rv_codec_ci_ldsp, NULL, DECOMP(op_ld))
> +OP(c_sdsp, "c.sdsp", rv_codec_css_sdsp, NULL, DECOMP(op_sd))
> +OP(c_lq, "c.lq", rv_codec_cl_lq, NULL, DECOMP(op_lq))
> +OP(c_sq, "c.sq", rv_codec_cs_sq, NULL, DECOMP(op_sq))
> +OP(c_lqsp, "c.lqsp", rv_codec_ci_lqsp, NULL, DECOMP(op_lq))
> +OP(c_sqsp, "c.sqsp", rv_codec_css_sqsp, NULL, DECOMP(op_sq))
> OP(nop, "nop", rv_codec_illegal, rv_fmt_none)
> OP(mv, "mv", rv_codec_illegal, rv_fmt_rd_rs1, rvcp_mv)
> OP(not, "not", rv_codec_illegal, rv_fmt_rd_rs1)
> @@ -904,8 +904,8 @@ OP(sspopchk, "sspopchk", rv_codec_r, rv_fmt_rs1)
> OP(ssrdp, "ssrdp", rv_codec_r, rv_fmt_rd)
> OP(ssamoswap_w, "ssamoswap.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> OP(ssamoswap_d, "ssamoswap.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> -OP(c_sspush, "c.sspush", rv_codec_cmop_ss, NULL,
> DECOMP(rv_op_sspush))
> -OP(c_sspopchk, "c.sspopchk", rv_codec_cmop_ss, NULL,
> DECOMP(rv_op_sspopchk))
> +OP(c_sspush, "c.sspush", rv_codec_cmop_ss, NULL, DECOMP(op_sspush))
> +OP(c_sspopchk, "c.sspopchk", rv_codec_cmop_ss, NULL,
> DECOMP(op_sspopchk))
> OP(cbo_inval, "cbo.inval", rv_codec_r, rv_fmt_rs1)
> OP(cbo_clean, "cbo.clean", rv_codec_r, rv_fmt_rs1)
> OP(cbo_flush, "cbo.flush", rv_codec_r, rv_fmt_rs1)
^ permalink raw reply [flat|nested] 119+ messages in thread
* Re: [PATCH 56/56] disas/riscv: Sort riscv-op.c.inc
2026-08-09 22:35 ` [PATCH 56/56] disas/riscv: Sort riscv-op.c.inc Richard Henderson
2026-08-10 2:59 ` Philippe Mathieu-Daudé
@ 2026-08-12 13:03 ` Alistair
1 sibling, 0 replies; 119+ messages in thread
From: Alistair @ 2026-08-12 13:03 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: qemu-riscv
On Sun, 2026-08-09 at 15:35 -0700, Richard Henderson wrote:
> To date, opcodes had to be added to the end of the list,
> resulting in quite the disorder. Sort via 'LANG=C sort'.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> disas/riscv-op.c.inc | 1704 +++++++++++++++++++++-------------------
> --
> 1 file changed, 852 insertions(+), 852 deletions(-)
>
> diff --git a/disas/riscv-op.c.inc b/disas/riscv-op.c.inc
> index cc939f557f..1d334e4857 100644
> --- a/disas/riscv-op.c.inc
> +++ b/disas/riscv-op.c.inc
> @@ -1,913 +1,913 @@
> -OP(illegal, "illegal", rv_codec_none, rv_fmt_none)
> -OP(lui, "lui", rv_codec_u, rv_fmt_rd_uimm)
> -OP(auipc, "auipc", rv_codec_u, rv_fmt_rd_uoffset)
> -OP(jal, "jal", rv_codec_uj, rv_fmt_rd_offset, rvcp_jal)
> -OP(jalr, "jalr", rv_codec_i, rv_fmt_rd_rs1_offset, rvcp_jalr)
> -OP(beq, "beq", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_beq)
> -OP(bne, "bne", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_bne)
> -OP(blt, "blt", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_blt)
> -OP(bge, "bge", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_bge)
> -OP(bltu, "bltu", rv_codec_sb, rv_fmt_rs1_rs2_offset)
> -OP(bgeu, "bgeu", rv_codec_sb, rv_fmt_rs1_rs2_offset)
> -OP(lb, "lb", rv_codec_i, rv_fmt_rd_offset_rs1)
> -OP(lh, "lh", rv_codec_i, rv_fmt_rd_offset_rs1)
> -OP(lw, "lw", rv_codec_i, rv_fmt_rd_offset_rs1)
> -OP(lbu, "lbu", rv_codec_i, rv_fmt_rd_offset_rs1)
> -OP(lhu, "lhu", rv_codec_i, rv_fmt_rd_offset_rs1)
> -OP(sb, "sb", rv_codec_s, rv_fmt_rs2_offset_rs1)
> -OP(sh, "sh", rv_codec_s, rv_fmt_rs2_offset_rs1)
> -OP(sw, "sw", rv_codec_s, rv_fmt_rs2_offset_rs1)
> -OP(addi, "addi", rv_codec_i, rv_fmt_rd_rs1_imm, rvcp_addi)
> -OP(slti, "slti", rv_codec_i, rv_fmt_rd_rs1_imm)
> -OP(sltiu, "sltiu", rv_codec_i, rv_fmt_rd_rs1_imm, rvcp_sltiu)
> -OP(xori, "xori", rv_codec_i, rv_fmt_rd_rs1_imm, rvcp_xori)
> -OP(ori, "ori", rv_codec_i, rv_fmt_rd_rs1_imm)
> -OP(andi, "andi", rv_codec_i, rv_fmt_rd_rs1_imm)
> -OP(slli, "slli", rv_codec_i_sh7, rv_fmt_rd_rs1_imm)
> -OP(srli, "srli", rv_codec_i_sh7, rv_fmt_rd_rs1_imm)
> -OP(srai, "srai", rv_codec_i_sh7, rv_fmt_rd_rs1_imm)
> OP(add, "add", rv_codec_r, rv_fmt_rd_rs1_rs2)
> -OP(sub, "sub", rv_codec_r, rv_fmt_rd_rs1_rs2, rvcp_sub)
> -OP(sll, "sll", rv_codec_r, rv_fmt_rd_rs1_rs2)
> -OP(slt, "slt", rv_codec_r, rv_fmt_rd_rs1_rs2, rvcp_slt)
> -OP(sltu, "sltu", rv_codec_r, rv_fmt_rd_rs1_rs2, rvcp_sltu)
> -OP(xor, "xor", rv_codec_r, rv_fmt_rd_rs1_rs2)
> -OP(srl, "srl", rv_codec_r, rv_fmt_rd_rs1_rs2)
> -OP(sra, "sra", rv_codec_r, rv_fmt_rd_rs1_rs2)
> -OP(or, "or", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(add_uw, "add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(addd, "addd", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(addi, "addi", rv_codec_i, rv_fmt_rd_rs1_imm, rvcp_addi)
> +OP(addid, "addid", rv_codec_i, rv_fmt_rd_rs1_imm)
> +OP(addiw, "addiw", rv_codec_i, rv_fmt_rd_rs1_imm, rvcp_addiw)
> +OP(addw, "addw", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(aes32dsi, "aes32dsi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs)
> +OP(aes32dsmi, "aes32dsmi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs)
> +OP(aes32esi, "aes32esi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs)
> +OP(aes32esmi, "aes32esmi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs)
> +OP(aes64ds, "aes64ds", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(aes64dsm, "aes64dsm", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(aes64es, "aes64es", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(aes64esm, "aes64esm", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(aes64im, "aes64im", rv_codec_r, rv_fmt_rd_rs1)
> +OP(aes64ks1i, "aes64ks1i", rv_codec_k_rnum, rv_fmt_rd_rs1_rnum)
> +OP(aes64ks2, "aes64ks2", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(amoadd_b, "amoadd.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> +OP(amoadd_d, "amoadd.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> +OP(amoadd_h, "amoadd.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> +OP(amoadd_q, "amoadd.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> +OP(amoadd_w, "amoadd.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> +OP(amoand_b, "amoand.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> +OP(amoand_d, "amoand.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> +OP(amoand_h, "amoand.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> +OP(amoand_q, "amoand.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> +OP(amoand_w, "amoand.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> +OP(amocas_b, "amocas.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> +OP(amocas_d, "amocas.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> +OP(amocas_h, "amocas.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> +OP(amocas_q, "amocas.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> +OP(amocas_w, "amocas.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> +OP(amomax_b, "amomax.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> +OP(amomax_d, "amomax.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> +OP(amomax_h, "amomax.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> +OP(amomax_q, "amomax.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> +OP(amomax_w, "amomax.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> +OP(amomaxu_b, "amomaxu.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> +OP(amomaxu_d, "amomaxu.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> +OP(amomaxu_h, "amomaxu.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> +OP(amomaxu_q, "amomaxu.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> +OP(amomaxu_w, "amomaxu.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> +OP(amomin_b, "amomin.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> +OP(amomin_d, "amomin.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> +OP(amomin_h, "amomin.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> +OP(amomin_q, "amomin.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> +OP(amomin_w, "amomin.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> +OP(amominu_b, "amominu.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> +OP(amominu_d, "amominu.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> +OP(amominu_h, "amominu.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> +OP(amominu_q, "amominu.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> +OP(amominu_w, "amominu.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> +OP(amoor_b, "amoor.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> +OP(amoor_d, "amoor.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> +OP(amoor_h, "amoor.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> +OP(amoor_q, "amoor.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> +OP(amoor_w, "amoor.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> +OP(amoswap_b, "amoswap.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> +OP(amoswap_d, "amoswap.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> +OP(amoswap_h, "amoswap.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> +OP(amoswap_q, "amoswap.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> +OP(amoswap_w, "amoswap.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> +OP(amoxor_b, "amoxor.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> +OP(amoxor_d, "amoxor.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> +OP(amoxor_h, "amoxor.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> +OP(amoxor_q, "amoxor.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> +OP(amoxor_w, "amoxor.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> OP(and, "and", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(andi, "andi", rv_codec_i, rv_fmt_rd_rs1_imm)
> +OP(andn, "andn", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(auipc, "auipc", rv_codec_u, rv_fmt_rd_uoffset)
> +OP(bclr, "bclr", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(bclri, "bclri", rv_codec_i_sh7, rv_fmt_rd_rs1_imm)
> +OP(beq, "beq", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_beq)
> +OP(beqz, "beqz", rv_codec_illegal, rv_fmt_rs1_offset)
> +OP(bext, "bext", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(bexti, "bexti", rv_codec_i_sh7, rv_fmt_rd_rs1_imm)
> +OP(bge, "bge", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_bge)
> +OP(bgeu, "bgeu", rv_codec_sb, rv_fmt_rs1_rs2_offset)
> +OP(bgez, "bgez", rv_codec_illegal, rv_fmt_rs1_offset)
> +OP(bgtz, "bgtz", rv_codec_illegal, rv_fmt_rs2_offset)
> +OP(binv, "binv", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(binvi, "binvi", rv_codec_i_sh7, rv_fmt_rd_rs1_imm)
> +OP(blez, "blez", rv_codec_illegal, rv_fmt_rs2_offset)
> +OP(blt, "blt", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_blt)
> +OP(bltu, "bltu", rv_codec_sb, rv_fmt_rs1_rs2_offset)
> +OP(bltz, "bltz", rv_codec_illegal, rv_fmt_rs1_offset)
> +OP(bne, "bne", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_bne)
> +OP(bnez, "bnez", rv_codec_illegal, rv_fmt_rs1_offset)
> +OP(brev8, "brev8", rv_codec_r, rv_fmt_rd_rs1)
> +OP(bset, "bset", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(bseti, "bseti", rv_codec_i_sh7, rv_fmt_rd_rs1_imm)
> +OP(c_add, "c.add", rv_codec_cr, NULL, DECOMP(op_add))
> +OP(c_addi, "c.addi", rv_codec_ci, NULL, DECOMP(op_addi))
> +OP(c_addi16sp, "c.addi16sp", rv_codec_ci_16sp, NULL,
> DECOMP(op_addi))
> +OP(c_addi4spn, "c.addi4spn", rv_codec_ciw_4spn, NULL,
> DECOMP(op_addi))
> +OP(c_addiw, "c.addiw", rv_codec_ci, NULL, DECOMP(op_addiw))
> +OP(c_addw, "c.addw", rv_codec_cs, NULL, DECOMP(op_addw))
> +OP(c_and, "c.and", rv_codec_cs, NULL, DECOMP(op_and))
> +OP(c_andi, "c.andi", rv_codec_cb_imm, NULL, DECOMP(op_andi))
> +OP(c_beqz, "c.beqz", rv_codec_cb, NULL, DECOMP(op_beqz))
> +OP(c_bnez, "c.bnez", rv_codec_cb, NULL, DECOMP(op_bnez))
> +OP(c_ebreak, "c.ebreak", rv_codec_ci_none, NULL, DECOMP(op_ebreak))
> +OP(c_fld, "c.fld", rv_codec_cl_ld, NULL, DECOMP(op_fld))
> +OP(c_fldsp, "c.fldsp", rv_codec_ci_ldsp, NULL, DECOMP(op_fld))
> +OP(c_flw, "c.flw", rv_codec_cl_lw, NULL, DECOMP(op_flw))
> +OP(c_flwsp, "c.flwsp", rv_codec_ci_lwsp, NULL, DECOMP(op_flw))
> +OP(c_fsd, "c.fsd", rv_codec_cs_sd, NULL, DECOMP(op_fsd))
> +OP(c_fsdsp, "c.fsdsp", rv_codec_css_sdsp, NULL, DECOMP(op_fsd))
> +OP(c_fsw, "c.fsw", rv_codec_cs_sw, NULL, DECOMP(op_fsw))
> +OP(c_fswsp, "c.fswsp", rv_codec_css_swsp, NULL, DECOMP(op_fsw))
> +OP(c_j, "c.j", rv_codec_cj, NULL, DECOMP(op_j))
> +OP(c_jal, "c.jal", rv_codec_cj_jal, NULL, DECOMP(op_jal))
> +OP(c_jalr, "c.jalr", rv_codec_cr_jalr, NULL, DECOMP(op_jalr))
> +OP(c_jr, "c.jr", rv_codec_cr_jr, NULL, DECOMP(op_jr))
> +OP(c_lbu, "c.lbu", rv_codec_zcb_lb, rv_fmt_rs1_rs2_zce_ldst)
> +OP(c_ld, "c.ld", rv_codec_cl_ld, NULL, DECOMP(op_ld))
> +OP(c_ldsp, "c.ldsp", rv_codec_ci_ldsp, NULL, DECOMP(op_ld))
> +OP(c_lh, "c.lh", rv_codec_zcb_lh, rv_fmt_rs1_rs2_zce_ldst)
> +OP(c_lhu, "c.lhu", rv_codec_zcb_lh, rv_fmt_rs1_rs2_zce_ldst)
> +OP(c_li, "c.li", rv_codec_ci_li, NULL, DECOMP(op_addi))
> +OP(c_lq, "c.lq", rv_codec_cl_lq, NULL, DECOMP(op_lq))
> +OP(c_lqsp, "c.lqsp", rv_codec_ci_lqsp, NULL, DECOMP(op_lq))
> +OP(c_lui, "c.lui", rv_codec_ci_lui, NULL, DECOMP(op_lui))
> +OP(c_lw, "c.lw", rv_codec_cl_lw, NULL, DECOMP(op_lw))
> +OP(c_lwsp, "c.lwsp", rv_codec_ci_lwsp, NULL, DECOMP(op_lw))
> +OP(c_mop, "c.mop", rv_codec_cmop, rv_fmt_cmop)
> +OP(c_mul, "c.mul", rv_codec_zcb_mul, rv_fmt_rd_rs2)
> +OP(c_mv, "c.mv", rv_codec_cr_mv, NULL, DECOMP(op_mv))
> +OP(c_not, "c.not", rv_codec_zcb_ext, rv_fmt_rd)
> +OP(c_or, "c.or", rv_codec_cs, NULL, DECOMP(op_or))
> +OP(c_sb, "c.sb", rv_codec_zcb_lb, rv_fmt_rs1_rs2_zce_ldst)
> +OP(c_sd, "c.sd", rv_codec_cs_sd, NULL, DECOMP(op_sd))
> +OP(c_sdsp, "c.sdsp", rv_codec_css_sdsp, NULL, DECOMP(op_sd))
> +OP(c_sext_b, "c.sext.b", rv_codec_zcb_ext, rv_fmt_rd)
> +OP(c_sext_h, "c.sext.h", rv_codec_zcb_ext, rv_fmt_rd)
> +OP(c_sh, "c.sh", rv_codec_zcb_lh, rv_fmt_rs1_rs2_zce_ldst)
> +OP(c_slli, "c.slli", rv_codec_ci_sh6, NULL, DECOMP(op_slli))
> +OP(c_sq, "c.sq", rv_codec_cs_sq, NULL, DECOMP(op_sq))
> +OP(c_sqsp, "c.sqsp", rv_codec_css_sqsp, NULL, DECOMP(op_sq))
> +OP(c_srai, "c.srai", rv_codec_cb_sh6, NULL, DECOMP(op_srai))
> +OP(c_srli, "c.srli", rv_codec_cb_sh6, NULL, DECOMP(op_srli))
> +OP(c_sspopchk, "c.sspopchk", rv_codec_cmop_ss, NULL,
> DECOMP(op_sspopchk))
> +OP(c_sspush, "c.sspush", rv_codec_cmop_ss, NULL, DECOMP(op_sspush))
> +OP(c_sub, "c.sub", rv_codec_cs, NULL, DECOMP(op_sub))
> +OP(c_subw, "c.subw", rv_codec_cs, NULL, DECOMP(op_subw))
> +OP(c_sw, "c.sw", rv_codec_cs_sw, NULL, DECOMP(op_sw))
> +OP(c_swsp, "c.swsp", rv_codec_css_swsp, NULL, DECOMP(op_sw))
> +OP(c_xor, "c.xor", rv_codec_cs, NULL, DECOMP(op_xor))
> +OP(c_zext_b, "c.zext.b", rv_codec_zcb_ext, rv_fmt_rd)
> +OP(c_zext_h, "c.zext.h", rv_codec_zcb_ext, rv_fmt_rd)
> +OP(c_zext_w, "c.zext.w", rv_codec_zcb_ext, rv_fmt_rd)
> +OP(cbo_clean, "cbo.clean", rv_codec_r, rv_fmt_rs1)
> +OP(cbo_flush, "cbo.flush", rv_codec_r, rv_fmt_rs1)
> +OP(cbo_inval, "cbo.inval", rv_codec_r, rv_fmt_rs1)
> +OP(cbo_zero, "cbo.zero", rv_codec_r, rv_fmt_rs1)
> +OP(clmul, "clmul", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(clmulh, "clmulh", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(clmulr, "clmulr", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(clz, "clz", rv_codec_r, rv_fmt_rd_rs1)
> +OP(clzw, "clzw", rv_codec_r, rv_fmt_rd_rs1)
> +OP(cm_jalt, "cm.jalt", rv_codec_zcmt_jt, rv_fmt_zcmt_index)
> +OP(cm_jt, "cm.jt", rv_codec_zcmt_jt, rv_fmt_zcmt_index)
> +OP(cm_mva01s, "cm.mva01s", rv_codec_zcmp_cm_mv, rv_fmt_rd_rs2)
> +OP(cm_mvsa01, "cm.mvsa01", rv_codec_zcmp_cm_mv, rv_fmt_rd_rs2)
> +OP(cm_pop, "cm.pop", rv_codec_zcmp_cm_pushpop, rv_fmt_pop_rlist)
> +OP(cm_popret, "cm.popret", rv_codec_zcmp_cm_pushpop,
> rv_fmt_pop_rlist)
> +OP(cm_popretz, "cm.popretz", rv_codec_zcmp_cm_pushpop,
> rv_fmt_pop_rlist)
> +OP(cm_push, "cm.push", rv_codec_zcmp_cm_pushpop, rv_fmt_push_rlist)
> +OP(cpop, "cpop", rv_codec_r, rv_fmt_rd_rs1)
> +OP(cpopw, "cpopw", rv_codec_r, rv_fmt_rd_rs1)
> +OP(csrrc, "csrrc", rv_codec_i_csr, rv_fmt_rd_csr_rs1)
> +OP(csrrci, "csrrci", rv_codec_i_csr, rv_fmt_rd_csr_zimm)
> +OP(csrrs, "csrrs", rv_codec_i_csr, rv_fmt_rd_csr_rs1)
> +OP(csrrsi, "csrrsi", rv_codec_i_csr, rv_fmt_rd_csr_zimm)
> +OP(csrrw, "csrrw", rv_codec_i_csr, rv_fmt_rd_csr_rs1)
> +OP(csrrwi, "csrrwi", rv_codec_i_csr, rv_fmt_rd_csr_zimm)
> +OP(ctz, "ctz", rv_codec_r, rv_fmt_rd_rs1)
> +OP(ctzw, "ctzw", rv_codec_r, rv_fmt_rd_rs1)
> +OP(czero_eqz, "czero.eqz", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(czero_nez, "czero.nez", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(div, "div", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(divd, "divd", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(divu, "divu", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(divud, "divud", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(divuw, "divuw", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(divw, "divw", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(dret, "dret", rv_codec_none, rv_fmt_none)
> +OP(ebreak, "ebreak", rv_codec_none, rv_fmt_none)
> +OP(ecall, "ecall", rv_codec_none, rv_fmt_none)
> +OP(fabs_d, "fabs.d", rv_codec_illegal, rv_fmt_frd_frs1)
> +OP(fabs_q, "fabs.q", rv_codec_illegal, rv_fmt_frd_frs1)
> +OP(fabs_s, "fabs.s", rv_codec_illegal, rv_fmt_frd_frs1)
> +OP(fadd_d, "fadd.d", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2)
> +OP(fadd_q, "fadd.q", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2)
> +OP(fadd_s, "fadd.s", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2)
> +OP(fclass_d, "fclass.d", rv_codec_r, rv_fmt_rd_frs1)
> +OP(fclass_q, "fclass.q", rv_codec_r, rv_fmt_rd_frs1)
> +OP(fclass_s, "fclass.s", rv_codec_r, rv_fmt_rd_frs1)
> +OP(fcvt_bf16_s, "fcvt.bf16.s", rv_codec_r_m, rv_fmt_rm_frd_frs1)
> +OP(fcvt_d_l, "fcvt.d.l", rv_codec_r_m, rv_fmt_rm_frd_rs1)
> +OP(fcvt_d_lu, "fcvt.d.lu", rv_codec_r_m, rv_fmt_rm_frd_rs1)
> +OP(fcvt_d_q, "fcvt.d.q", rv_codec_r_m, rv_fmt_rm_frd_frs1)
> +OP(fcvt_d_s, "fcvt.d.s", rv_codec_r_m, rv_fmt_rm_frd_frs1)
> +OP(fcvt_d_w, "fcvt.d.w", rv_codec_r_m, rv_fmt_rm_frd_rs1)
> +OP(fcvt_d_wu, "fcvt.d.wu", rv_codec_r_m, rv_fmt_rm_frd_rs1)
> +OP(fcvt_l_d, "fcvt.l.d", rv_codec_r_m, rv_fmt_rm_rd_frs1)
> +OP(fcvt_l_q, "fcvt.l.q", rv_codec_r_m, rv_fmt_rm_rd_frs1)
> +OP(fcvt_l_s, "fcvt.l.s", rv_codec_r_m, rv_fmt_rm_rd_frs1)
> +OP(fcvt_lu_d, "fcvt.lu.d", rv_codec_r_m, rv_fmt_rm_rd_frs1)
> +OP(fcvt_lu_q, "fcvt.lu.q", rv_codec_r_m, rv_fmt_rm_rd_frs1)
> +OP(fcvt_lu_s, "fcvt.lu.s", rv_codec_r_m, rv_fmt_rm_rd_frs1)
> +OP(fcvt_q_d, "fcvt.q.d", rv_codec_r_m, rv_fmt_rm_frd_frs1)
> +OP(fcvt_q_l, "fcvt.q.l", rv_codec_r_m, rv_fmt_rm_frd_rs1)
> +OP(fcvt_q_lu, "fcvt.q.lu", rv_codec_r_m, rv_fmt_rm_frd_rs1)
> +OP(fcvt_q_s, "fcvt.q.s", rv_codec_r_m, rv_fmt_rm_frd_frs1)
> +OP(fcvt_q_w, "fcvt.q.w", rv_codec_r_m, rv_fmt_rm_frd_rs1)
> +OP(fcvt_q_wu, "fcvt.q.wu", rv_codec_r_m, rv_fmt_rm_frd_rs1)
> +OP(fcvt_s_bf16, "fcvt.s.bf16", rv_codec_r_m, rv_fmt_rm_frd_frs1)
> +OP(fcvt_s_d, "fcvt.s.d", rv_codec_r_m, rv_fmt_rm_frd_frs1)
> +OP(fcvt_s_l, "fcvt.s.l", rv_codec_r_m, rv_fmt_rm_frd_rs1)
> +OP(fcvt_s_lu, "fcvt.s.lu", rv_codec_r_m, rv_fmt_rm_frd_rs1)
> +OP(fcvt_s_q, "fcvt.s.q", rv_codec_r_m, rv_fmt_rm_frd_frs1)
> +OP(fcvt_s_w, "fcvt.s.w", rv_codec_r_m, rv_fmt_rm_frd_rs1)
> +OP(fcvt_s_wu, "fcvt.s.wu", rv_codec_r_m, rv_fmt_rm_frd_rs1)
> +OP(fcvt_w_d, "fcvt.w.d", rv_codec_r_m, rv_fmt_rm_rd_frs1)
> +OP(fcvt_w_q, "fcvt.w.q", rv_codec_r_m, rv_fmt_rm_rd_frs1)
> +OP(fcvt_w_s, "fcvt.w.s", rv_codec_r_m, rv_fmt_rm_rd_frs1)
> +OP(fcvt_wu_d, "fcvt.wu.d", rv_codec_r_m, rv_fmt_rm_rd_frs1)
> +OP(fcvt_wu_q, "fcvt.wu.q", rv_codec_r_m, rv_fmt_rm_rd_frs1)
> +OP(fcvt_wu_s, "fcvt.wu.s", rv_codec_r_m, rv_fmt_rm_rd_frs1)
> +OP(fcvtmod_w_d, "fcvtmod.w.d", rv_codec_r_m, rv_fmt_rm_rd_frs1)
> +OP(fdiv_d, "fdiv.d", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2)
> +OP(fdiv_q, "fdiv.q", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2)
> +OP(fdiv_s, "fdiv.s", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2)
> OP(fence, "fence", rv_codec_r_f, rv_fmt_pred_succ)
> OP(fence_i, "fence.i", rv_codec_none, rv_fmt_none)
> -OP(lwu, "lwu", rv_codec_i, rv_fmt_rd_offset_rs1)
> +OP(feq_d, "feq.d", rv_codec_r, rv_fmt_rd_frs1_frs2)
> +OP(feq_q, "feq.q", rv_codec_r, rv_fmt_rd_frs1_frs2)
> +OP(feq_s, "feq.s", rv_codec_r, rv_fmt_rd_frs1_frs2)
> +OP(fld, "fld", rv_codec_i, rv_fmt_frd_offset_rs1)
> +OP(fle_d, "fle.d", rv_codec_r, rv_fmt_rd_frs1_frs2)
> +OP(fle_q, "fle.q", rv_codec_r, rv_fmt_rd_frs1_frs2)
> +OP(fle_s, "fle.s", rv_codec_r, rv_fmt_rd_frs1_frs2)
> +OP(fleq_d, "fleq.d", rv_codec_r, rv_fmt_rd_frs1_frs2)
> +OP(fleq_h, "fleq.h", rv_codec_r, rv_fmt_rd_frs1_frs2)
> +OP(fleq_q, "fleq.q", rv_codec_r, rv_fmt_rd_frs1_frs2)
> +OP(fleq_s, "fleq.s", rv_codec_r, rv_fmt_rd_frs1_frs2)
> +OP(flh, "flh", rv_codec_i, rv_fmt_frd_offset_rs1)
> +OP(fli_d, "fli.d", rv_codec_fli, rv_fmt_fli)
> +OP(fli_h, "fli.h", rv_codec_fli, rv_fmt_fli)
> +OP(fli_q, "fli.q", rv_codec_fli, rv_fmt_fli)
> +OP(fli_s, "fli.s", rv_codec_fli, rv_fmt_fli)
> +OP(flq, "flq", rv_codec_i, rv_fmt_frd_offset_rs1)
> +OP(flt_d, "flt.d", rv_codec_r, rv_fmt_rd_frs1_frs2)
> +OP(flt_q, "flt.q", rv_codec_r, rv_fmt_rd_frs1_frs2)
> +OP(flt_s, "flt.s", rv_codec_r, rv_fmt_rd_frs1_frs2)
> +OP(fltq_d, "fltq.d", rv_codec_r, rv_fmt_rd_frs1_frs2)
> +OP(fltq_h, "fltq.h", rv_codec_r, rv_fmt_rd_frs1_frs2)
> +OP(fltq_q, "fltq.q", rv_codec_r, rv_fmt_rd_frs1_frs2)
> +OP(fltq_s, "fltq.s", rv_codec_r, rv_fmt_rd_frs1_frs2)
> +OP(flw, "flw", rv_codec_i, rv_fmt_frd_offset_rs1)
> +OP(fmadd_d, "fmadd.d", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3)
> +OP(fmadd_q, "fmadd.q", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3)
> +OP(fmadd_s, "fmadd.s", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3)
> +OP(fmax_d, "fmax.d", rv_codec_r, rv_fmt_frd_frs1_frs2)
> +OP(fmax_q, "fmax.q", rv_codec_r, rv_fmt_frd_frs1_frs2)
> +OP(fmax_s, "fmax.s", rv_codec_r, rv_fmt_frd_frs1_frs2)
> +OP(fmaxm_d, "fmaxm.d", rv_codec_r, rv_fmt_frd_frs1_frs2)
> +OP(fmaxm_h, "fmaxm.h", rv_codec_r, rv_fmt_frd_frs1_frs2)
> +OP(fmaxm_q, "fmaxm.q", rv_codec_r, rv_fmt_frd_frs1_frs2)
> +OP(fmaxm_s, "fmaxm.s", rv_codec_r, rv_fmt_frd_frs1_frs2)
> +OP(fmin_d, "fmin.d", rv_codec_r, rv_fmt_frd_frs1_frs2)
> +OP(fmin_q, "fmin.q", rv_codec_r, rv_fmt_frd_frs1_frs2)
> +OP(fmin_s, "fmin.s", rv_codec_r, rv_fmt_frd_frs1_frs2)
> +OP(fminm_d, "fminm.d", rv_codec_r, rv_fmt_frd_frs1_frs2)
> +OP(fminm_h, "fminm.h", rv_codec_r, rv_fmt_frd_frs1_frs2)
> +OP(fminm_q, "fminm.q", rv_codec_r, rv_fmt_frd_frs1_frs2)
> +OP(fminm_s, "fminm.s", rv_codec_r, rv_fmt_frd_frs1_frs2)
> +OP(fmsub_d, "fmsub.d", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3)
> +OP(fmsub_q, "fmsub.q", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3)
> +OP(fmsub_s, "fmsub.s", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3)
> +OP(fmul_d, "fmul.d", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2)
> +OP(fmul_q, "fmul.q", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2)
> +OP(fmul_s, "fmul.s", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2)
> +OP(fmv_d, "fmv.d", rv_codec_illegal, rv_fmt_frd_frs1)
> +OP(fmv_d_x, "fmv.d.x", rv_codec_r, rv_fmt_frd_rs1)
> +OP(fmv_h_x, "fmv.h.x", rv_codec_r, rv_fmt_frd_rs1)
> +OP(fmv_q, "fmv.q", rv_codec_illegal, rv_fmt_frd_frs1)
> +OP(fmv_q_x, "fmv.q.x", rv_codec_r, rv_fmt_frd_rs1)
> +OP(fmv_s, "fmv.s", rv_codec_illegal, rv_fmt_frd_frs1)
> +OP(fmv_s_x, "fmv.s.x", rv_codec_r, rv_fmt_frd_rs1)
> +OP(fmv_x_d, "fmv.x.d", rv_codec_r, rv_fmt_rd_frs1)
> +OP(fmv_x_h, "fmv.x.h", rv_codec_r, rv_fmt_rd_frs1)
> +OP(fmv_x_q, "fmv.x.q", rv_codec_r, rv_fmt_rd_frs1)
> +OP(fmv_x_s, "fmv.x.s", rv_codec_r, rv_fmt_rd_frs1)
> +OP(fmvh_x_d, "fmvh.x.d", rv_codec_r, rv_fmt_rd_frs1)
> +OP(fmvh_x_q, "fmvh.x.q", rv_codec_r, rv_fmt_rd_frs1)
> +OP(fmvp_d_x, "fmvp.d.x", rv_codec_r, rv_fmt_frd_rs1_rs2)
> +OP(fmvp_q_x, "fmvp.q.x", rv_codec_r, rv_fmt_frd_rs1_rs2)
> +OP(fneg_d, "fneg.d", rv_codec_illegal, rv_fmt_frd_frs1)
> +OP(fneg_q, "fneg.q", rv_codec_illegal, rv_fmt_frd_frs1)
> +OP(fneg_s, "fneg.s", rv_codec_illegal, rv_fmt_frd_frs1)
> +OP(fnmadd_d, "fnmadd.d", rv_codec_r4_m,
> rv_fmt_rm_frd_frs1_frs2_frs3)
> +OP(fnmadd_q, "fnmadd.q", rv_codec_r4_m,
> rv_fmt_rm_frd_frs1_frs2_frs3)
> +OP(fnmadd_s, "fnmadd.s", rv_codec_r4_m,
> rv_fmt_rm_frd_frs1_frs2_frs3)
> +OP(fnmsub_d, "fnmsub.d", rv_codec_r4_m,
> rv_fmt_rm_frd_frs1_frs2_frs3)
> +OP(fnmsub_q, "fnmsub.q", rv_codec_r4_m,
> rv_fmt_rm_frd_frs1_frs2_frs3)
> +OP(fnmsub_s, "fnmsub.s", rv_codec_r4_m,
> rv_fmt_rm_frd_frs1_frs2_frs3)
> +OP(frcsr, "frcsr", rv_codec_i_csr, rv_fmt_rd)
> +OP(frflags, "frflags", rv_codec_i_csr, rv_fmt_rd)
> +OP(fround_d, "fround.d", rv_codec_r_m, rv_fmt_rm_frd_frs1)
> +OP(fround_h, "fround.h", rv_codec_r_m, rv_fmt_rm_frd_frs1)
> +OP(fround_q, "fround.q", rv_codec_r_m, rv_fmt_rm_frd_frs1)
> +OP(fround_s, "fround.s", rv_codec_r_m, rv_fmt_rm_frd_frs1)
> +OP(froundnx_d, "froundnx.d", rv_codec_r_m, rv_fmt_rm_frd_frs1)
> +OP(froundnx_h, "froundnx.h", rv_codec_r_m, rv_fmt_rm_frd_frs1)
> +OP(froundnx_q, "froundnx.q", rv_codec_r_m, rv_fmt_rm_frd_frs1)
> +OP(froundnx_s, "froundnx.s", rv_codec_r_m, rv_fmt_rm_frd_frs1)
> +OP(frrm, "frrm", rv_codec_i_csr, rv_fmt_rd)
> +OP(fscsr, "fscsr", rv_codec_i_csr, rv_fmt_rd_rs1)
> +OP(fsd, "fsd", rv_codec_s, rv_fmt_frs2_offset_rs1)
> +OP(fsflags, "fsflags", rv_codec_i_csr, rv_fmt_rd_rs1)
> +OP(fsflagsi, "fsflagsi", rv_codec_i_csr, rv_fmt_rd_zimm)
> +OP(fsgnj_d, "fsgnj.d", rv_codec_r, rv_fmt_frd_frs1_frs2,
> rvcp_fsgnj_d)
> +OP(fsgnj_q, "fsgnj.q", rv_codec_r, rv_fmt_frd_frs1_frs2,
> rvcp_fsgnj_q)
> +OP(fsgnj_s, "fsgnj.s", rv_codec_r, rv_fmt_frd_frs1_frs2,
> rvcp_fsgnj_s)
> +OP(fsgnjn_d, "fsgnjn.d", rv_codec_r, rv_fmt_frd_frs1_frs2,
> rvcp_fsgnjn_d)
> +OP(fsgnjn_q, "fsgnjn.q", rv_codec_r, rv_fmt_frd_frs1_frs2,
> rvcp_fsgnjn_q)
> +OP(fsgnjn_s, "fsgnjn.s", rv_codec_r, rv_fmt_frd_frs1_frs2,
> rvcp_fsgnjn_s)
> +OP(fsgnjx_d, "fsgnjx.d", rv_codec_r, rv_fmt_frd_frs1_frs2,
> rvcp_fsgnjx_d)
> +OP(fsgnjx_q, "fsgnjx.q", rv_codec_r, rv_fmt_frd_frs1_frs2,
> rvcp_fsgnjx_q)
> +OP(fsgnjx_s, "fsgnjx.s", rv_codec_r, rv_fmt_frd_frs1_frs2,
> rvcp_fsgnjx_s)
> +OP(fsh, "fsh", rv_codec_s, rv_fmt_frs2_offset_rs1)
> +OP(fsq, "fsq", rv_codec_s, rv_fmt_frs2_offset_rs1)
> +OP(fsqrt_d, "fsqrt.d", rv_codec_r_m, rv_fmt_rm_frd_frs1)
> +OP(fsqrt_q, "fsqrt.q", rv_codec_r_m, rv_fmt_rm_frd_frs1)
> +OP(fsqrt_s, "fsqrt.s", rv_codec_r_m, rv_fmt_rm_frd_frs1)
> +OP(fsrm, "fsrm", rv_codec_i_csr, rv_fmt_rd_rs1)
> +OP(fsrmi, "fsrmi", rv_codec_i_csr, rv_fmt_rd_zimm)
> +OP(fsub_d, "fsub.d", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2)
> +OP(fsub_q, "fsub.q", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2)
> +OP(fsub_s, "fsub.s", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2)
> +OP(fsw, "fsw", rv_codec_s, rv_fmt_frs2_offset_rs1)
> +OP(hret, "hret", rv_codec_none, rv_fmt_none)
> +OP(illegal, "illegal", rv_codec_none, rv_fmt_none)
> +OP(j, "j", rv_codec_illegal, rv_fmt_offset)
> +OP(jal, "jal", rv_codec_uj, rv_fmt_rd_offset, rvcp_jal)
> +OP(jal_ra, "jal", rv_codec_illegal, rv_fmt_offset)
> +OP(jalr, "jalr", rv_codec_i, rv_fmt_rd_rs1_offset, rvcp_jalr)
> +OP(jalr_ra, "jalr", rv_codec_illegal, rv_fmt_rs1)
> +OP(jr, "jr", rv_codec_illegal, rv_fmt_rs1, rvcp_jr)
> +OP(lb, "lb", rv_codec_i, rv_fmt_rd_offset_rs1)
> +OP(lbu, "lbu", rv_codec_i, rv_fmt_rd_offset_rs1)
> OP(ld, "ld", rv_codec_i, rv_fmt_rd_offset_rs1)
> -OP(sd, "sd", rv_codec_s, rv_fmt_rs2_offset_rs1)
> -OP(addiw, "addiw", rv_codec_i, rv_fmt_rd_rs1_imm, rvcp_addiw)
> -OP(slliw, "slliw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm)
> -OP(srliw, "srliw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm)
> -OP(sraiw, "sraiw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm)
> -OP(addw, "addw", rv_codec_r, rv_fmt_rd_rs1_rs2)
> -OP(subw, "subw", rv_codec_r, rv_fmt_rd_rs1_rs2, rvcp_subw)
> -OP(sllw, "sllw", rv_codec_r, rv_fmt_rd_rs1_rs2)
> -OP(srlw, "srlw", rv_codec_r, rv_fmt_rd_rs1_rs2)
> -OP(sraw, "sraw", rv_codec_r, rv_fmt_rd_rs1_rs2)
> OP(ldu, "ldu", rv_codec_i, rv_fmt_rd_offset_rs1)
> +OP(lh, "lh", rv_codec_i, rv_fmt_rd_offset_rs1)
> +OP(lhu, "lhu", rv_codec_i, rv_fmt_rd_offset_rs1)
> +OP(lpad, "lpad", rv_codec_lp, rv_fmt_imm)
> OP(lq, "lq", rv_codec_i, rv_fmt_rd_offset_rs1)
> -OP(sq, "sq", rv_codec_s, rv_fmt_rs2_offset_rs1)
> -OP(addid, "addid", rv_codec_i, rv_fmt_rd_rs1_imm)
> -OP(sllid, "sllid", rv_codec_i_sh6, rv_fmt_rd_rs1_imm)
> -OP(srlid, "srlid", rv_codec_i_sh6, rv_fmt_rd_rs1_imm)
> -OP(sraid, "sraid", rv_codec_i_sh6, rv_fmt_rd_rs1_imm)
> -OP(addd, "addd", rv_codec_r, rv_fmt_rd_rs1_rs2)
> -OP(subd, "subd", rv_codec_r, rv_fmt_rd_rs1_rs2)
> -OP(slld, "slld", rv_codec_r, rv_fmt_rd_rs1_rs2)
> -OP(srld, "srld", rv_codec_r, rv_fmt_rd_rs1_rs2)
> -OP(srad, "srad", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(lr_d, "lr.d", rv_codec_r_l, rv_fmt_aqrl_rd_rs1)
> +OP(lr_q, "lr.q", rv_codec_r_l, rv_fmt_aqrl_rd_rs1)
> +OP(lr_w, "lr.w", rv_codec_r_l, rv_fmt_aqrl_rd_rs1)
> +OP(lui, "lui", rv_codec_u, rv_fmt_rd_uimm)
> +OP(lw, "lw", rv_codec_i, rv_fmt_rd_offset_rs1)
> +OP(lwu, "lwu", rv_codec_i, rv_fmt_rd_offset_rs1)
> +OP(max, "max", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(maxu, "maxu", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(min, "min", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(minu, "minu", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(mnret, "mnret", rv_codec_none, rv_fmt_none)
> +OP(mop_r, "mop.r", rv_codec_mop_r, rv_fmt_mop_r)
> +OP(mop_rr, "mop.rr", rv_codec_mop_rr, rv_fmt_mop_rr)
> +OP(mret, "mret", rv_codec_none, rv_fmt_none)
> OP(mul, "mul", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(muld, "muld", rv_codec_r, rv_fmt_rd_rs1_rs2)
> OP(mulh, "mulh", rv_codec_r, rv_fmt_rd_rs1_rs2)
> OP(mulhsu, "mulhsu", rv_codec_r, rv_fmt_rd_rs1_rs2)
> OP(mulhu, "mulhu", rv_codec_r, rv_fmt_rd_rs1_rs2)
> -OP(div, "div", rv_codec_r, rv_fmt_rd_rs1_rs2)
> -OP(divu, "divu", rv_codec_r, rv_fmt_rd_rs1_rs2)
> -OP(rem, "rem", rv_codec_r, rv_fmt_rd_rs1_rs2)
> -OP(remu, "remu", rv_codec_r, rv_fmt_rd_rs1_rs2)
> OP(mulw, "mulw", rv_codec_r, rv_fmt_rd_rs1_rs2)
> -OP(divw, "divw", rv_codec_r, rv_fmt_rd_rs1_rs2)
> -OP(divuw, "divuw", rv_codec_r, rv_fmt_rd_rs1_rs2)
> -OP(remw, "remw", rv_codec_r, rv_fmt_rd_rs1_rs2)
> -OP(remuw, "remuw", rv_codec_r, rv_fmt_rd_rs1_rs2)
> -OP(muld, "muld", rv_codec_r, rv_fmt_rd_rs1_rs2)
> -OP(divd, "divd", rv_codec_r, rv_fmt_rd_rs1_rs2)
> -OP(divud, "divud", rv_codec_r, rv_fmt_rd_rs1_rs2)
> -OP(remd, "remd", rv_codec_r, rv_fmt_rd_rs1_rs2)
> -OP(remud, "remud", rv_codec_r, rv_fmt_rd_rs1_rs2)
> -OP(lr_w, "lr.w", rv_codec_r_l, rv_fmt_aqrl_rd_rs1)
> -OP(sc_w, "sc.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> -OP(amoswap_w, "amoswap.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> -OP(amoadd_w, "amoadd.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> -OP(amoxor_w, "amoxor.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> -OP(amoor_w, "amoor.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> -OP(amoand_w, "amoand.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> -OP(amomin_w, "amomin.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> -OP(amomax_w, "amomax.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> -OP(amominu_w, "amominu.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> -OP(amomaxu_w, "amomaxu.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> -OP(lr_d, "lr.d", rv_codec_r_l, rv_fmt_aqrl_rd_rs1)
> -OP(sc_d, "sc.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> -OP(amoswap_d, "amoswap.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> -OP(amoadd_d, "amoadd.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> -OP(amoxor_d, "amoxor.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> -OP(amoor_d, "amoor.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> -OP(amoand_d, "amoand.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> -OP(amomin_d, "amomin.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> -OP(amomax_d, "amomax.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> -OP(amominu_d, "amominu.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> -OP(amomaxu_d, "amomaxu.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> -OP(lr_q, "lr.q", rv_codec_r_l, rv_fmt_aqrl_rd_rs1)
> -OP(sc_q, "sc.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> -OP(amoswap_q, "amoswap.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> -OP(amoadd_q, "amoadd.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> -OP(amoxor_q, "amoxor.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> -OP(amoor_q, "amoor.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> -OP(amoand_q, "amoand.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> -OP(amomin_q, "amomin.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> -OP(amomax_q, "amomax.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> -OP(amominu_q, "amominu.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> -OP(amomaxu_q, "amomaxu.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> -OP(ecall, "ecall", rv_codec_none, rv_fmt_none)
> -OP(ebreak, "ebreak", rv_codec_none, rv_fmt_none)
> -OP(uret, "uret", rv_codec_none, rv_fmt_none)
> -OP(sret, "sret", rv_codec_none, rv_fmt_none)
> -OP(hret, "hret", rv_codec_none, rv_fmt_none)
> -OP(mret, "mret", rv_codec_none, rv_fmt_none)
> -OP(dret, "dret", rv_codec_none, rv_fmt_none)
> -OP(sfence_vm, "sfence.vm", rv_codec_r, rv_fmt_rs1)
> -OP(sfence_vma, "sfence.vma", rv_codec_r, rv_fmt_rs1_rs2)
> -OP(wfi, "wfi", rv_codec_none, rv_fmt_none)
> -OP(csrrw, "csrrw", rv_codec_i_csr, rv_fmt_rd_csr_rs1)
> -OP(csrrs, "csrrs", rv_codec_i_csr, rv_fmt_rd_csr_rs1)
> -OP(csrrc, "csrrc", rv_codec_i_csr, rv_fmt_rd_csr_rs1)
> -OP(csrrwi, "csrrwi", rv_codec_i_csr, rv_fmt_rd_csr_zimm)
> -OP(csrrsi, "csrrsi", rv_codec_i_csr, rv_fmt_rd_csr_zimm)
> -OP(csrrci, "csrrci", rv_codec_i_csr, rv_fmt_rd_csr_zimm)
> -OP(flw, "flw", rv_codec_i, rv_fmt_frd_offset_rs1)
> -OP(fsw, "fsw", rv_codec_s, rv_fmt_frs2_offset_rs1)
> -OP(fmadd_s, "fmadd.s", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3)
> -OP(fmsub_s, "fmsub.s", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3)
> -OP(fnmsub_s, "fnmsub.s", rv_codec_r4_m,
> rv_fmt_rm_frd_frs1_frs2_frs3)
> -OP(fnmadd_s, "fnmadd.s", rv_codec_r4_m,
> rv_fmt_rm_frd_frs1_frs2_frs3)
> -OP(fadd_s, "fadd.s", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2)
> -OP(fsub_s, "fsub.s", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2)
> -OP(fmul_s, "fmul.s", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2)
> -OP(fdiv_s, "fdiv.s", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2)
> -OP(fsgnj_s, "fsgnj.s", rv_codec_r, rv_fmt_frd_frs1_frs2,
> rvcp_fsgnj_s)
> -OP(fsgnjn_s, "fsgnjn.s", rv_codec_r, rv_fmt_frd_frs1_frs2,
> rvcp_fsgnjn_s)
> -OP(fsgnjx_s, "fsgnjx.s", rv_codec_r, rv_fmt_frd_frs1_frs2,
> rvcp_fsgnjx_s)
> -OP(fmin_s, "fmin.s", rv_codec_r, rv_fmt_frd_frs1_frs2)
> -OP(fmax_s, "fmax.s", rv_codec_r, rv_fmt_frd_frs1_frs2)
> -OP(fsqrt_s, "fsqrt.s", rv_codec_r_m, rv_fmt_rm_frd_frs1)
> -OP(fle_s, "fle.s", rv_codec_r, rv_fmt_rd_frs1_frs2)
> -OP(flt_s, "flt.s", rv_codec_r, rv_fmt_rd_frs1_frs2)
> -OP(feq_s, "feq.s", rv_codec_r, rv_fmt_rd_frs1_frs2)
> -OP(fcvt_w_s, "fcvt.w.s", rv_codec_r_m, rv_fmt_rm_rd_frs1)
> -OP(fcvt_wu_s, "fcvt.wu.s", rv_codec_r_m, rv_fmt_rm_rd_frs1)
> -OP(fcvt_s_w, "fcvt.s.w", rv_codec_r_m, rv_fmt_rm_frd_rs1)
> -OP(fcvt_s_wu, "fcvt.s.wu", rv_codec_r_m, rv_fmt_rm_frd_rs1)
> -OP(fmv_x_s, "fmv.x.s", rv_codec_r, rv_fmt_rd_frs1)
> -OP(fclass_s, "fclass.s", rv_codec_r, rv_fmt_rd_frs1)
> -OP(fmv_s_x, "fmv.s.x", rv_codec_r, rv_fmt_frd_rs1)
> -OP(fcvt_l_s, "fcvt.l.s", rv_codec_r_m, rv_fmt_rm_rd_frs1)
> -OP(fcvt_lu_s, "fcvt.lu.s", rv_codec_r_m, rv_fmt_rm_rd_frs1)
> -OP(fcvt_s_l, "fcvt.s.l", rv_codec_r_m, rv_fmt_rm_frd_rs1)
> -OP(fcvt_s_lu, "fcvt.s.lu", rv_codec_r_m, rv_fmt_rm_frd_rs1)
> -OP(fld, "fld", rv_codec_i, rv_fmt_frd_offset_rs1)
> -OP(fsd, "fsd", rv_codec_s, rv_fmt_frs2_offset_rs1)
> -OP(fmadd_d, "fmadd.d", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3)
> -OP(fmsub_d, "fmsub.d", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3)
> -OP(fnmsub_d, "fnmsub.d", rv_codec_r4_m,
> rv_fmt_rm_frd_frs1_frs2_frs3)
> -OP(fnmadd_d, "fnmadd.d", rv_codec_r4_m,
> rv_fmt_rm_frd_frs1_frs2_frs3)
> -OP(fadd_d, "fadd.d", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2)
> -OP(fsub_d, "fsub.d", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2)
> -OP(fmul_d, "fmul.d", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2)
> -OP(fdiv_d, "fdiv.d", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2)
> -OP(fsgnj_d, "fsgnj.d", rv_codec_r, rv_fmt_frd_frs1_frs2,
> rvcp_fsgnj_d)
> -OP(fsgnjn_d, "fsgnjn.d", rv_codec_r, rv_fmt_frd_frs1_frs2,
> rvcp_fsgnjn_d)
> -OP(fsgnjx_d, "fsgnjx.d", rv_codec_r, rv_fmt_frd_frs1_frs2,
> rvcp_fsgnjx_d)
> -OP(fmin_d, "fmin.d", rv_codec_r, rv_fmt_frd_frs1_frs2)
> -OP(fmax_d, "fmax.d", rv_codec_r, rv_fmt_frd_frs1_frs2)
> -OP(fcvt_s_d, "fcvt.s.d", rv_codec_r_m, rv_fmt_rm_frd_frs1)
> -OP(fcvt_d_s, "fcvt.d.s", rv_codec_r_m, rv_fmt_rm_frd_frs1)
> -OP(fsqrt_d, "fsqrt.d", rv_codec_r_m, rv_fmt_rm_frd_frs1)
> -OP(fle_d, "fle.d", rv_codec_r, rv_fmt_rd_frs1_frs2)
> -OP(flt_d, "flt.d", rv_codec_r, rv_fmt_rd_frs1_frs2)
> -OP(feq_d, "feq.d", rv_codec_r, rv_fmt_rd_frs1_frs2)
> -OP(fcvt_w_d, "fcvt.w.d", rv_codec_r_m, rv_fmt_rm_rd_frs1)
> -OP(fcvt_wu_d, "fcvt.wu.d", rv_codec_r_m, rv_fmt_rm_rd_frs1)
> -OP(fcvt_d_w, "fcvt.d.w", rv_codec_r_m, rv_fmt_rm_frd_rs1)
> -OP(fcvt_d_wu, "fcvt.d.wu", rv_codec_r_m, rv_fmt_rm_frd_rs1)
> -OP(fclass_d, "fclass.d", rv_codec_r, rv_fmt_rd_frs1)
> -OP(fcvt_l_d, "fcvt.l.d", rv_codec_r_m, rv_fmt_rm_rd_frs1)
> -OP(fcvt_lu_d, "fcvt.lu.d", rv_codec_r_m, rv_fmt_rm_rd_frs1)
> -OP(fmv_x_d, "fmv.x.d", rv_codec_r, rv_fmt_rd_frs1)
> -OP(fcvt_d_l, "fcvt.d.l", rv_codec_r_m, rv_fmt_rm_frd_rs1)
> -OP(fcvt_d_lu, "fcvt.d.lu", rv_codec_r_m, rv_fmt_rm_frd_rs1)
> -OP(fmv_d_x, "fmv.d.x", rv_codec_r, rv_fmt_frd_rs1)
> -OP(flq, "flq", rv_codec_i, rv_fmt_frd_offset_rs1)
> -OP(fsq, "fsq", rv_codec_s, rv_fmt_frs2_offset_rs1)
> -OP(fmadd_q, "fmadd.q", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3)
> -OP(fmsub_q, "fmsub.q", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3)
> -OP(fnmsub_q, "fnmsub.q", rv_codec_r4_m,
> rv_fmt_rm_frd_frs1_frs2_frs3)
> -OP(fnmadd_q, "fnmadd.q", rv_codec_r4_m,
> rv_fmt_rm_frd_frs1_frs2_frs3)
> -OP(fadd_q, "fadd.q", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2)
> -OP(fsub_q, "fsub.q", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2)
> -OP(fmul_q, "fmul.q", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2)
> -OP(fdiv_q, "fdiv.q", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2)
> -OP(fsgnj_q, "fsgnj.q", rv_codec_r, rv_fmt_frd_frs1_frs2,
> rvcp_fsgnj_q)
> -OP(fsgnjn_q, "fsgnjn.q", rv_codec_r, rv_fmt_frd_frs1_frs2,
> rvcp_fsgnjn_q)
> -OP(fsgnjx_q, "fsgnjx.q", rv_codec_r, rv_fmt_frd_frs1_frs2,
> rvcp_fsgnjx_q)
> -OP(fmin_q, "fmin.q", rv_codec_r, rv_fmt_frd_frs1_frs2)
> -OP(fmax_q, "fmax.q", rv_codec_r, rv_fmt_frd_frs1_frs2)
> -OP(fcvt_s_q, "fcvt.s.q", rv_codec_r_m, rv_fmt_rm_frd_frs1)
> -OP(fcvt_q_s, "fcvt.q.s", rv_codec_r_m, rv_fmt_rm_frd_frs1)
> -OP(fcvt_d_q, "fcvt.d.q", rv_codec_r_m, rv_fmt_rm_frd_frs1)
> -OP(fcvt_q_d, "fcvt.q.d", rv_codec_r_m, rv_fmt_rm_frd_frs1)
> -OP(fsqrt_q, "fsqrt.q", rv_codec_r_m, rv_fmt_rm_frd_frs1)
> -OP(fle_q, "fle.q", rv_codec_r, rv_fmt_rd_frs1_frs2)
> -OP(flt_q, "flt.q", rv_codec_r, rv_fmt_rd_frs1_frs2)
> -OP(feq_q, "feq.q", rv_codec_r, rv_fmt_rd_frs1_frs2)
> -OP(fcvt_w_q, "fcvt.w.q", rv_codec_r_m, rv_fmt_rm_rd_frs1)
> -OP(fcvt_wu_q, "fcvt.wu.q", rv_codec_r_m, rv_fmt_rm_rd_frs1)
> -OP(fcvt_q_w, "fcvt.q.w", rv_codec_r_m, rv_fmt_rm_frd_rs1)
> -OP(fcvt_q_wu, "fcvt.q.wu", rv_codec_r_m, rv_fmt_rm_frd_rs1)
> -OP(fclass_q, "fclass.q", rv_codec_r, rv_fmt_rd_frs1)
> -OP(fcvt_l_q, "fcvt.l.q", rv_codec_r_m, rv_fmt_rm_rd_frs1)
> -OP(fcvt_lu_q, "fcvt.lu.q", rv_codec_r_m, rv_fmt_rm_rd_frs1)
> -OP(fcvt_q_l, "fcvt.q.l", rv_codec_r_m, rv_fmt_rm_frd_rs1)
> -OP(fcvt_q_lu, "fcvt.q.lu", rv_codec_r_m, rv_fmt_rm_frd_rs1)
> -OP(fmv_x_q, "fmv.x.q", rv_codec_r, rv_fmt_rd_frs1)
> -OP(fmv_q_x, "fmv.q.x", rv_codec_r, rv_fmt_frd_rs1)
> -OP(c_addi4spn, "c.addi4spn", rv_codec_ciw_4spn, NULL,
> DECOMP(op_addi))
> -OP(c_fld, "c.fld", rv_codec_cl_ld, NULL, DECOMP(op_fld))
> -OP(c_lw, "c.lw", rv_codec_cl_lw, NULL, DECOMP(op_lw))
> -OP(c_flw, "c.flw", rv_codec_cl_lw, NULL, DECOMP(op_flw))
> -OP(c_fsd, "c.fsd", rv_codec_cs_sd, NULL, DECOMP(op_fsd))
> -OP(c_sw, "c.sw", rv_codec_cs_sw, NULL, DECOMP(op_sw))
> -OP(c_fsw, "c.fsw", rv_codec_cs_sw, NULL, DECOMP(op_fsw))
> -OP(c_addi, "c.addi", rv_codec_ci, NULL, DECOMP(op_addi))
> -OP(c_jal, "c.jal", rv_codec_cj_jal, NULL, DECOMP(op_jal))
> -OP(c_li, "c.li", rv_codec_ci_li, NULL, DECOMP(op_addi))
> -OP(c_addi16sp, "c.addi16sp", rv_codec_ci_16sp, NULL,
> DECOMP(op_addi))
> -OP(c_lui, "c.lui", rv_codec_ci_lui, NULL, DECOMP(op_lui))
> -OP(c_srli, "c.srli", rv_codec_cb_sh6, NULL, DECOMP(op_srli))
> -OP(c_srai, "c.srai", rv_codec_cb_sh6, NULL, DECOMP(op_srai))
> -OP(c_andi, "c.andi", rv_codec_cb_imm, NULL, DECOMP(op_andi))
> -OP(c_sub, "c.sub", rv_codec_cs, NULL, DECOMP(op_sub))
> -OP(c_xor, "c.xor", rv_codec_cs, NULL, DECOMP(op_xor))
> -OP(c_or, "c.or", rv_codec_cs, NULL, DECOMP(op_or))
> -OP(c_and, "c.and", rv_codec_cs, NULL, DECOMP(op_and))
> -OP(c_subw, "c.subw", rv_codec_cs, NULL, DECOMP(op_subw))
> -OP(c_addw, "c.addw", rv_codec_cs, NULL, DECOMP(op_addw))
> -OP(c_j, "c.j", rv_codec_cj, NULL, DECOMP(op_j))
> -OP(c_beqz, "c.beqz", rv_codec_cb, NULL, DECOMP(op_beqz))
> -OP(c_bnez, "c.bnez", rv_codec_cb, NULL, DECOMP(op_bnez))
> -OP(c_slli, "c.slli", rv_codec_ci_sh6, NULL, DECOMP(op_slli))
> -OP(c_fldsp, "c.fldsp", rv_codec_ci_ldsp, NULL, DECOMP(op_fld))
> -OP(c_lwsp, "c.lwsp", rv_codec_ci_lwsp, NULL, DECOMP(op_lw))
> -OP(c_flwsp, "c.flwsp", rv_codec_ci_lwsp, NULL, DECOMP(op_flw))
> -OP(c_jr, "c.jr", rv_codec_cr_jr, NULL, DECOMP(op_jr))
> -OP(c_mv, "c.mv", rv_codec_cr_mv, NULL, DECOMP(op_mv))
> -OP(c_ebreak, "c.ebreak", rv_codec_ci_none, NULL, DECOMP(op_ebreak))
> -OP(c_jalr, "c.jalr", rv_codec_cr_jalr, NULL, DECOMP(op_jalr))
> -OP(c_add, "c.add", rv_codec_cr, NULL, DECOMP(op_add))
> -OP(c_fsdsp, "c.fsdsp", rv_codec_css_sdsp, NULL, DECOMP(op_fsd))
> -OP(c_swsp, "c.swsp", rv_codec_css_swsp, NULL, DECOMP(op_sw))
> -OP(c_fswsp, "c.fswsp", rv_codec_css_swsp, NULL, DECOMP(op_fsw))
> -OP(c_ld, "c.ld", rv_codec_cl_ld, NULL, DECOMP(op_ld))
> -OP(c_sd, "c.sd", rv_codec_cs_sd, NULL, DECOMP(op_sd))
> -OP(c_addiw, "c.addiw", rv_codec_ci, NULL, DECOMP(op_addiw))
> -OP(c_ldsp, "c.ldsp", rv_codec_ci_ldsp, NULL, DECOMP(op_ld))
> -OP(c_sdsp, "c.sdsp", rv_codec_css_sdsp, NULL, DECOMP(op_sd))
> -OP(c_lq, "c.lq", rv_codec_cl_lq, NULL, DECOMP(op_lq))
> -OP(c_sq, "c.sq", rv_codec_cs_sq, NULL, DECOMP(op_sq))
> -OP(c_lqsp, "c.lqsp", rv_codec_ci_lqsp, NULL, DECOMP(op_lq))
> -OP(c_sqsp, "c.sqsp", rv_codec_css_sqsp, NULL, DECOMP(op_sq))
> -OP(nop, "nop", rv_codec_illegal, rv_fmt_none)
> OP(mv, "mv", rv_codec_illegal, rv_fmt_rd_rs1, rvcp_mv)
> -OP(not, "not", rv_codec_illegal, rv_fmt_rd_rs1)
> OP(neg, "neg", rv_codec_illegal, rv_fmt_rd_rs2)
> OP(negw, "negw", rv_codec_illegal, rv_fmt_rd_rs2)
> -OP(sext_w, "sext.w", rv_codec_illegal, rv_fmt_rd_rs1)
> -OP(seqz, "seqz", rv_codec_illegal, rv_fmt_rd_rs1)
> -OP(snez, "snez", rv_codec_illegal, rv_fmt_rd_rs2)
> -OP(sltz, "sltz", rv_codec_illegal, rv_fmt_rd_rs1)
> -OP(sgtz, "sgtz", rv_codec_illegal, rv_fmt_rd_rs2)
> -OP(fmv_s, "fmv.s", rv_codec_illegal, rv_fmt_frd_frs1)
> -OP(fabs_s, "fabs.s", rv_codec_illegal, rv_fmt_frd_frs1)
> -OP(fneg_s, "fneg.s", rv_codec_illegal, rv_fmt_frd_frs1)
> -OP(fmv_d, "fmv.d", rv_codec_illegal, rv_fmt_frd_frs1)
> -OP(fabs_d, "fabs.d", rv_codec_illegal, rv_fmt_frd_frs1)
> -OP(fneg_d, "fneg.d", rv_codec_illegal, rv_fmt_frd_frs1)
> -OP(fmv_q, "fmv.q", rv_codec_illegal, rv_fmt_frd_frs1)
> -OP(fabs_q, "fabs.q", rv_codec_illegal, rv_fmt_frd_frs1)
> -OP(fneg_q, "fneg.q", rv_codec_illegal, rv_fmt_frd_frs1)
> -OP(beqz, "beqz", rv_codec_illegal, rv_fmt_rs1_offset)
> -OP(bnez, "bnez", rv_codec_illegal, rv_fmt_rs1_offset)
> -OP(blez, "blez", rv_codec_illegal, rv_fmt_rs2_offset)
> -OP(bgez, "bgez", rv_codec_illegal, rv_fmt_rs1_offset)
> -OP(bltz, "bltz", rv_codec_illegal, rv_fmt_rs1_offset)
> -OP(bgtz, "bgtz", rv_codec_illegal, rv_fmt_rs2_offset)
> -OP(jal_ra, "jal", rv_codec_illegal, rv_fmt_offset)
> -OP(jalr_ra, "jalr", rv_codec_illegal, rv_fmt_rs1)
> -OP(j, "j", rv_codec_illegal, rv_fmt_offset)
> -OP(ret, "ret", rv_codec_illegal, rv_fmt_none)
> -OP(jr, "jr", rv_codec_illegal, rv_fmt_rs1, rvcp_jr)
> -OP(rdcycle, "rdcycle", rv_codec_i_csr, rv_fmt_rd)
> -OP(rdtime, "rdtime", rv_codec_i_csr, rv_fmt_rd)
> -OP(rdinstret, "rdinstret", rv_codec_i_csr, rv_fmt_rd)
> -OP(rdcycleh, "rdcycleh", rv_codec_i_csr, rv_fmt_rd)
> -OP(rdtimeh, "rdtimeh", rv_codec_i_csr, rv_fmt_rd)
> -OP(rdinstreth, "rdinstreth", rv_codec_i_csr, rv_fmt_rd)
> -OP(frcsr, "frcsr", rv_codec_i_csr, rv_fmt_rd)
> -OP(frrm, "frrm", rv_codec_i_csr, rv_fmt_rd)
> -OP(frflags, "frflags", rv_codec_i_csr, rv_fmt_rd)
> -OP(fscsr, "fscsr", rv_codec_i_csr, rv_fmt_rd_rs1)
> -OP(fsrm, "fsrm", rv_codec_i_csr, rv_fmt_rd_rs1)
> -OP(fsflags, "fsflags", rv_codec_i_csr, rv_fmt_rd_rs1)
> -OP(fsrmi, "fsrmi", rv_codec_i_csr, rv_fmt_rd_zimm)
> -OP(fsflagsi, "fsflagsi", rv_codec_i_csr, rv_fmt_rd_zimm)
> -OP(bseti, "bseti", rv_codec_i_sh7, rv_fmt_rd_rs1_imm)
> -OP(bclri, "bclri", rv_codec_i_sh7, rv_fmt_rd_rs1_imm)
> -OP(binvi, "binvi", rv_codec_i_sh7, rv_fmt_rd_rs1_imm)
> -OP(bexti, "bexti", rv_codec_i_sh7, rv_fmt_rd_rs1_imm)
> -OP(rori, "rori", rv_codec_i_sh7, rv_fmt_rd_rs1_imm)
> -OP(clz, "clz", rv_codec_r, rv_fmt_rd_rs1)
> -OP(ctz, "ctz", rv_codec_r, rv_fmt_rd_rs1)
> -OP(cpop, "cpop", rv_codec_r, rv_fmt_rd_rs1)
> -OP(sext_h, "sext.h", rv_codec_r, rv_fmt_rd_rs1)
> -OP(sext_b, "sext.b", rv_codec_r, rv_fmt_rd_rs1)
> -OP(xnor, "xnor", rv_codec_r, rv_fmt_rd_rs1_rs2)
> -OP(orn, "orn", rv_codec_r, rv_fmt_rd_rs1_rs2)
> -OP(andn, "andn", rv_codec_r, rv_fmt_rd_rs1_rs2)
> -OP(rol, "rol", rv_codec_r, rv_fmt_rd_rs1_rs2)
> -OP(ror, "ror", rv_codec_r, rv_fmt_rd_rs1_rs2)
> -OP(sh1add, "sh1add", rv_codec_r, rv_fmt_rd_rs1_rs2)
> -OP(sh2add, "sh2add", rv_codec_r, rv_fmt_rd_rs1_rs2)
> -OP(sh3add, "sh3add", rv_codec_r, rv_fmt_rd_rs1_rs2)
> -OP(sh1add_uw, "sh1add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2)
> -OP(sh2add_uw, "sh2add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2)
> -OP(sh3add_uw, "sh3add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2)
> -OP(clmul, "clmul", rv_codec_r, rv_fmt_rd_rs1_rs2)
> -OP(clmulr, "clmulr", rv_codec_r, rv_fmt_rd_rs1_rs2)
> -OP(clmulh, "clmulh", rv_codec_r, rv_fmt_rd_rs1_rs2)
> -OP(min, "min", rv_codec_r, rv_fmt_rd_rs1_rs2)
> -OP(minu, "minu", rv_codec_r, rv_fmt_rd_rs1_rs2)
> -OP(max, "max", rv_codec_r, rv_fmt_rd_rs1_rs2)
> -OP(maxu, "maxu", rv_codec_r, rv_fmt_rd_rs1_rs2)
> -OP(clzw, "clzw", rv_codec_r, rv_fmt_rd_rs1)
> -OP(ctzw, "ctzw", rv_codec_r, rv_fmt_rd_rs1)
> -OP(cpopw, "cpopw", rv_codec_r, rv_fmt_rd_rs1)
> -OP(slli_uw, "slli.uw", rv_codec_i_sh6, rv_fmt_rd_rs1_imm)
> -OP(add_uw, "add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2)
> -OP(rolw, "rolw", rv_codec_r, rv_fmt_rd_rs1_rs2)
> -OP(rorw, "rorw", rv_codec_r, rv_fmt_rd_rs1_rs2)
> -OP(rev8, "rev8", rv_codec_r, rv_fmt_rd_rs1)
> -OP(zext_h, "zext.h", rv_codec_r, rv_fmt_rd_rs1)
> -OP(roriw, "roriw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm)
> +OP(nop, "nop", rv_codec_illegal, rv_fmt_none)
> +OP(not, "not", rv_codec_illegal, rv_fmt_rd_rs1)
> +OP(or, "or", rv_codec_r, rv_fmt_rd_rs1_rs2)
> OP(orc_b, "orc.b", rv_codec_r, rv_fmt_rd_rs1)
> -OP(bset, "bset", rv_codec_r, rv_fmt_rd_rs1_rs2)
> -OP(bclr, "bclr", rv_codec_r, rv_fmt_rd_rs1_rs2)
> -OP(binv, "binv", rv_codec_r, rv_fmt_rd_rs1_rs2)
> -OP(bext, "bext", rv_codec_r, rv_fmt_rd_rs1_rs2)
> -OP(aes32esmi, "aes32esmi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs)
> -OP(aes32esi, "aes32esi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs)
> -OP(aes32dsmi, "aes32dsmi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs)
> -OP(aes32dsi, "aes32dsi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs)
> -OP(aes64ks1i, "aes64ks1i", rv_codec_k_rnum, rv_fmt_rd_rs1_rnum)
> -OP(aes64ks2, "aes64ks2", rv_codec_r, rv_fmt_rd_rs1_rs2)
> -OP(aes64im, "aes64im", rv_codec_r, rv_fmt_rd_rs1)
> -OP(aes64esm, "aes64esm", rv_codec_r, rv_fmt_rd_rs1_rs2)
> -OP(aes64es, "aes64es", rv_codec_r, rv_fmt_rd_rs1_rs2)
> -OP(aes64dsm, "aes64dsm", rv_codec_r, rv_fmt_rd_rs1_rs2)
> -OP(aes64ds, "aes64ds", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(ori, "ori", rv_codec_i, rv_fmt_rd_rs1_imm)
> +OP(orn, "orn", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(pack, "pack", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(packh, "packh", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(packw, "packw", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(rdcycle, "rdcycle", rv_codec_i_csr, rv_fmt_rd)
> +OP(rdcycleh, "rdcycleh", rv_codec_i_csr, rv_fmt_rd)
> +OP(rdinstret, "rdinstret", rv_codec_i_csr, rv_fmt_rd)
> +OP(rdinstreth, "rdinstreth", rv_codec_i_csr, rv_fmt_rd)
> +OP(rdtime, "rdtime", rv_codec_i_csr, rv_fmt_rd)
> +OP(rdtimeh, "rdtimeh", rv_codec_i_csr, rv_fmt_rd)
> +OP(rem, "rem", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(remd, "remd", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(remu, "remu", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(remud, "remud", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(remuw, "remuw", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(remw, "remw", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(ret, "ret", rv_codec_illegal, rv_fmt_none)
> +OP(rev8, "rev8", rv_codec_r, rv_fmt_rd_rs1)
> +OP(rol, "rol", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(rolw, "rolw", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(ror, "ror", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(rori, "rori", rv_codec_i_sh7, rv_fmt_rd_rs1_imm)
> +OP(roriw, "roriw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm)
> +OP(rorw, "rorw", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(sb, "sb", rv_codec_s, rv_fmt_rs2_offset_rs1)
> +OP(sc_d, "sc.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> +OP(sc_q, "sc.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> +OP(sc_w, "sc.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> +OP(sd, "sd", rv_codec_s, rv_fmt_rs2_offset_rs1)
> +OP(seqz, "seqz", rv_codec_illegal, rv_fmt_rd_rs1)
> +OP(sext_b, "sext.b", rv_codec_r, rv_fmt_rd_rs1)
> +OP(sext_h, "sext.h", rv_codec_r, rv_fmt_rd_rs1)
> +OP(sext_w, "sext.w", rv_codec_illegal, rv_fmt_rd_rs1)
> +OP(sfence_vm, "sfence.vm", rv_codec_r, rv_fmt_rs1)
> +OP(sfence_vma, "sfence.vma", rv_codec_r, rv_fmt_rs1_rs2)
> +OP(sgtz, "sgtz", rv_codec_illegal, rv_fmt_rd_rs2)
> +OP(sh, "sh", rv_codec_s, rv_fmt_rs2_offset_rs1)
> +OP(sh1add, "sh1add", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(sh1add_uw, "sh1add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(sh2add, "sh2add", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(sh2add_uw, "sh2add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(sh3add, "sh3add", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(sh3add_uw, "sh3add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2)
> OP(sha256sig0, "sha256sig0", rv_codec_r, rv_fmt_rd_rs1)
> OP(sha256sig1, "sha256sig1", rv_codec_r, rv_fmt_rd_rs1)
> OP(sha256sum0, "sha256sum0", rv_codec_r, rv_fmt_rd_rs1)
> OP(sha256sum1, "sha256sum1", rv_codec_r, rv_fmt_rd_rs1)
> OP(sha512sig0, "sha512sig0", rv_codec_r, rv_fmt_rd_rs1_rs2)
> -OP(sha512sig1, "sha512sig1", rv_codec_r, rv_fmt_rd_rs1_rs2)
> -OP(sha512sum0, "sha512sum0", rv_codec_r, rv_fmt_rd_rs1_rs2)
> -OP(sha512sum1, "sha512sum1", rv_codec_r, rv_fmt_rd_rs1_rs2)
> -OP(sha512sum0r, "sha512sum0r", rv_codec_r, rv_fmt_rd_rs1_rs2)
> -OP(sha512sum1r, "sha512sum1r", rv_codec_r, rv_fmt_rd_rs1_rs2)
> -OP(sha512sig0l, "sha512sig0l", rv_codec_r, rv_fmt_rd_rs1_rs2)
> OP(sha512sig0h, "sha512sig0h", rv_codec_r, rv_fmt_rd_rs1_rs2)
> -OP(sha512sig1l, "sha512sig1l", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(sha512sig0l, "sha512sig0l", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(sha512sig1, "sha512sig1", rv_codec_r, rv_fmt_rd_rs1_rs2)
> OP(sha512sig1h, "sha512sig1h", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(sha512sig1l, "sha512sig1l", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(sha512sum0, "sha512sum0", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(sha512sum0r, "sha512sum0r", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(sha512sum1, "sha512sum1", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(sha512sum1r, "sha512sum1r", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(sll, "sll", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(slld, "slld", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(slli, "slli", rv_codec_i_sh7, rv_fmt_rd_rs1_imm)
> +OP(slli_uw, "slli.uw", rv_codec_i_sh6, rv_fmt_rd_rs1_imm)
> +OP(sllid, "sllid", rv_codec_i_sh6, rv_fmt_rd_rs1_imm)
> +OP(slliw, "slliw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm)
> +OP(sllw, "sllw", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(slt, "slt", rv_codec_r, rv_fmt_rd_rs1_rs2, rvcp_slt)
> +OP(slti, "slti", rv_codec_i, rv_fmt_rd_rs1_imm)
> +OP(sltiu, "sltiu", rv_codec_i, rv_fmt_rd_rs1_imm, rvcp_sltiu)
> +OP(sltu, "sltu", rv_codec_r, rv_fmt_rd_rs1_rs2, rvcp_sltu)
> +OP(sltz, "sltz", rv_codec_illegal, rv_fmt_rd_rs1)
> OP(sm3p0, "sm3p0", rv_codec_r, rv_fmt_rd_rs1)
> OP(sm3p1, "sm3p1", rv_codec_r, rv_fmt_rd_rs1)
> OP(sm4ed, "sm4ed", rv_codec_k_bs, rv_fmt_rs1_rs2_bs)
> OP(sm4ks, "sm4ks", rv_codec_k_bs, rv_fmt_rs1_rs2_bs)
> -OP(brev8, "brev8", rv_codec_r, rv_fmt_rd_rs1)
> -OP(pack, "pack", rv_codec_r, rv_fmt_rd_rs1_rs2)
> -OP(packh, "packh", rv_codec_r, rv_fmt_rd_rs1_rs2)
> -OP(packw, "packw", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(snez, "snez", rv_codec_illegal, rv_fmt_rd_rs2)
> +OP(sq, "sq", rv_codec_s, rv_fmt_rs2_offset_rs1)
> +OP(sra, "sra", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(srad, "srad", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(srai, "srai", rv_codec_i_sh7, rv_fmt_rd_rs1_imm)
> +OP(sraid, "sraid", rv_codec_i_sh6, rv_fmt_rd_rs1_imm)
> +OP(sraiw, "sraiw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm)
> +OP(sraw, "sraw", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(sret, "sret", rv_codec_none, rv_fmt_none)
> +OP(srl, "srl", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(srld, "srld", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(srli, "srli", rv_codec_i_sh7, rv_fmt_rd_rs1_imm)
> +OP(srlid, "srlid", rv_codec_i_sh6, rv_fmt_rd_rs1_imm)
> +OP(srliw, "srliw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm)
> +OP(srlw, "srlw", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(ssamoswap_d, "ssamoswap.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> +OP(ssamoswap_w, "ssamoswap.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> +OP(sspopchk, "sspopchk", rv_codec_r, rv_fmt_rs1)
> +OP(sspush, "sspush", rv_codec_r, rv_fmt_rs2)
> +OP(ssrdp, "ssrdp", rv_codec_r, rv_fmt_rd)
> +OP(sub, "sub", rv_codec_r, rv_fmt_rd_rs1_rs2, rvcp_sub)
> +OP(subd, "subd", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(subw, "subw", rv_codec_r, rv_fmt_rd_rs1_rs2, rvcp_subw)
> +OP(sw, "sw", rv_codec_s, rv_fmt_rs2_offset_rs1)
> OP(unzip, "unzip", rv_codec_r, rv_fmt_rd_rs1)
> -OP(zip, "zip", rv_codec_r, rv_fmt_rd_rs1)
> -OP(xperm4, "xperm4", rv_codec_r, rv_fmt_rd_rs1_rs2)
> -OP(xperm8, "xperm8", rv_codec_r, rv_fmt_rd_rs1)
> -OP(vle8_v, "vle8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
> -OP(vle16_v, "vle16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
> -OP(vle32_v, "vle32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
> -OP(vle64_v, "vle64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
> -OP(vse8_v, "vse8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
> -OP(vse16_v, "vse16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
> -OP(vse32_v, "vse32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
> -OP(vse64_v, "vse64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
> -OP(vlm_v, "vlm.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
> -OP(vsm_v, "vsm.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
> -OP(vlse8_v, "vlse8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm)
> -OP(vlse16_v, "vlse16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm)
> -OP(vlse32_v, "vlse32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm)
> -OP(vlse64_v, "vlse64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm)
> -OP(vsse8_v, "vsse8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm)
> -OP(vsse16_v, "vsse16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm)
> -OP(vsse32_v, "vsse32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm)
> -OP(vsse64_v, "vsse64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm)
> -OP(vluxei8_v, "vluxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm)
> -OP(vluxei16_v, "vluxei16.v", rv_codec_v_r,
> rv_fmt_ldst_vd_rs1_vs2_vm)
> -OP(vluxei32_v, "vluxei32.v", rv_codec_v_r,
> rv_fmt_ldst_vd_rs1_vs2_vm)
> -OP(vluxei64_v, "vluxei64.v", rv_codec_v_r,
> rv_fmt_ldst_vd_rs1_vs2_vm)
> -OP(vloxei8_v, "vloxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm)
> -OP(vloxei16_v, "vloxei16.v", rv_codec_v_r,
> rv_fmt_ldst_vd_rs1_vs2_vm)
> -OP(vloxei32_v, "vloxei32.v", rv_codec_v_r,
> rv_fmt_ldst_vd_rs1_vs2_vm)
> -OP(vloxei64_v, "vloxei64.v", rv_codec_v_r,
> rv_fmt_ldst_vd_rs1_vs2_vm)
> -OP(vsuxei8_v, "vsuxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm)
> -OP(vsuxei16_v, "vsuxei16.v", rv_codec_v_r,
> rv_fmt_ldst_vd_rs1_vs2_vm)
> -OP(vsuxei32_v, "vsuxei32.v", rv_codec_v_r,
> rv_fmt_ldst_vd_rs1_vs2_vm)
> -OP(vsuxei64_v, "vsuxei64.v", rv_codec_v_r,
> rv_fmt_ldst_vd_rs1_vs2_vm)
> -OP(vsoxei8_v, "vsoxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm)
> -OP(vsoxei16_v, "vsoxei16.v", rv_codec_v_r,
> rv_fmt_ldst_vd_rs1_vs2_vm)
> -OP(vsoxei32_v, "vsoxei32.v", rv_codec_v_r,
> rv_fmt_ldst_vd_rs1_vs2_vm)
> -OP(vsoxei64_v, "vsoxei64.v", rv_codec_v_r,
> rv_fmt_ldst_vd_rs1_vs2_vm)
> -OP(vle8ff_v, "vle8ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
> -OP(vle16ff_v, "vle16ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
> -OP(vle32ff_v, "vle32ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
> -OP(vle64ff_v, "vle64ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
> -OP(vl1re8_v, "vl1re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
> -OP(vl1re16_v, "vl1re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
> -OP(vl1re32_v, "vl1re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
> -OP(vl1re64_v, "vl1re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
> -OP(vl2re8_v, "vl2re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
> -OP(vl2re16_v, "vl2re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
> -OP(vl2re32_v, "vl2re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
> -OP(vl2re64_v, "vl2re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
> -OP(vl4re8_v, "vl4re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
> -OP(vl4re16_v, "vl4re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
> -OP(vl4re32_v, "vl4re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
> -OP(vl4re64_v, "vl4re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
> -OP(vl8re8_v, "vl8re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
> -OP(vl8re16_v, "vl8re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
> -OP(vl8re32_v, "vl8re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
> -OP(vl8re64_v, "vl8re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
> -OP(vs1r_v, "vs1r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
> -OP(vs2r_v, "vs2r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
> -OP(vs4r_v, "vs4r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
> -OP(vs8r_v, "vs8r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
> -OP(vadd_vv, "vadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> -OP(vadd_vx, "vadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> -OP(vadd_vi, "vadd.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm)
> -OP(vsub_vv, "vsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> -OP(vsub_vx, "vsub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> -OP(vrsub_vx, "vrsub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> -OP(vrsub_vi, "vrsub.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm)
> -OP(vwaddu_vv, "vwaddu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> -OP(vwaddu_vx, "vwaddu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> -OP(vwadd_vv, "vwadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> -OP(vwadd_vx, "vwadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> -OP(vwsubu_vv, "vwsubu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> -OP(vwsubu_vx, "vwsubu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> -OP(vwsub_vv, "vwsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> -OP(vwsub_vx, "vwsub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> -OP(vwaddu_wv, "vwaddu.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> -OP(vwaddu_wx, "vwaddu.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> -OP(vwadd_wv, "vwadd.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> -OP(vwadd_wx, "vwadd.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> -OP(vwsubu_wv, "vwsubu.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> -OP(vwsubu_wx, "vwsubu.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> -OP(vwsub_wv, "vwsub.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> -OP(vwsub_wx, "vwsub.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> -OP(vadc_vvm, "vadc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl)
> -OP(vadc_vxm, "vadc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl)
> -OP(vadc_vim, "vadc.vim", rv_codec_v_i, rv_fmt_vd_vs2_imm_vl)
> -OP(vmadc_vvm, "vmadc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl)
> -OP(vmadc_vxm, "vmadc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl)
> -OP(vmadc_vim, "vmadc.vim", rv_codec_v_i, rv_fmt_vd_vs2_imm_vl)
> -OP(vsbc_vvm, "vsbc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl)
> -OP(vsbc_vxm, "vsbc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl)
> -OP(vmsbc_vvm, "vmsbc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl)
> -OP(vmsbc_vxm, "vmsbc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl)
> -OP(vand_vv, "vand.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> -OP(vand_vx, "vand.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> -OP(vand_vi, "vand.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm)
> -OP(vor_vv, "vor.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> -OP(vor_vx, "vor.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> -OP(vor_vi, "vor.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm)
> -OP(vxor_vv, "vxor.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> -OP(vxor_vx, "vxor.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> -OP(vxor_vi, "vxor.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm)
> -OP(vsll_vv, "vsll.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> -OP(vsll_vx, "vsll.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> -OP(vsll_vi, "vsll.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm)
> -OP(vsrl_vv, "vsrl.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> -OP(vsrl_vx, "vsrl.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> -OP(vsrl_vi, "vsrl.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm)
> -OP(vsra_vv, "vsra.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> -OP(vsra_vx, "vsra.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> -OP(vsra_vi, "vsra.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm)
> -OP(vnsrl_wv, "vnsrl.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> -OP(vnsrl_wx, "vnsrl.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> -OP(vnsrl_wi, "vnsrl.wi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm)
> -OP(vnsra_wv, "vnsra.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> -OP(vnsra_wx, "vnsra.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> -OP(vnsra_wi, "vnsra.wi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm)
> -OP(vmseq_vv, "vmseq.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> -OP(vmseq_vx, "vmseq.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> -OP(vmseq_vi, "vmseq.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm)
> -OP(vmsne_vv, "vmsne.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> -OP(vmsne_vx, "vmsne.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> -OP(vmsne_vi, "vmsne.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm)
> -OP(vmsltu_vv, "vmsltu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> -OP(vmsltu_vx, "vmsltu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> -OP(vmslt_vv, "vmslt.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> -OP(vmslt_vx, "vmslt.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> -OP(vmsleu_vv, "vmsleu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> -OP(vmsleu_vx, "vmsleu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> -OP(vmsleu_vi, "vmsleu.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm)
> -OP(vmsle_vv, "vmsle.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> -OP(vmsle_vx, "vmsle.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> -OP(vmsle_vi, "vmsle.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm)
> -OP(vmsgtu_vx, "vmsgtu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> -OP(vmsgtu_vi, "vmsgtu.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm)
> -OP(vmsgt_vx, "vmsgt.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> -OP(vmsgt_vi, "vmsgt.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm)
> -OP(vminu_vv, "vminu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> -OP(vminu_vx, "vminu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> -OP(vmin_vv, "vmin.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> -OP(vmin_vx, "vmin.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> -OP(vmaxu_vv, "vmaxu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> -OP(vmaxu_vx, "vmaxu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> -OP(vmax_vv, "vmax.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> -OP(vmax_vx, "vmax.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> -OP(vmul_vv, "vmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> -OP(vmul_vx, "vmul.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> -OP(vmulh_vv, "vmulh.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> -OP(vmulh_vx, "vmulh.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> -OP(vmulhu_vv, "vmulhu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> -OP(vmulhu_vx, "vmulhu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> -OP(vmulhsu_vv, "vmulhsu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> -OP(vmulhsu_vx, "vmulhsu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> -OP(vdivu_vv, "vdivu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> -OP(vdivu_vx, "vdivu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> -OP(vdiv_vv, "vdiv.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> -OP(vdiv_vx, "vdiv.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> -OP(vremu_vv, "vremu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> -OP(vremu_vx, "vremu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> -OP(vrem_vv, "vrem.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> -OP(vrem_vx, "vrem.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> -OP(vwmulu_vv, "vwmulu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> -OP(vwmulu_vx, "vwmulu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> -OP(vwmulsu_vv, "vwmulsu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> -OP(vwmulsu_vx, "vwmulsu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> -OP(vwmul_vv, "vwmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> -OP(vwmul_vx, "vwmul.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> -OP(vmacc_vv, "vmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
> -OP(vmacc_vx, "vmacc.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm)
> -OP(vnmsac_vv, "vnmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
> -OP(vnmsac_vx, "vnmsac.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm)
> -OP(vmadd_vv, "vmadd.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
> -OP(vmadd_vx, "vmadd.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm)
> -OP(vnmsub_vv, "vnmsub.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
> -OP(vnmsub_vx, "vnmsub.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm)
> -OP(vwmaccu_vv, "vwmaccu.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
> -OP(vwmaccu_vx, "vwmaccu.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm)
> -OP(vwmacc_vv, "vwmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
> -OP(vwmacc_vx, "vwmacc.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm)
> -OP(vwmaccsu_vv, "vwmaccsu.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
> -OP(vwmaccsu_vx, "vwmaccsu.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm)
> -OP(vwmaccus_vx, "vwmaccus.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm)
> -OP(vmv_v_v, "vmv.v.v", rv_codec_v_r, rv_fmt_vd_vs1)
> -OP(vmv_v_x, "vmv.v.x", rv_codec_v_r, rv_fmt_vd_rs1)
> -OP(vmv_v_i, "vmv.v.i", rv_codec_v_i, rv_fmt_vd_imm)
> -OP(vmerge_vvm, "vmerge.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl)
> -OP(vmerge_vxm, "vmerge.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl)
> -OP(vmerge_vim, "vmerge.vim", rv_codec_v_i, rv_fmt_vd_vs2_imm_vl)
> -OP(vsaddu_vv, "vsaddu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> -OP(vsaddu_vx, "vsaddu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> -OP(vsaddu_vi, "vsaddu.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm)
> -OP(vsadd_vv, "vsadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> -OP(vsadd_vx, "vsadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> -OP(vsadd_vi, "vsadd.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm)
> -OP(vssubu_vv, "vssubu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> -OP(vssubu_vx, "vssubu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> -OP(vssub_vv, "vssub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> -OP(vssub_vx, "vssub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> +OP(uret, "uret", rv_codec_none, rv_fmt_none)
> OP(vaadd_vv, "vaadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> OP(vaadd_vx, "vaadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> OP(vaaddu_vv, "vaaddu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> OP(vaaddu_vx, "vaaddu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> +OP(vadc_vim, "vadc.vim", rv_codec_v_i, rv_fmt_vd_vs2_imm_vl)
> +OP(vadc_vvm, "vadc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl)
> +OP(vadc_vxm, "vadc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl)
> +OP(vadd_vi, "vadd.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm)
> +OP(vadd_vv, "vadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vadd_vx, "vadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> +OP(vaesdf_vs, "vaesdf.vs", rv_codec_v_r, rv_fmt_vd_vs2)
> +OP(vaesdf_vv, "vaesdf.vv", rv_codec_v_r, rv_fmt_vd_vs2)
> +OP(vaesdm_vs, "vaesdm.vs", rv_codec_v_r, rv_fmt_vd_vs2)
> +OP(vaesdm_vv, "vaesdm.vv", rv_codec_v_r, rv_fmt_vd_vs2)
> +OP(vaesef_vs, "vaesef.vs", rv_codec_v_r, rv_fmt_vd_vs2)
> +OP(vaesef_vv, "vaesef.vv", rv_codec_v_r, rv_fmt_vd_vs2)
> +OP(vaesem_vs, "vaesem.vs", rv_codec_v_r, rv_fmt_vd_vs2)
> +OP(vaesem_vv, "vaesem.vv", rv_codec_v_r, rv_fmt_vd_vs2)
> +OP(vaeskf1_vi, "vaeskf1.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm)
> +OP(vaeskf2_vi, "vaeskf2.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm)
> +OP(vaesz_vs, "vaesz.vs", rv_codec_v_r, rv_fmt_vd_vs2)
> +OP(vand_vi, "vand.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm)
> +OP(vand_vv, "vand.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vand_vx, "vand.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> +OP(vandn_vv, "vandn.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vandn_vx, "vandn.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> OP(vasub_vv, "vasub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> OP(vasub_vx, "vasub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> OP(vasubu_vv, "vasubu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> OP(vasubu_vx, "vasubu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> -OP(vsmul_vv, "vsmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> -OP(vsmul_vx, "vsmul.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> -OP(vssrl_vv, "vssrl.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> -OP(vssrl_vx, "vssrl.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> -OP(vssrl_vi, "vssrl.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm)
> -OP(vssra_vv, "vssra.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> -OP(vssra_vx, "vssra.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> -OP(vssra_vi, "vssra.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm)
> -OP(vnclipu_wv, "vnclipu.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> -OP(vnclipu_wx, "vnclipu.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> -OP(vnclipu_wi, "vnclipu.wi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm)
> -OP(vnclip_wv, "vnclip.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> -OP(vnclip_wx, "vnclip.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> -OP(vnclip_wi, "vnclip.wi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm)
> -OP(vfadd_vv, "vfadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> -OP(vfadd_vf, "vfadd.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
> -OP(vfsub_vv, "vfsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> -OP(vfsub_vf, "vfsub.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
> -OP(vfrsub_vf, "vfrsub.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
> -OP(vfwadd_vv, "vfwadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> -OP(vfwadd_vf, "vfwadd.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
> -OP(vfwadd_wv, "vfwadd.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> -OP(vfwadd_wf, "vfwadd.wf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
> -OP(vfwsub_vv, "vfwsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> -OP(vfwsub_vf, "vfwsub.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
> -OP(vfwsub_wv, "vfwsub.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> -OP(vfwsub_wf, "vfwsub.wf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
> -OP(vfmul_vv, "vfmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> -OP(vfmul_vf, "vfmul.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
> -OP(vfdiv_vv, "vfdiv.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> -OP(vfdiv_vf, "vfdiv.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
> -OP(vfrdiv_vf, "vfrdiv.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
> -OP(vfwmul_vv, "vfwmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> -OP(vfwmul_vf, "vfwmul.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
> -OP(vfmacc_vv, "vfmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
> -OP(vfmacc_vf, "vfmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm)
> -OP(vfnmacc_vv, "vfnmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
> -OP(vfnmacc_vf, "vfnmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm)
> -OP(vfmsac_vv, "vfmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
> -OP(vfmsac_vf, "vfmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm)
> -OP(vfnmsac_vv, "vfnmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
> -OP(vfnmsac_vf, "vfnmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm)
> -OP(vfmadd_vv, "vfmadd.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
> -OP(vfmadd_vf, "vfmadd.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm)
> -OP(vfnmadd_vv, "vfnmadd.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
> -OP(vfnmadd_vf, "vfnmadd.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm)
> -OP(vfmsub_vv, "vfmsub.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
> -OP(vfmsub_vf, "vfmsub.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm)
> -OP(vfnmsub_vv, "vfnmsub.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
> -OP(vfnmsub_vf, "vfnmsub.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm)
> -OP(vfwmacc_vv, "vfwmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
> -OP(vfwmacc_vf, "vfwmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm)
> -OP(vfwnmacc_vv, "vfwnmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
> -OP(vfwnmacc_vf, "vfwnmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm)
> -OP(vfwmsac_vv, "vfwmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
> -OP(vfwmsac_vf, "vfwmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm)
> -OP(vfwnmsac_vv, "vfwnmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
> -OP(vfwnmsac_vf, "vfwnmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm)
> -OP(vfsqrt_v, "vfsqrt.v", rv_codec_v_r, rv_fmt_vd_vs2)
> -OP(vfrsqrt7_v, "vfrsqrt7.v", rv_codec_v_r, rv_fmt_vd_vs2)
> -OP(vfrec7_v, "vfrec7.v", rv_codec_v_r, rv_fmt_vd_vs2)
> -OP(vfmin_vv, "vfmin.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> -OP(vfmin_vf, "vfmin.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
> -OP(vfmax_vv, "vfmax.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> -OP(vfmax_vf, "vfmax.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
> -OP(vfsgnj_vv, "vfsgnj.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> -OP(vfsgnj_vf, "vfsgnj.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
> -OP(vfsgnjn_vv, "vfsgnjn.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> -OP(vfsgnjn_vf, "vfsgnjn.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
> -OP(vfsgnjx_vv, "vfsgnjx.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> -OP(vfsgnjx_vf, "vfsgnjx.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
> -OP(vfslide1up_vf, "vfslide1up.vf", rv_codec_v_r,
> rv_fmt_vd_vs2_fs1_vm)
> -OP(vfslide1down_vf, "vfslide1down.vf", rv_codec_v_r,
> rv_fmt_vd_vs2_fs1_vm)
> -OP(vmfeq_vv, "vmfeq.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> -OP(vmfeq_vf, "vmfeq.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
> -OP(vmfne_vv, "vmfne.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> -OP(vmfne_vf, "vmfne.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
> -OP(vmflt_vv, "vmflt.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> -OP(vmflt_vf, "vmflt.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
> -OP(vmfle_vv, "vmfle.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> -OP(vmfle_vf, "vmfle.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
> -OP(vmfgt_vf, "vmfgt.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
> -OP(vmfge_vf, "vmfge.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
> -OP(vfclass_v, "vfclass.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
> -OP(vfmerge_vfm, "vfmerge.vfm", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vl)
> -OP(vfmv_v_f, "vfmv.v.f", rv_codec_v_r, rv_fmt_vd_fs1)
> -OP(vfcvt_xu_f_v, "vfcvt.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
> -OP(vfcvt_x_f_v, "vfcvt.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
> -OP(vfcvt_f_xu_v, "vfcvt.f.xu.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
> -OP(vfcvt_f_x_v, "vfcvt.f.x.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
> -OP(vfcvt_rtz_xu_f_v, "vfcvt.rtz.xu.f.v", rv_codec_v_r,
> rv_fmt_vd_vs2_vm)
> -OP(vfcvt_rtz_x_f_v, "vfcvt.rtz.x.f.v", rv_codec_v_r,
> rv_fmt_vd_vs2_vm)
> -OP(vfwcvt_xu_f_v, "vfwcvt.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
> -OP(vfwcvt_x_f_v, "vfwcvt.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
> -OP(vfwcvt_f_xu_v, "vfwcvt.f.xu.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
> -OP(vfwcvt_f_x_v, "vfwcvt.f.x.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
> -OP(vfwcvt_f_f_v, "vfwcvt.f.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
> -OP(vfwcvt_rtz_xu_f_v, "vfwcvt.rtz.xu.f.v", rv_codec_v_r,
> rv_fmt_vd_vs2_vm)
> -OP(vfwcvt_rtz_x_f_v, "vfwcvt.rtz.x.f.v", rv_codec_v_r,
> rv_fmt_vd_vs2_vm)
> -OP(vfncvt_xu_f_w, "vfncvt.xu.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm)
> -OP(vfncvt_x_f_w, "vfncvt.x.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm)
> -OP(vfncvt_f_xu_w, "vfncvt.f.xu.w", rv_codec_v_r, rv_fmt_vd_vs2_vm)
> -OP(vfncvt_f_x_w, "vfncvt.f.x.w", rv_codec_v_r, rv_fmt_vd_vs2_vm)
> -OP(vfncvt_f_f_w, "vfncvt.f.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm)
> -OP(vfncvt_rod_f_f_w, "vfncvt.rod.f.f.w", rv_codec_v_r,
> rv_fmt_vd_vs2_vm)
> -OP(vfncvt_rtz_xu_f_w, "vfncvt.rtz.xu.f.w", rv_codec_v_r,
> rv_fmt_vd_vs2_vm)
> -OP(vfncvt_rtz_x_f_w, "vfncvt.rtz.x.f.w", rv_codec_v_r,
> rv_fmt_vd_vs2_vm)
> -OP(vredsum_vs, "vredsum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> -OP(vredand_vs, "vredand.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> -OP(vredor_vs, "vredor.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> -OP(vredxor_vs, "vredxor.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> -OP(vredminu_vs, "vredminu.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> -OP(vredmin_vs, "vredmin.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> -OP(vredmaxu_vs, "vredmaxu.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> -OP(vredmax_vs, "vredmax.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> -OP(vwredsumu_vs, "vwredsumu.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> -OP(vwredsum_vs, "vwredsum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> -OP(vfredusum_vs, "vfredusum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> -OP(vfredosum_vs, "vfredosum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> -OP(vfredmin_vs, "vfredmin.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> -OP(vfredmax_vs, "vfredmax.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> -OP(vfwredusum_vs, "vfwredusum.vs", rv_codec_v_r,
> rv_fmt_vd_vs2_vs1_vm)
> -OP(vfwredosum_vs, "vfwredosum.vs", rv_codec_v_r,
> rv_fmt_vd_vs2_vs1_vm)
> -OP(vmand_mm, "vmand.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> -OP(vmnand_mm, "vmnand.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> -OP(vmandn_mm, "vmandn.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> -OP(vmxor_mm, "vmxor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> -OP(vmor_mm, "vmor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> -OP(vmnor_mm, "vmnor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> -OP(vmorn_mm, "vmorn.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> -OP(vmxnor_mm, "vmxnor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> -OP(vcpop_m, "vcpop.m", rv_codec_v_r, rv_fmt_rd_vs2_vm)
> -OP(vfirst_m, "vfirst.m", rv_codec_v_r, rv_fmt_rd_vs2_vm)
> -OP(vmsbf_m, "vmsbf.m", rv_codec_v_r, rv_fmt_vd_vs2_vm)
> -OP(vmsif_m, "vmsif.m", rv_codec_v_r, rv_fmt_vd_vs2_vm)
> -OP(vmsof_m, "vmsof.m", rv_codec_v_r, rv_fmt_vd_vs2_vm)
> -OP(viota_m, "viota.m", rv_codec_v_r, rv_fmt_vd_vs2_vm)
> -OP(vid_v, "vid.v", rv_codec_v_r, rv_fmt_vd_vm)
> -OP(vmv_x_s, "vmv.x.s", rv_codec_v_r, rv_fmt_rd_vs2)
> -OP(vmv_s_x, "vmv.s.x", rv_codec_v_r, rv_fmt_vd_rs1)
> -OP(vfmv_f_s, "vfmv.f.s", rv_codec_v_r, rv_fmt_fd_vs2)
> -OP(vfmv_s_f, "vfmv.s.f", rv_codec_v_r, rv_fmt_vd_fs1)
> -OP(vslideup_vx, "vslideup.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> -OP(vslideup_vi, "vslideup.vi", rv_codec_v_i_u,
> rv_fmt_vd_vs2_uimm_vm)
> -OP(vslide1up_vx, "vslide1up.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> -OP(vslidedown_vx, "vslidedown.vx", rv_codec_v_r,
> rv_fmt_vd_vs2_rs1_vm)
> -OP(vslidedown_vi, "vslidedown.vi", rv_codec_v_i_u,
> rv_fmt_vd_vs2_uimm_vm)
> -OP(vslide1down_vx, "vslide1down.vx", rv_codec_v_r,
> rv_fmt_vd_vs2_rs1_vm)
> -OP(vrgather_vv, "vrgather.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> -OP(vrgatherei16_vv, "vrgatherei16.vv", rv_codec_v_r,
> rv_fmt_vd_vs2_vs1_vm)
> -OP(vrgather_vx, "vrgather.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> -OP(vrgather_vi, "vrgather.vi", rv_codec_v_i_u,
> rv_fmt_vd_vs2_uimm_vm)
> -OP(vcompress_vm, "vcompress.vm", rv_codec_v_r, rv_fmt_vd_vs2_vs1)
> -OP(vmv1r_v, "vmv1r.v", rv_codec_v_r, rv_fmt_vd_vs2)
> -OP(vmv2r_v, "vmv2r.v", rv_codec_v_r, rv_fmt_vd_vs2)
> -OP(vmv4r_v, "vmv4r.v", rv_codec_v_r, rv_fmt_vd_vs2)
> -OP(vmv8r_v, "vmv8r.v", rv_codec_v_r, rv_fmt_vd_vs2)
> -OP(vzext_vf2, "vzext.vf2", rv_codec_v_r, rv_fmt_vd_vs2_vm)
> -OP(vzext_vf4, "vzext.vf4", rv_codec_v_r, rv_fmt_vd_vs2_vm)
> -OP(vzext_vf8, "vzext.vf8", rv_codec_v_r, rv_fmt_vd_vs2_vm)
> -OP(vsext_vf2, "vsext.vf2", rv_codec_v_r, rv_fmt_vd_vs2_vm)
> -OP(vsext_vf4, "vsext.vf4", rv_codec_v_r, rv_fmt_vd_vs2_vm)
> -OP(vsext_vf8, "vsext.vf8", rv_codec_v_r, rv_fmt_vd_vs2_vm)
> -OP(vsetvli, "vsetvli", rv_codec_vsetvli, rv_fmt_vsetvli)
> -OP(vsetivli, "vsetivli", rv_codec_vsetivli, rv_fmt_vsetivli)
> -OP(vsetvl, "vsetvl", rv_codec_r, rv_fmt_rd_rs1_rs2)
> -OP(c_zext_b, "c.zext.b", rv_codec_zcb_ext, rv_fmt_rd)
> -OP(c_sext_b, "c.sext.b", rv_codec_zcb_ext, rv_fmt_rd)
> -OP(c_zext_h, "c.zext.h", rv_codec_zcb_ext, rv_fmt_rd)
> -OP(c_sext_h, "c.sext.h", rv_codec_zcb_ext, rv_fmt_rd)
> -OP(c_zext_w, "c.zext.w", rv_codec_zcb_ext, rv_fmt_rd)
> -OP(c_not, "c.not", rv_codec_zcb_ext, rv_fmt_rd)
> -OP(c_mul, "c.mul", rv_codec_zcb_mul, rv_fmt_rd_rs2)
> -OP(c_lbu, "c.lbu", rv_codec_zcb_lb, rv_fmt_rs1_rs2_zce_ldst)
> -OP(c_lhu, "c.lhu", rv_codec_zcb_lh, rv_fmt_rs1_rs2_zce_ldst)
> -OP(c_lh, "c.lh", rv_codec_zcb_lh, rv_fmt_rs1_rs2_zce_ldst)
> -OP(c_sb, "c.sb", rv_codec_zcb_lb, rv_fmt_rs1_rs2_zce_ldst)
> -OP(c_sh, "c.sh", rv_codec_zcb_lh, rv_fmt_rs1_rs2_zce_ldst)
> -OP(cm_push, "cm.push", rv_codec_zcmp_cm_pushpop, rv_fmt_push_rlist)
> -OP(cm_pop, "cm.pop", rv_codec_zcmp_cm_pushpop, rv_fmt_pop_rlist)
> -OP(cm_popret, "cm.popret", rv_codec_zcmp_cm_pushpop,
> rv_fmt_pop_rlist)
> -OP(cm_popretz, "cm.popretz", rv_codec_zcmp_cm_pushpop,
> rv_fmt_pop_rlist)
> -OP(cm_mva01s, "cm.mva01s", rv_codec_zcmp_cm_mv, rv_fmt_rd_rs2)
> -OP(cm_mvsa01, "cm.mvsa01", rv_codec_zcmp_cm_mv, rv_fmt_rd_rs2)
> -OP(cm_jt, "cm.jt", rv_codec_zcmt_jt, rv_fmt_zcmt_index)
> -OP(cm_jalt, "cm.jalt", rv_codec_zcmt_jt, rv_fmt_zcmt_index)
> -OP(czero_eqz, "czero.eqz", rv_codec_r, rv_fmt_rd_rs1_rs2)
> -OP(czero_nez, "czero.nez", rv_codec_r, rv_fmt_rd_rs1_rs2)
> -OP(fcvt_bf16_s, "fcvt.bf16.s", rv_codec_r_m, rv_fmt_rm_frd_frs1)
> -OP(fcvt_s_bf16, "fcvt.s.bf16", rv_codec_r_m, rv_fmt_rm_frd_frs1)
> -OP(vfncvtbf16_f_f_w, "vfncvtbf16.f.f.w", rv_codec_v_r,
> rv_fmt_vd_vs2_vm)
> -OP(vfwcvtbf16_f_f_v, "vfwcvtbf16.f.f.v", rv_codec_v_r,
> rv_fmt_vd_vs2_vm)
> -OP(vfwmaccbf16_vv, "vfwmaccbf16.vv", rv_codec_v_r,
> rv_fmt_vd_vs1_vs2_vm)
> -OP(vfwmaccbf16_vf, "vfwmaccbf16.vf", rv_codec_v_r,
> rv_fmt_vd_fs1_vs2_vm)
> -OP(flh, "flh", rv_codec_i, rv_fmt_frd_offset_rs1)
> -OP(fsh, "fsh", rv_codec_s, rv_fmt_frs2_offset_rs1)
> -OP(fmv_h_x, "fmv.h.x", rv_codec_r, rv_fmt_frd_rs1)
> -OP(fmv_x_h, "fmv.x.h", rv_codec_r, rv_fmt_rd_frs1)
> -OP(fli_s, "fli.s", rv_codec_fli, rv_fmt_fli)
> -OP(fli_d, "fli.d", rv_codec_fli, rv_fmt_fli)
> -OP(fli_q, "fli.q", rv_codec_fli, rv_fmt_fli)
> -OP(fli_h, "fli.h", rv_codec_fli, rv_fmt_fli)
> -OP(fminm_s, "fminm.s", rv_codec_r, rv_fmt_frd_frs1_frs2)
> -OP(fmaxm_s, "fmaxm.s", rv_codec_r, rv_fmt_frd_frs1_frs2)
> -OP(fminm_d, "fminm.d", rv_codec_r, rv_fmt_frd_frs1_frs2)
> -OP(fmaxm_d, "fmaxm.d", rv_codec_r, rv_fmt_frd_frs1_frs2)
> -OP(fminm_q, "fminm.q", rv_codec_r, rv_fmt_frd_frs1_frs2)
> -OP(fmaxm_q, "fmaxm.q", rv_codec_r, rv_fmt_frd_frs1_frs2)
> -OP(fminm_h, "fminm.h", rv_codec_r, rv_fmt_frd_frs1_frs2)
> -OP(fmaxm_h, "fmaxm.h", rv_codec_r, rv_fmt_frd_frs1_frs2)
> -OP(fround_s, "fround.s", rv_codec_r_m, rv_fmt_rm_frd_frs1)
> -OP(froundnx_s, "froundnx.s", rv_codec_r_m, rv_fmt_rm_frd_frs1)
> -OP(fround_d, "fround.d", rv_codec_r_m, rv_fmt_rm_frd_frs1)
> -OP(froundnx_d, "froundnx.d", rv_codec_r_m, rv_fmt_rm_frd_frs1)
> -OP(fround_q, "fround.q", rv_codec_r_m, rv_fmt_rm_frd_frs1)
> -OP(froundnx_q, "froundnx.q", rv_codec_r_m, rv_fmt_rm_frd_frs1)
> -OP(fround_h, "fround.h", rv_codec_r_m, rv_fmt_rm_frd_frs1)
> -OP(froundnx_h, "froundnx.h", rv_codec_r_m, rv_fmt_rm_frd_frs1)
> -OP(fcvtmod_w_d, "fcvtmod.w.d", rv_codec_r_m, rv_fmt_rm_rd_frs1)
> -OP(fmvh_x_d, "fmvh.x.d", rv_codec_r, rv_fmt_rd_frs1)
> -OP(fmvp_d_x, "fmvp.d.x", rv_codec_r, rv_fmt_frd_rs1_rs2)
> -OP(fmvh_x_q, "fmvh.x.q", rv_codec_r, rv_fmt_rd_frs1)
> -OP(fmvp_q_x, "fmvp.q.x", rv_codec_r, rv_fmt_frd_rs1_rs2)
> -OP(fleq_s, "fleq.s", rv_codec_r, rv_fmt_rd_frs1_frs2)
> -OP(fltq_s, "fltq.s", rv_codec_r, rv_fmt_rd_frs1_frs2)
> -OP(fleq_d, "fleq.d", rv_codec_r, rv_fmt_rd_frs1_frs2)
> -OP(fltq_d, "fltq.d", rv_codec_r, rv_fmt_rd_frs1_frs2)
> -OP(fleq_q, "fleq.q", rv_codec_r, rv_fmt_rd_frs1_frs2)
> -OP(fltq_q, "fltq.q", rv_codec_r, rv_fmt_rd_frs1_frs2)
> -OP(fleq_h, "fleq.h", rv_codec_r, rv_fmt_rd_frs1_frs2)
> -OP(fltq_h, "fltq.h", rv_codec_r, rv_fmt_rd_frs1_frs2)
> -OP(vaesdf_vv, "vaesdf.vv", rv_codec_v_r, rv_fmt_vd_vs2)
> -OP(vaesdf_vs, "vaesdf.vs", rv_codec_v_r, rv_fmt_vd_vs2)
> -OP(vaesdm_vv, "vaesdm.vv", rv_codec_v_r, rv_fmt_vd_vs2)
> -OP(vaesdm_vs, "vaesdm.vs", rv_codec_v_r, rv_fmt_vd_vs2)
> -OP(vaesef_vv, "vaesef.vv", rv_codec_v_r, rv_fmt_vd_vs2)
> -OP(vaesef_vs, "vaesef.vs", rv_codec_v_r, rv_fmt_vd_vs2)
> -OP(vaesem_vv, "vaesem.vv", rv_codec_v_r, rv_fmt_vd_vs2)
> -OP(vaesem_vs, "vaesem.vs", rv_codec_v_r, rv_fmt_vd_vs2)
> -OP(vaeskf1_vi, "vaeskf1.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm)
> -OP(vaeskf2_vi, "vaeskf2.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm)
> -OP(vaesz_vs, "vaesz.vs", rv_codec_v_r, rv_fmt_vd_vs2)
> -OP(vandn_vv, "vandn.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> -OP(vandn_vx, "vandn.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> -OP(vbrev_v, "vbrev.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
> OP(vbrev8_v, "vbrev8.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
> +OP(vbrev_v, "vbrev.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
> OP(vclmul_vv, "vclmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> OP(vclmul_vx, "vclmul.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> OP(vclmulh_vv, "vclmulh.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> OP(vclmulh_vx, "vclmulh.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> OP(vclz_v, "vclz.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
> +OP(vcompress_vm, "vcompress.vm", rv_codec_v_r, rv_fmt_vd_vs2_vs1)
> +OP(vcpop_m, "vcpop.m", rv_codec_v_r, rv_fmt_rd_vs2_vm)
> OP(vcpop_v, "vcpop.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
> OP(vctz_v, "vctz.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
> +OP(vdiv_vv, "vdiv.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vdiv_vx, "vdiv.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> +OP(vdivu_vv, "vdivu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vdivu_vx, "vdivu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> +OP(vfadd_vf, "vfadd.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
> +OP(vfadd_vv, "vfadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vfclass_v, "vfclass.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
> +OP(vfcvt_f_x_v, "vfcvt.f.x.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
> +OP(vfcvt_f_xu_v, "vfcvt.f.xu.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
> +OP(vfcvt_rtz_x_f_v, "vfcvt.rtz.x.f.v", rv_codec_v_r,
> rv_fmt_vd_vs2_vm)
> +OP(vfcvt_rtz_xu_f_v, "vfcvt.rtz.xu.f.v", rv_codec_v_r,
> rv_fmt_vd_vs2_vm)
> +OP(vfcvt_x_f_v, "vfcvt.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
> +OP(vfcvt_xu_f_v, "vfcvt.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
> +OP(vfdiv_vf, "vfdiv.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
> +OP(vfdiv_vv, "vfdiv.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vfirst_m, "vfirst.m", rv_codec_v_r, rv_fmt_rd_vs2_vm)
> +OP(vfmacc_vf, "vfmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm)
> +OP(vfmacc_vv, "vfmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
> +OP(vfmadd_vf, "vfmadd.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm)
> +OP(vfmadd_vv, "vfmadd.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
> +OP(vfmax_vf, "vfmax.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
> +OP(vfmax_vv, "vfmax.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vfmerge_vfm, "vfmerge.vfm", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vl)
> +OP(vfmin_vf, "vfmin.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
> +OP(vfmin_vv, "vfmin.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vfmsac_vf, "vfmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm)
> +OP(vfmsac_vv, "vfmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
> +OP(vfmsub_vf, "vfmsub.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm)
> +OP(vfmsub_vv, "vfmsub.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
> +OP(vfmul_vf, "vfmul.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
> +OP(vfmul_vv, "vfmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vfmv_f_s, "vfmv.f.s", rv_codec_v_r, rv_fmt_fd_vs2)
> +OP(vfmv_s_f, "vfmv.s.f", rv_codec_v_r, rv_fmt_vd_fs1)
> +OP(vfmv_v_f, "vfmv.v.f", rv_codec_v_r, rv_fmt_vd_fs1)
> +OP(vfncvt_f_f_w, "vfncvt.f.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm)
> +OP(vfncvt_f_x_w, "vfncvt.f.x.w", rv_codec_v_r, rv_fmt_vd_vs2_vm)
> +OP(vfncvt_f_xu_w, "vfncvt.f.xu.w", rv_codec_v_r, rv_fmt_vd_vs2_vm)
> +OP(vfncvt_rod_f_f_w, "vfncvt.rod.f.f.w", rv_codec_v_r,
> rv_fmt_vd_vs2_vm)
> +OP(vfncvt_rtz_x_f_w, "vfncvt.rtz.x.f.w", rv_codec_v_r,
> rv_fmt_vd_vs2_vm)
> +OP(vfncvt_rtz_xu_f_w, "vfncvt.rtz.xu.f.w", rv_codec_v_r,
> rv_fmt_vd_vs2_vm)
> +OP(vfncvt_x_f_w, "vfncvt.x.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm)
> +OP(vfncvt_xu_f_w, "vfncvt.xu.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm)
> +OP(vfncvtbf16_f_f_w, "vfncvtbf16.f.f.w", rv_codec_v_r,
> rv_fmt_vd_vs2_vm)
> +OP(vfnmacc_vf, "vfnmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm)
> +OP(vfnmacc_vv, "vfnmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
> +OP(vfnmadd_vf, "vfnmadd.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm)
> +OP(vfnmadd_vv, "vfnmadd.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
> +OP(vfnmsac_vf, "vfnmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm)
> +OP(vfnmsac_vv, "vfnmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
> +OP(vfnmsub_vf, "vfnmsub.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm)
> +OP(vfnmsub_vv, "vfnmsub.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
> +OP(vfrdiv_vf, "vfrdiv.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
> +OP(vfrec7_v, "vfrec7.v", rv_codec_v_r, rv_fmt_vd_vs2)
> +OP(vfredmax_vs, "vfredmax.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vfredmin_vs, "vfredmin.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vfredosum_vs, "vfredosum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vfredusum_vs, "vfredusum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vfrsqrt7_v, "vfrsqrt7.v", rv_codec_v_r, rv_fmt_vd_vs2)
> +OP(vfrsub_vf, "vfrsub.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
> +OP(vfsgnj_vf, "vfsgnj.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
> +OP(vfsgnj_vv, "vfsgnj.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vfsgnjn_vf, "vfsgnjn.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
> +OP(vfsgnjn_vv, "vfsgnjn.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vfsgnjx_vf, "vfsgnjx.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
> +OP(vfsgnjx_vv, "vfsgnjx.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vfslide1down_vf, "vfslide1down.vf", rv_codec_v_r,
> rv_fmt_vd_vs2_fs1_vm)
> +OP(vfslide1up_vf, "vfslide1up.vf", rv_codec_v_r,
> rv_fmt_vd_vs2_fs1_vm)
> +OP(vfsqrt_v, "vfsqrt.v", rv_codec_v_r, rv_fmt_vd_vs2)
> +OP(vfsub_vf, "vfsub.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
> +OP(vfsub_vv, "vfsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vfwadd_vf, "vfwadd.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
> +OP(vfwadd_vv, "vfwadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vfwadd_wf, "vfwadd.wf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
> +OP(vfwadd_wv, "vfwadd.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vfwcvt_f_f_v, "vfwcvt.f.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
> +OP(vfwcvt_f_x_v, "vfwcvt.f.x.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
> +OP(vfwcvt_f_xu_v, "vfwcvt.f.xu.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
> +OP(vfwcvt_rtz_x_f_v, "vfwcvt.rtz.x.f.v", rv_codec_v_r,
> rv_fmt_vd_vs2_vm)
> +OP(vfwcvt_rtz_xu_f_v, "vfwcvt.rtz.xu.f.v", rv_codec_v_r,
> rv_fmt_vd_vs2_vm)
> +OP(vfwcvt_x_f_v, "vfwcvt.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
> +OP(vfwcvt_xu_f_v, "vfwcvt.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
> +OP(vfwcvtbf16_f_f_v, "vfwcvtbf16.f.f.v", rv_codec_v_r,
> rv_fmt_vd_vs2_vm)
> +OP(vfwmacc_vf, "vfwmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm)
> +OP(vfwmacc_vv, "vfwmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
> +OP(vfwmaccbf16_vf, "vfwmaccbf16.vf", rv_codec_v_r,
> rv_fmt_vd_fs1_vs2_vm)
> +OP(vfwmaccbf16_vv, "vfwmaccbf16.vv", rv_codec_v_r,
> rv_fmt_vd_vs1_vs2_vm)
> +OP(vfwmsac_vf, "vfwmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm)
> +OP(vfwmsac_vv, "vfwmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
> +OP(vfwmul_vf, "vfwmul.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
> +OP(vfwmul_vv, "vfwmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vfwnmacc_vf, "vfwnmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm)
> +OP(vfwnmacc_vv, "vfwnmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
> +OP(vfwnmsac_vf, "vfwnmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm)
> +OP(vfwnmsac_vv, "vfwnmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
> +OP(vfwredosum_vs, "vfwredosum.vs", rv_codec_v_r,
> rv_fmt_vd_vs2_vs1_vm)
> +OP(vfwredusum_vs, "vfwredusum.vs", rv_codec_v_r,
> rv_fmt_vd_vs2_vs1_vm)
> +OP(vfwsub_vf, "vfwsub.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
> +OP(vfwsub_vv, "vfwsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vfwsub_wf, "vfwsub.wf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
> +OP(vfwsub_wv, "vfwsub.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> OP(vghsh_vv, "vghsh.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1)
> OP(vgmul_vv, "vgmul.vv", rv_codec_v_r, rv_fmt_vd_vs2)
> +OP(vid_v, "vid.v", rv_codec_v_r, rv_fmt_vd_vm)
> +OP(viota_m, "viota.m", rv_codec_v_r, rv_fmt_vd_vs2_vm)
> +OP(vl1re16_v, "vl1re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
> +OP(vl1re32_v, "vl1re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
> +OP(vl1re64_v, "vl1re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
> +OP(vl1re8_v, "vl1re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
> +OP(vl2re16_v, "vl2re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
> +OP(vl2re32_v, "vl2re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
> +OP(vl2re64_v, "vl2re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
> +OP(vl2re8_v, "vl2re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
> +OP(vl4re16_v, "vl4re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
> +OP(vl4re32_v, "vl4re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
> +OP(vl4re64_v, "vl4re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
> +OP(vl4re8_v, "vl4re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
> +OP(vl8re16_v, "vl8re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
> +OP(vl8re32_v, "vl8re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
> +OP(vl8re64_v, "vl8re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
> +OP(vl8re8_v, "vl8re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
> +OP(vle16_v, "vle16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
> +OP(vle16ff_v, "vle16ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
> +OP(vle32_v, "vle32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
> +OP(vle32ff_v, "vle32ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
> +OP(vle64_v, "vle64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
> +OP(vle64ff_v, "vle64ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
> +OP(vle8_v, "vle8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
> +OP(vle8ff_v, "vle8ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
> +OP(vlm_v, "vlm.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
> +OP(vloxei16_v, "vloxei16.v", rv_codec_v_r,
> rv_fmt_ldst_vd_rs1_vs2_vm)
> +OP(vloxei32_v, "vloxei32.v", rv_codec_v_r,
> rv_fmt_ldst_vd_rs1_vs2_vm)
> +OP(vloxei64_v, "vloxei64.v", rv_codec_v_r,
> rv_fmt_ldst_vd_rs1_vs2_vm)
> +OP(vloxei8_v, "vloxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm)
> +OP(vlse16_v, "vlse16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm)
> +OP(vlse32_v, "vlse32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm)
> +OP(vlse64_v, "vlse64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm)
> +OP(vlse8_v, "vlse8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm)
> +OP(vluxei16_v, "vluxei16.v", rv_codec_v_r,
> rv_fmt_ldst_vd_rs1_vs2_vm)
> +OP(vluxei32_v, "vluxei32.v", rv_codec_v_r,
> rv_fmt_ldst_vd_rs1_vs2_vm)
> +OP(vluxei64_v, "vluxei64.v", rv_codec_v_r,
> rv_fmt_ldst_vd_rs1_vs2_vm)
> +OP(vluxei8_v, "vluxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm)
> +OP(vmacc_vv, "vmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
> +OP(vmacc_vx, "vmacc.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm)
> +OP(vmadc_vim, "vmadc.vim", rv_codec_v_i, rv_fmt_vd_vs2_imm_vl)
> +OP(vmadc_vvm, "vmadc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl)
> +OP(vmadc_vxm, "vmadc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl)
> +OP(vmadd_vv, "vmadd.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
> +OP(vmadd_vx, "vmadd.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm)
> +OP(vmand_mm, "vmand.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vmandn_mm, "vmandn.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vmax_vv, "vmax.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vmax_vx, "vmax.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> +OP(vmaxu_vv, "vmaxu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vmaxu_vx, "vmaxu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> +OP(vmerge_vim, "vmerge.vim", rv_codec_v_i, rv_fmt_vd_vs2_imm_vl)
> +OP(vmerge_vvm, "vmerge.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl)
> +OP(vmerge_vxm, "vmerge.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl)
> +OP(vmfeq_vf, "vmfeq.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
> +OP(vmfeq_vv, "vmfeq.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vmfge_vf, "vmfge.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
> +OP(vmfgt_vf, "vmfgt.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
> +OP(vmfle_vf, "vmfle.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
> +OP(vmfle_vv, "vmfle.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vmflt_vf, "vmflt.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
> +OP(vmflt_vv, "vmflt.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vmfne_vf, "vmfne.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
> +OP(vmfne_vv, "vmfne.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vmin_vv, "vmin.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vmin_vx, "vmin.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> +OP(vminu_vv, "vminu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vminu_vx, "vminu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> +OP(vmnand_mm, "vmnand.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vmnor_mm, "vmnor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vmor_mm, "vmor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vmorn_mm, "vmorn.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vmsbc_vvm, "vmsbc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl)
> +OP(vmsbc_vxm, "vmsbc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl)
> +OP(vmsbf_m, "vmsbf.m", rv_codec_v_r, rv_fmt_vd_vs2_vm)
> +OP(vmseq_vi, "vmseq.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm)
> +OP(vmseq_vv, "vmseq.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vmseq_vx, "vmseq.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> +OP(vmsgt_vi, "vmsgt.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm)
> +OP(vmsgt_vx, "vmsgt.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> +OP(vmsgtu_vi, "vmsgtu.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm)
> +OP(vmsgtu_vx, "vmsgtu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> +OP(vmsif_m, "vmsif.m", rv_codec_v_r, rv_fmt_vd_vs2_vm)
> +OP(vmsle_vi, "vmsle.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm)
> +OP(vmsle_vv, "vmsle.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vmsle_vx, "vmsle.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> +OP(vmsleu_vi, "vmsleu.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm)
> +OP(vmsleu_vv, "vmsleu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vmsleu_vx, "vmsleu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> +OP(vmslt_vv, "vmslt.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vmslt_vx, "vmslt.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> +OP(vmsltu_vv, "vmsltu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vmsltu_vx, "vmsltu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> +OP(vmsne_vi, "vmsne.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm)
> +OP(vmsne_vv, "vmsne.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vmsne_vx, "vmsne.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> +OP(vmsof_m, "vmsof.m", rv_codec_v_r, rv_fmt_vd_vs2_vm)
> +OP(vmul_vv, "vmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vmul_vx, "vmul.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> +OP(vmulh_vv, "vmulh.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vmulh_vx, "vmulh.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> +OP(vmulhsu_vv, "vmulhsu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vmulhsu_vx, "vmulhsu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> +OP(vmulhu_vv, "vmulhu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vmulhu_vx, "vmulhu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> +OP(vmv1r_v, "vmv1r.v", rv_codec_v_r, rv_fmt_vd_vs2)
> +OP(vmv2r_v, "vmv2r.v", rv_codec_v_r, rv_fmt_vd_vs2)
> +OP(vmv4r_v, "vmv4r.v", rv_codec_v_r, rv_fmt_vd_vs2)
> +OP(vmv8r_v, "vmv8r.v", rv_codec_v_r, rv_fmt_vd_vs2)
> +OP(vmv_s_x, "vmv.s.x", rv_codec_v_r, rv_fmt_vd_rs1)
> +OP(vmv_v_i, "vmv.v.i", rv_codec_v_i, rv_fmt_vd_imm)
> +OP(vmv_v_v, "vmv.v.v", rv_codec_v_r, rv_fmt_vd_vs1)
> +OP(vmv_v_x, "vmv.v.x", rv_codec_v_r, rv_fmt_vd_rs1)
> +OP(vmv_x_s, "vmv.x.s", rv_codec_v_r, rv_fmt_rd_vs2)
> +OP(vmxnor_mm, "vmxnor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vmxor_mm, "vmxor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vnclip_wi, "vnclip.wi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm)
> +OP(vnclip_wv, "vnclip.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vnclip_wx, "vnclip.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> +OP(vnclipu_wi, "vnclipu.wi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm)
> +OP(vnclipu_wv, "vnclipu.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vnclipu_wx, "vnclipu.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> +OP(vnmsac_vv, "vnmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
> +OP(vnmsac_vx, "vnmsac.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm)
> +OP(vnmsub_vv, "vnmsub.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
> +OP(vnmsub_vx, "vnmsub.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm)
> +OP(vnsra_wi, "vnsra.wi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm)
> +OP(vnsra_wv, "vnsra.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vnsra_wx, "vnsra.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> +OP(vnsrl_wi, "vnsrl.wi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm)
> +OP(vnsrl_wv, "vnsrl.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vnsrl_wx, "vnsrl.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> +OP(vor_vi, "vor.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm)
> +OP(vor_vv, "vor.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vor_vx, "vor.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> +OP(vredand_vs, "vredand.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vredmax_vs, "vredmax.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vredmaxu_vs, "vredmaxu.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vredmin_vs, "vredmin.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vredminu_vs, "vredminu.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vredor_vs, "vredor.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vredsum_vs, "vredsum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vredxor_vs, "vredxor.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vrem_vv, "vrem.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vrem_vx, "vrem.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> +OP(vremu_vv, "vremu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vremu_vx, "vremu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> OP(vrev8_v, "vrev8.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
> +OP(vrgather_vi, "vrgather.vi", rv_codec_v_i_u,
> rv_fmt_vd_vs2_uimm_vm)
> +OP(vrgather_vv, "vrgather.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vrgather_vx, "vrgather.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> +OP(vrgatherei16_vv, "vrgatherei16.vv", rv_codec_v_r,
> rv_fmt_vd_vs2_vs1_vm)
> OP(vrol_vv, "vrol.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> OP(vrol_vx, "vrol.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> +OP(vror_vi, "vror.vi", rv_codec_vror_vi, rv_fmt_vd_vs2_uimm_vm)
> OP(vror_vv, "vror.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> OP(vror_vx, "vror.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> -OP(vror_vi, "vror.vi", rv_codec_vror_vi, rv_fmt_vd_vs2_uimm_vm)
> +OP(vrsub_vi, "vrsub.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm)
> +OP(vrsub_vx, "vrsub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> +OP(vs1r_v, "vs1r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
> +OP(vs2r_v, "vs2r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
> +OP(vs4r_v, "vs4r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
> +OP(vs8r_v, "vs8r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
> +OP(vsadd_vi, "vsadd.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm)
> +OP(vsadd_vv, "vsadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vsadd_vx, "vsadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> +OP(vsaddu_vi, "vsaddu.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm)
> +OP(vsaddu_vv, "vsaddu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vsaddu_vx, "vsaddu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> +OP(vsbc_vvm, "vsbc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl)
> +OP(vsbc_vxm, "vsbc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl)
> +OP(vse16_v, "vse16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
> +OP(vse32_v, "vse32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
> +OP(vse64_v, "vse64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
> +OP(vse8_v, "vse8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
> +OP(vsetivli, "vsetivli", rv_codec_vsetivli, rv_fmt_vsetivli)
> +OP(vsetvl, "vsetvl", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(vsetvli, "vsetvli", rv_codec_vsetvli, rv_fmt_vsetvli)
> +OP(vsext_vf2, "vsext.vf2", rv_codec_v_r, rv_fmt_vd_vs2_vm)
> +OP(vsext_vf4, "vsext.vf4", rv_codec_v_r, rv_fmt_vd_vs2_vm)
> +OP(vsext_vf8, "vsext.vf8", rv_codec_v_r, rv_fmt_vd_vs2_vm)
> OP(vsha2ch_vv, "vsha2ch.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1)
> OP(vsha2cl_vv, "vsha2cl.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1)
> OP(vsha2ms_vv, "vsha2ms.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1)
> +OP(vslide1down_vx, "vslide1down.vx", rv_codec_v_r,
> rv_fmt_vd_vs2_rs1_vm)
> +OP(vslide1up_vx, "vslide1up.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> +OP(vslidedown_vi, "vslidedown.vi", rv_codec_v_i_u,
> rv_fmt_vd_vs2_uimm_vm)
> +OP(vslidedown_vx, "vslidedown.vx", rv_codec_v_r,
> rv_fmt_vd_vs2_rs1_vm)
> +OP(vslideup_vi, "vslideup.vi", rv_codec_v_i_u,
> rv_fmt_vd_vs2_uimm_vm)
> +OP(vslideup_vx, "vslideup.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> +OP(vsll_vi, "vsll.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm)
> +OP(vsll_vv, "vsll.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vsll_vx, "vsll.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> OP(vsm3c_vi, "vsm3c.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm)
> OP(vsm3me_vv, "vsm3me.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1)
> OP(vsm4k_vi, "vsm4k.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm)
> -OP(vsm4r_vv, "vsm4r.vv", rv_codec_v_r, rv_fmt_vd_vs2)
> OP(vsm4r_vs, "vsm4r.vs", rv_codec_v_r, rv_fmt_vd_vs2)
> +OP(vsm4r_vv, "vsm4r.vv", rv_codec_v_r, rv_fmt_vd_vs2)
> +OP(vsm_v, "vsm.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
> +OP(vsmul_vv, "vsmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vsmul_vx, "vsmul.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> +OP(vsoxei16_v, "vsoxei16.v", rv_codec_v_r,
> rv_fmt_ldst_vd_rs1_vs2_vm)
> +OP(vsoxei32_v, "vsoxei32.v", rv_codec_v_r,
> rv_fmt_ldst_vd_rs1_vs2_vm)
> +OP(vsoxei64_v, "vsoxei64.v", rv_codec_v_r,
> rv_fmt_ldst_vd_rs1_vs2_vm)
> +OP(vsoxei8_v, "vsoxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm)
> +OP(vsra_vi, "vsra.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm)
> +OP(vsra_vv, "vsra.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vsra_vx, "vsra.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> +OP(vsrl_vi, "vsrl.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm)
> +OP(vsrl_vv, "vsrl.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vsrl_vx, "vsrl.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> +OP(vsse16_v, "vsse16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm)
> +OP(vsse32_v, "vsse32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm)
> +OP(vsse64_v, "vsse64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm)
> +OP(vsse8_v, "vsse8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm)
> +OP(vssra_vi, "vssra.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm)
> +OP(vssra_vv, "vssra.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vssra_vx, "vssra.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> +OP(vssrl_vi, "vssrl.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm)
> +OP(vssrl_vv, "vssrl.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vssrl_vx, "vssrl.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> +OP(vssub_vv, "vssub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vssub_vx, "vssub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> +OP(vssubu_vv, "vssubu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vssubu_vx, "vssubu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> +OP(vsub_vv, "vsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vsub_vx, "vsub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> +OP(vsuxei16_v, "vsuxei16.v", rv_codec_v_r,
> rv_fmt_ldst_vd_rs1_vs2_vm)
> +OP(vsuxei32_v, "vsuxei32.v", rv_codec_v_r,
> rv_fmt_ldst_vd_rs1_vs2_vm)
> +OP(vsuxei64_v, "vsuxei64.v", rv_codec_v_r,
> rv_fmt_ldst_vd_rs1_vs2_vm)
> +OP(vsuxei8_v, "vsuxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm)
> +OP(vwadd_vv, "vwadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vwadd_vx, "vwadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> +OP(vwadd_wv, "vwadd.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vwadd_wx, "vwadd.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> +OP(vwaddu_vv, "vwaddu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vwaddu_vx, "vwaddu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> +OP(vwaddu_wv, "vwaddu.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vwaddu_wx, "vwaddu.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> +OP(vwmacc_vv, "vwmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
> +OP(vwmacc_vx, "vwmacc.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm)
> +OP(vwmaccsu_vv, "vwmaccsu.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
> +OP(vwmaccsu_vx, "vwmaccsu.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm)
> +OP(vwmaccu_vv, "vwmaccu.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
> +OP(vwmaccu_vx, "vwmaccu.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm)
> +OP(vwmaccus_vx, "vwmaccus.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm)
> +OP(vwmul_vv, "vwmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vwmul_vx, "vwmul.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> +OP(vwmulsu_vv, "vwmulsu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vwmulsu_vx, "vwmulsu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> +OP(vwmulu_vv, "vwmulu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vwmulu_vx, "vwmulu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> +OP(vwredsum_vs, "vwredsum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vwredsumu_vs, "vwredsumu.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vwsll_vi, "vwsll.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm)
> OP(vwsll_vv, "vwsll.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> OP(vwsll_vx, "vwsll.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> -OP(vwsll_vi, "vwsll.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm)
> -OP(amocas_w, "amocas.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> -OP(amocas_d, "amocas.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> -OP(amocas_q, "amocas.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> -OP(mop_r, "mop.r", rv_codec_mop_r, rv_fmt_mop_r)
> -OP(mop_rr, "mop.rr", rv_codec_mop_rr, rv_fmt_mop_rr)
> -OP(c_mop, "c.mop", rv_codec_cmop, rv_fmt_cmop)
> -OP(amoswap_b, "amoswap.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> -OP(amoadd_b, "amoadd.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> -OP(amoxor_b, "amoxor.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> -OP(amoor_b, "amoor.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> -OP(amoand_b, "amoand.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> -OP(amomin_b, "amomin.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> -OP(amomax_b, "amomax.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> -OP(amominu_b, "amominu.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> -OP(amomaxu_b, "amomaxu.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> -OP(amoswap_h, "amoswap.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> -OP(amoadd_h, "amoadd.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> -OP(amoxor_h, "amoxor.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> -OP(amoor_h, "amoor.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> -OP(amoand_h, "amoand.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> -OP(amomin_h, "amomin.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> -OP(amomax_h, "amomax.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> -OP(amominu_h, "amominu.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> -OP(amomaxu_h, "amomaxu.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> -OP(amocas_b, "amocas.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> -OP(amocas_h, "amocas.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> -OP(wrs_sto, "wrs.sto", rv_codec_none, rv_fmt_none)
> +OP(vwsub_vv, "vwsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vwsub_vx, "vwsub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> +OP(vwsub_wv, "vwsub.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vwsub_wx, "vwsub.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> +OP(vwsubu_vv, "vwsubu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vwsubu_vx, "vwsubu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> +OP(vwsubu_wv, "vwsubu.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vwsubu_wx, "vwsubu.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> +OP(vxor_vi, "vxor.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm)
> +OP(vxor_vv, "vxor.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> +OP(vxor_vx, "vxor.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> +OP(vzext_vf2, "vzext.vf2", rv_codec_v_r, rv_fmt_vd_vs2_vm)
> +OP(vzext_vf4, "vzext.vf4", rv_codec_v_r, rv_fmt_vd_vs2_vm)
> +OP(vzext_vf8, "vzext.vf8", rv_codec_v_r, rv_fmt_vd_vs2_vm)
> +OP(wfi, "wfi", rv_codec_none, rv_fmt_none)
> OP(wrs_nto, "wrs.nto", rv_codec_none, rv_fmt_none)
> -OP(lpad, "lpad", rv_codec_lp, rv_fmt_imm)
> -OP(sspush, "sspush", rv_codec_r, rv_fmt_rs2)
> -OP(sspopchk, "sspopchk", rv_codec_r, rv_fmt_rs1)
> -OP(ssrdp, "ssrdp", rv_codec_r, rv_fmt_rd)
> -OP(ssamoswap_w, "ssamoswap.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> -OP(ssamoswap_d, "ssamoswap.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
> -OP(c_sspush, "c.sspush", rv_codec_cmop_ss, NULL, DECOMP(op_sspush))
> -OP(c_sspopchk, "c.sspopchk", rv_codec_cmop_ss, NULL,
> DECOMP(op_sspopchk))
> -OP(cbo_inval, "cbo.inval", rv_codec_r, rv_fmt_rs1)
> -OP(cbo_clean, "cbo.clean", rv_codec_r, rv_fmt_rs1)
> -OP(cbo_flush, "cbo.flush", rv_codec_r, rv_fmt_rs1)
> -OP(cbo_zero, "cbo.zero", rv_codec_r, rv_fmt_rs1)
> -OP(mnret, "mnret", rv_codec_none, rv_fmt_none)
> +OP(wrs_sto, "wrs.sto", rv_codec_none, rv_fmt_none)
> +OP(xnor, "xnor", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(xor, "xor", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(xori, "xori", rv_codec_i, rv_fmt_rd_rs1_imm, rvcp_xori)
> +OP(xperm4, "xperm4", rv_codec_r, rv_fmt_rd_rs1_rs2)
> +OP(xperm8, "xperm8", rv_codec_r, rv_fmt_rd_rs1)
> +OP(zext_h, "zext.h", rv_codec_r, rv_fmt_rd_rs1)
> +OP(zip, "zip", rv_codec_r, rv_fmt_rd_rs1)
^ permalink raw reply [flat|nested] 119+ messages in thread
end of thread, other threads:[~2026-08-12 13:03 UTC | newest]
Thread overview: 119+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2026-08-09 22:34 [RFC PATCH 00/56] disas/riscv: Reorganize the disassembler Richard Henderson
2026-08-09 22:34 ` [PATCH 01/56] disas/riscv: Fix th.srri decoding Richard Henderson
2026-08-11 19:54 ` Alistair
2026-08-09 22:34 ` [PATCH 02/56] disas/riscv: Fix 6-bit immediate extraction Richard Henderson
2026-08-11 19:55 ` Alistair
2026-08-09 22:34 ` [PATCH 03/56] disas/riscv: Use signed type for vector immediates Richard Henderson
2026-08-10 2:53 ` Philippe Mathieu-Daudé
2026-08-11 19:56 ` Alistair
2026-08-09 22:34 ` [PATCH 04/56] disas/riscv: Decode unsigned vector immediates as unsigned Richard Henderson
2026-08-11 19:57 ` Alistair
2026-08-09 22:34 ` [PATCH 05/56] disas/riscv: Use extract helpers for operand fields Richard Henderson
2026-08-11 19:58 ` Alistair
2026-08-09 22:34 ` [PATCH 06/56] disas/riscv: Move operand extractors earlier in file Richard Henderson
2026-08-11 19:59 ` Alistair
2026-08-09 22:34 ` [PATCH 07/56] disas/riscv: Reduce rv_insn to uint32_t Richard Henderson
2026-08-10 2:54 ` Philippe Mathieu-Daudé
2026-08-11 19:59 ` Alistair
2026-08-09 22:34 ` [PATCH 08/56] disas/riscv: Tidy dec initialization in disasm_inst Richard Henderson
2026-08-10 2:54 ` Philippe Mathieu-Daudé
2026-08-11 20:00 ` Alistair
2026-08-09 22:34 ` [PATCH 09/56] disas/riscv: Pass rv_opcode_data pointer to decode_inst_operands Richard Henderson
2026-08-11 20:02 ` Alistair
2026-08-09 22:34 ` [PATCH 10/56] disas/riscv: Pass rv_opcode_data pointer to/from decode_inst_decompress Richard Henderson
2026-08-11 20:04 ` Alistair
2026-08-09 22:35 ` [PATCH 11/56] disas/riscv: Pass rv_opcode_data pointer to/from decode_inst_lift_pseudo Richard Henderson
2026-08-11 20:05 ` Alistair
2026-08-09 22:35 ` [PATCH 12/56] disas/riscv: Pass rv_opcode_data pointer to format_inst Richard Henderson
2026-08-11 20:06 ` Alistair
2026-08-09 22:35 ` [PATCH 13/56] disas/riscv: Tidy disasm_inst main loop Richard Henderson
2026-08-11 20:08 ` Alistair
2026-08-09 22:35 ` [PATCH 14/56] disas/riscv: Set dec->opcode_data in decode function Richard Henderson
2026-08-11 20:09 ` Alistair
2026-08-09 22:35 ` [PATCH 15/56] disas/riscv: Drop explicit zero of rv_opcode_data fields Richard Henderson
2026-08-11 20:10 ` Alistair
2026-08-09 22:35 ` [PATCH 16/56] disas/riscv: Drop useless const in structures Richard Henderson
2026-08-10 2:55 ` Philippe Mathieu-Daudé
2026-08-11 20:10 ` Alistair
2026-08-09 22:35 ` [PATCH 17/56] disas/riscv: Drop codec from rv_decode Richard Henderson
2026-08-11 20:11 ` Alistair
2026-08-09 22:35 ` [PATCH 18/56] disas/riscv: Handle c.addi4spn imm != 0 during decode Richard Henderson
2026-08-11 20:12 ` Alistair
2026-08-09 22:35 ` [PATCH 19/56] disas/riscv: Simplify c.addi Richard Henderson
2026-08-11 20:14 ` Alistair
2026-08-09 22:35 ` [PATCH 20/56] disas/riscv: Handle c.lui imm != 0 during decode Richard Henderson
2026-08-11 20:14 ` Alistair
2026-08-09 22:35 ` [PATCH 21/56] disas/riscv: Handle c.{srli,srai} imm " Richard Henderson
2026-08-11 20:16 ` Alistair
2026-08-09 22:35 ` [PATCH 22/56] disas/riscv: Handle c.slli imm != 0 " Richard Henderson
2026-08-11 20:16 ` Alistair
2026-08-09 22:35 ` [PATCH 23/56] disas/riscv: Do not recognize c.{addw,subw} with rv32 Richard Henderson
2026-08-11 20:17 ` Alistair
2026-08-09 22:35 ` [PATCH 24/56] disas/riscv: Remove rvcd_imm_nz Richard Henderson
2026-08-11 20:17 ` Alistair
2026-08-09 22:35 ` [PATCH 25/56] disas/riscv: Unify decomp_rv{32,64,128} Richard Henderson
2026-08-11 20:18 ` Alistair
2026-08-09 22:35 ` [PATCH 26/56] disas/riscv: Drop always true branch psudeos Richard Henderson
2026-08-10 2:58 ` Philippe Mathieu-Daudé
2026-08-11 20:19 ` Alistair
2026-08-09 22:35 ` [PATCH 27/56] disas/riscv: Handle aliases of csrrw during decode Richard Henderson
2026-08-11 20:20 ` Alistair
2026-08-09 22:35 ` [PATCH 28/56] disas/riscv: Handle aliases of csrrs " Richard Henderson
2026-08-11 20:21 ` Alistair
2026-08-09 22:35 ` [PATCH 29/56] disas/riscv: Handle aliases of csrrwi " Richard Henderson
2026-08-11 20:22 ` Alistair
2026-08-09 22:35 ` [PATCH 30/56] disas/riscv: Break pseudo loop for jal and jalr Richard Henderson
2026-08-11 20:23 ` Alistair
2026-08-09 22:35 ` [PATCH 31/56] disas/riscv: Allow decode_inst_lift_pseudo to loop Richard Henderson
2026-08-11 20:23 ` Alistair
2026-08-09 22:35 ` [PATCH 32/56] disas/riscv: Handle decompression via decode_inst_lift_pseudo Richard Henderson
2026-08-11 20:24 ` Alistair
2026-08-09 22:35 ` [PATCH 33/56] disas/riscv: Drop format from DECOMP insns Richard Henderson
2026-08-11 20:25 ` Alistair
2026-08-09 22:35 ` [PATCH 34/56] disas/riscv: Tidy rv_comp_data terminators Richard Henderson
2026-08-11 20:25 ` Alistair
2026-08-09 22:35 ` [PATCH 35/56] disas/riscv: Chain "ret" pseudo off "jr" pseudo Richard Henderson
2026-08-11 20:26 ` Alistair
2026-08-09 22:35 ` [PATCH 36/56] disas/riscv: Chain "nop" pseudo off "mv" pseudo Richard Henderson
2026-08-11 20:27 ` Alistair
2026-08-09 22:35 ` [PATCH 37/56] disas/riscv: Use rv_codec_illegal for pseudos Richard Henderson
2026-08-11 20:27 ` Alistair
2026-08-09 22:35 ` [PATCH 38/56] disas/riscv: Simplify some insn decompressions Richard Henderson
2026-08-11 20:29 ` Alistair
2026-08-09 22:35 ` [PATCH 39/56] disas/riscv: Store op pointer in rv_comp_data Richard Henderson
2026-08-12 12:47 ` Alistair
2026-08-09 22:35 ` [PATCH 40/56] disas/riscv: Return rv_opcode_data pointer from decoders Richard Henderson
2026-08-12 12:48 ` Alistair
2026-08-09 22:35 ` [PATCH 41/56] disas/riscv: Reject all of OP-32 and OP-IMM-32 for RV32 Richard Henderson
2026-08-12 12:49 ` Alistair
2026-08-09 22:35 ` [PATCH 42/56] disas/riscv: Fix rv32 encoding of zext.h Richard Henderson
2026-08-12 12:49 ` Alistair
2026-08-09 22:35 ` [PATCH 43/56] disas/riscv: Fix isa decoding of rev8 Richard Henderson
2026-08-12 12:50 ` Alistair
2026-08-09 22:35 ` [PATCH 44/56] disas/riscv: Fix typo in th.lbib format Richard Henderson
2026-08-12 12:50 ` Alistair
2026-08-09 22:35 ` [PATCH 45/56] disas/riscv: Split ventana_opcode_data Richard Henderson
2026-08-12 12:51 ` Alistair
2026-08-09 22:35 ` [PATCH 46/56] disas/riscv: Split xlrbr_opcode_data Richard Henderson
2026-08-12 12:52 ` Alistair
2026-08-09 22:35 ` [PATCH 47/56] disas/riscv: Split xthead_opcode_data Richard Henderson
2026-08-12 12:53 ` Alistair
2026-08-09 22:35 ` [PATCH 48/56] disas/riscv: Move rv_op_illegal to riscv.c Richard Henderson
2026-08-12 12:54 ` Alistair
2026-08-09 22:35 ` [PATCH 49/56] disas/riscv: Split out riscv-op.c.inc Richard Henderson
2026-08-12 12:55 ` Alistair
2026-08-09 22:35 ` [PATCH 50/56] disas/riscv: Merge all mop.r.n to one pattern Richard Henderson
2026-08-12 12:57 ` Alistair
2026-08-09 22:35 ` [PATCH 51/56] disas/riscv: Merge all mop.rr.n " Richard Henderson
2026-08-12 12:57 ` Alistair
2026-08-09 22:35 ` [PATCH 52/56] disas/riscv: Merge all c.mop.n " Richard Henderson
2026-08-12 12:58 ` Alistair
2026-08-09 22:35 ` [PATCH 53/56] disas/riscv: Tidy decode of c.mop.n Richard Henderson
2026-08-12 12:59 ` Alistair
2026-08-09 22:35 ` [PATCH 54/56] disas/riscv: Tidy decode of mop.r.n and mop.rr.n Richard Henderson
2026-08-12 13:00 ` Alistair
2026-08-09 22:35 ` [PATCH 55/56] disas/riscv: Split rvi_opcode_data Richard Henderson
2026-08-12 13:02 ` Alistair
2026-08-09 22:35 ` [PATCH 56/56] disas/riscv: Sort riscv-op.c.inc Richard Henderson
2026-08-10 2:59 ` Philippe Mathieu-Daudé
2026-08-12 13:03 ` Alistair
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