[PATCH v2 00/15] drm/amdgpu/si: Make SI DPM workable

[PATCH v2 00/15] drm/amdgpu/si: Make SI DPM workable

[Huang Rui]

Hi all,

These patchest resolve the DPM issues of SI.
SI DPM doesn't work since it implemented, the following patches fix
several issues to make SI DPM workable now.

Patch 1: Update SI firmware path to share it with radeon

Patch 2 -> 4: Add firmware version for checking firmware loading via
sysfs.

Patch 5 -> 6: Refine the codes for si dpm.

Patch 7 -> 14: Fix the issues which impact DPM functionality.

Patch 15: Enable SI DPM by default.


Changes from V1 -> V2:
- Add a patch to update SI dpm path to firmware/radeon
- Reword patch 5 to "unused function" according to Christian's comments 
- Drop ASIC_IS_DCE6 macro
- Modify patch 11 to use "adev->mc.vram_type" instead of pi->mem_gddr5


Thanks,
Rui

Huang Rui (15):
  drm/amdgpu/si: update si firmware path
  drm/amdgpu: add gfx v6 firmware versions for sysfs dump
  drm/amdgpu: add gmc v6 firmware versions for sysfs dump
  drm/amdgpu/si: add SI smc firmware versions for sysfs dump
  drm/amdgpu: remove unused function forward define
  drm/amdgpu: use DRM print instead of printk
  drm/amdgpu: fix oland and hainan asic specific handle at
    si_program_aspm
  drm/amdgpu/si: drop ASIC_IS_DCE6 macro on SI
  drm/amdgpu: fix the tahiti specific value of DEEP_SLEEP_CLK_SEL field
  drm/amdgpu: fix to miss adding thermal controller
  drm/amdgpu: use vram_type instead of checking mem_gddr5 flag
  drm/amdgpu: fix incorrect index of CG_FFCT_0 register
  drm/amdgpu: introduce pcie port read/write entry
  drm/amdgpu: fix incorrect reading method at si_get_current_pcie_speed
  drm/amdgpu/si: enable SI DPM by default

 drivers/gpu/drm/amd/amdgpu/amdgpu.h           |   4 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c    |   2 +
 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c         |  14 ++++
 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c         |   2 +
 drivers/gpu/drm/amd/amdgpu/si.c               | 112 ++++++++++++++------------
 drivers/gpu/drm/amd/amdgpu/si_dpm.c           |  60 +++++++-------
 drivers/gpu/drm/amd/amdgpu/si_smc.c           |   1 +
 drivers/gpu/drm/amd/include/asic_reg/si/sid.h |   1 -
 8 files changed, 114 insertions(+), 82 deletions(-)

-- 
2.7.4

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[PATCH v2 01/15] drm/amdgpu/si: update si firmware path

[Huang Rui]

SI firmware is shared with radeon for now, so update path with this
patch.

Signed-off-by: Huang Rui <ray.huang@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/si_dpm.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/si_dpm.c b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
index 076f6cd..d66435d 100644
--- a/drivers/gpu/drm/amd/amdgpu/si_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
@@ -55,15 +55,15 @@
 
 #define BIOS_SCRATCH_4                                    0x5cd
 
-MODULE_FIRMWARE("amdgpu/tahiti_smc.bin");
+MODULE_FIRMWARE("radeon/tahiti_smc.bin");
 MODULE_FIRMWARE("radeon/tahiti_k_smc.bin");
-MODULE_FIRMWARE("amdgpu/pitcairn_smc.bin");
+MODULE_FIRMWARE("radeon/pitcairn_smc.bin");
 MODULE_FIRMWARE("radeon/pitcairn_k_smc.bin");
-MODULE_FIRMWARE("amdgpu/verde_smc.bin");
+MODULE_FIRMWARE("radeon/verde_smc.bin");
 MODULE_FIRMWARE("radeon/verde_k_smc.bin");
-MODULE_FIRMWARE("amdgpu/oland_smc.bin");
+MODULE_FIRMWARE("radeon/oland_smc.bin");
 MODULE_FIRMWARE("radeon/oland_k_smc.bin");
-MODULE_FIRMWARE("amdgpu/hainan_smc.bin");
+MODULE_FIRMWARE("radeon/hainan_smc.bin");
 MODULE_FIRMWARE("radeon/hainan_k_smc.bin");
 
 union power_info {
-- 
2.7.4

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[PATCH v2 02/15] drm/amdgpu: add gfx v6 firmware versions for sysfs dump

[Huang Rui]

Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
index f3ad4aa..17a560c 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
@@ -298,6 +298,8 @@ static int gfx_v6_0_init_microcode(struct amdgpu_device *adev)
 	const char *chip_name;
 	char fw_name[30];
 	int err;
+	const struct gfx_firmware_header_v1_0 *cp_hdr;
+	const struct rlc_firmware_header_v1_0 *rlc_hdr;
 
 	DRM_DEBUG("\n");
 
@@ -327,6 +329,9 @@ static int gfx_v6_0_init_microcode(struct amdgpu_device *adev)
 	err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
 	if (err)
 		goto out;
+	cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
+	adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
+	adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
 
 	snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
 	err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
@@ -335,6 +340,9 @@ static int gfx_v6_0_init_microcode(struct amdgpu_device *adev)
 	err = amdgpu_ucode_validate(adev->gfx.me_fw);
 	if (err)
 		goto out;
+	cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
+	adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
+	adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
 
 	snprintf(fw_name, sizeof(fw_name), "radeon/%s_ce.bin", chip_name);
 	err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
@@ -343,12 +351,18 @@ static int gfx_v6_0_init_microcode(struct amdgpu_device *adev)
 	err = amdgpu_ucode_validate(adev->gfx.ce_fw);
 	if (err)
 		goto out;
+	cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
+	adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
+	adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
 
 	snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", chip_name);
 	err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
 	if (err)
 		goto out;
 	err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
+	rlc_hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data;
+	adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
+	adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);
 
 out:
 	if (err) {
-- 
2.7.4

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[PATCH v2 03/15] drm/amdgpu: add gmc v6 firmware versions for sysfs dump

[Huang Rui]

Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
index c18a4ef..1d2952b 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
@@ -149,6 +149,8 @@ static int gmc_v6_0_mc_load_microcode(struct amdgpu_device *adev)
 	hdr = (const struct mc_firmware_header_v1_0 *)adev->mc.fw->data;
 
 	amdgpu_ucode_print_mc_hdr(&hdr->header);
+
+	adev->mc.fw_version = le32_to_cpu(hdr->header.ucode_version);
 	regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
 	new_io_mc_regs = (const __le32 *)
 		(adev->mc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
-- 
2.7.4

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[PATCH v2 04/15] drm/amdgpu/si: add SI smc firmware versions for sysfs dump

[Huang Rui]

Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/si_smc.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/si_smc.c b/drivers/gpu/drm/amd/amdgpu/si_smc.c
index 214f37c..c1c2594 100644
--- a/drivers/gpu/drm/amd/amdgpu/si_smc.c
+++ b/drivers/gpu/drm/amd/amdgpu/si_smc.c
@@ -224,6 +224,7 @@ int si_load_smc_ucode(struct amdgpu_device *adev, u32 limit)
 
 	amdgpu_ucode_print_smc_hdr(&hdr->header);
 
+	adev->pm.fw_version = le32_to_cpu(hdr->header.ucode_version);
 	ucode_start_address = le32_to_cpu(hdr->ucode_start_addr);
 	ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes);
 	src = (const u8 *)
-- 
2.7.4

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[PATCH v2 05/15] drm/amdgpu: remove unused function forward define

[Huang Rui]

The functions don't exists any more.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/si_dpm.c | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/si_dpm.c b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
index d66435d..fa56184 100644
--- a/drivers/gpu/drm/amd/amdgpu/si_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
@@ -1828,9 +1828,6 @@ struct evergreen_power_info *evergreen_get_pi(struct amdgpu_device *adev);
 struct ni_power_info *ni_get_pi(struct amdgpu_device *adev);
 struct  si_ps *si_get_ps(struct amdgpu_ps *rps);
 
-extern int si_mc_load_microcode(struct amdgpu_device *adev);
-extern void vce_v1_0_enable_mgcg(struct amdgpu_device *adev, bool enable);
-
 static int si_populate_voltage_value(struct amdgpu_device *adev,
 				     const struct atom_voltage_table *table,
 				     u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage);
-- 
2.7.4

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[PATCH v2 06/15] drm/amdgpu: use DRM print instead of printk

[Huang Rui]

Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/si_dpm.c | 15 +++++++--------
 1 file changed, 7 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/si_dpm.c b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
index fa56184..c9b0989 100644
--- a/drivers/gpu/drm/amd/amdgpu/si_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
@@ -7720,9 +7720,8 @@ static int si_dpm_init_microcode(struct amdgpu_device *adev)
 
 out:
 	if (err) {
-		printk(KERN_ERR
-		       "si_smc: Failed to load firmware. err = %d\"%s\"\n",
-		       err, fw_name);
+		DRM_ERROR("si_smc: Failed to load firmware. err = %d\"%s\"\n",
+			  err, fw_name);
 		release_firmware(adev->pm.fw);
 		adev->pm.fw = NULL;
 	}
@@ -7941,15 +7940,15 @@ static void si_dpm_print_power_state(struct amdgpu_device *adev,
                                
         amdgpu_dpm_print_class_info(rps->class, rps->class2);
         amdgpu_dpm_print_cap_info(rps->caps);
-        printk("\tuvd    vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
+        DRM_INFO("\tuvd    vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
         for (i = 0; i < ps->performance_level_count; i++) {
                 pl = &ps->performance_levels[i];
                 if (adev->asic_type >= CHIP_TAHITI)
-                        printk("\t\tpower level %d    sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n",
-                               i, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1);
+                        DRM_INFO("\t\tpower level %d    sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n",
+				 i, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1);
                 else
-                        printk("\t\tpower level %d    sclk: %u mclk: %u vddc: %u vddci: %u\n",
-                               i, pl->sclk, pl->mclk, pl->vddc, pl->vddci);
+                        DRM_INFO("\t\tpower level %d    sclk: %u mclk: %u vddc: %u vddci: %u\n",
+				 i, pl->sclk, pl->mclk, pl->vddc, pl->vddci);
         }
         amdgpu_dpm_print_ps_status(adev, rps);
 }
-- 
2.7.4

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[PATCH v2 07/15] drm/amdgpu: fix oland and hainan asic specific handle at si_program_aspm

[Huang Rui]

Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/si.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c
index d2309b7..d5fc197 100644
--- a/drivers/gpu/drm/amd/amdgpu/si.c
+++ b/drivers/gpu/drm/amd/amdgpu/si.c
@@ -1602,7 +1602,7 @@ static void si_program_aspm(struct amdgpu_device *adev)
 			if (orig != data)
 				si_pif_phy1_wreg(adev,PB1_PIF_PWRDOWN_1, data);
 
-			{
+			if ((adev->family != CHIP_OLAND) && (adev->family != CHIP_HAINAN)) {
 				orig = data = si_pif_phy0_rreg(adev,PB0_PIF_PWRDOWN_0);
 				data &= ~PLL_RAMP_UP_TIME_0_MASK;
 				if (orig != data)
@@ -1651,11 +1651,15 @@ static void si_program_aspm(struct amdgpu_device *adev)
 
 			orig = data = si_pif_phy0_rreg(adev,PB0_PIF_CNTL);
 			data &= ~LS2_EXIT_TIME_MASK;
+			if ((adev->family == CHIP_OLAND) || (adev->family == CHIP_HAINAN))
+				data |= LS2_EXIT_TIME(5);
 			if (orig != data)
 				si_pif_phy0_wreg(adev,PB0_PIF_CNTL, data);
 
 			orig = data = si_pif_phy1_rreg(adev,PB1_PIF_CNTL);
 			data &= ~LS2_EXIT_TIME_MASK;
+			if ((adev->family == CHIP_OLAND) || (adev->family == CHIP_HAINAN))
+				data |= LS2_EXIT_TIME(5);
 			if (orig != data)
 				si_pif_phy1_wreg(adev,PB1_PIF_CNTL, data);
 
-- 
2.7.4

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[PATCH v2 08/15] drm/amdgpu/si: drop ASIC_IS_DCE6 macro on SI

[Huang Rui]

Drop ASIC_IS_DCE6 macro, because it will check the asic types
explicitly in future.

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
---
 drivers/gpu/drm/amd/include/asic_reg/si/sid.h | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/include/asic_reg/si/sid.h b/drivers/gpu/drm/amd/include/asic_reg/si/sid.h
index 9609199..8c5608a 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/si/sid.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/si/sid.h
@@ -1968,7 +1968,6 @@
 #define AMDGPU_MM_INDEX		        0x0000
 #define AMDGPU_MM_DATA		        0x0001
 
-#define ASIC_IS_DCE6(adev) ((adev->asic_type == CHIP_VERDE))
 #define VERDE_NUM_CRTC 6
 #define	BLACKOUT_MODE_MASK			0x00000007
 #define	VGA_RENDER_CONTROL			0xC0
-- 
2.7.4

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[PATCH v2 09/15] drm/amdgpu: fix the tahiti specific value of DEEP_SLEEP_CLK_SEL field

[Huang Rui]

Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/si_dpm.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/si_dpm.c b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
index c9b0989..5269c33 100644
--- a/drivers/gpu/drm/amd/amdgpu/si_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
@@ -4173,7 +4173,13 @@ static void si_program_response_times(struct amdgpu_device *adev)
 static void si_program_ds_registers(struct amdgpu_device *adev)
 {
 	struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
-	u32 tmp = 1; /* XXX: 0x10 on tahiti A0 */
+	u32 tmp;
+
+	/* DEEP_SLEEP_CLK_SEL field should be 0x10 on tahiti A0 */
+	if (adev->asic_type == CHIP_TAHITI && adev->rev_id == 0x0)
+		tmp = 0x10;
+	else
+		tmp = 0x1;
 
 	if (eg_pi->sclk_deep_sleep) {
 		WREG32_P(MISC_CLK_CNTL, DEEP_SLEEP_CLK_SEL(tmp), ~DEEP_SLEEP_CLK_SEL_MASK);
-- 
2.7.4

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[PATCH v2 10/15] drm/amdgpu: fix to miss adding thermal controller

[Huang Rui]

Thermal controller isn't inited during si dpm sw_init phase.

Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/si_dpm.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/si_dpm.c b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
index 5269c33..ece2527 100644
--- a/drivers/gpu/drm/amd/amdgpu/si_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
@@ -7281,6 +7281,8 @@ static int si_parse_power_table(struct amdgpu_device *adev)
 		return -EINVAL;
 	power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
 
+	amdgpu_add_thermal_controller(adev);
+
 	state_array = (struct _StateArray *)
 		(mode_info->atom_context->bios + data_offset +
 		 le16_to_cpu(power_info->pplib.usStateArrayOffset));
-- 
2.7.4

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[PATCH v2 11/15] drm/amdgpu: use vram_type instead of checking mem_gddr5 flag

[Huang Rui]

For current design, it would better use vram_type member to check if
current vram is GDDR5. So remove the old mem_gddr5 flag.

Signed-off-by: Huang Rui <ray.huang@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/si_dpm.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/si_dpm.c b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
index ece2527..e1b2ab5 100644
--- a/drivers/gpu/drm/amd/amdgpu/si_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
@@ -4375,7 +4375,7 @@ static u8 si_get_strobe_mode_settings(struct amdgpu_device *adev, u32 mclk)
 	if (mclk <= pi->mclk_strobe_mode_threshold)
 		strobe_mode = true;
 
-	if (pi->mem_gddr5)
+	if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5)
 		result = si_get_mclk_frequency_ratio(mclk, strobe_mode);
 	else
 		result = si_get_ddr3_mclk_frequency_ratio(mclk);
@@ -4965,7 +4965,7 @@ static int si_populate_smc_initial_state(struct amdgpu_device *adev,
 
 	table->initialState.levels[0].gen2PCIE = (u8)si_pi->boot_pcie_gen;
 
-	if (pi->mem_gddr5) {
+	if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) {
 		table->initialState.levels[0].strobeMode =
 			si_get_strobe_mode_settings(adev,
 						    initial_state->performance_levels[0].mclk);
@@ -5237,7 +5237,7 @@ static int si_init_smc_table(struct amdgpu_device *adev)
 	if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)
 		table->systemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
 
-	if (pi->mem_gddr5)
+	if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5)
 		table->systemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
 
 	if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY)
@@ -5414,7 +5414,7 @@ static int si_populate_mclk_value(struct amdgpu_device *adev,
 	mpll_ad_func_cntl &= ~YCLK_POST_DIV_MASK;
 	mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div);
 
-	if (pi->mem_gddr5) {
+	if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) {
 		mpll_dq_func_cntl &= ~(YCLK_SEL_MASK | YCLK_POST_DIV_MASK);
 		mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel) |
 			YCLK_POST_DIV(mpll_param.post_div);
@@ -5426,7 +5426,7 @@ static int si_populate_mclk_value(struct amdgpu_device *adev,
 		u32 tmp;
 		u32 reference_clock = adev->clock.mpll.reference_freq;
 
-		if (pi->mem_gddr5)
+		if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5)
 			freq_nom = memory_clock * 4;
 		else
 			freq_nom = memory_clock * 2;
@@ -5518,7 +5518,7 @@ static int si_convert_power_level_to_smc(struct amdgpu_device *adev,
 			level->mcFlags |= SISLANDS_SMC_MC_PG_EN;
 	}
 
-	if (pi->mem_gddr5) {
+	if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) {
 		if (pl->mclk > pi->mclk_edc_enable_threshold)
 			level->mcFlags |= SISLANDS_SMC_MC_EDC_RD_FLAG;
 
-- 
2.7.4

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[PATCH v2 12/15] drm/amdgpu: fix incorrect index of CG_FFCT_0 register

[Huang Rui]

Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/si_dpm.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/si_dpm.c b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
index e1b2ab5..8541830 100644
--- a/drivers/gpu/drm/amd/amdgpu/si_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
@@ -4281,7 +4281,7 @@ static void si_program_tp(struct amdgpu_device *adev)
 	enum r600_td td = R600_TD_DFLT;
 
 	for (i = 0; i < R600_PM_NUMBER_OF_TC; i++)
-		WREG32(CG_FFCT_0 + (i * 10), (UTC_0(r600_utc[i]) | DTC_0(r600_dtc[i])));
+		WREG32(CG_FFCT_0 + i, (UTC_0(r600_utc[i]) | DTC_0(r600_dtc[i])));
 
 	if (td == R600_TD_AUTO)
 		WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL);
-- 
2.7.4

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[PATCH v2 13/15] drm/amdgpu: introduce pcie port read/write entry

[Huang Rui]

This patch adds pcie port read/write entry, because it will be also
used on si dpm part.

Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h        |   4 ++
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c |   2 +
 drivers/gpu/drm/amd/amdgpu/si.c            | 106 +++++++++++++++--------------
 3 files changed, 60 insertions(+), 52 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 19c9a2e..6eb1d3d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -2043,6 +2043,8 @@ struct amdgpu_device {
 	spinlock_t pcie_idx_lock;
 	amdgpu_rreg_t			pcie_rreg;
 	amdgpu_wreg_t			pcie_wreg;
+	amdgpu_rreg_t			pciep_rreg;
+	amdgpu_wreg_t			pciep_wreg;
 	/* protects concurrent UVD register access */
 	spinlock_t uvd_ctx_idx_lock;
 	amdgpu_rreg_t			uvd_ctx_rreg;
@@ -2183,6 +2185,8 @@ bool amdgpu_device_has_dal_support(struct amdgpu_device *adev);
 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))
+#define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg))
+#define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v))
 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg))
 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v))
 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg))
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 8eb5396..a20a2b2 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1544,6 +1544,8 @@ int amdgpu_device_init(struct amdgpu_device *adev,
 	adev->smc_wreg = &amdgpu_invalid_wreg;
 	adev->pcie_rreg = &amdgpu_invalid_rreg;
 	adev->pcie_wreg = &amdgpu_invalid_wreg;
+	adev->pciep_rreg = &amdgpu_invalid_rreg;
+	adev->pciep_wreg = &amdgpu_invalid_wreg;
 	adev->uvd_ctx_rreg = &amdgpu_invalid_rreg;
 	adev->uvd_ctx_wreg = &amdgpu_invalid_wreg;
 	adev->didt_rreg = &amdgpu_invalid_rreg;
diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c
index d5fc197..fee76b8 100644
--- a/drivers/gpu/drm/amd/amdgpu/si.c
+++ b/drivers/gpu/drm/amd/amdgpu/si.c
@@ -905,6 +905,31 @@ static void si_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 	spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
 }
 
+u32 si_pciep_rreg(struct amdgpu_device *adev, u32 reg)
+{
+	unsigned long flags;
+	u32 r;
+
+	spin_lock_irqsave(&adev->pcie_idx_lock, flags);
+	WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
+	(void)RREG32(PCIE_PORT_INDEX);
+	r = RREG32(PCIE_PORT_DATA);
+	spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
+	return r;
+}
+
+void si_pciep_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
+{
+	unsigned long flags;
+
+	spin_lock_irqsave(&adev->pcie_idx_lock, flags);
+	WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
+	(void)RREG32(PCIE_PORT_INDEX);
+	WREG32(PCIE_PORT_DATA, (v));
+	(void)RREG32(PCIE_PORT_DATA);
+	spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
+}
+
 static u32 si_smc_rreg(struct amdgpu_device *adev, u32 reg)
 {
 	unsigned long flags;
@@ -1125,6 +1150,8 @@ static int si_common_early_init(void *handle)
 	adev->smc_wreg = &si_smc_wreg;
 	adev->pcie_rreg = &si_pcie_rreg;
 	adev->pcie_wreg = &si_pcie_wreg;
+	adev->pciep_rreg = &si_pciep_rreg;
+	adev->pciep_wreg = &si_pciep_wreg;
 	adev->uvd_ctx_rreg = NULL;
 	adev->uvd_ctx_wreg = NULL;
 	adev->didt_rreg = NULL;
@@ -1316,31 +1343,6 @@ static void si_init_golden_registers(struct amdgpu_device *adev)
 	}
 }
 
-u32 si_pciep_rreg(struct amdgpu_device *adev, u32 reg)
-{
-	unsigned long flags;
-	u32 r;
-
-	spin_lock_irqsave(&adev->pcie_idx_lock, flags);
-	WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
-	(void)RREG32(PCIE_PORT_INDEX);
-	r = RREG32(PCIE_PORT_DATA);
-	spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
-	return r;
-}
-
-void si_pciep_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
-{
-	unsigned long flags;
-
-	spin_lock_irqsave(&adev->pcie_idx_lock, flags);
-	WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
-	(void)RREG32(PCIE_PORT_INDEX);
-	WREG32(PCIE_PORT_DATA, (v));
-	(void)RREG32(PCIE_PORT_DATA);
-	spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
-}
-
 static void si_pcie_gen3_enable(struct amdgpu_device *adev)
 {
 	struct pci_dev *root = adev->pdev->bus->self;
@@ -1365,7 +1367,7 @@ static void si_pcie_gen3_enable(struct amdgpu_device *adev)
 	if (!(mask & (DRM_PCIE_SPEED_50 | DRM_PCIE_SPEED_80)))
 		return;
 
-	speed_cntl = si_pciep_rreg(adev,PCIE_LC_SPEED_CNTL);
+	speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
 	current_data_rate = (speed_cntl & LC_CURRENT_DATA_RATE_MASK) >>
 		LC_CURRENT_DATA_RATE_SHIFT;
 	if (mask & DRM_PCIE_SPEED_80) {
@@ -1410,12 +1412,12 @@ static void si_pcie_gen3_enable(struct amdgpu_device *adev)
 			current_lw = (tmp & LC_OPERATING_LINK_WIDTH_MASK) >> LC_OPERATING_LINK_WIDTH_SHIFT;
 
 			if (current_lw < max_lw) {
-				tmp = si_pciep_rreg(adev, PCIE_LC_LINK_WIDTH_CNTL);
+				tmp = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
 				if (tmp & LC_RENEGOTIATION_SUPPORT) {
 					tmp &= ~(LC_LINK_WIDTH_MASK | LC_UPCONFIGURE_DIS);
 					tmp |= (max_lw << LC_LINK_WIDTH_SHIFT);
 					tmp |= LC_UPCONFIGURE_SUPPORT | LC_RENEGOTIATE_EN | LC_RECONFIG_NOW;
-					si_pciep_wreg(adev, PCIE_LC_LINK_WIDTH_CNTL, tmp);
+					WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, tmp);
 				}
 			}
 
@@ -1430,13 +1432,13 @@ static void si_pcie_gen3_enable(struct amdgpu_device *adev)
 				pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &bridge_cfg2);
 				pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &gpu_cfg2);
 
-				tmp = si_pciep_rreg(adev, PCIE_LC_CNTL4);
+				tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
 				tmp |= LC_SET_QUIESCE;
-				si_pciep_wreg(adev,PCIE_LC_CNTL4, tmp);
+				WREG32_PCIE_PORT(PCIE_LC_CNTL4, tmp);
 
-				tmp = si_pciep_rreg(adev, PCIE_LC_CNTL4);
+				tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
 				tmp |= LC_REDO_EQ;
-				si_pciep_wreg(adev, PCIE_LC_CNTL4, tmp);
+				WREG32_PCIE_PORT(PCIE_LC_CNTL4, tmp);
 
 				mdelay(100);
 
@@ -1460,16 +1462,16 @@ static void si_pcie_gen3_enable(struct amdgpu_device *adev)
 				tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 9)));
 				pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);
 
-				tmp = si_pciep_rreg(adev, PCIE_LC_CNTL4);
+				tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
 				tmp &= ~LC_SET_QUIESCE;
-				si_pciep_wreg(adev, PCIE_LC_CNTL4, tmp);
+				WREG32_PCIE_PORT(PCIE_LC_CNTL4, tmp);
 			}
 		}
 	}
 
 	speed_cntl |= LC_FORCE_EN_SW_SPEED_CHANGE | LC_FORCE_DIS_HW_SPEED_CHANGE;
 	speed_cntl &= ~LC_FORCE_DIS_SW_SPEED_CHANGE;
-	si_pciep_wreg(adev, PCIE_LC_SPEED_CNTL, speed_cntl);
+	WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
 
 	pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
 	tmp16 &= ~0xf;
@@ -1481,12 +1483,12 @@ static void si_pcie_gen3_enable(struct amdgpu_device *adev)
 		tmp16 |= 1;
 	pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);
 
-	speed_cntl = si_pciep_rreg(adev, PCIE_LC_SPEED_CNTL);
+	speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
 	speed_cntl |= LC_INITIATE_LINK_SPEED_CHANGE;
-	si_pciep_wreg(adev, PCIE_LC_SPEED_CNTL, speed_cntl);
+	WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
 
 	for (i = 0; i < adev->usec_timeout; i++) {
-		speed_cntl = si_pciep_rreg(adev, PCIE_LC_SPEED_CNTL);
+		speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
 		if ((speed_cntl & LC_INITIATE_LINK_SPEED_CHANGE) == 0)
 			break;
 		udelay(1);
@@ -1547,23 +1549,23 @@ static void si_program_aspm(struct amdgpu_device *adev)
 
 	if (adev->flags & AMD_IS_APU)
 		return;
-	orig = data = si_pciep_rreg(adev, PCIE_LC_N_FTS_CNTL);
+	orig = data = RREG32_PCIE_PORT(PCIE_LC_N_FTS_CNTL);
 	data &= ~LC_XMIT_N_FTS_MASK;
 	data |= LC_XMIT_N_FTS(0x24) | LC_XMIT_N_FTS_OVERRIDE_EN;
 	if (orig != data)
-		si_pciep_wreg(adev, PCIE_LC_N_FTS_CNTL, data);
+		WREG32_PCIE_PORT(PCIE_LC_N_FTS_CNTL, data);
 
-	orig = data = si_pciep_rreg(adev, PCIE_LC_CNTL3);
+	orig = data = RREG32_PCIE_PORT(PCIE_LC_CNTL3);
 	data |= LC_GO_TO_RECOVERY;
 	if (orig != data)
-		si_pciep_wreg(adev, PCIE_LC_CNTL3, data);
+		WREG32_PCIE_PORT(PCIE_LC_CNTL3, data);
 
 	orig = data = RREG32_PCIE(PCIE_P_CNTL);
 	data |= P_IGNORE_EDB_ERR;
 	if (orig != data)
 		WREG32_PCIE(PCIE_P_CNTL, data);
 
-	orig = data = si_pciep_rreg(adev, PCIE_LC_CNTL);
+	orig = data = RREG32_PCIE_PORT(PCIE_LC_CNTL);
 	data &= ~(LC_L0S_INACTIVITY_MASK | LC_L1_INACTIVITY_MASK);
 	data |= LC_PMI_TO_L1_DIS;
 	if (!disable_l0s)
@@ -1573,7 +1575,7 @@ static void si_program_aspm(struct amdgpu_device *adev)
 		data |= LC_L1_INACTIVITY(7);
 		data &= ~LC_PMI_TO_L1_DIS;
 		if (orig != data)
-			si_pciep_wreg(adev, PCIE_LC_CNTL, data);
+			WREG32_PCIE_PORT(PCIE_LC_CNTL, data);
 
 		if (!disable_plloff_in_l1) {
 			bool clk_req_support;
@@ -1643,11 +1645,11 @@ static void si_program_aspm(struct amdgpu_device *adev)
 				if (orig != data)
 					si_pif_phy1_wreg(adev,PB1_PIF_PWRDOWN_3, data);
 			}
-			orig = data = si_pciep_rreg(adev, PCIE_LC_LINK_WIDTH_CNTL);
+			orig = data = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
 			data &= ~LC_DYN_LANES_PWR_STATE_MASK;
 			data |= LC_DYN_LANES_PWR_STATE(3);
 			if (orig != data)
-				si_pciep_wreg(adev, PCIE_LC_LINK_WIDTH_CNTL, data);
+				WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, data);
 
 			orig = data = si_pif_phy0_rreg(adev,PB0_PIF_CNTL);
 			data &= ~LS2_EXIT_TIME_MASK;
@@ -1677,10 +1679,10 @@ static void si_program_aspm(struct amdgpu_device *adev)
 			}
 
 			if (clk_req_support) {
-				orig = data = si_pciep_rreg(adev, PCIE_LC_CNTL2);
+				orig = data = RREG32_PCIE_PORT(PCIE_LC_CNTL2);
 				data |= LC_ALLOW_PDWN_IN_L1 | LC_ALLOW_PDWN_IN_L23;
 				if (orig != data)
-					si_pciep_wreg(adev, PCIE_LC_CNTL2, data);
+					WREG32_PCIE_PORT(PCIE_LC_CNTL2, data);
 
 				orig = data = RREG32(THM_CLK_CNTL);
 				data &= ~(CMON_CLK_SEL_MASK | TMON_CLK_SEL_MASK);
@@ -1718,7 +1720,7 @@ static void si_program_aspm(struct amdgpu_device *adev)
 		}
 	} else {
 		if (orig != data)
-			si_pciep_wreg(adev, PCIE_LC_CNTL, data);
+			WREG32_PCIE_PORT(PCIE_LC_CNTL, data);
 	}
 
 	orig = data = RREG32_PCIE(PCIE_CNTL2);
@@ -1727,14 +1729,14 @@ static void si_program_aspm(struct amdgpu_device *adev)
 		WREG32_PCIE(PCIE_CNTL2, data);
 
 	if (!disable_l0s) {
-		data = si_pciep_rreg(adev, PCIE_LC_N_FTS_CNTL);
+		data = RREG32_PCIE_PORT(PCIE_LC_N_FTS_CNTL);
 		if((data & LC_N_FTS_MASK) == LC_N_FTS_MASK) {
 			data = RREG32_PCIE(PCIE_LC_STATUS1);
 			if ((data & LC_REVERSE_XMIT) && (data & LC_REVERSE_RCVR)) {
-				orig = data = si_pciep_rreg(adev, PCIE_LC_CNTL);
+				orig = data = RREG32_PCIE_PORT(PCIE_LC_CNTL);
 				data &= ~LC_L0S_INACTIVITY_MASK;
 				if (orig != data)
-					si_pciep_wreg(adev, PCIE_LC_CNTL, data);
+					WREG32_PCIE_PORT(PCIE_LC_CNTL, data);
 			}
 		}
 	}
-- 
2.7.4

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[PATCH v2 14/15] drm/amdgpu: fix incorrect reading method at si_get_current_pcie_speed

[Huang Rui]

Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/si_dpm.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/si_dpm.c b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
index 8541830..b63dd39 100644
--- a/drivers/gpu/drm/amd/amdgpu/si_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
@@ -6242,7 +6242,7 @@ static u16 si_get_current_pcie_speed(struct amdgpu_device *adev)
 {
 	u32 speed_cntl;
 
-	speed_cntl = RREG32_PCIE(PCIE_LC_SPEED_CNTL) & LC_CURRENT_DATA_RATE_MASK;
+	speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL) & LC_CURRENT_DATA_RATE_MASK;
 	speed_cntl >>= LC_CURRENT_DATA_RATE_SHIFT;
 
 	return (u16)speed_cntl;
-- 
2.7.4

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[PATCH v2 15/15] drm/amdgpu/si: enable SI DPM by default

[Huang Rui]

SI DPM issue is fixed, so enable it by default.

Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/si_dpm.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/si_dpm.c b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
index b63dd39..0c3bc22 100644
--- a/drivers/gpu/drm/amd/amdgpu/si_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
@@ -7633,7 +7633,7 @@ static int si_dpm_late_init(void *handle)
 	int ret;
 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
-	if (amdgpu_dpm <= 0)
+	if (!amdgpu_dpm)
 		return 0;
 
 	/* init the sysfs and debugfs files late */
@@ -7760,7 +7760,7 @@ static int si_dpm_sw_init(void *handle)
 	adev->pm.current_mclk = adev->clock.default_mclk;
 	adev->pm.int_thermal_type = THERMAL_TYPE_NONE;
 
-	if (amdgpu_dpm <= 0)
+	if (!amdgpu_dpm)
 		return 0;
 
 	ret = si_dpm_init_microcode(adev);
@@ -7805,7 +7805,7 @@ static int si_dpm_hw_init(void *handle)
 
 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
-	if (amdgpu_dpm <= 0)
+	if (!amdgpu_dpm)
 		return 0;
 
 	mutex_lock(&adev->pm.mutex);
-- 
2.7.4

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Re: [PATCH v2 00/15] drm/amdgpu/si: Make SI DPM workable

[Alex Deucher]

On Wed, Aug 31, 2016 at 1:23 AM, Huang Rui <ray.huang@amd.com> wrote:
> Hi all,
>
> These patchest resolve the DPM issues of SI.
> SI DPM doesn't work since it implemented, the following patches fix
> several issues to make SI DPM workable now.
>
> Patch 1: Update SI firmware path to share it with radeon
>
> Patch 2 -> 4: Add firmware version for checking firmware loading via
> sysfs.
>
> Patch 5 -> 6: Refine the codes for si dpm.
>
> Patch 7 -> 14: Fix the issues which impact DPM functionality.
>
> Patch 15: Enable SI DPM by default.
>
>
> Changes from V1 -> V2:
> - Add a patch to update SI dpm path to firmware/radeon
> - Reword patch 5 to "unused function" according to Christian's comments
> - Drop ASIC_IS_DCE6 macro
> - Modify patch 11 to use "adev->mc.vram_type" instead of pi->mem_gddr5
>

I've squashed most of these into the original patches and pushed the
whole things.  Thanks!

Alex

>
> Thanks,
> Rui
>
> Huang Rui (15):
>   drm/amdgpu/si: update si firmware path
>   drm/amdgpu: add gfx v6 firmware versions for sysfs dump
>   drm/amdgpu: add gmc v6 firmware versions for sysfs dump
>   drm/amdgpu/si: add SI smc firmware versions for sysfs dump
>   drm/amdgpu: remove unused function forward define
>   drm/amdgpu: use DRM print instead of printk
>   drm/amdgpu: fix oland and hainan asic specific handle at
>     si_program_aspm
>   drm/amdgpu/si: drop ASIC_IS_DCE6 macro on SI
>   drm/amdgpu: fix the tahiti specific value of DEEP_SLEEP_CLK_SEL field
>   drm/amdgpu: fix to miss adding thermal controller
>   drm/amdgpu: use vram_type instead of checking mem_gddr5 flag
>   drm/amdgpu: fix incorrect index of CG_FFCT_0 register
>   drm/amdgpu: introduce pcie port read/write entry
>   drm/amdgpu: fix incorrect reading method at si_get_current_pcie_speed
>   drm/amdgpu/si: enable SI DPM by default
>
>  drivers/gpu/drm/amd/amdgpu/amdgpu.h           |   4 +
>  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c    |   2 +
>  drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c         |  14 ++++
>  drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c         |   2 +
>  drivers/gpu/drm/amd/amdgpu/si.c               | 112 ++++++++++++++------------
>  drivers/gpu/drm/amd/amdgpu/si_dpm.c           |  60 +++++++-------
>  drivers/gpu/drm/amd/amdgpu/si_smc.c           |   1 +
>  drivers/gpu/drm/amd/include/asic_reg/si/sid.h |   1 -
>  8 files changed, 114 insertions(+), 82 deletions(-)
>
> --
> 2.7.4
>
> _______________________________________________
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> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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Re: [PATCH v2 00/15] drm/amdgpu/si: Make SI DPM workable

[Marek Olšák]

Hi Rui,

Do you have Tahiti LE in the office? It might be worth testing it to
see if it works. There were some issues with it in the past.

Marek

On Wed, Aug 31, 2016 at 7:23 AM, Huang Rui <ray.huang@amd.com> wrote:
> Hi all,
>
> These patchest resolve the DPM issues of SI.
> SI DPM doesn't work since it implemented, the following patches fix
> several issues to make SI DPM workable now.
>
> Patch 1: Update SI firmware path to share it with radeon
>
> Patch 2 -> 4: Add firmware version for checking firmware loading via
> sysfs.
>
> Patch 5 -> 6: Refine the codes for si dpm.
>
> Patch 7 -> 14: Fix the issues which impact DPM functionality.
>
> Patch 15: Enable SI DPM by default.
>
>
> Changes from V1 -> V2:
> - Add a patch to update SI dpm path to firmware/radeon
> - Reword patch 5 to "unused function" according to Christian's comments
> - Drop ASIC_IS_DCE6 macro
> - Modify patch 11 to use "adev->mc.vram_type" instead of pi->mem_gddr5
>
>
> Thanks,
> Rui
>
> Huang Rui (15):
>   drm/amdgpu/si: update si firmware path
>   drm/amdgpu: add gfx v6 firmware versions for sysfs dump
>   drm/amdgpu: add gmc v6 firmware versions for sysfs dump
>   drm/amdgpu/si: add SI smc firmware versions for sysfs dump
>   drm/amdgpu: remove unused function forward define
>   drm/amdgpu: use DRM print instead of printk
>   drm/amdgpu: fix oland and hainan asic specific handle at
>     si_program_aspm
>   drm/amdgpu/si: drop ASIC_IS_DCE6 macro on SI
>   drm/amdgpu: fix the tahiti specific value of DEEP_SLEEP_CLK_SEL field
>   drm/amdgpu: fix to miss adding thermal controller
>   drm/amdgpu: use vram_type instead of checking mem_gddr5 flag
>   drm/amdgpu: fix incorrect index of CG_FFCT_0 register
>   drm/amdgpu: introduce pcie port read/write entry
>   drm/amdgpu: fix incorrect reading method at si_get_current_pcie_speed
>   drm/amdgpu/si: enable SI DPM by default
>
>  drivers/gpu/drm/amd/amdgpu/amdgpu.h           |   4 +
>  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c    |   2 +
>  drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c         |  14 ++++
>  drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c         |   2 +
>  drivers/gpu/drm/amd/amdgpu/si.c               | 112 ++++++++++++++------------
>  drivers/gpu/drm/amd/amdgpu/si_dpm.c           |  60 +++++++-------
>  drivers/gpu/drm/amd/amdgpu/si_smc.c           |   1 +
>  drivers/gpu/drm/amd/include/asic_reg/si/sid.h |   1 -
>  8 files changed, 114 insertions(+), 82 deletions(-)
>
> --
> 2.7.4
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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Re: [PATCH v2 00/15] drm/amdgpu/si: Make SI DPM workable

[Huang Rui]

On Tue, Sep 06, 2016 at 03:31:46AM +0800, Marek Olšák wrote:
> Hi Rui,
> 
> Do you have Tahiti LE in the office? It might be worth testing it to
> see if it works. There were some issues with it in the past.
> 

I used Tahiti XT [Device ID 6798], do you know the device id of Tahiti LE?

Thanks,
Rui
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Re: [PATCH v2 00/15] drm/amdgpu/si: Make SI DPM workable

[Marek Olšák]

On Tue, Sep 6, 2016 at 4:35 AM, Huang Rui <ray.huang@amd.com> wrote:
> On Tue, Sep 06, 2016 at 03:31:46AM +0800, Marek Olšák wrote:
>> Hi Rui,
>>
>> Do you have Tahiti LE in the office? It might be worth testing it to
>> see if it works. There were some issues with it in the past.
>>
>
> I used Tahiti XT [Device ID 6798], do you know the device id of Tahiti LE?

No, I only know that Tahiti LE is Radeon HD 7870 XT. It was made by
Sapphire and Powercolor.

Marek
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Re: [PATCH v2 00/15] drm/amdgpu/si: Make SI DPM workable

[Huang Rui]

On Tue, Sep 06, 2016 at 04:04:10PM +0800, Marek Olšák wrote:
> On Tue, Sep 6, 2016 at 4:35 AM, Huang Rui <ray.huang@amd.com> wrote:
> > On Tue, Sep 06, 2016 at 03:31:46AM +0800, Marek Olšák wrote:
> >> Hi Rui,
> >>
> >> Do you have Tahiti LE in the office? It might be worth testing it to
> >> see if it works. There were some issues with it in the past.
> >>
> >
> > I used Tahiti XT [Device ID 6798], do you know the device id of Tahiti LE?
> 
> No, I only know that Tahiti LE is Radeon HD 7870 XT. It was made by
> Sapphire and Powercolor.
> 

OK, my card is Radeon HD 7970 XT. It works well. Do you know what kind of
issues, anymore info?

Thanks,
Rui
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Re: [PATCH v2 00/15] drm/amdgpu/si: Make SI DPM workable

[Michel Dänzer]

On 06/09/16 05:16 PM, Huang Rui wrote:
> On Tue, Sep 06, 2016 at 04:04:10PM +0800, Marek Olšák wrote:
>> On Tue, Sep 6, 2016 at 4:35 AM, Huang Rui <ray.huang@amd.com> wrote:
>>> On Tue, Sep 06, 2016 at 03:31:46AM +0800, Marek Olšák wrote:
>>>> Hi Rui,
>>>>
>>>> Do you have Tahiti LE in the office? It might be worth testing it to
>>>> see if it works. There were some issues with it in the past.
>>>>
>>>
>>> I used Tahiti XT [Device ID 6798], do you know the device id of Tahiti LE?
>>
>> No, I only know that Tahiti LE is Radeon HD 7870 XT. It was made by
>> Sapphire and Powercolor.
>>
> 
> OK, my card is Radeon HD 7970 XT. It works well. Do you know what kind of
> issues, anymore info?

See https://bugs.freedesktop.org/show_bug.cgi?id=60879 . The PCI ID is
0x679e.


-- 
Earthling Michel Dänzer               |               http://www.amd.com
Libre software enthusiast             |             Mesa and X developer
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