[PATCH 1/4] drm/amdgpu/mes: optimize compute loop handling

[PATCH 1/4] drm/amdgpu/mes: optimize compute loop handling

[Alex Deucher]

Break when we get to the end of the supported pipes
rather than continuing the loop.

Reviewed-by: Shaoyun.liu <Shaoyun.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
index 3b83880f9e2cc..10f14bf925778 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
@@ -132,7 +132,7 @@ int amdgpu_mes_init(struct amdgpu_device *adev)
 	for (i = 0; i < AMDGPU_MES_MAX_COMPUTE_PIPES; i++) {
 		/* use only 1st MEC pipes */
 		if (i >= adev->gfx.mec.num_pipe_per_mec)
-			continue;
+			break;
 		adev->mes.compute_hqd_mask[i] = 0xc;
 	}
 
-- 
2.48.1

[PATCH 2/4] drm/amdgpu/mes: enable compute pipes across all MEC

[Alex Deucher]

Enable pipes on both MECs for MES.

Fixes: 745f46b6a99f ("drm/amdgpu: enable mes v12 self test")
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
index 10f14bf925778..ac9b1708e20d8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
@@ -130,8 +130,7 @@ int amdgpu_mes_init(struct amdgpu_device *adev)
 	}
 
 	for (i = 0; i < AMDGPU_MES_MAX_COMPUTE_PIPES; i++) {
-		/* use only 1st MEC pipes */
-		if (i >= adev->gfx.mec.num_pipe_per_mec)
+		if (i >= (adev->gfx.mec.num_pipe_per_mec * adev->gfx.mec.num_mec))
 			break;
 		adev->mes.compute_hqd_mask[i] = 0xc;
 	}
-- 
2.48.1

[PATCH 3/4] drm/amdgpu/mes: drop MES 10.x leftovers

[Alex Deucher]

Leftover from MES bring up.  There is no production
MES support for MES 10.x.  The rest of the MES 10.x
code has already been removed so drop this.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 5 +----
 1 file changed, 1 insertion(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
index ac9b1708e20d8..fddec5d1f2444 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
@@ -136,11 +136,8 @@ int amdgpu_mes_init(struct amdgpu_device *adev)
 	}
 
 	for (i = 0; i < AMDGPU_MES_MAX_SDMA_PIPES; i++) {
-		if (amdgpu_ip_version(adev, SDMA0_HWIP, 0) <
-		    IP_VERSION(6, 0, 0))
-			adev->mes.sdma_hqd_mask[i] = i ? 0 : 0x3fc;
 		/* zero sdma_hqd_mask for non-existent engine */
-		else if (adev->sdma.num_instances == 1)
+		if (adev->sdma.num_instances == 1)
 			adev->mes.sdma_hqd_mask[i] = i ? 0 : 0xfc;
 		else
 			adev->mes.sdma_hqd_mask[i] = 0xfc;
-- 
2.48.1

[PATCH 4/4] drm/amdgpu/mes: clean up SDMA HQD loop

[Alex Deucher]

Follow the same logic as the other IP types.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 8 +++-----
 1 file changed, 3 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
index fddec5d1f2444..016af4e9c35fa 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
@@ -136,11 +136,9 @@ int amdgpu_mes_init(struct amdgpu_device *adev)
 	}
 
 	for (i = 0; i < AMDGPU_MES_MAX_SDMA_PIPES; i++) {
-		/* zero sdma_hqd_mask for non-existent engine */
-		if (adev->sdma.num_instances == 1)
-			adev->mes.sdma_hqd_mask[i] = i ? 0 : 0xfc;
-		else
-			adev->mes.sdma_hqd_mask[i] = 0xfc;
+		if (i >= adev->sdma.num_instances)
+			break;
+		adev->mes.sdma_hqd_mask[i] = 0xfc;
 	}
 
 	for (i = 0; i < AMDGPU_MAX_MES_PIPES; i++) {
-- 
2.48.1

RE: [PATCH 1/4] drm/amdgpu/mes: optimize compute loop handling

[Liang, Prike]

[Public]

Reviewed-by: Prike Liang <Prike.Liang@amd.com>

Regards,
      Prike

> -----Original Message-----
> From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Alex
> Deucher
> Sent: Thursday, March 20, 2025 3:09 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander <Alexander.Deucher@amd.com>; Liu, Shaoyun
> <Shaoyun.Liu@amd.com>
> Subject: [PATCH 1/4] drm/amdgpu/mes: optimize compute loop handling
>
> Break when we get to the end of the supported pipes rather than continuing the
> loop.
>
> Reviewed-by: Shaoyun.liu <Shaoyun.liu@amd.com>
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
> index 3b83880f9e2cc..10f14bf925778 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
> @@ -132,7 +132,7 @@ int amdgpu_mes_init(struct amdgpu_device *adev)
>       for (i = 0; i < AMDGPU_MES_MAX_COMPUTE_PIPES; i++) {
>               /* use only 1st MEC pipes */
>               if (i >= adev->gfx.mec.num_pipe_per_mec)
> -                     continue;
> +                     break;
>               adev->mes.compute_hqd_mask[i] = 0xc;
>       }
>
> --
> 2.48.1

RE: [PATCH 2/4] drm/amdgpu/mes: enable compute pipes across all MEC

[Liang, Prike]

[AMD Official Use Only - AMD Internal Distribution Only]

Reviewed-by: Prike Liang <Prike.Liang@amd.com>

Regards,
      Prike

> -----Original Message-----
> From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Alex
> Deucher
> Sent: Thursday, March 20, 2025 3:09 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander <Alexander.Deucher@amd.com>
> Subject: [PATCH 2/4] drm/amdgpu/mes: enable compute pipes across all MEC
>
> Enable pipes on both MECs for MES.
>
> Fixes: 745f46b6a99f ("drm/amdgpu: enable mes v12 self test")
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 3 +--
>  1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
> index 10f14bf925778..ac9b1708e20d8 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
> @@ -130,8 +130,7 @@ int amdgpu_mes_init(struct amdgpu_device *adev)
>       }
>
>       for (i = 0; i < AMDGPU_MES_MAX_COMPUTE_PIPES; i++) {
> -             /* use only 1st MEC pipes */
> -             if (i >= adev->gfx.mec.num_pipe_per_mec)
> +             if (i >= (adev->gfx.mec.num_pipe_per_mec * adev-
> >gfx.mec.num_mec))
>                       break;
>               adev->mes.compute_hqd_mask[i] = 0xc;
>       }
> --
> 2.48.1

RE: [PATCH 3/4] drm/amdgpu/mes: drop MES 10.x leftovers

[Liang, Prike]

[Public]

Acked-by: Prike Liang <Prike.Liang@amd.com>

Regards,
      Prike

> -----Original Message-----
> From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Alex
> Deucher
> Sent: Thursday, March 20, 2025 3:09 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander <Alexander.Deucher@amd.com>
> Subject: [PATCH 3/4] drm/amdgpu/mes: drop MES 10.x leftovers
>
> Leftover from MES bring up.  There is no production MES support for MES 10.x.
> The rest of the MES 10.x code has already been removed so drop this.
>
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 5 +----
>  1 file changed, 1 insertion(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
> index ac9b1708e20d8..fddec5d1f2444 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
> @@ -136,11 +136,8 @@ int amdgpu_mes_init(struct amdgpu_device *adev)
>       }
>
>       for (i = 0; i < AMDGPU_MES_MAX_SDMA_PIPES; i++) {
> -             if (amdgpu_ip_version(adev, SDMA0_HWIP, 0) <
> -                 IP_VERSION(6, 0, 0))
> -                     adev->mes.sdma_hqd_mask[i] = i ? 0 : 0x3fc;
>               /* zero sdma_hqd_mask for non-existent engine */
> -             else if (adev->sdma.num_instances == 1)
> +             if (adev->sdma.num_instances == 1)
>                       adev->mes.sdma_hqd_mask[i] = i ? 0 : 0xfc;
>               else
>                       adev->mes.sdma_hqd_mask[i] = 0xfc;
> --
> 2.48.1

Re: [PATCH 1/4] drm/amdgpu/mes: optimize compute loop handling

[Lazar, Lijo]

On 3/20/2025 12:38 AM, Alex Deucher wrote:
> Break when we get to the end of the supported pipes
> rather than continuing the loop.
> 
> Reviewed-by: Shaoyun.liu <Shaoyun.liu@amd.com>
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
> index 3b83880f9e2cc..10f14bf925778 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
> @@ -132,7 +132,7 @@ int amdgpu_mes_init(struct amdgpu_device *adev)
>  	for (i = 0; i < AMDGPU_MES_MAX_COMPUTE_PIPES; i++) {

Unless I'm not seeing something, why not just keep it i <
adev->gfx.mec.num_pipe_per_mec?

Thanks,
Lijo

>  		/* use only 1st MEC pipes */
>  		if (i >= adev->gfx.mec.num_pipe_per_mec)
> -			continue;
> +			break;
>  		adev->mes.compute_hqd_mask[i] = 0xc;
>  	}
>  

Re: [PATCH 2/4] drm/amdgpu/mes: enable compute pipes across all MEC

[Lazar, Lijo]

On 3/20/2025 12:38 AM, Alex Deucher wrote:
> Enable pipes on both MECs for MES.
> 
> Fixes: 745f46b6a99f ("drm/amdgpu: enable mes v12 self test")
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 3 +--
>  1 file changed, 1 insertion(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
> index 10f14bf925778..ac9b1708e20d8 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
> @@ -130,8 +130,7 @@ int amdgpu_mes_init(struct amdgpu_device *adev)
>  	}
>  
>  	for (i = 0; i < AMDGPU_MES_MAX_COMPUTE_PIPES; i++) {
> -		/* use only 1st MEC pipes */
> -		if (i >= adev->gfx.mec.num_pipe_per_mec)
> +		if (i >= (adev->gfx.mec.num_pipe_per_mec * adev->gfx.mec.num_mec))

Same comment as in patch 1.

Thanks,
Lijo

>  			break;
>  		adev->mes.compute_hqd_mask[i] = 0xc;
>  	}

RE: [PATCH 4/4] drm/amdgpu/mes: clean up SDMA HQD loop

[Liang, Prike]

[Public]

Reviewed-by: Prike Liang <Prike.Liang@amd.com>

Regards,
      Prike

> -----Original Message-----
> From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Alex
> Deucher
> Sent: Thursday, March 20, 2025 3:09 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander <Alexander.Deucher@amd.com>
> Subject: [PATCH 4/4] drm/amdgpu/mes: clean up SDMA HQD loop
>
> Follow the same logic as the other IP types.
>
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 8 +++-----
>  1 file changed, 3 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
> index fddec5d1f2444..016af4e9c35fa 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
> @@ -136,11 +136,9 @@ int amdgpu_mes_init(struct amdgpu_device *adev)
>       }
>
>       for (i = 0; i < AMDGPU_MES_MAX_SDMA_PIPES; i++) {
> -             /* zero sdma_hqd_mask for non-existent engine */
> -             if (adev->sdma.num_instances == 1)
> -                     adev->mes.sdma_hqd_mask[i] = i ? 0 : 0xfc;
> -             else
> -                     adev->mes.sdma_hqd_mask[i] = 0xfc;
> +             if (i >= adev->sdma.num_instances)
> +                     break;
> +             adev->mes.sdma_hqd_mask[i] = 0xfc;
>       }
>
>       for (i = 0; i < AMDGPU_MAX_MES_PIPES; i++) {
> --
> 2.48.1

RE: [PATCH 1/4] drm/amdgpu/mes: optimize compute loop handling

[Liang, Prike]

[Public]

> From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Lazar,
> Lijo
> Sent: Thursday, March 20, 2025 7:14 PM
> To: Deucher, Alexander <Alexander.Deucher@amd.com>; amd-
> gfx@lists.freedesktop.org
> Cc: Liu, Shaoyun <Shaoyun.Liu@amd.com>
> Subject: Re: [PATCH 1/4] drm/amdgpu/mes: optimize compute loop handling
>
>
>
> On 3/20/2025 12:38 AM, Alex Deucher wrote:
> > Break when we get to the end of the supported pipes rather than
> > continuing the loop.
> >
> > Reviewed-by: Shaoyun.liu <Shaoyun.liu@amd.com>
> > Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> > ---
> >  drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
> > index 3b83880f9e2cc..10f14bf925778 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
> > @@ -132,7 +132,7 @@ int amdgpu_mes_init(struct amdgpu_device *adev)
> >     for (i = 0; i < AMDGPU_MES_MAX_COMPUTE_PIPES; i++) {
>
> Unless I'm not seeing something, why not just keep it i <
> adev->gfx.mec.num_pipe_per_mec?
>
> Thanks,
> Lijo
>
This check way may benefit when the check case is adev->gfx.mec.num_pipe_per_mec < AMDGPU_MES_MAX_COMPUTE_PIPES; in this way it will reduce the later unused loop check.

Thanks,
Prike

> >             /* use only 1st MEC pipes */
> >             if (i >= adev->gfx.mec.num_pipe_per_mec)
> > -                   continue;
> > +                   break;
> >             adev->mes.compute_hqd_mask[i] = 0xc;
> >     }
> >

Re: [PATCH 1/4] drm/amdgpu/mes: optimize compute loop handling

[Alex Deucher]

On Thu, Mar 20, 2025 at 7:14 AM Lazar, Lijo <lijo.lazar@amd.com> wrote:
>
>
>
> On 3/20/2025 12:38 AM, Alex Deucher wrote:
> > Break when we get to the end of the supported pipes
> > rather than continuing the loop.
> >
> > Reviewed-by: Shaoyun.liu <Shaoyun.liu@amd.com>
> > Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> > ---
> >  drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
> > index 3b83880f9e2cc..10f14bf925778 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
> > @@ -132,7 +132,7 @@ int amdgpu_mes_init(struct amdgpu_device *adev)
> >       for (i = 0; i < AMDGPU_MES_MAX_COMPUTE_PIPES; i++) {
>
> Unless I'm not seeing something, why not just keep it i <
> adev->gfx.mec.num_pipe_per_mec?

AMDGPU_MES_MAX_COMPUTE_PIPES Is the size of the array and I think it
is aligned to the max supported by the firmware, so if we had
num_pipe_per_mec larger than that for some reason this would prevent
an overflow.

Alex

>
> Thanks,
> Lijo
>
> >               /* use only 1st MEC pipes */
> >               if (i >= adev->gfx.mec.num_pipe_per_mec)
> > -                     continue;
> > +                     break;
> >               adev->mes.compute_hqd_mask[i] = 0xc;
> >       }
> >
>

Re: [PATCH 2/4] drm/amdgpu/mes: enable compute pipes across all MEC

[Alex Deucher]

On Thu, Mar 20, 2025 at 7:15 AM Lazar, Lijo <lijo.lazar@amd.com> wrote:
>
>
>
> On 3/20/2025 12:38 AM, Alex Deucher wrote:
> > Enable pipes on both MECs for MES.
> >
> > Fixes: 745f46b6a99f ("drm/amdgpu: enable mes v12 self test")
> > Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> > ---
> >  drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 3 +--
> >  1 file changed, 1 insertion(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
> > index 10f14bf925778..ac9b1708e20d8 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
> > @@ -130,8 +130,7 @@ int amdgpu_mes_init(struct amdgpu_device *adev)
> >       }
> >
> >       for (i = 0; i < AMDGPU_MES_MAX_COMPUTE_PIPES; i++) {
> > -             /* use only 1st MEC pipes */
> > -             if (i >= adev->gfx.mec.num_pipe_per_mec)
> > +             if (i >= (adev->gfx.mec.num_pipe_per_mec * adev->gfx.mec.num_mec))
>
> Same comment as in patch 1.

This keeps the array access bounded.

Alex

>
> Thanks,
> Lijo
>
> >                       break;
> >               adev->mes.compute_hqd_mask[i] = 0xc;
> >       }
>

Re: [PATCH 1/4] drm/amdgpu/mes: optimize compute loop handling

[Lazar, Lijo]

On 3/20/2025 6:21 PM, Alex Deucher wrote:
> On Thu, Mar 20, 2025 at 7:14 AM Lazar, Lijo <lijo.lazar@amd.com> wrote:
>>
>>
>>
>> On 3/20/2025 12:38 AM, Alex Deucher wrote:
>>> Break when we get to the end of the supported pipes
>>> rather than continuing the loop.
>>>
>>> Reviewed-by: Shaoyun.liu <Shaoyun.liu@amd.com>
>>> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
>>> ---
>>>  drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 2 +-
>>>  1 file changed, 1 insertion(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
>>> index 3b83880f9e2cc..10f14bf925778 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
>>> @@ -132,7 +132,7 @@ int amdgpu_mes_init(struct amdgpu_device *adev)
>>>       for (i = 0; i < AMDGPU_MES_MAX_COMPUTE_PIPES; i++) {
>>
>> Unless I'm not seeing something, why not just keep it i <
>> adev->gfx.mec.num_pipe_per_mec?
> 
> AMDGPU_MES_MAX_COMPUTE_PIPES Is the size of the array and I think it
> is aligned to the max supported by the firmware, so if we had
> num_pipe_per_mec larger than that for some reason this would prevent
> an overflow.
> 

I think it should be kept the other way and array size should be fixed,
otherwise it hides a real problem.

Thanks,
Lijo

> Alex
> 
>>
>> Thanks,
>> Lijo
>>
>>>               /* use only 1st MEC pipes */
>>>               if (i >= adev->gfx.mec.num_pipe_per_mec)
>>> -                     continue;
>>> +                     break;
>>>               adev->mes.compute_hqd_mask[i] = 0xc;
>>>       }
>>>
>>

Re: [PATCH 1/4] drm/amdgpu/mes: optimize compute loop handling

[Alex Deucher]

On Thu, Mar 20, 2025 at 9:44 AM Lazar, Lijo <lijo.lazar@amd.com> wrote:
>
>
>
> On 3/20/2025 6:21 PM, Alex Deucher wrote:
> > On Thu, Mar 20, 2025 at 7:14 AM Lazar, Lijo <lijo.lazar@amd.com> wrote:
> >>
> >>
> >>
> >> On 3/20/2025 12:38 AM, Alex Deucher wrote:
> >>> Break when we get to the end of the supported pipes
> >>> rather than continuing the loop.
> >>>
> >>> Reviewed-by: Shaoyun.liu <Shaoyun.liu@amd.com>
> >>> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> >>> ---
> >>>  drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 2 +-
> >>>  1 file changed, 1 insertion(+), 1 deletion(-)
> >>>
> >>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
> >>> index 3b83880f9e2cc..10f14bf925778 100644
> >>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
> >>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
> >>> @@ -132,7 +132,7 @@ int amdgpu_mes_init(struct amdgpu_device *adev)
> >>>       for (i = 0; i < AMDGPU_MES_MAX_COMPUTE_PIPES; i++) {
> >>
> >> Unless I'm not seeing something, why not just keep it i <
> >> adev->gfx.mec.num_pipe_per_mec?
> >
> > AMDGPU_MES_MAX_COMPUTE_PIPES Is the size of the array and I think it
> > is aligned to the max supported by the firmware, so if we had
> > num_pipe_per_mec larger than that for some reason this would prevent
> > an overflow.
> >
>
> I think it should be kept the other way and array size should be fixed,
> otherwise it hides a real problem.

How about a dev_warn when we break out of the loop?  If we see that,
we can fix the array size or figure out why it's too large.

Alex

>
> Thanks,
> Lijo
>
> > Alex
> >
> >>
> >> Thanks,
> >> Lijo
> >>
> >>>               /* use only 1st MEC pipes */
> >>>               if (i >= adev->gfx.mec.num_pipe_per_mec)
> >>> -                     continue;
> >>> +                     break;
> >>>               adev->mes.compute_hqd_mask[i] = 0xc;
> >>>       }
> >>>
> >>
>

Re: [PATCH 1/4] drm/amdgpu/mes: optimize compute loop handling

[Lazar, Lijo]

On 3/20/2025 7:23 PM, Alex Deucher wrote:
> On Thu, Mar 20, 2025 at 9:44 AM Lazar, Lijo <lijo.lazar@amd.com> wrote:
>>
>>
>>
>> On 3/20/2025 6:21 PM, Alex Deucher wrote:
>>> On Thu, Mar 20, 2025 at 7:14 AM Lazar, Lijo <lijo.lazar@amd.com> wrote:
>>>>
>>>>
>>>>
>>>> On 3/20/2025 12:38 AM, Alex Deucher wrote:
>>>>> Break when we get to the end of the supported pipes
>>>>> rather than continuing the loop.
>>>>>
>>>>> Reviewed-by: Shaoyun.liu <Shaoyun.liu@amd.com>
>>>>> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
>>>>> ---
>>>>>  drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 2 +-
>>>>>  1 file changed, 1 insertion(+), 1 deletion(-)
>>>>>
>>>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
>>>>> index 3b83880f9e2cc..10f14bf925778 100644
>>>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
>>>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
>>>>> @@ -132,7 +132,7 @@ int amdgpu_mes_init(struct amdgpu_device *adev)
>>>>>       for (i = 0; i < AMDGPU_MES_MAX_COMPUTE_PIPES; i++) {
>>>>
>>>> Unless I'm not seeing something, why not just keep it i <
>>>> adev->gfx.mec.num_pipe_per_mec?
>>>
>>> AMDGPU_MES_MAX_COMPUTE_PIPES Is the size of the array and I think it
>>> is aligned to the max supported by the firmware, so if we had
>>> num_pipe_per_mec larger than that for some reason this would prevent
>>> an overflow.
>>>
>>
>> I think it should be kept the other way and array size should be fixed,
>> otherwise it hides a real problem.
> 
> How about a dev_warn when we break out of the loop?  If we see that,
> we can fix the array size or figure out why it's too large.
> 

Yes, that will do.

Thanks,
Lijo

> Alex
> 
>>
>> Thanks,
>> Lijo
>>
>>> Alex
>>>
>>>>
>>>> Thanks,
>>>> Lijo
>>>>
>>>>>               /* use only 1st MEC pipes */
>>>>>               if (i >= adev->gfx.mec.num_pipe_per_mec)
>>>>> -                     continue;
>>>>> +                     break;
>>>>>               adev->mes.compute_hqd_mask[i] = 0xc;
>>>>>       }
>>>>>
>>>>
>>