[PATCH 32/74] drm/amd/display: update dcn42b based on dcn42

[Wayne Lin <Wayne.Lin@amd.com>]

From: Charlene Liu <Charlene.Liu@amd.com>

Align DCN42B clocks and power gating with DCN42:
1. On DCN42, re-read DTBCLK while it is already enabled and turn it
   back on when the measured frequency drops below 590 MHz.
2. Align DCN42B HUBP/DPP power gating with DCN42 by disabling both.
3. Remove the unused DCN42B 300 MHz AC DCFCLK macro and the comment
   that described a wall-power floor. The function still only clamps
   a user force-min override to 200-600 MHz.

Cc: Gabe Teeger <gabe.teeger@amd.com>
Signed-off-by: Charlene Liu <Charlene.Liu@amd.com>
Signed-off-by: Wayne Lin <wayne.lin@amd.com>
---
 .../display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c  | 24 +++++++++----------
 .../dc/clk_mgr/dcn42b/dcn42b_clk_mgr.c        | 11 +++------
 .../dc/resource/dcn42b/dcn42b_resource.c      |  4 ++--
 3 files changed, 17 insertions(+), 22 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c
index 405145889ba2..d125ea196cb2 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c
@@ -258,21 +258,21 @@ void dcn42_update_clocks(struct clk_mgr *clk_mgr_base,
 			dcn42_smu_set_zstate_support(clk_mgr, DCN_ZSTATE_SUPPORT_DISALLOW);
 			clk_mgr_base->clks.zstate_support = new_clocks->zstate_support;
 		}
-		/* Only attempt to enable dtbclk if currently disabled AND new state requests it.
-		 * For dcn42b (no dtbclk hardware), init_clk_states sets dtbclk_en=false and
-		 * new_clocks->dtbclk_en should always be false, so this block never executes.
+		/* PMFW may stop dtbclk on idle, so re-read the actual frequency even when
+		 * clks.dtbclk_en is already set, and re-enable it if it has dropped.
 		 */
-		actual_dtbclk = dcn42_get_clock_freq_from_clkip(clk_mgr_base, clock_type_dtbclk);
-
-		if (new_clocks->dtbclk_en && actual_dtbclk < 590000) {
-
-			dcn42_update_clocks_update_dtb_dto(clk_mgr, context, new_clocks->ref_dtbclk_khz);
-			dcn42_smu_set_dtbclk(clk_mgr, true);
+		if (new_clocks->dtbclk_en) {
 			actual_dtbclk = dcn42_get_clock_freq_from_clkip(clk_mgr_base, clock_type_dtbclk);
 
-			if (actual_dtbclk > 590000) {
-				clk_mgr_base->clks.ref_dtbclk_khz = new_clocks->ref_dtbclk_khz;
-				clk_mgr_base->clks.dtbclk_en = new_clocks->dtbclk_en;
+			if (actual_dtbclk < 590000) {
+				dcn42_update_clocks_update_dtb_dto(clk_mgr, context, new_clocks->ref_dtbclk_khz);
+				dcn42_smu_set_dtbclk(clk_mgr, true);
+				actual_dtbclk = dcn42_get_clock_freq_from_clkip(clk_mgr_base, clock_type_dtbclk);
+
+				if (actual_dtbclk > 590000) {
+					clk_mgr_base->clks.ref_dtbclk_khz = new_clocks->ref_dtbclk_khz;
+					clk_mgr_base->clks.dtbclk_en = new_clocks->dtbclk_en;
+				}
 			}
 		}
 
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42b/dcn42b_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42b/dcn42b_clk_mgr.c
index 33f0099075c0..e18d705103ba 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42b/dcn42b_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42b/dcn42b_clk_mgr.c
@@ -393,18 +393,13 @@ uint32_t dcn42b_get_clock_freq_from_clkip(struct clk_mgr *clk_mgr_base, enum clo
 
 #define DCN42B_MIN_DCFCLK_MHZ 200
 #define DCN42B_MAX_DCFCLK_MHZ 600
-#define DCN42B_AC_MIN_DCFCLK_MHZ 300
 
 /*
  * dcn42b_update_clocks - DCN42B wrapper around dcn42_update_clocks.
  *
- * Establishes the DCN42B force-min-DCFCLK floor consumed by the shared
- * dcn42_update_clocks(), which applies it to new_clocks->dcfclk_khz:
- *   - a user override (dc->debug.force_min_dcfclk_mhz)
- *     wins, sanitized to the [200, 600] MHz supported range;
- *   - otherwise DCFCLK is floored at 300 MHz on wall power, and left
- *     unconstrained on battery.
- * dc->debug is restored afterwards so the override survives AC/DC transitions.
+ * Sanitizes the user force-min-DCFCLK override (dc->debug.force_min_dcfclk_mhz)
+ * to the [200, 600] MHz range supported by DCN42B before the shared
+ * dcn42_update_clocks() applies it to new_clocks->dcfclk_khz.
  */
 static void dcn42b_update_clocks(struct clk_mgr *clk_mgr_base,
 			struct dc_state *context,
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c
index 784cce09b89b..338c506588d9 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c
@@ -803,8 +803,8 @@ static const struct dc_debug_options debug_defaults_drv = {
 	.clock_trace = true,
 	.disable_pplib_clock_request = false,
 	.ignore_pg = false,
-	.disable_dpp_power_gate = false,
-	.disable_hubp_power_gate = false,
+	.disable_dpp_power_gate = true,
+	.disable_hubp_power_gate = true,
 	.disable_optc_power_gate = true,
 	.disable_dsc_power_gate = false,
 	.disable_dio_power_gate = true,
-- 
2.43.0