[PATCH 04/74] drm/amd/display: Skip UPSP programming when UPSP regs are absent

[Wayne Lin <Wayne.Lin@amd.com>]

From: Eric Bernstein <Eric.Bernstein@amd.com>

why:
DPP60 is shared by ASICs without a UPSP block. On those, UPSP register
offsets are 0 but masks may be non-zero, causing writes to address 0.

how:
Gate UPSP register access in DPP60 on the CNVC_UPSP_MODE register offset
instead of the field mask.

Cc: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Eric Bernstein <eric.bernstein@amd.com>
Signed-off-by: Wayne Lin <wayne.lin@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dpp/dcn60/dcn60_dpp.c      | 2 +-
 drivers/gpu/drm/amd/display/dc/dpp/dcn60/dcn60_dpp_dscl.c | 4 ++++
 2 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn60/dcn60_dpp.c b/drivers/gpu/drm/amd/display/dc/dpp/dcn60/dcn60_dpp.c
index 2ba8218e2ac2..dfdbc539ac42 100644
--- a/drivers/gpu/drm/amd/display/dc/dpp/dcn60/dcn60_dpp.c
+++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn60/dcn60_dpp.c
@@ -321,7 +321,7 @@ void dcn6_dpp_reset(struct dpp *dpp_base)
 	struct dcn60_dpp *dpp = TO_DCN60_DPP(dpp_base);
 
 	if (dpp->scl_data.upsp) {
-		if (dpp->tf_mask->UPSP_MODE) {
+		if (REG(CNVC_UPSP_MODE)) {
 			// Reset dpp registers used for upsp, lls
 			REG_WRITE(CNVC_UPSP_MODE, 0);
 			REG_WRITE(PRE_CSC_MODE, 0);
diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn60/dcn60_dpp_dscl.c b/drivers/gpu/drm/amd/display/dc/dpp/dcn60/dcn60_dpp_dscl.c
index d1a81e5616b3..b75eb2772799 100644
--- a/drivers/gpu/drm/amd/display/dc/dpp/dcn60/dcn60_dpp_dscl.c
+++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn60/dcn60_dpp_dscl.c
@@ -288,6 +288,10 @@ void dpp60_dscl_program_upsp(struct dpp *dpp_base,
 {
 	struct dcn60_dpp *dpp = TO_DCN60_DPP(dpp_base);
 
+	/* UPSP block is not present on all ASICs */
+	if (!REG(CNVC_UPSP_MODE))
+		return;
+
 	REG_SET_8(CNVC_UPSP_MODE, 0,
 			UPSP_MODE, dscl_prog_data->upsp_mode,
 			UPSP_V_NUM_TAPS, dscl_prog_data->upsp_v_num_taps,
-- 
2.43.0