[PATCH 40/74] drm/amd/display: enable DF C-state vote on DCN42B

[Wayne Lin <Wayne.Lin@amd.com>]

From: Charlene Liu <Charlene.Liu@amd.com>

why:
DCN42B shares the DCN42 hardware sequencer, so dcn42_prepare_bandwidth,
dcn42_hardware_release and dc_power_down_on_boot already try to vote DCN's
DF C-state policy through clk_mgr_funcs::notify_cstate_disable. The DCN42B
clk_mgr vtable never populated that callback, so every one of those call
sites was silently a no-op and DCN was never registered as a client of
PMFW's DF C-state arbiter on DCN42B. The PMFW side of the contract
(DALSMC_MSG_DfCstateDisable) is now releasing, so DCN42B can join the
arbiter instead of relying on the local DCHUBBUB watermark force selector.

how:
DCN42B already reuses the DCN42 SMU interface, so no new PMFW plumbing is
needed - only the DCN42B clk_mgr needs to opt in:

- hook dcn42_notify_cstate_disable into dcn42b_funcs
- clear dc_clocks.cstate_allow in dcn42b_init_clocks so D0 entry resyncs
  DAL with PMFW without sending a message, matching dcn42_init_clocks
- record the newly shared function in the dcn42b_clk_mgr.h reuse list

Also reword the DF C-state comment in dcn42_init_clocks, and its new DCN42B
copy. Comment only, no functional change.

No behaviour change for DCN42 or for DCN42B parts without SMU, since
dcn42_smu_set_df_cstate_disable() is a no-op when smu_present is false.

Cc: Gabe Teeger <gabe.teeger@amd.com>
Signed-off-by: Charlene Liu <Charlene.Liu@amd.com>
Signed-off-by: Wayne Lin <wayne.lin@amd.com>
---
 .../drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c   |  4 ++--
 .../drm/amd/display/dc/clk_mgr/dcn42b/dcn42b_clk_mgr.c | 10 ++++++++++
 .../drm/amd/display/dc/clk_mgr/dcn42b/dcn42b_clk_mgr.h |  1 +
 3 files changed, 13 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c
index d125ea196cb2..b1fbadd0d885 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c
@@ -628,8 +628,8 @@ DC_LOGGER_INIT(clk_mgr_base->ctx->logger);
 	 * DF C-state policy
 	 * D0 entry must NOT send a PMFW message, but must unconditionally clear
 	 * the cached vote so the next allow-side transition (prepare_bandwidth
-	 * or dc_power_down_on_boot) is guaranteed to issue a fresh
-	 * DfCstateDisable(Allow) and resync DAL with PMFW.
+	 * or dc_power_down_on_boot) always issues a fresh DfCstateDisable(Allow)
+	 * and resyncs DAL with PMFW.
 	 */
 	clk_mgr_base->clks.cstate_allow = false;
 
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42b/dcn42b_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42b/dcn42b_clk_mgr.c
index e18d705103ba..57291c10c917 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42b/dcn42b_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42b/dcn42b_clk_mgr.c
@@ -233,6 +233,15 @@ DC_LOGGER_INIT(clk_mgr_base->ctx->logger);
 
 	init_clk_states(clk_mgr_base);
 
+	/*
+	 * DF C-state policy
+	 * D0 entry must NOT send a PMFW message, but must unconditionally clear
+	 * the cached vote so the next allow-side transition (prepare_bandwidth
+	 * or dc_power_down_on_boot) always issues a fresh DfCstateDisable(Allow)
+	 * and resyncs DAL with PMFW.
+	 */
+	clk_mgr_base->clks.cstate_allow = false;
+
 	// to adjust dp_dto reference clock if ssc is enable otherwise to apply dprefclk
 	if (dcn42_is_spll_ssc_enabled(clk_mgr_base))
 		clk_mgr_base->dp_dto_source_clock_in_khz =
@@ -433,6 +442,7 @@ static struct clk_mgr_funcs dcn42b_funcs = {
 	.get_max_clock_khz = dcn42_get_max_clock_khz,
 	.get_dispclk_from_dentist = dcn42_get_dispclk_from_dentist,
 	.is_smu_present = dcn42_is_smu_present,
+	.notify_cstate_disable = dcn42_notify_cstate_disable,
 };
 
 typedef struct {
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42b/dcn42b_clk_mgr.h b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42b/dcn42b_clk_mgr.h
index 52ab87cdc7b6..ae871d43dbcf 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42b/dcn42b_clk_mgr.h
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42b/dcn42b_clk_mgr.h
@@ -13,6 +13,7 @@
  * - dcn42_get_dpm_table_from_smu (identical, only SMU calls)
  * - dcn42_are_clock_states_equal
  * - dcn42_enable_pme_wa
+ * - dcn42_notify_cstate_disable (same DALSMC DfCstateDisable message)
  * - dcn42_update_clocks_update_dpp_dto
  * - dcn42_update_clocks_update_dtb_dto
  * - dcn42_build_watermark_ranges
-- 
2.43.0