[PATCH 70/74] drm/amd/display: Get OPP heads and DPP pipes by stream in dc_resource

[Wayne Lin <Wayne.Lin@amd.com>]

From: Tony Cheng <tony.cheng@amd.com>

[Why]
The DC2 builders on dcn401 need every OPP head and DPP pipe of a stream,
across all of its ODM slices. Core2 walked a stream's DPP pipes with
its own helper. Pipe traversal belongs to dc_resource.

[How]
Add resource_get_opp_heads_for_stream and
resource_get_dpp_pipes_for_stream. Both find the OTG master of the
stream; the DPP pipes come slice by slice, in OPP head order. Core2
walks a stream's DPP pipes through dc_resource and drops
core2_next_dpp_pipe.

Cc: Jun Lei <jun.lei@amd.com>
Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Signed-off-by: Wayne Lin <wayne.lin@amd.com>
---
 .../gpu/drm/amd/display/dc/core/dc_resource.c | 32 +++++++++++++++++++
 .../gpu/drm/amd/display/dc/core2/dc_core2.c   | 27 +++++++++++-----
 drivers/gpu/drm/amd/display/dc/inc/resource.h | 18 +++++++++++
 3 files changed, 69 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 2240afde4089..7f770a43e1fe 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -2174,6 +2174,38 @@ int resource_get_dpp_pipes_for_opp_head(const struct pipe_ctx *opp_head,
 	return i;
 }
 
+int resource_get_opp_heads_for_stream(const struct dc_stream_state *stream,
+		struct resource_context *res_ctx,
+		struct pipe_ctx *opp_heads[MAX_PIPES])
+{
+	struct pipe_ctx *otg_master = resource_get_otg_master_for_stream(
+			res_ctx, stream);
+
+	if (!otg_master)
+		return 0;
+	return resource_get_opp_heads_for_otg_master(otg_master, res_ctx,
+			opp_heads);
+}
+
+int resource_get_dpp_pipes_for_stream(const struct dc_stream_state *stream,
+		struct resource_context *res_ctx,
+		struct pipe_ctx *dpp_pipes[MAX_PIPES])
+{
+	struct pipe_ctx *opp_heads[MAX_PIPES];
+	struct pipe_ctx *slice_pipes[MAX_PIPES];
+	int opp_head_count = resource_get_opp_heads_for_stream(stream, res_ctx,
+			opp_heads);
+	int i, j, slice_count, count = 0;
+
+	for (i = 0; i < opp_head_count; i++) {
+		slice_count = resource_get_dpp_pipes_for_opp_head(opp_heads[i],
+				res_ctx, slice_pipes);
+		for (j = 0; j < slice_count && count < MAX_PIPES; j++)
+			dpp_pipes[count++] = slice_pipes[j];
+	}
+	return count;
+}
+
 int resource_get_dpp_pipes_for_plane(const struct dc_plane_state *plane,
 		struct resource_context *res_ctx,
 		struct pipe_ctx *dpp_pipes[MAX_PIPES])
diff --git a/drivers/gpu/drm/amd/display/dc/core2/dc_core2.c b/drivers/gpu/drm/amd/display/dc/core2/dc_core2.c
index 33c52ef9b728..0e92c2e7a4e6 100644
--- a/drivers/gpu/drm/amd/display/dc/core2/dc_core2.c
+++ b/drivers/gpu/drm/amd/display/dc/core2/dc_core2.c
@@ -61,7 +61,8 @@ static struct pipe_ctx *core2_otg_master(struct dc_state *state)
 		return NULL;
 	for (i = 0; i < MAX_PIPES; i++) {
 		if (state->res_ctx.pipe_ctx[i].stream == state->streams[0] &&
-				!state->res_ctx.pipe_ctx[i].top_pipe)
+				!state->res_ctx.pipe_ctx[i].top_pipe &&
+				!state->res_ctx.pipe_ctx[i].prev_odm_pipe)
 			return &state->res_ctx.pipe_ctx[i];
 	}
 	return NULL;
@@ -160,10 +161,12 @@ static void core2_commit_enable_done(struct pipe_ctx *pipe)
 static void core2_commit_disable_done(struct dc *dc, struct pipe_ctx *pipe)
 {
 	struct dc_link *link = pipe->stream->link;
-	struct pipe_ctx *dpp_pipe;
+	struct pipe_ctx *dpp_pipes[MAX_PIPES];
+	int i, n = resource_get_dpp_pipes_for_stream(pipe->stream,
+			&dc->current_state->res_ctx, dpp_pipes);
 
-	for (dpp_pipe = pipe; dpp_pipe; dpp_pipe = dpp_pipe->bottom_pipe)
-		dpp_pipe->plane_res.hubp->power_gated = true;
+	for (i = 0; i < n; i++)
+		dpp_pipes[i]->plane_res.hubp->power_gated = true;
 	link->link_status.link_active = false;
 	link->phy_state.symclk_state = SYMCLK_OFF_TX_OFF;
 	pipe->stream->timing_adjust_pending = true;
@@ -314,11 +317,15 @@ static bool core2_update_state_supported(
  */
 static void core2_update_done(struct dc *dc, struct dc_state *context)
 {
+	struct pipe_ctx *dpp_pipes[MAX_PIPES];
 	struct pipe_ctx *pipe;
 	struct dc_plane_state *plane;
 	struct hubp *hubp;
+	int i, n = context->stream_count ? resource_get_dpp_pipes_for_stream(
+			context->streams[0], &context->res_ctx, dpp_pipes) : 0;
 
-	for (pipe = core2_otg_master(context); pipe; pipe = pipe->bottom_pipe) {
+	for (i = 0; i < n; i++) {
+		pipe = dpp_pipes[i];
 		if (!pipe->plane_state || !pipe->plane_res.hubp ||
 				!pipe->stream_res.opp)
 			return;
@@ -341,6 +348,8 @@ static void core2_update_state_execute(
 	struct dc *dc = scratch->dc;
 	struct dc_state *context = scratch->new_context;
 	struct pipe_ctx *pipe = core2_otg_master(context);
+	struct pipe_ctx *dpp_pipes[MAX_PIPES];
+	int i, n;
 
 	/*
 	 * The values DC1 computes into the context before it programs the
@@ -350,9 +359,11 @@ static void core2_update_state_execute(
 		return;
 	if (dc->res_pool->funcs->prepare_mcache_programming)
 		dc->res_pool->funcs->prepare_mcache_programming(dc, context);
-	for (; pipe; pipe = pipe->bottom_pipe)
-		pipe->plane_res.scl_data.lb_params.alpha_en =
-				pipe->plane_state->per_pixel_alpha;
+	n = resource_get_dpp_pipes_for_stream(pipe->stream, &context->res_ctx,
+			dpp_pipes);
+	for (i = 0; i < n; i++)
+		dpp_pipes[i]->plane_res.scl_data.lb_params.alpha_en =
+				dpp_pipes[i]->plane_state->per_pixel_alpha;
 
 	if (core2_build_and_run(dc, DCN_DECL_SEAMLESS_UPDATE, context) != DC_OK) {
 		ASSERT(false);
diff --git a/drivers/gpu/drm/amd/display/dc/inc/resource.h b/drivers/gpu/drm/amd/display/dc/inc/resource.h
index fbd874476aaf..5dc6173b3948 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/resource.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/resource.h
@@ -427,6 +427,24 @@ int resource_get_dpp_pipes_for_opp_head(const struct pipe_ctx *opp_head,
 		struct resource_context *res_ctx,
 		struct pipe_ctx *dpp_pipes[MAX_PIPES]);
 
+/*
+ * Get an array of OPP heads in opp_heads ordered with index low to high for
+ * the OTG master of stream in res_ctx.
+ * return - number of OPP heads in the array, 0 if stream has no OTG master.
+ */
+int resource_get_opp_heads_for_stream(const struct dc_stream_state *stream,
+		struct resource_context *res_ctx,
+		struct pipe_ctx *opp_heads[MAX_PIPES]);
+
+/*
+ * Get an array of DPP pipes in dpp_pipes for stream in res_ctx, ODM slice by
+ * slice, each slice top pipe first.
+ * return - number of DPP pipes in the array, 0 if stream has no OTG master.
+ */
+int resource_get_dpp_pipes_for_stream(const struct dc_stream_state *stream,
+		struct resource_context *res_ctx,
+		struct pipe_ctx *dpp_pipes[MAX_PIPES]);
+
 /*
  * Get an array of DPP pipes in dpp_pipes ordered with index low to high for
  * plane in res_ctx.
-- 
2.43.0