[RFC 00/10] amdgpu: implement Performance Monitor Counter support

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* [RFC 00/10] amdgpu: implement Performance Monitor Counter support
@ 2026-09-22  9:34 Zhu Lingshan
  2026-09-22  9:34 ` [RFC 01/10] drm/amdgpu: implement PMC ioctl framework Zhu Lingshan
                   ` (10 more replies)
  0 siblings, 11 replies; 23+ messages in thread
From: Zhu Lingshan @ 2026-09-22  9:34 UTC (permalink / raw)
  To: Alexander.Deucher, felix.kuehling; +Cc: Ray.Huang, amd-gfx, Zhu Lingshan

This series implements PMC support for amdgpu. Including two parts:
1) PMC Enablement
2) Profiler Reservation

The user space should take the reservation, then set PMC.

This series depends on and used new helper introduced in
another series:
https://lists.freedesktop.org/archives/amd-gfx/2026-August/151692.html

Please help Review

Thanks!

Zhu Lingshan (10):
  drm/amdgpu: implement PMC ioctl framework
  drm/amdgpu: add device-wide PMC config
  drm/amdgpu: introduce PMC ioctl handler
  drm/amdgpu: implement reservation mechanism for PMC
  drm/amdgpu: set device-wide PMC enablement indicator
  drm/amdgpu: GFX11: set mqd->perfcount from mqd_prop
  drm/amdgpu: GFX12: set mqd->perfcount from mqd_prop
  drm/amdgpu: GFX12.1: set mqd->perfcount from mqd_prop
  drm/amdgpu: implement device PMC handler
  drm/amdgpu: set userq perf state before publish it

 drivers/gpu/drm/amd/amdgpu/Makefile          |   2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu.h          |   8 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c   |   3 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c      |   4 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h      |   6 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_profiler.c | 166 +++++++++++++++++++
 drivers/gpu/drm/amd/amdgpu/amdgpu_profiler.h |  38 +++++
 drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c    |  95 ++++++++++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h    |   2 +
 drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c       |  11 ++
 drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c       |  11 ++
 drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c       |  11 ++
 include/uapi/drm/amdgpu_drm.h                |  36 ++++
 13 files changed, 390 insertions(+), 3 deletions(-)
 create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_profiler.c
 create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_profiler.h

-- 
2.55.0


^ permalink raw reply	[flat|nested] 23+ messages in thread

* [RFC 01/10] drm/amdgpu: implement PMC ioctl framework
  2026-09-22  9:34 [RFC 00/10] amdgpu: implement Performance Monitor Counter support Zhu Lingshan
@ 2026-09-22  9:34 ` Zhu Lingshan
  2026-09-23 14:17   ` James Zhu
  2026-09-22  9:34 ` [RFC 02/10] drm/amdgpu: add device-wide PMC config Zhu Lingshan
                   ` (9 subsequent siblings)
  10 siblings, 1 reply; 23+ messages in thread
From: Zhu Lingshan @ 2026-09-22  9:34 UTC (permalink / raw)
  To: Alexander.Deucher, felix.kuehling; +Cc: Ray.Huang, amd-gfx, Zhu Lingshan

This commit implements basic ioctl framework for PMC,
including basic operations.

This commit also implements AMDGPU_PROFILER_OP_VERSION
which report profiler version to the user space.

Signed-off-by: Zhu Lingshan <lingshan.zhu@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/Makefile          |  2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c      |  2 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_profiler.c | 44 ++++++++++++++++++++
 drivers/gpu/drm/amd/amdgpu/amdgpu_profiler.h | 33 +++++++++++++++
 include/uapi/drm/amdgpu_drm.h                | 36 ++++++++++++++++
 5 files changed, 116 insertions(+), 1 deletion(-)
 create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_profiler.c
 create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_profiler.h

diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile
index 6fb0a913e33b..d7db69e9d6a0 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -72,7 +72,7 @@ amdgpu-y += amdgpu_device.o amdgpu_reg_access.o amdgpu_doorbell_mgr.o amdgpu_kms
 	amdgpu_eeprom.o amdgpu_mca.o amdgpu_psp_ta.o amdgpu_lsdma.o amdgpu_lockdep.o \
 	amdgpu_ring_mux.o amdgpu_xcp.o amdgpu_seq64.o amdgpu_dev_coredump.o \
 	amdgpu_cper.o amdgpu_userq_fence.o amdgpu_eviction_fence.o amdgpu_ip.o \
-	amdgpu_wb.o amdgpu_cwsr.o amdgpu_events.o
+	amdgpu_wb.o amdgpu_cwsr.o amdgpu_events.o amdgpu_profiler.o
 
 amdgpu-$(CONFIG_PROC_FS) += amdgpu_fdinfo.o
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 7c473f60bd28..a98c4a47e196 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -55,6 +55,7 @@
 #include "amdgpu_cwsr.h"
 #include "amdgpu_userq_fence.h"
 #include "../amdxcp/amdgpu_xcp_drv.h"
+#include "amdgpu_profiler.h"
 
 /*
  * KMS wrapper.
@@ -3096,6 +3097,7 @@ const struct drm_ioctl_desc amdgpu_ioctls_kms[] = {
 	DRM_IOCTL_DEF_DRV(AMDGPU_USERQ_WAIT, amdgpu_userq_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
 	DRM_IOCTL_DEF_DRV(AMDGPU_GEM_LIST_HANDLES, amdgpu_gem_list_handles_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
 	DRM_IOCTL_DEF_DRV(AMDGPU_PROC_OPTIONS, amdgpu_proc_options_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
+	DRM_IOCTL_DEF_DRV(AMDGPU_PROFILER, amdgpu_profiler_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
 };
 
 static const struct drm_driver amdgpu_kms_driver = {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_profiler.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_profiler.c
new file mode 100644
index 000000000000..04902696adab
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_profiler.c
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright 2026 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#include <linux/errno.h>
+#include <drm/amdgpu_drm.h>
+#include "amdgpu_profiler.h"
+
+int amdgpu_profiler_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
+{
+	struct drm_amdgpu_profiler_args *args = data;
+
+	switch (args->op) {
+	case AMDGPU_PROFILER_OP_VERSION:
+		args->version = AMDGPU_PROFILER_VERSION_NUM;
+		return 0;
+	case AMDGPU_PROFILER_OP_RESERVE:
+		return -EOPNOTSUPP;
+	case AMDGPU_PROFILER_OP_PMC:
+		return -EOPNOTSUPP;
+	default:
+		return -EINVAL;
+	}
+}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_profiler.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_profiler.h
new file mode 100644
index 000000000000..c27b5f9b3ff0
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_profiler.h
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright 2026 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef __AMDGPU_PROFILER_H__
+#define __AMDGPU_PROFILER_H__
+
+#include <drm/drm_device.h>
+#include <drm/drm_file.h>
+
+int amdgpu_profiler_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
+
+#endif /* __AMDGPU_PROFILER_H__ */
diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
index 9222be9a6d2a..acc63804ba8c 100644
--- a/include/uapi/drm/amdgpu_drm.h
+++ b/include/uapi/drm/amdgpu_drm.h
@@ -60,6 +60,7 @@ extern "C" {
 #define DRM_AMDGPU_GEM_LIST_HANDLES	0x19
 #define DRM_AMDGPU_PROC_OPTIONS		0x1A
 #define DRM_AMDGPU_CWSR			0x1B
+#define DRM_AMDGPU_PROFILER		0x1C
 
 #define DRM_IOCTL_AMDGPU_GEM_CREATE	DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create)
 #define DRM_IOCTL_AMDGPU_GEM_MMAP	DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap)
@@ -83,6 +84,7 @@ extern "C" {
 #define DRM_IOCTL_AMDGPU_GEM_LIST_HANDLES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_LIST_HANDLES, struct drm_amdgpu_gem_list_handles)
 #define DRM_IOCTL_AMDGPU_PROC_OPTIONS	DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_PROC_OPTIONS, struct drm_amdgpu_proc_options)
 #define DRM_IOCTL_AMDGPU_CWSR	DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CWSR, union drm_amdgpu_cwsr)
+#define DRM_IOCTL_AMDGPU_PROFILER	DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_PROFILER, struct drm_amdgpu_profiler_args)
 
 /**
  * DOC: memory domains
@@ -1809,6 +1811,40 @@ struct drm_amdgpu_proc_options {
 	} kfd_sigbus_delay;
 };
 
+#define AMDGPU_PROFILER_VERSION_NUM	1
+
+enum amdgpu_profiler_ops {
+	AMDGPU_PROFILER_OP_VERSION = 1,
+	AMDGPU_PROFILER_OP_RESERVE = 2,
+	AMDGPU_PROFILER_OP_PMC = 3,
+};
+
+enum amdgpu_profiler_reserve_ops {
+	/* release the device resertaion, only the reservation owner do this */
+	AMDGPU_PROFILER_RELEASE = 0,
+	/* reserve the device profiler */
+	AMDGPU_PROFILER_RESERVE = 1,
+	/* Clear the device profiler reservation, in case the reservation
+	 * owner can no longer release the reservation(e.g., it crashes),
+	 * This operation does not take the reseration nor touch profielr state
+	 */
+	AMDGPU_PROFILER_CLEAR_RESERVATION = 2,
+};
+
+struct drm_amdgpu_profiler_args {
+	/* enum amdgpu_profiler_ops */
+	__u8 op;
+	__u8 pad[3];
+	union {
+		/* AMDGPU_PROFILER_OP_RESERVE: enum amdgpu_profiler_reserve_ops */
+		__u8 reserve;
+		/* AMDGPU_PROFILER_OP_PMC: 1 enable PMC, 0 disable PMC */
+		__u8 perfcount_enable;
+		/* AMDGPU_PROFILER_OP_VERSION: AMDGPU_PROFILER_VERSION_NUM */
+		__u32 version;
+	};
+};
+
 #if defined(__cplusplus)
 }
 #endif
-- 
2.55.0


^ permalink raw reply related	[flat|nested] 23+ messages in thread

* [RFC 02/10] drm/amdgpu: add device-wide PMC config
  2026-09-22  9:34 [RFC 00/10] amdgpu: implement Performance Monitor Counter support Zhu Lingshan
  2026-09-22  9:34 ` [RFC 01/10] drm/amdgpu: implement PMC ioctl framework Zhu Lingshan
@ 2026-09-22  9:34 ` Zhu Lingshan
  2026-09-23 14:13   ` James Zhu
  2026-09-22  9:34 ` [RFC 03/10] drm/amdgpu: introduce PMC ioctl handler Zhu Lingshan
                   ` (8 subsequent siblings)
  10 siblings, 1 reply; 23+ messages in thread
From: Zhu Lingshan @ 2026-09-22  9:34 UTC (permalink / raw)
  To: Alexander.Deucher, felix.kuehling; +Cc: Ray.Huang, amd-gfx, Zhu Lingshan

This commit implements a device-wide PMC config
for amdgpu, which including the profiling owner,
and the profiling enablement indicator.

Signed-off-by: Zhu Lingshan <lingshan.zhu@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h        | 8 ++++++++
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 3 +++
 2 files changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 8eff6b9ebe81..45897dca802f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -620,6 +620,12 @@ enum amdgpu_enforce_isolation_mode {
 	AMDGPU_ENFORCE_ISOLATION_NO_CLEANER_SHADER = 3,
 };
 
+struct amdgpu_pmc_profiler {
+	struct mutex		lock;
+	struct drm_file		*owner;
+	bool			enable;
+};
+
 struct amdgpu_device {
 	struct device			*dev;
 	struct pci_dev			*pdev;
@@ -818,6 +824,8 @@ struct amdgpu_device {
 	 */
 	struct xarray userq_doorbell_xa;
 
+	struct amdgpu_pmc_profiler	pmc_profiler;
+
 	/* df */
 	struct amdgpu_df                df;
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index c924a55fd16f..74ed42e53264 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -3673,6 +3673,7 @@ int amdgpu_device_init(struct amdgpu_device *adev,
 	mutex_init(&adev->pm.stable_pstate_ctx_lock);
 	mutex_init(&adev->benchmark_mutex);
 	mutex_init(&adev->gfx.reset_sem_mutex);
+	mutex_init(&adev->pmc_profiler.lock);
 
 	/* Associate locks with lockdep classes for ordering validation */
 	amdgpu_lockdep_set_class(adev);
@@ -4244,6 +4245,8 @@ void amdgpu_device_fini_sw(struct amdgpu_device *adev)
 	kfree(adev->pci_state);
 	kfree(adev->pcie_reset_ctx.swds_pcistate);
 	kfree(adev->pcie_reset_ctx.swus_pcistate);
+
+	mutex_destroy(&adev->pmc_profiler.lock);
 }
 
 /**
-- 
2.55.0


^ permalink raw reply related	[flat|nested] 23+ messages in thread

* [RFC 03/10] drm/amdgpu: introduce PMC ioctl handler
  2026-09-22  9:34 [RFC 00/10] amdgpu: implement Performance Monitor Counter support Zhu Lingshan
  2026-09-22  9:34 ` [RFC 01/10] drm/amdgpu: implement PMC ioctl framework Zhu Lingshan
  2026-09-22  9:34 ` [RFC 02/10] drm/amdgpu: add device-wide PMC config Zhu Lingshan
@ 2026-09-22  9:34 ` Zhu Lingshan
  2026-09-22  9:34 ` [RFC 04/10] drm/amdgpu: implement reservation mechanism for PMC Zhu Lingshan
                   ` (7 subsequent siblings)
  10 siblings, 0 replies; 23+ messages in thread
From: Zhu Lingshan @ 2026-09-22  9:34 UTC (permalink / raw)
  To: Alexander.Deucher, felix.kuehling; +Cc: Ray.Huang, amd-gfx, Zhu Lingshan

This commit introduces ioctl handler for PMC.

In this commit, the handler only performs
basic checkings, including permission and whether
user queues are enabled.

Signed-off-by: Zhu Lingshan <lingshan.zhu@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_profiler.c | 28 +++++++++++++++++++-
 1 file changed, 27 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_profiler.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_profiler.c
index 04902696adab..feff37279575 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_profiler.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_profiler.c
@@ -23,9 +23,35 @@
  */
 
 #include <linux/errno.h>
+#include <linux/capability.h>
 #include <drm/amdgpu_drm.h>
+#include "amdgpu.h"
+#include "amdgpu_userq.h"
 #include "amdgpu_profiler.h"
 
+static int amdgpu_profiler_check_access(struct drm_device *dev)
+{
+	if (!perfmon_capable())
+		return -EPERM;
+
+	if (!amdgpu_userq_enabled(dev))
+		return -EOPNOTSUPP;
+
+	return 0;
+}
+
+static int amdgpu_profiler_pmc(struct drm_device *dev, struct drm_file *filp,
+			       bool enable)
+{
+	int ret;
+
+	ret = amdgpu_profiler_check_access(dev);
+	if (ret)
+		return ret;
+
+	return -EOPNOTSUPP;
+}
+
 int amdgpu_profiler_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
 {
 	struct drm_amdgpu_profiler_args *args = data;
@@ -37,7 +63,7 @@ int amdgpu_profiler_ioctl(struct drm_device *dev, void *data, struct drm_file *f
 	case AMDGPU_PROFILER_OP_RESERVE:
 		return -EOPNOTSUPP;
 	case AMDGPU_PROFILER_OP_PMC:
-		return -EOPNOTSUPP;
+		return amdgpu_profiler_pmc(dev, filp, args->perfcount_enable);
 	default:
 		return -EINVAL;
 	}
-- 
2.55.0


^ permalink raw reply related	[flat|nested] 23+ messages in thread

* [RFC 04/10] drm/amdgpu: implement reservation mechanism for PMC
  2026-09-22  9:34 [RFC 00/10] amdgpu: implement Performance Monitor Counter support Zhu Lingshan
                   ` (2 preceding siblings ...)
  2026-09-22  9:34 ` [RFC 03/10] drm/amdgpu: introduce PMC ioctl handler Zhu Lingshan
@ 2026-09-22  9:34 ` Zhu Lingshan
  2026-09-22  9:34 ` [RFC 05/10] drm/amdgpu: set device-wide PMC enablement indicator Zhu Lingshan
                   ` (6 subsequent siblings)
  10 siblings, 0 replies; 23+ messages in thread
From: Zhu Lingshan @ 2026-09-22  9:34 UTC (permalink / raw)
  To: Alexander.Deucher, felix.kuehling; +Cc: Ray.Huang, amd-gfx, Zhu Lingshan

This commit implements reserving (take the profiling ownership)
and releasing (release the profiling ownership) of PMC.

A reservation can also be cleared by AMDGPU_PROFILER_CLEAR_RESERVATION
in case the owner can no longer release it, e.g., it crashes.

Releasing is separated from reserving path by design,
because the ownership needs to be kept during set_perfcount
to avoid racings.

Signed-off-by: Zhu Lingshan <lingshan.zhu@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c      |  1 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_profiler.c | 73 +++++++++++++++++++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_profiler.h |  3 +
 3 files changed, 76 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index a98c4a47e196..3dc563a64639 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -2988,6 +2988,7 @@ static int amdgpu_drm_release(struct inode *inode, struct file *filp)
 		amdgpu_evf_mgr_flush_suspend(&fpriv->evf_mgr);
 		amdgpu_userq_mgr_fini(&fpriv->userq_mgr);
 		amdgpu_evf_mgr_fini(&fpriv->evf_mgr);
+		amdgpu_profiler_release_device(drm_to_adev(dev), file_priv);
 		drm_dev_exit(idx);
 	}
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_profiler.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_profiler.c
index feff37279575..6464af0d1b10 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_profiler.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_profiler.c
@@ -29,6 +29,54 @@
 #include "amdgpu_userq.h"
 #include "amdgpu_profiler.h"
 
+static int amdgpu_profiler_reserve_device(struct amdgpu_device *adev,
+					  struct drm_file *filp)
+{
+	int ret;
+
+	mutex_lock(&adev->pmc_profiler.lock);
+
+	if (!adev->pmc_profiler.owner) {
+		adev->pmc_profiler.owner = filp;
+		ret = 0;
+	} else if (adev->pmc_profiler.owner == filp)
+		ret = -EALREADY;
+	else
+		ret = -EPERM;
+
+	mutex_unlock(&adev->pmc_profiler.lock);
+
+	return ret;
+}
+
+int amdgpu_profiler_release_device(struct amdgpu_device *adev,
+				   struct drm_file *filp)
+{
+	int ret;
+
+	mutex_lock(&adev->pmc_profiler.lock);
+
+	if (adev->pmc_profiler.owner == filp) {
+		adev->pmc_profiler.owner = NULL;
+		ret = 0;
+	} else
+		ret = -EPERM;
+
+	mutex_unlock(&adev->pmc_profiler.lock);
+
+	return ret;
+}
+
+/* Clear the reservation in case the owner that can no longer release
+ * the device, this function does not take the reserveion, nor touch the PMC state.
+ */
+static void amdgpu_profiler_clear_reservation(struct amdgpu_device *adev)
+{
+	mutex_lock(&adev->pmc_profiler.lock);
+	adev->pmc_profiler.owner = NULL;
+	mutex_unlock(&adev->pmc_profiler.lock);
+}
+
 static int amdgpu_profiler_check_access(struct drm_device *dev)
 {
 	if (!perfmon_capable())
@@ -40,6 +88,29 @@ static int amdgpu_profiler_check_access(struct drm_device *dev)
 	return 0;
 }
 
+static int amdgpu_profiler_reserve(struct drm_device *dev, struct drm_file *filp,
+				   u8 reserve)
+{
+	struct amdgpu_device *adev = drm_to_adev(dev);
+	int ret;
+
+	ret = amdgpu_profiler_check_access(dev);
+	if (ret)
+		return ret;
+
+	switch (reserve) {
+	case AMDGPU_PROFILER_RELEASE:
+		return amdgpu_profiler_release_device(adev, filp);
+	case AMDGPU_PROFILER_RESERVE:
+		return amdgpu_profiler_reserve_device(adev, filp);
+	case AMDGPU_PROFILER_CLEAR_RESERVATION:
+		amdgpu_profiler_clear_reservation(adev);
+		return 0;
+	default:
+		return -EINVAL;
+	}
+}
+
 static int amdgpu_profiler_pmc(struct drm_device *dev, struct drm_file *filp,
 			       bool enable)
 {
@@ -61,7 +132,7 @@ int amdgpu_profiler_ioctl(struct drm_device *dev, void *data, struct drm_file *f
 		args->version = AMDGPU_PROFILER_VERSION_NUM;
 		return 0;
 	case AMDGPU_PROFILER_OP_RESERVE:
-		return -EOPNOTSUPP;
+		return amdgpu_profiler_reserve(dev, filp, args->reserve);
 	case AMDGPU_PROFILER_OP_PMC:
 		return amdgpu_profiler_pmc(dev, filp, args->perfcount_enable);
 	default:
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_profiler.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_profiler.h
index c27b5f9b3ff0..048ce84f0ef2 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_profiler.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_profiler.h
@@ -28,6 +28,9 @@
 #include <drm/drm_device.h>
 #include <drm/drm_file.h>
 
+struct amdgpu_device;
+
+int amdgpu_profiler_release_device(struct amdgpu_device *adev, struct drm_file *filp);
 int amdgpu_profiler_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
 
 #endif /* __AMDGPU_PROFILER_H__ */
-- 
2.55.0


^ permalink raw reply related	[flat|nested] 23+ messages in thread

* [RFC 05/10] drm/amdgpu: set device-wide PMC enablement indicator
  2026-09-22  9:34 [RFC 00/10] amdgpu: implement Performance Monitor Counter support Zhu Lingshan
                   ` (3 preceding siblings ...)
  2026-09-22  9:34 ` [RFC 04/10] drm/amdgpu: implement reservation mechanism for PMC Zhu Lingshan
@ 2026-09-22  9:34 ` Zhu Lingshan
  2026-09-22  9:34 ` [RFC 06/10] drm/amdgpu: GFX11: set mqd->perfcount from mqd_prop Zhu Lingshan
                   ` (5 subsequent siblings)
  10 siblings, 0 replies; 23+ messages in thread
From: Zhu Lingshan @ 2026-09-22  9:34 UTC (permalink / raw)
  To: Alexander.Deucher, felix.kuehling; +Cc: Ray.Huang, amd-gfx, Zhu Lingshan

This commit introduces a new function amdgpu_profiler_set_perfcount
which sets the device-wide PMC enablement indicator.

Signed-off-by: Zhu Lingshan <lingshan.zhu@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c      |  1 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_profiler.c | 23 +++++++++++++++++++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_profiler.h |  2 ++
 3 files changed, 25 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 3dc563a64639..5b86fa50a95e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -2988,6 +2988,7 @@ static int amdgpu_drm_release(struct inode *inode, struct file *filp)
 		amdgpu_evf_mgr_flush_suspend(&fpriv->evf_mgr);
 		amdgpu_userq_mgr_fini(&fpriv->userq_mgr);
 		amdgpu_evf_mgr_fini(&fpriv->evf_mgr);
+		amdgpu_profiler_set_perfcount(drm_to_adev(dev), file_priv, false);
 		amdgpu_profiler_release_device(drm_to_adev(dev), file_priv);
 		drm_dev_exit(idx);
 	}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_profiler.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_profiler.c
index 6464af0d1b10..254fb8d77d80 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_profiler.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_profiler.c
@@ -77,6 +77,27 @@ static void amdgpu_profiler_clear_reservation(struct amdgpu_device *adev)
 	mutex_unlock(&adev->pmc_profiler.lock);
 }
 
+int amdgpu_profiler_set_perfcount(struct amdgpu_device *adev,
+				  struct drm_file *filp, bool enable)
+{
+	int ret;
+
+	mutex_lock(&adev->pmc_profiler.lock);
+
+	if (adev->pmc_profiler.owner == filp) {
+		/* set device-wide PMC enablement bit,
+		 * new created queues inherit it.
+		 */
+		adev->pmc_profiler.enable = enable;
+		ret = 0;
+	} else
+		ret = -EBUSY;
+
+	mutex_unlock(&adev->pmc_profiler.lock);
+
+	return ret;
+}
+
 static int amdgpu_profiler_check_access(struct drm_device *dev)
 {
 	if (!perfmon_capable())
@@ -120,7 +141,7 @@ static int amdgpu_profiler_pmc(struct drm_device *dev, struct drm_file *filp,
 	if (ret)
 		return ret;
 
-	return -EOPNOTSUPP;
+	return amdgpu_profiler_set_perfcount(drm_to_adev(dev), filp, enable);
 }
 
 int amdgpu_profiler_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_profiler.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_profiler.h
index 048ce84f0ef2..532aa7881191 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_profiler.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_profiler.h
@@ -30,6 +30,8 @@
 
 struct amdgpu_device;
 
+int amdgpu_profiler_set_perfcount(struct amdgpu_device *adev, struct drm_file *filp,
+				  bool enable);
 int amdgpu_profiler_release_device(struct amdgpu_device *adev, struct drm_file *filp);
 int amdgpu_profiler_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
 
-- 
2.55.0


^ permalink raw reply related	[flat|nested] 23+ messages in thread

* [RFC 06/10] drm/amdgpu: GFX11: set mqd->perfcount from mqd_prop
  2026-09-22  9:34 [RFC 00/10] amdgpu: implement Performance Monitor Counter support Zhu Lingshan
                   ` (4 preceding siblings ...)
  2026-09-22  9:34 ` [RFC 05/10] drm/amdgpu: set device-wide PMC enablement indicator Zhu Lingshan
@ 2026-09-22  9:34 ` Zhu Lingshan
  2026-09-22  9:34 ` [RFC 07/10] drm/amdgpu: GFX12: " Zhu Lingshan
                   ` (4 subsequent siblings)
  10 siblings, 0 replies; 23+ messages in thread
From: Zhu Lingshan @ 2026-09-22  9:34 UTC (permalink / raw)
  To: Alexander.Deucher, felix.kuehling; +Cc: Ray.Huang, amd-gfx, Zhu Lingshan

This commit implements a new callback set_mqd_perfcount
in struct amdgpu_mqd. This callback helps setting
mqd->compute_perfcount_enable from amdgpu_mqd_prop->perfcount_enable.

This is a per-IP callback and it is NULL if an IP does not
support PMC.

This commit also implements set_mqd_perfcount for GFX11.

Signed-off-by: Zhu Lingshan <lingshan.zhu@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h |  6 ++++++
 drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c  | 11 +++++++++++
 2 files changed, 17 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
index 7a5499ec1171..f7ae3d5484da 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
@@ -479,12 +479,18 @@ struct amdgpu_mqd_prop {
 	uint64_t ctx_save_area_addr;
 	uint32_t ctx_save_area_size;
 	uint32_t ctl_stack_size;
+	/* PMC compute_perfcount_enable that programmed into this queue's MQD */
+	bool perfcount_enable;
 };
 
 struct amdgpu_mqd {
 	unsigned mqd_size;
 	int (*init_mqd)(struct amdgpu_device *adev, void *mqd,
 			struct amdgpu_mqd_prop *p);
+	/* Per-IP callback to set compute_perfcount_enable,
+	 * NULL when this IP's MQD has no perfcount_enable field.
+	 */
+	void (*set_mqd_perfcount)(void *mqd, struct amdgpu_mqd_prop *p);
 };
 
 /*
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
index 254a72f26ec5..252a1096b4a0 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
@@ -4323,6 +4323,7 @@ static int gfx_v11_0_compute_mqd_init(struct amdgpu_device *adev, void *m,
 
 	mqd->header = 0xC0310800;
 	mqd->compute_pipelinestat_enable = 0x00000001;
+	mqd->compute_perfcount_enable = prop->perfcount_enable;
 	mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
 	mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
 	mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
@@ -4459,6 +4460,14 @@ static int gfx_v11_0_compute_mqd_init(struct amdgpu_device *adev, void *m,
 	return 0;
 }
 
+static void gfx_v11_0_compute_mqd_set_perfcount(void *m,
+						struct amdgpu_mqd_prop *prop)
+{
+	struct v11_compute_mqd *mqd = m;
+
+	mqd->compute_perfcount_enable = prop->perfcount_enable;
+}
+
 static int gfx_v11_0_kiq_init_register(struct amdgpu_ring *ring)
 {
 	struct amdgpu_device *adev = ring->adev;
@@ -7263,6 +7272,8 @@ static void gfx_v11_0_set_mqd_funcs(struct amdgpu_device *adev)
 		sizeof(struct v11_compute_mqd);
 	adev->mqds[AMDGPU_HW_IP_COMPUTE].init_mqd =
 		gfx_v11_0_compute_mqd_init;
+	adev->mqds[AMDGPU_HW_IP_COMPUTE].set_mqd_perfcount =
+		gfx_v11_0_compute_mqd_set_perfcount;
 }
 
 static void gfx_v11_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev,
-- 
2.55.0


^ permalink raw reply related	[flat|nested] 23+ messages in thread

* [RFC 07/10] drm/amdgpu: GFX12: set mqd->perfcount from mqd_prop
  2026-09-22  9:34 [RFC 00/10] amdgpu: implement Performance Monitor Counter support Zhu Lingshan
                   ` (5 preceding siblings ...)
  2026-09-22  9:34 ` [RFC 06/10] drm/amdgpu: GFX11: set mqd->perfcount from mqd_prop Zhu Lingshan
@ 2026-09-22  9:34 ` Zhu Lingshan
  2026-09-22  9:34 ` [RFC 08/10] drm/amdgpu: GFX12.1: " Zhu Lingshan
                   ` (3 subsequent siblings)
  10 siblings, 0 replies; 23+ messages in thread
From: Zhu Lingshan @ 2026-09-22  9:34 UTC (permalink / raw)
  To: Alexander.Deucher, felix.kuehling; +Cc: Ray.Huang, amd-gfx, Zhu Lingshan

This commit implements amdgpu_mqd->set_mqd_perfcount
for GFX12, which helps setting mqd->compute_perfcount_enable
from amdgpu_mqd_prop->perfcount_enable.

Signed-off-by: Zhu Lingshan <lingshan.zhu@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
index e26c56b4216f..fe9d7feb42fc 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
@@ -3160,6 +3160,7 @@ static int gfx_v12_0_compute_mqd_init(struct amdgpu_device *adev, void *m,
 
 	mqd->header = 0xC0310800;
 	mqd->compute_pipelinestat_enable = 0x00000001;
+	mqd->compute_perfcount_enable = prop->perfcount_enable;
 	mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
 	mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
 	mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
@@ -3313,6 +3314,14 @@ static int gfx_v12_0_compute_mqd_init(struct amdgpu_device *adev, void *m,
 	return 0;
 }
 
+static void gfx_v12_0_compute_mqd_set_perfcount(void *m,
+						struct amdgpu_mqd_prop *prop)
+{
+	struct v12_compute_mqd *mqd = m;
+
+	mqd->compute_perfcount_enable = prop->perfcount_enable;
+}
+
 static int gfx_v12_0_kiq_init_register(struct amdgpu_ring *ring)
 {
 	struct amdgpu_device *adev = ring->adev;
@@ -5542,6 +5551,8 @@ static void gfx_v12_0_set_mqd_funcs(struct amdgpu_device *adev)
 		sizeof(struct v12_compute_mqd);
 	adev->mqds[AMDGPU_HW_IP_COMPUTE].init_mqd =
 		gfx_v12_0_compute_mqd_init;
+	adev->mqds[AMDGPU_HW_IP_COMPUTE].set_mqd_perfcount =
+		gfx_v12_0_compute_mqd_set_perfcount;
 }
 
 static void gfx_v12_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev,
-- 
2.55.0


^ permalink raw reply related	[flat|nested] 23+ messages in thread

* [RFC 08/10] drm/amdgpu: GFX12.1: set mqd->perfcount from mqd_prop
  2026-09-22  9:34 [RFC 00/10] amdgpu: implement Performance Monitor Counter support Zhu Lingshan
                   ` (6 preceding siblings ...)
  2026-09-22  9:34 ` [RFC 07/10] drm/amdgpu: GFX12: " Zhu Lingshan
@ 2026-09-22  9:34 ` Zhu Lingshan
  2026-09-22  9:34 ` [RFC 09/10] drm/amdgpu: implement device PMC handler Zhu Lingshan
                   ` (2 subsequent siblings)
  10 siblings, 0 replies; 23+ messages in thread
From: Zhu Lingshan @ 2026-09-22  9:34 UTC (permalink / raw)
  To: Alexander.Deucher, felix.kuehling; +Cc: Ray.Huang, amd-gfx, Zhu Lingshan

This commit implements amdgpu_mqd->set_mqd_perfcount
for GFX12.1, which helps setting mqd->compute_perfcount_enable
from amdgpu_mqd_prop->perfcount_enable.

Signed-off-by: Zhu Lingshan <lingshan.zhu@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c
index b19a4956c222..ab70a77cfffb 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c
@@ -2170,6 +2170,7 @@ static int gfx_v12_1_compute_mqd_init(struct amdgpu_device *adev, void *m,
 
 	mqd->header = 0xC0310800;
 	mqd->compute_pipelinestat_enable = 0x00000001;
+	mqd->compute_perfcount_enable = prop->perfcount_enable;
 	mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
 	mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
 	mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
@@ -2298,6 +2299,14 @@ static int gfx_v12_1_compute_mqd_init(struct amdgpu_device *adev, void *m,
 	return 0;
 }
 
+static void gfx_v12_1_compute_mqd_set_perfcount(void *m,
+						struct amdgpu_mqd_prop *prop)
+{
+	struct v12_1_compute_mqd *mqd = m;
+
+	mqd->compute_perfcount_enable = prop->perfcount_enable;
+}
+
 static int gfx_v12_1_xcc_kiq_init_register(struct amdgpu_ring *ring,
 					   int xcc_id)
 {
@@ -4041,6 +4050,8 @@ static void gfx_v12_1_set_mqd_funcs(struct amdgpu_device *adev)
 		sizeof(struct v12_1_compute_mqd);
 	adev->mqds[AMDGPU_HW_IP_COMPUTE].init_mqd =
 		gfx_v12_1_compute_mqd_init;
+	adev->mqds[AMDGPU_HW_IP_COMPUTE].set_mqd_perfcount =
+		gfx_v12_1_compute_mqd_set_perfcount;
 }
 
 static void gfx_v12_1_set_user_cu_inactive_bitmap_per_sh(struct amdgpu_device *adev,
-- 
2.55.0


^ permalink raw reply related	[flat|nested] 23+ messages in thread

* [RFC 09/10] drm/amdgpu: implement device PMC handler
  2026-09-22  9:34 [RFC 00/10] amdgpu: implement Performance Monitor Counter support Zhu Lingshan
                   ` (7 preceding siblings ...)
  2026-09-22  9:34 ` [RFC 08/10] drm/amdgpu: GFX12.1: " Zhu Lingshan
@ 2026-09-22  9:34 ` Zhu Lingshan
  2026-09-22  9:34 ` [RFC 10/10] drm/amdgpu: set userq perf state before publish it Zhu Lingshan
  2026-09-23 14:02 ` [RFC 00/10] amdgpu: implement Performance Monitor Counter support James Zhu
  10 siblings, 0 replies; 23+ messages in thread
From: Zhu Lingshan @ 2026-09-22  9:34 UTC (permalink / raw)
  To: Alexander.Deucher, felix.kuehling; +Cc: Ray.Huang, amd-gfx, Zhu Lingshan

This commit implements device PMC handler

Signed-off-by: Zhu Lingshan <lingshan.zhu@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_profiler.c |  6 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c    | 68 ++++++++++++++++++++
 drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h    |  2 +
 3 files changed, 75 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_profiler.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_profiler.c
index 254fb8d77d80..f40c848331a0 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_profiler.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_profiler.c
@@ -95,7 +95,11 @@ int amdgpu_profiler_set_perfcount(struct amdgpu_device *adev,
 
 	mutex_unlock(&adev->pmc_profiler.lock);
 
-	return ret;
+	if (ret)
+		return ret;
+
+	/* no racings because the device was reserved by pmc_profiler.owner */
+	return amdgpu_set_perfcount(adev, enable);
 }
 
 static int amdgpu_profiler_check_access(struct drm_device *dev)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c
index 45e4225c0201..8a1f0841e8e7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c
@@ -1541,6 +1541,74 @@ int amdgpu_userq_resume(struct amdgpu_device *adev)
 	return 0;
 }
 
+static void amdgpu_userq_set_perfcount(struct amdgpu_usermode_queue *queue,
+				       bool enable)
+{
+	struct amdgpu_userq_mgr *uq_mgr = queue->userq_mgr;
+	struct amdgpu_device *adev = uq_mgr->adev;
+	struct amdgpu_mqd *mqd_funcs = &adev->mqds[queue->queue_type];
+	int r;
+
+	/* IP does not support PMC */
+	if (!mqd_funcs->set_mqd_perfcount)
+		return;
+
+	mutex_lock(&uq_mgr->userq_mutex);
+	queue->userq_prop->perfcount_enable = enable;
+
+	if (queue->state == AMDGPU_USERQ_STATE_MAPPED) {
+		r = amdgpu_userq_unmap_helper(queue);
+		if (r) {
+			drm_file_err(uq_mgr->file,
+				     "Failed to unmap user queue %llu when updating PMC\n",
+				     queue->doorbell_index);
+		} else {
+			mqd_funcs->set_mqd_perfcount(queue->mqd.cpu_ptr,
+						     queue->userq_prop);
+			r = amdgpu_userq_map_helper(queue);
+			if (r)
+				drm_file_err(uq_mgr->file,
+					     "Failed to map user queue %llu when updating PMC\n",
+					     queue->doorbell_index);
+		}
+	} else {
+		drm_dbg_driver(adev_to_drm(adev),
+			       "user queue  %llu is in state %d, skip it when updating PMC\n",
+			       queue->doorbell_index, queue->state);
+	}
+
+	mutex_unlock(&uq_mgr->userq_mutex);
+}
+
+/* set perfcount for every queue on the device. */
+int amdgpu_set_perfcount(struct amdgpu_device *adev, bool enable)
+{
+	struct amdgpu_usermode_queue *queue;
+	unsigned long queue_id = 0;
+
+	if (amdgpu_in_reset(adev))
+		return -EIO;
+
+	if (adev->userq_halt_for_enforce_isolation)
+		return -EAGAIN;
+
+	queue = amdgpu_userq_xa_find(&adev->userq_doorbell_xa, &queue_id);
+	while (queue) {
+		amdgpu_userq_set_perfcount(queue, enable);
+		amdgpu_userq_put(queue);
+
+		if (queue_id == ULONG_MAX)
+			break;
+
+		/* find next queue */
+		queue_id++;
+		queue = amdgpu_userq_xa_find(&adev->userq_doorbell_xa,
+					     &queue_id);
+	}
+
+	return 0;
+}
+
 int amdgpu_userq_stop_sched_for_enforce_isolation(struct amdgpu_device *adev,
 						  u32 idx)
 {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h
index 4c9a71b56792..2fcde5955d4d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h
@@ -189,6 +189,8 @@ int amdgpu_userq_stop_sched_for_enforce_isolation(struct amdgpu_device *adev,
 						  u32 idx);
 int amdgpu_userq_start_sched_for_enforce_isolation(struct amdgpu_device *adev,
 						   u32 idx);
+
+int amdgpu_set_perfcount(struct amdgpu_device *adev, bool enable);
 void amdgpu_userq_reset_work(struct work_struct *work);
 void amdgpu_userq_pre_reset(struct amdgpu_device *adev);
 int amdgpu_userq_post_reset(struct amdgpu_device *adev, bool vram_lost);
-- 
2.55.0


^ permalink raw reply related	[flat|nested] 23+ messages in thread

* [RFC 10/10] drm/amdgpu: set userq perf state before publish it
  2026-09-22  9:34 [RFC 00/10] amdgpu: implement Performance Monitor Counter support Zhu Lingshan
                   ` (8 preceding siblings ...)
  2026-09-22  9:34 ` [RFC 09/10] drm/amdgpu: implement device PMC handler Zhu Lingshan
@ 2026-09-22  9:34 ` Zhu Lingshan
  2026-09-23 14:02 ` [RFC 00/10] amdgpu: implement Performance Monitor Counter support James Zhu
  10 siblings, 0 replies; 23+ messages in thread
From: Zhu Lingshan @ 2026-09-22  9:34 UTC (permalink / raw)
  To: Alexander.Deucher, felix.kuehling; +Cc: Ray.Huang, amd-gfx, Zhu Lingshan

This commit sets the perf state of a user queue
before publish it.

Signed-off-by: Zhu Lingshan <lingshan.zhu@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c | 27 +++++++++++++++++++++--
 1 file changed, 25 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c
index 8a1f0841e8e7..fb4d8c8c6eef 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c
@@ -731,6 +731,30 @@ static int amdgpu_userq_priority_permit(struct drm_file *filp,
 	return -EACCES;
 }
 
+static int amdgpu_userq_attach(struct amdgpu_device *adev,
+			       struct amdgpu_usermode_queue *queue,
+			       u64 index)
+{
+	struct amdgpu_mqd *mqd_funcs = &adev->mqds[queue->queue_type];
+	int r;
+
+	mutex_lock(&adev->pmc_profiler.lock);
+
+	/* set the queue PMC state based on the device PMC state */
+	if (mqd_funcs->set_mqd_perfcount) {
+		queue->userq_prop->perfcount_enable = adev->pmc_profiler.enable;
+		mqd_funcs->set_mqd_perfcount(queue->mqd.cpu_ptr,
+					     queue->userq_prop);
+	}
+
+	/* attach the queue to the xarray */
+	r = xa_insert_irq(&adev->userq_doorbell_xa, index, queue, GFP_KERNEL);
+
+	mutex_unlock(&adev->pmc_profiler.lock);
+
+	return r;
+}
+
 static int
 amdgpu_userq_create(struct drm_file *filp, union drm_amdgpu_userq *args)
 {
@@ -831,8 +855,7 @@ amdgpu_userq_create(struct drm_file *filp, union drm_amdgpu_userq *args)
 	/* Update VM owner at userq submit-time for page-fault attribution. */
 	amdgpu_vm_set_task_info(&fpriv->vm);
 
-	r = xa_insert_irq(&adev->userq_doorbell_xa, index, queue,
-			  GFP_KERNEL);
+	r = amdgpu_userq_attach(adev, queue, index);
 	if (r)
 		goto clean_mqd;
 
-- 
2.55.0


^ permalink raw reply related	[flat|nested] 23+ messages in thread

* Re: [RFC 00/10] amdgpu: implement Performance Monitor Counter support
  2026-09-22  9:34 [RFC 00/10] amdgpu: implement Performance Monitor Counter support Zhu Lingshan
                   ` (9 preceding siblings ...)
  2026-09-22  9:34 ` [RFC 10/10] drm/amdgpu: set userq perf state before publish it Zhu Lingshan
@ 2026-09-23 14:02 ` James Zhu
  2026-09-23 15:02   ` Welton, Benjamin
  10 siblings, 1 reply; 23+ messages in thread
From: James Zhu @ 2026-09-23 14:02 UTC (permalink / raw)
  To: amd-gfx, Welton, Benjamin

Hi Ben,

Please review these PMC patches for unified Kernel interface.

Thanks and Best Regards!

James Zhu

On 2026-09-22 05:34, Zhu Lingshan wrote:
> This series implements PMC support for amdgpu. Including two parts:
> 1) PMC Enablement
> 2) Profiler Reservation
>
> The user space should take the reservation, then set PMC.
>
> This series depends on and used new helper introduced in
> another series:
> https://lists.freedesktop.org/archives/amd-gfx/2026-August/151692.html
>
> Please help Review
>
> Thanks!
>
> Zhu Lingshan (10):
>    drm/amdgpu: implement PMC ioctl framework
>    drm/amdgpu: add device-wide PMC config
>    drm/amdgpu: introduce PMC ioctl handler
>    drm/amdgpu: implement reservation mechanism for PMC
>    drm/amdgpu: set device-wide PMC enablement indicator
>    drm/amdgpu: GFX11: set mqd->perfcount from mqd_prop
>    drm/amdgpu: GFX12: set mqd->perfcount from mqd_prop
>    drm/amdgpu: GFX12.1: set mqd->perfcount from mqd_prop
>    drm/amdgpu: implement device PMC handler
>    drm/amdgpu: set userq perf state before publish it
>
>   drivers/gpu/drm/amd/amdgpu/Makefile          |   2 +-
>   drivers/gpu/drm/amd/amdgpu/amdgpu.h          |   8 +
>   drivers/gpu/drm/amd/amdgpu/amdgpu_device.c   |   3 +
>   drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c      |   4 +
>   drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h      |   6 +
>   drivers/gpu/drm/amd/amdgpu/amdgpu_profiler.c | 166 +++++++++++++++++++
>   drivers/gpu/drm/amd/amdgpu/amdgpu_profiler.h |  38 +++++
>   drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c    |  95 ++++++++++-
>   drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h    |   2 +
>   drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c       |  11 ++
>   drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c       |  11 ++
>   drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c       |  11 ++
>   include/uapi/drm/amdgpu_drm.h                |  36 ++++
>   13 files changed, 390 insertions(+), 3 deletions(-)
>   create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_profiler.c
>   create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_profiler.h
>

^ permalink raw reply	[flat|nested] 23+ messages in thread

* Re: [RFC 02/10] drm/amdgpu: add device-wide PMC config
  2026-09-22  9:34 ` [RFC 02/10] drm/amdgpu: add device-wide PMC config Zhu Lingshan
@ 2026-09-23 14:13   ` James Zhu
  2026-09-24  3:23     ` Zhu, Lingshan
  0 siblings, 1 reply; 23+ messages in thread
From: James Zhu @ 2026-09-23 14:13 UTC (permalink / raw)
  To: Zhu Lingshan, Alexander.Deucher, felix.kuehling; +Cc: Ray.Huang, amd-gfx


On 2026-09-22 05:34, Zhu Lingshan wrote:
> This commit implements a device-wide PMC config
> for amdgpu, which including the profiling owner,
> and the profiling enablement indicator.
[JZ] I think it should be render-node wide, not device-wide
>
> Signed-off-by: Zhu Lingshan <lingshan.zhu@amd.com>
> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu.h        | 8 ++++++++
>   drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 3 +++
>   2 files changed, 11 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index 8eff6b9ebe81..45897dca802f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -620,6 +620,12 @@ enum amdgpu_enforce_isolation_mode {
>   	AMDGPU_ENFORCE_ISOLATION_NO_CLEANER_SHADER = 3,
>   };
>   
> +struct amdgpu_pmc_profiler {
> +	struct mutex		lock;
> +	struct drm_file		*owner;
> +	bool			enable;
> +};
> +
>   struct amdgpu_device {
>   	struct device			*dev;
>   	struct pci_dev			*pdev;
> @@ -818,6 +824,8 @@ struct amdgpu_device {
>   	 */
>   	struct xarray userq_doorbell_xa;
>   
> +	struct amdgpu_pmc_profiler	pmc_profiler;
> +
>   	/* df */
>   	struct amdgpu_df                df;
>   
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index c924a55fd16f..74ed42e53264 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -3673,6 +3673,7 @@ int amdgpu_device_init(struct amdgpu_device *adev,
>   	mutex_init(&adev->pm.stable_pstate_ctx_lock);
>   	mutex_init(&adev->benchmark_mutex);
>   	mutex_init(&adev->gfx.reset_sem_mutex);
> +	mutex_init(&adev->pmc_profiler.lock);
>   
>   	/* Associate locks with lockdep classes for ordering validation */
>   	amdgpu_lockdep_set_class(adev);
> @@ -4244,6 +4245,8 @@ void amdgpu_device_fini_sw(struct amdgpu_device *adev)
>   	kfree(adev->pci_state);
>   	kfree(adev->pcie_reset_ctx.swds_pcistate);
>   	kfree(adev->pcie_reset_ctx.swus_pcistate);
> +
> +	mutex_destroy(&adev->pmc_profiler.lock);
>   }
>   
>   /**

^ permalink raw reply	[flat|nested] 23+ messages in thread

* Re: [RFC 01/10] drm/amdgpu: implement PMC ioctl framework
  2026-09-22  9:34 ` [RFC 01/10] drm/amdgpu: implement PMC ioctl framework Zhu Lingshan
@ 2026-09-23 14:17   ` James Zhu
  2026-09-24  3:38     ` Zhu, Lingshan
  0 siblings, 1 reply; 23+ messages in thread
From: James Zhu @ 2026-09-23 14:17 UTC (permalink / raw)
  To: Zhu Lingshan, Alexander.Deucher, felix.kuehling; +Cc: Ray.Huang, amd-gfx

[-- Attachment #1: Type: text/plain, Size: 8831 bytes --]


On 2026-09-22 05:34, Zhu Lingshan wrote:
> This commit implements basic ioctl framework for PMC,
> including basic operations.
>
> This commit also implements AMDGPU_PROFILER_OP_VERSION
> which report profiler version to the user space.
>
> Signed-off-by: Zhu Lingshan<lingshan.zhu@amd.com>
> ---
>   drivers/gpu/drm/amd/amdgpu/Makefile          |  2 +-
>   drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c      |  2 +
>   drivers/gpu/drm/amd/amdgpu/amdgpu_profiler.c | 44 ++++++++++++++++++++
>   drivers/gpu/drm/amd/amdgpu/amdgpu_profiler.h | 33 +++++++++++++++
>   include/uapi/drm/amdgpu_drm.h                | 36 ++++++++++++++++
>   5 files changed, 116 insertions(+), 1 deletion(-)
>   create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_profiler.c
>   create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_profiler.h
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile
> index 6fb0a913e33b..d7db69e9d6a0 100644
> --- a/drivers/gpu/drm/amd/amdgpu/Makefile
> +++ b/drivers/gpu/drm/amd/amdgpu/Makefile
> @@ -72,7 +72,7 @@ amdgpu-y += amdgpu_device.o amdgpu_reg_access.o amdgpu_doorbell_mgr.o amdgpu_kms
>   	amdgpu_eeprom.o amdgpu_mca.o amdgpu_psp_ta.o amdgpu_lsdma.o amdgpu_lockdep.o \
>   	amdgpu_ring_mux.o amdgpu_xcp.o amdgpu_seq64.o amdgpu_dev_coredump.o \
>   	amdgpu_cper.o amdgpu_userq_fence.o amdgpu_eviction_fence.o amdgpu_ip.o \
> -	amdgpu_wb.o amdgpu_cwsr.o amdgpu_events.o
> +	amdgpu_wb.o amdgpu_cwsr.o amdgpu_events.o amdgpu_profiler.o
>   
>   amdgpu-$(CONFIG_PROC_FS) += amdgpu_fdinfo.o
>   
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> index 7c473f60bd28..a98c4a47e196 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> @@ -55,6 +55,7 @@
>   #include "amdgpu_cwsr.h"
>   #include "amdgpu_userq_fence.h"
>   #include "../amdxcp/amdgpu_xcp_drv.h"
> +#include "amdgpu_profiler.h"
>   
>   /*
>    * KMS wrapper.
> @@ -3096,6 +3097,7 @@ const struct drm_ioctl_desc amdgpu_ioctls_kms[] = {
>   	DRM_IOCTL_DEF_DRV(AMDGPU_USERQ_WAIT, amdgpu_userq_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
>   	DRM_IOCTL_DEF_DRV(AMDGPU_GEM_LIST_HANDLES, amdgpu_gem_list_handles_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
>   	DRM_IOCTL_DEF_DRV(AMDGPU_PROC_OPTIONS, amdgpu_proc_options_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
> +	DRM_IOCTL_DEF_DRV(AMDGPU_PROFILER, amdgpu_profiler_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
>   };
>   
>   static const struct drm_driver amdgpu_kms_driver = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_profiler.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_profiler.c
> new file mode 100644
> index 000000000000..04902696adab
> --- /dev/null
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_profiler.c
> @@ -0,0 +1,44 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright 2026 Advanced Micro Devices, Inc.
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
> + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + *
> + */
> +
> +#include <linux/errno.h>
> +#include <drm/amdgpu_drm.h>
> +#include "amdgpu_profiler.h"
> +
> +int amdgpu_profiler_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
> +{
> +	struct drm_amdgpu_profiler_args *args = data;
> +
> +	switch (args->op) {
> +	case AMDGPU_PROFILER_OP_VERSION:
> +		args->version = AMDGPU_PROFILER_VERSION_NUM;
> +		return 0;
> +	case AMDGPU_PROFILER_OP_RESERVE:
> +		return -EOPNOTSUPP;
> +	case AMDGPU_PROFILER_OP_PMC:
> +		return -EOPNOTSUPP;
> +	default:
> +		return -EINVAL;
> +	}
> +}
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_profiler.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_profiler.h
> new file mode 100644
> index 000000000000..c27b5f9b3ff0
> --- /dev/null
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_profiler.h
> @@ -0,0 +1,33 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright 2026 Advanced Micro Devices, Inc.
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
> + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + *
> + */
> +
> +#ifndef __AMDGPU_PROFILER_H__
> +#define __AMDGPU_PROFILER_H__
> +
> +#include <drm/drm_device.h>
> +#include <drm/drm_file.h>
> +
> +int amdgpu_profiler_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
> +
> +#endif /* __AMDGPU_PROFILER_H__ */
> diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
> index 9222be9a6d2a..acc63804ba8c 100644
> --- a/include/uapi/drm/amdgpu_drm.h
> +++ b/include/uapi/drm/amdgpu_drm.h
> @@ -60,6 +60,7 @@ extern "C" {
>   #define DRM_AMDGPU_GEM_LIST_HANDLES	0x19
>   #define DRM_AMDGPU_PROC_OPTIONS		0x1A
>   #define DRM_AMDGPU_CWSR			0x1B
> +#define DRM_AMDGPU_PROFILER		0x1C
>   
>   #define DRM_IOCTL_AMDGPU_GEM_CREATE	DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create)
>   #define DRM_IOCTL_AMDGPU_GEM_MMAP	DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap)
> @@ -83,6 +84,7 @@ extern "C" {
>   #define DRM_IOCTL_AMDGPU_GEM_LIST_HANDLES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_LIST_HANDLES, struct drm_amdgpu_gem_list_handles)
>   #define DRM_IOCTL_AMDGPU_PROC_OPTIONS	DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_PROC_OPTIONS, struct drm_amdgpu_proc_options)
>   #define DRM_IOCTL_AMDGPU_CWSR	DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CWSR, union drm_amdgpu_cwsr)
> +#define DRM_IOCTL_AMDGPU_PROFILER	DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_PROFILER, struct drm_amdgpu_profiler_args)
>   
>   /**
>    * DOC: memory domains
> @@ -1809,6 +1811,40 @@ struct drm_amdgpu_proc_options {
>   	} kfd_sigbus_delay;
>   };
>   
> +#define AMDGPU_PROFILER_VERSION_NUM	1
> +
> +enum amdgpu_profiler_ops {
> +	AMDGPU_PROFILER_OP_VERSION = 1,
> +	AMDGPU_PROFILER_OP_RESERVE = 2,
[JZ] the implementation tells that it is AMDGPU_PROFILER_OP_PMC_RESERVE, 
it is better to put it under new PMC sub-ioctl op
> +	AMDGPU_PROFILER_OP_PMC = 3,
> +};
> +
> +enum amdgpu_profiler_reserve_ops {
> +	/* release the device resertaion, only the reservation owner do this */
> +	AMDGPU_PROFILER_RELEASE = 0,
> +	/* reserve the device profiler */
> +	AMDGPU_PROFILER_RESERVE = 1,
> +	/* Clear the device profiler reservation, in case the reservation
> +	 * owner can no longer release the reservation(e.g., it crashes),
> +	 * This operation does not take the reseration nor touch profielr state
> +	 */
> +	AMDGPU_PROFILER_CLEAR_RESERVATION = 2,
> +};
> +
> +struct drm_amdgpu_profiler_args {
> +	/* enum amdgpu_profiler_ops */
> +	__u8 op;
> +	__u8 pad[3];
> +	union {
> +		/* AMDGPU_PROFILER_OP_RESERVE: enum amdgpu_profiler_reserve_ops */
> +		__u8 reserve;
> +		/* AMDGPU_PROFILER_OP_PMC: 1 enable PMC, 0 disable PMC */
> +		__u8 perfcount_enable;
> +		/* AMDGPU_PROFILER_OP_VERSION: AMDGPU_PROFILER_VERSION_NUM */
> +		__u32 version;
> +	};
> +};
> +
>   #if defined(__cplusplus)
>   }
>   #endif

[-- Attachment #2: Type: text/html, Size: 9174 bytes --]

^ permalink raw reply	[flat|nested] 23+ messages in thread

* RE: [RFC 00/10] amdgpu: implement Performance Monitor Counter support
  2026-09-23 14:02 ` [RFC 00/10] amdgpu: implement Performance Monitor Counter support James Zhu
@ 2026-09-23 15:02   ` Welton, Benjamin
  2026-09-23 15:11     ` James Zhu
  2026-09-24  3:40     ` Zhu, Lingshan
  0 siblings, 2 replies; 23+ messages in thread
From: Welton, Benjamin @ 2026-09-23 15:02 UTC (permalink / raw)
  To: Zhu, James, amd-gfx@lists.freedesktop.org

AMD General

For some background on my end, is this the porting over of the existing profiler work to KGD?

Ben

-----Original Message-----
From: Zhu, James <James.Zhu@amd.com>
Sent: Wednesday, September 23, 2026 7:02 AM
To: amd-gfx@lists.freedesktop.org; Welton, Benjamin <Benjamin.Welton@amd.com>
Subject: Re: [RFC 00/10] amdgpu: implement Performance Monitor Counter support

Hi Ben,

Please review these PMC patches for unified Kernel interface.

Thanks and Best Regards!

James Zhu

On 2026-09-22 05:34, Zhu Lingshan wrote:
> This series implements PMC support for amdgpu. Including two parts:
> 1) PMC Enablement
> 2) Profiler Reservation
>
> The user space should take the reservation, then set PMC.
>
> This series depends on and used new helper introduced in another
> series:
> https://lists.freedesktop.org/archives/amd-gfx/2026-August/151692.html
>
> Please help Review
>
> Thanks!
>
> Zhu Lingshan (10):
>    drm/amdgpu: implement PMC ioctl framework
>    drm/amdgpu: add device-wide PMC config
>    drm/amdgpu: introduce PMC ioctl handler
>    drm/amdgpu: implement reservation mechanism for PMC
>    drm/amdgpu: set device-wide PMC enablement indicator
>    drm/amdgpu: GFX11: set mqd->perfcount from mqd_prop
>    drm/amdgpu: GFX12: set mqd->perfcount from mqd_prop
>    drm/amdgpu: GFX12.1: set mqd->perfcount from mqd_prop
>    drm/amdgpu: implement device PMC handler
>    drm/amdgpu: set userq perf state before publish it
>
>   drivers/gpu/drm/amd/amdgpu/Makefile          |   2 +-
>   drivers/gpu/drm/amd/amdgpu/amdgpu.h          |   8 +
>   drivers/gpu/drm/amd/amdgpu/amdgpu_device.c   |   3 +
>   drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c      |   4 +
>   drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h      |   6 +
>   drivers/gpu/drm/amd/amdgpu/amdgpu_profiler.c | 166 +++++++++++++++++++
>   drivers/gpu/drm/amd/amdgpu/amdgpu_profiler.h |  38 +++++
>   drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c    |  95 ++++++++++-
>   drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h    |   2 +
>   drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c       |  11 ++
>   drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c       |  11 ++
>   drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c       |  11 ++
>   include/uapi/drm/amdgpu_drm.h                |  36 ++++
>   13 files changed, 390 insertions(+), 3 deletions(-)
>   create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_profiler.c
>   create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_profiler.h
>

^ permalink raw reply	[flat|nested] 23+ messages in thread

* Re: [RFC 00/10] amdgpu: implement Performance Monitor Counter support
  2026-09-23 15:02   ` Welton, Benjamin
@ 2026-09-23 15:11     ` James Zhu
  2026-09-24  3:40     ` Zhu, Lingshan
  1 sibling, 0 replies; 23+ messages in thread
From: James Zhu @ 2026-09-23 15:11 UTC (permalink / raw)
  To: Welton, Benjamin, Zhu, James, amd-gfx@lists.freedesktop.org


On 2026-09-23 11:02, Welton, Benjamin wrote:
> AMD General
>
> For some background on my end, is this the porting over of the existing profiler work to KGD?
[JZ] Yes, for profiler-PMC only. One of the main changes is  from kfd 
device based PMC to render-node based PMC.
>
> Ben
>
> -----Original Message-----
> From: Zhu, James <James.Zhu@amd.com>
> Sent: Wednesday, September 23, 2026 7:02 AM
> To: amd-gfx@lists.freedesktop.org; Welton, Benjamin <Benjamin.Welton@amd.com>
> Subject: Re: [RFC 00/10] amdgpu: implement Performance Monitor Counter support
>
> Hi Ben,
>
> Please review these PMC patches for unified Kernel interface.
>
> Thanks and Best Regards!
>
> James Zhu
>
> On 2026-09-22 05:34, Zhu Lingshan wrote:
>> This series implements PMC support for amdgpu. Including two parts:
>> 1) PMC Enablement
>> 2) Profiler Reservation
>>
>> The user space should take the reservation, then set PMC.
>>
>> This series depends on and used new helper introduced in another
>> series:
>> https://lists.freedesktop.org/archives/amd-gfx/2026-August/151692.html
>>
>> Please help Review
>>
>> Thanks!
>>
>> Zhu Lingshan (10):
>>     drm/amdgpu: implement PMC ioctl framework
>>     drm/amdgpu: add device-wide PMC config
>>     drm/amdgpu: introduce PMC ioctl handler
>>     drm/amdgpu: implement reservation mechanism for PMC
>>     drm/amdgpu: set device-wide PMC enablement indicator
>>     drm/amdgpu: GFX11: set mqd->perfcount from mqd_prop
>>     drm/amdgpu: GFX12: set mqd->perfcount from mqd_prop
>>     drm/amdgpu: GFX12.1: set mqd->perfcount from mqd_prop
>>     drm/amdgpu: implement device PMC handler
>>     drm/amdgpu: set userq perf state before publish it
>>
>>    drivers/gpu/drm/amd/amdgpu/Makefile          |   2 +-
>>    drivers/gpu/drm/amd/amdgpu/amdgpu.h          |   8 +
>>    drivers/gpu/drm/amd/amdgpu/amdgpu_device.c   |   3 +
>>    drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c      |   4 +
>>    drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h      |   6 +
>>    drivers/gpu/drm/amd/amdgpu/amdgpu_profiler.c | 166 +++++++++++++++++++
>>    drivers/gpu/drm/amd/amdgpu/amdgpu_profiler.h |  38 +++++
>>    drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c    |  95 ++++++++++-
>>    drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h    |   2 +
>>    drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c       |  11 ++
>>    drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c       |  11 ++
>>    drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c       |  11 ++
>>    include/uapi/drm/amdgpu_drm.h                |  36 ++++
>>    13 files changed, 390 insertions(+), 3 deletions(-)
>>    create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_profiler.c
>>    create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_profiler.h
>>

^ permalink raw reply	[flat|nested] 23+ messages in thread

* Re: [RFC 02/10] drm/amdgpu: add device-wide PMC config
  2026-09-23 14:13   ` James Zhu
@ 2026-09-24  3:23     ` Zhu, Lingshan
  2026-09-24 15:40       ` James Zhu
  0 siblings, 1 reply; 23+ messages in thread
From: Zhu, Lingshan @ 2026-09-24  3:23 UTC (permalink / raw)
  To: James Zhu, Alexander.Deucher, felix.kuehling; +Cc: Ray.Huang, amd-gfx

[-- Attachment #1: Type: text/plain, Size: 2693 bytes --]

On 9/23/2026 10:13 PM, James Zhu wrote:

>
> On 2026-09-22 05:34, Zhu Lingshan wrote:
>> This commit implements a device-wide PMC config
>> for amdgpu, which including the profiling owner,
>> and the profiling enablement indicator.
> [JZ] I think it should be render-node wide, not device-wide

Hi James,

It could be, but we don't have a requirement document defines the scope.

But normally a profiler is a device scope,
I see KFD profiler operates on all queues under the device queue manager

Thanks
Lingshan 

>>
>> Signed-off-by: Zhu Lingshan <lingshan.zhu@amd.com>
>> ---
>>   drivers/gpu/drm/amd/amdgpu/amdgpu.h        | 8 ++++++++
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 3 +++
>>   2 files changed, 11 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>> index 8eff6b9ebe81..45897dca802f 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>> @@ -620,6 +620,12 @@ enum amdgpu_enforce_isolation_mode {
>>       AMDGPU_ENFORCE_ISOLATION_NO_CLEANER_SHADER = 3,
>>   };
>>   +struct amdgpu_pmc_profiler {
>> +    struct mutex        lock;
>> +    struct drm_file        *owner;
>> +    bool            enable;
>> +};
>> +
>>   struct amdgpu_device {
>>       struct device            *dev;
>>       struct pci_dev            *pdev;
>> @@ -818,6 +824,8 @@ struct amdgpu_device {
>>        */
>>       struct xarray userq_doorbell_xa;
>>   +    struct amdgpu_pmc_profiler    pmc_profiler;
>> +
>>       /* df */
>>       struct amdgpu_df                df;
>>   diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>> index c924a55fd16f..74ed42e53264 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>> @@ -3673,6 +3673,7 @@ int amdgpu_device_init(struct amdgpu_device *adev,
>>       mutex_init(&adev->pm.stable_pstate_ctx_lock);
>>       mutex_init(&adev->benchmark_mutex);
>>       mutex_init(&adev->gfx.reset_sem_mutex);
>> +    mutex_init(&adev->pmc_profiler.lock);
>>         /* Associate locks with lockdep classes for ordering
>> validation */
>>       amdgpu_lockdep_set_class(adev);
>> @@ -4244,6 +4245,8 @@ void amdgpu_device_fini_sw(struct amdgpu_device
>> *adev)
>>       kfree(adev->pci_state);
>>       kfree(adev->pcie_reset_ctx.swds_pcistate);
>>       kfree(adev->pcie_reset_ctx.swus_pcistate);
>> +
>> +    mutex_destroy(&adev->pmc_profiler.lock);
>>   }
>>     /**

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^ permalink raw reply	[flat|nested] 23+ messages in thread

* Re: [RFC 01/10] drm/amdgpu: implement PMC ioctl framework
  2026-09-23 14:17   ` James Zhu
@ 2026-09-24  3:38     ` Zhu, Lingshan
  2026-09-24 15:49       ` James Zhu
  0 siblings, 1 reply; 23+ messages in thread
From: Zhu, Lingshan @ 2026-09-24  3:38 UTC (permalink / raw)
  To: James Zhu, Alexander.Deucher, felix.kuehling; +Cc: Ray.Huang, amd-gfx

[-- Attachment #1: Type: text/plain, Size: 10160 bytes --]

On 9/23/2026 10:17 PM, James Zhu wrote:

>
> On 2026-09-22 05:34, Zhu Lingshan wrote:
>> This commit implements basic ioctl framework for PMC,
>> including basic operations.
>>
>> This commit also implements AMDGPU_PROFILER_OP_VERSION
>> which report profiler version to the user space.
>>
>> Signed-off-by: Zhu Lingshan<lingshan.zhu@amd.com>
>> ---
>>   drivers/gpu/drm/amd/amdgpu/Makefile          |  2 +-
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c      |  2 +
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_profiler.c | 44 ++++++++++++++++++++
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_profiler.h | 33 +++++++++++++++
>>   include/uapi/drm/amdgpu_drm.h                | 36 ++++++++++++++++
>>   5 files changed, 116 insertions(+), 1 deletion(-)
>>   create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_profiler.c
>>   create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_profiler.h
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile
>> b/drivers/gpu/drm/amd/amdgpu/Makefile
>> index 6fb0a913e33b..d7db69e9d6a0 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/Makefile
>> +++ b/drivers/gpu/drm/amd/amdgpu/Makefile
>> @@ -72,7 +72,7 @@ amdgpu-y += amdgpu_device.o amdgpu_reg_access.o
>> amdgpu_doorbell_mgr.o amdgpu_kms
>>       amdgpu_eeprom.o amdgpu_mca.o amdgpu_psp_ta.o amdgpu_lsdma.o
>> amdgpu_lockdep.o \
>>       amdgpu_ring_mux.o amdgpu_xcp.o amdgpu_seq64.o
>> amdgpu_dev_coredump.o \
>>       amdgpu_cper.o amdgpu_userq_fence.o amdgpu_eviction_fence.o
>> amdgpu_ip.o \
>> -    amdgpu_wb.o amdgpu_cwsr.o amdgpu_events.o
>> +    amdgpu_wb.o amdgpu_cwsr.o amdgpu_events.o amdgpu_profiler.o
>>     amdgpu-$(CONFIG_PROC_FS) += amdgpu_fdinfo.o
>>   diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
>> index 7c473f60bd28..a98c4a47e196 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
>> @@ -55,6 +55,7 @@
>>   #include "amdgpu_cwsr.h"
>>   #include "amdgpu_userq_fence.h"
>>   #include "../amdxcp/amdgpu_xcp_drv.h"
>> +#include "amdgpu_profiler.h"
>>     /*
>>    * KMS wrapper.
>> @@ -3096,6 +3097,7 @@ const struct drm_ioctl_desc amdgpu_ioctls_kms[]
>> = {
>>       DRM_IOCTL_DEF_DRV(AMDGPU_USERQ_WAIT, amdgpu_userq_wait_ioctl,
>> DRM_AUTH|DRM_RENDER_ALLOW),
>>       DRM_IOCTL_DEF_DRV(AMDGPU_GEM_LIST_HANDLES,
>> amdgpu_gem_list_handles_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
>>       DRM_IOCTL_DEF_DRV(AMDGPU_PROC_OPTIONS,
>> amdgpu_proc_options_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
>> +    DRM_IOCTL_DEF_DRV(AMDGPU_PROFILER, amdgpu_profiler_ioctl,
>> DRM_AUTH|DRM_RENDER_ALLOW),
>>   };
>>     static const struct drm_driver amdgpu_kms_driver = {
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_profiler.c
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_profiler.c
>> new file mode 100644
>> index 000000000000..04902696adab
>> --- /dev/null
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_profiler.c
>> @@ -0,0 +1,44 @@
>> +// SPDX-License-Identifier: MIT
>> +/*
>> + * Copyright 2026 Advanced Micro Devices, Inc.
>> + *
>> + * Permission is hereby granted, free of charge, to any person
>> obtaining a
>> + * copy of this software and associated documentation files (the
>> "Software"),
>> + * to deal in the Software without restriction, including without
>> limitation
>> + * the rights to use, copy, modify, merge, publish, distribute,
>> sublicense,
>> + * and/or sell copies of the Software, and to permit persons to whom
>> the
>> + * Software is furnished to do so, subject to the following conditions:
>> + *
>> + * The above copyright notice and this permission notice shall be
>> included in
>> + * all copies or substantial portions of the Software.
>> + *
>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
>> EXPRESS OR
>> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
>> MERCHANTABILITY,
>> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO
>> EVENT SHALL
>> + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM,
>> DAMAGES OR
>> + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
>> OTHERWISE,
>> + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
>> USE OR
>> + * OTHER DEALINGS IN THE SOFTWARE.
>> + *
>> + */
>> +
>> +#include <linux/errno.h>
>> +#include <drm/amdgpu_drm.h>
>> +#include "amdgpu_profiler.h"
>> +
>> +int amdgpu_profiler_ioctl(struct drm_device *dev, void *data, struct
>> drm_file *filp)
>> +{
>> +    struct drm_amdgpu_profiler_args *args = data;
>> +
>> +    switch (args->op) {
>> +    case AMDGPU_PROFILER_OP_VERSION:
>> +        args->version = AMDGPU_PROFILER_VERSION_NUM;
>> +        return 0;
>> +    case AMDGPU_PROFILER_OP_RESERVE:
>> +        return -EOPNOTSUPP;
>> +    case AMDGPU_PROFILER_OP_PMC:
>> +        return -EOPNOTSUPP;
>> +    default:
>> +        return -EINVAL;
>> +    }
>> +}
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_profiler.h
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_profiler.h
>> new file mode 100644
>> index 000000000000..c27b5f9b3ff0
>> --- /dev/null
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_profiler.h
>> @@ -0,0 +1,33 @@
>> +/* SPDX-License-Identifier: MIT */
>> +/*
>> + * Copyright 2026 Advanced Micro Devices, Inc.
>> + *
>> + * Permission is hereby granted, free of charge, to any person
>> obtaining a
>> + * copy of this software and associated documentation files (the
>> "Software"),
>> + * to deal in the Software without restriction, including without
>> limitation
>> + * the rights to use, copy, modify, merge, publish, distribute,
>> sublicense,
>> + * and/or sell copies of the Software, and to permit persons to whom
>> the
>> + * Software is furnished to do so, subject to the following conditions:
>> + *
>> + * The above copyright notice and this permission notice shall be
>> included in
>> + * all copies or substantial portions of the Software.
>> + *
>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
>> EXPRESS OR
>> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
>> MERCHANTABILITY,
>> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO
>> EVENT SHALL
>> + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM,
>> DAMAGES OR
>> + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
>> OTHERWISE,
>> + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
>> USE OR
>> + * OTHER DEALINGS IN THE SOFTWARE.
>> + *
>> + */
>> +
>> +#ifndef __AMDGPU_PROFILER_H__
>> +#define __AMDGPU_PROFILER_H__
>> +
>> +#include <drm/drm_device.h>
>> +#include <drm/drm_file.h>
>> +
>> +int amdgpu_profiler_ioctl(struct drm_device *dev, void *data, struct
>> drm_file *filp);
>> +
>> +#endif /* __AMDGPU_PROFILER_H__ */
>> diff --git a/include/uapi/drm/amdgpu_drm.h
>> b/include/uapi/drm/amdgpu_drm.h
>> index 9222be9a6d2a..acc63804ba8c 100644
>> --- a/include/uapi/drm/amdgpu_drm.h
>> +++ b/include/uapi/drm/amdgpu_drm.h
>> @@ -60,6 +60,7 @@ extern "C" {
>>   #define DRM_AMDGPU_GEM_LIST_HANDLES    0x19
>>   #define DRM_AMDGPU_PROC_OPTIONS        0x1A
>>   #define DRM_AMDGPU_CWSR            0x1B
>> +#define DRM_AMDGPU_PROFILER        0x1C
>>     #define DRM_IOCTL_AMDGPU_GEM_CREATE    DRM_IOWR(DRM_COMMAND_BASE
>> + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create)
>>   #define DRM_IOCTL_AMDGPU_GEM_MMAP    DRM_IOWR(DRM_COMMAND_BASE +
>> DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap)
>> @@ -83,6 +84,7 @@ extern "C" {
>>   #define DRM_IOCTL_AMDGPU_GEM_LIST_HANDLES DRM_IOWR(DRM_COMMAND_BASE
>> + DRM_AMDGPU_GEM_LIST_HANDLES, struct drm_amdgpu_gem_list_handles)
>>   #define DRM_IOCTL_AMDGPU_PROC_OPTIONS    DRM_IOWR(DRM_COMMAND_BASE
>> + DRM_AMDGPU_PROC_OPTIONS, struct drm_amdgpu_proc_options)
>>   #define DRM_IOCTL_AMDGPU_CWSR    DRM_IOWR(DRM_COMMAND_BASE +
>> DRM_AMDGPU_CWSR, union drm_amdgpu_cwsr)
>> +#define DRM_IOCTL_AMDGPU_PROFILER    DRM_IOWR(DRM_COMMAND_BASE +
>> DRM_AMDGPU_PROFILER, struct drm_amdgpu_profiler_args)
>>     /**
>>    * DOC: memory domains
>> @@ -1809,6 +1811,40 @@ struct drm_amdgpu_proc_options {
>>       } kfd_sigbus_delay;
>>   };
>>   +#define AMDGPU_PROFILER_VERSION_NUM    1
>> +
>> +enum amdgpu_profiler_ops {
>> +    AMDGPU_PROFILER_OP_VERSION = 1,
>> +    AMDGPU_PROFILER_OP_RESERVE = 2,
> [JZ] the implementation tells that it is
> AMDGPU_PROFILER_OP_PMC_RESERVE, it is better to put it under new PMC
> sub-ioctl op

Do you mean implement it like {bool pmc_enable, bool reserve} in a struct? I am not sure it is a good idea
and this reservation design is a improvement. Because it separates the reserve(lock) and unreserve(unlock),
so we don't need to keep the reservation during the PMC operations in a complex way, and we won't meet
the problems like how to handle the situation where the user tries to unlock but keeps enable = 1.

Thanks
Lingshan 

>> +    AMDGPU_PROFILER_OP_PMC = 3,
>> +};
>> +
>> +enum amdgpu_profiler_reserve_ops {
>> +    /* release the device resertaion, only the reservation owner do
>> this */
>> +    AMDGPU_PROFILER_RELEASE = 0,
>> +    /* reserve the device profiler */
>> +    AMDGPU_PROFILER_RESERVE = 1,
>> +    /* Clear the device profiler reservation, in case the reservation
>> +     * owner can no longer release the reservation(e.g., it crashes),
>> +     * This operation does not take the reseration nor touch
>> profielr state
>> +     */
>> +    AMDGPU_PROFILER_CLEAR_RESERVATION = 2,
>> +};
>> +
>> +struct drm_amdgpu_profiler_args {
>> +    /* enum amdgpu_profiler_ops */
>> +    __u8 op;
>> +    __u8 pad[3];
>> +    union {
>> +        /* AMDGPU_PROFILER_OP_RESERVE: enum
>> amdgpu_profiler_reserve_ops */
>> +        __u8 reserve;
>> +        /* AMDGPU_PROFILER_OP_PMC: 1 enable PMC, 0 disable PMC */
>> +        __u8 perfcount_enable;
>> +        /* AMDGPU_PROFILER_OP_VERSION: AMDGPU_PROFILER_VERSION_NUM */
>> +        __u32 version;
>> +    };
>> +};
>> +
>>   #if defined(__cplusplus)
>>   }
>>   #endif

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^ permalink raw reply	[flat|nested] 23+ messages in thread

* Re: [RFC 00/10] amdgpu: implement Performance Monitor Counter support
  2026-09-23 15:02   ` Welton, Benjamin
  2026-09-23 15:11     ` James Zhu
@ 2026-09-24  3:40     ` Zhu, Lingshan
  1 sibling, 0 replies; 23+ messages in thread
From: Zhu, Lingshan @ 2026-09-24  3:40 UTC (permalink / raw)
  To: Welton, Benjamin, Zhu, James, amd-gfx@lists.freedesktop.org

[-- Attachment #1: Type: text/plain, Size: 2942 bytes --]

On 9/23/2026 11:02 PM, Welton, Benjamin wrote:

> [Some people who received this message don't often get email from benjamin.welton@amd.com. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ]
>
> AMD General
>
> For some background on my end, is this the porting over of the existing profiler work to KGD?

Hello Ben,

Yes, it is a porting from KFD because I don't have any other documents.

However I still made some improvements like separate reservation from PMC enabling operation
to avoid some corner cases.

Thanks
Lingshan

>
> Ben
>
> -----Original Message-----
> From: Zhu, James <James.Zhu@amd.com>
> Sent: Wednesday, September 23, 2026 7:02 AM
> To: amd-gfx@lists.freedesktop.org; Welton, Benjamin <Benjamin.Welton@amd.com>
> Subject: Re: [RFC 00/10] amdgpu: implement Performance Monitor Counter support
>
> Hi Ben,
>
> Please review these PMC patches for unified Kernel interface.
>
> Thanks and Best Regards!
>
> James Zhu
>
> On 2026-09-22 05:34, Zhu Lingshan wrote:
>> This series implements PMC support for amdgpu. Including two parts:
>> 1) PMC Enablement
>> 2) Profiler Reservation
>>
>> The user space should take the reservation, then set PMC.
>>
>> This series depends on and used new helper introduced in another
>> series:
>> https://lists.freedesktop.org/archives/amd-gfx/2026-August/151692.html
>>
>> Please help Review
>>
>> Thanks!
>>
>> Zhu Lingshan (10):
>>    drm/amdgpu: implement PMC ioctl framework
>>    drm/amdgpu: add device-wide PMC config
>>    drm/amdgpu: introduce PMC ioctl handler
>>    drm/amdgpu: implement reservation mechanism for PMC
>>    drm/amdgpu: set device-wide PMC enablement indicator
>>    drm/amdgpu: GFX11: set mqd->perfcount from mqd_prop
>>    drm/amdgpu: GFX12: set mqd->perfcount from mqd_prop
>>    drm/amdgpu: GFX12.1: set mqd->perfcount from mqd_prop
>>    drm/amdgpu: implement device PMC handler
>>    drm/amdgpu: set userq perf state before publish it
>>
>>   drivers/gpu/drm/amd/amdgpu/Makefile          |   2 +-
>>   drivers/gpu/drm/amd/amdgpu/amdgpu.h          |   8 +
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_device.c   |   3 +
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c      |   4 +
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h      |   6 +
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_profiler.c | 166 +++++++++++++++++++
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_profiler.h |  38 +++++
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c    |  95 ++++++++++-
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h    |   2 +
>>   drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c       |  11 ++
>>   drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c       |  11 ++
>>   drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c       |  11 ++
>>   include/uapi/drm/amdgpu_drm.h                |  36 ++++
>>   13 files changed, 390 insertions(+), 3 deletions(-)
>>   create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_profiler.c
>>   create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_profiler.h
>>

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* Re: [RFC 02/10] drm/amdgpu: add device-wide PMC config
  2026-09-24  3:23     ` Zhu, Lingshan
@ 2026-09-24 15:40       ` James Zhu
  2026-10-08  7:50         ` Zhu, Lingshan
  0 siblings, 1 reply; 23+ messages in thread
From: James Zhu @ 2026-09-24 15:40 UTC (permalink / raw)
  To: Zhu, Lingshan, Alexander.Deucher, felix.kuehling; +Cc: Ray.Huang, amd-gfx

[-- Attachment #1: Type: text/plain, Size: 2973 bytes --]


On 2026-09-23 23:23, Zhu, Lingshan wrote:
> On 9/23/2026 10:13 PM, James Zhu wrote:
>>
>> On 2026-09-22 05:34, Zhu Lingshan wrote:
>>> This commit implements a device-wide PMC config
>>> for amdgpu, which including the profiling owner,
>>> and the profiling enablement indicator.
>> [JZ] I think it should be render-node wide, not device-wide
> Hi James,
>
> It could be, but we don't have a requirement document defines the scope.
>
> But normally a profiler is a device scope,
> I see KFD profiler operates on all queues under the device queue manager

[JZ] One device could be split into multiple nodes with different 
processes running.

I am wondering if this is really we want.  Ben may comment on it.

>
> Thanks
> Lingshan
>>>
>>> Signed-off-by: Zhu Lingshan <lingshan.zhu@amd.com>
>>> ---
>>>   drivers/gpu/drm/amd/amdgpu/amdgpu.h        | 8 ++++++++
>>>   drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 3 +++
>>>   2 files changed, 11 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>>> index 8eff6b9ebe81..45897dca802f 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>>> @@ -620,6 +620,12 @@ enum amdgpu_enforce_isolation_mode {
>>>       AMDGPU_ENFORCE_ISOLATION_NO_CLEANER_SHADER = 3,
>>>   };
>>>   +struct amdgpu_pmc_profiler {
>>> +    struct mutex        lock;
>>> +    struct drm_file        *owner;
>>> +    bool            enable;
>>> +};
>>> +
>>>   struct amdgpu_device {
>>>       struct device            *dev;
>>>       struct pci_dev            *pdev;
>>> @@ -818,6 +824,8 @@ struct amdgpu_device {
>>>        */
>>>       struct xarray userq_doorbell_xa;
>>>   +    struct amdgpu_pmc_profiler    pmc_profiler;
>>> +
>>>       /* df */
>>>       struct amdgpu_df                df;
>>>   diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>>> index c924a55fd16f..74ed42e53264 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>>> @@ -3673,6 +3673,7 @@ int amdgpu_device_init(struct amdgpu_device 
>>> *adev,
>>>       mutex_init(&adev->pm.stable_pstate_ctx_lock);
>>>       mutex_init(&adev->benchmark_mutex);
>>>       mutex_init(&adev->gfx.reset_sem_mutex);
>>> +    mutex_init(&adev->pmc_profiler.lock);
>>>         /* Associate locks with lockdep classes for ordering 
>>> validation */
>>>       amdgpu_lockdep_set_class(adev);
>>> @@ -4244,6 +4245,8 @@ void amdgpu_device_fini_sw(struct 
>>> amdgpu_device *adev)
>>>       kfree(adev->pci_state);
>>>       kfree(adev->pcie_reset_ctx.swds_pcistate);
>>>       kfree(adev->pcie_reset_ctx.swus_pcistate);
>>> +
>>> +    mutex_destroy(&adev->pmc_profiler.lock);
>>>   }
>>>     /**

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* Re: [RFC 01/10] drm/amdgpu: implement PMC ioctl framework
  2026-09-24  3:38     ` Zhu, Lingshan
@ 2026-09-24 15:49       ` James Zhu
  2026-10-08  7:59         ` Zhu, Lingshan
  0 siblings, 1 reply; 23+ messages in thread
From: James Zhu @ 2026-09-24 15:49 UTC (permalink / raw)
  To: Zhu, Lingshan, Alexander.Deucher, felix.kuehling; +Cc: Ray.Huang, amd-gfx

[-- Attachment #1: Type: text/plain, Size: 10603 bytes --]


On 2026-09-23 23:38, Zhu, Lingshan wrote:
> On 9/23/2026 10:17 PM, James Zhu wrote:
>>
>> On 2026-09-22 05:34, Zhu Lingshan wrote:
>>> This commit implements basic ioctl framework for PMC,
>>> including basic operations.
>>>
>>> This commit also implements AMDGPU_PROFILER_OP_VERSION
>>> which report profiler version to the user space.
>>>
>>> Signed-off-by: Zhu Lingshan<lingshan.zhu@amd.com>
>>> ---
>>>   drivers/gpu/drm/amd/amdgpu/Makefile          |  2 +-
>>>   drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c      |  2 +
>>>   drivers/gpu/drm/amd/amdgpu/amdgpu_profiler.c | 44 
>>> ++++++++++++++++++++
>>>   drivers/gpu/drm/amd/amdgpu/amdgpu_profiler.h | 33 +++++++++++++++
>>>   include/uapi/drm/amdgpu_drm.h                | 36 ++++++++++++++++
>>>   5 files changed, 116 insertions(+), 1 deletion(-)
>>>   create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_profiler.c
>>>   create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_profiler.h
>>>
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile 
>>> b/drivers/gpu/drm/amd/amdgpu/Makefile
>>> index 6fb0a913e33b..d7db69e9d6a0 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/Makefile
>>> +++ b/drivers/gpu/drm/amd/amdgpu/Makefile
>>> @@ -72,7 +72,7 @@ amdgpu-y += amdgpu_device.o amdgpu_reg_access.o 
>>> amdgpu_doorbell_mgr.o amdgpu_kms
>>>       amdgpu_eeprom.o amdgpu_mca.o amdgpu_psp_ta.o amdgpu_lsdma.o 
>>> amdgpu_lockdep.o \
>>>       amdgpu_ring_mux.o amdgpu_xcp.o amdgpu_seq64.o 
>>> amdgpu_dev_coredump.o \
>>>       amdgpu_cper.o amdgpu_userq_fence.o amdgpu_eviction_fence.o 
>>> amdgpu_ip.o \
>>> -    amdgpu_wb.o amdgpu_cwsr.o amdgpu_events.o
>>> +    amdgpu_wb.o amdgpu_cwsr.o amdgpu_events.o amdgpu_profiler.o
>>>     amdgpu-$(CONFIG_PROC_FS) += amdgpu_fdinfo.o
>>>   diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
>>> index 7c473f60bd28..a98c4a47e196 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
>>> @@ -55,6 +55,7 @@
>>>   #include "amdgpu_cwsr.h"
>>>   #include "amdgpu_userq_fence.h"
>>>   #include "../amdxcp/amdgpu_xcp_drv.h"
>>> +#include "amdgpu_profiler.h"
>>>     /*
>>>    * KMS wrapper.
>>> @@ -3096,6 +3097,7 @@ const struct drm_ioctl_desc 
>>> amdgpu_ioctls_kms[] = {
>>>       DRM_IOCTL_DEF_DRV(AMDGPU_USERQ_WAIT, amdgpu_userq_wait_ioctl, 
>>> DRM_AUTH|DRM_RENDER_ALLOW),
>>>       DRM_IOCTL_DEF_DRV(AMDGPU_GEM_LIST_HANDLES, 
>>> amdgpu_gem_list_handles_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
>>>       DRM_IOCTL_DEF_DRV(AMDGPU_PROC_OPTIONS, 
>>> amdgpu_proc_options_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
>>> +    DRM_IOCTL_DEF_DRV(AMDGPU_PROFILER, amdgpu_profiler_ioctl, 
>>> DRM_AUTH|DRM_RENDER_ALLOW),
>>>   };
>>>     static const struct drm_driver amdgpu_kms_driver = {
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_profiler.c 
>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_profiler.c
>>> new file mode 100644
>>> index 000000000000..04902696adab
>>> --- /dev/null
>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_profiler.c
>>> @@ -0,0 +1,44 @@
>>> +// SPDX-License-Identifier: MIT
>>> +/*
>>> + * Copyright 2026 Advanced Micro Devices, Inc.
>>> + *
>>> + * Permission is hereby granted, free of charge, to any person 
>>> obtaining a
>>> + * copy of this software and associated documentation files (the 
>>> "Software"),
>>> + * to deal in the Software without restriction, including without 
>>> limitation
>>> + * the rights to use, copy, modify, merge, publish, distribute, 
>>> sublicense,
>>> + * and/or sell copies of the Software, and to permit persons to 
>>> whom the
>>> + * Software is furnished to do so, subject to the following 
>>> conditions:
>>> + *
>>> + * The above copyright notice and this permission notice shall be 
>>> included in
>>> + * all copies or substantial portions of the Software.
>>> + *
>>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 
>>> EXPRESS OR
>>> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 
>>> MERCHANTABILITY,
>>> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO 
>>> EVENT SHALL
>>> + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, 
>>> DAMAGES OR
>>> + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 
>>> OTHERWISE,
>>> + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 
>>> USE OR
>>> + * OTHER DEALINGS IN THE SOFTWARE.
>>> + *
>>> + */
>>> +
>>> +#include <linux/errno.h>
>>> +#include <drm/amdgpu_drm.h>
>>> +#include "amdgpu_profiler.h"
>>> +
>>> +int amdgpu_profiler_ioctl(struct drm_device *dev, void *data, 
>>> struct drm_file *filp)
>>> +{
>>> +    struct drm_amdgpu_profiler_args *args = data;
>>> +
>>> +    switch (args->op) {
>>> +    case AMDGPU_PROFILER_OP_VERSION:
>>> +        args->version = AMDGPU_PROFILER_VERSION_NUM;
>>> +        return 0;
>>> +    case AMDGPU_PROFILER_OP_RESERVE:
>>> +        return -EOPNOTSUPP;
>>> +    case AMDGPU_PROFILER_OP_PMC:
>>> +        return -EOPNOTSUPP;
>>> +    default:
>>> +        return -EINVAL;
>>> +    }
>>> +}
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_profiler.h 
>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_profiler.h
>>> new file mode 100644
>>> index 000000000000..c27b5f9b3ff0
>>> --- /dev/null
>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_profiler.h
>>> @@ -0,0 +1,33 @@
>>> +/* SPDX-License-Identifier: MIT */
>>> +/*
>>> + * Copyright 2026 Advanced Micro Devices, Inc.
>>> + *
>>> + * Permission is hereby granted, free of charge, to any person 
>>> obtaining a
>>> + * copy of this software and associated documentation files (the 
>>> "Software"),
>>> + * to deal in the Software without restriction, including without 
>>> limitation
>>> + * the rights to use, copy, modify, merge, publish, distribute, 
>>> sublicense,
>>> + * and/or sell copies of the Software, and to permit persons to 
>>> whom the
>>> + * Software is furnished to do so, subject to the following 
>>> conditions:
>>> + *
>>> + * The above copyright notice and this permission notice shall be 
>>> included in
>>> + * all copies or substantial portions of the Software.
>>> + *
>>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 
>>> EXPRESS OR
>>> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 
>>> MERCHANTABILITY,
>>> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO 
>>> EVENT SHALL
>>> + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, 
>>> DAMAGES OR
>>> + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 
>>> OTHERWISE,
>>> + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 
>>> USE OR
>>> + * OTHER DEALINGS IN THE SOFTWARE.
>>> + *
>>> + */
>>> +
>>> +#ifndef __AMDGPU_PROFILER_H__
>>> +#define __AMDGPU_PROFILER_H__
>>> +
>>> +#include <drm/drm_device.h>
>>> +#include <drm/drm_file.h>
>>> +
>>> +int amdgpu_profiler_ioctl(struct drm_device *dev, void *data, 
>>> struct drm_file *filp);
>>> +
>>> +#endif /* __AMDGPU_PROFILER_H__ */
>>> diff --git a/include/uapi/drm/amdgpu_drm.h 
>>> b/include/uapi/drm/amdgpu_drm.h
>>> index 9222be9a6d2a..acc63804ba8c 100644
>>> --- a/include/uapi/drm/amdgpu_drm.h
>>> +++ b/include/uapi/drm/amdgpu_drm.h
>>> @@ -60,6 +60,7 @@ extern "C" {
>>>   #define DRM_AMDGPU_GEM_LIST_HANDLES    0x19
>>>   #define DRM_AMDGPU_PROC_OPTIONS        0x1A
>>>   #define DRM_AMDGPU_CWSR            0x1B
>>> +#define DRM_AMDGPU_PROFILER        0x1C
>>>     #define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + 
>>> DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create)
>>>   #define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + 
>>> DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap)
>>> @@ -83,6 +84,7 @@ extern "C" {
>>>   #define DRM_IOCTL_AMDGPU_GEM_LIST_HANDLES 
>>> DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_LIST_HANDLES, struct 
>>> drm_amdgpu_gem_list_handles)
>>>   #define DRM_IOCTL_AMDGPU_PROC_OPTIONS DRM_IOWR(DRM_COMMAND_BASE + 
>>> DRM_AMDGPU_PROC_OPTIONS, struct drm_amdgpu_proc_options)
>>>   #define DRM_IOCTL_AMDGPU_CWSR    DRM_IOWR(DRM_COMMAND_BASE + 
>>> DRM_AMDGPU_CWSR, union drm_amdgpu_cwsr)
>>> +#define DRM_IOCTL_AMDGPU_PROFILER DRM_IOWR(DRM_COMMAND_BASE + 
>>> DRM_AMDGPU_PROFILER, struct drm_amdgpu_profiler_args)
>>>     /**
>>>    * DOC: memory domains
>>> @@ -1809,6 +1811,40 @@ struct drm_amdgpu_proc_options {
>>>       } kfd_sigbus_delay;
>>>   };
>>>   +#define AMDGPU_PROFILER_VERSION_NUM    1
>>> +
>>> +enum amdgpu_profiler_ops {
>>> +    AMDGPU_PROFILER_OP_VERSION = 1,
>>> +    AMDGPU_PROFILER_OP_RESERVE = 2,
>> [JZ] the implementation tells that it is 
>> AMDGPU_PROFILER_OP_PMC_RESERVE, it is better to put it under new PMC 
>> sub-ioctl op
> Do you mean implement it like {bool pmc_enable, bool reserve} in a struct? I am not sure it is a good idea
> and this reservation design is a improvement. Because it separates the reserve(lock) and unreserve(unlock),
> so we don't need to keep the reservation during the PMC operations in a complex way, and we won't meet
> the problems like how to handle the situation where the user tries to unlock but keeps enable = 1.
[JZ] profiler includes PMC, PC sampling, SPM etc. do the other feature 
need reservation also?
>
> Thanks
> Lingshan
>>> +    AMDGPU_PROFILER_OP_PMC = 3,
>>> +};
>>> +
>>> +enum amdgpu_profiler_reserve_ops {
>>> +    /* release the device resertaion, only the reservation owner do 
>>> this */
>>> +    AMDGPU_PROFILER_RELEASE = 0,
>>> +    /* reserve the device profiler */
>>> +    AMDGPU_PROFILER_RESERVE = 1,
>>> +    /* Clear the device profiler reservation, in case the reservation
>>> +     * owner can no longer release the reservation(e.g., it crashes),
>>> +     * This operation does not take the reseration nor touch 
>>> profielr state
>>> +     */
>>> +    AMDGPU_PROFILER_CLEAR_RESERVATION = 2,
>>> +};
>>> +
>>> +struct drm_amdgpu_profiler_args {
>>> +    /* enum amdgpu_profiler_ops */
>>> +    __u8 op;
>>> +    __u8 pad[3];
>>> +    union {
>>> +        /* AMDGPU_PROFILER_OP_RESERVE: enum 
>>> amdgpu_profiler_reserve_ops */
>>> +        __u8 reserve;
>>> +        /* AMDGPU_PROFILER_OP_PMC: 1 enable PMC, 0 disable PMC */
>>> +        __u8 perfcount_enable;
>>> +        /* AMDGPU_PROFILER_OP_VERSION: AMDGPU_PROFILER_VERSION_NUM */
>>> +        __u32 version;
>>> +    };
>>> +};
>>> +
>>>   #if defined(__cplusplus)
>>>   }
>>>   #endif

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* Re: [RFC 02/10] drm/amdgpu: add device-wide PMC config
  2026-09-24 15:40       ` James Zhu
@ 2026-10-08  7:50         ` Zhu, Lingshan
  0 siblings, 0 replies; 23+ messages in thread
From: Zhu, Lingshan @ 2026-10-08  7:50 UTC (permalink / raw)
  To: James Zhu, Alexander.Deucher, felix.kuehling; +Cc: Ray.Huang, amd-gfx

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On 9/24/2026 11:40 PM, James Zhu wrote:

>
> On 2026-09-23 23:23, Zhu, Lingshan wrote:
>> On 9/23/2026 10:13 PM, James Zhu wrote:
>>>
>>> On 2026-09-22 05:34, Zhu Lingshan wrote:
>>>> This commit implements a device-wide PMC config
>>>> for amdgpu, which including the profiling owner,
>>>> and the profiling enablement indicator.
>>> [JZ] I think it should be render-node wide, not device-wide
>> Hi James,
>>
>> It could be, but we don't have a requirement document defines the scope.
>>
>> But normally a profiler is a device scope,
>> I see KFD profiler operates on all queues under the device queue manager
>
> [JZ] One device could be split into multiple nodes with different
> processes running.
>
> I am wondering if this is really we want.  Ben may comment on it.

Hello James,

Sorry for the late reply, it was mid-autumn festival and national holidays.

In my understanding, there is only one set of PMC registers on the device, so it should
be device scope.

Thanks
Lingshan

>
>>
>> Thanks
>> Lingshan
>>>>
>>>> Signed-off-by: Zhu Lingshan <lingshan.zhu@amd.com>
>>>> ---
>>>>   drivers/gpu/drm/amd/amdgpu/amdgpu.h        | 8 ++++++++
>>>>   drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 3 +++
>>>>   2 files changed, 11 insertions(+)
>>>>
>>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>>>> index 8eff6b9ebe81..45897dca802f 100644
>>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>>>> @@ -620,6 +620,12 @@ enum amdgpu_enforce_isolation_mode {
>>>>       AMDGPU_ENFORCE_ISOLATION_NO_CLEANER_SHADER = 3,
>>>>   };
>>>>   +struct amdgpu_pmc_profiler {
>>>> +    struct mutex        lock;
>>>> +    struct drm_file        *owner;
>>>> +    bool            enable;
>>>> +};
>>>> +
>>>>   struct amdgpu_device {
>>>>       struct device            *dev;
>>>>       struct pci_dev            *pdev;
>>>> @@ -818,6 +824,8 @@ struct amdgpu_device {
>>>>        */
>>>>       struct xarray userq_doorbell_xa;
>>>>   +    struct amdgpu_pmc_profiler    pmc_profiler;
>>>> +
>>>>       /* df */
>>>>       struct amdgpu_df                df;
>>>>   diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>>>> index c924a55fd16f..74ed42e53264 100644
>>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>>>> @@ -3673,6 +3673,7 @@ int amdgpu_device_init(struct amdgpu_device
>>>> *adev,
>>>>       mutex_init(&adev->pm.stable_pstate_ctx_lock);
>>>>       mutex_init(&adev->benchmark_mutex);
>>>>       mutex_init(&adev->gfx.reset_sem_mutex);
>>>> +    mutex_init(&adev->pmc_profiler.lock);
>>>>         /* Associate locks with lockdep classes for ordering
>>>> validation */
>>>>       amdgpu_lockdep_set_class(adev);
>>>> @@ -4244,6 +4245,8 @@ void amdgpu_device_fini_sw(struct
>>>> amdgpu_device *adev)
>>>>       kfree(adev->pci_state);
>>>>       kfree(adev->pcie_reset_ctx.swds_pcistate);
>>>>       kfree(adev->pcie_reset_ctx.swus_pcistate);
>>>> +
>>>> +    mutex_destroy(&adev->pmc_profiler.lock);
>>>>   }
>>>>     /**

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* Re: [RFC 01/10] drm/amdgpu: implement PMC ioctl framework
  2026-09-24 15:49       ` James Zhu
@ 2026-10-08  7:59         ` Zhu, Lingshan
  0 siblings, 0 replies; 23+ messages in thread
From: Zhu, Lingshan @ 2026-10-08  7:59 UTC (permalink / raw)
  To: James Zhu, Alexander.Deucher, felix.kuehling, Welton, Benjamin
  Cc: Ray.Huang, amd-gfx

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On 9/24/2026 11:49 PM, James Zhu wrote:

>
> On 2026-09-23 23:38, Zhu, Lingshan wrote:
>> On 9/23/2026 10:17 PM, James Zhu wrote:
>>>
>>> On 2026-09-22 05:34, Zhu Lingshan wrote:
>>>> This commit implements basic ioctl framework for PMC,
>>>> including basic operations.
>>>>
>>>> This commit also implements AMDGPU_PROFILER_OP_VERSION
>>>> which report profiler version to the user space.
>>>>
>>>> Signed-off-by: Zhu Lingshan<lingshan.zhu@amd.com>
>>>> ---
>>>>   drivers/gpu/drm/amd/amdgpu/Makefile          |  2 +-
>>>>   drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c      |  2 +
>>>>   drivers/gpu/drm/amd/amdgpu/amdgpu_profiler.c | 44
>>>> ++++++++++++++++++++
>>>>   drivers/gpu/drm/amd/amdgpu/amdgpu_profiler.h | 33 +++++++++++++++
>>>>   include/uapi/drm/amdgpu_drm.h                | 36 ++++++++++++++++
>>>>   5 files changed, 116 insertions(+), 1 deletion(-)
>>>>   create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_profiler.c
>>>>   create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_profiler.h
>>>>
>>>> diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile
>>>> b/drivers/gpu/drm/amd/amdgpu/Makefile
>>>> index 6fb0a913e33b..d7db69e9d6a0 100644
>>>> --- a/drivers/gpu/drm/amd/amdgpu/Makefile
>>>> +++ b/drivers/gpu/drm/amd/amdgpu/Makefile
>>>> @@ -72,7 +72,7 @@ amdgpu-y += amdgpu_device.o amdgpu_reg_access.o
>>>> amdgpu_doorbell_mgr.o amdgpu_kms
>>>>       amdgpu_eeprom.o amdgpu_mca.o amdgpu_psp_ta.o amdgpu_lsdma.o
>>>> amdgpu_lockdep.o \
>>>>       amdgpu_ring_mux.o amdgpu_xcp.o amdgpu_seq64.o
>>>> amdgpu_dev_coredump.o \
>>>>       amdgpu_cper.o amdgpu_userq_fence.o amdgpu_eviction_fence.o
>>>> amdgpu_ip.o \
>>>> -    amdgpu_wb.o amdgpu_cwsr.o amdgpu_events.o
>>>> +    amdgpu_wb.o amdgpu_cwsr.o amdgpu_events.o amdgpu_profiler.o
>>>>     amdgpu-$(CONFIG_PROC_FS) += amdgpu_fdinfo.o
>>>>   diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
>>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
>>>> index 7c473f60bd28..a98c4a47e196 100644
>>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
>>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
>>>> @@ -55,6 +55,7 @@
>>>>   #include "amdgpu_cwsr.h"
>>>>   #include "amdgpu_userq_fence.h"
>>>>   #include "../amdxcp/amdgpu_xcp_drv.h"
>>>> +#include "amdgpu_profiler.h"
>>>>     /*
>>>>    * KMS wrapper.
>>>> @@ -3096,6 +3097,7 @@ const struct drm_ioctl_desc
>>>> amdgpu_ioctls_kms[] = {
>>>>       DRM_IOCTL_DEF_DRV(AMDGPU_USERQ_WAIT, amdgpu_userq_wait_ioctl,
>>>> DRM_AUTH|DRM_RENDER_ALLOW),
>>>>       DRM_IOCTL_DEF_DRV(AMDGPU_GEM_LIST_HANDLES,
>>>> amdgpu_gem_list_handles_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
>>>>       DRM_IOCTL_DEF_DRV(AMDGPU_PROC_OPTIONS,
>>>> amdgpu_proc_options_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
>>>> +    DRM_IOCTL_DEF_DRV(AMDGPU_PROFILER, amdgpu_profiler_ioctl,
>>>> DRM_AUTH|DRM_RENDER_ALLOW),
>>>>   };
>>>>     static const struct drm_driver amdgpu_kms_driver = {
>>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_profiler.c
>>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_profiler.c
>>>> new file mode 100644
>>>> index 000000000000..04902696adab
>>>> --- /dev/null
>>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_profiler.c
>>>> @@ -0,0 +1,44 @@
>>>> +// SPDX-License-Identifier: MIT
>>>> +/*
>>>> + * Copyright 2026 Advanced Micro Devices, Inc.
>>>> + *
>>>> + * Permission is hereby granted, free of charge, to any person
>>>> obtaining a
>>>> + * copy of this software and associated documentation files (the
>>>> "Software"),
>>>> + * to deal in the Software without restriction, including without
>>>> limitation
>>>> + * the rights to use, copy, modify, merge, publish, distribute,
>>>> sublicense,
>>>> + * and/or sell copies of the Software, and to permit persons to
>>>> whom the
>>>> + * Software is furnished to do so, subject to the following
>>>> conditions:
>>>> + *
>>>> + * The above copyright notice and this permission notice shall be
>>>> included in
>>>> + * all copies or substantial portions of the Software.
>>>> + *
>>>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
>>>> EXPRESS OR
>>>> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
>>>> MERCHANTABILITY,
>>>> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO
>>>> EVENT SHALL
>>>> + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM,
>>>> DAMAGES OR
>>>> + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
>>>> OTHERWISE,
>>>> + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
>>>> USE OR
>>>> + * OTHER DEALINGS IN THE SOFTWARE.
>>>> + *
>>>> + */
>>>> +
>>>> +#include <linux/errno.h>
>>>> +#include <drm/amdgpu_drm.h>
>>>> +#include "amdgpu_profiler.h"
>>>> +
>>>> +int amdgpu_profiler_ioctl(struct drm_device *dev, void *data,
>>>> struct drm_file *filp)
>>>> +{
>>>> +    struct drm_amdgpu_profiler_args *args = data;
>>>> +
>>>> +    switch (args->op) {
>>>> +    case AMDGPU_PROFILER_OP_VERSION:
>>>> +        args->version = AMDGPU_PROFILER_VERSION_NUM;
>>>> +        return 0;
>>>> +    case AMDGPU_PROFILER_OP_RESERVE:
>>>> +        return -EOPNOTSUPP;
>>>> +    case AMDGPU_PROFILER_OP_PMC:
>>>> +        return -EOPNOTSUPP;
>>>> +    default:
>>>> +        return -EINVAL;
>>>> +    }
>>>> +}
>>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_profiler.h
>>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_profiler.h
>>>> new file mode 100644
>>>> index 000000000000..c27b5f9b3ff0
>>>> --- /dev/null
>>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_profiler.h
>>>> @@ -0,0 +1,33 @@
>>>> +/* SPDX-License-Identifier: MIT */
>>>> +/*
>>>> + * Copyright 2026 Advanced Micro Devices, Inc.
>>>> + *
>>>> + * Permission is hereby granted, free of charge, to any person
>>>> obtaining a
>>>> + * copy of this software and associated documentation files (the
>>>> "Software"),
>>>> + * to deal in the Software without restriction, including without
>>>> limitation
>>>> + * the rights to use, copy, modify, merge, publish, distribute,
>>>> sublicense,
>>>> + * and/or sell copies of the Software, and to permit persons to
>>>> whom the
>>>> + * Software is furnished to do so, subject to the following
>>>> conditions:
>>>> + *
>>>> + * The above copyright notice and this permission notice shall be
>>>> included in
>>>> + * all copies or substantial portions of the Software.
>>>> + *
>>>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
>>>> EXPRESS OR
>>>> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
>>>> MERCHANTABILITY,
>>>> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO
>>>> EVENT SHALL
>>>> + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM,
>>>> DAMAGES OR
>>>> + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
>>>> OTHERWISE,
>>>> + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
>>>> USE OR
>>>> + * OTHER DEALINGS IN THE SOFTWARE.
>>>> + *
>>>> + */
>>>> +
>>>> +#ifndef __AMDGPU_PROFILER_H__
>>>> +#define __AMDGPU_PROFILER_H__
>>>> +
>>>> +#include <drm/drm_device.h>
>>>> +#include <drm/drm_file.h>
>>>> +
>>>> +int amdgpu_profiler_ioctl(struct drm_device *dev, void *data,
>>>> struct drm_file *filp);
>>>> +
>>>> +#endif /* __AMDGPU_PROFILER_H__ */
>>>> diff --git a/include/uapi/drm/amdgpu_drm.h
>>>> b/include/uapi/drm/amdgpu_drm.h
>>>> index 9222be9a6d2a..acc63804ba8c 100644
>>>> --- a/include/uapi/drm/amdgpu_drm.h
>>>> +++ b/include/uapi/drm/amdgpu_drm.h
>>>> @@ -60,6 +60,7 @@ extern "C" {
>>>>   #define DRM_AMDGPU_GEM_LIST_HANDLES    0x19
>>>>   #define DRM_AMDGPU_PROC_OPTIONS        0x1A
>>>>   #define DRM_AMDGPU_CWSR            0x1B
>>>> +#define DRM_AMDGPU_PROFILER        0x1C
>>>>     #define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE +
>>>> DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create)
>>>>   #define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE +
>>>> DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap)
>>>> @@ -83,6 +84,7 @@ extern "C" {
>>>>   #define DRM_IOCTL_AMDGPU_GEM_LIST_HANDLES
>>>> DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_LIST_HANDLES, struct
>>>> drm_amdgpu_gem_list_handles)
>>>>   #define DRM_IOCTL_AMDGPU_PROC_OPTIONS DRM_IOWR(DRM_COMMAND_BASE +
>>>> DRM_AMDGPU_PROC_OPTIONS, struct drm_amdgpu_proc_options)
>>>>   #define DRM_IOCTL_AMDGPU_CWSR    DRM_IOWR(DRM_COMMAND_BASE +
>>>> DRM_AMDGPU_CWSR, union drm_amdgpu_cwsr)
>>>> +#define DRM_IOCTL_AMDGPU_PROFILER DRM_IOWR(DRM_COMMAND_BASE +
>>>> DRM_AMDGPU_PROFILER, struct drm_amdgpu_profiler_args)
>>>>     /**
>>>>    * DOC: memory domains
>>>> @@ -1809,6 +1811,40 @@ struct drm_amdgpu_proc_options {
>>>>       } kfd_sigbus_delay;
>>>>   };
>>>>   +#define AMDGPU_PROFILER_VERSION_NUM    1
>>>> +
>>>> +enum amdgpu_profiler_ops {
>>>> +    AMDGPU_PROFILER_OP_VERSION = 1,
>>>> +    AMDGPU_PROFILER_OP_RESERVE = 2,
>>> [JZ] the implementation tells that it is
>>> AMDGPU_PROFILER_OP_PMC_RESERVE, it is better to put it under new PMC
>>> sub-ioctl op
>> Do you mean implement it like {bool pmc_enable, bool reserve} in a
>> struct? I am not sure it is a good idea
>> and this reservation design is a improvement. Because it separates
>> the reserve(lock) and unreserve(unlock),
>> so we don't need to keep the reservation during the PMC operations in
>> a complex way, and we won't meet
>> the problems like how to handle the situation where the user tries to
>> unlock but keeps enable = 1.
> [JZ] profiler includes PMC, PC sampling, SPM etc. do the other feature
> need reservation also?

Hello James,

I think we should implement reservations, but in different ways:
1) if it is a device scope profiler, then we should implement a reservation mechanism like this one.
2) if the profiler facility allows running multiple type of profiler concurrently(e.g, PMC and PC together),
and some of the profiler may collect correlate data, then we need reservation because we don't want a profiler to
sniff another.
3) if it is a dri node or any sub function profiler, then we should implement a proper reservation in that level.

I believe we need a device level reservation for PMC.

Thanks
Lingshan

>>
>> Thanks
>> Lingshan
>>>> +    AMDGPU_PROFILER_OP_PMC = 3,
>>>> +};
>>>> +
>>>> +enum amdgpu_profiler_reserve_ops {
>>>> +    /* release the device resertaion, only the reservation owner
>>>> do this */
>>>> +    AMDGPU_PROFILER_RELEASE = 0,
>>>> +    /* reserve the device profiler */
>>>> +    AMDGPU_PROFILER_RESERVE = 1,
>>>> +    /* Clear the device profiler reservation, in case the reservation
>>>> +     * owner can no longer release the reservation(e.g., it crashes),
>>>> +     * This operation does not take the reseration nor touch
>>>> profielr state
>>>> +     */
>>>> +    AMDGPU_PROFILER_CLEAR_RESERVATION = 2,
>>>> +};
>>>> +
>>>> +struct drm_amdgpu_profiler_args {
>>>> +    /* enum amdgpu_profiler_ops */
>>>> +    __u8 op;
>>>> +    __u8 pad[3];
>>>> +    union {
>>>> +        /* AMDGPU_PROFILER_OP_RESERVE: enum
>>>> amdgpu_profiler_reserve_ops */
>>>> +        __u8 reserve;
>>>> +        /* AMDGPU_PROFILER_OP_PMC: 1 enable PMC, 0 disable PMC */
>>>> +        __u8 perfcount_enable;
>>>> +        /* AMDGPU_PROFILER_OP_VERSION: AMDGPU_PROFILER_VERSION_NUM */
>>>> +        __u32 version;
>>>> +    };
>>>> +};
>>>> +
>>>>   #if defined(__cplusplus)
>>>>   }
>>>>   #endif

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^ permalink raw reply	[flat|nested] 23+ messages in thread

end of thread, other threads:[~2026-10-08  7:59 UTC | newest]

Thread overview: 23+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2026-09-22  9:34 [RFC 00/10] amdgpu: implement Performance Monitor Counter support Zhu Lingshan
2026-09-22  9:34 ` [RFC 01/10] drm/amdgpu: implement PMC ioctl framework Zhu Lingshan
2026-09-23 14:17   ` James Zhu
2026-09-24  3:38     ` Zhu, Lingshan
2026-09-24 15:49       ` James Zhu
2026-10-08  7:59         ` Zhu, Lingshan
2026-09-22  9:34 ` [RFC 02/10] drm/amdgpu: add device-wide PMC config Zhu Lingshan
2026-09-23 14:13   ` James Zhu
2026-09-24  3:23     ` Zhu, Lingshan
2026-09-24 15:40       ` James Zhu
2026-10-08  7:50         ` Zhu, Lingshan
2026-09-22  9:34 ` [RFC 03/10] drm/amdgpu: introduce PMC ioctl handler Zhu Lingshan
2026-09-22  9:34 ` [RFC 04/10] drm/amdgpu: implement reservation mechanism for PMC Zhu Lingshan
2026-09-22  9:34 ` [RFC 05/10] drm/amdgpu: set device-wide PMC enablement indicator Zhu Lingshan
2026-09-22  9:34 ` [RFC 06/10] drm/amdgpu: GFX11: set mqd->perfcount from mqd_prop Zhu Lingshan
2026-09-22  9:34 ` [RFC 07/10] drm/amdgpu: GFX12: " Zhu Lingshan
2026-09-22  9:34 ` [RFC 08/10] drm/amdgpu: GFX12.1: " Zhu Lingshan
2026-09-22  9:34 ` [RFC 09/10] drm/amdgpu: implement device PMC handler Zhu Lingshan
2026-09-22  9:34 ` [RFC 10/10] drm/amdgpu: set userq perf state before publish it Zhu Lingshan
2026-09-23 14:02 ` [RFC 00/10] amdgpu: implement Performance Monitor Counter support James Zhu
2026-09-23 15:02   ` Welton, Benjamin
2026-09-23 15:11     ` James Zhu
2026-09-24  3:40     ` Zhu, Lingshan

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