* [PATCH 000/207] Add Support for Sienna Cichlid
@ 2020-06-01 17:59 Alex Deucher
2020-06-01 17:59 ` [PATCH 005/207] drm/amdgpu: add sienna_cichlid asic type Alex Deucher
` (82 more replies)
0 siblings, 83 replies; 88+ messages in thread
From: Alex Deucher @ 2020-06-01 17:59 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher
Sienna Cichlid is a GPU from AMD. This patch set adds support for it
including power management, display, kfd, interrupts, gfx, multi-media,
etc. The new register headers are really big so I haven't sent them to
the list. You can view the new patches including the register headers
on the following git branch:
https://cgit.freedesktop.org/~agd5f/linux/log/?h=amd-staging-drm-next-sienna_cichlid
Thanks,
Alex
Alex Deucher (2):
drm/amdgpu/mes10.1: add no scheduler flag for mes
drm/amdgpu/vcn3.0: schedule instance 0 for decode and 1 for encode
Bhawanpreet Lakha (28):
drm/amd/display: Add DCN3 chip ids
drm/amd/display: Add DCN3 DIO
drm/amd/display: Add DCN3 CLK_MGR
drm/amd/display: Add DCN3 DCCG
drm/amd/display: Add DCN3 OPTC
drm/amd/display: Add DCN3 OPP header
drm/amd/display: Add DCN3 MPC
drm/amd/display: Add DCN3 DPP
drm/amd/display: Add DCN3 HUBHUB
drm/amd/display: Add DCN3 HUBP
drm/amd/display: Add DCN3 MMHUBHUB
drm/amd/display: Add DCN3 DWB
drm/amd/display: Add DCN3 DML
drm/amd/display: Add DCN3 IRQ
drm/amd/display: Add DCN3 GPIO
drm/amd/display: Add DCN3 DMUB
drm/amd/display: Add DCN3 HWSEQ
drm/amd/display: Add DCN3 Support in DM (v2)
drm/amd/display: Add DCN3 Resource
drm/amd/display: Add DCN3 Command Table Helpers
drm/amd/display: Add DCN3 AFMT
drm/amd/display: Add DCN3 VPG
drm/amd/display: Init function tables for DCN3
drm/amd/display: Handle RGBE_ALPHA Pixel Format
drm/amd/display: Remove Unused Registers
drm/amdgpu: Enable DM block for DCN3
drm/amd/display: Add DCN3 blocks to Makefile
drm/amd/display: Add DCN3 to Kconfig
Boyuan Zhang (11):
drm/amdgpu: add clock gating DPG mode for VCN3.0
drm/amdgpu: add mc resume DPG mode for VCN3.0
drm/amdgpu: add start DPG mode for VCN3.0
drm/amdgpu: add stop DPG mode for VCN3.0
drm/amdgpu: add pause DPG mode for VCN3.0
drm/amdgpu: set indirect sram mode for VCN3.0
drm/amdgpu: add internal reg offset translation for VCN inst 1
drm/amdgpu: rename macro for VCN1.0
drm/amdgpu: rename macro for VCN2.0 2.5 and 3.0
drm/amdgpu: add workaround for issue in DPG for VCN3.0
drm/amdgpu: enable DPG mode for VCN3.0
Dmytro Laktyushkin (1):
drm/amd/display: fix and simplify pipe split logic for DCN3
Evan Quan (1):
drm/amd/powerplay: let PMFW to handle the features disablement on BACO
in V2
Hawking Zhang (7):
drm/amdgpu: force pa_sc_tile_steering_override to 0 for gfx10.3
drm/amdgpu: add vram_info v2_5 in atomfirmware header
drm/amdgpu: support query vram info for sienna_cichlid
drm/amdgpu: drop gfx_v10_0_tiling_mode_table_init
drm/amdgpu: add firmware_info v3_4 structure for Sienna_Cichlid
drm/amdgpu: add atomfirmware helper funciton to query reserved fb size
drm/amdgpu: switch to query reserved fb size from vbios (v3)
Hersen Wu (1):
sound/pci/hda: add sienna_cichlid audio asic id for sienna_cichlid up
Jack Xiao (25):
drm/amdgpu: assign the doorbell index to mes ring
drm/amdgpu: add the ring type definition of MES
drm/amdgpu: avoid dereferencing a NULL pointer
drm/amdgpu/mes: update some mes definitions
drm/amdgpu/mes10.1: allocate the eop buffer
drm/amdgpu/mes10.1: initialize the software part of mes ring
drm/amdgpu/mes10.1: implement the ring functions of mes specific
drm/amdgpu/mes10.1: allocate mqd buffer
drm/amdgpu/mes10.1: initialize the mqd
drm/amdgpu/mes10.1: install mes queue by register programming
drm/amdgpu/mes10.1: install mes queue via kiq
drm/amdgpu/mes10.1: enable the mes ring during initialization
drm/amdgpu/mes10.1: add the mes fw api
drm/amdgpu/mes10.1: add the helper function for mes command submission
drm/amdgpu/mes10.1: implement adding hardware queue
drm/amdgpu/mes10.1: implement removing hardware queue
drm/amdgpu/mes10.1: implement querying the scheduler status
drm/amdgpu/mes10.1: implement setting hardware resources
drm/amdgpu/mes10.1: add sienna_cichlid mes firmware support
drm/amdgpu/mes10.1: copy mes fw info into global fw array
drm/amdgpu: upload mes firmware to gpu buffer
drm/amdgpu/psp: convert amdgpu mes ucode type
drm/amdgpu: no need to set up GPU scheduler for mes ring
drm/amdgpu/mes10.1: update mes initialization
drm/amdgpu: add mes block to sienna_cichlid
James Zhu (1):
drm/amdgpu: fix typo for vcn3/jpeg3 idle check
Jay Cornwall (3):
drm/amdkfd: Add Sienna_Cichlid trap handler support
drm/amdkfd: Support newer assemblers in gfx10 trap handler
drm/amdkfd: Support debugger in Navi1x trap handler
Jerry (Fangzhi) Zuo (2):
drm/amd/display: Add dcn30 Headers (v2)
drm/amdgpu/dc: Add missing Sienna_Cichlid chip id
Kenneth Feng (10):
drm/amd/amdgpu: fix the HDP LS/DS/SD programming
drm/amd/amdgpu: add HDP mgcg and ls support
drm/amd/amdgpu: add IH cg support
drm/amd/amdgpu: add athub ls support
drm/amd/powerplay: enable athub pg
drm/amd/powerplay: enable mmhub pg
drm/amd/powerplay: enable GPO
drm/amd/powerplay: bundle GPO with gfx DPM
drm/amd/powerplay: enable fw ctf
drm/amd/powerplay: show gfxclk=0 in gfxoff state
Le Ma (4):
drm/amdgpu/mes: update mes fw api
drm/amdgpu/mes: add status fence memory definitions
drm/amdgpu/mes: allocate memory slots for hw resource setting
drm/amdgpu: skip VM inv eng assignment for mes ring
Leo Liu (14):
drm/amdgpu: add VCN3.0 register headers (v2)
drm/amdgpu: add 2rd VCN instance doorbell support
drm/amdgpu: add VCN3.0 support for Sienna_Cichlid
drm/amdgpu: add Sienna_Cichlid VCN PG and CG support (v2)
drm/amdgpu: enable VCN3.0 PG and CG for Sienna_Cichlid
drm/amdgpu: add Sienna_Cichlid VCN to the VCN family
drm/amdgpu: enable VCN3.0 for Sienna_Cichlid
drm/amdgpu: add JPEG3.0 support for Sienna_Cichlid
drm/amdgpu: add Sienna_Cichlid JPEG PG and CG support
drm/amdgpu: enable JPEG3.0 PG and CG for Sienna_Cichlid
drm/amdgpu: enable JPEG3.0 for Sienna_Cichlid
drm/amdgpu: change the offset for VCN FW cache window
drm/amdgpu: fix the PSP front door loading VCN firmware
drm/amdgpu: set the LMI ctrl and reset earlier
Likun Gao (90):
drm/amdgpu: add GC 10.3 header files (v2)
drm/amdgpu: add sienna_cichlid asic type
drm/amdgpu: add sienna_cichlid gpu info firmware v2
drm/amdgpu: set fw load type for sienna_cichlid
drm/amdgpu: set asic family and ip blocks for sienna_cichlid
drm/amdgpu/gfx10: add support for sienna_cichlid firmware
drm/amdgpu/gmc10: add sienna_cichlid support
drm/amdgpu/gfx10: add clockgating support for sienna_cichlid
drm/amdgpu/soc15: add support for sienna_cichlid
drm/amdgpu: initialize IP offset for sienna_cichlid (v2)
drm/amdgpu/soc15: add common ip block for sienna_cichlid
drm/amdgpu: add support on mmhub for sienna_cichlid
drm/amdgpu: add support gfxhub for sienna_cichlid (v3)
drm/amdgpu: add gmc ip block for sienna_cichlid
drm/amdgpu: add ih ip block for sienna_cichlid
drm/amdgpu: add gfx ip block for sienna_cichlid (v3)
drm/amdgpu: add sdma2 and sdma3 irqsrc header files for sienna_cichlid
(v2)
drm/amdgpu: add sdma ip block for sienna_cichlid (v5)
drm/amdgpu: correct SDMA3 IH clinet id for sienna_cichlid
drm/amdgpu/gfx10: change register configure for sienna_cichlid
drm/amdgpu: add virtual display support for sienna_cichlid
drm/amdgpu/powerplay: add initial swSMU support for sienna_cichlid
(v2)
drm/amd/powerplay: add support to set performance level for
sienna_cichlid
drm/amd/powerplay: set SOCCLK DPM for sienna_cichlid
drm/amd/powerplay: set FCLK DPM for sienna_cichlid
drm/amd/powerplay: enable Ultra Low Voltage for sienna_cichlid
drm/amd/powerplay: enable Graphics Clock Deep Sleep for sienna_cichlid
drm/amd/powerplay: enable SOC Clock Deep Sleep for sienna_cichlid
drm/amdgpu/powerplay: set Thermal control for sienna_cichlid
drm/amdgpu/powerplay: set UCLK DPM for sienna_cichlid
drm/amd/powerplay: make gfx ds can be configure for sienna_cichlid
drm/amd/powerplay: Enable SOCCLK ULV for sienna_cichlid
drm/amd/powerplay: enable DCEFCLK DPM and DS for sienna_cichlid
drm/amd/powerplay: support pcie value set and update for
sienna_cichlid
drm/amd/powerplay: support to print pcie levels for sienna_cichlid
drm/amd/powerplay: enable LCLK DPM for sienna_cichlid
drm/amd/powerplay: enable GFX SS for sienna_cichlid
drm/amd/powerplay: enable Fan control for sienna_cichlid
drm/amd/powerplay: support to get power index for sienna_cichlid
drm/amd/powerplay: enable PPT and TDC for sienna_cichlid
drm/amdgpu/powerplay: add smu block for sienna_cichlid
drm/amdgpu: skip ASD fw load for sienna_cichlid
drm/amdgpu/psp: add psp support for sienna_cichlid
drm/amdgpu: skip for reroute ih for sienna_cichlid psp ring init
currently
drm/amdgpu: enable psp ip block for sienna_cichlid
drm/amdgpu: update SDMA 5.2 microcode init
drm/amdgpu: add support for athub v2.1
drm/amdgpu: add gmc cg support for sienna_cichlid
drm/amdgpu: add psp block load condition for sienna_cichlid
drm/amdgpu: update the num of queue per pipe for mec on sienna_cichlid
drm/amdgpu/mes: correct register offset for sienna_cichlid
drm/amdgpu/gfx10: add gc golden setting for sienna_cichlid
drm/amdgpu: add cp firmware backdoor loading triger
drm/amdgpu: disable gfxoff for sienna_cichlid
drm/amdgpu: only send one sdma firmware for sienna_cichlid
drm/amdgpu: open GFX clock gating for sienna_cichlid
drm/amdgpu: update golden setting for gfx10.3
drm/amdgpu: Enable Multi Media Hub (MMHUB) Clock Gating for
sienna_cichlid.
drm/amdgpu: fix SDMA hdp flush engine conflict
drm/amdgpu: enable 3D pipe 1 on Sienna_Cichlid
drm/amd/powerplay: enable VR0HOT for sienna_cichlid
drm/amd/powerplay: enable FCLK DS for sienna_cichlid
drm/amd/powerplay: enable MM DPM PG for sienna_cichlid (v2)
drm/amd/powerplay: enable BACO for sienna_cichlid
drm/amd/powerplay: enable APCC DFLL for sienna_cichlid
drm/amd/powerplay: add function to get power limit for sienna_cichlid
drm/amdgpu: update golden setting for sienna_cichlid
drm/amd/powerplay: enable RSMU SMN PG for sienna_cichlid
drm/am/powerplay: enable OUT OF BAND MONITER for sienna_cichlid
drm/amd/powerplay: enable ULCK DS for sienna_cichlid
drm/amd/powerplay: and smc dpm info struct for sienna_cichlid
drm/amd/powerplay: append pptable for sienna_cichlid (v2)
drm/amd/powerplay: enable VDDCI and MVDD for sienna_cichlid
drm/amdgpu: skip GPU scheduler setup for KIQ and MES ring
drm/amdgpu: disable runtime pm for sienna_cichlid temporarily
drm/amd/powerplay: drop jpeg instance1 dpm setup
drm/amdgpu: only use one gfx pipe for Sienna_Cichlid
drm/amd/powerplay: support mclk socclk limit value set for
sienna_cichlid.
drm/amd/amdgpu: disable gfxoff to retrieve gfxclk
drm/amdgpu: enable gfxoff for sienna_cichlid
drm/amdgpu/psp: add structure to support PSP SPL
drm/amdgpu/psp: initialization PSP SPL fw
drm/amdgpu/psp: support for loading PSP SPL fw
drm/amdgpu: update golden setting for sienna_cichlid
drm/amd/powerplay: update smu function for sienna_cichlid
drm/amd/powerplay: drop sienna_cichlid hardcode of using pptable
drm/amdgpu: reserve fb according to return value from vbios
drm/amdgpu: support memory training for sienna_cichlid
drm/amdgpu: remove unnecessary check for mem train
drm/amdgpu: bypass tmr when reserve c2p memory
Yong Zhao (3):
drm/amdgpu: Add ATHUB 2.1 header files (v2)
drm/amdgpu: Use variable instead of constant for sdma doorbell range
drm/amdkfd: Support Sienna_Cichlid KFD v4
shaoyunl (4):
drm/amdkfd: sienna_cichlid virtual function support
drm/amdgpu: Sienna_Cichlid don't enable SMU for SRIOV
drm/amdgpu/sriov : Use kiq to do tlb invalidation for gfx10 on sriov
drm/amdgpu/sriov : Add sriov detection for sienna_cichlid
drivers/gpu/drm/amd/amdgpu/Makefile | 27 +-
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 4 -
.../drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c | 834 +
drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c | 5 -
.../gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c | 79 +-
.../gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h | 3 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 11 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h | 11 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 24 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 3 +
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h | 45 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 39 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 6 +
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 3 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 113 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 39 +
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h | 9 +
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 8 +
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 25 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 1 +
drivers/gpu/drm/amd/amdgpu/athub_v2_1.c | 100 +
drivers/gpu/drm/amd/amdgpu/athub_v2_1.h | 30 +
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 513 +-
drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c | 375 +
drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.h | 37 +
drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 81 +-
drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c | 613 +
drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.h | 29 +
drivers/gpu/drm/amd/amdgpu/mes_api_def.h | 443 +
drivers/gpu/drm/amd/amdgpu/mes_v10_1.c | 664 +-
drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c | 72 +-
drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 21 +-
drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c | 14 +-
drivers/gpu/drm/amd/amdgpu/nv.c | 62 +-
drivers/gpu/drm/amd/amdgpu/nv.h | 1 +
drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 52 +-
drivers/gpu/drm/amd/amdgpu/sdma_common.h | 42 +
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 1 +
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.h | 15 -
drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 1753 +
drivers/gpu/drm/amd/amdgpu/sdma_v5_2.h | 30 +
.../drm/amd/amdgpu/sienna_cichlid_reg_init.c | 54 +
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 96 +-
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 86 +-
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 94 +-
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 1689 +
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.h | 29 +
.../gpu/drm/amd/amdkfd/cwsr_trap_handler.h | 877 +-
.../amd/amdkfd/cwsr_trap_handler_gfx10.asm | 301 +-
drivers/gpu/drm/amd/amdkfd/kfd_crat.c | 1 +
drivers/gpu/drm/amd/amdkfd/kfd_device.c | 25 +
.../drm/amd/amdkfd/kfd_device_queue_manager.c | 1 +
drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c | 1 +
.../gpu/drm/amd/amdkfd/kfd_packet_manager.c | 1 +
drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 1 +
drivers/gpu/drm/amd/display/Kconfig | 8 +
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 27 +
.../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 20 +
drivers/gpu/drm/amd/display/dc/Makefile | 4 +
.../drm/amd/display/dc/bios/bios_parser2.c | 3 +
.../display/dc/bios/command_table_helper2.c | 5 +
.../dce112/command_table_helper2_dce112.c | 40 +
.../dce112/command_table_helper2_dce112.h | 3 +
.../gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 7 +
.../gpu/drm/amd/display/dc/clk_mgr/Makefile | 10 +
.../gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c | 22 +
.../drm/amd/display/dc/clk_mgr/dcn30/dalsmc.h | 60 +
.../display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c | 543 +
.../display/dc/clk_mgr/dcn30/dcn30_clk_mgr.h | 38 +
.../dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c | 255 +
.../dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.h | 108 +
drivers/gpu/drm/amd/display/dc/core/dc.c | 88 +
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 14 +
.../gpu/drm/amd/display/dc/core/dc_resource.c | 36 +-
.../gpu/drm/amd/display/dc/core/dc_stream.c | 37 +
drivers/gpu/drm/amd/display/dc/dc.h | 59 +
drivers/gpu/drm/amd/display/dc/dc_hw_types.h | 75 +
drivers/gpu/drm/amd/display/dc/dc_stream.h | 15 +
drivers/gpu/drm/amd/display/dc/dc_types.h | 34 +
drivers/gpu/drm/amd/display/dc/dce/dce_abm.h | 20 +
.../drm/amd/display/dc/dce/dce_clock_source.c | 153 +-
.../drm/amd/display/dc/dce/dce_clock_source.h | 42 +
.../gpu/drm/amd/display/dc/dce/dce_hwseq.h | 46 +
.../gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c | 12 +
.../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 5 +
.../amd/display/dc/dcn10/dcn10_link_encoder.h | 6 +
.../gpu/drm/amd/display/dc/dcn10/dcn10_optc.c | 10 +-
.../gpu/drm/amd/display/dc/dcn10/dcn10_optc.h | 62 +
.../display/dc/dcn10/dcn10_stream_encoder.h | 42 +
.../gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h | 22 +
.../gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c | 17 -
.../gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h | 12 -
.../drm/amd/display/dc/dcn20/dcn20_hubbub.c | 9 +
.../gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c | 20 +
.../gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h | 41 +
.../drm/amd/display/dc/dcn20/dcn20_hwseq.c | 85 +
.../amd/display/dc/dcn20/dcn20_link_encoder.h | 7 +-
.../drm/amd/display/dc/dcn20/dcn20_resource.c | 39 +
drivers/gpu/drm/amd/display/dc/dcn30/Makefile | 54 +
.../gpu/drm/amd/display/dc/dcn30/dcn30_afmt.c | 206 +
.../gpu/drm/amd/display/dc/dcn30/dcn30_afmt.h | 230 +
.../amd/display/dc/dcn30/dcn30_cm_common.c | 640 +
.../amd/display/dc/dcn30/dcn30_cm_common.h | 78 +
.../gpu/drm/amd/display/dc/dcn30/dcn30_dccg.c | 100 +
.../gpu/drm/amd/display/dc/dcn30/dcn30_dccg.h | 66 +
.../display/dc/dcn30/dcn30_dio_link_encoder.c | 205 +
.../display/dc/dcn30/dcn30_dio_link_encoder.h | 76 +
.../dc/dcn30/dcn30_dio_stream_encoder.c | 851 +
.../dc/dcn30/dcn30_dio_stream_encoder.h | 269 +
.../gpu/drm/amd/display/dc/dcn30/dcn30_dpp.c | 1414 +
.../gpu/drm/amd/display/dc/dcn30/dcn30_dpp.h | 608 +
.../drm/amd/display/dc/dcn30/dcn30_dpp_cm.c | 410 +
.../gpu/drm/amd/display/dc/dcn30/dcn30_dwb.c | 264 +
.../gpu/drm/amd/display/dc/dcn30/dcn30_dwb.h | 923 +
.../drm/amd/display/dc/dcn30/dcn30_dwb_cm.c | 354 +
.../drm/amd/display/dc/dcn30/dcn30_hubbub.c | 417 +
.../drm/amd/display/dc/dcn30/dcn30_hubbub.h | 119 +
.../gpu/drm/amd/display/dc/dcn30/dcn30_hubp.c | 532 +
.../gpu/drm/amd/display/dc/dcn30/dcn30_hubp.h | 292 +
.../drm/amd/display/dc/dcn30/dcn30_hwseq.c | 714 +
.../drm/amd/display/dc/dcn30/dcn30_hwseq.h | 70 +
.../gpu/drm/amd/display/dc/dcn30/dcn30_init.c | 148 +
.../gpu/drm/amd/display/dc/dcn30/dcn30_init.h | 33 +
.../drm/amd/display/dc/dcn30/dcn30_mmhubbub.c | 239 +
.../drm/amd/display/dc/dcn30/dcn30_mmhubbub.h | 463 +
.../gpu/drm/amd/display/dc/dcn30/dcn30_mpc.c | 1409 +
.../gpu/drm/amd/display/dc/dcn30/dcn30_mpc.h | 665 +
.../gpu/drm/amd/display/dc/dcn30/dcn30_opp.h | 36 +
.../gpu/drm/amd/display/dc/dcn30/dcn30_optc.c | 365 +
.../gpu/drm/amd/display/dc/dcn30/dcn30_optc.h | 333 +
.../drm/amd/display/dc/dcn30/dcn30_resource.c | 2671 +
.../drm/amd/display/dc/dcn30/dcn30_resource.h | 82 +
.../gpu/drm/amd/display/dc/dcn30/dcn30_vpg.c | 194 +
.../gpu/drm/amd/display/dc/dcn30/dcn30_vpg.h | 133 +
drivers/gpu/drm/amd/display/dc/dm_helpers.h | 23 +
drivers/gpu/drm/amd/display/dc/dml/Makefile | 7 +
.../dc/dml/dcn30/display_mode_vba_30.c | 6860 ++
.../dc/dml/dcn30/display_mode_vba_30.h | 43 +
.../dc/dml/dcn30/display_rq_dlg_calc_30.c | 1868 +
.../dc/dml/dcn30/display_rq_dlg_calc_30.h | 69 +
.../drm/amd/display/dc/dml/display_mode_lib.c | 181 +
.../drm/amd/display/dc/dml/display_mode_lib.h | 11 +
.../amd/display/dc/dml/display_mode_structs.h | 3 +
.../drm/amd/display/dc/dml/display_mode_vba.c | 3 +
.../drm/amd/display/dc/dml/display_mode_vba.h | 3 +
drivers/gpu/drm/amd/display/dc/gpio/Makefile | 10 +
.../display/dc/gpio/dcn30/hw_factory_dcn30.c | 257 +
.../display/dc/gpio/dcn30/hw_factory_dcn30.h | 33 +
.../dc/gpio/dcn30/hw_translate_dcn30.c | 387 +
.../dc/gpio/dcn30/hw_translate_dcn30.h | 35 +
.../gpu/drm/amd/display/dc/gpio/hw_factory.c | 9 +-
.../drm/amd/display/dc/gpio/hw_translate.c | 8 +
.../gpu/drm/amd/display/dc/inc/core_types.h | 25 +
.../gpu/drm/amd/display/dc/inc/hw/clk_mgr.h | 69 +
.../amd/display/dc/inc/hw/clk_mgr_internal.h | 14 +
.../gpu/drm/amd/display/dc/inc/hw/dchubbub.h | 6 +
drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h | 7 +
drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h | 83 +
drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h | 4 +
.../gpu/drm/amd/display/dc/inc/hw/hw_shared.h | 9 +
.../gpu/drm/amd/display/dc/inc/hw/mcif_wb.h | 8 +
drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h | 108 +
.../amd/display/dc/inc/hw/stream_encoder.h | 4 +
.../amd/display/dc/inc/hw/timing_generator.h | 19 +
.../gpu/drm/amd/display/dc/inc/hw_sequencer.h | 4 +
drivers/gpu/drm/amd/display/dc/inc/resource.h | 3 +
drivers/gpu/drm/amd/display/dc/irq/Makefile | 10 +
.../display/dc/irq/dcn30/irq_service_dcn30.c | 384 +
.../display/dc/irq/dcn30/irq_service_dcn30.h | 37 +
drivers/gpu/drm/amd/display/dmub/dmub_srv.h | 3 +
drivers/gpu/drm/amd/display/dmub/src/Makefile | 3 +
.../gpu/drm/amd/display/dmub/src/dmub_dcn30.c | 184 +
.../gpu/drm/amd/display/dmub/src/dmub_dcn30.h | 50 +
.../gpu/drm/amd/display/dmub/src/dmub_srv.c | 15 +
.../gpu/drm/amd/display/include/dal_asic_id.h | 4 +
.../gpu/drm/amd/display/include/dal_types.h | 1 +
.../asic_reg/athub/athub_2_1_0_offset.h | 523 +
.../asic_reg/athub/athub_2_1_0_sh_mask.h | 2378 +
.../include/asic_reg/dcn/dcn_3_0_0_offset.h | 17880 ++++
.../include/asic_reg/dcn/dcn_3_0_0_sh_mask.h | 70929 ++++++++++++++++
.../include/asic_reg/dcn/dpcs_3_0_0_offset.h | 573 +
.../include/asic_reg/dcn/dpcs_3_0_0_sh_mask.h | 3565 +
.../include/asic_reg/gc/gc_10_3_0_default.h | 7272 ++
.../include/asic_reg/gc/gc_10_3_0_offset.h | 13469 +++
.../include/asic_reg/gc/gc_10_3_0_sh_mask.h | 47692 +++++++++++
.../include/asic_reg/vcn/vcn_3_0_0_offset.h | 1542 +
.../include/asic_reg/vcn/vcn_3_0_0_sh_mask.h | 5496 ++
drivers/gpu/drm/amd/include/atomfirmware.h | 283 +
.../include/ivsrcid/sdma2/irqsrcs_sdma2_5_0.h | 45 +
.../include/ivsrcid/sdma3/irqsrcs_sdma3_5_0.h | 45 +
.../amd/include/sienna_cichlid_ip_offset.h | 1168 +
.../gpu/drm/amd/include/soc15_ih_clientid.h | 1 +
drivers/gpu/drm/amd/powerplay/Makefile | 2 +-
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 34 +-
.../inc/smu11_driver_if_sienna_cichlid.h | 1209 +
drivers/gpu/drm/amd/powerplay/inc/smu_types.h | 4 +
drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h | 1 +
.../drm/amd/powerplay/inc/smu_v11_0_7_ppsmc.h | 139 +
.../drm/amd/powerplay/sienna_cichlid_ppt.c | 2506 +
.../drm/amd/powerplay/sienna_cichlid_ppt.h | 37 +
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 13 +
include/drm/amd_asic_type.h | 1 +
sound/pci/hda/hda_intel.c | 3 +
205 files changed, 214201 insertions(+), 792 deletions(-)
create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c
create mode 100644 drivers/gpu/drm/amd/amdgpu/athub_v2_1.c
create mode 100644 drivers/gpu/drm/amd/amdgpu/athub_v2_1.h
create mode 100644 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c
create mode 100644 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.h
create mode 100644 drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c
create mode 100644 drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.h
create mode 100644 drivers/gpu/drm/amd/amdgpu/mes_api_def.h
create mode 100644 drivers/gpu/drm/amd/amdgpu/sdma_common.h
create mode 100644 drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
create mode 100644 drivers/gpu/drm/amd/amdgpu/sdma_v5_2.h
create mode 100644 drivers/gpu/drm/amd/amdgpu/sienna_cichlid_reg_init.c
create mode 100644 drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
create mode 100644 drivers/gpu/drm/amd/amdgpu/vcn_v3_0.h
create mode 100644 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dalsmc.h
create mode 100644 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c
create mode 100644 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.h
create mode 100644 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c
create mode 100644 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.h
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn30/Makefile
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn30/dcn30_afmt.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn30/dcn30_afmt.h
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn30/dcn30_cm_common.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn30/dcn30_cm_common.h
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dccg.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dccg.h
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_link_encoder.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_link_encoder.h
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.h
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.h
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp_cm.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dwb.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dwb.h
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dwb_cm.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubbub.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubbub.h
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubp.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubp.h
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.h
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn30/dcn30_init.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn30/dcn30_init.h
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.h
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn30/dcn30_opp.h
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.h
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.h
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn30/dcn30_vpg.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn30/dcn30_vpg.h
create mode 100644 drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.h
create mode 100644 drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.h
create mode 100644 drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_factory_dcn30.c
create mode 100644 drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_factory_dcn30.h
create mode 100644 drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c
create mode 100644 drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.h
create mode 100644 drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c
create mode 100644 drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.h
create mode 100644 drivers/gpu/drm/amd/display/dmub/src/dmub_dcn30.c
create mode 100644 drivers/gpu/drm/amd/display/dmub/src/dmub_dcn30.h
create mode 100644 drivers/gpu/drm/amd/include/asic_reg/athub/athub_2_1_0_offset.h
create mode 100644 drivers/gpu/drm/amd/include/asic_reg/athub/athub_2_1_0_sh_mask.h
create mode 100755 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_0_offset.h
create mode 100755 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_0_sh_mask.h
create mode 100755 drivers/gpu/drm/amd/include/asic_reg/dcn/dpcs_3_0_0_offset.h
create mode 100755 drivers/gpu/drm/amd/include/asic_reg/dcn/dpcs_3_0_0_sh_mask.h
create mode 100644 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_default.h
create mode 100644 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h
create mode 100644 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h
create mode 100644 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_offset.h
create mode 100644 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h
create mode 100644 drivers/gpu/drm/amd/include/ivsrcid/sdma2/irqsrcs_sdma2_5_0.h
create mode 100644 drivers/gpu/drm/amd/include/ivsrcid/sdma3/irqsrcs_sdma3_5_0.h
create mode 100644 drivers/gpu/drm/amd/include/sienna_cichlid_ip_offset.h
create mode 100644 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_sienna_cichlid.h
create mode 100644 drivers/gpu/drm/amd/powerplay/inc/smu_v11_0_7_ppsmc.h
create mode 100644 drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
create mode 100644 drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.h
--
2.25.4
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 88+ messages in thread
* [PATCH 005/207] drm/amdgpu: add sienna_cichlid asic type
2020-06-01 17:59 [PATCH 000/207] Add Support for Sienna Cichlid Alex Deucher
@ 2020-06-01 17:59 ` Alex Deucher
2020-06-01 17:59 ` [PATCH 006/207] drm/amdgpu: add sienna_cichlid gpu info firmware v2 Alex Deucher
` (81 subsequent siblings)
82 siblings, 0 replies; 88+ messages in thread
From: Alex Deucher @ 2020-06-01 17:59 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Likun Gao, Hawking Zhang
From: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 1 +
include/drm/amd_asic_type.h | 1 +
2 files changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index b633171281f8..5d1e445eef21 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -112,6 +112,7 @@ const char *amdgpu_asic_name[] = {
"NAVI10",
"NAVI14",
"NAVI12",
+ "SIENNA_CICHLID",
"LAST",
};
diff --git a/include/drm/amd_asic_type.h b/include/drm/amd_asic_type.h
index b1230e33d506..0c5bd1134460 100644
--- a/include/drm/amd_asic_type.h
+++ b/include/drm/amd_asic_type.h
@@ -54,6 +54,7 @@ enum amd_asic_type {
CHIP_NAVI10, /* 25 */
CHIP_NAVI14, /* 26 */
CHIP_NAVI12, /* 27 */
+ CHIP_SIENNA_CICHLID, /* 28 */
CHIP_LAST,
};
--
2.25.4
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH 006/207] drm/amdgpu: add sienna_cichlid gpu info firmware v2
2020-06-01 17:59 [PATCH 000/207] Add Support for Sienna Cichlid Alex Deucher
2020-06-01 17:59 ` [PATCH 005/207] drm/amdgpu: add sienna_cichlid asic type Alex Deucher
@ 2020-06-01 17:59 ` Alex Deucher
2020-06-01 17:59 ` [PATCH 007/207] drm/amdgpu: set fw load type for sienna_cichlid Alex Deucher
` (80 subsequent siblings)
82 siblings, 0 replies; 88+ messages in thread
From: Alex Deucher @ 2020-06-01 17:59 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Likun Gao, Hawking Zhang
From: Likun Gao <Likun.Gao@amd.com>
gpu info fw contains chip specific parameters.
v2: fix fw_name
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 5d1e445eef21..2a284d4bcf3c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -80,6 +80,7 @@ MODULE_FIRMWARE("amdgpu/renoir_gpu_info.bin");
MODULE_FIRMWARE("amdgpu/navi10_gpu_info.bin");
MODULE_FIRMWARE("amdgpu/navi14_gpu_info.bin");
MODULE_FIRMWARE("amdgpu/navi12_gpu_info.bin");
+MODULE_FIRMWARE("amdgpu/sienna_cichlid_gpu_info.bin");
#define AMDGPU_RESUME_MS 2000
@@ -1528,7 +1529,7 @@ static void amdgpu_device_enable_virtual_display(struct amdgpu_device *adev)
static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev)
{
const char *chip_name;
- char fw_name[30];
+ char fw_name[40];
int err;
const struct gpu_info_firmware_header_v1_0 *hdr;
@@ -1595,6 +1596,9 @@ static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev)
case CHIP_NAVI12:
chip_name = "navi12";
break;
+ case CHIP_SIENNA_CICHLID:
+ chip_name = "sienna_cichlid";
+ break;
}
snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_gpu_info.bin", chip_name);
--
2.25.4
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH 007/207] drm/amdgpu: set fw load type for sienna_cichlid
2020-06-01 17:59 [PATCH 000/207] Add Support for Sienna Cichlid Alex Deucher
2020-06-01 17:59 ` [PATCH 005/207] drm/amdgpu: add sienna_cichlid asic type Alex Deucher
2020-06-01 17:59 ` [PATCH 006/207] drm/amdgpu: add sienna_cichlid gpu info firmware v2 Alex Deucher
@ 2020-06-01 17:59 ` Alex Deucher
2020-06-01 17:59 ` [PATCH 008/207] drm/amdgpu: set asic family and ip blocks " Alex Deucher
` (79 subsequent siblings)
82 siblings, 0 replies; 88+ messages in thread
From: Alex Deucher @ 2020-06-01 17:59 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Likun Gao, Hawking Zhang
From: Likun Gao <Likun.Gao@amd.com>
Same as Navi1x.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
index 65bb25e31d45..74ac14466a78 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
@@ -365,6 +365,7 @@ amdgpu_ucode_get_load_type(struct amdgpu_device *adev, int load_type)
case CHIP_NAVI10:
case CHIP_NAVI14:
case CHIP_NAVI12:
+ case CHIP_SIENNA_CICHLID:
if (!load_type)
return AMDGPU_FW_LOAD_DIRECT;
else
--
2.25.4
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH 008/207] drm/amdgpu: set asic family and ip blocks for sienna_cichlid
2020-06-01 17:59 [PATCH 000/207] Add Support for Sienna Cichlid Alex Deucher
` (2 preceding siblings ...)
2020-06-01 17:59 ` [PATCH 007/207] drm/amdgpu: set fw load type for sienna_cichlid Alex Deucher
@ 2020-06-01 17:59 ` Alex Deucher
2020-06-01 17:59 ` [PATCH 009/207] drm/amdgpu/gfx10: add support for sienna_cichlid firmware Alex Deucher
` (78 subsequent siblings)
82 siblings, 0 replies; 88+ messages in thread
From: Alex Deucher @ 2020-06-01 17:59 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Likun Gao, Hawking Zhang
From: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 2a284d4bcf3c..3b6588e15c6b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1758,6 +1758,7 @@ static int amdgpu_device_ip_early_init(struct amdgpu_device *adev)
case CHIP_NAVI10:
case CHIP_NAVI14:
case CHIP_NAVI12:
+ case CHIP_SIENNA_CICHLID:
adev->family = AMDGPU_FAMILY_NV;
r = nv_set_ip_blocks(adev);
--
2.25.4
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH 009/207] drm/amdgpu/gfx10: add support for sienna_cichlid firmware
2020-06-01 17:59 [PATCH 000/207] Add Support for Sienna Cichlid Alex Deucher
` (3 preceding siblings ...)
2020-06-01 17:59 ` [PATCH 008/207] drm/amdgpu: set asic family and ip blocks " Alex Deucher
@ 2020-06-01 17:59 ` Alex Deucher
2020-06-01 17:59 ` [PATCH 010/207] drm/amdgpu/gmc10: add sienna_cichlid support Alex Deucher
` (77 subsequent siblings)
82 siblings, 0 replies; 88+ messages in thread
From: Alex Deucher @ 2020-06-01 17:59 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Likun Gao, Hawking Zhang
From: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index df2d2f609d0b..c2fbf037defc 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -89,6 +89,13 @@ MODULE_FIRMWARE("amdgpu/navi12_mec.bin");
MODULE_FIRMWARE("amdgpu/navi12_mec2.bin");
MODULE_FIRMWARE("amdgpu/navi12_rlc.bin");
+MODULE_FIRMWARE("amdgpu/sienna_cichlid_ce.bin");
+MODULE_FIRMWARE("amdgpu/sienna_cichlid_pfp.bin");
+MODULE_FIRMWARE("amdgpu/sienna_cichlid_me.bin");
+MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec.bin");
+MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec2.bin");
+MODULE_FIRMWARE("amdgpu/sienna_cichlid_rlc.bin");
+
static const struct soc15_reg_golden golden_settings_gc_10_1[] =
{
SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014),
@@ -3463,6 +3470,9 @@ static int gfx_v10_0_init_microcode(struct amdgpu_device *adev)
case CHIP_NAVI12:
chip_name = "navi12";
break;
+ case CHIP_SIENNA_CICHLID:
+ chip_name = "sienna_cichlid";
+ break;
default:
BUG();
}
--
2.25.4
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH 010/207] drm/amdgpu/gmc10: add sienna_cichlid support
2020-06-01 17:59 [PATCH 000/207] Add Support for Sienna Cichlid Alex Deucher
` (4 preceding siblings ...)
2020-06-01 17:59 ` [PATCH 009/207] drm/amdgpu/gfx10: add support for sienna_cichlid firmware Alex Deucher
@ 2020-06-01 17:59 ` Alex Deucher
2020-06-01 17:59 ` [PATCH 011/207] drm/amdgpu/gfx10: add clockgating support for sienna_cichlid Alex Deucher
` (76 subsequent siblings)
82 siblings, 0 replies; 88+ messages in thread
From: Alex Deucher @ 2020-06-01 17:59 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Likun Gao, Hawking Zhang
From: Likun Gao <Likun.Gao@amd.com>
Same as navi10.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
index ba2b7ac0c02d..fb8030cf65cd 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
@@ -712,6 +712,7 @@ static int gmc_v10_0_mc_init(struct amdgpu_device *adev)
case CHIP_NAVI10:
case CHIP_NAVI14:
case CHIP_NAVI12:
+ case CHIP_SIENNA_CICHLID:
default:
adev->gmc.gart_size = 512ULL << 20;
break;
@@ -798,6 +799,7 @@ static int gmc_v10_0_sw_init(void *handle)
case CHIP_NAVI10:
case CHIP_NAVI14:
case CHIP_NAVI12:
+ case CHIP_SIENNA_CICHLID:
adev->num_vmhubs = 2;
/*
* To fulfill 4-level page support,
@@ -896,6 +898,7 @@ static void gmc_v10_0_init_golden_registers(struct amdgpu_device *adev)
case CHIP_NAVI10:
case CHIP_NAVI14:
case CHIP_NAVI12:
+ case CHIP_SIENNA_CICHLID:
break;
default:
break;
--
2.25.4
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH 011/207] drm/amdgpu/gfx10: add clockgating support for sienna_cichlid
2020-06-01 17:59 [PATCH 000/207] Add Support for Sienna Cichlid Alex Deucher
` (5 preceding siblings ...)
2020-06-01 17:59 ` [PATCH 010/207] drm/amdgpu/gmc10: add sienna_cichlid support Alex Deucher
@ 2020-06-01 17:59 ` Alex Deucher
2020-06-01 17:59 ` [PATCH 012/207] drm/amdgpu/soc15: add " Alex Deucher
` (75 subsequent siblings)
82 siblings, 0 replies; 88+ messages in thread
From: Alex Deucher @ 2020-06-01 17:59 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Likun Gao, Hawking Zhang
From: Likun Gao <Likun.Gao@amd.com>
Same as navi10.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index c2fbf037defc..8a6a9ba85714 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -7154,6 +7154,7 @@ static int gfx_v10_0_set_clockgating_state(void *handle,
case CHIP_NAVI10:
case CHIP_NAVI14:
case CHIP_NAVI12:
+ case CHIP_SIENNA_CICHLID:
gfx_v10_0_update_gfx_clock_gating(adev,
state == AMD_CG_STATE_GATE);
break;
--
2.25.4
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH 012/207] drm/amdgpu/soc15: add support for sienna_cichlid
2020-06-01 17:59 [PATCH 000/207] Add Support for Sienna Cichlid Alex Deucher
` (6 preceding siblings ...)
2020-06-01 17:59 ` [PATCH 011/207] drm/amdgpu/gfx10: add clockgating support for sienna_cichlid Alex Deucher
@ 2020-06-01 17:59 ` Alex Deucher
2020-06-01 17:59 ` [PATCH 013/207] drm/amdgpu: initialize IP offset for sienna_cichlid (v2) Alex Deucher
` (74 subsequent siblings)
82 siblings, 0 replies; 88+ messages in thread
From: Alex Deucher @ 2020-06-01 17:59 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Likun Gao, Hawking Zhang
From: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/nv.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index fd3b9e21a5bd..642d18e70860 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -686,6 +686,11 @@ static int nv_common_early_init(void *handle)
adev->rev_id = 0;
adev->external_rev_id = adev->rev_id + 0xa;
break;
+ case CHIP_SIENNA_CICHLID:
+ adev->cg_flags = 0;
+ adev->pg_flags = 0;
+ adev->external_rev_id = adev->rev_id + 0x28;
+ break;
default:
/* FIXME: not supported yet */
return -EINVAL;
@@ -901,6 +906,7 @@ static int nv_common_set_clockgating_state(void *handle,
case CHIP_NAVI10:
case CHIP_NAVI14:
case CHIP_NAVI12:
+ case CHIP_SIENNA_CICHLID:
adev->nbio.funcs->update_medium_grain_clock_gating(adev,
state == AMD_CG_STATE_GATE);
adev->nbio.funcs->update_medium_grain_light_sleep(adev,
--
2.25.4
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH 013/207] drm/amdgpu: initialize IP offset for sienna_cichlid (v2)
2020-06-01 17:59 [PATCH 000/207] Add Support for Sienna Cichlid Alex Deucher
` (7 preceding siblings ...)
2020-06-01 17:59 ` [PATCH 012/207] drm/amdgpu/soc15: add " Alex Deucher
@ 2020-06-01 17:59 ` Alex Deucher
2020-06-01 17:59 ` [PATCH 014/207] drm/amdgpu/soc15: add common ip block for sienna_cichlid Alex Deucher
` (73 subsequent siblings)
82 siblings, 0 replies; 88+ messages in thread
From: Alex Deucher @ 2020-06-01 17:59 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Likun Gao, Hawking Zhang
From: Likun Gao <Likun.Gao@amd.com>
Add IP offset headers and state.
V2: squash in updates (Alex)
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/Makefile | 2 +-
drivers/gpu/drm/amd/amdgpu/nv.c | 3 +
drivers/gpu/drm/amd/amdgpu/nv.h | 1 +
.../drm/amd/amdgpu/sienna_cichlid_reg_init.c | 54 +
.../amd/include/sienna_cichlid_ip_offset.h | 1168 +++++++++++++++++
5 files changed, 1227 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/amd/amdgpu/sienna_cichlid_reg_init.c
create mode 100644 drivers/gpu/drm/amd/include/sienna_cichlid_ip_offset.h
diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile
index 210d57a4afc8..0fdcb71a4feb 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -68,7 +68,7 @@ amdgpu-$(CONFIG_DRM_AMDGPU_SI)+= si.o gmc_v6_0.o gfx_v6_0.o si_ih.o si_dma.o dce
amdgpu-y += \
vi.o mxgpu_vi.o nbio_v6_1.o soc15.o emu_soc.o mxgpu_ai.o nbio_v7_0.o vega10_reg_init.o \
vega20_reg_init.o nbio_v7_4.o nbio_v2_3.o nv.o navi10_reg_init.o navi14_reg_init.o \
- arct_reg_init.o navi12_reg_init.o mxgpu_nv.o
+ arct_reg_init.o navi12_reg_init.o mxgpu_nv.o sienna_cichlid_reg_init.o
# add DF block
amdgpu-y += \
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index 642d18e70860..9466dc52df53 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -407,6 +407,9 @@ static int nv_reg_base_init(struct amdgpu_device *adev)
case CHIP_NAVI12:
navi12_reg_base_init(adev);
break;
+ case CHIP_SIENNA_CICHLID:
+ sienna_cichlid_reg_base_init(adev);
+ break;
default:
return -EINVAL;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.h b/drivers/gpu/drm/amd/amdgpu/nv.h
index 82e6cb432f3d..b6a95f0122fb 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.h
+++ b/drivers/gpu/drm/amd/amdgpu/nv.h
@@ -32,4 +32,5 @@ int nv_set_ip_blocks(struct amdgpu_device *adev);
int navi10_reg_base_init(struct amdgpu_device *adev);
int navi14_reg_base_init(struct amdgpu_device *adev);
int navi12_reg_base_init(struct amdgpu_device *adev);
+int sienna_cichlid_reg_base_init(struct amdgpu_device *adev);
#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/sienna_cichlid_reg_init.c b/drivers/gpu/drm/amd/amdgpu/sienna_cichlid_reg_init.c
new file mode 100644
index 000000000000..5ee69f70c49b
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/sienna_cichlid_reg_init.c
@@ -0,0 +1,54 @@
+/*
+ * Copyright 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+#include "amdgpu.h"
+#include "nv.h"
+
+#include "soc15_common.h"
+#include "soc15_hw_ip.h"
+#include "sienna_cichlid_ip_offset.h"
+
+int sienna_cichlid_reg_base_init(struct amdgpu_device *adev)
+{
+ /* HW has more IP blocks, only initialized the blocke needed by driver */
+ uint32_t i;
+ for (i = 0 ; i < MAX_INSTANCE ; ++i) {
+ adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
+ adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i]));
+ adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i]));
+ adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i]));
+ adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i]));
+ adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i]));
+ adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i]));
+ adev->reg_offset[VCN_HWIP][i] = (uint32_t *)(&(VCN_BASE.instance[i]));
+ adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i]));
+ adev->reg_offset[DCE_HWIP][i] = (uint32_t *)(&(DCN_BASE.instance[i]));
+ adev->reg_offset[OSSSYS_HWIP][i] = (uint32_t *)(&(OSSSYS_BASE.instance[i]));
+ adev->reg_offset[SDMA0_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
+ adev->reg_offset[SDMA1_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
+ adev->reg_offset[SDMA2_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
+ adev->reg_offset[SDMA3_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
+ adev->reg_offset[SMUIO_HWIP][i] = (uint32_t *)(&(SMUIO_BASE.instance[i]));
+ adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i]));
+ }
+ return 0;
+}
diff --git a/drivers/gpu/drm/amd/include/sienna_cichlid_ip_offset.h b/drivers/gpu/drm/amd/include/sienna_cichlid_ip_offset.h
new file mode 100644
index 000000000000..06800c6fa049
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/sienna_cichlid_ip_offset.h
@@ -0,0 +1,1168 @@
+/*
+ * Copyright (C) 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _sienna_cichlid_ip_offset_HEADER
+#define _sienna_cichlid_ip_offset_HEADER
+
+#define MAX_INSTANCE 7
+#define MAX_SEGMENT 5
+
+
+struct IP_BASE_INSTANCE
+{
+ unsigned int segment[MAX_SEGMENT];
+};
+
+struct IP_BASE
+{
+ struct IP_BASE_INSTANCE instance[MAX_INSTANCE];
+};
+
+
+static const struct IP_BASE ATHUB_BASE = { { { { 0x00000C00, 0x02408C00, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE CLK_BASE = { { { { 0x00016C00, 0x02401800, 0, 0, 0 } },
+ { { 0x00016E00, 0x02401C00, 0, 0, 0 } },
+ { { 0x00017000, 0x02402000, 0, 0, 0 } },
+ { { 0x00017200, 0x02402400, 0, 0, 0 } },
+ { { 0x0001B000, 0x0242D800, 0, 0, 0 } },
+ { { 0x0001B200, 0x0242DC00, 0, 0, 0 } },
+ { { 0x0001B400, 0x0242E000, 0, 0, 0 } } } };
+static const struct IP_BASE DF_BASE = { { { { 0x00007000, 0x0240B800, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE DIO_BASE = { { { { 0x02404000, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE DCN_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE DPCS_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE FUSE_BASE = { { { { 0x00017400, 0x02401400, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE GC_BASE = { { { { 0x00001260, 0x0000A000, 0x0001C000, 0x02402C00, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE HDA_BASE = { { { { 0x004C0000, 0x02404800, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE HDP_BASE = { { { { 0x00000F20, 0x0240A400, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE MMHUB_BASE = { { { { 0x0001A000, 0x02408800, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE MP0_BASE = { { { { 0x00016000, 0x00DC0000, 0x00E00000, 0x00E40000, 0x0243FC00 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE MP1_BASE = { { { { 0x00016000, 0x00DC0000, 0x00E00000, 0x00E40000, 0x0243FC00 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE NBIO_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0241B000 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE OSSSYS_BASE = { { { { 0x000010A0, 0x0240A000, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE PCIE0_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0241B000 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE SDMA0_BASE = { { { { 0x00001260, 0x0000A000, 0x0001C000, 0x02402C00, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE SDMA1_BASE = { { { { 0x00001260, 0x0000A000, 0x0001C000, 0x02402C00, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE SMUIO_BASE = { { { { 0x00016800, 0x00016A00, 0x00440000, 0x02401000, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE THM_BASE = { { { { 0x00016600, 0x02400C00, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE UMC_BASE = { { { { 0x00014000, 0x02425800, 0, 0, 0 } },
+ { { 0x00054000, 0x02425C00, 0, 0, 0 } },
+ { { 0x00094000, 0x02426000, 0, 0, 0 } },
+ { { 0x000D4000, 0x02426400, 0, 0, 0 } },
+ { { 0x00114000, 0x02426800, 0, 0, 0 } },
+ { { 0x00154000, 0x02426C00, 0, 0, 0 } },
+ { { 0x00194000, 0x02427000, 0, 0, 0 } } } };
+static const struct IP_BASE USB0_BASE = { { { { 0x0242A800, 0x05B00000, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE VCN_BASE = { { { { 0x00007800, 0x00007E00, 0x02403000, 0, 0 } },
+ { { 0x00007B00, 0x00012000, 0x02445000, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } };
+
+
+#define ATHUB_BASE__INST0_SEG0 0x00000C00
+#define ATHUB_BASE__INST0_SEG1 0x02408C00
+#define ATHUB_BASE__INST0_SEG2 0
+#define ATHUB_BASE__INST0_SEG3 0
+#define ATHUB_BASE__INST0_SEG4 0
+
+#define ATHUB_BASE__INST1_SEG0 0
+#define ATHUB_BASE__INST1_SEG1 0
+#define ATHUB_BASE__INST1_SEG2 0
+#define ATHUB_BASE__INST1_SEG3 0
+#define ATHUB_BASE__INST1_SEG4 0
+
+#define ATHUB_BASE__INST2_SEG0 0
+#define ATHUB_BASE__INST2_SEG1 0
+#define ATHUB_BASE__INST2_SEG2 0
+#define ATHUB_BASE__INST2_SEG3 0
+#define ATHUB_BASE__INST2_SEG4 0
+
+#define ATHUB_BASE__INST3_SEG0 0
+#define ATHUB_BASE__INST3_SEG1 0
+#define ATHUB_BASE__INST3_SEG2 0
+#define ATHUB_BASE__INST3_SEG3 0
+#define ATHUB_BASE__INST3_SEG4 0
+
+#define ATHUB_BASE__INST4_SEG0 0
+#define ATHUB_BASE__INST4_SEG1 0
+#define ATHUB_BASE__INST4_SEG2 0
+#define ATHUB_BASE__INST4_SEG3 0
+#define ATHUB_BASE__INST4_SEG4 0
+
+#define ATHUB_BASE__INST5_SEG0 0
+#define ATHUB_BASE__INST5_SEG1 0
+#define ATHUB_BASE__INST5_SEG2 0
+#define ATHUB_BASE__INST5_SEG3 0
+#define ATHUB_BASE__INST5_SEG4 0
+
+#define ATHUB_BASE__INST6_SEG0 0
+#define ATHUB_BASE__INST6_SEG1 0
+#define ATHUB_BASE__INST6_SEG2 0
+#define ATHUB_BASE__INST6_SEG3 0
+#define ATHUB_BASE__INST6_SEG4 0
+
+#define CLK_BASE__INST0_SEG0 0x00016C00
+#define CLK_BASE__INST0_SEG1 0x02401800
+#define CLK_BASE__INST0_SEG2 0
+#define CLK_BASE__INST0_SEG3 0
+#define CLK_BASE__INST0_SEG4 0
+
+#define CLK_BASE__INST1_SEG0 0x00016E00
+#define CLK_BASE__INST1_SEG1 0x02401C00
+#define CLK_BASE__INST1_SEG2 0
+#define CLK_BASE__INST1_SEG3 0
+#define CLK_BASE__INST1_SEG4 0
+
+#define CLK_BASE__INST2_SEG0 0x00017000
+#define CLK_BASE__INST2_SEG1 0x02402000
+#define CLK_BASE__INST2_SEG2 0
+#define CLK_BASE__INST2_SEG3 0
+#define CLK_BASE__INST2_SEG4 0
+
+#define CLK_BASE__INST3_SEG0 0x00017200
+#define CLK_BASE__INST3_SEG1 0x02402400
+#define CLK_BASE__INST3_SEG2 0
+#define CLK_BASE__INST3_SEG3 0
+#define CLK_BASE__INST3_SEG4 0
+
+#define CLK_BASE__INST4_SEG0 0x0001B000
+#define CLK_BASE__INST4_SEG1 0x0242D800
+#define CLK_BASE__INST4_SEG2 0
+#define CLK_BASE__INST4_SEG3 0
+#define CLK_BASE__INST4_SEG4 0
+
+#define CLK_BASE__INST5_SEG0 0x0001B200
+#define CLK_BASE__INST5_SEG1 0x0242DC00
+#define CLK_BASE__INST5_SEG2 0
+#define CLK_BASE__INST5_SEG3 0
+#define CLK_BASE__INST5_SEG4 0
+
+#define CLK_BASE__INST6_SEG0 0x0001B400
+#define CLK_BASE__INST6_SEG1 0x0242E000
+#define CLK_BASE__INST6_SEG2 0
+#define CLK_BASE__INST6_SEG3 0
+#define CLK_BASE__INST6_SEG4 0
+
+#define DF_BASE__INST0_SEG0 0x00007000
+#define DF_BASE__INST0_SEG1 0x0240B800
+#define DF_BASE__INST0_SEG2 0
+#define DF_BASE__INST0_SEG3 0
+#define DF_BASE__INST0_SEG4 0
+
+#define DF_BASE__INST1_SEG0 0
+#define DF_BASE__INST1_SEG1 0
+#define DF_BASE__INST1_SEG2 0
+#define DF_BASE__INST1_SEG3 0
+#define DF_BASE__INST1_SEG4 0
+
+#define DF_BASE__INST2_SEG0 0
+#define DF_BASE__INST2_SEG1 0
+#define DF_BASE__INST2_SEG2 0
+#define DF_BASE__INST2_SEG3 0
+#define DF_BASE__INST2_SEG4 0
+
+#define DF_BASE__INST3_SEG0 0
+#define DF_BASE__INST3_SEG1 0
+#define DF_BASE__INST3_SEG2 0
+#define DF_BASE__INST3_SEG3 0
+#define DF_BASE__INST3_SEG4 0
+
+#define DF_BASE__INST4_SEG0 0
+#define DF_BASE__INST4_SEG1 0
+#define DF_BASE__INST4_SEG2 0
+#define DF_BASE__INST4_SEG3 0
+#define DF_BASE__INST4_SEG4 0
+
+#define DF_BASE__INST5_SEG0 0
+#define DF_BASE__INST5_SEG1 0
+#define DF_BASE__INST5_SEG2 0
+#define DF_BASE__INST5_SEG3 0
+#define DF_BASE__INST5_SEG4 0
+
+#define DF_BASE__INST6_SEG0 0
+#define DF_BASE__INST6_SEG1 0
+#define DF_BASE__INST6_SEG2 0
+#define DF_BASE__INST6_SEG3 0
+#define DF_BASE__INST6_SEG4 0
+
+#define DIO_BASE__INST0_SEG0 0x02404000
+#define DIO_BASE__INST0_SEG1 0
+#define DIO_BASE__INST0_SEG2 0
+#define DIO_BASE__INST0_SEG3 0
+#define DIO_BASE__INST0_SEG4 0
+
+#define DIO_BASE__INST1_SEG0 0
+#define DIO_BASE__INST1_SEG1 0
+#define DIO_BASE__INST1_SEG2 0
+#define DIO_BASE__INST1_SEG3 0
+#define DIO_BASE__INST1_SEG4 0
+
+#define DIO_BASE__INST2_SEG0 0
+#define DIO_BASE__INST2_SEG1 0
+#define DIO_BASE__INST2_SEG2 0
+#define DIO_BASE__INST2_SEG3 0
+#define DIO_BASE__INST2_SEG4 0
+
+#define DIO_BASE__INST3_SEG0 0
+#define DIO_BASE__INST3_SEG1 0
+#define DIO_BASE__INST3_SEG2 0
+#define DIO_BASE__INST3_SEG3 0
+#define DIO_BASE__INST3_SEG4 0
+
+#define DIO_BASE__INST4_SEG0 0
+#define DIO_BASE__INST4_SEG1 0
+#define DIO_BASE__INST4_SEG2 0
+#define DIO_BASE__INST4_SEG3 0
+#define DIO_BASE__INST4_SEG4 0
+
+#define DIO_BASE__INST5_SEG0 0
+#define DIO_BASE__INST5_SEG1 0
+#define DIO_BASE__INST5_SEG2 0
+#define DIO_BASE__INST5_SEG3 0
+#define DIO_BASE__INST5_SEG4 0
+
+#define DIO_BASE__INST6_SEG0 0
+#define DIO_BASE__INST6_SEG1 0
+#define DIO_BASE__INST6_SEG2 0
+#define DIO_BASE__INST6_SEG3 0
+#define DIO_BASE__INST6_SEG4 0
+
+#define DCN_BASE__INST0_SEG0 0x00000012
+#define DCN_BASE__INST0_SEG1 0x000000C0
+#define DCN_BASE__INST0_SEG2 0x000034C0
+#define DCN_BASE__INST0_SEG3 0x00009000
+#define DCN_BASE__INST0_SEG4 0x02403C00
+
+#define DCN_BASE__INST1_SEG0 0
+#define DCN_BASE__INST1_SEG1 0
+#define DCN_BASE__INST1_SEG2 0
+#define DCN_BASE__INST1_SEG3 0
+#define DCN_BASE__INST1_SEG4 0
+
+#define DCN_BASE__INST2_SEG0 0
+#define DCN_BASE__INST2_SEG1 0
+#define DCN_BASE__INST2_SEG2 0
+#define DCN_BASE__INST2_SEG3 0
+#define DCN_BASE__INST2_SEG4 0
+
+#define DCN_BASE__INST3_SEG0 0
+#define DCN_BASE__INST3_SEG1 0
+#define DCN_BASE__INST3_SEG2 0
+#define DCN_BASE__INST3_SEG3 0
+#define DCN_BASE__INST3_SEG4 0
+
+#define DCN_BASE__INST4_SEG0 0
+#define DCN_BASE__INST4_SEG1 0
+#define DCN_BASE__INST4_SEG2 0
+#define DCN_BASE__INST4_SEG3 0
+#define DCN_BASE__INST4_SEG4 0
+
+#define DCN_BASE__INST5_SEG0 0
+#define DCN_BASE__INST5_SEG1 0
+#define DCN_BASE__INST5_SEG2 0
+#define DCN_BASE__INST5_SEG3 0
+#define DCN_BASE__INST5_SEG4 0
+
+#define DCN_BASE__INST6_SEG0 0
+#define DCN_BASE__INST6_SEG1 0
+#define DCN_BASE__INST6_SEG2 0
+#define DCN_BASE__INST6_SEG3 0
+#define DCN_BASE__INST6_SEG4 0
+
+#define DPCS_BASE__INST0_SEG0 0x00000012
+#define DPCS_BASE__INST0_SEG1 0x000000C0
+#define DPCS_BASE__INST0_SEG2 0x000034C0
+#define DPCS_BASE__INST0_SEG3 0x00009000
+#define DPCS_BASE__INST0_SEG4 0x02403C00
+
+#define DPCS_BASE__INST1_SEG0 0
+#define DPCS_BASE__INST1_SEG1 0
+#define DPCS_BASE__INST1_SEG2 0
+#define DPCS_BASE__INST1_SEG3 0
+#define DPCS_BASE__INST1_SEG4 0
+
+#define DPCS_BASE__INST2_SEG0 0
+#define DPCS_BASE__INST2_SEG1 0
+#define DPCS_BASE__INST2_SEG2 0
+#define DPCS_BASE__INST2_SEG3 0
+#define DPCS_BASE__INST2_SEG4 0
+
+#define DPCS_BASE__INST3_SEG0 0
+#define DPCS_BASE__INST3_SEG1 0
+#define DPCS_BASE__INST3_SEG2 0
+#define DPCS_BASE__INST3_SEG3 0
+#define DPCS_BASE__INST3_SEG4 0
+
+#define DPCS_BASE__INST4_SEG0 0
+#define DPCS_BASE__INST4_SEG1 0
+#define DPCS_BASE__INST4_SEG2 0
+#define DPCS_BASE__INST4_SEG3 0
+#define DPCS_BASE__INST4_SEG4 0
+
+#define DPCS_BASE__INST5_SEG0 0
+#define DPCS_BASE__INST5_SEG1 0
+#define DPCS_BASE__INST5_SEG2 0
+#define DPCS_BASE__INST5_SEG3 0
+#define DPCS_BASE__INST5_SEG4 0
+
+#define DPCS_BASE__INST6_SEG0 0
+#define DPCS_BASE__INST6_SEG1 0
+#define DPCS_BASE__INST6_SEG2 0
+#define DPCS_BASE__INST6_SEG3 0
+#define DPCS_BASE__INST6_SEG4 0
+
+#define FUSE_BASE__INST0_SEG0 0x00017400
+#define FUSE_BASE__INST0_SEG1 0x02401400
+#define FUSE_BASE__INST0_SEG2 0
+#define FUSE_BASE__INST0_SEG3 0
+#define FUSE_BASE__INST0_SEG4 0
+
+#define FUSE_BASE__INST1_SEG0 0
+#define FUSE_BASE__INST1_SEG1 0
+#define FUSE_BASE__INST1_SEG2 0
+#define FUSE_BASE__INST1_SEG3 0
+#define FUSE_BASE__INST1_SEG4 0
+
+#define FUSE_BASE__INST2_SEG0 0
+#define FUSE_BASE__INST2_SEG1 0
+#define FUSE_BASE__INST2_SEG2 0
+#define FUSE_BASE__INST2_SEG3 0
+#define FUSE_BASE__INST2_SEG4 0
+
+#define FUSE_BASE__INST3_SEG0 0
+#define FUSE_BASE__INST3_SEG1 0
+#define FUSE_BASE__INST3_SEG2 0
+#define FUSE_BASE__INST3_SEG3 0
+#define FUSE_BASE__INST3_SEG4 0
+
+#define FUSE_BASE__INST4_SEG0 0
+#define FUSE_BASE__INST4_SEG1 0
+#define FUSE_BASE__INST4_SEG2 0
+#define FUSE_BASE__INST4_SEG3 0
+#define FUSE_BASE__INST4_SEG4 0
+
+#define FUSE_BASE__INST5_SEG0 0
+#define FUSE_BASE__INST5_SEG1 0
+#define FUSE_BASE__INST5_SEG2 0
+#define FUSE_BASE__INST5_SEG3 0
+#define FUSE_BASE__INST5_SEG4 0
+
+#define FUSE_BASE__INST6_SEG0 0
+#define FUSE_BASE__INST6_SEG1 0
+#define FUSE_BASE__INST6_SEG2 0
+#define FUSE_BASE__INST6_SEG3 0
+#define FUSE_BASE__INST6_SEG4 0
+
+#define GC_BASE__INST0_SEG0 0x00001260
+#define GC_BASE__INST0_SEG1 0x0000A000
+#define GC_BASE__INST0_SEG2 0x0001C000
+#define GC_BASE__INST0_SEG3 0x02402C00
+#define GC_BASE__INST0_SEG4 0
+
+#define GC_BASE__INST1_SEG0 0
+#define GC_BASE__INST1_SEG1 0
+#define GC_BASE__INST1_SEG2 0
+#define GC_BASE__INST1_SEG3 0
+#define GC_BASE__INST1_SEG4 0
+
+#define GC_BASE__INST2_SEG0 0
+#define GC_BASE__INST2_SEG1 0
+#define GC_BASE__INST2_SEG2 0
+#define GC_BASE__INST2_SEG3 0
+#define GC_BASE__INST2_SEG4 0
+
+#define GC_BASE__INST3_SEG0 0
+#define GC_BASE__INST3_SEG1 0
+#define GC_BASE__INST3_SEG2 0
+#define GC_BASE__INST3_SEG3 0
+#define GC_BASE__INST3_SEG4 0
+
+#define GC_BASE__INST4_SEG0 0
+#define GC_BASE__INST4_SEG1 0
+#define GC_BASE__INST4_SEG2 0
+#define GC_BASE__INST4_SEG3 0
+#define GC_BASE__INST4_SEG4 0
+
+#define GC_BASE__INST5_SEG0 0
+#define GC_BASE__INST5_SEG1 0
+#define GC_BASE__INST5_SEG2 0
+#define GC_BASE__INST5_SEG3 0
+#define GC_BASE__INST5_SEG4 0
+
+#define GC_BASE__INST6_SEG0 0
+#define GC_BASE__INST6_SEG1 0
+#define GC_BASE__INST6_SEG2 0
+#define GC_BASE__INST6_SEG3 0
+#define GC_BASE__INST6_SEG4 0
+
+#define HDA_BASE__INST0_SEG0 0x004C0000
+#define HDA_BASE__INST0_SEG1 0x02404800
+#define HDA_BASE__INST0_SEG2 0
+#define HDA_BASE__INST0_SEG3 0
+#define HDA_BASE__INST0_SEG4 0
+
+#define HDA_BASE__INST1_SEG0 0
+#define HDA_BASE__INST1_SEG1 0
+#define HDA_BASE__INST1_SEG2 0
+#define HDA_BASE__INST1_SEG3 0
+#define HDA_BASE__INST1_SEG4 0
+
+#define HDA_BASE__INST2_SEG0 0
+#define HDA_BASE__INST2_SEG1 0
+#define HDA_BASE__INST2_SEG2 0
+#define HDA_BASE__INST2_SEG3 0
+#define HDA_BASE__INST2_SEG4 0
+
+#define HDA_BASE__INST3_SEG0 0
+#define HDA_BASE__INST3_SEG1 0
+#define HDA_BASE__INST3_SEG2 0
+#define HDA_BASE__INST3_SEG3 0
+#define HDA_BASE__INST3_SEG4 0
+
+#define HDA_BASE__INST4_SEG0 0
+#define HDA_BASE__INST4_SEG1 0
+#define HDA_BASE__INST4_SEG2 0
+#define HDA_BASE__INST4_SEG3 0
+#define HDA_BASE__INST4_SEG4 0
+
+#define HDA_BASE__INST5_SEG0 0
+#define HDA_BASE__INST5_SEG1 0
+#define HDA_BASE__INST5_SEG2 0
+#define HDA_BASE__INST5_SEG3 0
+#define HDA_BASE__INST5_SEG4 0
+
+#define HDA_BASE__INST6_SEG0 0
+#define HDA_BASE__INST6_SEG1 0
+#define HDA_BASE__INST6_SEG2 0
+#define HDA_BASE__INST6_SEG3 0
+#define HDA_BASE__INST6_SEG4 0
+
+#define HDP_BASE__INST0_SEG0 0x00000F20
+#define HDP_BASE__INST0_SEG1 0x0240A400
+#define HDP_BASE__INST0_SEG2 0
+#define HDP_BASE__INST0_SEG3 0
+#define HDP_BASE__INST0_SEG4 0
+
+#define HDP_BASE__INST1_SEG0 0
+#define HDP_BASE__INST1_SEG1 0
+#define HDP_BASE__INST1_SEG2 0
+#define HDP_BASE__INST1_SEG3 0
+#define HDP_BASE__INST1_SEG4 0
+
+#define HDP_BASE__INST2_SEG0 0
+#define HDP_BASE__INST2_SEG1 0
+#define HDP_BASE__INST2_SEG2 0
+#define HDP_BASE__INST2_SEG3 0
+#define HDP_BASE__INST2_SEG4 0
+
+#define HDP_BASE__INST3_SEG0 0
+#define HDP_BASE__INST3_SEG1 0
+#define HDP_BASE__INST3_SEG2 0
+#define HDP_BASE__INST3_SEG3 0
+#define HDP_BASE__INST3_SEG4 0
+
+#define HDP_BASE__INST4_SEG0 0
+#define HDP_BASE__INST4_SEG1 0
+#define HDP_BASE__INST4_SEG2 0
+#define HDP_BASE__INST4_SEG3 0
+#define HDP_BASE__INST4_SEG4 0
+
+#define HDP_BASE__INST5_SEG0 0
+#define HDP_BASE__INST5_SEG1 0
+#define HDP_BASE__INST5_SEG2 0
+#define HDP_BASE__INST5_SEG3 0
+#define HDP_BASE__INST5_SEG4 0
+
+#define HDP_BASE__INST6_SEG0 0
+#define HDP_BASE__INST6_SEG1 0
+#define HDP_BASE__INST6_SEG2 0
+#define HDP_BASE__INST6_SEG3 0
+#define HDP_BASE__INST6_SEG4 0
+
+#define MMHUB_BASE__INST0_SEG0 0x0001A000
+#define MMHUB_BASE__INST0_SEG1 0x02408800
+#define MMHUB_BASE__INST0_SEG2 0
+#define MMHUB_BASE__INST0_SEG3 0
+#define MMHUB_BASE__INST0_SEG4 0
+
+#define MMHUB_BASE__INST1_SEG0 0
+#define MMHUB_BASE__INST1_SEG1 0
+#define MMHUB_BASE__INST1_SEG2 0
+#define MMHUB_BASE__INST1_SEG3 0
+#define MMHUB_BASE__INST1_SEG4 0
+
+#define MMHUB_BASE__INST2_SEG0 0
+#define MMHUB_BASE__INST2_SEG1 0
+#define MMHUB_BASE__INST2_SEG2 0
+#define MMHUB_BASE__INST2_SEG3 0
+#define MMHUB_BASE__INST2_SEG4 0
+
+#define MMHUB_BASE__INST3_SEG0 0
+#define MMHUB_BASE__INST3_SEG1 0
+#define MMHUB_BASE__INST3_SEG2 0
+#define MMHUB_BASE__INST3_SEG3 0
+#define MMHUB_BASE__INST3_SEG4 0
+
+#define MMHUB_BASE__INST4_SEG0 0
+#define MMHUB_BASE__INST4_SEG1 0
+#define MMHUB_BASE__INST4_SEG2 0
+#define MMHUB_BASE__INST4_SEG3 0
+#define MMHUB_BASE__INST4_SEG4 0
+
+#define MMHUB_BASE__INST5_SEG0 0
+#define MMHUB_BASE__INST5_SEG1 0
+#define MMHUB_BASE__INST5_SEG2 0
+#define MMHUB_BASE__INST5_SEG3 0
+#define MMHUB_BASE__INST5_SEG4 0
+
+#define MMHUB_BASE__INST6_SEG0 0
+#define MMHUB_BASE__INST6_SEG1 0
+#define MMHUB_BASE__INST6_SEG2 0
+#define MMHUB_BASE__INST6_SEG3 0
+#define MMHUB_BASE__INST6_SEG4 0
+
+#define MP0_BASE__INST0_SEG0 0x00016000
+#define MP0_BASE__INST0_SEG1 0x00DC0000
+#define MP0_BASE__INST0_SEG2 0x00E00000
+#define MP0_BASE__INST0_SEG3 0x00E40000
+#define MP0_BASE__INST0_SEG4 0x0243FC00
+
+#define MP0_BASE__INST1_SEG0 0
+#define MP0_BASE__INST1_SEG1 0
+#define MP0_BASE__INST1_SEG2 0
+#define MP0_BASE__INST1_SEG3 0
+#define MP0_BASE__INST1_SEG4 0
+
+#define MP0_BASE__INST2_SEG0 0
+#define MP0_BASE__INST2_SEG1 0
+#define MP0_BASE__INST2_SEG2 0
+#define MP0_BASE__INST2_SEG3 0
+#define MP0_BASE__INST2_SEG4 0
+
+#define MP0_BASE__INST3_SEG0 0
+#define MP0_BASE__INST3_SEG1 0
+#define MP0_BASE__INST3_SEG2 0
+#define MP0_BASE__INST3_SEG3 0
+#define MP0_BASE__INST3_SEG4 0
+
+#define MP0_BASE__INST4_SEG0 0
+#define MP0_BASE__INST4_SEG1 0
+#define MP0_BASE__INST4_SEG2 0
+#define MP0_BASE__INST4_SEG3 0
+#define MP0_BASE__INST4_SEG4 0
+
+#define MP0_BASE__INST5_SEG0 0
+#define MP0_BASE__INST5_SEG1 0
+#define MP0_BASE__INST5_SEG2 0
+#define MP0_BASE__INST5_SEG3 0
+#define MP0_BASE__INST5_SEG4 0
+
+#define MP0_BASE__INST6_SEG0 0
+#define MP0_BASE__INST6_SEG1 0
+#define MP0_BASE__INST6_SEG2 0
+#define MP0_BASE__INST6_SEG3 0
+#define MP0_BASE__INST6_SEG4 0
+
+#define MP1_BASE__INST0_SEG0 0x00016000
+#define MP1_BASE__INST0_SEG1 0x00DC0000
+#define MP1_BASE__INST0_SEG2 0x00E00000
+#define MP1_BASE__INST0_SEG3 0x00E40000
+#define MP1_BASE__INST0_SEG4 0x0243FC00
+
+#define MP1_BASE__INST1_SEG0 0
+#define MP1_BASE__INST1_SEG1 0
+#define MP1_BASE__INST1_SEG2 0
+#define MP1_BASE__INST1_SEG3 0
+#define MP1_BASE__INST1_SEG4 0
+
+#define MP1_BASE__INST2_SEG0 0
+#define MP1_BASE__INST2_SEG1 0
+#define MP1_BASE__INST2_SEG2 0
+#define MP1_BASE__INST2_SEG3 0
+#define MP1_BASE__INST2_SEG4 0
+
+#define MP1_BASE__INST3_SEG0 0
+#define MP1_BASE__INST3_SEG1 0
+#define MP1_BASE__INST3_SEG2 0
+#define MP1_BASE__INST3_SEG3 0
+#define MP1_BASE__INST3_SEG4 0
+
+#define MP1_BASE__INST4_SEG0 0
+#define MP1_BASE__INST4_SEG1 0
+#define MP1_BASE__INST4_SEG2 0
+#define MP1_BASE__INST4_SEG3 0
+#define MP1_BASE__INST4_SEG4 0
+
+#define MP1_BASE__INST5_SEG0 0
+#define MP1_BASE__INST5_SEG1 0
+#define MP1_BASE__INST5_SEG2 0
+#define MP1_BASE__INST5_SEG3 0
+#define MP1_BASE__INST5_SEG4 0
+
+#define MP1_BASE__INST6_SEG0 0
+#define MP1_BASE__INST6_SEG1 0
+#define MP1_BASE__INST6_SEG2 0
+#define MP1_BASE__INST6_SEG3 0
+#define MP1_BASE__INST6_SEG4 0
+
+#define NBIO_BASE__INST0_SEG0 0x00000000
+#define NBIO_BASE__INST0_SEG1 0x00000014
+#define NBIO_BASE__INST0_SEG2 0x00000D20
+#define NBIO_BASE__INST0_SEG3 0x00010400
+#define NBIO_BASE__INST0_SEG4 0x0241B000
+
+#define NBIO_BASE__INST1_SEG0 0
+#define NBIO_BASE__INST1_SEG1 0
+#define NBIO_BASE__INST1_SEG2 0
+#define NBIO_BASE__INST1_SEG3 0
+#define NBIO_BASE__INST1_SEG4 0
+
+#define NBIO_BASE__INST2_SEG0 0
+#define NBIO_BASE__INST2_SEG1 0
+#define NBIO_BASE__INST2_SEG2 0
+#define NBIO_BASE__INST2_SEG3 0
+#define NBIO_BASE__INST2_SEG4 0
+
+#define NBIO_BASE__INST3_SEG0 0
+#define NBIO_BASE__INST3_SEG1 0
+#define NBIO_BASE__INST3_SEG2 0
+#define NBIO_BASE__INST3_SEG3 0
+#define NBIO_BASE__INST3_SEG4 0
+
+#define NBIO_BASE__INST4_SEG0 0
+#define NBIO_BASE__INST4_SEG1 0
+#define NBIO_BASE__INST4_SEG2 0
+#define NBIO_BASE__INST4_SEG3 0
+#define NBIO_BASE__INST4_SEG4 0
+
+#define NBIO_BASE__INST5_SEG0 0
+#define NBIO_BASE__INST5_SEG1 0
+#define NBIO_BASE__INST5_SEG2 0
+#define NBIO_BASE__INST5_SEG3 0
+#define NBIO_BASE__INST5_SEG4 0
+
+#define NBIO_BASE__INST6_SEG0 0
+#define NBIO_BASE__INST6_SEG1 0
+#define NBIO_BASE__INST6_SEG2 0
+#define NBIO_BASE__INST6_SEG3 0
+#define NBIO_BASE__INST6_SEG4 0
+
+#define OSSSYS_BASE__INST0_SEG0 0x000010A0
+#define OSSSYS_BASE__INST0_SEG1 0x0240A000
+#define OSSSYS_BASE__INST0_SEG2 0
+#define OSSSYS_BASE__INST0_SEG3 0
+#define OSSSYS_BASE__INST0_SEG4 0
+
+#define OSSSYS_BASE__INST1_SEG0 0
+#define OSSSYS_BASE__INST1_SEG1 0
+#define OSSSYS_BASE__INST1_SEG2 0
+#define OSSSYS_BASE__INST1_SEG3 0
+#define OSSSYS_BASE__INST1_SEG4 0
+
+#define OSSSYS_BASE__INST2_SEG0 0
+#define OSSSYS_BASE__INST2_SEG1 0
+#define OSSSYS_BASE__INST2_SEG2 0
+#define OSSSYS_BASE__INST2_SEG3 0
+#define OSSSYS_BASE__INST2_SEG4 0
+
+#define OSSSYS_BASE__INST3_SEG0 0
+#define OSSSYS_BASE__INST3_SEG1 0
+#define OSSSYS_BASE__INST3_SEG2 0
+#define OSSSYS_BASE__INST3_SEG3 0
+#define OSSSYS_BASE__INST3_SEG4 0
+
+#define OSSSYS_BASE__INST4_SEG0 0
+#define OSSSYS_BASE__INST4_SEG1 0
+#define OSSSYS_BASE__INST4_SEG2 0
+#define OSSSYS_BASE__INST4_SEG3 0
+#define OSSSYS_BASE__INST4_SEG4 0
+
+#define OSSSYS_BASE__INST5_SEG0 0
+#define OSSSYS_BASE__INST5_SEG1 0
+#define OSSSYS_BASE__INST5_SEG2 0
+#define OSSSYS_BASE__INST5_SEG3 0
+#define OSSSYS_BASE__INST5_SEG4 0
+
+#define OSSSYS_BASE__INST6_SEG0 0
+#define OSSSYS_BASE__INST6_SEG1 0
+#define OSSSYS_BASE__INST6_SEG2 0
+#define OSSSYS_BASE__INST6_SEG3 0
+#define OSSSYS_BASE__INST6_SEG4 0
+
+#define PCIE0_BASE__INST0_SEG0 0x00000000
+#define PCIE0_BASE__INST0_SEG1 0x00000014
+#define PCIE0_BASE__INST0_SEG2 0x00000D20
+#define PCIE0_BASE__INST0_SEG3 0x00010400
+#define PCIE0_BASE__INST0_SEG4 0x0241B000
+
+#define PCIE0_BASE__INST1_SEG0 0
+#define PCIE0_BASE__INST1_SEG1 0
+#define PCIE0_BASE__INST1_SEG2 0
+#define PCIE0_BASE__INST1_SEG3 0
+#define PCIE0_BASE__INST1_SEG4 0
+
+#define PCIE0_BASE__INST2_SEG0 0
+#define PCIE0_BASE__INST2_SEG1 0
+#define PCIE0_BASE__INST2_SEG2 0
+#define PCIE0_BASE__INST2_SEG3 0
+#define PCIE0_BASE__INST2_SEG4 0
+
+#define PCIE0_BASE__INST3_SEG0 0
+#define PCIE0_BASE__INST3_SEG1 0
+#define PCIE0_BASE__INST3_SEG2 0
+#define PCIE0_BASE__INST3_SEG3 0
+#define PCIE0_BASE__INST3_SEG4 0
+
+#define PCIE0_BASE__INST4_SEG0 0
+#define PCIE0_BASE__INST4_SEG1 0
+#define PCIE0_BASE__INST4_SEG2 0
+#define PCIE0_BASE__INST4_SEG3 0
+#define PCIE0_BASE__INST4_SEG4 0
+
+#define PCIE0_BASE__INST5_SEG0 0
+#define PCIE0_BASE__INST5_SEG1 0
+#define PCIE0_BASE__INST5_SEG2 0
+#define PCIE0_BASE__INST5_SEG3 0
+#define PCIE0_BASE__INST5_SEG4 0
+
+#define PCIE0_BASE__INST6_SEG0 0
+#define PCIE0_BASE__INST6_SEG1 0
+#define PCIE0_BASE__INST6_SEG2 0
+#define PCIE0_BASE__INST6_SEG3 0
+#define PCIE0_BASE__INST6_SEG4 0
+
+#define SDMA0_BASE__INST0_SEG0 0x00001260
+#define SDMA0_BASE__INST0_SEG1 0x0000A000
+#define SDMA0_BASE__INST0_SEG2 0x0001C000
+#define SDMA0_BASE__INST0_SEG3 0x02402C00
+#define SDMA0_BASE__INST0_SEG4 0
+
+#define SDMA0_BASE__INST1_SEG0 0
+#define SDMA0_BASE__INST1_SEG1 0
+#define SDMA0_BASE__INST1_SEG2 0
+#define SDMA0_BASE__INST1_SEG3 0
+#define SDMA0_BASE__INST1_SEG4 0
+
+#define SDMA0_BASE__INST2_SEG0 0
+#define SDMA0_BASE__INST2_SEG1 0
+#define SDMA0_BASE__INST2_SEG2 0
+#define SDMA0_BASE__INST2_SEG3 0
+#define SDMA0_BASE__INST2_SEG4 0
+
+#define SDMA0_BASE__INST3_SEG0 0
+#define SDMA0_BASE__INST3_SEG1 0
+#define SDMA0_BASE__INST3_SEG2 0
+#define SDMA0_BASE__INST3_SEG3 0
+#define SDMA0_BASE__INST3_SEG4 0
+
+#define SDMA0_BASE__INST4_SEG0 0
+#define SDMA0_BASE__INST4_SEG1 0
+#define SDMA0_BASE__INST4_SEG2 0
+#define SDMA0_BASE__INST4_SEG3 0
+#define SDMA0_BASE__INST4_SEG4 0
+
+#define SDMA0_BASE__INST5_SEG0 0
+#define SDMA0_BASE__INST5_SEG1 0
+#define SDMA0_BASE__INST5_SEG2 0
+#define SDMA0_BASE__INST5_SEG3 0
+#define SDMA0_BASE__INST5_SEG4 0
+
+#define SDMA0_BASE__INST6_SEG0 0
+#define SDMA0_BASE__INST6_SEG1 0
+#define SDMA0_BASE__INST6_SEG2 0
+#define SDMA0_BASE__INST6_SEG3 0
+#define SDMA0_BASE__INST6_SEG4 0
+
+#define SDMA1_BASE__INST0_SEG0 0x00001260
+#define SDMA1_BASE__INST0_SEG1 0x0000A000
+#define SDMA1_BASE__INST0_SEG2 0x0001C000
+#define SDMA1_BASE__INST0_SEG3 0x02402C00
+#define SDMA1_BASE__INST0_SEG4 0
+
+#define SDMA1_BASE__INST1_SEG0 0
+#define SDMA1_BASE__INST1_SEG1 0
+#define SDMA1_BASE__INST1_SEG2 0
+#define SDMA1_BASE__INST1_SEG3 0
+#define SDMA1_BASE__INST1_SEG4 0
+
+#define SDMA1_BASE__INST2_SEG0 0
+#define SDMA1_BASE__INST2_SEG1 0
+#define SDMA1_BASE__INST2_SEG2 0
+#define SDMA1_BASE__INST2_SEG3 0
+#define SDMA1_BASE__INST2_SEG4 0
+
+#define SDMA1_BASE__INST3_SEG0 0
+#define SDMA1_BASE__INST3_SEG1 0
+#define SDMA1_BASE__INST3_SEG2 0
+#define SDMA1_BASE__INST3_SEG3 0
+#define SDMA1_BASE__INST3_SEG4 0
+
+#define SDMA1_BASE__INST4_SEG0 0
+#define SDMA1_BASE__INST4_SEG1 0
+#define SDMA1_BASE__INST4_SEG2 0
+#define SDMA1_BASE__INST4_SEG3 0
+#define SDMA1_BASE__INST4_SEG4 0
+
+#define SDMA1_BASE__INST5_SEG0 0
+#define SDMA1_BASE__INST5_SEG1 0
+#define SDMA1_BASE__INST5_SEG2 0
+#define SDMA1_BASE__INST5_SEG3 0
+#define SDMA1_BASE__INST5_SEG4 0
+
+#define SDMA1_BASE__INST6_SEG0 0
+#define SDMA1_BASE__INST6_SEG1 0
+#define SDMA1_BASE__INST6_SEG2 0
+#define SDMA1_BASE__INST6_SEG3 0
+#define SDMA1_BASE__INST6_SEG4 0
+
+#define SMUIO_BASE__INST0_SEG0 0x00016800
+#define SMUIO_BASE__INST0_SEG1 0x00016A00
+#define SMUIO_BASE__INST0_SEG2 0x00440000
+#define SMUIO_BASE__INST0_SEG3 0x02401000
+#define SMUIO_BASE__INST0_SEG4 0
+
+#define SMUIO_BASE__INST1_SEG0 0
+#define SMUIO_BASE__INST1_SEG1 0
+#define SMUIO_BASE__INST1_SEG2 0
+#define SMUIO_BASE__INST1_SEG3 0
+#define SMUIO_BASE__INST1_SEG4 0
+
+#define SMUIO_BASE__INST2_SEG0 0
+#define SMUIO_BASE__INST2_SEG1 0
+#define SMUIO_BASE__INST2_SEG2 0
+#define SMUIO_BASE__INST2_SEG3 0
+#define SMUIO_BASE__INST2_SEG4 0
+
+#define SMUIO_BASE__INST3_SEG0 0
+#define SMUIO_BASE__INST3_SEG1 0
+#define SMUIO_BASE__INST3_SEG2 0
+#define SMUIO_BASE__INST3_SEG3 0
+#define SMUIO_BASE__INST3_SEG4 0
+
+#define SMUIO_BASE__INST4_SEG0 0
+#define SMUIO_BASE__INST4_SEG1 0
+#define SMUIO_BASE__INST4_SEG2 0
+#define SMUIO_BASE__INST4_SEG3 0
+#define SMUIO_BASE__INST4_SEG4 0
+
+#define SMUIO_BASE__INST5_SEG0 0
+#define SMUIO_BASE__INST5_SEG1 0
+#define SMUIO_BASE__INST5_SEG2 0
+#define SMUIO_BASE__INST5_SEG3 0
+#define SMUIO_BASE__INST5_SEG4 0
+
+#define SMUIO_BASE__INST6_SEG0 0
+#define SMUIO_BASE__INST6_SEG1 0
+#define SMUIO_BASE__INST6_SEG2 0
+#define SMUIO_BASE__INST6_SEG3 0
+#define SMUIO_BASE__INST6_SEG4 0
+
+#define THM_BASE__INST0_SEG0 0x00016600
+#define THM_BASE__INST0_SEG1 0x02400C00
+#define THM_BASE__INST0_SEG2 0
+#define THM_BASE__INST0_SEG3 0
+#define THM_BASE__INST0_SEG4 0
+
+#define THM_BASE__INST1_SEG0 0
+#define THM_BASE__INST1_SEG1 0
+#define THM_BASE__INST1_SEG2 0
+#define THM_BASE__INST1_SEG3 0
+#define THM_BASE__INST1_SEG4 0
+
+#define THM_BASE__INST2_SEG0 0
+#define THM_BASE__INST2_SEG1 0
+#define THM_BASE__INST2_SEG2 0
+#define THM_BASE__INST2_SEG3 0
+#define THM_BASE__INST2_SEG4 0
+
+#define THM_BASE__INST3_SEG0 0
+#define THM_BASE__INST3_SEG1 0
+#define THM_BASE__INST3_SEG2 0
+#define THM_BASE__INST3_SEG3 0
+#define THM_BASE__INST3_SEG4 0
+
+#define THM_BASE__INST4_SEG0 0
+#define THM_BASE__INST4_SEG1 0
+#define THM_BASE__INST4_SEG2 0
+#define THM_BASE__INST4_SEG3 0
+#define THM_BASE__INST4_SEG4 0
+
+#define THM_BASE__INST5_SEG0 0
+#define THM_BASE__INST5_SEG1 0
+#define THM_BASE__INST5_SEG2 0
+#define THM_BASE__INST5_SEG3 0
+#define THM_BASE__INST5_SEG4 0
+
+#define THM_BASE__INST6_SEG0 0
+#define THM_BASE__INST6_SEG1 0
+#define THM_BASE__INST6_SEG2 0
+#define THM_BASE__INST6_SEG3 0
+#define THM_BASE__INST6_SEG4 0
+
+#define UMC_BASE__INST0_SEG0 0x00014000
+#define UMC_BASE__INST0_SEG1 0x02425800
+#define UMC_BASE__INST0_SEG2 0
+#define UMC_BASE__INST0_SEG3 0
+#define UMC_BASE__INST0_SEG4 0
+
+#define UMC_BASE__INST1_SEG0 0x00054000
+#define UMC_BASE__INST1_SEG1 0x02425C00
+#define UMC_BASE__INST1_SEG2 0
+#define UMC_BASE__INST1_SEG3 0
+#define UMC_BASE__INST1_SEG4 0
+
+#define UMC_BASE__INST2_SEG0 0x00094000
+#define UMC_BASE__INST2_SEG1 0x02426000
+#define UMC_BASE__INST2_SEG2 0
+#define UMC_BASE__INST2_SEG3 0
+#define UMC_BASE__INST2_SEG4 0
+
+#define UMC_BASE__INST3_SEG0 0x000D4000
+#define UMC_BASE__INST3_SEG1 0x02426400
+#define UMC_BASE__INST3_SEG2 0
+#define UMC_BASE__INST3_SEG3 0
+#define UMC_BASE__INST3_SEG4 0
+
+#define UMC_BASE__INST4_SEG0 0x00114000
+#define UMC_BASE__INST4_SEG1 0x02426800
+#define UMC_BASE__INST4_SEG2 0
+#define UMC_BASE__INST4_SEG3 0
+#define UMC_BASE__INST4_SEG4 0
+
+#define UMC_BASE__INST5_SEG0 0x00154000
+#define UMC_BASE__INST5_SEG1 0x02426C00
+#define UMC_BASE__INST5_SEG2 0
+#define UMC_BASE__INST5_SEG3 0
+#define UMC_BASE__INST5_SEG4 0
+
+#define UMC_BASE__INST6_SEG0 0x00194000
+#define UMC_BASE__INST6_SEG1 0x02427000
+#define UMC_BASE__INST6_SEG2 0
+#define UMC_BASE__INST6_SEG3 0
+#define UMC_BASE__INST6_SEG4 0
+
+#define USB0_BASE__INST0_SEG0 0x0242A800
+#define USB0_BASE__INST0_SEG1 0x05B00000
+#define USB0_BASE__INST0_SEG2 0
+#define USB0_BASE__INST0_SEG3 0
+#define USB0_BASE__INST0_SEG4 0
+
+#define USB0_BASE__INST1_SEG0 0
+#define USB0_BASE__INST1_SEG1 0
+#define USB0_BASE__INST1_SEG2 0
+#define USB0_BASE__INST1_SEG3 0
+#define USB0_BASE__INST1_SEG4 0
+
+#define USB0_BASE__INST2_SEG0 0
+#define USB0_BASE__INST2_SEG1 0
+#define USB0_BASE__INST2_SEG2 0
+#define USB0_BASE__INST2_SEG3 0
+#define USB0_BASE__INST2_SEG4 0
+
+#define USB0_BASE__INST3_SEG0 0
+#define USB0_BASE__INST3_SEG1 0
+#define USB0_BASE__INST3_SEG2 0
+#define USB0_BASE__INST3_SEG3 0
+#define USB0_BASE__INST3_SEG4 0
+
+#define USB0_BASE__INST4_SEG0 0
+#define USB0_BASE__INST4_SEG1 0
+#define USB0_BASE__INST4_SEG2 0
+#define USB0_BASE__INST4_SEG3 0
+#define USB0_BASE__INST4_SEG4 0
+
+#define USB0_BASE__INST5_SEG0 0
+#define USB0_BASE__INST5_SEG1 0
+#define USB0_BASE__INST5_SEG2 0
+#define USB0_BASE__INST5_SEG3 0
+#define USB0_BASE__INST5_SEG4 0
+
+#define USB0_BASE__INST6_SEG0 0
+#define USB0_BASE__INST6_SEG1 0
+#define USB0_BASE__INST6_SEG2 0
+#define USB0_BASE__INST6_SEG3 0
+#define USB0_BASE__INST6_SEG4 0
+
+#define VCN_BASE__INST0_SEG0 0x00007800
+#define VCN_BASE__INST0_SEG1 0x00007E00
+#define VCN_BASE__INST0_SEG2 0x02403000
+#define VCN_BASE__INST0_SEG3 0
+#define VCN_BASE__INST0_SEG4 0
+
+#define VCN_BASE__INST1_SEG0 0x00007B00
+#define VCN_BASE__INST1_SEG1 0x00012000
+#define VCN_BASE__INST1_SEG2 0x02445000
+#define VCN_BASE__INST1_SEG3 0
+#define VCN_BASE__INST1_SEG4 0
+
+#define VCN_BASE__INST2_SEG0 0
+#define VCN_BASE__INST2_SEG1 0
+#define VCN_BASE__INST2_SEG2 0
+#define VCN_BASE__INST2_SEG3 0
+#define VCN_BASE__INST2_SEG4 0
+
+#define VCN_BASE__INST3_SEG0 0
+#define VCN_BASE__INST3_SEG1 0
+#define VCN_BASE__INST3_SEG2 0
+#define VCN_BASE__INST3_SEG3 0
+#define VCN_BASE__INST3_SEG4 0
+
+#define VCN_BASE__INST4_SEG0 0
+#define VCN_BASE__INST4_SEG1 0
+#define VCN_BASE__INST4_SEG2 0
+#define VCN_BASE__INST4_SEG3 0
+#define VCN_BASE__INST4_SEG4 0
+
+#define VCN_BASE__INST5_SEG0 0
+#define VCN_BASE__INST5_SEG1 0
+#define VCN_BASE__INST5_SEG2 0
+#define VCN_BASE__INST5_SEG3 0
+#define VCN_BASE__INST5_SEG4 0
+
+#define VCN_BASE__INST6_SEG0 0
+#define VCN_BASE__INST6_SEG1 0
+#define VCN_BASE__INST6_SEG2 0
+#define VCN_BASE__INST6_SEG3 0
+#define VCN_BASE__INST6_SEG4 0
+
+#endif
--
2.25.4
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^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH 014/207] drm/amdgpu/soc15: add common ip block for sienna_cichlid
2020-06-01 17:59 [PATCH 000/207] Add Support for Sienna Cichlid Alex Deucher
` (8 preceding siblings ...)
2020-06-01 17:59 ` [PATCH 013/207] drm/amdgpu: initialize IP offset for sienna_cichlid (v2) Alex Deucher
@ 2020-06-01 17:59 ` Alex Deucher
2020-06-01 17:59 ` [PATCH 015/207] drm/amdgpu: add support on mmhub " Alex Deucher
` (72 subsequent siblings)
82 siblings, 0 replies; 88+ messages in thread
From: Alex Deucher @ 2020-06-01 17:59 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Likun Gao, Hawking Zhang
From: Likun Gao <Likun.Gao@amd.com>
Add common ip block for sienna_cichlid.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/nv.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index 9466dc52df53..fd250e46cca2 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -483,6 +483,9 @@ int nv_set_ip_blocks(struct amdgpu_device *adev)
if (!amdgpu_sriov_vf(adev))
amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block);
break;
+ case CHIP_SIENNA_CICHLID:
+ amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
+ break;
default:
return -EINVAL;
}
--
2.25.4
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^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH 015/207] drm/amdgpu: add support on mmhub for sienna_cichlid
2020-06-01 17:59 [PATCH 000/207] Add Support for Sienna Cichlid Alex Deucher
` (9 preceding siblings ...)
2020-06-01 17:59 ` [PATCH 014/207] drm/amdgpu/soc15: add common ip block for sienna_cichlid Alex Deucher
@ 2020-06-01 17:59 ` Alex Deucher
2020-06-01 17:59 ` [PATCH 016/207] drm/amdgpu: add support gfxhub for sienna_cichlid (v3) Alex Deucher
` (71 subsequent siblings)
82 siblings, 0 replies; 88+ messages in thread
From: Alex Deucher @ 2020-06-01 17:59 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Likun Gao, Hawking Zhang
From: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c | 71 ++++++++++++++++++++-----
1 file changed, 57 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
index 616309e85d6e..b83a56d67428 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
@@ -31,6 +31,11 @@
#include "soc15_common.h"
+#define mmMM_ATC_L2_MISC_CG_Sienna_Cichlid 0x064d
+#define mmMM_ATC_L2_MISC_CG_Sienna_Cichlid_BASE_IDX 0
+#define mmDAGB0_CNTL_MISC2_Sienna_Cichlid 0x0070
+#define mmDAGB0_CNTL_MISC2_Sienna_Cichlid_BASE_IDX 0
+
void mmhub_v2_0_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,
uint64_t page_table_base)
{
@@ -367,9 +372,16 @@ static void mmhub_v2_0_update_medium_grain_clock_gating(struct amdgpu_device *ad
{
uint32_t def, data, def1, data1;
- def = data = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG);
-
- def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2);
+ switch (adev->asic_type) {
+ case CHIP_SIENNA_CICHLID:
+ def = data = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG_Sienna_Cichlid);
+ def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2_Sienna_Cichlid);
+ break;
+ default:
+ def = data = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG);
+ def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2);
+ break;
+ }
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) {
data |= MM_ATC_L2_MISC_CG__ENABLE_MASK;
@@ -392,11 +404,20 @@ static void mmhub_v2_0_update_medium_grain_clock_gating(struct amdgpu_device *ad
DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
}
- if (def != data)
- WREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG, data);
-
- if (def1 != data1)
- WREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2, data1);
+ switch (adev->asic_type) {
+ case CHIP_SIENNA_CICHLID:
+ if (def != data)
+ WREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG_Sienna_Cichlid, data);
+ if (def1 != data1)
+ WREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2_Sienna_Cichlid, data1);
+ break;
+ default:
+ if (def != data)
+ WREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG, data);
+ if (def1 != data1)
+ WREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2, data1);
+ break;
+ }
}
static void mmhub_v2_0_update_medium_grain_light_sleep(struct amdgpu_device *adev,
@@ -404,15 +425,30 @@ static void mmhub_v2_0_update_medium_grain_light_sleep(struct amdgpu_device *ade
{
uint32_t def, data;
- def = data = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG);
+ switch (adev->asic_type) {
+ case CHIP_SIENNA_CICHLID:
+ def = data = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG_Sienna_Cichlid);
+ break;
+ default:
+ def = data = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG);
+ break;
+ }
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS))
data |= MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK;
else
data &= ~MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK;
- if (def != data)
- WREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG, data);
+ if (def != data) {
+ switch (adev->asic_type) {
+ case CHIP_SIENNA_CICHLID:
+ WREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG_Sienna_Cichlid, data);
+ break;
+ default:
+ WREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG, data);
+ break;
+ }
+ }
}
int mmhub_v2_0_set_clockgating(struct amdgpu_device *adev,
@@ -444,9 +480,16 @@ void mmhub_v2_0_get_clockgating(struct amdgpu_device *adev, u32 *flags)
if (amdgpu_sriov_vf(adev))
*flags = 0;
- data = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG);
-
- data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2);
+ switch (adev->asic_type) {
+ case CHIP_SIENNA_CICHLID:
+ data = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG_Sienna_Cichlid);
+ data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2_Sienna_Cichlid);
+ break;
+ default:
+ data = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG);
+ data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2);
+ break;
+ }
/* AMD_CG_SUPPORT_MC_MGCG */
if ((data & MM_ATC_L2_MISC_CG__ENABLE_MASK) &&
--
2.25.4
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^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH 016/207] drm/amdgpu: add support gfxhub for sienna_cichlid (v3)
2020-06-01 17:59 [PATCH 000/207] Add Support for Sienna Cichlid Alex Deucher
` (10 preceding siblings ...)
2020-06-01 17:59 ` [PATCH 015/207] drm/amdgpu: add support on mmhub " Alex Deucher
@ 2020-06-01 17:59 ` Alex Deucher
2020-06-01 17:59 ` [PATCH 017/207] drm/amdgpu: add gmc ip block for sienna_cichlid Alex Deucher
` (70 subsequent siblings)
82 siblings, 0 replies; 88+ messages in thread
From: Alex Deucher @ 2020-06-01 17:59 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Likun Gao, Hawking Zhang
From: Likun Gao <Likun.Gao@amd.com>
GFX10.3 is used for sienna_cichlid.
v2: squash in BANK_SELECT and FRAGMENT_SIZE fixes (Alex)
v3: squash in smallk update (Alex)
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/Makefile | 2 +-
drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c | 375 +++++++++++++++++++++++
drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.h | 37 +++
3 files changed, 413 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c
create mode 100644 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.h
diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile
index 0fdcb71a4feb..f6e16028a434 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -80,7 +80,7 @@ amdgpu-y += \
gmc_v7_0.o \
gmc_v8_0.o \
gfxhub_v1_0.o mmhub_v1_0.o gmc_v9_0.o gfxhub_v1_1.o mmhub_v9_4.o \
- gfxhub_v2_0.o mmhub_v2_0.o gmc_v10_0.o
+ gfxhub_v2_0.o mmhub_v2_0.o gmc_v10_0.o gfxhub_v2_1.o
# add UMC block
amdgpu-y += \
diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c
new file mode 100644
index 000000000000..34c12c8ce149
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c
@@ -0,0 +1,375 @@
+/*
+ * Copyright 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#include "amdgpu.h"
+#include "gfxhub_v2_1.h"
+
+#include "gc/gc_10_3_0_offset.h"
+#include "gc/gc_10_3_0_sh_mask.h"
+#include "gc/gc_10_3_0_default.h"
+#include "navi10_enum.h"
+
+#include "soc15_common.h"
+
+u64 gfxhub_v2_1_get_fb_location(struct amdgpu_device *adev)
+{
+ u64 base = RREG32_SOC15(GC, 0, mmGCMC_VM_FB_LOCATION_BASE);
+
+ base &= GCMC_VM_FB_LOCATION_BASE__FB_BASE_MASK;
+ base <<= 24;
+
+ return base;
+}
+
+u64 gfxhub_v2_1_get_mc_fb_offset(struct amdgpu_device *adev)
+{
+ return (u64)RREG32_SOC15(GC, 0, mmGCMC_VM_FB_OFFSET) << 24;
+}
+
+void gfxhub_v2_1_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,
+ uint64_t page_table_base)
+{
+ /* two registers distance between mmGCVM_CONTEXT0_* to mmGCVM_CONTEXT1_* */
+ int offset = mmGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32
+ - mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32;
+
+ WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
+ offset * vmid, lower_32_bits(page_table_base));
+
+ WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
+ offset * vmid, upper_32_bits(page_table_base));
+}
+
+static void gfxhub_v2_1_init_gart_aperture_regs(struct amdgpu_device *adev)
+{
+ uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
+
+ gfxhub_v2_1_setup_vm_pt_regs(adev, 0, pt_base);
+
+ WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
+ (u32)(adev->gmc.gart_start >> 12));
+ WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
+ (u32)(adev->gmc.gart_start >> 44));
+
+ WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
+ (u32)(adev->gmc.gart_end >> 12));
+ WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
+ (u32)(adev->gmc.gart_end >> 44));
+}
+
+static void gfxhub_v2_1_init_system_aperture_regs(struct amdgpu_device *adev)
+{
+ uint64_t value;
+
+ /* Disable AGP. */
+ WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_BASE, 0);
+ WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_TOP, 0);
+ WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_BOT, 0x00FFFFFF);
+
+ /* Program the system aperture low logical page number. */
+ WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_LOW_ADDR,
+ adev->gmc.vram_start >> 18);
+ WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
+ adev->gmc.vram_end >> 18);
+
+ /* Set default page address. */
+ value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start
+ + adev->vm_manager.vram_base_offset;
+ WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
+ (u32)(value >> 12));
+ WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
+ (u32)(value >> 44));
+
+ /* Program "protection fault". */
+ WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,
+ (u32)(adev->dummy_page_addr >> 12));
+ WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,
+ (u32)((u64)adev->dummy_page_addr >> 44));
+
+ WREG32_FIELD15(GC, 0, GCVM_L2_PROTECTION_FAULT_CNTL2,
+ ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1);
+}
+
+
+static void gfxhub_v2_1_init_tlb_regs(struct amdgpu_device *adev)
+{
+ uint32_t tmp;
+
+ /* Setup TLB control */
+ tmp = RREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL);
+
+ tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
+ tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
+ tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,
+ ENABLE_ADVANCED_DRIVER_MODEL, 1);
+ tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,
+ SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
+ tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);
+ tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,
+ MTYPE, MTYPE_UC); /* UC, uncached */
+
+ WREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL, tmp);
+}
+
+static void gfxhub_v2_1_init_cache_regs(struct amdgpu_device *adev)
+{
+ uint32_t tmp;
+
+ /* Setup L2 cache */
+ tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL);
+ tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_CACHE, 1);
+ tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0);
+ tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL,
+ ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);
+ /* XXX for emulation, Refer to closed source code.*/
+ tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL,
+ L2_PDE0_CACHE_TAG_GENERATION_MODE, 0);
+ tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);
+ tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
+ tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);
+ WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL, tmp);
+
+ tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL2);
+ tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
+ tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
+ WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL2, tmp);
+
+ tmp = mmGCVM_L2_CNTL3_DEFAULT;
+ if (adev->gmc.translate_further) {
+ tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 12);
+ tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3,
+ L2_CACHE_BIGK_FRAGMENT_SIZE, 9);
+ } else {
+ tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 9);
+ tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3,
+ L2_CACHE_BIGK_FRAGMENT_SIZE, 6);
+ }
+ WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL3, tmp);
+
+ tmp = mmGCVM_L2_CNTL4_DEFAULT;
+ tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
+ tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
+ WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL4, tmp);
+
+ tmp = mmGCVM_L2_CNTL5_DEFAULT;
+ tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0);
+ WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL5, tmp);
+}
+
+static void gfxhub_v2_1_enable_system_domain(struct amdgpu_device *adev)
+{
+ uint32_t tmp;
+
+ tmp = RREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_CNTL);
+ tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
+ tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
+ tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL,
+ RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0);
+ WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_CNTL, tmp);
+}
+
+static void gfxhub_v2_1_disable_identity_aperture(struct amdgpu_device *adev)
+{
+ WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32,
+ 0xFFFFFFFF);
+ WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32,
+ 0x0000000F);
+
+ WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32,
+ 0);
+ WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32,
+ 0);
+
+ WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32, 0);
+ WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32, 0);
+
+}
+
+static void gfxhub_v2_1_setup_vmid_config(struct amdgpu_device *adev)
+{
+ int i;
+ uint32_t tmp;
+
+ for (i = 0; i <= 14; i++) {
+ tmp = RREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_CNTL, i);
+ tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
+ tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
+ adev->vm_manager.num_level);
+ tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
+ RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
+ tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
+ DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
+ tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
+ PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
+ tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
+ VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
+ tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
+ READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
+ tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
+ WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
+ tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
+ EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
+ tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
+ PAGE_TABLE_BLOCK_SIZE,
+ adev->vm_manager.block_size - 9);
+ /* Send no-retry XNACK on fault to suppress VM fault storm. */
+ tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
+ RETRY_PERMISSION_OR_INVALID_PAGE_FAULT,
+ !amdgpu_noretry);
+ WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_CNTL, i, tmp);
+ WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, i*2, 0);
+ WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, i*2, 0);
+ WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32, i*2,
+ lower_32_bits(adev->vm_manager.max_pfn - 1));
+ WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32, i*2,
+ upper_32_bits(adev->vm_manager.max_pfn - 1));
+ }
+}
+
+static void gfxhub_v2_1_program_invalidation(struct amdgpu_device *adev)
+{
+ unsigned i;
+
+ for (i = 0 ; i < 18; ++i) {
+ WREG32_SOC15_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32,
+ 2 * i, 0xffffffff);
+ WREG32_SOC15_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32,
+ 2 * i, 0x1f);
+ }
+}
+
+int gfxhub_v2_1_gart_enable(struct amdgpu_device *adev)
+{
+ if (amdgpu_sriov_vf(adev)) {
+ /*
+ * GCMC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are
+ * VF copy registers so vbios post doesn't program them, for
+ * SRIOV driver need to program them
+ */
+ WREG32_SOC15(GC, 0, mmGCMC_VM_FB_LOCATION_BASE,
+ adev->gmc.vram_start >> 24);
+ WREG32_SOC15(GC, 0, mmGCMC_VM_FB_LOCATION_TOP,
+ adev->gmc.vram_end >> 24);
+ }
+
+ /* GART Enable. */
+ gfxhub_v2_1_init_gart_aperture_regs(adev);
+ gfxhub_v2_1_init_system_aperture_regs(adev);
+ gfxhub_v2_1_init_tlb_regs(adev);
+ gfxhub_v2_1_init_cache_regs(adev);
+
+ gfxhub_v2_1_enable_system_domain(adev);
+ gfxhub_v2_1_disable_identity_aperture(adev);
+ gfxhub_v2_1_setup_vmid_config(adev);
+ gfxhub_v2_1_program_invalidation(adev);
+
+ return 0;
+}
+
+void gfxhub_v2_1_gart_disable(struct amdgpu_device *adev)
+{
+ u32 tmp;
+ u32 i;
+
+ /* Disable all tables */
+ for (i = 0; i < 16; i++)
+ WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_CNTL, i, 0);
+
+ /* Setup TLB control */
+ tmp = RREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL);
+ tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
+ tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,
+ ENABLE_ADVANCED_DRIVER_MODEL, 0);
+ WREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL, tmp);
+
+ /* Setup L2 cache */
+ WREG32_FIELD15(GC, 0, GCVM_L2_CNTL, ENABLE_L2_CACHE, 0);
+ WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL3, 0);
+}
+
+/**
+ * gfxhub_v2_1_set_fault_enable_default - update GART/VM fault handling
+ *
+ * @adev: amdgpu_device pointer
+ * @value: true redirects VM faults to the default page
+ */
+void gfxhub_v2_1_set_fault_enable_default(struct amdgpu_device *adev,
+ bool value)
+{
+ u32 tmp;
+ tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL);
+ tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
+ RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
+ tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
+ PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
+ tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
+ PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value);
+ tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
+ PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value);
+ tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
+ TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT,
+ value);
+ tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
+ NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value);
+ tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
+ DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
+ tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
+ VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
+ tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
+ READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
+ tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
+ WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
+ tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
+ EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
+ if (!value) {
+ tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
+ CRASH_ON_NO_RETRY_FAULT, 1);
+ tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
+ CRASH_ON_RETRY_FAULT, 1);
+ }
+ WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL, tmp);
+}
+
+void gfxhub_v2_1_init(struct amdgpu_device *adev)
+{
+ struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
+
+ hub->ctx0_ptb_addr_lo32 =
+ SOC15_REG_OFFSET(GC, 0,
+ mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32);
+ hub->ctx0_ptb_addr_hi32 =
+ SOC15_REG_OFFSET(GC, 0,
+ mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32);
+ hub->vm_inv_eng0_sem =
+ SOC15_REG_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_SEM);
+ hub->vm_inv_eng0_req =
+ SOC15_REG_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_REQ);
+ hub->vm_inv_eng0_ack =
+ SOC15_REG_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_ACK);
+ hub->vm_context0_cntl =
+ SOC15_REG_OFFSET(GC, 0, mmGCVM_CONTEXT0_CNTL);
+ hub->vm_l2_pro_fault_status =
+ SOC15_REG_OFFSET(GC, 0, mmGCVM_L2_PROTECTION_FAULT_STATUS);
+ hub->vm_l2_pro_fault_cntl =
+ SOC15_REG_OFFSET(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL);
+}
diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.h b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.h
new file mode 100644
index 000000000000..e385ae024a47
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.h
@@ -0,0 +1,37 @@
+/*
+ * Copyright 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef __GFXHUB_V2_1_H__
+#define __GFXHUB_V2_1_H__
+
+u64 gfxhub_v2_1_get_fb_location(struct amdgpu_device *adev);
+int gfxhub_v2_1_gart_enable(struct amdgpu_device *adev);
+void gfxhub_v2_1_gart_disable(struct amdgpu_device *adev);
+void gfxhub_v2_1_set_fault_enable_default(struct amdgpu_device *adev,
+ bool value);
+void gfxhub_v2_1_init(struct amdgpu_device *adev);
+u64 gfxhub_v2_1_get_mc_fb_offset(struct amdgpu_device *adev);
+void gfxhub_v2_1_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,
+ uint64_t page_table_base);
+
+#endif
--
2.25.4
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH 017/207] drm/amdgpu: add gmc ip block for sienna_cichlid
2020-06-01 17:59 [PATCH 000/207] Add Support for Sienna Cichlid Alex Deucher
` (11 preceding siblings ...)
2020-06-01 17:59 ` [PATCH 016/207] drm/amdgpu: add support gfxhub for sienna_cichlid (v3) Alex Deucher
@ 2020-06-01 17:59 ` Alex Deucher
2020-06-01 17:59 ` [PATCH 018/207] drm/amdgpu: add ih " Alex Deucher
` (69 subsequent siblings)
82 siblings, 0 replies; 88+ messages in thread
From: Alex Deucher @ 2020-06-01 17:59 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Likun Gao, Hawking Zhang
From: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 49 +++++++++++++++++++-------
drivers/gpu/drm/amd/amdgpu/nv.c | 1 +
2 files changed, 37 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
index fb8030cf65cd..afca175a092c 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
@@ -45,6 +45,7 @@
#include "nbio_v2_3.h"
#include "gfxhub_v2_0.h"
+#include "gfxhub_v2_1.h"
#include "mmhub_v2_0.h"
#include "athub_v2_0.h"
/* XXX Move this macro to navi10 header file, which is like vid.h for VI.*/
@@ -666,13 +667,19 @@ static void gmc_v10_0_vram_gtt_location(struct amdgpu_device *adev,
{
u64 base = 0;
- base = gfxhub_v2_0_get_fb_location(adev);
+ if (adev->asic_type == CHIP_SIENNA_CICHLID)
+ base = gfxhub_v2_1_get_fb_location(adev);
+ else
+ base = gfxhub_v2_0_get_fb_location(adev);
amdgpu_gmc_vram_location(adev, &adev->gmc, base);
amdgpu_gmc_gart_location(adev, mc);
/* base offset of vram pages */
- adev->vm_manager.vram_base_offset = gfxhub_v2_0_get_mc_fb_offset(adev);
+ if (adev->asic_type == CHIP_SIENNA_CICHLID)
+ adev->vm_manager.vram_base_offset = gfxhub_v2_1_get_mc_fb_offset(adev);
+ else
+ adev->vm_manager.vram_base_offset = gfxhub_v2_0_get_mc_fb_offset(adev);
}
/**
@@ -781,20 +788,27 @@ static int gmc_v10_0_sw_init(void *handle)
int r, vram_width = 0, vram_type = 0, vram_vendor = 0;
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- gfxhub_v2_0_init(adev);
+ if (adev->asic_type == CHIP_SIENNA_CICHLID)
+ gfxhub_v2_1_init(adev);
+ else
+ gfxhub_v2_0_init(adev);
+
mmhub_v2_0_init(adev);
spin_lock_init(&adev->gmc.invalidate_lock);
- r = amdgpu_atomfirmware_get_vram_info(adev,
- &vram_width, &vram_type, &vram_vendor);
- if (!amdgpu_emu_mode)
- adev->gmc.vram_width = vram_width;
- else
+ if (adev->asic_type == CHIP_SIENNA_CICHLID && amdgpu_emu_mode == 1) {
+ adev->gmc.vram_type = AMDGPU_VRAM_TYPE_GDDR6;
adev->gmc.vram_width = 1 * 128; /* numchan * chansize */
+ } else {
+ r = amdgpu_atomfirmware_get_vram_info(adev,
+ &vram_width, &vram_type, &vram_vendor);
+ adev->gmc.vram_width = vram_width;
+
+ adev->gmc.vram_type = vram_type;
+ adev->gmc.vram_vendor = vram_vendor;
+ }
- adev->gmc.vram_type = vram_type;
- adev->gmc.vram_vendor = vram_vendor;
switch (adev->asic_type) {
case CHIP_NAVI10:
case CHIP_NAVI14:
@@ -925,7 +939,10 @@ static int gmc_v10_0_gart_enable(struct amdgpu_device *adev)
if (r)
return r;
- r = gfxhub_v2_0_gart_enable(adev);
+ if (adev->asic_type == CHIP_SIENNA_CICHLID)
+ r = gfxhub_v2_1_gart_enable(adev);
+ else
+ r = gfxhub_v2_0_gart_enable(adev);
if (r)
return r;
@@ -946,7 +963,10 @@ static int gmc_v10_0_gart_enable(struct amdgpu_device *adev)
value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ?
false : true;
- gfxhub_v2_0_set_fault_enable_default(adev, value);
+ if (adev->asic_type == CHIP_SIENNA_CICHLID)
+ gfxhub_v2_1_set_fault_enable_default(adev, value);
+ else
+ gfxhub_v2_0_set_fault_enable_default(adev, value);
mmhub_v2_0_set_fault_enable_default(adev, value);
gmc_v10_0_flush_gpu_tlb(adev, 0, AMDGPU_MMHUB_0, 0);
gmc_v10_0_flush_gpu_tlb(adev, 0, AMDGPU_GFXHUB_0, 0);
@@ -984,7 +1004,10 @@ static int gmc_v10_0_hw_init(void *handle)
*/
static void gmc_v10_0_gart_disable(struct amdgpu_device *adev)
{
- gfxhub_v2_0_gart_disable(adev);
+ if (adev->asic_type == CHIP_SIENNA_CICHLID)
+ gfxhub_v2_1_gart_disable(adev);
+ else
+ gfxhub_v2_0_gart_disable(adev);
mmhub_v2_0_gart_disable(adev);
amdgpu_gart_table_vram_unpin(adev);
}
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index fd250e46cca2..e6fc244d42aa 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -485,6 +485,7 @@ int nv_set_ip_blocks(struct amdgpu_device *adev)
break;
case CHIP_SIENNA_CICHLID:
amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
+ amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
break;
default:
return -EINVAL;
--
2.25.4
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH 018/207] drm/amdgpu: add ih ip block for sienna_cichlid
2020-06-01 17:59 [PATCH 000/207] Add Support for Sienna Cichlid Alex Deucher
` (12 preceding siblings ...)
2020-06-01 17:59 ` [PATCH 017/207] drm/amdgpu: add gmc ip block for sienna_cichlid Alex Deucher
@ 2020-06-01 17:59 ` Alex Deucher
2020-06-01 17:59 ` [PATCH 019/207] drm/amdgpu: add gfx ip block for sienna_cichlid (v3) Alex Deucher
` (68 subsequent siblings)
82 siblings, 0 replies; 88+ messages in thread
From: Alex Deucher @ 2020-06-01 17:59 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Likun Gao, Hawking Zhang
From: Likun Gao <Likun.Gao@amd.com>
Update IH handling for sienna_cichlid
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 21 +++++++++++++++++----
drivers/gpu/drm/amd/amdgpu/nv.c | 1 +
2 files changed, 18 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
index f97857ed3c7e..471dc82fd1aa 100644
--- a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
@@ -34,6 +34,9 @@
#define MAX_REARM_RETRY 10
+#define mmIH_CHICKEN_Sienna_Cichlid 0x018d
+#define mmIH_CHICKEN_Sienna_Cichlid_BASE_IDX 0
+
static void navi10_ih_set_interrupt_funcs(struct amdgpu_device *adev);
/**
@@ -265,10 +268,20 @@ static int navi10_ih_irq_init(struct amdgpu_device *adev)
if (unlikely(adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT)) {
if (ih->use_bus_addr) {
- ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN);
- ih_chicken = REG_SET_FIELD(ih_chicken,
- IH_CHICKEN, MC_SPACE_GPA_ENABLE, 1);
- WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN, ih_chicken);
+ switch (adev->asic_type) {
+ case CHIP_SIENNA_CICHLID:
+ ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN_Sienna_Cichlid);
+ ih_chicken = REG_SET_FIELD(ih_chicken,
+ IH_CHICKEN, MC_SPACE_GPA_ENABLE, 1);
+ WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN_Sienna_Cichlid, ih_chicken);
+ break;
+ default:
+ ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN);
+ ih_chicken = REG_SET_FIELD(ih_chicken,
+ IH_CHICKEN, MC_SPACE_GPA_ENABLE, 1);
+ WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN, ih_chicken);
+ break;
+ }
}
}
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index e6fc244d42aa..7600f42ba3e1 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -486,6 +486,7 @@ int nv_set_ip_blocks(struct amdgpu_device *adev)
case CHIP_SIENNA_CICHLID:
amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
+ amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
break;
default:
return -EINVAL;
--
2.25.4
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH 019/207] drm/amdgpu: add gfx ip block for sienna_cichlid (v3)
2020-06-01 17:59 [PATCH 000/207] Add Support for Sienna Cichlid Alex Deucher
` (13 preceding siblings ...)
2020-06-01 17:59 ` [PATCH 018/207] drm/amdgpu: add ih " Alex Deucher
@ 2020-06-01 17:59 ` Alex Deucher
2020-06-01 17:59 ` [PATCH 020/207] drm/amdgpu: add sdma2 and sdma3 irqsrc header files for sienna_cichlid (v2) Alex Deucher
` (67 subsequent siblings)
82 siblings, 0 replies; 88+ messages in thread
From: Alex Deucher @ 2020-06-01 17:59 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Likun Gao, Hawking Zhang
From: Likun Gao <Likun.Gao@amd.com>
Add support for GC 10.3.
v2: Squash in gb_addr_config fix (Alex)
v3: Add num_pkrs support (Alex)
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 1 +
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 15 +++++++++++++++
drivers/gpu/drm/amd/amdgpu/nv.c | 1 +
3 files changed, 17 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
index d43c11671a38..50be8e3a443b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
@@ -134,6 +134,7 @@ struct gb_addr_config {
uint8_t num_banks;
uint8_t num_se;
uint8_t num_rb_per_se;
+ uint8_t num_pkrs;
};
struct amdgpu_gfx_config {
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 8a6a9ba85714..feedbde0565d 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -63,6 +63,9 @@
#define mmCGTT_GS_NGG_CLK_CTRL 0x5087
#define mmCGTT_GS_NGG_CLK_CTRL_BASE_IDX 1
+#define GB_ADDR_CONFIG__NUM_PKRS__SHIFT 0x8
+#define GB_ADDR_CONFIG__NUM_PKRS_MASK 0x00000700L
+
MODULE_FIRMWARE("amdgpu/navi10_ce.bin");
MODULE_FIRMWARE("amdgpu/navi10_pfp.bin");
MODULE_FIRMWARE("amdgpu/navi10_me.bin");
@@ -4002,6 +4005,16 @@ static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev)
adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
break;
+ case CHIP_SIENNA_CICHLID:
+ adev->gfx.config.max_hw_contexts = 8;
+ adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
+ adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
+ adev->gfx.config.sc_hiz_tile_fifo_size = 0;
+ adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
+ gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
+ adev->gfx.config.gb_addr_config_fields.num_pkrs =
+ 1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS);
+ break;
default:
BUG();
break;
@@ -4107,6 +4120,7 @@ static int gfx_v10_0_sw_init(void *handle)
case CHIP_NAVI10:
case CHIP_NAVI14:
case CHIP_NAVI12:
+ case CHIP_SIENNA_CICHLID:
adev->gfx.me.num_me = 1;
adev->gfx.me.num_pipe_per_me = 1;
adev->gfx.me.num_queue_per_pipe = 1;
@@ -8253,6 +8267,7 @@ static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev)
switch (adev->asic_type) {
case CHIP_NAVI10:
case CHIP_NAVI14:
+ case CHIP_SIENNA_CICHLID:
adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs;
break;
case CHIP_NAVI12:
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index 7600f42ba3e1..6dd0adb78c3a 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -487,6 +487,7 @@ int nv_set_ip_blocks(struct amdgpu_device *adev)
amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
+ amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
break;
default:
return -EINVAL;
--
2.25.4
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH 020/207] drm/amdgpu: add sdma2 and sdma3 irqsrc header files for sienna_cichlid (v2)
2020-06-01 17:59 [PATCH 000/207] Add Support for Sienna Cichlid Alex Deucher
` (14 preceding siblings ...)
2020-06-01 17:59 ` [PATCH 019/207] drm/amdgpu: add gfx ip block for sienna_cichlid (v3) Alex Deucher
@ 2020-06-01 17:59 ` Alex Deucher
2020-06-01 17:59 ` [PATCH 021/207] drm/amdgpu: add sdma ip block for sienna_cichlid (v5) Alex Deucher
` (66 subsequent siblings)
82 siblings, 0 replies; 88+ messages in thread
From: Alex Deucher @ 2020-06-01 17:59 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Likun Gao, Hawking Zhang
From: Likun Gao <Likun.Gao@amd.com>
Add irq src headers for additional SDMA blocks.
v2: Add missing licenses (Alex)
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
.../include/ivsrcid/sdma2/irqsrcs_sdma2_5_0.h | 45 +++++++++++++++++++
.../include/ivsrcid/sdma3/irqsrcs_sdma3_5_0.h | 45 +++++++++++++++++++
2 files changed, 90 insertions(+)
create mode 100644 drivers/gpu/drm/amd/include/ivsrcid/sdma2/irqsrcs_sdma2_5_0.h
create mode 100644 drivers/gpu/drm/amd/include/ivsrcid/sdma3/irqsrcs_sdma3_5_0.h
diff --git a/drivers/gpu/drm/amd/include/ivsrcid/sdma2/irqsrcs_sdma2_5_0.h b/drivers/gpu/drm/amd/include/ivsrcid/sdma2/irqsrcs_sdma2_5_0.h
new file mode 100644
index 000000000000..daa498478ba6
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/ivsrcid/sdma2/irqsrcs_sdma2_5_0.h
@@ -0,0 +1,45 @@
+/*
+ * Copyright 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef __IRQSRCS_SDMA2_5_0_H__
+#define __IRQSRCS_SDMA2_5_0_H__
+
+
+#define SDMA2_5_0__SRCID__SDMA_ATOMIC_RTN_DONE 217 // 0xD9 SDMA atomic*_rtn ops complete
+#define SDMA2_5_0__SRCID__SDMA_ATOMIC_TIMEOUT 218 // 0xDA SDMA atomic CMPSWAP loop timeout
+#define SDMA2_5_0__SRCID__SDMA_IB_PREEMPT 219 // 0xDB sdma mid-command buffer preempt interrupt
+#define SDMA2_5_0__SRCID__SDMA_ECC 220 // 0xDC ECC Error
+#define SDMA2_5_0__SRCID__SDMA_PAGE_FAULT 221 // 0xDD Page Fault Error from UTCL2 when nack=3
+#define SDMA2_5_0__SRCID__SDMA_PAGE_NULL 222 // 0xDE Page Null from UTCL2 when nack=2
+#define SDMA2_5_0__SRCID__SDMA_XNACK 223 // 0xDF Page retry timeout after UTCL2 return nack=1
+#define SDMA2_5_0__SRCID__SDMA_TRAP 224 // 0xE0 Trap
+#define SDMA2_5_0__SRCID__SDMA_SEM_INCOMPLETE_TIMEOUT 225 // 0xE1 0xDAGPF (Sem incomplete timeout)
+#define SDMA2_5_0__SRCID__SDMA_SEM_WAIT_FAIL_TIMEOUT 226 // 0xE2 Semaphore wait fail timeout
+#define SDMA2_5_0__SRCID__SDMA_SRAM_ECC 228 // 0xE4 SRAM ECC Error
+#define SDMA2_5_0__SRCID__SDMA_PREEMPT 240 // 0xF0 SDMA New Run List
+#define SDMA2_5_0__SRCID__SDMA_VM_HOLE 242 // 0xF2 MC or SEM address in VM hole
+#define SDMA2_5_0__SRCID__SDMA_CTXEMPTY 243 // 0xF3 Context Empty
+#define SDMA2_5_0__SRCID__SDMA_DOORBELL_INVALID 244 // 0xF4 Doorbell BE invalid
+#define SDMA2_5_0__SRCID__SDMA_FROZEN 245 // 0xF5 SDMA Frozen
+#define SDMA2_5_0__SRCID__SDMA_POLL_TIMEOUT 246 // 0xF6 SRBM read poll timeout
+#define SDMA2_5_0__SRCID__SDMA_SRBMWRITE 247 // 0xF7 SRBM write Protection
+
+#endif // __IRQSRCS_SDMA2_5_0_H__
diff --git a/drivers/gpu/drm/amd/include/ivsrcid/sdma3/irqsrcs_sdma3_5_0.h b/drivers/gpu/drm/amd/include/ivsrcid/sdma3/irqsrcs_sdma3_5_0.h
new file mode 100644
index 000000000000..e0ee820d5097
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/ivsrcid/sdma3/irqsrcs_sdma3_5_0.h
@@ -0,0 +1,45 @@
+/*
+ * Copyright 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef __IRQSRCS_SDMA3_5_0_H__
+#define __IRQSRCS_SDMA3_5_0_H__
+
+
+#define SDMA3_5_0__SRCID__SDMA_ATOMIC_RTN_DONE 217 // 0xD9 SDMA atomic*_rtn ops complete
+#define SDMA3_5_0__SRCID__SDMA_ATOMIC_TIMEOUT 218 // 0xDA SDMA atomic CMPSWAP loop timeout
+#define SDMA3_5_0__SRCID__SDMA_IB_PREEMPT 219 // 0xDB sdma mid-command buffer preempt interrupt
+#define SDMA3_5_0__SRCID__SDMA_ECC 220 // 0xDC ECC Error
+#define SDMA3_5_0__SRCID__SDMA_PAGE_FAULT 221 // 0xDD Page Fault Error from UTCL2 when nack=3
+#define SDMA3_5_0__SRCID__SDMA_PAGE_NULL 222 // 0xDE Page Null from UTCL2 when nack=2
+#define SDMA3_5_0__SRCID__SDMA_XNACK 223 // 0xDF Page retry timeout after UTCL2 return nack=1
+#define SDMA3_5_0__SRCID__SDMA_TRAP 224 // 0xE0 Trap
+#define SDMA3_5_0__SRCID__SDMA_SEM_INCOMPLETE_TIMEOUT 225 // 0xE1 0xDAGPF (Sem incomplete timeout)
+#define SDMA3_5_0__SRCID__SDMA_SEM_WAIT_FAIL_TIMEOUT 226 // 0xE2 Semaphore wait fail timeout
+#define SDMA3_5_0__SRCID__SDMA_SRAM_ECC 228 // 0xE4 SRAM ECC Error
+#define SDMA3_5_0__SRCID__SDMA_PREEMPT 240 // 0xF0 SDMA New Run List
+#define SDMA3_5_0__SRCID__SDMA_VM_HOLE 242 // 0xF2 MC or SEM address in VM hole
+#define SDMA3_5_0__SRCID__SDMA_CTXEMPTY 243 // 0xF3 Context Empty
+#define SDMA3_5_0__SRCID__SDMA_DOORBELL_INVALID 244 // 0xF4 Doorbell BE invalid
+#define SDMA3_5_0__SRCID__SDMA_FROZEN 245 // 0xF5 SDMA Frozen
+#define SDMA3_5_0__SRCID__SDMA_POLL_TIMEOUT 246 // 0xF6 SRBM read poll timeout
+#define SDMA3_5_0__SRCID__SDMA_SRBMWRITE 247 // 0xF7 SRBM write Protection
+
+#endif // __IRQSRCS_SDMA3_5_0_H__
--
2.25.4
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH 021/207] drm/amdgpu: add sdma ip block for sienna_cichlid (v5)
2020-06-01 17:59 [PATCH 000/207] Add Support for Sienna Cichlid Alex Deucher
` (15 preceding siblings ...)
2020-06-01 17:59 ` [PATCH 020/207] drm/amdgpu: add sdma2 and sdma3 irqsrc header files for sienna_cichlid (v2) Alex Deucher
@ 2020-06-01 17:59 ` Alex Deucher
2020-06-01 17:59 ` [PATCH 022/207] drm/amdgpu: correct SDMA3 IH clinet id for sienna_cichlid Alex Deucher
` (65 subsequent siblings)
82 siblings, 0 replies; 88+ messages in thread
From: Alex Deucher @ 2020-06-01 17:59 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Likun Gao, Hawking Zhang
From: Likun Gao <Likun.Gao@amd.com>
Sienna_Cichlid have 4 sdma controllers.
v2: add missing license to sdma_common.h (Alex)
v3: rebase (Alex)
v4: squash in policy fix (Alex)
v4: squash in fw_name fix
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/Makefile | 3 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h | 2 +
drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c | 8 +-
drivers/gpu/drm/amd/amdgpu/nv.c | 4 +
drivers/gpu/drm/amd/amdgpu/sdma_common.h | 42 +
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 1 +
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.h | 15 -
drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 1715 ++++++++++++++++++
drivers/gpu/drm/amd/amdgpu/sdma_v5_2.h | 30 +
9 files changed, 1803 insertions(+), 17 deletions(-)
create mode 100644 drivers/gpu/drm/amd/amdgpu/sdma_common.h
create mode 100644 drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
create mode 100644 drivers/gpu/drm/amd/amdgpu/sdma_v5_2.h
diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile
index f6e16028a434..e78674121dfe 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -129,7 +129,8 @@ amdgpu-y += \
sdma_v2_4.o \
sdma_v3_0.o \
sdma_v4_0.o \
- sdma_v5_0.o
+ sdma_v5_0.o \
+ sdma_v5_2.o
# add MES block
amdgpu-y += \
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h
index 3fa18003d4d6..b8eb5ece37c0 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h
@@ -180,6 +180,8 @@ typedef enum _AMDGPU_NAVI10_DOORBELL_ASSIGNMENT
/* SDMA:256~335*/
AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0 = 0x100,
AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1 = 0x10A,
+ AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE2 = 0x114,
+ AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE3 = 0x11E,
/* IH: 376~391 */
AMDGPU_NAVI10_DOORBELL_IH = 0x178,
/* MMSCH: 392~407
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c b/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
index cbcf04578b99..4a00b064be10 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
@@ -33,6 +33,10 @@
#define smnCPM_CONTROL 0x11180460
#define smnPCIE_CNTL2 0x11180070
+#define mmBIF_SDMA2_DOORBELL_RANGE 0x01d6
+#define mmBIF_SDMA2_DOORBELL_RANGE_BASE_IDX 2
+#define mmBIF_SDMA3_DOORBELL_RANGE 0x01d7
+#define mmBIF_SDMA3_DOORBELL_RANGE_BASE_IDX 2
static void nbio_v2_3_remap_hdp_registers(struct amdgpu_device *adev)
{
@@ -81,7 +85,9 @@ static void nbio_v2_3_sdma_doorbell_range(struct amdgpu_device *adev, int instan
int doorbell_size)
{
u32 reg = instance == 0 ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE) :
- SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA1_DOORBELL_RANGE);
+ instance == 1 ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA1_DOORBELL_RANGE) :
+ instance == 2 ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA2_DOORBELL_RANGE) :
+ SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA3_DOORBELL_RANGE);
u32 doorbell_range = RREG32(reg);
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index 6dd0adb78c3a..860c69cccf94 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -53,6 +53,7 @@
#include "navi10_ih.h"
#include "gfx_v10_0.h"
#include "sdma_v5_0.h"
+#include "sdma_v5_2.h"
#include "vcn_v2_0.h"
#include "jpeg_v2_0.h"
#include "dce_virtual.h"
@@ -488,6 +489,7 @@ int nv_set_ip_blocks(struct amdgpu_device *adev)
amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
+ amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block);
break;
default:
return -EINVAL;
@@ -566,6 +568,8 @@ static void nv_init_doorbell_index(struct amdgpu_device *adev)
adev->doorbell_index.gfx_ring1 = AMDGPU_NAVI10_DOORBELL_GFX_RING1;
adev->doorbell_index.sdma_engine[0] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0;
adev->doorbell_index.sdma_engine[1] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1;
+ adev->doorbell_index.sdma_engine[2] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE2;
+ adev->doorbell_index.sdma_engine[3] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE3;
adev->doorbell_index.ih = AMDGPU_NAVI10_DOORBELL_IH;
adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_NAVI10_DOORBELL64_VCN0_1;
adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_NAVI10_DOORBELL64_VCN2_3;
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_common.h b/drivers/gpu/drm/amd/amdgpu/sdma_common.h
new file mode 100644
index 000000000000..8629ef7e8ad9
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_common.h
@@ -0,0 +1,42 @@
+/*
+ * Copyright 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef __SDMA_COMMON_H__
+#define __SDMA_COMMON_H__
+
+enum sdma_utcl2_cache_read_policy {
+ CACHE_READ_POLICY_L2__LRU = 0x00000000,
+ CACHE_READ_POLICY_L2__STREAM = 0x00000001,
+ CACHE_READ_POLICY_L2__NOA = 0x00000002,
+ CACHE_READ_POLICY_L2__DEFAULT = CACHE_READ_POLICY_L2__NOA,
+};
+
+enum sdma_utcl2_cache_write_policy {
+ CACHE_WRITE_POLICY_L2__LRU = 0x00000000,
+ CACHE_WRITE_POLICY_L2__STREAM = 0x00000001,
+ CACHE_WRITE_POLICY_L2__NOA = 0x00000002,
+ CACHE_WRITE_POLICY_L2__BYPASS = 0x00000003,
+ CACHE_WRITE_POLICY_L2__DEFAULT = CACHE_WRITE_POLICY_L2__BYPASS,
+};
+
+#endif /* __SDMA_COMMON_H__ */
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
index b544baf306f2..58d2a80af450 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
@@ -40,6 +40,7 @@
#include "soc15.h"
#include "navi10_sdma_pkt_open.h"
#include "nbio_v2_3.h"
+#include "sdma_common.h"
#include "sdma_v5_0.h"
MODULE_FIRMWARE("amdgpu/navi10_sdma.bin");
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.h b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.h
index d5a94e3d181c..d4e3c2e696f6 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.h
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.h
@@ -24,21 +24,6 @@
#ifndef __SDMA_V5_0_H__
#define __SDMA_V5_0_H__
-enum sdma_v5_0_utcl2_cache_read_policy {
- CACHE_READ_POLICY_L2__LRU = 0x00000000,
- CACHE_READ_POLICY_L2__STREAM = 0x00000001,
- CACHE_READ_POLICY_L2__NOA = 0x00000002,
- CACHE_READ_POLICY_L2__DEFAULT = CACHE_READ_POLICY_L2__NOA,
-};
-
-enum sdma_v5_0_utcl2_cache_write_policy {
- CACHE_WRITE_POLICY_L2__LRU = 0x00000000,
- CACHE_WRITE_POLICY_L2__STREAM = 0x00000001,
- CACHE_WRITE_POLICY_L2__NOA = 0x00000002,
- CACHE_WRITE_POLICY_L2__BYPASS = 0x00000003,
- CACHE_WRITE_POLICY_L2__DEFAULT = CACHE_WRITE_POLICY_L2__BYPASS,
-};
-
extern const struct amd_ip_funcs sdma_v5_0_ip_funcs;
extern const struct amdgpu_ip_block_version sdma_v5_0_ip_block;
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
new file mode 100644
index 000000000000..b9b218ba01ba
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
@@ -0,0 +1,1715 @@
+/*
+ * Copyright 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#include <linux/delay.h>
+#include <linux/firmware.h>
+#include <linux/module.h>
+#include <linux/pci.h>
+
+#include "amdgpu.h"
+#include "amdgpu_ucode.h"
+#include "amdgpu_trace.h"
+
+#include "gc/gc_10_3_0_offset.h"
+#include "gc/gc_10_3_0_sh_mask.h"
+#include "ivsrcid/sdma0/irqsrcs_sdma0_5_0.h"
+#include "ivsrcid/sdma1/irqsrcs_sdma1_5_0.h"
+#include "ivsrcid/sdma2/irqsrcs_sdma2_5_0.h"
+#include "ivsrcid/sdma3/irqsrcs_sdma3_5_0.h"
+
+#include "soc15_common.h"
+#include "soc15.h"
+#include "navi10_sdma_pkt_open.h"
+#include "nbio_v2_3.h"
+#include "sdma_common.h"
+#include "sdma_v5_2.h"
+
+MODULE_FIRMWARE("amdgpu/sienna_cichlid_sdma.bin");
+MODULE_FIRMWARE("amdgpu/sienna_cichlid_sdma1.bin");
+MODULE_FIRMWARE("amdgpu/sienna_cichlid_sdma2.bin");
+MODULE_FIRMWARE("amdgpu/sienna_cichlid_sdma3.bin");
+
+#define SDMA1_REG_OFFSET 0x600
+#define SDMA3_REG_OFFSET 0x400
+#define SDMA0_HYP_DEC_REG_START 0x5880
+#define SDMA0_HYP_DEC_REG_END 0x5893
+#define SDMA1_HYP_DEC_REG_OFFSET 0x20
+
+static void sdma_v5_2_set_ring_funcs(struct amdgpu_device *adev);
+static void sdma_v5_2_set_buffer_funcs(struct amdgpu_device *adev);
+static void sdma_v5_2_set_vm_pte_funcs(struct amdgpu_device *adev);
+static void sdma_v5_2_set_irq_funcs(struct amdgpu_device *adev);
+
+static u32 sdma_v5_2_get_reg_offset(struct amdgpu_device *adev, u32 instance, u32 internal_offset)
+{
+ u32 base;
+
+ if (internal_offset >= SDMA0_HYP_DEC_REG_START &&
+ internal_offset <= SDMA0_HYP_DEC_REG_END) {
+ base = adev->reg_offset[GC_HWIP][0][1];
+ if (instance != 0)
+ internal_offset += SDMA1_HYP_DEC_REG_OFFSET * instance;
+ } else {
+ if (instance < 2) {
+ base = adev->reg_offset[GC_HWIP][0][0];
+ if (instance == 1)
+ internal_offset += SDMA1_REG_OFFSET;
+ } else {
+ base = adev->reg_offset[GC_HWIP][0][2];
+ if (instance == 3)
+ internal_offset += SDMA3_REG_OFFSET;
+ }
+ }
+
+ return base + internal_offset;
+}
+
+static void sdma_v5_2_init_golden_registers(struct amdgpu_device *adev)
+{
+ switch (adev->asic_type) {
+ case CHIP_SIENNA_CICHLID:
+ break;
+ default:
+ break;
+ }
+}
+
+/**
+ * sdma_v5_2_init_microcode - load ucode images from disk
+ *
+ * @adev: amdgpu_device pointer
+ *
+ * Use the firmware interface to load the ucode images into
+ * the driver (not loaded into hw).
+ * Returns 0 on success, error on failure.
+ */
+
+// emulation only, won't work on real chip
+// navi10 real chip need to use PSP to load firmware
+static int sdma_v5_2_init_microcode(struct amdgpu_device *adev)
+{
+ const char *chip_name;
+ char fw_name[40];
+ int err = 0, i;
+ struct amdgpu_firmware_info *info = NULL;
+ const struct common_firmware_header *header = NULL;
+ const struct sdma_firmware_header_v1_0 *hdr;
+
+ DRM_DEBUG("\n");
+
+ switch (adev->asic_type) {
+ case CHIP_SIENNA_CICHLID:
+ chip_name = "sienna_cichlid";
+ break;
+ default:
+ BUG();
+ }
+
+ for (i = 0; i < adev->sdma.num_instances; i++) {
+ if (i == 0)
+ snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name);
+ else
+ snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma%d.bin", chip_name, i);
+ err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev);
+ if (err)
+ goto out;
+ err = amdgpu_ucode_validate(adev->sdma.instance[i].fw);
+ if (err)
+ goto out;
+ hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
+ adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
+ adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version);
+ if (adev->sdma.instance[i].feature_version >= 20)
+ adev->sdma.instance[i].burst_nop = true;
+ DRM_DEBUG("psp_load == '%s'\n",
+ adev->firmware.load_type == AMDGPU_FW_LOAD_PSP ? "true" : "false");
+
+ if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
+ info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
+ info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i;
+ info->fw = adev->sdma.instance[i].fw;
+ header = (const struct common_firmware_header *)info->fw->data;
+ adev->firmware.fw_size +=
+ ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
+ }
+ }
+out:
+ if (err) {
+ DRM_ERROR("sdma_v5_2: Failed to load firmware \"%s\"\n", fw_name);
+ for (i = 0; i < adev->sdma.num_instances; i++) {
+ release_firmware(adev->sdma.instance[i].fw);
+ adev->sdma.instance[i].fw = NULL;
+ }
+ }
+ return err;
+}
+
+static unsigned sdma_v5_2_ring_init_cond_exec(struct amdgpu_ring *ring)
+{
+ unsigned ret;
+
+ amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_COND_EXE));
+ amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
+ amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
+ amdgpu_ring_write(ring, 1);
+ ret = ring->wptr & ring->buf_mask;/* this is the offset we need patch later */
+ amdgpu_ring_write(ring, 0x55aa55aa);/* insert dummy here and patch it later */
+
+ return ret;
+}
+
+static void sdma_v5_2_ring_patch_cond_exec(struct amdgpu_ring *ring,
+ unsigned offset)
+{
+ unsigned cur;
+
+ BUG_ON(offset > ring->buf_mask);
+ BUG_ON(ring->ring[offset] != 0x55aa55aa);
+
+ cur = (ring->wptr - 1) & ring->buf_mask;
+ if (cur > offset)
+ ring->ring[offset] = cur - offset;
+ else
+ ring->ring[offset] = (ring->buf_mask + 1) - offset + cur;
+}
+
+/**
+ * sdma_v5_2_ring_get_rptr - get the current read pointer
+ *
+ * @ring: amdgpu ring pointer
+ *
+ * Get the current rptr from the hardware (NAVI10+).
+ */
+static uint64_t sdma_v5_2_ring_get_rptr(struct amdgpu_ring *ring)
+{
+ u64 *rptr;
+
+ /* XXX check if swapping is necessary on BE */
+ rptr = ((u64 *)&ring->adev->wb.wb[ring->rptr_offs]);
+
+ DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr);
+ return ((*rptr) >> 2);
+}
+
+/**
+ * sdma_v5_2_ring_get_wptr - get the current write pointer
+ *
+ * @ring: amdgpu ring pointer
+ *
+ * Get the current wptr from the hardware (NAVI10+).
+ */
+static uint64_t sdma_v5_2_ring_get_wptr(struct amdgpu_ring *ring)
+{
+ struct amdgpu_device *adev = ring->adev;
+ u64 *wptr = NULL;
+ uint64_t local_wptr = 0;
+
+ if (ring->use_doorbell) {
+ /* XXX check if swapping is necessary on BE */
+ wptr = ((u64 *)&adev->wb.wb[ring->wptr_offs]);
+ DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", *wptr);
+ *wptr = (*wptr) >> 2;
+ DRM_DEBUG("wptr/doorbell after shift == 0x%016llx\n", *wptr);
+ } else {
+ u32 lowbit, highbit;
+
+ wptr = &local_wptr;
+ lowbit = RREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR)) >> 2;
+ highbit = RREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI)) >> 2;
+
+ DRM_DEBUG("wptr [%i]high== 0x%08x low==0x%08x\n",
+ ring->me, highbit, lowbit);
+ *wptr = highbit;
+ *wptr = (*wptr) << 32;
+ *wptr |= lowbit;
+ }
+
+ return *wptr;
+}
+
+/**
+ * sdma_v5_2_ring_set_wptr - commit the write pointer
+ *
+ * @ring: amdgpu ring pointer
+ *
+ * Write the wptr back to the hardware (NAVI10+).
+ */
+static void sdma_v5_2_ring_set_wptr(struct amdgpu_ring *ring)
+{
+ struct amdgpu_device *adev = ring->adev;
+
+ DRM_DEBUG("Setting write pointer\n");
+ if (ring->use_doorbell) {
+ DRM_DEBUG("Using doorbell -- "
+ "wptr_offs == 0x%08x "
+ "lower_32_bits(ring->wptr) << 2 == 0x%08x "
+ "upper_32_bits(ring->wptr) << 2 == 0x%08x\n",
+ ring->wptr_offs,
+ lower_32_bits(ring->wptr << 2),
+ upper_32_bits(ring->wptr << 2));
+ /* XXX check if swapping is necessary on BE */
+ adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr << 2);
+ adev->wb.wb[ring->wptr_offs + 1] = upper_32_bits(ring->wptr << 2);
+ DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
+ ring->doorbell_index, ring->wptr << 2);
+ WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
+ } else {
+ DRM_DEBUG("Not using doorbell -- "
+ "mmSDMA%i_GFX_RB_WPTR == 0x%08x "
+ "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n",
+ ring->me,
+ lower_32_bits(ring->wptr << 2),
+ ring->me,
+ upper_32_bits(ring->wptr << 2));
+ WREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR),
+ lower_32_bits(ring->wptr << 2));
+ WREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI),
+ upper_32_bits(ring->wptr << 2));
+ }
+}
+
+static void sdma_v5_2_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
+{
+ struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
+ int i;
+
+ for (i = 0; i < count; i++)
+ if (sdma && sdma->burst_nop && (i == 0))
+ amdgpu_ring_write(ring, ring->funcs->nop |
+ SDMA_PKT_NOP_HEADER_COUNT(count - 1));
+ else
+ amdgpu_ring_write(ring, ring->funcs->nop);
+}
+
+/**
+ * sdma_v5_2_ring_emit_ib - Schedule an IB on the DMA engine
+ *
+ * @ring: amdgpu ring pointer
+ * @ib: IB object to schedule
+ *
+ * Schedule an IB in the DMA ring.
+ */
+static void sdma_v5_2_ring_emit_ib(struct amdgpu_ring *ring,
+ struct amdgpu_job *job,
+ struct amdgpu_ib *ib,
+ uint32_t flags)
+{
+ unsigned vmid = AMDGPU_JOB_GET_VMID(job);
+ uint64_t csa_mc_addr = amdgpu_sdma_get_csa_mc_addr(ring, vmid);
+
+ /* An IB packet must end on a 8 DW boundary--the next dword
+ * must be on a 8-dword boundary. Our IB packet below is 6
+ * dwords long, thus add x number of NOPs, such that, in
+ * modular arithmetic,
+ * wptr + 6 + x = 8k, k >= 0, which in C is,
+ * (wptr + 6 + x) % 8 = 0.
+ * The expression below, is a solution of x.
+ */
+ sdma_v5_2_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7);
+
+ amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
+ SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf));
+ /* base must be 32 byte aligned */
+ amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
+ amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
+ amdgpu_ring_write(ring, ib->length_dw);
+ amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr));
+ amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr));
+}
+
+/**
+ * sdma_v5_2_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
+ *
+ * @ring: amdgpu ring pointer
+ *
+ * Emit an hdp flush packet on the requested DMA ring.
+ */
+static void sdma_v5_2_ring_emit_hdp_flush(struct amdgpu_ring *ring)
+{
+ struct amdgpu_device *adev = ring->adev;
+ u32 ref_and_mask = 0;
+ const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
+
+ if (ring->me == 0)
+ ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0;
+ else
+ ref_and_mask = nbio_hf_reg->ref_and_mask_sdma1;
+
+ amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
+ SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
+ SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
+ amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_done_offset(adev)) << 2);
+ amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_req_offset(adev)) << 2);
+ amdgpu_ring_write(ring, ref_and_mask); /* reference */
+ amdgpu_ring_write(ring, ref_and_mask); /* mask */
+ amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
+ SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
+}
+
+/**
+ * sdma_v5_2_ring_emit_fence - emit a fence on the DMA ring
+ *
+ * @ring: amdgpu ring pointer
+ * @fence: amdgpu fence object
+ *
+ * Add a DMA fence packet to the ring to write
+ * the fence seq number and DMA trap packet to generate
+ * an interrupt if needed.
+ */
+static void sdma_v5_2_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
+ unsigned flags)
+{
+ struct amdgpu_device *adev = ring->adev;
+ bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
+ /* write the fence */
+ amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) |
+ SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); /* Ucached(UC) */
+ /* zero in first two bits */
+ BUG_ON(addr & 0x3);
+ amdgpu_ring_write(ring, lower_32_bits(addr));
+ amdgpu_ring_write(ring, upper_32_bits(addr));
+ amdgpu_ring_write(ring, lower_32_bits(seq));
+
+ /* optionally write high bits as well */
+ if (write64bit) {
+ addr += 4;
+ amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) |
+ SDMA_PKT_FENCE_HEADER_MTYPE(0x3));
+ /* zero in first two bits */
+ BUG_ON(addr & 0x3);
+ amdgpu_ring_write(ring, lower_32_bits(addr));
+ amdgpu_ring_write(ring, upper_32_bits(addr));
+ amdgpu_ring_write(ring, upper_32_bits(seq));
+ }
+
+ /* Interrupt not work fine on GFX10.1 model yet. Use fallback instead */
+ if ((flags & AMDGPU_FENCE_FLAG_INT) && adev->pdev->device != 0x50) {
+ /* generate an interrupt */
+ amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
+ amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
+ }
+}
+
+
+/**
+ * sdma_v5_2_gfx_stop - stop the gfx async dma engines
+ *
+ * @adev: amdgpu_device pointer
+ *
+ * Stop the gfx async dma ring buffers.
+ */
+static void sdma_v5_2_gfx_stop(struct amdgpu_device *adev)
+{
+ struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring;
+ struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring;
+ struct amdgpu_ring *sdma2 = &adev->sdma.instance[2].ring;
+ struct amdgpu_ring *sdma3 = &adev->sdma.instance[3].ring;
+ u32 rb_cntl, ib_cntl;
+ int i;
+
+ if ((adev->mman.buffer_funcs_ring == sdma0) ||
+ (adev->mman.buffer_funcs_ring == sdma1) ||
+ (adev->mman.buffer_funcs_ring == sdma2) ||
+ (adev->mman.buffer_funcs_ring == sdma3))
+ amdgpu_ttm_set_buffer_funcs_status(adev, false);
+
+ for (i = 0; i < adev->sdma.num_instances; i++) {
+ rb_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
+ rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
+ WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
+ ib_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
+ ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
+ WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
+ }
+
+ sdma0->sched.ready = false;
+ sdma1->sched.ready = false;
+ sdma2->sched.ready = false;
+ sdma3->sched.ready = false;
+}
+
+/**
+ * sdma_v5_2_rlc_stop - stop the compute async dma engines
+ *
+ * @adev: amdgpu_device pointer
+ *
+ * Stop the compute async dma queues.
+ */
+static void sdma_v5_2_rlc_stop(struct amdgpu_device *adev)
+{
+ /* XXX todo */
+}
+
+/**
+ * sdma_v_0_ctx_switch_enable - stop the async dma engines context switch
+ *
+ * @adev: amdgpu_device pointer
+ * @enable: enable/disable the DMA MEs context switch.
+ *
+ * Halt or unhalt the async dma engines context switch.
+ */
+static void sdma_v5_2_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
+{
+ u32 f32_cntl, phase_quantum = 0;
+ int i;
+
+ if (amdgpu_sdma_phase_quantum) {
+ unsigned value = amdgpu_sdma_phase_quantum;
+ unsigned unit = 0;
+
+ while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
+ SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) {
+ value = (value + 1) >> 1;
+ unit++;
+ }
+ if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
+ SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) {
+ value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
+ SDMA0_PHASE0_QUANTUM__VALUE__SHIFT);
+ unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
+ SDMA0_PHASE0_QUANTUM__UNIT__SHIFT);
+ WARN_ONCE(1,
+ "clamping sdma_phase_quantum to %uK clock cycles\n",
+ value << unit);
+ }
+ phase_quantum =
+ value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT |
+ unit << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT;
+ }
+
+ for (i = 0; i < adev->sdma.num_instances; i++) {
+ f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL));
+ f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
+ AUTO_CTXSW_ENABLE, enable ? 1 : 0);
+ if (enable && amdgpu_sdma_phase_quantum) {
+ WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM),
+ phase_quantum);
+ WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE1_QUANTUM),
+ phase_quantum);
+ WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM),
+ phase_quantum);
+ }
+ WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl);
+ }
+
+}
+
+/**
+ * sdma_v5_2_enable - stop the async dma engines
+ *
+ * @adev: amdgpu_device pointer
+ * @enable: enable/disable the DMA MEs.
+ *
+ * Halt or unhalt the async dma engines.
+ */
+static void sdma_v5_2_enable(struct amdgpu_device *adev, bool enable)
+{
+ u32 f32_cntl;
+ int i;
+
+ if (enable == false) {
+ sdma_v5_2_gfx_stop(adev);
+ sdma_v5_2_rlc_stop(adev);
+ }
+
+ for (i = 0; i < adev->sdma.num_instances; i++) {
+ f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
+ f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1);
+ WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl);
+ }
+}
+
+/**
+ * sdma_v5_2_gfx_resume - setup and start the async dma engines
+ *
+ * @adev: amdgpu_device pointer
+ *
+ * Set up the gfx DMA ring buffers and enable them.
+ * Returns 0 for success, error for failure.
+ */
+static int sdma_v5_2_gfx_resume(struct amdgpu_device *adev)
+{
+ struct amdgpu_ring *ring;
+ u32 rb_cntl, ib_cntl;
+ u32 rb_bufsz;
+ u32 wb_offset;
+ u32 doorbell;
+ u32 doorbell_offset;
+ u32 temp;
+ u32 wptr_poll_cntl;
+ u64 wptr_gpu_addr;
+ int i, r;
+
+ for (i = 0; i < adev->sdma.num_instances; i++) {
+ ring = &adev->sdma.instance[i].ring;
+ wb_offset = (ring->rptr_offs * 4);
+
+ WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0);
+
+ /* Set ring buffer size in dwords */
+ rb_bufsz = order_base_2(ring->ring_size / 4);
+ rb_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
+ rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
+#ifdef __BIG_ENDIAN
+ rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
+ rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
+ RPTR_WRITEBACK_SWAP_ENABLE, 1);
+#endif
+ WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
+
+ /* Initialize the ring buffer's read and write pointers */
+ WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0);
+ WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0);
+ WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0);
+ WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0);
+
+ /* setup the wptr shadow polling */
+ wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
+ WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO),
+ lower_32_bits(wptr_gpu_addr));
+ WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI),
+ upper_32_bits(wptr_gpu_addr));
+ wptr_poll_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i,
+ mmSDMA0_GFX_RB_WPTR_POLL_CNTL));
+ wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
+ SDMA0_GFX_RB_WPTR_POLL_CNTL,
+ F32_POLL_ENABLE, 1);
+ WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL),
+ wptr_poll_cntl);
+
+ /* set the wb address whether it's enabled or not */
+ WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI),
+ upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
+ WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO),
+ lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
+
+ rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
+
+ WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE), ring->gpu_addr >> 8);
+ WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI), ring->gpu_addr >> 40);
+
+ ring->wptr = 0;
+
+ /* before programing wptr to a less value, need set minor_ptr_update first */
+ WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1);
+
+ if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */
+ WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr) << 2);
+ WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2);
+ }
+
+ doorbell = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL));
+ doorbell_offset = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET));
+
+ if (ring->use_doorbell) {
+ doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1);
+ doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_GFX_DOORBELL_OFFSET,
+ OFFSET, ring->doorbell_index);
+ } else {
+ doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0);
+ }
+ WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL), doorbell);
+ WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET), doorbell_offset);
+
+ adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell,
+ ring->doorbell_index, 20);
+
+ if (amdgpu_sriov_vf(adev))
+ sdma_v5_2_ring_set_wptr(ring);
+
+ /* set minor_ptr_update to 0 after wptr programed */
+ WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0);
+
+ /* set utc l1 enable flag always to 1 */
+ temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL));
+ temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1);
+
+ /* enable MCBP */
+ temp = REG_SET_FIELD(temp, SDMA0_CNTL, MIDCMD_PREEMPT_ENABLE, 1);
+ WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), temp);
+
+ /* Set up RESP_MODE to non-copy addresses */
+ temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL));
+ temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3);
+ temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9);
+ WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL), temp);
+
+ /* program default cache read and write policy */
+ temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE));
+ /* clean read policy and write policy bits */
+ temp &= 0xFF0FFF;
+ temp |= ((CACHE_READ_POLICY_L2__DEFAULT << 12) |
+ (CACHE_WRITE_POLICY_L2__DEFAULT << 14) |
+ 0x01000000);
+ WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE), temp);
+
+ if (!amdgpu_sriov_vf(adev)) {
+ /* unhalt engine */
+ temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
+ temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0);
+ WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), temp);
+ }
+
+ /* enable DMA RB */
+ rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
+ WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
+
+ ib_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
+ ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
+#ifdef __BIG_ENDIAN
+ ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
+#endif
+ /* enable DMA IBs */
+ WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
+
+ ring->sched.ready = true;
+
+ if (amdgpu_sriov_vf(adev)) { /* bare-metal sequence doesn't need below to lines */
+ sdma_v5_2_ctx_switch_enable(adev, true);
+ sdma_v5_2_enable(adev, true);
+ }
+
+ r = amdgpu_ring_test_ring(ring);
+ if (r) {
+ ring->sched.ready = false;
+ return r;
+ }
+
+ if (adev->mman.buffer_funcs_ring == ring)
+ amdgpu_ttm_set_buffer_funcs_status(adev, true);
+ }
+
+ return 0;
+}
+
+/**
+ * sdma_v5_2_rlc_resume - setup and start the async dma engines
+ *
+ * @adev: amdgpu_device pointer
+ *
+ * Set up the compute DMA queues and enable them.
+ * Returns 0 for success, error for failure.
+ */
+static int sdma_v5_2_rlc_resume(struct amdgpu_device *adev)
+{
+ return 0;
+}
+
+/**
+ * sdma_v5_2_load_microcode - load the sDMA ME ucode
+ *
+ * @adev: amdgpu_device pointer
+ *
+ * Loads the sDMA0/1/2/3 ucode.
+ * Returns 0 for success, -EINVAL if the ucode is not available.
+ */
+static int sdma_v5_2_load_microcode(struct amdgpu_device *adev)
+{
+ const struct sdma_firmware_header_v1_0 *hdr;
+ const __le32 *fw_data;
+ u32 fw_size;
+ int i, j;
+
+ /* halt the MEs */
+ sdma_v5_2_enable(adev, false);
+
+ for (i = 0; i < adev->sdma.num_instances; i++) {
+ if (!adev->sdma.instance[i].fw)
+ return -EINVAL;
+
+ hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
+ amdgpu_ucode_print_sdma_hdr(&hdr->header);
+ fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
+
+ fw_data = (const __le32 *)
+ (adev->sdma.instance[i].fw->data +
+ le32_to_cpu(hdr->header.ucode_array_offset_bytes));
+
+ WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), 0);
+
+ for (j = 0; j < fw_size; j++) {
+ if (amdgpu_emu_mode == 1 && j % 500 == 0)
+ msleep(1);
+ WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UCODE_DATA), le32_to_cpup(fw_data++));
+ }
+
+ WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), adev->sdma.instance[i].fw_version);
+ }
+
+ return 0;
+}
+
+/**
+ * sdma_v5_2_start - setup and start the async dma engines
+ *
+ * @adev: amdgpu_device pointer
+ *
+ * Set up the DMA engines and enable them.
+ * Returns 0 for success, error for failure.
+ */
+static int sdma_v5_2_start(struct amdgpu_device *adev)
+{
+ int r = 0;
+
+ if (amdgpu_sriov_vf(adev)) {
+ sdma_v5_2_ctx_switch_enable(adev, false);
+ sdma_v5_2_enable(adev, false);
+
+ /* set RB registers */
+ r = sdma_v5_2_gfx_resume(adev);
+ return r;
+ }
+
+ if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
+ r = sdma_v5_2_load_microcode(adev);
+ if (r)
+ return r;
+
+ /* The value of mmSDMA_F32_CNTL is invalid the moment after loading fw */
+ if (amdgpu_emu_mode == 1)
+ msleep(1000);
+ }
+
+ /* unhalt the MEs */
+ sdma_v5_2_enable(adev, true);
+ /* enable sdma ring preemption */
+ sdma_v5_2_ctx_switch_enable(adev, true);
+
+ /* start the gfx rings and rlc compute queues */
+ r = sdma_v5_2_gfx_resume(adev);
+ if (r)
+ return r;
+ r = sdma_v5_2_rlc_resume(adev);
+
+ return r;
+}
+
+/**
+ * sdma_v5_2_ring_test_ring - simple async dma engine test
+ *
+ * @ring: amdgpu_ring structure holding ring information
+ *
+ * Test the DMA engine by writing using it to write an
+ * value to memory.
+ * Returns 0 for success, error for failure.
+ */
+static int sdma_v5_2_ring_test_ring(struct amdgpu_ring *ring)
+{
+ struct amdgpu_device *adev = ring->adev;
+ unsigned i;
+ unsigned index;
+ int r;
+ u32 tmp;
+ u64 gpu_addr;
+
+ r = amdgpu_device_wb_get(adev, &index);
+ if (r) {
+ dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
+ return r;
+ }
+
+ gpu_addr = adev->wb.gpu_addr + (index * 4);
+ tmp = 0xCAFEDEAD;
+ adev->wb.wb[index] = cpu_to_le32(tmp);
+
+ r = amdgpu_ring_alloc(ring, 5);
+ if (r) {
+ DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
+ amdgpu_device_wb_free(adev, index);
+ return r;
+ }
+
+ amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
+ SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
+ amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
+ amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
+ amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0));
+ amdgpu_ring_write(ring, 0xDEADBEEF);
+ amdgpu_ring_commit(ring);
+
+ for (i = 0; i < adev->usec_timeout; i++) {
+ tmp = le32_to_cpu(adev->wb.wb[index]);
+ if (tmp == 0xDEADBEEF)
+ break;
+ if (amdgpu_emu_mode == 1)
+ msleep(1);
+ else
+ udelay(1);
+ }
+
+ if (i >= adev->usec_timeout)
+ r = -ETIMEDOUT;
+
+ amdgpu_device_wb_free(adev, index);
+
+ return r;
+}
+
+/**
+ * sdma_v5_2_ring_test_ib - test an IB on the DMA engine
+ *
+ * @ring: amdgpu_ring structure holding ring information
+ *
+ * Test a simple IB in the DMA ring.
+ * Returns 0 on success, error on failure.
+ */
+static int sdma_v5_2_ring_test_ib(struct amdgpu_ring *ring, long timeout)
+{
+ struct amdgpu_device *adev = ring->adev;
+ struct amdgpu_ib ib;
+ struct dma_fence *f = NULL;
+ unsigned index;
+ long r;
+ u32 tmp = 0;
+ u64 gpu_addr;
+
+ r = amdgpu_device_wb_get(adev, &index);
+ if (r) {
+ dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r);
+ return r;
+ }
+
+ gpu_addr = adev->wb.gpu_addr + (index * 4);
+ tmp = 0xCAFEDEAD;
+ adev->wb.wb[index] = cpu_to_le32(tmp);
+ memset(&ib, 0, sizeof(ib));
+ r = amdgpu_ib_get(adev, NULL, 256, AMDGPU_IB_POOL_DIRECT, &ib);
+ if (r) {
+ DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
+ goto err0;
+ }
+
+ ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
+ SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
+ ib.ptr[1] = lower_32_bits(gpu_addr);
+ ib.ptr[2] = upper_32_bits(gpu_addr);
+ ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0);
+ ib.ptr[4] = 0xDEADBEEF;
+ ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
+ ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
+ ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
+ ib.length_dw = 8;
+
+ r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
+ if (r)
+ goto err1;
+
+ r = dma_fence_wait_timeout(f, false, timeout);
+ if (r == 0) {
+ DRM_ERROR("amdgpu: IB test timed out\n");
+ r = -ETIMEDOUT;
+ goto err1;
+ } else if (r < 0) {
+ DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
+ goto err1;
+ }
+ tmp = le32_to_cpu(adev->wb.wb[index]);
+ if (tmp == 0xDEADBEEF)
+ r = 0;
+ else
+ r = -EINVAL;
+
+err1:
+ amdgpu_ib_free(adev, &ib, NULL);
+ dma_fence_put(f);
+err0:
+ amdgpu_device_wb_free(adev, index);
+ return r;
+}
+
+
+/**
+ * sdma_v5_2_vm_copy_pte - update PTEs by copying them from the GART
+ *
+ * @ib: indirect buffer to fill with commands
+ * @pe: addr of the page entry
+ * @src: src addr to copy from
+ * @count: number of page entries to update
+ *
+ * Update PTEs by copying them from the GART using sDMA.
+ */
+static void sdma_v5_2_vm_copy_pte(struct amdgpu_ib *ib,
+ uint64_t pe, uint64_t src,
+ unsigned count)
+{
+ unsigned bytes = count * 8;
+
+ ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
+ SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
+ ib->ptr[ib->length_dw++] = bytes - 1;
+ ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
+ ib->ptr[ib->length_dw++] = lower_32_bits(src);
+ ib->ptr[ib->length_dw++] = upper_32_bits(src);
+ ib->ptr[ib->length_dw++] = lower_32_bits(pe);
+ ib->ptr[ib->length_dw++] = upper_32_bits(pe);
+
+}
+
+/**
+ * sdma_v5_2_vm_write_pte - update PTEs by writing them manually
+ *
+ * @ib: indirect buffer to fill with commands
+ * @pe: addr of the page entry
+ * @addr: dst addr to write into pe
+ * @count: number of page entries to update
+ * @incr: increase next addr by incr bytes
+ * @flags: access flags
+ *
+ * Update PTEs by writing them manually using sDMA.
+ */
+static void sdma_v5_2_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
+ uint64_t value, unsigned count,
+ uint32_t incr)
+{
+ unsigned ndw = count * 2;
+
+ ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
+ SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
+ ib->ptr[ib->length_dw++] = lower_32_bits(pe);
+ ib->ptr[ib->length_dw++] = upper_32_bits(pe);
+ ib->ptr[ib->length_dw++] = ndw - 1;
+ for (; ndw > 0; ndw -= 2) {
+ ib->ptr[ib->length_dw++] = lower_32_bits(value);
+ ib->ptr[ib->length_dw++] = upper_32_bits(value);
+ value += incr;
+ }
+}
+
+/**
+ * sdma_v5_2_vm_set_pte_pde - update the page tables using sDMA
+ *
+ * @ib: indirect buffer to fill with commands
+ * @pe: addr of the page entry
+ * @addr: dst addr to write into pe
+ * @count: number of page entries to update
+ * @incr: increase next addr by incr bytes
+ * @flags: access flags
+ *
+ * Update the page tables using sDMA.
+ */
+static void sdma_v5_2_vm_set_pte_pde(struct amdgpu_ib *ib,
+ uint64_t pe,
+ uint64_t addr, unsigned count,
+ uint32_t incr, uint64_t flags)
+{
+ /* for physically contiguous pages (vram) */
+ ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE);
+ ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
+ ib->ptr[ib->length_dw++] = upper_32_bits(pe);
+ ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
+ ib->ptr[ib->length_dw++] = upper_32_bits(flags);
+ ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
+ ib->ptr[ib->length_dw++] = upper_32_bits(addr);
+ ib->ptr[ib->length_dw++] = incr; /* increment size */
+ ib->ptr[ib->length_dw++] = 0;
+ ib->ptr[ib->length_dw++] = count - 1; /* number of entries */
+}
+
+/**
+ * sdma_v5_2_ring_pad_ib - pad the IB
+ *
+ * @ib: indirect buffer to fill with padding
+ *
+ * Pad the IB with NOPs to a boundary multiple of 8.
+ */
+static void sdma_v5_2_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
+{
+ struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
+ u32 pad_count;
+ int i;
+
+ pad_count = (-ib->length_dw) & 0x7;
+ for (i = 0; i < pad_count; i++)
+ if (sdma && sdma->burst_nop && (i == 0))
+ ib->ptr[ib->length_dw++] =
+ SDMA_PKT_HEADER_OP(SDMA_OP_NOP) |
+ SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
+ else
+ ib->ptr[ib->length_dw++] =
+ SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
+}
+
+
+/**
+ * sdma_v5_2_ring_emit_pipeline_sync - sync the pipeline
+ *
+ * @ring: amdgpu_ring pointer
+ *
+ * Make sure all previous operations are completed (CIK).
+ */
+static void sdma_v5_2_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
+{
+ uint32_t seq = ring->fence_drv.sync_seq;
+ uint64_t addr = ring->fence_drv.gpu_addr;
+
+ /* wait for idle */
+ amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
+ SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
+ SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */
+ SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1));
+ amdgpu_ring_write(ring, addr & 0xfffffffc);
+ amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
+ amdgpu_ring_write(ring, seq); /* reference */
+ amdgpu_ring_write(ring, 0xffffffff); /* mask */
+ amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
+ SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */
+}
+
+
+/**
+ * sdma_v5_2_ring_emit_vm_flush - vm flush using sDMA
+ *
+ * @ring: amdgpu_ring pointer
+ * @vm: amdgpu_vm pointer
+ *
+ * Update the page table base and flush the VM TLB
+ * using sDMA.
+ */
+static void sdma_v5_2_ring_emit_vm_flush(struct amdgpu_ring *ring,
+ unsigned vmid, uint64_t pd_addr)
+{
+ amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
+}
+
+static void sdma_v5_2_ring_emit_wreg(struct amdgpu_ring *ring,
+ uint32_t reg, uint32_t val)
+{
+ amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
+ SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
+ amdgpu_ring_write(ring, reg);
+ amdgpu_ring_write(ring, val);
+}
+
+static void sdma_v5_2_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
+ uint32_t val, uint32_t mask)
+{
+ amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
+ SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
+ SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* equal */
+ amdgpu_ring_write(ring, reg << 2);
+ amdgpu_ring_write(ring, 0);
+ amdgpu_ring_write(ring, val); /* reference */
+ amdgpu_ring_write(ring, mask); /* mask */
+ amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
+ SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10));
+}
+
+static void sdma_v5_2_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
+ uint32_t reg0, uint32_t reg1,
+ uint32_t ref, uint32_t mask)
+{
+ amdgpu_ring_emit_wreg(ring, reg0, ref);
+ /* wait for a cycle to reset vm_inv_eng*_ack */
+ amdgpu_ring_emit_reg_wait(ring, reg0, 0, 0);
+ amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask);
+}
+
+static int sdma_v5_2_early_init(void *handle)
+{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
+ adev->sdma.num_instances = 4;
+
+ sdma_v5_2_set_ring_funcs(adev);
+ sdma_v5_2_set_buffer_funcs(adev);
+ sdma_v5_2_set_vm_pte_funcs(adev);
+ sdma_v5_2_set_irq_funcs(adev);
+
+ return 0;
+}
+
+static int sdma_v5_2_sw_init(void *handle)
+{
+ struct amdgpu_ring *ring;
+ int r, i;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
+ /* SDMA trap event */
+ r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA0,
+ SDMA0_5_0__SRCID__SDMA_TRAP,
+ &adev->sdma.trap_irq);
+ if (r)
+ return r;
+
+ /* SDMA trap event */
+ r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA1,
+ SDMA1_5_0__SRCID__SDMA_TRAP,
+ &adev->sdma.trap_irq);
+ if (r)
+ return r;
+
+ /* SDMA trap event */
+ r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA2,
+ SDMA2_5_0__SRCID__SDMA_TRAP,
+ &adev->sdma.trap_irq);
+ if (r)
+ return r;
+
+ /* SDMA trap event */
+ r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA3,
+ SDMA3_5_0__SRCID__SDMA_TRAP,
+ &adev->sdma.trap_irq);
+ if (r)
+ return r;
+
+ r = sdma_v5_2_init_microcode(adev);
+ if (r) {
+ DRM_ERROR("Failed to load sdma firmware!\n");
+ return r;
+ }
+
+ for (i = 0; i < adev->sdma.num_instances; i++) {
+ ring = &adev->sdma.instance[i].ring;
+ ring->ring_obj = NULL;
+ ring->use_doorbell = true;
+
+ DRM_INFO("use_doorbell being set to: [%s]\n",
+ ring->use_doorbell?"true":"false");
+
+ ring->doorbell_index =
+ (adev->doorbell_index.sdma_engine[i] << 1); //get DWORD offset
+
+ sprintf(ring->name, "sdma%d", i);
+ r = amdgpu_ring_init(adev, ring, 1024,
+ &adev->sdma.trap_irq,
+ AMDGPU_SDMA_IRQ_INSTANCE0 + i,
+ AMDGPU_RING_PRIO_DEFAULT);
+ if (r)
+ return r;
+ }
+
+ return r;
+}
+
+static int sdma_v5_2_sw_fini(void *handle)
+{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ int i;
+
+ for (i = 0; i < adev->sdma.num_instances; i++)
+ amdgpu_ring_fini(&adev->sdma.instance[i].ring);
+
+ return 0;
+}
+
+static int sdma_v5_2_hw_init(void *handle)
+{
+ int r;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
+ sdma_v5_2_init_golden_registers(adev);
+
+ r = sdma_v5_2_start(adev);
+
+ return r;
+}
+
+static int sdma_v5_2_hw_fini(void *handle)
+{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
+ if (amdgpu_sriov_vf(adev))
+ return 0;
+
+ sdma_v5_2_ctx_switch_enable(adev, false);
+ sdma_v5_2_enable(adev, false);
+
+ return 0;
+}
+
+static int sdma_v5_2_suspend(void *handle)
+{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
+ return sdma_v5_2_hw_fini(adev);
+}
+
+static int sdma_v5_2_resume(void *handle)
+{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
+ return sdma_v5_2_hw_init(adev);
+}
+
+static bool sdma_v5_2_is_idle(void *handle)
+{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ u32 i;
+
+ for (i = 0; i < adev->sdma.num_instances; i++) {
+ u32 tmp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_STATUS_REG));
+
+ if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK))
+ return false;
+ }
+
+ return true;
+}
+
+static int sdma_v5_2_wait_for_idle(void *handle)
+{
+ unsigned i;
+ u32 sdma0, sdma1, sdma2, sdma3;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
+ for (i = 0; i < adev->usec_timeout; i++) {
+ sdma0 = RREG32(sdma_v5_2_get_reg_offset(adev, 0, mmSDMA0_STATUS_REG));
+ sdma1 = RREG32(sdma_v5_2_get_reg_offset(adev, 1, mmSDMA0_STATUS_REG));
+ sdma2 = RREG32(sdma_v5_2_get_reg_offset(adev, 2, mmSDMA0_STATUS_REG));
+ sdma3 = RREG32(sdma_v5_2_get_reg_offset(adev, 3, mmSDMA0_STATUS_REG));
+
+ if (sdma0 & sdma1 & sdma2 & sdma3 & SDMA0_STATUS_REG__IDLE_MASK)
+ return 0;
+ udelay(1);
+ }
+ return -ETIMEDOUT;
+}
+
+static int sdma_v5_2_soft_reset(void *handle)
+{
+ /* todo */
+
+ return 0;
+}
+
+static int sdma_v5_2_ring_preempt_ib(struct amdgpu_ring *ring)
+{
+ int i, r = 0;
+ struct amdgpu_device *adev = ring->adev;
+ u32 index = 0;
+ u64 sdma_gfx_preempt;
+
+ amdgpu_sdma_get_index_from_ring(ring, &index);
+ sdma_gfx_preempt =
+ sdma_v5_2_get_reg_offset(adev, index, mmSDMA0_GFX_PREEMPT);
+
+ /* assert preemption condition */
+ amdgpu_ring_set_preempt_cond_exec(ring, false);
+
+ /* emit the trailing fence */
+ ring->trail_seq += 1;
+ amdgpu_ring_alloc(ring, 10);
+ sdma_v5_2_ring_emit_fence(ring, ring->trail_fence_gpu_addr,
+ ring->trail_seq, 0);
+ amdgpu_ring_commit(ring);
+
+ /* assert IB preemption */
+ WREG32(sdma_gfx_preempt, 1);
+
+ /* poll the trailing fence */
+ for (i = 0; i < adev->usec_timeout; i++) {
+ if (ring->trail_seq ==
+ le32_to_cpu(*(ring->trail_fence_cpu_addr)))
+ break;
+ udelay(1);
+ }
+
+ if (i >= adev->usec_timeout) {
+ r = -EINVAL;
+ DRM_ERROR("ring %d failed to be preempted\n", ring->idx);
+ }
+
+ /* deassert IB preemption */
+ WREG32(sdma_gfx_preempt, 0);
+
+ /* deassert the preemption condition */
+ amdgpu_ring_set_preempt_cond_exec(ring, true);
+ return r;
+}
+
+static int sdma_v5_2_set_trap_irq_state(struct amdgpu_device *adev,
+ struct amdgpu_irq_src *source,
+ unsigned type,
+ enum amdgpu_interrupt_state state)
+{
+ u32 sdma_cntl;
+
+ u32 reg_offset = sdma_v5_2_get_reg_offset(adev, type, mmSDMA0_CNTL);
+
+ sdma_cntl = RREG32(reg_offset);
+ sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,
+ state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
+ WREG32(reg_offset, sdma_cntl);
+
+ return 0;
+}
+
+static int sdma_v5_2_process_trap_irq(struct amdgpu_device *adev,
+ struct amdgpu_irq_src *source,
+ struct amdgpu_iv_entry *entry)
+{
+ DRM_DEBUG("IH: SDMA trap\n");
+ switch (entry->client_id) {
+ case SOC15_IH_CLIENTID_SDMA0:
+ switch (entry->ring_id) {
+ case 0:
+ amdgpu_fence_process(&adev->sdma.instance[0].ring);
+ break;
+ case 1:
+ /* XXX compute */
+ break;
+ case 2:
+ /* XXX compute */
+ break;
+ case 3:
+ /* XXX page queue*/
+ break;
+ }
+ break;
+ case SOC15_IH_CLIENTID_SDMA1:
+ switch (entry->ring_id) {
+ case 0:
+ amdgpu_fence_process(&adev->sdma.instance[1].ring);
+ break;
+ case 1:
+ /* XXX compute */
+ break;
+ case 2:
+ /* XXX compute */
+ break;
+ case 3:
+ /* XXX page queue*/
+ break;
+ }
+ break;
+ case SOC15_IH_CLIENTID_SDMA2:
+ switch (entry->ring_id) {
+ case 0:
+ amdgpu_fence_process(&adev->sdma.instance[2].ring);
+ break;
+ case 1:
+ /* XXX compute */
+ break;
+ case 2:
+ /* XXX compute */
+ break;
+ case 3:
+ /* XXX page queue*/
+ break;
+ }
+ break;
+ case SOC15_IH_CLIENTID_SDMA3:
+ switch (entry->ring_id) {
+ case 0:
+ amdgpu_fence_process(&adev->sdma.instance[3].ring);
+ break;
+ case 1:
+ /* XXX compute */
+ break;
+ case 2:
+ /* XXX compute */
+ break;
+ case 3:
+ /* XXX page queue*/
+ break;
+ }
+ break;
+ }
+ return 0;
+}
+
+static int sdma_v5_2_process_illegal_inst_irq(struct amdgpu_device *adev,
+ struct amdgpu_irq_src *source,
+ struct amdgpu_iv_entry *entry)
+{
+ return 0;
+}
+
+static void sdma_v5_2_update_medium_grain_clock_gating(struct amdgpu_device *adev,
+ bool enable)
+{
+ uint32_t data, def;
+ int i;
+
+ for (i = 0; i < adev->sdma.num_instances; i++) {
+ if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
+ /* Enable sdma clock gating */
+ def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL));
+ data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
+ SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
+ SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
+ SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
+ SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK |
+ SDMA0_CLK_CTRL__SOFT_OVERRIDER_REG_MASK);
+ if (def != data)
+ WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data);
+ } else {
+ /* Disable sdma clock gating */
+ def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL));
+ data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
+ SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
+ SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
+ SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
+ SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK |
+ SDMA0_CLK_CTRL__SOFT_OVERRIDER_REG_MASK);
+ if (def != data)
+ WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data);
+ }
+ }
+}
+
+static void sdma_v5_2_update_medium_grain_light_sleep(struct amdgpu_device *adev,
+ bool enable)
+{
+ uint32_t data, def;
+ int i;
+
+ for (i = 0; i < adev->sdma.num_instances; i++) {
+ if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
+ /* Enable sdma mem light sleep */
+ def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL));
+ data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
+ if (def != data)
+ WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data);
+
+ } else {
+ /* Disable sdma mem light sleep */
+ def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL));
+ data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
+ if (def != data)
+ WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data);
+
+ }
+ }
+}
+
+static int sdma_v5_2_set_clockgating_state(void *handle,
+ enum amd_clockgating_state state)
+{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
+ if (amdgpu_sriov_vf(adev))
+ return 0;
+
+ switch (adev->asic_type) {
+ case CHIP_SIENNA_CICHLID:
+ sdma_v5_2_update_medium_grain_clock_gating(adev,
+ state == AMD_CG_STATE_GATE ? true : false);
+ sdma_v5_2_update_medium_grain_light_sleep(adev,
+ state == AMD_CG_STATE_GATE ? true : false);
+ break;
+ default:
+ break;
+ }
+
+ return 0;
+}
+
+static int sdma_v5_2_set_powergating_state(void *handle,
+ enum amd_powergating_state state)
+{
+ return 0;
+}
+
+static void sdma_v5_2_get_clockgating_state(void *handle, u32 *flags)
+{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ int data;
+
+ if (amdgpu_sriov_vf(adev))
+ *flags = 0;
+
+ /* AMD_CG_SUPPORT_SDMA_LS */
+ data = RREG32(sdma_v5_2_get_reg_offset(adev, 0, mmSDMA0_POWER_CNTL));
+ if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK)
+ *flags |= AMD_CG_SUPPORT_SDMA_LS;
+}
+
+const struct amd_ip_funcs sdma_v5_2_ip_funcs = {
+ .name = "sdma_v5_2",
+ .early_init = sdma_v5_2_early_init,
+ .late_init = NULL,
+ .sw_init = sdma_v5_2_sw_init,
+ .sw_fini = sdma_v5_2_sw_fini,
+ .hw_init = sdma_v5_2_hw_init,
+ .hw_fini = sdma_v5_2_hw_fini,
+ .suspend = sdma_v5_2_suspend,
+ .resume = sdma_v5_2_resume,
+ .is_idle = sdma_v5_2_is_idle,
+ .wait_for_idle = sdma_v5_2_wait_for_idle,
+ .soft_reset = sdma_v5_2_soft_reset,
+ .set_clockgating_state = sdma_v5_2_set_clockgating_state,
+ .set_powergating_state = sdma_v5_2_set_powergating_state,
+ .get_clockgating_state = sdma_v5_2_get_clockgating_state,
+};
+
+static const struct amdgpu_ring_funcs sdma_v5_2_ring_funcs = {
+ .type = AMDGPU_RING_TYPE_SDMA,
+ .align_mask = 0xf,
+ .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
+ .support_64bit_ptrs = true,
+ .vmhub = AMDGPU_GFXHUB_0,
+ .get_rptr = sdma_v5_2_ring_get_rptr,
+ .get_wptr = sdma_v5_2_ring_get_wptr,
+ .set_wptr = sdma_v5_2_ring_set_wptr,
+ .emit_frame_size =
+ 5 + /* sdma_v5_2_ring_init_cond_exec */
+ 6 + /* sdma_v5_2_ring_emit_hdp_flush */
+ 3 + /* hdp_invalidate */
+ 6 + /* sdma_v5_2_ring_emit_pipeline_sync */
+ /* sdma_v5_2_ring_emit_vm_flush */
+ SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
+ SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 +
+ 10 + 10 + 10, /* sdma_v5_2_ring_emit_fence x3 for user fence, vm fence */
+ .emit_ib_size = 7 + 6, /* sdma_v5_2_ring_emit_ib */
+ .emit_ib = sdma_v5_2_ring_emit_ib,
+ .emit_fence = sdma_v5_2_ring_emit_fence,
+ .emit_pipeline_sync = sdma_v5_2_ring_emit_pipeline_sync,
+ .emit_vm_flush = sdma_v5_2_ring_emit_vm_flush,
+ .emit_hdp_flush = sdma_v5_2_ring_emit_hdp_flush,
+ .test_ring = sdma_v5_2_ring_test_ring,
+ .test_ib = sdma_v5_2_ring_test_ib,
+ .insert_nop = sdma_v5_2_ring_insert_nop,
+ .pad_ib = sdma_v5_2_ring_pad_ib,
+ .emit_wreg = sdma_v5_2_ring_emit_wreg,
+ .emit_reg_wait = sdma_v5_2_ring_emit_reg_wait,
+ .emit_reg_write_reg_wait = sdma_v5_2_ring_emit_reg_write_reg_wait,
+ .init_cond_exec = sdma_v5_2_ring_init_cond_exec,
+ .patch_cond_exec = sdma_v5_2_ring_patch_cond_exec,
+ .preempt_ib = sdma_v5_2_ring_preempt_ib,
+};
+
+static void sdma_v5_2_set_ring_funcs(struct amdgpu_device *adev)
+{
+ int i;
+
+ for (i = 0; i < adev->sdma.num_instances; i++) {
+ adev->sdma.instance[i].ring.funcs = &sdma_v5_2_ring_funcs;
+ adev->sdma.instance[i].ring.me = i;
+ }
+}
+
+static const struct amdgpu_irq_src_funcs sdma_v5_2_trap_irq_funcs = {
+ .set = sdma_v5_2_set_trap_irq_state,
+ .process = sdma_v5_2_process_trap_irq,
+};
+
+static const struct amdgpu_irq_src_funcs sdma_v5_2_illegal_inst_irq_funcs = {
+ .process = sdma_v5_2_process_illegal_inst_irq,
+};
+
+static void sdma_v5_2_set_irq_funcs(struct amdgpu_device *adev)
+{
+ adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE0 +
+ adev->sdma.num_instances;
+ adev->sdma.trap_irq.funcs = &sdma_v5_2_trap_irq_funcs;
+ adev->sdma.illegal_inst_irq.funcs = &sdma_v5_2_illegal_inst_irq_funcs;
+}
+
+/**
+ * sdma_v5_2_emit_copy_buffer - copy buffer using the sDMA engine
+ *
+ * @ring: amdgpu_ring structure holding ring information
+ * @src_offset: src GPU address
+ * @dst_offset: dst GPU address
+ * @byte_count: number of bytes to xfer
+ *
+ * Copy GPU buffers using the DMA engine.
+ * Used by the amdgpu ttm implementation to move pages if
+ * registered as the asic copy callback.
+ */
+static void sdma_v5_2_emit_copy_buffer(struct amdgpu_ib *ib,
+ uint64_t src_offset,
+ uint64_t dst_offset,
+ uint32_t byte_count,
+ bool tmz)
+{
+ ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
+ SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) |
+ SDMA_PKT_COPY_LINEAR_HEADER_TMZ(tmz ? 1 : 0);
+ ib->ptr[ib->length_dw++] = byte_count - 1;
+ ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
+ ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
+ ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
+ ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
+ ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
+}
+
+/**
+ * sdma_v5_2_emit_fill_buffer - fill buffer using the sDMA engine
+ *
+ * @ring: amdgpu_ring structure holding ring information
+ * @src_data: value to write to buffer
+ * @dst_offset: dst GPU address
+ * @byte_count: number of bytes to xfer
+ *
+ * Fill GPU buffers using the DMA engine.
+ */
+static void sdma_v5_2_emit_fill_buffer(struct amdgpu_ib *ib,
+ uint32_t src_data,
+ uint64_t dst_offset,
+ uint32_t byte_count)
+{
+ ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
+ ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
+ ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
+ ib->ptr[ib->length_dw++] = src_data;
+ ib->ptr[ib->length_dw++] = byte_count - 1;
+}
+
+static const struct amdgpu_buffer_funcs sdma_v5_2_buffer_funcs = {
+ .copy_max_bytes = 0x400000,
+ .copy_num_dw = 7,
+ .emit_copy_buffer = sdma_v5_2_emit_copy_buffer,
+
+ .fill_max_bytes = 0x400000,
+ .fill_num_dw = 5,
+ .emit_fill_buffer = sdma_v5_2_emit_fill_buffer,
+};
+
+static void sdma_v5_2_set_buffer_funcs(struct amdgpu_device *adev)
+{
+ if (adev->mman.buffer_funcs == NULL) {
+ adev->mman.buffer_funcs = &sdma_v5_2_buffer_funcs;
+ adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
+ }
+}
+
+static const struct amdgpu_vm_pte_funcs sdma_v5_2_vm_pte_funcs = {
+ .copy_pte_num_dw = 7,
+ .copy_pte = sdma_v5_2_vm_copy_pte,
+ .write_pte = sdma_v5_2_vm_write_pte,
+ .set_pte_pde = sdma_v5_2_vm_set_pte_pde,
+};
+
+static void sdma_v5_2_set_vm_pte_funcs(struct amdgpu_device *adev)
+{
+ unsigned i;
+
+ if (adev->vm_manager.vm_pte_funcs == NULL) {
+ adev->vm_manager.vm_pte_funcs = &sdma_v5_2_vm_pte_funcs;
+ for (i = 0; i < adev->sdma.num_instances; i++) {
+ adev->vm_manager.vm_pte_scheds[i] =
+ &adev->sdma.instance[i].ring.sched;
+ }
+ adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
+ }
+}
+
+const struct amdgpu_ip_block_version sdma_v5_2_ip_block = {
+ .type = AMD_IP_BLOCK_TYPE_SDMA,
+ .major = 5,
+ .minor = 2,
+ .rev = 0,
+ .funcs = &sdma_v5_2_ip_funcs,
+};
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.h b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.h
new file mode 100644
index 000000000000..b70414fef2a1
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.h
@@ -0,0 +1,30 @@
+/*
+ * Copyright 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef __SDMA_V5_2_H__
+#define __SDMA_V5_2_H__
+
+extern const struct amd_ip_funcs sdma_v5_2_ip_funcs;
+extern const struct amdgpu_ip_block_version sdma_v5_2_ip_block;
+
+#endif /* __SDMA_V5_2_H__ */
--
2.25.4
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH 022/207] drm/amdgpu: correct SDMA3 IH clinet id for sienna_cichlid
2020-06-01 17:59 [PATCH 000/207] Add Support for Sienna Cichlid Alex Deucher
` (16 preceding siblings ...)
2020-06-01 17:59 ` [PATCH 021/207] drm/amdgpu: add sdma ip block for sienna_cichlid (v5) Alex Deucher
@ 2020-06-01 17:59 ` Alex Deucher
2020-06-01 17:59 ` [PATCH 023/207] drm/amdgpu/gfx10: change register configure " Alex Deucher
` (64 subsequent siblings)
82 siblings, 0 replies; 88+ messages in thread
From: Alex Deucher @ 2020-06-01 17:59 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Likun Gao, Hawking Zhang
From: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 4 ++--
drivers/gpu/drm/amd/include/soc15_ih_clientid.h | 1 +
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
index b9b218ba01ba..5a47f105cd14 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
@@ -1166,7 +1166,7 @@ static int sdma_v5_2_sw_init(void *handle)
return r;
/* SDMA trap event */
- r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA3,
+ r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA3_Sienna_Cichlid,
SDMA3_5_0__SRCID__SDMA_TRAP,
&adev->sdma.trap_irq);
if (r)
@@ -1408,7 +1408,7 @@ static int sdma_v5_2_process_trap_irq(struct amdgpu_device *adev,
break;
}
break;
- case SOC15_IH_CLIENTID_SDMA3:
+ case SOC15_IH_CLIENTID_SDMA3_Sienna_Cichlid:
switch (entry->ring_id) {
case 0:
amdgpu_fence_process(&adev->sdma.instance[3].ring);
diff --git a/drivers/gpu/drm/amd/include/soc15_ih_clientid.h b/drivers/gpu/drm/amd/include/soc15_ih_clientid.h
index 1794ad1fc4fc..fb67bb55ed79 100644
--- a/drivers/gpu/drm/amd/include/soc15_ih_clientid.h
+++ b/drivers/gpu/drm/amd/include/soc15_ih_clientid.h
@@ -66,6 +66,7 @@ enum soc15_ih_clientid {
SOC15_IH_CLIENTID_VCN1 = SOC15_IH_CLIENTID_UVD1,
SOC15_IH_CLIENTID_SDMA2 = SOC15_IH_CLIENTID_ACP,
SOC15_IH_CLIENTID_SDMA3 = SOC15_IH_CLIENTID_DCE,
+ SOC15_IH_CLIENTID_SDMA3_Sienna_Cichlid = SOC15_IH_CLIENTID_ISP,
SOC15_IH_CLIENTID_SDMA4 = SOC15_IH_CLIENTID_ISP,
SOC15_IH_CLIENTID_SDMA5 = SOC15_IH_CLIENTID_VCE0,
SOC15_IH_CLIENTID_SDMA6 = SOC15_IH_CLIENTID_XDMA,
--
2.25.4
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH 023/207] drm/amdgpu/gfx10: change register configure for sienna_cichlid
2020-06-01 17:59 [PATCH 000/207] Add Support for Sienna Cichlid Alex Deucher
` (17 preceding siblings ...)
2020-06-01 17:59 ` [PATCH 022/207] drm/amdgpu: correct SDMA3 IH clinet id for sienna_cichlid Alex Deucher
@ 2020-06-01 17:59 ` Alex Deucher
2020-06-01 17:59 ` [PATCH 024/207] drm/amdgpu: add virtual display support " Alex Deucher
` (63 subsequent siblings)
82 siblings, 0 replies; 88+ messages in thread
From: Alex Deucher @ 2020-06-01 17:59 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Likun Gao, Hawking Zhang
From: Likun Gao <Likun.Gao@amd.com>
Update sienna_cichlid register configuration for sienna_cichlid
to match the update of header files.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 369 +++++++++++++++++++------
1 file changed, 278 insertions(+), 91 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index feedbde0565d..5cbee23d2ff8 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -66,6 +66,33 @@
#define GB_ADDR_CONFIG__NUM_PKRS__SHIFT 0x8
#define GB_ADDR_CONFIG__NUM_PKRS_MASK 0x00000700L
+#define mmCP_MEC_CNTL_Sienna_Cichlid 0x0f55
+#define mmCP_MEC_CNTL_Sienna_Cichlid_BASE_IDX 0
+#define mmRLC_SAFE_MODE_Sienna_Cichlid 0x4ca0
+#define mmRLC_SAFE_MODE_Sienna_Cichlid_BASE_IDX 1
+#define mmRLC_CP_SCHEDULERS_Sienna_Cichlid 0x4ca1
+#define mmRLC_CP_SCHEDULERS_Sienna_Cichlid_BASE_IDX 1
+#define mmSPI_CONFIG_CNTL_Sienna_Cichlid 0x11ec
+#define mmSPI_CONFIG_CNTL_Sienna_Cichlid_BASE_IDX 0
+#define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid 0x0fc1
+#define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid_BASE_IDX 0
+#define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid 0x0fc2
+#define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid_BASE_IDX 0
+#define mmVGT_TF_RING_SIZE_Sienna_Cichlid 0x0fc3
+#define mmVGT_TF_RING_SIZE_Sienna_Cichlid_BASE_IDX 0
+#define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid 0x0fc4
+#define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid_BASE_IDX 0
+#define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid 0x0fc5
+#define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid_BASE_IDX 0
+#define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid 0x0fc6
+#define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid_BASE_IDX 0
+#define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid__SHIFT 0x1a
+#define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid_MASK 0x04000000L
+#define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid_MASK 0x00000FFCL
+#define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid__SHIFT 0x2
+#define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK 0x00000FFCL
+#define PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC_Sienna_Cichlid_MASK 0x00300000L
+
MODULE_FIRMWARE("amdgpu/navi10_ce.bin");
MODULE_FIRMWARE("amdgpu/navi10_pfp.bin");
MODULE_FIRMWARE("amdgpu/navi10_me.bin");
@@ -4396,9 +4423,18 @@ static u32 gfx_v10_0_init_pa_sc_tile_steering_override(struct amdgpu_device *ade
pa_sc_tile_steering_override |=
(order_base_2(num_rb_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC__SHIFT) &
PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC_MASK;
- pa_sc_tile_steering_override |=
- (order_base_2(num_packer_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC__SHIFT) &
- PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC_MASK;
+ switch (adev->asic_type) {
+ case CHIP_SIENNA_CICHLID:
+ pa_sc_tile_steering_override |=
+ (order_base_2(num_packer_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC__SHIFT) &
+ PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC_Sienna_Cichlid_MASK;
+ break;
+ default:
+ pa_sc_tile_steering_override |=
+ (order_base_2(num_packer_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC__SHIFT) &
+ PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC_MASK;
+ break;
+ }
return pa_sc_tile_steering_override;
}
@@ -5578,12 +5614,24 @@ static void gfx_v10_0_cp_gfx_set_doorbell(struct amdgpu_device *adev,
DOORBELL_EN, 0);
}
WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp);
- tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
- DOORBELL_RANGE_LOWER, ring->doorbell_index);
- WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
+ switch (adev->asic_type) {
+ case CHIP_SIENNA_CICHLID:
+ tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
+ DOORBELL_RANGE_LOWER_Sienna_Cichlid, ring->doorbell_index);
+ WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
+
+ WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
+ CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK);
+ break;
+ default:
+ tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
+ DOORBELL_RANGE_LOWER, ring->doorbell_index);
+ WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
- WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
- CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
+ WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
+ CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
+ break;
+ }
}
static int gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev)
@@ -5698,11 +5746,27 @@ static int gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev)
static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
{
if (enable) {
- WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0);
+ switch (adev->asic_type) {
+ case CHIP_SIENNA_CICHLID:
+ WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid, 0);
+ break;
+ default:
+ WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0);
+ break;
+ }
} else {
- WREG32_SOC15(GC, 0, mmCP_MEC_CNTL,
- (CP_MEC_CNTL__MEC_ME1_HALT_MASK |
- CP_MEC_CNTL__MEC_ME2_HALT_MASK));
+ switch (adev->asic_type) {
+ case CHIP_SIENNA_CICHLID:
+ WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid,
+ (CP_MEC_CNTL__MEC_ME1_HALT_MASK |
+ CP_MEC_CNTL__MEC_ME2_HALT_MASK));
+ break;
+ default:
+ WREG32_SOC15(GC, 0, mmCP_MEC_CNTL,
+ (CP_MEC_CNTL__MEC_ME1_HALT_MASK |
+ CP_MEC_CNTL__MEC_ME2_HALT_MASK));
+ break;
+ }
adev->gfx.kiq.ring.sched.ready = false;
}
udelay(50);
@@ -5784,12 +5848,24 @@ static void gfx_v10_0_kiq_setting(struct amdgpu_ring *ring)
struct amdgpu_device *adev = ring->adev;
/* tell RLC which is KIQ queue */
- tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
- tmp &= 0xffffff00;
- tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
- WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
- tmp |= 0x80;
- WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
+ switch (adev->asic_type) {
+ case CHIP_SIENNA_CICHLID:
+ tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid);
+ tmp &= 0xffffff00;
+ tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
+ WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp);
+ tmp |= 0x80;
+ WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp);
+ break;
+ default:
+ tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
+ tmp &= 0xffffff00;
+ tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
+ WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
+ tmp |= 0x80;
+ WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
+ break;
+ }
}
static int gfx_v10_0_gfx_mqd_init(struct amdgpu_ring *ring)
@@ -6475,18 +6551,33 @@ static bool gfx_v10_0_check_grbm_cam_remapping(struct amdgpu_device *adev)
/* check if mmVGT_ESGS_RING_SIZE_UMD
* has been remapped to mmVGT_ESGS_RING_SIZE */
- data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE);
-
- WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, 0);
+ switch (adev->asic_type) {
+ case CHIP_SIENNA_CICHLID:
+ data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid);
+ WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, 0);
+ WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern);
- WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern);
+ if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) == pattern) {
+ WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD , data);
+ return true;
+ } else {
+ WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, data);
+ return false;
+ }
+ break;
+ default:
+ data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE);
+ WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, 0);
+ WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern);
- if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE) == pattern) {
- WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, data);
- return true;
- } else {
- WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, data);
- return false;
+ if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE) == pattern) {
+ WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, data);
+ return true;
+ } else {
+ WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, data);
+ return false;
+ }
+ break;
}
}
@@ -6498,59 +6589,119 @@ static void gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device *adev)
* index will auto-inc after each data writting */
WREG32_SOC15(GC, 0, mmGRBM_CAM_INDEX, 0);
- /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */
- data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) <<
- GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
- (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE) <<
- GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
- WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
- WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
-
- /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */
- data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) <<
- GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
- (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE) <<
- GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
- WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
- WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
-
- /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */
- data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) <<
- GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
- (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI) <<
- GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
- WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
- WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
-
- /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */
- data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) <<
- GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
- (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM) <<
- GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
- WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
- WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
-
- /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */
- data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) <<
- GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
- (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE) <<
- GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
- WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
- WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
-
- /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */
- data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) <<
- GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
- (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE) <<
- GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
- WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
- WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
+ switch (adev->asic_type) {
+ case CHIP_SIENNA_CICHLID:
+ /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */
+ data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) <<
+ GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
+ (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_Sienna_Cichlid) <<
+ GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
+ WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
+ WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
+
+ /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */
+ data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) <<
+ GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
+ (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_Sienna_Cichlid) <<
+ GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
+ WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
+ WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
+
+ /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */
+ data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) <<
+ GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
+ (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid) <<
+ GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
+ WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
+ WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
+
+ /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */
+ data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) <<
+ GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
+ (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid) <<
+ GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
+ WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
+ WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
+
+ /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */
+ data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) <<
+ GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
+ (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) <<
+ GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
+ WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
+ WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
+
+ /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */
+ data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) <<
+ GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
+ (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_Sienna_Cichlid) <<
+ GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
+ WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
+ WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
+
+ /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */
+ data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) <<
+ GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
+ (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_Sienna_Cichlid) <<
+ GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
+ break;
+ default:
+ /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */
+ data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) <<
+ GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
+ (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE) <<
+ GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
+ WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
+ WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
+
+ /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */
+ data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) <<
+ GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
+ (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE) <<
+ GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
+ WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
+ WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
+
+ /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */
+ data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) <<
+ GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
+ (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI) <<
+ GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
+ WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
+ WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
+
+ /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */
+ data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) <<
+ GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
+ (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM) <<
+ GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
+ WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
+ WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
+
+ /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */
+ data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) <<
+ GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
+ (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE) <<
+ GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
+ WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
+ WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
+
+ /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */
+ data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) <<
+ GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
+ (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE) <<
+ GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
+ WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
+ WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
+
+ /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */
+ data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) <<
+ GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
+ (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL) <<
+ GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
+ break;
+ }
- /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */
- data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) <<
- GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
- (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL) <<
- GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
}
@@ -6722,10 +6873,22 @@ static int gfx_v10_0_soft_reset(void *handle)
/* GRBM_STATUS2 */
tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2);
- if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
- grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
- GRBM_SOFT_RESET, SOFT_RESET_RLC,
- 1);
+ switch (adev->asic_type) {
+ case CHIP_SIENNA_CICHLID:
+ if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY_Sienna_Cichlid))
+ grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
+ GRBM_SOFT_RESET,
+ SOFT_RESET_RLC,
+ 1);
+ break;
+ default:
+ if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
+ grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
+ GRBM_SOFT_RESET,
+ SOFT_RESET_RLC,
+ 1);
+ break;
+ }
if (grbm_soft_reset) {
/* stop the rlc */
@@ -6848,13 +7011,30 @@ static void gfx_v10_0_set_safe_mode(struct amdgpu_device *adev)
data = RLC_SAFE_MODE__CMD_MASK;
data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
- WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
- /* wait for RLC_SAFE_MODE */
- for (i = 0; i < adev->usec_timeout; i++) {
- if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD))
- break;
- udelay(1);
+ switch (adev->asic_type) {
+ case CHIP_SIENNA_CICHLID:
+ WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data);
+
+ /* wait for RLC_SAFE_MODE */
+ for (i = 0; i < adev->usec_timeout; i++) {
+ if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid),
+ RLC_SAFE_MODE, CMD))
+ break;
+ udelay(1);
+ }
+ break;
+ default:
+ WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
+
+ /* wait for RLC_SAFE_MODE */
+ for (i = 0; i < adev->usec_timeout; i++) {
+ if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE),
+ RLC_SAFE_MODE, CMD))
+ break;
+ udelay(1);
+ }
+ break;
}
}
@@ -6863,7 +7043,14 @@ static void gfx_v10_0_unset_safe_mode(struct amdgpu_device *adev)
uint32_t data;
data = RLC_SAFE_MODE__CMD_MASK;
- WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
+ switch (adev->asic_type) {
+ case CHIP_SIENNA_CICHLID:
+ WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data);
+ break;
+ default:
+ WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
+ break;
+ }
}
static void gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
--
2.25.4
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH 024/207] drm/amdgpu: add virtual display support for sienna_cichlid
2020-06-01 17:59 [PATCH 000/207] Add Support for Sienna Cichlid Alex Deucher
` (18 preceding siblings ...)
2020-06-01 17:59 ` [PATCH 023/207] drm/amdgpu/gfx10: change register configure " Alex Deucher
@ 2020-06-01 17:59 ` Alex Deucher
2020-06-01 17:59 ` [PATCH 025/207] drm/amdgpu/powerplay: add initial swSMU support for sienna_cichlid (v2) Alex Deucher
` (62 subsequent siblings)
82 siblings, 0 replies; 88+ messages in thread
From: Alex Deucher @ 2020-06-01 17:59 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Likun Gao, Hawking Zhang
From: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/nv.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index 860c69cccf94..1b17fca98fef 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -488,6 +488,8 @@ int nv_set_ip_blocks(struct amdgpu_device *adev)
amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
+ if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
+ amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block);
break;
--
2.25.4
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH 025/207] drm/amdgpu/powerplay: add initial swSMU support for sienna_cichlid (v2)
2020-06-01 17:59 [PATCH 000/207] Add Support for Sienna Cichlid Alex Deucher
` (19 preceding siblings ...)
2020-06-01 17:59 ` [PATCH 024/207] drm/amdgpu: add virtual display support " Alex Deucher
@ 2020-06-01 17:59 ` Alex Deucher
2020-06-01 17:59 ` [PATCH 026/207] drm/amd/powerplay: add support to set performance level for sienna_cichlid Alex Deucher
` (61 subsequent siblings)
82 siblings, 0 replies; 88+ messages in thread
From: Alex Deucher @ 2020-06-01 17:59 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Likun Gao, Evan Quan, Kevin Wang
From: Likun Gao <Likun.Gao@amd.com>
SMU11 based similar to navi1x.
v2: squash in SMU IF updates
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/powerplay/Makefile | 2 +-
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 10 +-
.../inc/smu11_driver_if_sienna_cichlid.h | 1209 ++++++++++
drivers/gpu/drm/amd/powerplay/inc/smu_types.h | 2 +
drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h | 1 +
.../drm/amd/powerplay/inc/smu_v11_0_7_ppsmc.h | 139 ++
.../drm/amd/powerplay/sienna_cichlid_ppt.c | 2080 +++++++++++++++++
.../drm/amd/powerplay/sienna_cichlid_ppt.h | 28 +
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 15 +-
9 files changed, 3482 insertions(+), 4 deletions(-)
create mode 100644 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_sienna_cichlid.h
create mode 100644 drivers/gpu/drm/amd/powerplay/inc/smu_v11_0_7_ppsmc.h
create mode 100644 drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
create mode 100644 drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.h
diff --git a/drivers/gpu/drm/amd/powerplay/Makefile b/drivers/gpu/drm/amd/powerplay/Makefile
index 709a6dc0f321..d27a02ac5f53 100644
--- a/drivers/gpu/drm/amd/powerplay/Makefile
+++ b/drivers/gpu/drm/amd/powerplay/Makefile
@@ -35,7 +35,7 @@ AMD_POWERPLAY = $(addsuffix /Makefile,$(addprefix $(FULL_AMD_PATH)/powerplay/,$(
include $(AMD_POWERPLAY)
-POWER_MGR = amd_powerplay.o amdgpu_smu.o smu_v11_0.o smu_v12_0.o arcturus_ppt.o navi10_ppt.o renoir_ppt.o
+POWER_MGR = amd_powerplay.o amdgpu_smu.o smu_v11_0.o smu_v12_0.o arcturus_ppt.o navi10_ppt.o renoir_ppt.o sienna_cichlid_ppt.o
AMD_PP_POWER = $(addprefix $(AMD_PP_PATH)/,$(POWER_MGR))
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 5294aa7cdde1..870fe32437b6 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -31,6 +31,7 @@
#include "atom.h"
#include "arcturus_ppt.h"
#include "navi10_ppt.h"
+#include "sienna_cichlid_ppt.h"
#include "renoir_ppt.h"
#undef __SMU_DUMMY_MAP
@@ -762,6 +763,9 @@ static int smu_set_funcs(struct amdgpu_device *adev)
/* OD is not supported on Arcturus */
smu->od_enabled =false;
break;
+ case CHIP_SIENNA_CICHLID:
+ sienna_cichlid_set_ppt_funcs(smu);
+ break;
case CHIP_RENOIR:
renoir_set_ppt_funcs(smu);
break;
@@ -1049,7 +1053,8 @@ static int smu_smc_table_hw_init(struct smu_context *smu,
return 0;
}
- if (adev->asic_type != CHIP_ARCTURUS) {
+ if (adev->asic_type != CHIP_ARCTURUS &&
+ adev->asic_type != CHIP_SIENNA_CICHLID) {
ret = smu_init_display_count(smu, 0);
if (ret)
return ret;
@@ -1159,7 +1164,8 @@ static int smu_smc_table_hw_init(struct smu_context *smu,
}
}
- if (adev->asic_type != CHIP_ARCTURUS) {
+ if (adev->asic_type != CHIP_ARCTURUS &&
+ adev->asic_type != CHIP_SIENNA_CICHLID) {
ret = smu_notify_display_change(smu);
if (ret)
return ret;
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_sienna_cichlid.h b/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_sienna_cichlid.h
new file mode 100644
index 000000000000..bdffba1f0086
--- /dev/null
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_sienna_cichlid.h
@@ -0,0 +1,1209 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef __SMU11_DRIVER_IF_SIENNA_CICHLID_H__
+#define __SMU11_DRIVER_IF_SIENNA_CICHLID_H__
+
+// *** IMPORTANT ***
+// SMU TEAM: Always increment the interface version if
+// any structure is changed in this file
+#define SMU11_DRIVER_IF_VERSION 0x30
+
+#define PPTABLE_Sienna_Cichlid_SMU_VERSION 4
+
+#define NUM_GFXCLK_DPM_LEVELS 16
+#define NUM_SMNCLK_DPM_LEVELS 2
+#define NUM_SOCCLK_DPM_LEVELS 8
+#define NUM_MP0CLK_DPM_LEVELS 2
+#define NUM_DCLK_DPM_LEVELS 8
+#define NUM_VCLK_DPM_LEVELS 8
+#define NUM_DCEFCLK_DPM_LEVELS 8
+#define NUM_PHYCLK_DPM_LEVELS 8
+#define NUM_DISPCLK_DPM_LEVELS 8
+#define NUM_PIXCLK_DPM_LEVELS 8
+#define NUM_DTBCLK_DPM_LEVELS 8
+#define NUM_UCLK_DPM_LEVELS 4
+#define NUM_MP1CLK_DPM_LEVELS 2
+#define NUM_LINK_LEVELS 2
+#define NUM_FCLK_DPM_LEVELS 8
+#define NUM_XGMI_LEVELS 2
+#define NUM_XGMI_PSTATE_LEVELS 4
+#define NUM_OD_FAN_MAX_POINTS 6
+
+#define MAX_GFXCLK_DPM_LEVEL (NUM_GFXCLK_DPM_LEVELS - 1)
+#define MAX_SMNCLK_DPM_LEVEL (NUM_SMNCLK_DPM_LEVELS - 1)
+#define MAX_SOCCLK_DPM_LEVEL (NUM_SOCCLK_DPM_LEVELS - 1)
+#define MAX_MP0CLK_DPM_LEVEL (NUM_MP0CLK_DPM_LEVELS - 1)
+#define MAX_DCLK_DPM_LEVEL (NUM_DCLK_DPM_LEVELS - 1)
+#define MAX_VCLK_DPM_LEVEL (NUM_VCLK_DPM_LEVELS - 1)
+#define MAX_DCEFCLK_DPM_LEVEL (NUM_DCEFCLK_DPM_LEVELS - 1)
+#define MAX_DISPCLK_DPM_LEVEL (NUM_DISPCLK_DPM_LEVELS - 1)
+#define MAX_PIXCLK_DPM_LEVEL (NUM_PIXCLK_DPM_LEVELS - 1)
+#define MAX_PHYCLK_DPM_LEVEL (NUM_PHYCLK_DPM_LEVELS - 1)
+#define MAX_DTBCLK_DPM_LEVEL (NUM_DTBCLK_DPM_LEVELS - 1)
+#define MAX_UCLK_DPM_LEVEL (NUM_UCLK_DPM_LEVELS - 1)
+#define MAX_MP1CLK_DPM_LEVEL (NUM_MP1CLK_DPM_LEVELS - 1)
+#define MAX_LINK_LEVEL (NUM_LINK_LEVELS - 1)
+#define MAX_FCLK_DPM_LEVEL (NUM_FCLK_DPM_LEVELS - 1)
+
+//Gemini Modes
+#define PPSMC_GeminiModeNone 0 //Single GPU board
+#define PPSMC_GeminiModeMaster 1 //Master GPU on a Gemini board
+#define PPSMC_GeminiModeSlave 2 //Slave GPU on a Gemini board
+
+// Feature Control Defines
+// DPM
+#define FEATURE_DPM_PREFETCHER_BIT 0
+#define FEATURE_DPM_GFXCLK_BIT 1
+#define FEATURE_DPM_GFX_GPO_BIT 2
+#define FEATURE_DPM_UCLK_BIT 3
+#define FEATURE_DPM_FCLK_BIT 4
+#define FEATURE_DPM_SOCCLK_BIT 5
+#define FEATURE_DPM_MP0CLK_BIT 6
+#define FEATURE_DPM_LINK_BIT 7
+#define FEATURE_DPM_DCEFCLK_BIT 8
+#define FEATURE_DPM_XGMI_BIT 9
+#define FEATURE_MEM_VDDCI_SCALING_BIT 10
+#define FEATURE_MEM_MVDD_SCALING_BIT 11
+
+//Idle
+#define FEATURE_DS_GFXCLK_BIT 12
+#define FEATURE_DS_SOCCLK_BIT 13
+#define FEATURE_DS_FCLK_BIT 14
+#define FEATURE_DS_LCLK_BIT 15
+#define FEATURE_DS_DCEFCLK_BIT 16
+#define FEATURE_DS_UCLK_BIT 17
+#define FEATURE_GFX_ULV_BIT 18
+#define FEATURE_FW_DSTATE_BIT 19
+#define FEATURE_GFXOFF_BIT 20
+#define FEATURE_BACO_BIT 21
+#define FEATURE_MM_DPM_PG_BIT 22
+#define FEATURE_SPARE_23_BIT 23
+//Throttler/Response
+#define FEATURE_PPT_BIT 24
+#define FEATURE_TDC_BIT 25
+#define FEATURE_APCC_PLUS_BIT 26
+#define FEATURE_GTHR_BIT 27
+#define FEATURE_ACDC_BIT 28
+#define FEATURE_VR0HOT_BIT 29
+#define FEATURE_VR1HOT_BIT 30
+#define FEATURE_FW_CTF_BIT 31
+#define FEATURE_FAN_CONTROL_BIT 32
+#define FEATURE_THERMAL_BIT 33
+#define FEATURE_GFX_DCS_BIT 34
+//VF
+#define FEATURE_RM_BIT 35
+#define FEATURE_LED_DISPLAY_BIT 36
+//Other
+#define FEATURE_GFX_SS_BIT 37
+#define FEATURE_OUT_OF_BAND_MONITOR_BIT 38
+#define FEATURE_TEMP_DEPENDENT_VMIN_BIT 39
+
+#define FEATURE_MMHUB_PG_BIT 40
+#define FEATURE_ATHUB_PG_BIT 41
+#define FEATURE_APCC_DFLL_BIT 42
+#define FEATURE_DF_SUPERV_BIT 43
+#define FEATURE_RSMU_SMN_CG_BIT 44
+#define FEATURE_DF_CSTATE_BIT 45
+#define FEATURE_2_STEP_PSTATE_BIT 46
+#define FEATURE_SMNCLK_DPM_BIT 47
+#define FEATURE_SPARE_48_BIT 48
+#define FEATURE_SPARE_49_BIT 49
+#define FEATURE_SPARE_50_BIT 50
+#define FEATURE_SPARE_51_BIT 51
+#define FEATURE_SPARE_52_BIT 52
+#define FEATURE_SPARE_53_BIT 53
+#define FEATURE_SPARE_54_BIT 54
+#define FEATURE_SPARE_55_BIT 55
+#define FEATURE_SPARE_56_BIT 56
+#define FEATURE_SPARE_57_BIT 57
+#define FEATURE_SPARE_58_BIT 58
+#define FEATURE_SPARE_59_BIT 59
+#define FEATURE_SPARE_60_BIT 60
+#define FEATURE_SPARE_61_BIT 61
+#define FEATURE_SPARE_62_BIT 62
+#define FEATURE_SPARE_63_BIT 63
+#define NUM_FEATURES 64
+
+//For use with feature control messages
+typedef enum {
+ FEATURE_PWR_ALL,
+ FEATURE_PWR_S5,
+ FEATURE_PWR_BACO,
+ FEATURE_PWR_SOC,
+ FEATURE_PWR_GFX,
+ FEATURE_PWR_DOMAIN_COUNT,
+} FEATURE_PWR_DOMAIN_e;
+
+
+// Debug Overrides Bitmask
+#define DPM_OVERRIDE_DISABLE_FCLK_PID 0x00000001
+#define DPM_OVERRIDE_DISABLE_UCLK_PID 0x00000002
+#define DPM_OVERRIDE_DISABLE_VOLT_LINK_VCN_FCLK 0x00000004
+#define DPM_OVERRIDE_ENABLE_FREQ_LINK_VCLK_FCLK 0x00000008
+#define DPM_OVERRIDE_ENABLE_FREQ_LINK_DCLK_FCLK 0x00000010
+#define DPM_OVERRIDE_ENABLE_FREQ_LINK_GFXCLK_SOCCLK 0x00000020
+#define DPM_OVERRIDE_ENABLE_FREQ_LINK_GFXCLK_UCLK 0x00000040
+#define DPM_OVERRIDE_DISABLE_VOLT_LINK_DCE_FCLK 0x00000080
+#define DPM_OVERRIDE_DISABLE_VOLT_LINK_MP0_SOCCLK 0x00000100
+#define DPM_OVERRIDE_DISABLE_DFLL_PLL_SHUTDOWN 0x00000200
+#define DPM_OVERRIDE_DISABLE_MEMORY_TEMPERATURE_READ 0x00000400
+#define DPM_OVERRIDE_DISABLE_VOLT_LINK_VCN_DCEFCLK 0x00000800
+#define DPM_OVERRIDE_DISABLE_FAST_FCLK_TIMER 0x00001000
+#define DPM_OVERRIDE_DISABLE_VCN_PG 0x00002000
+#define DPM_OVERRIDE_DISABLE_FMAX_VMAX 0x00004000
+
+// VR Mapping Bit Defines
+#define VR_MAPPING_VR_SELECT_MASK 0x01
+#define VR_MAPPING_VR_SELECT_SHIFT 0x00
+
+#define VR_MAPPING_PLANE_SELECT_MASK 0x02
+#define VR_MAPPING_PLANE_SELECT_SHIFT 0x01
+
+// PSI Bit Defines
+#define PSI_SEL_VR0_PLANE0_PSI0 0x01
+#define PSI_SEL_VR0_PLANE0_PSI1 0x02
+#define PSI_SEL_VR0_PLANE1_PSI0 0x04
+#define PSI_SEL_VR0_PLANE1_PSI1 0x08
+#define PSI_SEL_VR1_PLANE0_PSI0 0x10
+#define PSI_SEL_VR1_PLANE0_PSI1 0x20
+#define PSI_SEL_VR1_PLANE1_PSI0 0x40
+#define PSI_SEL_VR1_PLANE1_PSI1 0x80
+
+// Throttler Control/Status Bits
+#define THROTTLER_PADDING_BIT 0
+#define THROTTLER_TEMP_EDGE_BIT 1
+#define THROTTLER_TEMP_HOTSPOT_BIT 2
+#define THROTTLER_TEMP_MEM_BIT 3
+#define THROTTLER_TEMP_VR_GFX_BIT 4
+#define THROTTLER_TEMP_VR_MEM0_BIT 5
+#define THROTTLER_TEMP_VR_MEM1_BIT 6
+#define THROTTLER_TEMP_VR_SOC_BIT 7
+#define THROTTLER_TEMP_LIQUID0_BIT 8
+#define THROTTLER_TEMP_LIQUID1_BIT 9
+#define THROTTLER_TEMP_PLX_BIT 10
+#define THROTTLER_TDC_GFX_BIT 11
+#define THROTTLER_TDC_SOC_BIT 12
+#define THROTTLER_PPT0_BIT 13
+#define THROTTLER_PPT1_BIT 14
+#define THROTTLER_PPT2_BIT 15
+#define THROTTLER_PPT3_BIT 16
+#define THROTTLER_FIT_BIT 17
+#define THROTTLER_PPM_BIT 18
+#define THROTTLER_APCC_BIT 19
+
+// FW DState Features Control Bits
+// FW DState Features Control Bits
+#define FW_DSTATE_SOC_ULV_BIT 0
+#define FW_DSTATE_G6_HSR_BIT 1
+#define FW_DSTATE_G6_PHY_VDDCI_OFF_BIT 2
+#define FW_DSTATE_MP0_DS_BIT 3
+#define FW_DSTATE_SMN_DS_BIT 4
+#define FW_DSTATE_MP1_DS_BIT 5
+#define FW_DSTATE_MP1_WHISPER_MODE_BIT 6
+#define FW_DSTATE_SOC_LIV_MIN_BIT 7
+#define FW_DSTATE_SOC_PLL_PWRDN_BIT 8
+#define FW_DSTATE_MEM_PLL_PWRDN_BIT 9
+#define FW_DSTATE_OPTIMIZE_MALL_REFRESH_BIT 10
+#define FW_DSTATE_MEM_PSI_BIT 11
+
+#define FW_DSTATE_SOC_ULV_MASK (1 << FW_DSTATE_SOC_ULV_BIT )
+#define FW_DSTATE_G6_HSR_MASK (1 << FW_DSTATE_G6_HSR_BIT )
+#define FW_DSTATE_G6_PHY_VDDCI_OFF_MASK (1 << FW_DSTATE_G6_PHY_VDDCI_OFF_BIT )
+#define FW_DSTATE_MP1_DS_MASK (1 << FW_DSTATE_MP1_DS_BIT )
+#define FW_DSTATE_MP0_DS_MASK (1 << FW_DSTATE_MP0_DS_BIT )
+#define FW_DSTATE_SMN_DS_MASK (1 << FW_DSTATE_SMN_DS_BIT )
+#define FW_DSTATE_MP1_WHISPER_MODE_MASK (1 << FW_DSTATE_MP1_WHISPER_MODE_BIT )
+#define FW_DSTATE_SOC_LIV_MIN_MASK (1 << FW_DSTATE_SOC_LIV_MIN_BIT )
+#define FW_DSTATE_SOC_PLL_PWRDN_MASK (1 << FW_DSTATE_SOC_PLL_PWRDN_BIT )
+#define FW_DSTATE_MEM_PLL_PWRDN_MASK (1 << FW_DSTATE_MEM_PLL_PWRDN_BIT )
+#define FW_DSTATE_OPTIMIZE_MALL_REFRESH_MASK (1 << FW_DSTATE_OPTIMIZE_MALL_REFRESH_BIT )
+#define FW_DSTATE_MEM_PSI_MASK (1 << FW_DSTATE_MEM_PSI_BIT )
+
+// GFX GPO Feature Contains PACE and DEM sub features
+#define GFX_GPO_PACE_BIT 0
+#define GFX_GPO_DEM_BIT 1
+
+#define GFX_GPO_PACE_MASK (1 << GFX_GPO_PACE_BIT)
+#define GFX_GPO_DEM_MASK (1 << GFX_GPO_DEM_BIT )
+
+#define GPO_UPDATE_REQ_UCLKDPM_MASK 0x1
+#define GPO_UPDATE_REQ_FCLKDPM_MASK 0x2
+#define GPO_UPDATE_REQ_MALLHIT_MASK 0x4
+
+
+//LED Display Mask & Control Bits
+#define LED_DISPLAY_GFX_DPM_BIT 0
+#define LED_DISPLAY_PCIE_BIT 1
+#define LED_DISPLAY_ERROR_BIT 2
+
+//RLC Pace Table total number of levels
+#define RLC_PACE_TABLE_NUM_LEVELS 16
+
+typedef enum {
+ DRAM_BIT_WIDTH_DISABLED = 0,
+ DRAM_BIT_WIDTH_X_8,
+ DRAM_BIT_WIDTH_X_16,
+ DRAM_BIT_WIDTH_X_32,
+ DRAM_BIT_WIDTH_X_64, // NOT USED.
+ DRAM_BIT_WIDTH_X_128,
+ DRAM_BIT_WIDTH_COUNT,
+} DRAM_BIT_WIDTH_TYPE_e;
+
+//I2C Interface
+#define NUM_I2C_CONTROLLERS 16
+
+#define I2C_CONTROLLER_ENABLED 1
+#define I2C_CONTROLLER_DISABLED 0
+
+#define MAX_SW_I2C_COMMANDS 24
+
+typedef enum {
+ I2C_CONTROLLER_PORT_0 = 0, //CKSVII2C0
+ I2C_CONTROLLER_PORT_1 = 1, //CKSVII2C1
+ I2C_CONTROLLER_PORT_COUNT,
+} I2cControllerPort_e;
+
+typedef enum {
+ I2C_CONTROLLER_NAME_VR_GFX = 0,
+ I2C_CONTROLLER_NAME_VR_SOC,
+ I2C_CONTROLLER_NAME_VR_VDDCI,
+ I2C_CONTROLLER_NAME_VR_MVDD,
+ I2C_CONTROLLER_NAME_LIQUID0,
+ I2C_CONTROLLER_NAME_LIQUID1,
+ I2C_CONTROLLER_NAME_PLX,
+ I2C_CONTROLLER_NAME_OTHER,
+ I2C_CONTROLLER_NAME_COUNT,
+} I2cControllerName_e;
+
+typedef enum {
+ I2C_CONTROLLER_THROTTLER_TYPE_NONE = 0,
+ I2C_CONTROLLER_THROTTLER_VR_GFX,
+ I2C_CONTROLLER_THROTTLER_VR_SOC,
+ I2C_CONTROLLER_THROTTLER_VR_VDDCI,
+ I2C_CONTROLLER_THROTTLER_VR_MVDD,
+ I2C_CONTROLLER_THROTTLER_LIQUID0,
+ I2C_CONTROLLER_THROTTLER_LIQUID1,
+ I2C_CONTROLLER_THROTTLER_PLX,
+ I2C_CONTROLLER_THROTTLER_INA3221,
+ I2C_CONTROLLER_THROTTLER_COUNT,
+} I2cControllerThrottler_e;
+
+typedef enum {
+ I2C_CONTROLLER_PROTOCOL_VR_XPDE132G5,
+ I2C_CONTROLLER_PROTOCOL_VR_IR35217,
+ I2C_CONTROLLER_PROTOCOL_TMP_TMP102A,
+ I2C_CONTROLLER_PROTOCOL_INA3221,
+ I2C_CONTROLLER_PROTOCOL_COUNT,
+} I2cControllerProtocol_e;
+
+typedef struct {
+ uint8_t Enabled;
+ uint8_t Speed;
+ uint8_t SlaveAddress;
+ uint8_t ControllerPort;
+ uint8_t ControllerName;
+ uint8_t ThermalThrotter;
+ uint8_t I2cProtocol;
+ uint8_t PaddingConfig;
+} I2cControllerConfig_t;
+
+typedef enum {
+ I2C_PORT_SVD_SCL = 0,
+ I2C_PORT_GPIO,
+} I2cPort_e;
+
+typedef enum {
+ I2C_SPEED_FAST_50K = 0, //50 Kbits/s
+ I2C_SPEED_FAST_100K, //100 Kbits/s
+ I2C_SPEED_FAST_400K, //400 Kbits/s
+ I2C_SPEED_FAST_PLUS_1M, //1 Mbits/s (in fast mode)
+ I2C_SPEED_HIGH_1M, //1 Mbits/s (in high speed mode)
+ I2C_SPEED_HIGH_2M, //2.3 Mbits/s
+ I2C_SPEED_COUNT,
+} I2cSpeed_e;
+
+typedef enum {
+ I2C_CMD_READ = 0,
+ I2C_CMD_WRITE,
+ I2C_CMD_COUNT,
+} I2cCmdType_e;
+
+typedef enum {
+ FAN_MODE_AUTO = 0,
+ FAN_MODE_MANUAL_LINEAR,
+} FanMode_e;
+
+#define CMDCONFIG_STOP_BIT 0
+#define CMDCONFIG_RESTART_BIT 1
+#define CMDCONFIG_READWRITE_BIT 2 //bit should be 0 for read, 1 for write
+
+#define CMDCONFIG_STOP_MASK (1 << CMDCONFIG_STOP_BIT)
+#define CMDCONFIG_RESTART_MASK (1 << CMDCONFIG_RESTART_BIT)
+#define CMDCONFIG_READWRITE_MASK (1 << CMDCONFIG_READWRITE_BIT)
+
+typedef struct {
+ uint8_t ReadWriteData; //Return data for read. Data to send for write
+ uint8_t CmdConfig; //Includes whether associated command should have a stop or restart command, and is a read or write
+} SwI2cCmd_t; //SW I2C Command Table
+
+typedef struct {
+ uint8_t I2CcontrollerPort; //CKSVII2C0(0) or //CKSVII2C1(1)
+ uint8_t I2CSpeed; //Use I2cSpeed_e to indicate speed to select
+ uint8_t SlaveAddress; //Slave address of device
+ uint8_t NumCmds; //Number of commands
+
+ SwI2cCmd_t SwI2cCmds[MAX_SW_I2C_COMMANDS];
+} SwI2cRequest_t; // SW I2C Request Table
+
+typedef struct {
+ SwI2cRequest_t SwI2cRequest;
+
+ uint32_t Spare[8];
+ uint32_t MmHubPadding[8]; // SMU internal use
+} SwI2cRequestExternal_t;
+
+//D3HOT sequences
+typedef enum {
+ BACO_SEQUENCE,
+ MSR_SEQUENCE,
+ BAMACO_SEQUENCE,
+ ULPS_SEQUENCE,
+ D3HOT_SEQUENCE_COUNT,
+} D3HOTSequence_e;
+
+//THis is aligned with RSMU PGFSM Register Mapping
+typedef enum {
+ PG_DYNAMIC_MODE = 0,
+ PG_STATIC_MODE,
+} PowerGatingMode_e;
+
+//This is aligned with RSMU PGFSM Register Mapping
+typedef enum {
+ PG_POWER_DOWN = 0,
+ PG_POWER_UP,
+} PowerGatingSettings_e;
+
+typedef struct {
+ uint32_t a; // store in IEEE float format in this variable
+ uint32_t b; // store in IEEE float format in this variable
+ uint32_t c; // store in IEEE float format in this variable
+} QuadraticInt_t;
+
+typedef struct {
+ uint32_t a; // store in fixed point, [31:20] signed integer, [19:0] fractional bits
+ uint32_t b; // store in fixed point, [31:20] signed integer, [19:0] fractional bits
+ uint32_t c; // store in fixed point, [31:20] signed integer, [19:0] fractional bits
+} QuadraticFixedPoint_t;
+
+typedef struct {
+ uint32_t m; // store in IEEE float format in this variable
+ uint32_t b; // store in IEEE float format in this variable
+} LinearInt_t;
+
+typedef struct {
+ uint32_t a; // store in IEEE float format in this variable
+ uint32_t b; // store in IEEE float format in this variable
+ uint32_t c; // store in IEEE float format in this variable
+} DroopInt_t;
+
+//Piecewise linear droop model, Sienna_Cichlid currently used only for GFX DFLL
+#define NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS 5
+typedef enum {
+ PIECEWISE_LINEAR_FUSED_MODEL = 0,
+ PIECEWISE_LINEAR_PP_MODEL,
+ QUADRATIC_PP_MODEL,
+} DfllDroopModelSelect_e;
+
+typedef struct {
+ uint32_t Fset[NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS]; //in GHz, store in IEEE float format
+ uint32_t Vdroop[NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS]; //in V , store in IEEE float format
+}PiecewiseLinearDroopInt_t;
+
+typedef enum {
+ GFXCLK_SOURCE_PLL = 0,
+ GFXCLK_SOURCE_DFLL,
+ GFXCLK_SOURCE_COUNT,
+} GFXCLK_SOURCE_e;
+
+//Only Clks that have DPM descriptors are listed here
+typedef enum {
+ PPCLK_GFXCLK = 0,
+ PPCLK_SOCCLK,
+ PPCLK_UCLK,
+ PPCLK_FCLK,
+ PPCLK_DCLK_0,
+ PPCLK_VCLK_0,
+ PPCLK_DCLK_1,
+ PPCLK_VCLK_1,
+ PPCLK_DCEFCLK,
+ PPCLK_DISPCLK,
+ PPCLK_PIXCLK,
+ PPCLK_PHYCLK,
+ PPCLK_DTBCLK,
+ PPCLK_COUNT,
+} PPCLK_e;
+
+typedef enum {
+ VOLTAGE_MODE_AVFS = 0,
+ VOLTAGE_MODE_AVFS_SS,
+ VOLTAGE_MODE_SS,
+ VOLTAGE_MODE_COUNT,
+} VOLTAGE_MODE_e;
+
+
+typedef enum {
+ AVFS_VOLTAGE_GFX = 0,
+ AVFS_VOLTAGE_SOC,
+ AVFS_VOLTAGE_COUNT,
+} AVFS_VOLTAGE_TYPE_e;
+
+typedef enum {
+ UCLK_DIV_BY_1 = 0,
+ UCLK_DIV_BY_2,
+ UCLK_DIV_BY_4,
+ UCLK_DIV_BY_8,
+} UCLK_DIV_e;
+
+typedef enum {
+ GPIO_INT_POLARITY_ACTIVE_LOW = 0,
+ GPIO_INT_POLARITY_ACTIVE_HIGH,
+} GpioIntPolarity_e;
+
+typedef enum {
+ PWR_CONFIG_TDP = 0,
+ PWR_CONFIG_TGP,
+ PWR_CONFIG_TCP_ESTIMATED,
+ PWR_CONFIG_TCP_MEASURED,
+} PwrConfig_e;
+
+typedef enum {
+ XGMI_LINK_RATE_2 = 2, // 2Gbps
+ XGMI_LINK_RATE_4 = 4, // 4Gbps
+ XGMI_LINK_RATE_8 = 8, // 8Gbps
+ XGMI_LINK_RATE_12 = 12, // 12Gbps
+ XGMI_LINK_RATE_16 = 16, // 16Gbps
+ XGMI_LINK_RATE_17 = 17, // 17Gbps
+ XGMI_LINK_RATE_18 = 18, // 18Gbps
+ XGMI_LINK_RATE_19 = 19, // 19Gbps
+ XGMI_LINK_RATE_20 = 20, // 20Gbps
+ XGMI_LINK_RATE_21 = 21, // 21Gbps
+ XGMI_LINK_RATE_22 = 22, // 22Gbps
+ XGMI_LINK_RATE_23 = 23, // 23Gbps
+ XGMI_LINK_RATE_24 = 24, // 24Gbps
+ XGMI_LINK_RATE_25 = 25, // 25Gbps
+ XGMI_LINK_RATE_COUNT
+} XGMI_LINK_RATE_e;
+
+typedef enum {
+ XGMI_LINK_WIDTH_1 = 0, // x1
+ XGMI_LINK_WIDTH_2, // x2
+ XGMI_LINK_WIDTH_4, // x4
+ XGMI_LINK_WIDTH_8, // x8
+ XGMI_LINK_WIDTH_9, // x9
+ XGMI_LINK_WIDTH_16, // x16
+ XGMI_LINK_WIDTH_COUNT
+} XGMI_LINK_WIDTH_e;
+
+typedef struct {
+ uint8_t VoltageMode; // 0 - AVFS only, 1- min(AVFS,SS), 2-SS only
+ uint8_t SnapToDiscrete; // 0 - Fine grained DPM, 1 - Discrete DPM
+ uint8_t NumDiscreteLevels; // Set to 2 (Fmin, Fmax) when using fine grained DPM, otherwise set to # discrete levels used
+ uint8_t Padding;
+ LinearInt_t ConversionToAvfsClk; // Transfer function to AVFS Clock (GHz->GHz)
+ QuadraticInt_t SsCurve; // Slow-slow curve (GHz->V)
+ uint16_t SsFmin; // Fmin for SS curve. If SS curve is selected, will use V@SSFmin for F <= Fmin
+ uint16_t Padding16;
+} DpmDescriptor_t;
+
+typedef enum {
+ PPT_THROTTLER_PPT0,
+ PPT_THROTTLER_PPT1,
+ PPT_THROTTLER_PPT2,
+ PPT_THROTTLER_PPT3,
+ PPT_THROTTLER_COUNT
+} PPT_THROTTLER_e;
+
+typedef enum {
+ TEMP_EDGE,
+ TEMP_HOTSPOT,
+ TEMP_MEM,
+ TEMP_VR_GFX,
+ TEMP_VR_MEM0,
+ TEMP_VR_MEM1,
+ TEMP_VR_SOC,
+ TEMP_LIQUID0,
+ TEMP_LIQUID1,
+ TEMP_PLX,
+ TEMP_COUNT,
+} TEMP_e;
+
+typedef enum {
+ TDC_THROTTLER_GFX,
+ TDC_THROTTLER_SOC,
+ TDC_THROTTLER_COUNT
+} TDC_THROTTLER_e;
+
+// Used for 2-step UCLK DPM change workaround
+typedef struct {
+ uint16_t Fmin;
+ uint16_t Fmax;
+} UclkDpmChangeRange_t;
+
+typedef struct {
+ // MAJOR SECTION: SKU PARAMETERS
+
+ uint32_t Version;
+
+ // SECTION: Feature Enablement
+ uint32_t FeaturesToRun[NUM_FEATURES / 32];
+
+ // SECTION: Infrastructure Limits
+ uint16_t SocketPowerLimitAc[PPT_THROTTLER_COUNT]; // Watts
+ uint16_t SocketPowerLimitAcTau[PPT_THROTTLER_COUNT]; // Time constant of LPF in ms
+ uint16_t SocketPowerLimitDc[PPT_THROTTLER_COUNT]; // Watts
+ uint16_t SocketPowerLimitDcTau[PPT_THROTTLER_COUNT]; // Time constant of LPF in ms
+
+ uint16_t TdcLimit[TDC_THROTTLER_COUNT]; // Amps
+ uint16_t TdcLimitTau[TDC_THROTTLER_COUNT]; // Time constant of LPF in ms
+
+ uint16_t TemperatureLimit[TEMP_COUNT]; // Celcius
+
+ uint32_t FitLimit; // Failures in time (failures per million parts over the defined lifetime)
+
+ // SECTION: Power Configuration
+ uint8_t TotalPowerConfig; //0-TDP, 1-TGP, 2-TCP Estimated, 3-TCP Measured. Use defines from PwrConfig_e
+ uint8_t TotalPowerPadding[3];
+
+ // SECTION: APCC Settings
+ uint32_t ApccPlusResidencyLimit;
+
+ //SECTION: SMNCLK DPM
+ uint16_t SmnclkDpmFreq [NUM_SMNCLK_DPM_LEVELS]; // in MHz
+ uint16_t SmnclkDpmVoltage [NUM_SMNCLK_DPM_LEVELS]; // mV(Q2)
+
+ uint32_t PaddingAPCC[4];
+
+ // SECTION: Throttler settings
+ uint32_t ThrottlerControlMask; // See Throtter masks defines
+
+ // SECTION: FW DSTATE Settings
+ uint32_t FwDStateMask; // See FW DState masks defines
+
+ // SECTION: ULV Settings
+ uint16_t UlvVoltageOffsetSoc; // In mV(Q2)
+ uint16_t UlvVoltageOffsetGfx; // In mV(Q2)
+
+ uint16_t MinVoltageUlvGfx; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_GFX in ULV mode
+ uint16_t MinVoltageUlvSoc; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_SOC in ULV mode
+
+ uint16_t SocLIVmin; // In mV(Q2) Long Idle Vmin (deep ULV), for VDD_SOC
+ uint16_t PaddingLIVmin;
+
+ uint8_t GceaLinkMgrIdleThreshold; //Set by SMU FW during enablment of GFXOFF. Controls delay for GFX SDP port disconnection during idle events
+ uint8_t paddingRlcUlvParams[3];
+
+ // SECTION: Voltage Control Parameters
+ uint16_t MinVoltageGfx; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_GFX
+ uint16_t MinVoltageSoc; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_SOC
+ uint16_t MaxVoltageGfx; // In mV(Q2) Maximum Voltage allowable of VDD_GFX
+ uint16_t MaxVoltageSoc; // In mV(Q2) Maximum Voltage allowable of VDD_SOC
+
+ uint16_t LoadLineResistanceGfx; // In mOhms with 8 fractional bits
+ uint16_t LoadLineResistanceSoc; // In mOhms with 8 fractional bits
+
+ // SECTION: Temperature Dependent Vmin
+ uint16_t VDDGFX_TVmin; //Celcius
+ uint16_t VDDSOC_TVmin; //Celcius
+ uint16_t VDDGFX_Vmin_HiTemp; // mV Q2
+ uint16_t VDDGFX_Vmin_LoTemp; // mV Q2
+ uint16_t VDDSOC_Vmin_HiTemp; // mV Q2
+ uint16_t VDDSOC_Vmin_LoTemp; // mV Q2
+
+ uint16_t VDDGFX_TVminHystersis; // Celcius
+ uint16_t VDDSOC_TVminHystersis; // Celcius
+
+ //SECTION: DPM Config 1
+ DpmDescriptor_t DpmDescriptor[PPCLK_COUNT];
+
+ uint16_t FreqTableGfx [NUM_GFXCLK_DPM_LEVELS ]; // In MHz
+ uint16_t FreqTableVclk [NUM_VCLK_DPM_LEVELS ]; // In MHz
+ uint16_t FreqTableDclk [NUM_DCLK_DPM_LEVELS ]; // In MHz
+ uint16_t FreqTableSocclk [NUM_SOCCLK_DPM_LEVELS ]; // In MHz
+ uint16_t FreqTableUclk [NUM_UCLK_DPM_LEVELS ]; // In MHz
+ uint16_t FreqTableDcefclk [NUM_DCEFCLK_DPM_LEVELS ]; // In MHz
+ uint16_t FreqTableDispclk [NUM_DISPCLK_DPM_LEVELS ]; // In MHz
+ uint16_t FreqTablePixclk [NUM_PIXCLK_DPM_LEVELS ]; // In MHz
+ uint16_t FreqTablePhyclk [NUM_PHYCLK_DPM_LEVELS ]; // In MHz
+ uint16_t FreqTableDtbclk [NUM_DTBCLK_DPM_LEVELS ]; // In MHz
+ uint16_t FreqTableFclk [NUM_FCLK_DPM_LEVELS ]; // In MHz
+ uint32_t Paddingclks[16];
+
+ uint32_t DcModeMaxFreq [PPCLK_COUNT ]; // In MHz
+
+ uint8_t FreqTableUclkDiv [NUM_UCLK_DPM_LEVELS ]; // 0:Div-1, 1:Div-1/2, 2:Div-1/4, 3:Div-1/8
+
+ // Used for MALL performance boost
+ uint16_t FclkBoostFreq; // In Mhz
+ uint16_t FclkParamPadding;
+
+ // SECTION: DPM Config 2
+ uint16_t Mp0clkFreq [NUM_MP0CLK_DPM_LEVELS]; // in MHz
+ uint16_t Mp0DpmVoltage [NUM_MP0CLK_DPM_LEVELS]; // mV(Q2)
+ uint16_t MemVddciVoltage [NUM_UCLK_DPM_LEVELS]; // mV(Q2)
+ uint16_t MemMvddVoltage [NUM_UCLK_DPM_LEVELS]; // mV(Q2)
+ // GFXCLK DPM
+ uint16_t GfxclkFgfxoffEntry; // in Mhz
+ uint16_t GfxclkFinit; // in Mhz
+ uint16_t GfxclkFidle; // in MHz
+ uint8_t GfxclkSource; // 0 = PLL, 1 = DFLL
+ uint8_t GfxclkPadding;
+
+ // GFX GPO
+ uint8_t GfxGpoSubFeatureMask; // bit 0 = PACE, bit 1 = DEM
+ uint8_t GfxGpoEnabledWorkPolicyMask; //Any policy that GPO can be enabled
+ uint8_t GfxGpoDisabledWorkPolicyMask; //Any policy that GPO can be disabled
+ uint8_t GfxGpoPadding[1];
+ uint32_t GfxGpoVotingAllow; //For indicating which feature changes should result in a GPO table recalculation
+
+ uint32_t GfxGpoPadding32[4];
+
+ uint16_t GfxDcsFopt; // Optimal GFXCLK for DCS in Mhz
+ uint16_t GfxDcsFclkFopt; // Optimal FCLK for DCS in Mhz
+ uint16_t GfxDcsUclkFopt; // Optimal UCLK for DCS in Mhz
+
+ uint16_t DcsGfxOffVoltage; //Voltage in mV(Q2) applied to VDDGFX when entering DCS GFXOFF phase
+
+ uint16_t DcsMinGfxOffTime; //Minimum amount of time PMFW shuts GFX OFF as part of GFX DCS phase
+ uint16_t DcsMaxGfxOffTime; //Maximum amount of time PMFW can shut GFX OFF as part of GFX DCS phase at a stretch.
+
+ uint32_t DcsMinCreditAccum; //Min amount of positive credit accumulation before waking GFX up as part of DCS.
+
+ uint16_t DcsExitHysteresis; //The min amount of time power credit accumulator should have a value > 0 before SMU exits the DCS throttling phase.
+ uint16_t DcsTimeout; //This is the amount of time SMU FW waits for RLC to put GFX into GFXOFF before reverting to the fallback mechanism of throttling GFXCLK to Fmin.
+
+ uint32_t DcsParamPadding[5];
+
+ uint16_t FlopsPerByteTable[RLC_PACE_TABLE_NUM_LEVELS]; // Q8.8
+
+ // UCLK section
+ uint8_t LowestUclkReservedForUlv; // Set this to 1 if UCLK DPM0 is reserved for ULV-mode only
+ uint8_t PaddingMem[3];
+
+ uint8_t UclkDpmPstates [NUM_UCLK_DPM_LEVELS]; // 4 DPM states, 0-P0, 1-P1, 2-P2, 3-P3.
+
+ // Used for 2-Step UCLK change workaround
+ UclkDpmChangeRange_t UclkDpmSrcFreqRange; // In Mhz
+ UclkDpmChangeRange_t UclkDpmTargFreqRange; // In Mhz
+ uint16_t UclkDpmMidstepFreq; // In Mhz
+ uint16_t UclkMidstepPadding;
+
+ // Link DPM Settings
+ uint8_t PcieGenSpeed[NUM_LINK_LEVELS]; ///< 0:PciE-gen1 1:PciE-gen2 2:PciE-gen3 3:PciE-gen4
+ uint8_t PcieLaneCount[NUM_LINK_LEVELS]; ///< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16
+ uint16_t LclkFreq[NUM_LINK_LEVELS];
+
+ // SECTION: Fan Control
+ uint16_t FanStopTemp; //Celcius
+ uint16_t FanStartTemp; //Celcius
+
+ uint16_t FanGain[TEMP_COUNT];
+
+ uint16_t FanPwmMin;
+ uint16_t FanAcousticLimitRpm;
+ uint16_t FanThrottlingRpm;
+ uint16_t FanMaximumRpm;
+ uint16_t MGpuFanBoostLimitRpm;
+ uint16_t FanTargetTemperature;
+ uint16_t FanTargetGfxclk;
+ uint16_t FanPadding16;
+ uint8_t FanTempInputSelect;
+ uint8_t FanPadding;
+ uint8_t FanZeroRpmEnable;
+ uint8_t FanTachEdgePerRev;
+
+ // The following are AFC override parameters. Leave at 0 to use FW defaults.
+ int16_t FuzzyFan_ErrorSetDelta;
+ int16_t FuzzyFan_ErrorRateSetDelta;
+ int16_t FuzzyFan_PwmSetDelta;
+ uint16_t FuzzyFan_Reserved;
+
+ // SECTION: AVFS
+ // Overrides
+ uint8_t OverrideAvfsGb[AVFS_VOLTAGE_COUNT];
+ uint8_t dBtcGbGfxDfllModelSelect; //0 -> fused piece-wise model, 1 -> piece-wise linear(PPTable), 2 -> quadratic model(PPTable)
+ uint8_t Padding8_Avfs;
+
+ QuadraticInt_t qAvfsGb[AVFS_VOLTAGE_COUNT]; // GHz->V Override of fused curve
+ DroopInt_t dBtcGbGfxPll; // GHz->V BtcGb
+ DroopInt_t dBtcGbGfxDfll; // GHz->V BtcGb
+ DroopInt_t dBtcGbSoc; // GHz->V BtcGb
+ LinearInt_t qAgingGb[AVFS_VOLTAGE_COUNT]; // GHz->V
+
+ PiecewiseLinearDroopInt_t PiecewiseLinearDroopIntGfxDfll; //GHz ->Vstore in IEEE float format
+
+ QuadraticInt_t qStaticVoltageOffset[AVFS_VOLTAGE_COUNT]; // GHz->V
+
+ uint16_t DcTol[AVFS_VOLTAGE_COUNT]; // mV Q2
+
+ uint8_t DcBtcEnabled[AVFS_VOLTAGE_COUNT];
+ uint8_t Padding8_GfxBtc[2];
+
+ uint16_t DcBtcMin[AVFS_VOLTAGE_COUNT]; // mV Q2
+ uint16_t DcBtcMax[AVFS_VOLTAGE_COUNT]; // mV Q2
+
+ uint16_t DcBtcGb[AVFS_VOLTAGE_COUNT]; // mV Q2
+
+ // SECTION: XGMI
+ uint8_t XgmiDpmPstates[NUM_XGMI_LEVELS]; // 2 DPM states, high and low. 0-P0, 1-P1, 2-P2, 3-P3.
+ uint8_t XgmiDpmSpare[2];
+
+ // SECTION: Advanced Options
+ uint32_t DebugOverrides;
+ QuadraticInt_t ReservedEquation0;
+ QuadraticInt_t ReservedEquation1;
+ QuadraticInt_t ReservedEquation2;
+ QuadraticInt_t ReservedEquation3;
+
+ // SECTION: Sku Reserved
+ uint32_t SkuReserved[15];
+
+ // MAJOR SECTION: BOARD PARAMETERS
+
+ //SECTION: Gaming Clocks
+ uint32_t GamingClk[6];
+
+ // SECTION: I2C Control
+ I2cControllerConfig_t I2cControllers[NUM_I2C_CONTROLLERS];
+
+ uint8_t GpioScl; // GPIO Number for SCL Line, used only for CKSVII2C1
+ uint8_t GpioSda; // GPIO Number for SDA Line, used only for CKSVII2C1
+ uint8_t FchUsbPdSlaveAddr; //For requesting USB PD controller S-states via FCH I2C when entering PME turn off
+ uint8_t I2cSpare[1];
+
+ // SECTION: SVI2 Board Parameters
+ uint8_t VddGfxVrMapping; // Use VR_MAPPING* bitfields
+ uint8_t VddSocVrMapping; // Use VR_MAPPING* bitfields
+ uint8_t VddMem0VrMapping; // Use VR_MAPPING* bitfields
+ uint8_t VddMem1VrMapping; // Use VR_MAPPING* bitfields
+
+ uint8_t GfxUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode
+ uint8_t SocUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode
+ uint8_t VddciUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode
+ uint8_t MvddUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode
+
+ // SECTION: Telemetry Settings
+ uint16_t GfxMaxCurrent; // in Amps
+ int8_t GfxOffset; // in Amps
+ uint8_t Padding_TelemetryGfx;
+
+ uint16_t SocMaxCurrent; // in Amps
+ int8_t SocOffset; // in Amps
+ uint8_t Padding_TelemetrySoc;
+
+ uint16_t Mem0MaxCurrent; // in Amps
+ int8_t Mem0Offset; // in Amps
+ uint8_t Padding_TelemetryMem0;
+
+ uint16_t Mem1MaxCurrent; // in Amps
+ int8_t Mem1Offset; // in Amps
+ uint8_t Padding_TelemetryMem1;
+
+ uint32_t MvddRatio; // This is used for MVDD Svi2 Div Ratio workaround. It has 16 fractional bits (Q16.16)
+
+ // SECTION: GPIO Settings
+ uint8_t AcDcGpio; // GPIO pin configured for AC/DC switching
+ uint8_t AcDcPolarity; // GPIO polarity for AC/DC switching
+ uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event
+ uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event
+
+ uint8_t VR1HotGpio; // GPIO pin configured for VR1 HOT event
+ uint8_t VR1HotPolarity; // GPIO polarity for VR1 HOT event
+ uint8_t GthrGpio; // GPIO pin configured for GTHR Event
+ uint8_t GthrPolarity; // replace GPIO polarity for GTHR
+
+ // LED Display Settings
+ uint8_t LedPin0; // GPIO number for LedPin[0]
+ uint8_t LedPin1; // GPIO number for LedPin[1]
+ uint8_t LedPin2; // GPIO number for LedPin[2]
+ uint8_t LedEnableMask;
+
+ uint8_t LedPcie; // GPIO number for PCIE results
+ uint8_t LedError; // GPIO number for Error Cases
+ uint8_t LedSpare1[2];
+
+ // SECTION: Clock Spread Spectrum
+
+ // GFXCLK PLL Spread Spectrum
+ uint8_t PllGfxclkSpreadEnabled; // on or off
+ uint8_t PllGfxclkSpreadPercent; // Q4.4
+ uint16_t PllGfxclkSpreadFreq; // kHz
+
+ // GFXCLK DFLL Spread Spectrum
+ uint8_t DfllGfxclkSpreadEnabled; // on or off
+ uint8_t DfllGfxclkSpreadPercent; // Q4.4
+ uint16_t DfllGfxclkSpreadFreq; // kHz
+
+ // UCLK Spread Spectrum
+ uint8_t UclkSpreadEnabled; // on or off
+ uint8_t UclkSpreadPercent; // Q4.4
+ uint16_t UclkSpreadFreq; // kHz
+
+ // FCLK Spread Spectrum
+ uint8_t FclkSpreadEnabled; // on or off
+ uint8_t FclkSpreadPercent; // Q4.4
+ uint16_t FclkSpreadFreq; // kHz
+
+ // Section: Memory Config
+ uint32_t MemoryChannelEnabled; // For DRAM use only, Max 32 channels enabled bit mask.
+
+ uint8_t DramBitWidth; // For DRAM use only. See Dram Bit width type defines
+ uint8_t PaddingMem1[3];
+
+ // Section: Total Board Power
+ uint16_t TotalBoardPower; //Only needed for TCP Estimated case, where TCP = TGP+Total Board Power
+ uint16_t BoardPowerPadding;
+
+ // SECTION: XGMI Training
+ uint8_t XgmiLinkSpeed [NUM_XGMI_PSTATE_LEVELS];
+ uint8_t XgmiLinkWidth [NUM_XGMI_PSTATE_LEVELS];
+
+ uint16_t XgmiFclkFreq [NUM_XGMI_PSTATE_LEVELS];
+ uint16_t XgmiSocVoltage [NUM_XGMI_PSTATE_LEVELS];
+
+ // SECTION: UMC feature flags
+ uint8_t HsrEnabled;
+ uint8_t VddqOffEnabled;
+ uint8_t PaddingUmcFlags[2];
+
+ // SECTION: Board Reserved
+ uint32_t BoardReserved[15];
+
+ // SECTION: Structure Padding
+
+ // Padding for MMHUB - do not modify this
+ uint32_t MmHubPadding[8]; // SMU internal use
+
+} PPTable_t;
+
+typedef struct {
+ // Time constant parameters for clock averages in ms
+ uint16_t GfxclkAverageLpfTau;
+ uint16_t FclkAverageLpfTau;
+ uint16_t UclkAverageLpfTau;
+ uint16_t GfxActivityLpfTau;
+ uint16_t UclkActivityLpfTau;
+ uint16_t SocketPowerLpfTau;
+} DriverSmuConfig_t;
+
+typedef struct {
+ DriverSmuConfig_t DriverSmuConfig;
+
+ uint32_t Spare[8];
+ // Padding - ignore
+ uint32_t MmHubPadding[8]; // SMU internal use
+} DriverSmuConfigExternal_t;
+
+typedef struct {
+ uint16_t GfxclkFmin; // MHz
+ uint16_t GfxclkFmax; // MHz
+ QuadraticInt_t CustomGfxVfCurve; // a: mV/MHz^2, b: mv/MHz, c: mV
+ uint16_t CustomCurveFmin; // MHz
+ uint16_t UclkFmin; // MHz
+ uint16_t UclkFmax; // MHz
+ int16_t OverDrivePct; // %
+ uint16_t FanMaximumRpm;
+ uint16_t FanMinimumPwm;
+ uint16_t FanTargetTemperature; // Degree Celcius
+ uint8_t FanLinearPwmPoints[NUM_OD_FAN_MAX_POINTS];
+ uint8_t FanLinearTempPoints[NUM_OD_FAN_MAX_POINTS];
+ uint16_t MaxOpTemp; // Degree Celcius
+ uint8_t FanZeroRpmEnable;
+ uint8_t FanZeroRpmStopTemp;
+ uint8_t FanMode;
+ uint8_t Padding[1];
+} OverDriveTable_t;
+
+typedef struct {
+ OverDriveTable_t OverDriveTable;
+ uint32_t Spare[8];
+
+ uint32_t MmHubPadding[8]; // SMU internal use
+} OverDriveTableExternal_t;
+
+typedef struct {
+ uint32_t CurrClock[PPCLK_COUNT];
+ uint16_t AverageGfxclkFrequency;
+ uint16_t AverageFclkFrequency;
+ uint16_t AverageUclkFrequency ;
+ uint16_t AverageGfxActivity ;
+ uint16_t AverageUclkActivity ;
+ uint8_t CurrSocVoltageOffset ;
+ uint8_t CurrGfxVoltageOffset ;
+ uint8_t CurrMemVidOffset ;
+ uint8_t Padding8 ;
+ uint16_t AverageSocketPower ;
+ uint16_t TemperatureEdge ;
+ uint16_t TemperatureHotspot ;
+ uint16_t TemperatureMem ;
+ uint16_t TemperatureVrGfx ;
+ uint16_t TemperatureVrMem0 ;
+ uint16_t TemperatureVrMem1 ;
+ uint16_t TemperatureVrSoc ;
+ uint16_t TemperatureLiquid0 ;
+ uint16_t TemperatureLiquid1 ;
+ uint16_t TemperaturePlx ;
+ uint32_t ThrottlerStatus ;
+
+ uint8_t LinkDpmLevel;
+ uint8_t CurrFanPwm;
+ uint16_t CurrFanSpeed;
+
+ //BACO metrics, PMFW-1721
+ //metrics for D3hot entry/exit and driver ARM msgs
+ uint8_t D3HotEntryCountPerMode[D3HOT_SEQUENCE_COUNT];
+ uint8_t D3HotExitCountPerMode[D3HOT_SEQUENCE_COUNT];
+ uint8_t ArmMsgReceivedCountPerMode[D3HOT_SEQUENCE_COUNT];
+} SmuMetrics_t;
+
+typedef struct {
+ SmuMetrics_t SmuMetrics;
+ uint32_t Spare[5];
+
+ // Padding - ignore
+ uint32_t MmHubPadding[8]; // SMU internal use
+} SmuMetricsExternal_t;
+
+typedef struct {
+ uint16_t MinClock; // This is either DCEFCLK or SOCCLK (in MHz)
+ uint16_t MaxClock; // This is either DCEFCLK or SOCCLK (in MHz)
+ uint16_t MinUclk;
+ uint16_t MaxUclk;
+
+ uint8_t WmSetting;
+ uint8_t Flags;
+ uint8_t Padding[2];
+
+} WatermarkRowGeneric_t;
+
+#define NUM_WM_RANGES 4
+
+typedef enum {
+ WM_SOCCLK = 0,
+ WM_DCEFCLK,
+ WM_COUNT,
+} WM_CLOCK_e;
+
+typedef enum {
+ WATERMARKS_CLOCK_RANGE = 0,
+ WATERMARKS_DUMMY_PSTATE,
+ WATERMARKS_MALL,
+ WATERMARKS_COUNT,
+} WATERMARKS_FLAGS_e;
+
+typedef struct {
+ // Watermarks
+ WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES];
+} Watermarks_t;
+
+typedef struct {
+ Watermarks_t Watermarks;
+
+ uint32_t MmHubPadding[8]; // SMU internal use
+} WatermarksExternal_t;
+
+typedef struct {
+ uint16_t avgPsmCount[67];
+ uint16_t minPsmCount[67];
+ float avgPsmVoltage[67];
+ float minPsmVoltage[67];
+} AvfsDebugTable_t;
+
+typedef struct {
+ AvfsDebugTable_t AvfsDebugTable;
+
+ uint32_t MmHubPadding[8]; // SMU internal use
+} AvfsDebugTableExternal_t;
+
+typedef struct {
+ uint8_t AvfsVersion;
+ uint8_t Padding;
+
+ uint8_t AvfsEn[AVFS_VOLTAGE_COUNT];
+
+ uint8_t OverrideVFT[AVFS_VOLTAGE_COUNT];
+ uint8_t OverrideAvfsGb[AVFS_VOLTAGE_COUNT];
+
+ uint8_t OverrideTemperatures[AVFS_VOLTAGE_COUNT];
+ uint8_t OverrideVInversion[AVFS_VOLTAGE_COUNT];
+ uint8_t OverrideP2V[AVFS_VOLTAGE_COUNT];
+ uint8_t OverrideP2VCharzFreq[AVFS_VOLTAGE_COUNT];
+
+ int32_t VFT0_m1[AVFS_VOLTAGE_COUNT]; // Q8.24
+ int32_t VFT0_m2[AVFS_VOLTAGE_COUNT]; // Q12.12
+ int32_t VFT0_b[AVFS_VOLTAGE_COUNT]; // Q32
+
+ int32_t VFT1_m1[AVFS_VOLTAGE_COUNT]; // Q8.16
+ int32_t VFT1_m2[AVFS_VOLTAGE_COUNT]; // Q12.12
+ int32_t VFT1_b[AVFS_VOLTAGE_COUNT]; // Q32
+
+ int32_t VFT2_m1[AVFS_VOLTAGE_COUNT]; // Q8.16
+ int32_t VFT2_m2[AVFS_VOLTAGE_COUNT]; // Q12.12
+ int32_t VFT2_b[AVFS_VOLTAGE_COUNT]; // Q32
+
+ int32_t AvfsGb0_m1[AVFS_VOLTAGE_COUNT]; // Q8.24
+ int32_t AvfsGb0_m2[AVFS_VOLTAGE_COUNT]; // Q12.12
+ int32_t AvfsGb0_b[AVFS_VOLTAGE_COUNT]; // Q32
+
+ int32_t AcBtcGb_m1[AVFS_VOLTAGE_COUNT]; // Q8.24
+ int32_t AcBtcGb_m2[AVFS_VOLTAGE_COUNT]; // Q12.12
+ int32_t AcBtcGb_b[AVFS_VOLTAGE_COUNT]; // Q32
+
+ uint32_t AvfsTempCold[AVFS_VOLTAGE_COUNT];
+ uint32_t AvfsTempMid[AVFS_VOLTAGE_COUNT];
+ uint32_t AvfsTempHot[AVFS_VOLTAGE_COUNT];
+
+ uint32_t VInversion[AVFS_VOLTAGE_COUNT]; // in mV with 2 fractional bits
+
+
+ int32_t P2V_m1[AVFS_VOLTAGE_COUNT]; // Q8.24
+ int32_t P2V_m2[AVFS_VOLTAGE_COUNT]; // Q12.12
+ int32_t P2V_b[AVFS_VOLTAGE_COUNT]; // Q32
+
+ uint32_t P2VCharzFreq[AVFS_VOLTAGE_COUNT]; // in 10KHz units
+
+ uint32_t EnabledAvfsModules[3]; //Sienna_Cichlid - 67 AVFS modules
+} AvfsFuseOverride_t;
+
+typedef struct {
+ AvfsFuseOverride_t AvfsFuseOverride;
+
+ uint32_t MmHubPadding[8]; // SMU internal use
+} AvfsFuseOverrideExternal_t;
+
+typedef struct {
+ uint8_t Gfx_ActiveHystLimit;
+ uint8_t Gfx_IdleHystLimit;
+ uint8_t Gfx_FPS;
+ uint8_t Gfx_MinActiveFreqType;
+ uint8_t Gfx_BoosterFreqType;
+ uint8_t Gfx_MinFreqStep; // Minimum delta between current and target frequeny in order for FW to change clock.
+ uint16_t Gfx_MinActiveFreq; // MHz
+ uint16_t Gfx_BoosterFreq; // MHz
+ uint16_t Gfx_PD_Data_time_constant; // Time constant of PD controller in ms
+ uint32_t Gfx_PD_Data_limit_a; // Q16
+ uint32_t Gfx_PD_Data_limit_b; // Q16
+ uint32_t Gfx_PD_Data_limit_c; // Q16
+ uint32_t Gfx_PD_Data_error_coeff; // Q16
+ uint32_t Gfx_PD_Data_error_rate_coeff; // Q16
+
+ uint8_t Fclk_ActiveHystLimit;
+ uint8_t Fclk_IdleHystLimit;
+ uint8_t Fclk_FPS;
+ uint8_t Fclk_MinActiveFreqType;
+ uint8_t Fclk_BoosterFreqType;
+ uint8_t Fclk_MinFreqStep; // Minimum delta between current and target frequeny in order for FW to change clock.
+ uint16_t Fclk_MinActiveFreq; // MHz
+ uint16_t Fclk_BoosterFreq; // MHz
+ uint16_t Fclk_PD_Data_time_constant; // Time constant of PD controller in ms
+ uint32_t Fclk_PD_Data_limit_a; // Q16
+ uint32_t Fclk_PD_Data_limit_b; // Q16
+ uint32_t Fclk_PD_Data_limit_c; // Q16
+ uint32_t Fclk_PD_Data_error_coeff; // Q16
+ uint32_t Fclk_PD_Data_error_rate_coeff; // Q16
+
+ uint8_t Mem_ActiveHystLimit;
+ uint8_t Mem_IdleHystLimit;
+ uint8_t Mem_FPS;
+ uint8_t Mem_MinActiveFreqType;
+ uint8_t Mem_BoosterFreqType;
+ uint8_t Mem_MinFreqStep; // Minimum delta between current and target frequeny in order for FW to change clock.
+ uint16_t Mem_MinActiveFreq; // MHz
+ uint16_t Mem_BoosterFreq; // MHz
+ uint16_t Mem_PD_Data_time_constant; // Time constant of PD controller in ms
+ uint32_t Mem_PD_Data_limit_a; // Q16
+ uint32_t Mem_PD_Data_limit_b; // Q16
+ uint32_t Mem_PD_Data_limit_c; // Q16
+ uint32_t Mem_PD_Data_error_coeff; // Q16
+ uint32_t Mem_PD_Data_error_rate_coeff; // Q16
+
+ uint32_t Mem_UpThreshold_Limit; // Q16
+ uint8_t Mem_UpHystLimit;
+ uint8_t Mem_DownHystLimit;
+ uint16_t Mem_Fps;
+
+} DpmActivityMonitorCoeffInt_t;
+
+
+typedef struct {
+ DpmActivityMonitorCoeffInt_t DpmActivityMonitorCoeffInt;
+ uint32_t MmHubPadding[8]; // SMU internal use
+} DpmActivityMonitorCoeffIntExternal_t;
+
+// Workload bits
+#define WORKLOAD_PPLIB_DEFAULT_BIT 0
+#define WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT 1
+#define WORKLOAD_PPLIB_POWER_SAVING_BIT 2
+#define WORKLOAD_PPLIB_VIDEO_BIT 3
+#define WORKLOAD_PPLIB_VR_BIT 4
+#define WORKLOAD_PPLIB_COMPUTE_BIT 5
+#define WORKLOAD_PPLIB_CUSTOM_BIT 6
+#define WORKLOAD_PPLIB_COUNT 7
+
+
+// These defines are used with the following messages:
+// SMC_MSG_TransferTableDram2Smu
+// SMC_MSG_TransferTableSmu2Dram
+
+// Table transfer status
+#define TABLE_TRANSFER_OK 0x0
+#define TABLE_TRANSFER_FAILED 0xFF
+
+// Table types
+#define TABLE_PPTABLE 0
+#define TABLE_WATERMARKS 1
+#define TABLE_AVFS_PSM_DEBUG 2
+#define TABLE_AVFS_FUSE_OVERRIDE 3
+#define TABLE_PMSTATUSLOG 4
+#define TABLE_SMU_METRICS 5
+#define TABLE_DRIVER_SMU_CONFIG 6
+#define TABLE_ACTIVITY_MONITOR_COEFF 7
+#define TABLE_OVERDRIVE 8
+#define TABLE_I2C_COMMANDS 9
+#define TABLE_PACE 10
+#define TABLE_COUNT 11
+
+typedef struct {
+ float FlopsPerByteTable[RLC_PACE_TABLE_NUM_LEVELS];
+} RlcPaceFlopsPerByteOverride_t;
+
+typedef struct {
+ RlcPaceFlopsPerByteOverride_t RlcPaceFlopsPerByteOverride;
+
+ uint32_t MmHubPadding[8]; // SMU internal use
+} RlcPaceFlopsPerByteOverrideExternal_t;
+
+// These defines are used with the SMC_MSG_SetUclkFastSwitch message.
+#define UCLK_SWITCH_SLOW 0
+#define UCLK_SWITCH_FAST 1
+#endif
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_types.h b/drivers/gpu/drm/amd/powerplay/inc/smu_types.h
index ee7dac4693d4..1ef791f36888 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smu_types.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu_types.h
@@ -185,6 +185,8 @@ enum smu_clk_type {
SMU_GFXCLK,
SMU_VCLK,
SMU_DCLK,
+ SMU_VCLK1,
+ SMU_DCLK1,
SMU_ECLK,
SMU_SOCCLK,
SMU_UCLK,
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
index 71f829ab306e..4682a2fd4381 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
@@ -30,6 +30,7 @@
#define SMU11_DRIVER_IF_VERSION_NV10 0x36
#define SMU11_DRIVER_IF_VERSION_NV12 0x33
#define SMU11_DRIVER_IF_VERSION_NV14 0x36
+#define SMU11_DRIVER_IF_VERSION_Sienna_Cichlid 0x30
/* MP Apertures */
#define MP0_Public 0x03800000
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0_7_ppsmc.h b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0_7_ppsmc.h
new file mode 100644
index 000000000000..35dd6072cc45
--- /dev/null
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0_7_ppsmc.h
@@ -0,0 +1,139 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef SMU_V11_0_7_PPSMC_H
+#define SMU_V11_0_7_PPSMC_H
+
+#define PPSMC_VERSION 0x1
+
+// SMU Response Codes:
+#define PPSMC_Result_OK 0x1
+#define PPSMC_Result_Failed 0xFF
+#define PPSMC_Result_UnknownCmd 0xFE
+#define PPSMC_Result_CmdRejectedPrereq 0xFD
+#define PPSMC_Result_CmdRejectedBusy 0xFC
+
+// Message Definitions:
+// BASIC
+#define PPSMC_MSG_TestMessage 0x1
+#define PPSMC_MSG_GetSmuVersion 0x2
+#define PPSMC_MSG_GetDriverIfVersion 0x3
+#define PPSMC_MSG_SetAllowedFeaturesMaskLow 0x4
+#define PPSMC_MSG_SetAllowedFeaturesMaskHigh 0x5
+#define PPSMC_MSG_EnableAllSmuFeatures 0x6
+#define PPSMC_MSG_DisableAllSmuFeatures 0x7
+#define PPSMC_MSG_EnableSmuFeaturesLow 0x8
+#define PPSMC_MSG_EnableSmuFeaturesHigh 0x9
+#define PPSMC_MSG_DisableSmuFeaturesLow 0xA
+#define PPSMC_MSG_DisableSmuFeaturesHigh 0xB
+#define PPSMC_MSG_GetRunningSmuFeaturesLow 0xC
+#define PPSMC_MSG_GetRunningSmuFeaturesHigh 0xD
+#define PPSMC_MSG_SetDriverDramAddrHigh 0xE
+#define PPSMC_MSG_SetDriverDramAddrLow 0xF
+#define PPSMC_MSG_SetToolsDramAddrHigh 0x10
+#define PPSMC_MSG_SetToolsDramAddrLow 0x11
+#define PPSMC_MSG_TransferTableSmu2Dram 0x12
+#define PPSMC_MSG_TransferTableDram2Smu 0x13
+#define PPSMC_MSG_UseDefaultPPTable 0x14
+
+//BACO/BAMACO/BOMACO
+#define PPSMC_MSG_EnterBaco 0x15
+#define PPSMC_MSG_ExitBaco 0x16
+#define PPSMC_MSG_ArmD3 0x17
+#define PPSMC_MSG_BacoAudioD3PME 0x18
+
+//DPM
+#define PPSMC_MSG_SetSoftMinByFreq 0x19
+#define PPSMC_MSG_SetSoftMaxByFreq 0x1A
+#define PPSMC_MSG_SetHardMinByFreq 0x1B
+#define PPSMC_MSG_SetHardMaxByFreq 0x1C
+#define PPSMC_MSG_GetMinDpmFreq 0x1D
+#define PPSMC_MSG_GetMaxDpmFreq 0x1E
+#define PPSMC_MSG_GetDpmFreqByIndex 0x1F
+#define PPSMC_MSG_OverridePcieParameters 0x20
+
+//DramLog Set DramAddrHigh
+#define PPSMC_MSG_DramLogSetDramAddrHigh 0x21
+
+#define PPSMC_MSG_SetWorkloadMask 0x22
+#define PPSMC_MSG_SetUclkFastSwitch 0x23
+#define PPSMC_MSG_GetVoltageByDpm 0x24
+#define PPSMC_MSG_SetVideoFps 0x25
+#define PPSMC_MSG_GetDcModeMaxDpmFreq 0x26
+
+//DramLog Set DramAddrLow
+#define PPSMC_MSG_DramLogSetDramAddrLow 0x27
+
+//Power Gating
+#define PPSMC_MSG_AllowGfxOff 0x28
+#define PPSMC_MSG_DisallowGfxOff 0x29
+#define PPSMC_MSG_PowerUpVcn 0x2A
+#define PPSMC_MSG_PowerDownVcn 0x2B
+#define PPSMC_MSG_PowerUpJpeg 0x2C
+#define PPSMC_MSG_PowerDownJpeg 0x2D
+
+//Resets
+#define PPSMC_MSG_PrepareMp1ForUnload 0x2E
+
+//DramLog Set DramLog SetDramSize
+#define PPSMC_MSG_DramLogSetDramSize 0x2F
+
+#define PPSMC_MSG_Mode1Reset 0x30
+
+//Set SystemVirtual DramAddrHigh
+#define PPSMC_MSG_SetSystemVirtualDramAddrHigh 0x31
+
+//ACDC Power Source
+#define PPSMC_MSG_SetPptLimit 0x32
+#define PPSMC_MSG_GetPptLimit 0x33
+#define PPSMC_MSG_ReenableAcDcInterrupt 0x34
+#define PPSMC_MSG_NotifyPowerSource 0x35
+
+//BTC
+#define PPSMC_MSG_RunDcBtc 0x36
+
+//Set SystemVirtual DramAddrLow
+#define PPSMC_MSG_SetSystemVirtualDramAddrLow 0x38
+
+//Others
+#define PPSMC_MSG_SetMemoryChannelEnable 0x39
+#define PPSMC_MSG_SetDramBitWidth 0x3A
+#define PPSMC_MSG_SetGeminiMode 0x3B
+#define PPSMC_MSG_SetGeminiApertureHigh 0x3C
+#define PPSMC_MSG_SetGeminiApertureLow 0x3D
+
+#define PPSMC_MSG_SetTemperatureInputSelect 0x3E
+#define PPSMC_MSG_SetFwDstatesMask 0x3F
+#define PPSMC_MSG_SetThrottlerMask 0x40
+
+#define PPSMC_MSG_SetExternalClientDfCstateAllow 0x41
+#define PPSMC_MSG_EnableOutOfBandMonTesting 0x42
+#define PPSMC_MSG_SetMGpuFanBoostLimitRpm 0x43
+
+#define PPSMC_MSG_SetNumBadHbmPagesRetired 0x44
+#define PPSMC_MSG_SetGpoFeaturePMask 0x45
+#define PPSMC_MSG_SetSMBUSInterrupt 0x46
+
+#define PPSMC_Message_Count 0x47
+
+#endif
diff --git a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
new file mode 100644
index 000000000000..e034dcd25c70
--- /dev/null
+++ b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
@@ -0,0 +1,2080 @@
+/*
+ * Copyright 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#include "pp_debug.h"
+#include <linux/firmware.h>
+#include <linux/pci.h>
+#include "amdgpu.h"
+#include "amdgpu_smu.h"
+#include "smu_internal.h"
+#include "atomfirmware.h"
+#include "amdgpu_atomfirmware.h"
+#include "smu_v11_0.h"
+#include "smu11_driver_if_sienna_cichlid.h"
+#include "soc15_common.h"
+#include "atom.h"
+#include "sienna_cichlid_ppt.h"
+#include "smu_v11_0_pptable.h"
+#include "smu_v11_0_7_ppsmc.h"
+
+#include "asic_reg/mp/mp_11_0_sh_mask.h"
+
+#define FEATURE_MASK(feature) (1ULL << feature)
+#define SMC_DPM_FEATURE ( \
+ FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) | \
+ FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT))
+
+#define MSG_MAP(msg, index) \
+ [SMU_MSG_##msg] = {1, (index)}
+
+static struct smu_11_0_cmn2aisc_mapping sienna_cichlid_message_map[SMU_MSG_MAX_COUNT] = {
+ MSG_MAP(TestMessage, PPSMC_MSG_TestMessage),
+ MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion),
+ MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion),
+ MSG_MAP(SetAllowedFeaturesMaskLow, PPSMC_MSG_SetAllowedFeaturesMaskLow),
+ MSG_MAP(SetAllowedFeaturesMaskHigh, PPSMC_MSG_SetAllowedFeaturesMaskHigh),
+ MSG_MAP(EnableAllSmuFeatures, PPSMC_MSG_EnableAllSmuFeatures),
+ MSG_MAP(DisableAllSmuFeatures, PPSMC_MSG_DisableAllSmuFeatures),
+ MSG_MAP(EnableSmuFeaturesLow, PPSMC_MSG_EnableSmuFeaturesLow),
+ MSG_MAP(EnableSmuFeaturesHigh, PPSMC_MSG_EnableSmuFeaturesHigh),
+ MSG_MAP(DisableSmuFeaturesLow, PPSMC_MSG_DisableSmuFeaturesLow),
+ MSG_MAP(DisableSmuFeaturesHigh, PPSMC_MSG_DisableSmuFeaturesHigh),
+ MSG_MAP(GetEnabledSmuFeaturesLow, PPSMC_MSG_GetRunningSmuFeaturesLow),
+ MSG_MAP(GetEnabledSmuFeaturesHigh, PPSMC_MSG_GetRunningSmuFeaturesHigh),
+ MSG_MAP(SetWorkloadMask, PPSMC_MSG_SetWorkloadMask),
+ MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit),
+ MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh),
+ MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow),
+ MSG_MAP(SetToolsDramAddrHigh, PPSMC_MSG_SetToolsDramAddrHigh),
+ MSG_MAP(SetToolsDramAddrLow, PPSMC_MSG_SetToolsDramAddrLow),
+ MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram),
+ MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu),
+ MSG_MAP(UseDefaultPPTable, PPSMC_MSG_UseDefaultPPTable),
+ MSG_MAP(EnterBaco, PPSMC_MSG_EnterBaco),
+ MSG_MAP(SetSoftMinByFreq, PPSMC_MSG_SetSoftMinByFreq),
+ MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq),
+ MSG_MAP(SetHardMinByFreq, PPSMC_MSG_SetHardMinByFreq),
+ MSG_MAP(SetHardMaxByFreq, PPSMC_MSG_SetHardMaxByFreq),
+ MSG_MAP(GetMinDpmFreq, PPSMC_MSG_GetMinDpmFreq),
+ MSG_MAP(GetMaxDpmFreq, PPSMC_MSG_GetMaxDpmFreq),
+ MSG_MAP(GetDpmFreqByIndex, PPSMC_MSG_GetDpmFreqByIndex),
+ MSG_MAP(SetGeminiMode, PPSMC_MSG_SetGeminiMode),
+ MSG_MAP(SetGeminiApertureHigh, PPSMC_MSG_SetGeminiApertureHigh),
+ MSG_MAP(SetGeminiApertureLow, PPSMC_MSG_SetGeminiApertureLow),
+ MSG_MAP(OverridePcieParameters, PPSMC_MSG_OverridePcieParameters),
+ MSG_MAP(ReenableAcDcInterrupt, PPSMC_MSG_ReenableAcDcInterrupt),
+ MSG_MAP(NotifyPowerSource, PPSMC_MSG_NotifyPowerSource),
+ MSG_MAP(SetUclkFastSwitch, PPSMC_MSG_SetUclkFastSwitch),
+ MSG_MAP(SetVideoFps, PPSMC_MSG_SetVideoFps),
+ MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload),
+ MSG_MAP(AllowGfxOff, PPSMC_MSG_AllowGfxOff),
+ MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisallowGfxOff),
+ MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit),
+ MSG_MAP(GetDcModeMaxDpmFreq, PPSMC_MSG_GetDcModeMaxDpmFreq),
+ MSG_MAP(ExitBaco, PPSMC_MSG_ExitBaco),
+ MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn),
+ MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn),
+ MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg),
+ MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg),
+ MSG_MAP(BacoAudioD3PME, PPSMC_MSG_BacoAudioD3PME),
+};
+
+static struct smu_11_0_cmn2aisc_mapping sienna_cichlid_clk_map[SMU_CLK_COUNT] = {
+ CLK_MAP(GFXCLK, PPCLK_GFXCLK),
+ CLK_MAP(SCLK, PPCLK_GFXCLK),
+ CLK_MAP(SOCCLK, PPCLK_SOCCLK),
+ CLK_MAP(FCLK, PPCLK_FCLK),
+ CLK_MAP(UCLK, PPCLK_UCLK),
+ CLK_MAP(MCLK, PPCLK_UCLK),
+ CLK_MAP(DCLK, PPCLK_DCLK_0),
+ CLK_MAP(DCLK1, PPCLK_DCLK_0),
+ CLK_MAP(VCLK, PPCLK_VCLK_1),
+ CLK_MAP(VCLK1, PPCLK_VCLK_1),
+ CLK_MAP(DCEFCLK, PPCLK_DCEFCLK),
+ CLK_MAP(DISPCLK, PPCLK_DISPCLK),
+ CLK_MAP(PIXCLK, PPCLK_PIXCLK),
+ CLK_MAP(PHYCLK, PPCLK_PHYCLK),
+};
+
+static struct smu_11_0_cmn2aisc_mapping sienna_cichlid_feature_mask_map[SMU_FEATURE_COUNT] = {
+ FEA_MAP(DPM_PREFETCHER),
+ FEA_MAP(DPM_GFXCLK),
+ FEA_MAP(DPM_UCLK),
+ FEA_MAP(DPM_SOCCLK),
+ FEA_MAP(DPM_MP0CLK),
+ FEA_MAP(DPM_LINK),
+ FEA_MAP(DPM_DCEFCLK),
+ FEA_MAP(MEM_VDDCI_SCALING),
+ FEA_MAP(MEM_MVDD_SCALING),
+ FEA_MAP(DS_GFXCLK),
+ FEA_MAP(DS_SOCCLK),
+ FEA_MAP(DS_LCLK),
+ FEA_MAP(DS_DCEFCLK),
+ FEA_MAP(DS_UCLK),
+ FEA_MAP(GFX_ULV),
+ FEA_MAP(FW_DSTATE),
+ FEA_MAP(GFXOFF),
+ FEA_MAP(BACO),
+ FEA_MAP(RSMU_SMN_CG),
+ FEA_MAP(PPT),
+ FEA_MAP(TDC),
+ FEA_MAP(APCC_PLUS),
+ FEA_MAP(GTHR),
+ FEA_MAP(ACDC),
+ FEA_MAP(VR0HOT),
+ FEA_MAP(VR1HOT),
+ FEA_MAP(FW_CTF),
+ FEA_MAP(FAN_CONTROL),
+ FEA_MAP(THERMAL),
+ FEA_MAP(GFX_DCS),
+ FEA_MAP(RM),
+ FEA_MAP(LED_DISPLAY),
+ FEA_MAP(GFX_SS),
+ FEA_MAP(OUT_OF_BAND_MONITOR),
+ FEA_MAP(TEMP_DEPENDENT_VMIN),
+ FEA_MAP(MMHUB_PG),
+ FEA_MAP(ATHUB_PG),
+};
+
+static struct smu_11_0_cmn2aisc_mapping sienna_cichlid_table_map[SMU_TABLE_COUNT] = {
+ TAB_MAP(PPTABLE),
+ TAB_MAP(WATERMARKS),
+ TAB_MAP(AVFS_PSM_DEBUG),
+ TAB_MAP(AVFS_FUSE_OVERRIDE),
+ TAB_MAP(PMSTATUSLOG),
+ TAB_MAP(SMU_METRICS),
+ TAB_MAP(DRIVER_SMU_CONFIG),
+ TAB_MAP(ACTIVITY_MONITOR_COEFF),
+ TAB_MAP(OVERDRIVE),
+ TAB_MAP(I2C_COMMANDS),
+ TAB_MAP(PACE),
+};
+
+static struct smu_11_0_cmn2aisc_mapping sienna_cichlid_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
+ WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT, WORKLOAD_PPLIB_DEFAULT_BIT),
+ WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D, WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
+ WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING, WORKLOAD_PPLIB_POWER_SAVING_BIT),
+ WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT),
+ WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT),
+ WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_CUSTOM_BIT),
+ WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT),
+};
+
+static int sienna_cichlid_get_smu_msg_index(struct smu_context *smc, uint32_t index)
+{
+ struct smu_11_0_cmn2aisc_mapping mapping;
+
+ if (index >= SMU_MSG_MAX_COUNT)
+ return -EINVAL;
+
+ mapping = sienna_cichlid_message_map[index];
+ if (!(mapping.valid_mapping)) {
+ return -EINVAL;
+ }
+
+ return mapping.map_to;
+}
+
+static int sienna_cichlid_get_smu_clk_index(struct smu_context *smc, uint32_t index)
+{
+ struct smu_11_0_cmn2aisc_mapping mapping;
+
+ if (index >= SMU_CLK_COUNT)
+ return -EINVAL;
+
+ mapping = sienna_cichlid_clk_map[index];
+ if (!(mapping.valid_mapping)) {
+ return -EINVAL;
+ }
+
+ return mapping.map_to;
+}
+
+static int sienna_cichlid_get_smu_feature_index(struct smu_context *smc, uint32_t index)
+{
+ struct smu_11_0_cmn2aisc_mapping mapping;
+
+ if (index >= SMU_FEATURE_COUNT)
+ return -EINVAL;
+
+ mapping = sienna_cichlid_feature_mask_map[index];
+ if (!(mapping.valid_mapping)) {
+ return -EINVAL;
+ }
+
+ return mapping.map_to;
+}
+
+static int sienna_cichlid_get_smu_table_index(struct smu_context *smc, uint32_t index)
+{
+ struct smu_11_0_cmn2aisc_mapping mapping;
+
+ if (index >= SMU_TABLE_COUNT)
+ return -EINVAL;
+
+ mapping = sienna_cichlid_table_map[index];
+ if (!(mapping.valid_mapping)) {
+ return -EINVAL;
+ }
+
+ return mapping.map_to;
+}
+
+static int sienna_cichlid_get_workload_type(struct smu_context *smu, enum PP_SMC_POWER_PROFILE profile)
+{
+ struct smu_11_0_cmn2aisc_mapping mapping;
+
+ if (profile > PP_SMC_POWER_PROFILE_CUSTOM)
+ return -EINVAL;
+
+ mapping = sienna_cichlid_workload_map[profile];
+ if (!(mapping.valid_mapping)) {
+ return -EINVAL;
+ }
+
+ return mapping.map_to;
+}
+
+static int
+sienna_cichlid_get_allowed_feature_mask(struct smu_context *smu,
+ uint32_t *feature_mask, uint32_t num)
+{
+ if (num > 2)
+ return -EINVAL;
+
+ memset(feature_mask, 0, sizeof(uint32_t) * num);
+
+ *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT)
+ | FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT);
+
+ return 0;
+}
+
+static int sienna_cichlid_check_powerplay_table(struct smu_context *smu)
+{
+ return 0;
+}
+
+static int sienna_cichlid_append_powerplay_table(struct smu_context *smu)
+{
+ return 0;
+}
+
+static int sienna_cichlid_store_powerplay_table(struct smu_context *smu)
+{
+ struct smu_11_0_powerplay_table *powerplay_table = NULL;
+ struct smu_table_context *table_context = &smu->smu_table;
+ struct smu_baco_context *smu_baco = &smu->smu_baco;
+
+ if (!table_context->power_play_table)
+ return -EINVAL;
+
+ powerplay_table = table_context->power_play_table;
+
+ memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
+ sizeof(PPTable_t));
+
+ table_context->thermal_controller_type = powerplay_table->thermal_controller_type;
+
+ mutex_lock(&smu_baco->mutex);
+ if (powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_BACO ||
+ powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_MACO)
+ smu_baco->platform_support = true;
+ mutex_unlock(&smu_baco->mutex);
+
+ return 0;
+}
+
+static int sienna_cichlid_tables_init(struct smu_context *smu, struct smu_table *tables)
+{
+ struct smu_table_context *smu_table = &smu->smu_table;
+
+ SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
+ PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
+ SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
+ PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
+ SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
+ PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
+ SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTable_t),
+ PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
+ SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
+ PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
+ SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF,
+ sizeof(DpmActivityMonitorCoeffInt_t), PAGE_SIZE,
+ AMDGPU_GEM_DOMAIN_VRAM);
+
+ smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
+ if (!smu_table->metrics_table)
+ return -ENOMEM;
+ smu_table->metrics_time = 0;
+
+ return 0;
+}
+
+static int sienna_cichlid_get_metrics_table(struct smu_context *smu,
+ SmuMetrics_t *metrics_table)
+{
+ struct smu_table_context *smu_table= &smu->smu_table;
+ int ret = 0;
+
+ mutex_lock(&smu->metrics_lock);
+ if (!smu_table->metrics_time || time_after(jiffies, smu_table->metrics_time + msecs_to_jiffies(100))) {
+ ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0,
+ (void *)smu_table->metrics_table, false);
+ if (ret) {
+ pr_info("Failed to export SMU metrics table!\n");
+ mutex_unlock(&smu->metrics_lock);
+ return ret;
+ }
+ smu_table->metrics_time = jiffies;
+ }
+
+ memcpy(metrics_table, smu_table->metrics_table, sizeof(SmuMetrics_t));
+ mutex_unlock(&smu->metrics_lock);
+
+ return ret;
+}
+
+static int sienna_cichlid_allocate_dpm_context(struct smu_context *smu)
+{
+ struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
+
+ if (smu_dpm->dpm_context)
+ return -EINVAL;
+
+ smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
+ GFP_KERNEL);
+ if (!smu_dpm->dpm_context)
+ return -ENOMEM;
+
+ smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context);
+
+ return 0;
+}
+
+static int sienna_cichlid_set_default_dpm_table(struct smu_context *smu)
+{
+ struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
+ struct smu_table_context *table_context = &smu->smu_table;
+ struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
+ PPTable_t *driver_ppt = NULL;
+
+ driver_ppt = table_context->driver_pptable;
+
+ dpm_context->dpm_tables.soc_table.min = driver_ppt->FreqTableSocclk[0];
+ dpm_context->dpm_tables.soc_table.max = driver_ppt->FreqTableSocclk[NUM_SOCCLK_DPM_LEVELS - 1];
+
+ dpm_context->dpm_tables.gfx_table.min = driver_ppt->FreqTableGfx[0];
+ dpm_context->dpm_tables.gfx_table.max = driver_ppt->FreqTableGfx[NUM_GFXCLK_DPM_LEVELS - 1];
+
+ dpm_context->dpm_tables.uclk_table.min = driver_ppt->FreqTableUclk[0];
+ dpm_context->dpm_tables.uclk_table.max = driver_ppt->FreqTableUclk[NUM_UCLK_DPM_LEVELS - 1];
+
+ dpm_context->dpm_tables.vclk_table.min = driver_ppt->FreqTableVclk[0];
+ dpm_context->dpm_tables.vclk_table.max = driver_ppt->FreqTableVclk[NUM_VCLK_DPM_LEVELS - 1];
+
+ dpm_context->dpm_tables.dclk_table.min = driver_ppt->FreqTableDclk[0];
+ dpm_context->dpm_tables.dclk_table.max = driver_ppt->FreqTableDclk[NUM_DCLK_DPM_LEVELS - 1];
+
+ dpm_context->dpm_tables.dcef_table.min = driver_ppt->FreqTableDcefclk[0];
+ dpm_context->dpm_tables.dcef_table.max = driver_ppt->FreqTableDcefclk[NUM_DCEFCLK_DPM_LEVELS - 1];
+
+ dpm_context->dpm_tables.pixel_table.min = driver_ppt->FreqTablePixclk[0];
+ dpm_context->dpm_tables.pixel_table.max = driver_ppt->FreqTablePixclk[NUM_PIXCLK_DPM_LEVELS - 1];
+
+ dpm_context->dpm_tables.display_table.min = driver_ppt->FreqTableDispclk[0];
+ dpm_context->dpm_tables.display_table.max = driver_ppt->FreqTableDispclk[NUM_DISPCLK_DPM_LEVELS - 1];
+
+ dpm_context->dpm_tables.phy_table.min = driver_ppt->FreqTablePhyclk[0];
+ dpm_context->dpm_tables.phy_table.max = driver_ppt->FreqTablePhyclk[NUM_PHYCLK_DPM_LEVELS - 1];
+
+ return 0;
+}
+
+static int sienna_cichlid_dpm_set_uvd_enable(struct smu_context *smu, bool enable)
+{
+ struct smu_power_context *smu_power = &smu->smu_power;
+ struct smu_power_gate *power_gate = &smu_power->power_gate;
+ int ret = 0;
+
+ if (enable) {
+ /* vcn dpm on is a prerequisite for vcn power gate messages */
+ if (smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
+ ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 1, NULL);
+ if (ret)
+ return ret;
+ }
+ power_gate->vcn_gated = false;
+ } else {
+ if (smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
+ ret = smu_send_smc_msg(smu, SMU_MSG_PowerDownVcn, NULL);
+ if (ret)
+ return ret;
+ }
+ power_gate->vcn_gated = true;
+ }
+
+ return ret;
+}
+
+static int sienna_cichlid_get_current_clk_freq_by_table(struct smu_context *smu,
+ enum smu_clk_type clk_type,
+ uint32_t *value)
+{
+ int ret = 0, clk_id = 0;
+ SmuMetrics_t metrics;
+
+ ret = sienna_cichlid_get_metrics_table(smu, &metrics);
+ if (ret)
+ return ret;
+
+ clk_id = smu_clk_get_index(smu, clk_type);
+ if (clk_id < 0)
+ return clk_id;
+
+ *value = metrics.CurrClock[clk_id];
+
+ return ret;
+}
+
+static bool sienna_cichlid_is_support_fine_grained_dpm(struct smu_context *smu, enum smu_clk_type clk_type)
+{
+ PPTable_t *pptable = smu->smu_table.driver_pptable;
+ DpmDescriptor_t *dpm_desc = NULL;
+ uint32_t clk_index = 0;
+
+ clk_index = smu_clk_get_index(smu, clk_type);
+ dpm_desc = &pptable->DpmDescriptor[clk_index];
+
+ /* 0 - Fine grained DPM, 1 - Discrete DPM */
+ return dpm_desc->SnapToDiscrete == 0 ? true : false;
+}
+
+static int sienna_cichlid_print_clk_levels(struct smu_context *smu,
+ enum smu_clk_type clk_type, char *buf)
+{
+ int i, size = 0, ret = 0;
+ uint32_t cur_value = 0, value = 0, count = 0;
+ uint32_t freq_values[3] = {0};
+ uint32_t mark_index = 0;
+
+ switch (clk_type) {
+ case SMU_GFXCLK:
+ case SMU_SCLK:
+ case SMU_SOCCLK:
+ case SMU_MCLK:
+ case SMU_UCLK:
+ case SMU_FCLK:
+ case SMU_DCEFCLK:
+ ret = smu_get_current_clk_freq(smu, clk_type, &cur_value);
+ if (ret)
+ return size;
+
+ /* 10KHz -> MHz */
+ cur_value = cur_value / 100;
+
+ ret = smu_get_dpm_level_count(smu, clk_type, &count);
+ if (ret)
+ return size;
+
+ if (!sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) {
+ for (i = 0; i < count; i++) {
+ ret = smu_get_dpm_freq_by_index(smu, clk_type, i, &value);
+ if (ret)
+ return size;
+
+ size += sprintf(buf + size, "%d: %uMhz %s\n", i, value,
+ cur_value == value ? "*" : "");
+ }
+ } else {
+ ret = smu_get_dpm_freq_by_index(smu, clk_type, 0, &freq_values[0]);
+ if (ret)
+ return size;
+ ret = smu_get_dpm_freq_by_index(smu, clk_type, count - 1, &freq_values[2]);
+ if (ret)
+ return size;
+
+ freq_values[1] = cur_value;
+ mark_index = cur_value == freq_values[0] ? 0 :
+ cur_value == freq_values[2] ? 2 : 1;
+ if (mark_index != 1)
+ freq_values[1] = (freq_values[0] + freq_values[2]) / 2;
+
+ for (i = 0; i < 3; i++) {
+ size += sprintf(buf + size, "%d: %uMhz %s\n", i, freq_values[i],
+ i == mark_index ? "*" : "");
+ }
+
+ }
+ break;
+ default:
+ break;
+ }
+
+ return size;
+}
+
+static int sienna_cichlid_force_clk_levels(struct smu_context *smu,
+ enum smu_clk_type clk_type, uint32_t mask)
+{
+
+ int ret = 0, size = 0;
+ uint32_t soft_min_level = 0, soft_max_level = 0, min_freq = 0, max_freq = 0;
+
+ soft_min_level = mask ? (ffs(mask) - 1) : 0;
+ soft_max_level = mask ? (fls(mask) - 1) : 0;
+
+ switch (clk_type) {
+ case SMU_GFXCLK:
+ case SMU_SCLK:
+ case SMU_SOCCLK:
+ case SMU_MCLK:
+ case SMU_UCLK:
+ case SMU_DCEFCLK:
+ case SMU_FCLK:
+ ret = smu_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq);
+ if (ret)
+ return size;
+
+ ret = smu_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq);
+ if (ret)
+ return size;
+
+ ret = smu_set_soft_freq_range(smu, clk_type, min_freq, max_freq, false);
+ if (ret)
+ return size;
+ break;
+ default:
+ break;
+ }
+
+ return size;
+}
+
+static int sienna_cichlid_populate_umd_state_clk(struct smu_context *smu)
+{
+ int ret = 0;
+ uint32_t min_sclk_freq = 0, min_mclk_freq = 0;
+
+ ret = smu_get_dpm_freq_range(smu, SMU_SCLK, &min_sclk_freq, NULL, false);
+ if (ret)
+ return ret;
+
+ smu->pstate_sclk = min_sclk_freq * 100;
+
+ ret = smu_get_dpm_freq_range(smu, SMU_MCLK, &min_mclk_freq, NULL, false);
+ if (ret)
+ return ret;
+
+ smu->pstate_mclk = min_mclk_freq * 100;
+
+ return ret;
+}
+
+static int sienna_cichlid_get_clock_by_type_with_latency(struct smu_context *smu,
+ enum smu_clk_type clk_type,
+ struct pp_clock_levels_with_latency *clocks)
+{
+ int ret = 0, i = 0;
+ uint32_t level_count = 0, freq = 0;
+
+ switch (clk_type) {
+ case SMU_GFXCLK:
+ case SMU_DCEFCLK:
+ case SMU_SOCCLK:
+ ret = smu_get_dpm_level_count(smu, clk_type, &level_count);
+ if (ret)
+ return ret;
+
+ level_count = min(level_count, (uint32_t)MAX_NUM_CLOCKS);
+ clocks->num_levels = level_count;
+
+ for (i = 0; i < level_count; i++) {
+ ret = smu_get_dpm_freq_by_index(smu, clk_type, i, &freq);
+ if (ret)
+ return ret;
+
+ clocks->data[i].clocks_in_khz = freq * 1000;
+ clocks->data[i].latency_in_us = 0;
+ }
+ break;
+ default:
+ break;
+ }
+
+ return ret;
+}
+
+static int sienna_cichlid_pre_display_config_changed(struct smu_context *smu)
+{
+ int ret = 0;
+ uint32_t max_freq = 0;
+
+ /* Sienna_Cichlid do not support to change display num currently */
+ return 0;
+#if 0
+ ret = smu_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 0, NULL);
+ if (ret)
+ return ret;
+#endif
+
+ if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
+ ret = smu_get_dpm_freq_range(smu, SMU_UCLK, NULL, &max_freq, false);
+ if (ret)
+ return ret;
+ ret = smu_set_hard_freq_range(smu, SMU_UCLK, 0, max_freq);
+ if (ret)
+ return ret;
+ }
+
+ return ret;
+}
+
+static int sienna_cichlid_display_config_changed(struct smu_context *smu)
+{
+ int ret = 0;
+
+ if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
+ !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
+ ret = smu_write_watermarks_table(smu);
+ if (ret)
+ return ret;
+
+ smu->watermarks_bitmap |= WATERMARKS_LOADED;
+ }
+
+ if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
+ smu_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
+ smu_feature_is_supported(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
+ /* Sienna_Cichlid do not support to change display num currently */
+ ret = 0;
+#if 0
+ ret = smu_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays,
+ smu->display_config->num_display, NULL);
+#endif
+ if (ret)
+ return ret;
+ }
+
+ return ret;
+}
+
+static int sienna_cichlid_force_dpm_limit_value(struct smu_context *smu, bool highest)
+{
+ int ret = 0, i = 0;
+ uint32_t min_freq, max_freq, force_freq;
+ enum smu_clk_type clk_type;
+
+ enum smu_clk_type clks[] = {
+ SMU_GFXCLK,
+ };
+
+ for (i = 0; i < ARRAY_SIZE(clks); i++) {
+ clk_type = clks[i];
+ ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq, &max_freq, false);
+ if (ret)
+ return ret;
+
+ force_freq = highest ? max_freq : min_freq;
+ ret = smu_set_soft_freq_range(smu, clk_type, force_freq, force_freq, false);
+ if (ret)
+ return ret;
+ }
+
+ return ret;
+}
+
+static int sienna_cichlid_unforce_dpm_levels(struct smu_context *smu)
+{
+ int ret = 0, i = 0;
+ uint32_t min_freq, max_freq;
+ enum smu_clk_type clk_type;
+
+ enum smu_clk_type clks[] = {
+ SMU_GFXCLK,
+ };
+
+ for (i = 0; i < ARRAY_SIZE(clks); i++) {
+ clk_type = clks[i];
+ ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq, &max_freq, false);
+ if (ret)
+ return ret;
+
+ ret = smu_set_soft_freq_range(smu, clk_type, min_freq, max_freq, false);
+ if (ret)
+ return ret;
+ }
+
+ return ret;
+}
+
+static int sienna_cichlid_get_gpu_power(struct smu_context *smu, uint32_t *value)
+{
+ int ret = 0;
+ SmuMetrics_t metrics;
+
+ if (!value)
+ return -EINVAL;
+
+ ret = sienna_cichlid_get_metrics_table(smu, &metrics);
+ if (ret)
+ return ret;
+
+ *value = metrics.AverageSocketPower << 8;
+
+ return 0;
+}
+
+static int sienna_cichlid_get_current_activity_percent(struct smu_context *smu,
+ enum amd_pp_sensors sensor,
+ uint32_t *value)
+{
+ int ret = 0;
+ SmuMetrics_t metrics;
+
+ if (!value)
+ return -EINVAL;
+
+ ret = sienna_cichlid_get_metrics_table(smu, &metrics);
+ if (ret)
+ return ret;
+
+ switch (sensor) {
+ case AMDGPU_PP_SENSOR_GPU_LOAD:
+ *value = metrics.AverageGfxActivity;
+ break;
+ case AMDGPU_PP_SENSOR_MEM_LOAD:
+ *value = metrics.AverageUclkActivity;
+ break;
+ default:
+ pr_err("Invalid sensor for retrieving clock activity\n");
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static bool sienna_cichlid_is_dpm_running(struct smu_context *smu)
+{
+ int ret = 0;
+ uint32_t feature_mask[2];
+ unsigned long feature_enabled;
+ ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
+ feature_enabled = (unsigned long)((uint64_t)feature_mask[0] |
+ ((uint64_t)feature_mask[1] << 32));
+ return !!(feature_enabled & SMC_DPM_FEATURE);
+}
+
+static int sienna_cichlid_get_fan_speed_rpm(struct smu_context *smu,
+ uint32_t *speed)
+{
+ SmuMetrics_t metrics;
+ int ret = 0;
+
+ if (!speed)
+ return -EINVAL;
+
+ ret = sienna_cichlid_get_metrics_table(smu, &metrics);
+ if (ret)
+ return ret;
+
+ *speed = metrics.CurrFanSpeed;
+
+ return ret;
+}
+
+static int sienna_cichlid_get_fan_speed_percent(struct smu_context *smu,
+ uint32_t *speed)
+{
+ int ret = 0;
+ uint32_t percent = 0;
+ uint32_t current_rpm;
+ PPTable_t *pptable = smu->smu_table.driver_pptable;
+
+ ret = sienna_cichlid_get_fan_speed_rpm(smu, ¤t_rpm);
+ if (ret)
+ return ret;
+
+ percent = current_rpm * 100 / pptable->FanMaximumRpm;
+ *speed = percent > 100 ? 100 : percent;
+
+ return ret;
+}
+
+static int sienna_cichlid_get_power_profile_mode(struct smu_context *smu, char *buf)
+{
+ DpmActivityMonitorCoeffInt_t activity_monitor;
+ uint32_t i, size = 0;
+ int16_t workload_type = 0;
+ static const char *profile_name[] = {
+ "BOOTUP_DEFAULT",
+ "3D_FULL_SCREEN",
+ "POWER_SAVING",
+ "VIDEO",
+ "VR",
+ "COMPUTE",
+ "CUSTOM"};
+ static const char *title[] = {
+ "PROFILE_INDEX(NAME)",
+ "CLOCK_TYPE(NAME)",
+ "FPS",
+ "MinFreqType",
+ "MinActiveFreqType",
+ "MinActiveFreq",
+ "BoosterFreqType",
+ "BoosterFreq",
+ "PD_Data_limit_c",
+ "PD_Data_error_coeff",
+ "PD_Data_error_rate_coeff"};
+ int result = 0;
+
+ if (!buf)
+ return -EINVAL;
+
+ size += sprintf(buf + size, "%16s %s %s %s %s %s %s %s %s %s %s\n",
+ title[0], title[1], title[2], title[3], title[4], title[5],
+ title[6], title[7], title[8], title[9], title[10]);
+
+ for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
+ /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
+ workload_type = smu_workload_get_type(smu, i);
+ if (workload_type < 0)
+ return -EINVAL;
+
+ result = smu_update_table(smu,
+ SMU_TABLE_ACTIVITY_MONITOR_COEFF, workload_type,
+ (void *)(&activity_monitor), false);
+ if (result) {
+ pr_err("[%s] Failed to get activity monitor!", __func__);
+ return result;
+ }
+
+ size += sprintf(buf + size, "%2d %14s%s:\n",
+ i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
+
+ size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
+ " ",
+ 0,
+ "GFXCLK",
+ activity_monitor.Gfx_FPS,
+ activity_monitor.Gfx_MinFreqStep,
+ activity_monitor.Gfx_MinActiveFreqType,
+ activity_monitor.Gfx_MinActiveFreq,
+ activity_monitor.Gfx_BoosterFreqType,
+ activity_monitor.Gfx_BoosterFreq,
+ activity_monitor.Gfx_PD_Data_limit_c,
+ activity_monitor.Gfx_PD_Data_error_coeff,
+ activity_monitor.Gfx_PD_Data_error_rate_coeff);
+
+ size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
+ " ",
+ 1,
+ "SOCCLK",
+ activity_monitor.Fclk_FPS,
+ activity_monitor.Fclk_MinFreqStep,
+ activity_monitor.Fclk_MinActiveFreqType,
+ activity_monitor.Fclk_MinActiveFreq,
+ activity_monitor.Fclk_BoosterFreqType,
+ activity_monitor.Fclk_BoosterFreq,
+ activity_monitor.Fclk_PD_Data_limit_c,
+ activity_monitor.Fclk_PD_Data_error_coeff,
+ activity_monitor.Fclk_PD_Data_error_rate_coeff);
+
+ size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
+ " ",
+ 2,
+ "MEMLK",
+ activity_monitor.Mem_FPS,
+ activity_monitor.Mem_MinFreqStep,
+ activity_monitor.Mem_MinActiveFreqType,
+ activity_monitor.Mem_MinActiveFreq,
+ activity_monitor.Mem_BoosterFreqType,
+ activity_monitor.Mem_BoosterFreq,
+ activity_monitor.Mem_PD_Data_limit_c,
+ activity_monitor.Mem_PD_Data_error_coeff,
+ activity_monitor.Mem_PD_Data_error_rate_coeff);
+ }
+
+ return size;
+}
+
+static int sienna_cichlid_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size)
+{
+ DpmActivityMonitorCoeffInt_t activity_monitor;
+ int workload_type, ret = 0;
+
+ smu->power_profile_mode = input[size];
+
+ if (smu->power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
+ pr_err("Invalid power profile mode %d\n", smu->power_profile_mode);
+ return -EINVAL;
+ }
+
+ if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
+ if (size < 0)
+ return -EINVAL;
+
+ ret = smu_update_table(smu,
+ SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
+ (void *)(&activity_monitor), false);
+ if (ret) {
+ pr_err("[%s] Failed to get activity monitor!", __func__);
+ return ret;
+ }
+
+ switch (input[0]) {
+ case 0: /* Gfxclk */
+ activity_monitor.Gfx_FPS = input[1];
+ activity_monitor.Gfx_MinFreqStep = input[2];
+ activity_monitor.Gfx_MinActiveFreqType = input[3];
+ activity_monitor.Gfx_MinActiveFreq = input[4];
+ activity_monitor.Gfx_BoosterFreqType = input[5];
+ activity_monitor.Gfx_BoosterFreq = input[6];
+ activity_monitor.Gfx_PD_Data_limit_c = input[7];
+ activity_monitor.Gfx_PD_Data_error_coeff = input[8];
+ activity_monitor.Gfx_PD_Data_error_rate_coeff = input[9];
+ break;
+ case 1: /* Socclk */
+ activity_monitor.Fclk_FPS = input[1];
+ activity_monitor.Fclk_MinFreqStep = input[2];
+ activity_monitor.Fclk_MinActiveFreqType = input[3];
+ activity_monitor.Fclk_MinActiveFreq = input[4];
+ activity_monitor.Fclk_BoosterFreqType = input[5];
+ activity_monitor.Fclk_BoosterFreq = input[6];
+ activity_monitor.Fclk_PD_Data_limit_c = input[7];
+ activity_monitor.Fclk_PD_Data_error_coeff = input[8];
+ activity_monitor.Fclk_PD_Data_error_rate_coeff = input[9];
+ break;
+ case 2: /* Memlk */
+ activity_monitor.Mem_FPS = input[1];
+ activity_monitor.Mem_MinFreqStep = input[2];
+ activity_monitor.Mem_MinActiveFreqType = input[3];
+ activity_monitor.Mem_MinActiveFreq = input[4];
+ activity_monitor.Mem_BoosterFreqType = input[5];
+ activity_monitor.Mem_BoosterFreq = input[6];
+ activity_monitor.Mem_PD_Data_limit_c = input[7];
+ activity_monitor.Mem_PD_Data_error_coeff = input[8];
+ activity_monitor.Mem_PD_Data_error_rate_coeff = input[9];
+ break;
+ }
+
+ ret = smu_update_table(smu,
+ SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
+ (void *)(&activity_monitor), true);
+ if (ret) {
+ pr_err("[%s] Failed to set activity monitor!", __func__);
+ return ret;
+ }
+ }
+
+ /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
+ workload_type = smu_workload_get_type(smu, smu->power_profile_mode);
+ if (workload_type < 0)
+ return -EINVAL;
+ smu_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,
+ 1 << workload_type, NULL);
+
+ return ret;
+}
+
+static int sienna_cichlid_get_profiling_clk_mask(struct smu_context *smu,
+ enum amd_dpm_forced_level level,
+ uint32_t *sclk_mask,
+ uint32_t *mclk_mask,
+ uint32_t *soc_mask)
+{
+ int ret = 0;
+ uint32_t level_count = 0;
+
+ if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
+ if (sclk_mask)
+ *sclk_mask = 0;
+ } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
+ if (mclk_mask)
+ *mclk_mask = 0;
+ } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
+ if(sclk_mask) {
+ ret = smu_get_dpm_level_count(smu, SMU_SCLK, &level_count);
+ if (ret)
+ return ret;
+ *sclk_mask = level_count - 1;
+ }
+
+ if(mclk_mask) {
+ ret = smu_get_dpm_level_count(smu, SMU_MCLK, &level_count);
+ if (ret)
+ return ret;
+ *mclk_mask = level_count - 1;
+ }
+
+ if(soc_mask) {
+ ret = smu_get_dpm_level_count(smu, SMU_SOCCLK, &level_count);
+ if (ret)
+ return ret;
+ *soc_mask = level_count - 1;
+ }
+ }
+
+ return ret;
+}
+
+static int sienna_cichlid_notify_smc_display_config(struct smu_context *smu)
+{
+ struct smu_clocks min_clocks = {0};
+ struct pp_display_clock_request clock_req;
+ int ret = 0;
+
+ min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk;
+ min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk;
+ min_clocks.memory_clock = smu->display_config->min_mem_set_clock;
+
+ if (smu_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
+ clock_req.clock_type = amd_pp_dcef_clock;
+ clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10;
+
+ ret = smu_v11_0_display_clock_voltage_request(smu, &clock_req);
+ if (!ret) {
+ if (smu_feature_is_supported(smu, SMU_FEATURE_DS_DCEFCLK_BIT)) {
+ pr_err("Attempt to set divider for DCEFCLK Failed as it not support currently!");
+ return ret;
+ }
+ } else {
+ pr_info("Attempt to set Hard Min for DCEFCLK Failed!");
+ }
+ }
+
+ if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
+ ret = smu_set_hard_freq_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0);
+ if (ret) {
+ pr_err("[%s] Set hard min uclk failed!", __func__);
+ return ret;
+ }
+ }
+
+ return 0;
+}
+
+static int sienna_cichlid_set_watermarks_table(struct smu_context *smu,
+ void *watermarks, struct
+ dm_pp_wm_sets_with_clock_ranges_soc15
+ *clock_ranges)
+{
+ int i;
+ Watermarks_t *table = watermarks;
+
+ if (!table || !clock_ranges)
+ return -EINVAL;
+
+ if (clock_ranges->num_wm_dmif_sets > 4 ||
+ clock_ranges->num_wm_mcif_sets > 4)
+ return -EINVAL;
+
+ for (i = 0; i < clock_ranges->num_wm_dmif_sets; i++) {
+ table->WatermarkRow[1][i].MinClock =
+ cpu_to_le16((uint16_t)
+ (clock_ranges->wm_dmif_clocks_ranges[i].wm_min_dcfclk_clk_in_khz /
+ 1000));
+ table->WatermarkRow[1][i].MaxClock =
+ cpu_to_le16((uint16_t)
+ (clock_ranges->wm_dmif_clocks_ranges[i].wm_max_dcfclk_clk_in_khz /
+ 1000));
+ table->WatermarkRow[1][i].MinUclk =
+ cpu_to_le16((uint16_t)
+ (clock_ranges->wm_dmif_clocks_ranges[i].wm_min_mem_clk_in_khz /
+ 1000));
+ table->WatermarkRow[1][i].MaxUclk =
+ cpu_to_le16((uint16_t)
+ (clock_ranges->wm_dmif_clocks_ranges[i].wm_max_mem_clk_in_khz /
+ 1000));
+ table->WatermarkRow[1][i].WmSetting = (uint8_t)
+ clock_ranges->wm_dmif_clocks_ranges[i].wm_set_id;
+ }
+
+ for (i = 0; i < clock_ranges->num_wm_mcif_sets; i++) {
+ table->WatermarkRow[0][i].MinClock =
+ cpu_to_le16((uint16_t)
+ (clock_ranges->wm_mcif_clocks_ranges[i].wm_min_socclk_clk_in_khz /
+ 1000));
+ table->WatermarkRow[0][i].MaxClock =
+ cpu_to_le16((uint16_t)
+ (clock_ranges->wm_mcif_clocks_ranges[i].wm_max_socclk_clk_in_khz /
+ 1000));
+ table->WatermarkRow[0][i].MinUclk =
+ cpu_to_le16((uint16_t)
+ (clock_ranges->wm_mcif_clocks_ranges[i].wm_min_mem_clk_in_khz /
+ 1000));
+ table->WatermarkRow[0][i].MaxUclk =
+ cpu_to_le16((uint16_t)
+ (clock_ranges->wm_mcif_clocks_ranges[i].wm_max_mem_clk_in_khz /
+ 1000));
+ table->WatermarkRow[0][i].WmSetting = (uint8_t)
+ clock_ranges->wm_mcif_clocks_ranges[i].wm_set_id;
+ }
+
+ return 0;
+}
+
+static int sienna_cichlid_thermal_get_temperature(struct smu_context *smu,
+ enum amd_pp_sensors sensor,
+ uint32_t *value)
+{
+ SmuMetrics_t metrics;
+ int ret = 0;
+
+ if (!value)
+ return -EINVAL;
+
+ ret = sienna_cichlid_get_metrics_table(smu, &metrics);
+ if (ret)
+ return ret;
+
+ switch (sensor) {
+ case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
+ *value = metrics.TemperatureHotspot *
+ SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
+ break;
+ case AMDGPU_PP_SENSOR_EDGE_TEMP:
+ *value = metrics.TemperatureEdge *
+ SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
+ break;
+ case AMDGPU_PP_SENSOR_MEM_TEMP:
+ *value = metrics.TemperatureMem *
+ SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
+ break;
+ default:
+ pr_err("Invalid sensor for retrieving temp\n");
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int sienna_cichlid_read_sensor(struct smu_context *smu,
+ enum amd_pp_sensors sensor,
+ void *data, uint32_t *size)
+{
+ int ret = 0;
+ struct smu_table_context *table_context = &smu->smu_table;
+ PPTable_t *pptable = table_context->driver_pptable;
+
+ if(!data || !size)
+ return -EINVAL;
+
+ mutex_lock(&smu->sensor_lock);
+ switch (sensor) {
+ case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
+ *(uint32_t *)data = pptable->FanMaximumRpm;
+ *size = 4;
+ break;
+ case AMDGPU_PP_SENSOR_MEM_LOAD:
+ case AMDGPU_PP_SENSOR_GPU_LOAD:
+ ret = sienna_cichlid_get_current_activity_percent(smu, sensor, (uint32_t *)data);
+ *size = 4;
+ break;
+ case AMDGPU_PP_SENSOR_GPU_POWER:
+ ret = sienna_cichlid_get_gpu_power(smu, (uint32_t *)data);
+ *size = 4;
+ break;
+ case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
+ case AMDGPU_PP_SENSOR_EDGE_TEMP:
+ case AMDGPU_PP_SENSOR_MEM_TEMP:
+ ret = sienna_cichlid_thermal_get_temperature(smu, sensor, (uint32_t *)data);
+ *size = 4;
+ break;
+ default:
+ ret = smu_v11_0_read_sensor(smu, sensor, data, size);
+ }
+ mutex_unlock(&smu->sensor_lock);
+
+ return ret;
+}
+
+static int sienna_cichlid_get_uclk_dpm_states(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states)
+{
+ uint32_t num_discrete_levels = 0;
+ uint16_t *dpm_levels = NULL;
+ uint16_t i = 0;
+ struct smu_table_context *table_context = &smu->smu_table;
+ PPTable_t *driver_ppt = NULL;
+
+ if (!clocks_in_khz || !num_states || !table_context->driver_pptable)
+ return -EINVAL;
+
+ driver_ppt = table_context->driver_pptable;
+ num_discrete_levels = driver_ppt->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels;
+ dpm_levels = driver_ppt->FreqTableUclk;
+
+ if (num_discrete_levels == 0 || dpm_levels == NULL)
+ return -EINVAL;
+
+ *num_states = num_discrete_levels;
+ for (i = 0; i < num_discrete_levels; i++) {
+ /* convert to khz */
+ *clocks_in_khz = (*dpm_levels) * 1000;
+ clocks_in_khz++;
+ dpm_levels++;
+ }
+
+ return 0;
+}
+
+static int sienna_cichlid_get_thermal_temperature_range(struct smu_context *smu,
+ struct smu_temperature_range *range)
+{
+ struct smu_table_context *table_context = &smu->smu_table;
+ struct smu_11_0_powerplay_table *powerplay_table = table_context->power_play_table;
+
+ if (!range || !powerplay_table)
+ return -EINVAL;
+
+ range->max = powerplay_table->software_shutdown_temp *
+ SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
+
+ return 0;
+}
+
+static int sienna_cichlid_display_disable_memory_clock_switch(struct smu_context *smu,
+ bool disable_memory_clock_switch)
+{
+ int ret = 0;
+ struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks =
+ (struct smu_11_0_max_sustainable_clocks *)
+ smu->smu_table.max_sustainable_clocks;
+ uint32_t min_memory_clock = smu->hard_min_uclk_req_from_dal;
+ uint32_t max_memory_clock = max_sustainable_clocks->uclock;
+
+ if(smu->disable_uclk_switch == disable_memory_clock_switch)
+ return 0;
+
+ if(disable_memory_clock_switch)
+ ret = smu_set_hard_freq_range(smu, SMU_UCLK, max_memory_clock, 0);
+ else
+ ret = smu_set_hard_freq_range(smu, SMU_UCLK, min_memory_clock, 0);
+
+ if(!ret)
+ smu->disable_uclk_switch = disable_memory_clock_switch;
+
+ return ret;
+}
+
+static int sienna_cichlid_get_power_limit(struct smu_context *smu,
+ uint32_t *limit,
+ bool cap)
+{
+ PPTable_t *pptable = smu->smu_table.driver_pptable;
+ uint32_t asic_default_power_limit = 0;
+ int ret = 0;
+ int power_src;
+
+ if (!smu->power_limit) {
+ if (smu_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
+ power_src = smu_power_get_index(smu, SMU_POWER_SOURCE_AC);
+ if (power_src < 0)
+ return -EINVAL;
+
+ ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetPptLimit,
+ power_src << 16, &asic_default_power_limit);
+ if (ret) {
+ pr_err("[%s] get PPT limit failed!", __func__);
+ return ret;
+ }
+ } else {
+ /* the last hope to figure out the ppt limit */
+ if (!pptable) {
+ pr_err("Cannot get PPT limit due to pptable missing!");
+ return -EINVAL;
+ }
+ asic_default_power_limit =
+ pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0];
+ }
+
+ smu->power_limit = asic_default_power_limit;
+ }
+
+ if (cap)
+ *limit = smu_v11_0_get_max_power_limit(smu);
+ else
+ *limit = smu->power_limit;
+
+ return 0;
+}
+
+static void sienna_cichlid_dump_pptable(struct smu_context *smu)
+{
+ struct smu_table_context *table_context = &smu->smu_table;
+ PPTable_t *pptable = table_context->driver_pptable;
+ int i;
+
+ pr_info("Dumped PPTable:\n");
+
+ pr_info("Version = 0x%08x\n", pptable->Version);
+ pr_info("FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0]);
+ pr_info("FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1]);
+
+ for (i = 0; i < PPT_THROTTLER_COUNT; i++) {
+ pr_info("SocketPowerLimitAc[%d] = 0x%x\n", i, pptable->SocketPowerLimitAc[i]);
+ pr_info("SocketPowerLimitAcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitAcTau[i]);
+ pr_info("SocketPowerLimitDc[%d] = 0x%x\n", i, pptable->SocketPowerLimitDc[i]);
+ pr_info("SocketPowerLimitDcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitDcTau[i]);
+ }
+
+ for (i = 0; i < TDC_THROTTLER_COUNT; i++) {
+ pr_info("TdcLimit[%d] = 0x%x\n", i, pptable->TdcLimit[i]);
+ pr_info("TdcLimitTau[%d] = 0x%x\n", i, pptable->TdcLimitTau[i]);
+ }
+
+ for (i = 0; i < TEMP_COUNT; i++) {
+ pr_info("TemperatureLimit[%d] = 0x%x\n", i, pptable->TemperatureLimit[i]);
+ }
+
+ pr_info("FitLimit = 0x%x\n", pptable->FitLimit);
+ pr_info("TotalPowerConfig = 0x%x\n", pptable->TotalPowerConfig);
+ pr_info("TotalPowerPadding[0] = 0x%x\n", pptable->TotalPowerPadding[0]);
+ pr_info("TotalPowerPadding[1] = 0x%x\n", pptable->TotalPowerPadding[1]);
+ pr_info("TotalPowerPadding[2] = 0x%x\n", pptable->TotalPowerPadding[2]);
+
+ pr_info("ApccPlusResidencyLimit = 0x%x\n", pptable->ApccPlusResidencyLimit);
+ for (i = 0; i < NUM_SMNCLK_DPM_LEVELS; i++) {
+ pr_info("SmnclkDpmFreq[%d] = 0x%x\n", i, pptable->SmnclkDpmFreq[i]);
+ pr_info("SmnclkDpmVoltage[%d] = 0x%x\n", i, pptable->SmnclkDpmVoltage[i]);
+ }
+ pr_info("PaddingAPCC[0] = 0x%x\n", pptable->PaddingAPCC[0]);
+ pr_info("PaddingAPCC[1] = 0x%x\n", pptable->PaddingAPCC[1]);
+ pr_info("PaddingAPCC[2] = 0x%x\n", pptable->PaddingAPCC[2]);
+ pr_info("PaddingAPCC[3] = 0x%x\n", pptable->PaddingAPCC[3]);
+
+ pr_info("ThrottlerControlMask = 0x%x\n", pptable->ThrottlerControlMask);
+
+ pr_info("FwDStateMask = 0x%x\n", pptable->FwDStateMask);
+
+ pr_info("UlvVoltageOffsetSoc = 0x%x\n", pptable->UlvVoltageOffsetSoc);
+ pr_info("UlvVoltageOffsetGfx = 0x%x\n", pptable->UlvVoltageOffsetGfx);
+ pr_info("MinVoltageUlvGfx = 0x%x\n", pptable->MinVoltageUlvGfx);
+ pr_info("MinVoltageUlvSoc = 0x%x\n", pptable->MinVoltageUlvSoc);
+
+ pr_info("SocLIVmin = 0x%x\n", pptable->SocLIVmin);
+ pr_info("PaddingLIVmin = 0x%x\n", pptable->PaddingLIVmin);
+
+ pr_info("GceaLinkMgrIdleThreshold = 0x%x\n", pptable->GceaLinkMgrIdleThreshold);
+ pr_info("paddingRlcUlvParams[0] = 0x%x\n", pptable->paddingRlcUlvParams[0]);
+ pr_info("paddingRlcUlvParams[1] = 0x%x\n", pptable->paddingRlcUlvParams[1]);
+ pr_info("paddingRlcUlvParams[2] = 0x%x\n", pptable->paddingRlcUlvParams[2]);
+
+ pr_info("MinVoltageGfx = 0x%x\n", pptable->MinVoltageGfx);
+ pr_info("MinVoltageSoc = 0x%x\n", pptable->MinVoltageSoc);
+ pr_info("MaxVoltageGfx = 0x%x\n", pptable->MaxVoltageGfx);
+ pr_info("MaxVoltageSoc = 0x%x\n", pptable->MaxVoltageSoc);
+
+ pr_info("LoadLineResistanceGfx = 0x%x\n", pptable->LoadLineResistanceGfx);
+ pr_info("LoadLineResistanceSoc = 0x%x\n", pptable->LoadLineResistanceSoc);
+
+ pr_info("VDDGFX_TVmin = 0x%x\n", pptable->VDDGFX_TVmin);
+ pr_info("VDDSOC_TVmin = 0x%x\n", pptable->VDDSOC_TVmin);
+ pr_info("VDDGFX_Vmin_HiTemp = 0x%x\n", pptable->VDDGFX_Vmin_HiTemp);
+ pr_info("VDDGFX_Vmin_LoTemp = 0x%x\n", pptable->VDDGFX_Vmin_LoTemp);
+ pr_info("VDDSOC_Vmin_HiTemp = 0x%x\n", pptable->VDDSOC_Vmin_HiTemp);
+ pr_info("VDDSOC_Vmin_LoTemp = 0x%x\n", pptable->VDDSOC_Vmin_LoTemp);
+ pr_info("VDDGFX_TVminHystersis = 0x%x\n", pptable->VDDGFX_TVminHystersis);
+ pr_info("VDDSOC_TVminHystersis = 0x%x\n", pptable->VDDSOC_TVminHystersis);
+
+ pr_info("[PPCLK_GFXCLK]\n"
+ " .VoltageMode = 0x%02x\n"
+ " .SnapToDiscrete = 0x%02x\n"
+ " .NumDiscreteLevels = 0x%02x\n"
+ " .padding = 0x%02x\n"
+ " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
+ " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
+ " .SsFmin = 0x%04x\n"
+ " .Padding_16 = 0x%04x\n",
+ pptable->DpmDescriptor[PPCLK_GFXCLK].VoltageMode,
+ pptable->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete,
+ pptable->DpmDescriptor[PPCLK_GFXCLK].NumDiscreteLevels,
+ pptable->DpmDescriptor[PPCLK_GFXCLK].Padding,
+ pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.m,
+ pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.b,
+ pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.a,
+ pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.b,
+ pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.c,
+ pptable->DpmDescriptor[PPCLK_GFXCLK].SsFmin,
+ pptable->DpmDescriptor[PPCLK_GFXCLK].Padding16);
+
+ pr_info("[PPCLK_SOCCLK]\n"
+ " .VoltageMode = 0x%02x\n"
+ " .SnapToDiscrete = 0x%02x\n"
+ " .NumDiscreteLevels = 0x%02x\n"
+ " .padding = 0x%02x\n"
+ " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
+ " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
+ " .SsFmin = 0x%04x\n"
+ " .Padding_16 = 0x%04x\n",
+ pptable->DpmDescriptor[PPCLK_SOCCLK].VoltageMode,
+ pptable->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete,
+ pptable->DpmDescriptor[PPCLK_SOCCLK].NumDiscreteLevels,
+ pptable->DpmDescriptor[PPCLK_SOCCLK].Padding,
+ pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.m,
+ pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.b,
+ pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.a,
+ pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.b,
+ pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.c,
+ pptable->DpmDescriptor[PPCLK_SOCCLK].SsFmin,
+ pptable->DpmDescriptor[PPCLK_SOCCLK].Padding16);
+
+ pr_info("[PPCLK_UCLK]\n"
+ " .VoltageMode = 0x%02x\n"
+ " .SnapToDiscrete = 0x%02x\n"
+ " .NumDiscreteLevels = 0x%02x\n"
+ " .padding = 0x%02x\n"
+ " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
+ " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
+ " .SsFmin = 0x%04x\n"
+ " .Padding_16 = 0x%04x\n",
+ pptable->DpmDescriptor[PPCLK_UCLK].VoltageMode,
+ pptable->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete,
+ pptable->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels,
+ pptable->DpmDescriptor[PPCLK_UCLK].Padding,
+ pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.m,
+ pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.b,
+ pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.a,
+ pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.b,
+ pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.c,
+ pptable->DpmDescriptor[PPCLK_UCLK].SsFmin,
+ pptable->DpmDescriptor[PPCLK_UCLK].Padding16);
+
+ pr_info("[PPCLK_FCLK]\n"
+ " .VoltageMode = 0x%02x\n"
+ " .SnapToDiscrete = 0x%02x\n"
+ " .NumDiscreteLevels = 0x%02x\n"
+ " .padding = 0x%02x\n"
+ " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
+ " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
+ " .SsFmin = 0x%04x\n"
+ " .Padding_16 = 0x%04x\n",
+ pptable->DpmDescriptor[PPCLK_FCLK].VoltageMode,
+ pptable->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete,
+ pptable->DpmDescriptor[PPCLK_FCLK].NumDiscreteLevels,
+ pptable->DpmDescriptor[PPCLK_FCLK].Padding,
+ pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.m,
+ pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.b,
+ pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.a,
+ pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.b,
+ pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.c,
+ pptable->DpmDescriptor[PPCLK_FCLK].SsFmin,
+ pptable->DpmDescriptor[PPCLK_FCLK].Padding16);
+
+ pr_info("[PPCLK_DCLK_0]\n"
+ " .VoltageMode = 0x%02x\n"
+ " .SnapToDiscrete = 0x%02x\n"
+ " .NumDiscreteLevels = 0x%02x\n"
+ " .padding = 0x%02x\n"
+ " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
+ " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
+ " .SsFmin = 0x%04x\n"
+ " .Padding_16 = 0x%04x\n",
+ pptable->DpmDescriptor[PPCLK_DCLK_0].VoltageMode,
+ pptable->DpmDescriptor[PPCLK_DCLK_0].SnapToDiscrete,
+ pptable->DpmDescriptor[PPCLK_DCLK_0].NumDiscreteLevels,
+ pptable->DpmDescriptor[PPCLK_DCLK_0].Padding,
+ pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.m,
+ pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.b,
+ pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.a,
+ pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.b,
+ pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.c,
+ pptable->DpmDescriptor[PPCLK_DCLK_0].SsFmin,
+ pptable->DpmDescriptor[PPCLK_DCLK_0].Padding16);
+
+ pr_info("[PPCLK_VCLK_0]\n"
+ " .VoltageMode = 0x%02x\n"
+ " .SnapToDiscrete = 0x%02x\n"
+ " .NumDiscreteLevels = 0x%02x\n"
+ " .padding = 0x%02x\n"
+ " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
+ " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
+ " .SsFmin = 0x%04x\n"
+ " .Padding_16 = 0x%04x\n",
+ pptable->DpmDescriptor[PPCLK_VCLK_0].VoltageMode,
+ pptable->DpmDescriptor[PPCLK_VCLK_0].SnapToDiscrete,
+ pptable->DpmDescriptor[PPCLK_VCLK_0].NumDiscreteLevels,
+ pptable->DpmDescriptor[PPCLK_VCLK_0].Padding,
+ pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.m,
+ pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.b,
+ pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.a,
+ pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.b,
+ pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.c,
+ pptable->DpmDescriptor[PPCLK_VCLK_0].SsFmin,
+ pptable->DpmDescriptor[PPCLK_VCLK_0].Padding16);
+
+ pr_info("[PPCLK_DCLK_1]\n"
+ " .VoltageMode = 0x%02x\n"
+ " .SnapToDiscrete = 0x%02x\n"
+ " .NumDiscreteLevels = 0x%02x\n"
+ " .padding = 0x%02x\n"
+ " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
+ " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
+ " .SsFmin = 0x%04x\n"
+ " .Padding_16 = 0x%04x\n",
+ pptable->DpmDescriptor[PPCLK_DCLK_1].VoltageMode,
+ pptable->DpmDescriptor[PPCLK_DCLK_1].SnapToDiscrete,
+ pptable->DpmDescriptor[PPCLK_DCLK_1].NumDiscreteLevels,
+ pptable->DpmDescriptor[PPCLK_DCLK_1].Padding,
+ pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.m,
+ pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.b,
+ pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.a,
+ pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.b,
+ pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.c,
+ pptable->DpmDescriptor[PPCLK_DCLK_1].SsFmin,
+ pptable->DpmDescriptor[PPCLK_DCLK_1].Padding16);
+
+ pr_info("[PPCLK_VCLK_1]\n"
+ " .VoltageMode = 0x%02x\n"
+ " .SnapToDiscrete = 0x%02x\n"
+ " .NumDiscreteLevels = 0x%02x\n"
+ " .padding = 0x%02x\n"
+ " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
+ " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
+ " .SsFmin = 0x%04x\n"
+ " .Padding_16 = 0x%04x\n",
+ pptable->DpmDescriptor[PPCLK_VCLK_1].VoltageMode,
+ pptable->DpmDescriptor[PPCLK_VCLK_1].SnapToDiscrete,
+ pptable->DpmDescriptor[PPCLK_VCLK_1].NumDiscreteLevels,
+ pptable->DpmDescriptor[PPCLK_VCLK_1].Padding,
+ pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.m,
+ pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.b,
+ pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.a,
+ pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.b,
+ pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.c,
+ pptable->DpmDescriptor[PPCLK_VCLK_1].SsFmin,
+ pptable->DpmDescriptor[PPCLK_VCLK_1].Padding16);
+
+ pr_info("FreqTableGfx\n");
+ for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++)
+ pr_info(" .[%02d] = 0x%x\n", i, pptable->FreqTableGfx[i]);
+
+ pr_info("FreqTableVclk\n");
+ for (i = 0; i < NUM_VCLK_DPM_LEVELS; i++)
+ pr_info(" .[%02d] = 0x%x\n", i, pptable->FreqTableVclk[i]);
+
+ pr_info("FreqTableDclk\n");
+ for (i = 0; i < NUM_DCLK_DPM_LEVELS; i++)
+ pr_info(" .[%02d] = 0x%x\n", i, pptable->FreqTableDclk[i]);
+
+ pr_info("FreqTableSocclk\n");
+ for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++)
+ pr_info(" .[%02d] = 0x%x\n", i, pptable->FreqTableSocclk[i]);
+
+ pr_info("FreqTableUclk\n");
+ for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
+ pr_info(" .[%02d] = 0x%x\n", i, pptable->FreqTableUclk[i]);
+
+ pr_info("FreqTableFclk\n");
+ for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++)
+ pr_info(" .[%02d] = 0x%x\n", i, pptable->FreqTableFclk[i]);
+
+ pr_info("Paddingclks[0] = 0x%x\n", pptable->Paddingclks[0]);
+ pr_info("Paddingclks[1] = 0x%x\n", pptable->Paddingclks[1]);
+ pr_info("Paddingclks[2] = 0x%x\n", pptable->Paddingclks[2]);
+ pr_info("Paddingclks[3] = 0x%x\n", pptable->Paddingclks[3]);
+ pr_info("Paddingclks[4] = 0x%x\n", pptable->Paddingclks[4]);
+ pr_info("Paddingclks[5] = 0x%x\n", pptable->Paddingclks[5]);
+ pr_info("Paddingclks[6] = 0x%x\n", pptable->Paddingclks[6]);
+ pr_info("Paddingclks[7] = 0x%x\n", pptable->Paddingclks[7]);
+ pr_info("Paddingclks[8] = 0x%x\n", pptable->Paddingclks[8]);
+ pr_info("Paddingclks[9] = 0x%x\n", pptable->Paddingclks[9]);
+ pr_info("Paddingclks[10] = 0x%x\n", pptable->Paddingclks[10]);
+ pr_info("Paddingclks[11] = 0x%x\n", pptable->Paddingclks[11]);
+ pr_info("Paddingclks[12] = 0x%x\n", pptable->Paddingclks[12]);
+ pr_info("Paddingclks[13] = 0x%x\n", pptable->Paddingclks[13]);
+ pr_info("Paddingclks[14] = 0x%x\n", pptable->Paddingclks[14]);
+ pr_info("Paddingclks[15] = 0x%x\n", pptable->Paddingclks[15]);
+
+ pr_info("DcModeMaxFreq\n");
+ pr_info(" .PPCLK_GFXCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_GFXCLK]);
+ pr_info(" .PPCLK_SOCCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_SOCCLK]);
+ pr_info(" .PPCLK_UCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_UCLK]);
+ pr_info(" .PPCLK_FCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_FCLK]);
+ pr_info(" .PPCLK_DCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_0]);
+ pr_info(" .PPCLK_VCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_0]);
+ pr_info(" .PPCLK_DCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_1]);
+ pr_info(" .PPCLK_VCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_1]);
+
+ pr_info("FreqTableUclkDiv\n");
+ for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
+ pr_info(" .[%d] = 0x%x\n", i, pptable->FreqTableUclkDiv[i]);
+
+ pr_info("FclkBoostFreq = 0x%x\n", pptable->FclkBoostFreq);
+ pr_info("FclkParamPadding = 0x%x\n", pptable->FclkParamPadding);
+
+ pr_info("Mp0clkFreq\n");
+ for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
+ pr_info(" .[%d] = 0x%x\n", i, pptable->Mp0clkFreq[i]);
+
+ pr_info("Mp0DpmVoltage\n");
+ for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
+ pr_info(" .[%d] = 0x%x\n", i, pptable->Mp0DpmVoltage[i]);
+
+ pr_info("MemVddciVoltage\n");
+ for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
+ pr_info(" .[%d] = 0x%x\n", i, pptable->MemVddciVoltage[i]);
+
+ pr_info("MemMvddVoltage\n");
+ for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
+ pr_info(" .[%d] = 0x%x\n", i, pptable->MemMvddVoltage[i]);
+
+ pr_info("GfxclkFgfxoffEntry = 0x%x\n", pptable->GfxclkFgfxoffEntry);
+ pr_info("GfxclkFinit = 0x%x\n", pptable->GfxclkFinit);
+ pr_info("GfxclkFidle = 0x%x\n", pptable->GfxclkFidle);
+ pr_info("GfxclkSource = 0x%x\n", pptable->GfxclkSource);
+ pr_info("GfxclkPadding = 0x%x\n", pptable->GfxclkPadding);
+
+ pr_info("GfxGpoSubFeatureMask = 0x%x\n", pptable->GfxGpoSubFeatureMask);
+
+ pr_info("GfxGpoEnabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoEnabledWorkPolicyMask);
+ pr_info("GfxGpoDisabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoDisabledWorkPolicyMask);
+ pr_info("GfxGpoPadding[0] = 0x%x\n", pptable->GfxGpoPadding[0]);
+ pr_info("GfxGpoVotingAllow = 0x%x\n", pptable->GfxGpoVotingAllow);
+ pr_info("GfxGpoPadding32[0] = 0x%x\n", pptable->GfxGpoPadding32[0]);
+ pr_info("GfxGpoPadding32[1] = 0x%x\n", pptable->GfxGpoPadding32[1]);
+ pr_info("GfxGpoPadding32[2] = 0x%x\n", pptable->GfxGpoPadding32[2]);
+ pr_info("GfxGpoPadding32[3] = 0x%x\n", pptable->GfxGpoPadding32[3]);
+ pr_info("GfxDcsFopt = 0x%x\n", pptable->GfxDcsFopt);
+ pr_info("GfxDcsFclkFopt = 0x%x\n", pptable->GfxDcsFclkFopt);
+ pr_info("GfxDcsUclkFopt = 0x%x\n", pptable->GfxDcsUclkFopt);
+
+ pr_info("DcsGfxOffVoltage = 0x%x\n", pptable->DcsGfxOffVoltage);
+ pr_info("DcsMinGfxOffTime = 0x%x\n", pptable->DcsMinGfxOffTime);
+ pr_info("DcsMaxGfxOffTime = 0x%x\n", pptable->DcsMaxGfxOffTime);
+ pr_info("DcsMinCreditAccum = 0x%x\n", pptable->DcsMinCreditAccum);
+ pr_info("DcsExitHysteresis = 0x%x\n", pptable->DcsExitHysteresis);
+ pr_info("DcsTimeout = 0x%x\n", pptable->DcsTimeout);
+
+ pr_info("DcsParamPadding[0] = 0x%x\n", pptable->DcsParamPadding[0]);
+ pr_info("DcsParamPadding[1] = 0x%x\n", pptable->DcsParamPadding[1]);
+ pr_info("DcsParamPadding[2] = 0x%x\n", pptable->DcsParamPadding[2]);
+ pr_info("DcsParamPadding[3] = 0x%x\n", pptable->DcsParamPadding[3]);
+ pr_info("DcsParamPadding[4] = 0x%x\n", pptable->DcsParamPadding[4]);
+
+ pr_info("FlopsPerByteTable\n");
+ for (i = 0; i < RLC_PACE_TABLE_NUM_LEVELS; i++)
+ pr_info(" .[%d] = 0x%x\n", i, pptable->FlopsPerByteTable[i]);
+
+ pr_info("LowestUclkReservedForUlv = 0x%x\n", pptable->LowestUclkReservedForUlv);
+ pr_info("vddingMem[0] = 0x%x\n", pptable->PaddingMem[0]);
+ pr_info("vddingMem[1] = 0x%x\n", pptable->PaddingMem[1]);
+ pr_info("vddingMem[2] = 0x%x\n", pptable->PaddingMem[2]);
+
+ pr_info("UclkDpmPstates\n");
+ for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
+ pr_info(" .[%d] = 0x%x\n", i, pptable->UclkDpmPstates[i]);
+
+ pr_info("UclkDpmSrcFreqRange\n");
+ pr_info(" .Fmin = 0x%x\n",
+ pptable->UclkDpmSrcFreqRange.Fmin);
+ pr_info(" .Fmax = 0x%x\n",
+ pptable->UclkDpmSrcFreqRange.Fmax);
+ pr_info("UclkDpmTargFreqRange\n");
+ pr_info(" .Fmin = 0x%x\n",
+ pptable->UclkDpmTargFreqRange.Fmin);
+ pr_info(" .Fmax = 0x%x\n",
+ pptable->UclkDpmTargFreqRange.Fmax);
+ pr_info("UclkDpmMidstepFreq = 0x%x\n", pptable->UclkDpmMidstepFreq);
+ pr_info("UclkMidstepPadding = 0x%x\n", pptable->UclkMidstepPadding);
+
+ pr_info("PcieGenSpeed\n");
+ for (i = 0; i < NUM_LINK_LEVELS; i++)
+ pr_info(" .[%d] = 0x%x\n", i, pptable->PcieGenSpeed[i]);
+
+ pr_info("PcieLaneCount\n");
+ for (i = 0; i < NUM_LINK_LEVELS; i++)
+ pr_info(" .[%d] = 0x%x\n", i, pptable->PcieLaneCount[i]);
+
+ pr_info("LclkFreq\n");
+ for (i = 0; i < NUM_LINK_LEVELS; i++)
+ pr_info(" .[%d] = 0x%x\n", i, pptable->LclkFreq[i]);
+
+ pr_info("FanStopTemp = 0x%x\n", pptable->FanStopTemp);
+ pr_info("FanStartTemp = 0x%x\n", pptable->FanStartTemp);
+
+ pr_info("FanGain\n");
+ for (i = 0; i < TEMP_COUNT; i++)
+ pr_info(" .[%d] = 0x%x\n", i, pptable->FanGain[i]);
+
+ pr_info("FanPwmMin = 0x%x\n", pptable->FanPwmMin);
+ pr_info("FanAcousticLimitRpm = 0x%x\n", pptable->FanAcousticLimitRpm);
+ pr_info("FanThrottlingRpm = 0x%x\n", pptable->FanThrottlingRpm);
+ pr_info("FanMaximumRpm = 0x%x\n", pptable->FanMaximumRpm);
+ pr_info("MGpuFanBoostLimitRpm = 0x%x\n", pptable->MGpuFanBoostLimitRpm);
+ pr_info("FanTargetTemperature = 0x%x\n", pptable->FanTargetTemperature);
+ pr_info("FanTargetGfxclk = 0x%x\n", pptable->FanTargetGfxclk);
+ pr_info("FanPadding16 = 0x%x\n", pptable->FanPadding16);
+ pr_info("FanTempInputSelect = 0x%x\n", pptable->FanTempInputSelect);
+ pr_info("FanPadding = 0x%x\n", pptable->FanPadding);
+ pr_info("FanZeroRpmEnable = 0x%x\n", pptable->FanZeroRpmEnable);
+ pr_info("FanTachEdgePerRev = 0x%x\n", pptable->FanTachEdgePerRev);
+
+ pr_info("FuzzyFan_ErrorSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorSetDelta);
+ pr_info("FuzzyFan_ErrorRateSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorRateSetDelta);
+ pr_info("FuzzyFan_PwmSetDelta = 0x%x\n", pptable->FuzzyFan_PwmSetDelta);
+ pr_info("FuzzyFan_Reserved = 0x%x\n", pptable->FuzzyFan_Reserved);
+
+ pr_info("OverrideAvfsGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_GFX]);
+ pr_info("OverrideAvfsGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_SOC]);
+ pr_info("dBtcGbGfxDfllModelSelect = 0x%x\n", pptable->dBtcGbGfxDfllModelSelect);
+ pr_info("Padding8_Avfs = 0x%x\n", pptable->Padding8_Avfs);
+
+ pr_info("qAvfsGb[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
+ pptable->qAvfsGb[AVFS_VOLTAGE_GFX].a,
+ pptable->qAvfsGb[AVFS_VOLTAGE_GFX].b,
+ pptable->qAvfsGb[AVFS_VOLTAGE_GFX].c);
+ pr_info("qAvfsGb[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
+ pptable->qAvfsGb[AVFS_VOLTAGE_SOC].a,
+ pptable->qAvfsGb[AVFS_VOLTAGE_SOC].b,
+ pptable->qAvfsGb[AVFS_VOLTAGE_SOC].c);
+ pr_info("dBtcGbGfxPll{a = 0x%x b = 0x%x c = 0x%x}\n",
+ pptable->dBtcGbGfxPll.a,
+ pptable->dBtcGbGfxPll.b,
+ pptable->dBtcGbGfxPll.c);
+ pr_info("dBtcGbGfxAfll{a = 0x%x b = 0x%x c = 0x%x}\n",
+ pptable->dBtcGbGfxDfll.a,
+ pptable->dBtcGbGfxDfll.b,
+ pptable->dBtcGbGfxDfll.c);
+ pr_info("dBtcGbSoc{a = 0x%x b = 0x%x c = 0x%x}\n",
+ pptable->dBtcGbSoc.a,
+ pptable->dBtcGbSoc.b,
+ pptable->dBtcGbSoc.c);
+ pr_info("qAgingGb[AVFS_VOLTAGE_GFX]{m = 0x%x b = 0x%x}\n",
+ pptable->qAgingGb[AVFS_VOLTAGE_GFX].m,
+ pptable->qAgingGb[AVFS_VOLTAGE_GFX].b);
+ pr_info("qAgingGb[AVFS_VOLTAGE_SOC]{m = 0x%x b = 0x%x}\n",
+ pptable->qAgingGb[AVFS_VOLTAGE_SOC].m,
+ pptable->qAgingGb[AVFS_VOLTAGE_SOC].b);
+
+ pr_info("PiecewiseLinearDroopIntGfxDfll\n");
+ for (i = 0; i < NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS; i++) {
+ pr_info(" Fset[%d] = 0x%x\n",
+ i, pptable->PiecewiseLinearDroopIntGfxDfll.Fset[i]);
+ pr_info(" Vdroop[%d] = 0x%x\n",
+ i, pptable->PiecewiseLinearDroopIntGfxDfll.Vdroop[i]);
+ }
+
+ pr_info("qStaticVoltageOffset[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
+ pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].a,
+ pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].b,
+ pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].c);
+ pr_info("qStaticVoltageOffset[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
+ pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].a,
+ pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].b,
+ pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].c);
+
+ pr_info("DcTol[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_GFX]);
+ pr_info("DcTol[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_SOC]);
+
+ pr_info("DcBtcEnabled[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_GFX]);
+ pr_info("DcBtcEnabled[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_SOC]);
+ pr_info("Padding8_GfxBtc[0] = 0x%x\n", pptable->Padding8_GfxBtc[0]);
+ pr_info("Padding8_GfxBtc[1] = 0x%x\n", pptable->Padding8_GfxBtc[1]);
+
+ pr_info("DcBtcMin[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_GFX]);
+ pr_info("DcBtcMin[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_SOC]);
+ pr_info("DcBtcMax[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_GFX]);
+ pr_info("DcBtcMax[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_SOC]);
+
+ pr_info("DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_GFX]);
+ pr_info("DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_SOC]);
+
+ pr_info("XgmiDpmPstates\n");
+ for (i = 0; i < NUM_XGMI_LEVELS; i++)
+ pr_info(" .[%d] = 0x%x\n", i, pptable->XgmiDpmPstates[i]);
+ pr_info("XgmiDpmSpare[0] = 0x%02x\n", pptable->XgmiDpmSpare[0]);
+ pr_info("XgmiDpmSpare[1] = 0x%02x\n", pptable->XgmiDpmSpare[1]);
+
+ pr_info("DebugOverrides = 0x%x\n", pptable->DebugOverrides);
+ pr_info("ReservedEquation0{a = 0x%x b = 0x%x c = 0x%x}\n",
+ pptable->ReservedEquation0.a,
+ pptable->ReservedEquation0.b,
+ pptable->ReservedEquation0.c);
+ pr_info("ReservedEquation1{a = 0x%x b = 0x%x c = 0x%x}\n",
+ pptable->ReservedEquation1.a,
+ pptable->ReservedEquation1.b,
+ pptable->ReservedEquation1.c);
+ pr_info("ReservedEquation2{a = 0x%x b = 0x%x c = 0x%x}\n",
+ pptable->ReservedEquation2.a,
+ pptable->ReservedEquation2.b,
+ pptable->ReservedEquation2.c);
+ pr_info("ReservedEquation3{a = 0x%x b = 0x%x c = 0x%x}\n",
+ pptable->ReservedEquation3.a,
+ pptable->ReservedEquation3.b,
+ pptable->ReservedEquation3.c);
+
+ pr_info("SkuReserved[0] = 0x%x\n", pptable->SkuReserved[0]);
+ pr_info("SkuReserved[1] = 0x%x\n", pptable->SkuReserved[1]);
+ pr_info("SkuReserved[2] = 0x%x\n", pptable->SkuReserved[2]);
+ pr_info("SkuReserved[3] = 0x%x\n", pptable->SkuReserved[3]);
+ pr_info("SkuReserved[4] = 0x%x\n", pptable->SkuReserved[4]);
+ pr_info("SkuReserved[5] = 0x%x\n", pptable->SkuReserved[5]);
+ pr_info("SkuReserved[6] = 0x%x\n", pptable->SkuReserved[6]);
+ pr_info("SkuReserved[7] = 0x%x\n", pptable->SkuReserved[7]);
+ pr_info("SkuReserved[8] = 0x%x\n", pptable->SkuReserved[8]);
+ pr_info("SkuReserved[9] = 0x%x\n", pptable->SkuReserved[9]);
+ pr_info("SkuReserved[10] = 0x%x\n", pptable->SkuReserved[10]);
+ pr_info("SkuReserved[11] = 0x%x\n", pptable->SkuReserved[11]);
+ pr_info("SkuReserved[12] = 0x%x\n", pptable->SkuReserved[12]);
+ pr_info("SkuReserved[13] = 0x%x\n", pptable->SkuReserved[13]);
+ pr_info("SkuReserved[14] = 0x%x\n", pptable->SkuReserved[14]);
+
+ pr_info("GamingClk[0] = 0x%x\n", pptable->GamingClk[0]);
+ pr_info("GamingClk[1] = 0x%x\n", pptable->GamingClk[1]);
+ pr_info("GamingClk[2] = 0x%x\n", pptable->GamingClk[2]);
+ pr_info("GamingClk[3] = 0x%x\n", pptable->GamingClk[3]);
+ pr_info("GamingClk[4] = 0x%x\n", pptable->GamingClk[4]);
+ pr_info("GamingClk[5] = 0x%x\n", pptable->GamingClk[5]);
+
+ for (i = 0; i < NUM_I2C_CONTROLLERS; i++) {
+ pr_info("I2cControllers[%d]:\n", i);
+ pr_info(" .Enabled = 0x%x\n",
+ pptable->I2cControllers[i].Enabled);
+ pr_info(" .Speed = 0x%x\n",
+ pptable->I2cControllers[i].Speed);
+ pr_info(" .SlaveAddress = 0x%x\n",
+ pptable->I2cControllers[i].SlaveAddress);
+ pr_info(" .ControllerPort = 0x%x\n",
+ pptable->I2cControllers[i].ControllerPort);
+ pr_info(" .ControllerName = 0x%x\n",
+ pptable->I2cControllers[i].ControllerName);
+ pr_info(" .ThermalThrottler = 0x%x\n",
+ pptable->I2cControllers[i].ThermalThrotter);
+ pr_info(" .I2cProtocol = 0x%x\n",
+ pptable->I2cControllers[i].I2cProtocol);
+ pr_info(" .PaddingConfig = 0x%x\n",
+ pptable->I2cControllers[i].PaddingConfig);
+ }
+
+ pr_info("GpioScl = 0x%x\n", pptable->GpioScl);
+ pr_info("GpioSda = 0x%x\n", pptable->GpioSda);
+ pr_info("FchUsbPdSlaveAddr = 0x%x\n", pptable->FchUsbPdSlaveAddr);
+ pr_info("I2cSpare[0] = 0x%x\n", pptable->I2cSpare[0]);
+
+ pr_info("Board Parameters:\n");
+ pr_info("VddGfxVrMapping = 0x%x\n", pptable->VddGfxVrMapping);
+ pr_info("VddSocVrMapping = 0x%x\n", pptable->VddSocVrMapping);
+ pr_info("VddMem0VrMapping = 0x%x\n", pptable->VddMem0VrMapping);
+ pr_info("VddMem1VrMapping = 0x%x\n", pptable->VddMem1VrMapping);
+ pr_info("GfxUlvPhaseSheddingMask = 0x%x\n", pptable->GfxUlvPhaseSheddingMask);
+ pr_info("SocUlvPhaseSheddingMask = 0x%x\n", pptable->SocUlvPhaseSheddingMask);
+ pr_info("VddciUlvPhaseSheddingMask = 0x%x\n", pptable->VddciUlvPhaseSheddingMask);
+ pr_info("MvddUlvPhaseSheddingMask = 0x%x\n", pptable->MvddUlvPhaseSheddingMask);
+
+ pr_info("GfxMaxCurrent = 0x%x\n", pptable->GfxMaxCurrent);
+ pr_info("GfxOffset = 0x%x\n", pptable->GfxOffset);
+ pr_info("Padding_TelemetryGfx = 0x%x\n", pptable->Padding_TelemetryGfx);
+
+ pr_info("SocMaxCurrent = 0x%x\n", pptable->SocMaxCurrent);
+ pr_info("SocOffset = 0x%x\n", pptable->SocOffset);
+ pr_info("Padding_TelemetrySoc = 0x%x\n", pptable->Padding_TelemetrySoc);
+
+ pr_info("Mem0MaxCurrent = 0x%x\n", pptable->Mem0MaxCurrent);
+ pr_info("Mem0Offset = 0x%x\n", pptable->Mem0Offset);
+ pr_info("Padding_TelemetryMem0 = 0x%x\n", pptable->Padding_TelemetryMem0);
+
+ pr_info("Mem1MaxCurrent = 0x%x\n", pptable->Mem1MaxCurrent);
+ pr_info("Mem1Offset = 0x%x\n", pptable->Mem1Offset);
+ pr_info("Padding_TelemetryMem1 = 0x%x\n", pptable->Padding_TelemetryMem1);
+
+ pr_info("MvddRatio = 0x%x\n", pptable->MvddRatio);
+
+ pr_info("AcDcGpio = 0x%x\n", pptable->AcDcGpio);
+ pr_info("AcDcPolarity = 0x%x\n", pptable->AcDcPolarity);
+ pr_info("VR0HotGpio = 0x%x\n", pptable->VR0HotGpio);
+ pr_info("VR0HotPolarity = 0x%x\n", pptable->VR0HotPolarity);
+ pr_info("VR1HotGpio = 0x%x\n", pptable->VR1HotGpio);
+ pr_info("VR1HotPolarity = 0x%x\n", pptable->VR1HotPolarity);
+ pr_info("GthrGpio = 0x%x\n", pptable->GthrGpio);
+ pr_info("GthrPolarity = 0x%x\n", pptable->GthrPolarity);
+ pr_info("LedPin0 = 0x%x\n", pptable->LedPin0);
+ pr_info("LedPin1 = 0x%x\n", pptable->LedPin1);
+ pr_info("LedPin2 = 0x%x\n", pptable->LedPin2);
+ pr_info("LedEnableMask = 0x%x\n", pptable->LedEnableMask);
+ pr_info("LedPcie = 0x%x\n", pptable->LedPcie);
+ pr_info("LedError = 0x%x\n", pptable->LedError);
+ pr_info("LedSpare1[0] = 0x%x\n", pptable->LedSpare1[0]);
+ pr_info("LedSpare1[1] = 0x%x\n", pptable->LedSpare1[1]);
+
+ pr_info("PllGfxclkSpreadEnabled = 0x%x\n", pptable->PllGfxclkSpreadEnabled);
+ pr_info("PllGfxclkSpreadPercent = 0x%x\n", pptable->PllGfxclkSpreadPercent);
+ pr_info("PllGfxclkSpreadFreq = 0x%x\n", pptable->PllGfxclkSpreadFreq);
+
+ pr_info("DfllGfxclkSpreadEnabled = 0x%x\n", pptable->DfllGfxclkSpreadEnabled);
+ pr_info("DfllGfxclkSpreadPercent = 0x%x\n", pptable->DfllGfxclkSpreadPercent);
+ pr_info("DfllGfxclkSpreadFreq = 0x%x\n", pptable->DfllGfxclkSpreadFreq);
+
+ pr_info("UclkSpreadEnabled = 0x%x\n", pptable->UclkSpreadEnabled);
+ pr_info("UclkSpreadPercent = 0x%x\n", pptable->UclkSpreadPercent);
+ pr_info("UclkSpreadFreq = 0x%x\n", pptable->UclkSpreadFreq);
+
+ pr_info("FclkSpreadEnabled = 0x%x\n", pptable->FclkSpreadEnabled);
+ pr_info("FclkSpreadPercent = 0x%x\n", pptable->FclkSpreadPercent);
+ pr_info("FclkSpreadFreq = 0x%x\n", pptable->FclkSpreadFreq);
+
+ pr_info("MemoryChannelEnabled = 0x%x\n", pptable->MemoryChannelEnabled);
+ pr_info("DramBitWidth = 0x%x\n", pptable->DramBitWidth);
+ pr_info("PaddingMem1[0] = 0x%x\n", pptable->PaddingMem1[0]);
+ pr_info("PaddingMem1[1] = 0x%x\n", pptable->PaddingMem1[1]);
+ pr_info("PaddingMem1[2] = 0x%x\n", pptable->PaddingMem1[2]);
+
+ pr_info("TotalBoardPower = 0x%x\n", pptable->TotalBoardPower);
+ pr_info("BoardPowerPadding = 0x%x\n", pptable->BoardPowerPadding);
+
+ pr_info("XgmiLinkSpeed\n");
+ for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
+ pr_info(" .[%d] = 0x%x\n", i, pptable->XgmiLinkSpeed[i]);
+ pr_info("XgmiLinkWidth\n");
+ for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
+ pr_info(" .[%d] = 0x%x\n", i, pptable->XgmiLinkWidth[i]);
+ pr_info("XgmiFclkFreq\n");
+ for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
+ pr_info(" .[%d] = 0x%x\n", i, pptable->XgmiFclkFreq[i]);
+ pr_info("XgmiSocVoltage\n");
+ for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
+ pr_info(" .[%d] = 0x%x\n", i, pptable->XgmiSocVoltage[i]);
+
+ pr_info("HsrEnabled = 0x%x\n", pptable->HsrEnabled);
+ pr_info("VddqOffEnabled = 0x%x\n", pptable->VddqOffEnabled);
+ pr_info("PaddingUmcFlags[0] = 0x%x\n", pptable->PaddingUmcFlags[0]);
+ pr_info("PaddingUmcFlags[1] = 0x%x\n", pptable->PaddingUmcFlags[1]);
+
+ pr_info("BoardReserved[0] = 0x%x\n", pptable->BoardReserved[0]);
+ pr_info("BoardReserved[1] = 0x%x\n", pptable->BoardReserved[1]);
+ pr_info("BoardReserved[2] = 0x%x\n", pptable->BoardReserved[2]);
+ pr_info("BoardReserved[3] = 0x%x\n", pptable->BoardReserved[3]);
+ pr_info("BoardReserved[4] = 0x%x\n", pptable->BoardReserved[4]);
+ pr_info("BoardReserved[5] = 0x%x\n", pptable->BoardReserved[5]);
+ pr_info("BoardReserved[6] = 0x%x\n", pptable->BoardReserved[6]);
+ pr_info("BoardReserved[7] = 0x%x\n", pptable->BoardReserved[7]);
+ pr_info("BoardReserved[8] = 0x%x\n", pptable->BoardReserved[8]);
+ pr_info("BoardReserved[9] = 0x%x\n", pptable->BoardReserved[9]);
+ pr_info("BoardReserved[10] = 0x%x\n", pptable->BoardReserved[10]);
+ pr_info("BoardReserved[11] = 0x%x\n", pptable->BoardReserved[11]);
+ pr_info("BoardReserved[12] = 0x%x\n", pptable->BoardReserved[12]);
+ pr_info("BoardReserved[13] = 0x%x\n", pptable->BoardReserved[13]);
+ pr_info("BoardReserved[14] = 0x%x\n", pptable->BoardReserved[14]);
+
+ pr_info("MmHubPadding[0] = 0x%x\n", pptable->MmHubPadding[0]);
+ pr_info("MmHubPadding[1] = 0x%x\n", pptable->MmHubPadding[1]);
+ pr_info("MmHubPadding[2] = 0x%x\n", pptable->MmHubPadding[2]);
+ pr_info("MmHubPadding[3] = 0x%x\n", pptable->MmHubPadding[3]);
+ pr_info("MmHubPadding[4] = 0x%x\n", pptable->MmHubPadding[4]);
+ pr_info("MmHubPadding[5] = 0x%x\n", pptable->MmHubPadding[5]);
+ pr_info("MmHubPadding[6] = 0x%x\n", pptable->MmHubPadding[6]);
+ pr_info("MmHubPadding[7] = 0x%x\n", pptable->MmHubPadding[7]);
+}
+
+static const struct pptable_funcs sienna_cichlid_ppt_funcs = {
+ .tables_init = sienna_cichlid_tables_init,
+ .alloc_dpm_context = sienna_cichlid_allocate_dpm_context,
+ .store_powerplay_table = sienna_cichlid_store_powerplay_table,
+ .check_powerplay_table = sienna_cichlid_check_powerplay_table,
+ .append_powerplay_table = sienna_cichlid_append_powerplay_table,
+ .get_smu_msg_index = sienna_cichlid_get_smu_msg_index,
+ .get_smu_clk_index = sienna_cichlid_get_smu_clk_index,
+ .get_smu_feature_index = sienna_cichlid_get_smu_feature_index,
+ .get_smu_table_index = sienna_cichlid_get_smu_table_index,
+ .get_workload_type = sienna_cichlid_get_workload_type,
+ .get_allowed_feature_mask = sienna_cichlid_get_allowed_feature_mask,
+ .set_default_dpm_table = sienna_cichlid_set_default_dpm_table,
+ .dpm_set_uvd_enable = sienna_cichlid_dpm_set_uvd_enable,
+ .get_current_clk_freq_by_table = sienna_cichlid_get_current_clk_freq_by_table,
+ .print_clk_levels = sienna_cichlid_print_clk_levels,
+ .force_clk_levels = sienna_cichlid_force_clk_levels,
+ .populate_umd_state_clk = sienna_cichlid_populate_umd_state_clk,
+ .get_clock_by_type_with_latency = sienna_cichlid_get_clock_by_type_with_latency,
+ .pre_display_config_changed = sienna_cichlid_pre_display_config_changed,
+ .display_config_changed = sienna_cichlid_display_config_changed,
+ .notify_smc_display_config = sienna_cichlid_notify_smc_display_config,
+ .force_dpm_limit_value = sienna_cichlid_force_dpm_limit_value,
+ .unforce_dpm_levels = sienna_cichlid_unforce_dpm_levels,
+ .is_dpm_running = sienna_cichlid_is_dpm_running,
+ .get_fan_speed_percent = sienna_cichlid_get_fan_speed_percent,
+ .get_fan_speed_rpm = sienna_cichlid_get_fan_speed_rpm,
+ .get_power_profile_mode = sienna_cichlid_get_power_profile_mode,
+ .set_power_profile_mode = sienna_cichlid_set_power_profile_mode,
+ .get_profiling_clk_mask = sienna_cichlid_get_profiling_clk_mask,
+ .set_watermarks_table = sienna_cichlid_set_watermarks_table,
+ .read_sensor = sienna_cichlid_read_sensor,
+ .get_uclk_dpm_states = sienna_cichlid_get_uclk_dpm_states,
+ .get_thermal_temperature_range = sienna_cichlid_get_thermal_temperature_range,
+ .display_disable_memory_clock_switch = sienna_cichlid_display_disable_memory_clock_switch,
+ .get_power_limit = sienna_cichlid_get_power_limit,
+ .dump_pptable = sienna_cichlid_dump_pptable,
+ .init_microcode = smu_v11_0_init_microcode,
+ .load_microcode = smu_v11_0_load_microcode,
+ .init_smc_tables = smu_v11_0_init_smc_tables,
+ .fini_smc_tables = smu_v11_0_fini_smc_tables,
+ .init_power = smu_v11_0_init_power,
+ .fini_power = smu_v11_0_fini_power,
+ .check_fw_status = smu_v11_0_check_fw_status,
+ .setup_pptable = smu_v11_0_setup_pptable,
+ .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
+ .get_clk_info_from_vbios = smu_v11_0_get_clk_info_from_vbios,
+ .check_pptable = smu_v11_0_check_pptable,
+ .parse_pptable = smu_v11_0_parse_pptable,
+ .populate_smc_tables = smu_v11_0_populate_smc_pptable,
+ .check_fw_version = smu_v11_0_check_fw_version,
+ .write_pptable = smu_v11_0_write_pptable,
+ .set_min_dcef_deep_sleep = smu_v11_0_set_min_dcef_deep_sleep,
+ .set_driver_table_location = smu_v11_0_set_driver_table_location,
+ .set_tool_table_location = smu_v11_0_set_tool_table_location,
+ .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
+ .system_features_control = smu_v11_0_system_features_control,
+ .send_smc_msg_with_param = smu_v11_0_send_msg_with_param,
+ .init_display_count = smu_v11_0_init_display_count,
+ .set_allowed_mask = smu_v11_0_set_allowed_mask,
+ .get_enabled_mask = smu_v11_0_get_enabled_mask,
+ .notify_display_change = smu_v11_0_notify_display_change,
+ .set_power_limit = smu_v11_0_set_power_limit,
+ .get_current_clk_freq = smu_v11_0_get_current_clk_freq,
+ .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
+ .enable_thermal_alert = smu_v11_0_enable_thermal_alert,
+ .disable_thermal_alert = smu_v11_0_disable_thermal_alert,
+ .set_deep_sleep_dcefclk = smu_v11_0_set_deep_sleep_dcefclk,
+ .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
+ .get_fan_control_mode = smu_v11_0_get_fan_control_mode,
+ .set_fan_control_mode = smu_v11_0_set_fan_control_mode,
+ .set_fan_speed_percent = smu_v11_0_set_fan_speed_percent,
+ .set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm,
+ .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
+ .gfx_off_control = smu_v11_0_gfx_off_control,
+ .register_irq_handler = smu_v11_0_register_irq_handler,
+ .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
+ .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,
+ .baco_is_support= smu_v11_0_baco_is_support,
+ .baco_get_state = smu_v11_0_baco_get_state,
+ .baco_set_state = smu_v11_0_baco_set_state,
+ .baco_enter = smu_v11_0_baco_enter,
+ .baco_exit = smu_v11_0_baco_exit,
+ .get_dpm_ultimate_freq = smu_v11_0_get_dpm_ultimate_freq,
+ .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
+ .override_pcie_parameters = smu_v11_0_override_pcie_parameters,
+};
+
+void sienna_cichlid_set_ppt_funcs(struct smu_context *smu)
+{
+ smu->ppt_funcs = &sienna_cichlid_ppt_funcs;
+}
diff --git a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.h b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.h
new file mode 100644
index 000000000000..ce4e4fe43806
--- /dev/null
+++ b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+#ifndef __SIENNA_CICHLID_PPT_H__
+#define __SIENNA_CICHLID_PPT_H__
+
+extern void sienna_cichlid_set_ppt_funcs(struct smu_context *smu);
+
+#endif
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index d6bdd2126f72..b9575f1c22a3 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -50,6 +50,7 @@ MODULE_FIRMWARE("amdgpu/arcturus_smc.bin");
MODULE_FIRMWARE("amdgpu/navi10_smc.bin");
MODULE_FIRMWARE("amdgpu/navi14_smc.bin");
MODULE_FIRMWARE("amdgpu/navi12_smc.bin");
+MODULE_FIRMWARE("amdgpu/sienna_cichlid_smc.bin");
#define SMU11_VOLTAGE_SCALE 4
@@ -159,6 +160,9 @@ int smu_v11_0_init_microcode(struct smu_context *smu)
case CHIP_NAVI12:
chip_name = "navi12";
break;
+ case CHIP_SIENNA_CICHLID:
+ chip_name = "sienna_cichlid";
+ break;
default:
BUG();
}
@@ -278,6 +282,9 @@ int smu_v11_0_check_fw_version(struct smu_context *smu)
case CHIP_NAVI14:
smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_NV14;
break;
+ case CHIP_SIENNA_CICHLID:
+ smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Sienna_Cichlid;
+ break;
default:
pr_err("smu unsupported asic type:%d.\n", smu->adev->asic_type);
smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_INV;
@@ -359,7 +366,8 @@ int smu_v11_0_setup_pptable(struct smu_context *smu)
hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
version_major = le16_to_cpu(hdr->header.header_version_major);
version_minor = le16_to_cpu(hdr->header.header_version_minor);
- if (version_major == 2 && smu->smu_table.boot_values.pp_table_id > 0) {
+ if ((version_major == 2 && smu->smu_table.boot_values.pp_table_id > 0) ||
+ adev->asic_type == CHIP_SIENNA_CICHLID) {
pr_info("use driver provided pptable %d\n", smu->smu_table.boot_values.pp_table_id);
switch (version_minor) {
case 0:
@@ -829,6 +837,11 @@ int smu_v11_0_set_tool_table_location(struct smu_context *smu)
int smu_v11_0_init_display_count(struct smu_context *smu, uint32_t count)
{
int ret = 0;
+ struct amdgpu_device *adev = smu->adev;
+
+ /* Sienna_Cichlid do not support to change display num currently */
+ if (adev->asic_type == CHIP_SIENNA_CICHLID)
+ return 0;
if (!smu->pm_enabled)
return ret;
--
2.25.4
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^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH 026/207] drm/amd/powerplay: add support to set performance level for sienna_cichlid
2020-06-01 17:59 [PATCH 000/207] Add Support for Sienna Cichlid Alex Deucher
` (20 preceding siblings ...)
2020-06-01 17:59 ` [PATCH 025/207] drm/amdgpu/powerplay: add initial swSMU support for sienna_cichlid (v2) Alex Deucher
@ 2020-06-01 17:59 ` Alex Deucher
2020-06-01 17:59 ` [PATCH 027/207] drm/amd/powerplay: set SOCCLK DPM " Alex Deucher
` (60 subsequent siblings)
82 siblings, 0 replies; 88+ messages in thread
From: Alex Deucher @ 2020-06-01 17:59 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Likun Gao, Kenneth Feng
From: Likun Gao <Likun.Gao@amd.com>
Support for performance level set for sienna_cichlid.
Set standard performance level not fully support, will set to auto
performance level.
Set peak performance level not fully support, will do nothing with it.
Force clk level only support for 2 level for fine grained DPM.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
.../drm/amd/powerplay/sienna_cichlid_ppt.c | 83 +++++++++++++++++++
1 file changed, 83 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
index e034dcd25c70..4aa174117af3 100644
--- a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
@@ -552,6 +552,12 @@ static int sienna_cichlid_force_clk_levels(struct smu_context *smu,
case SMU_UCLK:
case SMU_DCEFCLK:
case SMU_FCLK:
+ /* There is only 2 levels for fine grained DPM */
+ if (sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) {
+ soft_max_level = (soft_max_level >= 1 ? 1 : 0);
+ soft_min_level = (soft_min_level >= 1 ? 1 : 0);
+ }
+
ret = smu_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq);
if (ret)
return size;
@@ -1238,6 +1244,82 @@ static int sienna_cichlid_get_uclk_dpm_states(struct smu_context *smu, uint32_t
return 0;
}
+static int sienna_cichlid_set_performance_level(struct smu_context *smu,
+ enum amd_dpm_forced_level level);
+
+static int sienna_cichlid_set_standard_performance_level(struct smu_context *smu)
+{
+ struct amdgpu_device *adev = smu->adev;
+ int ret = 0;
+ uint32_t sclk_freq = 0, uclk_freq = 0;
+
+ switch (adev->asic_type) {
+ /* TODO: need to set specify clk value by asic type, not support yet*/
+ default:
+ /* by default, this is same as auto performance level */
+ return sienna_cichlid_set_performance_level(smu, AMD_DPM_FORCED_LEVEL_AUTO);
+ }
+
+ ret = smu_set_soft_freq_range(smu, SMU_SCLK, sclk_freq, sclk_freq, false);
+ if (ret)
+ return ret;
+ ret = smu_set_soft_freq_range(smu, SMU_UCLK, uclk_freq, uclk_freq, false);
+ if (ret)
+ return ret;
+
+ return ret;
+}
+
+static int sienna_cichlid_set_peak_performance_level(struct smu_context *smu)
+{
+ int ret = 0;
+
+ /* TODO: not support yet*/
+ return ret;
+}
+
+static int sienna_cichlid_set_performance_level(struct smu_context *smu,
+ enum amd_dpm_forced_level level)
+{
+ int ret = 0;
+ uint32_t sclk_mask, mclk_mask, soc_mask;
+
+ switch (level) {
+ case AMD_DPM_FORCED_LEVEL_HIGH:
+ ret = smu_force_dpm_limit_value(smu, true);
+ break;
+ case AMD_DPM_FORCED_LEVEL_LOW:
+ ret = smu_force_dpm_limit_value(smu, false);
+ break;
+ case AMD_DPM_FORCED_LEVEL_AUTO:
+ ret = smu_unforce_dpm_levels(smu);
+ break;
+ case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
+ ret = sienna_cichlid_set_standard_performance_level(smu);
+ break;
+ case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
+ case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
+ ret = smu_get_profiling_clk_mask(smu, level,
+ &sclk_mask,
+ &mclk_mask,
+ &soc_mask);
+ if (ret)
+ return ret;
+ smu_force_clk_levels(smu, SMU_SCLK, 1 << sclk_mask, false);
+ smu_force_clk_levels(smu, SMU_MCLK, 1 << mclk_mask, false);
+ smu_force_clk_levels(smu, SMU_SOCCLK, 1 << soc_mask, false);
+ break;
+ case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
+ ret = sienna_cichlid_set_peak_performance_level(smu);
+ break;
+ case AMD_DPM_FORCED_LEVEL_MANUAL:
+ case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
+ default:
+ break;
+ }
+ return ret;
+}
+
static int sienna_cichlid_get_thermal_temperature_range(struct smu_context *smu,
struct smu_temperature_range *range)
{
@@ -2019,6 +2101,7 @@ static const struct pptable_funcs sienna_cichlid_ppt_funcs = {
.set_watermarks_table = sienna_cichlid_set_watermarks_table,
.read_sensor = sienna_cichlid_read_sensor,
.get_uclk_dpm_states = sienna_cichlid_get_uclk_dpm_states,
+ .set_performance_level = sienna_cichlid_set_performance_level,
.get_thermal_temperature_range = sienna_cichlid_get_thermal_temperature_range,
.display_disable_memory_clock_switch = sienna_cichlid_display_disable_memory_clock_switch,
.get_power_limit = sienna_cichlid_get_power_limit,
--
2.25.4
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH 027/207] drm/amd/powerplay: set SOCCLK DPM for sienna_cichlid
2020-06-01 17:59 [PATCH 000/207] Add Support for Sienna Cichlid Alex Deucher
` (21 preceding siblings ...)
2020-06-01 17:59 ` [PATCH 026/207] drm/amd/powerplay: add support to set performance level for sienna_cichlid Alex Deucher
@ 2020-06-01 17:59 ` Alex Deucher
2020-06-01 17:59 ` [PATCH 028/207] drm/amd/powerplay: set FCLK " Alex Deucher
` (59 subsequent siblings)
82 siblings, 0 replies; 88+ messages in thread
From: Alex Deucher @ 2020-06-01 17:59 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Likun Gao, Kenneth Feng
From: Likun Gao <Likun.Gao@amd.com>
Support for SOCCLK DPM for sienna_cichlid.
Use feature mask to control DPM for sienna_cichlid.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c | 14 +++++++++++---
1 file changed, 11 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
index 4aa174117af3..4a60b688d3c3 100644
--- a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
@@ -42,7 +42,8 @@
#define FEATURE_MASK(feature) (1ULL << feature)
#define SMC_DPM_FEATURE ( \
FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) | \
- FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT))
+ FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT) | \
+ FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT))
#define MSG_MAP(msg, index) \
[SMU_MSG_##msg] = {1, (index)}
@@ -259,13 +260,20 @@ static int
sienna_cichlid_get_allowed_feature_mask(struct smu_context *smu,
uint32_t *feature_mask, uint32_t num)
{
+ struct amdgpu_device *adev = smu->adev;
+
if (num > 2)
return -EINVAL;
memset(feature_mask, 0, sizeof(uint32_t) * num);
- *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT)
- | FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT);
+ *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT);
+
+ if (adev->pm.pp_feature & PP_SCLK_DPM_MASK)
+ *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT);
+
+ if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)
+ *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
return 0;
}
--
2.25.4
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH 028/207] drm/amd/powerplay: set FCLK DPM for sienna_cichlid
2020-06-01 17:59 [PATCH 000/207] Add Support for Sienna Cichlid Alex Deucher
` (22 preceding siblings ...)
2020-06-01 17:59 ` [PATCH 027/207] drm/amd/powerplay: set SOCCLK DPM " Alex Deucher
@ 2020-06-01 17:59 ` Alex Deucher
2020-06-01 17:59 ` [PATCH 029/207] drm/amd/powerplay: enable Ultra Low Voltage " Alex Deucher
` (58 subsequent siblings)
82 siblings, 0 replies; 88+ messages in thread
From: Alex Deucher @ 2020-06-01 17:59 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Likun Gao, Kenneth Feng
From: Likun Gao <Likun.Gao@amd.com>
Support for FCLK DPM for sienna_cichlid.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
index 4a60b688d3c3..f1aeef79e204 100644
--- a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
@@ -43,7 +43,8 @@
#define SMC_DPM_FEATURE ( \
FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) | \
FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT) | \
- FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT))
+ FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT) | \
+ FEATURE_MASK(FEATURE_DPM_FCLK_BIT))
#define MSG_MAP(msg, index) \
[SMU_MSG_##msg] = {1, (index)}
@@ -267,7 +268,8 @@ sienna_cichlid_get_allowed_feature_mask(struct smu_context *smu,
memset(feature_mask, 0, sizeof(uint32_t) * num);
- *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT);
+ *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT)
+ | FEATURE_MASK(FEATURE_DPM_FCLK_BIT);
if (adev->pm.pp_feature & PP_SCLK_DPM_MASK)
*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT);
--
2.25.4
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH 029/207] drm/amd/powerplay: enable Ultra Low Voltage for sienna_cichlid
2020-06-01 17:59 [PATCH 000/207] Add Support for Sienna Cichlid Alex Deucher
` (23 preceding siblings ...)
2020-06-01 17:59 ` [PATCH 028/207] drm/amd/powerplay: set FCLK " Alex Deucher
@ 2020-06-01 17:59 ` Alex Deucher
2020-06-01 17:59 ` [PATCH 030/207] drm/amd/powerplay: enable Graphics Clock Deep Sleep " Alex Deucher
` (57 subsequent siblings)
82 siblings, 0 replies; 88+ messages in thread
From: Alex Deucher @ 2020-06-01 17:59 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Likun Gao, Kenneth Feng
From: Likun Gao <Likun.Gao@amd.com>
Support Ultra Low Voltage for sienna_cichlid.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
index f1aeef79e204..75310858dc0c 100644
--- a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
@@ -277,6 +277,9 @@ sienna_cichlid_get_allowed_feature_mask(struct smu_context *smu,
if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)
*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
+ if (adev->pm.pp_feature & PP_ULV_MASK)
+ *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT);
+
return 0;
}
--
2.25.4
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH 030/207] drm/amd/powerplay: enable Graphics Clock Deep Sleep for sienna_cichlid
2020-06-01 17:59 [PATCH 000/207] Add Support for Sienna Cichlid Alex Deucher
` (24 preceding siblings ...)
2020-06-01 17:59 ` [PATCH 029/207] drm/amd/powerplay: enable Ultra Low Voltage " Alex Deucher
@ 2020-06-01 17:59 ` Alex Deucher
2020-06-01 17:59 ` [PATCH 031/207] drm/amd/powerplay: enable SOC " Alex Deucher
` (56 subsequent siblings)
82 siblings, 0 replies; 88+ messages in thread
From: Alex Deucher @ 2020-06-01 17:59 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Likun Gao, Kenneth Feng
From: Likun Gao <Likun.Gao@amd.com>
Enable Graphics Clock Deep Sleep for sienna_cichlid.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
index 75310858dc0c..82d38eb7ba58 100644
--- a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
@@ -269,7 +269,8 @@ sienna_cichlid_get_allowed_feature_mask(struct smu_context *smu,
memset(feature_mask, 0, sizeof(uint32_t) * num);
*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT)
- | FEATURE_MASK(FEATURE_DPM_FCLK_BIT);
+ | FEATURE_MASK(FEATURE_DPM_FCLK_BIT)
+ | FEATURE_MASK(FEATURE_DS_GFXCLK_BIT);
if (adev->pm.pp_feature & PP_SCLK_DPM_MASK)
*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT);
--
2.25.4
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH 031/207] drm/amd/powerplay: enable SOC Clock Deep Sleep for sienna_cichlid
2020-06-01 17:59 [PATCH 000/207] Add Support for Sienna Cichlid Alex Deucher
` (25 preceding siblings ...)
2020-06-01 17:59 ` [PATCH 030/207] drm/amd/powerplay: enable Graphics Clock Deep Sleep " Alex Deucher
@ 2020-06-01 17:59 ` Alex Deucher
2020-06-01 17:59 ` [PATCH 032/207] drm/amdgpu/powerplay: set Thermal control " Alex Deucher
` (55 subsequent siblings)
82 siblings, 0 replies; 88+ messages in thread
From: Alex Deucher @ 2020-06-01 17:59 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Likun Gao, Kenneth Feng
From: Likun Gao <Likun.Gao@amd.com>
Enable System On Chip Clock Deep Sleep for sienna_cichlid.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
index 82d38eb7ba58..a046fb4db610 100644
--- a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
@@ -270,7 +270,8 @@ sienna_cichlid_get_allowed_feature_mask(struct smu_context *smu,
*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT)
| FEATURE_MASK(FEATURE_DPM_FCLK_BIT)
- | FEATURE_MASK(FEATURE_DS_GFXCLK_BIT);
+ | FEATURE_MASK(FEATURE_DS_GFXCLK_BIT)
+ | FEATURE_MASK(FEATURE_DS_SOCCLK_BIT);
if (adev->pm.pp_feature & PP_SCLK_DPM_MASK)
*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT);
--
2.25.4
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH 032/207] drm/amdgpu/powerplay: set Thermal control for sienna_cichlid
2020-06-01 17:59 [PATCH 000/207] Add Support for Sienna Cichlid Alex Deucher
` (26 preceding siblings ...)
2020-06-01 17:59 ` [PATCH 031/207] drm/amd/powerplay: enable SOC " Alex Deucher
@ 2020-06-01 17:59 ` Alex Deucher
2020-06-01 17:59 ` [PATCH 033/207] drm/amdgpu/powerplay: set UCLK DPM " Alex Deucher
` (54 subsequent siblings)
82 siblings, 0 replies; 88+ messages in thread
From: Alex Deucher @ 2020-06-01 17:59 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Likun Gao, Kenneth Feng
From: Likun Gao <Likun.Gao@amd.com>
Enable Auto Thermal Throttling for sienna_cichlid.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
index a046fb4db610..a96de546c19b 100644
--- a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
@@ -271,7 +271,8 @@ sienna_cichlid_get_allowed_feature_mask(struct smu_context *smu,
*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT)
| FEATURE_MASK(FEATURE_DPM_FCLK_BIT)
| FEATURE_MASK(FEATURE_DS_GFXCLK_BIT)
- | FEATURE_MASK(FEATURE_DS_SOCCLK_BIT);
+ | FEATURE_MASK(FEATURE_DS_SOCCLK_BIT)
+ | FEATURE_MASK(FEATURE_THERMAL_BIT);
if (adev->pm.pp_feature & PP_SCLK_DPM_MASK)
*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT);
--
2.25.4
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH 033/207] drm/amdgpu/powerplay: set UCLK DPM for sienna_cichlid
2020-06-01 17:59 [PATCH 000/207] Add Support for Sienna Cichlid Alex Deucher
` (27 preceding siblings ...)
2020-06-01 17:59 ` [PATCH 032/207] drm/amdgpu/powerplay: set Thermal control " Alex Deucher
@ 2020-06-01 17:59 ` Alex Deucher
2020-06-01 17:59 ` [PATCH 034/207] drm/amd/powerplay: make gfx ds can be configure " Alex Deucher
` (53 subsequent siblings)
82 siblings, 0 replies; 88+ messages in thread
From: Alex Deucher @ 2020-06-01 17:59 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Likun Gao, Kenneth Feng
From: Likun Gao <Likun.Gao@amd.com>
Enable uclk dpm for sienna_cichlid.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
index a96de546c19b..75c31597a478 100644
--- a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
@@ -43,6 +43,7 @@
#define SMC_DPM_FEATURE ( \
FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) | \
FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT) | \
+ FEATURE_MASK(FEATURE_DPM_UCLK_BIT) | \
FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT) | \
FEATURE_MASK(FEATURE_DPM_FCLK_BIT))
@@ -277,6 +278,9 @@ sienna_cichlid_get_allowed_feature_mask(struct smu_context *smu,
if (adev->pm.pp_feature & PP_SCLK_DPM_MASK)
*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT);
+ if (adev->pm.pp_feature & PP_MCLK_DPM_MASK)
+ *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT);
+
if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)
*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
--
2.25.4
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH 034/207] drm/amd/powerplay: make gfx ds can be configure for sienna_cichlid
2020-06-01 17:59 [PATCH 000/207] Add Support for Sienna Cichlid Alex Deucher
` (28 preceding siblings ...)
2020-06-01 17:59 ` [PATCH 033/207] drm/amdgpu/powerplay: set UCLK DPM " Alex Deucher
@ 2020-06-01 17:59 ` Alex Deucher
2020-06-01 17:59 ` [PATCH 035/207] drm/amd/powerplay: Enable SOCCLK ULV " Alex Deucher
` (52 subsequent siblings)
82 siblings, 0 replies; 88+ messages in thread
From: Alex Deucher @ 2020-06-01 17:59 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Likun Gao, Kenneth Feng
From: Likun Gao <Likun.Gao@amd.com>
Make GFX deep sleep can be configure for sienna_cichlid.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
index 75c31597a478..49e157f2b39f 100644
--- a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
@@ -271,7 +271,6 @@ sienna_cichlid_get_allowed_feature_mask(struct smu_context *smu,
*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT)
| FEATURE_MASK(FEATURE_DPM_FCLK_BIT)
- | FEATURE_MASK(FEATURE_DS_GFXCLK_BIT)
| FEATURE_MASK(FEATURE_DS_SOCCLK_BIT)
| FEATURE_MASK(FEATURE_THERMAL_BIT);
@@ -287,6 +286,9 @@ sienna_cichlid_get_allowed_feature_mask(struct smu_context *smu,
if (adev->pm.pp_feature & PP_ULV_MASK)
*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT);
+ if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)
+ *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT);
+
return 0;
}
--
2.25.4
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH 035/207] drm/amd/powerplay: Enable SOCCLK ULV for sienna_cichlid
2020-06-01 17:59 [PATCH 000/207] Add Support for Sienna Cichlid Alex Deucher
` (29 preceding siblings ...)
2020-06-01 17:59 ` [PATCH 034/207] drm/amd/powerplay: make gfx ds can be configure " Alex Deucher
@ 2020-06-01 17:59 ` Alex Deucher
2020-06-01 17:59 ` [PATCH 036/207] drm/amd/powerplay: enable DCEFCLK DPM and DS " Alex Deucher
` (51 subsequent siblings)
82 siblings, 0 replies; 88+ messages in thread
From: Alex Deucher @ 2020-06-01 17:59 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Likun Gao, Kenneth Feng
From: Likun Gao <Likun.Gao@amd.com>
Enable FW DSTATE for sienna_cichlid.
Enable DF CSTATE for sienna_cichlid.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
index 49e157f2b39f..a91e6f753bea 100644
--- a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
@@ -272,6 +272,8 @@ sienna_cichlid_get_allowed_feature_mask(struct smu_context *smu,
*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT)
| FEATURE_MASK(FEATURE_DPM_FCLK_BIT)
| FEATURE_MASK(FEATURE_DS_SOCCLK_BIT)
+ | FEATURE_MASK(FEATURE_FW_DSTATE_BIT)
+ | FEATURE_MASK(FEATURE_DF_CSTATE_BIT)
| FEATURE_MASK(FEATURE_THERMAL_BIT);
if (adev->pm.pp_feature & PP_SCLK_DPM_MASK)
--
2.25.4
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH 036/207] drm/amd/powerplay: enable DCEFCLK DPM and DS for sienna_cichlid
2020-06-01 17:59 [PATCH 000/207] Add Support for Sienna Cichlid Alex Deucher
` (30 preceding siblings ...)
2020-06-01 17:59 ` [PATCH 035/207] drm/amd/powerplay: Enable SOCCLK ULV " Alex Deucher
@ 2020-06-01 17:59 ` Alex Deucher
2020-06-01 17:59 ` [PATCH 037/207] drm/amd/powerplay: support pcie value set and update " Alex Deucher
` (50 subsequent siblings)
82 siblings, 0 replies; 88+ messages in thread
From: Alex Deucher @ 2020-06-01 17:59 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Likun Gao, Kenneth Feng
From: Likun Gao <Likun.Gao@amd.com>
Enable Display Clocks Dynamic Power Management (DPM) for sienna_cichlid.
Enable Display Controller Engine Fabric Clock Deep Sleep for sienna_cichlid.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
index a91e6f753bea..852c364fd7a3 100644
--- a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
@@ -45,7 +45,8 @@
FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT) | \
FEATURE_MASK(FEATURE_DPM_UCLK_BIT) | \
FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT) | \
- FEATURE_MASK(FEATURE_DPM_FCLK_BIT))
+ FEATURE_MASK(FEATURE_DPM_FCLK_BIT) | \
+ FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT))
#define MSG_MAP(msg, index) \
[SMU_MSG_##msg] = {1, (index)}
@@ -272,6 +273,7 @@ sienna_cichlid_get_allowed_feature_mask(struct smu_context *smu,
*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT)
| FEATURE_MASK(FEATURE_DPM_FCLK_BIT)
| FEATURE_MASK(FEATURE_DS_SOCCLK_BIT)
+ | FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT)
| FEATURE_MASK(FEATURE_FW_DSTATE_BIT)
| FEATURE_MASK(FEATURE_DF_CSTATE_BIT)
| FEATURE_MASK(FEATURE_THERMAL_BIT);
@@ -282,6 +284,9 @@ sienna_cichlid_get_allowed_feature_mask(struct smu_context *smu,
if (adev->pm.pp_feature & PP_MCLK_DPM_MASK)
*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT);
+ if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK)
+ *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT);
+
if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)
*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
--
2.25.4
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH 037/207] drm/amd/powerplay: support pcie value set and update for sienna_cichlid
2020-06-01 17:59 [PATCH 000/207] Add Support for Sienna Cichlid Alex Deucher
` (31 preceding siblings ...)
2020-06-01 17:59 ` [PATCH 036/207] drm/amd/powerplay: enable DCEFCLK DPM and DS " Alex Deucher
@ 2020-06-01 17:59 ` Alex Deucher
2020-06-01 17:59 ` [PATCH 038/207] drm/amd/powerplay: support to print pcie levels " Alex Deucher
` (49 subsequent siblings)
82 siblings, 0 replies; 88+ messages in thread
From: Alex Deucher @ 2020-06-01 17:59 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Likun Gao, Kenneth Feng
From: Likun Gao <Likun.Gao@amd.com>
Add support to set default pcie parameters for sienna_cichlid.
Add support to update pcie parameters for sienna_cichlid.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
.../drm/amd/powerplay/sienna_cichlid_ppt.c | 42 +++++++++++++++++++
1 file changed, 42 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
index 852c364fd7a3..5b4319b0da6c 100644
--- a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
@@ -407,6 +407,7 @@ static int sienna_cichlid_set_default_dpm_table(struct smu_context *smu)
struct smu_table_context *table_context = &smu->smu_table;
struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
PPTable_t *driver_ppt = NULL;
+ int i;
driver_ppt = table_context->driver_pptable;
@@ -437,6 +438,11 @@ static int sienna_cichlid_set_default_dpm_table(struct smu_context *smu)
dpm_context->dpm_tables.phy_table.min = driver_ppt->FreqTablePhyclk[0];
dpm_context->dpm_tables.phy_table.max = driver_ppt->FreqTablePhyclk[NUM_PHYCLK_DPM_LEVELS - 1];
+ for (i = 0; i < MAX_PCIE_CONF; i++) {
+ dpm_context->dpm_tables.pcie_table.pcie_gen[i] = driver_ppt->PcieGenSpeed[i];
+ dpm_context->dpm_tables.pcie_table.pcie_lane[i] = driver_ppt->PcieLaneCount[i];
+ }
+
return 0;
}
@@ -1430,6 +1436,41 @@ static int sienna_cichlid_get_power_limit(struct smu_context *smu,
return 0;
}
+static int sienna_cichlid_update_pcie_parameters(struct smu_context *smu,
+ uint32_t pcie_gen_cap,
+ uint32_t pcie_width_cap)
+{
+ PPTable_t *pptable = smu->smu_table.driver_pptable;
+ int ret, i;
+ uint32_t smu_pcie_arg;
+
+ struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
+ struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
+
+ for (i = 0; i < NUM_LINK_LEVELS; i++) {
+ smu_pcie_arg = (i << 16) |
+ ((pptable->PcieGenSpeed[i] <= pcie_gen_cap) ?
+ (pptable->PcieGenSpeed[i] << 8) :
+ (pcie_gen_cap << 8)) |
+ ((pptable->PcieLaneCount[i] <= pcie_width_cap) ?
+ pptable->PcieLaneCount[i] :
+ pcie_width_cap);
+
+ ret = smu_send_smc_msg_with_param(smu,
+ SMU_MSG_OverridePcieParameters,
+ smu_pcie_arg, NULL);
+ if (ret)
+ return ret;
+
+ if (pptable->PcieGenSpeed[i] > pcie_gen_cap)
+ dpm_context->dpm_tables.pcie_table.pcie_gen[i] = pcie_gen_cap;
+ if (pptable->PcieLaneCount[i] > pcie_width_cap)
+ dpm_context->dpm_tables.pcie_table.pcie_lane[i] = pcie_width_cap;
+ }
+
+ return 0;
+}
+
static void sienna_cichlid_dump_pptable(struct smu_context *smu)
{
struct smu_table_context *table_context = &smu->smu_table;
@@ -2134,6 +2175,7 @@ static const struct pptable_funcs sienna_cichlid_ppt_funcs = {
.get_thermal_temperature_range = sienna_cichlid_get_thermal_temperature_range,
.display_disable_memory_clock_switch = sienna_cichlid_display_disable_memory_clock_switch,
.get_power_limit = sienna_cichlid_get_power_limit,
+ .update_pcie_parameters = sienna_cichlid_update_pcie_parameters,
.dump_pptable = sienna_cichlid_dump_pptable,
.init_microcode = smu_v11_0_init_microcode,
.load_microcode = smu_v11_0_load_microcode,
--
2.25.4
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH 038/207] drm/amd/powerplay: support to print pcie levels for sienna_cichlid
2020-06-01 17:59 [PATCH 000/207] Add Support for Sienna Cichlid Alex Deucher
` (32 preceding siblings ...)
2020-06-01 17:59 ` [PATCH 037/207] drm/amd/powerplay: support pcie value set and update " Alex Deucher
@ 2020-06-01 17:59 ` Alex Deucher
2020-06-01 17:59 ` [PATCH 039/207] drm/amd/powerplay: enable LCLK DPM " Alex Deucher
` (48 subsequent siblings)
82 siblings, 0 replies; 88+ messages in thread
From: Alex Deucher @ 2020-06-01 17:59 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Likun Gao, Kenneth Feng
From: Likun Gao <Likun.Gao@amd.com>
Support to print PCIE clk levels for sienna_cichlid.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
.../drm/amd/powerplay/sienna_cichlid_ppt.c | 31 +++++++++++++++++++
.../drm/amd/powerplay/sienna_cichlid_ppt.h | 3 ++
2 files changed, 34 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
index 5b4319b0da6c..662a95585c27 100644
--- a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
@@ -37,6 +37,7 @@
#include "smu_v11_0_pptable.h"
#include "smu_v11_0_7_ppsmc.h"
+#include "nbio/nbio_2_3_sh_mask.h"
#include "asic_reg/mp/mp_11_0_sh_mask.h"
#define FEATURE_MASK(feature) (1ULL << feature)
@@ -508,10 +509,16 @@ static bool sienna_cichlid_is_support_fine_grained_dpm(struct smu_context *smu,
static int sienna_cichlid_print_clk_levels(struct smu_context *smu,
enum smu_clk_type clk_type, char *buf)
{
+ struct amdgpu_device *adev = smu->adev;
+ struct smu_table_context *table_context = &smu->smu_table;
+ struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
+ struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
+ PPTable_t *pptable = (PPTable_t *)table_context->driver_pptable;
int i, size = 0, ret = 0;
uint32_t cur_value = 0, value = 0, count = 0;
uint32_t freq_values[3] = {0};
uint32_t mark_index = 0;
+ uint32_t gen_speed, lane_width;
switch (clk_type) {
case SMU_GFXCLK:
@@ -562,6 +569,30 @@ static int sienna_cichlid_print_clk_levels(struct smu_context *smu,
}
break;
+ case SMU_PCIE:
+ gen_speed = (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) &
+ PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK)
+ >> PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
+ lane_width = (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) &
+ PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK)
+ >> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT;
+ for (i = 0; i < NUM_LINK_LEVELS; i++)
+ size += sprintf(buf + size, "%d: %s %s %dMhz %s\n", i,
+ (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 0) ? "2.5GT/s," :
+ (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 1) ? "5.0GT/s," :
+ (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 2) ? "8.0GT/s," :
+ (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 3) ? "16.0GT/s," : "",
+ (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 1) ? "x1" :
+ (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 2) ? "x2" :
+ (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 3) ? "x4" :
+ (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 4) ? "x8" :
+ (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 5) ? "x12" :
+ (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 6) ? "x16" : "",
+ pptable->LclkFreq[i],
+ (gen_speed == dpm_context->dpm_tables.pcie_table.pcie_gen[i]) &&
+ (lane_width == dpm_context->dpm_tables.pcie_table.pcie_lane[i]) ?
+ "*" : "");
+ break;
default:
break;
}
diff --git a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.h b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.h
index ce4e4fe43806..bc04ae326990 100644
--- a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.h
+++ b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.h
@@ -25,4 +25,7 @@
extern void sienna_cichlid_set_ppt_funcs(struct smu_context *smu);
+#define smnPCIE_LC_SPEED_CNTL 0x11140290
+#define smnPCIE_LC_LINK_WIDTH_CNTL 0x11140288
+
#endif
--
2.25.4
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH 039/207] drm/amd/powerplay: enable LCLK DPM for sienna_cichlid
2020-06-01 17:59 [PATCH 000/207] Add Support for Sienna Cichlid Alex Deucher
` (33 preceding siblings ...)
2020-06-01 17:59 ` [PATCH 038/207] drm/amd/powerplay: support to print pcie levels " Alex Deucher
@ 2020-06-01 17:59 ` Alex Deucher
2020-06-01 17:59 ` [PATCH 040/207] drm/amd/powerplay: enable GFX SS " Alex Deucher
` (47 subsequent siblings)
82 siblings, 0 replies; 88+ messages in thread
From: Alex Deucher @ 2020-06-01 17:59 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Likun Gao, Kenneth Feng
From: Likun Gao <Likun.Gao@amd.com>
Enable LCLK DPM for sienna_cichlid.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
index 662a95585c27..e4bbd282eede 100644
--- a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
@@ -45,6 +45,7 @@
FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) | \
FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT) | \
FEATURE_MASK(FEATURE_DPM_UCLK_BIT) | \
+ FEATURE_MASK(FEATURE_DPM_LINK_BIT) | \
FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT) | \
FEATURE_MASK(FEATURE_DPM_FCLK_BIT) | \
FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT))
@@ -285,6 +286,9 @@ sienna_cichlid_get_allowed_feature_mask(struct smu_context *smu,
if (adev->pm.pp_feature & PP_MCLK_DPM_MASK)
*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT);
+ if (adev->pm.pp_feature & PP_PCIE_DPM_MASK)
+ *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_LINK_BIT);
+
if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK)
*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT);
--
2.25.4
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH 040/207] drm/amd/powerplay: enable GFX SS for sienna_cichlid
2020-06-01 17:59 [PATCH 000/207] Add Support for Sienna Cichlid Alex Deucher
` (34 preceding siblings ...)
2020-06-01 17:59 ` [PATCH 039/207] drm/amd/powerplay: enable LCLK DPM " Alex Deucher
@ 2020-06-01 17:59 ` Alex Deucher
2020-06-01 17:59 ` [PATCH 041/207] drm/amd/powerplay: enable Fan control " Alex Deucher
` (46 subsequent siblings)
82 siblings, 0 replies; 88+ messages in thread
From: Alex Deucher @ 2020-06-01 17:59 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Likun Gao, Kenneth Feng
From: Likun Gao <Likun.Gao@amd.com>
Enable Graphics Clock (GFXCLK) Spread Spectrum for sienna_cichlid.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
index e4bbd282eede..1c0dbc5b5d94 100644
--- a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
@@ -278,6 +278,7 @@ sienna_cichlid_get_allowed_feature_mask(struct smu_context *smu,
| FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT)
| FEATURE_MASK(FEATURE_FW_DSTATE_BIT)
| FEATURE_MASK(FEATURE_DF_CSTATE_BIT)
+ | FEATURE_MASK(FEATURE_GFX_SS_BIT)
| FEATURE_MASK(FEATURE_THERMAL_BIT);
if (adev->pm.pp_feature & PP_SCLK_DPM_MASK)
--
2.25.4
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH 041/207] drm/amd/powerplay: enable Fan control for sienna_cichlid
2020-06-01 17:59 [PATCH 000/207] Add Support for Sienna Cichlid Alex Deucher
` (35 preceding siblings ...)
2020-06-01 17:59 ` [PATCH 040/207] drm/amd/powerplay: enable GFX SS " Alex Deucher
@ 2020-06-01 17:59 ` Alex Deucher
2020-06-01 17:59 ` [PATCH 042/207] drm/amd/powerplay: support to get power index " Alex Deucher
` (45 subsequent siblings)
82 siblings, 0 replies; 88+ messages in thread
From: Alex Deucher @ 2020-06-01 17:59 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Likun Gao, Kenneth Feng
From: Likun Gao <Likun.Gao@amd.com>
Support for Advanced Fan Control (AFC+) for sienna_cichlid.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
index 1c0dbc5b5d94..5e98f471297b 100644
--- a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
@@ -279,6 +279,7 @@ sienna_cichlid_get_allowed_feature_mask(struct smu_context *smu,
| FEATURE_MASK(FEATURE_FW_DSTATE_BIT)
| FEATURE_MASK(FEATURE_DF_CSTATE_BIT)
| FEATURE_MASK(FEATURE_GFX_SS_BIT)
+ | FEATURE_MASK(FEATURE_FAN_CONTROL_BIT)
| FEATURE_MASK(FEATURE_THERMAL_BIT);
if (adev->pm.pp_feature & PP_SCLK_DPM_MASK)
--
2.25.4
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH 042/207] drm/amd/powerplay: support to get power index for sienna_cichlid
2020-06-01 17:59 [PATCH 000/207] Add Support for Sienna Cichlid Alex Deucher
` (36 preceding siblings ...)
2020-06-01 17:59 ` [PATCH 041/207] drm/amd/powerplay: enable Fan control " Alex Deucher
@ 2020-06-01 17:59 ` Alex Deucher
2020-06-01 17:59 ` [PATCH 043/207] drm/amd/powerplay: enable PPT and TDC " Alex Deucher
` (44 subsequent siblings)
82 siblings, 0 replies; 88+ messages in thread
From: Alex Deucher @ 2020-06-01 17:59 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Likun Gao, Kenneth Feng
From: Likun Gao <Likun.Gao@amd.com>
Add function to get smu power index for sienna_cichlid.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
.../drm/amd/powerplay/sienna_cichlid_ppt.c | 21 +++++++++++++++++++
.../drm/amd/powerplay/sienna_cichlid_ppt.h | 6 ++++++
2 files changed, 27 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
index 5e98f471297b..8b59b2aba94a 100644
--- a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
@@ -176,6 +176,11 @@ static struct smu_11_0_cmn2aisc_mapping sienna_cichlid_table_map[SMU_TABLE_COUNT
TAB_MAP(PACE),
};
+static struct smu_11_0_cmn2aisc_mapping sienna_cichlid_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
+ PWR_MAP(AC),
+ PWR_MAP(DC),
+};
+
static struct smu_11_0_cmn2aisc_mapping sienna_cichlid_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT, WORKLOAD_PPLIB_DEFAULT_BIT),
WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D, WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
@@ -246,6 +251,21 @@ static int sienna_cichlid_get_smu_table_index(struct smu_context *smc, uint32_t
return mapping.map_to;
}
+static int sienna_cichlid_get_pwr_src_index(struct smu_context *smc, uint32_t index)
+{
+ struct smu_11_0_cmn2aisc_mapping mapping;
+
+ if (index >= SMU_POWER_SOURCE_COUNT)
+ return -EINVAL;
+
+ mapping = sienna_cichlid_pwr_src_map[index];
+ if (!(mapping.valid_mapping)) {
+ return -EINVAL;
+ }
+
+ return mapping.map_to;
+}
+
static int sienna_cichlid_get_workload_type(struct smu_context *smu, enum PP_SMC_POWER_PROFILE profile)
{
struct smu_11_0_cmn2aisc_mapping mapping;
@@ -2185,6 +2205,7 @@ static const struct pptable_funcs sienna_cichlid_ppt_funcs = {
.get_smu_clk_index = sienna_cichlid_get_smu_clk_index,
.get_smu_feature_index = sienna_cichlid_get_smu_feature_index,
.get_smu_table_index = sienna_cichlid_get_smu_table_index,
+ .get_smu_power_index = sienna_cichlid_get_pwr_src_index,
.get_workload_type = sienna_cichlid_get_workload_type,
.get_allowed_feature_mask = sienna_cichlid_get_allowed_feature_mask,
.set_default_dpm_table = sienna_cichlid_set_default_dpm_table,
diff --git a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.h b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.h
index bc04ae326990..8078886e4cbc 100644
--- a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.h
+++ b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.h
@@ -23,6 +23,12 @@
#ifndef __SIENNA_CICHLID_PPT_H__
#define __SIENNA_CICHLID_PPT_H__
+typedef enum {
+ POWER_SOURCE_AC,
+ POWER_SOURCE_DC,
+ POWER_SOURCE_COUNT,
+} POWER_SOURCE_e;
+
extern void sienna_cichlid_set_ppt_funcs(struct smu_context *smu);
#define smnPCIE_LC_SPEED_CNTL 0x11140290
--
2.25.4
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH 043/207] drm/amd/powerplay: enable PPT and TDC for sienna_cichlid
2020-06-01 17:59 [PATCH 000/207] Add Support for Sienna Cichlid Alex Deucher
` (37 preceding siblings ...)
2020-06-01 17:59 ` [PATCH 042/207] drm/amd/powerplay: support to get power index " Alex Deucher
@ 2020-06-01 17:59 ` Alex Deucher
2020-06-01 17:59 ` [PATCH 044/207] drm/amdgpu/powerplay: add smu block " Alex Deucher
` (43 subsequent siblings)
82 siblings, 0 replies; 88+ messages in thread
From: Alex Deucher @ 2020-06-01 17:59 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Likun Gao, Kenneth Feng
From: Likun Gao <Likun.Gao@amd.com>
Enable PPT and TDC for sienna_cichlid.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
index 8b59b2aba94a..5e2b01a565b3 100644
--- a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
@@ -299,6 +299,8 @@ sienna_cichlid_get_allowed_feature_mask(struct smu_context *smu,
| FEATURE_MASK(FEATURE_FW_DSTATE_BIT)
| FEATURE_MASK(FEATURE_DF_CSTATE_BIT)
| FEATURE_MASK(FEATURE_GFX_SS_BIT)
+ | FEATURE_MASK(FEATURE_PPT_BIT)
+ | FEATURE_MASK(FEATURE_TDC_BIT)
| FEATURE_MASK(FEATURE_FAN_CONTROL_BIT)
| FEATURE_MASK(FEATURE_THERMAL_BIT);
--
2.25.4
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH 044/207] drm/amdgpu/powerplay: add smu block for sienna_cichlid
2020-06-01 17:59 [PATCH 000/207] Add Support for Sienna Cichlid Alex Deucher
` (38 preceding siblings ...)
2020-06-01 17:59 ` [PATCH 043/207] drm/amd/powerplay: enable PPT and TDC " Alex Deucher
@ 2020-06-01 17:59 ` Alex Deucher
2020-06-01 17:59 ` [PATCH 045/207] drm/amdgpu: skip ASD fw load " Alex Deucher
` (42 subsequent siblings)
82 siblings, 0 replies; 88+ messages in thread
From: Alex Deucher @ 2020-06-01 17:59 UTC (permalink / raw)
To: amd-gfx; +Cc: Likun Gao, Jack Xiao
From: Likun Gao <Likun.Gao@amd.com>
Add SMU block for sienna_cichlid with psp load type.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
---
drivers/gpu/drm/amd/amdgpu/nv.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index 1b17fca98fef..e2d97bcdf328 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -488,6 +488,9 @@ int nv_set_ip_blocks(struct amdgpu_device *adev)
amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
+ if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
+ is_support_sw_smu(adev))
+ amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
--
2.25.4
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH 045/207] drm/amdgpu: skip ASD fw load for sienna_cichlid
2020-06-01 17:59 [PATCH 000/207] Add Support for Sienna Cichlid Alex Deucher
` (39 preceding siblings ...)
2020-06-01 17:59 ` [PATCH 044/207] drm/amdgpu/powerplay: add smu block " Alex Deucher
@ 2020-06-01 17:59 ` Alex Deucher
2020-06-01 17:59 ` [PATCH 046/207] drm/amdgpu/psp: add psp support " Alex Deucher
` (41 subsequent siblings)
82 siblings, 0 replies; 88+ messages in thread
From: Alex Deucher @ 2020-06-01 17:59 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Likun Gao, Hawking Zhang
From: Likun Gao <Likun.Gao@amd.com>
Skip ASD FW load for sienna_cichlid currently.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 2 +-
drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 8 +++++---
2 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index 679d96719410..982899aaad9d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -432,7 +432,7 @@ static int psp_asd_load(struct psp_context *psp)
* add workaround to bypass it for sriov now.
* TODO: add version check to make it common
*/
- if (amdgpu_sriov_vf(psp->adev))
+ if (amdgpu_sriov_vf(psp->adev) || (psp->adev->asic_type == CHIP_SIENNA_CICHLID))
return 0;
cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
index 9ec6e3819dff..427eccc649dc 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
@@ -103,9 +103,11 @@ static int psp_v11_0_init_microcode(struct psp_context *psp)
if (err)
return err;
- err = psp_init_asd_microcode(psp, chip_name);
- if (err)
- return err;
+ if (adev->asic_type != CHIP_SIENNA_CICHLID) {
+ err = psp_init_asd_microcode(psp, chip_name);
+ if (err)
+ return err;
+ }
switch (adev->asic_type) {
case CHIP_VEGA20:
--
2.25.4
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH 046/207] drm/amdgpu/psp: add psp support for sienna_cichlid
2020-06-01 17:59 [PATCH 000/207] Add Support for Sienna Cichlid Alex Deucher
` (40 preceding siblings ...)
2020-06-01 17:59 ` [PATCH 045/207] drm/amdgpu: skip ASD fw load " Alex Deucher
@ 2020-06-01 17:59 ` Alex Deucher
2020-06-01 17:59 ` [PATCH 047/207] drm/amdgpu: skip for reroute ih for sienna_cichlid psp ring init currently Alex Deucher
` (40 subsequent siblings)
82 siblings, 0 replies; 88+ messages in thread
From: Alex Deucher @ 2020-06-01 17:59 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Likun Gao, Jack Xiao
From: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 1 +
drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 7 +++++++
2 files changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index 982899aaad9d..6c05071defdd 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -98,6 +98,7 @@ static int psp_early_init(void *handle)
case CHIP_NAVI10:
case CHIP_NAVI14:
case CHIP_NAVI12:
+ case CHIP_SIENNA_CICHLID:
psp_v11_0_set_psp_funcs(psp);
psp->autoload_supported = true;
break;
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
index 427eccc649dc..349fc6f2de12 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
@@ -55,6 +55,8 @@ MODULE_FIRMWARE("amdgpu/navi12_ta.bin");
MODULE_FIRMWARE("amdgpu/arcturus_sos.bin");
MODULE_FIRMWARE("amdgpu/arcturus_asd.bin");
MODULE_FIRMWARE("amdgpu/arcturus_ta.bin");
+MODULE_FIRMWARE("amdgpu/sienna_cichlid_sos.bin");
+MODULE_FIRMWARE("amdgpu/sienna_cichlid_asd.bin");
/* address block */
#define smnMP1_FIRMWARE_FLAGS 0x3010024
@@ -95,6 +97,9 @@ static int psp_v11_0_init_microcode(struct psp_context *psp)
case CHIP_ARCTURUS:
chip_name = "arcturus";
break;
+ case CHIP_SIENNA_CICHLID:
+ chip_name = "sienna_cichlid";
+ break;
default:
BUG();
}
@@ -167,6 +172,8 @@ static int psp_v11_0_init_microcode(struct psp_context *psp)
le32_to_cpu(ta_hdr->ta_dtm_offset_bytes);
}
break;
+ case CHIP_SIENNA_CICHLID:
+ break;
default:
BUG();
}
--
2.25.4
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH 047/207] drm/amdgpu: skip for reroute ih for sienna_cichlid psp ring init currently
2020-06-01 17:59 [PATCH 000/207] Add Support for Sienna Cichlid Alex Deucher
` (41 preceding siblings ...)
2020-06-01 17:59 ` [PATCH 046/207] drm/amdgpu/psp: add psp support " Alex Deucher
@ 2020-06-01 17:59 ` Alex Deucher
2020-06-01 18:00 ` [PATCH 048/207] drm/amdgpu: enable psp ip block for sienna_cichlid Alex Deucher
` (39 subsequent siblings)
82 siblings, 0 replies; 88+ messages in thread
From: Alex Deucher @ 2020-06-01 17:59 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Likun Gao, Jack Xiao
From: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
index 349fc6f2de12..234ba127ec2e 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
@@ -363,7 +363,8 @@ static int psp_v11_0_ring_init(struct psp_context *psp,
struct psp_ring *ring;
struct amdgpu_device *adev = psp->adev;
- if (!amdgpu_sriov_vf(adev))
+ if ((!amdgpu_sriov_vf(adev)) &&
+ (adev->asic_type != CHIP_SIENNA_CICHLID))
psp_v11_0_reroute_ih(psp);
ring = &psp->km_ring;
--
2.25.4
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH 048/207] drm/amdgpu: enable psp ip block for sienna_cichlid
2020-06-01 17:59 [PATCH 000/207] Add Support for Sienna Cichlid Alex Deucher
` (42 preceding siblings ...)
2020-06-01 17:59 ` [PATCH 047/207] drm/amdgpu: skip for reroute ih for sienna_cichlid psp ring init currently Alex Deucher
@ 2020-06-01 18:00 ` Alex Deucher
2020-06-01 18:00 ` [PATCH 049/207] drm/amdgpu: update SDMA 5.2 microcode init Alex Deucher
` (38 subsequent siblings)
82 siblings, 0 replies; 88+ messages in thread
From: Alex Deucher @ 2020-06-01 18:00 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Likun Gao, Jack Xiao
From: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/nv.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index e2d97bcdf328..a4a80aed4b96 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -488,6 +488,7 @@ int nv_set_ip_blocks(struct amdgpu_device *adev)
amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
+ amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
is_support_sw_smu(adev))
amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
--
2.25.4
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH 049/207] drm/amdgpu: update SDMA 5.2 microcode init
2020-06-01 17:59 [PATCH 000/207] Add Support for Sienna Cichlid Alex Deucher
` (43 preceding siblings ...)
2020-06-01 18:00 ` [PATCH 048/207] drm/amdgpu: enable psp ip block for sienna_cichlid Alex Deucher
@ 2020-06-01 18:00 ` Alex Deucher
2020-06-01 18:00 ` [PATCH 050/207] drm/amdgpu: Use variable instead of constant for sdma doorbell range Alex Deucher
` (37 subsequent siblings)
82 siblings, 0 replies; 88+ messages in thread
From: Alex Deucher @ 2020-06-01 18:00 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Likun Gao, John Clements
From: Likun Gao <Likun.Gao@amd.com>
Removed loading duplicate instances of SDMA FW for Sienna_Cichlid,
As sienna_cichlid only use a single image for all instances.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: John Clements <john.clements@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 99 ++++++++++++++++++--------
1 file changed, 69 insertions(+), 30 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
index 5a47f105cd14..82145572e5a3 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
@@ -45,9 +45,6 @@
#include "sdma_v5_2.h"
MODULE_FIRMWARE("amdgpu/sienna_cichlid_sdma.bin");
-MODULE_FIRMWARE("amdgpu/sienna_cichlid_sdma1.bin");
-MODULE_FIRMWARE("amdgpu/sienna_cichlid_sdma2.bin");
-MODULE_FIRMWARE("amdgpu/sienna_cichlid_sdma3.bin");
#define SDMA1_REG_OFFSET 0x600
#define SDMA3_REG_OFFSET 0x400
@@ -94,6 +91,41 @@ static void sdma_v5_2_init_golden_registers(struct amdgpu_device *adev)
}
}
+static int sdma_v5_2_init_inst_ctx(struct amdgpu_sdma_instance *sdma_inst)
+{
+ int err = 0;
+ const struct sdma_firmware_header_v1_0 *hdr;
+
+ err = amdgpu_ucode_validate(sdma_inst->fw);
+ if (err)
+ return err;
+
+ hdr = (const struct sdma_firmware_header_v1_0 *)sdma_inst->fw->data;
+ sdma_inst->fw_version = le32_to_cpu(hdr->header.ucode_version);
+ sdma_inst->feature_version = le32_to_cpu(hdr->ucode_feature_version);
+
+ if (sdma_inst->feature_version >= 20)
+ sdma_inst->burst_nop = true;
+
+ return 0;
+}
+
+static void sdma_v5_2_destroy_inst_ctx(struct amdgpu_device *adev)
+{
+ int i;
+
+ for (i = 0; i < adev->sdma.num_instances; i++) {
+ if (adev->sdma.instance[i].fw != NULL)
+ release_firmware(adev->sdma.instance[i].fw);
+
+ if (adev->asic_type == CHIP_SIENNA_CICHLID)
+ break;
+ }
+
+ memset((void*)adev->sdma.instance, 0,
+ sizeof(struct amdgpu_sdma_instance) * AMDGPU_MAX_SDMA_INSTANCES);
+}
+
/**
* sdma_v5_2_init_microcode - load ucode images from disk
*
@@ -113,7 +145,6 @@ static int sdma_v5_2_init_microcode(struct amdgpu_device *adev)
int err = 0, i;
struct amdgpu_firmware_info *info = NULL;
const struct common_firmware_header *header = NULL;
- const struct sdma_firmware_header_v1_0 *hdr;
DRM_DEBUG("\n");
@@ -125,26 +156,38 @@ static int sdma_v5_2_init_microcode(struct amdgpu_device *adev)
BUG();
}
- for (i = 0; i < adev->sdma.num_instances; i++) {
- if (i == 0)
- snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name);
- else
+ snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name);
+
+ err = request_firmware(&adev->sdma.instance[0].fw, fw_name, adev->dev);
+ if (err)
+ goto out;
+
+ err = sdma_v5_2_init_inst_ctx(&adev->sdma.instance[0]);
+ if (err)
+ goto out;
+
+ for (i = 1; i < adev->sdma.num_instances; i++) {
+ if (adev->asic_type == CHIP_SIENNA_CICHLID) {
+ memcpy((void*)&adev->sdma.instance[i],
+ (void*)&adev->sdma.instance[0],
+ sizeof(struct amdgpu_sdma_instance));
+ } else {
snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma%d.bin", chip_name, i);
- err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev);
- if (err)
- goto out;
- err = amdgpu_ucode_validate(adev->sdma.instance[i].fw);
- if (err)
- goto out;
- hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
- adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
- adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version);
- if (adev->sdma.instance[i].feature_version >= 20)
- adev->sdma.instance[i].burst_nop = true;
- DRM_DEBUG("psp_load == '%s'\n",
- adev->firmware.load_type == AMDGPU_FW_LOAD_PSP ? "true" : "false");
-
- if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
+ err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev);
+ if (err)
+ goto out;
+
+ err = sdma_v5_2_init_inst_ctx(&adev->sdma.instance[0]);
+ if (err)
+ goto out;
+ }
+ }
+
+ DRM_DEBUG("psp_load == '%s'\n",
+ adev->firmware.load_type == AMDGPU_FW_LOAD_PSP ? "true" : "false");
+
+ if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
+ for (i = 0; i < adev->sdma.num_instances; i++) {
info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i;
info->fw = adev->sdma.instance[i].fw;
@@ -153,13 +196,11 @@ static int sdma_v5_2_init_microcode(struct amdgpu_device *adev)
ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
}
}
+
out:
if (err) {
DRM_ERROR("sdma_v5_2: Failed to load firmware \"%s\"\n", fw_name);
- for (i = 0; i < adev->sdma.num_instances; i++) {
- release_firmware(adev->sdma.instance[i].fw);
- adev->sdma.instance[i].fw = NULL;
- }
+ sdma_v5_2_destroy_inst_ctx(adev);
}
return err;
}
@@ -1204,10 +1245,8 @@ static int sdma_v5_2_sw_init(void *handle)
static int sdma_v5_2_sw_fini(void *handle)
{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- int i;
- for (i = 0; i < adev->sdma.num_instances; i++)
- amdgpu_ring_fini(&adev->sdma.instance[i].ring);
+ sdma_v5_2_destroy_inst_ctx(adev);
return 0;
}
--
2.25.4
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH 050/207] drm/amdgpu: Use variable instead of constant for sdma doorbell range
2020-06-01 17:59 [PATCH 000/207] Add Support for Sienna Cichlid Alex Deucher
` (44 preceding siblings ...)
2020-06-01 18:00 ` [PATCH 049/207] drm/amdgpu: update SDMA 5.2 microcode init Alex Deucher
@ 2020-06-01 18:00 ` Alex Deucher
2020-06-01 18:00 ` [PATCH 051/207] drm/amdgpu: add support for athub v2.1 Alex Deucher
` (36 subsequent siblings)
82 siblings, 0 replies; 88+ messages in thread
From: Alex Deucher @ 2020-06-01 18:00 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Yong Zhao
From: Yong Zhao <Yong.Zhao@amd.com>
Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
index 82145572e5a3..52206050adb9 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
@@ -673,7 +673,8 @@ static int sdma_v5_2_gfx_resume(struct amdgpu_device *adev)
WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET), doorbell_offset);
adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell,
- ring->doorbell_index, 20);
+ ring->doorbell_index,
+ adev->doorbell_index.sdma_doorbell_range);
if (amdgpu_sriov_vf(adev))
sdma_v5_2_ring_set_wptr(ring);
--
2.25.4
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH 051/207] drm/amdgpu: add support for athub v2.1
2020-06-01 17:59 [PATCH 000/207] Add Support for Sienna Cichlid Alex Deucher
` (45 preceding siblings ...)
2020-06-01 18:00 ` [PATCH 050/207] drm/amdgpu: Use variable instead of constant for sdma doorbell range Alex Deucher
@ 2020-06-01 18:00 ` Alex Deucher
2020-06-01 18:00 ` [PATCH 052/207] drm/amdgpu: add gmc cg support for sienna_cichlid Alex Deucher
` (35 subsequent siblings)
82 siblings, 0 replies; 88+ messages in thread
From: Alex Deucher @ 2020-06-01 18:00 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Likun Gao, Hawking Zhang
From: Likun Gao <Likun.Gao@amd.com>
Add athub v2.1 function and support to compile it.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/Makefile | 3 +-
drivers/gpu/drm/amd/amdgpu/athub_v2_1.c | 100 ++++++++++++++++++++++++
drivers/gpu/drm/amd/amdgpu/athub_v2_1.h | 30 +++++++
3 files changed, 132 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/amd/amdgpu/athub_v2_1.c
create mode 100644 drivers/gpu/drm/amd/amdgpu/athub_v2_1.h
diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile
index e78674121dfe..38b6ec10751f 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -163,7 +163,8 @@ amdgpu-y += \
# add ATHUB block
amdgpu-y += \
athub_v1_0.o \
- athub_v2_0.o
+ athub_v2_0.o \
+ athub_v2_1.o
# add amdkfd interfaces
amdgpu-y += amdgpu_amdkfd.o
diff --git a/drivers/gpu/drm/amd/amdgpu/athub_v2_1.c b/drivers/gpu/drm/amd/amdgpu/athub_v2_1.c
new file mode 100644
index 000000000000..0219bd6ce1b2
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/athub_v2_1.c
@@ -0,0 +1,100 @@
+/*
+ * Copyright 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#include "amdgpu.h"
+#include "athub_v2_1.h"
+
+#include "athub/athub_2_1_0_offset.h"
+#include "athub/athub_2_1_0_sh_mask.h"
+#include "navi10_enum.h"
+
+#include "soc15_common.h"
+
+static void
+athub_v2_1_update_medium_grain_clock_gating(struct amdgpu_device *adev,
+ bool enable)
+{
+ uint32_t def, data;
+
+ def = data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL);
+
+ if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG))
+ data |= ATHUB_MISC_CNTL__CG_ENABLE_MASK;
+ else
+ data &= ~ATHUB_MISC_CNTL__CG_ENABLE_MASK;
+
+ if (def != data)
+ WREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL, data);
+}
+
+static void
+athub_v2_1_update_medium_grain_light_sleep(struct amdgpu_device *adev,
+ bool enable)
+{
+ uint32_t def, data;
+
+ def = data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL);
+
+ if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS) &&
+ (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
+ data |= ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK;
+ else
+ data &= ~ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK;
+
+ if(def != data)
+ WREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL, data);
+}
+
+int athub_v2_1_set_clockgating(struct amdgpu_device *adev,
+ enum amd_clockgating_state state)
+{
+ if (amdgpu_sriov_vf(adev))
+ return 0;
+
+ switch (adev->asic_type) {
+ case CHIP_SIENNA_CICHLID:
+ athub_v2_1_update_medium_grain_clock_gating(adev,
+ state == AMD_CG_STATE_GATE ? true : false);
+ athub_v2_1_update_medium_grain_light_sleep(adev,
+ state == AMD_CG_STATE_GATE ? true : false);
+ break;
+ default:
+ break;
+ }
+
+ return 0;
+}
+
+void athub_v2_1_get_clockgating(struct amdgpu_device *adev, u32 *flags)
+{
+ int data;
+
+ /* AMD_CG_SUPPORT_ATHUB_MGCG */
+ data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL);
+ if (data & ATHUB_MISC_CNTL__CG_ENABLE_MASK)
+ *flags |= AMD_CG_SUPPORT_ATHUB_MGCG;
+
+ /* AMD_CG_SUPPORT_ATHUB_LS */
+ if (data & ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK)
+ *flags |= AMD_CG_SUPPORT_ATHUB_LS;
+}
diff --git a/drivers/gpu/drm/amd/amdgpu/athub_v2_1.h b/drivers/gpu/drm/amd/amdgpu/athub_v2_1.h
new file mode 100644
index 000000000000..5e6824c0f591
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/athub_v2_1.h
@@ -0,0 +1,30 @@
+/*
+ * Copyright 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+#ifndef __ATHUB_V2_1_H__
+#define __ATHUB_V2_1_H__
+
+int athub_v2_1_set_clockgating(struct amdgpu_device *adev,
+ enum amd_clockgating_state state);
+void athub_v2_1_get_clockgating(struct amdgpu_device *adev, u32 *flags);
+
+#endif
--
2.25.4
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH 052/207] drm/amdgpu: add gmc cg support for sienna_cichlid
2020-06-01 17:59 [PATCH 000/207] Add Support for Sienna Cichlid Alex Deucher
` (46 preceding siblings ...)
2020-06-01 18:00 ` [PATCH 051/207] drm/amdgpu: add support for athub v2.1 Alex Deucher
@ 2020-06-01 18:00 ` Alex Deucher
2020-06-01 18:00 ` [PATCH 053/207] drm/amdgpu: add psp block load condition " Alex Deucher
` (34 subsequent siblings)
82 siblings, 0 replies; 88+ messages in thread
From: Alex Deucher @ 2020-06-01 18:00 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Likun Gao, Hawking Zhang
From: Likun Gao <Likun.Gao@amd.com>
Add gmc clockgating support for sienna_cichlid.
The athub version used for sienna_cichlid is v2.1.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 11 +++++++++--
drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c | 1 +
2 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
index afca175a092c..ce2f72430403 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
@@ -48,6 +48,7 @@
#include "gfxhub_v2_1.h"
#include "mmhub_v2_0.h"
#include "athub_v2_0.h"
+#include "athub_v2_1.h"
/* XXX Move this macro to navi10 header file, which is like vid.h for VI.*/
#define AMDGPU_NUM_OF_VMIDS 8
@@ -1078,7 +1079,10 @@ static int gmc_v10_0_set_clockgating_state(void *handle,
if (r)
return r;
- return athub_v2_0_set_clockgating(adev, state);
+ if (adev->asic_type == CHIP_SIENNA_CICHLID)
+ return athub_v2_1_set_clockgating(adev, state);
+ else
+ return athub_v2_0_set_clockgating(adev, state);
}
static void gmc_v10_0_get_clockgating_state(void *handle, u32 *flags)
@@ -1087,7 +1091,10 @@ static void gmc_v10_0_get_clockgating_state(void *handle, u32 *flags)
mmhub_v2_0_get_clockgating(adev, flags);
- athub_v2_0_get_clockgating(adev, flags);
+ if (adev->asic_type == CHIP_SIENNA_CICHLID)
+ athub_v2_1_get_clockgating(adev, flags);
+ else
+ athub_v2_0_get_clockgating(adev, flags);
}
static int gmc_v10_0_set_powergating_state(void *handle,
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
index b83a56d67428..af0866af63a5 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
@@ -461,6 +461,7 @@ int mmhub_v2_0_set_clockgating(struct amdgpu_device *adev,
case CHIP_NAVI10:
case CHIP_NAVI14:
case CHIP_NAVI12:
+ case CHIP_SIENNA_CICHLID:
mmhub_v2_0_update_medium_grain_clock_gating(adev,
state == AMD_CG_STATE_GATE);
mmhub_v2_0_update_medium_grain_light_sleep(adev,
--
2.25.4
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH 053/207] drm/amdgpu: add psp block load condition for sienna_cichlid
2020-06-01 17:59 [PATCH 000/207] Add Support for Sienna Cichlid Alex Deucher
` (47 preceding siblings ...)
2020-06-01 18:00 ` [PATCH 052/207] drm/amdgpu: add gmc cg support for sienna_cichlid Alex Deucher
@ 2020-06-01 18:00 ` Alex Deucher
2020-06-01 18:00 ` [PATCH 054/207] drm/amdgpu: add 2rd VCN instance doorbell support Alex Deucher
` (33 subsequent siblings)
82 siblings, 0 replies; 88+ messages in thread
From: Alex Deucher @ 2020-06-01 18:00 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Likun Gao, Hawking Zhang
From: Likun Gao <Likun.Gao@amd.com>
Enable PSP block for firmware loading and other security
setup only when amdgpu use PSP load type to load ucode.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/nv.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index a4a80aed4b96..b4178ce267f3 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -488,7 +488,8 @@ int nv_set_ip_blocks(struct amdgpu_device *adev)
amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
- amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
+ if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
+ amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
is_support_sw_smu(adev))
amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
--
2.25.4
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH 054/207] drm/amdgpu: add 2rd VCN instance doorbell support
2020-06-01 17:59 [PATCH 000/207] Add Support for Sienna Cichlid Alex Deucher
` (48 preceding siblings ...)
2020-06-01 18:00 ` [PATCH 053/207] drm/amdgpu: add psp block load condition " Alex Deucher
@ 2020-06-01 18:00 ` Alex Deucher
2020-06-01 18:00 ` [PATCH 055/207] drm/amdgpu: assign the doorbell index to mes ring Alex Deucher
` (32 subsequent siblings)
82 siblings, 0 replies; 88+ messages in thread
From: Alex Deucher @ 2020-06-01 18:00 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, James Zhu, Leo Liu
From: Leo Liu <leo.liu@amd.com>
Sienna_Cichlid have 2 VCN instances, using different register for range
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h | 7 ++++++-
drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c | 6 +++++-
2 files changed, 11 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h
index b8eb5ece37c0..821289bff93a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h
@@ -193,8 +193,13 @@ typedef enum _AMDGPU_NAVI10_DOORBELL_ASSIGNMENT
AMDGPU_NAVI10_DOORBELL64_VCN4_5 = 0x18A,
AMDGPU_NAVI10_DOORBELL64_VCN6_7 = 0x18B,
+ AMDGPU_NAVI10_DOORBELL64_VCN8_9 = 0x18C,
+ AMDGPU_NAVI10_DOORBELL64_VCNa_b = 0x18D,
+ AMDGPU_NAVI10_DOORBELL64_VCNc_d = 0x18E,
+ AMDGPU_NAVI10_DOORBELL64_VCNe_f = 0x18F,
+
AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0,
- AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP = AMDGPU_NAVI10_DOORBELL64_VCN6_7,
+ AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP = AMDGPU_NAVI10_DOORBELL64_VCNe_f,
AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT = 0x18F,
AMDGPU_NAVI10_DOORBELL_INVALID = 0xFFFF
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c b/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
index 4a00b064be10..7429f30398b9 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
@@ -38,6 +38,9 @@
#define mmBIF_SDMA3_DOORBELL_RANGE 0x01d7
#define mmBIF_SDMA3_DOORBELL_RANGE_BASE_IDX 2
+#define mmBIF_MMSCH1_DOORBELL_RANGE 0x01d8
+#define mmBIF_MMSCH1_DOORBELL_RANGE_BASE_IDX 2
+
static void nbio_v2_3_remap_hdp_registers(struct amdgpu_device *adev)
{
WREG32_SOC15(NBIO, 0, mmREMAP_HDP_MEM_FLUSH_CNTL,
@@ -109,7 +112,8 @@ static void nbio_v2_3_sdma_doorbell_range(struct amdgpu_device *adev, int instan
static void nbio_v2_3_vcn_doorbell_range(struct amdgpu_device *adev, bool use_doorbell,
int doorbell_index, int instance)
{
- u32 reg = SOC15_REG_OFFSET(NBIO, 0, mmBIF_MMSCH0_DOORBELL_RANGE);
+ u32 reg = instance ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_MMSCH1_DOORBELL_RANGE) :
+ SOC15_REG_OFFSET(NBIO, 0, mmBIF_MMSCH0_DOORBELL_RANGE);
u32 doorbell_range = RREG32(reg);
--
2.25.4
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH 055/207] drm/amdgpu: assign the doorbell index to mes ring
2020-06-01 17:59 [PATCH 000/207] Add Support for Sienna Cichlid Alex Deucher
` (49 preceding siblings ...)
2020-06-01 18:00 ` [PATCH 054/207] drm/amdgpu: add 2rd VCN instance doorbell support Alex Deucher
@ 2020-06-01 18:00 ` Alex Deucher
2020-06-01 18:00 ` [PATCH 056/207] drm/amdgpu: add the ring type definition of MES Alex Deucher
` (31 subsequent siblings)
82 siblings, 0 replies; 88+ messages in thread
From: Alex Deucher @ 2020-06-01 18:00 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Jack Xiao, Hawking Zhang
From: Jack Xiao <Jack.Xiao@amd.com>
MES ring will use the assigned doorbell index for
command submission.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h | 2 ++
drivers/gpu/drm/amd/amdgpu/nv.c | 1 +
2 files changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h
index 821289bff93a..89e6ad30396f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h
@@ -53,6 +53,7 @@ struct amdgpu_doorbell_index {
uint32_t gfx_ring0;
uint32_t gfx_ring1;
uint32_t sdma_engine[8];
+ uint32_t mes_ring;
uint32_t ih;
union {
struct {
@@ -177,6 +178,7 @@ typedef enum _AMDGPU_NAVI10_DOORBELL_ASSIGNMENT
AMDGPU_NAVI10_DOORBELL_USERQUEUE_END = 0x08A,
AMDGPU_NAVI10_DOORBELL_GFX_RING0 = 0x08B,
AMDGPU_NAVI10_DOORBELL_GFX_RING1 = 0x08C,
+ AMDGPU_NAVI10_DOORBELL_MES_RING = 0x090,
/* SDMA:256~335*/
AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0 = 0x100,
AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1 = 0x10A,
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index b4178ce267f3..cad66cb1b6c2 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -573,6 +573,7 @@ static void nv_init_doorbell_index(struct amdgpu_device *adev)
adev->doorbell_index.userqueue_end = AMDGPU_NAVI10_DOORBELL_USERQUEUE_END;
adev->doorbell_index.gfx_ring0 = AMDGPU_NAVI10_DOORBELL_GFX_RING0;
adev->doorbell_index.gfx_ring1 = AMDGPU_NAVI10_DOORBELL_GFX_RING1;
+ adev->doorbell_index.mes_ring = AMDGPU_NAVI10_DOORBELL_MES_RING;
adev->doorbell_index.sdma_engine[0] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0;
adev->doorbell_index.sdma_engine[1] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1;
adev->doorbell_index.sdma_engine[2] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE2;
--
2.25.4
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH 056/207] drm/amdgpu: add the ring type definition of MES
2020-06-01 17:59 [PATCH 000/207] Add Support for Sienna Cichlid Alex Deucher
` (50 preceding siblings ...)
2020-06-01 18:00 ` [PATCH 055/207] drm/amdgpu: assign the doorbell index to mes ring Alex Deucher
@ 2020-06-01 18:00 ` Alex Deucher
2020-06-01 18:00 ` [PATCH 057/207] drm/amdgpu: avoid dereferencing a NULL pointer Alex Deucher
` (30 subsequent siblings)
82 siblings, 0 replies; 88+ messages in thread
From: Alex Deucher @ 2020-06-01 18:00 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Jack Xiao, Hawking Zhang
From: Jack Xiao <Jack.Xiao@amd.com>
Add a new ring type definition.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
index be218754629a..da871d84b742 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
@@ -62,7 +62,8 @@ enum amdgpu_ring_type {
AMDGPU_RING_TYPE_VCN_DEC = AMDGPU_HW_IP_VCN_DEC,
AMDGPU_RING_TYPE_VCN_ENC = AMDGPU_HW_IP_VCN_ENC,
AMDGPU_RING_TYPE_VCN_JPEG = AMDGPU_HW_IP_VCN_JPEG,
- AMDGPU_RING_TYPE_KIQ
+ AMDGPU_RING_TYPE_KIQ,
+ AMDGPU_RING_TYPE_MES
};
enum amdgpu_ib_pool_type {
--
2.25.4
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH 057/207] drm/amdgpu: avoid dereferencing a NULL pointer
2020-06-01 17:59 [PATCH 000/207] Add Support for Sienna Cichlid Alex Deucher
` (51 preceding siblings ...)
2020-06-01 18:00 ` [PATCH 056/207] drm/amdgpu: add the ring type definition of MES Alex Deucher
@ 2020-06-01 18:00 ` Alex Deucher
2020-06-01 18:00 ` [PATCH 058/207] drm/amdgpu/mes: update some mes definitions Alex Deucher
` (29 subsequent siblings)
82 siblings, 0 replies; 88+ messages in thread
From: Alex Deucher @ 2020-06-01 18:00 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Jack Xiao, Christian König, Hawking Zhang
From: Jack Xiao <Jack.Xiao@amd.com>
Check if irq_src is NULL to avoid dereferencing a NULL pointer,
for MES ring is uneccessary to recieve an interrupt notification.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 19 ++++++++++++-------
1 file changed, 12 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
index d878fe7fee51..3414e119f0cb 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
@@ -416,7 +416,9 @@ int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring,
ring->fence_drv.gpu_addr = adev->uvd.inst[ring->me].gpu_addr + index;
}
amdgpu_fence_write(ring, atomic_read(&ring->fence_drv.last_seq));
- amdgpu_irq_get(adev, irq_src, irq_type);
+
+ if (irq_src)
+ amdgpu_irq_get(adev, irq_src, irq_type);
ring->fence_drv.irq_src = irq_src;
ring->fence_drv.irq_type = irq_type;
@@ -537,8 +539,9 @@ void amdgpu_fence_driver_fini(struct amdgpu_device *adev)
/* no need to trigger GPU reset as we are unloading */
amdgpu_fence_driver_force_completion(ring);
}
- amdgpu_irq_put(adev, ring->fence_drv.irq_src,
- ring->fence_drv.irq_type);
+ if (ring->fence_drv.irq_src)
+ amdgpu_irq_put(adev, ring->fence_drv.irq_src,
+ ring->fence_drv.irq_type);
drm_sched_fini(&ring->sched);
del_timer_sync(&ring->fence_drv.fallback_timer);
for (j = 0; j <= ring->fence_drv.num_fences_mask; ++j)
@@ -574,8 +577,9 @@ void amdgpu_fence_driver_suspend(struct amdgpu_device *adev)
}
/* disable the interrupt */
- amdgpu_irq_put(adev, ring->fence_drv.irq_src,
- ring->fence_drv.irq_type);
+ if (ring->fence_drv.irq_src)
+ amdgpu_irq_put(adev, ring->fence_drv.irq_src,
+ ring->fence_drv.irq_type);
}
}
@@ -601,8 +605,9 @@ void amdgpu_fence_driver_resume(struct amdgpu_device *adev)
continue;
/* enable the interrupt */
- amdgpu_irq_get(adev, ring->fence_drv.irq_src,
- ring->fence_drv.irq_type);
+ if (ring->fence_drv.irq_src)
+ amdgpu_irq_get(adev, ring->fence_drv.irq_src,
+ ring->fence_drv.irq_type);
}
}
--
2.25.4
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH 058/207] drm/amdgpu/mes: update some mes definitions
2020-06-01 17:59 [PATCH 000/207] Add Support for Sienna Cichlid Alex Deucher
` (52 preceding siblings ...)
2020-06-01 18:00 ` [PATCH 057/207] drm/amdgpu: avoid dereferencing a NULL pointer Alex Deucher
@ 2020-06-01 18:00 ` Alex Deucher
2020-06-01 18:00 ` [PATCH 059/207] drm/amdgpu/mes10.1: allocate the eop buffer Alex Deucher
` (28 subsequent siblings)
82 siblings, 0 replies; 88+ messages in thread
From: Alex Deucher @ 2020-06-01 18:00 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Jack Xiao, Hawking Zhang
From: Jack Xiao <Jack.Xiao@amd.com>
Update some mes definitions.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h | 42 +++++++++++++++++++++++--
1 file changed, 40 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
index 78fe49033543..4da9d8f50578 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
@@ -24,10 +24,32 @@
#ifndef __AMDGPU_MES_H__
#define __AMDGPU_MES_H__
+#define AMDGPU_MES_MAX_COMPUTE_PIPES 8
+#define AMDGPU_MES_MAX_GFX_PIPES 2
+#define AMDGPU_MES_MAX_SDMA_PIPES 2
+
+enum amdgpu_mes_priority_level {
+ AMDGPU_MES_PRIORITY_LEVEL_LOW = 0,
+ AMDGPU_MES_PRIORITY_LEVEL_NORMAL = 1,
+ AMDGPU_MES_PRIORITY_LEVEL_MEDIUM = 2,
+ AMDGPU_MES_PRIORITY_LEVEL_HIGH = 3,
+ AMDGPU_MES_PRIORITY_LEVEL_REALTIME = 4,
+ AMDGPU_MES_PRIORITY_NUM_LEVELS
+};
+
struct amdgpu_mes_funcs;
struct amdgpu_mes {
- struct amdgpu_adev *adev;
+ struct amdgpu_device *adev;
+
+ uint32_t total_max_queue;
+ uint32_t doorbell_id_offset;
+ uint32_t max_doorbell_slices;
+
+ uint64_t default_process_quantum;
+ uint64_t default_gang_quantum;
+
+ struct amdgpu_ring ring;
const struct firmware *fw;
@@ -45,8 +67,24 @@ struct amdgpu_mes {
uint32_t data_fw_version;
uint64_t data_start_addr;
+ /* eop gpu obj */
+ struct amdgpu_bo *eop_gpu_obj;
+ uint64_t eop_gpu_addr;
+
+ void *mqd_backup;
+
+ uint32_t vmid_mask_gfxhub;
+ uint32_t vmid_mask_mmhub;
+ uint32_t compute_hqd_mask[AMDGPU_MES_MAX_COMPUTE_PIPES];
+ uint32_t gfx_hqd_mask[AMDGPU_MES_MAX_GFX_PIPES];
+ uint32_t sdma_hqd_mask[AMDGPU_MES_MAX_SDMA_PIPES];
+ uint32_t agreegated_doorbells[AMDGPU_MES_PRIORITY_NUM_LEVELS];
+ uint32_t sch_ctx_offs;
+ uint64_t sch_ctx_gpu_addr;
+ uint64_t *sch_ctx_ptr;
+
/* ip specific functions */
- struct amdgpu_mes_funcs *funcs;
+ const struct amdgpu_mes_funcs *funcs;
};
struct mes_add_queue_input {
--
2.25.4
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH 059/207] drm/amdgpu/mes10.1: allocate the eop buffer
2020-06-01 17:59 [PATCH 000/207] Add Support for Sienna Cichlid Alex Deucher
` (53 preceding siblings ...)
2020-06-01 18:00 ` [PATCH 058/207] drm/amdgpu/mes: update some mes definitions Alex Deucher
@ 2020-06-01 18:00 ` Alex Deucher
2020-06-01 18:00 ` [PATCH 060/207] drm/amdgpu/mes10.1: initialize the software part of mes ring Alex Deucher
` (27 subsequent siblings)
82 siblings, 0 replies; 88+ messages in thread
From: Alex Deucher @ 2020-06-01 18:00 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Jack Xiao, Hawking Zhang
From: Jack Xiao <Jack.Xiao@amd.com>
eop buffer will be used for mes queue setup.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/mes_v10_1.c | 33 ++++++++++++++++++++++++++
1 file changed, 33 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c b/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
index 29fab7984855..7970107be532 100644
--- a/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
@@ -31,6 +31,8 @@
MODULE_FIRMWARE("amdgpu/navi10_mes.bin");
+#define MES_EOP_SIZE 2048
+
static int mes_v10_1_add_hw_queue(struct amdgpu_mes *mes,
struct mes_add_queue_input *input)
{
@@ -283,6 +285,29 @@ static int mes_v10_1_load_microcode(struct amdgpu_device *adev)
return 0;
}
+static int mes_v10_1_allocate_eop_buf(struct amdgpu_device *adev)
+{
+ int r;
+ u32 *eop;
+
+ r = amdgpu_bo_create_reserved(adev, MES_EOP_SIZE, PAGE_SIZE,
+ AMDGPU_GEM_DOMAIN_GTT,
+ &adev->mes.eop_gpu_obj,
+ &adev->mes.eop_gpu_addr,
+ (void **)&eop);
+ if (r) {
+ dev_warn(adev->dev, "(%d) create EOP bo failed\n", r);
+ return r;
+ }
+
+ memset(eop, 0, adev->mes.eop_gpu_obj->tbo.mem.size);
+
+ amdgpu_bo_kunmap(adev->mes.eop_gpu_obj);
+ amdgpu_bo_unreserve(adev->mes.eop_gpu_obj);
+
+ return 0;
+}
+
static int mes_v10_1_sw_init(void *handle)
{
int r;
@@ -292,6 +317,10 @@ static int mes_v10_1_sw_init(void *handle)
if (r)
return r;
+ r = mes_v10_1_allocate_eop_buf(adev);
+ if (r)
+ return r;
+
return 0;
}
@@ -299,6 +328,10 @@ static int mes_v10_1_sw_fini(void *handle)
{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ amdgpu_bo_free_kernel(&adev->mes.eop_gpu_obj,
+ &adev->mes.eop_gpu_addr,
+ NULL);
+
mes_v10_1_free_microcode(adev);
return 0;
--
2.25.4
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^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH 060/207] drm/amdgpu/mes10.1: initialize the software part of mes ring
2020-06-01 17:59 [PATCH 000/207] Add Support for Sienna Cichlid Alex Deucher
` (54 preceding siblings ...)
2020-06-01 18:00 ` [PATCH 059/207] drm/amdgpu/mes10.1: allocate the eop buffer Alex Deucher
@ 2020-06-01 18:00 ` Alex Deucher
2020-06-01 18:00 ` [PATCH 061/207] drm/amdgpu/mes10.1: implement the ring functions of mes specific Alex Deucher
` (26 subsequent siblings)
82 siblings, 0 replies; 88+ messages in thread
From: Alex Deucher @ 2020-06-01 18:00 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Jack Xiao, Hawking Zhang
From: Jack Xiao <Jack.Xiao@amd.com>
Do the software initialization on the mes ring.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/mes_v10_1.c | 26 ++++++++++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c b/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
index 7970107be532..4f7e345673ca 100644
--- a/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
@@ -308,11 +308,37 @@ static int mes_v10_1_allocate_eop_buf(struct amdgpu_device *adev)
return 0;
}
+static int mes_v10_1_ring_init(struct amdgpu_device *adev)
+{
+ struct amdgpu_ring *ring;
+ int r;
+
+ ring = &adev->mes.ring;
+
+ ring->me = 3;
+ ring->pipe = 0;
+ ring->queue = 0;
+
+ ring->ring_obj = NULL;
+ ring->use_doorbell = true;
+ ring->doorbell_index = adev->doorbell_index.mes_ring << 1;
+ ring->eop_gpu_addr = adev->mes.eop_gpu_addr;
+ sprintf(ring->name, "mes_%d.%d.%d", ring->me, ring->pipe, ring->queue);
+
+ r = amdgpu_ring_init(adev, ring, 1024, NULL, 0, AMDGPU_RING_PRIO_DEFAULT);
+ if (r)
+ return r;
+
+ return 0;
+}
+
static int mes_v10_1_sw_init(void *handle)
{
int r;
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ adev->mes.adev = adev;
+
r = mes_v10_1_init_microcode(adev);
if (r)
return r;
--
2.25.4
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^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH 061/207] drm/amdgpu/mes10.1: implement the ring functions of mes specific
2020-06-01 17:59 [PATCH 000/207] Add Support for Sienna Cichlid Alex Deucher
` (55 preceding siblings ...)
2020-06-01 18:00 ` [PATCH 060/207] drm/amdgpu/mes10.1: initialize the software part of mes ring Alex Deucher
@ 2020-06-01 18:00 ` Alex Deucher
2020-06-02 10:00 ` Christian König
2020-06-01 18:00 ` [PATCH 062/207] drm/amdgpu/mes10.1: allocate mqd buffer Alex Deucher
` (25 subsequent siblings)
82 siblings, 1 reply; 88+ messages in thread
From: Alex Deucher @ 2020-06-01 18:00 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Jack Xiao, Hawking Zhang
From: Jack Xiao <Jack.Xiao@amd.com>
Implement mes ring functions and set up them.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/mes_v10_1.c | 43 ++++++++++++++++++++++++++
1 file changed, 43 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c b/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
index 4f7e345673ca..80f6812d8ecf 100644
--- a/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
@@ -33,6 +33,47 @@ MODULE_FIRMWARE("amdgpu/navi10_mes.bin");
#define MES_EOP_SIZE 2048
+static void mes_v10_1_ring_set_wptr(struct amdgpu_ring *ring)
+{
+ struct amdgpu_device *adev = ring->adev;
+
+ if (ring->use_doorbell) {
+ atomic64_set((atomic64_t*)&adev->wb.wb[ring->wptr_offs],
+ ring->wptr);
+ WDOORBELL64(ring->doorbell_index, ring->wptr);
+ } else {
+ BUG();
+ }
+}
+
+static u64 mes_v10_1_ring_get_rptr(struct amdgpu_ring *ring)
+{
+ return ring->adev->wb.wb[ring->rptr_offs];
+}
+
+static u64 mes_v10_1_ring_get_wptr(struct amdgpu_ring *ring)
+{
+ u64 wptr;
+
+ if (ring->use_doorbell)
+ wptr = atomic64_read((atomic64_t *)
+ &ring->adev->wb.wb[ring->wptr_offs]);
+ else
+ BUG();
+ return wptr;
+}
+
+static const struct amdgpu_ring_funcs mes_v10_1_ring_funcs = {
+ .type = AMDGPU_RING_TYPE_MES,
+ .align_mask = 1,
+ .nop = 0,
+ .support_64bit_ptrs = true,
+ .get_rptr = mes_v10_1_ring_get_rptr,
+ .get_wptr = mes_v10_1_ring_get_wptr,
+ .set_wptr = mes_v10_1_ring_set_wptr,
+ .insert_nop = amdgpu_ring_insert_nop,
+};
+
static int mes_v10_1_add_hw_queue(struct amdgpu_mes *mes,
struct mes_add_queue_input *input)
{
@@ -315,6 +356,8 @@ static int mes_v10_1_ring_init(struct amdgpu_device *adev)
ring = &adev->mes.ring;
+ ring->funcs = &mes_v10_1_ring_funcs;
+
ring->me = 3;
ring->pipe = 0;
ring->queue = 0;
--
2.25.4
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH 062/207] drm/amdgpu/mes10.1: allocate mqd buffer
2020-06-01 17:59 [PATCH 000/207] Add Support for Sienna Cichlid Alex Deucher
` (56 preceding siblings ...)
2020-06-01 18:00 ` [PATCH 061/207] drm/amdgpu/mes10.1: implement the ring functions of mes specific Alex Deucher
@ 2020-06-01 18:00 ` Alex Deucher
2020-06-01 18:00 ` [PATCH 063/207] drm/amdgpu/mes10.1: initialize the mqd Alex Deucher
` (24 subsequent siblings)
82 siblings, 0 replies; 88+ messages in thread
From: Alex Deucher @ 2020-06-01 18:00 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Jack Xiao, Hawking Zhang
From: Jack Xiao <Jack.Xiao@amd.com>
Allocate mqd buffer preparing for mes queue setup.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/mes_v10_1.c | 37 ++++++++++++++++++++++++++
1 file changed, 37 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c b/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
index 80f6812d8ecf..ace82c477f01 100644
--- a/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
@@ -28,6 +28,7 @@
#include "nv.h"
#include "gc/gc_10_1_0_offset.h"
#include "gc/gc_10_1_0_sh_mask.h"
+#include "v10_structs.h"
MODULE_FIRMWARE("amdgpu/navi10_mes.bin");
@@ -375,6 +376,32 @@ static int mes_v10_1_ring_init(struct amdgpu_device *adev)
return 0;
}
+static int mes_v10_1_mqd_sw_init(struct amdgpu_device *adev)
+{
+ int r, mqd_size = sizeof(struct v10_compute_mqd);
+ struct amdgpu_ring *ring = &adev->mes.ring;
+
+ if (ring->mqd_obj)
+ return 0;
+
+ r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE,
+ AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj,
+ &ring->mqd_gpu_addr, &ring->mqd_ptr);
+ if (r) {
+ dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r);
+ return r;
+ }
+
+ /* prepare MQD backup */
+ adev->mes.mqd_backup = kmalloc(mqd_size, GFP_KERNEL);
+ if (!adev->mes.mqd_backup)
+ dev_warn(adev->dev,
+ "no memory to create MQD backup for ring %s\n",
+ ring->name);
+
+ return 0;
+}
+
static int mes_v10_1_sw_init(void *handle)
{
int r;
@@ -390,6 +417,10 @@ static int mes_v10_1_sw_init(void *handle)
if (r)
return r;
+ r = mes_v10_1_mqd_sw_init(adev);
+ if (r)
+ return r;
+
return 0;
}
@@ -397,6 +428,12 @@ static int mes_v10_1_sw_fini(void *handle)
{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ kfree(adev->mes.mqd_backup);
+
+ amdgpu_bo_free_kernel(&adev->mes.ring.mqd_obj,
+ &adev->mes.ring.mqd_gpu_addr,
+ &adev->mes.ring.mqd_ptr);
+
amdgpu_bo_free_kernel(&adev->mes.eop_gpu_obj,
&adev->mes.eop_gpu_addr,
NULL);
--
2.25.4
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH 063/207] drm/amdgpu/mes10.1: initialize the mqd
2020-06-01 17:59 [PATCH 000/207] Add Support for Sienna Cichlid Alex Deucher
` (57 preceding siblings ...)
2020-06-01 18:00 ` [PATCH 062/207] drm/amdgpu/mes10.1: allocate mqd buffer Alex Deucher
@ 2020-06-01 18:00 ` Alex Deucher
2020-06-01 18:00 ` [PATCH 064/207] drm/amdgpu/mes10.1: install mes queue by register programming Alex Deucher
` (23 subsequent siblings)
82 siblings, 0 replies; 88+ messages in thread
From: Alex Deucher @ 2020-06-01 18:00 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Jack Xiao, Hawking Zhang
From: Jack Xiao <Jack.Xiao@amd.com>
Initialize the mqd according to mes ring setup.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/mes_v10_1.c | 130 +++++++++++++++++++++++++
1 file changed, 130 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c b/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
index ace82c477f01..36d8314b8d39 100644
--- a/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
@@ -350,6 +350,136 @@ static int mes_v10_1_allocate_eop_buf(struct amdgpu_device *adev)
return 0;
}
+static int mes_v10_1_mqd_init(struct amdgpu_ring *ring)
+{
+ struct amdgpu_device *adev = ring->adev;
+ struct v10_compute_mqd *mqd = ring->mqd_ptr;
+ uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
+ uint32_t tmp;
+
+ mqd->header = 0xC0310800;
+ mqd->compute_pipelinestat_enable = 0x00000001;
+ mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
+ mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
+ mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
+ mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
+ mqd->compute_misc_reserved = 0x00000003;
+
+ eop_base_addr = ring->eop_gpu_addr >> 8;
+ mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;
+ mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
+
+ /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
+ tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL);
+ tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
+ (order_base_2(MES_EOP_SIZE / 4) - 1));
+
+ mqd->cp_hqd_eop_control = tmp;
+
+ /* enable doorbell? */
+ tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
+
+ if (ring->use_doorbell) {
+ tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
+ DOORBELL_OFFSET, ring->doorbell_index);
+ tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
+ DOORBELL_EN, 1);
+ tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
+ DOORBELL_SOURCE, 0);
+ tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
+ DOORBELL_HIT, 0);
+ }
+ else
+ tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
+ DOORBELL_EN, 0);
+
+ mqd->cp_hqd_pq_doorbell_control = tmp;
+
+ /* disable the queue if it's active */
+ ring->wptr = 0;
+ mqd->cp_hqd_dequeue_request = 0;
+ mqd->cp_hqd_pq_rptr = 0;
+ mqd->cp_hqd_pq_wptr_lo = 0;
+ mqd->cp_hqd_pq_wptr_hi = 0;
+
+ /* set the pointer to the MQD */
+ mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc;
+ mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
+
+ /* set MQD vmid to 0 */
+ tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL);
+ tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
+ mqd->cp_mqd_control = tmp;
+
+ /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
+ hqd_gpu_addr = ring->gpu_addr >> 8;
+ mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
+ mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
+
+ /* set up the HQD, this is similar to CP_RB0_CNTL */
+ tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL);
+ tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
+ (order_base_2(ring->ring_size / 4) - 1));
+ tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
+ ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
+#ifdef __BIG_ENDIAN
+ tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
+#endif
+ tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
+ tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0);
+ tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
+ tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
+ mqd->cp_hqd_pq_control = tmp;
+
+ /* set the wb address whether it's enabled or not */
+ wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
+ mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
+ mqd->cp_hqd_pq_rptr_report_addr_hi =
+ upper_32_bits(wb_gpu_addr) & 0xffff;
+
+ /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
+ wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
+ mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffff8;
+ mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
+
+ tmp = 0;
+ /* enable the doorbell if requested */
+ if (ring->use_doorbell) {
+ tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
+ tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
+ DOORBELL_OFFSET, ring->doorbell_index);
+
+ tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
+ DOORBELL_EN, 1);
+ tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
+ DOORBELL_SOURCE, 0);
+ tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
+ DOORBELL_HIT, 0);
+ }
+
+ mqd->cp_hqd_pq_doorbell_control = tmp;
+
+ /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
+ ring->wptr = 0;
+ mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR);
+
+ /* set the vmid for the queue */
+ mqd->cp_hqd_vmid = 0;
+
+ tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE);
+ tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
+ mqd->cp_hqd_persistent_state = tmp;
+
+ /* set MIN_IB_AVAIL_SIZE */
+ tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL);
+ tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
+ mqd->cp_hqd_ib_control = tmp;
+
+ /* activate the queue */
+ mqd->cp_hqd_active = 1;
+ return 0;
+}
+
static int mes_v10_1_ring_init(struct amdgpu_device *adev)
{
struct amdgpu_ring *ring;
--
2.25.4
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^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH 064/207] drm/amdgpu/mes10.1: install mes queue by register programming
2020-06-01 17:59 [PATCH 000/207] Add Support for Sienna Cichlid Alex Deucher
` (58 preceding siblings ...)
2020-06-01 18:00 ` [PATCH 063/207] drm/amdgpu/mes10.1: initialize the mqd Alex Deucher
@ 2020-06-01 18:00 ` Alex Deucher
2020-06-01 18:00 ` [PATCH 065/207] drm/amdgpu/mes10.1: install mes queue via kiq Alex Deucher
` (22 subsequent siblings)
82 siblings, 0 replies; 88+ messages in thread
From: Alex Deucher @ 2020-06-01 18:00 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Jack Xiao, Hawking Zhang
From: Jack Xiao <Jack.Xiao@amd.com>
Directly writing mes queue registers to set up it.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/mes_v10_1.c | 62 ++++++++++++++++++++++++++
1 file changed, 62 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c b/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
index 36d8314b8d39..02c7e4807a3e 100644
--- a/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
@@ -480,6 +480,68 @@ static int mes_v10_1_mqd_init(struct amdgpu_ring *ring)
return 0;
}
+static void mes_v10_1_queue_init_register(struct amdgpu_ring *ring)
+{
+ struct v10_compute_mqd *mqd = ring->mqd_ptr;
+ struct amdgpu_device *adev = ring->adev;
+ uint32_t data = 0;
+
+ mutex_lock(&adev->srbm_mutex);
+ nv_grbm_select(adev, 3, 0, 0, 0);
+
+ /* set CP_HQD_VMID.VMID = 0. */
+ data = RREG32_SOC15(GC, 0, mmCP_HQD_VMID);
+ data = REG_SET_FIELD(data, CP_HQD_VMID, VMID, 0);
+ WREG32_SOC15(GC, 0, mmCP_HQD_VMID, data);
+
+ /* set CP_HQD_PQ_DOORBELL_CONTROL.DOORBELL_EN=0 */
+ data = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
+ data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL,
+ DOORBELL_EN, 0);
+ WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, data);
+
+ /* set CP_MQD_BASE_ADDR/HI with the MQD base address */
+ WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr_lo);
+ WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi);
+
+ /* set CP_MQD_CONTROL.VMID=0 */
+ data = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL);
+ data = REG_SET_FIELD(data, CP_MQD_CONTROL, VMID, 0);
+ WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL, 0);
+
+ /* set CP_HQD_PQ_BASE/HI with the ring buffer base address */
+ WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE, mqd->cp_hqd_pq_base_lo);
+ WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi);
+
+ /* set CP_HQD_PQ_RPTR_REPORT_ADDR/HI */
+ WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR,
+ mqd->cp_hqd_pq_rptr_report_addr_lo);
+ WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
+ mqd->cp_hqd_pq_rptr_report_addr_hi);
+
+ /* set CP_HQD_PQ_CONTROL */
+ WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL, mqd->cp_hqd_pq_control);
+
+ /* set CP_HQD_PQ_WPTR_POLL_ADDR/HI */
+ WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR,
+ mqd->cp_hqd_pq_wptr_poll_addr_lo);
+ WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
+ mqd->cp_hqd_pq_wptr_poll_addr_hi);
+
+ /* set CP_HQD_PQ_DOORBELL_CONTROL */
+ WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
+ mqd->cp_hqd_pq_doorbell_control);
+
+ /* set CP_HQD_PERSISTENT_STATE.PRELOAD_SIZE=0x53 */
+ WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE, mqd->cp_hqd_persistent_state);
+
+ /* set CP_HQD_ACTIVE.ACTIVE=1 */
+ WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, mqd->cp_hqd_active);
+
+ nv_grbm_select(adev, 0, 0, 0, 0);
+ mutex_unlock(&adev->srbm_mutex);
+}
+
static int mes_v10_1_ring_init(struct amdgpu_device *adev)
{
struct amdgpu_ring *ring;
--
2.25.4
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH 065/207] drm/amdgpu/mes10.1: install mes queue via kiq
2020-06-01 17:59 [PATCH 000/207] Add Support for Sienna Cichlid Alex Deucher
` (59 preceding siblings ...)
2020-06-01 18:00 ` [PATCH 064/207] drm/amdgpu/mes10.1: install mes queue by register programming Alex Deucher
@ 2020-06-01 18:00 ` Alex Deucher
2020-06-01 18:00 ` [PATCH 066/207] drm/amdgpu/mes10.1: enable the mes ring during initialization Alex Deucher
` (21 subsequent siblings)
82 siblings, 0 replies; 88+ messages in thread
From: Alex Deucher @ 2020-06-01 18:00 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Jack Xiao, Hawking Zhang
From: Jack Xiao <Jack.Xiao@amd.com>
Install mes queue via kiq. Disable it temporarily
until it's workable.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/mes_v10_1.c | 27 ++++++++++++++++++++++++++
1 file changed, 27 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c b/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
index 02c7e4807a3e..31e8e7120640 100644
--- a/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
@@ -542,6 +542,33 @@ static void mes_v10_1_queue_init_register(struct amdgpu_ring *ring)
mutex_unlock(&adev->srbm_mutex);
}
+#if 0
+static int mes_v10_1_kiq_enable_queue(struct amdgpu_device *adev)
+{
+ struct amdgpu_kiq *kiq = &adev->gfx.kiq;
+ struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring;
+ int r;
+
+ if (!kiq->pmf || !kiq->pmf->kiq_map_queues)
+ return -EINVAL;
+
+ r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size);
+ if (r) {
+ DRM_ERROR("Failed to lock KIQ (%d).\n", r);
+ return r;
+ }
+
+ kiq->pmf->kiq_map_queues(kiq_ring, &adev->mes.ring);
+
+ r = amdgpu_ring_test_ring(kiq_ring);
+ if (r) {
+ DRM_ERROR("kfq enable failed\n");
+ kiq_ring->sched.ready = false;
+ }
+ return r;
+}
+#endif
+
static int mes_v10_1_ring_init(struct amdgpu_device *adev)
{
struct amdgpu_ring *ring;
--
2.25.4
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH 066/207] drm/amdgpu/mes10.1: enable the mes ring during initialization
2020-06-01 17:59 [PATCH 000/207] Add Support for Sienna Cichlid Alex Deucher
` (60 preceding siblings ...)
2020-06-01 18:00 ` [PATCH 065/207] drm/amdgpu/mes10.1: install mes queue via kiq Alex Deucher
@ 2020-06-01 18:00 ` Alex Deucher
2020-06-01 18:00 ` [PATCH 067/207] drm/amdgpu/mes10.1: add the mes fw api Alex Deucher
` (20 subsequent siblings)
82 siblings, 0 replies; 88+ messages in thread
From: Alex Deucher @ 2020-06-01 18:00 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Jack Xiao, Hawking Zhang
From: Jack Xiao <Jack.Xiao@amd.com>
Enable the mes ring during mes block initialization.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/mes_v10_1.c | 31 ++++++++++++++++++++++++++
1 file changed, 31 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c b/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
index 31e8e7120640..36a92bf2c4ca 100644
--- a/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
@@ -32,6 +32,8 @@
MODULE_FIRMWARE("amdgpu/navi10_mes.bin");
+static int mes_v10_1_hw_fini(void *handle);
+
#define MES_EOP_SIZE 2048
static void mes_v10_1_ring_set_wptr(struct amdgpu_ring *ring)
@@ -569,6 +571,25 @@ static int mes_v10_1_kiq_enable_queue(struct amdgpu_device *adev)
}
#endif
+static int mes_v10_1_queue_init(struct amdgpu_device *adev)
+{
+ int r;
+
+ r = mes_v10_1_mqd_init(&adev->mes.ring);
+ if (r)
+ return r;
+
+#if 0
+ r = mes_v10_1_kiq_enable_queue(adev);
+ if (r)
+ return r;
+#else
+ mes_v10_1_queue_init_register(&adev->mes.ring);
+#endif
+
+ return 0;
+}
+
static int mes_v10_1_ring_init(struct amdgpu_device *adev)
{
struct amdgpu_ring *ring;
@@ -640,6 +661,10 @@ static int mes_v10_1_sw_init(void *handle)
if (r)
return r;
+ r = mes_v10_1_ring_init(adev);
+ if (r)
+ return r;
+
return 0;
}
@@ -680,6 +705,12 @@ static int mes_v10_1_hw_init(void *handle)
mes_v10_1_enable(adev, true);
+ r = mes_v10_1_queue_init(adev);
+ if (r) {
+ mes_v10_1_hw_fini(adev);
+ return r;
+ }
+
return 0;
}
--
2.25.4
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH 067/207] drm/amdgpu/mes10.1: add the mes fw api
2020-06-01 17:59 [PATCH 000/207] Add Support for Sienna Cichlid Alex Deucher
` (61 preceding siblings ...)
2020-06-01 18:00 ` [PATCH 066/207] drm/amdgpu/mes10.1: enable the mes ring during initialization Alex Deucher
@ 2020-06-01 18:00 ` Alex Deucher
2020-06-01 18:00 ` [PATCH 068/207] drm/amdgpu/mes10.1: add the helper function for mes command submission Alex Deucher
` (19 subsequent siblings)
82 siblings, 0 replies; 88+ messages in thread
From: Alex Deucher @ 2020-06-01 18:00 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Jack Xiao, Hawking Zhang
From: Jack Xiao <Jack.Xiao@amd.com>
Add the definitions of mes commands.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/mes_api_def.h | 405 +++++++++++++++++++++++
drivers/gpu/drm/amd/amdgpu/mes_v10_1.c | 1 +
2 files changed, 406 insertions(+)
create mode 100644 drivers/gpu/drm/amd/amdgpu/mes_api_def.h
diff --git a/drivers/gpu/drm/amd/amdgpu/mes_api_def.h b/drivers/gpu/drm/amd/amdgpu/mes_api_def.h
new file mode 100644
index 000000000000..da040845de00
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/mes_api_def.h
@@ -0,0 +1,405 @@
+/*
+ * Copyright 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef __MES_API_DEF_H__
+#define __MES_API_DEF_H__
+
+#pragma pack(push, 4)
+
+typedef uint32_t uint32;
+typedef uint64_t uint64;
+
+#define MES_API_VERSION 1
+
+//Driver submits one API(cmd) as a single Frame and this command size is same for all API
+//to ease the debugging and parsing of ring buffer.
+enum {API_FRAME_SIZE_IN_DWORDS = 64};
+
+//To avoid command in scheduler context to be overwritten whenenver mutilple interrupts come in,
+//this creates another queue
+enum {API_NUMBER_OF_COMMAND_MAX = 32};
+
+enum MES_API_TYPE
+{
+ MES_API_TYPE_SCHEDULER = 1,
+ MES_API_TYPE_MAX
+};
+
+enum MES_SCH_API_OPCODE
+{
+ MES_SCH_API_SET_HW_RSRC = 0,
+ MES_SCH_API_SET_SCHEDULING_CONFIG = 1, //agreegated db, quantums, etc
+ MES_SCH_API_ADD_QUEUE = 2,
+ MES_SCH_API_REMOVE_QUEUE = 3,
+ MES_SCH_API_PERFORM_YIELD = 4,
+ MES_SCH_API_SET_GANG_PRIORITY_LEVEL = 5, //For windows GANG = Context
+ MES_SCH_API_SUSPEND = 6,
+ MES_SCH_API_RESUME = 7,
+ MES_SCH_API_RESET = 8,
+ MES_SCH_API_SET_LOG_BUFFER = 9,
+ MES_SCH_API_CHANGE_GANG_PRORITY = 10,
+ MES_SCH_API_QUERY_SCHEDULER_STATUS = 11,
+ MES_SCH_API_PROGRAM_GDS = 12,
+ MES_SCH_API_MAX = 0xFF
+};
+
+union MES_API_HEADER
+{
+ struct
+ {
+ uint32 type : 4; // 0 - Invalid; 1 - Scheduling; 2 - TBD
+ uint32 opcode : 8;
+ uint32 dwsize : 8; //including header
+ uint32 reserved : 12;
+ };
+
+ uint32 u32All;
+};
+
+enum MES_AMD_PRIORITY_LEVEL
+{
+ AMD_PRIORITY_LEVEL_LOW = 0,
+ AMD_PRIORITY_LEVEL_NORMAL = 1,
+ AMD_PRIORITY_LEVEL_MEDIUM = 2,
+ AMD_PRIORITY_LEVEL_HIGH = 3,
+ AMD_PRIORITY_LEVEL_REALTIME = 4,
+ AMD_PRIORITY_NUM_LEVELS
+};
+
+enum MES_QUEUE_TYPE
+{
+ MES_QUEUE_TYPE_GFX,
+ MES_QUEUE_TYPE_COMPUTE,
+ MES_QUEUE_TYPE_SDMA,
+ MES_QUEUE_TYPE_MAX,
+};
+
+struct MES_API_STATUS
+{
+ uint64 api_completion_fence_addr;
+ uint64 api_completion_fence_value;
+};
+
+enum { MAX_COMPUTE_PIPES = 8 };
+enum { MAX_GFX_PIPES = 2 };
+enum { MAX_SDMA_PIPES = 2 };
+
+enum { MAX_COMPUTE_HQD_PER_PIPE = 8 };
+enum { MAX_GFX_HQD_PER_PIPE = 8 };
+enum { MAX_SDMA_HQD_PER_PIPE = 10 };
+
+enum { MAX_QUEUES_IN_A_GANG = 8 };
+
+enum VM_HUB_TYPE
+{
+ VM_HUB_TYPE_GC = 0,
+ VM_HUB_TYPE_MM = 1,
+ VM_HUB_TYPE_MAX,
+};
+
+enum { VMID_INVALID = 0xffff };
+
+enum { MAX_VMID_GCHUB = 16 };
+enum { MAX_VMID_MMHUB = 16 };
+
+enum MES_LOG_OPERATION
+{
+ MES_LOG_OPERATION_CONTEXT_STATE_CHANGE = 0
+};
+
+enum MES_LOG_CONTEXT_STATE
+{
+ MES_LOG_CONTEXT_STATE_IDLE = 0,
+ MES_LOG_CONTEXT_STATE_RUNNING = 1,
+ MES_LOG_CONTEXT_STATE_READY = 2,
+ MES_LOG_CONTEXT_STATE_READY_STANDBY = 3,
+};
+
+struct MES_LOG_CONTEXT_STATE_CHANGE
+{
+ void* h_context;
+ enum MES_LOG_CONTEXT_STATE new_context_state;
+};
+
+struct MES_LOG_ENTRY_HEADER
+{
+ uint32 first_free_entry_index;
+ uint32 wraparound_count;
+ uint64 number_of_entries;
+ uint64 reserved[2];
+};
+
+struct MES_LOG_ENTRY_DATA
+{
+ uint64 gpu_time_stamp;
+ uint32 operation_type; //operation_type is of MES_LOG_OPERATION type
+ uint32 reserved_operation_type_bits;
+ union
+ {
+ struct MES_LOG_CONTEXT_STATE_CHANGE context_state_change;
+ uint64 reserved_operation_data[2];
+ };
+};
+
+struct MES_LOG_BUFFER
+{
+ struct MES_LOG_ENTRY_HEADER header;
+ struct MES_LOG_ENTRY_DATA entries[1];
+};
+
+union MESAPI_SET_HW_RESOURCES
+{
+ struct
+ {
+ union MES_API_HEADER header;
+ uint32 vmid_mask_mmhub;
+ uint32 vmid_mask_gfxhub;
+ uint32 gds_size;
+ uint32 paging_vmid;
+ uint32 compute_hqd_mask[MAX_COMPUTE_PIPES];
+ uint32 gfx_hqd_mask[MAX_GFX_PIPES];
+ uint32 sdma_hqd_mask[MAX_SDMA_PIPES];
+ uint32 agreegated_doorbells[AMD_PRIORITY_NUM_LEVELS];
+ uint64 g_sch_ctx_gpu_mc_ptr;
+ struct MES_API_STATUS api_status;
+ };
+
+ uint32 max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
+};
+
+union MESAPI__ADD_QUEUE
+{
+ struct
+ {
+ union MES_API_HEADER header;
+ uint32 process_id;
+ uint64 page_table_base_addr;
+ uint64 process_va_start;
+ uint64 process_va_end;
+ uint64 process_quantum;
+ uint64 process_context_addr;
+ uint64 gang_quantum;
+ uint64 gang_context_addr;
+ uint32 inprocess_gang_priority;
+ enum MES_AMD_PRIORITY_LEVEL gang_global_priority_level;
+ uint32 doorbell_offset;
+ uint64 mqd_addr;
+ uint64 wptr_addr;
+ enum MES_QUEUE_TYPE queue_type;
+ uint32 gds_base;
+ uint32 gds_size;
+ uint32 gws_base;
+ uint32 gws_size;
+ uint32 oa_mask;
+
+ struct
+ {
+ uint32 paging : 1;
+ uint32 program_gds : 1;
+ uint32 reserved : 30;
+ };
+ struct MES_API_STATUS api_status;
+ };
+
+ uint32 max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
+};
+
+union MESAPI__REMOVE_QUEUE
+{
+ struct
+ {
+ union MES_API_HEADER header;
+ uint32 doorbell_offset;
+ uint64 gang_context_addr;
+ struct MES_API_STATUS api_status;
+ };
+
+ uint32 max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
+};
+
+union MESAPI__SET_SCHEDULING_CONFIG
+{
+ struct
+ {
+ union MES_API_HEADER header;
+ // Grace period when preempting another priority band for this priority band.
+ // The value for idle priority band is ignored, as it never preempts other bands.
+ uint64 grace_period_other_levels[AMD_PRIORITY_NUM_LEVELS];
+
+ // Default quantum for scheduling across processes within a priority band.
+ uint64 process_quantum_for_level[AMD_PRIORITY_NUM_LEVELS];
+
+ // Default grace period for processes that preempt each other within a priority band.
+ uint64 process_grace_period_same_level[AMD_PRIORITY_NUM_LEVELS];
+
+ // For normal level this field specifies the target GPU percentage in situations when it's starved by the high level.
+ // Valid values are between 0 and 50, with the default being 10.
+ uint32 normal_yield_percent;
+
+ struct MES_API_STATUS api_status;
+ };
+
+ uint32 max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
+};
+
+union MESAPI__PERFORM_YIELD
+{
+ struct
+ {
+ union MES_API_HEADER header;
+ uint32 dummy;
+ struct MES_API_STATUS api_status;
+ };
+
+ uint32 max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
+};
+
+union MESAPI__CHANGE_GANG_PRIORITY_LEVEL
+{
+ struct
+ {
+ union MES_API_HEADER header;
+ uint32 inprocess_gang_priority;
+ enum MES_AMD_PRIORITY_LEVEL gang_global_priority_level;
+ uint64 gang_quantum;
+ uint64 gang_context_addr;
+ struct MES_API_STATUS api_status;
+ };
+
+ uint32 max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
+};
+
+union MESAPI__SUSPEND
+{
+ struct
+ {
+ union MES_API_HEADER header;
+ //false - suspend all gangs; true - specific gang
+ struct
+ {
+ uint32 suspend_all_gangs : 1;
+ uint32 reserved : 31;
+ };
+ //gang_context_addr is valid only if suspend_all = false
+ uint64 gang_context_addr;
+
+ uint64 suspend_fence_addr;
+ uint32 suspend_fence_value;
+
+ struct MES_API_STATUS api_status;
+ };
+
+ uint32 max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
+};
+
+union MESAPI__RESUME
+{
+ struct
+ {
+ union MES_API_HEADER header;
+ //false - resume all gangs; true - specified gang
+ struct
+ {
+ uint32 resume_all_gangs : 1;
+ uint32 reserved : 31;
+ };
+ //valid only if resume_all_gangs = false
+ uint64 gang_context_addr;
+
+ struct MES_API_STATUS api_status;
+ };
+
+ uint32 max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
+};
+
+union MESAPI__RESET
+{
+ struct
+ {
+ union MES_API_HEADER header;
+
+ struct
+ {
+ uint32 reset_queue : 1;
+ uint32 reserved : 31;
+ };
+
+ uint64 gang_context_addr;
+ uint32 doorbell_offset; //valid only if reset_queue = true
+ struct MES_API_STATUS api_status;
+ };
+
+ uint32 max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
+};
+
+union MESAPI__SET_LOGGING_BUFFER
+{
+ struct
+ {
+ union MES_API_HEADER header;
+ //There are separate log buffers for each queue type
+ enum MES_QUEUE_TYPE log_type;
+ //Log buffer GPU Address
+ uint64 logging_buffer_addr;
+ //number of entries in the log buffer
+ uint32 number_of_entries;
+ //Entry index at which CPU interrupt needs to be signalled
+ uint32 interrupt_entry;
+
+ struct MES_API_STATUS api_status;
+ };
+
+ uint32 max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
+};
+
+union MESAPI__QUERY_MES_STATUS
+{
+ struct
+ {
+ union MES_API_HEADER header;
+ bool mes_healthy; //0 - not healthy, 1 - healthy
+ struct MES_API_STATUS api_status;
+ };
+
+ uint32 max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
+};
+
+union MESAPI__PROGRAM_GDS
+{
+ struct
+ {
+ union MES_API_HEADER header;
+ uint64 process_context_addr;
+ uint32 gds_base;
+ uint32 gds_size;
+ uint32 gws_base;
+ uint32 gws_size;
+ uint32 oa_mask;
+ struct MES_API_STATUS api_status;
+ };
+
+ uint32 max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
+};
+
+#pragma pack(pop)
+#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c b/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
index 36a92bf2c4ca..da89b6a6507c 100644
--- a/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
@@ -29,6 +29,7 @@
#include "gc/gc_10_1_0_offset.h"
#include "gc/gc_10_1_0_sh_mask.h"
#include "v10_structs.h"
+#include "mes_api_def.h"
MODULE_FIRMWARE("amdgpu/navi10_mes.bin");
--
2.25.4
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH 068/207] drm/amdgpu/mes10.1: add the helper function for mes command submission
2020-06-01 17:59 [PATCH 000/207] Add Support for Sienna Cichlid Alex Deucher
` (62 preceding siblings ...)
2020-06-01 18:00 ` [PATCH 067/207] drm/amdgpu/mes10.1: add the mes fw api Alex Deucher
@ 2020-06-01 18:00 ` Alex Deucher
2020-06-01 18:00 ` [PATCH 069/207] drm/amdgpu/mes10.1: implement adding hardware queue Alex Deucher
` (18 subsequent siblings)
82 siblings, 0 replies; 88+ messages in thread
From: Alex Deucher @ 2020-06-01 18:00 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Jack Xiao, Hawking Zhang
From: Jack Xiao <Jack.Xiao@amd.com>
The helper function is used to submit mes command and poll waiting
for the command completion.
v2: replaced with amdgpu_fence_wait_polling to wait.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/mes_v10_1.c | 30 ++++++++++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c b/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
index da89b6a6507c..3ce77839468d 100644
--- a/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
@@ -78,6 +78,36 @@ static const struct amdgpu_ring_funcs mes_v10_1_ring_funcs = {
.insert_nop = amdgpu_ring_insert_nop,
};
+static int mes_v10_1_submit_pkt_and_poll_completion(struct amdgpu_mes *mes,
+ void *pkt, int size)
+{
+ int ndw = size / 4;
+ signed long r;
+ union MESAPI__ADD_QUEUE *x_pkt = pkt;
+ struct amdgpu_device *adev = mes->adev;
+ struct amdgpu_ring *ring = &mes->ring;
+
+ BUG_ON(size % 4 != 0);
+
+ if (amdgpu_ring_alloc(ring, ndw))
+ return -ENOMEM;
+
+ amdgpu_ring_write_multiple(ring, pkt, ndw);
+ amdgpu_ring_commit(ring);
+
+ DRM_DEBUG("MES msg=%d was emitted\n", x_pkt->header.opcode);
+
+ r = amdgpu_fence_wait_polling(ring, ring->fence_drv.sync_seq,
+ adev->usec_timeout);
+ if (r < 1) {
+ DRM_ERROR("MES failed to response msg=%d\n",
+ x_pkt->header.opcode);
+ return -ETIMEDOUT;
+ }
+
+ return 0;
+}
+
static int mes_v10_1_add_hw_queue(struct amdgpu_mes *mes,
struct mes_add_queue_input *input)
{
--
2.25.4
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH 069/207] drm/amdgpu/mes10.1: implement adding hardware queue
2020-06-01 17:59 [PATCH 000/207] Add Support for Sienna Cichlid Alex Deucher
` (63 preceding siblings ...)
2020-06-01 18:00 ` [PATCH 068/207] drm/amdgpu/mes10.1: add the helper function for mes command submission Alex Deucher
@ 2020-06-01 18:00 ` Alex Deucher
2020-06-01 18:00 ` [PATCH 070/207] drm/amdgpu/mes10.1: implement removing " Alex Deucher
` (17 subsequent siblings)
82 siblings, 0 replies; 88+ messages in thread
From: Alex Deucher @ 2020-06-01 18:00 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Jack Xiao, Hawking Zhang
From: Jack Xiao <Jack.Xiao@amd.com>
The routine is implemented to generate mes command
to install a hardware queue.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/mes_v10_1.c | 50 +++++++++++++++++++++++++-
1 file changed, 49 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c b/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
index 3ce77839468d..e1c0443031f9 100644
--- a/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
@@ -108,10 +108,58 @@ static int mes_v10_1_submit_pkt_and_poll_completion(struct amdgpu_mes *mes,
return 0;
}
+static int convert_to_mes_queue_type(int queue_type)
+{
+ if (queue_type == AMDGPU_RING_TYPE_GFX)
+ return MES_QUEUE_TYPE_GFX;
+ else if (queue_type == AMDGPU_RING_TYPE_COMPUTE)
+ return MES_QUEUE_TYPE_COMPUTE;
+ else if (queue_type == AMDGPU_RING_TYPE_SDMA)
+ return MES_QUEUE_TYPE_SDMA;
+ else
+ BUG();
+ return -1;
+}
+
static int mes_v10_1_add_hw_queue(struct amdgpu_mes *mes,
struct mes_add_queue_input *input)
{
- return 0;
+ struct amdgpu_device *adev = mes->adev;
+ union MESAPI__ADD_QUEUE mes_add_queue_pkt;
+
+ memset(&mes_add_queue_pkt, 0, sizeof(mes_add_queue_pkt));
+
+ mes_add_queue_pkt.header.type = MES_API_TYPE_SCHEDULER;
+ mes_add_queue_pkt.header.opcode = MES_SCH_API_ADD_QUEUE;
+ mes_add_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
+
+ mes_add_queue_pkt.process_id = input->process_id;
+ mes_add_queue_pkt.page_table_base_addr =
+ input->page_table_base_addr - adev->gmc.vram_start;
+ mes_add_queue_pkt.process_va_start = input->process_va_start;
+ mes_add_queue_pkt.process_va_end = input->process_va_end;
+ mes_add_queue_pkt.process_quantum = input->process_quantum;
+ mes_add_queue_pkt.process_context_addr = input->process_context_addr;
+ mes_add_queue_pkt.gang_quantum = input->gang_quantum;
+ mes_add_queue_pkt.gang_context_addr = input->gang_context_addr;
+ mes_add_queue_pkt.inprocess_gang_priority =
+ input->inprocess_gang_priority;
+ mes_add_queue_pkt.gang_global_priority_level =
+ input->gang_global_priority_level;
+ mes_add_queue_pkt.doorbell_offset = input->doorbell_offset;
+ mes_add_queue_pkt.mqd_addr = input->mqd_addr;
+ mes_add_queue_pkt.wptr_addr = input->wptr_addr;
+ mes_add_queue_pkt.queue_type =
+ convert_to_mes_queue_type(input->queue_type);
+ mes_add_queue_pkt.paging = input->paging;
+
+ mes_add_queue_pkt.api_status.api_completion_fence_addr =
+ mes->ring.fence_drv.gpu_addr;
+ mes_add_queue_pkt.api_status.api_completion_fence_value =
+ ++mes->ring.fence_drv.sync_seq;
+
+ return mes_v10_1_submit_pkt_and_poll_completion(mes,
+ &mes_add_queue_pkt, sizeof(mes_add_queue_pkt));
}
static int mes_v10_1_remove_hw_queue(struct amdgpu_mes *mes,
--
2.25.4
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH 070/207] drm/amdgpu/mes10.1: implement removing hardware queue
2020-06-01 17:59 [PATCH 000/207] Add Support for Sienna Cichlid Alex Deucher
` (64 preceding siblings ...)
2020-06-01 18:00 ` [PATCH 069/207] drm/amdgpu/mes10.1: implement adding hardware queue Alex Deucher
@ 2020-06-01 18:00 ` Alex Deucher
2020-06-01 18:00 ` [PATCH 071/207] drm/amdgpu/mes10.1: implement querying the scheduler status Alex Deucher
` (16 subsequent siblings)
82 siblings, 0 replies; 88+ messages in thread
From: Alex Deucher @ 2020-06-01 18:00 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Jack Xiao, Hawking Zhang
From: Jack Xiao <Jack.Xiao@amd.com>
The routine is implemented to generate mes command to remove
a specified hardware queue.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/mes_v10_1.c | 19 ++++++++++++++++++-
1 file changed, 18 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c b/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
index e1c0443031f9..bd986e5fa474 100644
--- a/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
@@ -165,7 +165,24 @@ static int mes_v10_1_add_hw_queue(struct amdgpu_mes *mes,
static int mes_v10_1_remove_hw_queue(struct amdgpu_mes *mes,
struct mes_remove_queue_input *input)
{
- return 0;
+ union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt;
+
+ memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt));
+
+ mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER;
+ mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE;
+ mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
+
+ mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset;
+ mes_remove_queue_pkt.gang_context_addr = input->gang_context_addr;
+
+ mes_remove_queue_pkt.api_status.api_completion_fence_addr =
+ mes->ring.fence_drv.gpu_addr;
+ mes_remove_queue_pkt.api_status.api_completion_fence_value =
+ ++mes->ring.fence_drv.sync_seq;
+
+ return mes_v10_1_submit_pkt_and_poll_completion(mes,
+ &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt));
}
static int mes_v10_1_suspend_gang(struct amdgpu_mes *mes,
--
2.25.4
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH 071/207] drm/amdgpu/mes10.1: implement querying the scheduler status
2020-06-01 17:59 [PATCH 000/207] Add Support for Sienna Cichlid Alex Deucher
` (65 preceding siblings ...)
2020-06-01 18:00 ` [PATCH 070/207] drm/amdgpu/mes10.1: implement removing " Alex Deucher
@ 2020-06-01 18:00 ` Alex Deucher
2020-06-01 18:00 ` [PATCH 072/207] drm/amdgpu/mes10.1: implement setting hardware resources Alex Deucher
` (15 subsequent siblings)
82 siblings, 0 replies; 88+ messages in thread
From: Alex Deucher @ 2020-06-01 18:00 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Jack Xiao, Hawking Zhang
From: Jack Xiao <Jack.Xiao@amd.com>
The routine is implemented to generate mes command
to query the status of hardware scheduler.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/mes_v10_1.c | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c b/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
index bd986e5fa474..27374561ff4d 100644
--- a/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
@@ -197,6 +197,25 @@ static int mes_v10_1_resume_gang(struct amdgpu_mes *mes,
return 0;
}
+static int mes_v10_1_query_sched_status(struct amdgpu_mes *mes)
+{
+ union MESAPI__QUERY_MES_STATUS mes_status_pkt;
+
+ memset(&mes_status_pkt, 0, sizeof(mes_status_pkt));
+
+ mes_status_pkt.header.type = MES_API_TYPE_SCHEDULER;
+ mes_status_pkt.header.opcode = MES_SCH_API_QUERY_SCHEDULER_STATUS;
+ mes_status_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
+
+ mes_status_pkt.api_status.api_completion_fence_addr =
+ mes->ring.fence_drv.gpu_addr;
+ mes_status_pkt.api_status.api_completion_fence_value =
+ ++mes->ring.fence_drv.sync_seq;
+
+ return mes_v10_1_submit_pkt_and_poll_completion(mes,
+ &mes_status_pkt, sizeof(mes_status_pkt));
+}
+
static const struct amdgpu_mes_funcs mes_v10_1_funcs = {
.add_hw_queue = mes_v10_1_add_hw_queue,
.remove_hw_queue = mes_v10_1_remove_hw_queue,
--
2.25.4
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH 072/207] drm/amdgpu/mes10.1: implement setting hardware resources
2020-06-01 17:59 [PATCH 000/207] Add Support for Sienna Cichlid Alex Deucher
` (66 preceding siblings ...)
2020-06-01 18:00 ` [PATCH 071/207] drm/amdgpu/mes10.1: implement querying the scheduler status Alex Deucher
@ 2020-06-01 18:00 ` Alex Deucher
2020-06-01 18:00 ` [PATCH 073/207] drm/amdgpu/mes10.1: add sienna_cichlid mes firmware support Alex Deucher
` (14 subsequent siblings)
82 siblings, 0 replies; 88+ messages in thread
From: Alex Deucher @ 2020-06-01 18:00 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Jack Xiao, Hawking Zhang
From: Jack Xiao <Jack.Xiao@amd.com>
The routine is implemented to generate mes command to
assign the hardware resources which can be scheduled
to mes.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/mes_v10_1.c | 41 ++++++++++++++++++++++++++
1 file changed, 41 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c b/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
index 27374561ff4d..8102ffcf949c 100644
--- a/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
@@ -216,6 +216,47 @@ static int mes_v10_1_query_sched_status(struct amdgpu_mes *mes)
&mes_status_pkt, sizeof(mes_status_pkt));
}
+static int mes_v10_1_set_hw_resources(struct amdgpu_mes *mes)
+{
+ int i;
+ struct amdgpu_device *adev = mes->adev;
+ union MESAPI_SET_HW_RESOURCES mes_set_hw_res_pkt;
+
+ memset(&mes_set_hw_res_pkt, 0, sizeof(mes_set_hw_res_pkt));
+
+ mes_set_hw_res_pkt.header.type = MES_API_TYPE_SCHEDULER;
+ mes_set_hw_res_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC;
+ mes_set_hw_res_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
+
+ mes_set_hw_res_pkt.vmid_mask_mmhub = mes->vmid_mask_mmhub;
+ mes_set_hw_res_pkt.vmid_mask_gfxhub = mes->vmid_mask_gfxhub;
+ mes_set_hw_res_pkt.gds_size = adev->gds.gds_size;
+ mes_set_hw_res_pkt.paging_vmid = 0;
+ mes_set_hw_res_pkt.g_sch_ctx_gpu_mc_ptr = mes->sch_ctx_gpu_addr;
+
+ for (i = 0; i < MAX_COMPUTE_PIPES; i++)
+ mes_set_hw_res_pkt.compute_hqd_mask[i] =
+ mes->compute_hqd_mask[i];
+
+ for (i = 0; i < MAX_GFX_PIPES; i++)
+ mes_set_hw_res_pkt.gfx_hqd_mask[i] = mes->gfx_hqd_mask[i];
+
+ for (i = 0; i < MAX_SDMA_PIPES; i++)
+ mes_set_hw_res_pkt.sdma_hqd_mask[i] = mes->sdma_hqd_mask[i];
+
+ for (i = 0; i < AMD_PRIORITY_NUM_LEVELS; i++)
+ mes_set_hw_res_pkt.agreegated_doorbells[i] =
+ mes->agreegated_doorbells[i];
+
+ mes_set_hw_res_pkt.api_status.api_completion_fence_addr =
+ mes->ring.fence_drv.gpu_addr;
+ mes_set_hw_res_pkt.api_status.api_completion_fence_value =
+ ++mes->ring.fence_drv.sync_seq;
+
+ return mes_v10_1_submit_pkt_and_poll_completion(mes,
+ &mes_set_hw_res_pkt, sizeof(mes_set_hw_res_pkt));
+}
+
static const struct amdgpu_mes_funcs mes_v10_1_funcs = {
.add_hw_queue = mes_v10_1_add_hw_queue,
.remove_hw_queue = mes_v10_1_remove_hw_queue,
--
2.25.4
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH 073/207] drm/amdgpu/mes10.1: add sienna_cichlid mes firmware support
2020-06-01 17:59 [PATCH 000/207] Add Support for Sienna Cichlid Alex Deucher
` (67 preceding siblings ...)
2020-06-01 18:00 ` [PATCH 072/207] drm/amdgpu/mes10.1: implement setting hardware resources Alex Deucher
@ 2020-06-01 18:00 ` Alex Deucher
2020-06-01 18:00 ` [PATCH 074/207] drm/amdgpu/mes10.1: copy mes fw info into global fw array Alex Deucher
` (13 subsequent siblings)
82 siblings, 0 replies; 88+ messages in thread
From: Alex Deucher @ 2020-06-01 18:00 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Jack Xiao, Hawking Zhang
From: Jack Xiao <Jack.Xiao@amd.com>
Add sienna_cichlid mes firmware support.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/mes_v10_1.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c b/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
index 8102ffcf949c..a6a96cf96b22 100644
--- a/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
@@ -32,6 +32,7 @@
#include "mes_api_def.h"
MODULE_FIRMWARE("amdgpu/navi10_mes.bin");
+MODULE_FIRMWARE("amdgpu/sienna_cichlid_mes.bin");
static int mes_v10_1_hw_fini(void *handle);
@@ -275,6 +276,9 @@ static int mes_v10_1_init_microcode(struct amdgpu_device *adev)
case CHIP_NAVI10:
chip_name = "navi10";
break;
+ case CHIP_SIENNA_CICHLID:
+ chip_name = "sienna_cichlid";
+ break;
default:
BUG();
}
--
2.25.4
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH 074/207] drm/amdgpu/mes10.1: copy mes fw info into global fw array
2020-06-01 17:59 [PATCH 000/207] Add Support for Sienna Cichlid Alex Deucher
` (68 preceding siblings ...)
2020-06-01 18:00 ` [PATCH 073/207] drm/amdgpu/mes10.1: add sienna_cichlid mes firmware support Alex Deucher
@ 2020-06-01 18:00 ` Alex Deucher
2020-06-01 18:00 ` [PATCH 075/207] drm/amdgpu: upload mes firmware to gpu buffer Alex Deucher
` (12 subsequent siblings)
82 siblings, 0 replies; 88+ messages in thread
From: Alex Deucher @ 2020-06-01 18:00 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Jack Xiao, Hawking Zhang
From: Jack Xiao <Jack.Xiao@amd.com>
Copy mes firmware info into into global fw array, preparing
for fw front door loading.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/mes_v10_1.c | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c b/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
index a6a96cf96b22..a0fd3c3c7397 100644
--- a/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
@@ -271,6 +271,7 @@ static int mes_v10_1_init_microcode(struct amdgpu_device *adev)
char fw_name[30];
int err;
const struct mes_firmware_header_v1_0 *mes_hdr;
+ struct amdgpu_firmware_info *info;
switch (adev->asic_type) {
case CHIP_NAVI10:
@@ -306,6 +307,22 @@ static int mes_v10_1_init_microcode(struct amdgpu_device *adev)
le32_to_cpu(mes_hdr->mes_data_start_addr_lo) |
((uint64_t)(le32_to_cpu(mes_hdr->mes_data_start_addr_hi)) << 32);
+ if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
+ info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MES];
+ info->ucode_id = AMDGPU_UCODE_ID_CP_MES;
+ info->fw = adev->mes.fw;
+ adev->firmware.fw_size +=
+ ALIGN(le32_to_cpu(mes_hdr->mes_ucode_size_bytes),
+ PAGE_SIZE);
+
+ info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MES_DATA];
+ info->ucode_id = AMDGPU_UCODE_ID_CP_MES_DATA;
+ info->fw = adev->mes.fw;
+ adev->firmware.fw_size +=
+ ALIGN(le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes),
+ PAGE_SIZE);
+ }
+
return 0;
}
--
2.25.4
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH 075/207] drm/amdgpu: upload mes firmware to gpu buffer
2020-06-01 17:59 [PATCH 000/207] Add Support for Sienna Cichlid Alex Deucher
` (69 preceding siblings ...)
2020-06-01 18:00 ` [PATCH 074/207] drm/amdgpu/mes10.1: copy mes fw info into global fw array Alex Deucher
@ 2020-06-01 18:00 ` Alex Deucher
2020-06-01 18:00 ` [PATCH 076/207] drm/amdgpu/psp: convert amdgpu mes ucode type Alex Deucher
` (11 subsequent siblings)
82 siblings, 0 replies; 88+ messages in thread
From: Alex Deucher @ 2020-06-01 18:00 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Jack Xiao, Hawking Zhang
From: Jack Xiao <Jack.Xiao@amd.com>
Copy mes firmware to gpu buffer.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
index 74ac14466a78..cf3438696fce 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
@@ -449,6 +449,7 @@ static int amdgpu_ucode_init_single_fw(struct amdgpu_device *adev,
const struct gfx_firmware_header_v1_0 *cp_hdr = NULL;
const struct dmcu_firmware_header_v1_0 *dmcu_hdr = NULL;
const struct dmcub_firmware_header_v1_0 *dmcub_hdr = NULL;
+ const struct mes_firmware_header_v1_0 *mes_hdr = NULL;
if (NULL == ucode->fw)
return 0;
@@ -463,12 +464,15 @@ static int amdgpu_ucode_init_single_fw(struct amdgpu_device *adev,
cp_hdr = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data;
dmcu_hdr = (const struct dmcu_firmware_header_v1_0 *)ucode->fw->data;
dmcub_hdr = (const struct dmcub_firmware_header_v1_0 *)ucode->fw->data;
+ mes_hdr = (const struct mes_firmware_header_v1_0 *)ucode->fw->data;
if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP ||
(ucode->ucode_id != AMDGPU_UCODE_ID_CP_MEC1 &&
ucode->ucode_id != AMDGPU_UCODE_ID_CP_MEC2 &&
ucode->ucode_id != AMDGPU_UCODE_ID_CP_MEC1_JT &&
ucode->ucode_id != AMDGPU_UCODE_ID_CP_MEC2_JT &&
+ ucode->ucode_id != AMDGPU_UCODE_ID_CP_MES &&
+ ucode->ucode_id != AMDGPU_UCODE_ID_CP_MES_DATA &&
ucode->ucode_id != AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL &&
ucode->ucode_id != AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM &&
ucode->ucode_id != AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM &&
@@ -528,6 +532,16 @@ static int amdgpu_ucode_init_single_fw(struct amdgpu_device *adev,
ucode->ucode_size = adev->gfx.rlc.save_restore_list_srm_size_bytes;
memcpy(ucode->kaddr, adev->gfx.rlc.save_restore_list_srm,
ucode->ucode_size);
+ } else if (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MES) {
+ ucode->ucode_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes);
+ memcpy(ucode->kaddr, (void *)((uint8_t *)adev->mes.fw->data +
+ le32_to_cpu(mes_hdr->mes_ucode_offset_bytes)),
+ ucode->ucode_size);
+ } else if (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MES_DATA) {
+ ucode->ucode_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes);
+ memcpy(ucode->kaddr, (void *)((uint8_t *)adev->mes.fw->data +
+ le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes)),
+ ucode->ucode_size);
}
return 0;
--
2.25.4
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH 076/207] drm/amdgpu/psp: convert amdgpu mes ucode type
2020-06-01 17:59 [PATCH 000/207] Add Support for Sienna Cichlid Alex Deucher
` (70 preceding siblings ...)
2020-06-01 18:00 ` [PATCH 075/207] drm/amdgpu: upload mes firmware to gpu buffer Alex Deucher
@ 2020-06-01 18:00 ` Alex Deucher
2020-06-01 18:00 ` [PATCH 077/207] drm/amdgpu: no need to set up GPU scheduler for mes ring Alex Deucher
` (10 subsequent siblings)
82 siblings, 0 replies; 88+ messages in thread
From: Alex Deucher @ 2020-06-01 18:00 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Jack Xiao, Hawking Zhang
From: Jack Xiao <Jack.Xiao@amd.com>
Convert to psp defined ucode item, so that psp can recognize them.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index 6c05071defdd..4ed542b69377 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -1428,6 +1428,12 @@ static int psp_get_fw_type(struct amdgpu_firmware_info *ucode,
case AMDGPU_UCODE_ID_SDMA7:
*type = GFX_FW_TYPE_SDMA7;
break;
+ case AMDGPU_UCODE_ID_CP_MES:
+ *type = GFX_FW_TYPE_CP_MES;
+ break;
+ case AMDGPU_UCODE_ID_CP_MES_DATA:
+ *type = GFX_FW_TYPE_MES_STACK;
+ break;
case AMDGPU_UCODE_ID_CP_CE:
*type = GFX_FW_TYPE_CP_CE;
break;
--
2.25.4
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH 077/207] drm/amdgpu: no need to set up GPU scheduler for mes ring
2020-06-01 17:59 [PATCH 000/207] Add Support for Sienna Cichlid Alex Deucher
` (71 preceding siblings ...)
2020-06-01 18:00 ` [PATCH 076/207] drm/amdgpu/psp: convert amdgpu mes ucode type Alex Deucher
@ 2020-06-01 18:00 ` Alex Deucher
2020-06-02 9:30 ` Christian König
2020-06-01 18:00 ` [PATCH 078/207] drm/amdgpu/mes10.1: update mes initialization Alex Deucher
` (9 subsequent siblings)
82 siblings, 1 reply; 88+ messages in thread
From: Alex Deucher @ 2020-06-01 18:00 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Jack Xiao, Christian König, Hawking Zhang
From: Jack Xiao <Jack.Xiao@amd.com>
As mes ring directly submits to hardwared,
it's no need to set up GPU scheduler for mes ring.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
index 3414e119f0cb..8712a2e1b869 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
@@ -469,8 +469,9 @@ int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring,
if (!ring->fence_drv.fences)
return -ENOMEM;
- /* No need to setup the GPU scheduler for KIQ ring */
- if (ring->funcs->type != AMDGPU_RING_TYPE_KIQ) {
+ /* No need to setup the GPU scheduler for KIQ and MES ring */
+ if (ring->funcs->type != AMDGPU_RING_TYPE_KIQ ||
+ ring->funcs->type != AMDGPU_RING_TYPE_MES) {
switch (ring->funcs->type) {
case AMDGPU_RING_TYPE_GFX:
timeout = adev->gfx_timeout;
--
2.25.4
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH 078/207] drm/amdgpu/mes10.1: update mes initialization
2020-06-01 17:59 [PATCH 000/207] Add Support for Sienna Cichlid Alex Deucher
` (72 preceding siblings ...)
2020-06-01 18:00 ` [PATCH 077/207] drm/amdgpu: no need to set up GPU scheduler for mes ring Alex Deucher
@ 2020-06-01 18:00 ` Alex Deucher
2020-06-01 18:00 ` [PATCH 079/207] drm/amdgpu: add mes block to sienna_cichlid Alex Deucher
` (8 subsequent siblings)
82 siblings, 0 replies; 88+ messages in thread
From: Alex Deucher @ 2020-06-01 18:00 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Jack Xiao, Hawking Zhang
From: Jack Xiao <Jack.Xiao@amd.com>
Update mes initialization sequence.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/mes_v10_1.c | 20 +++++++++++++++-----
1 file changed, 15 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c b/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
index a0fd3c3c7397..8d2469fe2174 100644
--- a/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
@@ -825,6 +825,7 @@ static int mes_v10_1_sw_init(void *handle)
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
adev->mes.adev = adev;
+ adev->mes.funcs = &mes_v10_1_funcs;
r = mes_v10_1_init_microcode(adev);
if (r)
@@ -875,20 +876,29 @@ static int mes_v10_1_hw_init(void *handle)
DRM_ERROR("failed to MES fw, r=%d\n", r);
return r;
}
- } else {
- DRM_ERROR("only support direct fw loading on MES\n");
- return -EINVAL;
}
mes_v10_1_enable(adev, true);
r = mes_v10_1_queue_init(adev);
+ if (r)
+ goto failure;
+
+ r = mes_v10_1_set_hw_resources(&adev->mes);
+ if (r)
+ goto failure;
+
+ r = mes_v10_1_query_sched_status(&adev->mes);
if (r) {
- mes_v10_1_hw_fini(adev);
- return r;
+ DRM_ERROR("MES is busy\n");
+ goto failure;
}
return 0;
+
+failure:
+ mes_v10_1_hw_fini(adev);
+ return r;
}
static int mes_v10_1_hw_fini(void *handle)
--
2.25.4
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH 079/207] drm/amdgpu: add mes block to sienna_cichlid
2020-06-01 17:59 [PATCH 000/207] Add Support for Sienna Cichlid Alex Deucher
` (73 preceding siblings ...)
2020-06-01 18:00 ` [PATCH 078/207] drm/amdgpu/mes10.1: update mes initialization Alex Deucher
@ 2020-06-01 18:00 ` Alex Deucher
2020-06-01 18:00 ` [PATCH 080/207] drm/amdgpu: update the num of queue per pipe for mec on sienna_cichlid Alex Deucher
` (7 subsequent siblings)
82 siblings, 0 replies; 88+ messages in thread
From: Alex Deucher @ 2020-06-01 18:00 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Jack Xiao, Hawking Zhang
From: Jack Xiao <Jack.Xiao@amd.com>
Add mes block support to sienna_cichlid.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/nv.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index cad66cb1b6c2..587d0b6821f8 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -497,6 +497,8 @@ int nv_set_ip_blocks(struct amdgpu_device *adev)
amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block);
+ if (adev->enable_mes)
+ amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block);
break;
default:
return -EINVAL;
--
2.25.4
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH 080/207] drm/amdgpu: update the num of queue per pipe for mec on sienna_cichlid
2020-06-01 17:59 [PATCH 000/207] Add Support for Sienna Cichlid Alex Deucher
` (74 preceding siblings ...)
2020-06-01 18:00 ` [PATCH 079/207] drm/amdgpu: add mes block to sienna_cichlid Alex Deucher
@ 2020-06-01 18:00 ` Alex Deucher
2020-06-01 18:00 ` [PATCH 081/207] drm/amdgpu/mes: correct register offset for sienna_cichlid Alex Deucher
` (6 subsequent siblings)
82 siblings, 0 replies; 88+ messages in thread
From: Alex Deucher @ 2020-06-01 18:00 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Likun Gao, Huang Rui
From: Likun Gao <Likun.Gao@amd.com>
The number of queue per pipe for mec on sienna_cichlid should be 4.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 5cbee23d2ff8..69458d5ccb09 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -4147,7 +4147,6 @@ static int gfx_v10_0_sw_init(void *handle)
case CHIP_NAVI10:
case CHIP_NAVI14:
case CHIP_NAVI12:
- case CHIP_SIENNA_CICHLID:
adev->gfx.me.num_me = 1;
adev->gfx.me.num_pipe_per_me = 1;
adev->gfx.me.num_queue_per_pipe = 1;
@@ -4155,6 +4154,14 @@ static int gfx_v10_0_sw_init(void *handle)
adev->gfx.mec.num_pipe_per_mec = 4;
adev->gfx.mec.num_queue_per_pipe = 8;
break;
+ case CHIP_SIENNA_CICHLID:
+ adev->gfx.me.num_me = 1;
+ adev->gfx.me.num_pipe_per_me = 2;
+ adev->gfx.me.num_queue_per_pipe = 1;
+ adev->gfx.mec.num_mec = 2;
+ adev->gfx.mec.num_pipe_per_mec = 4;
+ adev->gfx.mec.num_queue_per_pipe = 4;
+ break;
default:
adev->gfx.me.num_me = 1;
adev->gfx.me.num_pipe_per_me = 1;
--
2.25.4
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH 081/207] drm/amdgpu/mes: correct register offset for sienna_cichlid
2020-06-01 17:59 [PATCH 000/207] Add Support for Sienna Cichlid Alex Deucher
` (75 preceding siblings ...)
2020-06-01 18:00 ` [PATCH 080/207] drm/amdgpu: update the num of queue per pipe for mec on sienna_cichlid Alex Deucher
@ 2020-06-01 18:00 ` Alex Deucher
2020-06-01 18:00 ` [PATCH 082/207] drm/amdgpu: add VCN3.0 support for Sienna_Cichlid Alex Deucher
` (5 subsequent siblings)
82 siblings, 0 replies; 88+ messages in thread
From: Alex Deucher @ 2020-06-01 18:00 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Likun Gao, Jack Xiao
From: Likun Gao <Likun.Gao@amd.com>
Correct CP_MES_IC_OP_CNTL register address for sienna_cichlid on mes v10.1.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/mes_v10_1.c | 39 +++++++++++++++++++++++---
1 file changed, 35 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c b/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
index 8d2469fe2174..447bee159089 100644
--- a/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
@@ -31,6 +31,9 @@
#include "v10_structs.h"
#include "mes_api_def.h"
+#define mmCP_MES_IC_OP_CNTL_Sienna_Cichlid 0x2820
+#define mmCP_MES_IC_OP_CNTL_Sienna_Cichlid_BASE_IDX 1
+
MODULE_FIRMWARE("amdgpu/navi10_mes.bin");
MODULE_FIRMWARE("amdgpu/sienna_cichlid_mes.bin");
@@ -490,15 +493,43 @@ static int mes_v10_1_load_microcode(struct amdgpu_device *adev)
WREG32_SOC15(GC, 0, mmCP_MES_MDBOUND_LO, 0x3FFFF);
/* invalidate ICACHE */
- data = RREG32_SOC15(GC, 0, mmCP_MES_IC_OP_CNTL);
+ switch (adev->asic_type) {
+ case CHIP_SIENNA_CICHLID:
+ data = RREG32_SOC15(GC, 0, mmCP_MES_IC_OP_CNTL_Sienna_Cichlid);
+ break;
+ default:
+ data = RREG32_SOC15(GC, 0, mmCP_MES_IC_OP_CNTL);
+ break;
+ }
data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 0);
data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, INVALIDATE_CACHE, 1);
- WREG32_SOC15(GC, 0, mmCP_MES_IC_OP_CNTL, data);
+ switch (adev->asic_type) {
+ case CHIP_SIENNA_CICHLID:
+ WREG32_SOC15(GC, 0, mmCP_MES_IC_OP_CNTL_Sienna_Cichlid, data);
+ break;
+ default:
+ WREG32_SOC15(GC, 0, mmCP_MES_IC_OP_CNTL, data);
+ break;
+ }
/* prime the ICACHE. */
- data = RREG32_SOC15(GC, 0, mmCP_MES_IC_OP_CNTL);
+ switch (adev->asic_type) {
+ case CHIP_SIENNA_CICHLID:
+ data = RREG32_SOC15(GC, 0, mmCP_MES_IC_OP_CNTL_Sienna_Cichlid);
+ break;
+ default:
+ data = RREG32_SOC15(GC, 0, mmCP_MES_IC_OP_CNTL);
+ break;
+ }
data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 1);
- WREG32_SOC15(GC, 0, mmCP_MES_IC_OP_CNTL, data);
+ switch (adev->asic_type) {
+ case CHIP_SIENNA_CICHLID:
+ WREG32_SOC15(GC, 0, mmCP_MES_IC_OP_CNTL_Sienna_Cichlid, data);
+ break;
+ default:
+ WREG32_SOC15(GC, 0, mmCP_MES_IC_OP_CNTL, data);
+ break;
+ }
nv_grbm_select(adev, 0, 0, 0, 0);
mutex_unlock(&adev->srbm_mutex);
--
2.25.4
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH 082/207] drm/amdgpu: add VCN3.0 support for Sienna_Cichlid
2020-06-01 17:59 [PATCH 000/207] Add Support for Sienna Cichlid Alex Deucher
` (76 preceding siblings ...)
2020-06-01 18:00 ` [PATCH 081/207] drm/amdgpu/mes: correct register offset for sienna_cichlid Alex Deucher
@ 2020-06-01 18:00 ` Alex Deucher
2020-06-01 18:00 ` [PATCH 083/207] drm/amdgpu: add Sienna_Cichlid VCN PG and CG support (v2) Alex Deucher
` (4 subsequent siblings)
82 siblings, 0 replies; 88+ messages in thread
From: Alex Deucher @ 2020-06-01 18:00 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, James Zhu, Leo Liu
From: Leo Liu <leo.liu@amd.com>
With basic IP block functions and ring functions
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/Makefile | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 1 +
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 971 ++++++++++++++++++++++++
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.h | 29 +
4 files changed, 1002 insertions(+)
create mode 100644 drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
create mode 100644 drivers/gpu/drm/amd/amdgpu/vcn_v3_0.h
diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile
index 38b6ec10751f..3cab3fea59d4 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -155,6 +155,7 @@ amdgpu-y += \
vcn_v1_0.o \
vcn_v2_0.o \
vcn_v2_5.o \
+ vcn_v3_0.o \
amdgpu_jpeg.o \
jpeg_v1_0.o \
jpeg_v2_0.o \
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
index 90aa12b22725..7a2d5f8d1247 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
@@ -142,6 +142,7 @@ enum fw_queue_mode {
enum engine_status_constants {
UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON = 0x2AAAA0,
UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON_2_0 = 0xAAAA0,
+ UVD_PGFSM_STATUS__UVDM_UVDU_UVDLM_PWR_ON_3_0 = 0x2A2A8AA0,
UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON = 0x00000002,
UVD_STATUS__UVD_BUSY = 0x00000004,
GB_ADDR_CONFIG_DEFAULT = 0x26010011,
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
new file mode 100644
index 000000000000..2833f06fb4bb
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
@@ -0,0 +1,971 @@
+/*
+ * Copyright 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#include <linux/firmware.h>
+#include "amdgpu.h"
+#include "amdgpu_vcn.h"
+#include "amdgpu_pm.h"
+#include "soc15.h"
+#include "soc15d.h"
+#include "vcn_v2_0.h"
+
+#include "vcn/vcn_3_0_0_offset.h"
+#include "vcn/vcn_3_0_0_sh_mask.h"
+#include "ivsrcid/vcn/irqsrcs_vcn_2_0.h"
+
+#define mmUVD_CONTEXT_ID_INTERNAL_OFFSET 0x27
+#define mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET 0x0f
+#define mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET 0x10
+#define mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET 0x11
+#define mmUVD_NO_OP_INTERNAL_OFFSET 0x29
+#define mmUVD_GP_SCRATCH8_INTERNAL_OFFSET 0x66
+#define mmUVD_SCRATCH9_INTERNAL_OFFSET 0xc01d
+
+#define mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET 0x431
+#define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET 0x3b4
+#define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET 0x3b5
+#define mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET 0x25c
+
+#define VCN_INSTANCES_SIENNA_CICHLID 2
+
+static void vcn_v3_0_set_dec_ring_funcs(struct amdgpu_device *adev);
+static void vcn_v3_0_set_enc_ring_funcs(struct amdgpu_device *adev);
+static void vcn_v3_0_set_irq_funcs(struct amdgpu_device *adev);
+static int vcn_v3_0_set_powergating_state(void *handle,
+ enum amd_powergating_state state);
+
+static int amdgpu_ih_clientid_vcns[] = {
+ SOC15_IH_CLIENTID_VCN,
+ SOC15_IH_CLIENTID_VCN1
+};
+
+/**
+ * vcn_v3_0_early_init - set function pointers
+ *
+ * @handle: amdgpu_device pointer
+ *
+ * Set ring and irq function pointers
+ */
+static int vcn_v3_0_early_init(void *handle)
+{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ if (adev->asic_type == CHIP_SIENNA_CICHLID) {
+ u32 harvest;
+ int i;
+
+ adev->vcn.num_vcn_inst = VCN_INSTANCES_SIENNA_CICHLID;
+ for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
+ harvest = RREG32_SOC15(VCN, i, mmCC_UVD_HARVESTING);
+ if (harvest & CC_UVD_HARVESTING__UVD_DISABLE_MASK)
+ adev->vcn.harvest_config |= 1 << i;
+ }
+
+ if (adev->vcn.harvest_config == (AMDGPU_VCN_HARVEST_VCN0 |
+ AMDGPU_VCN_HARVEST_VCN1))
+ /* both instances are harvested, disable the block */
+ return -ENOENT;
+ } else
+ adev->vcn.num_vcn_inst = 1;
+
+ adev->vcn.num_enc_rings = 2;
+
+ vcn_v3_0_set_dec_ring_funcs(adev);
+ vcn_v3_0_set_enc_ring_funcs(adev);
+ vcn_v3_0_set_irq_funcs(adev);
+
+ return 0;
+}
+
+/**
+ * vcn_v3_0_sw_init - sw init for VCN block
+ *
+ * @handle: amdgpu_device pointer
+ *
+ * Load firmware and sw initialization
+ */
+static int vcn_v3_0_sw_init(void *handle)
+{
+ struct amdgpu_ring *ring;
+ int i, j, r;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
+ r = amdgpu_vcn_sw_init(adev);
+ if (r)
+ return r;
+
+ if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
+ const struct common_firmware_header *hdr;
+ hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
+ adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].ucode_id = AMDGPU_UCODE_ID_VCN;
+ adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].fw = adev->vcn.fw;
+ adev->firmware.fw_size +=
+ ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE);
+
+ if (adev->vcn.num_vcn_inst == VCN_INSTANCES_SIENNA_CICHLID) {
+ adev->firmware.ucode[AMDGPU_UCODE_ID_VCN1].ucode_id = AMDGPU_UCODE_ID_VCN1;
+ adev->firmware.ucode[AMDGPU_UCODE_ID_VCN1].fw = adev->vcn.fw;
+ adev->firmware.fw_size +=
+ ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE);
+ }
+ DRM_INFO("PSP loading VCN firmware\n");
+ }
+
+ r = amdgpu_vcn_resume(adev);
+ if (r)
+ return r;
+
+ for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
+ if (adev->vcn.harvest_config & (1 << i))
+ continue;
+
+ adev->vcn.internal.context_id = mmUVD_CONTEXT_ID_INTERNAL_OFFSET;
+ adev->vcn.internal.ib_vmid = mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET;
+ adev->vcn.internal.ib_bar_low = mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET;
+ adev->vcn.internal.ib_bar_high = mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET;
+ adev->vcn.internal.ib_size = mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET;
+ adev->vcn.internal.gp_scratch8 = mmUVD_GP_SCRATCH8_INTERNAL_OFFSET;
+
+ adev->vcn.internal.scratch9 = mmUVD_SCRATCH9_INTERNAL_OFFSET;
+ adev->vcn.inst[i].external.scratch9 = SOC15_REG_OFFSET(VCN, i, mmUVD_SCRATCH9);
+ adev->vcn.internal.data0 = mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET;
+ adev->vcn.inst[i].external.data0 = SOC15_REG_OFFSET(VCN, i, mmUVD_GPCOM_VCPU_DATA0);
+ adev->vcn.internal.data1 = mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET;
+ adev->vcn.inst[i].external.data1 = SOC15_REG_OFFSET(VCN, i, mmUVD_GPCOM_VCPU_DATA1);
+ adev->vcn.internal.cmd = mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET;
+ adev->vcn.inst[i].external.cmd = SOC15_REG_OFFSET(VCN, i, mmUVD_GPCOM_VCPU_CMD);
+ adev->vcn.internal.nop = mmUVD_NO_OP_INTERNAL_OFFSET;
+ adev->vcn.inst[i].external.nop = SOC15_REG_OFFSET(VCN, i, mmUVD_NO_OP);
+
+ /* VCN DEC TRAP */
+ r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i],
+ VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, &adev->vcn.inst[i].irq);
+ if (r)
+ return r;
+
+ ring = &adev->vcn.inst[i].ring_dec;
+ ring->use_doorbell = true;
+ ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 8 * i;
+ sprintf(ring->name, "vcn_dec_%d", i);
+ r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0,
+ AMDGPU_RING_PRIO_DEFAULT);
+ if (r)
+ return r;
+
+ for (j = 0; j < adev->vcn.num_enc_rings; ++j) {
+ /* VCN ENC TRAP */
+ r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i],
+ j + VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst[i].irq);
+ if (r)
+ return r;
+
+ ring = &adev->vcn.inst[i].ring_enc[j];
+ ring->use_doorbell = true;
+ ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 2 + j + 8 * i;
+ sprintf(ring->name, "vcn_enc_%d.%d", i, j);
+ r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0,
+ AMDGPU_RING_PRIO_DEFAULT);
+ if (r)
+ return r;
+ }
+ }
+
+ return 0;
+}
+
+/**
+ * vcn_v3_0_sw_fini - sw fini for VCN block
+ *
+ * @handle: amdgpu_device pointer
+ *
+ * VCN suspend and free up sw allocation
+ */
+static int vcn_v3_0_sw_fini(void *handle)
+{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ int r;
+
+ r = amdgpu_vcn_suspend(adev);
+ if (r)
+ return r;
+
+ r = amdgpu_vcn_sw_fini(adev);
+
+ return r;
+}
+
+/**
+ * vcn_v3_0_hw_init - start and test VCN block
+ *
+ * @handle: amdgpu_device pointer
+ *
+ * Initialize the hardware, boot up the VCPU and do some testing
+ */
+static int vcn_v3_0_hw_init(void *handle)
+{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_ring *ring;
+ int i, j, r;
+
+ for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
+ if (adev->vcn.harvest_config & (1 << i))
+ continue;
+
+ ring = &adev->vcn.inst[i].ring_dec;
+
+ adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,
+ ring->doorbell_index, i);
+
+ r = amdgpu_ring_test_helper(ring);
+ if (r)
+ goto done;
+
+ for (j = 0; j < adev->vcn.num_enc_rings; ++j) {
+ ring = &adev->vcn.inst[i].ring_enc[j];
+ r = amdgpu_ring_test_helper(ring);
+ if (r)
+ goto done;
+ }
+ }
+
+done:
+ if (!r)
+ DRM_INFO("VCN decode and encode initialized successfully.\n");
+
+ return r;
+}
+
+/**
+ * vcn_v3_0_hw_fini - stop the hardware block
+ *
+ * @handle: amdgpu_device pointer
+ *
+ * Stop the VCN block, mark ring as not ready any more
+ */
+static int vcn_v3_0_hw_fini(void *handle)
+{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_ring *ring;
+ int i, j;
+
+ for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
+ if (adev->vcn.harvest_config & (1 << i))
+ continue;
+
+ ring = &adev->vcn.inst[i].ring_dec;
+
+ if (RREG32_SOC15(VCN, i, mmUVD_STATUS))
+ vcn_v3_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
+
+ ring->sched.ready = false;
+
+ for (j = 0; j < adev->vcn.num_enc_rings; ++j) {
+ ring = &adev->vcn.inst[i].ring_enc[j];
+ ring->sched.ready = false;
+ }
+ }
+
+ return 0;
+}
+
+/**
+ * vcn_v3_0_suspend - suspend VCN block
+ *
+ * @handle: amdgpu_device pointer
+ *
+ * HW fini and suspend VCN block
+ */
+static int vcn_v3_0_suspend(void *handle)
+{
+ int r;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
+ r = vcn_v3_0_hw_fini(adev);
+ if (r)
+ return r;
+
+ r = amdgpu_vcn_suspend(adev);
+
+ return r;
+}
+
+/**
+ * vcn_v3_0_resume - resume VCN block
+ *
+ * @handle: amdgpu_device pointer
+ *
+ * Resume firmware and hw init VCN block
+ */
+static int vcn_v3_0_resume(void *handle)
+{
+ int r;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
+ r = amdgpu_vcn_resume(adev);
+ if (r)
+ return r;
+
+ r = vcn_v3_0_hw_init(adev);
+
+ return r;
+}
+
+/**
+ * vcn_v3_0_mc_resume - memory controller programming
+ *
+ * @adev: amdgpu_device pointer
+ * @inst: instance number
+ *
+ * Let the VCN memory controller know it's offsets
+ */
+static void vcn_v3_0_mc_resume(struct amdgpu_device *adev, int inst)
+{
+ uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4);
+ uint32_t offset;
+
+ /* cache window 0: fw */
+ if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
+ WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
+ (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo));
+ WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
+ (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi));
+ WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET0, 0);
+ offset = 0;
+ } else {
+ WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
+ lower_32_bits(adev->vcn.inst[inst].gpu_addr));
+ WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
+ upper_32_bits(adev->vcn.inst[inst].gpu_addr));
+ offset = size;
+ /* No signed header for now from firmware
+ WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET0,
+ AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
+ */
+ WREG32_SOC15(UVD, inst, mmUVD_VCPU_CACHE_OFFSET0, 0);
+ }
+ WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_SIZE0, size);
+
+ /* cache window 1: stack */
+ WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,
+ lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset));
+ WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,
+ upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset));
+ WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET1, 0);
+ WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE);
+
+ /* cache window 2: context */
+ WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,
+ lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
+ WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,
+ upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
+ WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET2, 0);
+ WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE);
+}
+
+static int vcn_v3_0_start(struct amdgpu_device *adev)
+{
+ struct amdgpu_ring *ring;
+ uint32_t rb_bufsz, tmp;
+ int i, j, k, r;
+
+ if (adev->pm.dpm_enabled)
+ amdgpu_dpm_enable_uvd(adev, true);
+
+ for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
+ if (adev->vcn.harvest_config & (1 << i))
+ continue;
+
+ /* set VCN status busy */
+ tmp = RREG32_SOC15(VCN, i, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY;
+ WREG32_SOC15(VCN, i, mmUVD_STATUS, tmp);
+
+ /* enable VCPU clock */
+ WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL),
+ UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK);
+
+ /* disable master interrupt */
+ WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN), 0,
+ ~UVD_MASTINT_EN__VCPU_EN_MASK);
+
+ /* setup mmUVD_LMI_CTRL */
+ tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL);
+ WREG32_SOC15(VCN, i, mmUVD_LMI_CTRL, tmp |
+ UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
+ UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
+ UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
+ UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK);
+
+ /* setup mmUVD_MPC_CNTL */
+ tmp = RREG32_SOC15(VCN, i, mmUVD_MPC_CNTL);
+ tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK;
+ tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT;
+ WREG32_SOC15(VCN, i, mmUVD_MPC_CNTL, tmp);
+
+ /* setup UVD_MPC_SET_MUXA0 */
+ WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUXA0,
+ ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
+ (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
+ (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
+ (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)));
+
+ /* setup UVD_MPC_SET_MUXB0 */
+ WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUXB0,
+ ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
+ (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
+ (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
+ (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)));
+
+ /* setup mmUVD_MPC_SET_MUX */
+ WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUX,
+ ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
+ (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
+ (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)));
+
+ vcn_v3_0_mc_resume(adev, i);
+
+ /* VCN global tiling registers */
+ WREG32_SOC15(VCN, i, mmUVD_GFX10_ADDR_CONFIG,
+ adev->gfx.config.gb_addr_config);
+
+ /* enable LMI MC and UMC channels */
+ WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_LMI_CTRL2), 0,
+ ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
+
+ tmp = RREG32_SOC15(VCN, i, mmUVD_SOFT_RESET);
+ tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
+ tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
+ WREG32_SOC15(VCN, i, mmUVD_SOFT_RESET, tmp);
+
+ /* unblock VCPU register access */
+ WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_RB_ARB_CTRL), 0,
+ ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);
+
+ /* release VCPU reset to boot */
+ WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0,
+ ~UVD_VCPU_CNTL__BLK_RST_MASK);
+
+ for (j = 0; j < 10; ++j) {
+ uint32_t status;
+
+ for (k = 0; k < 100; ++k) {
+ status = RREG32_SOC15(VCN, i, mmUVD_STATUS);
+ if (status & 2)
+ break;
+ mdelay(10);
+ }
+ r = 0;
+ if (status & 2)
+ break;
+
+ DRM_ERROR("VCN[%d] decode not responding, trying to reset the VCPU!!!\n", i);
+ WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL),
+ UVD_VCPU_CNTL__BLK_RST_MASK,
+ ~UVD_VCPU_CNTL__BLK_RST_MASK);
+ mdelay(10);
+ WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0,
+ ~UVD_VCPU_CNTL__BLK_RST_MASK);
+
+ mdelay(10);
+ r = -1;
+ }
+
+ if (r) {
+ DRM_ERROR("VCN[%d] decode not responding, giving up!!!\n", i);
+ return r;
+ }
+
+ /* enable master interrupt */
+ WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN),
+ UVD_MASTINT_EN__VCPU_EN_MASK,
+ ~UVD_MASTINT_EN__VCPU_EN_MASK);
+
+ /* clear the busy bit of VCN_STATUS */
+ WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_STATUS), 0,
+ ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT));
+
+ WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_VMID, 0);
+
+ ring = &adev->vcn.inst[i].ring_dec;
+ /* force RBC into idle state */
+ rb_bufsz = order_base_2(ring->ring_size);
+ tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
+ tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
+ tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
+ tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
+ tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
+ WREG32_SOC15(VCN, i, mmUVD_RBC_RB_CNTL, tmp);
+
+ /* programm the RB_BASE for ring buffer */
+ WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
+ lower_32_bits(ring->gpu_addr));
+ WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
+ upper_32_bits(ring->gpu_addr));
+
+ /* Initialize the ring buffer's read and write pointers */
+ WREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR, 0);
+
+ ring->wptr = RREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR);
+ WREG32_SOC15(VCN, i, mmUVD_RBC_RB_WPTR,
+ lower_32_bits(ring->wptr));
+ ring = &adev->vcn.inst[i].ring_enc[0];
+ WREG32_SOC15(VCN, i, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
+ WREG32_SOC15(VCN, i, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
+ WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO, ring->gpu_addr);
+ WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
+ WREG32_SOC15(VCN, i, mmUVD_RB_SIZE, ring->ring_size / 4);
+
+ ring = &adev->vcn.inst[i].ring_enc[1];
+ WREG32_SOC15(VCN, i, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
+ WREG32_SOC15(VCN, i, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
+ WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO2, ring->gpu_addr);
+ WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
+ WREG32_SOC15(VCN, i, mmUVD_RB_SIZE2, ring->ring_size / 4);
+ }
+
+ return 0;
+}
+
+static int vcn_v3_0_stop(struct amdgpu_device *adev)
+{
+ uint32_t tmp;
+ int i, r = 0;
+
+ for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
+ if (adev->vcn.harvest_config & (1 << i))
+ continue;
+
+ /* wait for vcn idle */
+ SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7, r);
+ if (r)
+ return r;
+
+ tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK |
+ UVD_LMI_STATUS__READ_CLEAN_MASK |
+ UVD_LMI_STATUS__WRITE_CLEAN_MASK |
+ UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK;
+ SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp, r);
+ if (r)
+ return r;
+
+ /* disable LMI UMC channel */
+ tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2);
+ tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK;
+ WREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2, tmp);
+ tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK|
+ UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK;
+ SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp, r);
+ if (r)
+ return r;
+
+ /* block VCPU register access */
+ WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_RB_ARB_CTRL),
+ UVD_RB_ARB_CTRL__VCPU_DIS_MASK,
+ ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);
+
+ /* reset VCPU */
+ WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL),
+ UVD_VCPU_CNTL__BLK_RST_MASK,
+ ~UVD_VCPU_CNTL__BLK_RST_MASK);
+
+ /* disable VCPU clock */
+ WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0,
+ ~(UVD_VCPU_CNTL__CLK_EN_MASK));
+
+ /* apply soft reset */
+ tmp = RREG32_SOC15(VCN, i, mmUVD_SOFT_RESET);
+ tmp |= UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
+ WREG32_SOC15(VCN, i, mmUVD_SOFT_RESET, tmp);
+ tmp = RREG32_SOC15(VCN, i, mmUVD_SOFT_RESET);
+ tmp |= UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
+ WREG32_SOC15(VCN, i, mmUVD_SOFT_RESET, tmp);
+
+ /* clear status */
+ WREG32_SOC15(VCN, i, mmUVD_STATUS, 0);
+ }
+
+ if (adev->pm.dpm_enabled)
+ amdgpu_dpm_enable_uvd(adev, false);
+
+ return 0;
+}
+
+/**
+ * vcn_v3_0_dec_ring_get_rptr - get read pointer
+ *
+ * @ring: amdgpu_ring pointer
+ *
+ * Returns the current hardware read pointer
+ */
+static uint64_t vcn_v3_0_dec_ring_get_rptr(struct amdgpu_ring *ring)
+{
+ struct amdgpu_device *adev = ring->adev;
+
+ return RREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_RPTR);
+}
+
+/**
+ * vcn_v3_0_dec_ring_get_wptr - get write pointer
+ *
+ * @ring: amdgpu_ring pointer
+ *
+ * Returns the current hardware write pointer
+ */
+static uint64_t vcn_v3_0_dec_ring_get_wptr(struct amdgpu_ring *ring)
+{
+ struct amdgpu_device *adev = ring->adev;
+
+ if (ring->use_doorbell)
+ return adev->wb.wb[ring->wptr_offs];
+ else
+ return RREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_WPTR);
+}
+
+/**
+ * vcn_v3_0_dec_ring_set_wptr - set write pointer
+ *
+ * @ring: amdgpu_ring pointer
+ *
+ * Commits the write pointer to the hardware
+ */
+static void vcn_v3_0_dec_ring_set_wptr(struct amdgpu_ring *ring)
+{
+ struct amdgpu_device *adev = ring->adev;
+
+ if (ring->use_doorbell) {
+ adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
+ WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
+ } else {
+ WREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
+ }
+}
+
+static const struct amdgpu_ring_funcs vcn_v3_0_dec_ring_vm_funcs = {
+ .type = AMDGPU_RING_TYPE_VCN_DEC,
+ .align_mask = 0xf,
+ .vmhub = AMDGPU_MMHUB_0,
+ .get_rptr = vcn_v3_0_dec_ring_get_rptr,
+ .get_wptr = vcn_v3_0_dec_ring_get_wptr,
+ .set_wptr = vcn_v3_0_dec_ring_set_wptr,
+ .emit_frame_size =
+ SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
+ SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
+ 8 + /* vcn_v2_0_dec_ring_emit_vm_flush */
+ 14 + 14 + /* vcn_v2_0_dec_ring_emit_fence x2 vm fence */
+ 6,
+ .emit_ib_size = 8, /* vcn_v2_0_dec_ring_emit_ib */
+ .emit_ib = vcn_v2_0_dec_ring_emit_ib,
+ .emit_fence = vcn_v2_0_dec_ring_emit_fence,
+ .emit_vm_flush = vcn_v2_0_dec_ring_emit_vm_flush,
+ .test_ring = amdgpu_vcn_dec_ring_test_ring,
+ .test_ib = amdgpu_vcn_dec_ring_test_ib,
+ .insert_nop = vcn_v2_0_dec_ring_insert_nop,
+ .insert_start = vcn_v2_0_dec_ring_insert_start,
+ .insert_end = vcn_v2_0_dec_ring_insert_end,
+ .pad_ib = amdgpu_ring_generic_pad_ib,
+ .begin_use = amdgpu_vcn_ring_begin_use,
+ .end_use = amdgpu_vcn_ring_end_use,
+ .emit_wreg = vcn_v2_0_dec_ring_emit_wreg,
+ .emit_reg_wait = vcn_v2_0_dec_ring_emit_reg_wait,
+ .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
+};
+
+/**
+ * vcn_v3_0_enc_ring_get_rptr - get enc read pointer
+ *
+ * @ring: amdgpu_ring pointer
+ *
+ * Returns the current hardware enc read pointer
+ */
+static uint64_t vcn_v3_0_enc_ring_get_rptr(struct amdgpu_ring *ring)
+{
+ struct amdgpu_device *adev = ring->adev;
+
+ if (ring == &adev->vcn.inst[ring->me].ring_enc[0])
+ return RREG32_SOC15(VCN, ring->me, mmUVD_RB_RPTR);
+ else
+ return RREG32_SOC15(VCN, ring->me, mmUVD_RB_RPTR2);
+}
+
+/**
+ * vcn_v3_0_enc_ring_get_wptr - get enc write pointer
+ *
+ * @ring: amdgpu_ring pointer
+ *
+ * Returns the current hardware enc write pointer
+ */
+static uint64_t vcn_v3_0_enc_ring_get_wptr(struct amdgpu_ring *ring)
+{
+ struct amdgpu_device *adev = ring->adev;
+
+ if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) {
+ if (ring->use_doorbell)
+ return adev->wb.wb[ring->wptr_offs];
+ else
+ return RREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR);
+ } else {
+ if (ring->use_doorbell)
+ return adev->wb.wb[ring->wptr_offs];
+ else
+ return RREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR2);
+ }
+}
+
+/**
+ * vcn_v3_0_enc_ring_set_wptr - set enc write pointer
+ *
+ * @ring: amdgpu_ring pointer
+ *
+ * Commits the enc write pointer to the hardware
+ */
+static void vcn_v3_0_enc_ring_set_wptr(struct amdgpu_ring *ring)
+{
+ struct amdgpu_device *adev = ring->adev;
+
+ if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) {
+ if (ring->use_doorbell) {
+ adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
+ WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
+ } else {
+ WREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
+ }
+ } else {
+ if (ring->use_doorbell) {
+ adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
+ WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
+ } else {
+ WREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
+ }
+ }
+}
+
+static const struct amdgpu_ring_funcs vcn_v3_0_enc_ring_vm_funcs = {
+ .type = AMDGPU_RING_TYPE_VCN_ENC,
+ .align_mask = 0x3f,
+ .nop = VCN_ENC_CMD_NO_OP,
+ .vmhub = AMDGPU_MMHUB_0,
+ .get_rptr = vcn_v3_0_enc_ring_get_rptr,
+ .get_wptr = vcn_v3_0_enc_ring_get_wptr,
+ .set_wptr = vcn_v3_0_enc_ring_set_wptr,
+ .emit_frame_size =
+ SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
+ SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 +
+ 4 + /* vcn_v2_0_enc_ring_emit_vm_flush */
+ 5 + 5 + /* vcn_v2_0_enc_ring_emit_fence x2 vm fence */
+ 1, /* vcn_v2_0_enc_ring_insert_end */
+ .emit_ib_size = 5, /* vcn_v2_0_enc_ring_emit_ib */
+ .emit_ib = vcn_v2_0_enc_ring_emit_ib,
+ .emit_fence = vcn_v2_0_enc_ring_emit_fence,
+ .emit_vm_flush = vcn_v2_0_enc_ring_emit_vm_flush,
+ .test_ring = amdgpu_vcn_enc_ring_test_ring,
+ .test_ib = amdgpu_vcn_enc_ring_test_ib,
+ .insert_nop = amdgpu_ring_insert_nop,
+ .insert_end = vcn_v2_0_enc_ring_insert_end,
+ .pad_ib = amdgpu_ring_generic_pad_ib,
+ .begin_use = amdgpu_vcn_ring_begin_use,
+ .end_use = amdgpu_vcn_ring_end_use,
+ .emit_wreg = vcn_v2_0_enc_ring_emit_wreg,
+ .emit_reg_wait = vcn_v2_0_enc_ring_emit_reg_wait,
+ .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
+};
+
+static void vcn_v3_0_set_dec_ring_funcs(struct amdgpu_device *adev)
+{
+ int i;
+
+ for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
+ if (adev->vcn.harvest_config & (1 << i))
+ continue;
+
+ adev->vcn.inst[i].ring_dec.funcs = &vcn_v3_0_dec_ring_vm_funcs;
+ adev->vcn.inst[i].ring_dec.me = i;
+ DRM_INFO("VCN(%d) decode is enabled in VM mode\n", i);
+ }
+}
+
+static void vcn_v3_0_set_enc_ring_funcs(struct amdgpu_device *adev)
+{
+ int i, j;
+
+ for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
+ if (adev->vcn.harvest_config & (1 << i))
+ continue;
+
+ for (j = 0; j < adev->vcn.num_enc_rings; ++j) {
+ adev->vcn.inst[i].ring_enc[j].funcs = &vcn_v3_0_enc_ring_vm_funcs;
+ adev->vcn.inst[i].ring_enc[j].me = i;
+ }
+ DRM_INFO("VCN(%d) encode is enabled in VM mode\n", i);
+ }
+}
+
+static bool vcn_v3_0_is_idle(void *handle)
+{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ int i, ret = 1;
+
+ for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
+ if (adev->vcn.harvest_config & (1 << i))
+ continue;
+
+ ret &= (RREG32_SOC15(VCN, i, mmUVD_STATUS) == UVD_STATUS__IDLE);
+ }
+
+ return ret;
+}
+
+static int vcn_v3_0_wait_for_idle(void *handle)
+{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ int i, ret = 0;
+
+ for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
+ if (adev->vcn.harvest_config & (1 << i))
+ continue;
+
+ SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE,
+ UVD_STATUS__IDLE, ret);
+ if (ret)
+ return ret;
+ }
+
+ return ret;
+}
+
+static int vcn_v3_0_set_clockgating_state(void *handle,
+ enum amd_clockgating_state state)
+{
+ return 0;
+}
+
+static int vcn_v3_0_set_powergating_state(void *handle,
+ enum amd_powergating_state state)
+{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ int ret;
+
+ if(state == adev->vcn.cur_state)
+ return 0;
+
+ if (state == AMD_PG_STATE_GATE)
+ ret = vcn_v3_0_stop(adev);
+ else
+ ret = vcn_v3_0_start(adev);
+
+ if(!ret)
+ adev->vcn.cur_state = state;
+
+ return ret;
+}
+
+static int vcn_v3_0_set_interrupt_state(struct amdgpu_device *adev,
+ struct amdgpu_irq_src *source,
+ unsigned type,
+ enum amdgpu_interrupt_state state)
+{
+ return 0;
+}
+
+static int vcn_v3_0_process_interrupt(struct amdgpu_device *adev,
+ struct amdgpu_irq_src *source,
+ struct amdgpu_iv_entry *entry)
+{
+ uint32_t ip_instance;
+
+ switch (entry->client_id) {
+ case SOC15_IH_CLIENTID_VCN:
+ ip_instance = 0;
+ break;
+ case SOC15_IH_CLIENTID_VCN1:
+ ip_instance = 1;
+ break;
+ default:
+ DRM_ERROR("Unhandled client id: %d\n", entry->client_id);
+ return 0;
+ }
+
+ DRM_DEBUG("IH: VCN TRAP\n");
+
+ switch (entry->src_id) {
+ case VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT:
+ amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_dec);
+ break;
+ case VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE:
+ amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[0]);
+ break;
+ case VCN_2_0__SRCID__UVD_ENC_LOW_LATENCY:
+ amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[1]);
+ break;
+ default:
+ DRM_ERROR("Unhandled interrupt: %d %d\n",
+ entry->src_id, entry->src_data[0]);
+ break;
+ }
+
+ return 0;
+}
+
+static const struct amdgpu_irq_src_funcs vcn_v3_0_irq_funcs = {
+ .set = vcn_v3_0_set_interrupt_state,
+ .process = vcn_v3_0_process_interrupt,
+};
+
+static void vcn_v3_0_set_irq_funcs(struct amdgpu_device *adev)
+{
+ int i;
+
+ for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
+ if (adev->vcn.harvest_config & (1 << i))
+ continue;
+
+ adev->vcn.inst[i].irq.num_types = adev->vcn.num_enc_rings + 1;
+ adev->vcn.inst[i].irq.funcs = &vcn_v3_0_irq_funcs;
+ }
+}
+
+static const struct amd_ip_funcs vcn_v3_0_ip_funcs = {
+ .name = "vcn_v3_0",
+ .early_init = vcn_v3_0_early_init,
+ .late_init = NULL,
+ .sw_init = vcn_v3_0_sw_init,
+ .sw_fini = vcn_v3_0_sw_fini,
+ .hw_init = vcn_v3_0_hw_init,
+ .hw_fini = vcn_v3_0_hw_fini,
+ .suspend = vcn_v3_0_suspend,
+ .resume = vcn_v3_0_resume,
+ .is_idle = vcn_v3_0_is_idle,
+ .wait_for_idle = vcn_v3_0_wait_for_idle,
+ .check_soft_reset = NULL,
+ .pre_soft_reset = NULL,
+ .soft_reset = NULL,
+ .post_soft_reset = NULL,
+ .set_clockgating_state = vcn_v3_0_set_clockgating_state,
+ .set_powergating_state = vcn_v3_0_set_powergating_state,
+};
+
+const struct amdgpu_ip_block_version vcn_v3_0_ip_block =
+{
+ .type = AMD_IP_BLOCK_TYPE_VCN,
+ .major = 3,
+ .minor = 0,
+ .rev = 0,
+ .funcs = &vcn_v3_0_ip_funcs,
+};
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.h b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.h
new file mode 100644
index 000000000000..31683582d778
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.h
@@ -0,0 +1,29 @@
+/*
+ * Copyright 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef __VCN_V3_0_H__
+#define __VCN_V3_0_H__
+
+extern const struct amdgpu_ip_block_version vcn_v3_0_ip_block;
+
+#endif /* __VCN_V3_0_H__ */
--
2.25.4
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amd-gfx@lists.freedesktop.org
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^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH 083/207] drm/amdgpu: add Sienna_Cichlid VCN PG and CG support (v2)
2020-06-01 17:59 [PATCH 000/207] Add Support for Sienna Cichlid Alex Deucher
` (77 preceding siblings ...)
2020-06-01 18:00 ` [PATCH 082/207] drm/amdgpu: add VCN3.0 support for Sienna_Cichlid Alex Deucher
@ 2020-06-01 18:00 ` Alex Deucher
2020-06-01 18:00 ` [PATCH 084/207] drm/amdgpu: enable VCN3.0 PG and CG for Sienna_Cichlid Alex Deucher
` (3 subsequent siblings)
82 siblings, 0 replies; 88+ messages in thread
From: Alex Deucher @ 2020-06-01 18:00 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, James Zhu, Leo Liu
From: Leo Liu <leo.liu@amd.com>
This is for static powergating and clockgating
v2: fix registers (Alex)
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 332 ++++++++++++++++++++++++++
1 file changed, 332 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
index 2833f06fb4bb..011edbdd4e55 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
@@ -381,6 +381,309 @@ static void vcn_v3_0_mc_resume(struct amdgpu_device *adev, int inst)
WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE);
}
+static void vcn_v3_0_disable_static_power_gating(struct amdgpu_device *adev, int inst)
+{
+ uint32_t data = 0;
+ int ret;
+
+ if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
+ data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
+ | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT
+ | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
+ | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT
+ | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
+ | 2 << UVD_PGFSM_CONFIG__UVDIRL_PWR_CONFIG__SHIFT
+ | 1 << UVD_PGFSM_CONFIG__UVDLM_PWR_CONFIG__SHIFT
+ | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
+ | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
+ | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT
+ | 2 << UVD_PGFSM_CONFIG__UVDAB_PWR_CONFIG__SHIFT
+ | 2 << UVD_PGFSM_CONFIG__UVDATD_PWR_CONFIG__SHIFT
+ | 2 << UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG__SHIFT
+ | 2 << UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG__SHIFT);
+
+ WREG32_SOC15(VCN, inst, mmUVD_PGFSM_CONFIG, data);
+ SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_PGFSM_STATUS,
+ UVD_PGFSM_STATUS__UVDM_UVDU_UVDLM_PWR_ON_3_0, 0x3F3FFFFF, ret);
+ } else {
+ data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
+ | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT
+ | 1 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
+ | 1 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT
+ | 1 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
+ | 1 << UVD_PGFSM_CONFIG__UVDIRL_PWR_CONFIG__SHIFT
+ | 1 << UVD_PGFSM_CONFIG__UVDLM_PWR_CONFIG__SHIFT
+ | 1 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
+ | 1 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
+ | 1 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT
+ | 1 << UVD_PGFSM_CONFIG__UVDAB_PWR_CONFIG__SHIFT
+ | 1 << UVD_PGFSM_CONFIG__UVDATD_PWR_CONFIG__SHIFT
+ | 1 << UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG__SHIFT
+ | 1 << UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG__SHIFT);
+ WREG32_SOC15(VCN, inst, mmUVD_PGFSM_CONFIG, data);
+ SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_PGFSM_STATUS, 0, 0x3F3FFFFF, ret);
+ }
+
+ data = RREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS);
+ data &= ~0x103;
+ if (adev->pg_flags & AMD_PG_SUPPORT_VCN)
+ data |= UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON |
+ UVD_POWER_STATUS__UVD_PG_EN_MASK;
+
+ WREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS, data);
+}
+
+static void vcn_v3_0_enable_static_power_gating(struct amdgpu_device *adev, int inst)
+{
+ uint32_t data;
+ int ret;
+
+ if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
+ /* Before power off, this indicator has to be turned on */
+ data = RREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS);
+ data &= ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK;
+ data |= UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF;
+ WREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS, data);
+
+ data = (2 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
+ | 2 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT
+ | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
+ | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT
+ | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
+ | 2 << UVD_PGFSM_CONFIG__UVDIRL_PWR_CONFIG__SHIFT
+ | 2 << UVD_PGFSM_CONFIG__UVDLM_PWR_CONFIG__SHIFT
+ | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
+ | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
+ | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT
+ | 2 << UVD_PGFSM_CONFIG__UVDAB_PWR_CONFIG__SHIFT
+ | 2 << UVD_PGFSM_CONFIG__UVDATD_PWR_CONFIG__SHIFT
+ | 2 << UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG__SHIFT
+ | 2 << UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG__SHIFT);
+ WREG32_SOC15(VCN, inst, mmUVD_PGFSM_CONFIG, data);
+
+ data = (2 << UVD_PGFSM_STATUS__UVDM_PWR_STATUS__SHIFT
+ | 2 << UVD_PGFSM_STATUS__UVDU_PWR_STATUS__SHIFT
+ | 2 << UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT
+ | 2 << UVD_PGFSM_STATUS__UVDC_PWR_STATUS__SHIFT
+ | 2 << UVD_PGFSM_STATUS__UVDB_PWR_STATUS__SHIFT
+ | 2 << UVD_PGFSM_STATUS__UVDIRL_PWR_STATUS__SHIFT
+ | 2 << UVD_PGFSM_STATUS__UVDLM_PWR_STATUS__SHIFT
+ | 2 << UVD_PGFSM_STATUS__UVDTD_PWR_STATUS__SHIFT
+ | 2 << UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT
+ | 2 << UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT
+ | 2 << UVD_PGFSM_STATUS__UVDAB_PWR_STATUS__SHIFT
+ | 2 << UVD_PGFSM_STATUS__UVDATD_PWR_STATUS__SHIFT
+ | 2 << UVD_PGFSM_STATUS__UVDNA_PWR_STATUS__SHIFT
+ | 2 << UVD_PGFSM_STATUS__UVDNB_PWR_STATUS__SHIFT);
+ SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_PGFSM_STATUS, data, 0x3F3FFFFF, ret);
+ }
+}
+
+/**
+ * vcn_v3_0_disable_clock_gating - disable VCN clock gating
+ *
+ * @adev: amdgpu_device pointer
+ * @inst: instance number
+ *
+ * Disable clock gating for VCN block
+ */
+static void vcn_v3_0_disable_clock_gating(struct amdgpu_device *adev, int inst)
+{
+ uint32_t data;
+ int ret = 0;
+
+ /* VCN disable CGC */
+ data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL);
+ if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
+ data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
+ else
+ data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
+ data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
+ data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
+ WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data);
+
+ data = RREG32_SOC15(VCN, inst, mmUVD_CGC_GATE);
+ data &= ~(UVD_CGC_GATE__SYS_MASK
+ | UVD_CGC_GATE__UDEC_MASK
+ | UVD_CGC_GATE__MPEG2_MASK
+ | UVD_CGC_GATE__REGS_MASK
+ | UVD_CGC_GATE__RBC_MASK
+ | UVD_CGC_GATE__LMI_MC_MASK
+ | UVD_CGC_GATE__LMI_UMC_MASK
+ | UVD_CGC_GATE__IDCT_MASK
+ | UVD_CGC_GATE__MPRD_MASK
+ | UVD_CGC_GATE__MPC_MASK
+ | UVD_CGC_GATE__LBSI_MASK
+ | UVD_CGC_GATE__LRBBM_MASK
+ | UVD_CGC_GATE__UDEC_RE_MASK
+ | UVD_CGC_GATE__UDEC_CM_MASK
+ | UVD_CGC_GATE__UDEC_IT_MASK
+ | UVD_CGC_GATE__UDEC_DB_MASK
+ | UVD_CGC_GATE__UDEC_MP_MASK
+ | UVD_CGC_GATE__WCB_MASK
+ | UVD_CGC_GATE__VCPU_MASK
+ | UVD_CGC_GATE__MMSCH_MASK);
+
+ WREG32_SOC15(VCN, inst, mmUVD_CGC_GATE, data);
+
+ SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_CGC_GATE, 0, 0xFFFFFFFF, ret);
+
+ data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL);
+ data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK
+ | UVD_CGC_CTRL__UDEC_CM_MODE_MASK
+ | UVD_CGC_CTRL__UDEC_IT_MODE_MASK
+ | UVD_CGC_CTRL__UDEC_DB_MODE_MASK
+ | UVD_CGC_CTRL__UDEC_MP_MODE_MASK
+ | UVD_CGC_CTRL__SYS_MODE_MASK
+ | UVD_CGC_CTRL__UDEC_MODE_MASK
+ | UVD_CGC_CTRL__MPEG2_MODE_MASK
+ | UVD_CGC_CTRL__REGS_MODE_MASK
+ | UVD_CGC_CTRL__RBC_MODE_MASK
+ | UVD_CGC_CTRL__LMI_MC_MODE_MASK
+ | UVD_CGC_CTRL__LMI_UMC_MODE_MASK
+ | UVD_CGC_CTRL__IDCT_MODE_MASK
+ | UVD_CGC_CTRL__MPRD_MODE_MASK
+ | UVD_CGC_CTRL__MPC_MODE_MASK
+ | UVD_CGC_CTRL__LBSI_MODE_MASK
+ | UVD_CGC_CTRL__LRBBM_MODE_MASK
+ | UVD_CGC_CTRL__WCB_MODE_MASK
+ | UVD_CGC_CTRL__VCPU_MODE_MASK
+ | UVD_CGC_CTRL__MMSCH_MODE_MASK);
+ WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data);
+
+ data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE);
+ data |= (UVD_SUVD_CGC_GATE__SRE_MASK
+ | UVD_SUVD_CGC_GATE__SIT_MASK
+ | UVD_SUVD_CGC_GATE__SMP_MASK
+ | UVD_SUVD_CGC_GATE__SCM_MASK
+ | UVD_SUVD_CGC_GATE__SDB_MASK
+ | UVD_SUVD_CGC_GATE__SRE_H264_MASK
+ | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK
+ | UVD_SUVD_CGC_GATE__SIT_H264_MASK
+ | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK
+ | UVD_SUVD_CGC_GATE__SCM_H264_MASK
+ | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK
+ | UVD_SUVD_CGC_GATE__SDB_H264_MASK
+ | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK
+ | UVD_SUVD_CGC_GATE__SCLR_MASK
+ | UVD_SUVD_CGC_GATE__ENT_MASK
+ | UVD_SUVD_CGC_GATE__IME_MASK
+ | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK
+ | UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK
+ | UVD_SUVD_CGC_GATE__SITE_MASK
+ | UVD_SUVD_CGC_GATE__SRE_VP9_MASK
+ | UVD_SUVD_CGC_GATE__SCM_VP9_MASK
+ | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK
+ | UVD_SUVD_CGC_GATE__SDB_VP9_MASK
+ | UVD_SUVD_CGC_GATE__IME_HEVC_MASK
+ | UVD_SUVD_CGC_GATE__EFC_MASK
+ | UVD_SUVD_CGC_GATE__SAOE_MASK
+ | 0x08000000
+ | UVD_SUVD_CGC_GATE__FBC_PCLK_MASK
+ | UVD_SUVD_CGC_GATE__FBC_CCLK_MASK
+ | 0x40000000
+ | UVD_SUVD_CGC_GATE__SMPA_MASK);
+ WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE, data);
+
+ data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE2);
+ data |= (UVD_SUVD_CGC_GATE2__MPBE0_MASK
+ | UVD_SUVD_CGC_GATE2__MPBE1_MASK
+ | 0x00000004
+ | 0x00000008
+ | UVD_SUVD_CGC_GATE2__MPC1_MASK);
+ WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE2, data);
+
+ data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL);
+ data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
+ | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
+ | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
+ | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
+ | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
+ | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
+ | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
+ | UVD_SUVD_CGC_CTRL__IME_MODE_MASK
+ | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK
+ | UVD_SUVD_CGC_CTRL__EFC_MODE_MASK
+ | UVD_SUVD_CGC_CTRL__SAOE_MODE_MASK
+ | UVD_SUVD_CGC_CTRL__SMPA_MODE_MASK
+ | UVD_SUVD_CGC_CTRL__MPBE0_MODE_MASK
+ | UVD_SUVD_CGC_CTRL__MPBE1_MODE_MASK
+ | 0x00008000
+ | 0x00010000
+ | UVD_SUVD_CGC_CTRL__MPC1_MODE_MASK
+ | UVD_SUVD_CGC_CTRL__FBC_PCLK_MASK
+ | UVD_SUVD_CGC_CTRL__FBC_CCLK_MASK);
+ WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL, data);
+}
+
+/**
+ * vcn_v3_0_enable_clock_gating - enable VCN clock gating
+ *
+ * @adev: amdgpu_device pointer
+ * @inst: instance number
+ *
+ * Enable clock gating for VCN block
+ */
+static void vcn_v3_0_enable_clock_gating(struct amdgpu_device *adev, int inst)
+{
+ uint32_t data;
+
+ /* enable VCN CGC */
+ data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL);
+ if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
+ data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
+ else
+ data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
+ data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
+ data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
+ WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data);
+
+ data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL);
+ data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK
+ | UVD_CGC_CTRL__UDEC_CM_MODE_MASK
+ | UVD_CGC_CTRL__UDEC_IT_MODE_MASK
+ | UVD_CGC_CTRL__UDEC_DB_MODE_MASK
+ | UVD_CGC_CTRL__UDEC_MP_MODE_MASK
+ | UVD_CGC_CTRL__SYS_MODE_MASK
+ | UVD_CGC_CTRL__UDEC_MODE_MASK
+ | UVD_CGC_CTRL__MPEG2_MODE_MASK
+ | UVD_CGC_CTRL__REGS_MODE_MASK
+ | UVD_CGC_CTRL__RBC_MODE_MASK
+ | UVD_CGC_CTRL__LMI_MC_MODE_MASK
+ | UVD_CGC_CTRL__LMI_UMC_MODE_MASK
+ | UVD_CGC_CTRL__IDCT_MODE_MASK
+ | UVD_CGC_CTRL__MPRD_MODE_MASK
+ | UVD_CGC_CTRL__MPC_MODE_MASK
+ | UVD_CGC_CTRL__LBSI_MODE_MASK
+ | UVD_CGC_CTRL__LRBBM_MODE_MASK
+ | UVD_CGC_CTRL__WCB_MODE_MASK
+ | UVD_CGC_CTRL__VCPU_MODE_MASK
+ | UVD_CGC_CTRL__MMSCH_MODE_MASK);
+ WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data);
+
+ data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL);
+ data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
+ | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
+ | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
+ | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
+ | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
+ | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
+ | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
+ | UVD_SUVD_CGC_CTRL__IME_MODE_MASK
+ | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK
+ | UVD_SUVD_CGC_CTRL__EFC_MODE_MASK
+ | UVD_SUVD_CGC_CTRL__SAOE_MODE_MASK
+ | UVD_SUVD_CGC_CTRL__SMPA_MODE_MASK
+ | UVD_SUVD_CGC_CTRL__MPBE0_MODE_MASK
+ | UVD_SUVD_CGC_CTRL__MPBE1_MODE_MASK
+ | 0x00008000
+ | 0x00010000
+ | UVD_SUVD_CGC_CTRL__MPC1_MODE_MASK
+ | UVD_SUVD_CGC_CTRL__FBC_PCLK_MASK
+ | UVD_SUVD_CGC_CTRL__FBC_CCLK_MASK);
+ WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL, data);
+}
+
static int vcn_v3_0_start(struct amdgpu_device *adev)
{
struct amdgpu_ring *ring;
@@ -394,10 +697,16 @@ static int vcn_v3_0_start(struct amdgpu_device *adev)
if (adev->vcn.harvest_config & (1 << i))
continue;
+ /* disable VCN power gating */
+ vcn_v3_0_disable_static_power_gating(adev, i);
+
/* set VCN status busy */
tmp = RREG32_SOC15(VCN, i, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY;
WREG32_SOC15(VCN, i, mmUVD_STATUS, tmp);
+ /*SW clock gating */
+ vcn_v3_0_disable_clock_gating(adev, i);
+
/* enable VCPU clock */
WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL),
UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK);
@@ -600,6 +909,12 @@ static int vcn_v3_0_stop(struct amdgpu_device *adev)
/* clear status */
WREG32_SOC15(VCN, i, mmUVD_STATUS, 0);
+
+ /* apply HW clock gating */
+ vcn_v3_0_enable_clock_gating(adev, i);
+
+ /* enable VCN power gating */
+ vcn_v3_0_enable_static_power_gating(adev, i);
}
if (adev->pm.dpm_enabled)
@@ -853,6 +1168,23 @@ static int vcn_v3_0_wait_for_idle(void *handle)
static int vcn_v3_0_set_clockgating_state(void *handle,
enum amd_clockgating_state state)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
+ int i;
+
+ for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
+ if (adev->vcn.harvest_config & (1 << i))
+ continue;
+
+ if (enable) {
+ if (RREG32_SOC15(VCN, i, mmUVD_STATUS) == UVD_STATUS__IDLE)
+ return -EBUSY;
+ vcn_v3_0_enable_clock_gating(adev, i);
+ } else {
+ vcn_v3_0_disable_clock_gating(adev, i);
+ }
+ }
+
return 0;
}
--
2.25.4
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH 084/207] drm/amdgpu: enable VCN3.0 PG and CG for Sienna_Cichlid
2020-06-01 17:59 [PATCH 000/207] Add Support for Sienna Cichlid Alex Deucher
` (78 preceding siblings ...)
2020-06-01 18:00 ` [PATCH 083/207] drm/amdgpu: add Sienna_Cichlid VCN PG and CG support (v2) Alex Deucher
@ 2020-06-01 18:00 ` Alex Deucher
2020-06-01 18:00 ` [PATCH 085/207] drm/amdgpu: add Sienna_Cichlid VCN to the VCN family Alex Deucher
` (2 subsequent siblings)
82 siblings, 0 replies; 88+ messages in thread
From: Alex Deucher @ 2020-06-01 18:00 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, James Zhu, Leo Liu
From: Leo Liu <leo.liu@amd.com>
By setting up the flags to the ASIC
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/nv.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index 587d0b6821f8..80428ae470c1 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -710,8 +710,8 @@ static int nv_common_early_init(void *handle)
adev->external_rev_id = adev->rev_id + 0xa;
break;
case CHIP_SIENNA_CICHLID:
- adev->cg_flags = 0;
- adev->pg_flags = 0;
+ adev->cg_flags = AMD_CG_SUPPORT_VCN_MGCG;
+ adev->pg_flags = AMD_PG_SUPPORT_VCN;
adev->external_rev_id = adev->rev_id + 0x28;
break;
default:
--
2.25.4
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH 085/207] drm/amdgpu: add Sienna_Cichlid VCN to the VCN family
2020-06-01 17:59 [PATCH 000/207] Add Support for Sienna Cichlid Alex Deucher
` (79 preceding siblings ...)
2020-06-01 18:00 ` [PATCH 084/207] drm/amdgpu: enable VCN3.0 PG and CG for Sienna_Cichlid Alex Deucher
@ 2020-06-01 18:00 ` Alex Deucher
2020-06-01 18:00 ` [PATCH 086/207] drm/amdgpu: enable VCN3.0 for Sienna_Cichlid Alex Deucher
2020-06-01 18:00 ` [PATCH 087/207] drm/amdgpu: add JPEG3.0 support " Alex Deucher
82 siblings, 0 replies; 88+ messages in thread
From: Alex Deucher @ 2020-06-01 18:00 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, James Zhu, Leo Liu
From: Leo Liu <leo.liu@amd.com>
By adding Sienna_Cichlid VCN firmware
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index 2badbc0355f2..fff77b629d04 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -42,6 +42,7 @@
#define FIRMWARE_NAVI10 "amdgpu/navi10_vcn.bin"
#define FIRMWARE_NAVI14 "amdgpu/navi14_vcn.bin"
#define FIRMWARE_NAVI12 "amdgpu/navi12_vcn.bin"
+#define FIRMWARE_SIENNA_CICHLID "amdgpu/sienna_cichlid_vcn.bin"
MODULE_FIRMWARE(FIRMWARE_RAVEN);
MODULE_FIRMWARE(FIRMWARE_PICASSO);
@@ -51,6 +52,7 @@ MODULE_FIRMWARE(FIRMWARE_RENOIR);
MODULE_FIRMWARE(FIRMWARE_NAVI10);
MODULE_FIRMWARE(FIRMWARE_NAVI14);
MODULE_FIRMWARE(FIRMWARE_NAVI12);
+MODULE_FIRMWARE(FIRMWARE_SIENNA_CICHLID);
static void amdgpu_vcn_idle_work_handler(struct work_struct *work);
@@ -107,6 +109,9 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev)
(adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
adev->vcn.indirect_sram = true;
break;
+ case CHIP_SIENNA_CICHLID:
+ fw_name = FIRMWARE_SIENNA_CICHLID;
+ break;
default:
return -EINVAL;
}
--
2.25.4
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH 086/207] drm/amdgpu: enable VCN3.0 for Sienna_Cichlid
2020-06-01 17:59 [PATCH 000/207] Add Support for Sienna Cichlid Alex Deucher
` (80 preceding siblings ...)
2020-06-01 18:00 ` [PATCH 085/207] drm/amdgpu: add Sienna_Cichlid VCN to the VCN family Alex Deucher
@ 2020-06-01 18:00 ` Alex Deucher
2020-06-01 18:00 ` [PATCH 087/207] drm/amdgpu: add JPEG3.0 support " Alex Deucher
82 siblings, 0 replies; 88+ messages in thread
From: Alex Deucher @ 2020-06-01 18:00 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, James Zhu, Leo Liu
From: Leo Liu <leo.liu@amd.com>
By adding VCN HW block to Sienna_Cichlid
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/nv.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index 80428ae470c1..a7a03706025a 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -56,6 +56,7 @@
#include "sdma_v5_2.h"
#include "vcn_v2_0.h"
#include "jpeg_v2_0.h"
+#include "vcn_v3_0.h"
#include "dce_virtual.h"
#include "mes_v10_1.h"
#include "mxgpu_nv.h"
@@ -497,6 +498,7 @@ int nv_set_ip_blocks(struct amdgpu_device *adev)
amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block);
+ amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
if (adev->enable_mes)
amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block);
break;
--
2.25.4
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^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH 087/207] drm/amdgpu: add JPEG3.0 support for Sienna_Cichlid
2020-06-01 17:59 [PATCH 000/207] Add Support for Sienna Cichlid Alex Deucher
` (81 preceding siblings ...)
2020-06-01 18:00 ` [PATCH 086/207] drm/amdgpu: enable VCN3.0 for Sienna_Cichlid Alex Deucher
@ 2020-06-01 18:00 ` Alex Deucher
82 siblings, 0 replies; 88+ messages in thread
From: Alex Deucher @ 2020-06-01 18:00 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, James Zhu, Leo Liu
From: Leo Liu <leo.liu@amd.com>
With basic IP block functions and ring functions
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/Makefile | 3 +-
drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c | 484 +++++++++++++++++++++++++
drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.h | 29 ++
3 files changed, 515 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c
create mode 100644 drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.h
diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile
index 3cab3fea59d4..179070b12cde 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -159,7 +159,8 @@ amdgpu-y += \
amdgpu_jpeg.o \
jpeg_v1_0.o \
jpeg_v2_0.o \
- jpeg_v2_5.o
+ jpeg_v2_5.o \
+ jpeg_v3_0.o
# add ATHUB block
amdgpu-y += \
diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c
new file mode 100644
index 000000000000..af70aea0205c
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c
@@ -0,0 +1,484 @@
+/*
+ * Copyright 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#include "amdgpu.h"
+#include "amdgpu_jpeg.h"
+#include "amdgpu_pm.h"
+#include "soc15.h"
+#include "soc15d.h"
+#include "jpeg_v2_0.h"
+
+#include "vcn/vcn_3_0_0_offset.h"
+#include "vcn/vcn_3_0_0_sh_mask.h"
+#include "ivsrcid/vcn/irqsrcs_vcn_2_0.h"
+
+#define mmUVD_JPEG_PITCH_INTERNAL_OFFSET 0x401f
+
+static void jpeg_v3_0_set_dec_ring_funcs(struct amdgpu_device *adev);
+static void jpeg_v3_0_set_irq_funcs(struct amdgpu_device *adev);
+static int jpeg_v3_0_set_powergating_state(void *handle,
+ enum amd_powergating_state state);
+
+/**
+ * jpeg_v3_0_early_init - set function pointers
+ *
+ * @handle: amdgpu_device pointer
+ *
+ * Set ring and irq function pointers
+ */
+static int jpeg_v3_0_early_init(void *handle)
+{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ if (adev->asic_type == CHIP_SIENNA_CICHLID) {
+ u32 harvest = RREG32_SOC15(JPEG, 0, mmCC_UVD_HARVESTING);
+
+ if (harvest & CC_UVD_HARVESTING__UVD_DISABLE_MASK)
+ return -ENOENT;
+ }
+ adev->jpeg.num_jpeg_inst = 1;
+
+ jpeg_v3_0_set_dec_ring_funcs(adev);
+ jpeg_v3_0_set_irq_funcs(adev);
+
+ return 0;
+}
+
+/**
+ * jpeg_v3_0_sw_init - sw init for JPEG block
+ *
+ * @handle: amdgpu_device pointer
+ *
+ * Load firmware and sw initialization
+ */
+static int jpeg_v3_0_sw_init(void *handle)
+{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_ring *ring;
+ int r;
+
+ /* JPEG TRAP */
+ r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN,
+ VCN_2_0__SRCID__JPEG_DECODE, &adev->jpeg.inst->irq);
+ if (r)
+ return r;
+
+ r = amdgpu_jpeg_sw_init(adev);
+ if (r)
+ return r;
+
+ r = amdgpu_jpeg_resume(adev);
+ if (r)
+ return r;
+
+ ring = &adev->jpeg.inst->ring_dec;
+ ring->use_doorbell = true;
+ ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 1;
+ sprintf(ring->name, "jpeg_dec");
+ r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq, 0,
+ AMDGPU_RING_PRIO_DEFAULT);
+ if (r)
+ return r;
+
+ adev->jpeg.internal.jpeg_pitch = mmUVD_JPEG_PITCH_INTERNAL_OFFSET;
+ adev->jpeg.inst->external.jpeg_pitch = SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_PITCH);
+
+ return 0;
+}
+
+/**
+ * jpeg_v3_0_sw_fini - sw fini for JPEG block
+ *
+ * @handle: amdgpu_device pointer
+ *
+ * JPEG suspend and free up sw allocation
+ */
+static int jpeg_v3_0_sw_fini(void *handle)
+{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ int r;
+
+ r = amdgpu_jpeg_suspend(adev);
+ if (r)
+ return r;
+
+ r = amdgpu_jpeg_sw_fini(adev);
+
+ return r;
+}
+
+/**
+ * jpeg_v3_0_hw_init - start and test JPEG block
+ *
+ * @handle: amdgpu_device pointer
+ *
+ */
+static int jpeg_v3_0_hw_init(void *handle)
+{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_ring *ring = &adev->jpeg.inst->ring_dec;
+ int r;
+
+ adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,
+ (adev->doorbell_index.vcn.vcn_ring0_1 << 1), 0);
+
+ r = amdgpu_ring_test_helper(ring);
+ if (r)
+ return r;
+
+ DRM_INFO("JPEG decode initialized successfully.\n");
+
+ return 0;
+}
+
+/**
+ * jpeg_v3_0_hw_fini - stop the hardware block
+ *
+ * @handle: amdgpu_device pointer
+ *
+ * Stop the JPEG block, mark ring as not ready any more
+ */
+static int jpeg_v3_0_hw_fini(void *handle)
+{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_ring *ring;
+
+ ring = &adev->jpeg.inst->ring_dec;
+ if (adev->jpeg.cur_state != AMD_PG_STATE_GATE &&
+ RREG32_SOC15(JPEG, 0, mmUVD_JRBC_STATUS))
+ jpeg_v3_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
+
+ ring->sched.ready = false;
+
+ return 0;
+}
+
+/**
+ * jpeg_v3_0_suspend - suspend JPEG block
+ *
+ * @handle: amdgpu_device pointer
+ *
+ * HW fini and suspend JPEG block
+ */
+static int jpeg_v3_0_suspend(void *handle)
+{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ int r;
+
+ r = jpeg_v3_0_hw_fini(adev);
+ if (r)
+ return r;
+
+ r = amdgpu_jpeg_suspend(adev);
+
+ return r;
+}
+
+/**
+ * jpeg_v3_0_resume - resume JPEG block
+ *
+ * @handle: amdgpu_device pointer
+ *
+ * Resume firmware and hw init JPEG block
+ */
+static int jpeg_v3_0_resume(void *handle)
+{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ int r;
+
+ r = amdgpu_jpeg_resume(adev);
+ if (r)
+ return r;
+
+ r = jpeg_v3_0_hw_init(adev);
+
+ return r;
+}
+
+/**
+ * jpeg_v3_0_start - start JPEG block
+ *
+ * @adev: amdgpu_device pointer
+ *
+ * Setup and start the JPEG block
+ */
+static int jpeg_v3_0_start(struct amdgpu_device *adev)
+{
+ struct amdgpu_ring *ring = &adev->jpeg.inst->ring_dec;
+
+ if (adev->pm.dpm_enabled)
+ amdgpu_dpm_enable_jpeg(adev, true);
+
+ /* MJPEG global tiling registers */
+ WREG32_SOC15(JPEG, 0, mmJPEG_DEC_GFX10_ADDR_CONFIG,
+ adev->gfx.config.gb_addr_config);
+ WREG32_SOC15(JPEG, 0, mmJPEG_ENC_GFX10_ADDR_CONFIG,
+ adev->gfx.config.gb_addr_config);
+
+ /* enable JMI channel */
+ WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JMI_CNTL), 0,
+ ~UVD_JMI_CNTL__SOFT_RESET_MASK);
+
+ /* enable System Interrupt for JRBC */
+ WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmJPEG_SYS_INT_EN),
+ JPEG_SYS_INT_EN__DJRBC_MASK,
+ ~JPEG_SYS_INT_EN__DJRBC_MASK);
+
+ WREG32_SOC15(JPEG, 0, mmUVD_LMI_JRBC_RB_VMID, 0);
+ WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_CNTL, (0x00000001L | 0x00000002L));
+ WREG32_SOC15(JPEG, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW,
+ lower_32_bits(ring->gpu_addr));
+ WREG32_SOC15(JPEG, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH,
+ upper_32_bits(ring->gpu_addr));
+ WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_RPTR, 0);
+ WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR, 0);
+ WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_CNTL, 0x00000002L);
+ WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_SIZE, ring->ring_size / 4);
+ ring->wptr = RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR);
+
+ return 0;
+}
+
+/**
+ * jpeg_v3_0_stop - stop JPEG block
+ *
+ * @adev: amdgpu_device pointer
+ *
+ * stop the JPEG block
+ */
+static int jpeg_v3_0_stop(struct amdgpu_device *adev)
+{
+ /* reset JMI */
+ WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JMI_CNTL),
+ UVD_JMI_CNTL__SOFT_RESET_MASK,
+ ~UVD_JMI_CNTL__SOFT_RESET_MASK);
+
+ if (adev->pm.dpm_enabled)
+ amdgpu_dpm_enable_jpeg(adev, false);
+
+ return 0;
+}
+
+/**
+ * jpeg_v3_0_dec_ring_get_rptr - get read pointer
+ *
+ * @ring: amdgpu_ring pointer
+ *
+ * Returns the current hardware read pointer
+ */
+static uint64_t jpeg_v3_0_dec_ring_get_rptr(struct amdgpu_ring *ring)
+{
+ struct amdgpu_device *adev = ring->adev;
+
+ return RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_RPTR);
+}
+
+/**
+ * jpeg_v3_0_dec_ring_get_wptr - get write pointer
+ *
+ * @ring: amdgpu_ring pointer
+ *
+ * Returns the current hardware write pointer
+ */
+static uint64_t jpeg_v3_0_dec_ring_get_wptr(struct amdgpu_ring *ring)
+{
+ struct amdgpu_device *adev = ring->adev;
+
+ if (ring->use_doorbell)
+ return adev->wb.wb[ring->wptr_offs];
+ else
+ return RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR);
+}
+
+/**
+ * jpeg_v3_0_dec_ring_set_wptr - set write pointer
+ *
+ * @ring: amdgpu_ring pointer
+ *
+ * Commits the write pointer to the hardware
+ */
+static void jpeg_v3_0_dec_ring_set_wptr(struct amdgpu_ring *ring)
+{
+ struct amdgpu_device *adev = ring->adev;
+
+ if (ring->use_doorbell) {
+ adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
+ WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
+ } else {
+ WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr));
+ }
+}
+
+static bool jpeg_v3_0_is_idle(void *handle)
+{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ int ret = 1;
+
+ ret &= (((RREG32_SOC15(JPEG, 0, mmUVD_JRBC_STATUS) &
+ UVD_JRBC_STATUS__RB_JOB_DONE_MASK) ==
+ UVD_JRBC_STATUS__RB_JOB_DONE_MASK));
+
+ return ret;
+}
+
+static int jpeg_v3_0_wait_for_idle(void *handle)
+{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ int ret = 0;
+
+ SOC15_WAIT_ON_RREG(JPEG, 0, mmUVD_JRBC_STATUS,
+ UVD_JRBC_STATUS__RB_JOB_DONE_MASK,
+ UVD_JRBC_STATUS__RB_JOB_DONE_MASK, ret);
+ if (ret)
+ return ret;
+
+ return ret;
+}
+
+static int jpeg_v3_0_set_clockgating_state(void *handle,
+ enum amd_clockgating_state state)
+{
+ return 0;
+}
+
+static int jpeg_v3_0_set_powergating_state(void *handle,
+ enum amd_powergating_state state)
+{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ int ret;
+
+ if(state == adev->jpeg.cur_state)
+ return 0;
+
+ if (state == AMD_PG_STATE_GATE)
+ ret = jpeg_v3_0_stop(adev);
+ else
+ ret = jpeg_v3_0_start(adev);
+
+ if(!ret)
+ adev->jpeg.cur_state = state;
+
+ return ret;
+}
+
+static int jpeg_v3_0_set_interrupt_state(struct amdgpu_device *adev,
+ struct amdgpu_irq_src *source,
+ unsigned type,
+ enum amdgpu_interrupt_state state)
+{
+ return 0;
+}
+
+static int jpeg_v3_0_process_interrupt(struct amdgpu_device *adev,
+ struct amdgpu_irq_src *source,
+ struct amdgpu_iv_entry *entry)
+{
+ DRM_DEBUG("IH: JPEG TRAP\n");
+
+ switch (entry->src_id) {
+ case VCN_2_0__SRCID__JPEG_DECODE:
+ amdgpu_fence_process(&adev->jpeg.inst->ring_dec);
+ break;
+ default:
+ DRM_ERROR("Unhandled interrupt: %d %d\n",
+ entry->src_id, entry->src_data[0]);
+ break;
+ }
+
+ return 0;
+}
+
+static const struct amd_ip_funcs jpeg_v3_0_ip_funcs = {
+ .name = "jpeg_v3_0",
+ .early_init = jpeg_v3_0_early_init,
+ .late_init = NULL,
+ .sw_init = jpeg_v3_0_sw_init,
+ .sw_fini = jpeg_v3_0_sw_fini,
+ .hw_init = jpeg_v3_0_hw_init,
+ .hw_fini = jpeg_v3_0_hw_fini,
+ .suspend = jpeg_v3_0_suspend,
+ .resume = jpeg_v3_0_resume,
+ .is_idle = jpeg_v3_0_is_idle,
+ .wait_for_idle = jpeg_v3_0_wait_for_idle,
+ .check_soft_reset = NULL,
+ .pre_soft_reset = NULL,
+ .soft_reset = NULL,
+ .post_soft_reset = NULL,
+ .set_clockgating_state = jpeg_v3_0_set_clockgating_state,
+ .set_powergating_state = jpeg_v3_0_set_powergating_state,
+};
+
+static const struct amdgpu_ring_funcs jpeg_v3_0_dec_ring_vm_funcs = {
+ .type = AMDGPU_RING_TYPE_VCN_JPEG,
+ .align_mask = 0xf,
+ .vmhub = AMDGPU_MMHUB_0,
+ .get_rptr = jpeg_v3_0_dec_ring_get_rptr,
+ .get_wptr = jpeg_v3_0_dec_ring_get_wptr,
+ .set_wptr = jpeg_v3_0_dec_ring_set_wptr,
+ .emit_frame_size =
+ SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
+ SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
+ 8 + /* jpeg_v3_0_dec_ring_emit_vm_flush */
+ 18 + 18 + /* jpeg_v3_0_dec_ring_emit_fence x2 vm fence */
+ 8 + 16,
+ .emit_ib_size = 22, /* jpeg_v3_0_dec_ring_emit_ib */
+ .emit_ib = jpeg_v2_0_dec_ring_emit_ib,
+ .emit_fence = jpeg_v2_0_dec_ring_emit_fence,
+ .emit_vm_flush = jpeg_v2_0_dec_ring_emit_vm_flush,
+ .test_ring = amdgpu_jpeg_dec_ring_test_ring,
+ .test_ib = amdgpu_jpeg_dec_ring_test_ib,
+ .insert_nop = jpeg_v2_0_dec_ring_nop,
+ .insert_start = jpeg_v2_0_dec_ring_insert_start,
+ .insert_end = jpeg_v2_0_dec_ring_insert_end,
+ .pad_ib = amdgpu_ring_generic_pad_ib,
+ .begin_use = amdgpu_jpeg_ring_begin_use,
+ .end_use = amdgpu_jpeg_ring_end_use,
+ .emit_wreg = jpeg_v2_0_dec_ring_emit_wreg,
+ .emit_reg_wait = jpeg_v2_0_dec_ring_emit_reg_wait,
+ .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
+};
+
+static void jpeg_v3_0_set_dec_ring_funcs(struct amdgpu_device *adev)
+{
+ adev->jpeg.inst->ring_dec.funcs = &jpeg_v3_0_dec_ring_vm_funcs;
+ DRM_INFO("JPEG decode is enabled in VM mode\n");
+}
+
+static const struct amdgpu_irq_src_funcs jpeg_v3_0_irq_funcs = {
+ .set = jpeg_v3_0_set_interrupt_state,
+ .process = jpeg_v3_0_process_interrupt,
+};
+
+static void jpeg_v3_0_set_irq_funcs(struct amdgpu_device *adev)
+{
+ adev->jpeg.inst->irq.num_types = 1;
+ adev->jpeg.inst->irq.funcs = &jpeg_v3_0_irq_funcs;
+}
+
+const struct amdgpu_ip_block_version jpeg_v3_0_ip_block =
+{
+ .type = AMD_IP_BLOCK_TYPE_JPEG,
+ .major = 3,
+ .minor = 0,
+ .rev = 0,
+ .funcs = &jpeg_v3_0_ip_funcs,
+};
diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.h b/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.h
new file mode 100644
index 000000000000..ce775a0c742f
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.h
@@ -0,0 +1,29 @@
+/*
+ * Copyright 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef __JPEG_V3_0_H__
+#define __JPEG_V3_0_H__
+
+extern const struct amdgpu_ip_block_version jpeg_v3_0_ip_block;
+
+#endif /* __JPEG_V3_0_H__ */
--
2.25.4
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 88+ messages in thread
* Re: [PATCH 077/207] drm/amdgpu: no need to set up GPU scheduler for mes ring
2020-06-01 18:00 ` [PATCH 077/207] drm/amdgpu: no need to set up GPU scheduler for mes ring Alex Deucher
@ 2020-06-02 9:30 ` Christian König
2020-06-02 18:51 ` Alex Deucher
0 siblings, 1 reply; 88+ messages in thread
From: Christian König @ 2020-06-02 9:30 UTC (permalink / raw)
To: Alex Deucher, amd-gfx; +Cc: Alex Deucher, Jack Xiao, Hawking Zhang
Am 01.06.20 um 20:00 schrieb Alex Deucher:
> From: Jack Xiao <Jack.Xiao@amd.com>
>
> As mes ring directly submits to hardwared,
> it's no need to set up GPU scheduler for mes ring.
>
> Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
> Acked-by: Alex Deucher <alexander.deucher@amd.com>
> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
> Reviewed-by: Christian König <christian.koenig@amd.com>
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
> index 3414e119f0cb..8712a2e1b869 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
> @@ -469,8 +469,9 @@ int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring,
> if (!ring->fence_drv.fences)
> return -ENOMEM;
>
> - /* No need to setup the GPU scheduler for KIQ ring */
> - if (ring->funcs->type != AMDGPU_RING_TYPE_KIQ) {
> + /* No need to setup the GPU scheduler for KIQ and MES ring */
> + if (ring->funcs->type != AMDGPU_RING_TYPE_KIQ ||
> + ring->funcs->type != AMDGPU_RING_TYPE_MES) {
BTW: Making this a flag in the ring->funcs struct would probably be
cleaner than checking the two types here.
But not a must have right now.
Christian.
> switch (ring->funcs->type) {
> case AMDGPU_RING_TYPE_GFX:
> timeout = adev->gfx_timeout;
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^ permalink raw reply [flat|nested] 88+ messages in thread
* Re: [PATCH 061/207] drm/amdgpu/mes10.1: implement the ring functions of mes specific
2020-06-01 18:00 ` [PATCH 061/207] drm/amdgpu/mes10.1: implement the ring functions of mes specific Alex Deucher
@ 2020-06-02 10:00 ` Christian König
2020-06-02 18:59 ` Alex Deucher
0 siblings, 1 reply; 88+ messages in thread
From: Christian König @ 2020-06-02 10:00 UTC (permalink / raw)
To: Alex Deucher, amd-gfx; +Cc: Alex Deucher, Jack Xiao, Hawking Zhang
Am 01.06.20 um 20:00 schrieb Alex Deucher:
> From: Jack Xiao <Jack.Xiao@amd.com>
>
> Implement mes ring functions and set up them.
>
> Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
> Acked-by: Alex Deucher <alexander.deucher@amd.com>
> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/mes_v10_1.c | 43 ++++++++++++++++++++++++++
> 1 file changed, 43 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c b/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
> index 4f7e345673ca..80f6812d8ecf 100644
> --- a/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
> +++ b/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
> @@ -33,6 +33,47 @@ MODULE_FIRMWARE("amdgpu/navi10_mes.bin");
>
> #define MES_EOP_SIZE 2048
>
> +static void mes_v10_1_ring_set_wptr(struct amdgpu_ring *ring)
> +{
> + struct amdgpu_device *adev = ring->adev;
> +
> + if (ring->use_doorbell) {
> + atomic64_set((atomic64_t*)&adev->wb.wb[ring->wptr_offs],
> + ring->wptr);
This atomic64_t type case still looks fishy to me. IIRC we agreed to not
use them, don't we?
> + WDOORBELL64(ring->doorbell_index, ring->wptr);
> + } else {
> + BUG();
Do we really need the BUG() here and below?
Christian.
> + }
> +}
> +
> +static u64 mes_v10_1_ring_get_rptr(struct amdgpu_ring *ring)
> +{
> + return ring->adev->wb.wb[ring->rptr_offs];
> +}
> +
> +static u64 mes_v10_1_ring_get_wptr(struct amdgpu_ring *ring)
> +{
> + u64 wptr;
> +
> + if (ring->use_doorbell)
> + wptr = atomic64_read((atomic64_t *)
> + &ring->adev->wb.wb[ring->wptr_offs]);
> + else
> + BUG();
> + return wptr;
> +}
> +
> +static const struct amdgpu_ring_funcs mes_v10_1_ring_funcs = {
> + .type = AMDGPU_RING_TYPE_MES,
> + .align_mask = 1,
> + .nop = 0,
> + .support_64bit_ptrs = true,
> + .get_rptr = mes_v10_1_ring_get_rptr,
> + .get_wptr = mes_v10_1_ring_get_wptr,
> + .set_wptr = mes_v10_1_ring_set_wptr,
> + .insert_nop = amdgpu_ring_insert_nop,
> +};
> +
> static int mes_v10_1_add_hw_queue(struct amdgpu_mes *mes,
> struct mes_add_queue_input *input)
> {
> @@ -315,6 +356,8 @@ static int mes_v10_1_ring_init(struct amdgpu_device *adev)
>
> ring = &adev->mes.ring;
>
> + ring->funcs = &mes_v10_1_ring_funcs;
> +
> ring->me = 3;
> ring->pipe = 0;
> ring->queue = 0;
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^ permalink raw reply [flat|nested] 88+ messages in thread
* Re: [PATCH 077/207] drm/amdgpu: no need to set up GPU scheduler for mes ring
2020-06-02 9:30 ` Christian König
@ 2020-06-02 18:51 ` Alex Deucher
0 siblings, 0 replies; 88+ messages in thread
From: Alex Deucher @ 2020-06-02 18:51 UTC (permalink / raw)
To: Christian König; +Cc: Alex Deucher, Jack Xiao, amd-gfx list, Hawking Zhang
On Tue, Jun 2, 2020 at 5:30 AM Christian König <christian.koenig@amd.com> wrote:
>
> Am 01.06.20 um 20:00 schrieb Alex Deucher:
> > From: Jack Xiao <Jack.Xiao@amd.com>
> >
> > As mes ring directly submits to hardwared,
> > it's no need to set up GPU scheduler for mes ring.
> >
> > Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
> > Acked-by: Alex Deucher <alexander.deucher@amd.com>
> > Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
> > Reviewed-by: Christian König <christian.koenig@amd.com>
> > Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> > ---
> > drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 5 +++--
> > 1 file changed, 3 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
> > index 3414e119f0cb..8712a2e1b869 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
> > @@ -469,8 +469,9 @@ int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring,
> > if (!ring->fence_drv.fences)
> > return -ENOMEM;
> >
> > - /* No need to setup the GPU scheduler for KIQ ring */
> > - if (ring->funcs->type != AMDGPU_RING_TYPE_KIQ) {
> > + /* No need to setup the GPU scheduler for KIQ and MES ring */
> > + if (ring->funcs->type != AMDGPU_RING_TYPE_KIQ ||
> > + ring->funcs->type != AMDGPU_RING_TYPE_MES) {
>
> BTW: Making this a flag in the ring->funcs struct would probably be
> cleaner than checking the two types here.
>
> But not a must have right now.
Already added a flag for this, just missed this case.
Alex
>
> Christian.
>
> > switch (ring->funcs->type) {
> > case AMDGPU_RING_TYPE_GFX:
> > timeout = adev->gfx_timeout;
>
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 88+ messages in thread
* Re: [PATCH 061/207] drm/amdgpu/mes10.1: implement the ring functions of mes specific
2020-06-02 10:00 ` Christian König
@ 2020-06-02 18:59 ` Alex Deucher
0 siblings, 0 replies; 88+ messages in thread
From: Alex Deucher @ 2020-06-02 18:59 UTC (permalink / raw)
To: Christian Koenig; +Cc: Alex Deucher, Jack Xiao, amd-gfx list, Hawking Zhang
On Tue, Jun 2, 2020 at 6:00 AM Christian König
<ckoenig.leichtzumerken@gmail.com> wrote:
>
> Am 01.06.20 um 20:00 schrieb Alex Deucher:
> > From: Jack Xiao <Jack.Xiao@amd.com>
> >
> > Implement mes ring functions and set up them.
> >
> > Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
> > Acked-by: Alex Deucher <alexander.deucher@amd.com>
> > Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
> > Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> > ---
> > drivers/gpu/drm/amd/amdgpu/mes_v10_1.c | 43 ++++++++++++++++++++++++++
> > 1 file changed, 43 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c b/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
> > index 4f7e345673ca..80f6812d8ecf 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
> > @@ -33,6 +33,47 @@ MODULE_FIRMWARE("amdgpu/navi10_mes.bin");
> >
> > #define MES_EOP_SIZE 2048
> >
> > +static void mes_v10_1_ring_set_wptr(struct amdgpu_ring *ring)
> > +{
> > + struct amdgpu_device *adev = ring->adev;
> > +
> > + if (ring->use_doorbell) {
> > + atomic64_set((atomic64_t*)&adev->wb.wb[ring->wptr_offs],
> > + ring->wptr);
>
> This atomic64_t type case still looks fishy to me. IIRC we agreed to not
> use them, don't we?
We use them for all the other ring code. If we change it, we should
probably change it everywhere. I don't think we ever agreed on a
replacement.
>
> > + WDOORBELL64(ring->doorbell_index, ring->wptr);
> > + } else {
> > + BUG();
>
> Do we really need the BUG() here and below?
>
We shouldn't ever actually hit these cases since the rings don't work
without doorbells. Maybe it would be better to add a WARN_ON() if
someone tries to set ring->use_doorbell to false for MES.
Alex
> Christian.
>
> > + }
> > +}
> > +
> > +static u64 mes_v10_1_ring_get_rptr(struct amdgpu_ring *ring)
> > +{
> > + return ring->adev->wb.wb[ring->rptr_offs];
> > +}
> > +
> > +static u64 mes_v10_1_ring_get_wptr(struct amdgpu_ring *ring)
> > +{
> > + u64 wptr;
> > +
> > + if (ring->use_doorbell)
> > + wptr = atomic64_read((atomic64_t *)
> > + &ring->adev->wb.wb[ring->wptr_offs]);
> > + else
> > + BUG();
> > + return wptr;
> > +}
> > +
> > +static const struct amdgpu_ring_funcs mes_v10_1_ring_funcs = {
> > + .type = AMDGPU_RING_TYPE_MES,
> > + .align_mask = 1,
> > + .nop = 0,
> > + .support_64bit_ptrs = true,
> > + .get_rptr = mes_v10_1_ring_get_rptr,
> > + .get_wptr = mes_v10_1_ring_get_wptr,
> > + .set_wptr = mes_v10_1_ring_set_wptr,
> > + .insert_nop = amdgpu_ring_insert_nop,
> > +};
> > +
> > static int mes_v10_1_add_hw_queue(struct amdgpu_mes *mes,
> > struct mes_add_queue_input *input)
> > {
> > @@ -315,6 +356,8 @@ static int mes_v10_1_ring_init(struct amdgpu_device *adev)
> >
> > ring = &adev->mes.ring;
> >
> > + ring->funcs = &mes_v10_1_ring_funcs;
> > +
> > ring->me = 3;
> > ring->pipe = 0;
> > ring->queue = 0;
>
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^ permalink raw reply [flat|nested] 88+ messages in thread
end of thread, other threads:[~2020-06-02 18:59 UTC | newest]
Thread overview: 88+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2020-06-01 17:59 [PATCH 000/207] Add Support for Sienna Cichlid Alex Deucher
2020-06-01 17:59 ` [PATCH 005/207] drm/amdgpu: add sienna_cichlid asic type Alex Deucher
2020-06-01 17:59 ` [PATCH 006/207] drm/amdgpu: add sienna_cichlid gpu info firmware v2 Alex Deucher
2020-06-01 17:59 ` [PATCH 007/207] drm/amdgpu: set fw load type for sienna_cichlid Alex Deucher
2020-06-01 17:59 ` [PATCH 008/207] drm/amdgpu: set asic family and ip blocks " Alex Deucher
2020-06-01 17:59 ` [PATCH 009/207] drm/amdgpu/gfx10: add support for sienna_cichlid firmware Alex Deucher
2020-06-01 17:59 ` [PATCH 010/207] drm/amdgpu/gmc10: add sienna_cichlid support Alex Deucher
2020-06-01 17:59 ` [PATCH 011/207] drm/amdgpu/gfx10: add clockgating support for sienna_cichlid Alex Deucher
2020-06-01 17:59 ` [PATCH 012/207] drm/amdgpu/soc15: add " Alex Deucher
2020-06-01 17:59 ` [PATCH 013/207] drm/amdgpu: initialize IP offset for sienna_cichlid (v2) Alex Deucher
2020-06-01 17:59 ` [PATCH 014/207] drm/amdgpu/soc15: add common ip block for sienna_cichlid Alex Deucher
2020-06-01 17:59 ` [PATCH 015/207] drm/amdgpu: add support on mmhub " Alex Deucher
2020-06-01 17:59 ` [PATCH 016/207] drm/amdgpu: add support gfxhub for sienna_cichlid (v3) Alex Deucher
2020-06-01 17:59 ` [PATCH 017/207] drm/amdgpu: add gmc ip block for sienna_cichlid Alex Deucher
2020-06-01 17:59 ` [PATCH 018/207] drm/amdgpu: add ih " Alex Deucher
2020-06-01 17:59 ` [PATCH 019/207] drm/amdgpu: add gfx ip block for sienna_cichlid (v3) Alex Deucher
2020-06-01 17:59 ` [PATCH 020/207] drm/amdgpu: add sdma2 and sdma3 irqsrc header files for sienna_cichlid (v2) Alex Deucher
2020-06-01 17:59 ` [PATCH 021/207] drm/amdgpu: add sdma ip block for sienna_cichlid (v5) Alex Deucher
2020-06-01 17:59 ` [PATCH 022/207] drm/amdgpu: correct SDMA3 IH clinet id for sienna_cichlid Alex Deucher
2020-06-01 17:59 ` [PATCH 023/207] drm/amdgpu/gfx10: change register configure " Alex Deucher
2020-06-01 17:59 ` [PATCH 024/207] drm/amdgpu: add virtual display support " Alex Deucher
2020-06-01 17:59 ` [PATCH 025/207] drm/amdgpu/powerplay: add initial swSMU support for sienna_cichlid (v2) Alex Deucher
2020-06-01 17:59 ` [PATCH 026/207] drm/amd/powerplay: add support to set performance level for sienna_cichlid Alex Deucher
2020-06-01 17:59 ` [PATCH 027/207] drm/amd/powerplay: set SOCCLK DPM " Alex Deucher
2020-06-01 17:59 ` [PATCH 028/207] drm/amd/powerplay: set FCLK " Alex Deucher
2020-06-01 17:59 ` [PATCH 029/207] drm/amd/powerplay: enable Ultra Low Voltage " Alex Deucher
2020-06-01 17:59 ` [PATCH 030/207] drm/amd/powerplay: enable Graphics Clock Deep Sleep " Alex Deucher
2020-06-01 17:59 ` [PATCH 031/207] drm/amd/powerplay: enable SOC " Alex Deucher
2020-06-01 17:59 ` [PATCH 032/207] drm/amdgpu/powerplay: set Thermal control " Alex Deucher
2020-06-01 17:59 ` [PATCH 033/207] drm/amdgpu/powerplay: set UCLK DPM " Alex Deucher
2020-06-01 17:59 ` [PATCH 034/207] drm/amd/powerplay: make gfx ds can be configure " Alex Deucher
2020-06-01 17:59 ` [PATCH 035/207] drm/amd/powerplay: Enable SOCCLK ULV " Alex Deucher
2020-06-01 17:59 ` [PATCH 036/207] drm/amd/powerplay: enable DCEFCLK DPM and DS " Alex Deucher
2020-06-01 17:59 ` [PATCH 037/207] drm/amd/powerplay: support pcie value set and update " Alex Deucher
2020-06-01 17:59 ` [PATCH 038/207] drm/amd/powerplay: support to print pcie levels " Alex Deucher
2020-06-01 17:59 ` [PATCH 039/207] drm/amd/powerplay: enable LCLK DPM " Alex Deucher
2020-06-01 17:59 ` [PATCH 040/207] drm/amd/powerplay: enable GFX SS " Alex Deucher
2020-06-01 17:59 ` [PATCH 041/207] drm/amd/powerplay: enable Fan control " Alex Deucher
2020-06-01 17:59 ` [PATCH 042/207] drm/amd/powerplay: support to get power index " Alex Deucher
2020-06-01 17:59 ` [PATCH 043/207] drm/amd/powerplay: enable PPT and TDC " Alex Deucher
2020-06-01 17:59 ` [PATCH 044/207] drm/amdgpu/powerplay: add smu block " Alex Deucher
2020-06-01 17:59 ` [PATCH 045/207] drm/amdgpu: skip ASD fw load " Alex Deucher
2020-06-01 17:59 ` [PATCH 046/207] drm/amdgpu/psp: add psp support " Alex Deucher
2020-06-01 17:59 ` [PATCH 047/207] drm/amdgpu: skip for reroute ih for sienna_cichlid psp ring init currently Alex Deucher
2020-06-01 18:00 ` [PATCH 048/207] drm/amdgpu: enable psp ip block for sienna_cichlid Alex Deucher
2020-06-01 18:00 ` [PATCH 049/207] drm/amdgpu: update SDMA 5.2 microcode init Alex Deucher
2020-06-01 18:00 ` [PATCH 050/207] drm/amdgpu: Use variable instead of constant for sdma doorbell range Alex Deucher
2020-06-01 18:00 ` [PATCH 051/207] drm/amdgpu: add support for athub v2.1 Alex Deucher
2020-06-01 18:00 ` [PATCH 052/207] drm/amdgpu: add gmc cg support for sienna_cichlid Alex Deucher
2020-06-01 18:00 ` [PATCH 053/207] drm/amdgpu: add psp block load condition " Alex Deucher
2020-06-01 18:00 ` [PATCH 054/207] drm/amdgpu: add 2rd VCN instance doorbell support Alex Deucher
2020-06-01 18:00 ` [PATCH 055/207] drm/amdgpu: assign the doorbell index to mes ring Alex Deucher
2020-06-01 18:00 ` [PATCH 056/207] drm/amdgpu: add the ring type definition of MES Alex Deucher
2020-06-01 18:00 ` [PATCH 057/207] drm/amdgpu: avoid dereferencing a NULL pointer Alex Deucher
2020-06-01 18:00 ` [PATCH 058/207] drm/amdgpu/mes: update some mes definitions Alex Deucher
2020-06-01 18:00 ` [PATCH 059/207] drm/amdgpu/mes10.1: allocate the eop buffer Alex Deucher
2020-06-01 18:00 ` [PATCH 060/207] drm/amdgpu/mes10.1: initialize the software part of mes ring Alex Deucher
2020-06-01 18:00 ` [PATCH 061/207] drm/amdgpu/mes10.1: implement the ring functions of mes specific Alex Deucher
2020-06-02 10:00 ` Christian König
2020-06-02 18:59 ` Alex Deucher
2020-06-01 18:00 ` [PATCH 062/207] drm/amdgpu/mes10.1: allocate mqd buffer Alex Deucher
2020-06-01 18:00 ` [PATCH 063/207] drm/amdgpu/mes10.1: initialize the mqd Alex Deucher
2020-06-01 18:00 ` [PATCH 064/207] drm/amdgpu/mes10.1: install mes queue by register programming Alex Deucher
2020-06-01 18:00 ` [PATCH 065/207] drm/amdgpu/mes10.1: install mes queue via kiq Alex Deucher
2020-06-01 18:00 ` [PATCH 066/207] drm/amdgpu/mes10.1: enable the mes ring during initialization Alex Deucher
2020-06-01 18:00 ` [PATCH 067/207] drm/amdgpu/mes10.1: add the mes fw api Alex Deucher
2020-06-01 18:00 ` [PATCH 068/207] drm/amdgpu/mes10.1: add the helper function for mes command submission Alex Deucher
2020-06-01 18:00 ` [PATCH 069/207] drm/amdgpu/mes10.1: implement adding hardware queue Alex Deucher
2020-06-01 18:00 ` [PATCH 070/207] drm/amdgpu/mes10.1: implement removing " Alex Deucher
2020-06-01 18:00 ` [PATCH 071/207] drm/amdgpu/mes10.1: implement querying the scheduler status Alex Deucher
2020-06-01 18:00 ` [PATCH 072/207] drm/amdgpu/mes10.1: implement setting hardware resources Alex Deucher
2020-06-01 18:00 ` [PATCH 073/207] drm/amdgpu/mes10.1: add sienna_cichlid mes firmware support Alex Deucher
2020-06-01 18:00 ` [PATCH 074/207] drm/amdgpu/mes10.1: copy mes fw info into global fw array Alex Deucher
2020-06-01 18:00 ` [PATCH 075/207] drm/amdgpu: upload mes firmware to gpu buffer Alex Deucher
2020-06-01 18:00 ` [PATCH 076/207] drm/amdgpu/psp: convert amdgpu mes ucode type Alex Deucher
2020-06-01 18:00 ` [PATCH 077/207] drm/amdgpu: no need to set up GPU scheduler for mes ring Alex Deucher
2020-06-02 9:30 ` Christian König
2020-06-02 18:51 ` Alex Deucher
2020-06-01 18:00 ` [PATCH 078/207] drm/amdgpu/mes10.1: update mes initialization Alex Deucher
2020-06-01 18:00 ` [PATCH 079/207] drm/amdgpu: add mes block to sienna_cichlid Alex Deucher
2020-06-01 18:00 ` [PATCH 080/207] drm/amdgpu: update the num of queue per pipe for mec on sienna_cichlid Alex Deucher
2020-06-01 18:00 ` [PATCH 081/207] drm/amdgpu/mes: correct register offset for sienna_cichlid Alex Deucher
2020-06-01 18:00 ` [PATCH 082/207] drm/amdgpu: add VCN3.0 support for Sienna_Cichlid Alex Deucher
2020-06-01 18:00 ` [PATCH 083/207] drm/amdgpu: add Sienna_Cichlid VCN PG and CG support (v2) Alex Deucher
2020-06-01 18:00 ` [PATCH 084/207] drm/amdgpu: enable VCN3.0 PG and CG for Sienna_Cichlid Alex Deucher
2020-06-01 18:00 ` [PATCH 085/207] drm/amdgpu: add Sienna_Cichlid VCN to the VCN family Alex Deucher
2020-06-01 18:00 ` [PATCH 086/207] drm/amdgpu: enable VCN3.0 for Sienna_Cichlid Alex Deucher
2020-06-01 18:00 ` [PATCH 087/207] drm/amdgpu: add JPEG3.0 support " Alex Deucher
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